├── README.md └── STM32F3_Sine_Square_Gen ├── Makefile ├── STM32F303CBT6.cfg ├── build └── Debug │ └── GNU_ARM-Linux │ ├── sintab.o │ ├── sintab.o.d │ ├── stm32f3_sine_square_gen.o │ ├── stm32f3_sine_square_gen.o.d │ ├── usb.o │ └── usb.o.d ├── burn.sh ├── compile.sh ├── core_cm4.h ├── debug.sh ├── dist └── Debug │ └── GNU_ARM-Linux │ ├── STM32F3_Drum_Box.elf │ └── STM32F3_Sine_Square_Gen.elf ├── nbproject ├── Makefile-Debug.mk ├── Makefile-Release.mk ├── Makefile-impl.mk ├── Makefile-variables.mk ├── Package-Debug.bash ├── Package-Release.bash ├── configurations.xml ├── private │ ├── Makefile-variables.mk │ ├── c_standard_headers_indexer.c │ ├── configurations.xml │ ├── cpp_standard_headers_indexer.cpp │ ├── launcher.properties │ └── private.xml ├── project.properties └── project.xml ├── sin_table.ods ├── sintab.c ├── sintab.h ├── stm32f303-128k.ld ├── stm32f303_db.h ├── stm32f303xc.h ├── stm32f3_sine_square_gen.c ├── stm32f3xx.h ├── usb.c └── usb.h /README.md: -------------------------------------------------------------------------------- 1 | # STM32F303_Sine_Square_Generator 2 | An bare metal STM32F303CB project that generates a perfect 1KHz sine wave and 4 90 degree phase shifted square waves at also 1KHz 3 | 4 | This project is build with Netbeans 8.2. 5 | Programming the STM32F303CB is done with an ST-Link V2. In Netbeans click the run button to upload to the device. 6 | 7 | Output of the sine wave is found on PA4 (the DAC channel 1 output) 8 | The 4 square waves are found on the pins PB6, PB7, PB8, PB9 9 | 10 | A 1602, 1604, 2002 or 2004 display can be connected to the pins: 11 | PC14 for RS, PC15 for E, PA0 - PA3 for databus 12 | 13 | A rotary encoder can be connected to PB0 and PB1 14 | 15 | On the display the current phase difference between the sine wave and the square waves is shown. With the rotray encoder it can be moved in steps of half a degree. 16 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # There exist several targets which are by default empty and which can be 3 | # used for execution of your targets. These targets are usually executed 4 | # before and after some main targets. They are: 5 | # 6 | # .build-pre: called before 'build' target 7 | # .build-post: called after 'build' target 8 | # .clean-pre: called before 'clean' target 9 | # .clean-post: called after 'clean' target 10 | # .clobber-pre: called before 'clobber' target 11 | # .clobber-post: called after 'clobber' target 12 | # .all-pre: called before 'all' target 13 | # .all-post: called after 'all' target 14 | # .help-pre: called before 'help' target 15 | # .help-post: called after 'help' target 16 | # 17 | # Targets beginning with '.' are not intended to be called on their own. 18 | # 19 | # Main targets can be executed directly, and they are: 20 | # 21 | # build build a specific configuration 22 | # clean remove built files from a configuration 23 | # clobber remove all built files 24 | # all build all configurations 25 | # help print help mesage 26 | # 27 | # Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and 28 | # .help-impl are implemented in nbproject/makefile-impl.mk. 29 | # 30 | # Available make variables: 31 | # 32 | # CND_BASEDIR base directory for relative paths 33 | # CND_DISTDIR default top distribution directory (build artifacts) 34 | # CND_BUILDDIR default top build directory (object files, ...) 35 | # CONF name of current configuration 36 | # CND_PLATFORM_${CONF} platform name (current configuration) 37 | # CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration) 38 | # CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration) 39 | # CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration) 40 | # CND_PACKAGE_DIR_${CONF} directory of package (current configuration) 41 | # CND_PACKAGE_NAME_${CONF} name of package (current configuration) 42 | # CND_PACKAGE_PATH_${CONF} path to package (current configuration) 43 | # 44 | # NOCDDL 45 | 46 | 47 | # Environment 48 | MKDIR=mkdir 49 | CP=cp 50 | CCADMIN=CCadmin 51 | 52 | 53 | # build 54 | build: .build-post 55 | 56 | .build-pre: 57 | # Add your pre 'build' code here... 58 | 59 | .build-post: .build-impl 60 | # Add your post 'build' code here... 61 | 62 | 63 | # clean 64 | clean: .clean-post 65 | 66 | .clean-pre: 67 | # Add your pre 'clean' code here... 68 | 69 | .clean-post: .clean-impl 70 | # Add your post 'clean' code here... 71 | 72 | 73 | # clobber 74 | clobber: .clobber-post 75 | 76 | .clobber-pre: 77 | # Add your pre 'clobber' code here... 78 | 79 | .clobber-post: .clobber-impl 80 | # Add your post 'clobber' code here... 81 | 82 | 83 | # all 84 | all: .all-post 85 | 86 | .all-pre: 87 | # Add your pre 'all' code here... 88 | 89 | .all-post: .all-impl 90 | # Add your post 'all' code here... 91 | 92 | 93 | # build tests 94 | build-tests: .build-tests-post 95 | 96 | .build-tests-pre: 97 | # Add your pre 'build-tests' code here... 98 | 99 | .build-tests-post: .build-tests-impl 100 | # Add your post 'build-tests' code here... 101 | 102 | 103 | # run tests 104 | test: .test-post 105 | 106 | .test-pre: build-tests 107 | # Add your pre 'test' code here... 108 | 109 | .test-post: .test-impl 110 | # Add your post 'test' code here... 111 | 112 | 113 | # help 114 | help: .help-post 115 | 116 | .help-pre: 117 | # Add your pre 'help' code here... 118 | 119 | .help-post: .help-impl 120 | # Add your post 'help' code here... 121 | 122 | 123 | 124 | # include project implementation makefile 125 | include nbproject/Makefile-impl.mk 126 | 127 | # include project make variables 128 | include nbproject/Makefile-variables.mk 129 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/STM32F303CBT6.cfg: -------------------------------------------------------------------------------- 1 | set CHIPNAME STM32F303CBT6 2 | source [find interface/stlink-v2.cfg] 3 | transport select hla_swd 4 | set WORKAREASIZE 0x2000 5 | source [find target/stm32f3x.cfg] 6 | 7 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/sintab.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/sintab.o -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/sintab.o.d: -------------------------------------------------------------------------------- 1 | build/Debug/GNU_ARM-Linux/sintab.o: sintab.c 2 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/stm32f3_sine_square_gen.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/stm32f3_sine_square_gen.o -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/stm32f3_sine_square_gen.o.d: -------------------------------------------------------------------------------- 1 | build/Debug/GNU_ARM-Linux/stm32f3_sine_square_gen.o: \ 2 | stm32f3_sine_square_gen.c stm32f303_db.h usb.h sintab.h 3 | 4 | stm32f303_db.h: 5 | 6 | usb.h: 7 | 8 | sintab.h: 9 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/usb.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/usb.o -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/build/Debug/GNU_ARM-Linux/usb.o.d: -------------------------------------------------------------------------------- 1 | build/Debug/GNU_ARM-Linux/usb.o: usb.c stm32f303_db.h usb.h 2 | 3 | stm32f303_db.h: 4 | 5 | usb.h: 6 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/burn.sh: -------------------------------------------------------------------------------- 1 | openocd -f STM32F103C8T6.cfg -c init -c targets -c halt -c "flash write_image erase stm_usb.elf" -c "verify_image stm_usb.elf" -c "reset run" 2 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/compile.sh: -------------------------------------------------------------------------------- 1 | arm-none-eabi-gcc -Wall -Wno-write-strings -Wno-char-subscripts -fno-stack-protector -DNO_STDLIB=1 -O3 -mcpu=cortex-m3 -mthumb -c *.c 2 | arm-none-eabi-ld -T stm32f103-64k.ld -nostdlib -Map=test.map -o stm_usb.elf *.o 3 | arm-none-eabi-objcopy stm_usb.elf -O ihex stm_usb.hex 4 | arm-none-eabi-size stm_usb.elf 5 | rm *.o 6 | rm *.map 7 | #rm *.elf 8 | 9 | #openocd -f STM32F103C8T6.cfg -c init -c targets -c halt -c "flash write_image erase stm_usb.elf" -c "verify_image stm_usb.elf" -c "reset run" 10 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/debug.sh: -------------------------------------------------------------------------------- 1 | openocd -f STM32F103C8T6.cfg 2 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/dist/Debug/GNU_ARM-Linux/STM32F3_Drum_Box.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/dist/Debug/GNU_ARM-Linux/STM32F3_Drum_Box.elf -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/dist/Debug/GNU_ARM-Linux/STM32F3_Sine_Square_Gen.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/dist/Debug/GNU_ARM-Linux/STM32F3_Sine_Square_Gen.elf -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/Makefile-Debug.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated Makefile - do not edit! 3 | # 4 | # Edit the Makefile in the project folder instead (../Makefile). Each target 5 | # has a -pre and a -post target defined where you can add customized code. 6 | # 7 | # This makefile implements configuration specific macros and targets. 8 | 9 | 10 | # Environment 11 | MKDIR=mkdir 12 | CP=cp 13 | GREP=grep 14 | NM=nm 15 | CCADMIN=CCadmin 16 | RANLIB=ranlib 17 | CC=arm-none-eabi-gcc 18 | CCC=arm-none-eabi-g++ 19 | CXX=arm-none-eabi-g++ 20 | FC=gfortran 21 | AS=arm-none-eabi-gcc 22 | 23 | # Macros 24 | CND_PLATFORM=GNU_ARM-Linux 25 | CND_DLIB_EXT=so 26 | CND_CONF=Debug 27 | CND_DISTDIR=dist 28 | CND_BUILDDIR=build 29 | 30 | # Include project Makefile 31 | include Makefile 32 | 33 | # Object Directory 34 | OBJECTDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM} 35 | 36 | # Object Files 37 | OBJECTFILES= \ 38 | ${OBJECTDIR}/sintab.o \ 39 | ${OBJECTDIR}/stm32f3_sine_square_gen.o \ 40 | ${OBJECTDIR}/usb.o 41 | 42 | 43 | # C Compiler Flags 44 | CFLAGS=-Wall -Wno-write-strings -Wno-char-subscripts -fno-stack-protector -DNO_STDLIB=1 -mcpu=cortex-m4 -mthumb -O3 45 | 46 | # CC Compiler Flags 47 | CCFLAGS= 48 | CXXFLAGS= 49 | 50 | # Fortran Compiler Flags 51 | FFLAGS= 52 | 53 | # Assembler Flags 54 | ASFLAGS=-x assembler-with-cpp -c -O0 -mcpu=cortex-m4 -mthumb -Wall -fmessage-length=0 55 | 56 | # Link Libraries and Options 57 | LDLIBSOPTIONS= 58 | 59 | # Build Targets 60 | .build-conf: ${BUILD_SUBPROJECTS} 61 | "${MAKE}" -f nbproject/Makefile-${CND_CONF}.mk ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/STM32F3_Sine_Square_Gen.elf 62 | 63 | ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/STM32F3_Sine_Square_Gen.elf: ${OBJECTFILES} 64 | ${MKDIR} -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM} 65 | arm-none-eabi-gcc -o ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/STM32F3_Sine_Square_Gen.elf ${OBJECTFILES} ${LDLIBSOPTIONS} -T./stm32f303-128k.ld -nostdlib 66 | 67 | ${OBJECTDIR}/sintab.o: sintab.c 68 | ${MKDIR} -p ${OBJECTDIR} 69 | ${RM} "$@.d" 70 | $(COMPILE.c) -g -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/sintab.o sintab.c 71 | 72 | ${OBJECTDIR}/stm32f3_sine_square_gen.o: stm32f3_sine_square_gen.c 73 | ${MKDIR} -p ${OBJECTDIR} 74 | ${RM} "$@.d" 75 | $(COMPILE.c) -g -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/stm32f3_sine_square_gen.o stm32f3_sine_square_gen.c 76 | 77 | ${OBJECTDIR}/usb.o: usb.c 78 | ${MKDIR} -p ${OBJECTDIR} 79 | ${RM} "$@.d" 80 | $(COMPILE.c) -g -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/usb.o usb.c 81 | 82 | # Subprojects 83 | .build-subprojects: 84 | 85 | # Clean Targets 86 | .clean-conf: ${CLEAN_SUBPROJECTS} 87 | ${RM} -r ${CND_BUILDDIR}/${CND_CONF} 88 | 89 | # Subprojects 90 | .clean-subprojects: 91 | 92 | # Enable dependency checking 93 | .dep.inc: .depcheck-impl 94 | 95 | include .dep.inc 96 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/Makefile-Release.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated Makefile - do not edit! 3 | # 4 | # Edit the Makefile in the project folder instead (../Makefile). Each target 5 | # has a -pre and a -post target defined where you can add customized code. 6 | # 7 | # This makefile implements configuration specific macros and targets. 8 | 9 | 10 | # Environment 11 | MKDIR=mkdir 12 | CP=cp 13 | GREP=grep 14 | NM=nm 15 | CCADMIN=CCadmin 16 | RANLIB=ranlib 17 | CC=arm-none-eabi-gcc 18 | CCC=g++ 19 | CXX=g++ 20 | FC=gfortran 21 | AS=as 22 | 23 | # Macros 24 | CND_PLATFORM=GNU-Linux 25 | CND_DLIB_EXT=so 26 | CND_CONF=Release 27 | CND_DISTDIR=dist 28 | CND_BUILDDIR=build 29 | 30 | # Include project Makefile 31 | include Makefile 32 | 33 | # Object Directory 34 | OBJECTDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM} 35 | 36 | # Object Files 37 | OBJECTFILES= \ 38 | ${OBJECTDIR}/sintab.o \ 39 | ${OBJECTDIR}/stm32f3_sine_square_gen.o \ 40 | ${OBJECTDIR}/usb.o 41 | 42 | 43 | # C Compiler Flags 44 | CFLAGS=-Wall -Wno-write-strings -Wno-char-subscripts -fno-stack-protector -DNO_STDLIB=1 -O3 -mcpu=cortex-m4 -mthumb 45 | 46 | # CC Compiler Flags 47 | CCFLAGS= 48 | CXXFLAGS= 49 | 50 | # Fortran Compiler Flags 51 | FFLAGS= 52 | 53 | # Assembler Flags 54 | ASFLAGS= 55 | 56 | # Link Libraries and Options 57 | LDLIBSOPTIONS= 58 | 59 | # Build Targets 60 | .build-conf: ${BUILD_SUBPROJECTS} 61 | "${MAKE}" -f nbproject/Makefile-${CND_CONF}.mk ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/stm32f3_sine_square_gen 62 | 63 | ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/stm32f3_sine_square_gen: ${OBJECTFILES} 64 | ${MKDIR} -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM} 65 | arm-none-eabi-gcc -o ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/stm32f3_sine_square_gen ${OBJECTFILES} ${LDLIBSOPTIONS} -T./stm32f303-64k.ld -nostdlib 66 | 67 | ${OBJECTDIR}/sintab.o: sintab.c 68 | ${MKDIR} -p ${OBJECTDIR} 69 | ${RM} "$@.d" 70 | $(COMPILE.c) -O2 -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/sintab.o sintab.c 71 | 72 | ${OBJECTDIR}/stm32f3_sine_square_gen.o: stm32f3_sine_square_gen.c 73 | ${MKDIR} -p ${OBJECTDIR} 74 | ${RM} "$@.d" 75 | $(COMPILE.c) -O2 -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/stm32f3_sine_square_gen.o stm32f3_sine_square_gen.c 76 | 77 | ${OBJECTDIR}/usb.o: usb.c 78 | ${MKDIR} -p ${OBJECTDIR} 79 | ${RM} "$@.d" 80 | $(COMPILE.c) -O2 -MMD -MP -MF "$@.d" -o ${OBJECTDIR}/usb.o usb.c 81 | 82 | # Subprojects 83 | .build-subprojects: 84 | 85 | # Clean Targets 86 | .clean-conf: ${CLEAN_SUBPROJECTS} 87 | ${RM} -r ${CND_BUILDDIR}/${CND_CONF} 88 | 89 | # Subprojects 90 | .clean-subprojects: 91 | 92 | # Enable dependency checking 93 | .dep.inc: .depcheck-impl 94 | 95 | include .dep.inc 96 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/Makefile-impl.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated Makefile - do not edit! 3 | # 4 | # Edit the Makefile in the project folder instead (../Makefile). Each target 5 | # has a pre- and a post- target defined where you can add customization code. 6 | # 7 | # This makefile implements macros and targets common to all configurations. 8 | # 9 | # NOCDDL 10 | 11 | 12 | # Building and Cleaning subprojects are done by default, but can be controlled with the SUB 13 | # macro. If SUB=no, subprojects will not be built or cleaned. The following macro 14 | # statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf 15 | # and .clean-reqprojects-conf unless SUB has the value 'no' 16 | SUB_no=NO 17 | SUBPROJECTS=${SUB_${SUB}} 18 | BUILD_SUBPROJECTS_=.build-subprojects 19 | BUILD_SUBPROJECTS_NO= 20 | BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}} 21 | CLEAN_SUBPROJECTS_=.clean-subprojects 22 | CLEAN_SUBPROJECTS_NO= 23 | CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}} 24 | 25 | 26 | # Project Name 27 | PROJECTNAME=STM32F3_Sine_Square_Gen 28 | 29 | # Active Configuration 30 | DEFAULTCONF=Debug 31 | CONF=${DEFAULTCONF} 32 | 33 | # All Configurations 34 | ALLCONFS=Debug Release 35 | 36 | 37 | # build 38 | .build-impl: .build-pre .validate-impl .depcheck-impl 39 | @#echo "=> Running $@... Configuration=$(CONF)" 40 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .build-conf 41 | 42 | 43 | # clean 44 | .clean-impl: .clean-pre .validate-impl .depcheck-impl 45 | @#echo "=> Running $@... Configuration=$(CONF)" 46 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .clean-conf 47 | 48 | 49 | # clobber 50 | .clobber-impl: .clobber-pre .depcheck-impl 51 | @#echo "=> Running $@..." 52 | for CONF in ${ALLCONFS}; \ 53 | do \ 54 | "${MAKE}" -f nbproject/Makefile-$${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .clean-conf; \ 55 | done 56 | 57 | # all 58 | .all-impl: .all-pre .depcheck-impl 59 | @#echo "=> Running $@..." 60 | for CONF in ${ALLCONFS}; \ 61 | do \ 62 | "${MAKE}" -f nbproject/Makefile-$${CONF}.mk QMAKE=${QMAKE} SUBPROJECTS=${SUBPROJECTS} .build-conf; \ 63 | done 64 | 65 | # build tests 66 | .build-tests-impl: .build-impl .build-tests-pre 67 | @#echo "=> Running $@... Configuration=$(CONF)" 68 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-tests-conf 69 | 70 | # run tests 71 | .test-impl: .build-tests-impl .test-pre 72 | @#echo "=> Running $@... Configuration=$(CONF)" 73 | "${MAKE}" -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .test-conf 74 | 75 | # dependency checking support 76 | .depcheck-impl: 77 | @echo "# This code depends on make tool being used" >.dep.inc 78 | @if [ -n "${MAKE_VERSION}" ]; then \ 79 | echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES} \$${TESTOBJECTFILES}))" >>.dep.inc; \ 80 | echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \ 81 | echo "include \$${DEPFILES}" >>.dep.inc; \ 82 | echo "endif" >>.dep.inc; \ 83 | else \ 84 | echo ".KEEP_STATE:" >>.dep.inc; \ 85 | echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \ 86 | fi 87 | 88 | # configuration validation 89 | .validate-impl: 90 | @if [ ! -f nbproject/Makefile-${CONF}.mk ]; \ 91 | then \ 92 | echo ""; \ 93 | echo "Error: can not find the makefile for configuration '${CONF}' in project ${PROJECTNAME}"; \ 94 | echo "See 'make help' for details."; \ 95 | echo "Current directory: " `pwd`; \ 96 | echo ""; \ 97 | fi 98 | @if [ ! -f nbproject/Makefile-${CONF}.mk ]; \ 99 | then \ 100 | exit 1; \ 101 | fi 102 | 103 | 104 | # help 105 | .help-impl: .help-pre 106 | @echo "This makefile supports the following configurations:" 107 | @echo " ${ALLCONFS}" 108 | @echo "" 109 | @echo "and the following targets:" 110 | @echo " build (default target)" 111 | @echo " clean" 112 | @echo " clobber" 113 | @echo " all" 114 | @echo " help" 115 | @echo "" 116 | @echo "Makefile Usage:" 117 | @echo " make [CONF=] [SUB=no] build" 118 | @echo " make [CONF=] [SUB=no] clean" 119 | @echo " make [SUB=no] clobber" 120 | @echo " make [SUB=no] all" 121 | @echo " make help" 122 | @echo "" 123 | @echo "Target 'build' will build a specific configuration and, unless 'SUB=no'," 124 | @echo " also build subprojects." 125 | @echo "Target 'clean' will clean a specific configuration and, unless 'SUB=no'," 126 | @echo " also clean subprojects." 127 | @echo "Target 'clobber' will remove all built files from all configurations and," 128 | @echo " unless 'SUB=no', also from subprojects." 129 | @echo "Target 'all' will will build all configurations and, unless 'SUB=no'," 130 | @echo " also build subprojects." 131 | @echo "Target 'help' prints this message." 132 | @echo "" 133 | 134 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/Makefile-variables.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated - do not edit! 3 | # 4 | # NOCDDL 5 | # 6 | CND_BASEDIR=`pwd` 7 | CND_BUILDDIR=build 8 | CND_DISTDIR=dist 9 | # Debug configuration 10 | CND_PLATFORM_Debug=GNU_ARM-Linux 11 | CND_ARTIFACT_DIR_Debug=dist/Debug/GNU_ARM-Linux 12 | CND_ARTIFACT_NAME_Debug=STM32F3_Sine_Square_Gen.elf 13 | CND_ARTIFACT_PATH_Debug=dist/Debug/GNU_ARM-Linux/STM32F3_Sine_Square_Gen.elf 14 | CND_PACKAGE_DIR_Debug=dist/Debug/GNU_ARM-Linux/package 15 | CND_PACKAGE_NAME_Debug=stm32f3sinesquaregen.tar 16 | CND_PACKAGE_PATH_Debug=dist/Debug/GNU_ARM-Linux/package/stm32f3sinesquaregen.tar 17 | # Release configuration 18 | CND_PLATFORM_Release=GNU-Linux 19 | CND_ARTIFACT_DIR_Release=dist/Release/GNU-Linux 20 | CND_ARTIFACT_NAME_Release=stm32f3_sine_square_gen 21 | CND_ARTIFACT_PATH_Release=dist/Release/GNU-Linux/stm32f3_sine_square_gen 22 | CND_PACKAGE_DIR_Release=dist/Release/GNU-Linux/package 23 | CND_PACKAGE_NAME_Release=stm32f3sinesquaregen.tar 24 | CND_PACKAGE_PATH_Release=dist/Release/GNU-Linux/package/stm32f3sinesquaregen.tar 25 | # 26 | # include compiler specific variables 27 | # 28 | # dmake command 29 | ROOT:sh = test -f nbproject/private/Makefile-variables.mk || \ 30 | (mkdir -p nbproject/private && touch nbproject/private/Makefile-variables.mk) 31 | # 32 | # gmake command 33 | .PHONY: $(shell test -f nbproject/private/Makefile-variables.mk || (mkdir -p nbproject/private && touch nbproject/private/Makefile-variables.mk)) 34 | # 35 | include nbproject/private/Makefile-variables.mk 36 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/Package-Debug.bash: -------------------------------------------------------------------------------- 1 | #!/bin/bash -x 2 | 3 | # 4 | # Generated - do not edit! 5 | # 6 | 7 | # Macros 8 | TOP=`pwd` 9 | CND_PLATFORM=GNU_ARM-Linux 10 | CND_CONF=Debug 11 | CND_DISTDIR=dist 12 | CND_BUILDDIR=build 13 | CND_DLIB_EXT=so 14 | NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging 15 | TMPDIRNAME=tmp-packaging 16 | OUTPUT_PATH=${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/STM32F3_Sine_Square_Gen.elf 17 | OUTPUT_BASENAME=STM32F3_Sine_Square_Gen.elf 18 | PACKAGE_TOP_DIR=stm32f3sinesquaregen/ 19 | 20 | # Functions 21 | function checkReturnCode 22 | { 23 | rc=$? 24 | if [ $rc != 0 ] 25 | then 26 | exit $rc 27 | fi 28 | } 29 | function makeDirectory 30 | # $1 directory path 31 | # $2 permission (optional) 32 | { 33 | mkdir -p "$1" 34 | checkReturnCode 35 | if [ "$2" != "" ] 36 | then 37 | chmod $2 "$1" 38 | checkReturnCode 39 | fi 40 | } 41 | function copyFileToTmpDir 42 | # $1 from-file path 43 | # $2 to-file path 44 | # $3 permission 45 | { 46 | cp "$1" "$2" 47 | checkReturnCode 48 | if [ "$3" != "" ] 49 | then 50 | chmod $3 "$2" 51 | checkReturnCode 52 | fi 53 | } 54 | 55 | # Setup 56 | cd "${TOP}" 57 | mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package 58 | rm -rf ${NBTMPDIR} 59 | mkdir -p ${NBTMPDIR} 60 | 61 | # Copy files and create directories and links 62 | cd "${TOP}" 63 | makeDirectory "${NBTMPDIR}/stm32f3sinesquaregen/bin" 64 | copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 65 | 66 | 67 | # Generate tar file 68 | cd "${TOP}" 69 | rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stm32f3sinesquaregen.tar 70 | cd ${NBTMPDIR} 71 | tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stm32f3sinesquaregen.tar * 72 | checkReturnCode 73 | 74 | # Cleanup 75 | cd "${TOP}" 76 | rm -rf ${NBTMPDIR} 77 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/Package-Release.bash: -------------------------------------------------------------------------------- 1 | #!/bin/bash -x 2 | 3 | # 4 | # Generated - do not edit! 5 | # 6 | 7 | # Macros 8 | TOP=`pwd` 9 | CND_PLATFORM=GNU-Linux 10 | CND_CONF=Release 11 | CND_DISTDIR=dist 12 | CND_BUILDDIR=build 13 | CND_DLIB_EXT=so 14 | NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging 15 | TMPDIRNAME=tmp-packaging 16 | OUTPUT_PATH=${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/stm32f3_sine_square_gen 17 | OUTPUT_BASENAME=stm32f3_sine_square_gen 18 | PACKAGE_TOP_DIR=stm32f3sinesquaregen/ 19 | 20 | # Functions 21 | function checkReturnCode 22 | { 23 | rc=$? 24 | if [ $rc != 0 ] 25 | then 26 | exit $rc 27 | fi 28 | } 29 | function makeDirectory 30 | # $1 directory path 31 | # $2 permission (optional) 32 | { 33 | mkdir -p "$1" 34 | checkReturnCode 35 | if [ "$2" != "" ] 36 | then 37 | chmod $2 "$1" 38 | checkReturnCode 39 | fi 40 | } 41 | function copyFileToTmpDir 42 | # $1 from-file path 43 | # $2 to-file path 44 | # $3 permission 45 | { 46 | cp "$1" "$2" 47 | checkReturnCode 48 | if [ "$3" != "" ] 49 | then 50 | chmod $3 "$2" 51 | checkReturnCode 52 | fi 53 | } 54 | 55 | # Setup 56 | cd "${TOP}" 57 | mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package 58 | rm -rf ${NBTMPDIR} 59 | mkdir -p ${NBTMPDIR} 60 | 61 | # Copy files and create directories and links 62 | cd "${TOP}" 63 | makeDirectory "${NBTMPDIR}/stm32f3sinesquaregen/bin" 64 | copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 65 | 66 | 67 | # Generate tar file 68 | cd "${TOP}" 69 | rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stm32f3sinesquaregen.tar 70 | cd ${NBTMPDIR} 71 | tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stm32f3sinesquaregen.tar * 72 | checkReturnCode 73 | 74 | # Cleanup 75 | cd "${TOP}" 76 | rm -rf ${NBTMPDIR} 77 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/configurations.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | sintab.h 8 | stm32f303_db.h 9 | usb.h 10 | 11 | 14 | 15 | 18 | sintab.c 19 | stm32f3_sine_square_gen.c 20 | usb.c 21 | 22 | 26 | 27 | 31 | Makefile 32 | STM32F303C8T6.cfg 33 | stm32f303-64k.ld 34 | 35 | 36 | Makefile 37 | 38 | 39 | 40 | GNU_ARM|GNU 41 | true 42 | false 43 | 44 | 45 | 46 | -Wall -Wno-write-strings -Wno-char-subscripts -fno-stack-protector -DNO_STDLIB=1 -mcpu=cortex-m4 -mthumb -O3 47 | false 48 | 49 | 50 | false 51 | 52 | 53 | arm-none-eabi-gcc 54 | -x assembler-with-cpp -c -O0 -mcpu=cortex-m4 -mthumb -Wall -fmessage-length=0 55 | 56 | 57 | ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/STM32F3_Sine_Square_Gen.elf 58 | arm-none-eabi-gcc 59 | -T./stm32f303-128k.ld -nostdlib 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | GNU|GNU 78 | true 79 | false 80 | 81 | 82 | 83 | 5 84 | arm-none-eabi-gcc 85 | -Wall -Wno-write-strings -Wno-char-subscripts -fno-stack-protector -DNO_STDLIB=1 -O3 -mcpu=cortex-m4 -mthumb 86 | 87 | 88 | 5 89 | 90 | 91 | 5 92 | 93 | 94 | 5 95 | 96 | 97 | arm-none-eabi-gcc 98 | -T./stm32f303-64k.ld -nostdlib 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/private/Makefile-variables.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Generated - do not edit! 3 | # 4 | # NOCDDL 5 | # 6 | # Debug configuration 7 | # Release configuration 8 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/private/c_standard_headers_indexer.c: -------------------------------------------------------------------------------- 1 | /* 2 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS HEADER. 3 | * 4 | * Copyright (c) 2016 Oracle and/or its affiliates. All rights reserved. 5 | * 6 | * Oracle and Java are registered trademarks of Oracle and/or its affiliates. 7 | * Other names may be trademarks of their respective owners. 8 | * 9 | * The contents of this file are subject to the terms of either the GNU 10 | * General Public License Version 2 only ("GPL") or the Common 11 | * Development and Distribution License("CDDL") (collectively, the 12 | * "License"). You may not use this file except in compliance with the 13 | * License. You can obtain a copy of the License at 14 | * http://www.netbeans.org/cddl-gplv2.html 15 | * or nbbuild/licenses/CDDL-GPL-2-CP. See the License for the 16 | * specific language governing permissions and limitations under the 17 | * License. When distributing the software, include this License Header 18 | * Notice in each file and include the License file at 19 | * nbbuild/licenses/CDDL-GPL-2-CP. Oracle designates this 20 | * particular file as subject to the "Classpath" exception as provided 21 | * by Oracle in the GPL Version 2 section of the License file that 22 | * accompanied this code. If applicable, add the following below the 23 | * License Header, with the fields enclosed by brackets [] replaced by 24 | * your own identifying information: 25 | * "Portions Copyrighted [year] [name of copyright owner]" 26 | * 27 | * If you wish your version of this file to be governed by only the CDDL 28 | * or only the GPL Version 2, indicate your decision by adding 29 | * "[Contributor] elects to include this software in this distribution 30 | * under the [CDDL or GPL Version 2] license." If you do not indicate a 31 | * single choice of license, a recipient has the option to distribute 32 | * your version of this file under either the CDDL, the GPL Version 2 or 33 | * to extend the choice of license to its licensees as provided above. 34 | * However, if you add GPL Version 2 code and therefore, elected the GPL 35 | * Version 2 license, then the option applies only if the new code is 36 | * made subject to such option by the copyright holder. 37 | * 38 | * Contributor(s): 39 | */ 40 | 41 | // List of standard headers was taken in http://en.cppreference.com/w/c/header 42 | 43 | #include // Conditionally compiled macro that compares its argument to zero 44 | #include // Functions to determine the type contained in character data 45 | #include // Macros reporting error conditions 46 | #include // Limits of float types 47 | #include // Sizes of basic types 48 | #include // Localization utilities 49 | #include // Common mathematics functions 50 | #include // Nonlocal jumps 51 | #include // Signal handling 52 | #include // Variable arguments 53 | #include // Common macro definitions 54 | #include // Input/output 55 | #include // String handling 56 | #include // General utilities: memory management, program utilities, string conversions, random numbers 57 | #include // Time/date utilities 58 | #include // (since C95) Alternative operator spellings 59 | #include // (since C95) Extended multibyte and wide character utilities 60 | #include // (since C95) Wide character classification and mapping utilities 61 | #ifdef _STDC_C99 62 | #include // (since C99) Complex number arithmetic 63 | #include // (since C99) Floating-point environment 64 | #include // (since C99) Format conversion of integer types 65 | #include // (since C99) Boolean type 66 | #include // (since C99) Fixed-width integer types 67 | #include // (since C99) Type-generic math (macros wrapping math.h and complex.h) 68 | #endif 69 | #ifdef _STDC_C11 70 | #include // (since C11) alignas and alignof convenience macros 71 | #include // (since C11) Atomic types 72 | #include // (since C11) noreturn convenience macros 73 | #include // (since C11) Thread library 74 | #include // (since C11) UTF-16 and UTF-32 character utilities 75 | #endif 76 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/private/configurations.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | Makefile 4 | 5 | 6 | 7 | localhost 8 | 2 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 20 | 21 | 22 | 23 | 24 | gdb 25 | 26 | 27 | 28 | "${OUTPUT_PATH}" 29 | /usr/bin/arm-none-eabi-objcopy -S -O binary ${OUTPUT_PATH} 30 | openocd -f STM32F303C8T6.cfg -c init -c targets -c halt -c "flash write_image erase ${OUTPUT_PATH}" -c "verify_image ${OUTPUT_PATH}" -c "reset run" 31 | openocd -f STM32F303CBT6.cfg -c init -c targets -c halt -c "flash write_image erase ${OUTPUT_PATH}" -c "verify_image ${OUTPUT_PATH}" -c "reset run" 32 | 33 | openocd -f STM32F303CBT6.cfg -c init -c targets -c halt -c "flash write_image erase ${OUTPUT_PATH}" -c "verify_image ${OUTPUT_PATH}" -c "reset run" 34 | 35 | true 36 | 0 37 | 0 38 | 39 | 40 | 41 | 42 | 43 | 44 | localhost 45 | 2 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | gdb 61 | 62 | 63 | 64 | "${OUTPUT_PATH}" 65 | 66 | "${OUTPUT_PATH}" 67 | 68 | true 69 | 0 70 | 0 71 | 72 | 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/private/cpp_standard_headers_indexer.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS HEADER. 3 | * 4 | * Copyright (c) 2016 Oracle and/or its affiliates. All rights reserved. 5 | * 6 | * Oracle and Java are registered trademarks of Oracle and/or its affiliates. 7 | * Other names may be trademarks of their respective owners. 8 | * 9 | * The contents of this file are subject to the terms of either the GNU 10 | * General Public License Version 2 only ("GPL") or the Common 11 | * Development and Distribution License("CDDL") (collectively, the 12 | * "License"). You may not use this file except in compliance with the 13 | * License. You can obtain a copy of the License at 14 | * http://www.netbeans.org/cddl-gplv2.html 15 | * or nbbuild/licenses/CDDL-GPL-2-CP. See the License for the 16 | * specific language governing permissions and limitations under the 17 | * License. When distributing the software, include this License Header 18 | * Notice in each file and include the License file at 19 | * nbbuild/licenses/CDDL-GPL-2-CP. Oracle designates this 20 | * particular file as subject to the "Classpath" exception as provided 21 | * by Oracle in the GPL Version 2 section of the License file that 22 | * accompanied this code. If applicable, add the following below the 23 | * License Header, with the fields enclosed by brackets [] replaced by 24 | * your own identifying information: 25 | * "Portions Copyrighted [year] [name of copyright owner]" 26 | * 27 | * If you wish your version of this file to be governed by only the CDDL 28 | * or only the GPL Version 2, indicate your decision by adding 29 | * "[Contributor] elects to include this software in this distribution 30 | * under the [CDDL or GPL Version 2] license." If you do not indicate a 31 | * single choice of license, a recipient has the option to distribute 32 | * your version of this file under either the CDDL, the GPL Version 2 or 33 | * to extend the choice of license to its licensees as provided above. 34 | * However, if you add GPL Version 2 code and therefore, elected the GPL 35 | * Version 2 license, then the option applies only if the new code is 36 | * made subject to such option by the copyright holder. 37 | * 38 | * Contributor(s): 39 | */ 40 | 41 | // List of standard headers was taken in http://en.cppreference.com/w/cpp/header 42 | 43 | #include // General purpose utilities: program control, dynamic memory allocation, random numbers, sort and search 44 | #include // Functions and macro constants for signal management 45 | #include // Macro (and function) that saves (and jumps) to an execution context 46 | #include // Handling of variable length argument lists 47 | #include // Runtime type information utilities 48 | #include // std::bitset class template 49 | #include // Function objects, designed for use with the standard algorithms 50 | #include // Various utility components 51 | #include // C-style time/date utilites 52 | #include // typedefs for types such as size_t, NULL and others 53 | #include // Low-level memory management utilities 54 | #include // Higher level memory management utilities 55 | #include // limits of integral types 56 | #include // limits of float types 57 | #include // standardized way to query properties of arithmetic types 58 | #include // Exception handling utilities 59 | #include // Standard exception objects 60 | #include // Conditionally compiled macro that compares its argument to zero 61 | #include // Macro containing the last error number 62 | #include // functions to determine the type contained in character data 63 | #include // functions for determining the type of wide character data 64 | #include // various narrow character string handling functions 65 | #include // various wide and multibyte string handling functions 66 | #include // std::basic_string class template 67 | #include // std::vector container 68 | #include // std::deque container 69 | #include // std::list container 70 | #include // std::set and std::multiset associative containers 71 | #include // std::map and std::multimap associative containers 72 | #include // std::stack container adaptor 73 | #include // std::queue and std::priority_queue container adaptors 74 | #include // Algorithms that operate on containers 75 | #include // Container iterators 76 | #include // Common mathematics functions 77 | #include // Complex number type 78 | #include // Class for representing and manipulating arrays of values 79 | #include // Numeric operations on values in containers 80 | #include // forward declarations of all classes in the input/output library 81 | #include // std::ios_base class, std::basic_ios class template and several typedefs 82 | #include // std::basic_istream class template and several typedefs 83 | #include // std::basic_ostream, std::basic_iostream class templates and several typedefs 84 | #include // several standard stream objects 85 | #include // std::basic_fstream, std::basic_ifstream, std::basic_ofstream class templates and several typedefs 86 | #include // std::basic_stringstream, std::basic_istringstream, std::basic_ostringstream class templates and several typedefs 87 | #include // std::strstream, std::istrstream, std::ostrstream(deprecated) 88 | #include // Helper functions to control the format or input and output 89 | #include // std::basic_streambuf class template 90 | #include // C-style input-output functions 91 | #include // Localization utilities 92 | #include // C localization utilities 93 | #include // empty header. The macros that appear in iso646.h in C are keywords in C++ 94 | #if __cplusplus >= 201103L 95 | #include // (since C++11) std::type_index 96 | #include // (since C++11) Compile-time type information 97 | #include // (since C++11) C++ time utilites 98 | #include // (since C++11) std::initializer_list class template 99 | #include // (since C++11) std::tuple class template 100 | #include // (since C++11) Nested allocator class 101 | #include // (since C++11) fixed-size types and limits of other types 102 | #include // (since C++11) formatting macros , intmax_t and uintmax_t math and conversions 103 | #include // (since C++11) defines std::error_code, a platform-dependent error code 104 | #include // (since C++11) C-style Unicode character conversion functions 105 | #include // (since C++11) std::array container 106 | #include // (since C++11) std::forward_list container 107 | #include // (since C++11) std::unordered_set and std::unordered_multiset unordered associative containers 108 | #include // (since C++11) std::unordered_map and std::unordered_multimap unordered associative containers 109 | #include // (since C++11) Random number generators and distributions 110 | #include // (since C++11) Compile-time rational arithmetic 111 | #include // (since C++11) Floating-point environment access functions 112 | #include // (since C++11) Unicode conversion facilities 113 | #include // (since C++11) Classes, algorithms and iterators to support regular expression processing 114 | #include // (since C++11) Atomic operations library 115 | #include // (since C++11)(deprecated in C++17) simply includes the header 116 | #include // (since C++11)(deprecated in C++17) simply includes the headers (until C++17) (since C++17) and : the overloads equivalent to the contents of the C header tgmath.h are already provided by those headers 117 | #include // (since C++11)(deprecated in C++17) defines one compatibility macro constant 118 | #include // (since C++11)(deprecated in C++17) defines one compatibility macro constant 119 | #include // (since C++11) std::thread class and supporting functions 120 | #include // (since C++11) mutual exclusion primitives 121 | #include // (since C++11) primitives for asynchronous computations 122 | #include // (since C++11) thread waiting conditions 123 | #endif 124 | #if __cplusplus >= 201300L 125 | #include // (since C++14) shared mutual exclusion primitives 126 | #endif 127 | #if __cplusplus >= 201500L 128 | #include // (since C++17) std::any class template 129 | #include // (since C++17) std::optional class template 130 | #include // (since C++17) std::variant class template 131 | #include // (since C++17) Polymorphic allocators and memory resources 132 | #include // (since C++17) std::basic_string_view class template 133 | #include // (since C++17) Predefined execution policies for parallel versions of the algorithms 134 | #include // (since C++17) std::path class and supporting functions 135 | #endif 136 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/private/launcher.properties: -------------------------------------------------------------------------------- 1 | # Launchers File syntax: 2 | # 3 | # [Must-have property line] 4 | # launcher1.runCommand= 5 | # [Optional extra properties] 6 | # launcher1.displayName= 7 | # launcher1.hide= 8 | # launcher1.buildCommand= 9 | # launcher1.runDir= 10 | # launcher1.runInOwnTab= 11 | # launcher1.symbolFiles= 12 | # launcher1.env.= 13 | # (If this value is quoted with ` it is handled as a native command which execution result will become the value) 14 | # [Common launcher properties] 15 | # common.runDir= 16 | # (This value is overwritten by a launcher specific runDir value if the latter exists) 17 | # common.env.= 18 | # (Environment variables from common launcher are merged with launcher specific variables) 19 | # common.symbolFiles= 20 | # (This value is overwritten by a launcher specific symbolFiles value if the latter exists) 21 | # 22 | # In runDir, symbolFiles and env fields you can use these macroses: 23 | # ${PROJECT_DIR} - project directory absolute path 24 | # ${OUTPUT_PATH} - linker output path (relative to project directory path) 25 | # ${OUTPUT_BASENAME}- linker output filename 26 | # ${TESTDIR} - test files directory (relative to project directory path) 27 | # ${OBJECTDIR} - object files directory (relative to project directory path) 28 | # ${CND_DISTDIR} - distribution directory (relative to project directory path) 29 | # ${CND_BUILDDIR} - build directory (relative to project directory path) 30 | # ${CND_PLATFORM} - platform name 31 | # ${CND_CONF} - configuration name 32 | # ${CND_DLIB_EXT} - dynamic library extension 33 | # 34 | # All the project launchers must be listed in the file! 35 | # 36 | # launcher1.runCommand=... 37 | # launcher2.runCommand=... 38 | # ... 39 | # common.runDir=... 40 | # common.env.KEY=VALUE 41 | 42 | # launcher1.runCommand= -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/private/private.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1 5 | 0 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/project.properties: -------------------------------------------------------------------------------- 1 | #Thu Mar 14 17:55:27 CET 2019 2 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/nbproject/project.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | org.netbeans.modules.cnd.makeproject 4 | 5 | 6 | STM32F3_Sine_Square_Gen 7 | c 8 | 9 | h 10 | UTF-8 11 | 12 | 13 | 14 | 15 | Debug 16 | 1 17 | 18 | 19 | Release 20 | 1 21 | 22 | 23 | 24 | false 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/sin_table.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/sin_table.ods -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/sintab.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | //DMA based sine generation needs a full period in a table. 4 | //For 1KHz sine from a FS of 720KHz requires a table based on .5 degree steps 5 | 6 | const uint16_t dmasinetable_1950[] = 7 | { 8 | 2048, 2065, 2082, 2099, 2116, 2133, 2150, 2167, 2184, 2201, 2218, 2235, 2252, 2269, 2286, 2303, 2319, 2336, 2353, 2370, 9 | 2387, 2403, 2420, 2437, 2453, 2470, 2487, 2503, 2520, 2536, 2553, 2569, 2585, 2602, 2618, 2634, 2651, 2667, 2683, 2699, 10 | 2715, 2731, 2747, 2763, 2778, 2794, 2810, 2826, 2841, 2857, 2872, 2887, 2903, 2918, 2933, 2948, 2963, 2978, 2993, 3008, 11 | 3023, 3038, 3052, 3067, 3081, 3096, 3110, 3124, 3138, 3152, 3166, 3180, 3194, 3208, 3222, 3235, 3249, 3262, 3275, 3288, 12 | 3301, 3314, 3327, 3340, 3353, 3365, 3378, 3390, 3403, 3415, 3427, 3439, 3451, 3462, 3474, 3486, 3497, 3508, 3520, 3531, 13 | 3542, 3553, 3563, 3574, 3585, 3595, 3605, 3616, 3626, 3636, 3645, 3655, 3665, 3674, 3683, 3693, 3702, 3711, 3719, 3728, 14 | 3737, 3745, 3754, 3762, 3770, 3778, 3785, 3793, 3801, 3808, 3815, 3822, 3829, 3836, 3843, 3850, 3856, 3862, 3868, 3875, 15 | 3880, 3886, 3892, 3897, 3903, 3908, 3913, 3918, 3922, 3927, 3932, 3936, 3940, 3944, 3948, 3952, 3955, 3959, 3962, 3965, 16 | 3968, 3971, 3974, 3977, 3979, 3981, 3983, 3985, 3987, 3989, 3991, 3992, 3993, 3994, 3995, 3996, 3997, 3997, 3998, 3998, 17 | 3998, 3998, 3998, 3997, 3997, 3996, 3995, 3994, 3993, 3992, 3991, 3989, 3987, 3985, 3983, 3981, 3979, 3977, 3974, 3971, 18 | 3968, 3965, 3962, 3959, 3955, 3952, 3948, 3944, 3940, 3936, 3932, 3927, 3922, 3918, 3913, 3908, 3903, 3897, 3892, 3886, 19 | 3880, 3875, 3868, 3862, 3856, 3850, 3843, 3836, 3829, 3822, 3815, 3808, 3801, 3793, 3785, 3778, 3770, 3762, 3754, 3745, 20 | 3737, 3728, 3719, 3711, 3702, 3693, 3683, 3674, 3665, 3655, 3645, 3636, 3626, 3616, 3605, 3595, 3585, 3574, 3563, 3553, 21 | 3542, 3531, 3520, 3508, 3497, 3486, 3474, 3462, 3451, 3439, 3427, 3415, 3403, 3390, 3378, 3365, 3353, 3340, 3327, 3314, 22 | 3301, 3288, 3275, 3262, 3249, 3235, 3222, 3208, 3194, 3180, 3166, 3152, 3138, 3124, 3110, 3096, 3081, 3067, 3052, 3038, 23 | 3023, 3008, 2993, 2978, 2963, 2948, 2933, 2918, 2903, 2887, 2872, 2857, 2841, 2826, 2810, 2794, 2778, 2763, 2747, 2731, 24 | 2715, 2699, 2683, 2667, 2651, 2634, 2618, 2602, 2585, 2569, 2553, 2536, 2520, 2503, 2487, 2470, 2453, 2437, 2420, 2403, 25 | 2387, 2370, 2353, 2336, 2319, 2303, 2286, 2269, 2252, 2235, 2218, 2201, 2184, 2167, 2150, 2133, 2116, 2099, 2082, 2065, 26 | 2048, 2031, 2014, 1997, 1980, 1963, 1946, 1929, 1912, 1895, 1878, 1861, 1844, 1827, 1810, 1793, 1777, 1760, 1743, 1726, 27 | 1709, 1693, 1676, 1659, 1643, 1626, 1609, 1593, 1576, 1560, 1543, 1527, 1511, 1494, 1478, 1462, 1445, 1429, 1413, 1397, 28 | 1381, 1365, 1349, 1333, 1318, 1302, 1286, 1270, 1255, 1239, 1224, 1209, 1193, 1178, 1163, 1148, 1133, 1118, 1103, 1088, 29 | 1073, 1058, 1044, 1029, 1015, 1000, 986, 972, 958, 944, 930, 916, 902, 888, 874, 861, 847, 834, 821, 808, 30 | 795, 782, 769, 756, 743, 731, 718, 706, 693, 681, 669, 657, 645, 634, 622, 610, 599, 588, 576, 565, 31 | 554, 543, 533, 522, 511, 501, 491, 480, 470, 460, 451, 441, 431, 422, 413, 403, 394, 385, 377, 368, 32 | 359, 351, 342, 334, 326, 318, 311, 303, 295, 288, 281, 274, 267, 260, 253, 246, 240, 234, 228, 221, 33 | 216, 210, 204, 199, 193, 188, 183, 178, 174, 169, 164, 160, 156, 152, 148, 144, 141, 137, 134, 131, 34 | 128, 125, 122, 119, 117, 115, 113, 111, 109, 107, 105, 104, 103, 102, 101, 100, 99, 99, 98, 98, 35 | 98, 98, 98, 99, 99, 100, 101, 102, 103, 104, 105, 107, 109, 111, 113, 115, 117, 119, 122, 125, 36 | 128, 131, 134, 137, 141, 144, 148, 152, 156, 160, 164, 169, 174, 178, 183, 188, 193, 199, 204, 210, 37 | 216, 221, 228, 234, 240, 246, 253, 260, 267, 274, 281, 288, 295, 303, 311, 318, 326, 334, 342, 351, 38 | 359, 368, 377, 385, 394, 403, 413, 422, 431, 441, 451, 460, 470, 480, 491, 501, 511, 522, 533, 543, 39 | 554, 565, 576, 588, 599, 610, 622, 634, 645, 657, 669, 681, 693, 706, 718, 731, 743, 756, 769, 782, 40 | 795, 808, 821, 834, 847, 861, 874, 888, 902, 916, 930, 944, 958, 972, 986, 1000, 1015, 1029, 1044, 1058, 41 | 1073, 1088, 1103, 1118, 1133, 1148, 1163, 1178, 1193, 1209, 1224, 1239, 1255, 1270, 1286, 1302, 1318, 1333, 1349, 1365, 42 | 1381, 1397, 1413, 1429, 1445, 1462, 1478, 1494, 1511, 1527, 1543, 1560, 1576, 1593, 1609, 1626, 1643, 1659, 1676, 1693, 43 | 1709, 1726, 1743, 1760, 1777, 1793, 1810, 1827, 1844, 1861, 1878, 1895, 1912, 1929, 1946, 1963, 1980, 1997, 2014, 2031 44 | }; 45 | 46 | 47 | const uint16_t dmasinetable_1900[] = 48 | { 49 | 2048, 2065, 2081, 2098, 2114, 2131, 2147, 2164, 2181, 2197, 2214, 2230, 2247, 2263, 2280, 2296, 2312, 2329, 2345, 2362, 2378, 2394, 2411, 2427, 2443, 2459, 2475, 2492, 2508, 2524, 50 | 2540, 2556, 2572, 2588, 2604, 2619, 2635, 2651, 2667, 2682, 2698, 2713, 2729, 2744, 2760, 2775, 2790, 2806, 2821, 2836, 2851, 2866, 2881, 2896, 2911, 2925, 2940, 2955, 2969, 2984, 51 | 2998, 3012, 3027, 3041, 3055, 3069, 3083, 3097, 3110, 3124, 3138, 3151, 3165, 3178, 3191, 3205, 3218, 3231, 3244, 3257, 3269, 3282, 3295, 3307, 3319, 3332, 3344, 3356, 3368, 3380, 52 | 3392, 3403, 3415, 3426, 3438, 3449, 3460, 3471, 3482, 3493, 3503, 3514, 3525, 3535, 3545, 3555, 3565, 3575, 3585, 3595, 3604, 3614, 3623, 3632, 3641, 3650, 3659, 3668, 3677, 3685, 53 | 3693, 3702, 3710, 3718, 3726, 3733, 3741, 3748, 3756, 3763, 3770, 3777, 3784, 3790, 3797, 3803, 3810, 3816, 3822, 3828, 3833, 3839, 3844, 3850, 3855, 3860, 3865, 3870, 3874, 3879, 54 | 3883, 3887, 3892, 3896, 3899, 3903, 3906, 3910, 3913, 3916, 3919, 3922, 3925, 3927, 3930, 3932, 3934, 3936, 3938, 3939, 3941, 3942, 3943, 3944, 3945, 3946, 3947, 3947, 3948, 3948, 55 | 3948, 3948, 3948, 3947, 3947, 3946, 3945, 3944, 3943, 3942, 3941, 3939, 3938, 3936, 3934, 3932, 3930, 3927, 3925, 3922, 3919, 3916, 3913, 3910, 3906, 3903, 3899, 3896, 3892, 3887, 56 | 3883, 3879, 3874, 3870, 3865, 3860, 3855, 3850, 3844, 3839, 3833, 3828, 3822, 3816, 3810, 3803, 3797, 3790, 3784, 3777, 3770, 3763, 3756, 3748, 3741, 3733, 3726, 3718, 3710, 3702, 57 | 3693, 3685, 3677, 3668, 3659, 3650, 3641, 3632, 3623, 3614, 3604, 3595, 3585, 3575, 3565, 3555, 3545, 3535, 3525, 3514, 3503, 3493, 3482, 3471, 3460, 3449, 3438, 3426, 3415, 3403, 58 | 3392, 3380, 3368, 3356, 3344, 3332, 3319, 3307, 3295, 3282, 3269, 3257, 3244, 3231, 3218, 3205, 3191, 3178, 3165, 3151, 3138, 3124, 3110, 3097, 3083, 3069, 3055, 3041, 3027, 3012, 59 | 2998, 2984, 2969, 2955, 2940, 2925, 2911, 2896, 2881, 2866, 2851, 2836, 2821, 2806, 2790, 2775, 2760, 2744, 2729, 2713, 2698, 2682, 2667, 2651, 2635, 2619, 2604, 2588, 2572, 2556, 60 | 2540, 2524, 2508, 2492, 2475, 2459, 2443, 2427, 2411, 2394, 2378, 2362, 2345, 2329, 2312, 2296, 2280, 2263, 2247, 2230, 2214, 2197, 2181, 2164, 2147, 2131, 2114, 2098, 2081, 2065, 61 | 2048, 2031, 2015, 1998, 1982, 1965, 1949, 1932, 1915, 1899, 1882, 1866, 1849, 1833, 1816, 1800, 1784, 1767, 1751, 1734, 1718, 1702, 1685, 1669, 1653, 1637, 1621, 1604, 1588, 1572, 62 | 1556, 1540, 1524, 1508, 1492, 1477, 1461, 1445, 1429, 1414, 1398, 1383, 1367, 1352, 1336, 1321, 1306, 1290, 1275, 1260, 1245, 1230, 1215, 1200, 1185, 1171, 1156, 1141, 1127, 1112, 63 | 1098, 1084, 1069, 1055, 1041, 1027, 1013, 999, 986, 972, 958, 945, 931, 918, 905, 891, 878, 865, 852, 839, 827, 814, 801, 789, 777, 764, 752, 740, 728, 716, 704, 693, 681, 670, 658, 64 | 647, 636, 625, 614, 603, 593, 582, 571, 561, 551, 541, 531, 521, 511, 501, 492, 482, 473, 464, 455, 446, 437, 428, 419, 411, 403, 394, 386, 378, 370, 363, 355, 348, 340, 333, 326, 319, 65 | 312, 306, 299, 293, 286, 280, 274, 268, 263, 257, 252, 246, 241, 236, 231, 226, 222, 217, 213, 209, 204, 200, 197, 193, 190, 186, 183, 180, 177, 174, 171, 169, 166, 164, 162, 160, 158, 66 | 157, 155, 154, 153, 152, 151, 150, 149, 149, 148, 148, 148, 148, 148, 149, 149, 150, 151, 152, 153, 154, 155, 157, 158, 160, 162, 164, 166, 169, 171, 174, 177, 180, 183, 186, 190, 193, 67 | 197, 200, 204, 209, 213, 217, 222, 226, 231, 236, 241, 246, 252, 257, 263, 268, 274, 280, 286, 293, 299, 306, 312, 319, 326, 333, 340, 348, 355, 363, 370, 378, 386, 394, 403, 411, 419, 68 | 428, 437, 446, 455, 464, 473, 482, 492, 501, 511, 521, 531, 541, 551, 561, 571, 582, 593, 603, 614, 625, 636, 647, 658, 670, 681, 693, 704, 716, 728, 740, 752, 764, 777, 789, 801, 814, 69 | 827, 839, 852, 865, 878, 891, 905, 918, 931, 945, 958, 972, 986, 999, 1013, 1027, 1041, 1055, 1069, 1084, 1098, 1112, 1127, 1141, 1156, 1171, 1185, 1200, 1215, 1230, 1245, 1260, 1275, 70 | 1290, 1306, 1321, 1336, 1352, 1367, 1383, 1398, 1414, 1429, 1445, 1461, 1477, 1492, 1508, 1524, 1540, 1556, 1572, 1588, 1604, 1621, 1637, 1653, 1669, 1685, 1702, 1718, 1734, 1751, 71 | 1767, 1784, 1800, 1816, 1833, 1849, 1866, 1882, 1899, 1915, 1932, 1949, 1965, 1982, 1998, 2015, 2031, 2048 72 | }; -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/sintab.h: -------------------------------------------------------------------------------- 1 | #ifndef SINTAB_H 2 | #define SINTAB_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #define STEPS_360_DEGREES 720 //For a full period there are 720 steps 9 | #define MAX_COUNT_90_DEGREES 179 //Timer 3 max count 10 | #define HALF_COUNT_90_DEGREES 90 //Timer 3 half way count 11 | #define QUARTER_COUNT_90_DEGREES 45 //Timer 3 quarter way count 12 | #define MAX_PHASE 719 //Max settable phase 13 | 14 | //Reference to the actual table 15 | extern const uint16_t dmasinetable_1950[]; 16 | extern const uint16_t dmasinetable_1900[]; 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif /* SINTAB_H */ 23 | 24 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/stm32f303-128k.ld: -------------------------------------------------------------------------------- 1 | /* useful reference: www.linuxselfhelp.com/gnu/ld/html_chapter/ld_toc.html */ 2 | MEMORY 3 | { 4 | flash : org = 0x08000000, len = 128k 5 | ram : org = 0x20000000, len = 32k 6 | } 7 | 8 | SECTIONS 9 | { 10 | . = ORIGIN(flash); 11 | .text : 12 | { 13 | *(.vectors); /* The interrupt vectors */ 14 | *(.text); 15 | } >flash 16 | 17 | . = ORIGIN(ram); 18 | .data : 19 | { 20 | INIT_DATA_VALUES = LOADADDR(.data); 21 | INIT_DATA_START = .; 22 | *(.data); 23 | INIT_DATA_END = .; 24 | } >ram AT>flash 25 | 26 | BSS_START = .; 27 | .bss : 28 | { 29 | *(.bss); 30 | } >ram 31 | 32 | BSS_END = .; 33 | } 34 | 35 | 36 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/stm32f303_db.h: -------------------------------------------------------------------------------- 1 | #ifndef __STM32F303_H_ 2 | #define __STM32F303_H_ 3 | 4 | #include 5 | 6 | #define __IO volatile 7 | 8 | #define __IM volatile const //Defines 'read only' structure member permissions 9 | #define __OM volatile //Defines 'write only' structure member permissions 10 | #define __IOM volatile //Defines 'read / write' structure member permissions 11 | 12 | //Power Control 13 | typedef struct 14 | { 15 | __IO uint32_t CR; 16 | __IO uint32_t CSR; 17 | } PWR_TypeDef; 18 | 19 | 20 | //Reset and Clock Control 21 | typedef struct 22 | { 23 | __IO uint32_t CR; 24 | __IO uint32_t CFGR; 25 | __IO uint32_t CIR; 26 | __IO uint32_t APB2RSTR; 27 | __IO uint32_t APB1RSTR; 28 | __IO uint32_t AHBENR; 29 | __IO uint32_t APB2ENR; 30 | __IO uint32_t APB1ENR; 31 | __IO uint32_t BDCR; 32 | __IO uint32_t CSR; 33 | __IO uint32_t AHBRSTR; 34 | __IO uint32_t CFGR2; 35 | __IO uint32_t CFGR3; 36 | } RCC_TypeDef; 37 | 38 | //FLASH Registers 39 | typedef struct 40 | { 41 | __IO uint32_t ACR; 42 | __IO uint32_t KEYR; 43 | __IO uint32_t OPTKEYR; 44 | __IO uint32_t SR; 45 | __IO uint32_t CR; 46 | __IO uint32_t AR; 47 | __IO uint32_t RESERVED; 48 | __IO uint32_t OBR; 49 | __IO uint32_t WRPR; 50 | } FLASH_TypeDef; 51 | 52 | //Real-Time Clock 53 | typedef struct 54 | { 55 | __IO uint32_t TR; 56 | __IO uint32_t DR; 57 | __IO uint32_t CR; 58 | __IO uint32_t ISR; 59 | __IO uint32_t PRER; 60 | __IO uint32_t WUTR; 61 | uint32_t RESERVED0; 62 | __IO uint32_t ALRMAR; 63 | __IO uint32_t ALRMBR; 64 | __IO uint32_t WPR; 65 | __IO uint32_t SSR; 66 | __IO uint32_t SHIFTR; 67 | __IO uint32_t TSTR; 68 | __IO uint32_t TSDR; 69 | __IO uint32_t TSSSR; 70 | __IO uint32_t CALR; 71 | __IO uint32_t TAFCR; 72 | __IO uint32_t ALRMASSR; 73 | __IO uint32_t ALRMBSSR; 74 | uint32_t RESERVED7; 75 | __IO uint32_t BKP0R; 76 | __IO uint32_t BKP1R; 77 | __IO uint32_t BKP2R; 78 | __IO uint32_t BKP3R; 79 | __IO uint32_t BKP4R; 80 | __IO uint32_t BKP5R; 81 | __IO uint32_t BKP6R; 82 | __IO uint32_t BKP7R; 83 | __IO uint32_t BKP8R; 84 | __IO uint32_t BKP9R; 85 | __IO uint32_t BKP10R; 86 | __IO uint32_t BKP11R; 87 | __IO uint32_t BKP12R; 88 | __IO uint32_t BKP13R; 89 | __IO uint32_t BKP14R; 90 | __IO uint32_t BKP15R; 91 | } RTC_TypeDef; 92 | 93 | //General Purpose I/O 94 | typedef struct 95 | { 96 | __IO uint32_t MODER; //GPIO port mode register, Address offset: 0x00 97 | __IO uint32_t OTYPER; //GPIO port output type register, Address offset: 0x04 98 | __IO uint32_t OSPEEDR; //GPIO port output speed register, Address offset: 0x08 99 | __IO uint32_t PUPDR; //GPIO port pull-up/pull-down register, Address offset: 0x0C 100 | __IO uint32_t IDR; //GPIO port input data register, Address offset: 0x10 101 | __IO uint32_t ODR; //GPIO port output data register, Address offset: 0x14 102 | __IO uint32_t BSRR; //GPIO port bit set/reset register, Address offset: 0x1A 103 | __IO uint32_t LCKR; //GPIO port configuration lock register, Address offset: 0x1C 104 | __IO uint32_t AFR[2]; //GPIO alternate function registers, Address offset: 0x20-0x24 105 | __IO uint32_t BRR; //GPIO bit reset register, Address offset: 0x28 106 | } GPIO_TypeDef; 107 | 108 | //TIM Timers 109 | typedef struct 110 | { 111 | __IO uint32_t CR1; //TIM control register 1, Address offset: 0x00 112 | __IO uint32_t CR2; //TIM control register 2, Address offset: 0x04 113 | __IO uint32_t SMCR; //TIM slave Mode Control register, Address offset: 0x08 114 | __IO uint32_t DIER; //TIM DMA/interrupt enable register, Address offset: 0x0C 115 | __IO uint32_t SR; //TIM status register, Address offset: 0x10 116 | __IO uint32_t EGR; //TIM event generation register, Address offset: 0x14 117 | __IO uint32_t CCMR1; //TIM capture/compare mode register 1, Address offset: 0x18 118 | __IO uint32_t CCMR2; //TIM capture/compare mode register 2, Address offset: 0x1C 119 | __IO uint32_t CCER; //TIM capture/compare enable register, Address offset: 0x20 120 | __IO uint32_t CNT; //TIM counter register, Address offset: 0x24 121 | __IO uint32_t PSC; //TIM prescaler register, Address offset: 0x28 122 | __IO uint32_t ARR; //TIM auto-reload register, Address offset: 0x2C 123 | __IO uint32_t RCR; //TIM repetition counter register, Address offset: 0x30 124 | __IO uint32_t CCR1; //TIM capture/compare register 1, Address offset: 0x34 125 | __IO uint32_t CCR2; //TIM capture/compare register 2, Address offset: 0x38 126 | __IO uint32_t CCR3; //TIM capture/compare register 3, Address offset: 0x3C 127 | __IO uint32_t CCR4; //TIM capture/compare register 4, Address offset: 0x40 128 | __IO uint32_t BDTR; //TIM break and dead-time register, Address offset: 0x44 129 | __IO uint32_t DCR; //TIM DMA control register, Address offset: 0x48 130 | __IO uint32_t DMAR; //TIM DMA address for full transfer register, Address offset: 0x4C 131 | __IO uint32_t OR; //TIM option register, Address offset: 0x50 132 | __IO uint32_t CCMR3; //TIM capture/compare mode register 3, Address offset: 0x54 133 | __IO uint32_t CCR5; //TIM capture/compare register5, Address offset: 0x58 134 | __IO uint32_t CCR6; //TIM capture/compare register 4, Address offset: 0x5C 135 | }TIM_TypeDef; 136 | 137 | //External Interrupt/Event Controller 138 | typedef struct 139 | { 140 | __IO uint32_t IMR; 141 | __IO uint32_t EMR; 142 | __IO uint32_t RTSR; 143 | __IO uint32_t FTSR; 144 | __IO uint32_t SWIER; 145 | __IO uint32_t PR; 146 | uint32_t RESERVED1; 147 | uint32_t RESERVED2; 148 | __IO uint32_t IMR2; 149 | __IO uint32_t EMR2; 150 | __IO uint32_t RTSR2; 151 | __IO uint32_t FTSR2; 152 | __IO uint32_t SWIER2; 153 | __IO uint32_t PR2; 154 | } EXTI_TypeDef; 155 | 156 | //Structure type to access the System Control Block (SCB). 157 | typedef struct 158 | { 159 | __IM uint32_t CPUID; //Offset: 0x000 (R/ ) CPUID Base Register 160 | __IOM uint32_t ICSR; //Offset: 0x004 (R/W) Interrupt Control and State Register 161 | __IOM uint32_t VTOR; //Offset: 0x008 (R/W) Vector Table Offset Register 162 | __IOM uint32_t AIRCR; //Offset: 0x00C (R/W) Application Interrupt and Reset Control Register 163 | __IOM uint32_t SCR; //Offset: 0x010 (R/W) System Control Register 164 | __IOM uint32_t CCR; //Offset: 0x014 (R/W) Configuration Control Register 165 | __IOM uint8_t SHP[12U]; //Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) 166 | __IOM uint32_t SHCSR; //Offset: 0x024 (R/W) System Handler Control and State Register 167 | __IOM uint32_t CFSR; //Offset: 0x028 (R/W) Configurable Fault Status Register 168 | __IOM uint32_t HFSR; //Offset: 0x02C (R/W) HardFault Status Register 169 | __IOM uint32_t DFSR; //Offset: 0x030 (R/W) Debug Fault Status Register 170 | __IOM uint32_t MMFAR; //Offset: 0x034 (R/W) MemManage Fault Address Register 171 | __IOM uint32_t BFAR; //Offset: 0x038 (R/W) BusFault Address Register 172 | __IOM uint32_t AFSR; //Offset: 0x03C (R/W) Auxiliary Fault Status Register 173 | __IM uint32_t PFR[2U]; //Offset: 0x040 (R/ ) Processor Feature Register 174 | __IM uint32_t DFR; //Offset: 0x048 (R/ ) Debug Feature Register 175 | __IM uint32_t ADR; //Offset: 0x04C (R/ ) Auxiliary Feature Register 176 | __IM uint32_t MMFR[4U]; //Offset: 0x050 (R/ ) Memory Model Feature Register 177 | __IM uint32_t ISAR[5U]; //Offset: 0x060 (R/ ) Instruction Set Attributes Register 178 | uint32_t RESERVED0[5U]; 179 | __IOM uint32_t CPACR; //Offset: 0x088 (R/W) Coprocessor Access Control Register 180 | } SCB_Type; 181 | 182 | //Structure type to access the Nested Vectored Interrupt Controller (NVIC) 183 | typedef struct 184 | { 185 | __IOM uint32_t ISER[8U]; //Offset: 0x000 (R/W) Interrupt Set Enable Register 186 | uint32_t RESERVED0[24U]; 187 | __IOM uint32_t ICER[8U]; //Offset: 0x080 (R/W) Interrupt Clear Enable Register 188 | uint32_t RSERVED1[24U]; 189 | __IOM uint32_t ISPR[8U]; //Offset: 0x100 (R/W) Interrupt Set Pending Register 190 | uint32_t RESERVED2[24U]; 191 | __IOM uint32_t ICPR[8U]; //Offset: 0x180 (R/W) Interrupt Clear Pending Register 192 | uint32_t RESERVED3[24U]; 193 | __IOM uint32_t IABR[8U]; //Offset: 0x200 (R/W) Interrupt Active bit Register 194 | uint32_t RESERVED4[56U]; 195 | __IOM uint8_t IP[240U]; //Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) 196 | uint32_t RESERVED5[644U]; 197 | __OM uint32_t STIR; //Offset: 0xE00 ( /W) Software Trigger Interrupt Register 198 | } NVIC_Type; 199 | 200 | //Structure typedef to access the System Tick Timer 201 | typedef struct 202 | { 203 | __IOM uint32_t CTRL; //Offset: 0x000 (R/W) SysTick Control and Status Register 204 | __IOM uint32_t LOAD; //Offset: 0x004 (R/W) SysTick Reload Value Register 205 | __IOM uint32_t VAL; //Offset: 0x008 (R/W) SysTick Current Value Register 206 | __IM uint32_t CALIB; //Offset: 0x00C (R/ ) SysTick Calibration Register 207 | } STK_Type; 208 | 209 | //DMA channel 210 | typedef struct 211 | { 212 | __IO uint32_t CCR; //DMA channel x configuration register 213 | __IO uint32_t CNDTR; //DMA channel x number of data register 214 | __IO uint32_t CPAR; //DMA channel x peripheral address register 215 | __IO uint32_t CMAR; //DMA channel x memory address register 216 | } DMA_Channel_TypeDef; 217 | 218 | //DMA 219 | typedef struct 220 | { 221 | __IO uint32_t ISR; //DMA interrupt status register, Address offset: 0x00 222 | __IO uint32_t IFCR; //DMA interrupt flag clear register, Address offset: 0x04 223 | } DMA_TypeDef; 224 | 225 | //Digital to Analog Converter 226 | typedef struct 227 | { 228 | __IO uint32_t CR; //DAC control register, Address offset: 0x00 229 | __IO uint32_t SWTRIGR; //DAC software trigger register, Address offset: 0x04 230 | __IO uint32_t DHR12R1; //DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 231 | __IO uint32_t DHR12L1; //DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C 232 | __IO uint32_t DHR8R1; //DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 233 | __IO uint32_t DHR12R2; //DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 234 | __IO uint32_t DHR12L2; //DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 235 | __IO uint32_t DHR8R2; //DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C 236 | __IO uint32_t DHR12RD; //Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 237 | __IO uint32_t DHR12LD; //DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 238 | __IO uint32_t DHR8RD; //DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 239 | __IO uint32_t DOR1; //DAC channel1 data output register, Address offset: 0x2C 240 | __IO uint32_t DOR2; //DAC channel2 data output register, Address offset: 0x30 241 | __IO uint32_t SR; //DAC status register, Address offset: 0x34 242 | } DAC_TypeDef; 243 | 244 | //Analog to digital converter 245 | typedef struct 246 | { 247 | __IO uint32_t ISR; //ADC Interrupt and Status Register, Address offset: 0x00 248 | __IO uint32_t IER; //ADC Interrupt Enable Register, Address offset: 0x04 249 | __IO uint32_t CR; //ADC control register, Address offset: 0x08 250 | __IO uint32_t CFGR; //ADC Configuration register, Address offset: 0x0C 251 | uint32_t RESERVED0; //Reserved, 0x010 252 | __IO uint32_t SMPR1; //ADC sample time register 1, Address offset: 0x14 253 | __IO uint32_t SMPR2; //ADC sample time register 2, Address offset: 0x18 254 | uint32_t RESERVED1; //Reserved, 0x01C 255 | __IO uint32_t TR1; //ADC watchdog threshold register 1, Address offset: 0x20 256 | __IO uint32_t TR2; //ADC watchdog threshold register 2, Address offset: 0x24 257 | __IO uint32_t TR3; //ADC watchdog threshold register 3, Address offset: 0x28 258 | uint32_t RESERVED2; //Reserved, 0x02C 259 | __IO uint32_t SQR1; //ADC regular sequence register 1, Address offset: 0x30 260 | __IO uint32_t SQR2; //ADC regular sequence register 2, Address offset: 0x34 261 | __IO uint32_t SQR3; //ADC regular sequence register 3, Address offset: 0x38 262 | __IO uint32_t SQR4; //ADC regular sequence register 4, Address offset: 0x3C 263 | __IO uint32_t DR; //ADC regular data register, Address offset: 0x40 264 | uint32_t RESERVED3; //Reserved, 0x044 265 | uint32_t RESERVED4; //Reserved, 0x048 266 | __IO uint32_t JSQR; //ADC injected sequence register, Address offset: 0x4C 267 | uint32_t RESERVED5[4]; //Reserved, 0x050 - 0x05C 268 | __IO uint32_t OFR1; //ADC offset register 1, Address offset: 0x60 269 | __IO uint32_t OFR2; //ADC offset register 2, Address offset: 0x64 270 | __IO uint32_t OFR3; //ADC offset register 3, Address offset: 0x68 271 | __IO uint32_t OFR4; //ADC offset register 4, Address offset: 0x6C 272 | uint32_t RESERVED6[4]; //Reserved, 0x070 - 0x07C 273 | __IO uint32_t JDR1; //ADC injected data register 1, Address offset: 0x80 274 | __IO uint32_t JDR2; //ADC injected data register 2, Address offset: 0x84 275 | __IO uint32_t JDR3; //ADC injected data register 3, Address offset: 0x88 276 | __IO uint32_t JDR4; //ADC injected data register 4, Address offset: 0x8C 277 | uint32_t RESERVED7[4]; //Reserved, 0x090 - 0x09C 278 | __IO uint32_t AWD2CR; //ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 279 | __IO uint32_t AWD3CR; //ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 280 | uint32_t RESERVED8; //Reserved, 0x0A8 281 | uint32_t RESERVED9; //Reserved, 0x0AC 282 | __IO uint32_t DIFSEL; //ADC Differential Mode Selection Register, Address offset: 0xB0 283 | __IO uint32_t CALFACT; //ADC Calibration Factors, Address offset: 0xB4 284 | } ADC_TypeDef; 285 | 286 | //Common registers of an ADC pair 287 | typedef struct 288 | { 289 | __IO uint32_t CSR; //ADC Common status register, Address offset: ADC1/3 base address + 0x300 290 | uint32_t RESERVED; //Reserved, Address offset: ADC1/3 base address + 0x304 291 | __IO uint32_t CCR; //ADC common control register, Address offset: ADC1/3 base address + 0x308 292 | __IO uint32_t CDR; //ADC common regular data register for dual and triple modes, Address offset: ADC1/3 base address + 0x30C 293 | } ADC_Common_TypeDef; 294 | 295 | //Universal Serial Bus Full Speed Device 296 | typedef struct 297 | { 298 | __IO uint16_t EP0R; //USB Endpoint 0 register, Address offset: 0x00 299 | __IO uint16_t RESERVED0; //Reserved 300 | __IO uint16_t EP1R; //USB Endpoint 1 register, Address offset: 0x04 301 | __IO uint16_t RESERVED1; //Reserved 302 | __IO uint16_t EP2R; //USB Endpoint 2 register, Address offset: 0x08 303 | __IO uint16_t RESERVED2; //Reserved 304 | __IO uint16_t EP3R; //USB Endpoint 3 register, Address offset: 0x0C 305 | __IO uint16_t RESERVED3; //Reserved 306 | __IO uint16_t EP4R; //USB Endpoint 4 register, Address offset: 0x10 307 | __IO uint16_t RESERVED4; //Reserved 308 | __IO uint16_t EP5R; //USB Endpoint 5 register, Address offset: 0x14 309 | __IO uint16_t RESERVED5; //Reserved 310 | __IO uint16_t EP6R; //USB Endpoint 6 register, Address offset: 0x18 311 | __IO uint16_t RESERVED6; //Reserved 312 | __IO uint16_t EP7R; //USB Endpoint 7 register, Address offset: 0x1C 313 | __IO uint16_t RESERVED7[17]; //Reserved 314 | __IO uint16_t CNTR; //Control register, Address offset: 0x40 315 | __IO uint16_t RESERVED8; //Reserved 316 | __IO uint16_t ISTR; //Interrupt status register, Address offset: 0x44 317 | __IO uint16_t RESERVED9; //Reserved 318 | __IO uint16_t FNR; //Frame number register, Address offset: 0x48 319 | __IO uint16_t RESERVEDA; //Reserved 320 | __IO uint16_t DADDR; //Device address register, Address offset: 0x4C 321 | __IO uint16_t RESERVEDB; //Reserved 322 | __IO uint16_t BTABLE; //Buffer Table address register, Address offset: 0x50 323 | __IO uint16_t RESERVEDC; //Reserved 324 | } USB_TypeDef; 325 | 326 | //Packet memory entry 327 | typedef struct 328 | { 329 | __IO uint16_t DATA; 330 | uint16_t RESERVED; 331 | }PMA_ENTRY; 332 | 333 | //Structure for PMA 334 | typedef struct 335 | { 336 | PMA_ENTRY MEMORY[256]; 337 | } PMA_TypeDef; 338 | 339 | //Structure for Buffer Descriptor Table 340 | typedef struct 341 | { 342 | PMA_ENTRY TX_ADDRESS; 343 | PMA_ENTRY TX_COUNT; 344 | PMA_ENTRY RX_ADDRESS; 345 | PMA_ENTRY RX_COUNT; 346 | } BTABLE_ENTRY; 347 | 348 | //Structure for endpoint descriptors 349 | typedef struct 350 | { 351 | BTABLE_ENTRY EPD[8]; 352 | } BTABLE_TypeDef; 353 | 354 | typedef union 355 | { 356 | uint16_t word; 357 | struct BYTES 358 | { 359 | uint8_t low; 360 | uint8_t high; 361 | } bytes; 362 | } wbcombi; 363 | 364 | 365 | #define PMA_BASE (0x40006000L) //USB_IP Packet Memory Area base address 366 | 367 | #define PMA ((PMA_TypeDef *) PMA_BASE) 368 | #define EPBTABLE ((BTABLE_TypeDef *) PMA_BASE) 369 | 370 | 371 | #define RCC_BASE 0x40021000 372 | #define PWR_BASE 0x40007000 373 | #define RTC_BASE 0x40002800 374 | #define EXTI_BASE 0x40010400 375 | 376 | #define USB_BASE 0x40005C00 377 | 378 | #define GPIOA_BASE 0x48000000 379 | #define GPIOB_BASE 0x48000400 380 | #define GPIOC_BASE 0x48000800 381 | 382 | #define DMA1_BASE 0x40020000 383 | #define DMA1_Channel1_BASE 0x40020008 384 | #define DMA1_Channel2_BASE 0x4002001C 385 | #define DMA1_Channel3_BASE 0x40020030 386 | #define DMA1_Channel4_BASE 0x40020044 387 | #define DMA1_Channel5_BASE 0x40020058 388 | #define DMA1_Channel6_BASE 0x4002006C 389 | #define DMA1_Channel7_BASE 0x40020080 390 | #define DMA2_BASE 0x40020400 391 | #define DMA2_Channel1_BASE 0x40020408 392 | #define DMA2_Channel2_BASE 0x4002041C 393 | #define DMA2_Channel3_BASE 0x40020430 394 | #define DMA2_Channel4_BASE 0x40020444 395 | #define DMA2_Channel5_BASE 0x40020458 396 | 397 | #define ADC1_BASE 0x50000000 398 | #define ADC2_BASE 0x50000100 399 | #define ADC1_2_COMMON_BASE 0x50000300 400 | #define ADC3_BASE 0x50000400 401 | #define ADC4_BASE 0x50000500 402 | #define ADC3_4_COMMON_BASE 0x50000700 403 | 404 | #define DAC1_BASE 0x40007400 405 | 406 | #define TIM1_BASE 0x40012C00 407 | 408 | #define TIM2_BASE 0x40000000 409 | #define TIM3_BASE 0x40000400 410 | #define TIM4_BASE 0x40000800 411 | 412 | #define USART_BASE 0x40013800 413 | 414 | #define NVIC_BASE 0xE000E100 415 | #define SCB_BASE 0xE000ED00 416 | #define STK_BASE 0xE000E010 417 | 418 | #define FLASH_BASE 0x40022000 419 | 420 | #define FLASH_START 0x08000000 421 | 422 | 423 | 424 | 425 | 426 | #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) 427 | #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) 428 | #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) 429 | 430 | #define TIM1 ((TIM_TypeDef *)TIM1_BASE) 431 | #define TIM2 ((TIM_TypeDef *)TIM2_BASE) 432 | #define TIM3 ((TIM_TypeDef *)TIM3_BASE) 433 | #define TIM4 ((TIM_TypeDef *)TIM4_BASE) 434 | 435 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 436 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 437 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 438 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 439 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 440 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 441 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 442 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 443 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 444 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 445 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 446 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 447 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 448 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 449 | 450 | #define DAC1 ((DAC_TypeDef *)DAC1_BASE) 451 | 452 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 453 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 454 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 455 | #define ADC4 ((ADC_TypeDef *) ADC4_BASE) 456 | #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE) 457 | #define ADC34_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE) 458 | 459 | #define PWR ((PWR_TypeDef *)PWR_BASE) 460 | #define RCC ((RCC_TypeDef *)RCC_BASE) 461 | #define USB ((USB_TypeDef *)USB_BASE) 462 | #define FLASH ((FLASH_TypeDef *)FLASH_BASE) 463 | #define RTC ((RTC_TypeDef *)RTC_BASE) 464 | #define EXTI ((EXTI_TypeDef *)EXTI_BASE) 465 | #define SCB ((SCB_Type *)SCB_BASE) 466 | #define NVIC ((NVIC_Type *)NVIC_BASE) 467 | #define STK ((STK_Type *)STK_BASE) 468 | 469 | 470 | #define DMA1_CH3_IRQn 13 471 | #define USB_LP_CAN1_RX0_IRQn 20 472 | #define TIM1_UP_IRQn 25 473 | #define TIM2_IRQn 28 474 | #define TIM3_IRQn 29 475 | 476 | 477 | #define FLASH_ACR_LATENCY_2 0x00000004 478 | #define FLASH_ACR_PRFTBE 0x00000010 //Prefetch Buffer Enable 479 | 480 | #define RCC_CFGR_PLLMULL9 0x001C0000 //PLL input clock*9 481 | #define RCC_CFGR_PLLSRC 0x00010000 //PLL entry clock source 482 | #define RCC_CFGR_PPRE1_DIV2 0x00000400 //HCLK divided by 2 483 | #define RCC_CFGR_PPRE2_DIV2 0x00002000 //HCLK divided by 2 484 | 485 | #define RCC_CR_HSEON 0x00010000 //External High Speed clock enable 486 | #define RCC_CR_HSERDY 0x00020000 //External High Speed clock ready flag 487 | 488 | #define RCC_CR_PLLON 0x01000000 //PLL enable 489 | #define RCC_CR_PLLRDY 0x02000000 //PLL clock ready flag 490 | 491 | #define RCC_CFGR_SW_PLL 0x00000002 //PLL selected as system clock 492 | #define RCC_CFGR_SWS_PLL 0x00000008 //PLL used as system clock 493 | 494 | // Bit definition for RCC_AHBENR register 495 | #define RCC_AHBENR_DMA1EN 0x00000001 //DMA1 clock enable 496 | #define RCC_AHBENR_DMA2EN 0x00000002 //DMA2 clock enable 497 | #define RCC_AHBENR_SRAMEN 0x00000004 //SRAM interface clock enable 498 | #define RCC_AHBENR_FLITFEN 0x00000010 //FLITF clock enable 499 | #define RCC_AHBENR_CRCEN 0x00000040 //CRC clock enable 500 | #define RCC_AHBENR_GPIOAEN 0x00020000 //GPIOA clock enable 501 | #define RCC_AHBENR_GPIOBEN 0x00040000 //GPIOB clock enable 502 | #define RCC_AHBENR_GPIOCEN 0x00080000 //GPIOC clock enable 503 | #define RCC_AHBENR_GPIODEN 0x00100000 //GPIOD clock enable 504 | #define RCC_AHBENR_GPIOEEN 0x00200000 //GPIOE clock enable 505 | #define RCC_AHBENR_GPIOFEN 0x00400000 //GPIOF clock enable 506 | #define RCC_AHBENR_TSCEN 0x01000000 //TS clock enable 507 | #define RCC_AHBENR_ADC12EN 0x10000000 //ADC1 & ADC2 clock enable 508 | #define RCC_AHBENR_ADC34EN 0x20000000 //ADC3 & ADC4 clock enable 509 | 510 | // Bit definition for RCC_APB2ENR register 511 | #define RCC_APB2ENR_SYSCFGEN 0x00000001 //SYSCFG clock enable 512 | #define RCC_APB2ENR_TIM1EN 0x00000800 //TIM1 clock enable 513 | #define RCC_APB2ENR_SPI1EN 0x00001000 //SPI1 clock enable 514 | #define RCC_APB2ENR_TIM8EN 0x00002000 //TIM8 clock enable 515 | #define RCC_APB2ENR_USART1EN 0x00004000 //USART1 clock enable 516 | #define RCC_APB2ENR_TIM15EN 0x00010000 //TIM15 clock enable 517 | #define RCC_APB2ENR_TIM16EN 0x00020000 //TIM16 clock enable 518 | #define RCC_APB2ENR_TIM17EN 0x00040000 //TIM17 clock enable 519 | 520 | //Bit definition for RCC_APB1ENR register 521 | #define RCC_APB1ENR_TIM2EN 0x00000001 //Timer 2 clock enable 522 | #define RCC_APB1ENR_TIM3EN 0x00000002 //Timer 3 clock enable 523 | #define RCC_APB1ENR_TIM4EN 0x00000004 //Timer 4 clock enable 524 | #define RCC_APB1ENR_TIM6EN 0x00000010 //Timer 6 clock enable 525 | #define RCC_APB1ENR_TIM7EN 0x00000020 //Timer 7 clock enable 526 | #define RCC_APB1ENR_WWDGEN 0x00000800 //Window Watchdog clock enable 527 | #define RCC_APB1ENR_SPI2EN 0x00004000 //SPI2 clock enable 528 | #define RCC_APB1ENR_SPI3EN 0x00008000 //SPI3 clock enable 529 | #define RCC_APB1ENR_USART2EN 0x00020000 //USART 2 clock enable 530 | #define RCC_APB1ENR_USART3EN 0x00040000 //USART 3 clock enable 531 | #define RCC_APB1ENR_UART4EN 0x00080000 //UART 4 clock enable 532 | #define RCC_APB1ENR_UART5EN 0x00100000 //UART 5 clock enable 533 | #define RCC_APB1ENR_I2C1EN 0x00200000 //I2C 1 clock enable 534 | #define RCC_APB1ENR_I2C2EN 0x00400000 //I2C 2 clock enable 535 | #define RCC_APB1ENR_USBEN 0x00800000 //USB clock enable 536 | #define RCC_APB1ENR_CANEN 0x02000000 //CAN clock enable 537 | #define RCC_APB1ENR_PWREN 0x10000000 //PWR clock enable 538 | #define RCC_APB1ENR_DAC1EN 0x20000000 //DAC 1 clock enable 539 | 540 | 541 | #define PWR_CR_DBP 0x00000100 //Disable Backup Domain write protection 542 | 543 | //Bit definition for RCC_CSR register 544 | #define RCC_CSR_LSION 0x00000001 //Internal Low Speed oscillator enable 545 | #define RCC_CSR_LSIRDY 0x00000002 //Internal Low Speed oscillator Ready 546 | #define RCC_CSR_RMVF 0x01000000 //Remove reset flag 547 | #define RCC_CSR_PINRSTF 0x04000000 //PIN reset flag 548 | #define RCC_CSR_PORRSTF 0x08000000 //POR/PDR reset flag 549 | #define RCC_CSR_SFTRSTF 0x10000000 //Software Reset flag 550 | #define RCC_CSR_IWDGRSTF 0x20000000 //Independent Watchdog reset flag 551 | #define RCC_CSR_WWDGRSTF 0x40000000 //Window watchdog reset flag 552 | #define RCC_CSR_LPWRRSTF 0x80000000 //Low-Power reset flag 553 | 554 | //Bit definition for RCC_BDCR register 555 | #define RCC_BDCR_LSEON 0x00000001 //External Low Speed oscillator enable 556 | #define RCC_BDCR_LSERDY 0x00000002 //External Low Speed oscillator Ready 557 | #define RCC_BDCR_LSEBYP 0x00000004 //External Low Speed oscillator Bypass 558 | 559 | //RTC configuration 560 | #define RCC_BDCR_RTCSEL 0x00000300 //RTCSEL[1:0] bits (RTC clock source selection) 561 | #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000 //No clock 562 | #define RCC_BDCR_RTCSEL_LSE 0x00000100 //LSE oscillator clock used as RTC clock 563 | #define RCC_BDCR_RTCSEL_LSI 0x00000200 //LSI oscillator clock used as RTC clock 564 | #define RCC_BDCR_RTCSEL_HSE 0x00000300 //HSE oscillator clock divided by 128 used as RTC clock 565 | 566 | #define RCC_BDCR_RTCEN 0x00008000 //RTC clock enable 567 | #define RCC_BDCR_BDRST 0x00010000 //Backup domain software reset 568 | 569 | #define RTC_CRL_RSF 0x00000008 //Registers Synchronized Flag 570 | #define RTC_CRL_CNF 0x00000010 //Configuration Flag 571 | #define RTC_CRL_RTOFF 0x00000020 //RTC operation OFF 572 | 573 | 574 | #define TIM_CCER_CC1E 0x00000001 //Capture/Compare 1 output enable 575 | #define TIM_CCER_CC1P 0x00000002 //Capture/Compare 1 output Polarity 576 | 577 | #define TIM_CCER_CC2E 0x00000010 //Capture/Compare 2 output enable 578 | #define TIM_CCER_CC2P 0x00000020 //Capture/Compare 2 output Polarity 579 | 580 | #define TIM_CCER_CC3E 0x00000100 //Capture/Compare 3 output enable 581 | #define TIM_CCER_CC3P 0x00000200 //Capture/Compare 3 output Polarity 582 | 583 | #define TIM_CCER_CC4E 0x00001000 //Capture/Compare 4 output enable 584 | #define TIM_CCER_CC4P 0x00002000 //Capture/Compare 4 output Polarity 585 | 586 | 587 | #define TIM_CR2_MMS 0x00000070 //MMS[2:0] bits (Master Mode Selection) 588 | #define TIM_CR2_MMS_0 0x00000010 589 | #define TIM_CR2_MMS_1 0x00000020 590 | #define TIM_CR2_MMS_2 0x00000040 591 | 592 | #define TIM_CR1_CEN 0x00000001 //Counter enable 593 | 594 | #define TIM_CR1_ARPE 0x00000080 //Auto-reload preload enable 595 | 596 | #define TIM_CR1_CMS 0x00000060 //CMS[1:0] bits (Center-aligned mode selection) 597 | #define TIM_CR1_CMS_0 0x00000020 598 | #define TIM_CR1_CMS_1 0x00000040 599 | 600 | 601 | 602 | #define TIM_SMCR_SMS 0x00010007 //SMS[2:0] bits (Slave mode selection) 603 | #define TIM_SMCR_SMS_0 0x00000001 604 | #define TIM_SMCR_SMS_1 0x00000002 605 | #define TIM_SMCR_SMS_2 0x00000004 606 | #define TIM_SMCR_SMS_3 0x00010000 607 | 608 | #define TIM_CCMR1_OC1PE 0x00000008 //Output Compare 1 Preload enable 609 | 610 | #define TIM_CCMR1_OC1M 0x00010070 //OC1M[2:0] bits (Output Compare 1 Mode) 611 | #define TIM_CCMR1_OC1M_0 0x00000010 612 | #define TIM_CCMR1_OC1M_1 0x00000020 613 | #define TIM_CCMR1_OC1M_2 0x00000040 614 | #define TIM_CCMR1_OC1M_3 0x00010000 615 | 616 | 617 | #define TIM_CCMR1_OC2M 0x01007000 //OC2M[2:0] bits (Output Compare 2 Mode) 618 | #define TIM_CCMR1_OC2M_0 0x00001000 619 | #define TIM_CCMR1_OC2M_1 0x00002000 620 | #define TIM_CCMR1_OC2M_2 0x00004000 621 | #define TIM_CCMR1_OC2M_3 0x01000000 622 | 623 | 624 | #define TIM_CCMR2_OC3M 0x00010070 //OC1M[2:0] bits (Output Compare 3 Mode) 625 | #define TIM_CCMR2_OC3M_0 0x00000010 626 | #define TIM_CCMR2_OC3M_1 0x00000020 627 | #define TIM_CCMR2_OC3M_2 0x00000040 628 | #define TIM_CCMR2_OC3M_3 0x00010000 629 | 630 | 631 | #define TIM_CCMR2_OC4M 0x01007000 //OC2M[2:0] bits (Output Compare 4 Mode) 632 | #define TIM_CCMR2_OC4M_0 0x00001000 633 | #define TIM_CCMR2_OC4M_1 0x00002000 634 | #define TIM_CCMR2_OC4M_2 0x00004000 635 | #define TIM_CCMR2_OC4M_3 0x01000000 636 | 637 | 638 | #define TIM_BDTR_MOE 0x00008000 //Main Output enable 639 | 640 | #define TIM_DIER_UIE 0x00000001 //Update interrupt enable 641 | 642 | #define TIM_DIER_UDE 0x00000100 //Update DMA request enable 643 | 644 | #define TIM_DIER_CC1IE 0x00000002 //Capture/Compare 1 interrupt enable 645 | 646 | 647 | #define TIM_SR_CC1IF 0x00000002 //Capture/Compare 1 interrupt Flag 648 | 649 | 650 | #define AFIO_MAPR_TIM3_REMAP_1 0x00000800 //Timer3 pins on alternate function pins 651 | 652 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE 0x02000000 //JTAG-DP Disabled and SW-DP Enabled 653 | 654 | 655 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 656 | 657 | #define EXTI_Line18 ((uint32_t)0x40000) //External interrupt line 18 Connected to the USB Device/USB OTG FS 658 | 659 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) //2 bits for pre-emption priority, 2 bits for subpriority 660 | 661 | #define STK_CTRL_ENABLE 0x00000001 //Enable the system timer 662 | #define STK_CTRL_INT_ENABLE 0x00000002 //Enable the system timer interrupt 663 | #define STK_CTRL_CLK_CPU 0x00000004 //Select the cpu clock as system timer input clock 664 | #define STK_CTRL_OVERFLOW 0x00010000 //Overflow flag 665 | 666 | 667 | #define USB_CNTR_SOFM 0x00000200 //Start Of Frame Interrupt Mask 668 | #define USB_CNTR_RESETM 0x00000400 //RESET Interrupt Mask 669 | #define USB_CNTR_SUSPM 0x00000800 //Suspend mode Interrupt Mask 670 | #define USB_CNTR_CTRM 0x00008000 //Correct Transfer Interrupt Mask 671 | 672 | #define USB_EP_TX_VALID 0x00000030 //EndPoint TX VALID 673 | #define USB_EP_TX_NAK 0x00000020 //EndPoint TX NAKed 674 | 675 | #define USB_EP_CTR_RX 0x00008000 //EndPoint Correct TRansfer RX 676 | #define USB_EPRX_STAT 0x00003000 //EndPoint RX STATus bit field 677 | #define USB_EP_SETUP 0x00000800 //EndPoint SETUP 678 | #define USB_EP_T_FIELD 0x00000600 //EndPoint TYPE 679 | #define USB_EP_KIND 0x00000100 //EndPoint KIND 680 | #define USB_EP_CTR_TX 0x00000080 //EndPoint Correct TRansfer TX 681 | #define USB_EPTX_STAT 0x00000030 //EndPoint TX STATus bit field 682 | #define USB_EPADDR_FIELD 0x0000000F //EndPoint ADDRess FIELD 683 | 684 | #define USB_EPREG_MASK (USB_EP_CTR_RX | USB_EP_SETUP | USB_EP_T_FIELD | USB_EP_KIND | USB_EP_CTR_TX | USB_EPADDR_FIELD) 685 | 686 | #define USB_ISTR_EP_ID 0x0000000F //Endpoint Identifier 687 | #define USB_ISTR_ESOF 0x00000100 //Expected Start Of Frame 688 | #define USB_ISTR_SOF 0x00000200 //Start Of Frame 689 | #define USB_ISTR_RESET 0x00000400 //USB RESET request 690 | #define USB_ISTR_SUSP 0x00000800 //Suspend mode request 691 | #define USB_ISTR_WKUP 0x00001000 //Wake up 692 | #define USB_ISTR_ERR 0x00002000 //Error 693 | #define USB_ISTR_PMAOVR 0x00004000 //Packet Memory Area Over / Underrun 694 | #define USB_ISTR_CTR 0x00008000 //Correct Transfer 695 | 696 | #define USB_EP_BULK 0x00000000 //EndPoint BULK 697 | #define USB_EP_CONTROL 0x00000200 //EndPoint CONTROL 698 | #define USB_EP_INTERRUPT 0x00000600 //EndPoint INTERRUPT 699 | 700 | #define USB_EP_RX_DIS 0x00000000 //EndPoint RX DISabled 701 | #define USB_EP_RX_VALID 0x00003000 //EndPoint RX VALID 702 | 703 | #define USB_DADDR_EF 0x00000080 //Enable Function 704 | 705 | 706 | 707 | 708 | 709 | 710 | //Bit definition for DAC_CR register 711 | #define DAC_CR_EN1 0x00000001 //DAC channel1 enable 712 | #define DAC_CR_BOFF1 0x00000002 //DAC channel1 output buffer disable 713 | #define DAC_CR_TEN1 0x00000004 //DAC channel1 Trigger enable 714 | 715 | #define DAC_CR_TSEL1 0x00000038 //TSEL1[2:0] (DAC channel1 Trigger selection) 716 | #define DAC_CR_TSEL1_0 0x00000008 717 | #define DAC_CR_TSEL1_1 0x00000010 718 | #define DAC_CR_TSEL1_2 0x00000020 719 | 720 | #define DAC_CR_TSEL1_SOFTWARE 0x00000038 721 | 722 | 723 | #define DAC_CR_WAVE1 0x000000C0 //WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) 724 | #define DAC_CR_WAVE1_0 0x00000040 725 | #define DAC_CR_WAVE1_1 0x00000080 726 | 727 | #define DAC_CR_MAMP1 0x00000F00 //MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) 728 | #define DAC_CR_MAMP1_0 0x00000100 729 | #define DAC_CR_MAMP1_1 0x00000200 730 | #define DAC_CR_MAMP1_2 0x00000400 731 | #define DAC_CR_MAMP1_3 0x00000800 732 | 733 | #define DAC_CR_DMAEN1 0x00001000 //DAC channel1 DMA enable 734 | #define DAC_CR_DMAUDRIE1 0x00002000 //DAC channel1 DMA underrun IT enable 735 | #define DAC_CR_EN2 0x00010000 //DAC channel2 enable 736 | #define DAC_CR_BOFF2 0x00020000 //DAC channel2 output buffer disable 737 | #define DAC_CR_TEN2 0x00040000 //DAC channel2 Trigger enable 738 | 739 | #define DAC_CR_TSEL2 0x00380000 //TSEL2[2:0] (DAC channel2 Trigger selection) 740 | #define DAC_CR_TSEL2_0 0x00080000 741 | #define DAC_CR_TSEL2_1 0x00100000 742 | #define DAC_CR_TSEL2_2 0x00200000 743 | 744 | #define DAC_CR_WAVE2 0x00C00000 //WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) 745 | #define DAC_CR_WAVE2_0 0x00400000 746 | #define DAC_CR_WAVE2_1 0x00800000 747 | 748 | #define DAC_CR_MAMP2 0x0F000000 //MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) 749 | #define DAC_CR_MAMP2_0 0x01000000 750 | #define DAC_CR_MAMP2_1 0x02000000 751 | #define DAC_CR_MAMP2_2 0x04000000 752 | #define DAC_CR_MAMP2_3 0x08000000 753 | 754 | #define DAC_CR_DMAEN2 0x10000000 //DAC channel2 DMA enabled 755 | #define DAC_CR_DMAUDRIE2 0x20000000 //DAC channel2 DMA underrun IT enable 756 | 757 | //Bit definition for DAC_SWTRIGR register 758 | #define DAC_SWTRIGR_SWTRIG1 0x00000001 //DAC channel1 software trigger 759 | #define DAC_SWTRIGR_SWTRIG2 0x00000002 //DAC channel2 software trigger 760 | 761 | //Bit definition for DAC_DHR12R1 register 762 | #define DAC_DHR12R1_DACC1DHR 0x00000FFF //DAC channel1 12-bit Right aligned data 763 | 764 | //Bit definition for DAC_DHR12L1 register 765 | #define DAC_DHR12L1_DACC1DHR 0x0000FFF0 //DAC channel1 12-bit Left aligned data 766 | 767 | //Bit definition for DAC_DHR8R1 register 768 | #define DAC_DHR8R1_DACC1DHR 0x000000FF //DAC channel1 8-bit Right aligned data 769 | 770 | //Bit definition for DAC_DHR12R2 register 771 | #define DAC_DHR12R2_DACC2DHR 0x00000FFF //DAC channel2 12-bit Right aligned data 772 | 773 | //Bit definition for DAC_DHR12L2 register 774 | #define DAC_DHR12L2_DACC2DHR 0x0000FFF0 //DAC channel2 12-bit Left aligned data 775 | 776 | //Bit definition for DAC_DHR8R2 register 777 | #define DAC_DHR8R2_DACC2DHR 0x000000FF //DAC channel2 8-bit Right aligned data 778 | 779 | //Bit definition for DAC_DHR12RD register 780 | #define DAC_DHR12RD_DACC1DHR 0x00000FFF //DAC channel1 12-bit Right aligned data 781 | #define DAC_DHR12RD_DACC2DHR 0x0FFF0000 //DAC channel2 12-bit Right aligned data 782 | 783 | //Bit definition for DAC_DHR12LD register 784 | #define DAC_DHR12LD_DACC1DHR 0x0000FFF0 //DAC channel1 12-bit Left aligned data 785 | #define DAC_DHR12LD_DACC2DHR 0xFFF00000 //DAC channel2 12-bit Left aligned data 786 | 787 | //Bit definition for DAC_DHR8RD register 788 | #define DAC_DHR8RD_DACC1DHR 0x000000FF //DAC channel1 8-bit Right aligned data 789 | #define DAC_DHR8RD_DACC2DHR 0x0000FF00 //DAC channel2 8-bit Right aligned data 790 | 791 | //Bit definition for DAC_DOR1 register 792 | #define DAC_DOR1_DACC1DOR 0x00000FFF //DAC channel1 data output 793 | 794 | //Bit definition for DAC_DOR2 register 795 | #define DAC_DOR2_DACC2DOR 0x00000FFF //DAC channel2 data output 796 | 797 | //Bit definition for DAC_SR register 798 | #define DAC_SR_DMAUDR1 0x00002000 //DAC channel1 DMA underrun flag 799 | #define DAC_SR_DMAUDR2 0x20000000 //DAC channel2 DMA underrun flag 800 | 801 | //ADC defines 802 | 803 | #define ADC_ISR_ADRDY 0x00000001 //ADC ready flag 804 | 805 | 806 | 807 | #define ADC_CR_ADEN 0x00000001 //ADC enable 808 | 809 | #define ADC_CR_ADCAL 0x80000000 //ADC calibration 810 | 811 | #define ADC_CR_ADVREG_INTERMEDIATE 0x00000000 //Set ADC voltage regulator to intermediate state 812 | #define ADC_CR_ADVREG_ON 0x10000000 //Set ADC voltage regulator to on state 813 | #define ADC_CR_ADVREG_OFF 0x20000000 //Set ADC voltage regulator to off state 814 | 815 | #define ADC_SQR1_SQ1_POS 6 //Position of lsb for first serquence channel selector 816 | #define ADC_SQR1_SQ1_MSK 0x000007C0 //Bit mask for first serquence channel selector 817 | 818 | 819 | //Sample times are in adc clock cycles plus one half cycle. (So ADC_SAMPLE_TIME_7 means 7.5 adc clock cycles) 820 | #define ADC_SAMPLE_TIME_1 0 821 | #define ADC_SAMPLE_TIME_2 1 822 | #define ADC_SAMPLE_TIME_4 2 823 | #define ADC_SAMPLE_TIME_7 3 824 | #define ADC_SAMPLE_TIME_19 4 825 | #define ADC_SAMPLE_TIME_61 5 826 | #define ADC_SAMPLE_TIME_181 6 827 | #define ADC_SAMPLE_TIME_601 7 828 | 829 | #define ADC_SMPR1_CH3_POS 9 //Position of lsb for third channel sample time setting 830 | #define ADC_SMPR1_CH3_MSK 0x00000E00 //Bit mask for third channel sample time setting 831 | 832 | 833 | #define ADC_CCR_CKMODE_ASYNC 0x00000000 //Asynchronous clock mode 834 | #define ADC_CCR_CKMODE_HCLK_1 0x00010000 //Synchronous clock mode, HCLK / 1 835 | #define ADC_CCR_CKMODE_HCLK_2 0x00020000 //Synchronous clock mode, HCLK / 2 836 | #define ADC_CCR_CKMODE_HCLK_4 0x00030000 //Synchronous clock mode, HCLK / 4 837 | 838 | #define ADC_CCR_MDMA_OFF 0x00000000 //DMA in dual mode disabled 839 | #define ADC_CCR_MDMA_10_12_BIT 0x00008000 //DMA in dual mode set for 10 or 12 bits 840 | #define ADC_CCR_MDMA_6_8_BIT 0x0000C000 //DMA in dual mode set for 6 or 8 bits 841 | 842 | #define ADC_CCR_DMACFG_CIRCULAIR 0x00002000 //DMA in circulair mode 843 | 844 | #define ADC_CCR_MULTI_RS 0x00000006 //Multi mode regulair simultaneous only 845 | 846 | 847 | //DMA definitions 848 | #define DMA_CCR_EN 0x00000001 //Channel enable 849 | #define DMA_CCR_TCIE 0x00000002 //Transfer complete interrupt enable 850 | #define DMA_CCR_HTIE 0x00000004 //Half Transfer interrupt enable 851 | #define DMA_CCR_TEIE 0x00000008 //Transfer error interrupt enable 852 | #define DMA_CCR_DIR 0x00000010 //Data transfer direction 853 | #define DMA_CCR_CIRC 0x00000020 //Circular mode 854 | #define DMA_CCR_PINC 0x00000040 //Peripheral increment mode 855 | #define DMA_CCR_MINC 0x00000080 //Memory increment mode 856 | 857 | #define DMA_CCR_PSIZE 0x00000300 //PSIZE[1:0] bits (Peripheral size) 858 | #define DMA_CCR_PSIZE_0 0x00000100 859 | #define DMA_CCR_PSIZE_1 0x00000200 860 | 861 | #define DMA_CCR_MSIZE 0x00000C00 //MSIZE[1:0] bits (Memory size) 862 | #define DMA_CCR_MSIZE_0 0x00000400 863 | #define DMA_CCR_MSIZE_1 0x00000800 864 | 865 | #define DMA_CCR_PL 0x00003000 //PL[1:0] bits(Channel Priority level) 866 | #define DMA_CCR_PL_0 0x00001000 867 | #define DMA_CCR_PL_1 0x00002000 868 | 869 | #define DMA_CCR_MEM2MEM 0x00004000 //Memory to memory mode 870 | 871 | 872 | 873 | 874 | //Bitmap for the gpio settings 875 | //Bit 0:1 Mode 876 | //Bit 4 Output type 877 | //Bit 8:9 Output speed 878 | //Bit 12:13 Pull-up pull-down settings 879 | 880 | #define GPIO_MODE_MASK 0x00000003 881 | #define GPIO_TYPE_MASK 0x00000010 882 | #define GPIO_SPEED_MASK 0x00000300 883 | #define GPIO_PUPD_MASK 0x00003000 884 | 885 | //General purpose output options 886 | //Push pull 887 | #define GPIO_OUTPUT_PP_LOW_SPEED 0x00000001 888 | #define GPIO_OUTPUT_PP_MEDIUM_SPEED 0x00000101 889 | #define GPIO_OUTPUT_PP_HIGH_SPEED 0x00000301 890 | 891 | //Push pull with pull up 892 | #define GPIO_OUTPUT_PP_PU_LOW_SPEED 0x00001001 893 | #define GPIO_OUTPUT_PP_PU_MEDIUM_SPEED 0x00001101 894 | #define GPIO_OUTPUT_PP_PU_HIGH_SPEED 0x00001301 895 | 896 | //Push pull with pull down 897 | #define GPIO_OUTPUT_PP_PD_LOW_SPEED 0x00002001 898 | #define GPIO_OUTPUT_PP_PD_MEDIUM_SPEED 0x00002101 899 | #define GPIO_OUTPUT_PP_PD_HIGH_SPEED 0x00002301 900 | 901 | //Open drain 902 | #define GPIO_OUTPUT_OD_LOW_SPEED 0x00000011 903 | #define GPIO_OUTPUT_OD_MEDIUM_SPEED 0x00000111 904 | #define GPIO_OUTPUT_OD_HIGH_SPEED 0x00000311 905 | 906 | //Open drain with pull up 907 | #define GPIO_OUTPUT_OD_PU_LOW_SPEED 0x00001011 908 | #define GPIO_OUTPUT_OD_PU_MEDIUM_SPEED 0x00001111 909 | #define GPIO_OUTPUT_OD_PU_HIGH_SPEED 0x00001311 910 | 911 | //Open drain with pull down 912 | #define GPIO_OUTPUT_OD_PD_LOW_SPEED 0x00002011 913 | #define GPIO_OUTPUT_OD_PD_MEDIUM_SPEED 0x00002111 914 | #define GPIO_OUTPUT_OD_PD_HIGH_SPEED 0x00002311 915 | 916 | //Alternate function options 917 | //Push pull 918 | #define GPIO_AF_PP_LOW_SPEED 0x00000002 919 | #define GPIO_AF_PP_MEDIUM_SPEED 0x00000102 920 | #define GPIO_AF_PP_HIGH_SPEED 0x00000302 921 | 922 | //Push pull with pull up 923 | #define GPIO_AF_PP_PU_LOW_SPEED 0x00001002 924 | #define GPIO_AF_PP_PU_MEDIUM_SPEED 0x00001102 925 | #define GPIO_AF_PP_PU_HIGH_SPEED 0x00001302 926 | 927 | //Push pull with pull down 928 | #define GPIO_AF_PP_PD_LOW_SPEED 0x00002002 929 | #define GPIO_AF_PP_PD_MEDIUM_SPEED 0x00002102 930 | #define GPIO_AF_PP_PD_HIGH_SPEED 0x00002302 931 | 932 | //Open drain 933 | #define GPIO_AF_OD_LOW_SPEED 0x00000012 934 | #define GPIO_AF_OD_MEDIUM_SPEED 0x00000112 935 | #define GPIO_AF_OD_HIGH_SPEED 0x00000312 936 | 937 | //Open drain with pull up 938 | #define GPIO_AF_OD_PU_LOW_SPEED 0x00001012 939 | #define GPIO_AF_OD_PU_MEDIUM_SPEED 0x00001112 940 | #define GPIO_AF_OD_PU_HIGH_SPEED 0x00001312 941 | 942 | //Open drain with pull down 943 | #define GPIO_AF_OD_PD_LOW_SPEED 0x00002012 944 | #define GPIO_AF_OD_PD_MEDIUM_SPEED 0x00002112 945 | #define GPIO_AF_OD_PD_HIGH_SPEED 0x00002312 946 | 947 | //General purpose input options 948 | #define GPIO_INPUT_FLOAT 0x00000000 949 | #define GPIO_INPUT_PULLUP 0x00001000 950 | #define GPIO_INPUT_PULLDOWN 0x00002000 951 | 952 | //Analog option 953 | #define GPIO_ANALOG 0x00000003 954 | 955 | 956 | #endif 957 | 958 | 959 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/stm32f3_sine_square_gen.c: -------------------------------------------------------------------------------- 1 | //Run openocd for debugging 2 | //openocd -f ~/NetBeansProjects/STM32/F303/STM_Sine_Square_Gen/STM32F303CBT6.cfg 3 | //openocd -f ~/Data/NetbeansProjects/STM32/F303/STM32F3_Sine_Square_Gen/STM32F303CBT6.cfg 4 | 5 | #include "stm32f303_db.h" 6 | #include "usb.h" 7 | #include "sintab.h" 8 | 9 | //STM3F303 has: 10 | // a different clock configuration and other AHB and ABP bus setup 11 | // enabling of peripherals is done in the same way, but differ in what is connected to which bus 12 | // a different GPIO setup 13 | // a different way of moving alternate functions for the pins. AFIO is SYSCFG and is used to remap functions not pins 14 | // the ADC's are different in configuration and usage 15 | // the xB device has 32KB of standard RAM and 8KB of core coupled memory 16 | // the xC device has 40KB of standard RAM and 8KB of core coupled memory 17 | 18 | //The top of stack is set to the address right after the end of the internal RAM 19 | //For the xB version this is at 0x20007D00 (32KB) 20 | //For the xC version this is at 0x20009C40 (40KB) 21 | #define STACK_TOP 0x20007D00 22 | 23 | //Simple embedded systems can do without a separate heap. 24 | //This means not using standard libraries 25 | //Memory is statically declared and used. 26 | //To allow for a proper working leave memory for the stack to grow so do not use more then RAM size - 1024 bytes 27 | 28 | //Programming the STM32 in C starting from the reset vector needs the following steps in given order 29 | // 1) Setup the interrupt and exception vector table 30 | // 2) Configure C variables (resetHandler) 31 | // 3) Configure the clock system and enable the needed peripheral clocks 32 | // 4) Configure the input / output pins 33 | // 5) Configure the peripherals 34 | // 6) Enable the interrupts 35 | // 7) Loop through the main code 36 | 37 | extern unsigned char INIT_DATA_VALUES; 38 | extern unsigned char INIT_DATA_START; 39 | extern unsigned char INIT_DATA_END; 40 | extern unsigned char BSS_START; 41 | extern unsigned char BSS_END; 42 | 43 | int main(void); 44 | void resetHandler(void); 45 | void tim2IrqHandler(void); 46 | void tim3IrqHandler(void); 47 | 48 | //Vector table is setup in flash at the ".vectors" location, which is defined in the linker script file stm32f303-128k.ld 49 | //See ST manual PM0214 chapter 2.3.4 50 | const void * intVectors[76] __attribute__((section(".vectors"))) = 51 | { 52 | (void*) STACK_TOP, 53 | resetHandler, 54 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0, 55 | 0,0,0,0,0,0,0,0,0,0, 56 | 0,0,0,0,0,0,0,0,0,0, 57 | usbIrqHandler, 58 | 0,0,0,0, 59 | 0, //tim1IrqHandler, 60 | 0,0, 61 | tim2IrqHandler, 62 | tim3IrqHandler, 63 | 0,0,0,0,0,0,0,0,0 64 | }; 65 | 66 | //On reset this handler is called to setup the initial memory state 67 | void resetHandler(void) 68 | { 69 | unsigned char volatile *src; 70 | unsigned char volatile *dst; 71 | unsigned len; 72 | 73 | //Setup pointers and counter for copying initial values from flash to normal memory 74 | //This concerns all variables that are declared globally with an initial value 75 | src= &INIT_DATA_VALUES; 76 | dst= &INIT_DATA_START; 77 | len= &INIT_DATA_END - &INIT_DATA_START; 78 | 79 | while(len--) 80 | *dst++ = *src++; 81 | 82 | //Setup pointer and counter for erasing all the other variables 83 | dst = &BSS_START; 84 | len = &BSS_END - &BSS_START; 85 | 86 | while(len--) 87 | *dst++=0; 88 | 89 | //Go and start the main process 90 | main(); 91 | } 92 | 93 | //The number of microseconds must be less then 1864135. (just over 1.8 second) 94 | //Multiplied by 9 gives the number of ticks. 95 | //With this it can only lead to a single timer overflow, which this function can handle 96 | void usdelay(int32_t usec) 97 | { 98 | int32_t end = STK->VAL - (usec * 9); 99 | 100 | //Check if there is the need to wait for an timer overflow 101 | if(end <= 0) 102 | { 103 | //Wait for the overflow to occur 104 | while((STK->CTRL & STK_CTRL_OVERFLOW) == 0); 105 | 106 | //calculate the new end value 107 | end += 0x00FFFFFF; 108 | } 109 | 110 | //Wait till the timer reaches the intended value for the given delay 111 | while(STK->VAL >= end); 112 | } 113 | 114 | //Simple function for setup of an IO pin 115 | void InitIOPin(GPIO_TypeDef *port, uint32_t pin, uint32_t setting, uint32_t alternatefunction) 116 | { 117 | //Each pin uses two bits in the mode register for four modes (MODER) 118 | // 00 input 119 | // 01 general purpose output 120 | // 10 alternate function 121 | // 11 analog 122 | 123 | //For an output there are two types (OTYPER) 124 | // 0 Pull up / down 125 | // 1 Open drain 126 | 127 | //There are three output speed settings (OSPEEDR) 128 | // x0 Low speed 129 | // 01 Medium speed 130 | // 11 High speed 131 | 132 | //There are three pull up and pull down possibilities (PUPDR) 133 | // 00 No pull up or pull down 134 | // 01 Pull up 135 | // 10 Pull down 136 | 137 | //Create a base pointer for either the lower or the higher alternate function register 138 | __IO uint32_t *reg; 139 | 140 | //2 bit settings need to be shifted twice the distance 141 | uint32_t shifter = pin * 2; 142 | 143 | //Set the requested configuration 144 | port->MODER |= (setting & GPIO_MODE_MASK) << shifter; 145 | port->OTYPER |= ((setting & GPIO_TYPE_MASK) >> 4) << pin; 146 | port->OSPEEDR |= ((setting & GPIO_SPEED_MASK) >> 8) << shifter; 147 | port->PUPDR |= ((setting & GPIO_PUPD_MASK) >> 12) << shifter; 148 | 149 | //See if the lower alternate function register or the higher alternate function register needs to be used 150 | if(pin < 8) 151 | { 152 | //Low control register used for first 8 pins 153 | reg = &port->AFR[0]; 154 | } 155 | else 156 | { 157 | //Force pin into 8 pins per register range 158 | pin -= 8; 159 | 160 | //High control register used for upper 8 pins 161 | reg = &port->AFR[1]; 162 | } 163 | 164 | //4 control bits used per pin 165 | pin *= 4; 166 | 167 | //Reset bits first and set new mode and configuration. 168 | *reg &= ~(0x0F << pin); 169 | *reg |= ((alternatefunction & 0x0F) << pin); 170 | } 171 | 172 | void writedisplay(uint8_t data, uint8_t type) 173 | { 174 | //Based on type set the RS line (low for commands, high for data) 175 | if(type == 0) 176 | GPIOC->ODR &= ~(1 << 14); 177 | else 178 | GPIOC->ODR |= 1 << 14; 179 | 180 | //Put upper four bits on data bus and allow for some data setup time 181 | GPIOA->ODR &= 0xFFF0; 182 | GPIOA->ODR |= data >> 4; 183 | usdelay(2); 184 | 185 | //pulse display enable high for at least a microsecond 186 | GPIOC->ODR |= 1 << 15; 187 | usdelay(2); 188 | GPIOC->ODR &= ~(1 << 15); 189 | usdelay(20); 190 | 191 | //Put lower four bits on data bus and allow for some data setup time 192 | GPIOA->ODR &= 0xFFF0; 193 | GPIOA->ODR |= data & 0x0F; 194 | usdelay(2); 195 | 196 | //pulse display enable high for at least a microsecond 197 | GPIOC->ODR |= 1 << 15; 198 | usdelay(2); 199 | GPIOC->ODR &= ~(1 << 15); 200 | 201 | //Wait for data to be processed (>37us) 202 | usdelay(100); 203 | } 204 | 205 | void initdisplay(void) 206 | { 207 | //Make sure enable is low to start with 208 | GPIOC->ODR &= ~(1 << 15); 209 | 210 | //Wait at least 50ms after reset 211 | usdelay(50000); 212 | 213 | //Reset display by setting it to 8 bit mode three times in a row with long delays in between 214 | GPIOA->ODR &= 0xFFF0; 215 | GPIOA->ODR |= 3; 216 | usdelay(2); 217 | 218 | //pulse display enable high for at least a microsecond and wait 4.5ms 219 | GPIOC->ODR |= 1 << 15; 220 | usdelay(2); 221 | GPIOC->ODR &= ~(1 << 15); 222 | usdelay(4500); 223 | 224 | //pulse display enable high again for at least a microsecond and wait 4.5ms 225 | GPIOC->ODR |= 1 << 15; 226 | usdelay(2); 227 | GPIOC->ODR &= ~(1 << 15); 228 | usdelay(4500); 229 | 230 | //pulse display enable high for third and last time for at least a microsecond and wait 150us 231 | GPIOC->ODR |= 1 << 15; 232 | usdelay(2); 233 | GPIOC->ODR &= ~(1 << 15); 234 | usdelay(150); 235 | 236 | //Set display in 4 bits mode by resetting D4 and allow for some data setup time 237 | GPIOA->ODR &= 0xFFFE; 238 | usdelay(2); 239 | 240 | //pulse display enable high for at least a microsecond and wait 100us 241 | GPIOC->ODR |= 1 << 15; 242 | usdelay(2); 243 | GPIOC->ODR &= ~(1 << 15); 244 | usdelay(100); 245 | 246 | //Keep display in 4 bits mode and specify 2 lines with 5x8 font 247 | writedisplay(0x28, 0); 248 | 249 | //Turn display on without blinking cursor 250 | writedisplay(0x0C, 0); 251 | 252 | //Clear the display 253 | writedisplay(0x01, 0); 254 | 255 | //Wait till cleared 256 | usdelay(2000); 257 | 258 | //Set entry mode to no shift and increment address 259 | writedisplay(0x06, 0); 260 | 261 | //Wait till entry mode is set 262 | //Some displays need a long time 263 | usdelay(20000); 264 | } 265 | 266 | void displaystring(char *string, uint8_t position) 267 | { 268 | uint8_t pos; 269 | 270 | while(*string) 271 | { 272 | //Translate input position to display position 273 | pos = position++; 274 | 275 | if((pos >= 20) && (pos < 40)) 276 | pos += 44; 277 | else if((pos >= 40) && (pos < 60)) 278 | pos -= 20; 279 | else if((pos >= 60) && (pos < 80)) 280 | pos += 24; 281 | 282 | writedisplay(0x80 + pos,0); //Output position command 283 | writedisplay(*string++,1); //Write the actual character 284 | } 285 | } 286 | 287 | void displayint(int32_t value, uint8_t position) 288 | { 289 | //Decimal 290 | //Hexadecimal 291 | //Left justify 292 | //Right justify (default) 293 | //Left pad with 0 294 | //left pad with spaces 295 | char b[12] = { ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', '\0'}; 296 | uint32_t u = value; 297 | uint8_t n = 0; 298 | uint8_t i = 11; 299 | 300 | if(value == 0) 301 | { 302 | //Put a 0 in the for last index 303 | b[--i] = '0'; 304 | } 305 | else 306 | { 307 | //Check if negative value 308 | if(value < 0) 309 | { 310 | //Negate if so and signal negative sign needed 311 | u = -value; 312 | n = 1; 313 | } 314 | 315 | //Process the digits 316 | while(u) 317 | { 318 | //Add current digit to decreased index 319 | b[--i] = (u % 10) + '0'; 320 | 321 | //Take of the current digit 322 | u /= 10; 323 | } 324 | } 325 | 326 | //Check if negative number and if so put a minus in front of it 327 | if(n == 1) 328 | b[--i] = '-'; 329 | 330 | //Display the string from the current index 331 | displaystring(&b[i], position); 332 | } 333 | 334 | void displaydegree(int32_t value, uint8_t position) 335 | { 336 | char b[12] = { ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', '0', '.', '0', '\0'}; 337 | uint32_t u = value / 2; 338 | uint8_t i = 9; 339 | 340 | if(u == 0) 341 | { 342 | b[--i] = '0'; 343 | } 344 | else 345 | { 346 | while(u) 347 | { 348 | b[--i] = (u % 10) + '0'; 349 | 350 | u /= 10; 351 | } 352 | } 353 | 354 | //Check if half a degree 355 | if(value & 1) 356 | b[10] = '5'; 357 | 358 | displaystring(&b[i], position); 359 | } 360 | 361 | //Table for decoding states of a rotary encoder 362 | const int8_t encoderstates[] = { 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 1, 0, 0, 0, 0 }; 363 | 364 | //Table for square wave states 365 | //Write to BSRR register. A 1 sets or resets a pin based on upper (reset) or lower (set) 16 bits. 366 | //Output on pin B6, B7, B8, B9 367 | //Initial state needs to be B6 low, B7 high, B8 low, B9 high (0000 0010 1000 0000) 0x0280 368 | //0000 0010 0100 0000 => 0000 0000 1000 0000 0000 0000 0100 0000 369 | //0000 0001 0100 0000 => 0000 0010 0000 0000 0000 0001 0000 0000 370 | //0000 0001 1000 0000 => 0000 0000 0100 0000 0000 0000 1000 0000 371 | //0000 0010 1000 0000 => 0000 0001 0000 0000 0000 0010 0000 0000 372 | //const int16_t squarewavestates[] = {0x0240, 0x0140, 0x0180, 0x0280}; 373 | const int32_t squarewavestates[] = {0x00800040, 0x02000100, 0x00400080, 0x01000200}; 374 | 375 | //Variables now global for reading in interrupt routine 376 | volatile int16_t phase = 0; 377 | volatile int16_t prevphase = 0; 378 | volatile int16_t phasediff; 379 | volatile int16_t sinephase; 380 | volatile int16_t squarephase; 381 | volatile int16_t currentphase; 382 | volatile int16_t timcnt; 383 | 384 | //Main program part 385 | int main(void) 386 | { 387 | //Setup flash to work with 72MHz clock 388 | //Enable the Prefetch Buffer and Set to 2 wait states 389 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2; 390 | 391 | //Configure system clock 392 | //External oscillator: 8MHz 393 | //PLL multiplier: x9 394 | //SYSCLK: 72MHz 395 | //AHB: SYSCLK = 72MHz 396 | //APB1: SYSCLK/2 = 36MHz //Timer 2,3 and 4 run on 72MHz since APB1 divider is not 1 397 | //APB2: SYSCLK/2 = 36MHz //Timer 1 also runs on 72MHz since APB2 divider is not 1 398 | //ADC: SYSCLK/6 = 12MHz 399 | //USB: SYSCLK/1.5 = 48MHz 400 | RCC->CFGR = RCC_CFGR_PLLMULL9 | RCC_CFGR_PLLSRC | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2; 401 | 402 | //Enable external oscillator 403 | RCC->CR |= RCC_CR_HSEON; 404 | 405 | //Wait for the clock to become stable 406 | while((RCC->CR & RCC_CR_HSERDY) != RCC_CR_HSERDY); 407 | 408 | //Enable the PLL 409 | RCC->CR |= RCC_CR_PLLON; 410 | 411 | //Wait for the PLL to become stable 412 | while((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY); 413 | 414 | //Switch to the PLL clock as system clock source. Since on reset these bits are set to 0 no need to clear first. 415 | RCC->CFGR |= RCC_CFGR_SW_PLL; 416 | 417 | //Wait for the PLL to become the clock source 418 | while((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL); 419 | 420 | //From this point on it is not possible to change the clock configuration without switching back to HSI 421 | 422 | //Enable the used peripherals. PORTA, PORTB, PORTC and DMA1 423 | RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_DMA1EN; //RCC_AHBENR_ADC12EN | | RCC_AHBENR_DMA2EN 424 | 425 | //Enable TIM1 426 | RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; 427 | 428 | //Enable TIM2, TIM3 and DAC1 429 | RCC->APB1ENR |= RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN | RCC_APB1ENR_DAC1EN; 430 | 431 | //Enable the system timer for delay function 432 | //In default setting with 72MHz AHB clock this timer runs on 9MHz, so 111ns per tick. Takes 9 ticks for a microsecond 433 | STK->LOAD = 0x00FFFFFF; 434 | STK->CTRL = STK_CTRL_ENABLE; 435 | 436 | //Decide which clock is best to be used for the ADC 437 | //There are two possibilities. AHB clock divided by 1,2 of 4 to be synchronous with the AHB clock 438 | //or the pll clock divided by a prescaler. With this clock the conversions can be asynchronous to timer triggers and lead to jitter. 439 | 440 | //PA2 is ADC1_IN3 (PA3 is ADC1_IN4 and negative input for IN3 in differential mode) 441 | //PA6 is ADC2_IN3 (PA7 is ADC2_IN4 and negative input for IN3 in differential mode) 442 | 443 | //Before using the ADC it is needed to turn on the internal voltage regulator 444 | //It is also needed to calibrate the ADC. When both single ended and differential inputs are used one needs 445 | //to do separate calibrations for each type. Otherwise only the one for the type in use needs to be done 446 | //Only after these steps the ADC can be enabled 447 | //After enabling the ADC a wait until ADCRDY is set needs to be done before converting any channels 448 | 449 | //For simultaneous getting the voltage and the current it is possible to use the master slave mode of two connected ADC's 450 | //Select the regular simultaneous mode 451 | 452 | //To reduce noise the ADC clock can be lowered to sysclk/4 when synchronous mode is used. 453 | //With a sample time of 7.5 clock cycles the conversion is done in 20 clock cycles. This leads to a max rate 454 | //of 900KHz when the sysclk is 72MHz 455 | 456 | //ADC1 uses DMA1 channel1 457 | //ADC2 uses DMA2 either channel1 or channel3 (only when remapped) 458 | 459 | //On the blue pill the VDDA pin is connected to VDD, so DAC output can be routed back into the ADC. 460 | 461 | //Init the USB device 462 | usbInit(); 463 | 464 | //IO pins need to be configured first 465 | //Pin with LED to show activity 466 | InitIOPin(GPIOC, 13, GPIO_OUTPUT_PP_LOW_SPEED, 0); 467 | 468 | //Time measurement pin irq tim 3 469 | InitIOPin(GPIOA, 6, GPIO_OUTPUT_PP_MEDIUM_SPEED, 0); 470 | 471 | //SPI Display connections 472 | //InitIOPin(GPIOA, 2, GPIO_OUTPUT_PP_MEDIUM_SPEED, 0); //Reset (RES) (RESET) 473 | //InitIOPin(GPIOA, 3, GPIO_OUTPUT_PP_MEDIUM_SPEED, 0); //Register select (RS) (A0) (DS/RS) 474 | //InitIOPin(GPIOA, 15, GPIO_AF_PP_HIGH_SPEED, 5); //Chip select SPI/NSS (CS) 475 | //InitIOPin(GPIOB, 3, GPIO_AF_PP_HIGH_SPEED, 6); //Clock SPI/SCK (SCK) (SCL) 476 | //InitIOPin(GPIOB, 5, GPIO_AF_PP_HIGH_SPEED, 6); //Data SPI/MOSI (SDA) (SDI) 477 | 478 | //LCD 1602 display connection 479 | //PC14 for RS, PC15 for E, PA0 - PA3 for databus 480 | InitIOPin(GPIOA, 0, GPIO_OUTPUT_PP_LOW_SPEED, 0); 481 | InitIOPin(GPIOA, 1, GPIO_OUTPUT_PP_LOW_SPEED, 0); 482 | InitIOPin(GPIOA, 2, GPIO_OUTPUT_PP_LOW_SPEED, 0); 483 | InitIOPin(GPIOA, 3, GPIO_OUTPUT_PP_LOW_SPEED, 0); 484 | InitIOPin(GPIOC, 14, GPIO_OUTPUT_PP_LOW_SPEED, 0); 485 | InitIOPin(GPIOC, 15, GPIO_OUTPUT_PP_LOW_SPEED, 0); 486 | 487 | //Rotary encoder pins. External pullups are used. Debouncing filter might be needed 488 | InitIOPin(GPIOB, 0, GPIO_INPUT_FLOAT, 0); 489 | InitIOPin(GPIOB, 1, GPIO_INPUT_FLOAT, 0); 490 | 491 | //USB pins need to be set for correct alternate function 492 | InitIOPin(GPIOA, 11, GPIO_AF_PP_HIGH_SPEED, 14); 493 | InitIOPin(GPIOA, 12, GPIO_AF_PP_HIGH_SPEED, 14); 494 | 495 | //Square wave output pins 496 | InitIOPin(GPIOB, 6, GPIO_OUTPUT_PP_LOW_SPEED, 0); //90 degree 497 | InitIOPin(GPIOB, 7, GPIO_OUTPUT_PP_LOW_SPEED, 0); //270 degree 498 | InitIOPin(GPIOB, 8, GPIO_OUTPUT_PP_LOW_SPEED, 0); //180 degree 499 | InitIOPin(GPIOB, 9, GPIO_OUTPUT_PP_LOW_SPEED, 0); //0 degree 500 | 501 | //DAC pin need to be set for analog 502 | InitIOPin(GPIOA, 4, GPIO_ANALOG, 0); 503 | 504 | //ADC input pins need to be set for analog 505 | // InitIOPin(GPIOA, 2, GPIO_ANALOG, 0); //ADC1_IN3 506 | // InitIOPin(GPIOA, 6, GPIO_ANALOG, 0); //ADC2_IN3 507 | 508 | //Set initial state on square wave pins 509 | GPIOB->ODR |= 0x0280; 510 | 511 | //Setup the DMA channel for timer 1 overflow to write data into the dac 512 | DMA1_Channel5->CPAR = (uint32_t)&DAC1->DHR12R1; 513 | DMA1_Channel5->CMAR = (uint32_t)dmasinetable_1900; 514 | DMA1_Channel5->CNDTR = STEPS_360_DEGREES; 515 | DMA1_Channel5->CCR = DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_EN; 516 | 517 | //Setup the DMA channel for timer 3 overflow to write data to port b 518 | DMA1_Channel3->CPAR = (uint32_t)&GPIOB->BSRR; 519 | DMA1_Channel3->CMAR = (uint32_t)squarewavestates; 520 | DMA1_Channel3->CNDTR = 4; 521 | DMA1_Channel3->CCR = DMA_CCR_MSIZE_1 | DMA_CCR_PSIZE_1 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_EN; 522 | 523 | //Setup the dac. Only first channel for now 524 | //Output buffer is enabled, no wave generation. Data is automatically transferred to the output. 525 | //Since DMA is used based on a timer overflow the DAC will not be triggered by an event. 526 | DAC1->CR = DAC_CR_EN1 | DAC_CR_BOFF1; 527 | 528 | //Initialize on half voltage 529 | DAC1->DHR12R1 = 2048; 530 | 531 | //Output the value 532 | DAC1->SWTRIGR = 1; 533 | 534 | //Timer 1 is used to trigger the dma that outputs the sine data to the dac. It runs at a frequency of 720KHz 535 | TIM1->CNT = 0; //No initial count 536 | TIM1->PSC = 0; //No prescaler 537 | TIM1->ARR = 99; //Divide master clock by 100. Counts from 0 to 99, which is 100 ticks. 538 | 539 | //Timer 1 up counting. Preload and dma on update enabled. 540 | TIM1->DIER = TIM_DIER_UDE; 541 | TIM1->CR2 = TIM_CR2_MMS_1; 542 | 543 | //Timer 2 is used for blinking the led on PC13 544 | TIM2->CNT = 0; 545 | TIM2->PSC = 15999; //72MHz / 16000 = 4500Hz 546 | TIM2->ARR = 1124; //4500Hz / 1125 = 4Hz; 547 | 548 | //Timer 2 generates an interrupt at a 4Hz rate. 549 | TIM2->DIER = TIM_DIER_UIE; 550 | TIM2->CR1 = TIM_CR1_CEN; 551 | 552 | //Timer 3 generates the 4KHz clock to trigger the dma for the creation of the 4 square wave signals 553 | TIM3->CNT = 0; //Initial phase on 0 degrees 554 | TIM3->PSC = 0; //No prescaler 555 | TIM3->ARR = MAX_COUNT_90_DEGREES; //720KHz / 180 = 4KHz; 556 | TIM3->CCR1 = HALF_COUNT_90_DEGREES; //For compare interrupt halfway the timer count 557 | 558 | //Enable the DMA trigger 559 | TIM3->DIER = TIM_DIER_UDE; 560 | TIM3->SMCR = TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; //Clock source for timer 3 is timer 1 (TS = 000) 561 | 562 | //Start the timers used for sine and square wave generation 563 | TIM1->CR1 = TIM_CR1_CEN; 564 | TIM3->CR1 = TIM_CR1_CEN; 565 | 566 | 567 | //ADC is for future features 568 | /* 569 | 570 | //Setup ADC 1 and 2 for converting simultaneous on inputs PA2 and PA6 571 | //Put converters in intermediate state before turning on the voltage regulator 572 | ADC1->CR = ADC_CR_ADVREG_INTERMEDIATE; 573 | ADC2->CR = ADC_CR_ADVREG_INTERMEDIATE; 574 | 575 | //Wait for 10us to make sure things are settled 576 | usdelay(10); 577 | 578 | //Turn on the voltage regulators 579 | ADC1->CR = ADC_CR_ADVREG_ON; 580 | ADC2->CR = ADC_CR_ADVREG_ON; 581 | 582 | //Wait for 20us to make sure things are settled 583 | usdelay(20); 584 | 585 | //Start calibration for single ended conversions 586 | ADC1->CR |= ADC_CR_ADCAL; 587 | ADC2->CR |= ADC_CR_ADCAL; 588 | 589 | //Wait till calibration of both converters is done 590 | while((ADC1->CR & ADC_CR_ADCAL) || (ADC2->CR & ADC_CR_ADCAL)); 591 | 592 | //Setup the channels to be converted. Only a single channel per ADC 593 | //Channel 0 is not mapped so range is from 1 to 18. 594 | //Sequence count is 1 on reset 595 | ADC1->SQR1 = 3 << ADC_SQR1_SQ1_POS; 596 | ADC2->SQR1 = 3 << ADC_SQR1_SQ1_POS; 597 | 598 | //Setup the sample time for the channels in use. 7,5 adc clock cycles is used 599 | ADC1->SMPR1 = ADC_SAMPLE_TIME_7 << ADC_SMPR1_CH3_POS; 600 | ADC2->SMPR1 = ADC_SAMPLE_TIME_7 << ADC_SMPR1_CH3_POS; 601 | 602 | //Setup dual mode for simultaneous conversions 603 | //Clock is synchronous HCLK divided by 4, DMA in 12bit mode 604 | ADC12_COMMON->CCR = ADC_CCR_CKMODE_HCLK_4 | ADC_CCR_MDMA_10_12_BIT | ADC_CCR_DMACFG_CIRCULAIR | ADC_CCR_MULTI_RS; 605 | 606 | //Setup DMA for the ADC's 607 | 608 | //Enable both converters 609 | ADC1->CR |= ADC_CR_ADEN; 610 | ADC2->CR |= ADC_CR_ADEN; 611 | 612 | //Wait till both converters are ready 613 | while((ADC1->ISR & ADC_ISR_ADRDY) || (ADC2->CR & ADC_ISR_ADRDY)); 614 | 615 | */ 616 | 617 | //Set priority for timer 1, 2 interrupt to be higher then the other interrupts 618 | //This is an array of 8 bit registers, of which only the upper 4 bits are used for the priority allowing for 16 levels 619 | //By grouping this is separated to allow for having sub priorities within a single group. 620 | //In the usb init this is set for 4 group priorities with each 4 sub priorities. 621 | //The higher the number the lower the priority 622 | //NVIC->IP[TIM1_UP_IRQn] = 0x80; //(1000b) Group priority 2, sub priority 0 623 | NVIC->IP[TIM2_IRQn] = 0x90; //(1001b) Group priority 2, sub priority 1 624 | NVIC->IP[TIM3_IRQn] = 0x80; //(1000b) Group priority 2, sub priority 0 625 | 626 | //Enable the timer 1 and 2 interrupt 627 | //This is an array of 32 bit registers, only used to enable an interrupt. To disable the ICER registers need to be used 628 | //Each register serves 32 interrupts, so to get the register for the interrupt, shift the IRQ number right 5 times (divide by 32) and to get 629 | //the right interrupt enable bit, shift a unsigned 32 bit integer 1 the IRQ number anded with 31 (modulo 32) times to the right 630 | //NVIC->ISER[TIM1_UP_IRQn >> 0x05] = (uint32_t)0x01 << (TIM1_UP_IRQn & 0x1F); 631 | NVIC->ISER[TIM2_IRQn >> 0x05] = (uint32_t)0x01 << (TIM2_IRQn & 0x1F); 632 | NVIC->ISER[TIM3_IRQn >> 0x05] = (uint32_t)0x01 << (TIM3_IRQn & 0x1F); 633 | 634 | 635 | //Initialize the attached display 636 | initdisplay(); 637 | 638 | //Show the initial phase shift 639 | displaystring("FASE: 0.0 GRD", 0); 640 | 641 | //Variable for rotary encoder handling 642 | uint8_t h = 0; 643 | 644 | while(1) 645 | { 646 | //Get character from USB receive buffer 647 | int16_t c = usbRead(); 648 | 649 | //Echo it when valid character 650 | if(c != -1) 651 | usbSend(c); 652 | 653 | //Rotary encoder part 654 | //Hardware debouncing door 10Komh pullup en 10Kohm serie weerstand en 10nf condensator naar ground. 655 | 656 | //2ms delay 657 | usdelay(2000); 658 | 659 | //Read the encoder pins 660 | h <<= 2; 661 | h |= (GPIOB->IDR & 0x03); 662 | 663 | //Modify the count accordingly 664 | phase += encoderstates[h & 0x0F]; 665 | 666 | if(phase < 0) //Check on underrun and fall back to maximum 667 | phase = MAX_PHASE; 668 | else if(phase > MAX_PHASE) //Check on overrun and fall back to minimum 669 | phase = 0; 670 | 671 | //Check if a change in phase 672 | if(phase != prevphase) 673 | { 674 | //Update previous phase for filtering 675 | prevphase = phase; 676 | 677 | //Display the new phase 678 | displaystring("FASE: GRD", 0); 679 | displaydegree(phase, 6); 680 | 681 | //Clear any pending interrupts to make sure the event takes place on the actual moment 682 | TIM3->SR = 0; 683 | 684 | //And enable the compare interrupt to make the adjustment 685 | TIM3->DIER |= TIM_DIER_CC1IE; 686 | } 687 | } 688 | } 689 | 690 | //Handler for timer 2 interrupt. Only used to blink the led on the board 691 | void tim2IrqHandler(void) 692 | { 693 | //Clear the interrupt flags 694 | TIM2->SR = 0; 695 | 696 | //Toggle the led output pin 697 | GPIOC->ODR ^= (1 << 13); 698 | } 699 | 700 | //Handler for timer 3 interrupt. Used to shift the phase within certain limits 701 | void tim3IrqHandler(void) 702 | { 703 | //Set pin for time measurement PA6 704 | GPIOA->ODR |= 0x0040; 705 | 706 | //Make sure it is the compare interrupt in use 707 | if(TIM3->SR & TIM_SR_CC1IF) 708 | { 709 | //Determine the current phase difference 710 | sinephase = STEPS_360_DEGREES - DMA1_Channel5->CNDTR; //dma counter counts down, so subtraction from max is needed 711 | squarephase = ((4 - DMA1_Channel3->CNDTR) * 180) + TIM3->CNT; //Each square wave dma step indicates 180 half degrees 712 | currentphase = sinephase - squarephase; 713 | 714 | //Phase needs to be positive 715 | if(currentphase < 0) 716 | currentphase += STEPS_360_DEGREES; 717 | 718 | //Calculate the needed phase difference 719 | phasediff = currentphase - phase; 720 | 721 | //Check if timer needs to be updated 722 | if(phasediff) 723 | { 724 | //Check if difference out of quarter count range and limit if so 725 | if(phasediff > QUARTER_COUNT_90_DEGREES) 726 | phasediff = QUARTER_COUNT_90_DEGREES; 727 | else if(phasediff < -QUARTER_COUNT_90_DEGREES) 728 | phasediff = -QUARTER_COUNT_90_DEGREES; 729 | else 730 | TIM3->DIER &= ~TIM_DIER_CC1IE; //Within the limits then one correction is enough so disable the interrupt 731 | 732 | //Adjust timer 3 count for the new phase 733 | TIM3->CNT += phasediff; 734 | } 735 | else 736 | TIM3->DIER &= ~TIM_DIER_CC1IE; //No correction needed so disable the interrupt 737 | } 738 | 739 | //Clear the interrupt flags 740 | TIM3->SR = 0; 741 | 742 | //Clear pin for time measurement PA6 743 | GPIOA->ODR &= 0xFFBF; 744 | } 745 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/stm32f3xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pecostm32/STM32F303_Sine_Square_Generator/f1a17ef6844389ab1cfd1d9db1db52c8ac7bc0e8/STM32F3_Sine_Square_Gen/stm32f3xx.h -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/usb.c: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // Simple USB implementation for STM32F103C8T6 Bluepill board 3 | // Based on CH340 USB to serial converter and derived from STM virtual com port 4 | // but uses way less code. Lacks error and suspend handling. 5 | // 6 | // To use the USB device the system clock needs to be either 48MHz or 72MHz 7 | // Select the right SUB clock divide setting to have a 48MHz USB clock 8 | // RCC->CFGR USB_PRE bit 9 | // 0 for 72MHz system clock 10 | // 1 for 48MHZ system clock 11 | //------------------------------------------------------------------------------ 12 | 13 | #include "stm32f303_db.h" 14 | #include "usb.h" 15 | 16 | //Global memory assignment for USB device 17 | uint8_t usb_rx[64]; //Buffer for USB receive data 18 | uint8_t volatile usb_rx_in_idx = 0; //Index for putting data into the USB receive buffer 19 | uint8_t volatile usb_rx_out_idx = 0; //Index for taking data from the USB receive buffer. Set volatile since it changes in interrupt routine. 20 | 21 | uint8_t usb_tx[64]; //Buffer for USB transmit data 22 | uint8_t volatile usb_tx_in_idx = 0; //Index for putting data into the USB transmit buffer 23 | uint8_t volatile usb_tx_out_idx = 0; //Index for taking data from the USB transmit buffer. Set volatile since it changes in interrupt routine. 24 | 25 | volatile uint16_t *EP0TxPtr; //Endpoint 0 transmit pointer. Data needs to be send in 8 byte blocks. This pointer keeps track of where to get the data from 26 | volatile uint8_t EP0TxLen; //Endpoint 0 transmit length. This length counter keeps track of how many bytes still need to be send. 27 | volatile uint8_t DeviceAddress = 0; //Flag to signal host has send a "set address" command, which needs to be set after confirmation transmission. 28 | volatile uint8_t DeviceConfigured = 0; //Flag to signal device is up and running. 29 | volatile uint8_t EP2DisableTX = 0; //Flag to disable the endpoint 2 transmission function. 30 | 31 | //USB Standard Device Descriptor 32 | const uint8_t DeviceDescriptor[] = 33 | { 34 | 0x12, // bLength 35 | 0x01, // bDescriptorType 36 | 0x10, 37 | 0x01, // bcdUSB = 1.1 38 | 0xFF, // bDeviceClass: Vendor 39 | 0x00, // bDeviceSubClass 40 | 0x00, // bDeviceProtocol 41 | 0x08, // bMaxPacketSize0 = 8 42 | 0x86, 43 | 0x1A, // idVendor = 0x1A86 44 | 0x23, 45 | 0x75, // idProduct = 0x7523 46 | 0x62, 47 | 0x02, // bcdDevice = 2.62 48 | 0x00, // Index of string descriptor describing manufacturer 49 | 0x02, // Index of string descriptor describing product 50 | 0x00, // Index of string descriptor describing the device's serial number 51 | 0x01 // bNumConfigurations 52 | }; 53 | 54 | //USB Configuration Descriptor 55 | const uint8_t ConfigDescriptor[] = 56 | { 57 | 0x09, // bLength: Configuration Descriptor size 58 | 0x02, // bDescriptorType: Configuration 59 | 0x27, // wTotalLength:no of returned bytes 60 | 0x00, 61 | 0x01, // bNumInterfaces: 1 interface 62 | 0x01, // bConfigurationValue: Configuration value 63 | 0x00, // iConfiguration: Index of string descriptor describing the configuration 64 | 0x80, // bmAttributes: self powered 65 | 0x31, // MaxPower 98 mA 66 | 67 | //Interface Descriptor 68 | 0x09, // bLength: Interface Descriptor size 69 | 0x04, // bDescriptorType: Interface 70 | // Interface descriptor type 71 | 0x00, // bInterfaceNumber: Number of Interface 72 | 0x00, // bAlternateSetting: Alternate setting 73 | 0x03, // bNumEndpoints: 3 endpoints used 74 | 0xFF, // bInterfaceClass: Vendor Interface Class 75 | 0x01, // bInterfaceSubClass 76 | 0x02, // bInterfaceProtocol 77 | 0x00, // iInterface: 78 | 79 | //Endpoint 2 IN Descriptor 80 | 0x07, // bLength: Endpoint Descriptor size 81 | 0x05, // bDescriptorType: Endpoint 82 | 0x82, // bEndpointAddress: (IN2) 83 | 0x02, // bmAttributes: Bulk 84 | 0x20, // wMaxPacketSize: 85 | 0x00, 86 | 0x00, // bInterval: 87 | 88 | //Endpoint 2 OUT Descriptor 89 | 0x07, // bLength: Endpoint Descriptor size 90 | 0x05, // bDescriptorType: Endpoint 91 | 0x02, // bEndpointAddress: (OUT2) 92 | 0x02, // bmAttributes: Bulk 93 | 0x20, // wMaxPacketSize: 94 | 0x00, 95 | 0x00, // bInterval: ignore for Bulk transfer 96 | 97 | //Endpoint 1 IN Descriptor 98 | 0x07, // bLength: Endpoint Descriptor size 99 | 0x05, // bDescriptorType: Endpoint 100 | 0x81, // bEndpointAddress: (IN1) 101 | 0x03, // bmAttributes: Interrupt 102 | 0x08, // wMaxPacketSize: 103 | 0x00, 104 | 0x01 // bInterval 105 | }; 106 | 107 | //USB String Descriptors 108 | const uint8_t StringLangID[] = 109 | { 110 | 0x04, 111 | 0x03, 112 | 0x09, 113 | 0x04 // LangID = 0x0409: U.S. English 114 | }; 115 | 116 | const uint8_t StringVendor[] = 117 | { 118 | 0x26, // Size of Vendor string 119 | 0x03, // bDescriptorType 120 | // Manufacturer: "STMicroelectronics" 121 | 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, 122 | 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, 123 | 'c', 0, 's', 0 124 | }; 125 | 126 | const uint8_t StringProduct[] = 127 | { 128 | 0x1C, // bLength 129 | 0x03, // bDescriptorType 130 | // Serial name: "USB 2.0-Serial" 131 | 'U', 0, 'S', 0, 'B', 0, '2', 0, '.', 0, '0', 0, '-', 0, 132 | 'S', 0, 'e', 0, 'r', 0, 'i', 0, 'a', 0, 'l', 0 133 | }; 134 | 135 | const uint8_t StringSerial[] = 136 | { 137 | 0x1C, // bLength 138 | 0x03, // bDescriptorType 139 | // Serial name: "USB 2.0-Serial" 140 | 'U', 0, 'S', 0, 'B', 0, '2', 0, '.', 0, '0', 0, '-', 0, 141 | 'S', 0, 'e', 0, 'r', 0, 'i', 0, 'a', 0, 'l', 0 142 | }; 143 | 144 | //Vendor specifics 145 | const uint8_t vendorVersion[] = { 0x31, 0x00 }; 146 | const uint8_t vendorAttach[] = { 0xC3, 0x00 }; 147 | const uint8_t vendorStatus[] = { 0xFF, 0xEE }; 148 | 149 | //Function for getting a character from the USB receive buffer 150 | int16_t usbRead(void) 151 | { 152 | uint8_t c; 153 | 154 | //See if there is any data in the buffer 155 | if(usb_rx_out_idx == usb_rx_in_idx) 156 | return -1; 157 | 158 | //Get available character 159 | c = usb_rx[usb_rx_out_idx++]; 160 | 161 | //Keep index in valid range 162 | usb_rx_out_idx %= sizeof(usb_rx); 163 | 164 | return c; 165 | } 166 | 167 | //Function for putting a character in the USB transmit buffer 168 | void usbSend(uint8_t c) 169 | { 170 | uint8_t charsfree; 171 | 172 | //Wait until there is room in the transmit buffer 173 | do 174 | { 175 | //Calculate the number of free bytes minus one. Need one byte free because indexes being the same means empty buffer. 176 | charsfree = usb_tx_out_idx - usb_tx_in_idx - 1; 177 | 178 | //When the in index is higher than the out index the result is negative so add the size of the buffer to get the 179 | //number of free bytes. Otherwise the result is already positive 180 | if(usb_tx_in_idx >= usb_tx_out_idx) 181 | charsfree += sizeof(usb_tx); 182 | 183 | //When charsfree is 0 the buffer is full so calculate again till space comes available 184 | } while(charsfree == 0); 185 | 186 | //Disable transmission while putting character in the buffer 187 | EP2DisableTX = 1; 188 | 189 | //Put the character in the transmit buffer and move to next free location 190 | usb_tx[usb_tx_in_idx++] = c; 191 | 192 | //Keep index in range of buffer size 193 | usb_tx_in_idx %= sizeof(usb_tx); 194 | 195 | //Enable transmission when done 196 | EP2DisableTX = 0; 197 | } 198 | 199 | void usbInit(void) 200 | { 201 | //Setup the USB peripheral 202 | //Enable USB 203 | RCC->APB1ENR |= RCC_APB1ENR_USBEN; 204 | 205 | //Configure EXTI line 18 which is internally connected to the USB interrupt 206 | EXTI->PR = EXTI_Line18; //Clear possible pending interrupt first 207 | EXTI->RTSR |= EXTI_Line18; //Set to trigger on rising edge 208 | EXTI->IMR |= EXTI_Line18; //Enable the interrupt 209 | 210 | //Configure the Nested Vector Interrupt Controller 211 | //Set 2 bit for preemption (group) priority and 2 bits for sub priority 212 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup_2; 213 | 214 | //Set priority for USB interrupt to be lower then the other interrupts 215 | //This is an array of 8 bit registers, of which only the upper 4 bits are used for the priority allowing for 16 levels 216 | //By grouping this is separated to allow for having sub priorities within a single group. 217 | //The higher the number the lower the priority 218 | NVIC->IP[USB_LP_CAN1_RX0_IRQn] = 0xC0; //(1100b) Group priority 3, sub priority 0 219 | 220 | //Enable the USB interrupt 221 | //This is an array of 32 bit registers, only used to enable an interrupt. To disable the ICER registers need to be used 222 | //Each register serves 32 interrupts, so to get the register for the interrupt, shift the IRQ number right 5 times (divide by 32) and to get 223 | //the right interrupt enable bit, shift a unsigned 32 bit integer 1 the IRQ number anded with 31 (modulo 32) times to the right 224 | NVIC->ISER[USB_LP_CAN1_RX0_IRQn >> 0x05] = (uint32_t)0x01 << (USB_LP_CAN1_RX0_IRQn & 0x1F); 225 | 226 | //Setup the Endpoints needed for this USB device 227 | //Endpoint buffer descriptor table is located in the PMA, pointed to by the BTABLE register 228 | USB->BTABLE = BTABLE_ADDRESS; 229 | 230 | //Clear all pending USB interrupts 231 | USB->ISTR = 0; 232 | 233 | //Enable the needed interrupts to handle the USB tasks and clear the reset and power down bit to start the device 234 | USB->CNTR = USB_CNTR_SOFM | USB_CNTR_RESETM | USB_CNTR_CTRM; 235 | } 236 | 237 | void EP0SendData(uint16_t *sptr, uint16_t len, uint16_t maxlen) 238 | { 239 | uint32_t *dptr = (uint32_t *)EP0TX_BASE; 240 | 241 | if(len > maxlen) 242 | len = maxlen; 243 | 244 | EP0TxPtr = sptr; 245 | EP0TxLen = len; 246 | 247 | //Check if more bytes to send than buffer space available 248 | if(len > 8) 249 | len = 8; 250 | 251 | //Take of the number of bytes being send now 252 | EP0TxLen -= len; 253 | 254 | //Signal to the USB device how many bytes need to be send 255 | EPBTABLE->EPD[0].TX_COUNT.DATA = len; 256 | 257 | //Number of bytes needs to be divided by two because transfer is done two bytes at a time 258 | //Add one extra to allow for odd number of bytes to be handled 259 | len = (len + 1) / 2; 260 | 261 | //Copy the bytes to the PMA 262 | while(len--) 263 | *dptr++ = (uint32_t)*EP0TxPtr++; 264 | 265 | //Signal ready to transmit by preparing for toggling the needed TX status bits 266 | //Keep the other bits unaltered, by using the previous data or the invariant value 267 | USB->EP0R = ((USB->EP0R ^ USB_EP_TX_VALID) & (USB_EPREG_MASK | USB_EPTX_STAT)) | USB_EP_CTR_RX | USB_EP_CTR_TX; 268 | } 269 | 270 | void EP2SendData(void) 271 | { 272 | uint32_t *dptr = (uint32_t *)EP2TX_BASE; 273 | uint16_t usbdata; 274 | uint16_t cnt; 275 | 276 | //Check if transmission has been disabled 277 | if(EP2DisableTX == 1) 278 | return; 279 | 280 | //Check if there is data to send to the host 281 | //Calculate the number of bytes available in the buffer 282 | if((cnt = usb_tx_in_idx - usb_tx_out_idx) != 0) 283 | { 284 | //When out index bigger then in index data has a rollover in the buffer so need add the size of the buffer to get the right number 285 | if(usb_tx_out_idx > usb_tx_in_idx) 286 | cnt += sizeof(usb_tx); 287 | 288 | //Check if available number of characters more then the USB buffer size. If so limit the number to be copied 289 | if(cnt > 32) 290 | cnt = 32; 291 | 292 | //Signal to the USB device how many bytes need to be send 293 | EPBTABLE->EPD[2].TX_COUNT.DATA = cnt; 294 | 295 | //Copy all the needed bytes to the PMA two bytes at a time 296 | while(cnt--) 297 | { 298 | //Put first byte in low part of the temporary storage for making 16 bits data 299 | usbdata = (uint16_t)(usb_tx[usb_tx_out_idx++]); 300 | 301 | //Check if out index needs to rollover back to start of buffer 302 | usb_tx_out_idx %= sizeof(usb_tx); 303 | 304 | //See if next byte available 305 | if(cnt) 306 | { 307 | //Put second byte in high part of the temporary storage for making 16 bits data 308 | usbdata |= (uint16_t)(usb_tx[usb_tx_out_idx++] << 8); 309 | 310 | //Check if out index needs to rollover back to start of buffer 311 | usb_tx_out_idx %= sizeof(usb_tx); 312 | 313 | //Did the second byte 314 | cnt--; 315 | } 316 | 317 | //Store the data in the PMA and point to next 16 bits data field 318 | *dptr++ = usbdata; 319 | } 320 | 321 | //Signal ready to transmit by preparing for toggling the needed TX status bits 322 | //Keep the other bits unaltered, by using the previous data or the invariant value 323 | USB->EP2R = ((USB->EP2R ^ USB_EP_TX_VALID) & (USB_EPREG_MASK | USB_EPTX_STAT)) | USB_EP_CTR_RX | USB_EP_CTR_TX; 324 | } 325 | } 326 | 327 | void usbIrqHandler(void) 328 | { 329 | //Check if we received an USB start of frame 330 | if(USB->ISTR & USB_ISTR_SOF) 331 | { 332 | //Check if device is configured to send data 333 | if(DeviceConfigured == 1) 334 | { 335 | //Send data through endpoint 2 336 | EP2SendData(); 337 | } 338 | 339 | //Reset the interrupt flag 340 | USB->ISTR = (uint16_t)(~USB_ISTR_SOF); 341 | } 342 | 343 | //Check if we received an USB expected start of frame 344 | if(USB->ISTR & USB_ISTR_ESOF) 345 | { 346 | //Reset the interrupt flag 347 | USB->ISTR = (uint16_t)(~USB_ISTR_ESOF); 348 | } 349 | 350 | //Check if we received an USB correct transfer 351 | if(USB->ISTR & USB_ISTR_CTR) 352 | { 353 | uint8_t epid = USB->ISTR & USB_ISTR_EP_ID; 354 | 355 | //Check if the control end point is addressed 356 | if(epid == 0) 357 | { 358 | //Check if data received 359 | if(USB->EP0R & USB_EP_CTR_RX) 360 | { 361 | //For the control endpoint the type is kept on control and the address stays on 0 362 | //The EP_KIND bit is not used so kept on zero 363 | //Reset the CTR RX bit by writing a zero to it 364 | USB->EP0R = USB_EP_CONTROL | USB_EP_CTR_TX; 365 | 366 | //Check if setup data received 367 | if(USB->EP0R & USB_EP_SETUP) 368 | { 369 | //Process the setup data 370 | switch(SETUPPACKET->bRequest) 371 | { 372 | case USB_REQUEST_SET_ADDRESS: 373 | //Send zero length packet 374 | EP0SendData(0, 0, 8); 375 | 376 | //Prepare the device address for being set after zero length data has been transmitted 377 | DeviceAddress = SETUPPACKET->wValue.bytes.low; 378 | break; 379 | 380 | case USB_REQUEST_GET_DESCRIPTOR: 381 | switch(SETUPPACKET->wValue.bytes.high) 382 | { 383 | case USB_DEVICE_DESC_TYPE: 384 | EP0SendData((uint16_t *)DeviceDescriptor, sizeof(DeviceDescriptor), SETUPPACKET->wLength); 385 | break; 386 | 387 | case USB_CFG_DESC_TYPE: 388 | EP0SendData((uint16_t *)ConfigDescriptor, sizeof(ConfigDescriptor), SETUPPACKET->wLength); 389 | break; 390 | 391 | case USB_STR_DESC_TYPE: 392 | switch(SETUPPACKET->wValue.bytes.low) 393 | { 394 | case 0: 395 | EP0SendData((uint16_t *)StringLangID, sizeof(StringLangID), SETUPPACKET->wLength); 396 | break; 397 | 398 | case 1: 399 | EP0SendData((uint16_t *)StringVendor, sizeof(StringVendor), SETUPPACKET->wLength); 400 | break; 401 | 402 | case 2: 403 | EP0SendData((uint16_t *)StringProduct, sizeof(StringProduct), SETUPPACKET->wLength); 404 | break; 405 | 406 | case 3: 407 | EP0SendData((uint16_t *)StringSerial, sizeof(StringSerial), SETUPPACKET->wLength); 408 | break; 409 | } 410 | break; 411 | 412 | default: 413 | EP0SendData(0, 0, 8); 414 | break; 415 | } 416 | break; 417 | 418 | case USB_REQUEST_SET_CONFIGURATION: 419 | case USB_CH340_REQ_SERIAL_INIT: 420 | case USB_CH340_REQ_WRITE_REG: 421 | case USB_CH340_REQ_MODEM_CTRL: 422 | //Respond with 0 length packet 423 | EP0SendData(0, 0, 8); 424 | break; 425 | 426 | case USB_CH340_REQ_VENDOR_VERSION: 427 | EP0SendData((uint16_t *)vendorVersion, sizeof(vendorVersion), SETUPPACKET->wLength); 428 | break; 429 | 430 | case USB_CH340_REQ_READ_REG: 431 | if(SETUPPACKET->wValue.word == USB_CH340_READ_ATTACH) 432 | EP0SendData((uint16_t *)vendorAttach, sizeof(vendorAttach), SETUPPACKET->wLength); 433 | else if(SETUPPACKET->wValue.word == USB_CH340_READ_STATUS) 434 | EP0SendData((uint16_t *)vendorStatus, sizeof(vendorStatus), SETUPPACKET->wLength); 435 | break; 436 | } 437 | } 438 | 439 | //Signal we are ready to receive more data by preparing for toggling the needed RX status bits 440 | //Keep the other bits unaltered, by using the previous data or the invariant value 441 | USB->EP0R = ((USB->EP0R ^ USB_EP_RX_VALID) & (USB_EPREG_MASK | USB_EPRX_STAT)) | USB_EP_CTR_RX | USB_EP_CTR_TX; 442 | } 443 | 444 | if(USB->EP0R & USB_EP_CTR_TX) 445 | { 446 | //Reset the CTR TX bit by writing a zero to it 447 | USB->EP0R = USB_EP_CONTROL | USB_EP_CTR_RX; 448 | 449 | //Check if a set device address has been received 450 | if(DeviceAddress) 451 | { 452 | //Set the received address and keep the device enabled 453 | USB->DADDR = DeviceAddress | USB_DADDR_EF; 454 | 455 | //Clear flag so address not set again 456 | DeviceAddress = 0; 457 | 458 | //Signal device is active 459 | DeviceConfigured = 1; 460 | } 461 | 462 | //Check if we need to send something 463 | if(EP0TxLen) 464 | { 465 | //TX means data send to the host 466 | //So check if more data needs to be send. 467 | uint32_t *dptr = (uint32_t *)EP0TX_BASE; 468 | uint8_t len = EP0TxLen; 469 | 470 | //Check if more bytes to send then space available 471 | if(len > 8) 472 | len = 8; 473 | 474 | //Take of the number of bytes being send now 475 | EP0TxLen -= len; 476 | 477 | //Signal to the USB device how many bytes need to be send 478 | EPBTABLE->EPD[0].TX_COUNT.DATA = len; 479 | 480 | //Number of bytes needs to be divided by two because transfer is done two bytes at a time 481 | //Add one extra to allow for odd number of bytes to be handled 482 | len = (len + 1) / 2; 483 | 484 | //Copy the bytes to the PMA 485 | while(len--) 486 | *dptr++ = (uint32_t)*EP0TxPtr++; 487 | 488 | //Signal ready to transmit by preparing for toggling the needed TX status bits 489 | //Keep the other bits unaltered, by using the previous data or the invariant value 490 | USB->EP0R = ((USB->EP0R ^ USB_EP_TX_VALID) & (USB_EPREG_MASK | USB_EPTX_STAT)) | USB_EP_CTR_RX | USB_EP_CTR_TX; 491 | } 492 | } 493 | } 494 | else if(epid == 2) 495 | { 496 | //Endpoint 2 is used to handle the serial communication data 497 | 498 | //Check if data received 499 | if(USB->EP2R & USB_EP_CTR_RX) 500 | { 501 | //Reset the CTR RX bit by writing a zero to it 502 | USB->EP2R = USB_EP_BULK | USB_EP_CTR_TX | 0x0002; 503 | 504 | //Get the number of bytes to process 505 | uint8_t cnt = EPBTABLE->EPD[2].RX_COUNT.DATA & 0x7F; 506 | uint32_t *dptr = (uint32_t *)EP2RX_BASE; 507 | uint16_t data; 508 | 509 | //Copy the data from the PMA to the receive buffer 510 | while(cnt--) 511 | { 512 | //Get two bytes from the PMA 513 | data = *dptr++; 514 | 515 | //Put the first byte in the receive buffer 516 | usb_rx[usb_rx_in_idx++] = data & 0xFF; 517 | usb_rx_in_idx %= sizeof(usb_rx); 518 | 519 | //Check if more bytes need to be processed 520 | if(cnt) 521 | { 522 | //Put the second byte in the receive buffer 523 | usb_rx[usb_rx_in_idx++] = (data >> 8) & 0xFF; 524 | usb_rx_in_idx %= sizeof(usb_rx); 525 | cnt--; 526 | } 527 | } 528 | 529 | //Signal we are ready to receive more data by preparing for toggling the needed RX status bits 530 | //Keep the other bits unaltered, by using the previous data or the invariant value 531 | USB->EP2R = ((USB->EP2R ^ USB_EP_RX_VALID) & (USB_EPREG_MASK | USB_EPRX_STAT)) | USB_EP_CTR_RX | USB_EP_CTR_TX; 532 | } 533 | 534 | //Data has been send so check if we need to send some more 535 | if(USB->EP2R & USB_EP_CTR_TX) 536 | { 537 | //Reset the CTR TX bit by writing a zero to it 538 | USB->EP2R = USB_EP_BULK | USB_EP_CTR_RX | 0x0002; 539 | 540 | EP2SendData(); 541 | } 542 | } 543 | } 544 | 545 | //Check if we received an USB reset 546 | if(USB->ISTR & USB_ISTR_RESET) 547 | { 548 | //Endpoint 0 is the control endpoint 549 | //Endpoint registers have toggle bits. These are toggled by writing a 1. It concerns the status bits and the dtog bits 550 | //They also have write 0 clear bits. These are the correct transfer bits. So cleared by writing a 0. Writing 1 has no effect 551 | //On receipt of an USB reset all endpoint registers are cleared, except for the two CTR bits. 552 | 553 | //Set the type of this endpoint to control, receive valid and stall transmission. Endpoint address is 0. 554 | USB->EP0R = USB_EP_CONTROL | USB_EP_RX_VALID | USB_EP_TX_NAK | USB_EP_CTR_RX | USB_EP_CTR_TX; 555 | 556 | //Setup send and receive buffer 557 | EPBTABLE->EPD[0].TX_ADDRESS.DATA = 0x0080; 558 | EPBTABLE->EPD[0].TX_COUNT.DATA = 0; 559 | EPBTABLE->EPD[0].RX_ADDRESS.DATA = 0x0040; 560 | EPBTABLE->EPD[0].RX_COUNT.DATA = USB_8_BYTE_RX_BUF; 561 | 562 | //Set endpoint 1 to interrupt and transmit nak and receive disabled. Endpoint address is 1; 563 | USB->EP1R = USB_EP_INTERRUPT | USB_EP_RX_DIS | USB_EP_TX_NAK | USB_EP_CTR_RX | USB_EP_CTR_TX | 0x0001; 564 | 565 | //Setup send and receive buffer. Receive is disabled so 0 byte buffer 566 | EPBTABLE->EPD[1].TX_ADDRESS.DATA = 0x0110; 567 | EPBTABLE->EPD[1].TX_COUNT.DATA = 0; 568 | EPBTABLE->EPD[1].RX_ADDRESS.DATA = 0x0000; 569 | EPBTABLE->EPD[1].RX_COUNT.DATA = 0; 570 | 571 | //Set endpoint 2 to bulk and transmit nak and receive valid. Endpoint address is 2 572 | USB->EP2R = USB_EP_BULK | USB_EP_RX_VALID | USB_EP_TX_NAK | USB_EP_CTR_RX | USB_EP_CTR_TX | 0x0002; 573 | 574 | //Setup send and receive buffer 575 | EPBTABLE->EPD[2].TX_ADDRESS.DATA = 0x00C0; 576 | EPBTABLE->EPD[2].TX_COUNT.DATA = 0; 577 | EPBTABLE->EPD[2].RX_ADDRESS.DATA = 0x0100; 578 | EPBTABLE->EPD[2].RX_COUNT.DATA = USB_32_BYTE_RX_BUF; 579 | 580 | //Allow some USB events to generate interrupts 581 | USB->CNTR = USB_CNTR_SOFM | USB_CNTR_RESETM | USB_CNTR_CTRM; 582 | 583 | //The endpoint buffer table is at the start of the PMA 584 | USB->BTABLE = BTABLE_ADDRESS; 585 | 586 | //Reset the device address and keep the device enabled 587 | USB->DADDR = USB_DADDR_EF; 588 | 589 | //Signal device is not active 590 | DeviceConfigured = 0; 591 | 592 | //Reset all interrupt flags 593 | USB->ISTR = 0; 594 | } 595 | } 596 | 597 | -------------------------------------------------------------------------------- /STM32F3_Sine_Square_Gen/usb.h: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------------ 2 | // Simple USB implementation for STM32F103C8T6 Bluepill board 3 | // Based on CH340 USB to serial converter and derived from STM virtual com port 4 | // but uses way less code. Lacks error handling. 5 | // 6 | // To use the USB device the system clock needs to be either 48MHz or 72MHz 7 | // Select the right SUB clock divide setting to have a 48MHz USB clock 8 | // RCC->CFGR USB_PRE bit 9 | // 0 for 72MHz system clock 10 | // 1 for 48MHZ system clock 11 | //------------------------------------------------------------------------------ 12 | 13 | #ifndef USB_H 14 | #define USB_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | void usbInit(void); //Needs to be called before the USB device can be used 21 | void usbIrqHandler(void); //Needs to be set in the interrupt vector table 22 | void usbSend(uint8_t c); //Can be called to send a character 23 | int16_t usbRead(void); //Can be called to get a character. Returns -1 when nothing available 24 | 25 | //Default USB endpoint settings 26 | #define EP0RX_BASE 0x40006080 //Endpoint 0 receive buffer base 27 | #define EP0TX_BASE 0x40006100 //Endpoint 0 transmit buffer base 28 | 29 | #define EP2RX_BASE 0x40006200 //Endpoint 2 receive buffer base 30 | #define EP2TX_BASE 0x40006180 //Endpoint 2 transmit buffer base 31 | 32 | #define BTABLE_ADDRESS 0x00 33 | 34 | //Overlay on PMA endpoint 0 receive buffer to get to setup data 35 | typedef struct 36 | { 37 | __IO uint8_t bmRequestType; 38 | __IO uint8_t bRequest; 39 | uint16_t RESERVED1; 40 | __IO wbcombi wValue; 41 | uint16_t RESERVED2; 42 | __IO wbcombi wIndex; 43 | uint16_t RESERVED3; 44 | __IO uint16_t wLength; 45 | uint16_t RESERVED4; 46 | } SETUP_PCKT_TypeDef; 47 | 48 | #define SETUPPACKET ((SETUP_PCKT_TypeDef *) EP0RX_BASE) 49 | 50 | 51 | //Receive count has a special format. The 10 least significant bits represent the number of actually received bytes 52 | //The upper 6 bits use a block count system where the buffer size is either multiples of 2 or 32 53 | //So for an 8 byte buffer the setting is msb low and a block count of 4 54 | //So for an 32 byte buffer the setting is msb low and a block count of 16 55 | #define USB_8_BYTE_RX_BUF 0x1000U 56 | #define USB_32_BYTE_RX_BUF 0x4000U 57 | 58 | 59 | //bmRequestType.Type 60 | #define REQUEST_STANDARD 0 61 | #define REQUEST_CLASS 1 62 | #define REQUEST_VENDOR 2 63 | #define REQUEST_RESERVED 3 64 | 65 | //USB Standard Request Codes 66 | #define USB_REQUEST_GET_STATUS 0 67 | #define USB_REQUEST_CLEAR_FEATURE 1 68 | #define USB_REQUEST_SET_FEATURE 3 69 | #define USB_REQUEST_SET_ADDRESS 5 70 | #define USB_REQUEST_GET_DESCRIPTOR 6 71 | #define USB_REQUEST_SET_DESCRIPTOR 7 72 | #define USB_REQUEST_GET_CONFIGURATION 8 73 | #define USB_REQUEST_SET_CONFIGURATION 9 74 | #define USB_REQUEST_GET_INTERFACE 10 75 | #define USB_REQUEST_SET_INTERFACE 11 76 | #define USB_REQUEST_SYNC_FRAME 12 77 | 78 | // USB Descriptor Types 79 | #define USB_DEVICE_DESC_TYPE 1 80 | #define USB_CFG_DESC_TYPE 2 81 | #define USB_STR_DESC_TYPE 3 82 | #define USB_IFACE_DESC_TYPE 4 83 | #define USB_EP_DESC_TYPE 5 84 | #define USB_DEVICE_QR_DESC_TYPE 6 85 | #define USB_OSPEED_CFG_DESC_TYPE 7 86 | #define USB_IFACE_PWR_DESC_TYPE 8 87 | 88 | 89 | #define USB_CH340_REQ_VENDOR_VERSION 0x5F 90 | #define USB_CH340_REQ_READ_REG 0x95 91 | #define USB_CH340_REQ_WRITE_REG 0x9A 92 | #define USB_CH340_REQ_SERIAL_INIT 0xA1 93 | #define USB_CH340_REQ_MODEM_CTRL 0xA4 94 | 95 | #define USB_CH340_READ_ATTACH 0x2518 //For reading the line control setting 96 | #define USB_CH340_READ_STATUS 0x0706 //For reading the modem line status 97 | 98 | #define USB_CH340_REG_BAUDRATE 0x1312 99 | #define USB_CH340_REG_BAUDFACTOR 0x0F2C //Sends the low byte of the factor for more precise baud setting 100 | #define USB_CH340_REG_LINECONTROL 0x2518 //For writing the line control settings when used 101 | //Some linux variants have a different driver where this is not used 102 | //Is always 0x50 which should be 0xC3 103 | 104 | #define CH340_LCR_ENABLE_RX 0x80 105 | #define CH340_LCR_ENABLE_TX 0x40 106 | #define CH340_LCR_MARK_SPACE 0x20 107 | #define CH340_LCR_PAR_EVEN 0x10 108 | #define CH340_LCR_ENABLE_PAR 0x08 109 | #define CH340_LCR_STOP_BITS_2 0x04 110 | #define CH340_LCR_CS8 0x03 111 | #define CH340_LCR_CS7 0x02 112 | #define CH340_LCR_CS6 0x01 113 | #define CH340_LCR_CS5 0x00 114 | 115 | #define CH340_LCR_NOF_BITS_MASK 0x03 116 | 117 | #define CH340_BIT_CTS 0x01 118 | #define CH340_BIT_DSR 0x02 119 | #define CH340_BIT_RI 0x04 120 | #define CH340_BIT_DCD 0x08 121 | 122 | #define CH340_BAUDRATE_FACTOR 1532620800 123 | #define CH340_BAUDRATE_DIVMAX 3 124 | 125 | #ifdef __cplusplus 126 | } 127 | #endif 128 | 129 | #endif /* USB_H */ 130 | 131 | --------------------------------------------------------------------------------