├── .dir-locals.el ├── .gitignore ├── .gitmodules ├── .travis.yml ├── CMakeLists.txt ├── LICENSE ├── README.md ├── cmake └── Macros.cmake ├── contrib └── CMakeLists.txt ├── rtl ├── CMakeLists.txt ├── clk_div_by_3 │ ├── CMakeLists.txt │ ├── README.md │ ├── clk_div_by_3.cpp │ ├── clk_div_by_3.sv │ ├── clk_div_by_3.tcl.in │ └── clk_div_by_3.xdc.in ├── count_ones │ ├── CMakeLists.txt │ ├── README.md │ ├── count_ones.cpp │ └── count_ones.sv ├── count_zeros_32 │ ├── CMakeLists.txt │ ├── count_zeros_32.cpp │ └── count_zeros_32.sv ├── detect_sequence │ ├── CMakeLists.txt │ ├── detect_sequence.cpp │ ├── detect_sequence.sv │ ├── detect_sequence.tcl.in │ └── detect_sequence.xdc.in ├── div_by_3 │ ├── CMakeLists.txt │ ├── div_by_3.cpp │ └── div_by_3.sv ├── fibonacci │ ├── CMakeLists.txt │ ├── fibonacci.cpp │ └── fibonacci.sv ├── fifo_async │ ├── CMakeLists.txt │ ├── README.md │ ├── fifo_async.sv │ ├── fifo_async.tcl.in │ ├── fifo_async.xdc.in │ ├── fifo_async_tb.cpp │ ├── fifo_async_tb.h │ ├── fifo_async_tb.sv │ └── fifo_async_tb_ports.h ├── fifo_multi_push │ ├── CMakeLists.txt │ ├── README.md │ ├── fifo_multi_push.cpp │ ├── fifo_multi_push.sv │ ├── fifo_multi_push.tcl.in │ └── fifo_multi_push.xdc.in ├── fifo_n │ ├── CMakeLists.txt │ ├── README.md │ ├── fifo_n.cpp │ ├── fifo_n.sv │ ├── fifo_n.tcl.in │ └── fifo_n.xdc.in ├── fifo_ptr │ ├── CMakeLists.txt │ ├── fifo_ptr.cpp │ └── fifo_ptr.sv ├── fifo_sr │ ├── CMakeLists.txt │ ├── README.md │ ├── fifo_sr.cpp │ └── fifo_sr.sv ├── fused_multiply_add │ ├── CMakeLists.txt │ ├── fused_multiply_add.cpp │ └── fused_multiply_add.sv ├── gates_from_MUX2X1 │ ├── CMakeLists.txt │ ├── README.md │ ├── gates_from_MUX2X1.cpp │ └── gates_from_MUX2X1.sv ├── increment │ ├── CMakeLists.txt │ ├── README.md │ ├── increment.cpp │ └── increment.sv ├── latency │ ├── CMakeLists.txt │ ├── README.md │ ├── latency.cpp │ ├── latency.sv │ ├── latency.tcl.in │ └── latency.xdc.in ├── mcp_formulation │ ├── CMakeLists.txt │ ├── mcp_formulation.cpp │ ├── mcp_formulation.sv │ ├── mcp_formulation_c.sv │ └── mcp_formulation_l.sv ├── missing_duplicated_word │ ├── CMakeLists.txt │ ├── README.md │ ├── missing_duplicated_word.cpp │ └── missing_duplicated_word.sv ├── multi_counter │ ├── CMakeLists.txt │ ├── README.md │ ├── multi_counter.cpp │ ├── multi_counter.sv │ └── multi_counter_pkg.vh ├── multi_counter_variants │ ├── CMakeLists.txt │ ├── README.md │ ├── multi_counter_variants.cpp │ ├── multi_counter_variants.sv │ ├── multi_counter_variants.tcl.in │ ├── multi_counter_variants.xdc.in │ └── multi_counter_variants_pkg.vh ├── multiply_by_21 │ ├── CMakeLists.txt │ ├── README.md │ ├── multiply_by_21.cpp │ └── multiply_by_21.sv ├── one_or_two │ ├── CMakeLists.txt │ ├── README.md │ ├── one_or_two.cpp │ ├── one_or_two.sv │ ├── one_or_two.tcl.in │ └── one_or_two.xdc.in ├── pipelined_add_constant │ ├── A.sv │ ├── B.sv │ ├── CMakeLists.txt │ ├── pipelined_add_constant.cpp │ ├── pipelined_add_constant.sv │ └── two_cycle_adder.sv ├── sorted_lists │ ├── CMakeLists.txt │ ├── README.md │ ├── sorted_lists.cpp │ ├── sorted_lists.max.rpt │ ├── sorted_lists.min.rpt │ ├── sorted_lists.sv │ ├── sorted_lists.tcl.in │ ├── sorted_lists.xdc.in │ ├── sorted_lists_pkg.vh │ └── sorting_network.sv ├── using_full_adders │ ├── CMakeLists.txt │ ├── README.md │ ├── using_full_adders.cpp │ └── using_full_adders.sv ├── vending_machine_dp │ ├── CMakeLists.txt │ ├── README.md │ ├── vending_machine_dp.cpp │ ├── vending_machine_dp.sv │ ├── vending_machine_dp.tcl.in │ └── vending_machine_dp.xdc.in ├── vending_machine_fsm │ ├── CMakeLists.txt │ ├── README.md │ ├── vending_machine_fsm.cpp │ ├── vending_machine_fsm.sv │ ├── vending_machine_fsm.tcl.in │ └── vending_machine_fsm.xdc.in ├── zero_indices_fast │ ├── CMakeLists.txt │ ├── zero_indices_fast.cpp │ ├── zero_indices_fast.sv │ └── zero_indices_slow.sv └── zero_indices_slow │ ├── CMakeLists.txt │ ├── zero_indices_slow.cpp │ └── zero_indices_slow.sv └── scripts └── verilate.sh /.dir-locals.el: -------------------------------------------------------------------------------- 1 | ((nil . ((fill-column 80))) 2 | (verilog-mode . ((verilog-align-ifelse . t) 3 | (verilog-auto-delete-trailing-whitespace . t) 4 | (verilog-auto-inst-param-value . t) 5 | (verilog-auto-inst-vector . nil) 6 | (verilog-auto-lineup . 'all) 7 | (verilog-auto-newline . nil) 8 | (verilog-auto-save-policy . nil) 9 | (verilog-auto-template-warn-unused . t) 10 | (verilog-case-indent . 2) 11 | (verilog-cexp-indent . 2) 12 | (verilog-highlight-grouping-keywords . t) 13 | (verilog-highlight-modules . t) 14 | (verilog-indent-level . 2) 15 | (verilog-indent-level-behavioral . 2) 16 | (verilog-indent-level-declaration . 2) 17 | (verilog-indent-level-module . 2) 18 | (verilog-tab-to-comment . t)))) 19 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Build directories 2 | build 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "contrib/libtb"] 2 | path = contrib/libtb 3 | url = https://github.com/stephenry/libtb.git 4 | [submodule "contrib/libv"] 5 | path = contrib/libv 6 | url = https://github.com/stephenry/libv.git 7 | [submodule "contrib/systemc"] 8 | path = contrib/systemc 9 | url = https://github.com/stephenry/systemc.git 10 | [submodule "contrib/libpd"] 11 | path = contrib/libpd 12 | url = https://github.com/stephenry/libpd.git 13 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | sudo: required 2 | language: c++ 3 | dist: trusty 4 | 5 | cache: 6 | apt: true 7 | directories: 8 | - ${TRAVIS_BUILD_DIR}/deps/llvm-3.9.0 9 | 10 | matrix: 11 | include: 12 | - os: linux 13 | env: COMPILER=g++-6 BOOST_VERSION=default 14 | compiler: gcc 15 | 16 | addons: 17 | apt: 18 | sources: &sources 19 | - george-edison55-precise-backports 20 | - ubuntu-toolchain-r-test 21 | packages: 22 | - cmake 23 | - cmake-data 24 | 25 | before_install: 26 | - sudo apt-get install verilator 27 | - sudo apt-get install libboost-dev 28 | - sudo apt-get install libboost-program-options-dev 29 | 30 | script: 31 | - | 32 | git submodule init 33 | git submodule update 34 | mkdir build 35 | pushd build 36 | cmake ../ 37 | make 38 | 39 | # TODO: notifications 40 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | CMAKE_MINIMUM_REQUIRED(VERSION 3.2) 29 | PROJECT(hw_interview_questions) 30 | 31 | SET(CMAKE_CXX_STANDARD 11) 32 | 33 | # Each 'answer' replicates the same set of CMAKE targets. Although the targets 34 | # are in different directories, and therefore do not conflict, CMAKE 35 | # specifically disallows such a construction to remain compatible with GUI IDE. 36 | # 37 | set_property(GLOBAL PROPERTY ALLOW_DUPLICATE_CUSTOM_TARGETS 1) 38 | 39 | SET(CMAKE_MODULE_PATH 40 | ${CMAKE_MODULE_PATH} 41 | ${CMAKE_SOURCE_DIR}/cmake 42 | ${CMAKE_SOURCE_DIR}/contrib/libtb/cmake 43 | ${CMAKE_SOURCE_DIR}/contrib/libpd/cmake 44 | ) 45 | 46 | INCLUDE(cmake/Macros.cmake) 47 | 48 | ADD_SUBDIRECTORY(contrib) 49 | ADD_SUBDIRECTORY(rtl) 50 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Hardware Interview Questions 2 | 3 | [![Build Status](https://travis-ci.org/stephenry/hw_interview_questions.svg?branch=master)](https://travis-ci.org/stephenry/hw_interview_questions) 4 | 5 | ## Introduction 6 | 7 | This project presents solutions to common hardware design/VLSI interview 8 | questions. Presented are SystemVerilog implementations alongside self-checking 9 | verification environments. Thorough discussion on the elements saught by 10 | interviewer in a candidates solution provided. 11 | 12 | ## System Requirements 13 | * cmake >= 3.2 14 | * systemc >= 2.3.1 15 | * verilator >= 3.9 16 | * clang >= 3.9 17 | 18 | ## Build Steps (SIM) 19 | ~~~~ 20 | git clone https://github.com/stephenry/hw_interview_questions 21 | cd hw_interview_questions 22 | git submodule update --init --recursive 23 | mkdir build 24 | cd build 25 | cmake ../ 26 | make 27 | ~~~~ 28 | 29 | ## PD (VIVADO) 30 | 31 | A standard Vivado flow is supported for each answer. PD libaries must 32 | be explicitly selected during configuration (below). Within each answer, 33 | a new target 'vivado' is present that invokes a standard Vivado flow. 34 | 35 | ~~~~ 36 | cmake ../ -DTARGET_VIVADO 37 | make vivado 38 | ~~~~ 39 | 40 | ## Run Steps 41 | Upon successful completion of the build process. Tests can be executed by 42 | invoking the generated executable in the RTL directory. 43 | 44 | ## Answers 45 | * __count_ones__ Answer to compute the population count of an input vector. 46 | * __fifo_async__ Answer to demonstrate the construction of a standard 47 | asynchronous FIFO. 48 | * __fifo_n__ Answer to construct N-statically sized FIFO from a single 49 | dual-ported, synchronous SRAM. 50 | * __fifo_sr__ Answer to implement a shift-register FIFO in a power efficient 51 | manner. 52 | * __fifo_ptr__ Answer to implement a ptr-based FIFO. 53 | * __gates_from_MUX2X1__ Answer to derive AND, OR, XOR and INV logic gates from a 54 | MUX2X standard cell. 55 | * __increment__ Answer to derive logic to compute an increment function. 56 | * __latency__ Answer to compute the average latency of a command stream to and 57 | from some external agent. 58 | * __multi_counter__ Answer to demonstrate basic forwarding and pipeline 59 | concepts. Multiple counters are retained in a central state table. They are 60 | then randomly incremented or decremented on demand. 61 | * __multi_counter_variant__ Alternate solutions to multi_counter problem. 62 | * __one_or_two__ Answer to detect whether for an arbitrary input vector, 0-bits 63 | are set, 1-bit is set, or greater than 1 bit is set. 64 | * __mcp_formulation (Multi-Cycle Path Formulation)__ Answer to pass a vector 65 | between two clock domains using a multi-cycle path. 66 | * __detect_sequence__ Answer to detect a given sequence within an input 67 | serial stream. 68 | * __vending_machine_fsm__ Answer to design a FSM to emulate the behavior of a 69 | simple vending machine. 70 | * __vending_machine_dp__ Variant of FSM solution whereby some accumulation of a 71 | running count is required before an IRN-BRU shall be emitted. 72 | * __clk_div_by_3__ Divide a clock by an odd number while retaining a 50% duty 73 | cycle. 74 | * __missing_duplicated_word__ Answer to detect the value of a non-duplicated 75 | integer in a state table containing duplicated entries. 76 | * __multiply_by_21__ Answer to demonstrate how a constant value can be 77 | efficiently multiplied against a randomized vector. 78 | 79 | ## Disclaimer 80 | Contributions are welcome however please consider that the current project 81 | remains very much a work in progress and that ancillary libraries, upon which 82 | this code depends, remain under active development. 83 | -------------------------------------------------------------------------------- /cmake/Macros.cmake: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | MACRO(EMIT_ANSWER ANSWER) 29 | SET(VERILATED_OBJ "${CMAKE_CURRENT_BINARY_DIR}/obj") 30 | SET(VERILATED_LIB "${VERILATED_OBJ}/V${ANSWER}__ALL.a") 31 | SET(VERILATOR_INCLUDE 32 | "-I${Libv_VINCLUDE_DIRS} -I${CMAKE_CURRENT_SOURCE_DIR} -I${Libtb_VINCLUDE_DIRS} -I${LibpdTech_VINCLUDE_DIRS} -I${Libpd_VINCLUDE_DIRS}" 33 | ) 34 | ADD_CUSTOM_TARGET( 35 | verilate 36 | COMMAND ${CMAKE_COMMAND} -E env 37 | ANSWER=${ANSWER} 38 | VERILATED_OBJ=${VERILATED_OBJ} 39 | VERILATOR_INCLUDE=${VERILATOR_INCLUDE} 40 | VERILATOR_EXE=${Verilator_EXE} 41 | SYSTEMC_INCLUDE=${SystemC_INCLUDE_DIR} 42 | SYSTEMC_LIBDIR=${SystemC_LIBRARY} 43 | CMAKE_CURRENT_SOURCE_DIR=${CMAKE_CURRENT_SOURCE_DIR} 44 | ${CMAKE_SOURCE_DIR}/scripts/verilate.sh 45 | ) 46 | ADD_EXECUTABLE(${ANSWER} ${ANSWER}.cpp) 47 | ADD_DEPENDENCIES(${ANSWER} verilate) 48 | TARGET_INCLUDE_DIRECTORIES(${ANSWER} PUBLIC 49 | ${Verilator_INCLUDE_DIR} 50 | ${SystemC_INCLUDE_DIR} 51 | ${Libtb_INCLUDE_DIRS} 52 | ${VERILATED_OBJ} 53 | ) 54 | TARGET_LINK_LIBRARIES(${ANSWER} 55 | ${SystemC_LIBRARY} 56 | ${VERILATED_LIB} 57 | verilated 58 | pthread 59 | tb 60 | ) 61 | ENDMACRO() 62 | -------------------------------------------------------------------------------- /contrib/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | ADD_SUBDIRECTORY(systemc) 29 | FIND_PACKAGE(SystemC REQUIRED) 30 | # 31 | FIND_PACKAGE(Verilator REQUIRED) 32 | BUILD_VERILATOR_LIBS() 33 | # 34 | ADD_SUBDIRECTORY(libtb) 35 | ADD_SUBDIRECTORY(libv) 36 | 37 | FIND_PACKAGE(Vivado) 38 | ADD_SUBDIRECTORY(libpd) 39 | -------------------------------------------------------------------------------- /rtl/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | ADD_SUBDIRECTORY(one_or_two) 29 | ADD_SUBDIRECTORY(latency) 30 | ADD_SUBDIRECTORY(multi_counter) 31 | ADD_SUBDIRECTORY(multi_counter_variants) 32 | ADD_SUBDIRECTORY(gates_from_MUX2X1) 33 | ADD_SUBDIRECTORY(increment) 34 | ADD_SUBDIRECTORY(fifo_async) 35 | ADD_SUBDIRECTORY(fifo_multi_push) 36 | ADD_SUBDIRECTORY(fifo_n) 37 | ADD_SUBDIRECTORY(fifo_sr) 38 | ADD_SUBDIRECTORY(fifo_ptr) 39 | ADD_SUBDIRECTORY(count_ones) 40 | ADD_SUBDIRECTORY(mcp_formulation) 41 | ADD_SUBDIRECTORY(detect_sequence) 42 | ADD_SUBDIRECTORY(vending_machine_fsm) 43 | ADD_SUBDIRECTORY(vending_machine_dp) 44 | ADD_SUBDIRECTORY(clk_div_by_3) 45 | ADD_SUBDIRECTORY(missing_duplicated_word) 46 | ADD_SUBDIRECTORY(multiply_by_21) 47 | ADD_SUBDIRECTORY(sorted_lists) 48 | ADD_SUBDIRECTORY(pipelined_add_constant) 49 | ADD_SUBDIRECTORY(zero_indices_slow) 50 | ADD_SUBDIRECTORY(zero_indices_fast) 51 | ADD_SUBDIRECTORY(count_zeros_32) 52 | ADD_SUBDIRECTORY(div_by_3) 53 | ADD_SUBDIRECTORY(fused_multiply_add) 54 | ADD_SUBDIRECTORY(fibonacci) 55 | ADD_SUBDIRECTORY(using_full_adders) 56 | -------------------------------------------------------------------------------- /rtl/clk_div_by_3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(clk_div_by_3) 29 | LIBPD_VIVADO(clk_div_by_3) 30 | -------------------------------------------------------------------------------- /rtl/clk_div_by_3/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | # Company 4 | 5 | # Problem 6 | 7 | Generate a circuit that divides a clock by some odd number (in this 8 | case 3). In particular, the duty-cycle of the clock must be 50%. 9 | 10 | # Notes 11 | -------------------------------------------------------------------------------- /rtl/clk_div_by_3/clk_div_by_3.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include "Vclk_div_by_3.h" 30 | 31 | #define PORTS(__func) \ 32 | __func(clk_div_3, bool) 33 | 34 | struct ClkDivBy3Tb : libtb::TopLevel 35 | { 36 | using UUT = Vclk_div_by_3; 37 | 38 | SC_HAS_PROCESS(ClkDivBy3Tb); 39 | ClkDivBy3Tb(sc_core::sc_module_name mn = "t") 40 | : libtb::TopLevel(mn) 41 | , uut_("uut") 42 | #define __construct_signals(__name, __type)\ 43 | , __name##_(#__name) 44 | PORTS(__construct_signals) 45 | #undef __construct_signals 46 | { 47 | uut_.clk(clk()); 48 | uut_.rst(rst()); 49 | #define __bind_signals(__name, __type) \ 50 | uut_.__name(__name##_); 51 | PORTS(__bind_signals) 52 | #undef __bind_signals 53 | } 54 | 55 | bool run_test() { 56 | LIBTB_REPORT_INFO("Stimulus starts..."); 57 | wait(1000, SC_NS); 58 | LIBTB_REPORT_INFO("Stimulus ends."); 59 | 60 | return true; 61 | } 62 | 63 | UUT uut_; 64 | #define __declare_signals(__name, __type) \ 65 | sc_core::sc_signal<__type> __name##_; 66 | PORTS(__declare_signals) 67 | #undef __declare_signals 68 | }; 69 | 70 | int sc_main(int argc, char **argv) 71 | { 72 | using namespace libtb; 73 | return LibTbSim(argc, argv).start(); 74 | } 75 | -------------------------------------------------------------------------------- /rtl/clk_div_by_3/clk_div_by_3.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | `define HAS_DETFF 1 29 | 30 | module clk_div_by_3 (input clk, input rst, output logic clk_div_3); 31 | 32 | 33 | logic [1:0] cnt_pos_r, cnt_pos_w; 34 | logic [1:0] cnt_neg_r, cnt_neg_w; 35 | 36 | 37 | logic cnt_pos_out_r; 38 | logic cnt_neg_out_r; 39 | `ifndef HAS_DETFF 40 | logic cnt_pos_out_w; 41 | logic cnt_neg_out_w; 42 | `endif 43 | 44 | always_comb 45 | begin 46 | cnt_pos_w = (cnt_pos_r == 'd2) ? 'b0 : cnt_pos_r + 'b1; 47 | cnt_neg_w = (cnt_neg_r == 'd2) ? 'b0 : cnt_neg_r + 'b1; 48 | end 49 | 50 | `ifdef HAS_DETFF 51 | // On FPGA flows, attempt to avoid glitches by flopping all combinatorial 52 | // logic in the path before clock generation. The presence of the OR is 53 | // undersirable but necessary. 54 | // 55 | always_comb clk_div_3 = cnt_pos_out_r | cnt_neg_out_r; 56 | `else 57 | // Flop output using Double-Edge Triggered FF to eliminate any possibility of 58 | // glitching on generated clock. NOTE: DETFF are unsupported on FPGA flows. 59 | // 60 | detff u_detff (.q(clk_div_3), .d_p(cnt_pos_w), .d_n(cnt_pos_n), .clk(clk)); 61 | `endif 62 | 63 | `ifdef HAS_DETFF 64 | always_ff @(posedge clk) 65 | cnt_pos_out_r <= (cnt_pos_w == '0); 66 | `endif 67 | 68 | `ifdef HAS_DETFF 69 | always_ff @(negedge clk) 70 | cnt_neg_out_r <= (cnt_neg_w == '0); 71 | `endif 72 | 73 | always_ff @(posedge clk or negedge rst) 74 | if (rst) 75 | cnt_pos_r <= '0; 76 | else 77 | cnt_pos_r <= cnt_pos_w; 78 | 79 | always_ff @(negedge clk or negedge rst) 80 | if (rst) 81 | cnt_neg_r <= 'd2; 82 | else 83 | cnt_neg_r <= cnt_neg_w; 84 | 85 | endmodule // clk_div_by_3 86 | -------------------------------------------------------------------------------- /rtl/clk_div_by_3/clk_div_by_3.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj clk_div_by_3 29 | 30 | create_project $prj -in_memory 31 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 32 | read_verilog @LIBPD_TECH_ROOT@/oddr.sv 33 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 34 | synth_design -name $prj -top $prj -verilog_define LIBPD=1 35 | opt_design 36 | place_design 37 | phys_opt_design 38 | route_design 39 | report_timing_summary 40 | -------------------------------------------------------------------------------- /rtl/clk_div_by_3/clk_div_by_3.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 10.00 -name CLK -waveform {0.000 0.500} [get_ports clk] 29 | create_generated_clock -divide_by 3 -source [get_ports clk] [get_ports clk_div_3] 30 | -------------------------------------------------------------------------------- /rtl/count_ones/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(count_ones) 29 | -------------------------------------------------------------------------------- /rtl/count_ones/README.md: -------------------------------------------------------------------------------- 1 | # Count Ones (population count) 2 | 3 | # Question 4 | 5 | Given an input logic vector, compute the number of set bits (the population 6 | count). 7 | 8 | # Commentary 9 | 10 | The population count function is very common in software, although perhaps more 11 | infrequent in logic design. Presented here is simply a question that may be 12 | poised to gain an appreciation of a candidates ability to write synthesizable 13 | Verilog and to understand the relative trade-offs between different solutions. 14 | 15 | Presented are three possible solutions to this problem. 16 | 17 | ## R0 - Gated Adders 18 | 19 | For each bit in the vector, a M = LOG2(A) + 1 adder is infered. The input to 20 | each adder is 'b1 gated upon the presence of a 1 in the current bit position of 21 | A. This solution is relatively trivial however scales poorly with N, M-bit 22 | adders infered. 23 | 24 | ## R1 - Look Up Table 25 | 26 | Instead, bit counts can be pre-computed for certain vector lengths. Although the 27 | approach remains similar to that of the prior solution, the number of adders can 28 | be reduced by W, where W is the width of the LUT. 29 | 30 | In the presented solution, LUT functionality is implemented using a 31 | combinatorial logic cone derived from A. It is not implemented as a specific ROM 32 | macro as may have been implied. 33 | 34 | ## R2 - Carry Save Adder (CSA) 35 | 36 | A Carry Save Adder (CSA) can be infered using 3:2 compressor blocks. Such blocks 37 | are commonly optimized in most standard cell libraries and are therefore area 38 | and performance efficient. The final population counter is derived by infering a 39 | final full-adder using the standard CSA approach. This solution, although the 40 | most area and performance efficient, is slightly harder to code, and cannot be 41 | easily parameterized for reuse. 42 | -------------------------------------------------------------------------------- /rtl/count_ones/count_ones.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include "Vcount_ones.h" 30 | 31 | #define PORTS(__func) \ 32 | __func(A, WordT) \ 33 | __func(fail, bool) 34 | 35 | const int TB_N = 10000; 36 | 37 | struct CountOnesTb : libtb::TopLevel 38 | { 39 | using WordT = uint32_t; 40 | SC_HAS_PROCESS(CountOnesTb); 41 | CountOnesTb(sc_core::sc_module_name mn = "t") 42 | : uut_("uut") 43 | { 44 | SC_METHOD(m_checker); 45 | sensitive << e_tb_sample(); 46 | dont_initialize(); 47 | 48 | #define __bind_ports(__name, __type) \ 49 | uut_.__name(__name##_); 50 | PORTS(__bind_ports) 51 | #undef __bind_ports 52 | } 53 | 54 | bool run_test() { 55 | 56 | A_ = 0; 57 | t_wait_reset_done(); 58 | 59 | for (int i = 0; i < TB_N; i++) { 60 | A_ = libtb::random(); 61 | t_wait_posedge_clk(); 62 | } 63 | return false; 64 | } 65 | 66 | void m_checker() { 67 | LIBTB_ASSERT_ERROR(!fail_); 68 | } 69 | 70 | #define __declare_signals(__name, __type) \ 71 | sc_core::sc_signal<__type> __name##_; 72 | PORTS(__declare_signals) 73 | #undef __declare_signals 74 | Vcount_ones uut_; 75 | }; 76 | 77 | 78 | int sc_main(int argc, char **argv) 79 | { 80 | using namespace libtb; 81 | return LibTbSim(argc, argv).start(); 82 | } 83 | -------------------------------------------------------------------------------- /rtl/count_ones/count_ones.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module count_ones (input [7:0] A, output logic fail); 29 | 30 | 31 | localparam int RESULT_W = $clog2(8) + 1; 32 | typedef logic [RESULT_W-1:0] result_t; 33 | 34 | logic [2:0] fail_v; 35 | 36 | result_t r0; 37 | always_comb 38 | begin : naive_PROC 39 | r0 = '0; 40 | for (int i = 0; i < 8; i++) 41 | r0 += ({RESULT_W{A[i]}} & 'b1); 42 | end 43 | 44 | function logic [2:0] LUT(input [3:0] in); 45 | case (in) 46 | 4'b0000: return 0; 47 | 4'b0001: return 1; 48 | 4'b0010: return 1; 49 | 4'b0011: return 2; 50 | 4'b0100: return 1; 51 | 4'b0101: return 2; 52 | 4'b0110: return 2; 53 | 4'b0111: return 3; 54 | 4'b1000: return 1; 55 | 4'b1001: return 2; 56 | 4'b1010: return 2; 57 | 4'b1011: return 3; 58 | 4'b1100: return 2; 59 | 4'b1101: return 3; 60 | 4'b1110: return 3; 61 | 4'b1111: return 4; 62 | default: return 0; 63 | endcase 64 | endfunction // LUT 65 | 66 | result_t r1; 67 | always_comb 68 | begin : lut4_PROC 69 | r1 = '0; 70 | for (int i = 0; i < 2; i++) 71 | r1 += LUT(A[(4 * i) +: 4]); 72 | end // block: lut4_PROC 73 | 74 | function [1:0] compress_3_to_2 (input [2:0] in); 75 | logic [1:0] r; 76 | r [0] = (^in); 77 | r [1] = (&in[1:0]) | (in[2] & (|in[1:0])); 78 | return r; 79 | endfunction 80 | 81 | result_t r2; 82 | logic unused_cout2; 83 | always_comb 84 | begin : csa_PROC 85 | logic [1:0] r0_0 = compress_3_to_2(A [2:0]); 86 | logic [1:0] r0_1 = compress_3_to_2(A [5:3]); 87 | logic [1:0] r0_2 = compress_3_to_2({1'b0, A [7:6]}); 88 | 89 | logic [1:0] r1_0 = compress_3_to_2({r0_2 [0], r0_1[0], r0_0 [0]}); 90 | logic [1:0] r1_1 = compress_3_to_2({r0_2 [1], r0_1[1], r0_0 [1]}); 91 | 92 | {unused_cout2, r2} = {1'b0, r1_1, 1'b0} + {2'b0, r1_0}; 93 | end // block: csa_PROC 94 | 95 | always_comb 96 | begin : combine_result_PROC 97 | 98 | result_t cnt = result_t'($countones(A)); 99 | 100 | fail_v = '0; 101 | fail_v [0] = (cnt != r0); 102 | fail_v [1] = (cnt != r1); 103 | fail_v [2] = (cnt != r2); 104 | 105 | fail = (|fail_v); 106 | 107 | end // block: combine_result_PROC 108 | 109 | endmodule // count_ones 110 | -------------------------------------------------------------------------------- /rtl/count_zeros_32/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(count_zeros_32) 29 | -------------------------------------------------------------------------------- /rtl/count_zeros_32/count_zeros_32.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include "Vcount_zeros_32.h" 33 | 34 | #define PORTS(__func) \ 35 | __func(pass, bool) \ 36 | __func(x, uint32_t) \ 37 | __func(valid_r, bool) \ 38 | __func(y, uint32_t) 39 | 40 | struct CountZeros32Tb : libtb::TopLevel 41 | { 42 | using UUT = Vcount_zeros_32; 43 | SC_HAS_PROCESS(CountZeros32Tb); 44 | CountZeros32Tb(sc_core::sc_module_name mn = "t") 45 | : uut_("uut") 46 | #define __construct_signal(__name, __type) \ 47 | , __name##_(#__name) 48 | PORTS(__construct_signal) 49 | #undef __construct_signal 50 | { 51 | SC_METHOD(m_checker); 52 | dont_initialize(); 53 | sensitive << e_tb_sample(); 54 | 55 | uut_.clk(clk()); 56 | uut_.rst(rst()); 57 | #define __bind_signal(__name, __type) \ 58 | uut_.__name(__name##_); 59 | PORTS(__bind_signal) 60 | #undef __bind_signals 61 | } 62 | bool run_test() 63 | { 64 | t_wait_reset_done(); 65 | LIBTB_REPORT_INFO("Stimulus starts..."); 66 | 67 | int n = 10000; 68 | while (n--) { 69 | pass_ = true; 70 | const uint32_t x = libtb::random(); 71 | const uint32_t cnt = bitset<32>(x).flip().count(); 72 | x_ = x; 73 | std::stringstream ss; 74 | ss << "Validating bitmap: " << bitset<32>(x).to_string() 75 | << " (ZERO=" << cnt << ")" 76 | ; 77 | LIBTB_REPORT_DEBUG(ss.str()); 78 | t_wait_posedge_clk(); 79 | expected_.push_back(cnt); 80 | } 81 | pass_ = false; 82 | 83 | t_wait_posedge_clk(10); 84 | LIBTB_REPORT_INFO("Stimulus ends.."); 85 | return false; 86 | } 87 | 88 | void m_checker() 89 | { 90 | if (valid_r_) { 91 | if (expected_.size() == 0) { 92 | std::stringstream ss; 93 | ss << "Unexpected result"; 94 | LIBTB_REPORT_ERROR(ss.str()); 95 | return; 96 | } 97 | 98 | const uint32_t actual = y_; 99 | const uint32_t expected = expected_.front(); expected_.pop_front(); 100 | if (actual != expected) { 101 | std::stringstream ss; 102 | ss << "Mismatch detected: " 103 | << " Actual: " << actual 104 | << " Expected: " << expected; 105 | LIBTB_REPORT_ERROR(ss.str()); 106 | } else { 107 | std::stringstream ss; 108 | ss << "Validated cnt=" << actual; 109 | LIBTB_REPORT_DEBUG(ss.str()); 110 | } 111 | } 112 | } 113 | std::deque expected_; 114 | #define __declare_signal(__name, __type) \ 115 | sc_core::sc_signal<__type> __name##_; 116 | PORTS(__declare_signal) 117 | #undef __declare_signal 118 | UUT uut_; 119 | }; 120 | 121 | int sc_main(int argc, char **argv) 122 | { 123 | using namespace libtb; 124 | return LibTbSim(argc, argv).start(); 125 | } 126 | -------------------------------------------------------------------------------- /rtl/detect_sequence/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(detect_sequence) 29 | LIBPD_VIVADO(detect_sequence) 30 | -------------------------------------------------------------------------------- /rtl/detect_sequence/detect_sequence.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016-17, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include "Vdetect_sequence.h" 30 | 31 | #define PORTS(__func) \ 32 | __func(in, bool) \ 33 | __func(fail_r, bool) 34 | 35 | class DetectSequenceTb : libtb::TopLevel 36 | { 37 | public: 38 | SC_HAS_PROCESS(DetectSequenceTb); 39 | DetectSequenceTb(sc_core::sc_module_name mn = "t") 40 | : uut_("uut") 41 | #define __declare_signals(__name, __type) \ 42 | , __name##_(#__name) 43 | PORTS(__declare_signals) 44 | #undef __declare_signals 45 | { 46 | SC_METHOD(m_checker); 47 | dont_initialize(); 48 | sensitive << e_tb_sample(); 49 | 50 | uut_.clk(clk()); 51 | uut_.rst(rst()); 52 | #define __bind_signals(__name, __type) \ 53 | uut_.__name(__name##_); 54 | PORTS(__bind_signals) 55 | #undef __bind_signals 56 | 57 | wave_on("foo.vcd", uut_); 58 | } 59 | 60 | bool run_test() 61 | { 62 | LIBTB_REPORT_INFO("Stimulus starts...."); 63 | for (int i = 0; i < N; i++) { 64 | in_ = (libtb::random_integer_in_range(100) < 40); 65 | t_wait_posedge_clk(); 66 | } 67 | LIBTB_REPORT_INFO("Stimulus ends."); 68 | return false; 69 | } 70 | 71 | void m_checker() { 72 | LIBTB_ASSERT_ERROR(!fail_r_); 73 | } 74 | 75 | const int N{10000}; 76 | #define __declare_signals(__name, __type) \ 77 | sc_core::sc_signal<__type> __name##_; 78 | PORTS(__declare_signals) 79 | #undef __declare_signals 80 | Vdetect_sequence uut_; 81 | }; 82 | 83 | int sc_main (int argc, char **argv) 84 | { 85 | using namespace libtb; 86 | DetectSequenceTb t; 87 | LibTbContext::init(argc, argv); 88 | return LibTbContext::start(); 89 | } 90 | -------------------------------------------------------------------------------- /rtl/detect_sequence/detect_sequence.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj detect_sequence 29 | create_project latency -in_memory 30 | 31 | # Source 32 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 33 | 34 | # XDC 35 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 36 | 37 | # PD FLOW 38 | synth_design -name $prj -top $prj -include_dirs {@LIBPD_INCLUDE_DIRS@} 39 | opt_design 40 | place_design 41 | phys_opt_design 42 | route_design 43 | report_timing_summary 44 | -------------------------------------------------------------------------------- /rtl/detect_sequence/detect_sequence.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 10.0 -name CLK [get_ports clk] 29 | 30 | # HACK: resolve hold violation on in -> shift_w [0].D (i.e. a shift register 31 | # using an input port). This exists because PIN mappings are - purposefully - 32 | # left undefined for simplicity. 33 | # 34 | set_input_delay -clock CLK 5.0 [all_inputs] 35 | set_output_delay -clock CLK 1.0 [all_outputs] 36 | -------------------------------------------------------------------------------- /rtl/div_by_3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(div_by_3) 29 | -------------------------------------------------------------------------------- /rtl/fibonacci/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(fibonacci) 29 | -------------------------------------------------------------------------------- /rtl/fibonacci/fibonacci.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include 30 | #include "Vfibonacci.h" 31 | 32 | #define PORTS(__func) \ 33 | __func(y, uint32_t) 34 | 35 | struct FibonacciTb : libtb::TopLevel 36 | { 37 | using UUT = Vfibonacci; 38 | SC_HAS_PROCESS(FibonacciTb); 39 | FibonacciTb(sc_core::sc_module_name mn = "t") 40 | : uut_("uut") 41 | #define __construct_signal(__name, __type) \ 42 | , __name##_(#__name) 43 | PORTS(__construct_signal) 44 | #undef __construct_signal 45 | { 46 | SC_METHOD(m_checker); 47 | dont_initialize(); 48 | sensitive << e_reset_done(); 49 | 50 | uut_.clk(clk()); 51 | uut_.rst(rst()); 52 | #define __bind_signal(__name, __type) \ 53 | uut_.__name(__name##_); 54 | PORTS(__bind_signal) 55 | #undef __bind_signals 56 | } 57 | bool run_test() { 58 | wait(1, SC_US); 59 | return true; 60 | } 61 | void m_checker() { 62 | const uint32_t expected = step_fibonacci(); 63 | const uint32_t actual = y_; 64 | if (actual != expected) { 65 | std::stringstream ss; 66 | ss << "Mismatch: " 67 | << " actual=" << actual 68 | << " expected=" << expected 69 | ; 70 | LIBTB_REPORT_ERROR(ss.str()); 71 | } else { 72 | std::stringstream ss; 73 | ss << "Validated " << actual; 74 | LIBTB_REPORT_DEBUG(ss.str()); 75 | } 76 | next_trigger(clk().posedge_event()); 77 | } 78 | int step_fibonacci() { 79 | const int ret = round_ ? f1_ : f0_; 80 | (round_ ? f1_ : f0_) = f0_ + f1_; 81 | round_ = !round_; 82 | return ret; 83 | } 84 | int f0_{1}, f1_{1}; 85 | bool round_{false}; 86 | #define __declare_signal(__name, __type) \ 87 | sc_core::sc_signal<__type> __name##_; 88 | PORTS(__declare_signal) 89 | #undef __declare_signal 90 | UUT uut_; 91 | }; 92 | 93 | int sc_main (int argc, char **argv) 94 | { 95 | using namespace libtb; 96 | return LibTbSim(argc, argv).start(); 97 | } 98 | -------------------------------------------------------------------------------- /rtl/fibonacci/fibonacci.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module fibonacci ( 29 | 30 | //======================================================================== // 31 | // // 32 | // Misc. // 33 | // // 34 | //======================================================================== // 35 | 36 | input clk 37 | , input rst 38 | 39 | //======================================================================== // 40 | // // 41 | // Out // 42 | // // 43 | //======================================================================== // 44 | 45 | , output logic [31:0] y 46 | 47 | ); 48 | 49 | typedef logic [31:0] cnt_t; 50 | cnt_t x_0_r, x_1_r, x_w; 51 | logic x_0_en, x_1_en; 52 | logic sel_r, sel_w; 53 | logic UNUSED_cout; 54 | 55 | // ------------------------------------------------------------------------ // 56 | // 57 | always_comb 58 | begin : upt_PROC 59 | 60 | // 61 | sel_w = (~sel_r); 62 | 63 | // 64 | y = sel_r ? x_1_r : x_0_r; 65 | 66 | // 67 | {UNUSED_cout, x_w} = x_0_r + x_1_r; 68 | 69 | // 70 | x_0_en = (~sel_r); 71 | x_1_en = ( sel_r); 72 | 73 | end // block: upt_PROC 74 | 75 | // ------------------------------------------------------------------------ // 76 | // 77 | always_ff @(posedge clk) 78 | if (rst) 79 | sel_r <= '0; 80 | else 81 | sel_r <= sel_w; 82 | 83 | // ------------------------------------------------------------------------ // 84 | // 85 | always_ff @(posedge clk) 86 | if (rst) begin 87 | x_0_r <= 'b1; 88 | x_1_r <= 'b1; 89 | end else begin 90 | if (x_0_en) 91 | x_0_r <= x_w; 92 | if (x_1_en) 93 | x_1_r <= x_w; 94 | end 95 | 96 | endmodule // fibonacci 97 | -------------------------------------------------------------------------------- /rtl/fifo_async/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== ## 2 | ## Copyright (c) 2017, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== ## 27 | 28 | EMIT_ANSWER(fifo_async_tb) 29 | LIBPD_VIVADO(fifo_async) 30 | -------------------------------------------------------------------------------- /rtl/fifo_async/README.md: -------------------------------------------------------------------------------- 1 | # Asynchronous FIFO 2 | 3 | # Question 4 | 5 | Design (and constrain) a FIFO/Queue module where the PUSH interface is 6 | asynchronous to the POP interface. 7 | 8 | # Answer 9 | 10 | The design of asynchronous FIFO is well documented. Read-/Write- pointers are 11 | communicated across the clock boundary using GRAY encoding. GRAY encoding 12 | presents the key advantage that upon increment or decrement, at most one bit 13 | shall change. By result of this, downstream resynchronization logic shall 14 | capture either the new value or the old value. In contrast, in a traditional 15 | binary scheme, the old, the new and any intermediate states may be captured. 16 | 17 | The token gotcha in this example is the infamous "Qualcomm bug". GRAY pointers 18 | are computed as a combinatorial function of the standard binary pointers. After 19 | looking at waveforms in VCS, it is easy to forget that such combinatorial logic 20 | does not compute its result at one precise instand in time. All logic cones, 21 | even GRAY encoded logic, require some time to compute their result. Before that 22 | point, the result is undefined. Here, the term undefined also means 23 | wrong. Applying a standard synchronizing approach to the GRAY cone can result in 24 | invalid values. This is by consequence of the differing settling times and skew 25 | at each GRAY wire. The solution is to FLOP the computed GRAY code using the 26 | LAUNCH clock before it is passed to the CAPTURING clocks resynchronizer. 27 | 28 | ## NOTE: 29 | Apparently, Qualcomm had to respin a chip after the additional GRAY flop was 30 | omitted from a asynchronous FIFO used throughout the chip. 31 | -------------------------------------------------------------------------------- /rtl/fifo_async/fifo_async.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj fifo_async 29 | create_project latency -in_memory 30 | 31 | # Source 32 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 33 | read_verilog @LIBV_ROOT@/mem_egress_pipe.sv 34 | read_verilog @LIBPD_TECH_ROOT@/dpsram.sv 35 | read_verilog @LIBPD_TECH_ROOT@/sync_ff.sv 36 | 37 | # XDC 38 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 39 | 40 | # PD FLOW 41 | synth_design -name $prj -top $prj -include_dirs {@LIBPD_INCLUDE_DIRS@} 42 | opt_design 43 | place_design 44 | phys_opt_design 45 | route_design 46 | report_timing_summary 47 | report_cdc 48 | -------------------------------------------------------------------------------- /rtl/fifo_async/fifo_async.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | # Create clocks with some arbitrary phase. 29 | # 30 | create_clock -period 10.00 -name WCLK -waveform {0.000 5.000} [get_ports wclk] 31 | create_clock -period 13.00 -name RCLK -waveform {0.000 8.000} [get_ports rclk] 32 | 33 | set_input_delay -clock WCLK 1.0 [get_ports push] 34 | set_input_delay -clock WCLK 1.0 [get_ports push_data] 35 | set_input_delay -clock RCLK 1.0 [get_ports pop] 36 | set_output_delay -clock RCLK 1.0 [get_ports pop_data] 37 | set_output_delay -clock RCLK 1.0 [get_ports empty_r] 38 | set_output_delay -clock WCLK 1.0 [get_ports full_r] 39 | 40 | # Create false-path across synchronization boundary to disable timing 41 | # analysis. 42 | # 43 | set_clock_groups -asynchronous -group {WCLK} -group {RCLK} 44 | -------------------------------------------------------------------------------- /rtl/fifo_async/fifo_async_tb.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include "fifo_async_tb.h" 29 | #include 30 | 31 | fifo_async_tb::fifo_async_tb() : libtb::TopLevel("t"), uut_("uut") { 32 | SC_METHOD(m_checker); 33 | sensitive << e_reset_done(); 34 | dont_initialize(); 35 | } 36 | fifo_async_tb::~fifo_async_tb() {} 37 | 38 | void fifo_async_tb::bind_rtl() { 39 | uut_.rclk(clk()); 40 | uut_.rrst(rst()); 41 | #define __bind_signals(__name, __type) uut_.__name(__name##_); 42 | FIFO_ASYNC_PORTS(__bind_signals) 43 | #undef __bind_signals 44 | } 45 | 46 | void fifo_async_tb::pop_idle() { pop_ = false; } 47 | 48 | void fifo_async_tb::m_checker() { 49 | pop_idle(); 50 | 51 | if (!empty_r_) { 52 | pop_ = true; 53 | if (queue_.size() == 0) { 54 | // TODO: Error raised pre-reset. Modify libtb to hold-off e_reset_done 55 | // LIBTB_REPORT_ERROR("Pop not predicted"); 56 | return; 57 | } 58 | const WordT actual = pop_data_; 59 | const WordT expected = queue_.front(); 60 | queue_.pop_front(); 61 | 62 | if (expected != actual) { 63 | std::stringstream ss; 64 | ss << "Actual: " << std::hex << actual << " " 65 | << "Expected: " << std::hex << expected; 66 | LIBTB_REPORT_ERROR(ss.str()); 67 | } 68 | } 69 | next_trigger(e_tb_sample()); 70 | } 71 | 72 | 73 | struct test_0 : public fifo_async_tb { 74 | SC_HAS_PROCESS(test_0); 75 | test_0() { bind_rtl(); } 76 | virtual ~test_0() {} 77 | bool run_test() { 78 | LIBTB_REPORT_INFO("Stimulus begins"); 79 | b_reset(); 80 | 81 | unsigned N = 10000; 82 | while (N--) b_push(libtb::random()); 83 | 84 | LIBTB_REPORT_INFO("Stimulus ends"); 85 | return true; 86 | } 87 | void b_reset() { 88 | wrst_ = false; 89 | wait(wclk_.posedge_event()); 90 | wrst_ = true; 91 | wait(wclk_.posedge_event()); 92 | wrst_ = false; 93 | } 94 | virtual void bind_rtl() { 95 | uut_.wclk(wclk_); 96 | uut_.wrst(wrst_); 97 | fifo_async_tb::bind_rtl(); 98 | } 99 | 100 | void b_push(WordT w) { 101 | push_ = true; 102 | push_data_ = w; 103 | queue_.push_back(w); 104 | wait(wclk_.posedge_event()); 105 | } 106 | 107 | sc_core::sc_clock wclk_; 108 | sc_core::sc_signal wrst_; 109 | }; 110 | 111 | int sc_main(int argc, char **argv) { 112 | using namespace libtb; 113 | test_0 t; 114 | LibTbContext::init(argc, argv); 115 | return LibTbContext::start(); 116 | } 117 | -------------------------------------------------------------------------------- /rtl/fifo_async/fifo_async_tb.h: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include 30 | #include "Vfifo_async_tb.h" 31 | #include "fifo_async_tb_ports.h" 32 | 33 | using WordT = vluint32_t; 34 | 35 | struct fifo_async_tb : public libtb::TopLevel { 36 | SC_HAS_PROCESS(fifo_async_tb); 37 | fifo_async_tb(); 38 | virtual ~fifo_async_tb(); 39 | 40 | protected: 41 | void m_checker(); 42 | void pop_idle(); 43 | virtual void bind_rtl(); 44 | Vfifo_async_tb uut_; 45 | #define __declare_signal(__name, __type) \ 46 | sc_core::sc_signal<__type> __name##_; 47 | FIFO_ASYNC_PORTS(__declare_signal) 48 | #undef __declare_signal 49 | std::deque queue_; 50 | }; 51 | -------------------------------------------------------------------------------- /rtl/fifo_async/fifo_async_tb.sv: -------------------------------------------------------------------------------- 1 | // -*-verilog-*- 2 | //========================================================================== // 3 | // Copyright (c) 2017, Stephen Henry 4 | // All rights reserved. 5 | // 6 | // Redistribution and use in source and binary forms, with or without 7 | // modification, are permitted provided that the following conditions are met: 8 | // 9 | // * Redistributions of source code must retain the above copyright notice, this 10 | // list of conditions and the following disclaimer. 11 | // 12 | // * Redistributions in binary form must reproduce the above copyright notice, 13 | // this list of conditions and the following disclaimer in the documentation 14 | // and/or other materials provided with the distribution. 15 | // 16 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 | // POSSIBILITY OF SUCH DAMAGE. 27 | //========================================================================== // 28 | 29 | module fifo_async_tb (/*AUTOARG*/ 30 | // Outputs 31 | pop_data, full_r, empty_r, 32 | // Inputs 33 | wrst, wclk, rrst, rclk, push_data, push, pop 34 | ); 35 | `define __OVERRIDE_CLK wclk 36 | `include "libtb_tb_top_inc.vh" 37 | /*AUTOINPUT*/ 38 | // Beginning of automatic inputs (from unused autoinst inputs) 39 | input pop; // To u_fifo_async of fifo_async.v 40 | input push; // To u_fifo_async of fifo_async.v 41 | input [31:0] push_data; // To u_fifo_async of fifo_async.v 42 | input rclk; // To u_fifo_async of fifo_async.v 43 | input rrst; // To u_fifo_async of fifo_async.v 44 | input wclk; // To u_fifo_async of fifo_async.v 45 | input wrst; // To u_fifo_async of fifo_async.v 46 | // End of automatics 47 | /*AUTOOUTPUT*/ 48 | // Beginning of automatic outputs (from unused autoinst outputs) 49 | output logic empty_r; // From u_fifo_async of fifo_async.v 50 | output logic full_r; // From u_fifo_async of fifo_async.v 51 | output logic [31:0] pop_data; // From u_fifo_async of fifo_async.v 52 | // End of automatics 53 | fifo_async #( 54 | // Parameters 55 | .W (32), 56 | .N (32) 57 | /*AUTOINSTPARAM*/) u_fifo_async 58 | (/*AUTOINST*/ 59 | // Outputs 60 | .pop_data (pop_data[31:0]), 61 | .empty_r (empty_r), 62 | .full_r (full_r), 63 | // Inputs 64 | .wclk (wclk), 65 | .wrst (wrst), 66 | .rclk (rclk), 67 | .rrst (rrst), 68 | .push (push), 69 | .push_data (push_data[31:0]), 70 | .pop (pop)); 71 | endmodule // fifo_async 72 | -------------------------------------------------------------------------------- /rtl/fifo_async/fifo_async_tb_ports.h: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #define FIFO_ASYNC_PORTS(__func) \ 29 | __func(push, bool) \ 30 | __func(push_data, WordT) \ 31 | __func(pop, bool) \ 32 | __func(pop_data, WordT) \ 33 | __func(empty_r, bool) \ 34 | __func(full_r, bool) 35 | -------------------------------------------------------------------------------- /rtl/fifo_multi_push/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(fifo_multi_push) 29 | LIBPD_VIVADO(fifo_multi_push) 30 | -------------------------------------------------------------------------------- /rtl/fifo_multi_push/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | Unknown 4 | 5 | # Company 6 | 7 | Unknown 8 | 9 | # Problem Statement 10 | 11 | Queue data structures are well-known. Construct a N-Queue data 12 | structure that can consume between 0 and N push operations per cycle 13 | and consume between 0 and 1 pop operations per cycle. Ordering between 14 | push operations must be maintained as in a standard 1-input queue. 15 | 16 | # Commentary 17 | 18 | N/A 19 | -------------------------------------------------------------------------------- /rtl/fifo_multi_push/fifo_multi_push.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj fifo_multi_push 29 | 30 | create_project $prj -in_memory 31 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 32 | read_verilog @LIBV_ROOT@/popcnt.sv 33 | read_verilog @LIBV_ROOT@/rotate.sv 34 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 35 | synth_design -name $prj -top $prj -verilog_define LIBPD=1 36 | opt_design 37 | place_design 38 | phys_opt_design 39 | route_design 40 | report_timing_summary 41 | -------------------------------------------------------------------------------- /rtl/fifo_multi_push/fifo_multi_push.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 20.00 -name CLK -waveform {0.000 0.500} [get_ports clk] 29 | set_input_delay -clock CLK 5.0 [all_inputs] 30 | set_output_delay -clock CLK 5.0 [all_outputs] 31 | -------------------------------------------------------------------------------- /rtl/fifo_n/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(fifo_n) 29 | LIBPD_VIVADO(fifo_n) 30 | -------------------------------------------------------------------------------- /rtl/fifo_n/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | Unknown 4 | 5 | # Company 6 | 7 | Unknown 8 | 9 | # Problem Statement 10 | 11 | From a dual-ported synchronous SRAM macro, carve N-statically sized 12 | FIFO/Queue data structures. Each data structure must support 13 | simultaneous push/pop operation, as in a tradition queue. 14 | 15 | # Commentary 16 | 17 | The N-Context (Virtual-Queue) problem is a logical extension of the 18 | traditional FIFO design which the additional qualification that the 19 | address into the RAM are prepended by the Context ID. 20 | -------------------------------------------------------------------------------- /rtl/fifo_n/fifo_n.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj fifo_n 29 | 30 | create_project $prj -in_memory 31 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 32 | read_verilog @LIBPD_TECH_ROOT@/dpsrams.sv 33 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 34 | synth_design -name $prj -top $prj -verilog_define LIBPD=1 35 | opt_design 36 | place_design 37 | phys_opt_design 38 | route_design 39 | report_timing_summary 40 | -------------------------------------------------------------------------------- /rtl/fifo_n/fifo_n.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 20.00 -name CLK -waveform {0.000 0.500} [get_ports clk] 29 | set_input_delay -clock CLK 5.0 [all_inputs] 30 | set_output_delay -clock CLK 5.0 [all_outputs] 31 | -------------------------------------------------------------------------------- /rtl/fifo_ptr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(fifo_ptr) 29 | 30 | -------------------------------------------------------------------------------- /rtl/fifo_sr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(fifo_sr) 29 | #LIBPD_VIVADO(fifo_sr) 30 | -------------------------------------------------------------------------------- /rtl/fifo_sr/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | # Company 4 | 5 | N/A 6 | 7 | # Problem Statement 8 | 9 | Construct a N-depth Queue of W-width using a shift-register 10 | structure. Pop operations may be asynchronous to the pop strobe. The 11 | structure must be power efficient. 12 | 13 | # Commentary 14 | 15 | A queue can be trivially implemented as a shift register. On each push 16 | operation, all state in registers is shifted one step. Although 17 | trivial, the unnecessary data movement results in increased power 18 | consumption. Instead, the same effect can be realized by using a 1h 19 | read/write strobe pointer into a static flop array. Clocks to the flop 20 | array are gated for except when being written. 21 | -------------------------------------------------------------------------------- /rtl/fused_multiply_add/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(fused_multiply_add) 29 | -------------------------------------------------------------------------------- /rtl/gates_from_MUX2X1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(gates_from_MUX2X1) 29 | -------------------------------------------------------------------------------- /rtl/gates_from_MUX2X1/README.md: -------------------------------------------------------------------------------- 1 | # gates_from_MUX2X1 2 | 3 | # Question 4 | 5 | Using just a simple 2-input multiplexor, construct equivalent 2-input INV, AND, 6 | OR and XOR gates. 7 | 8 | # Commentary 9 | 10 | The question is fairly straightforward considering that it is also possible to 11 | tie MUX inputs to VDD and GND. 12 | 13 | * INV 14 | 15 | Mux selects between inputs 0 and 1. Input 0 is tied to true; Input 1 is tied to 16 | false. The MUX selection line acts as the input to the INV. 17 | 18 | * AND 19 | 20 | Similarly, to calculate AB, A is set as the MUX select line, Input 1 is set a 21 | B. The output of the MUX is true only when both A and B are true. 22 | 23 | * OR 24 | 25 | Extending the AND solution: Y is derive as the output of the MUX gate. MUX 26 | select is driven by B. Input 0 is driven to A, Input 1 is driven to B. 27 | 28 | * XOR 29 | 30 | The XOR gate cannot be computed directly from a single MUX gate. Instead, it 31 | must be computed from the previously derived GATE primitives using the familiar 32 | formula for XOR: A!B + !AB. 33 | -------------------------------------------------------------------------------- /rtl/gates_from_MUX2X1/gates_from_MUX2X1.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include "Vgates_from_MUX2X1.h" 30 | 31 | #define PORTS(__func) \ 32 | __func(a, bool) \ 33 | __func(b, bool) \ 34 | __func(fail, bool) 35 | 36 | struct GatesFromMux2X1Tb : libtb::TopLevel 37 | { 38 | SC_HAS_PROCESS(GatesFromMux2X1Tb); 39 | GatesFromMux2X1Tb(sc_core::sc_module_name mn = "t") 40 | : uut_("uut") { 41 | 42 | SC_METHOD(m_checker); 43 | sensitive << e_tb_sample(); 44 | dont_initialize(); 45 | 46 | #define __bind_ports(__name, __type) \ 47 | uut_.__name(__name##_); 48 | PORTS(__bind_ports) 49 | #undef __bind_ports 50 | } 51 | 52 | bool run_test() { 53 | a_ = false; 54 | b_ = false; 55 | t_wait_reset_done(); 56 | 57 | // 58 | a_ = false; 59 | b_ = false; 60 | t_wait_posedge_clk(); 61 | 62 | // 63 | a_ = true; 64 | b_ = false; 65 | t_wait_posedge_clk(); 66 | 67 | // 68 | a_ = false; 69 | b_ = true; 70 | t_wait_posedge_clk(); 71 | 72 | // 73 | a_ = true; 74 | b_ = true; 75 | t_wait_posedge_clk(); 76 | 77 | return false; 78 | } 79 | 80 | void m_checker() { 81 | LIBTB_ASSERT_ERROR(!fail_); 82 | } 83 | 84 | #define __define_signals(__name, __type) \ 85 | sc_core::sc_signal<__type> __name##_; 86 | PORTS(__define_signals) 87 | #undef __define_signals 88 | Vgates_from_MUX2X1 uut_; 89 | }; 90 | 91 | int sc_main(int argc, char **argv) 92 | { 93 | using namespace libtb; 94 | 95 | return LibTbSim(argc, argv).start(); 96 | } 97 | -------------------------------------------------------------------------------- /rtl/gates_from_MUX2X1/gates_from_MUX2X1.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module gates_from_MUX2X1 ( input a, input b, output logic fail ); 29 | 30 | logic [3:0] fail_v; 31 | 32 | logic y_inv_expected; 33 | logic y_and_expected; 34 | logic y_or_expected; 35 | logic y_xor_expected; 36 | 37 | logic y_inv_actual; 38 | logic y_and_actual; 39 | logic y_or_actual; 40 | logic y_xor_actual; 41 | 42 | `define MUX2X1(__a, __b, __sel) ((~(__sel) & (__a)) | ((__sel) & (__b))) 43 | 44 | always_comb 45 | begin : gates_PROC 46 | 47 | fail_v = '0; 48 | 49 | // inv: Y = (!A) 50 | y_inv_expected = (~a); 51 | y_inv_actual = `MUX2X1(1, 0, a); 52 | fail_v[0] = (y_inv_expected ^ y_inv_actual); 53 | 54 | // and: Y = AB 55 | y_and_expected = (a & b); 56 | y_and_actual = `MUX2X1(0, a, b); 57 | fail_v[1] = (y_and_expected ^ y_and_actual); 58 | 59 | // or: Y = A + B 60 | y_or_expected = (a | b); 61 | y_or_actual = `MUX2X1(a, 1, b); 62 | fail_v[2] = (y_or_expected ^ y_or_actual); 63 | 64 | // xor: Y = A!B + !AB 65 | y_xor_expected = (a ^ b); 66 | 67 | begin : xor_BLOCK 68 | logic a_inv = `MUX2X1(1, 0, a); 69 | logic b_inv = `MUX2X1(1, 0, b); 70 | 71 | logic a_nb_and = `MUX2X1(0, a, b_inv); 72 | logic na_b_and = `MUX2X1(0, b, a_inv); 73 | 74 | y_xor_actual = `MUX2X1(na_b_and, 1, a_nb_and); 75 | end 76 | fail_v[3] = (y_xor_expected ^ y_xor_actual); 77 | 78 | end // block: gates_PROC 79 | `undef MUX2X1 80 | 81 | always_comb fail = (|fail_v); 82 | 83 | endmodule // gates_from_MUX2X1 84 | -------------------------------------------------------------------------------- /rtl/increment/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(increment) 29 | -------------------------------------------------------------------------------- /rtl/increment/README.md: -------------------------------------------------------------------------------- 1 | # Increment 2 | 3 | # Question 4 | 5 | Derive code to detect the first 0 in an input vector and to invert it, and all 6 | preceding bits. What function does the logic perform? 7 | 8 | # Commentary 9 | 10 | Code to compute this function is presented. 11 | 12 | It turns out, non-obviously, that this function actually computes an 13 | increment-by-1 function on the input vector. It remains up for debate 14 | whether the advantage that such logic would have over the inference of 15 | a traditional full-adder. Additionally, the complexity of the 16 | resultant code obscures the fact that it computes a trivially and 17 | well-known function. In this case, it would almost always be advisible 18 | for the logic designer to write a simple increment function and all 19 | synthesize to infer the most efficient structure at the gate-level. 20 | -------------------------------------------------------------------------------- /rtl/increment/increment.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include "Vincrement.h" 30 | 31 | #define PORTS(__func) \ 32 | __func(A, WordT) \ 33 | __func(fail, bool) 34 | 35 | const int TB_N = 10000; 36 | 37 | struct IncrementTb : libtb::TopLevel 38 | { 39 | using WordT = uint32_t; 40 | 41 | SC_HAS_PROCESS(IncrementTb); 42 | IncrementTb(sc_core::sc_module_name mn = "t") 43 | : uut_("uut") 44 | { 45 | SC_METHOD(m_checker); 46 | sensitive << e_tb_sample(); 47 | dont_initialize(); 48 | 49 | #define __bind_ports(__name, __type) \ 50 | uut_.__name(__name##_); 51 | PORTS(__bind_ports) 52 | #undef __bind_ports 53 | } 54 | 55 | bool run_test() { 56 | 57 | A_ = 0; 58 | t_wait_reset_done(); 59 | 60 | for (int i = 0; i < TB_N; i++) { 61 | A_ = libtb::random(); 62 | t_wait_posedge_clk(); 63 | } 64 | 65 | return false; 66 | } 67 | 68 | void m_checker() { 69 | LIBTB_ASSERT_ERROR(!fail_); 70 | } 71 | 72 | #define __declare_signals(__name, __type) \ 73 | sc_core::sc_signal<__type> __name##_; 74 | PORTS(__declare_signals) 75 | #undef __declare_signals 76 | 77 | Vincrement uut_; 78 | }; 79 | 80 | int sc_main(int argc, char **argv) 81 | { 82 | using namespace libtb; 83 | 84 | return LibTbSim(argc, argv).start(); 85 | } 86 | -------------------------------------------------------------------------------- /rtl/increment/increment.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module increment #(parameter int W = 32) (input [W-1:0] A, output logic fail); 29 | 30 | typedef logic [W-1:0] w_t; 31 | 32 | // 33 | w_t y_naive; 34 | logic unused_co; 35 | // 36 | w_t y_optimal; 37 | 38 | // Function to compute a 1hot mask denoting the position of the right-most 0 39 | // in an input vector. 40 | // 41 | function w_t ffs0 (input w_t x); 42 | w_t ret = '0; 43 | for (int i = W - 1; i >= 0; i--) 44 | if (x[i] == 0) 45 | ret = (1 << i); 46 | return ret; 47 | endfunction // ffs0 48 | 49 | // Function to derive the inclusive lsb-oriented mask from an input 1hot mask. 50 | // 51 | function w_t inclusive_mask(input w_t x); 52 | w_t ret = '0; 53 | logic bit_set = '0; 54 | for (int i = W - 1; i >= 0; i--) begin 55 | bit_set |= x[i]; 56 | ret[i] = bit_set; 57 | end 58 | return ret; 59 | endfunction 60 | 61 | // 62 | always_comb 63 | {unused_co, y_naive} = (A + 'b1); 64 | 65 | // 66 | always_comb 67 | begin : increment_PROC 68 | 69 | w_t first_0_1hot_vec = ffs0(A); 70 | 71 | w_t first_0_and_mask = inclusive_mask(first_0_1hot_vec); 72 | 73 | y_optimal = (A ^ first_0_and_mask); 74 | 75 | end // block: increment_PROC 76 | 77 | // 78 | always_comb fail = (y_naive != y_optimal); 79 | 80 | endmodule // increment 81 | -------------------------------------------------------------------------------- /rtl/latency/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(latency) 29 | LIBPD_VIVADO(latency) 30 | -------------------------------------------------------------------------------- /rtl/latency/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | # Company 4 | 5 | Apple 6 | 7 | # Problem Statement 8 | 9 | Commands are issued to some agent. Reponses return from the agent after some 10 | undefined latency. Derive logic that will compute the average latency 11 | experienced by each command. Commands cannot be TAGGED and shall be considered 12 | to be opaque to the logic. Additionally, the number of commands issued is 13 | unknown and unbounded. 14 | 15 | # Commentary 16 | 17 | This question is without doubt non-trivial to someone without prior knowledge of 18 | the solution, however it is a common question asked by some of the larger 19 | companies, particularlly Apple. 20 | 21 | It turns out, that the latency can be computed relatively trivially using only 22 | three counters. 23 | 24 | * At the start of the interval of interest, the counters are reset to 0. 25 | * Counter 1 tracks the total number of commands issued to the agent over the 26 | interval of interest. This is computed by simply incrementing the counter each 27 | time a command is issued. 28 | * Counter 2 tracks the total number of commands that are presently inflight at 29 | any point in time. The counter is incremented on issue, and decremented on 30 | retirement/committal. 31 | * Counter 3 tracks the aggregate latency of all commands. The counter is 32 | incremented on each cycle by the current count retained by Counter 2. 33 | * Average latency is computed by dividing the value of Counter 3 by Counter 1 34 | upon completion of the interval of interest. 35 | 36 | ## Notes: 37 | 38 | Division is a non-trivial and costly function to perform in hardware. Therefore, 39 | the majority of implementations simply expose Counter 1 and Counter 3 as 40 | software-visible registers and the latency computed in software. 41 | 42 | The key to understanding the solution is with Counter 3. It is impossible to 43 | compute the latency of any single command in the system. Instead, one must 44 | compute the overall latency experience by ALL commands in the interval of 45 | interest. From this, the average latency can be computed trivially. 46 | -------------------------------------------------------------------------------- /rtl/latency/latency.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj latency 29 | 30 | create_project $prj -in_memory 31 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 32 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 33 | synth_design -name $prj -top $prj -verilog_define LIBPD=1 34 | opt_design 35 | place_design 36 | phys_opt_design 37 | route_design 38 | report_timing_summary 39 | -------------------------------------------------------------------------------- /rtl/latency/latency.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 10.00 -name CLK -waveform {0.000 0.500} [get_ports clk] 29 | set_input_delay -clock CLK 5.0 [all_inputs] 30 | set_output_delay -clock CLK 5.0 [all_outputs] 31 | 32 | -------------------------------------------------------------------------------- /rtl/mcp_formulation/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(mcp_formulation) 29 | -------------------------------------------------------------------------------- /rtl/missing_duplicated_word/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(missing_duplicated_word) 29 | -------------------------------------------------------------------------------- /rtl/missing_duplicated_word/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | # Company 4 | 5 | Google 6 | 7 | # Problem 8 | 9 | Given an array with 2n+1 integer elements, n elements appear twice in arbitrary 10 | places in the array and a single integer appears only once somewhere 11 | inside. Find the lonely integer with O(n) operations and O(1) extra memory. 12 | 13 | # Commentary 14 | 15 | An even occurence of a variable can be detected by flipping a bit each time it 16 | is sampled (zero occurences is considered even). For a SRAM containing 2N+1 17 | entries, of width W, odd occurances of a variable can be detected by maintaining 18 | a 2^W vector, and flipping the corresponding bit in the vector each time the 19 | value is read from SRAM. After having queried the state table, provided the 20 | input is not malformed, the non-duplicated value can be identified by encoding 21 | the final 1 hot vector. 22 | 23 | # Complexity 24 | 25 | O(N) lookup operations are required. Lookup is linear with the number of table 26 | entries. Recall that O(2N+1)=O(N), as one could mistakely assume that the 2N+1 27 | table can only be queried using N operations.. 28 | 29 | O(1) state is required (with respect to N). 30 | 31 | O(2^W) state is required with respect to W. 32 | -------------------------------------------------------------------------------- /rtl/multi_counter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(multi_counter) 29 | -------------------------------------------------------------------------------- /rtl/multi_counter/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | Unknown 4 | 5 | # Company 6 | 7 | Fungible/Google 8 | 9 | # Problem Statement 10 | 11 | Maintain a set of counters that can be incremented, decremented of initialized 12 | based upon in incoming comamnd. The counters are implemented in a single 13 | dual-ported synchronous SRAM (or register file). Implement a pipeline to compute 14 | updates to the counters such that commands can be consumed at the rate of 1 per 15 | cycle. 16 | 17 | # Commentary 18 | 19 | This question is designed to present an understanding of basic pipelining 20 | concepts. In particular, the requirement to support back-to-back commands 21 | (possibly referencing the same counter), necessitates the use of oprand 22 | forwarding. 23 | 24 | The pipeline design can be relatively trivial as there is no need to support 25 | replay, stall conditions, committal and/or retirement states. 26 | -------------------------------------------------------------------------------- /rtl/multi_counter/multi_counter_pkg.vh: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | `ifndef MULTI_COUNTER_PKG_VH 29 | `define MULTI_COUNTER_PKG_VH 30 | 31 | package multi_counter_pkg; 32 | 33 | // ------------------------------------------------------------------------ // 34 | // 35 | parameter int OP_OUTPUT_B = 4; 36 | // 37 | parameter int OP_READ_B = 3; 38 | // 39 | parameter int OP_WRITE_B = 2; 40 | 41 | // ------------------------------------------------------------------------ // 42 | // __ 43 | // 44 | typedef enum logic [4:0] { 45 | // No Operation 46 | OP_NOP = 5'b0_00_00, 47 | 48 | // Initialize CMD 49 | OP_INIT = 5'b0_01_00, 50 | 51 | // Increment CMD 52 | OP_INCR = 5'b0_11_00, 53 | 54 | // Decrement CMD 55 | OP_DECR = 5'b0_11_01, 56 | 57 | // Query CMD 58 | OP_QRY = 5'b1_10_00 59 | 60 | } op_t; 61 | 62 | endpackage // multi_counter_pkg 63 | 64 | `endif 65 | -------------------------------------------------------------------------------- /rtl/multi_counter_variants/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(multi_counter_variants) 29 | 30 | LIBPD_VIVADO(multi_counter_variants) 31 | -------------------------------------------------------------------------------- /rtl/multi_counter_variants/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | # Company 4 | 5 | Google 6 | 7 | # Problem 8 | 9 | Maintain a set of counters that can be incremented, decremented of initialized 10 | based upon in incoming command. 11 | 12 | # Commentary 13 | 14 | There are multiple possible solutions to the question as posed each 15 | varying in complexity. The correct solution largely depends upon the 16 | counter count and desired clock frequency. 17 | 18 | Three solutions are presented: 19 | 20 | * __Simple Flop Table__ 21 | 22 | The simplest of the three solutions solves the problem by 23 | maintaining counter state entirely in flops. State is muxed by 24 | command id, modified and written back in one cycle. This is fairly 25 | straight forward however it suffers from, 1) the mux operation on 26 | the initial state lookup and 2) the consequent writeback to the 27 | state table. In 1) there is an N-to-1 mux, in 2) there is a O(N) 28 | fan-out at the output of the adder/subtractor. By consequence of 29 | this, the propose solution perhaps suffers from lower overall 30 | achievable clock frequency and may not be scalable to large N. 31 | 32 | * __Multiple Engines__ 33 | 34 | The second approach is to, similarly, maintain state in flops but 35 | replicate state update logic with each context. At the cost of some 36 | area overhead, the solution presented can be scaled to a larger N 37 | although there remains some fan-out issues on the command interface 38 | and on the output MUX. 39 | 40 | * __Pipeline__ 41 | 42 | The third, and most effiicent solution (but also the most complex), 43 | is to maintain state within a dual-ported synchronous SRAM. A 44 | pipeline is implemented around SRAM to manage lookup and writeback 45 | operations. This solution is largely invariant to changes in N and 46 | is capable of achieving a good Fmax. 47 | 48 | 49 | # NOTES 50 | 51 | In modern geometries, the transition to a dedicated SRAM module is 52 | typically only justified when the number of bits to be retain exceeds 53 | (on the order of) 1k-10kbits. Otherwise, a FF based structure is more 54 | efficient in terms of area. Largely, modern geometries are quite 55 | forgiving when it comes to synthesizing large FF-based arrays, 56 | although this -of course- largely depends upon the particular 57 | application. 58 | -------------------------------------------------------------------------------- /rtl/multi_counter_variants/multi_counter_variants.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj multi_counter_variants 29 | create_project latency -in_memory 30 | 31 | # Source 32 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 33 | read_verilog @LIBPD_TECH_ROOT@/dpsram.sv 34 | 35 | # XDC 36 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 37 | 38 | # PD FLOW 39 | synth_design -name $prj -top $prj -include_dirs {@LIBPD_INCLUDE_DIRS@} 40 | opt_design 41 | place_design 42 | phys_opt_design 43 | route_design 44 | report_timing_summary 45 | -------------------------------------------------------------------------------- /rtl/multi_counter_variants/multi_counter_variants.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 10.00 -name CLK -waveform {0.000 5.000} [get_ports clk] 29 | set_input_delay -clock CLK 1.0 [all_inputs] 30 | set_output_delay -clock CLK 1.0 [all_outputs] 31 | -------------------------------------------------------------------------------- /rtl/multi_counter_variants/multi_counter_variants_pkg.vh: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | `ifndef MULTI_COUNTER_VARIANTS_PKG_VH 29 | `define MULTI_COUNTER_VARIANTS_PKG_VH 30 | 31 | package multi_counter_variants_pkg; 32 | 33 | // ------------------------------------------------------------------------ // 34 | // 35 | parameter int OP_OUTPUT_B = 4; 36 | // 37 | parameter int OP_READ_B = 3; 38 | // 39 | parameter int OP_WRITE_B = 2; 40 | 41 | // ------------------------------------------------------------------------ // 42 | // __ 43 | // 44 | typedef enum logic [4:0] { 45 | // No Operation 46 | OP_NOP = 5'b0_00_00, 47 | 48 | // Initialize CMD 49 | OP_INIT = 5'b0_01_00, 50 | 51 | // Increment CMD 52 | OP_INCR = 5'b0_11_00, 53 | 54 | // Decrement CMD 55 | OP_DECR = 5'b0_11_01, 56 | 57 | // Query CMD 58 | OP_QRY = 5'b1_10_00 59 | 60 | } op_t; 61 | 62 | endpackage // multi_counter_variants_pkg 63 | 64 | `endif 65 | -------------------------------------------------------------------------------- /rtl/multiply_by_21/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(multiply_by_21) 29 | 30 | -------------------------------------------------------------------------------- /rtl/multiply_by_21/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | Unknown 4 | 5 | # Company 6 | 7 | Unknown 8 | 9 | # Problem Statement 10 | 11 | A constant, sparse integer is to be multiplied against an arbitrary 12 | width random vector. Derive efficient logic to perform this 13 | operation. (Sparse means that the vector has only a small number of 14 | bits set). 15 | 16 | # Commentary 17 | 18 | Multiplication is simply repeated addition over differing shifts. For a 19 | sparse constant, multiplication can be carried out efficiently by 20 | infering N adders (where N is the population count of the constant) 21 | adding the i'th shifted version of the input (where 'i' is the 22 | location of the bit in the constant vector). 23 | 24 | Addition can be efficiently performed by using a CSA structure. Which 25 | should be efficiently infered by repeated addition operators. 26 | -------------------------------------------------------------------------------- /rtl/multiply_by_21/multiply_by_21.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016-17, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include 30 | #include "Vmultiply_by_21.h" 31 | 32 | using DataT = uint32_t; 33 | 34 | #define PORTS(__func) \ 35 | __func(a, DataT) \ 36 | __func(fail, bool) 37 | 38 | struct MultiplyBy21Tb : libtb::TopLevel 39 | { 40 | SC_HAS_PROCESS(MultiplyBy21Tb); 41 | MultiplyBy21Tb(sc_core::sc_module_name mn = "t") 42 | : libtb::TopLevel(mn) 43 | , uut_("uut") 44 | #define __construct_signals(__name, __type) \ 45 | , __name##_(#__name) 46 | PORTS(__construct_signals) 47 | #undef __construct_signals 48 | { 49 | SC_METHOD(m_checker); 50 | sensitive << e_tb_sample(); 51 | dont_initialize(); 52 | 53 | #define __bind_signals(__name, __type) \ 54 | uut_.__name(__name##_); 55 | PORTS(__bind_signals) 56 | #undef __bind_signals 57 | } 58 | 59 | bool run_test() { 60 | LIBTB_REPORT_INFO("Stimulus starts"); 61 | int n = N_; 62 | while (n--) { 63 | a_ = libtb::random(); 64 | wait(10, SC_NS); 65 | } 66 | LIBTB_REPORT_INFO("Stimulus ends"); 67 | return false; 68 | } 69 | 70 | void m_checker() 71 | { 72 | LIBTB_ASSERT_FATAL(!fail_); 73 | } 74 | 75 | const int N_{10000}; 76 | #define __declare_signals(__name, __type) \ 77 | sc_core::sc_signal<__type> __name##_; 78 | PORTS(__declare_signals) 79 | #undef __declare_signals 80 | Vmultiply_by_21 uut_; 81 | }; 82 | 83 | int sc_main (int argc, char **argv) 84 | { 85 | return libtb::LibTbSim(argc, argv).start(); 86 | } 87 | -------------------------------------------------------------------------------- /rtl/multiply_by_21/multiply_by_21.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module multiply_by_21 #(parameter int W = 32) (input [W-1:0] a, 29 | output logic fail); 30 | 31 | localparam int X = 21; // 10101 32 | localparam int Y_W = W + $clog2(X) + 1; 33 | typedef logic [Y_W-1:0] y_t; 34 | 35 | y_t y_expected; 36 | y_t y_actual; 37 | 38 | always_comb 39 | begin : compute_y_PROC 40 | 41 | // 42 | y_expected = a * X; 43 | 44 | // Infer an adder for the sparse bits set to 1 in the 45 | // multiplication factor. Note, since the predicate is an 46 | // elaboration-time constant, the inference carried out by a 47 | // synthesis tool should be static and minimal. 48 | // 49 | y_actual = '0; 50 | for (int i = 0; i < $bits(X); i++) 51 | if (X[i]) 52 | y_actual += y_t'(a) << i; 53 | 54 | // This is structurally equivalent to: 55 | // y_actual += y_t'(a); 56 | // y_actual += y_t'(a) << 2; 57 | // y_actual += y_t'(a) << 4; 58 | 59 | // NOTE: y_t'(a) << 4 != y_t'(a << 4). 60 | // The RHS is wrong because the extension should take place 61 | // before the shift operation (not after). The RHS results in 62 | // truncation of the output result. 63 | 64 | fail = (y_actual != y_expected); 65 | 66 | end // block: compute_y_PROC 67 | 68 | endmodule // multiply_by_21 69 | 70 | 71 | -------------------------------------------------------------------------------- /rtl/one_or_two/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(one_or_two) 29 | LIBPD_VIVADO(one_or_two) 30 | -------------------------------------------------------------------------------- /rtl/one_or_two/README.md: -------------------------------------------------------------------------------- 1 | # one_or_two 2 | 3 | # Question 4 | 5 | For a given logic vector, of arbitrary length, derive logic that detects the 6 | following conditions: 7 | 8 | * 0-bits are set in the vector 9 | * 1-bit is set in the vector 10 | * ``>=``2-bits are set in the vector 11 | 12 | Do so in a means that is efficient in terms of logic utilization and independent 13 | of vector length. 14 | 15 | # Commentary 16 | 17 | This question is designed to illustrate a candidates understating of basic logic 18 | concepts. 19 | 20 | * 0-bits are set in the vector 21 | 22 | This can be derived trivially by the following code: 23 | ~~~ 24 | always_comb has_set_0 = (A == '0); 25 | ~~~ 26 | or 27 | ~~~ 28 | always_comb has_set_0 = (~|A); 29 | ~~~ 30 | 31 | In both cases, this logic should synthesize to an NOR-reduction operation on the 32 | input vector. This can be computed trivially and inferred through Verilog 33 | independently of the length of A. 34 | 35 | * 1-bit is set in the vector 36 | 37 | The presence of set bits in the vector can be found trivially as: 38 | ~~~ 39 | always_comb has_set_at_least_1 = (|A); 40 | ~~~ 41 | 42 | the OR-reduction of the input vector. This does not indicate however whether 43 | only one bit is set in the vector. It turns out that this can be computed as: 44 | ~~~ 45 | always_comb only_1_bit_set = ~|(A & (A - 1)); 46 | ~~~ 47 | 48 | This relation is true only if A is a one-hot vector. 49 | 50 | * ``>=``2-bits are set in the vector 51 | 52 | Derived as a function of the prior logic, the condition can be calculated as: 53 | ~~~ 54 | always_comb has_set_more_than_1 = (~has_set_0) & (~has_set_1); 55 | ~~~ 56 | 57 | Additionally, the candidate may wish to qualify the condition such that its 58 | assertion is defeated if the logic vector is only 1-bit in length. 59 | -------------------------------------------------------------------------------- /rtl/one_or_two/one_or_two.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module one_or_two #(parameter int W = 32) ( 29 | 30 | //========================================================================== // 31 | // // 32 | // Input // 33 | // // 34 | //========================================================================== // 35 | 36 | input [W-1:0] x 37 | 38 | //========================================================================== // 39 | // // 40 | // Control // 41 | // // 42 | //========================================================================== // 43 | 44 | , input logic inv 45 | 46 | //========================================================================== // 47 | // // 48 | // Output // 49 | // // 50 | //========================================================================== // 51 | 52 | , output logic has_set_0 53 | 54 | , output logic has_set_1 55 | 56 | , output logic has_set_more_than_1 57 | ); 58 | 59 | // ======================================================================== // 60 | // // 61 | // Wires // 62 | // // 63 | // ======================================================================== // 64 | 65 | logic [W-1:0] x_cond; 66 | logic is_power_of_2; 67 | 68 | // ======================================================================== // 69 | // // 70 | // Combinatorial Logic // 71 | // // 72 | // ======================================================================== // 73 | 74 | // ------------------------------------------------------------------------ // 75 | // 76 | always_comb 77 | begin : one_or_two_PROC 78 | 79 | // 80 | x_cond = x ^ {W{inv}}; 81 | 82 | // 83 | has_set_0 = (~|x_cond); 84 | 85 | // Critical path is through is_power_of_2 86 | // 87 | is_power_of_2 = ~|(x_cond & (x_cond - 1)); 88 | 89 | // 90 | has_set_1 = (~has_set_0) & is_power_of_2; 91 | 92 | // 93 | has_set_more_than_1 = (W > 1) & (~has_set_0) & (~has_set_1); 94 | 95 | end // block: one_or_two_PROC 96 | 97 | endmodule // one_or_two 98 | -------------------------------------------------------------------------------- /rtl/one_or_two/one_or_two.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj one_or_two 29 | create_project latency -in_memory 30 | 31 | # Source 32 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 33 | 34 | # XDC 35 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 36 | 37 | # PD FLOW 38 | synth_design -name $prj -top $prj -include_dirs {@LIBPD_INCLUDE_DIRS@} 39 | opt_design 40 | place_design 41 | phys_opt_design 42 | route_design 43 | report_timing_summary 44 | -------------------------------------------------------------------------------- /rtl/one_or_two/one_or_two.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | # Virtual clock for I/O reference 29 | create_clock -period 12.0 -name VCLK 30 | 31 | set_input_delay -clock VCLK 1.0 [all_inputs] 32 | set_output_delay -clock VCLK 1.0 [all_outputs] 33 | -------------------------------------------------------------------------------- /rtl/pipelined_add_constant/A.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | 29 | module A#(parameter int W = 32) 30 | ( 31 | //======================================================================== // 32 | // // 33 | // Misc. // 34 | // // 35 | //======================================================================== // 36 | 37 | input clk 38 | , input rst 39 | 40 | //======================================================================== // 41 | // // 42 | // Oprands // 43 | // // 44 | //======================================================================== // 45 | 46 | , input [W-1:0] a_init 47 | , input [W-1:0] i 48 | // 49 | , input init 50 | 51 | //======================================================================== // 52 | // // 53 | // Result // 54 | // // 55 | //======================================================================== // 56 | 57 | , output logic [W-1:0] y_w 58 | ); 59 | 60 | typedef logic [W-1:0] w_t; 61 | w_t A_r, A_w, I_r; 62 | 63 | // ------------------------------------------------------------------------ // 64 | // 65 | always_comb 66 | begin 67 | 68 | // 69 | A_w = A_r + w_t'(I_r); 70 | 71 | // 72 | y_w = A_w; 73 | 74 | end 75 | 76 | // ------------------------------------------------------------------------ // 77 | // 78 | always_ff @(posedge clk) 79 | if (init) 80 | I_r <= i; 81 | 82 | // ------------------------------------------------------------------------ // 83 | // 84 | always_ff @(posedge clk) 85 | if (rst) 86 | A_r <= '0; 87 | else 88 | A_r <= init ? a_init : A_w; 89 | 90 | endmodule // A 91 | 92 | -------------------------------------------------------------------------------- /rtl/pipelined_add_constant/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(pipelined_add_constant) 29 | -------------------------------------------------------------------------------- /rtl/pipelined_add_constant/pipelined_add_constant.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2016-17, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include "Vpipelined_add_constant.h" 30 | 31 | #define PORTS(__func) \ 32 | __func(fail, bool) 33 | 34 | class Pipelined_add_constantTb : libtb::TopLevel 35 | { 36 | public: 37 | SC_HAS_PROCESS(Pipelined_add_constantTb); 38 | Pipelined_add_constantTb(sc_core::sc_module_name mn = "t") 39 | : uut_("uut") 40 | #define __declare_signals(__name, __type) \ 41 | , __name##_(#__name) 42 | PORTS(__declare_signals) 43 | #undef __declare_signals 44 | { 45 | SC_METHOD(m_checker); 46 | dont_initialize(); 47 | sensitive << e_tb_sample(); 48 | 49 | uut_.clk(clk()); 50 | uut_.rst(rst()); 51 | #define __bind_signals(__name, __type) \ 52 | uut_.__name(__name##_); 53 | PORTS(__bind_signals) 54 | #undef __bind_signals 55 | } 56 | 57 | bool run_test() 58 | { 59 | t_wait_reset_done(); 60 | reset_complete_ = true; 61 | LIBTB_REPORT_INFO("Stimulus starts...."); 62 | wait (1, SC_US); 63 | LIBTB_REPORT_INFO("Stimulus ends."); 64 | return false; 65 | } 66 | 67 | void m_checker() { 68 | if (!reset_complete_) 69 | return; 70 | LIBTB_ASSERT_ERROR(!fail_); 71 | } 72 | 73 | bool reset_complete_{false}; 74 | #define __declare_signals(__name, __type) \ 75 | sc_core::sc_signal<__type> __name##_; 76 | PORTS(__declare_signals) 77 | #undef __declare_signals 78 | Vpipelined_add_constant uut_; 79 | }; 80 | 81 | int sc_main (int argc, char **argv) 82 | { 83 | using namespace libtb; 84 | return LibTbSim(argc, argv).start(); 85 | } 86 | -------------------------------------------------------------------------------- /rtl/pipelined_add_constant/two_cycle_adder.sv: -------------------------------------------------------------------------------- 1 | module two_cycle_adder #(parameter int W = 32) ( 2 | 3 | //======================================================================== // 4 | // // 5 | // Misc. // 6 | // // 7 | //======================================================================== // 8 | 9 | input clk 10 | 11 | , input cin 12 | , input [W-1:0] a 13 | , input [W-1:0] b 14 | 15 | , output logic cout 16 | , output logic [W-1:0] y 17 | ); 18 | 19 | typedef logic [W-1:0] w_t; 20 | typedef struct packed { logic cout; w_t w;} result_t; 21 | 22 | result_t result_0_w, result_0_r; 23 | always_comb 24 | begin 25 | result_0_w = a + b + w_t'(cin); 26 | {cout, y} = result_0_r; 27 | end 28 | 29 | always_ff @(posedge clk) begin 30 | result_0_r <= result_0_w; 31 | end 32 | 33 | endmodule // two_cycle_adder 34 | -------------------------------------------------------------------------------- /rtl/sorted_lists/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(sorted_lists) 29 | LIBPD_VIVADO(sorted_lists) 30 | -------------------------------------------------------------------------------- /rtl/sorted_lists/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | Networking Match/Action data paths 4 | 5 | # Problem Statement 6 | 7 | M-lists (M=64) are maintained. The lists are ordered, although the ordering (GT 8 | or LT) is irrelevant. Each entry in the list maintains a {KEY, SIZE} pair. The 9 | list is ordered on the value of KEY. SIZE is considered a payload which is 10 | simply retained by the machine and returned to the client. 11 | 12 | List state can be modified using the following commands: 13 | 14 | * CLEAR: All State associated with the LIST is cleared (reset to 15 | initial state). 16 | 17 | * ADD: A {KEY, SIZE} pair is added to the LIST 18 | 19 | * DELETE: A {KEY, SIZE} pair is deleted from the LIST based upon an input 20 | KEY operand. If the KEY is not present, an error is signalled. 21 | 22 | * REPLACE: The SIZE field of a {KEY, SIZE} pair is replaced based 23 | upon an input KEY operand. 24 | 25 | A QUERY interface is present. From this a particular LIST is addressed and the 26 | N'th largest/smallest returned. 27 | 28 | Each list can be modified "every other cycle". The Query bus may be active at 29 | the time a list is modified however it can be assumed that a list being actively 30 | modified shall not be queried. 31 | 32 | 33 | # Performance Objectives/Actuals 34 | 35 | Objective: List state can be updated "every-other-cycle"; therefore a 36 | utilization of around 50% is required. List state can be queried on each cycle. 37 | 38 | # Implementation 39 | 40 | The question is purposefully misleading because it is worded in such a fashion 41 | that it implies that state must be internally maintained using a Linked List 42 | structure. This is possible, however it is not possible to achieve the stated 43 | performance objectives using a linked list. The DELETE and REPLACE operations 44 | too suggest that some associative addressing is required as in this case an 45 | operation is performed based upon the KEY match. To perform this using a LL 46 | structure is O(N) with the length of the list. 47 | 48 | The proposed implementation maintains the list structure as a tuple of entries 49 | in a table. The entries are unordered. ADD, DELETE, REPLACE, CLEAR commands are 50 | trivially implemented based upon an associative "HIT" operation and writeback. 51 | 52 | The Query bus is implemented by performing a lookup on the LIST state and 53 | combinatorially sorting all entries on the KEY. The N'th largest/smallest can be 54 | trivially derived. 55 | 56 | Inbound updates commands and coincident with Query operations. This results in a 57 | structural hazard on the port count the RAMs used to maintain the table. The 58 | table is therefore duplicated to increase port count as necessary. The UPDATE 59 | logic maintains ownership of the table, therefore forwarding is unnecessary. 60 | 61 | # Verification Methodology 62 | 63 | A C++ behavioral model is implemented to emulate the machine. A randomized 64 | series of update commands are generated based upon the machine state and 65 | injected into RTL. The behavioral model is updated in parallel with the 66 | application of UPDATE stimulus. Stimulus is appropriately constrained. 67 | 68 | Post-initialization, query commands are emitted and responses checked against 69 | expected behavior. 70 | 71 | # PD 72 | 73 | The target operating clock frequency of the block is 150-170 MHz. Two 74 | key optimizations 75 | 76 | * The update pipeline is not completely forwarded. Consequently, it 77 | cannot support back to back update commands to the same ID. The 78 | pipeline can support back-to-back commands to differing ID. 79 | 80 | * The sort network is pipelined after each comparison operation 81 | (accounting for parallelism between operations). This is a fairly 82 | lengthy comparison, 64b subtraction, and may therefore be 83 | slow. There are no requirements on latency, therefore pipeline is 84 | applied. 85 | 86 | # Commentary 87 | -------------------------------------------------------------------------------- /rtl/sorted_lists/sorted_lists.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | 29 | set prj sorted_lists 30 | create_project latency -in_memory 31 | 32 | ## Require a large device because of I/O count. 33 | set_property part XC7A200TFFG1156 [current_project] 34 | 35 | # Source 36 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 37 | read_verilog @LIBV_ROOT@/popcnt.sv 38 | read_verilog @LIBV_ROOT@/delay_pipe.sv 39 | read_verilog @LIBV_ROOT@/ffs.sv 40 | read_verilog @LIBV_ROOT@/encoder.sv 41 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/sorting_network.sv 42 | read_verilog @LIBPD_TECH_ROOT@/dpsrams.sv 43 | 44 | # XDC 45 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 46 | 47 | # PD FLOW 48 | synth_design -name $prj -top $prj -include_dirs {@LIBPD_INCLUDE_DIRS@} 49 | opt_design 50 | place_design 51 | phys_opt_design 52 | route_design 53 | report_timing_summary 54 | -------------------------------------------------------------------------------- /rtl/sorted_lists/sorted_lists.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 10.00 -name CLK -waveform {0.000 5.000} [get_ports clk] 29 | set_input_delay -clock CLK 1.0 [all_inputs] 30 | set_output_delay -clock CLK 1.0 [all_outputs] 31 | -------------------------------------------------------------------------------- /rtl/sorted_lists/sorted_lists_pkg.vh: -------------------------------------------------------------------------------- 1 | `ifndef SORTED_LISTS_PKG_VH 2 | `define SORTED_LISTS_PKG_VH 3 | 4 | //========================================================================== // 5 | // Copyright (c) 2017, Stephen Henry 6 | // All rights reserved. 7 | // 8 | // Redistribution and use in source and binary forms, with or without 9 | // modification, are permitted provided that the following conditions are met: 10 | // 11 | // * Redistributions of source code must retain the above copyright notice, this 12 | // list of conditions and the following disclaimer. 13 | // 14 | // * Redistributions in binary form must reproduce the above copyright notice, 15 | // this list of conditions and the following disclaimer in the documentation 16 | // and/or other materials provided with the distribution. 17 | // 18 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 | // POSSIBILITY OF SUCH DAMAGE. 29 | //========================================================================== // 30 | 31 | package sorted_lists_pkg; 32 | 33 | // The number of entries in the list. 34 | // 35 | localparam int N = 4; 36 | 37 | // The number of lists 38 | // 39 | localparam int M = 64; 40 | 41 | // 42 | typedef logic [63:0] key_t; 43 | typedef logic [31:0] size_t; 44 | 45 | // 46 | typedef struct packed { 47 | logic vld; 48 | key_t key; 49 | size_t size; 50 | } entry_t; 51 | 52 | // 53 | typedef struct packed { 54 | entry_t [N-1:0] e; 55 | } table_state_t; 56 | 57 | endpackage // sorted_lists_pkg 58 | 59 | `endif 60 | -------------------------------------------------------------------------------- /rtl/using_full_adders/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(using_full_adders) 29 | -------------------------------------------------------------------------------- /rtl/using_full_adders/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | Carry Save Adder 4 | 5 | # Company 6 | 7 | Qualcomm 8 | 9 | # Problem 10 | 11 | You have seven, 1b numbers. If you have only full-adders, compute their sum in 12 | the most efficient manner. 13 | 14 | # Solution 15 | 16 | This is a simple test of knowledge. A CSA can be used to effectively add each 17 | number to produce the population count (the 3:2 compression function in a CSA 18 | is, afterall, simply a Full Adder). 19 | 20 | 21 | For the vector ABC_DEF_G, the CSA structure can be optimized by noting that 22 | after compression of ABC and DEF we are left with two 2b numbers an a 1b number 23 | (G). The final sum can be computed using G as the carry-in to full adder of the 24 | LSB. This optimized structure requires only 4 full-adders instead of 5 25 | full-adders using a naive CSA. 26 | 27 | # Notes 28 | 29 | Do not ask this question to a senior engineer as they would likely laugh in your 30 | face. Secondly, this is a very, very poor question because it really does not 31 | measure (by any objective means) a candidates ability to design RTL. It is a 32 | stupid, hypothetical problem that proves little about a candidates 33 | ability. Moreso, if the interviewer has learned this question by rote, and they 34 | understand only the solution, not the concept behind Carry Save Adders. Run. Run 35 | fast. They're idiots. 36 | -------------------------------------------------------------------------------- /rtl/using_full_adders/using_full_adders.cpp: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | #include 29 | #include 30 | #include "Vusing_full_adders.h" 31 | #define PORTS(__func) \ 32 | __func(x, uint32_t) \ 33 | __func(fail, bool) 34 | 35 | struct UsingFullAddersTb : libtb::TopLevel 36 | { 37 | using UUT = Vusing_full_adders; 38 | SC_HAS_PROCESS(UsingFullAddersTb); 39 | UsingFullAddersTb(sc_core::sc_module_name mn = "t") 40 | : uut_("uut") 41 | #define __construct_signal(__name, __type) \ 42 | , __name##_(#__name) 43 | PORTS(__construct_signal) 44 | #undef __construct_signal 45 | { 46 | SC_METHOD(m_checker); 47 | dont_initialize(); 48 | sensitive << e_reset_done(); 49 | uut_.clk(clk()); 50 | uut_.rst(rst()); 51 | #define __bind_signal(__name, __type) \ 52 | uut_.__name(__name##_); 53 | PORTS(__bind_signal) 54 | #undef __bind_signals 55 | } 56 | void m_checker() { 57 | if (fail_) { 58 | std::stringstream ss; 59 | ss << "Mismatch detected x=" << x_; 60 | LIBTB_REPORT_ERROR(ss.str()); 61 | } 62 | next_trigger(clk().posedge_event()); 63 | } 64 | bool run_test() { 65 | x_ = 0; 66 | t_wait_reset_done(); 67 | int n = 10000; 68 | while (n--) 69 | { 70 | x_ = libtb::random_integer_in_range(7, 0); 71 | t_wait_posedge_clk(); 72 | } 73 | return false; 74 | } 75 | #define __declare_signal(__name, __type) \ 76 | sc_core::sc_signal<__type> __name##_; 77 | PORTS(__declare_signal) 78 | #undef __declare_signal 79 | UUT uut_; 80 | }; 81 | 82 | int sc_main (int argc, char **argv) 83 | { 84 | using namespace libtb; 85 | return LibTbSim(argc, argv).start(); 86 | } 87 | -------------------------------------------------------------------------------- /rtl/using_full_adders/using_full_adders.sv: -------------------------------------------------------------------------------- 1 | //========================================================================== // 2 | // Copyright (c) 2017, Stephen Henry 3 | // All rights reserved. 4 | // 5 | // Redistribution and use in source and binary forms, with or without 6 | // modification, are permitted provided that the following conditions are met: 7 | // 8 | // * Redistributions of source code must retain the above copyright notice, this 9 | // list of conditions and the following disclaimer. 10 | // 11 | // * Redistributions in binary form must reproduce the above copyright notice, 12 | // this list of conditions and the following disclaimer in the documentation 13 | // and/or other materials provided with the distribution. 14 | // 15 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | // POSSIBILITY OF SUCH DAMAGE. 26 | //========================================================================== // 27 | 28 | module using_full_adders (output logic fail, 29 | input logic [6:0] x, 30 | input logic clk, 31 | input logic rst); 32 | 33 | 34 | function [1:0] full_adder (input logic a, input logic b, input logic cin); 35 | logic [1:0] ret = '0; 36 | ret [0] = ^{a, b, cin}; 37 | ret [1] = (a&b) | (cin & (a | b)); 38 | return ret; 39 | endfunction // full_adder 40 | 41 | typedef logic [2:0] w_t; 42 | w_t expected; 43 | w_t solution_0; 44 | w_t solution_1; 45 | 46 | // ------------------------------------------------------------------------ // 47 | // 48 | always_comb 49 | begin 50 | 51 | // 52 | fail = '0; 53 | 54 | // 55 | expected = $countones(x); 56 | 57 | // Solution 0 (CSA) 58 | 59 | // 60 | begin 61 | 62 | logic [2:0] s0_a; 63 | logic [2:0] s0_b; 64 | logic cout; 65 | 66 | // CSA reduction 1 67 | // 68 | s0_a = '0; 69 | s0_a [1:0] = full_adder (x [2], x [1], x [0]); 70 | 71 | // CSA reduction 2 72 | // 73 | s0_b = '0; 74 | s0_b [1:0] = full_adder (x [5], x [4], x [3]); 75 | 76 | // Ripple Carry Adder 77 | // 78 | {cout, solution_0 [0]} = full_adder (s0_a [0], s0_b [0], 1'b0); 79 | {cout, solution_0 [1]} = full_adder (s0_a [1], s0_b [1], cout); 80 | {cout, solution_0 [2]} = full_adder (s0_a [2], s0_b [2], cout); 81 | 82 | end 83 | 84 | // Solution 1 (Minimal CSA using Cin - 4 FA) 85 | // 86 | begin 87 | 88 | logic [1:0] s1_a = full_adder (x [2], x[1], x[0]); 89 | logic [1:0] s1_b = full_adder (x [5], x[4], x[3]); 90 | logic [1:0] s1_c = full_adder (s1_a [0], s1_b [0], x [6]); 91 | logic [1:0] s1_d = full_adder (s1_a [1], s1_b [1], s1_c [1]); 92 | 93 | solution_1 = {s1_d, s1_c [0]}; 94 | end 95 | 96 | // 97 | fail |= (expected != solution_0); 98 | fail |= (expected != solution_1); 99 | 100 | end 101 | 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /rtl/vending_machine_dp/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(vending_machine_dp) 29 | LIBPD_VIVADO(vending_machine_dp) 30 | -------------------------------------------------------------------------------- /rtl/vending_machine_dp/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | "Digital Design: A Systems Approach" Dally, Harting 4 | 5 | # Company 6 | 7 | Google 8 | 9 | # Problem Statement 10 | 11 | 16.3.1 "Vending Machine FSM" 12 | 13 | # Commentary 14 | 15 | TBD 16 | -------------------------------------------------------------------------------- /rtl/vending_machine_dp/vending_machine_dp.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj vending_machine_dp 29 | 30 | create_project $prj -in_memory 31 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 32 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 33 | synth_design -name $prj -top $prj -verilog_define LIBPD=1 34 | opt_design 35 | place_design 36 | phys_opt_design 37 | route_design 38 | report_timing_summary 39 | -------------------------------------------------------------------------------- /rtl/vending_machine_dp/vending_machine_dp.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 20.00 -name CLK -waveform {0.000 10.000} [get_ports clk] 29 | set_input_delay -clock CLK 1.0 [all_inputs] 30 | set_output_delay -clock CLK 1.0 [all_outputs] 31 | 32 | -------------------------------------------------------------------------------- /rtl/vending_machine_fsm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(vending_machine_fsm) 29 | LIBPD_VIVADO(vending_machine_fsm) 30 | -------------------------------------------------------------------------------- /rtl/vending_machine_fsm/README.md: -------------------------------------------------------------------------------- 1 | # Origin 2 | 3 | "Digital Design: A Systems Approach" Dally, Harting 4 | 5 | # Company 6 | 7 | Google 8 | 9 | # Problem Statement 10 | 11 | [Design an FSM which] vends a single $0.40 item and only accepts nickels and 12 | dimes. This input signals are nickel and dime and the outputs are vend and 13 | change. The two input signals are pulsed high when a nickel or a dime is 14 | inserted into the machine. When enough money has been added, the vend signal 15 | goes high for a single cycle. If $0.45 had been inserted, change also pulses 16 | high for one cycle. After vending an item, the state returns to the initial 17 | state where no money has been inserted. 18 | 19 | # Commentary 20 | 21 | TBD 22 | -------------------------------------------------------------------------------- /rtl/vending_machine_fsm/vending_machine_fsm.tcl.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | set prj vending_machine_fsm 29 | create_project latency -in_memory 30 | 31 | # Source 32 | read_verilog @CMAKE_CURRENT_SOURCE_DIR@/$prj.sv 33 | 34 | # XDC 35 | read_xdc @CMAKE_CURRENT_BINARY_DIR@/$prj.xdc 36 | 37 | # PD FLOW 38 | synth_design -name $prj -top $prj -include_dirs {@LIBPD_INCLUDE_DIRS@} 39 | opt_design 40 | place_design 41 | phys_opt_design 42 | route_design 43 | report_timing_summary 44 | -------------------------------------------------------------------------------- /rtl/vending_machine_fsm/vending_machine_fsm.xdc.in: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | create_clock -period 10.0 -name CLK [get_ports clk] 29 | 30 | set_input_delay -clock CLK 1.0 [all_inputs] 31 | set_output_delay -clock CLK 1.0 [all_outputs] 32 | -------------------------------------------------------------------------------- /rtl/zero_indices_fast/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(zero_indices_fast) 29 | -------------------------------------------------------------------------------- /rtl/zero_indices_slow/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | EMIT_ANSWER(zero_indices_slow) 29 | -------------------------------------------------------------------------------- /scripts/verilate.sh: -------------------------------------------------------------------------------- 1 | ##========================================================================== // 2 | ## Copyright (c) 2016, Stephen Henry 3 | ## All rights reserved. 4 | ## 5 | ## Redistribution and use in source and binary forms, with or without 6 | ## modification, are permitted provided that the following conditions are met: 7 | ## 8 | ## * Redistributions of source code must retain the above copyright notice, this 9 | ## list of conditions and the following disclaimer. 10 | ## 11 | ## * Redistributions in binary form must reproduce the above copyright notice, 12 | ## this list of conditions and the following disclaimer in the documentation 13 | ## and/or other materials provided with the distribution. 14 | ## 15 | ## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | ## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | ## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 | ## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 | ## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 | ## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 | ## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 | ## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 | ## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 | ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 | ## POSSIBILITY OF SUCH DAMAGE. 26 | ##========================================================================== // 27 | 28 | if [ -z "${VERILATOR_INCLUDE}" ]; then 29 | echo "VERILATOR_INCLUDE not defined" 30 | exit 1 31 | fi 32 | 33 | if [ -z ${VERILATED_OBJ} ]; then 34 | echo "VERILATED_OBJ not defined" 35 | exit 1 36 | fi 37 | 38 | if [ -z ${CMAKE_CURRENT_SOURCE_DIR} ]; then 39 | echo "CMAKE_CURRENT_SOURCE_DIR not defined" 40 | exit 1 41 | fi 42 | 43 | if [ -z ${ANSWER} ]; then 44 | echo "ANSWER not defined" 45 | exit 1 46 | fi 47 | 48 | # Invoke Verilator 49 | # 50 | ${VERILATOR_EXE} --sc ${VERILATOR_INCLUDE} \ 51 | --trace --trace-structs \ 52 | --Mdir ${VERILATED_OBJ} \ 53 | ${VERILATOR_OPTIONS} \ 54 | ${CMAKE_CURRENT_SOURCE_DIR}/${ANSWER}.sv 55 | 56 | # Build generated source 57 | # 58 | make -C ${VERILATED_OBJ} -f "V${ANSWER}.mk" 59 | 60 | exit 0 61 | --------------------------------------------------------------------------------