├── .gitignore ├── LICENSE ├── README ├── cortexm_irqs.h ├── efm32 ├── efm32-biggest.ld ├── efm32g.lst ├── efm32gg.lst ├── efm32lg.lst ├── efm32tg.lst └── efm32wg.lst ├── examples ├── Makefile └── example-no-io.c ├── kinetis ├── kl25.ld ├── kl25.lst └── kl25.yaml ├── linkscript.ld ├── lpc ├── lpc800.lst ├── lpc810.ld ├── lpc811.ld └── lpc812.ld ├── nrf51 ├── nrf51.lst └── nrf51822.ld ├── psoc ├── psoc4.ld └── psoc4.lst ├── scripts ├── irqgen-all.sh └── irqgen.py ├── startup.c ├── stm32 ├── stm32-biggest.ld ├── stm32-smallest.ld └── stm32f100.lst └── tm4 └── lm4f120h5qr.ld /.gitignore: -------------------------------------------------------------------------------- 1 | examples/bin-* 2 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Core, MCU-independent startup.c and linkscript.ld are in Public Domain. 2 | 3 | For other files, consult each individually for licensing status (can 4 | be Public Domain or liberal license like BSD). 5 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | cortex-uni-startup is a project to create unified/easily portable startup 2 | code and linker script for any ARM Cortex-M CPUs/MCUs. 3 | 4 | Supported out of the box: 5 | * Basic Cortex-M CPU with standard interrupts 6 | * STElectronics STM32 7 | * Energy Micro EFM32 8 | * Texas Instruments Tiva-C TM4 (former Stellaris LM4) 9 | * NXP LPC800 10 | * Nordic Semi NRF51 11 | * Cypress PSoC4 12 | 13 | New MCU is very easy to add - just use existing code as the example! 14 | 15 | Basic usage example is provided in example/ directory. Note that as this 16 | project deals only with Cortex-M startup, the example does not perform any 17 | I/O operations like LED blinking. If you are interested in I/O and register 18 | mappings for any Cortex-M MCU, please visit sister project 19 | https://github.com/pfalcon/libperipha. 20 | 21 | For advanced usage of both cortex-uni-startup and libperipha, see 22 | https://github.com/pfalcon/PeripheralTemplateLibrary . 23 | -------------------------------------------------------------------------------- /cortexm_irqs.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - IRQ handler declarations for C++ 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky based on article by Vanya Sergeev 7 | * http://dev.frozeneskimo.com/notes/cortex_cmsis/ , GNU ld documentation 8 | * and numerous other public resources. 9 | * 10 | */ 11 | 12 | #ifdef __cplusplus 13 | extern "C" { 14 | #endif 15 | 16 | void Reset_Handler(void); 17 | void NMI_Handler(void); 18 | void HardFault_Handler(void); 19 | void MemManage_Handler(void); 20 | void BusFault_Handler(void); 21 | void UsageFault_Handler(void); 22 | void SVC_Handler(void); 23 | void DebugMon_Handler(void); 24 | void PendSV_Handler(void); 25 | void SysTick_Handler(void); 26 | 27 | #ifdef __cplusplus 28 | } 29 | #endif 30 | -------------------------------------------------------------------------------- /efm32/efm32-biggest.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | MEMORY 11 | { 12 | flash : ORIGIN = 0x00000000, LENGTH = 1M 13 | sram : ORIGIN = 0x20000000, LENGTH = 128K 14 | } 15 | 16 | /* Include main link script. Note: it will be searched in -L paths. */ 17 | INCLUDE linkscript.ld 18 | -------------------------------------------------------------------------------- /efm32/efm32g.lst: -------------------------------------------------------------------------------- 1 | # Energy Micro EFM32 Gecko IRQ list 2 | # d0001_efm32g_reference_manual.pdf p.12 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | DMA 9 | GPIO_EVEN 10 | TIMER0 11 | USART0_RX 12 | USART0_TX 13 | ACMP0 14 | ADC0 15 | DAC0 16 | I2C0 17 | GPIO_ODD 18 | TIMER1 19 | TIMER2 20 | USART1_RX 21 | USART1_TX 22 | USART2_RX 23 | USART2_TX 24 | UART0_RX 25 | UART0_TX 26 | LEUART0 27 | LEUART1 28 | LETIMER0 29 | PCNT0 30 | PCNT1 31 | PCNT2 32 | RTC 33 | CMU 34 | VCMP 35 | LCD 36 | MSC 37 | AES 38 | -------------------------------------------------------------------------------- /efm32/efm32gg.lst: -------------------------------------------------------------------------------- 1 | # Energy Micro EFM32 Giant Gecko IRQ list 2 | # d0053_efm32gg_reference_manual.pdf p.13 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | DMA 9 | GPIO_EVEN 10 | TIMER0 11 | USART0_RX 12 | USART0_TX 13 | USB 14 | ACMP0 15 | ADC0 16 | DAC0 17 | I2C0 18 | I2C1 19 | GPIO_ODD 20 | TIMER1 21 | TIMER2 22 | TIMER3 23 | USART1_RX 24 | USART1_TX 25 | LESENSE 26 | USART2_RX 27 | USART2_TX 28 | UART0_RX 29 | UART0_TX 30 | UART1_RX 31 | UART1_TX 32 | LEUART0 33 | LEUART1 34 | LETIMER0 35 | PCNT0 36 | PCNT1 37 | PCNT2 38 | RTC 39 | BURTC 40 | CMU 41 | VCMP 42 | LCD 43 | MSC 44 | AES 45 | EBI 46 | -------------------------------------------------------------------------------- /efm32/efm32lg.lst: -------------------------------------------------------------------------------- 1 | # Energy Micro EFM32 Leopard Gecko IRQ list 2 | # d0183_efm32lg_reference_manual.pdf p.13 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | DMA 9 | GPIO_EVEN 10 | TIMER0 11 | USART0_RX 12 | USART0_TX 13 | USB 14 | ACMP0 15 | ADC0 16 | DAC0 17 | I2C0 18 | I2C1 19 | GPIO_ODD 20 | TIMER1 21 | TIMER2 22 | TIMER3 23 | USART1_RX 24 | USART1_TX 25 | LESENSE 26 | USART2_RX 27 | USART2_TX 28 | UART0_RX 29 | UART0_TX 30 | UART1_RX 31 | UART1_TX 32 | LEUART0 33 | LEUART1 34 | LETIMER0 35 | PCNT0 36 | PCNT1 37 | PCNT2 38 | RTC 39 | BURTC 40 | CMU 41 | VCMP 42 | LCD 43 | MSC 44 | AES 45 | EBI 46 | -------------------------------------------------------------------------------- /efm32/efm32tg.lst: -------------------------------------------------------------------------------- 1 | # Energy Micro EFM32 Tiny Gecko IRQ list 2 | # d0034_efm32tg_reference_manual.pdf p.12 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | DMA 9 | GPIO_EVEN 10 | TIMER0 11 | USART0_RX 12 | USART0_TX 13 | ACMP0 14 | ADC0 15 | DAC0 16 | I2C0 17 | GPIO_ODD 18 | TIMER1 19 | USART1_RX 20 | USART1_TX 21 | LESENSE 22 | LEUART0 23 | LETIMER0 24 | PCNT0 25 | RTC 26 | CMU 27 | VCMP 28 | LCD 29 | MSC 30 | AES 31 | -------------------------------------------------------------------------------- /efm32/efm32wg.lst: -------------------------------------------------------------------------------- 1 | # Energy Micro EFM32 Wonder Gecko IRQ list 2 | # d0233_efm32wg_reference_manual.pdf p.13 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | DMA 9 | GPIO_EVEN 10 | TIMER0 11 | USART0_RX 12 | USART0_TX 13 | USB 14 | ACMP0 15 | ADC0 16 | DAC0 17 | I2C0 18 | I2C1 19 | GPIO_ODD 20 | TIMER1 21 | TIMER2 22 | TIMER3 23 | USART1_RX 24 | USART1_TX 25 | LESENSE 26 | USART2_RX 27 | USART2_TX 28 | UART0_RX 29 | UART0_TX 30 | UART1_RX 31 | UART1_TX 32 | LEUART0 33 | LEUART1 34 | LETIMER0 35 | PCNT0 36 | PCNT1 37 | PCNT2 38 | RTC 39 | BURTC 40 | CMU 41 | VCMP 42 | LCD 43 | MSC 44 | AES 45 | EBI 46 | EMU 47 | FPUEH 48 | -------------------------------------------------------------------------------- /examples/Makefile: -------------------------------------------------------------------------------- 1 | # Path to cortex-startup toplevel dir 2 | # You can reuse this Makefile for your projects by just updating this var 3 | CORTEX_STARTUP = .. 4 | 5 | CROSS_COMPILE = arm-none-eabi- 6 | GCC_VER = 7 | CC = $(CROSS_COMPILE)gcc$(GCC_VER) 8 | # Target subarch to build for 9 | TARGET = stm32/stm32-smallest 10 | # Name output dir after target. Other alternative for multi-dir projects is 11 | # bin-$(TARGET) 12 | TARGETDIR = bin-$(TARGET) 13 | # Short one-character alias for TARGETDIR 14 | T = $(TARGETDIR) 15 | 16 | STARTUP = $(CORTEX_STARTUP)/startup.c 17 | LINKSCRIPT = $(TARGET).ld 18 | 19 | # Generic target flags which used for both compiling and linking. We compile 20 | # startup code at linking stage, so this may (and sometimes should) contain 21 | # -D defines 22 | TARGET_FLAGS = -mthumb -mcpu=cortex-m3 -DNO_SYSTEMINIT 23 | TARGET_CFLAGS = $(TARGET_FLAGS) 24 | TARGET_LDFLAGS = $(TARGET_FLAGS) --static -nostartfiles -T$(LINKSCRIPT) $(STARTUP) 25 | 26 | CFLAGS = $(TARGET_CFLAGS) 27 | LDFLAGS = $(TARGET_LDFLAGS) -Wl,-Map=$@.map,--cref 28 | # We don't have libs per se, but for includes in linkscripts to work, 29 | # they should be on -L path. 30 | LDLIBS = -L$(CORTEX_STARTUP) 31 | 32 | all: $T/example-no-io 33 | 34 | # This corresponds to a builtin make rule, except puts object files to TARGETDIR 35 | $T/%.o: %.c 36 | mkdir -p $T 37 | $(CC) $(CPPFLAGS) $(CFLAGS) -c $^ -o $@ 38 | 39 | # Add rules for specific applications here 40 | $T/example-no-io: $T/example-no-io.o 41 | $T/example-no-io.o: example-no-io.c 42 | -------------------------------------------------------------------------------- /examples/example-no-io.c: -------------------------------------------------------------------------------- 1 | /* 2 | * This is simple example file which does do any I/O and thus 3 | * can be compiled and run on any Cortex-M MCU. However, to see 4 | * its effect, you'll need to use debugger. 5 | */ 6 | 7 | volatile int var; 8 | 9 | void main() 10 | { 11 | while (1) { 12 | var ^= 0x55; 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /kinetis/kl25.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | /* KL25P80M48SF0RM.pdf p.72, p.105 */ 11 | MEMORY 12 | { 13 | flash : ORIGIN = 0x00000000, LENGTH = 128K 14 | sram : ORIGIN = 0x20000000, LENGTH = 16K 15 | } 16 | 17 | /* Include main link script. Note: it will be searched in -L paths. */ 18 | INCLUDE linkscript.ld 19 | -------------------------------------------------------------------------------- /kinetis/kl25.lst: -------------------------------------------------------------------------------- 1 | # Freescale KL25 series IRQ list 2 | # p.53 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | 0 DMA0 9 | 1 DMA1 10 | 2 DMA2 11 | 3 DMA3 12 | 5 FTFA 13 | 6 PMC 14 | 7 LLWU 15 | 8 I2C0 16 | 9 I2C1 17 | 10 SPI0 18 | 11 SPI1 19 | 12 UART0 20 | 13 UART1 21 | 14 UART2 22 | 15 ADC0 23 | 16 CMP0 24 | 17 TPM0 25 | 18 TPM1 26 | 19 TPM2 27 | 20 RTC_ALARM 28 | 21 RTC_TICK 29 | 22 PIT 30 | 24 USB 31 | 25 DAC0 32 | 26 TSI0 33 | 27 MCG 34 | 28 LPTMR0 35 | 30 GPIO_A 36 | 31 GPIO_D 37 | -------------------------------------------------------------------------------- /kinetis/kl25.yaml: -------------------------------------------------------------------------------- 1 | defaults: 2 | flash: 3 | addr: 0 4 | sram: 5 | # Vendor goes mad aka diversity: p.76 6 | # "The on-chip SRAM is split into two ranges, 1/4 is allocated to SRAM_L and 3/4 is allocated to SRAM_U." 7 | addr: 0x20000000 - size / 4 8 | 9 | MKL25Z32: 10 | flash: {size: 32K} 11 | sram: {size: 4K} 12 | MKL25Z64: 13 | flash: {size: 64K} 14 | sram: {size: 8K} 15 | MKL25Z128: 16 | flash: {size: 128K} 17 | sram: {size: 16K} 18 | -------------------------------------------------------------------------------- /linkscript.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky based on article by Vanya Sergeev 7 | * http://dev.frozeneskimo.com/notes/cortex_cmsis/ , GNU ld documentation 8 | * and numerous other public resources. 9 | * 10 | */ 11 | 12 | ENTRY(Reset_Handler) 13 | 14 | SECTIONS { 15 | 16 | .text : 17 | { 18 | KEEP(*(.vectors)) 19 | KEEP(*(.cortex_vectors)) 20 | KEEP(*(.vendor_vectors)) 21 | *(.text*) 22 | *(.rodata*) 23 | _end_text = .; 24 | } >flash 25 | 26 | /* http://sourceware.org/binutils/docs/ld/Output-Section-LMA.html */ 27 | .data : 28 | { 29 | _start_data = .; 30 | *(.data*) 31 | _end_data = .; 32 | } >sram AT >flash 33 | 34 | .bss : 35 | { 36 | _start_bss = .; 37 | *(.bss*) 38 | *(COMMON) 39 | _end_bss = .; 40 | } >sram 41 | 42 | . = ALIGN(4); 43 | 44 | _start_stack = .; 45 | /* http://sourceware.org/binutils/docs/ld/MEMORY.html */ 46 | PROVIDE(_end_stack = ORIGIN(sram) + LENGTH(sram)); 47 | } 48 | 49 | _end = .; 50 | -------------------------------------------------------------------------------- /lpc/lpc800.lst: -------------------------------------------------------------------------------- 1 | # NXP LPC800 series IRQ list 2 | # UM10601.pdf rev.1.2 p.11 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | 0 SPI0 9 | 1 SPI1 10 | 3 UART0 11 | 4 UART1 12 | 5 UART2 13 | 8 I2C0 14 | 9 SCT 15 | 10 MRT 16 | 11 CMP 17 | 12 WDT 18 | 13 BOD 19 | 15 WKT 20 | 24 PININT0 21 | 25 PININT1 22 | 26 PININT2 23 | 27 PININT3 24 | 28 PININT4 25 | 29 PININT5 26 | 30 PININT6 27 | 31 PININT7 28 | -------------------------------------------------------------------------------- /lpc/lpc810.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | /* UM10601 Ch.2 p.9 */ 11 | MEMORY 12 | { 13 | flash : ORIGIN = 0x00000000, LENGTH = 4K 14 | sram : ORIGIN = 0x10000000, LENGTH = 1K 15 | } 16 | 17 | /* Include main link script. Note: it will be searched in -L paths. */ 18 | INCLUDE linkscript.ld 19 | -------------------------------------------------------------------------------- /lpc/lpc811.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | /* UM10601 Ch.2 p.9 */ 11 | MEMORY 12 | { 13 | flash : ORIGIN = 0x00000000, LENGTH = 8K 14 | sram : ORIGIN = 0x10000000, LENGTH = 2K 15 | } 16 | 17 | /* Include main link script. Note: it will be searched in -L paths. */ 18 | INCLUDE linkscript.ld 19 | -------------------------------------------------------------------------------- /lpc/lpc812.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | /* UM10601 Ch.2 p.9 */ 11 | MEMORY 12 | { 13 | flash : ORIGIN = 0x00000000, LENGTH = 16K 14 | sram : ORIGIN = 0x10000000, LENGTH = 4K 15 | } 16 | 17 | /* Include main link script. Note: it will be searched in -L paths. */ 18 | INCLUDE linkscript.ld 19 | -------------------------------------------------------------------------------- /nrf51/nrf51.lst: -------------------------------------------------------------------------------- 1 | # Nordic Semi nRF51822 IRQ list 2 | # nRF51_Reference_manual v1.1.pdf p.12 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | 0 POWER_CLOCK 9 | 1 RADIO 10 | 2 UART0 11 | 3 SPI0_TWI0 12 | 4 SPI1_TWI1 13 | 6 GPIOTE 14 | 7 ADC 15 | 8 TIMER0 16 | 9 TIMER1 17 | 10 TIMER2 18 | 11 RTC0 19 | 12 TEMP 20 | 13 RNG 21 | 14 ECB 22 | 15 CCM_AAR 23 | 16 WDT 24 | 17 RTC1 25 | 18 QDEC 26 | 30 NVMC 27 | 31 PPI 28 | -------------------------------------------------------------------------------- /nrf51/nrf51822.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | MEMORY 11 | { 12 | flash : ORIGIN = 0x00000000, LENGTH = 256K /* There's also variant with 128K */ 13 | sram : ORIGIN = 0x20000000, LENGTH = 16K 14 | } 15 | 16 | /* Include main link script. Note: it will be searched in -L paths. */ 17 | INCLUDE linkscript.ld 18 | -------------------------------------------------------------------------------- /psoc/psoc4.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | * Reference: PSoC4_Architecture_TRM_001-85634_0C_V.pdf 9 | */ 10 | 11 | MEMORY 12 | { 13 | flash : ORIGIN = 0x00000000, LENGTH = 32K 14 | sram : ORIGIN = 0x20000000, LENGTH = 4K 15 | } 16 | 17 | /* Include main link script. Note: it will be searched in -L paths. */ 18 | INCLUDE linkscript.ld 19 | -------------------------------------------------------------------------------- /psoc/psoc4.lst: -------------------------------------------------------------------------------- 1 | # Cypress PSoC4 IRQ list 2 | # PSoC4 Architecture_TRM_001-85634_0A.pdf p.41 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | 0 GPIOP0 9 | 1 GPIOP1 10 | 2 GPIOP2 11 | 3 GPIOP3 12 | 4 GPIOP4 13 | 8 LPCOMP 14 | 9 WDT 15 | 10 SCB1 16 | 11 SCB2 17 | 12 SPC 18 | 13 PWR 19 | 14 SAR 20 | 15 CSD 21 | 16 TCPWM0 22 | 17 TCPWM1 23 | 18 TCPWM2 24 | 19 TCPWM3 25 | -------------------------------------------------------------------------------- /scripts/irqgen-all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | find .. -name "*.lst" | tee /dev/stderr | xargs -n1 ./irqgen.py 4 | -------------------------------------------------------------------------------- /scripts/irqgen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import sys 3 | import os 4 | 5 | 6 | irqs = [] 7 | f = open(sys.argv[1]) 8 | no = 0 9 | for l in f: 10 | l = l.strip() 11 | if l[0] == "#": 12 | continue 13 | fields = [f.strip() for f in l.split()] 14 | assert len(fields) <= 2 15 | if len(fields) == 2: 16 | fields[0] = int(fields[0]) 17 | else: 18 | fields = [no, fields[0]] 19 | no += 1 20 | irqs.append(fields) 21 | 22 | dir, fname = os.path.split(sys.argv[1]) 23 | fout = open(dir + "/startup-" + fname.rsplit('.', 1)[0] + ".c", "w") 24 | print >>fout, '#include "../startup.c"' 25 | print >>fout 26 | 27 | for i in irqs: 28 | print >>fout, 'void %s_IRQHandler(void) ALIAS("Dummy_Handler");' % i[1] 29 | 30 | 31 | print >>fout 32 | 33 | print >>fout, 'void *vendor_vector_table[] __attribute__ ((section(".vendor_vectors"))) = {' 34 | no = 0 35 | for i in irqs: 36 | if no != i[0]: 37 | # Gap detected 38 | assert no < i[0], "Interrupt numbers are not in increasing sequence" 39 | while no < i[0]: 40 | print >>fout, '0,' 41 | no += 1 42 | 43 | assert i[0] == no 44 | print >>fout, '%s_IRQHandler,' % i[1] 45 | no += 1 46 | 47 | print >>fout, '};' 48 | -------------------------------------------------------------------------------- /startup.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - C startup file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky based on article by Vanya Sergeev 7 | * http://dev.frozeneskimo.com/notes/cortex_cmsis/ , GNU ld documentation 8 | * and numerous other public resources. 9 | * 10 | */ 11 | 12 | #include 13 | 14 | /* Declare linker-defined symbols. The only thing of interest 15 | regarding these symbols is their *address*. uint32_t hints 16 | of alignment. */ 17 | extern uint32_t _end_text; 18 | extern uint32_t _start_data; 19 | extern uint32_t _end_data; 20 | extern uint32_t _start_bss; 21 | extern uint32_t _end_bss; 22 | extern uint32_t _start_stack; 23 | extern uint32_t _end_stack; 24 | 25 | /* C main function */ 26 | extern int main(void); 27 | /* Device-specific initialization function. Optional, any Cortex-M 28 | should be able to start up in its default mode on its own, though 29 | some may have errata for some peripherals (including PLL) which 30 | this function may "patch". */ 31 | extern void SystemInit(void); 32 | 33 | void Dummy_Handler(void); 34 | 35 | /* Cortex-M core interrupt handlers */ 36 | #define ALIAS(sym) __attribute__((weak, alias (sym))) 37 | 38 | void Reset_Handler(void); 39 | void NMI_Handler(void) ALIAS("Dummy_Handler"); 40 | void HardFault_Handler(void) ALIAS("Dummy_Handler"); 41 | void MemManage_Handler(void) ALIAS("Dummy_Handler"); 42 | void BusFault_Handler(void) ALIAS("Dummy_Handler"); 43 | void UsageFault_Handler(void) ALIAS("Dummy_Handler"); 44 | void SVC_Handler(void) ALIAS("Dummy_Handler"); 45 | void DebugMon_Handler(void) ALIAS("Dummy_Handler"); 46 | void PendSV_Handler(void) ALIAS("Dummy_Handler"); 47 | void SysTick_Handler(void) ALIAS("Dummy_Handler"); 48 | 49 | 50 | /* 16 standard Cortex-M vectors - these are present in every MCU */ 51 | void *core_vector_table[16] __attribute__ ((section(".cortex_vectors"))) = { 52 | // See http://sourceware.org/binutils/docs/ld/Source-Code-Reference.html 53 | // why the address is used here (if not intuitive) 54 | &_end_stack, 55 | Reset_Handler, 56 | NMI_Handler, 57 | HardFault_Handler, 58 | MemManage_Handler, 59 | BusFault_Handler, 60 | UsageFault_Handler, 61 | 0, 62 | 0, 63 | 0, 64 | 0, 65 | SVC_Handler, 66 | DebugMon_Handler, 67 | 0, 68 | PendSV_Handler, 69 | SysTick_Handler, 70 | }; 71 | 72 | /* Based on http://sourceware.org/binutils/docs/ld/Output-Section-LMA.html */ 73 | void Reset_Handler(void) { 74 | register uint32_t *src, *dst; 75 | 76 | /* Copy data section from flash to RAM */ 77 | src = &_end_text; 78 | dst = &_start_data; 79 | while (dst < &_end_data) 80 | *dst++ = *src++; 81 | 82 | /* Clear the bss section, assumes .bss goes directly after .data */ 83 | dst = &_start_bss; 84 | while (dst < &_end_bss) 85 | *dst++ = 0; 86 | 87 | #ifndef NO_SYSTEMINIT 88 | SystemInit(); 89 | #endif 90 | main(); 91 | while (1); 92 | } 93 | 94 | void Dummy_Handler(void) { 95 | /* Receiving an unexpected interrupt is considered a bug 96 | in the program. Let's make it very visible by just 97 | hanging the processing. Ignoring it by just returning 98 | may result in very complicated debugging sessions. */ 99 | while (1); 100 | } 101 | -------------------------------------------------------------------------------- /stm32/stm32-biggest.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | MEMORY 11 | { 12 | flash : ORIGIN = 0x08000000, LENGTH = 1M /* They say 1M devices have 2 banks of 512K, go figure */ 13 | sram : ORIGIN = 0x20000000, LENGTH = 96K 14 | } 15 | 16 | /* Include main link script. Note: it will be searched in -L paths. */ 17 | INCLUDE linkscript.ld 18 | -------------------------------------------------------------------------------- /stm32/stm32-smallest.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | MEMORY 11 | { 12 | flash : ORIGIN = 0x08000000, LENGTH = 16K 13 | sram : ORIGIN = 0x20000000, LENGTH = 4K 14 | } 15 | 16 | /* Include main link script. Note: it will be searched in -L paths. */ 17 | INCLUDE linkscript.ld 18 | -------------------------------------------------------------------------------- /stm32/stm32f100.lst: -------------------------------------------------------------------------------- 1 | # STM32F100 IRQ list 2 | # CD00246267 RM0041 DocID 16188 Rev 4 p.129 3 | # 4 | # This file is in public domain 5 | # 6 | # Put together by Paul Sokolovsky 7 | # 8 | 0 WWDG 9 | 1 PVD 10 | 2 TAMPER_STAMP 11 | 3 RTC_WKUP 12 | 4 FLASH 13 | 5 RCC 14 | 6 EXTI0 15 | 7 EXTI1 16 | 8 EXTI2 17 | 9 EXTI3 18 | 10 EXTI4 19 | 11 DMA1_Channel1 20 | 12 DMA1_Channel2 21 | 13 DMA1_Channel3 22 | 14 DMA1_Channel4 23 | 15 DMA1_Channel5 24 | 16 DMA1_Channel6 25 | 17 DMA1_Channel7 26 | 18 ADC1 27 | 23 EXTI9_5 28 | 24 TIM1_BRK_TIM15 29 | 25 TIM1_UP_TIM16 30 | 26 TIM1_TRG_COM_TIM17 31 | 27 TIM1_CC 32 | 28 TIM2 33 | 29 TIM3 34 | 30 TIM4 35 | 31 I2C1_EV 36 | 32 I2C1_ER 37 | 33 I2C2_EV 38 | 34 I2C2_ER 39 | 35 SPI1 40 | 36 SPI2 41 | 37 USART1 42 | 38 USART2 43 | 39 USART3 44 | 40 EXTI15_10 45 | 41 RTC_Alarm 46 | 42 CEC 47 | 43 TIM12 48 | 44 TIM13 49 | 45 TIM14 50 | 48 FSMC 51 | 50 TIM5 52 | 51 SPI3 53 | 52 UART4 54 | 53 UART5 55 | 54 TIM6_DAC 56 | 55 TIM7 57 | 56 DMA2_Channel1 58 | 57 DMA2_Channel2 59 | 58 DMA2_Channel3 60 | 59 DMA2_Channel4_5 61 | 60 DMA2_Channel5 62 | -------------------------------------------------------------------------------- /tm4/lm4f120h5qr.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Unified Cortex Startup - GNU ld linker script file 3 | * 4 | * This file is in public domain 5 | * 6 | * Put together by Paul Sokolovsky 7 | * 8 | */ 9 | 10 | MEMORY 11 | { 12 | flash : ORIGIN = 0x00000000, LENGTH = 256K 13 | sram : ORIGIN = 0x20000000, LENGTH = 32K 14 | } 15 | 16 | /* Include main link script. Note: it will be searched in -L paths. */ 17 | INCLUDE linkscript.ld 18 | --------------------------------------------------------------------------------