├── .gitattributes ├── Pocket ├── dist │ ├── Assets │ │ └── playstation │ │ │ └── common │ │ │ ├── rom.bin_dummy │ │ │ └── scph5500.bin_dummy │ ├── Cores │ │ └── pgate1.PlayStation │ │ │ ├── audio.json │ │ │ ├── input.json │ │ │ ├── variants.json │ │ │ ├── bitstream.rbf_r │ │ │ ├── interact.json │ │ │ ├── info.txt │ │ │ ├── video.json │ │ │ ├── data.json │ │ │ └── core.json │ └── Platforms │ │ ├── _images │ │ └── playstation.bin │ │ └── playstation.json ├── core.sflp ├── ap_core.fit.summary ├── usage.txt └── core_top.v ├── PAD.sflp ├── ADSR.sflp ├── Timer.sflp ├── mul_s11.v ├── mul_s16.v ├── mul_s17.v ├── mul_s32.v ├── mul_u32.v ├── Cache_IR.sflp ├── DMA_SPU.sflp ├── R3000A.sflp ├── VGA_ctrl.sflp ├── div_u32.sflp ├── drawPoly.sflp ├── drawRect.sflp ├── dsp_ch.sflp ├── mul_s16s8.v ├── mul_s18s16.v ├── mul_s26s16.v ├── reverb.sflp ├── demo ├── mul_s10.v ├── demo_core.sflp ├── Makefile ├── cos_table.sflp └── sin_table.sflp ├── ram_8x2352.sflp ├── Cache_Texture.sflp ├── DE0-CV ├── core.sflp ├── PlayStation_top.v └── PlayStation.sdc ├── DE2-115 ├── core.sflp ├── PlayStation.sof ├── PlayStation_top.v ├── quartus_start.bat ├── configure.bat ├── PlayStation.fit.summary ├── PlayStation.sdc └── PlayStation.qsf ├── RateTableAdd_rom.v ├── RateTableSub_rom.v ├── drawFillRect.sflp ├── img ├── v_TobalNo1.jpg ├── 20230318_XI.jpg ├── PS_20210225_ok.jpg ├── v_SagaFrontier2.jpg ├── 20230129_Dewprism.jpg ├── 20230203_RayStorm.jpg ├── 20230129_Einhander.jpg ├── 20250228_RockmanX6.jpg ├── 20250909_OmegaBoost.jpg ├── 20251129_Musashiden.jpg ├── 20251129_Xenogears.jpg ├── 20230318_VagrantStory.jpg ├── 20230201_MetalGearSolid.jpg ├── 20250228_ValkyrieProfile.jpg ├── 20230202_IsInternalSection.jpg └── 20251129_SeikenDensetsuLoM.jpg ├── PAD_controller.sflp ├── RateTableAdd_f_rom.v ├── RateTableSub_f_rom.v ├── CDROM_controller.sflp ├── DDS_50to33868800.sflp ├── PlayStation_core.sflp ├── SoundProcessingUnit.sflp ├── DigitalSignalProcessor.sflp ├── GraphicProcessingUnit.sflp ├── GeometryTransformationEngine.sflp ├── bcd_btoi.v ├── dsdac10.sflp ├── bcd_itob.v ├── ram_16x32k.sflp ├── ram_320x240x15.sflp ├── compare_s11.v ├── bsr_s16.sflp ├── bsr_s24.sflp ├── bsr_s32.sflp ├── LICENSE ├── Scratchpad.sflp ├── DMA_OTC.sflp ├── Makefile ├── DMA_CDR.sflp ├── view_ram_ctrl.sflp ├── gte_DIVIDE.sflp ├── README.md ├── MDEC.sflp ├── gte_LIMIT.sflp ├── DMA_GPU.sflp └── inv_table.sflp /.gitattributes: -------------------------------------------------------------------------------- 1 | *.sflp linguist-language=C 2 | -------------------------------------------------------------------------------- /Pocket/dist/Assets/playstation/common/rom.bin_dummy: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Pocket/dist/Assets/playstation/common/scph5500.bin_dummy: -------------------------------------------------------------------------------- 1 | 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[] 5 | } 6 | } -------------------------------------------------------------------------------- /Pocket/dist/Cores/pgate1.PlayStation/bitstream.rbf_r: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pgate1/PlayStation_on_FPGA/HEAD/Pocket/dist/Cores/pgate1.PlayStation/bitstream.rbf_r -------------------------------------------------------------------------------- /Pocket/dist/Cores/pgate1.PlayStation/interact.json: -------------------------------------------------------------------------------- 1 | { 2 | "interact": { 3 | "magic": "APF_VER_1", 4 | "variables": [], 5 | "messages": [] 6 | } 7 | } -------------------------------------------------------------------------------- /bcd_btoi.v: -------------------------------------------------------------------------------- 1 | 2 | module bcd_btoi( 3 | input [7:0] bcd, 4 | output [7:0] bin, 5 | input con 6 | ); 7 | 8 | assign bin = ({4'h0, bcd[7:4]} * 8'h0A) + {4'h0, bcd[3:0]}; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /Pocket/dist/Platforms/playstation.json: -------------------------------------------------------------------------------- 1 | { 2 | "platform": { 3 | "category": "Console", 4 | "name": "PlayStation", 5 | "year": 1994, 6 | "manufacturer": "Sony Computer Entertainment" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /Pocket/dist/Cores/pgate1.PlayStation/info.txt: -------------------------------------------------------------------------------- 1 | PlayStation on FPGA feat. Analogue Pocket 2 | 3 | This is a port of the basic functions of the first PlayStation to Analogue Pocket. 4 | Sound and movie functions have been left out to fit in Pocket's FPGA. 5 | -------------------------------------------------------------------------------- /DE2-115/configure.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | set PATH=%QUARTUS_ROOTDIR%\bin64;%QUARTUS_ROOTDIR%\bin32;%QUARTUS_ROOTDIR%\bin;%PATH% 4 | 5 | quartus_pgm.exe -c "USB-Blaster" -m JTAG -o p;output_files\PlayStation.sof 6 | 7 | echo Press any key to finish. 8 | pause > nul 9 | -------------------------------------------------------------------------------- /dsdac10.sflp: -------------------------------------------------------------------------------- 1 | 2 | // Delta Sigma Converter 3 | 4 | circuit dsdac10 5 | { 6 | input DACin<10>; 7 | output DACout; 8 | 9 | reg_wr sigma<12>; // +2 10 | sel delta<12>; // +2 11 | 12 | delta = sigma<11> || sigma<11> || DACin; 13 | sigma += delta; 14 | DACout = sigma<11>; 15 | } 16 | 17 | -------------------------------------------------------------------------------- /bcd_itob.v: -------------------------------------------------------------------------------- 1 | 2 | module bcd_itob( 3 | input [7:0] bin, 4 | output [7:0] bcd, 5 | input con 6 | ); 7 | 8 | wire [7:0] bcd_0; 9 | wire [7:0] bcd_1; 10 | 11 | assign bcd_0 = bin % 8'h0A; 12 | assign bcd_1 = bin / 8'h0A; 13 | 14 | assign bcd[3:0] = bcd_0[3:0]; 15 | assign bcd[7:4] = bcd_1[3:0]; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /ram_16x32k.sflp: -------------------------------------------------------------------------------- 1 | 2 | // test RAM 3 | // 16bit 32k depth 4 | 5 | circuit ram_16x32k 6 | { 7 | input adrs<15>, din<16>; 8 | output dout<16>; 9 | instrin read(adrs), write(adrs, din); 10 | 11 | mem cells[32768]<16>; 12 | reg dout_reg<16>; 13 | 14 | instruct read dout_reg := cells[adrs]; 15 | dout = dout_reg; 16 | 17 | instruct write cells[adrs] := din; 18 | 19 | } 20 | -------------------------------------------------------------------------------- /Pocket/dist/Cores/pgate1.PlayStation/video.json: -------------------------------------------------------------------------------- 1 | { 2 | "video": { 3 | "magic": "APF_VER_1", 4 | "scaler_modes": [ 5 | { 6 | "width": 640, 7 | "height": 480, 8 | "aspect_w": 4, 9 | "aspect_h": 3, 10 | "rotation": 0, 11 | "mirror": 0 12 | } 13 | ] 14 | } 15 | } -------------------------------------------------------------------------------- /ram_320x240x15.sflp: -------------------------------------------------------------------------------- 1 | 2 | // test VRAM 3 | // 320x240 15bit 4 | // x<9>, y<8> 5 | 6 | circuit ram_320x240x15 7 | { 8 | input adrs<17>, din<15>; 9 | output dout<15>; 10 | instrin read(adrs), write(adrs, din); 11 | 12 | // 76800 / 0x1380(4992) = 13 | mem cells[320*240]<15>; 14 | reg dout_reg<15>; 15 | 16 | instruct read dout_reg := cells[adrs]; 17 | dout = dout_reg; 18 | 19 | instruct write cells[adrs] := din; 20 | } 21 | -------------------------------------------------------------------------------- /demo/Makefile: -------------------------------------------------------------------------------- 1 | .SUFFIXES: .sflp .sfl .h .v 2 | 3 | SFLP = demo_core.sflp sin_table.sflp cos_table.sflp 4 | SFLS = $(SFLP:.sflp=.sfl) 5 | HEAD = $(SFLP:.sflp=.h) 6 | VLOG = $(SFLS:.sfl=.v) 7 | 8 | MAKEFLAGS += --no-print-directory 9 | 10 | sfl2vl: 11 | make sfl 12 | make vl 13 | verilator --lint-only demo.v 14 | # ok 15 | 16 | sfl: $(SFLS) 17 | 18 | vl: $(VLOG) 19 | 20 | .sflp.sfl: 21 | sflp $< $@ 22 | 23 | .sfl.v: 24 | sfl2vl $< -O2 25 | 26 | clean: 27 | rm -f $(SFLP:.sflp=.sfl) $(SFLP:.sflp=.h) $(SFLS:.sfl=.v) 28 | 29 | -------------------------------------------------------------------------------- /compare_s11.v: -------------------------------------------------------------------------------- 1 | 2 | module compare_s11 ( 3 | a, b, gt, lt, gte, lte, result 4 | ); 5 | input signed [10:0] a, b; 6 | input gt, lt, gte, lte; 7 | output wire result; 8 | 9 | assign result = 10 | (gt & (a > b)) | 11 | (lt & (a < b)) | 12 | (gte & (a >= b)) | 13 | (lte & (a <= b)); 14 | 15 | /* 16 | output reg result; 17 | always @* begin 18 | case (1'b1) 19 | gt : result = a > b; 20 | lt : result = a < b; 21 | gte : result = a >= b; 22 | lte : result = a <= b; 23 | endcase 24 | end 25 | */ 26 | endmodule 27 | -------------------------------------------------------------------------------- /bsr_s16.sflp: -------------------------------------------------------------------------------- 1 | 2 | // Barrel Shifter Right signed 16 bit 3 | 4 | circuit bsr_s16 5 | { 6 | input din<16>, shift<4>; 7 | output dout<16>; 8 | instrin con(din, shift); 9 | 10 | sel bs0<16>, bs1<16>, bs2<16>; 11 | 12 | any{ 13 | shift<0> : bs0 = 16#din<15:1>; 14 | else : bs0 = din; 15 | } 16 | any{ 17 | shift<1> : bs1 = 16#bs0<15:2>; 18 | else : bs1 = bs0; 19 | } 20 | any{ 21 | shift<2> : bs2 = 16#bs1<15:4>; 22 | else : bs2 = bs1; 23 | } 24 | any{ 25 | shift<3> : dout = 16#bs2<15:8>; 26 | else : dout = bs2; 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /bsr_s24.sflp: -------------------------------------------------------------------------------- 1 | 2 | // Barrel Shifter Right Signed 24 bit 3 | 4 | circuit bsr_s24 5 | { 6 | input din<24>, shift<4>; 7 | output dout<24>; 8 | instrin con(din, shift); 9 | 10 | sel bs0<24>, bs1<24>, bs2<24>; 11 | 12 | any{ 13 | shift<0> : bs0 = 24#din<23:1>; 14 | else : bs0 = din; 15 | } 16 | any{ 17 | shift<1> : bs1 = 24#bs0<23:2>; 18 | else : bs1 = bs0; 19 | } 20 | any{ 21 | shift<2> : bs2 = 24#bs1<23:4>; 22 | else : bs2 = bs1; 23 | } 24 | any{ 25 | shift<3> : dout = 24#bs2<23:8>; 26 | else : dout = bs2; 27 | } 28 | 29 | } 30 | -------------------------------------------------------------------------------- /bsr_s32.sflp: -------------------------------------------------------------------------------- 1 | 2 | // Barrel Shifter Right signed 32 bit 3 | 4 | circuit bsr_s32 5 | { 6 | input din<32>, shift<5>; 7 | output dout<32>; 8 | instrin con(din, shift); 9 | 10 | sel bs0<32>, bs1<32>, bs2<32>, bs3<32>; 11 | 12 | any{ 13 | shift<0> : bs0 = 32#din<31:1>; 14 | else : bs0 = din; 15 | } 16 | any{ 17 | shift<1> : bs1 = 32#bs0<31:2>; 18 | else : bs1 = bs0; 19 | } 20 | any{ 21 | shift<2> : bs2 = 32#bs1<31:4>; 22 | else : bs2 = bs1; 23 | } 24 | any{ 25 | shift<3> : bs3 = 32#bs2<31:8>; 26 | else : bs3 = bs2; 27 | } 28 | any{ 29 | shift<4> : dout = 32#bs3<31:16>; 30 | else : dout = bs3; 31 | } 32 | 33 | } 34 | -------------------------------------------------------------------------------- /Pocket/dist/Cores/pgate1.PlayStation/data.json: -------------------------------------------------------------------------------- 1 | { 2 | "data": { 3 | "magic": "APF_VER_1", 4 | "data_slots": [ 5 | { 6 | "name": "BIOS", 7 | "id": "0x20", 8 | "required": false, 9 | "parameters": "0x008", 10 | "deferload": true, 11 | "filename": "scph5500.bin", 12 | "size_exact": 524288, 13 | "address": "0x00000000" 14 | }, 15 | { 16 | "name": "ROM", 17 | "id": "0x40", 18 | "required": true, 19 | "parameters": "0x008", 20 | "deferload": true, 21 | "extensions": ["bin", "img", "exe"], 22 | "size_maximum": "0x40000000", 23 | "address": "0x00080000" 24 | } 25 | ] 26 | } 27 | } -------------------------------------------------------------------------------- /DE2-115/PlayStation.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Sat Apr 02 15:07:03 2022 2 | Quartus II 64-Bit Version : 13.1.4 Build 182 03/12/2014 SJ Web Edition 3 | Revision Name : PlayStation 4 | Top-level Entity Name : PlayStation_top 5 | Family : Cyclone IV E 6 | Device : EP4CE115F29C7 7 | Timing Models : Final 8 | Total logic elements : 73,305 / 114,480 ( 64 % ) 9 | Total combinational functions : 69,884 / 114,480 ( 61 % ) 10 | Dedicated logic registers : 23,908 / 114,480 ( 21 % ) 11 | Total registers : 23994 12 | Total pins : 340 / 529 ( 64 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 2,542,464 / 3,981,312 ( 64 % ) 15 | Embedded Multiplier 9-bit elements : 416 / 532 ( 78 % ) 16 | Total PLLs : 1 / 4 ( 25 % ) 17 | -------------------------------------------------------------------------------- /Pocket/ap_core.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Wed Dec 03 21:31:10 2025 2 | Quartus Prime Version : 18.1.1 Build 646 04/11/2019 Patches 1.18std SJ Lite Edition 3 | Revision Name : ap_core 4 | Top-level Entity Name : apf_top 5 | Family : Cyclone V 6 | Device : 5CEBA4F23C8 7 | Timing Models : Final 8 | Logic utilization (in ALMs) : 17,060 / 18,480 ( 92 % ) 9 | Total registers : 13386 10 | Total pins : 224 / 224 ( 100 % ) 11 | Total virtual pins : 0 12 | Total block memory bits : 2,406,963 / 3,153,920 ( 76 % ) 13 | Total RAM Blocks : 307 / 308 ( 100 % ) 14 | Total DSP Blocks : 58 / 66 ( 88 % ) 15 | Total HSSI RX PCSs : 0 16 | Total HSSI PMA RX Deserializers : 0 17 | Total HSSI TX PCSs : 0 18 | Total HSSI PMA TX Serializers : 0 19 | Total PLLs : 1 / 4 ( 25 % ) 20 | Total DLLs : 0 / 4 ( 0 % ) 21 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 pgate1 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Pocket/dist/Cores/pgate1.PlayStation/core.json: -------------------------------------------------------------------------------- 1 | { 2 | "core": { 3 | "magic": "APF_VER_1", 4 | "metadata": { 5 | "platform_ids": ["playstation"], 6 | "shortname": "PlayStation", 7 | "description": "PlayStation on FPGA feat. Pocket", 8 | "author": "pgate1", 9 | "url": "https://github.com/pgate1/PlayStation_on_FPGA", 10 | "version": "0.3.1", 11 | "date_release": "2025-11-30" 12 | }, 13 | "framework": { 14 | "target_product": "Analogue Pocket", 15 | "version_required": "1.1", 16 | "sleep_supported": false, 17 | "dock": { 18 | "supported": true, 19 | "analog_output": false 20 | }, 21 | "hardware": { 22 | "link_port": false, 23 | "cartridge_adapter": -1 24 | } 25 | }, 26 | "cores": [ 27 | { 28 | "name": "default", 29 | "id": 0, 30 | "filename": "bitstream.rbf_r" 31 | } 32 | ] 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /Scratchpad.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | Scratchpad 3 | by pgate1 4 | */ 5 | 6 | circuit Scratchpad 7 | { 8 | input A<10>, Din<32>, Word<3>; 9 | instrin read(A), write(A, Din, Word); 10 | output Dout<32>; 11 | reg Dout0_reg<8>, Dout1_reg<8>, Dout2_reg<8>, Dout3_reg<8>; 12 | 13 | mem ram0[256]<8>, ram1[256]<8>, ram2[256]<8>, ram3[256]<8>; 14 | 15 | sel index<8>; 16 | index = A<9:2>; 17 | 18 | instruct read par{ 19 | Dout0_reg := ram0[index]; 20 | Dout1_reg := ram1[index]; 21 | Dout2_reg := ram2[index]; 22 | Dout3_reg := ram3[index]; 23 | } 24 | Dout = Dout3_reg || Dout2_reg || Dout1_reg || Dout0_reg; 25 | 26 | instruct write par{ 27 | any{ 28 | Word==1 : any{ 29 | A<1:0>==0b00 : ram0[index] := Din<7:0>; 30 | A<1:0>==0b01 : ram1[index] := Din<7:0>; 31 | A<1:0>==0b10 : ram2[index] := Din<7:0>; 32 | A<1:0>==0b11 : ram3[index] := Din<7:0>; 33 | } 34 | Word==2 : any{ 35 | A<1>==0b0 : par{ 36 | ram0[index] := Din< 7:0>; 37 | ram1[index] := Din<15:8>; 38 | } 39 | else : par{ 40 | ram2[index] := Din< 7:0>; 41 | ram3[index] := Din<15:8>; 42 | } 43 | } 44 | else : par{ // Word==4 45 | ram0[index] := Din< 7: 0>; 46 | ram1[index] := Din<15: 8>; 47 | ram2[index] := Din<23:16>; 48 | ram3[index] := Din<31:24>; 49 | } 50 | } 51 | } 52 | 53 | } 54 | -------------------------------------------------------------------------------- /DMA_OTC.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | DMA for OTC 3 | by pgate1 4 | */ 5 | 6 | circuit DMA_OTC 7 | { 8 | input DmaMADR_6<32>, DmaBCR_6<32>; 9 | 10 | output A<21>, D<32>; 11 | instrout wram_write(A, D); 12 | 13 | instrin Execute; 14 | instrin wram_ack; 15 | output running; 16 | 17 | instrin run33; 18 | sel int_wait_max<16>; 19 | reg_wr count_rst; 20 | instrout interrupt; 21 | output int_waiting; 22 | 23 | instrself halt(h_code); 24 | sel h_code<8>; 25 | reg_wr h_code_reg<8>; 26 | output halt_code<8>; 27 | 28 | output dbg<32>; 29 | //reg_wr count<16>; 30 | //input dbg_in<16>; 31 | 32 | stage_name run_dma { task do(); } 33 | stage_name int_wait { task do(count_rst); } 34 | 35 | running = 36 | // Execute | 37 | run_dma.do; 38 | 39 | instruct halt h_code_reg := h_code; 40 | halt_code = h_code_reg; 41 | 42 | //dbg = 0x0000||count; 43 | 44 | instruct Execute par{ 45 | generate run_dma.do(); 46 | } 47 | 48 | int_wait_max = DmaBCR_6<15:0>; 49 | 50 | int_waiting = int_wait.do; 51 | 52 | stage run_dma { 53 | reg bcr<16>, madr<21>; 54 | first_state st1; 55 | state st1 par{ 56 | madr := DmaMADR_6<20:2> || 0b00; 57 | bcr := DmaBCR_6<15:0>; 58 | if(DmaBCR_6==0) goto st3; 59 | else goto st2; 60 | } 61 | state st2 if(wram_ack){ 62 | wram_write(madr, 0x00||((0b000||madr)-4)); 63 | madr -= 4; 64 | bcr--; 65 | if(bcr==1) goto st3; 66 | } 67 | state st3 if(wram_ack){ 68 | wram_write(madr+4, 0x00FFFFFF); 69 | goto st4; 70 | } 71 | state st4 if(wram_ack){ 72 | generate int_wait.do(0b1); 73 | goto st1; 74 | finish; 75 | } 76 | } 77 | 78 | stage int_wait { 79 | reg int_wait_count<16>; 80 | first_state st1; 81 | state st1 par{ 82 | int_wait_count := int_wait_max; 83 | count_rst := 0b0; 84 | if(count_rst) goto st2; 85 | } 86 | state st2 if(run33){ 87 | int_wait_count--; 88 | if(int_wait_count==0){ 89 | interrupt(); 90 | goto st1; 91 | finish; 92 | } 93 | if(count_rst) goto st1; 94 | } 95 | } 96 | 97 | } 98 | -------------------------------------------------------------------------------- /DE0-CV/PlayStation.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name inclk50 -period 50MHz [get_ports CLOCK_50] 2 | 3 | #set clk_sdram_device {sdram_pll_100_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} 4 | #set clk_sdram_ctrl {sdram_pll_100_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} 5 | 6 | create_generated_clock -name clk_core -source [get_ports {CLOCK_50}] [get_pins {sdram_pll_100_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 7 | create_generated_clock -name clk_sdram_ctrl -source [get_ports {CLOCK_50}] -multiply_by 2 [get_pins {sdram_pll_100_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] 8 | create_generated_clock -name clk_sdram_device -source [get_ports {CLOCK_50}] -multiply_by 2 -phase -3.000 [get_pins {sdram_pll_100_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] 9 | 10 | derive_pll_clocks 11 | derive_clock_uncertainty 12 | 13 | set_false_path -from inclk50 -to clk_sdram_device 14 | set_false_path -from inclk50 -to clk_sdram_ctrl 15 | set_false_path -from clk_sdram_ctrl -to inclk50 16 | set_false_path -from clk_sdram_device 17 | #set_false_path -from clk_sdram_ctrl -to clk_core 18 | #set_false_path -from clk_core -to clk_sdram_ctrl 19 | 20 | set PERIOD 20 21 | set tSetUp 13 22 | set tHold 3 23 | set_input_delay -clock inclk50 -max [expr $PERIOD - $tSetUp] [all_inputs] 24 | set_input_delay -clock inclk50 -min [expr $tHold] [all_inputs] 25 | set tCOMAX 18 26 | set tCOMIN 1 27 | set_output_delay -clock inclk50 -max [expr $PERIOD - $tCOMAX] [all_outputs] 28 | set_output_delay -clock inclk50 -min [expr -$tCOMIN] [all_outputs] 29 | 30 | set_output_delay -clock clk_sdram_device -max 1.5ns [get_ports {DRAM_ADDR* DRAM_BA* DRAM_CKE DRAM_RAS_N DRAM_CAS_N DRAM_CS_N DRAM_WE_N DRAM_LDQM DRAM_UDQM}] 31 | set_output_delay -clock clk_sdram_device -min -4.8ns [get_ports {DRAM_ADDR* DRAM_BA* DRAM_CKE DRAM_RAS_N DRAM_CAS_N DRAM_CS_N DRAM_WE_N DRAM_LDQM DRAM_UDQM}] 32 | set_input_delay -clock clk_sdram_device -max 5.4ns -add_delay [get_ports {DRAM_DQ[*]}] 33 | set_input_delay -clock clk_sdram_device -min 2.7ns -add_delay [get_ports {DRAM_DQ[*]}] 34 | set_output_delay -clock clk_sdram_device -max 1.5ns -add_delay [get_ports {DRAM_DQ[*]}] 35 | set_output_delay -clock clk_sdram_device -min -4.8ns -add_delay [get_ports {DRAM_DQ[*]}] 36 | -------------------------------------------------------------------------------- /DE2-115/PlayStation.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name inclk50 -period 50MHz [get_ports {CLOCK_50}] 2 | 3 | set clk50 {psx_pll_inst|altpll_component|auto_generated|pll1|clk[0]} 4 | set clk_sdram_device {psx_pll_inst|altpll_component|auto_generated|pll1|clk[1]} 5 | set clk_sdram_ctrl {psx_pll_inst|altpll_component|auto_generated|pll1|clk[2]} 6 | set clk_audio {psx_pll_inst|altpll_component|auto_generated|pll1|clk[3]} 7 | create_clock -name clk_audcnt -period 18.432MHz [get_registers {AUDIO_ctrl:AU|oAUD_BCK}] 8 | create_clock -name clk_i2c -period 20KHz [get_registers {I2C_AV_Config:DACConfU|mI2C_CTRL_CLK}] 9 | 10 | derive_pll_clocks 11 | derive_clock_uncertainty 12 | 13 | set PERIOD 20 14 | set tSetUp 13 15 | set tHold 3 16 | set_input_delay -clock $clk50 -max [expr $PERIOD - $tSetUp] [all_inputs] 17 | set_input_delay -clock $clk50 -min [expr $tHold] [all_inputs] 18 | set tCOMAX 18 19 | set tCOMIN 1 20 | set_output_delay -clock $clk50 -max [expr $PERIOD - $tCOMAX] [all_outputs] 21 | set_output_delay -clock $clk50 -min [expr -$tCOMIN] [all_outputs] 22 | 23 | set_input_delay -clock $clk_sdram_device -max 6.4ns -add_delay [get_ports {DRAM_DQ[*]}] 24 | set_input_delay -clock $clk_sdram_device -min 3.7ns -add_delay [get_ports {DRAM_DQ[*]}] 25 | set_output_delay -clock $clk_sdram_device -max 1.6ns -add_delay [get_ports {DRAM_DQ* DRAM_ADDR* DRAM_BA* DRAM_CKE DRAM_CLK DRAM_RAS_N DRAM_CAS_N DRAM_CS_N DRAM_WE_N}] 26 | set_output_delay -clock $clk_sdram_device -min -0.9ns -add_delay [get_ports {DRAM_DQ* DRAM_ADDR* DRAM_BA* DRAM_CKE DRAM_CLK DRAM_RAS_N DRAM_CAS_N DRAM_CS_N DRAM_WE_N}] 27 | 28 | set_false_path -from $clk50 -to $clk_audio 29 | set_false_path -from $clk_audio -to $clk50 30 | set_false_path -from $clk_sdram_device 31 | set_false_path -from $clk50 -to $clk_sdram_ctrl 32 | set_false_path -from $clk_sdram_ctrl -to $clk_sdram_device 33 | set_false_path -from clk_audcnt -to $clk50 34 | set_false_path -from $clk50 -to clk_audcnt 35 | set_false_path -from $clk50 -to clk_i2c 36 | set_false_path -from clk_i2c -to $clk50 37 | set_false_path -from clk_audcnt -to $clk_audio 38 | set_false_path -from $clk_audio -to clk_audcnt 39 | 40 | set_false_path -from [get_ports {KEY[*]}] 41 | set_false_path -from [get_ports {SW[*]}] 42 | set_false_path -to [get_ports {LEDG[*]}] 43 | set_false_path -to [get_ports {LEDR[*]}] 44 | set_false_path -to [get_ports {HEX*}] 45 | set_false_path -to [get_ports {VGA_*}] 46 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | .SUFFIXES: .sflp .sfl .h .v 2 | 3 | SFLP = PlayStation_core.sflp R3000A.sflp div_u32.sflp bsr_s32.sflp Cache_IR.sflp Timer.sflp \ 4 | DDS_50to33868800.sflp DMA_SPU.sflp SoundProcessingUnit.sflp DigitalSignalProcessor.sflp dsp_ch.sflp bsr_s16.sflp \ 5 | bsr_s24.sflp ADSR.sflp reverb.sflp ram_16x32k.sflp dsdac10.sflp GraphicProcessingUnit.sflp \ 6 | DMA_OTC.sflp DMA_GPU.sflp VGA_ctrl.sflp ram_320x240x15_dp.sflp inv_table.sflp drawPoly.sflp \ 7 | drawFillRect.sflp view_ram_ctrl.sflp view_ram_ctrl_one.sflp CDROM_controller.sflp PAD_controller.sflp PAD.sflp drawRect.sflp \ 8 | ram_8x2352.sflp DMA_CDR.sflp \ 9 | GeometryTransformationEngine.sflp gte_DIVIDE.sflp gte_LIMIT.sflp Scratchpad.sflp \ 10 | pseudo_cdrom_data.sflp MDEC.sflp Cache_Texture.sflp 11 | 12 | SFLS = $(SFLP:.sflp=.sfl) 13 | HEAD = $(SFLP:.sflp=.h) 14 | VLOG = $(SFLS:.sfl=.v) 15 | 16 | MAKEFLAGS += --no-print-directory 17 | 18 | sfl2vl: 19 | make sfl 20 | make vl 21 | # verilator --cc dsp_ch.v --compiler msvc --public 22 | # verilator --cc GraphicProcessingUnit.v --compiler msvc --public --l2-name v 23 | # verilator --cc drawPoly.v --compiler msvc --public --l2-name v 24 | # verilator --cc CDROM_controller.v --compiler msvc --public --l2-name v 25 | # verilator --cc PAD_controller.v --compiler msvc --public --l2-name v 26 | # verilator --cc drawTextureRect.v --compiler msvc --public --l2-name v 27 | # verilator --cc GeometryTransformationEngine.v --compiler msvc --public --l2-name v 28 | # verilator --cc gte_DIVIDE.v --compiler msvc --public --l2-name v 29 | # verilator --cc R3000A.v --compiler msvc --public --l2-name v 30 | # verilator --cc GeometryTransformationEngine.v --Mdir obj_dir_gcc --exe gte_sim.cpp --public --l2-name v 31 | # cd obj_dir_gcc; make -j -f VGeometryTransformationEngine.mk; ./VGeometryTransformationEngine.exe; cd ../ 32 | # verilator --cc PlayStation_core.v --compiler msvc --public --l2-name v 33 | # verilator --cc CDROM_controller.v --compiler msvc --public --l2-name v 34 | # verilator --cc PAD_controller.v --compiler msvc --public --l2-name v 35 | 36 | verilator --lint-only PlayStation_core.v --quiet-stats -y demo 37 | # verilator --lint-only core.v -y demo -y ../../hdl -y ../../DE2-115 38 | # verilator --cc core_sim.v --compiler msvc --public --l2-name v 39 | # ok 40 | 41 | sfl: $(SFLS) 42 | 43 | vl: $(VLOG) 44 | 45 | .sflp.sfl: 46 | sflp $< 47 | 48 | .sfl.v: 49 | sfl2vl $< -O2 50 | 51 | clean: 52 | rm -f $(SFLP:.sflp=.sfl) $(SFLP:.sflp=.h) $(SFLS:.sfl=.v) 53 | 54 | -------------------------------------------------------------------------------- /DMA_CDR.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | DMA for CD-ROM 3 | by pgate1 4 | */ 5 | 6 | circuit DMA_CDR 7 | { 8 | input DmaMADR_3<32>, DmaBCR_3<32>, DmaCHCR_3<32>; 9 | 10 | output A<21>, Dout<32>; 11 | instrout wram_write(A, Dout); 12 | 13 | instrout dma_read_req(); 14 | input dma_read_data<8>; 15 | 16 | instrin Execute; 17 | instrin wram_ack; 18 | output running; 19 | 20 | instrin run33; 21 | sel int_wait_max<16>; 22 | reg_wr count_rst; 23 | instrout interrupt; 24 | // output int_waiting; 25 | 26 | sel dma_size<18>; 27 | 28 | instrself halt(h_code); 29 | sel h_code<8>; 30 | reg_wr halt_code_reg<8>; 31 | output halt_code<8>; 32 | 33 | output dbg<32>; 34 | reg_wr dbg_reg<32>; 35 | output dbg_sum<32>; 36 | reg_wr sum<32>; 37 | 38 | stage_name run_dma { task do(); } 39 | stage_name int_wait { task do(count_rst); } 40 | 41 | instruct halt halt_code_reg := h_code; 42 | halt_code = halt_code_reg; 43 | 44 | dbg32 = dbg32_reg; 45 | 46 | running = /*Execute |*/ run_dma.do; 47 | 48 | instruct Execute par{ 49 | generate run_dma.do(); 50 | } 51 | 52 | dma_size = DmaBCR_3<15:0> || 0b00; 53 | 54 | any{ 55 | DmaCHCR_3==0x11000000 : int_wait_max = dma_size<17:2>; 56 | DmaCHCR_3==0x11400100 : int_wait_max = dma_size<17:2> >> 2; 57 | } 58 | 59 | stage run_dma { 60 | reg madr<21>, dma_count<18>; 61 | mem dma_data[4]<8>; 62 | first_state st_init; 63 | state st_init par{ 64 | madr := DmaMADR_3<20:2> || 0b00; 65 | dma_count := 0; 66 | goto st_read; 67 | } 68 | state st_read par{ 69 | dma_read_req(); 70 | goto st_readw; 71 | } 72 | state st_readw par{ 73 | any(i=0;i<4;i++){ 74 | dma_count<1:0>==i : dma_data[i] := dma_read_data; 75 | } 76 | dma_count++; 77 | goto st_write; 78 | } 79 | state st_write if(wram_ack){ 80 | if(madr<1:0>==3) wram_write(madr, dma_data[3]||dma_data[2]||dma_data[1]||dma_data[0]); 81 | madr++; 82 | if(dma_count==dma_size) goto st_end; 83 | else goto st_read; 84 | } 85 | state st_end if(wram_ack){ 86 | generate int_wait.do(0b1); 87 | goto st_init; 88 | finish; 89 | } 90 | } 91 | 92 | stage int_wait { 93 | reg int_wait_count<16>; 94 | first_state st1; 95 | state st1 par{ 96 | int_wait_count := int_wait_max; 97 | count_rst := 0b0; 98 | if(count_rst) goto st2; 99 | } 100 | state st2 if(run33){ 101 | int_wait_count--; 102 | if(int_wait_count==0){ 103 | interrupt(); 104 | goto st1; 105 | finish; 106 | } 107 | if(count_rst) goto st1; 108 | } 109 | } 110 | 111 | } 112 | -------------------------------------------------------------------------------- /view_ram_ctrl.sflp: -------------------------------------------------------------------------------- 1 | 2 | // RGB RAM & to VGA Flip Buffer 3 | 4 | %i "ram_320x240x15_dp.h" 5 | 6 | circuit view_ram_ctrl 7 | { 8 | input in_x<9>, in_y<8>, in_R<5>, in_G<5>, in_B<5>; 9 | instrin write(in_x, in_y, in_R, in_G, in_B); 10 | output out_R<5>, out_G<5>, out_B<5>; 11 | instrin read, bank_change, read_adrs_reset; 12 | reg_wr write_ok; 13 | 14 | instrin fill_view_on, draw_notdisp_side; 15 | input frame_rate<2>; 16 | 17 | reg_ws reset; 18 | 19 | ram_320x240x15_dp ram0, ram1; 20 | reg_wr radrs_x<9>, radrs_y<9>, bank; 21 | sel col<15>; 22 | 23 | stage_name clear_stg { task do(); } 24 | 25 | if(reset){ 26 | // generate clear_stg.do(); 27 | reset := 0b0; 28 | } 29 | 30 | if(clear_stg.do){ 31 | col = 0; 32 | } 33 | else{ 34 | if(^bank) col = ram0.dout; 35 | else col = ram1.dout; 36 | } 37 | out_R = col<14:10>; 38 | out_G = col< 9: 5>; 39 | out_B = col< 4: 0>; 40 | 41 | // GPU DispPos update 42 | instruct bank_change par{ 43 | // bank := ^bank; 44 | 45 | // reg_wr frame<2>; 46 | // if(frame==frame_rate){ 47 | if(write_ok) bank := ^bank; 48 | write_ok := 0b0; 49 | // frame := 0; 50 | // } 51 | // else frame++; 52 | 53 | } 54 | 55 | instruct read_adrs_reset par{ 56 | radrs_x := 0; 57 | radrs_y := 0; 58 | } 59 | 60 | // insert reg 61 | reg_wr write_adrs<17>, write_data<15>, fill_view_on_reg, write_req; 62 | instruct write if(^clear_stg.do){ 63 | // y * 320 + x 64 | write_adrs := ((9#0b0||in_y)<<8) + ((9#0b0||in_y)<<6) + (8#0b0||in_x); 65 | write_data := in_R || in_G || in_B; 66 | fill_view_on_reg := fill_view_on; 67 | write_req := 0b1; 68 | } 69 | 70 | if(write_req){ 71 | if(^write) write_req := 0b0; 72 | 73 | //bank 0 1 74 | //not 0 0 1 75 | // disp 1 1 0 76 | if(bank @ draw_notdisp_side){ 77 | ram0.write(write_adrs, write_data); 78 | if(^fill_view_on_reg) write_ok := 0b1; 79 | } 80 | else{ 81 | ram1.write(write_adrs, write_data); 82 | if(^fill_view_on_reg) write_ok := 0b1; 83 | } 84 | } 85 | 86 | instruct read if(^clear_stg.do){ 87 | sel radrs<17>; 88 | // y * 320 + x 89 | radrs = ((9#0b0||radrs_y<8:1>)<<8) + ((9#0b0||radrs_y<8:1>)<<6) + (8#0b0||radrs_x); 90 | if(^bank) ram0.read(radrs); 91 | else ram1.read(radrs); 92 | if(radrs_x==319){ 93 | radrs_x := 0; 94 | radrs_y++; 95 | } 96 | else radrs_x++; 97 | } 98 | /* 99 | stage clear_stg { 100 | par{ 101 | ram0.write(write_adrs, 0); 102 | ram1.write(write_adrs, 0); 103 | write_adrs++; 104 | if(/&write_adrs) finish; 105 | } 106 | } 107 | */ 108 | } 109 | -------------------------------------------------------------------------------- /Pocket/usage.txt: -------------------------------------------------------------------------------- 1 | 2 | PlayStation on FPGA feat. Analogue Pocket 3 | 4 | 5 | [ CAUTION, the screen flickering, protect your eyes. ] 6 | If the screen is flickering, do not leave it for a long time, but turn off the power. 7 | If the flickering remains on the screen, turn off the power and leave it for a day. 8 | 9 | 10 | This is a port of the basic functions of the first PlayStation to Analogue Pocket. 11 | Sound and movie functions have been left out to fit in Pocket's FPGA. 12 | The FPS is low because the main memory and VRAM are shared. 13 | 14 | 15 | * Using core. 16 | 17 | 1. Put the "Assets", "Cores" and "Platforms" in the dist on the SD card. 18 | 19 | 2. Put the PlayStation SCPH5500 BIOS file on the Assets/playstation/common. 20 | The file name is "scph5500.bin". Other versions of BIOS have not been tested. 21 | 22 | 3. Put the .bin or .img created from the PlayStation-ROM with image creation software 23 | (e.g. ImgBurn) in the Assets/playstation/common. 24 | 25 | Assets 26 | playstation 27 | common 28 | rom.bin (get it from the game CD) 29 | scph5500.bin (replace dummy) 30 | Cores 31 | pgate1.PlayStation 32 | bitstream.rbf_r 33 | *.json 34 | Platforms 35 | _images 36 | playstation.bin 37 | playstation.json 38 | 39 | 4. OK. Insert the SD card into the Pocket, turn it on, and select PlayStation core from openFPGA. 40 | 41 | 5. There are three choices from the file browser. 42 | 43 | If you choose rom.bin(.img), the game will launch via the PS logo (if you are lucky). 44 | 45 | If you choose scph5500.bin, the PlayStation main menu will appear. 46 | 47 | If you choose a PS-X EXE format demo program such as PSXNICCC.exe, it will run without going through the PS logo. 48 | 49 | 6. Have fun until your Pocket's battery runs out. 50 | 51 | If it works happily, please take a video of it and upload it to X(Twitter). I will be delighted. 52 | 53 | 54 | * What to do when it doesn't work. 55 | 56 | Error in framework File ID [32] size bad. 57 | -> The file size of BIOS must be 524,288 bytes. 58 | 59 | Immediately after the first black screen, red lines appear on all four sides. 60 | -> It may not be a valid BIOS file. Please check the checksum. 61 | 62 | Cannot proceed after PS logo is displayed, red lines appear on all four sides. 63 | -> This software is not yet supported. Sorry. 64 | 65 | The game won't start after the PS logo. 66 | -> The movie is probably being processed (dark green), so hit the Start button repeatedly after 67 | the PS logo to skip the movie. If you time it right, you might be able to skip the movie. 68 | If it still doesn't start, it's still not supported. 69 | 70 | During play, red or yellow lines appeared on all four sides and the game stopped. 71 | -> PlayStatoin Core has issued a HALT code. Insufficient functionality. Sorry. 72 | Red lines : CPU runaway for unknown reasons. 73 | Yellow lines : Some feature implementation is missing. 74 | 75 | 76 | 2025/11/30 pgate1 77 | -------------------------------------------------------------------------------- /gte_DIVIDE.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | DIVIDE in GTE 3 | by pgate1 4 | */ 5 | 6 | declare mul_u32 interface 7 | { 8 | input a<32>, b<32>; 9 | output dout<64>; 10 | instrin con; 11 | instr_arg con(a, b); 12 | } 13 | 14 | circuit gte_DIVIDE 15 | { 16 | input H<16>, SZ3<16>; 17 | instrin con0(H, SZ3), con1, con2, con3(H, SZ3); 18 | output dout<32>; 19 | 20 | mem unr_table[256]<8> = { 21 | 0xFF,0xFD,0xFB,0xF9,0xF7,0xF5,0xF3,0xF1,0xEF,0xEE,0xEC,0xEA,0xE8,0xE6,0xE4,0xE3, 22 | 0xE1,0xDF,0xDD,0xDC,0xDA,0xD8,0xD6,0xD5,0xD3,0xD1,0xD0,0xCE,0xCD,0xCB,0xC9,0xC8, 23 | 0xC6,0xC5,0xC3,0xC1,0xC0,0xBE,0xBD,0xBB,0xBA,0xB8,0xB7,0xB5,0xB4,0xB2,0xB1,0xB0, 24 | 0xAE,0xAD,0xAB,0xAA,0xA9,0xA7,0xA6,0xA4,0xA3,0xA2,0xA0,0x9F,0x9E,0x9C,0x9B,0x9A, 25 | 0x99,0x97,0x96,0x95,0x94,0x92,0x91,0x90,0x8F,0x8D,0x8C,0x8B,0x8A,0x89,0x87,0x86, 26 | 0x85,0x84,0x83,0x82,0x81,0x7F,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x75,0x74, 27 | 0x73,0x72,0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64, 28 | 0x63,0x62,0x61,0x60,0x5F,0x5E,0x5D,0x5D,0x5C,0x5B,0x5A,0x59,0x58,0x57,0x56,0x55, 29 | 0x54,0x53,0x53,0x52,0x51,0x50,0x4F,0x4E,0x4D,0x4D,0x4C,0x4B,0x4A,0x49,0x48,0x48, 30 | 0x47,0x46,0x45,0x44,0x43,0x43,0x42,0x41,0x40,0x3F,0x3F,0x3E,0x3D,0x3C,0x3C,0x3B, 31 | 0x3A,0x39,0x39,0x38,0x37,0x36,0x36,0x35,0x34,0x33,0x33,0x32,0x31,0x31,0x30,0x2F, 32 | 0x2E,0x2E,0x2D,0x2C,0x2C,0x2B,0x2A,0x2A,0x29,0x28,0x28,0x27,0x26,0x26,0x25,0x24, 33 | 0x24,0x23,0x22,0x22,0x21,0x20,0x20,0x1F,0x1E,0x1E,0x1D,0x1D,0x1C,0x1B,0x1B,0x1A, 34 | 0x19,0x19,0x18,0x18,0x17,0x16,0x16,0x15,0x15,0x14,0x14,0x13,0x12,0x12,0x11,0x11, 35 | 0x10,0x0F,0x0F,0x0E,0x0E,0x0D,0x0D,0x0C,0x0C,0x0B,0x0A,0x0A,0x09,0x09,0x08,0x08, 36 | 0x07,0x07,0x06,0x06,0x05,0x05,0x04,0x04,0x03,0x03,0x02,0x02,0x01,0x01,0x00,0x00 37 | }; 38 | 39 | sel unr_table_adrs<8>; 40 | instrself unr_table_read(unr_table_adrs); 41 | reg unr_table_dout<8>; 42 | 43 | mul_u32 mul12, mul3; 44 | 45 | sel s_CLZ<16>, CLZ_ret<4>; 46 | instrself CLZ(s_CLZ); 47 | 48 | instruct CLZ par{ // Count Leading Zero 49 | alt(i=0;i<16;i++){ 50 | s_CLZ<15-i> : CLZ_ret = i; 51 | // else : CLZ_ret = 16; 52 | } 53 | } 54 | 55 | sel z<4>; 56 | z = CLZ(SZ3).CLZ_ret; 57 | sel n<17>; 58 | n = ((0x0000 || H) << z)<16:0>; 59 | sel d<16>; 60 | d = SZ3 << z; 61 | 62 | reg_wr n0<17>, d0<16>; 63 | instruct con0 par{ 64 | n0 := n; 65 | d0 := d; 66 | unr_table_read((d - 0x7FC0)<14:7>); 67 | } 68 | 69 | instruct unr_table_read unr_table_dout := unr_table[unr_table_adrs]; 70 | 71 | sel index<9>, u0<12>; 72 | index = (d0 - 0x7FC0)<15:7>; 73 | if(index<8>) u0 = 0x101; 74 | else u0 = (0x0 || unr_table_dout) + 0x101; 75 | 76 | reg_wr d1<17>; 77 | instruct con1 par{ 78 | // d0<16> * u0<10> 79 | d1 := ((0x02000080 - mul12.con(16#0b0||d0, 20#0b0||u0).dout<31:0>) >> 8)<16:0>; // 32 * 16 80 | } 81 | 82 | reg_wr d2<18>; 83 | instruct con2 par{ 84 | // d1<17> * u0<10> 85 | d2 := ((0x00000080 + mul12.con(15#0b0||d1, 20#0b0||u0).dout<31:0>) >> 8)<17:0>; // 32 * 16 86 | } 87 | 88 | sel n1<17>; 89 | instruct con3 par{ 90 | // n0<17> * d2<18> 91 | n1 = ((mul3.con(15#0b0||n0, 14#0b0||d2).dout<35:0> + 0x000008000) >> 16)<16:0>; // 32 * 32 92 | } 93 | 94 | if((H<15>==0b0) & (((0b00||H)-(0b0||SZ3||0b0))<17>==0b1)) dout = 15#0b0||n1; 95 | else dout = 0xFFFFFFFF; 96 | } 97 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PlayStation on FPGA 2 | implemented PlayStation on an FPGA. 3 | 4 | 15 | 16 | PlayStation Sound Player on FPGA 17 | PlayStation on FPGA feat. DE2-115 (Run kernel) 18 | PlayStation on FPGA feat. Pocket (No sound, movie. The frame rate is slow because the main memory and vram are shared.) 19 | 20 | 50 | 51 | ## Screenshots 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | ## Working game list 62 | 63 | Here's a list of games that work a little. There may be other games that work as well. 64 | 65 | - Einhander 66 | - Ridge Racer 67 | - Tobal No.1 68 | - Tobal 2 69 | - iS internal section 70 | - Saga Frontier 2 71 | - Dewprism 72 | - Vagrant Story 73 | - RayStorm 74 | - Raycrisis 75 | - Rockman X4 76 | - Rockman X5 77 | - Rockman X6 78 | - Ace Combat 2 79 | - XI 80 | - Love & Destroy 81 | - Metal Gear Solid Integral VR disc 82 | - Valkyrie Profile 83 | - Omega Boost 84 | - Final Fantasy Tactics 85 | - Brave Fencer Musashiden 86 | - Chocobo Racing 87 | - Racing Lagoon 88 | - Seiken Densetsu Legend of Mana 89 | - G Darius 90 | - Silent Bomber 91 | - Xenogears 92 | 93 | User reports. 94 | 95 | - GUNPEY 96 | - Speed Power Gunbike 97 | - Rakugaki Showtime 98 | - Mr. Driller 99 | - Harmful Park 100 | - Runabout 101 | - Kaette Kita Cyborg Kurochan 102 | - Bloody Roar 103 | - Minna no Golf 2 104 | 105 | ## Future implementation plans. 106 | 107 | - GPU: Transparent drawing, texture blending. 108 | - SIO: Handling save data. 109 | - Pocket: Change resolution. 110 | - Pocket: Sound is simulated using a square wave. 111 | - GPU: Draw lines. 112 | - CPU: Write buffer to WorkRAM. 113 | - SPU: Pipelined. 114 | - GTE: Processing optimization. 115 | 116 | -------------------------------------------------------------------------------- /MDEC.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | Motion Decoder 3 | by pgate1 4 | */ 5 | 6 | circuit MDEC 7 | { 8 | input DmaMADR_0<32>, DmaBCR_0<32>; 9 | input DmaMADR_1<32>, DmaBCR_1<32>; 10 | 11 | input din<32>; 12 | instrin WriteCmd(din), WriteCtrl(din); 13 | instrin ReadData, ReadStatus; 14 | output dout<32>; 15 | 16 | output wram_adrs<21>, wram_din<24>, wram_word<2>; 17 | instrout wram_write(wram_adrs, wram_din, wram_word); 18 | instrout wram_read(wram_adrs); 19 | input wram_dout<16>; 20 | instrin wram_ack; 21 | 22 | reg bcr<32>; 23 | sel dma_size<16>; 24 | 25 | reg_wr reg0<32>, reg1<32>; 26 | 27 | reg_wr rl<21>; 28 | 29 | instrin DMAin_Execute, DMAout_Execute; 30 | output running, waiting; 31 | 32 | instrin run33; 33 | reg int_wait_max<16>; 34 | reg_wr count0_rst, count1_rst; 35 | instrout mdec0_interrupt, mdec1_interrupt; 36 | 37 | instrout end_of_data; 38 | 39 | stage_name run_dma0 { task do(); } 40 | stage_name int_wait0 { task do(int_wait_max, count0_rst); } 41 | stage_name run_dma1 { task do(); } 42 | stage_name int_wait1 { task do(int_wait_max, count1_rst); } 43 | 44 | instruct WriteCmd par{ 45 | reg0 := din; 46 | } 47 | 48 | instruct WriteCtrl par{ 49 | if(din<31>){ 50 | reg0 := 0x00000000; 51 | reg1 := 0x00000000; 52 | } 53 | } 54 | 55 | instruct ReadData par{ 56 | dout = reg0; 57 | } 58 | 59 | instruct ReadStatus par{ 60 | dout = reg1; 61 | } 62 | 63 | // uint32 size = (bcr >> 16) * (bcr & 0xFFFF); 64 | // 16 * 16 = 32; 65 | dma_size = 64;//size_mul.con(bcr<31:16>, bcr<15:0>).dout; 66 | 67 | running = run_dma0.do | run_dma1.do; 68 | waiting = running | int_wait0.do | int_wait1.do; 69 | 70 | instruct DMAin_Execute par{ 71 | generate run_dma0.do(); 72 | } 73 | 74 | instruct DMAout_Execute par{ 75 | generate run_dma1.do(); 76 | } 77 | 78 | stage run_dma0 { 79 | first_state st1; 80 | state st1 par{ 81 | reg1 |= 0x00800000; 82 | bcr := DmaBCR_0; 83 | goto st2; 84 | } 85 | state st2 par{ 86 | switch(reg0<31:29>){ 87 | case 0: par{ 88 | mdec0_interrupt(); 89 | } 90 | case 1: par{ 91 | rl := DmaMADR_0<20:2> || 0b00; 92 | reg1 |= 0x20000000; // BUSY 93 | } 94 | case 2: par{ 95 | generate int_wait0.do(dma_size >> 2, 1); 96 | } 97 | case 3: par{ 98 | generate int_wait0.do(dma_size >> 2, 1); 99 | } 100 | } 101 | 102 | goto st1; 103 | finish; 104 | } 105 | } 106 | 107 | stage int_wait0 { 108 | reg int_wait_count0<16>; 109 | first_state st1; 110 | state st1 par{ 111 | int_wait_count0 := int_wait_max; 112 | count0_rst := 0b0; 113 | if(count0_rst) goto st2; 114 | } 115 | state st2 if(run33){ 116 | int_wait_count0--; 117 | if(int_wait_count0==0){ 118 | mdec0_interrupt(); 119 | goto st1; 120 | finish; 121 | } 122 | if(count0_rst) goto st1; 123 | } 124 | } 125 | 126 | stage run_dma1 { 127 | reg block_count<5>; 128 | reg col<8>; 129 | reg image_adrs<21>; 130 | reg image_count<8>; 131 | first_state st_init; 132 | state st_init par{ 133 | bcr := DmaBCR_1; 134 | block_count := 1; 135 | image_adrs := DmaMADR_1<20:2> || 0b00; 136 | goto st_end; 137 | // goto st_read; 138 | } 139 | /* 140 | state st_read if(wram_ack){ 141 | wram_read(rl); 142 | rl += 2; 143 | goto st_readw; 144 | } 145 | state st_readw if(wram_ack){ 146 | if(wram_dout!=0xFE00){ 147 | col := wram_dout<13:6>; 148 | goto st_read; 149 | } 150 | else{ // 0xFE00 151 | image_count := 0; 152 | goto st_write; 153 | } 154 | } 155 | state st_write if(wram_ack){ 156 | any{ 157 | reg0<27> : par{ // 15bit color 158 | wram_write(image_adrs, 0x00 || col || col, 2); 159 | image_adrs += 2; 160 | } 161 | else : par{ // 24bit color 162 | wram_write(image_adrs, col || col || col, 3); 163 | image_adrs += 3; 164 | } 165 | } 166 | image_count++; 167 | if(image_count==255){ 168 | if(block_count==12) goto st_end; // test 169 | else goto st_read; 170 | block_count++; 171 | } 172 | } 173 | */ 174 | state st_end if(wram_ack){ 175 | generate int_wait1.do(18432 /*dma_size << 2*/, 1); 176 | goto st_init; 177 | finish; 178 | } 179 | } 180 | 181 | stage int_wait1 { 182 | reg int_wait_count1<16>; 183 | first_state st1; 184 | state st1 par{ 185 | int_wait_count1 := int_wait_max; 186 | count1_rst := 0b0; 187 | if(count1_rst) goto st2; 188 | } 189 | state st2 if(run33){ 190 | int_wait_count1--; 191 | if(int_wait_count1==0){ 192 | mdec1_interrupt(); 193 | 194 | // end_of_data(); 195 | reg1 &= ^0x20800000; 196 | 197 | goto st1; 198 | finish; 199 | } 200 | if(count1_rst) goto st1; 201 | } 202 | } 203 | 204 | } 205 | -------------------------------------------------------------------------------- /demo/cos_table.sflp: -------------------------------------------------------------------------------- 1 | 2 | circuit cos_table 3 | { 4 | input angle<9>; 5 | instrin read(angle); 6 | output dout<10>; 7 | reg_wr dout_reg<10>; 8 | 9 | mem cells[512]<10> = { 10 | 256, 11 | 255, 12 | 255, 13 | 255, 14 | 255, 15 | 255, 16 | 254, 17 | 254, 18 | 253, 19 | 252, 20 | 252, 21 | 251, 22 | 250, 23 | 249, 24 | 248, 25 | 247, 26 | 246, 27 | 244, 28 | 243, 29 | 242, 30 | 240, 31 | 238, 32 | 237, 33 | 235, 34 | 233, 35 | 232, 36 | 230, 37 | 228, 38 | 226, 39 | 223, 40 | 221, 41 | 219, 42 | 217, 43 | 214, 44 | 212, 45 | 209, 46 | 207, 47 | 204, 48 | 201, 49 | 198, 50 | 196, 51 | 193, 52 | 190, 53 | 187, 54 | 184, 55 | 181, 56 | 177, 57 | 174, 58 | 171, 59 | 167, 60 | 164, 61 | 161, 62 | 157, 63 | 154, 64 | 150, 65 | 146, 66 | 143, 67 | 139, 68 | 135, 69 | 131, 70 | 127, 71 | 124, 72 | 120, 73 | 116, 74 | 112, 75 | 108, 76 | 104, 77 | 100, 78 | 95, 79 | 91, 80 | 87, 81 | 83, 82 | 79, 83 | 74, 84 | 70, 85 | 66, 86 | 61, 87 | 57, 88 | 53, 89 | 48, 90 | 44, 91 | 40, 92 | 35, 93 | 31, 94 | 26, 95 | 22, 96 | 17, 97 | 13, 98 | 8, 99 | 4, 100 | 0, 101 | -4, 102 | -8, 103 | -13, 104 | -17, 105 | -22, 106 | -26, 107 | -31, 108 | -35, 109 | -40, 110 | -44, 111 | -48, 112 | -53, 113 | -57, 114 | -61, 115 | -66, 116 | -70, 117 | -74, 118 | -79, 119 | -83, 120 | -87, 121 | -91, 122 | -95, 123 | -100, 124 | -104, 125 | -108, 126 | -112, 127 | -116, 128 | -120, 129 | -124, 130 | -128, 131 | -131, 132 | -135, 133 | -139, 134 | -143, 135 | -146, 136 | -150, 137 | -154, 138 | -157, 139 | -161, 140 | -164, 141 | -167, 142 | -171, 143 | -174, 144 | -177, 145 | -181, 146 | -184, 147 | -187, 148 | -190, 149 | -193, 150 | -196, 151 | -198, 152 | -201, 153 | -204, 154 | -207, 155 | -209, 156 | -212, 157 | -214, 158 | -217, 159 | -219, 160 | -221, 161 | -223, 162 | -226, 163 | -228, 164 | -230, 165 | -232, 166 | -233, 167 | -235, 168 | -237, 169 | -238, 170 | -240, 171 | -242, 172 | -243, 173 | -244, 174 | -246, 175 | -247, 176 | -248, 177 | -249, 178 | -250, 179 | -251, 180 | -252, 181 | -252, 182 | -253, 183 | -254, 184 | -254, 185 | -255, 186 | -255, 187 | -255, 188 | -255, 189 | -255, 190 | -256, 191 | -255, 192 | -255, 193 | -255, 194 | -255, 195 | -255, 196 | -254, 197 | -254, 198 | -253, 199 | -252, 200 | -252, 201 | -251, 202 | -250, 203 | -249, 204 | -248, 205 | -247, 206 | -246, 207 | -244, 208 | -243, 209 | -242, 210 | -240, 211 | -238, 212 | -237, 213 | -235, 214 | -233, 215 | -232, 216 | -230, 217 | -228, 218 | -226, 219 | -223, 220 | -221, 221 | -219, 222 | -217, 223 | -214, 224 | -212, 225 | -209, 226 | -207, 227 | -204, 228 | -201, 229 | -198, 230 | -196, 231 | -193, 232 | -190, 233 | -187, 234 | -184, 235 | -181, 236 | -177, 237 | -174, 238 | -171, 239 | -167, 240 | -164, 241 | -161, 242 | -157, 243 | -154, 244 | -150, 245 | -146, 246 | -143, 247 | -139, 248 | -135, 249 | -131, 250 | -127, 251 | -124, 252 | -120, 253 | -116, 254 | -112, 255 | -108, 256 | -104, 257 | -100, 258 | -95, 259 | -91, 260 | -87, 261 | -83, 262 | -79, 263 | -74, 264 | -70, 265 | -66, 266 | -61, 267 | -57, 268 | -53, 269 | -48, 270 | -44, 271 | -40, 272 | -35, 273 | -31, 274 | -26, 275 | -22, 276 | -17, 277 | -13, 278 | -8, 279 | -4, 280 | 0, 281 | 4, 282 | 8, 283 | 13, 284 | 17, 285 | 22, 286 | 26, 287 | 31, 288 | 35, 289 | 40, 290 | 44, 291 | 48, 292 | 53, 293 | 57, 294 | 61, 295 | 66, 296 | 70, 297 | 74, 298 | 79, 299 | 83, 300 | 87, 301 | 91, 302 | 95, 303 | 100, 304 | 104, 305 | 108, 306 | 112, 307 | 116, 308 | 120, 309 | 124, 310 | 128, 311 | 131, 312 | 135, 313 | 139, 314 | 143, 315 | 146, 316 | 150, 317 | 154, 318 | 157, 319 | 161, 320 | 164, 321 | 167, 322 | 171, 323 | 174, 324 | 177, 325 | 181, 326 | 184, 327 | 187, 328 | 190, 329 | 193, 330 | 196, 331 | 198, 332 | 201, 333 | 204, 334 | 207, 335 | 209, 336 | 212, 337 | 214, 338 | 217, 339 | 219, 340 | 221, 341 | 223, 342 | 226, 343 | 228, 344 | 230, 345 | 232, 346 | 233, 347 | 235, 348 | 237, 349 | 238, 350 | 240, 351 | 242, 352 | 243, 353 | 244, 354 | 246, 355 | 247, 356 | 248, 357 | 249, 358 | 250, 359 | 251, 360 | 252, 361 | 252, 362 | 253, 363 | 254, 364 | 254, 365 | 255, 366 | 255, 367 | 255, 368 | 255, 369 | 255 370 | }; 371 | 372 | instruct read par{ 373 | dout_reg := cells[angle]; 374 | } 375 | 376 | dout = dout_reg; 377 | } 378 | -------------------------------------------------------------------------------- /demo/sin_table.sflp: -------------------------------------------------------------------------------- 1 | 2 | circuit sin_table 3 | { 4 | input angle<9>; 5 | instrin read(angle); 6 | output dout<10>; 7 | reg_wr dout_reg<10>; 8 | 9 | mem cells[512]<10> = { 10 | 0, 11 | 4, 12 | 8, 13 | 13, 14 | 17, 15 | 22, 16 | 26, 17 | 31, 18 | 35, 19 | 40, 20 | 44, 21 | 48, 22 | 53, 23 | 57, 24 | 61, 25 | 66, 26 | 70, 27 | 74, 28 | 79, 29 | 83, 30 | 87, 31 | 91, 32 | 95, 33 | 100, 34 | 104, 35 | 108, 36 | 112, 37 | 116, 38 | 120, 39 | 124, 40 | 128, 41 | 131, 42 | 135, 43 | 139, 44 | 143, 45 | 146, 46 | 150, 47 | 154, 48 | 157, 49 | 161, 50 | 164, 51 | 167, 52 | 171, 53 | 174, 54 | 177, 55 | 181, 56 | 184, 57 | 187, 58 | 190, 59 | 193, 60 | 196, 61 | 198, 62 | 201, 63 | 204, 64 | 207, 65 | 209, 66 | 212, 67 | 214, 68 | 217, 69 | 219, 70 | 221, 71 | 223, 72 | 226, 73 | 228, 74 | 230, 75 | 232, 76 | 233, 77 | 235, 78 | 237, 79 | 238, 80 | 240, 81 | 242, 82 | 243, 83 | 244, 84 | 246, 85 | 247, 86 | 248, 87 | 249, 88 | 250, 89 | 251, 90 | 252, 91 | 252, 92 | 253, 93 | 254, 94 | 254, 95 | 255, 96 | 255, 97 | 255, 98 | 255, 99 | 255, 100 | 256, 101 | 255, 102 | 255, 103 | 255, 104 | 255, 105 | 255, 106 | 254, 107 | 254, 108 | 253, 109 | 252, 110 | 252, 111 | 251, 112 | 250, 113 | 249, 114 | 248, 115 | 247, 116 | 246, 117 | 244, 118 | 243, 119 | 242, 120 | 240, 121 | 238, 122 | 237, 123 | 235, 124 | 233, 125 | 232, 126 | 230, 127 | 228, 128 | 226, 129 | 223, 130 | 221, 131 | 219, 132 | 217, 133 | 214, 134 | 212, 135 | 209, 136 | 207, 137 | 204, 138 | 201, 139 | 198, 140 | 196, 141 | 193, 142 | 190, 143 | 187, 144 | 184, 145 | 181, 146 | 177, 147 | 174, 148 | 171, 149 | 167, 150 | 164, 151 | 161, 152 | 157, 153 | 154, 154 | 150, 155 | 146, 156 | 143, 157 | 139, 158 | 135, 159 | 131, 160 | 127, 161 | 124, 162 | 120, 163 | 116, 164 | 112, 165 | 108, 166 | 104, 167 | 100, 168 | 95, 169 | 91, 170 | 87, 171 | 83, 172 | 79, 173 | 74, 174 | 70, 175 | 66, 176 | 61, 177 | 57, 178 | 53, 179 | 48, 180 | 44, 181 | 40, 182 | 35, 183 | 31, 184 | 26, 185 | 22, 186 | 17, 187 | 13, 188 | 8, 189 | 4, 190 | 0, 191 | -4, 192 | -8, 193 | -13, 194 | -17, 195 | -22, 196 | -26, 197 | -31, 198 | -35, 199 | -40, 200 | -44, 201 | -48, 202 | -53, 203 | -57, 204 | -61, 205 | -66, 206 | -70, 207 | -74, 208 | -79, 209 | -83, 210 | -87, 211 | -91, 212 | -95, 213 | -100, 214 | -104, 215 | -108, 216 | -112, 217 | -116, 218 | -120, 219 | -124, 220 | -128, 221 | -131, 222 | -135, 223 | -139, 224 | -143, 225 | -146, 226 | -150, 227 | -154, 228 | -157, 229 | -161, 230 | -164, 231 | -167, 232 | -171, 233 | -174, 234 | -177, 235 | -181, 236 | -184, 237 | -187, 238 | -190, 239 | -193, 240 | -196, 241 | -198, 242 | -201, 243 | -204, 244 | -207, 245 | -209, 246 | -212, 247 | -214, 248 | -217, 249 | -219, 250 | -221, 251 | -223, 252 | -226, 253 | -228, 254 | -230, 255 | -232, 256 | -233, 257 | -235, 258 | -237, 259 | -238, 260 | -240, 261 | -242, 262 | -243, 263 | -244, 264 | -246, 265 | -247, 266 | -248, 267 | -249, 268 | -250, 269 | -251, 270 | -252, 271 | -252, 272 | -253, 273 | -254, 274 | -254, 275 | -255, 276 | -255, 277 | -255, 278 | -255, 279 | -255, 280 | -256, 281 | -255, 282 | -255, 283 | -255, 284 | -255, 285 | -255, 286 | -254, 287 | -254, 288 | -253, 289 | -252, 290 | -252, 291 | -251, 292 | -250, 293 | -249, 294 | -248, 295 | -247, 296 | -246, 297 | -244, 298 | -243, 299 | -242, 300 | -240, 301 | -238, 302 | -237, 303 | -235, 304 | -233, 305 | -232, 306 | -230, 307 | -228, 308 | -226, 309 | -223, 310 | -221, 311 | -219, 312 | -217, 313 | -214, 314 | -212, 315 | -209, 316 | -207, 317 | -204, 318 | -201, 319 | -198, 320 | -196, 321 | -193, 322 | -190, 323 | -187, 324 | -184, 325 | -181, 326 | -177, 327 | -174, 328 | -171, 329 | -167, 330 | -164, 331 | -161, 332 | -157, 333 | -154, 334 | -150, 335 | -146, 336 | -143, 337 | -139, 338 | -135, 339 | -131, 340 | -127, 341 | -124, 342 | -120, 343 | -116, 344 | -112, 345 | -108, 346 | -104, 347 | -100, 348 | -95, 349 | -91, 350 | -87, 351 | -83, 352 | -79, 353 | -74, 354 | -70, 355 | -66, 356 | -61, 357 | -57, 358 | -53, 359 | -48, 360 | -44, 361 | -40, 362 | -35, 363 | -31, 364 | -26, 365 | -22, 366 | -17, 367 | -13, 368 | -8, 369 | -4 370 | }; 371 | 372 | instruct read par{ 373 | dout_reg := cells[angle]; 374 | } 375 | 376 | dout = dout_reg; 377 | } 378 | -------------------------------------------------------------------------------- /gte_LIMIT.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | LIMIT in GTE 3 | by pgate1 4 | */ 5 | 6 | circuit gte_LIMIT 7 | { 8 | input limB1_val<32>, limB1_lim; 9 | instrin limB1(limB1_val, limB1_lim); 10 | output limB1_ret<16>; 11 | 12 | input limB2_val<32>, limB2_lim; 13 | instrin limB2(limB2_val, limB2_lim); 14 | output limB2_ret<16>; 15 | 16 | input limB3_val<32>, limB3_lim; 17 | instrin limB3(limB3_val, limB3_lim); 18 | output limB3_ret<16>; 19 | 20 | input limC1_val<32>; 21 | instrin limC1(limC1_val); 22 | output limC1_ret<8>; 23 | 24 | input limC2_val<32>; 25 | instrin limC2(limC2_val); 26 | output limC2_ret<8>; 27 | 28 | input limC3_val<32>; 29 | instrin limC3(limC3_val); 30 | output limC3_ret<8>; 31 | 32 | input limD_val<32>; 33 | instrin limD(limD_val); 34 | output limD_ret<16>; 35 | 36 | output FLAG<32>; 37 | instrout set_FLAG(FLAG); 38 | 39 | /* 40 | // #define limB1(a, l) LIM((a), 0x7fff, -0x8000 * !l, (1 << 24)) 41 | // #define limB2(a, l) LIM((a), 0x7fff, -0x8000 * !l, (1 << 23)) 42 | // #define limB3(a, l) LIM((a), 0x7fff, -0x8000 * !l, (1 << 22)) 43 | static inline s64 LIM(s64 value, s64 max, s64 min, u32 f) { 44 | s64 ret = value; 45 | if (value > max) { 46 | gteFLAG |= f; 47 | ret = max; 48 | } else if (value < min) { 49 | gteFLAG |= f; 50 | ret = min; 51 | } 52 | return ret; 53 | } 54 | */ 55 | instruct limB1 par{ 56 | any{ 57 | // (limB1_val<31>==0b0) & (limB1_val<30:15>!=0x0000) : par{ // value > 0x00007FFF 58 | (limB1_val<31>==0b0) & (/|limB1_val<30:15>) : par{ // value > 0x00007FFF 59 | set_FLAG(0x01000000); 60 | limB1_ret = 0x7FFF; 61 | } 62 | // (limB1_lim==0b0) & (limB1_val<31>==0b1) & (limB1_val<30:15>!=0xFFFF) : par{ // value < 0xFFFF8000 63 | (limB1_lim==0b0) & (limB1_val<31>==0b1) & (^/&limB1_val<30:15>) : par{ // value < 0xFFFF8000 64 | set_FLAG(0x01000000); 65 | limB1_ret = 0x8000; 66 | } 67 | (limB1_lim==0b1) & (limB1_val<31>==0b1) : par{ // value < 0x00000000 68 | set_FLAG(0x01000000); 69 | limB1_ret = 0x0000; 70 | } 71 | else : limB1_ret = limB1_val<15:0>; 72 | } 73 | } 74 | 75 | instruct limB2 par{ 76 | any{ 77 | // (limB2_val<31>==0b0) & (limB2_val<30:15>!=0x0000) : par{ // value > 0x00007FFF 78 | (limB2_val<31>==0b0) & (/|limB2_val<30:15>) : par{ // value > 0x00007FFF 79 | set_FLAG(0x00800000); 80 | limB2_ret = 0x7FFF; 81 | } 82 | // (limB2_lim==0b0) & (limB2_val<31>==0b1) & (limB2_val<30:15>!=0xFFFF) : par{ // value < 0xFFFF8000 83 | (limB2_lim==0b0) & (limB2_val<31>==0b1) & (^/&limB2_val<30:15>) : par{ // value < 0xFFFF8000 84 | set_FLAG(0x00800000); 85 | limB2_ret = 0x8000; 86 | } 87 | (limB2_lim==0b1) & (limB2_val<31>==0b1) : par{ // value < 0x00000000 88 | set_FLAG(0x00800000); 89 | limB2_ret = 0x0000; 90 | } 91 | else : limB2_ret = limB2_val<15:0>; 92 | } 93 | } 94 | 95 | instruct limB3 par{ 96 | any{ 97 | // (limB3_val<31>==0b0) & (limB3_val<30:15>!=0x0000) : par{ // value > 0x00007FFF 98 | (limB3_val<31>==0b0) & (/|limB3_val<30:15>) : par{ // value > 0x00007FFF 99 | set_FLAG(0x00400000); 100 | limB3_ret = 0x7FFF; 101 | } 102 | // (limB3_lim==0b0) & (limB3_val<31>==0b1) & (limB3_val<30:15>!=0xFFFF) : par{ // value < 0xFFFF8000 103 | (limB3_lim==0b0) & (limB3_val<31>==0b1) & (^/&limB3_val<30:15>) : par{ // value < 0xFFFF8000 104 | set_FLAG(0x00400000); 105 | limB3_ret = 0x8000; 106 | } 107 | (limB3_lim==0b1) & (limB3_val<31>==0b1) : par{ // value < 0x00000000 108 | set_FLAG(0x00400000); 109 | limB3_ret = 0x0000; 110 | } 111 | else : limB3_ret = limB3_val<15:0>; 112 | } 113 | } 114 | 115 | // #define limC1(a) LIM((a), 0x00ff, 0x0000, (1 << 21)) 116 | instruct limC1 par{ 117 | any{ // ok 118 | (limC1_val<31>==0b0) & (limC1_val<30:8>!=0) : par{ // value > 0x00FF 119 | set_FLAG(0x00200000); 120 | limC1_ret = 0xFF; 121 | } 122 | limC1_val<31>==0b1 : par{ // value < 0x0000 123 | set_FLAG(0x00200000); 124 | limC1_ret = 0x00; 125 | } 126 | else : limC1_ret = limC1_val<7:0>; 127 | } 128 | } 129 | // #define limC2(a) LIM((a), 0x00ff, 0x0000, (1 << 20)) 130 | instruct limC2 par{ 131 | any{ // ok 132 | (limC2_val<31>==0b0) & (limC2_val<30:8>!=0) : par{ // value > 0x00FF 133 | set_FLAG(0x00100000); 134 | limC2_ret = 0xFF; 135 | } 136 | limC2_val<31>==0b1 : par{ // value < 0x0000 137 | set_FLAG(0x00100000); 138 | limC2_ret = 0x00; 139 | } 140 | else : limC2_ret = limC2_val<7:0>; 141 | } 142 | } 143 | // #define limC3(a) LIM((a), 0x00ff, 0x0000, (1 << 19)) 144 | instruct limC3 par{ 145 | any{ // ok 146 | (limC3_val<31>==0b0) & (limC3_val<30:8>!=0) : par{ // value > 0x00FF 147 | set_FLAG(0x00080000); 148 | limC3_ret = 0xFF; 149 | } 150 | limC3_val<31>==0b1 : par{ // value < 0x0000 151 | set_FLAG(0x00080000); 152 | limC3_ret = 0x00; 153 | } 154 | else : limC3_ret = limC3_val<7:0>; 155 | } 156 | } 157 | 158 | // #define limD(a) LIM((a), 0xffff, 0x0000, (1 << 18)) 159 | instruct limD par{ 160 | any{ 161 | (limD_val<31>==0b0) & (limD_val<30:16>!=0) : par{ // value > 0x0000FFFF 162 | set_FLAG(0x00040000); 163 | limD_ret = 0xFFFF; 164 | } 165 | limD_val<31>==0b1 : par{ // value < 0x00000000 166 | set_FLAG(0x00040000); 167 | limD_ret = 0x0000; 168 | } 169 | else : limD_ret = limD_val<15:0>; 170 | } 171 | } 172 | 173 | } 174 | -------------------------------------------------------------------------------- /DMA_GPU.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | DMA for GPU 3 | by pgate1 4 | */ 5 | 6 | circuit DMA_GPU 7 | { 8 | input DmaMADR_2<32>, DmaBCR_2<32>; 9 | 10 | output A<21>; 11 | instrout wram_read(A); 12 | input Din<32>; 13 | 14 | output Dout<32>; 15 | instrout gpu_dma_write_req(Dout); 16 | instrout gpu_dma_read_req(); 17 | instrout wram_write(A, Dout); 18 | 19 | reg block_count<16>, block_size<16>; 20 | reg dma_block<16>, dma_count<16>; 21 | 22 | reg madr<21>, dma_data<32>; 23 | 24 | instrin Execute_mem2vram; 25 | instrin wram_ack; 26 | output running; 27 | 28 | instrin Execute_chain; 29 | reg block_addr<21>, next_addr<24>; 30 | 31 | instrin Execute_vram2mem; 32 | 33 | input gpu_busy, gpu_drawing; 34 | instrin gpu_vram_ack; 35 | 36 | output gpu_status_ready_recieve_dmablock; 37 | 38 | instrin run33; 39 | reg trans_count<16>; 40 | reg_wr count_rst; 41 | instrout interrupt; 42 | output int_waiting; 43 | 44 | instrself halt(h_code); 45 | sel h_code<8>; 46 | reg_wr halt_code_reg<8>; 47 | output halt_code<8>; 48 | output dbg<32>; 49 | reg_wr dbg_reg<32>; 50 | 51 | stage_name run_mem2vram { task do(); } 52 | stage_name run_chain { task do(); } 53 | stage_name run_vram2mem { task do(); } 54 | stage_name int_wait { task do(count_rst); } 55 | 56 | instruct halt halt_code_reg := h_code; 57 | halt_code = halt_code_reg; 58 | //dbg = 0x000000 || count_m; 59 | //dbg = sum; 60 | dbg = dbg_reg; 61 | 62 | instruct Execute_mem2vram par{ 63 | generate run_mem2vram.do(); 64 | } 65 | 66 | instruct Execute_chain par{ 67 | generate run_chain.do(); 68 | } 69 | 70 | instruct Execute_vram2mem par{ 71 | generate run_vram2mem.do(); 72 | } 73 | 74 | running = 75 | // Execute_mem2vram | Execute_chain | Execute_vram2mem | 76 | run_mem2vram.do | run_chain.do | run_vram2mem.do; 77 | 78 | // running = 79 | // run_mem2vram.do | run_vram2mem.do | 80 | // (run_chain.do & ^gpu_drawing); 81 | 82 | gpu_status_ready_recieve_dmablock = ^(run_mem2vram.do | run_chain.do); 83 | 84 | int_waiting = int_wait.do; 85 | 86 | stage run_mem2vram { 87 | first_state st_init; 88 | state st_init par{ 89 | if(run_chain.do){ 90 | madr := block_addr; 91 | goto st_read; 92 | } 93 | else{ 94 | // u32 *ptr = (u32*)(ram + (madr>>2)); 95 | madr := DmaMADR_2<20:2> || 0b00; 96 | // u32 bcr = DmaBCR[n]; 97 | // u32 size = (bcr >> 16) * (bcr & 0xFFFF); 98 | block_count := DmaBCR_2<31:16>; 99 | block_size := DmaBCR_2<15:0>; 100 | trans_count := 0; 101 | if((DmaBCR_2<31:16>==0) | (DmaBCR_2<15:0>==0)) goto st_end; 102 | else goto st_read; 103 | } 104 | dma_count := 0; 105 | dma_block := 1; 106 | } 107 | state st_read if(wram_ack & ^gpu_busy){ 108 | wram_read(madr); 109 | madr += 4; 110 | dma_count++; 111 | trans_count++; 112 | goto st_readw; 113 | } 114 | state st_readw if(wram_ack & ^gpu_busy){ 115 | dma_data := Din; 116 | goto st_write; 117 | } 118 | state st_write if(^gpu_busy){ 119 | gpu_dma_write_req(dma_data); 120 | if(dma_count==block_size){ 121 | if(dma_block==block_count){ 122 | if(^run_chain.do) trans_count := trans_count >> 1; 123 | goto st_end; 124 | } 125 | else goto st_read; 126 | dma_count := 0; 127 | dma_block++; 128 | } 129 | else goto st_read; 130 | } 131 | state st_end if(^gpu_busy){ 132 | if(^run_chain.do){ 133 | generate int_wait.do(0b1); 134 | } 135 | goto st_init; 136 | finish; 137 | } 138 | } 139 | 140 | stage run_chain { 141 | first_state st_init; 142 | state st_init par{ 143 | next_addr := DmaMADR_2<23:0>; 144 | trans_count := 0; 145 | goto st_read; 146 | } 147 | state st_read if(wram_ack & ^gpu_busy){ 148 | wram_read(next_addr<20:2> || 0b00); 149 | block_addr := next_addr<20:0> + 4; 150 | goto st_trans; 151 | } 152 | state st_trans if(wram_ack & ^gpu_busy){ 153 | block_size := 0x00 || Din<31:24>; 154 | block_count := 0x0001; 155 | next_addr := Din<23:0>; 156 | if(Din<31:24>!=0) generate run_mem2vram.do(); 157 | goto st_end; 158 | } 159 | state st_end if(^run_mem2vram.do){ 160 | if((next_addr!=0xFFFFFF) & (next_addr<20:2>!=0)) goto st_read; 161 | else{ 162 | generate int_wait.do(0b1); 163 | goto st_init; 164 | finish; 165 | } 166 | } 167 | } 168 | 169 | stage run_vram2mem { 170 | first_state st_init; 171 | state st_init par{ 172 | // uint32 *ptr = (uint32*)(ram + (madr>>2)); 173 | madr := DmaMADR_2<20:2> || 0b00; 174 | // uint32 bcr = DmaBCR[n]; 175 | block_count := DmaBCR_2<31:16>; 176 | block_size := DmaBCR_2<15:0>; 177 | dma_count := 0; 178 | dma_block := 1; 179 | trans_count := 0; 180 | if((DmaBCR_2<31:16>==0) | (DmaBCR_2<15:0>==0)) goto st_end; 181 | else goto st_read; 182 | } 183 | state st_read if(^gpu_busy){ 184 | gpu_dma_read_req(); 185 | dma_count++; 186 | trans_count++; 187 | goto st_readw; 188 | } 189 | state st_readw if(gpu_vram_ack){ 190 | dma_data := Din; 191 | goto st_write; 192 | } 193 | state st_write if(wram_ack & ^gpu_busy){ 194 | wram_write(madr, dma_data); 195 | madr += 4; 196 | if(dma_count==block_size){ 197 | if(dma_block==block_count) goto st_end; 198 | else goto st_read; 199 | dma_count := 0; 200 | dma_block++; 201 | } 202 | else goto st_read; 203 | } 204 | state st_end if(wram_ack & ^gpu_busy){ 205 | generate int_wait.do(0b1); 206 | goto st_init; 207 | finish; 208 | } 209 | } 210 | 211 | stage int_wait { 212 | reg int_wait_count<16>; 213 | first_state st1; 214 | state st1 par{ 215 | int_wait_count := trans_count; 216 | count_rst := 0b0; 217 | if(count_rst) goto st2; 218 | } 219 | state st2 if(run33){ 220 | int_wait_count--; 221 | if(int_wait_count==0){ 222 | interrupt(); 223 | goto st1; 224 | finish; 225 | } 226 | if(count_rst) goto st1; 227 | if(run_mem2vram.do | run_chain.do | run_vram2mem.do){ 228 | goto st1; 229 | finish; 230 | } 231 | } 232 | } 233 | 234 | } 235 | -------------------------------------------------------------------------------- /DE2-115/PlayStation.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2012 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 32-bit 20 | # Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition 21 | # Date created = 17:17:58 April 07, 2016 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # PSX_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | set_global_assignment -name FAMILY "Cyclone IV E" 39 | set_global_assignment -name DEVICE EP4CE115F29C7 40 | set_global_assignment -name TOP_LEVEL_ENTITY PlayStation_top 41 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1.33" 42 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:17:58 APRIL 07, 2016" 43 | set_global_assignment -name LAST_QUARTUS_VERSION 13.1 44 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 45 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 46 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 47 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 49 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 50 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 51 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF 52 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 53 | 54 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 55 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 56 | set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64 57 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 58 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 59 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 60 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 61 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 62 | 63 | source ../../../DE2-115/DE2_115_top_assignments.qsf 64 | 65 | 66 | 67 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 68 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 69 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 70 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY 71 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW 72 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0 73 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1 74 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2 75 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0] 76 | set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1] 77 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*] 78 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*] 79 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*] 80 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*] 81 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N 82 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N 83 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CKE 84 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CLK 85 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N 86 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CS_N 87 | set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*] 88 | set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|DRAM_* 89 | set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC 90 | set_global_assignment -name VERILOG_FILE "../../../DE2-115/psx_pll/psx_pll.v" 91 | set_global_assignment -name VERILOG_FILE ../PAD.v 92 | set_global_assignment -name VERILOG_FILE ../compare_s11.v 93 | set_global_assignment -name VERILOG_FILE ../bcd_itob.v 94 | set_global_assignment -name VERILOG_FILE ../bcd_btoi.v 95 | set_global_assignment -name VERILOG_FILE ../Scratchpad.v 96 | set_global_assignment -name VERILOG_FILE ../mul_u8.v 97 | set_global_assignment -name SDC_FILE ../PlayStation.sdc 98 | set_global_assignment -name VERILOG_FILE ../PlayStation_top.v 99 | set_global_assignment -name VERILOG_FILE ../PlayStation_core.v 100 | set_global_assignment -name VERILOG_FILE ../gte_LIMIT.v 101 | set_global_assignment -name VERILOG_FILE ../gte_DIVIDE.v 102 | set_global_assignment -name VERILOG_FILE ../mul_s32.v 103 | set_global_assignment -name VERILOG_FILE ../GeometryTransformationEngine.v 104 | set_global_assignment -name VERILOG_FILE ../DMA_CDR.v 105 | set_global_assignment -name VERILOG_FILE ../ram_8x4k.v 106 | set_global_assignment -name VERILOG_FILE ../mul_s26s16.v 107 | set_global_assignment -name VERILOG_FILE ../mul_s18s16.v 108 | set_global_assignment -name VERILOG_FILE ../drawRect.v 109 | set_global_assignment -name VERILOG_FILE ../view_ram_ctrl.v 110 | set_global_assignment -name VERILOG_FILE ../demo/demo.v 111 | set_global_assignment -name VERILOG_FILE ../mul_u9.v 112 | set_global_assignment -name VERILOG_FILE ../drawFillRect.v 113 | set_global_assignment -name VERILOG_FILE ../drawPoly.v 114 | set_global_assignment -name VERILOG_FILE ../Cache_IR.v 115 | set_global_assignment -name VERILOG_FILE "../../../DE2-115/sdram100MHz_core50MHz/sdram_ctrl_100.v" 116 | set_global_assignment -name VERILOG_FILE "../../../DE2-115/sdram100MHz_core50MHz/sdram_pll_100.v" 117 | set_global_assignment -name VERILOG_FILE ../PAD_controller.v 118 | set_global_assignment -name VERILOG_FILE ../CDROM_controller.v 119 | set_global_assignment -name VERILOG_FILE ../mul_s11.v 120 | set_global_assignment -name VERILOG_FILE ../inv_table.v 121 | set_global_assignment -name VERILOG_FILE ../ram_320x240x15.v 122 | set_global_assignment -name VERILOG_FILE ../VGA_ctrl.v 123 | set_global_assignment -name VERILOG_FILE ../DMA_GPU.v 124 | set_global_assignment -name VERILOG_FILE ../ram_16x32k.v 125 | set_global_assignment -name VERILOG_FILE ../DMA_SPU.v 126 | set_global_assignment -name VERILOG_FILE ../DMA_OTC.v 127 | set_global_assignment -name VERILOG_FILE ../GraphicProcessingUnit.v 128 | set_global_assignment -name VERILOG_FILE ../../../hdl/fat16.v 129 | set_global_assignment -name VERILOG_FILE ../dsdac10.v 130 | set_global_assignment -name VERILOG_FILE "../../../DE2-115/ram_8x512.v" 131 | set_global_assignment -name VERILOG_FILE ../reverb.v 132 | set_global_assignment -name VERILOG_FILE ../bsr_s24.v 133 | set_global_assignment -name VERILOG_FILE ../RateTableSub_rom.v 134 | set_global_assignment -name VERILOG_FILE ../RateTableSub_f_rom.v 135 | set_global_assignment -name VERILOG_FILE ../RateTableAdd_rom.v 136 | set_global_assignment -name VERILOG_FILE ../RateTableAdd_f_rom.v 137 | set_global_assignment -name VERILOG_FILE ../mul_s17.v 138 | set_global_assignment -name VERILOG_FILE ../ADSR.v 139 | set_global_assignment -name VERILOG_FILE ../mul_s16s8.v 140 | set_global_assignment -name VERILOG_FILE ../bsr_s32.v 141 | set_global_assignment -name VERILOG_FILE ../bsr_s16.v 142 | set_global_assignment -name VERILOG_FILE ../mul_s16.v 143 | set_global_assignment -name VERILOG_FILE ../DigitalSignalProcessor.v 144 | set_global_assignment -name VERILOG_FILE ../DDS_50to33868800.v 145 | set_global_assignment -name VERILOG_FILE ../Timer.v 146 | set_global_assignment -name VERILOG_FILE ../../../hdl/dpram_8x512.v 147 | set_global_assignment -name VERILOG_FILE ../../../hdl/barrel_shifter_left_32.v 148 | set_global_assignment -name VERILOG_FILE ../core.v 149 | set_global_assignment -name VERILOG_FILE "../../../DE2-115/DE2_115.v" 150 | set_global_assignment -name VERILOG_FILE ../SoundProcessingUnit.v 151 | set_global_assignment -name VERILOG_FILE ../R3000A.v 152 | set_global_assignment -name VERILOG_FILE ../mul_u32.v 153 | set_global_assignment -name VERILOG_FILE ../mul_u16.v 154 | set_global_assignment -name VERILOG_FILE ../dsp_ch.v 155 | set_global_assignment -name VERILOG_FILE ../div_u32.v 156 | set_global_assignment -name CDF_FILE output_files/PlayStation.cdf 157 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /inv_table.sflp: -------------------------------------------------------------------------------- 1 | /* 2 | ((1<<15)/a)-1 3 | */ 4 | circuit inv_table 5 | { 6 | input adrs<10>; 7 | instrin read(adrs); 8 | output dout<16>; 9 | reg dout_reg<16>; 10 | 11 | mem cells[1024]<16> = { 12 | 0, 13 | 32767, 14 | 16383, 15 | 10921, 16 | 8191, 17 | 6552, 18 | 5460, 19 | 4680, 20 | 4095, 21 | 3639, 22 | 3275, 23 | 2977, 24 | 2729, 25 | 2519, 26 | 2339, 27 | 2183, 28 | 2047, 29 | 1926, 30 | 1819, 31 | 1723, 32 | 1637, 33 | 1559, 34 | 1488, 35 | 1423, 36 | 1364, 37 | 1309, 38 | 1259, 39 | 1212, 40 | 1169, 41 | 1128, 42 | 1091, 43 | 1056, 44 | 1023, 45 | 991, 46 | 962, 47 | 935, 48 | 909, 49 | 884, 50 | 861, 51 | 839, 52 | 818, 53 | 798, 54 | 779, 55 | 761, 56 | 743, 57 | 727, 58 | 711, 59 | 696, 60 | 681, 61 | 667, 62 | 654, 63 | 641, 64 | 629, 65 | 617, 66 | 605, 67 | 594, 68 | 584, 69 | 573, 70 | 563, 71 | 554, 72 | 545, 73 | 536, 74 | 527, 75 | 519, 76 | 511, 77 | 503, 78 | 495, 79 | 488, 80 | 480, 81 | 473, 82 | 467, 83 | 460, 84 | 454, 85 | 447, 86 | 441, 87 | 435, 88 | 430, 89 | 424, 90 | 419, 91 | 413, 92 | 408, 93 | 403, 94 | 398, 95 | 393, 96 | 389, 97 | 384, 98 | 380, 99 | 375, 100 | 371, 101 | 367, 102 | 363, 103 | 359, 104 | 355, 105 | 351, 106 | 347, 107 | 343, 108 | 340, 109 | 336, 110 | 333, 111 | 329, 112 | 326, 113 | 323, 114 | 320, 115 | 317, 116 | 314, 117 | 311, 118 | 308, 119 | 305, 120 | 302, 121 | 299, 122 | 296, 123 | 294, 124 | 291, 125 | 288, 126 | 286, 127 | 283, 128 | 281, 129 | 279, 130 | 276, 131 | 274, 132 | 272, 133 | 269, 134 | 267, 135 | 265, 136 | 263, 137 | 261, 138 | 259, 139 | 257, 140 | 255, 141 | 253, 142 | 251, 143 | 249, 144 | 247, 145 | 245, 146 | 243, 147 | 241, 148 | 239, 149 | 238, 150 | 236, 151 | 234, 152 | 233, 153 | 231, 154 | 229, 155 | 228, 156 | 226, 157 | 224, 158 | 223, 159 | 221, 160 | 220, 161 | 218, 162 | 217, 163 | 216, 164 | 214, 165 | 213, 166 | 211, 167 | 210, 168 | 209, 169 | 207, 170 | 206, 171 | 205, 172 | 203, 173 | 202, 174 | 201, 175 | 200, 176 | 198, 177 | 197, 178 | 196, 179 | 195, 180 | 194, 181 | 192, 182 | 191, 183 | 190, 184 | 189, 185 | 188, 186 | 187, 187 | 186, 188 | 185, 189 | 184, 190 | 183, 191 | 182, 192 | 181, 193 | 180, 194 | 179, 195 | 178, 196 | 177, 197 | 176, 198 | 175, 199 | 174, 200 | 173, 201 | 172, 202 | 171, 203 | 170, 204 | 169, 205 | 168, 206 | 167, 207 | 167, 208 | 166, 209 | 165, 210 | 164, 211 | 163, 212 | 162, 213 | 162, 214 | 161, 215 | 160, 216 | 159, 217 | 158, 218 | 158, 219 | 157, 220 | 156, 221 | 155, 222 | 155, 223 | 154, 224 | 153, 225 | 152, 226 | 152, 227 | 151, 228 | 150, 229 | 150, 230 | 149, 231 | 148, 232 | 147, 233 | 147, 234 | 146, 235 | 145, 236 | 145, 237 | 144, 238 | 143, 239 | 143, 240 | 142, 241 | 142, 242 | 141, 243 | 140, 244 | 140, 245 | 139, 246 | 139, 247 | 138, 248 | 137, 249 | 137, 250 | 136, 251 | 136, 252 | 135, 253 | 134, 254 | 134, 255 | 133, 256 | 133, 257 | 132, 258 | 132, 259 | 131, 260 | 131, 261 | 130, 262 | 130, 263 | 129, 264 | 129, 265 | 128, 266 | 128, 267 | 127, 268 | 127, 269 | 126, 270 | 126, 271 | 125, 272 | 125, 273 | 124, 274 | 124, 275 | 123, 276 | 123, 277 | 122, 278 | 122, 279 | 121, 280 | 121, 281 | 120, 282 | 120, 283 | 119, 284 | 119, 285 | 119, 286 | 118, 287 | 118, 288 | 117, 289 | 117, 290 | 116, 291 | 116, 292 | 116, 293 | 115, 294 | 115, 295 | 114, 296 | 114, 297 | 113, 298 | 113, 299 | 113, 300 | 112, 301 | 112, 302 | 111, 303 | 111, 304 | 111, 305 | 110, 306 | 110, 307 | 110, 308 | 109, 309 | 109, 310 | 108, 311 | 108, 312 | 108, 313 | 107, 314 | 107, 315 | 107, 316 | 106, 317 | 106, 318 | 106, 319 | 105, 320 | 105, 321 | 105, 322 | 104, 323 | 104, 324 | 104, 325 | 103, 326 | 103, 327 | 103, 328 | 102, 329 | 102, 330 | 102, 331 | 101, 332 | 101, 333 | 101, 334 | 100, 335 | 100, 336 | 100, 337 | 99, 338 | 99, 339 | 99, 340 | 98, 341 | 98, 342 | 98, 343 | 97, 344 | 97, 345 | 97, 346 | 97, 347 | 96, 348 | 96, 349 | 96, 350 | 95, 351 | 95, 352 | 95, 353 | 95, 354 | 94, 355 | 94, 356 | 94, 357 | 93, 358 | 93, 359 | 93, 360 | 93, 361 | 92, 362 | 92, 363 | 92, 364 | 92, 365 | 91, 366 | 91, 367 | 91, 368 | 91, 369 | 90, 370 | 90, 371 | 90, 372 | 90, 373 | 89, 374 | 89, 375 | 89, 376 | 89, 377 | 88, 378 | 88, 379 | 88, 380 | 88, 381 | 87, 382 | 87, 383 | 87, 384 | 87, 385 | 86, 386 | 86, 387 | 86, 388 | 86, 389 | 85, 390 | 85, 391 | 85, 392 | 85, 393 | 85, 394 | 84, 395 | 84, 396 | 84, 397 | 84, 398 | 83, 399 | 83, 400 | 83, 401 | 83, 402 | 83, 403 | 82, 404 | 82, 405 | 82, 406 | 82, 407 | 81, 408 | 81, 409 | 81, 410 | 81, 411 | 81, 412 | 80, 413 | 80, 414 | 80, 415 | 80, 416 | 80, 417 | 79, 418 | 79, 419 | 79, 420 | 79, 421 | 79, 422 | 78, 423 | 78, 424 | 78, 425 | 78, 426 | 78, 427 | 77, 428 | 77, 429 | 77, 430 | 77, 431 | 77, 432 | 77, 433 | 76, 434 | 76, 435 | 76, 436 | 76, 437 | 76, 438 | 75, 439 | 75, 440 | 75, 441 | 75, 442 | 75, 443 | 75, 444 | 74, 445 | 74, 446 | 74, 447 | 74, 448 | 74, 449 | 73, 450 | 73, 451 | 73, 452 | 73, 453 | 73, 454 | 73, 455 | 72, 456 | 72, 457 | 72, 458 | 72, 459 | 72, 460 | 72, 461 | 71, 462 | 71, 463 | 71, 464 | 71, 465 | 71, 466 | 71, 467 | 71, 468 | 70, 469 | 70, 470 | 70, 471 | 70, 472 | 70, 473 | 70, 474 | 69, 475 | 69, 476 | 69, 477 | 69, 478 | 69, 479 | 69, 480 | 69, 481 | 68, 482 | 68, 483 | 68, 484 | 68, 485 | 68, 486 | 68, 487 | 67, 488 | 67, 489 | 67, 490 | 67, 491 | 67, 492 | 67, 493 | 67, 494 | 66, 495 | 66, 496 | 66, 497 | 66, 498 | 66, 499 | 66, 500 | 66, 501 | 66, 502 | 65, 503 | 65, 504 | 65, 505 | 65, 506 | 65, 507 | 65, 508 | 65, 509 | 64, 510 | 64, 511 | 64, 512 | 64, 513 | 64, 514 | 64, 515 | 64, 516 | 64, 517 | 63, 518 | 63, 519 | 63, 520 | 63, 521 | 63, 522 | 63, 523 | 63, 524 | 63, 525 | 62, 526 | 62, 527 | 62, 528 | 62, 529 | 62, 530 | 62, 531 | 62, 532 | 62, 533 | 61, 534 | 61, 535 | 61, 536 | 61, 537 | 61, 538 | 61, 539 | 61, 540 | 61, 541 | 60, 542 | 60, 543 | 60, 544 | 60, 545 | 60, 546 | 60, 547 | 60, 548 | 60, 549 | 60, 550 | 59, 551 | 59, 552 | 59, 553 | 59, 554 | 59, 555 | 59, 556 | 59, 557 | 59, 558 | 59, 559 | 58, 560 | 58, 561 | 58, 562 | 58, 563 | 58, 564 | 58, 565 | 58, 566 | 58, 567 | 58, 568 | 57, 569 | 57, 570 | 57, 571 | 57, 572 | 57, 573 | 57, 574 | 57, 575 | 57, 576 | 57, 577 | 56, 578 | 56, 579 | 56, 580 | 56, 581 | 56, 582 | 56, 583 | 56, 584 | 56, 585 | 56, 586 | 56, 587 | 55, 588 | 55, 589 | 55, 590 | 55, 591 | 55, 592 | 55, 593 | 55, 594 | 55, 595 | 55, 596 | 55, 597 | 55, 598 | 54, 599 | 54, 600 | 54, 601 | 54, 602 | 54, 603 | 54, 604 | 54, 605 | 54, 606 | 54, 607 | 54, 608 | 53, 609 | 53, 610 | 53, 611 | 53, 612 | 53, 613 | 53, 614 | 53, 615 | 53, 616 | 53, 617 | 53, 618 | 53, 619 | 52, 620 | 52, 621 | 52, 622 | 52, 623 | 52, 624 | 52, 625 | 52, 626 | 52, 627 | 52, 628 | 52, 629 | 52, 630 | 52, 631 | 51, 632 | 51, 633 | 51, 634 | 51, 635 | 51, 636 | 51, 637 | 51, 638 | 51, 639 | 51, 640 | 51, 641 | 51, 642 | 51, 643 | 50, 644 | 50, 645 | 50, 646 | 50, 647 | 50, 648 | 50, 649 | 50, 650 | 50, 651 | 50, 652 | 50, 653 | 50, 654 | 50, 655 | 49, 656 | 49, 657 | 49, 658 | 49, 659 | 49, 660 | 49, 661 | 49, 662 | 49, 663 | 49, 664 | 49, 665 | 49, 666 | 49, 667 | 49, 668 | 48, 669 | 48, 670 | 48, 671 | 48, 672 | 48, 673 | 48, 674 | 48, 675 | 48, 676 | 48, 677 | 48, 678 | 48, 679 | 48, 680 | 48, 681 | 47, 682 | 47, 683 | 47, 684 | 47, 685 | 47, 686 | 47, 687 | 47, 688 | 47, 689 | 47, 690 | 47, 691 | 47, 692 | 47, 693 | 47, 694 | 47, 695 | 46, 696 | 46, 697 | 46, 698 | 46, 699 | 46, 700 | 46, 701 | 46, 702 | 46, 703 | 46, 704 | 46, 705 | 46, 706 | 46, 707 | 46, 708 | 46, 709 | 46, 710 | 45, 711 | 45, 712 | 45, 713 | 45, 714 | 45, 715 | 45, 716 | 45, 717 | 45, 718 | 45, 719 | 45, 720 | 45, 721 | 45, 722 | 45, 723 | 45, 724 | 45, 725 | 44, 726 | 44, 727 | 44, 728 | 44, 729 | 44, 730 | 44, 731 | 44, 732 | 44, 733 | 44, 734 | 44, 735 | 44, 736 | 44, 737 | 44, 738 | 44, 739 | 44, 740 | 44, 741 | 43, 742 | 43, 743 | 43, 744 | 43, 745 | 43, 746 | 43, 747 | 43, 748 | 43, 749 | 43, 750 | 43, 751 | 43, 752 | 43, 753 | 43, 754 | 43, 755 | 43, 756 | 43, 757 | 42, 758 | 42, 759 | 42, 760 | 42, 761 | 42, 762 | 42, 763 | 42, 764 | 42, 765 | 42, 766 | 42, 767 | 42, 768 | 42, 769 | 42, 770 | 42, 771 | 42, 772 | 42, 773 | 42, 774 | 42, 775 | 41, 776 | 41, 777 | 41, 778 | 41, 779 | 41, 780 | 41, 781 | 41, 782 | 41, 783 | 41, 784 | 41, 785 | 41, 786 | 41, 787 | 41, 788 | 41, 789 | 41, 790 | 41, 791 | 41, 792 | 41, 793 | 40, 794 | 40, 795 | 40, 796 | 40, 797 | 40, 798 | 40, 799 | 40, 800 | 40, 801 | 40, 802 | 40, 803 | 40, 804 | 40, 805 | 40, 806 | 40, 807 | 40, 808 | 40, 809 | 40, 810 | 40, 811 | 40, 812 | 39, 813 | 39, 814 | 39, 815 | 39, 816 | 39, 817 | 39, 818 | 39, 819 | 39, 820 | 39, 821 | 39, 822 | 39, 823 | 39, 824 | 39, 825 | 39, 826 | 39, 827 | 39, 828 | 39, 829 | 39, 830 | 39, 831 | 39, 832 | 38, 833 | 38, 834 | 38, 835 | 38, 836 | 38, 837 | 38, 838 | 38, 839 | 38, 840 | 38, 841 | 38, 842 | 38, 843 | 38, 844 | 38, 845 | 38, 846 | 38, 847 | 38, 848 | 38, 849 | 38, 850 | 38, 851 | 38, 852 | 38, 853 | 37, 854 | 37, 855 | 37, 856 | 37, 857 | 37, 858 | 37, 859 | 37, 860 | 37, 861 | 37, 862 | 37, 863 | 37, 864 | 37, 865 | 37, 866 | 37, 867 | 37, 868 | 37, 869 | 37, 870 | 37, 871 | 37, 872 | 37, 873 | 37, 874 | 37, 875 | 36, 876 | 36, 877 | 36, 878 | 36, 879 | 36, 880 | 36, 881 | 36, 882 | 36, 883 | 36, 884 | 36, 885 | 36, 886 | 36, 887 | 36, 888 | 36, 889 | 36, 890 | 36, 891 | 36, 892 | 36, 893 | 36, 894 | 36, 895 | 36, 896 | 36, 897 | 36, 898 | 35, 899 | 35, 900 | 35, 901 | 35, 902 | 35, 903 | 35, 904 | 35, 905 | 35, 906 | 35, 907 | 35, 908 | 35, 909 | 35, 910 | 35, 911 | 35, 912 | 35, 913 | 35, 914 | 35, 915 | 35, 916 | 35, 917 | 35, 918 | 35, 919 | 35, 920 | 35, 921 | 35, 922 | 35, 923 | 34, 924 | 34, 925 | 34, 926 | 34, 927 | 34, 928 | 34, 929 | 34, 930 | 34, 931 | 34, 932 | 34, 933 | 34, 934 | 34, 935 | 34, 936 | 34, 937 | 34, 938 | 34, 939 | 34, 940 | 34, 941 | 34, 942 | 34, 943 | 34, 944 | 34, 945 | 34, 946 | 34, 947 | 34, 948 | 34, 949 | 33, 950 | 33, 951 | 33, 952 | 33, 953 | 33, 954 | 33, 955 | 33, 956 | 33, 957 | 33, 958 | 33, 959 | 33, 960 | 33, 961 | 33, 962 | 33, 963 | 33, 964 | 33, 965 | 33, 966 | 33, 967 | 33, 968 | 33, 969 | 33, 970 | 33, 971 | 33, 972 | 33, 973 | 33, 974 | 33, 975 | 33, 976 | 32, 977 | 32, 978 | 32, 979 | 32, 980 | 32, 981 | 32, 982 | 32, 983 | 32, 984 | 32, 985 | 32, 986 | 32, 987 | 32, 988 | 32, 989 | 32, 990 | 32, 991 | 32, 992 | 32, 993 | 32, 994 | 32, 995 | 32, 996 | 32, 997 | 32, 998 | 32, 999 | 32, 1000 | 32, 1001 | 32, 1002 | 32, 1003 | 32, 1004 | 32, 1005 | 31, 1006 | 31, 1007 | 31, 1008 | 31, 1009 | 31, 1010 | 31, 1011 | 31, 1012 | 31, 1013 | 31, 1014 | 31, 1015 | 31, 1016 | 31, 1017 | 31, 1018 | 31, 1019 | 31, 1020 | 31, 1021 | 31, 1022 | 31, 1023 | 31, 1024 | 31, 1025 | 31, 1026 | 31, 1027 | 31, 1028 | 31, 1029 | 31, 1030 | 31, 1031 | 31, 1032 | 31, 1033 | 31, 1034 | 31, 1035 | 31 1036 | }; 1037 | 1038 | instruct read dout_reg := cells[adrs]; 1039 | dout = dout_reg; 1040 | } 1041 | -------------------------------------------------------------------------------- /Pocket/core_top.v: -------------------------------------------------------------------------------- 1 | // 2 | // User core top-level 3 | // 4 | // Instantiated by the real top-level: apf_top 5 | // 6 | 7 | `default_nettype none 8 | 9 | module core_top ( 10 | 11 | // 12 | // physical connections 13 | // 14 | 15 | /////////////////////////////////////////////////// 16 | // clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous 17 | 18 | input wire clk_74a, // mainclk1 19 | input wire clk_74b, // mainclk1 20 | 21 | /////////////////////////////////////////////////// 22 | // cartridge interface 23 | // switches between 3.3v and 5v mechanically 24 | // output enable for multibit translators controlled by pic32 25 | 26 | // GBA AD[15:8] 27 | inout wire [7:0] cart_tran_bank2, 28 | output wire cart_tran_bank2_dir, 29 | 30 | // GBA AD[7:0] 31 | inout wire [7:0] cart_tran_bank3, 32 | output wire cart_tran_bank3_dir, 33 | 34 | // GBA A[23:16] 35 | inout wire [7:0] cart_tran_bank1, 36 | output wire cart_tran_bank1_dir, 37 | 38 | // GBA [7] PHI# 39 | // GBA [6] WR# 40 | // GBA [5] RD# 41 | // GBA [4] CS1#/CS# 42 | // [3:0] unwired 43 | inout wire [7:4] cart_tran_bank0, 44 | output wire cart_tran_bank0_dir, 45 | 46 | // GBA CS2#/RES# 47 | inout wire cart_tran_pin30, 48 | output wire cart_tran_pin30_dir, 49 | // when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit 50 | // the goal is that when unconfigured, the FPGA weak pullups won't interfere. 51 | // thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators 52 | // and general IO drive this pin. 53 | output wire cart_pin30_pwroff_reset, 54 | 55 | // GBA IRQ/DRQ 56 | inout wire cart_tran_pin31, 57 | output wire cart_tran_pin31_dir, 58 | 59 | // infrared 60 | input wire port_ir_rx, 61 | output wire port_ir_tx, 62 | output wire port_ir_rx_disable, 63 | 64 | // GBA link port 65 | inout wire port_tran_si, 66 | output wire port_tran_si_dir, 67 | inout wire port_tran_so, 68 | output wire port_tran_so_dir, 69 | inout wire port_tran_sck, 70 | output wire port_tran_sck_dir, 71 | inout wire port_tran_sd, 72 | output wire port_tran_sd_dir, 73 | 74 | /////////////////////////////////////////////////// 75 | // cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) 76 | 77 | output wire [21:16] cram0_a, 78 | inout wire [15:0] cram0_dq, 79 | input wire cram0_wait, 80 | output wire cram0_clk, 81 | output wire cram0_adv_n, 82 | output wire cram0_cre, 83 | output wire cram0_ce0_n, 84 | output wire cram0_ce1_n, 85 | output wire cram0_oe_n, 86 | output wire cram0_we_n, 87 | output wire cram0_ub_n, 88 | output wire cram0_lb_n, 89 | 90 | output wire [21:16] cram1_a, 91 | inout wire [15:0] cram1_dq, 92 | input wire cram1_wait, 93 | output wire cram1_clk, 94 | output wire cram1_adv_n, 95 | output wire cram1_cre, 96 | output wire cram1_ce0_n, 97 | output wire cram1_ce1_n, 98 | output wire cram1_oe_n, 99 | output wire cram1_we_n, 100 | output wire cram1_ub_n, 101 | output wire cram1_lb_n, 102 | 103 | /////////////////////////////////////////////////// 104 | // sdram, 512mbit 16bit 105 | 106 | output wire [12:0] dram_a, 107 | output wire [1:0] dram_ba, 108 | inout wire [15:0] dram_dq, 109 | output wire [1:0] dram_dqm, 110 | output wire dram_clk, 111 | output wire dram_cke, 112 | output wire dram_ras_n, 113 | output wire dram_cas_n, 114 | output wire dram_we_n, 115 | 116 | /////////////////////////////////////////////////// 117 | // sram, 1mbit 16bit 118 | 119 | output wire [16:0] sram_a, 120 | inout wire [15:0] sram_dq, 121 | output wire sram_oe_n, 122 | output wire sram_we_n, 123 | output wire sram_ub_n, 124 | output wire sram_lb_n, 125 | 126 | /////////////////////////////////////////////////// 127 | // vblank driven by dock for sync in a certain mode 128 | 129 | input wire vblank, 130 | 131 | /////////////////////////////////////////////////// 132 | // i/o to 6515D breakout usb uart 133 | 134 | output wire dbg_tx, 135 | input wire dbg_rx, 136 | 137 | /////////////////////////////////////////////////// 138 | // i/o pads near jtag connector user can solder to 139 | 140 | output wire user1, 141 | input wire user2, 142 | 143 | /////////////////////////////////////////////////// 144 | // RFU internal i2c bus 145 | 146 | inout wire aux_sda, 147 | output wire aux_scl, 148 | 149 | /////////////////////////////////////////////////// 150 | // RFU, do not use 151 | output wire vpll_feed, 152 | 153 | 154 | // 155 | // logical connections 156 | // 157 | 158 | /////////////////////////////////////////////////// 159 | // video, audio output to scaler 160 | output wire [23:0] video_rgb, 161 | output wire video_rgb_clock, 162 | output wire video_rgb_clock_90, 163 | output wire video_de, 164 | output wire video_skip, 165 | output wire video_vs, 166 | output wire video_hs, 167 | 168 | output wire audio_mclk, 169 | input wire audio_adc, 170 | output wire audio_dac, 171 | output wire audio_lrck, 172 | 173 | /////////////////////////////////////////////////// 174 | // bridge bus connection 175 | // synchronous to clk_74a 176 | output wire bridge_endian_little, 177 | input wire [31:0] bridge_addr, 178 | input wire bridge_rd, 179 | output reg [31:0] bridge_rd_data, 180 | input wire bridge_wr, 181 | input wire [31:0] bridge_wr_data, 182 | 183 | /////////////////////////////////////////////////// 184 | // controller data 185 | // 186 | // key bitmap: 187 | // [0] dpad_up 188 | // [1] dpad_down 189 | // [2] dpad_left 190 | // [3] dpad_right 191 | // [4] face_a 192 | // [5] face_b 193 | // [6] face_x 194 | // [7] face_y 195 | // [8] trig_l1 196 | // [9] trig_r1 197 | // [10] trig_l2 198 | // [11] trig_r2 199 | // [12] trig_l3 200 | // [13] trig_r3 201 | // [14] face_select 202 | // [15] face_start 203 | // [31:28] type 204 | // joy values - unsigned 205 | // [ 7: 0] lstick_x 206 | // [15: 8] lstick_y 207 | // [23:16] rstick_x 208 | // [31:24] rstick_y 209 | // trigger values - unsigned 210 | // [ 7: 0] ltrig 211 | // [15: 8] rtrig 212 | // 213 | input wire [31:0] cont1_key, 214 | input wire [31:0] cont2_key, 215 | input wire [31:0] cont3_key, 216 | input wire [31:0] cont4_key, 217 | input wire [31:0] cont1_joy, 218 | input wire [31:0] cont2_joy, 219 | input wire [31:0] cont3_joy, 220 | input wire [31:0] cont4_joy, 221 | input wire [15:0] cont1_trig, 222 | input wire [15:0] cont2_trig, 223 | input wire [15:0] cont3_trig, 224 | input wire [15:0] cont4_trig 225 | 226 | ); 227 | 228 | // not using the IR port, so turn off both the LED, and 229 | // disable the receive circuit to save power 230 | assign port_ir_tx = 0; 231 | assign port_ir_rx_disable = 1; 232 | 233 | // bridge endianness 234 | assign bridge_endian_little = 1; 235 | 236 | // cart is unused, so set all level translators accordingly 237 | // directions are 0:IN, 1:OUT 238 | assign cart_tran_bank3 = 8'hzz; 239 | assign cart_tran_bank3_dir = 1'b0; 240 | assign cart_tran_bank2 = 8'hzz; 241 | assign cart_tran_bank2_dir = 1'b0; 242 | assign cart_tran_bank1 = 8'hzz; 243 | assign cart_tran_bank1_dir = 1'b0; 244 | assign cart_tran_bank0 = 4'hf; 245 | assign cart_tran_bank0_dir = 1'b1; 246 | assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself 247 | assign cart_tran_pin30_dir = 1'bz; 248 | assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this 249 | assign cart_tran_pin31 = 1'bz; // input 250 | assign cart_tran_pin31_dir = 1'b0; // input 251 | 252 | // link port is unused, set to input only to be safe 253 | // each bit may be bidirectional in some applications 254 | assign port_tran_so = 1'bz; 255 | assign port_tran_so_dir = 1'b0; // SO is output only 256 | assign port_tran_si = 1'bz; 257 | assign port_tran_si_dir = 1'b0; // SI is input only 258 | assign port_tran_sck = 1'bz; 259 | assign port_tran_sck_dir = 1'b0; // clock direction can change 260 | assign port_tran_sd = 1'bz; 261 | assign port_tran_sd_dir = 1'b0; // SD is input and not used 262 | 263 | // tie off the rest of the pins we are not using 264 | assign cram0_a = 'h0; 265 | assign cram0_dq = {16{1'bZ}}; 266 | assign cram0_clk = 0; 267 | assign cram0_adv_n = 1; 268 | assign cram0_cre = 0; 269 | assign cram0_ce0_n = 1; 270 | assign cram0_ce1_n = 1; 271 | assign cram0_oe_n = 1; 272 | assign cram0_we_n = 1; 273 | assign cram0_ub_n = 1; 274 | assign cram0_lb_n = 1; 275 | 276 | assign cram1_a = 'h0; 277 | assign cram1_dq = {16{1'bZ}}; 278 | assign cram1_clk = 0; 279 | assign cram1_adv_n = 1; 280 | assign cram1_cre = 0; 281 | assign cram1_ce0_n = 1; 282 | assign cram1_ce1_n = 1; 283 | assign cram1_oe_n = 1; 284 | assign cram1_we_n = 1; 285 | assign cram1_ub_n = 1; 286 | assign cram1_lb_n = 1; 287 | /* 288 | assign dram_a = 'h0; 289 | assign dram_ba = 'h0; 290 | assign dram_dq = {16{1'bZ}}; 291 | assign dram_dqm = 'h0; 292 | assign dram_clk = 'h0; 293 | assign dram_cke = 'h0; 294 | assign dram_ras_n = 'h1; 295 | assign dram_cas_n = 'h1; 296 | assign dram_we_n = 'h1; 297 | */ 298 | /* 299 | assign sram_a = 'h0; 300 | assign sram_dq = {16{1'bZ}}; 301 | assign sram_oe_n = 1; 302 | assign sram_we_n = 1; 303 | assign sram_ub_n = 1; 304 | assign sram_lb_n = 1; 305 | */ 306 | assign dbg_tx = 1'bZ; 307 | assign user1 = 1'bZ; 308 | assign aux_scl = 1'bZ; 309 | assign vpll_feed = 1'bZ; 310 | 311 | 312 | // for bridge write data, we just broadcast it to all bus devices 313 | // for bridge read data, we have to mux it 314 | // add your own devices here 315 | always @(*) begin 316 | casex(bridge_addr) 317 | default: begin 318 | // all unmapped addresses are zero 319 | bridge_rd_data <= 0; 320 | end 321 | 32'hF8xxxxxx: begin 322 | bridge_rd_data <= cmd_bridge_rd_data; 323 | end 324 | endcase 325 | end 326 | 327 | 328 | // 329 | // host/target command handler 330 | // 331 | wire reset_n; // driven by host commands, can be used as core-wide reset 332 | wire [31:0] cmd_bridge_rd_data; 333 | 334 | // bridge host commands 335 | // synchronous to clk_74a 336 | wire status_boot_done = pll_core_locked_s; 337 | wire status_setup_done = pll_core_locked_s; // rising edge triggers a target command 338 | wire status_running = reset_n; // we are running as soon as reset_n goes high 339 | 340 | wire dataslot_requestread; 341 | wire [15:0] dataslot_requestread_id; 342 | wire dataslot_requestread_ack = 1; 343 | wire dataslot_requestread_ok = 1; 344 | 345 | wire dataslot_requestwrite; 346 | wire [15:0] dataslot_requestwrite_id; 347 | wire [31:0] dataslot_requestwrite_size; 348 | wire dataslot_requestwrite_ack = 1; 349 | wire dataslot_requestwrite_ok = 1; 350 | 351 | wire dataslot_update; 352 | wire [15:0] dataslot_update_id; 353 | wire [31:0] dataslot_update_size; 354 | 355 | wire dataslot_allcomplete; 356 | 357 | wire [31:0] rtc_epoch_seconds; 358 | wire [31:0] rtc_date_bcd; 359 | wire [31:0] rtc_time_bcd; 360 | wire rtc_valid; 361 | 362 | wire savestate_supported; 363 | wire [31:0] savestate_addr; 364 | wire [31:0] savestate_size; 365 | wire [31:0] savestate_maxloadsize; 366 | 367 | wire savestate_start; 368 | wire savestate_start_ack; 369 | wire savestate_start_busy; 370 | wire savestate_start_ok; 371 | wire savestate_start_err; 372 | 373 | wire savestate_load; 374 | wire savestate_load_ack; 375 | wire savestate_load_busy; 376 | wire savestate_load_ok; 377 | wire savestate_load_err; 378 | 379 | wire osnotify_inmenu; 380 | 381 | // bridge target commands 382 | // synchronous to clk_74a 383 | 384 | reg target_dataslot_read; 385 | reg target_dataslot_write; 386 | reg target_dataslot_getfile; // require additional param/resp structs to be mapped 387 | reg target_dataslot_openfile; // require additional param/resp structs to be mapped 388 | 389 | wire target_dataslot_ack; 390 | wire target_dataslot_done; 391 | wire [2:0] target_dataslot_err; 392 | 393 | reg [15:0] target_dataslot_id; 394 | reg [31:0] target_dataslot_slotoffset; 395 | reg [31:0] target_dataslot_bridgeaddr; 396 | reg [31:0] target_dataslot_length; 397 | 398 | wire [31:0] target_buffer_param_struct; // to be mapped/implemented when using some Target commands 399 | wire [31:0] target_buffer_resp_struct; // to be mapped/implemented when using some Target commands 400 | 401 | // bridge data slot access 402 | // synchronous to clk_74a 403 | 404 | wire [9:0] datatable_addr; 405 | wire datatable_wren; 406 | wire [31:0] datatable_data; 407 | wire [31:0] datatable_q; 408 | 409 | core_bridge_cmd icb ( 410 | 411 | .clk ( clk_74a ), 412 | .reset_n ( reset_n ), 413 | 414 | .bridge_endian_little ( bridge_endian_little ), 415 | .bridge_addr ( bridge_addr ), 416 | .bridge_rd ( bridge_rd ), 417 | .bridge_rd_data ( cmd_bridge_rd_data ), 418 | .bridge_wr ( bridge_wr ), 419 | .bridge_wr_data ( bridge_wr_data ), 420 | 421 | .status_boot_done ( status_boot_done ), 422 | .status_setup_done ( status_setup_done ), 423 | .status_running ( status_running ), 424 | 425 | .dataslot_requestread ( dataslot_requestread ), 426 | .dataslot_requestread_id ( dataslot_requestread_id ), 427 | .dataslot_requestread_ack ( dataslot_requestread_ack ), 428 | .dataslot_requestread_ok ( dataslot_requestread_ok ), 429 | 430 | .dataslot_requestwrite ( dataslot_requestwrite ), 431 | .dataslot_requestwrite_id ( dataslot_requestwrite_id ), 432 | .dataslot_requestwrite_size ( dataslot_requestwrite_size ), 433 | .dataslot_requestwrite_ack ( dataslot_requestwrite_ack ), 434 | .dataslot_requestwrite_ok ( dataslot_requestwrite_ok ), 435 | 436 | .dataslot_update ( dataslot_update ), 437 | .dataslot_update_id ( dataslot_update_id ), 438 | .dataslot_update_size ( dataslot_update_size ), 439 | 440 | .dataslot_allcomplete ( dataslot_allcomplete ), 441 | 442 | .rtc_epoch_seconds ( rtc_epoch_seconds ), 443 | .rtc_date_bcd ( rtc_date_bcd ), 444 | .rtc_time_bcd ( rtc_time_bcd ), 445 | .rtc_valid ( rtc_valid ), 446 | 447 | .savestate_supported ( savestate_supported ), 448 | .savestate_addr ( savestate_addr ), 449 | .savestate_size ( savestate_size ), 450 | .savestate_maxloadsize ( savestate_maxloadsize ), 451 | 452 | .savestate_start ( savestate_start ), 453 | .savestate_start_ack ( savestate_start_ack ), 454 | .savestate_start_busy ( savestate_start_busy ), 455 | .savestate_start_ok ( savestate_start_ok ), 456 | .savestate_start_err ( savestate_start_err ), 457 | 458 | .savestate_load ( savestate_load ), 459 | .savestate_load_ack ( savestate_load_ack ), 460 | .savestate_load_busy ( savestate_load_busy ), 461 | .savestate_load_ok ( savestate_load_ok ), 462 | .savestate_load_err ( savestate_load_err ), 463 | 464 | .osnotify_inmenu ( osnotify_inmenu ), 465 | 466 | .target_dataslot_read ( target_dataslot_read ), 467 | .target_dataslot_write ( target_dataslot_write ), 468 | .target_dataslot_getfile ( target_dataslot_getfile ), 469 | .target_dataslot_openfile ( target_dataslot_openfile ), 470 | 471 | .target_dataslot_ack ( target_dataslot_ack ), 472 | .target_dataslot_done ( target_dataslot_done ), 473 | .target_dataslot_err ( target_dataslot_err ), 474 | 475 | .target_dataslot_id ( target_dataslot_id ), 476 | .target_dataslot_slotoffset ( target_dataslot_slotoffset ), 477 | .target_dataslot_bridgeaddr ( target_dataslot_bridgeaddr ), 478 | .target_dataslot_length ( target_dataslot_length ), 479 | 480 | .target_buffer_param_struct ( target_buffer_param_struct ), 481 | .target_buffer_resp_struct ( target_buffer_resp_struct ), 482 | 483 | .datatable_addr ( datatable_addr ), 484 | .datatable_wren ( datatable_wren ), 485 | .datatable_data ( datatable_data ), 486 | .datatable_q ( datatable_q ) 487 | 488 | ); 489 | 490 | 491 | 492 | // reg ram1_word_rd; 493 | reg ram1_word_wr; 494 | reg [23:0] ram1_word_addr; 495 | reg [1:0] ram1_word_wrmask; 496 | reg [31:0] ram1_word_data; 497 | // wire [31:0] ram1_word_q; 498 | // wire ram1_word_busy; 499 | 500 | reg bram_word_wr; 501 | reg sram_word_wr; 502 | 503 | reg [2:0] reload_state; 504 | reg ram_reloading; 505 | 506 | wire [15:0] target_id; 507 | wire [31:0] target_slotoffset; 508 | wire [31:0] target_bridgeaddr; 509 | wire [31:0] target_length; 510 | 511 | reg set_sdram_in, set_bram_in, set_sram_in; 512 | 513 | wire set_sdram, set_sdram_s, set_sdram_r; 514 | synch_3 s_setsdram(set_sdram, set_sdram_s, clk_74a, set_sdram_r); 515 | wire set_bram, set_bram_s, set_bram_r; 516 | synch_3 s_setbram(set_bram, set_bram_s, clk_74a, set_bram_r); 517 | wire set_sram, set_sram_s, set_sram_r; 518 | synch_3 s_setsram(set_sram, set_sram_s, clk_74a, set_sram_r); 519 | 520 | initial begin 521 | set_sdram_in <= 0; 522 | set_bram_in <= 0; 523 | set_sram_in <= 0; 524 | 525 | ram_reloading <= 0; 526 | 527 | reload_state <= 0; 528 | target_dataslot_read <= 0; 529 | end 530 | 531 | 532 | always @(posedge clk_74a) begin 533 | ram1_word_wr <= 0; 534 | bram_word_wr <= 0; 535 | sram_word_wr <= 0; 536 | // handle memory mapped I/O from pocket 537 | 538 | if(bridge_wr) begin 539 | casex(bridge_addr[31:24]) 540 | 8'b000000xx: begin 541 | // 64mbyte sdram mapped at 0x0 542 | 543 | // the ram controller's word port is 32bit aligned 544 | if(set_sdram_in) ram1_word_wr <= 1; 545 | if(set_bram_in) bram_word_wr <= 1; 546 | if(set_sram_in) sram_word_wr <= 1; 547 | 548 | ram1_word_wrmask <= 2'b00; 549 | ram1_word_addr <= bridge_addr[25:2]; 550 | ram1_word_data <= bridge_wr_data; 551 | end 552 | endcase 553 | end 554 | 555 | case(reload_state) 556 | 0: begin 557 | if(set_sdram_r | set_bram_r | set_sram_r) begin 558 | if(set_sdram_r) set_sdram_in <= 1; 559 | if(set_bram_r) set_bram_in <= 1; 560 | if(set_sram_r) set_sram_in <= 1; 561 | 562 | ram_reloading <= 1; 563 | 564 | // start the command 565 | target_dataslot_id <= target_id; 566 | target_dataslot_slotoffset <= target_slotoffset; 567 | target_dataslot_bridgeaddr <= target_bridgeaddr; 568 | target_dataslot_length <= target_length; 569 | target_dataslot_read <= 1; 570 | 571 | reload_state <= 1; 572 | end 573 | end 574 | 1: begin 575 | // wait for ack 576 | if(target_dataslot_ack) begin 577 | target_dataslot_read <= 0; 578 | // target_dataslot_write <= 0; 579 | reload_state <= 2; 580 | end 581 | end 582 | 2: begin 583 | if(target_dataslot_done) begin 584 | set_sdram_in <= 0; 585 | set_bram_in <= 0; 586 | set_sram_in <= 0; 587 | ram_reloading <= 0; 588 | reload_state <= 0; 589 | end 590 | end 591 | endcase 592 | end 593 | 594 | wire target_dataslot_read_s; 595 | synch_3 sread(target_dataslot_read, target_dataslot_read_s, clk_50); 596 | wire ram_reloading_s; 597 | synch_3 sreload(ram_reloading, ram_reloading_s, clk_50); 598 | 599 | wire word_wr_s, word_wr_r; 600 | synch_3 s3(ram1_word_wr, word_wr_s, dram_ctrl_clk, word_wr_r); 601 | 602 | reg [1:0] ram_word_wr_hold; 603 | always @(negedge reset_n or posedge clk_74a) begin 604 | if(reset_n==1'b0) begin 605 | ram_word_wr_hold <= 0; 606 | end 607 | else if(bram_word_wr | sram_word_wr) begin 608 | ram_word_wr_hold <= 1; 609 | end 610 | else if(ram_word_wr_hold!=0) begin 611 | ram_word_wr_hold <= ram_word_wr_hold + 1; 612 | end 613 | end 614 | 615 | wire ram_word_wr_hold_s, ram_word_wr_hold_r; 616 | synch_3 swrhold(|ram_word_wr_hold, ram_word_wr_hold_s, clk_50, ram_word_wr_hold_r); 617 | 618 | wire [15:0] key_s; 619 | synch_3 #(.WIDTH(16)) synch_controler(cont1_key[15:0], key_s, clk_50); 620 | 621 | //////////////////////////////////////////////////////////////////////////////////////// 622 | 623 | wire [15:0] dram_Din; 624 | wire dram_Din_En; 625 | 626 | wire [24:0] core_sdram_adrs; 627 | wire core_sdram_write; 628 | wire [127:0] core_sdram_din; 629 | wire [15:0] core_sdram_enable; 630 | wire [3:0] core_sdram_burst; 631 | wire core_sdram_read; 632 | wire [127:0] sdram_dout; 633 | wire sdram_ack_100; 634 | 635 | wire [15:0] sram_Din; 636 | wire sram_DEn; 637 | 638 | core CU ( 639 | .p_reset(~reset_n), 640 | .m_clock(clk_50), 641 | //--------------------- Pad -------------------------------- 642 | .key(key_s), 643 | //--------------------- SDRAM Interface -------------------- 644 | .sdram_write(core_sdram_write), .sdram_adrs(core_sdram_adrs), .sdram_din(core_sdram_din), 645 | .sdram_enable(core_sdram_enable), .sdram_burst(core_sdram_burst), 646 | .sdram_read(core_sdram_read), .sdram_dout(sdram_dout), 647 | .sdram_ack_100(sdram_ack_100), 648 | //--------------------- SRAM ------------------------------- 649 | .SRAM_OEn(sram_oe_n), .SRAM_WEn(sram_we_n), .SRAM_UBn(sram_ub_n), .SRAM_LBn(sram_lb_n), 650 | .SRAM_ADDR(sram_a), .SRAM_Din(sram_Din), .SRAM_DEn(sram_DEn), .SRAM_Dout(sram_dq), 651 | //--------------------- VGA -------------------------------- 652 | .VGA_HS(video_hs), .VGA_VS(video_vs), .VGA_DE(video_de), 653 | .VGA_R(video_rgb[23:16]), .VGA_G(video_rgb[15:8]), .VGA_B(video_rgb[7:0]), 654 | 655 | .set_sdram(set_sdram), .set_bram(set_bram), .set_sram(set_sram), 656 | .target_id(target_id), .target_slotoffset(target_slotoffset), 657 | .target_bridgeaddr(target_bridgeaddr), .target_length(target_length), 658 | .bram_word_wr(ram_word_wr_hold_r), .bram_wdata(ram1_word_data), 659 | .sram_word_wr(ram_word_wr_hold_r), .sram_wdata(ram1_word_data), 660 | .target_dataslot_read(target_dataslot_read_s), .ram_reloading(ram_reloading_s) 661 | ); 662 | 663 | assign dram_cke = 1'b1; 664 | assign dram_dq = dram_Din_En==1'b0 ? dram_Din : 16'hzzzz; 665 | 666 | wire sdram_write; 667 | wire [24:0] sdram_adrs; 668 | wire [127:0] sdram_din; 669 | wire [15:0] sdram_enable; 670 | wire [3:0] sdram_burst; 671 | wire sdram_read; 672 | 673 | assign sdram_write = word_wr_r | core_sdram_write; 674 | assign sdram_adrs = (word_wr_r ? {ram1_word_addr, 1'b0} : 25'b0) | ((core_sdram_write | core_sdram_read) ? core_sdram_adrs : 25'b0); 675 | assign sdram_din = (word_wr_r ? {96'b0, ram1_word_data} : 128'b0) | (core_sdram_write ? core_sdram_din : 128'b0); 676 | assign sdram_enable = (word_wr_r ? 16'h000F : 16'b0) | (core_sdram_write ? core_sdram_enable : 16'b0); 677 | assign sdram_burst = (word_wr_r ? 2 : 0) | ((core_sdram_write | core_sdram_read) ? core_sdram_burst : 0); 678 | assign sdram_read = core_sdram_read; 679 | 680 | sdram128_burstn_ctrl_100 sdram_ctrl_inst ( 681 | .p_reset(~pll_core_locked), 682 | .m_clock(dram_ctrl_clk), 683 | .RASn(dram_ras_n), 684 | .CASn(dram_cas_n), 685 | .WEn(dram_we_n), 686 | .DQM(dram_dqm), 687 | .DEn(dram_Din_En), 688 | .BA(dram_ba), 689 | .A(dram_a), 690 | .Din(dram_Din), 691 | .Dout(dram_dq), 692 | 693 | .write(sdram_write), 694 | .adrs(sdram_adrs), 695 | .din(sdram_din), 696 | .enable(sdram_enable), 697 | .burst(sdram_burst), 698 | .read(sdram_read), 699 | .dout(sdram_dout), 700 | .manual_refresh(1'b0), 701 | .refresh_go(1'b0), 702 | .ack(sdram_ack_100) 703 | ); 704 | 705 | assign sram_dq = sram_DEn==1'b0 ? sram_Din : 16'hzzzz; 706 | 707 | 708 | assign video_rgb_clock = clk_25; 709 | assign video_rgb_clock_90 = clk_25_90deg; 710 | //assign video_rgb = vidout_rgb; 711 | //assign video_de = vidout_de; 712 | assign video_skip = 0;//vidout_skip; 713 | //assign video_vs = vidout_vs; 714 | //assign video_hs = vidout_hs; 715 | 716 | 717 | 718 | // 719 | // audio i2s silence generator 720 | // see other examples for actual audio generation 721 | // 722 | 723 | assign audio_mclk = audgen_mclk; 724 | assign audio_dac = audgen_dac; 725 | assign audio_lrck = audgen_lrck; 726 | 727 | // generate MCLK = 12.288mhz with fractional accumulator 728 | reg [21:0] audgen_accum; 729 | reg audgen_mclk; 730 | parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2; 731 | always @(posedge clk_74a) begin 732 | audgen_accum <= audgen_accum + CYCLE_48KHZ; 733 | if(audgen_accum >= 21'd742500) begin 734 | audgen_mclk <= ~audgen_mclk; 735 | audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ; 736 | end 737 | end 738 | 739 | // generate SCLK = 3.072mhz by dividing MCLK by 4 740 | reg [1:0] aud_mclk_divider; 741 | wire audgen_sclk = aud_mclk_divider[1] ;// synthesis keep; 742 | reg audgen_lrck_1; 743 | always @(posedge audgen_mclk) begin 744 | aud_mclk_divider <= aud_mclk_divider + 1'b1; 745 | end 746 | 747 | // shift out audio data as I2S 748 | // 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits 749 | // 750 | reg [4:0] audgen_lrck_cnt; 751 | reg audgen_lrck; 752 | reg audgen_dac; 753 | always @(negedge audgen_sclk) begin 754 | audgen_dac <= 1'b0; 755 | // 48khz * 64 756 | audgen_lrck_cnt <= audgen_lrck_cnt + 1'b1; 757 | if(audgen_lrck_cnt == 31) begin 758 | // switch channels 759 | audgen_lrck <= ~audgen_lrck; 760 | 761 | end 762 | end 763 | 764 | 765 | /////////////////////////////////////////////// 766 | 767 | wire clk_50; 768 | wire dram_ctrl_clk; 769 | wire clk_25; 770 | wire clk_25_90deg; 771 | wire pll_core_locked; 772 | wire pll_core_locked_s; 773 | synch_3 s01(pll_core_locked, pll_core_locked_s, clk_74a); 774 | 775 | main_pll_0002 mpll ( 776 | .refclk(clk_74a), 777 | .rst(0), 778 | 779 | .outclk_0(clk_50), 780 | 781 | .outclk_1(dram_ctrl_clk), 782 | .outclk_2(dram_clk), 783 | 784 | .outclk_3(clk_25), 785 | .outclk_4(clk_25_90deg), 786 | 787 | .locked(pll_core_locked) 788 | ); 789 | 790 | 791 | endmodule 792 | --------------------------------------------------------------------------------