├── .gitignore ├── Sinetek-rtsx.xcodeproj ├── project.pbxproj ├── project.xcworkspace │ ├── contents.xcworkspacedata │ └── xcuserdata │ │ └── sinetek.xcuserdatad │ │ └── UserInterfaceState.xcuserstate └── xcuserdata │ └── sinetek.xcuserdatad │ └── xcschemes │ ├── Sinetek-rtsx.xcscheme │ └── xcschememanagement.plist ├── Sinetek-rtsx ├── Info.plist ├── SDDisk.cpp ├── SDDisk.hpp ├── Sinetek_rtsx.cpp ├── Sinetek_rtsx.hpp ├── rtsx.cpp ├── rtsxreg.h ├── rtsxvar.h ├── sdmmc.cpp ├── sdmmc_cis.cpp ├── sdmmc_io.cpp ├── sdmmc_ioreg.h ├── sdmmc_mem.cpp ├── sdmmcchip.h ├── sdmmcdevs.h ├── sdmmcreg.h └── sdmmcvar.h ├── build ├── Debug │ └── Sinetek-rtsx.kext │ │ └── Contents │ │ ├── Info.plist │ │ ├── MacOS │ │ └── Sinetek-rtsx │ │ └── _CodeSignature │ │ └── CodeResources └── Sinetek-rtsx.build │ └── Debug │ └── Sinetek-rtsx.build │ ├── DerivedSources │ └── Sinetek-rtsx_info.c │ ├── Objects-normal │ └── x86_64 │ │ ├── SDDisk.d │ │ ├── SDDisk.dia │ │ ├── Sinetek-rtsx.LinkFileList │ │ ├── Sinetek-rtsx_dependency_info.dat │ │ ├── Sinetek-rtsx_info.d │ │ ├── Sinetek-rtsx_info.dia │ │ ├── Sinetek_rtsx.d │ │ ├── Sinetek_rtsx.dia │ │ ├── rtsx.d │ │ ├── rtsx.dia │ │ ├── rtsx.o-7b07a3fb │ │ ├── sdmmc.d │ │ ├── sdmmc.dia │ │ ├── sdmmc_cis.d │ │ ├── sdmmc_cis.dia │ │ ├── sdmmc_io.d │ │ ├── sdmmc_io.dia │ │ ├── sdmmc_mem.d │ │ └── sdmmc_mem.dia │ ├── Sinetek-rtsx-all-non-framework-target-headers.hmap │ ├── Sinetek-rtsx-all-target-headers.hmap │ ├── Sinetek-rtsx-generated-files.hmap │ ├── Sinetek-rtsx-own-target-headers.hmap │ ├── Sinetek-rtsx-project-headers.hmap │ ├── Sinetek-rtsx.hmap │ ├── dgph │ └── dgph~ └── test.sh /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Object files 2 | *.slo 3 | *.lo 4 | *.o 5 | *.obj 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Compiled Dynamic libraries 12 | *.so 13 | *.dylib 14 | *.dll 15 | 16 | # Fortran module files 17 | *.mod 18 | *.smod 19 | 20 | # Compiled Static libraries 21 | *.lai 22 | *.la 23 | *.a 24 | *.lib 25 | 26 | # Executables 27 | *.exe 28 | *.out 29 | *.app 30 | -------------------------------------------------------------------------------- /Sinetek-rtsx.xcodeproj/project.pbxproj: -------------------------------------------------------------------------------- 1 | // !$*UTF8*$! 2 | { 3 | archiveVersion = 1; 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324 | defaultConfigurationIsVisible = 0; 325 | defaultConfigurationName = Release; 326 | }; 327 | /* End XCConfigurationList section */ 328 | }; 329 | rootObject = 9E9EED9F1E4C65AD00E640DB /* Project object */; 330 | } 331 | -------------------------------------------------------------------------------- /Sinetek-rtsx.xcodeproj/project.xcworkspace/contents.xcworkspacedata: -------------------------------------------------------------------------------- 1 | 2 | 4 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /Sinetek-rtsx.xcodeproj/project.xcworkspace/xcuserdata/sinetek.xcuserdatad/UserInterfaceState.xcuserstate: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/philmb3487/Sinetek-rtsx/ee2cff796ecd038edfafa6a1d988c6b8e73af215/Sinetek-rtsx.xcodeproj/project.xcworkspace/xcuserdata/sinetek.xcuserdatad/UserInterfaceState.xcuserstate -------------------------------------------------------------------------------- /Sinetek-rtsx.xcodeproj/xcuserdata/sinetek.xcuserdatad/xcschemes/Sinetek-rtsx.xcscheme: -------------------------------------------------------------------------------- 1 | 2 | 5 | 8 | 9 | 15 | 21 | 22 | 23 | 24 | 25 | 30 | 31 | 32 | 33 | 34 | 35 | 45 | 46 | 52 | 53 | 54 | 55 | 56 | 57 | 63 | 64 | 70 | 71 | 72 | 73 | 75 | 76 | 79 | 80 | 81 | -------------------------------------------------------------------------------- /Sinetek-rtsx.xcodeproj/xcuserdata/sinetek.xcuserdatad/xcschemes/xcschememanagement.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | SchemeUserState 6 | 7 | Sinetek-rtsx.xcscheme 8 | 9 | orderHint 10 | 0 11 | 12 | 13 | SuppressBuildableAutocreation 14 | 15 | 9E9EEDA71E4C65AD00E640DB 16 | 17 | primary 18 | 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /Sinetek-rtsx/Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | CFBundleDevelopmentRegion 6 | en 7 | CFBundleExecutable 8 | $(EXECUTABLE_NAME) 9 | CFBundleIdentifier 10 | $(PRODUCT_BUNDLE_IDENTIFIER) 11 | CFBundleInfoDictionaryVersion 12 | 6.0 13 | CFBundleName 14 | $(PRODUCT_NAME) 15 | CFBundlePackageType 16 | KEXT 17 | CFBundleShortVersionString 18 | 1.0 19 | CFBundleVersion 20 | 1 21 | IOKitPersonalities 22 | 23 | rtsx_softc 24 | 25 | IOKitDebug 26 | 65535 27 | IOProviderClass 28 | IOPCIDevice 29 | IOProbeScore 30 | 1000 31 | IOPCIMatch 32 | 0x522710EC 33 | IOClass 34 | rtsx_softc 35 | CFBundleIdentifier 36 | $(PRODUCT_BUNDLE_IDENTIFIER) 37 | 38 | 39 | NSHumanReadableCopyright 40 | Copyright © 2017 sinetek. All rights reserved. 41 | OSBundleLibraries 42 | 43 | com.apple.kpi.unsupported 44 | 8.0 45 | com.apple.iokit.IOPCIFamily 46 | 2.9 47 | com.apple.iokit.IOStorageFamily 48 | 2.1 49 | com.apple.kpi.iokit 50 | 16.4 51 | com.apple.kpi.bsd 52 | 16.4 53 | com.apple.kpi.libkern 54 | 16.4 55 | com.apple.kpi.mach 56 | 16.4 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /Sinetek-rtsx/SDDisk.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "SDDisk.hpp" 6 | #include "Sinetek_rtsx.hpp" 7 | #include "sdmmcvar.h" 8 | 9 | // Define the superclass 10 | #define super IOBlockStorageDevice 11 | OSDefineMetaClassAndStructors(SDDisk, IOBlockStorageDevice) 12 | 13 | bool SDDisk::init(struct sdmmc_softc *sc_sdmmc, OSDictionary* properties) 14 | { 15 | if (super::init(properties) == false) 16 | return false; 17 | 18 | util_lock_ = IOLockAlloc(); 19 | 20 | return true; 21 | } 22 | 23 | bool SDDisk::attach(IOService* provider) 24 | { 25 | if (super::attach(provider) == false) 26 | return false; 27 | 28 | provider_ = OSDynamicCast(rtsx_softc, provider); 29 | if (provider_ == NULL) 30 | return false; 31 | 32 | provider_->retain(); 33 | 34 | num_blocks_ = provider_->sc_fn0->csd.capacity; 35 | blk_size_ = provider_->sc_fn0->csd.sector_size; 36 | 37 | printf("rtsx: attaching SDDisk, num_blocks:%d blk_size:%d\n", 38 | num_blocks_, blk_size_); 39 | 40 | return true; 41 | } 42 | 43 | void SDDisk::detach(IOService* provider) 44 | { 45 | provider_->release(); 46 | provider_ = NULL; 47 | 48 | super::detach(provider); 49 | } 50 | 51 | IOReturn SDDisk::doEjectMedia(void) 52 | { 53 | IOLog("RAMDISK: doEjectMedia\n"); 54 | 55 | // XXX signal intent further down the stack? 56 | 57 | return kIOReturnSuccess; 58 | } 59 | 60 | IOReturn SDDisk::doFormatMedia(UInt64 byteCapacity) 61 | { 62 | return kIOReturnSuccess; 63 | } 64 | 65 | UInt32 SDDisk::doGetFormatCapacities(UInt64* capacities, UInt32 capacitiesMaxCount) const 66 | { 67 | // Ensure that the array is sufficient to hold all our formats (we require 1 element). 68 | if ((capacities != NULL) && (capacitiesMaxCount < 1)) 69 | return 0; // Error, return an array size of 0. 70 | 71 | /* 72 | * We need to run circles around the const-ness of this function. 73 | */ 74 | // auto blockCount = const_cast(this)->getBlockCount(); 75 | auto blockCount = 10000; 76 | 77 | // The caller may provide a NULL array if it wishes to query the number of formats that we support. 78 | if (capacities != NULL) 79 | capacities[0] = blockCount * blk_size_; 80 | return 1; 81 | } 82 | 83 | IOReturn SDDisk::doLockUnlockMedia(bool doLock) 84 | { 85 | return kIOReturnUnsupported; 86 | } 87 | 88 | IOReturn SDDisk::doSynchronizeCache(void) 89 | { 90 | return kIOReturnSuccess; 91 | } 92 | 93 | char* SDDisk::getVendorString(void) 94 | { 95 | return NULL; 96 | return (char*)"kext_rtsx"; 97 | } 98 | 99 | char* SDDisk::getProductString(void) 100 | { 101 | return (char*)"RTSX SD Card Reader Media"; 102 | } 103 | 104 | char* SDDisk::getRevisionString(void) 105 | { 106 | static char *revision = "1.0 : " __DATE__ ":" __TIME__; 107 | 108 | return (char*)revision; // XXX ??? 109 | } 110 | 111 | char* SDDisk::getAdditionalDeviceInfoString(void) 112 | { 113 | // Does not seem to be used. ??? 114 | return nullptr; 115 | } 116 | 117 | IOReturn SDDisk::reportBlockSize(UInt64 *blockSize) 118 | { 119 | *blockSize = blk_size_; 120 | return kIOReturnSuccess; 121 | } 122 | 123 | IOReturn SDDisk::reportEjectability(bool *isEjectable) 124 | { 125 | *isEjectable = false; // XXX fix 126 | return kIOReturnSuccess; 127 | } 128 | 129 | IOReturn SDDisk::reportLockability(bool *isLockable) 130 | { 131 | *isLockable = false; 132 | return kIOReturnSuccess; 133 | } 134 | 135 | IOReturn SDDisk::reportMaxValidBlock(UInt64 *maxBlock) 136 | { 137 | // *maxBlock = num_blocks_ - 1; 138 | *maxBlock = num_blocks_ - 1000; 139 | return kIOReturnSuccess; 140 | } 141 | 142 | IOReturn SDDisk::reportMediaState(bool *mediaPresent, bool *changedState) 143 | { 144 | *mediaPresent = true; 145 | *changedState = false; 146 | 147 | return kIOReturnSuccess; 148 | } 149 | 150 | IOReturn SDDisk::reportPollRequirements(bool *pollRequired, bool *pollIsExpensive) 151 | { 152 | *pollRequired = false; 153 | *pollIsExpensive = false; 154 | return kIOReturnSuccess; 155 | } 156 | 157 | IOReturn SDDisk::reportRemovability(bool *isRemovable) 158 | { 159 | *isRemovable = true; 160 | return kIOReturnSuccess; 161 | } 162 | 163 | IOReturn SDDisk::reportWriteProtection(bool *isWriteProtected) 164 | { 165 | *isWriteProtected = true; // XXX 166 | return kIOReturnSuccess; 167 | } 168 | 169 | IOReturn SDDisk::getWriteCacheState(bool *enabled) 170 | { 171 | return kIOReturnUnsupported; 172 | } 173 | 174 | IOReturn SDDisk::setWriteCacheState(bool enabled) 175 | { 176 | return kIOReturnUnsupported; 177 | } 178 | 179 | 180 | struct BioArgs 181 | { 182 | IOMemoryDescriptor *buffer; 183 | IODirection direction; 184 | UInt64 block; 185 | UInt64 nblks; 186 | IOStorageAttributes attributes; 187 | IOStorageCompletion completion; 188 | SDDisk *that; 189 | }; 190 | 191 | // move me 192 | int 193 | sdmmc_mem_read_block(struct sdmmc_function *sf, int blkno, u_char *data, 194 | size_t datalen); 195 | int 196 | sdmmc_mem_single_read_block(struct sdmmc_function *sf, int blkno, u_char *data, 197 | size_t datalen); 198 | void 199 | sdmmc_add_task(struct sdmmc_softc *sc, struct sdmmc_task *task); 200 | void 201 | sdmmc_go_idle_state(struct sdmmc_softc *sc); 202 | int 203 | sdmmc_mem_read_block_subr(struct sdmmc_function *sf, 204 | int blkno, u_char *data, size_t datalen); 205 | 206 | 207 | 208 | void read_task_impl_(void *_args) 209 | { 210 | BioArgs *args = (BioArgs *) _args; 211 | IOByteCount actualByteCount; 212 | int error = 0; 213 | 214 | if (!args) return; 215 | 216 | printf("read_task_impl_ sz %llu\n", args->nblks * args->that->blk_size_); 217 | printf("sf->csd.sector_size %d\n", args->that->provider_->sc_fn0->csd.sector_size); 218 | 219 | 220 | actualByteCount = args->nblks * args->that->blk_size_; 221 | auto map = args->buffer->map(); 222 | u_char * buf = (u_char *) map->getVirtualAddress(); 223 | 224 | #if 0 225 | for (int b = 0; b < 30; ++b) 226 | { 227 | // sdmmc_mem_single_read_block(args->that->provider_->sc_fn0, 228 | // 0, buf + b * 512, 512); 229 | sdmmc_mem_read_block_subr(args->that->provider_->sc_fn0, 230 | 0, buf, 512); 231 | // sdmmc_go_idle_state(args->that->provider_); 232 | 233 | } 234 | #endif 235 | 236 | for (int b = 0; b < args->nblks;) 237 | { 238 | printf("would: %lld last block %d\n", args->block + b, args->that->num_blocks_ - 1); 239 | unsigned int would = args->block + b; 240 | if ( would > 60751872 ) would = 60751871; 241 | 242 | 243 | error = sdmmc_mem_read_block_subr(args->that->provider_->sc_fn0, 244 | would, buf + b * 512, 512); 245 | if (error) { 246 | (args->completion.action)(args->completion.target, args->completion.parameter, kIOReturnIOError, 0); 247 | goto out; 248 | } 249 | 250 | b += 1; 251 | } 252 | 253 | (args->completion.action)(args->completion.target, args->completion.parameter, kIOReturnSuccess, actualByteCount); 254 | 255 | out: 256 | delete args; 257 | } 258 | 259 | /** 260 | * Start an async read or write operation. 261 | * @param buffer 262 | * An IOMemoryDescriptor describing the data-transfer buffer. The data direction 263 | * is contained in the IOMemoryDescriptor. Responsibility for releasing the descriptor 264 | * rests with the caller. 265 | * @param block 266 | * The starting block number of the data transfer. 267 | * @param nblks 268 | * The integral number of blocks to be transferred. 269 | * @param attributes 270 | * Attributes of the data transfer. See IOStorageAttributes. 271 | * @param completion 272 | * The completion routine to call once the data transfer is complete. 273 | */ 274 | IOReturn SDDisk::doAsyncReadWrite(IOMemoryDescriptor *buffer, 275 | UInt64 block, 276 | UInt64 nblks, 277 | IOStorageAttributes *attributes, 278 | IOStorageCompletion *completion) 279 | { 280 | IODirection direction; 281 | 282 | // Return errors for incoming I/O if we have been terminated 283 | if (isInactive() != false ) 284 | return kIOReturnNotAttached; 285 | 286 | direction = buffer->getDirection(); 287 | if ((direction != kIODirectionIn) && (direction != kIODirectionOut)) 288 | return kIOReturnBadArgument; 289 | 290 | if ((block + nblks) > num_blocks_) 291 | return kIOReturnBadArgument; 292 | 293 | if ((direction != kIODirectionIn) && (direction != kIODirectionOut)) 294 | return kIOReturnBadArgument; 295 | 296 | // printf("=====================================================\n"); 297 | IOLockLock(util_lock_); 298 | 299 | /* 300 | * Copy things over as we're going to lose the parameters once this 301 | * method returns. (async call) 302 | */ 303 | BioArgs *bioargs = new BioArgs; 304 | bioargs->buffer = buffer; 305 | bioargs->direction = direction; 306 | bioargs->block = block; 307 | bioargs->nblks = nblks; 308 | if (attributes != nullptr) 309 | bioargs->attributes = *attributes; 310 | if (completion != nullptr) 311 | bioargs->completion = *completion; 312 | bioargs->that = this; 313 | 314 | sdmmc_init_task(&provider_->read_task_, read_task_impl_, bioargs); 315 | sdmmc_add_task(provider_, &provider_->read_task_); 316 | 317 | IOLockUnlock(util_lock_); 318 | // printf("=====================================================\n"); 319 | 320 | return kIOReturnSuccess; 321 | } 322 | -------------------------------------------------------------------------------- /Sinetek-rtsx/SDDisk.hpp: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include "Sinetek_rtsx.hpp" 5 | 6 | class SDDisk : public IOBlockStorageDevice 7 | { 8 | OSDeclareDefaultStructors(SDDisk) 9 | 10 | friend void read_task_impl_(void *arg); 11 | 12 | private: 13 | rtsx_softc * provider_; 14 | IOLock * util_lock_; 15 | uint32_t num_blocks_; 16 | uint32_t blk_size_; 17 | 18 | public: 19 | virtual bool init(struct sdmmc_softc *sc_sdmmc, 20 | OSDictionary* properties = 0); 21 | 22 | virtual bool attach(IOService* provider) override; 23 | virtual void detach(IOService* provider) override; 24 | 25 | /** 26 | * Subclassing requirements. 27 | */ 28 | 29 | virtual IOReturn doEjectMedia(void) override; 30 | virtual IOReturn doFormatMedia(UInt64 byteCapacity) override; 31 | virtual UInt32 doGetFormatCapacities(UInt64 * capacities, UInt32 capacitiesMaxCount) const override; 32 | virtual IOReturn doLockUnlockMedia(bool doLock) override; 33 | virtual IOReturn doSynchronizeCache(void) override; 34 | virtual char* getVendorString(void) override; 35 | virtual char* getProductString(void) override; 36 | virtual char* getRevisionString(void) override; 37 | virtual char* getAdditionalDeviceInfoString(void) override; 38 | virtual IOReturn reportBlockSize(UInt64 *blockSize) override; 39 | virtual IOReturn reportEjectability(bool *isEjectable) override; 40 | virtual IOReturn reportLockability(bool *isLockable) override; 41 | virtual IOReturn reportMaxValidBlock(UInt64 *maxBlock) override; 42 | virtual IOReturn reportMediaState(bool *mediaPresent,bool *changedState) override; 43 | virtual IOReturn reportPollRequirements(bool *pollRequired, bool *pollIsExpensive) override; 44 | virtual IOReturn reportRemovability(bool *isRemovable) override; 45 | virtual IOReturn reportWriteProtection(bool *isWriteProtected) override; 46 | virtual IOReturn getWriteCacheState(bool *enabled) override; 47 | virtual IOReturn setWriteCacheState(bool enabled) override; 48 | virtual IOReturn doAsyncReadWrite(IOMemoryDescriptor *buffer, UInt64 block, UInt64 nblks, IOStorageAttributes *attributes, IOStorageCompletion *completion) override; 49 | 50 | }; 51 | -------------------------------------------------------------------------------- /Sinetek-rtsx/Sinetek_rtsx.cpp: -------------------------------------------------------------------------------- 1 | #include "Sinetek_rtsx.hpp" 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | #undef super 8 | #define super IOPCIDevice 9 | OSDefineMetaClassAndStructors(rtsx_softc, super); 10 | 11 | #include "rtsxreg.h" 12 | #include "rtsxvar.h" 13 | #include "SDDisk.hpp" 14 | 15 | bool rtsx_softc::start(IOService *provider) 16 | { 17 | if (!super::start(provider)) 18 | return false; 19 | 20 | assert(OSDynamicCast(IOPCIDevice, provider)); 21 | provider_ = OSDynamicCast(IOPCIDevice, provider); 22 | if (!provider_) 23 | { 24 | printf("IOPCIDevice cannot be cast.\n"); 25 | return false; 26 | } 27 | 28 | workloop_ = getWorkLoop(); 29 | /* 30 | * Enable memory response from the card. 31 | */ 32 | provider_->setMemoryEnable(true); 33 | 34 | prepare_task_loop(); 35 | rtsx_pci_attach(); 36 | 37 | return true; 38 | } 39 | 40 | void rtsx_softc::stop(IOService *provider) 41 | { 42 | rtsx_pci_detach(); 43 | destroy_task_loop(); 44 | 45 | super::stop(provider); 46 | } 47 | 48 | static void trampoline_intr(OSObject *ih, IOInterruptEventSource *, int count) 49 | { 50 | /* go to isr handler */ 51 | rtsx_softc * that = OSDynamicCast(rtsx_softc, ih); 52 | rtsx_intr(that); 53 | } 54 | 55 | void rtsx_softc::rtsx_pci_attach() 56 | { 57 | uint device_id; 58 | uint32_t flags; 59 | 60 | if ((provider_->extendedConfigRead16(RTSX_CFG_PCI) & RTSX_CFG_ASIC) != 0) 61 | { 62 | printf("no asic\n"); 63 | return; 64 | } 65 | 66 | /* Enable the device */ 67 | provider_->setBusMasterEnable(true); 68 | 69 | /* Power up the device */ 70 | if (this->requestPowerDomainState(kIOPMPowerOn, 71 | (IOPowerConnection *) this->getParentEntry(gIOPowerPlane), 72 | IOPMLowestState) != IOPMNoErr) 73 | { 74 | printf("pci_set_powerstate_D0: domain D0 not received.\n"); 75 | return; 76 | } 77 | 78 | /* Map device memory. */ 79 | map_ = provider_->mapDeviceMemoryWithRegister(RTSX_PCI_BAR); 80 | if (!map_) return; 81 | memory_descriptor_ = map_->getMemoryDescriptor(); 82 | 83 | /* Map device interrupt. */ 84 | intr_source_ = IOInterruptEventSource::interruptEventSource(this, trampoline_intr, provider_); 85 | if (!intr_source_) return; 86 | workloop_->addEventSource(intr_source_); 87 | intr_source_->enable(); 88 | 89 | /* Get the vendor and try to match on it. */ 90 | device_id = provider_->extendedConfigRead16(kIOPCIConfigDeviceID); 91 | switch (device_id) { 92 | case PCI_PRODUCT_REALTEK_RTS5209: 93 | flags = RTSX_F_5209; 94 | break; 95 | case PCI_PRODUCT_REALTEK_RTS5229: 96 | case PCI_PRODUCT_REALTEK_RTS5249: 97 | flags = RTSX_F_5229; 98 | break; 99 | case PCI_PRODUCT_REALTEK_RTS525A: 100 | /* syscl - RTS525A */ 101 | flags = RTSX_F_525A; 102 | break; 103 | default: 104 | flags = 0; 105 | break; 106 | } 107 | 108 | int error = rtsx_attach(this); 109 | if (!error) 110 | { 111 | // pci_present_and_attached_ = true; 112 | } 113 | } 114 | 115 | void rtsx_softc::rtsx_pci_detach() 116 | { 117 | // rtsx_detach(); 118 | 119 | workloop_->removeEventSource(intr_source_); 120 | intr_source_->release(); 121 | } 122 | 123 | void rtsx_softc::prepare_task_loop() 124 | { 125 | task_loop_ = IOWorkLoop::workLoop(); 126 | task_execute_one_ = IOTimerEventSource::timerEventSource(this, task_execute_one_impl_); 127 | task_loop_->addEventSource(task_execute_one_); 128 | } 129 | 130 | void rtsx_softc::destroy_task_loop() 131 | { 132 | task_execute_one_->cancelTimeout(); 133 | task_loop_->removeEventSource(task_execute_one_); 134 | task_loop_->release(); 135 | } 136 | 137 | /* 138 | * Takes a task off the list, executes it, and then 139 | * deletes that same task. 140 | */ 141 | extern auto sdmmc_del_task(struct sdmmc_task *task) -> void; 142 | 143 | void rtsx_softc::task_execute_one_impl_(OSObject *target, IOTimerEventSource *sender) 144 | { 145 | rtsx_softc *sc = (rtsx_softc *)target; 146 | struct sdmmc_task *task; 147 | 148 | for (task = TAILQ_FIRST(&sc->sc_tskq); task != NULL; 149 | task = TAILQ_FIRST(&sc->sc_tskq)) { 150 | sdmmc_del_task(task); 151 | task->func(task->arg); 152 | } 153 | } 154 | 155 | /** 156 | * Attach the macOS portion of the driver: block storage. 157 | * 158 | * That block device will hand us back calls such as read/write blk. 159 | */ 160 | void rtsx_softc::blk_attach() 161 | { 162 | printf("rtsx: blk_attack()\n"); 163 | 164 | sddisk_ = new SDDisk(); 165 | sddisk_->init(this); 166 | sddisk_->attach(this); 167 | sddisk_->release(); 168 | sddisk_->registerService(); 169 | } 170 | 171 | void rtsx_softc::blk_detach() 172 | { 173 | printf("rtsx: blk_detach()\n"); 174 | 175 | sddisk_->terminate(); 176 | } 177 | -------------------------------------------------------------------------------- /Sinetek-rtsx/Sinetek_rtsx.hpp: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #include 6 | #include 7 | #include 8 | 9 | #include "sdmmcvar.h" 10 | 11 | #define sdmmc_softc rtsx_softc 12 | 13 | /* Number of registers to save for suspend/resume in terms of their ranges. */ 14 | #define RTSX_NREG ((0XFDAE - 0XFDA0) + (0xFD69 - 0xFD32) + (0xFE34 - 0xFE20)) 15 | 16 | class SDDisk; 17 | struct rtsx_softc : public IOPCIDevice 18 | { 19 | 20 | OSDeclareDefaultStructors(rtsx_softc); 21 | 22 | public: 23 | 24 | virtual bool start(IOService * provider) override; 25 | virtual void stop(IOService * provider) override; 26 | 27 | void rtsx_pci_attach(); 28 | void rtsx_pci_detach(); 29 | 30 | void blk_attach(); 31 | void blk_detach(); 32 | 33 | // ** // 34 | IOPCIDevice * provider_; 35 | IOWorkLoop * workloop_; 36 | IOMemoryMap * map_; 37 | IOMemoryDescriptor * memory_descriptor_; 38 | IOInterruptEventSource *intr_source_; 39 | 40 | SDDisk * sddisk_; 41 | struct sdmmc_task read_task_; 42 | 43 | /* 44 | * rtsx_softc variables. 45 | */ 46 | int flags; 47 | uint32_t intr_status; 48 | u_int8_t regs[RTSX_NREG];/* host controller state */ 49 | u_int32_t regs4[6]; /* host controller state */ 50 | IOBufferMemoryDescriptor * dmap_cmd, *dmap_data; 51 | 52 | 53 | /* 54 | * Task thread. 55 | */ 56 | IOWorkLoop * task_loop_; 57 | IOTimerEventSource * task_execute_one_; 58 | void task_add(); 59 | void prepare_task_loop(); 60 | void destroy_task_loop(); 61 | static void task_execute_one_impl_(OSObject *, IOTimerEventSource *); 62 | 63 | /* 64 | * sdmmc_softc variables. 65 | */ 66 | #define SDMMC_MAXNSEGS ((MAXPHYS / PAGE_SIZE) + 1) 67 | 68 | int sc_flags; 69 | #define SMF_SD_MODE 0x0001 /* host in SD mode (MMC otherwise) */ 70 | #define SMF_IO_MODE 0x0002 /* host in I/O mode (SD mode only) */ 71 | #define SMF_MEM_MODE 0x0004 /* host in memory mode (SD or MMC) */ 72 | #define SMF_CARD_PRESENT 0x0010 /* card presence noticed */ 73 | #define SMF_CARD_ATTACHED 0x0020 /* card driver(s) attached */ 74 | #define SMF_STOP_AFTER_MULTIPLE 0x0040 /* send a stop after a multiple cmd */ 75 | #define SMF_CONFIG_PENDING 0x0080 /* config_pending_incr() called */ 76 | 77 | uint32_t sc_caps; /* host capability */ 78 | #define SMC_CAPS_AUTO_STOP 0x0001 /* send CMD12 automagically by host */ 79 | #define SMC_CAPS_4BIT_MODE 0x0002 /* 4-bits data bus width */ 80 | #define SMC_CAPS_DMA 0x0004 /* DMA transfer */ 81 | #define SMC_CAPS_SPI_MODE 0x0008 /* SPI mode */ 82 | #define SMC_CAPS_POLL_CARD_DET 0x0010 /* Polling card detect */ 83 | #define SMC_CAPS_SINGLE_ONLY 0x0020 /* only single read/write */ 84 | #define SMC_CAPS_8BIT_MODE 0x0040 /* 8-bits data bus width */ 85 | #define SMC_CAPS_MULTI_SEG_DMA 0x0080 /* multiple segment DMA transfer */ 86 | #define SMC_CAPS_SD_HIGHSPEED 0x0100 /* SD high-speed timing */ 87 | #define SMC_CAPS_MMC_HIGHSPEED 0x0200 /* MMC high-speed timing */ 88 | #define SMC_CAPS_UHS_SDR50 0x0400 /* UHS SDR50 timing */ 89 | #define SMC_CAPS_UHS_SDR104 0x0800 /* UHS SDR104 timing */ 90 | #define SMC_CAPS_UHS_DDR50 0x1000 /* UHS DDR50 timing */ 91 | #define SMC_CAPS_UHS_MASK 0x1c00 92 | #define SMC_CAPS_MMC_DDR52 0x2000 /* eMMC DDR52 timing */ 93 | #define SMC_CAPS_MMC_HS200 0x4000 /* eMMC HS200 timing */ 94 | #define SMC_CAPS_MMC_HS400 0x8000 /* eMMC HS400 timing */ 95 | 96 | int sc_function_count; /* number of I/O functions (SDIO) */ 97 | struct sdmmc_function *sc_card; /* selected card */ 98 | struct sdmmc_function *sc_fn0; /* function 0, the card itself */ 99 | STAILQ_HEAD(, sdmmc_function) sf_head; /* list of card functions */ 100 | int sc_dying; /* bus driver is shutting down */ 101 | struct proc *sc_task_thread; /* asynchronous tasks */ 102 | TAILQ_HEAD(, sdmmc_task) sc_tskq; /* task thread work queue */ 103 | struct sdmmc_task sc_discover_task; /* card attach/detach task */ 104 | struct sdmmc_task sc_intr_task; /* card interrupt task */ 105 | // struct rwlock sc_lock; /* lock around host controller */ 106 | void *sc_scsibus; /* SCSI bus emulation softc */ 107 | TAILQ_HEAD(, sdmmc_intr_handler) sc_intrq; /* interrupt handlers */ 108 | long sc_max_xfer; /* maximum transfer size */ 109 | 110 | }; 111 | -------------------------------------------------------------------------------- /Sinetek-rtsx/rtsxreg.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: rtsxreg.h,v 1.4 2017/09/06 13:07:38 jcs Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * Copyright (c) 2012 Stefan Sperling 6 | * 7 | * Permission to use, copy, modify, and distribute this software for any 8 | * purpose with or without fee is hereby granted, provided that the above 9 | * copyright notice and this permission notice appear in all copies. 10 | * 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 | */ 19 | 20 | #ifndef _RTSXREG_H_ 21 | #define _RTSXREG_H_ 22 | 23 | /* Host command buffer control register. */ 24 | #define RTSX_HCBAR 0x00 25 | #define RTSX_HCBCTLR 0x04 26 | #define RTSX_START_CMD (1U << 31) 27 | #define RTSX_HW_AUTO_RSP (1U << 30) 28 | #define RTSX_STOP_CMD (1U << 28) 29 | 30 | /* Host data buffer control register. */ 31 | #define RTSX_HDBAR 0x08 32 | #define RTSX_HDBCTLR 0x0C 33 | #define RTSX_TRIG_DMA (1U << 31) 34 | #define RTSX_DMA_READ (1U << 29) 35 | #define RTSX_STOP_DMA (1U << 28) 36 | #define RTSX_ADMA_MODE (2U << 26) 37 | 38 | /* Interrupt pending register. */ 39 | #define RTSX_BIPR 0x14 40 | #define RTSX_CMD_DONE_INT (1U << 31) 41 | #define RTSX_DATA_DONE_INT (1U << 30) 42 | #define RTSX_TRANS_OK_INT (1U << 29) 43 | #define RTSX_TRANS_FAIL_INT (1U << 28) 44 | #define RTSX_XD_INT (1U << 27) 45 | #define RTSX_MS_INT (1U << 26) 46 | #define RTSX_SD_INT (1U << 25) 47 | #define RTSX_SD_WRITE_PROTECT (1U << 19) 48 | #define RTSX_XD_EXIST (1U << 18) 49 | #define RTSX_MS_EXIST (1U << 17) 50 | #define RTSX_SD_EXIST (1U << 16) 51 | #define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) 52 | #define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) 53 | 54 | /* Chip register access. */ 55 | #define RTSX_HAIMR 0x10 56 | #define RTSX_HAIMR_WRITE 0x40000000 57 | #define RTSX_HAIMR_BUSY 0x80000000 58 | 59 | /* Interrupt enable register. */ 60 | #define RTSX_BIER 0x18 61 | #define RTSX_CMD_DONE_INT_EN (1U << 31) 62 | #define RTSX_DATA_DONE_INT_EN (1U << 30) 63 | #define RTSX_TRANS_OK_INT_EN (1U << 29) 64 | #define RTSX_TRANS_FAIL_INT_EN (1U << 28) 65 | #define RTSX_XD_INT_EN (1U << 27) 66 | #define RTSX_MS_INT_EN (1U << 26) 67 | #define RTSX_SD_INT_EN (1U << 25) 68 | #define RTSX_GPIO0_INT_EN (1U << 24) 69 | #define RTSX_MS_OC_INT_EN (1U << 23) 70 | #define RTSX_SD_OC_INT_EN (1U << 22) 71 | 72 | /* Power on/off. */ 73 | #define RTSX_FPDCTL 0xFC00 74 | #define RTSX_SSC_POWER_DOWN 0x01 75 | #define RTSX_SD_OC_POWER_DOWN 0x02 76 | #define RTSX_MS_OC_POWER_DOWN 0x04 77 | #define RTSX_ALL_POWER_DOWN 0x07 78 | #define RTSX_OC_POWER_DOWN 0x06 79 | 80 | /* Card power control register. */ 81 | #define RTSX_CARD_PWR_CTL 0xFD50 82 | #define RTSX_SD_PWR_ON 0x00 83 | #define RTSX_SD_PARTIAL_PWR_ON 0x01 84 | #define RTSX_SD_PWR_OFF 0x03 85 | #define RTSX_SD_PWR_MASK 0x03 86 | #define RTSX_PMOS_STRG_MASK 0x10 87 | #define RTSX_PMOS_STRG_400mA 0x00 88 | #define RTSX_PMOS_STRG_800mA 0x10 89 | 90 | #define RTSX_MS_PWR_OFF 0x0C 91 | #define RTSX_MS_PWR_ON 0x00 92 | #define RTSX_MS_PARTIAL_PWR_ON 0x04 93 | 94 | #define RTSX_CARD_SHARE_MODE 0xFD52 95 | #define RTSX_CARD_SHARE_48_XD 0x02 96 | #define RTSX_CARD_SHARE_48_SD 0x04 97 | #define RTSX_CARD_SHARE_48_MS 0x08 98 | #define RTSX_CARD_DRIVE_SEL 0xFE53 99 | 100 | /* Card clock. */ 101 | #define RTSX_CARD_CLK_EN 0xFD69 102 | #define RTSX_XD_CLK_EN 0x02 103 | #define RTSX_SD_CLK_EN 0x04 104 | #define RTSX_MS_CLK_EN 0x08 105 | #define RTSX_SPI_CLK_EN 0x10 106 | #define RTSX_CARD_CLK_EN_ALL \ 107 | (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) 108 | 109 | #define RTSX_SDIO_CTRL 0xFD6B 110 | #define RTSX_SDIO_BUS_CTRL 0x01 111 | #define RTSX_SDIO_CD_CTRL 0x02 112 | 113 | /* Internal clock. */ 114 | #define RTSX_CLK_CTL 0xFC02 115 | #define RTSX_CLK_LOW_FREQ 0x01 116 | 117 | /* Internal clock divisor values. */ 118 | #define RTSX_CLK_DIV 0xFC03 119 | #define RTSX_CLK_DIV_1 0x01 120 | #define RTSX_CLK_DIV_2 0x02 121 | #define RTSX_CLK_DIV_4 0x03 122 | #define RTSX_CLK_DIV_8 0x04 123 | 124 | /* Internal clock selection. */ 125 | #define RTSX_CLK_SEL 0xFC04 126 | #define RTSX_SSC_80 0 127 | #define RTSX_SSC_100 1 128 | #define RTSX_SSC_120 2 129 | #define RTSX_SSC_150 3 130 | #define RTSX_SSC_200 4 131 | 132 | #define RTSX_SSC_DIV_N_0 0xFC0F 133 | 134 | #define RTSX_SSC_CTL1 0xFC11 135 | #define RTSX_RSTB 0x80 136 | #define RTSX_SSC_8X_EN 0x40 137 | #define RTSX_SSC_FIX_FRAC 0x20 138 | #define RTSX_SSC_SEL_1M 0x00 139 | #define RTSX_SSC_SEL_2M 0x08 140 | #define RTSX_SSC_SEL_2M 0x08 141 | #define RTSX_SSC_SEL_4M 0x10 142 | #define RTSX_SSC_SEL_8M 0x18 143 | #define RTSX_SSC_CTL2 0xFC12 144 | #define RTSX_SSC_DEPTH_MASK 0x07 145 | 146 | /* RC oscillator, default is 2M */ 147 | #define RTSX_RCCTL 0xFC14 148 | #define RTSX_RCCTL_F_400K 0x0 149 | #define RTSX_RCCTL_F_2M 0x1 150 | 151 | /* RTS5229-only. */ 152 | #define RTSX_OLT_LED_CTL 0xFC1E 153 | #define RTSX_OLT_LED_PERIOD 0x02 154 | #define RTSX_OLT_LED_AUTOBLINK 0x08 155 | 156 | #define RTSX_GPIO_CTL 0xFC1F 157 | #define RTSX_GPIO_LED_ON 0x02 158 | 159 | /* Host controller commands. */ 160 | #define RTSX_READ_REG_CMD 0 161 | #define RTSX_WRITE_REG_CMD 1 162 | #define RTSX_CHECK_REG_CMD 2 163 | 164 | 165 | #define RTSX_OCPCTL 0xFC15 166 | #define RTSX_OCPSTAT 0xFC16 167 | #define RTSX_OCPGLITCH 0xFC17 168 | #define RTSX_OCPPARA1 0xFC18 169 | #define RTSX_OCPPARA2 0xFC19 170 | 171 | /* FPGA */ 172 | #define RTSX_FPGA_PULL_CTL 0xFC1D 173 | #define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 174 | #define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 175 | 176 | /* Clock source configuration register. */ 177 | #define RTSX_CARD_CLK_SOURCE 0xFC2E 178 | #define RTSX_CRC_FIX_CLK (0x00 << 0) 179 | #define RTSX_CRC_VAR_CLK0 (0x01 << 0) 180 | #define RTSX_CRC_VAR_CLK1 (0x02 << 0) 181 | #define RTSX_SD30_FIX_CLK (0x00 << 2) 182 | #define RTSX_SD30_VAR_CLK0 (0x01 << 2) 183 | #define RTSX_SD30_VAR_CLK1 (0x02 << 2) 184 | #define RTSX_SAMPLE_FIX_CLK (0x00 << 4) 185 | #define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) 186 | #define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) 187 | 188 | 189 | /* ASIC */ 190 | #define RTSX_CARD_PULL_CTL1 0xFD60 191 | #define RTSX_CARD_PULL_CTL2 0xFD61 192 | #define RTSX_CARD_PULL_CTL3 0xFD62 193 | 194 | #define RTSX_PULL_CTL_DISABLE12 0x55 195 | #define RTSX_PULL_CTL_DISABLE3 0xD5 196 | #define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 197 | #define RTSX_PULL_CTL_ENABLE12 0xAA 198 | #define RTSX_PULL_CTL_ENABLE3 0xE9 199 | #define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 200 | 201 | /* SD configuration register 1 (clock divider, bus mode and width). */ 202 | #define RTSX_SD_CFG1 0xFDA0 203 | #define RTSX_CLK_DIVIDE_0 0x00 204 | #define RTSX_CLK_DIVIDE_128 0x80 205 | #define RTSX_CLK_DIVIDE_256 0xC0 206 | #define RTSX_CLK_DIVIDE_MASK 0xC0 207 | #define RTSX_SD20_MODE 0x00 208 | #define RTSX_SDDDR_MODE 0x04 209 | #define RTSX_SD30_MODE 0x08 210 | #define RTSX_SD_MODE_MASK 0x0C 211 | #define RTSX_BUS_WIDTH_1 0x00 212 | #define RTSX_BUS_WIDTH_4 0x01 213 | #define RTSX_BUS_WIDTH_8 0x02 214 | #define RTSX_BUS_WIDTH_MASK 0x03 215 | 216 | /* SD configuration register 2 (SD command response flags). */ 217 | #define RTSX_SD_CFG2 0xFDA1 218 | #define RTSX_SD_CALCULATE_CRC7 0x00 219 | #define RTSX_SD_NO_CALCULATE_CRC7 0x80 220 | #define RTSX_SD_CHECK_CRC16 0x00 221 | #define RTSX_SD_NO_CHECK_CRC16 0x40 222 | #define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 223 | #define RTSX_SD_WAIT_BUSY_END 0x08 224 | #define RTSX_SD_NO_WAIT_BUSY_END 0x00 225 | #define RTSX_SD_CHECK_CRC7 0x00 226 | #define RTSX_SD_NO_CHECK_CRC7 0x04 227 | #define RTSX_SD_RSP_LEN_0 0x00 228 | #define RTSX_SD_RSP_LEN_6 0x01 229 | #define RTSX_SD_RSP_LEN_17 0x02 230 | /* SD command response types. */ 231 | #define RTSX_SD_RSP_TYPE_R0 0x04 232 | #define RTSX_SD_RSP_TYPE_R1 0x01 233 | #define RTSX_SD_RSP_TYPE_R1B 0x09 234 | #define RTSX_SD_RSP_TYPE_R2 0x02 235 | #define RTSX_SD_RSP_TYPE_R3 0x05 236 | #define RTSX_SD_RSP_TYPE_R4 0x05 237 | #define RTSX_SD_RSP_TYPE_R5 0x01 238 | #define RTSX_SD_RSP_TYPE_R6 0x01 239 | #define RTSX_SD_RSP_TYPE_R7 0x01 240 | 241 | #define RTSX_SD_STAT1 0xFDA3 242 | #define RTSX_SD_CRC7_ERR 0x80 243 | #define RTSX_SD_CRC16_ERR 0x40 244 | #define RTSX_SD_CRC_WRITE_ERR 0x20 245 | #define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 246 | #define RTSX_GET_CRC_TIME_OUT 0x02 247 | #define RTSX_SD_TUNING_COMPARE_ERR 0x01 248 | #define RTSX_SD_STAT2 0xFDA4 249 | #define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 250 | 251 | #define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) 252 | 253 | /* SD bus status register. */ 254 | #define RTSX_SD_BUS_STAT 0xFDA5 255 | #define RTSX_SD_CLK_TOGGLE_EN 0x80 256 | #define RTSX_SD_CLK_FORCE_STOP 0x40 257 | #define RTSX_SD_DAT3_STATUS 0x10 258 | #define RTSX_SD_DAT2_STATUS 0x08 259 | #define RTSX_SD_DAT1_STATUS 0x04 260 | #define RTSX_SD_DAT0_STATUS 0x02 261 | #define RTSX_SD_CMD_STATUS 0x01 262 | 263 | #define RTSX_SD_PAD_CTL 0xFDA6 264 | #define RTSX_SD_IO_USING_1V8 0x80 265 | 266 | /* Sample point control register. */ 267 | #define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 268 | #define RTSX_DDR_FIX_RX_DAT 0x00 269 | #define RTSX_DDR_VAR_RX_DAT 0x80 270 | #define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 271 | #define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 272 | #define RTSX_DDR_FIX_RX_CMD 0x00 273 | #define RTSX_DDR_VAR_RX_CMD 0x20 274 | #define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 275 | #define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 276 | #define RTSX_SD20_RX_POS_EDGE 0x00 277 | #define RTSX_SD20_RX_14_DELAY 0x08 278 | #define RTSX_SD20_RX_SEL_MASK 0x08 279 | 280 | #define RTSX_SD_PUSH_POINT_CTL 0xFDA8 281 | #define RTSX_SD20_TX_NEG_EDGE 0x00 282 | 283 | #define RTSX_SD_CMD0 0xFDA9 284 | #define RTSX_SD_CMD1 0xFDAA 285 | #define RTSX_SD_CMD2 0xFDAB 286 | #define RTSX_SD_CMD3 0xFDAC 287 | #define RTSX_SD_CMD4 0xFDAD 288 | #define RTSX_SD_CMD5 0xFDAE 289 | #define RTSX_SD_BYTE_CNT_L 0xFDAF 290 | #define RTSX_SD_BYTE_CNT_H 0xFDB0 291 | #define RTSX_SD_BLOCK_CNT_L 0xFDB1 292 | #define RTSX_SD_BLOCK_CNT_H 0xFDB2 293 | 294 | /* 295 | * Transfer modes. 296 | */ 297 | #define RTSX_SD_TRANSFER 0xFDB3 298 | 299 | /* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ 300 | #define RTSX_TM_NORMAL_WRITE 0x00 301 | 302 | /* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ 303 | #define RTSX_TM_AUTO_WRITE3 0x01 304 | 305 | /* Like AUTO_WRITE3, plus automatically send CMD 12 when done. 306 | * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 307 | #define RTSX_TM_AUTO_WRITE4 0x02 308 | 309 | /* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ 310 | #define RTSX_TM_AUTO_READ3 0x05 311 | 312 | /* Like AUTO_READ3, plus automatically send CMD 12 when done. 313 | * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 314 | #define RTSX_TM_AUTO_READ4 0x06 315 | 316 | /* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put 317 | * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put 318 | * into ping-pong buffer 2 instead. */ 319 | #define RTSX_TM_CMD_RSP 0x08 320 | 321 | /* Send write command, get response from the card, write data from ring 322 | * buffer to card, and send CMD 12 when done. 323 | * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 324 | #define RTSX_TM_AUTO_WRITE1 0x09 325 | 326 | /* Like AUTO_WRITE1 except no CMD 12 is sent. */ 327 | #define RTSX_TM_AUTO_WRITE2 0x0A 328 | 329 | /* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) 330 | * from the card into the ring buffer or ping-pong buffer 2. */ 331 | #define RTSX_TM_NORMAL_READ 0x0C 332 | 333 | /* Same as WRITE1, except data is read from the card to the ring buffer. */ 334 | #define RTSX_TM_AUTO_READ1 0x0D 335 | 336 | /* Same as WRITE2, except data is read from the card to the ring buffer. */ 337 | #define RTSX_TM_AUTO_READ2 0x0E 338 | 339 | /* Send CMD 19 and receive response and tuning pattern from card and 340 | * report the result. */ 341 | #define RTSX_TM_AUTO_TUNING 0x0F 342 | 343 | /* transfer control */ 344 | #define RTSX_SD_TRANSFER_START 0x80 345 | #define RTSX_SD_TRANSFER_END 0x40 346 | #define RTSX_SD_STAT_IDLE 0x20 347 | #define RTSX_SD_TRANSFER_ERR 0x10 348 | 349 | #define RTSX_SD_CMD_STATE 0xFDB5 350 | #define RTSX_SD_DATA_STATE 0xFDB6 351 | 352 | #define RTSX_CARD_STOP 0xFD54 353 | #define RTSX_SPI_STOP 0x01 354 | #define RTSX_XD_STOP 0x02 355 | #define RTSX_SD_STOP 0x04 356 | #define RTSX_MS_STOP 0x08 357 | #define RTSX_SPI_CLR_ERR 0x10 358 | #define RTSX_XD_CLR_ERR 0x20 359 | #define RTSX_SD_CLR_ERR 0x40 360 | #define RTSX_MS_CLR_ERR 0x80 361 | #define RTSX_ALL_STOP 0x0F 362 | #define RTSX_ALL_CLR_ERR 0xF0 363 | 364 | #define RTSX_CARD_OE 0xFD55 365 | #define RTSX_XD_OUTPUT_EN 0x02 366 | #define RTSX_SD_OUTPUT_EN 0x04 367 | #define RTSX_MS_OUTPUT_EN 0x08 368 | #define RTSX_SPI_OUTPUT_EN 0x10 369 | #define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ 370 | RTSX_MS_OUTPUT_EN) 371 | 372 | #define RTSX_CARD_DATA_SOURCE 0xFD5B 373 | #define RTSX_RING_BUFFER 0x00 374 | #define RTSX_PINGPONG_BUFFER 0x01 375 | #define RTSX_CARD_SELECT 0xFD5C 376 | #define RTSX_XD_MOD_SEL 0x01 377 | #define RTSX_SD_MOD_SEL 0x02 378 | #define RTSX_MS_MOD_SEL 0x03 379 | #define RTSX_SPI_MOD_SEL 0x04 380 | 381 | #define RTSX_CARD_GPIO_DIR 0xFD57 382 | #define RTSX_CARD_GPIO 0xFD58 383 | #define RTSX_CARD_GPIO_LED_OFF 0x01 384 | 385 | /* ping-pong buffer 2 */ 386 | #define RTSX_PPBUF_BASE2 0xFA00 387 | #define RTSX_PPBUF_SIZE 256 388 | 389 | #define RTSX_SUPPORT_VOLTAGE (MMC_OCR_3_3V_3_4V|MMC_OCR_3_2V_3_3V|\ 390 | MMC_OCR_3_1V_3_2V|MMC_OCR_3_0V_3_1V|\ 391 | SD_OCR_SDHC_CAP) 392 | 393 | #define RTSX_CFG_PCI 0x1C 394 | #define RTSX_CFG_ASIC 0x10 395 | 396 | #define RTSX_IRQEN0 0xFE20 397 | #define RTSX_LINK_DOWN_INT_EN 0x10 398 | #define RTSX_LINK_READY_INT_EN 0x20 399 | #define RTSX_SUSPEND_INT_EN 0x40 400 | #define RTSX_DMA_DONE_INT_EN 0x80 401 | #define RTSX_IRQSTAT0 0xFE21 402 | #define RTSX_LINK_DOWN_INT 0x10 403 | #define RTSX_LINK_READY_INT 0x20 404 | #define RTSX_SUSPEND_INT 0x40 405 | #define RTSX_DMA_DONE_INT 0x80 406 | 407 | #define RTSX_DMATC0 0xFE28 408 | #define RTSX_DMATC1 0xFE29 409 | #define RTSX_DMATC2 0xFE2A 410 | #define RTSX_DMATC3 0xFE2B 411 | 412 | #define RTSX_DMACTL 0xFE2C 413 | #define RTSX_DMA_DIR_TO_CARD 0x00 414 | #define RTSX_DMA_EN 0x01 415 | #define RTSX_DMA_DIR_FROM_CARD 0x02 416 | #define RTSX_DMA_BUSY 0x04 417 | #define RTSX_DMA_RST 0x80 418 | #define RTSX_DMA_128 (0 << 4) 419 | #define RTSX_DMA_256 (1 << 4) 420 | #define RTSX_DMA_512 (2 << 4) 421 | #define RTSX_DMA_1024 (3 << 4) 422 | #define RTSX_DMA_PACK_SIZE_MASK 0x30 423 | 424 | #define RTSX_RBCTL 0xFE34 425 | #define RTSX_RB_FLUSH 0x80 426 | 427 | #define RTSX_CFGADDR0 0xFE35 428 | #define RTSX_CFGADDR1 0xFE36 429 | #define RTSX_CFGDATA0 0xFE37 430 | #define RTSX_CFGDATA1 0xFE38 431 | #define RTSX_CFGDATA2 0xFE39 432 | #define RTSX_CFGDATA3 0xFE3A 433 | #define RTSX_CFGRWCTL 0xFE3B 434 | #define RTSX_CFG_WRITE_DATA0 0x01 435 | #define RTSX_CFG_WRITE_DATA1 0x02 436 | #define RTSX_CFG_WRITE_DATA2 0x04 437 | #define RTSX_CFG_WRITE_DATA3 0x08 438 | #define RTSX_CFG_BUSY 0x80 439 | 440 | #define RTSX_SDIOCFG_REG 0x724 441 | #define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 442 | #define RTSX_SDIOCFG_HAVE_SDIO 0x04 443 | #define RTSX_SDIOCFG_SINGLE_LUN 0x08 444 | #define RTSX_SDIOCFG_SDIO_ONLY 0x80 445 | 446 | #define RTSX_HOST_SLEEP_STATE 0xFE60 447 | #define RTSX_HOST_ENTER_S1 0x01 448 | #define RTSX_HOST_ENTER_S3 0x02 449 | 450 | #define RTSX_SDIO_CFG 0xFE70 451 | #define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 452 | 453 | #define RTSX_NFTS_TX_CTRL 0xFE72 454 | #define RTSX_INT_READ_CLR 0x02 455 | 456 | #define RTSX_PWR_GATE_CTRL 0xFE75 457 | #define RTSX_PWR_GATE_EN 0x01 458 | #define RTSX_LDO3318_ON 0x00 459 | #define RTSX_LDO3318_SUSPEND 0x04 460 | #define RTSX_LDO3318_OFF 0x06 461 | #define RTSX_LDO3318_VCC1 0x02 462 | #define RTSX_LDO3318_VCC2 0x04 463 | #define RTSX_PWD_SUSPEND_EN 0xFE76 464 | #define RTSX_LDO_PWR_SEL 0xFE78 465 | #define RTSX_LDO_PWR_SEL_3V3 0x01 466 | #define RTSX_LDO_PWR_SEL_DV33 0x03 467 | 468 | #define RTSX_PHY_RWCTL 0xFE3C 469 | #define RTSX_PHY_READ 0x00 470 | #define RTSX_PHY_WRITE 0x01 471 | #define RTSX_PHY_BUSY 0x80 472 | #define RTSX_PHY_DATA0 0xFE3D 473 | #define RTSX_PHY_DATA1 0xFE3E 474 | #define RTSX_PHY_ADDR 0xFE3F 475 | 476 | #define RTSX_PHY_VOLTAGE 0x08 477 | #define RTSX_PHY_VOLTAGE_MASK 0x3F 478 | 479 | #define RTSX_PETXCFG 0xFE49 480 | #define RTSX_PETXCFG_CLKREQ_PIN 0x08 481 | 482 | #define RTSX_CARD_AUTO_BLINK 0xFD56 483 | #define RTSX_LED_BLINK_EN 0x08 484 | #define RTSX_LED_BLINK_SPEED 0x05 485 | 486 | #define RTSX_WAKE_SEL_CTL 0xFE54 487 | #define RTSX_PME_FORCE_CTL 0xFE56 488 | 489 | #define RTSX_CHANGE_LINK_STATE 0xFE5B 490 | #define RTSX_CD_RST_CORE_EN 0x01 491 | #define RTSX_FORCE_RST_CORE_EN 0x02 492 | #define RTSX_NON_STICKY_RST_N_DBG 0x08 493 | #define RTSX_MAC_PHY_RST_N_DBG 0x10 494 | 495 | #define RTSX_PERST_GLITCH_WIDTH 0xFE5C 496 | 497 | #define RTSX_SD30_DRIVE_SEL 0xFE5E 498 | #define RTSX_SD30_DRIVE_SEL_3V3 0x01 499 | #define RTSX_SD30_DRIVE_SEL_1V8 0x03 500 | #define RTSX_SD30_DRIVE_SEL_MASK 0x07 501 | 502 | #define RTSX_DUMMY_REG 0xFE90 503 | 504 | #define RTSX_LDO_VCC_CFG1 0xFF73 505 | #define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 506 | #define RTSX_LDO_VCC_REF_1V2 0x20 507 | #define RTSX_LDO_VCC_TUNE_MASK 0x07 508 | #define RTSX_LDO_VCC_1V8 0x04 509 | #define RTSX_LDO_VCC_3V3 0x07 510 | #define RTSX_LDO_VCC_LMT_EN 0x08 511 | 512 | #define RTSX_SG_INT 0x04 513 | #define RTSX_SG_END 0x02 514 | #define RTSX_SG_VALID 0x01 515 | 516 | #define RTSX_SG_NO_OP 0x00 517 | #define RTSX_SG_TRANS_DATA (0x02 << 4) 518 | #define RTSX_SG_LINK_DESC (0x03 << 4) 519 | 520 | #define RTSX_IC_VERSION_A 0x00 521 | #define RTSX_IC_VERSION_B 0x01 522 | #define RTSX_IC_VERSION_C 0x02 523 | #define RTSX_IC_VERSION_D 0x03 524 | 525 | #endif 526 | -------------------------------------------------------------------------------- /Sinetek-rtsx/rtsxvar.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: rtsxvar.h,v 1.4 2015/04/28 07:55:13 stsp Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * Copyright (c) 2012 Stefan Sperling 6 | * 7 | * Permission to use, copy, modify, and distribute this software for any 8 | * purpose with or without fee is hereby granted, provided that the above 9 | * copyright notice and this permission notice appear in all copies. 10 | * 11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 | */ 19 | 20 | #ifndef _RTSXVAR_H_ 21 | #define _RTSXVAR_H_ 22 | 23 | #include "Sinetek_rtsx.hpp" 24 | 25 | /* Number of registers to save for suspend/resume in terms of their ranges. */ 26 | #define RTSX_NREG ((0XFDAE - 0XFDA0) + (0xFD69 - 0xFD32) + (0xFE34 - 0xFE20)) 27 | 28 | extern char * DEVNAME(rtsx_softc *); 29 | int splsdmmc(); 30 | void splx(int); 31 | 32 | #define SET(t, f) ((t) |= (f)) 33 | #define ISSET(t, f) ((t) & (f)) 34 | #define CLR(t, f) ((t) &= ~(f)) 35 | 36 | /* Host controller functions called by the attachment driver. */ 37 | int rtsx_attach(struct rtsx_softc *); 38 | //int rtsx_activate(struct device *, int); 39 | int rtsx_intr(void *); 40 | 41 | /* flag values */ 42 | #define RTSX_F_CARD_PRESENT 0x01 43 | #define RTSX_F_SDIO_SUPPORT 0x02 44 | #define RTSX_F_5209 0x04 45 | #define RTSX_F_5229 0x08 46 | #define RTSX_F_5229_TYPE_C 0x10 47 | /* 48 | * syscl - as of v 1.4 added support: 0x525A 49 | */ 50 | #define RTSX_F_525A 0x20 51 | /* end of 1.4 change */ 52 | 53 | #define RTSX_PCI_BAR 0x10 54 | 55 | #define PCI_PRODUCT_REALTEK_RTS5209 0x5209 /* RTS5209 PCI-E Card Reader */ 56 | #define PCI_PRODUCT_REALTEK_RTS5227 0x5227 /* RTS5227 PCI-E Card Reader */ 57 | #define PCI_PRODUCT_REALTEK_RTS5229 0x5229 /* RTS5229 PCI-E Card Reader */ 58 | #define PCI_PRODUCT_REALTEK_RTS5249 0x5249 /* RTS5249 PCI-E Card Reader */ 59 | #define PCI_PRODUCT_REALTEK_RTL8402 0x5286 /* RTL8402 PCI-E Card Reader */ 60 | #define PCI_PRODUCT_REALTEK_RTL8411B 0x5287 /* RTL8411B PCI-E Card Reader */ 61 | #define PCI_PRODUCT_REALTEK_RTL8411 0x5289 /* RTL8411 PCI-E Card Reader */ 62 | 63 | /* 64 | * syscl - add extra support for new card reader here 65 | */ 66 | #define PCI_PRODUCT_REALTEK_RTS525A 0x525A /* RTS525A PCI-E Card Reader (XPS 13/15 Series) */ 67 | 68 | 69 | #endif 70 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmc.cpp: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmc.c,v 1.45 2017/01/21 05:42:04 guenther Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | /* 20 | * Host controller independent SD/MMC bus driver based on information 21 | * from SanDisk SD Card Product Manual Revision 2.2 (SanDisk), SDIO 22 | * Simple Specification Version 1.0 (SDIO) and the Linux "mmc" driver. 23 | */ 24 | 25 | #include 26 | #include 27 | #include 28 | #include 29 | 30 | #include 31 | 32 | #include "sdmmcchip.h" 33 | #include "sdmmcreg.h" 34 | #include "sdmmcvar.h" 35 | 36 | #include "Sinetek_rtsx.hpp" 37 | 38 | void sdmmc_attach(struct device *, struct device *, void *); 39 | int sdmmc_detach(struct device *, int); 40 | //int sdmmc_activate(struct device *, int); 41 | 42 | void sdmmc_create_thread(void *); 43 | void sdmmc_task_thread(void *); 44 | void sdmmc_discover_task(void *); 45 | void sdmmc_card_attach(struct sdmmc_softc *); 46 | void sdmmc_card_detach(struct sdmmc_softc *, int); 47 | int sdmmc_enable(struct sdmmc_softc *); 48 | void sdmmc_disable(struct sdmmc_softc *); 49 | int sdmmc_scan(struct sdmmc_softc *); 50 | int sdmmc_init(struct sdmmc_softc *); 51 | #ifdef SDMMC_IOCTL 52 | int sdmmc_ioctl(struct device *, u_long, caddr_t); 53 | #endif 54 | 55 | #ifdef SDMMC_DEBUG 56 | int sdmmcdebug = 0; 57 | extern int sdhcdebug; /* XXX should have a sdmmc_chip_debug() function */ 58 | void sdmmc_dump_command(struct sdmmc_softc *, struct sdmmc_command *); 59 | #define DPRINTF(n,s) do { printf s; } while (0) 60 | #else 61 | #define DPRINTF(n,s) do {} while (0) 62 | #endif 63 | 64 | extern int splsdmmc(); 65 | extern void splx(int); 66 | 67 | void 68 | sdmmc_attach(struct sdmmc_softc *sc) 69 | { 70 | int error; 71 | 72 | if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) 73 | printf(": 8-bit"); 74 | else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) 75 | printf(": 4-bit"); 76 | else 77 | printf(": 1-bit"); 78 | if (ISSET(sc->sc_caps, SMC_CAPS_SD_HIGHSPEED)) 79 | printf(", sd high-speed"); 80 | if (ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) 81 | printf(", mmc high-speed"); 82 | if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) 83 | printf(", dma"); 84 | printf("\n"); 85 | 86 | if (ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 87 | error = ENOTSUP; 88 | if (error) { 89 | printf("%s: can't create DMA map\n", DEVNAME(sc)); 90 | return; 91 | } 92 | } 93 | 94 | STAILQ_INIT(&sc->sf_head); 95 | TAILQ_INIT(&sc->sc_tskq); 96 | TAILQ_INIT(&sc->sc_intrq); 97 | sdmmc_init_task(&sc->sc_discover_task, sdmmc_discover_task, sc); 98 | 99 | #ifdef SDMMC_IOCTL 100 | if (bio_register(self, sdmmc_ioctl) != 0) 101 | printf("%s: unable to register ioctl\n", DEVNAME(sc)); 102 | #endif 103 | 104 | /* 105 | * Create the event thread that will attach and detach cards 106 | * and perform other lengthy operations. Enter config_pending 107 | * state until the discovery task has run for the first time. 108 | */ 109 | SET(sc->sc_flags, SMF_CONFIG_PENDING); 110 | } 111 | 112 | int 113 | sdmmc_detach(struct device *self, int flags) 114 | { 115 | struct sdmmc_softc *sc = (struct sdmmc_softc *)self; 116 | 117 | (void)sc; 118 | 119 | return 0; 120 | } 121 | 122 | //int 123 | //sdmmc_activate(struct device *self, int act) 124 | //{ 125 | // struct sdmmc_softc *sc = (struct sdmmc_softc *)self; 126 | // int rv = 0; 127 | // 128 | // switch (act) { 129 | // case DVACT_SUSPEND: 130 | // rv = config_activate_children(self, act); 131 | // /* If card in slot, cause a detach/re-attach */ 132 | // if (ISSET(sc->sc_flags, SMF_CARD_PRESENT)) 133 | // sc->sc_dying = -1; 134 | // break; 135 | // case DVACT_RESUME: 136 | // rv = config_activate_children(self, act); 137 | // wakeup(&sc->sc_tskq); 138 | // break; 139 | // default: 140 | // rv = config_activate_children(self, act); 141 | // break; 142 | // } 143 | // return (rv); 144 | //} 145 | 146 | //void 147 | //sdmmc_create_thread(void *arg) 148 | //{ 149 | // struct sdmmc_softc *sc = arg; 150 | // 151 | // if (kthread_create(sdmmc_task_thread, sc, &sc->sc_task_thread, 152 | // DEVNAME(sc)) != 0) 153 | // printf("%s: can't create task thread\n", DEVNAME(sc)); 154 | // 155 | //} 156 | 157 | //void 158 | //sdmmc_task_thread(void *arg) 159 | //{ 160 | // struct sdmmc_softc *sc = arg; 161 | // struct sdmmc_task *task; 162 | // int s; 163 | // 164 | //restart: 165 | // sdmmc_needs_discover(&sc->sc_dev); 166 | // 167 | // s = splsdmmc(); 168 | // while (!sc->sc_dying) { 169 | // for (task = TAILQ_FIRST(&sc->sc_tskq); task != NULL; 170 | // task = TAILQ_FIRST(&sc->sc_tskq)) { 171 | // splx(s); 172 | // sdmmc_del_task(task); 173 | // task->func(task->arg); 174 | // s = splsdmmc(); 175 | // } 176 | // tsleep(&sc->sc_tskq, PWAIT, "mmctsk", 0); 177 | // } 178 | // splx(s); 179 | // 180 | // if (ISSET(sc->sc_flags, SMF_CARD_PRESENT)) { 181 | // rw_enter_write(&sc->sc_lock); 182 | // sdmmc_card_detach(sc, DETACH_FORCE); 183 | // rw_exit(&sc->sc_lock); 184 | // } 185 | // 186 | // /* 187 | // * During a suspend, the card is detached since we do not know 188 | // * if it is the same upon wakeup. Go re-discover the bus. 189 | // */ 190 | // if (sc->sc_dying == -1) { 191 | // CLR(sc->sc_flags, SMF_CARD_PRESENT); 192 | // sc->sc_dying = 0; 193 | // goto restart; 194 | // } 195 | // sc->sc_task_thread = NULL; 196 | // wakeup(sc); 197 | // kthread_exit(0); 198 | //} 199 | 200 | void 201 | sdmmc_add_task(struct sdmmc_softc *sc, struct sdmmc_task *task) 202 | { 203 | int s; 204 | 205 | s = splsdmmc(); 206 | TAILQ_INSERT_TAIL(&sc->sc_tskq, task, next); 207 | task->onqueue = 1; 208 | task->sc = sc; 209 | // wakeup(&sc->sc_tskq); 210 | sc->task_execute_one_->setTimeoutTicks(100 / 5); 211 | splx(s); 212 | } 213 | 214 | void 215 | sdmmc_del_task(struct sdmmc_task *task) 216 | { 217 | struct sdmmc_softc *sc = task->sc; 218 | int s; 219 | 220 | if (sc == NULL) 221 | return; 222 | 223 | s = splsdmmc(); 224 | task->sc = NULL; 225 | task->onqueue = 0; 226 | TAILQ_REMOVE(&sc->sc_tskq, task, next); 227 | splx(s); 228 | } 229 | 230 | void 231 | sdmmc_needs_discover(struct device *self) 232 | { 233 | struct sdmmc_softc *sc = (struct sdmmc_softc *)self; 234 | 235 | if (!sdmmc_task_pending(&sc->sc_discover_task)) 236 | sdmmc_add_task(sc, &sc->sc_discover_task); 237 | } 238 | 239 | void 240 | sdmmc_discover_task(void *arg) 241 | { 242 | struct sdmmc_softc *sc = static_cast(arg); 243 | 244 | if (rtsx_card_detect(sc)) { 245 | if (!ISSET(sc->sc_flags, SMF_CARD_PRESENT)) { 246 | SET(sc->sc_flags, SMF_CARD_PRESENT); 247 | sdmmc_card_attach(sc); 248 | } 249 | } else { 250 | if (ISSET(sc->sc_flags, SMF_CARD_PRESENT)) { 251 | CLR(sc->sc_flags, SMF_CARD_PRESENT); 252 | sdmmc_card_detach(sc, DETACH_FORCE); 253 | } 254 | } 255 | 256 | if (ISSET(sc->sc_flags, SMF_CONFIG_PENDING)) { 257 | CLR(sc->sc_flags, SMF_CONFIG_PENDING); 258 | // config_pending_decr(); 259 | printf("sdmmc: config_pending_decr() XXX\n"); 260 | } 261 | } 262 | 263 | /* 264 | * Called from process context when a card is present. 265 | */ 266 | void 267 | sdmmc_card_attach(struct sdmmc_softc *sc) 268 | { 269 | DPRINTF(1,("%s: attach card\n", DEVNAME(sc))); 270 | 271 | CLR(sc->sc_flags, SMF_CARD_ATTACHED); 272 | 273 | /* 274 | * Power up the card (or card stack). 275 | */ 276 | if (sdmmc_enable(sc) != 0) { 277 | printf("%s: can't enable card\n", DEVNAME(sc)); 278 | goto err; 279 | } 280 | 281 | /* 282 | * Scan for I/O functions and memory cards on the bus, 283 | * allocating a sdmmc_function structure for each. 284 | */ 285 | if (sdmmc_scan(sc) != 0) { 286 | printf("%s: no functions\n", DEVNAME(sc)); 287 | goto err; 288 | } 289 | 290 | /* 291 | * Initialize the I/O functions and memory cards. 292 | */ 293 | if (sdmmc_init(sc) != 0) { 294 | printf("%s: init failed\n", DEVNAME(sc)); 295 | goto err; 296 | } 297 | 298 | /* Attach SCSI emulation for memory cards. */ 299 | if (ISSET(sc->sc_flags, SMF_MEM_MODE)) 300 | sc->blk_attach(); 301 | 302 | /* Attach I/O function drivers. */ 303 | if (ISSET(sc->sc_flags, SMF_IO_MODE)) 304 | sdmmc_io_attach(sc); 305 | 306 | SET(sc->sc_flags, SMF_CARD_ATTACHED); 307 | return; 308 | err: 309 | sdmmc_card_detach(sc, DETACH_FORCE); 310 | } 311 | 312 | /* 313 | * Called from process context with DETACH_* flags from 314 | * when cards are gone. 315 | */ 316 | void 317 | sdmmc_card_detach(struct sdmmc_softc *sc, int flags) 318 | { 319 | struct sdmmc_function *sf, *sfnext; 320 | 321 | DPRINTF(1,("%s: detach card\n", DEVNAME(sc))); 322 | 323 | if (ISSET(sc->sc_flags, SMF_CARD_ATTACHED)) { 324 | /* Detach I/O function drivers. */ 325 | if (ISSET(sc->sc_flags, SMF_IO_MODE)) 326 | sdmmc_io_detach(sc); 327 | 328 | /* Detach the SCSI emulation for memory cards. */ 329 | if (ISSET(sc->sc_flags, SMF_MEM_MODE)) 330 | sc->blk_detach(); 331 | 332 | CLR(sc->sc_flags, SMF_CARD_ATTACHED); 333 | } 334 | 335 | /* Power down. */ 336 | sdmmc_disable(sc); 337 | 338 | /* Free all sdmmc_function structures. */ 339 | for (sf = STAILQ_FIRST(&sc->sf_head); sf != NULL; sf = sfnext) { 340 | sfnext = STAILQ_NEXT(sf, sf_list); 341 | sdmmc_function_free(sf); 342 | } 343 | STAILQ_INIT(&sc->sf_head); 344 | sc->sc_function_count = 0; 345 | sc->sc_fn0 = NULL; 346 | } 347 | 348 | int 349 | sdmmc_enable(struct sdmmc_softc *sc) 350 | { 351 | u_int32_t host_ocr; 352 | int error; 353 | 354 | /* 355 | * Calculate the equivalent of the card OCR from the host 356 | * capabilities and select the maximum supported bus voltage. 357 | */ 358 | host_ocr = rtsx_host_ocr(sc); 359 | error = rtsx_bus_power(sc, host_ocr); 360 | if (error != 0) { 361 | printf("%s: can't supply bus power\n", DEVNAME(sc)); 362 | goto err; 363 | } 364 | 365 | /* 366 | * Select the minimum clock frequency. 367 | */ 368 | error = rtsx_bus_clock(sc, 369 | SDMMC_SDCLK_400KHZ, SDMMC_TIMING_LEGACY); 370 | if (error != 0) { 371 | printf("%s: can't supply clock\n", DEVNAME(sc)); 372 | goto err; 373 | } 374 | 375 | /* XXX wait for card to power up */ 376 | sdmmc_delay(250000); 377 | 378 | /* Initialize SD I/O card function(s). */ 379 | if ((error = sdmmc_io_enable(sc)) != 0) 380 | goto err; 381 | 382 | /* Initialize SD/MMC memory card(s). */ 383 | if (ISSET(sc->sc_flags, SMF_MEM_MODE) && 384 | (error = sdmmc_mem_enable(sc)) != 0) 385 | goto err; 386 | 387 | err: 388 | if (error != 0) 389 | sdmmc_disable(sc); 390 | 391 | return error; 392 | } 393 | 394 | void 395 | sdmmc_disable(struct sdmmc_softc *sc) 396 | { 397 | /* XXX complete commands if card is still present. */ 398 | 399 | /* Make sure no card is still selected. */ 400 | (void)sdmmc_select_card(sc, NULL); 401 | 402 | /* Turn off bus power and clock. */ 403 | (void)rtsx_bus_clock(sc, 404 | SDMMC_SDCLK_OFF, SDMMC_TIMING_LEGACY); 405 | (void)rtsx_bus_power(sc, 0); 406 | } 407 | 408 | /* 409 | * Set the lowest bus voltage supported by the card and the host. 410 | */ 411 | int 412 | sdmmc_set_bus_power(struct sdmmc_softc *sc, u_int32_t host_ocr, 413 | u_int32_t card_ocr) 414 | { 415 | u_int32_t bit; 416 | 417 | /* Mask off unsupported voltage levels and select the lowest. */ 418 | DPRINTF(1,("%s: host_ocr=%x ", DEVNAME(sc), host_ocr)); 419 | host_ocr &= card_ocr; 420 | for (bit = 4; bit < 23; bit++) { 421 | if (ISSET(host_ocr, 1<sc = sc; 443 | sf->number = -1; 444 | sf->cis.manufacturer = SDMMC_VENDOR_INVALID; 445 | sf->cis.product = SDMMC_PRODUCT_INVALID; 446 | sf->cis.function = SDMMC_FUNCTION_INVALID; 447 | return sf; 448 | } 449 | 450 | void 451 | sdmmc_function_free(struct sdmmc_function *sf) 452 | { 453 | // free(sf, M_DEVBUF, 0); 454 | delete [] (uint8_t *) sf; 455 | } 456 | 457 | /* 458 | * Scan for I/O functions and memory cards on the bus, allocating a 459 | * sdmmc_function structure for each. 460 | */ 461 | int 462 | sdmmc_scan(struct sdmmc_softc *sc) 463 | { 464 | 465 | /* Scan for I/O functions. */ 466 | if (ISSET(sc->sc_flags, SMF_IO_MODE)) 467 | sdmmc_io_scan(sc); 468 | 469 | /* Scan for memory cards on the bus. */ 470 | if (ISSET(sc->sc_flags, SMF_MEM_MODE)) 471 | sdmmc_mem_scan(sc); 472 | 473 | /* There should be at least one function now. */ 474 | if (STAILQ_EMPTY(&sc->sf_head)) { 475 | printf("%s: can't identify card\n", DEVNAME(sc)); 476 | return 1; 477 | } 478 | return 0; 479 | } 480 | 481 | /* 482 | * Initialize all the distinguished functions of the card, be it I/O 483 | * or memory functions. 484 | */ 485 | int 486 | sdmmc_init(struct sdmmc_softc *sc) 487 | { 488 | struct sdmmc_function *sf; 489 | 490 | /* Initialize all identified card functions. */ 491 | STAILQ_FOREACH(sf, &sc->sf_head, sf_list) { 492 | if (ISSET(sc->sc_flags, SMF_IO_MODE) && 493 | sdmmc_io_init(sc, sf) != 0) 494 | printf("%s: i/o init failed\n", DEVNAME(sc)); 495 | 496 | if (ISSET(sc->sc_flags, SMF_MEM_MODE) && 497 | sdmmc_mem_init(sc, sf) != 0) 498 | printf("%s: mem init failed\n", DEVNAME(sc)); 499 | } 500 | 501 | /* Any good functions left after initialization? */ 502 | STAILQ_FOREACH(sf, &sc->sf_head, sf_list) { 503 | if (!ISSET(sf->flags, SFF_ERROR)) 504 | return 0; 505 | } 506 | /* No, we should probably power down the card. */ 507 | return 1; 508 | } 509 | 510 | void 511 | sdmmc_delay(u_int usecs) 512 | { 513 | IODelay(usecs); 514 | } 515 | 516 | int 517 | sdmmc_app_command(struct sdmmc_softc *sc, struct sdmmc_command *cmd) 518 | { 519 | struct sdmmc_command acmd; 520 | int error; 521 | 522 | bzero(&acmd, sizeof acmd); 523 | acmd.c_opcode = MMC_APP_CMD; 524 | acmd.c_arg = 0; 525 | if (sc->sc_card != NULL) { 526 | acmd.c_arg = sc->sc_card->rca << 16; 527 | } 528 | acmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 529 | 530 | error = sdmmc_mmc_command(sc, &acmd); 531 | if (error != 0) { 532 | return error; 533 | } 534 | 535 | if (!ISSET(MMC_R1(acmd.c_resp), MMC_R1_APP_CMD)) { 536 | /* Card does not support application commands. */ 537 | return ENODEV; 538 | } 539 | 540 | error = sdmmc_mmc_command(sc, cmd); 541 | return error; 542 | } 543 | 544 | /* 545 | * Execute MMC command and data transfers. All interactions with the 546 | * host controller to complete the command happen in the context of 547 | * the current process. 548 | */ 549 | int 550 | sdmmc_mmc_command(struct sdmmc_softc *sc, struct sdmmc_command *cmd) 551 | { 552 | int error; 553 | 554 | rtsx_exec_command(sc, cmd); 555 | 556 | #ifdef SDMMC_DEBUG 557 | sdmmc_dump_command(sc, cmd); 558 | #endif 559 | 560 | error = cmd->c_error; 561 | wakeup(cmd); 562 | 563 | return error; 564 | } 565 | 566 | /* 567 | * Send the "GO IDLE STATE" command. 568 | */ 569 | void 570 | sdmmc_go_idle_state(struct sdmmc_softc *sc) 571 | { 572 | struct sdmmc_command cmd; 573 | 574 | bzero(&cmd, sizeof cmd); 575 | cmd.c_opcode = MMC_GO_IDLE_STATE; 576 | cmd.c_flags = SCF_CMD_BC | SCF_RSP_R0; 577 | 578 | (void)sdmmc_mmc_command(sc, &cmd); 579 | } 580 | 581 | /* 582 | * Send the "SEND_IF_COND" command, to check operating condition 583 | */ 584 | int 585 | sdmmc_send_if_cond(struct sdmmc_softc *sc, uint32_t card_ocr) 586 | { 587 | struct sdmmc_command cmd; 588 | uint8_t pat = 0x23; /* any pattern will do here */ 589 | uint8_t res; 590 | 591 | bzero(&cmd, sizeof cmd); 592 | 593 | cmd.c_opcode = SD_SEND_IF_COND; 594 | cmd.c_arg = ((card_ocr & SD_OCR_VOL_MASK) != 0) << 8 | pat; 595 | cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R7; 596 | 597 | if (sdmmc_mmc_command(sc, &cmd) != 0) 598 | return 1; 599 | 600 | res = cmd.c_resp[0]; 601 | if (res != pat) 602 | return 1; 603 | else 604 | return 0; 605 | } 606 | 607 | /* 608 | * Retrieve (SD) or set (MMC) the relative card address (RCA). 609 | */ 610 | int 611 | sdmmc_set_relative_addr(struct sdmmc_softc *sc, 612 | struct sdmmc_function *sf) 613 | { 614 | struct sdmmc_command cmd; 615 | 616 | bzero(&cmd, sizeof cmd); 617 | 618 | if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 619 | cmd.c_opcode = SD_SEND_RELATIVE_ADDR; 620 | cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R6; 621 | } else { 622 | cmd.c_opcode = MMC_SET_RELATIVE_ADDR; 623 | cmd.c_arg = MMC_ARG_RCA(sf->rca); 624 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 625 | } 626 | 627 | if (sdmmc_mmc_command(sc, &cmd) != 0) 628 | return 1; 629 | 630 | if (ISSET(sc->sc_flags, SMF_SD_MODE)) 631 | sf->rca = SD_R6_RCA(cmd.c_resp); 632 | return 0; 633 | } 634 | 635 | int 636 | sdmmc_select_card(struct sdmmc_softc *sc, struct sdmmc_function *sf) 637 | { 638 | struct sdmmc_command cmd; 639 | int error; 640 | 641 | if (sc->sc_card == sf || (sf && sc->sc_card && 642 | sc->sc_card->rca == sf->rca)) { 643 | sc->sc_card = sf; 644 | return 0; 645 | } 646 | 647 | bzero(&cmd, sizeof cmd); 648 | cmd.c_opcode = MMC_SELECT_CARD; 649 | cmd.c_arg = sf == NULL ? 0 : MMC_ARG_RCA(sf->rca); 650 | cmd.c_flags = SCF_CMD_AC | (sf == NULL ? SCF_RSP_R0 : SCF_RSP_R1); 651 | error = sdmmc_mmc_command(sc, &cmd); 652 | if (error == 0 || sf == NULL) 653 | sc->sc_card = sf; 654 | return error; 655 | } 656 | 657 | #ifdef SDMMC_IOCTL 658 | int 659 | sdmmc_ioctl(struct device *self, u_long request, caddr_t addr) 660 | { 661 | struct sdmmc_softc *sc = (struct sdmmc_softc *)self; 662 | struct sdmmc_command *ucmd; 663 | struct sdmmc_command cmd; 664 | void *data; 665 | int error = 0; 666 | 667 | switch (request) { 668 | #ifdef SDMMC_DEBUG 669 | case SDIOCSETDEBUG: 670 | sdmmcdebug = (((struct bio_sdmmc_debug *)addr)->debug) & 0xff; 671 | sdhcdebug = (((struct bio_sdmmc_debug *)addr)->debug >> 8) & 0xff; 672 | break; 673 | #endif 674 | 675 | case SDIOCEXECMMC: 676 | case SDIOCEXECAPP: 677 | ucmd = &((struct bio_sdmmc_command *)addr)->cmd; 678 | 679 | /* Refuse to transfer more than 512K per command. */ 680 | if (ucmd->c_datalen > 524288) 681 | return ENOMEM; 682 | 683 | /* Verify that the data buffer is safe to copy. */ 684 | if ((ucmd->c_datalen > 0 && ucmd->c_data == NULL) || 685 | (ucmd->c_datalen < 1 && ucmd->c_data != NULL) || 686 | ucmd->c_datalen < 0) 687 | return EINVAL; 688 | 689 | bzero(&cmd, sizeof cmd); 690 | cmd.c_opcode = ucmd->c_opcode; 691 | cmd.c_arg = ucmd->c_arg; 692 | cmd.c_flags = ucmd->c_flags; 693 | cmd.c_blklen = ucmd->c_blklen; 694 | 695 | if (ucmd->c_data) { 696 | data = malloc(ucmd->c_datalen, M_TEMP, 697 | M_WAITOK | M_CANFAIL); 698 | if (data == NULL) 699 | return ENOMEM; 700 | error = copyin(ucmd->c_data, data, ucmd->c_datalen); 701 | if (error != 0) 702 | goto exec_done; 703 | 704 | cmd.c_data = data; 705 | cmd.c_datalen = ucmd->c_datalen; 706 | } 707 | 708 | rw_enter_write(&sc->sc_lock); 709 | if (request == SDIOCEXECMMC) 710 | error = sdmmc_mmc_command(sc, &cmd); 711 | else 712 | error = sdmmc_app_command(sc, &cmd); 713 | rw_exit(&sc->sc_lock); 714 | if (error && !cmd.c_error) 715 | cmd.c_error = error; 716 | 717 | bcopy(&cmd.c_resp, ucmd->c_resp, sizeof cmd.c_resp); 718 | ucmd->c_flags = cmd.c_flags; 719 | ucmd->c_error = cmd.c_error; 720 | 721 | if (ucmd->c_data) 722 | error = copyout(data, ucmd->c_data, ucmd->c_datalen); 723 | else 724 | error = 0; 725 | 726 | exec_done: 727 | if (ucmd->c_data) 728 | free(data, M_TEMP, 0); 729 | break; 730 | 731 | default: 732 | return ENOTTY; 733 | } 734 | return error; 735 | } 736 | #endif 737 | 738 | #ifdef SDMMC_DEBUG 739 | void 740 | sdmmc_dump_command(struct sdmmc_softc *sc, struct sdmmc_command *cmd) 741 | { 742 | int i; 743 | 744 | DPRINTF(1,("%s: cmd %u arg=%#x data=%p dlen=%d flags=%#x " 745 | "proc=\"%s\" (error %d)\n", DEVNAME(sc), cmd->c_opcode, 746 | cmd->c_arg, cmd->c_data, cmd->c_datalen, cmd->c_flags, 747 | "", cmd->c_error)); 748 | 749 | if (cmd->c_error || sdmmcdebug < 1) 750 | return; 751 | 752 | printf("%s: resp=", DEVNAME(sc)); 753 | if (ISSET(cmd->c_flags, SCF_RSP_136)) 754 | for (i = 0; i < sizeof cmd->c_resp; i++) 755 | printf("%02x ", ((u_char *)cmd->c_resp)[i]); 756 | else if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 757 | for (i = 0; i < 4; i++) 758 | printf("%02x ", ((u_char *)cmd->c_resp)[i]); 759 | printf("\n"); 760 | } 761 | #endif 762 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmc_cis.cpp: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmc_cis.c,v 1.7 2016/04/23 14:15:59 kettenis Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | /* Routines to decode the Card Information Structure of SD I/O cards */ 20 | 21 | #include 22 | #include 23 | 24 | #include "sdmmc_ioreg.h" 25 | #include "sdmmcdevs.h" 26 | #include "sdmmcvar.h" 27 | 28 | #include "Sinetek_rtsx.hpp" 29 | 30 | u_int32_t sdmmc_cisptr(struct sdmmc_function *); 31 | 32 | #ifdef SDMMC_DEBUG 33 | #define DPRINTF(s) printf s 34 | #else 35 | #define DPRINTF(s) /**/ 36 | #endif 37 | 38 | u_int32_t 39 | sdmmc_cisptr(struct sdmmc_function *sf) 40 | { 41 | struct sdmmc_function *sf0 = sf->sc->sc_fn0; 42 | u_int32_t cisptr = 0; 43 | int reg; 44 | 45 | reg = SD_IO_CCCR_CISPTR + (sf->number * SD_IO_CCCR_SIZE); 46 | cisptr |= sdmmc_io_read_1(sf0, reg + 0) << 0; 47 | cisptr |= sdmmc_io_read_1(sf0, reg + 1) << 8; 48 | cisptr |= sdmmc_io_read_1(sf0, reg + 2) << 16; 49 | 50 | return cisptr; 51 | } 52 | 53 | int 54 | sdmmc_read_cis(struct sdmmc_function *sf, struct sdmmc_cis *cis) 55 | { 56 | struct sdmmc_function *sf0 = sf->sc->sc_fn0; 57 | int reg; 58 | u_int8_t tplcode; 59 | u_int8_t tpllen; 60 | 61 | reg = (int)sdmmc_cisptr(sf); 62 | if (reg < SD_IO_CIS_START || 63 | reg >= (SD_IO_CIS_START+SD_IO_CIS_SIZE-16)) { 64 | printf("%s: bad CIS ptr %#x\n", DEVNAME(sf->sc), reg); 65 | return 1; 66 | } 67 | 68 | for (;;) { 69 | tplcode = sdmmc_io_read_1(sf0, reg++); 70 | if (tplcode == SD_IO_CISTPL_END) 71 | break; 72 | if (tplcode == SD_IO_CISTPL_NULL) 73 | continue; 74 | 75 | tpllen = sdmmc_io_read_1(sf0, reg++); 76 | if (tpllen == 0) { 77 | printf("%s: CIS parse error at %d, " 78 | "tuple code %#x, length %d\n", 79 | DEVNAME(sf->sc), reg, tplcode, tpllen); 80 | break; 81 | } 82 | 83 | switch (tplcode) { 84 | case SD_IO_CISTPL_FUNCID: 85 | if (tpllen < 2) { 86 | printf("%s: bad CISTPL_FUNCID length\n", 87 | DEVNAME(sf->sc)); 88 | reg += tpllen; 89 | break; 90 | } 91 | cis->function = sdmmc_io_read_1(sf0, reg); 92 | reg += tpllen; 93 | break; 94 | case SD_IO_CISTPL_MANFID: 95 | if (tpllen < 4) { 96 | printf("%s: bad CISTPL_MANFID length\n", 97 | DEVNAME(sf->sc)); 98 | reg += tpllen; 99 | break; 100 | } 101 | cis->manufacturer = sdmmc_io_read_1(sf0, reg++); 102 | cis->manufacturer |= sdmmc_io_read_1(sf0, reg++) << 8; 103 | cis->product = sdmmc_io_read_1(sf0, reg++); 104 | cis->product |= sdmmc_io_read_1(sf0, reg++) << 8; 105 | break; 106 | case SD_IO_CISTPL_VERS_1: 107 | if (tpllen < 2) { 108 | printf("%s: CISTPL_VERS_1 too short\n", 109 | DEVNAME(sf->sc)); 110 | reg += tpllen; 111 | break; 112 | } 113 | { 114 | int start, i, ch, count; 115 | 116 | cis->cis1_major = sdmmc_io_read_1(sf0, reg++); 117 | cis->cis1_minor = sdmmc_io_read_1(sf0, reg++); 118 | 119 | for (count = 0, start = 0, i = 0; 120 | (count < 4) && ((i + 4) < 256); i++) { 121 | ch = sdmmc_io_read_1(sf0, reg + i); 122 | if (ch == 0xff) 123 | break; 124 | cis->cis1_info_buf[i] = ch; 125 | if (ch == 0) { 126 | cis->cis1_info[count] = 127 | cis->cis1_info_buf + start; 128 | start = i + 1; 129 | count++; 130 | } 131 | } 132 | 133 | reg += tpllen - 2; 134 | } 135 | break; 136 | default: 137 | DPRINTF(("%s: unknown tuple code %#x, length %d\n", 138 | DEVNAME(sf->sc), tplcode, tpllen)); 139 | reg += tpllen; 140 | break; 141 | } 142 | } 143 | 144 | return 0; 145 | } 146 | 147 | void 148 | sdmmc_print_cis(struct sdmmc_function *sf) 149 | { 150 | struct sdmmc_cis *cis = &sf->cis; 151 | int i; 152 | 153 | printf("%s: CIS version %d.%d\n", DEVNAME(sf->sc), 154 | cis->cis1_major, cis->cis1_minor); 155 | 156 | printf("%s: CIS info: ", DEVNAME(sf->sc)); 157 | for (i = 0; i < 4; i++) { 158 | if (cis->cis1_info[i] == NULL) 159 | break; 160 | if (i) 161 | printf(", "); 162 | printf("%s", cis->cis1_info[i]); 163 | } 164 | printf("\n"); 165 | 166 | printf("%s: Manufacturer code 0x%x, product 0x%x\n", 167 | DEVNAME(sf->sc), cis->manufacturer, cis->product); 168 | 169 | printf("%s: function %d: ", DEVNAME(sf->sc), sf->number); 170 | switch (sf->cis.function) { 171 | case TPLFID_FUNCTION_SDIO: 172 | printf("SDIO"); 173 | break; 174 | default: 175 | printf("unknown (%d)", sf->cis.function); 176 | break; 177 | } 178 | printf("\n"); 179 | } 180 | 181 | void 182 | sdmmc_check_cis_quirks(struct sdmmc_function *sf) 183 | { 184 | if (sf->cis.manufacturer == SDMMC_VENDOR_SPECTEC && 185 | sf->cis.product == SDMMC_PRODUCT_SPECTEC_SDW820) { 186 | /* This card lacks the VERS_1 tuple. */ 187 | sf->cis.cis1_major = 0x01; 188 | sf->cis.cis1_minor = 0x00; 189 | sf->cis.cis1_info[0] = "Spectec"; 190 | sf->cis.cis1_info[1] = "SDIO WLAN Card"; 191 | sf->cis.cis1_info[2] = "SDW-820"; 192 | sf->cis.cis1_info[3] = ""; 193 | } 194 | } 195 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmc_io.cpp: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmc_io.c,v 1.27 2016/09/11 10:22:16 mglocker Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | /* Routines for SD I/O cards. */ 20 | 21 | #include 22 | #include 23 | #include 24 | #include 25 | 26 | #include "sdmmc_ioreg.h" 27 | #include "sdmmcchip.h" 28 | #include "sdmmcvar.h" 29 | 30 | #include "Sinetek_rtsx.hpp" 31 | 32 | struct sdmmc_intr_handler { 33 | struct sdmmc_softc *ih_softc; 34 | const char *ih_name; 35 | int (*ih_fun)(void *); 36 | void *ih_arg; 37 | TAILQ_ENTRY(sdmmc_intr_handler) entry; 38 | }; 39 | 40 | int sdmmc_submatch(struct device *, void *, void *); 41 | int sdmmc_print(void *, const char *); 42 | int sdmmc_io_rw_direct(struct sdmmc_softc *, struct sdmmc_function *, 43 | int, u_char *, int); 44 | int sdmmc_io_rw_extended(struct sdmmc_softc *, struct sdmmc_function *, 45 | int, u_char *, int, int); 46 | int sdmmc_io_xchg(struct sdmmc_softc *, struct sdmmc_function *, 47 | int, u_char *); 48 | void sdmmc_io_reset(struct sdmmc_softc *); 49 | int sdmmc_io_send_op_cond(struct sdmmc_softc *, u_int32_t, u_int32_t *); 50 | 51 | #ifdef SDMMC_DEBUG 52 | #define DPRINTF(s) printf s 53 | #else 54 | #define DPRINTF(s) /**/ 55 | #endif 56 | 57 | #ifdef SDMMC_DEBUG 58 | int sdmmc_verbose = 1; 59 | #else 60 | int sdmmc_verbose = 0; 61 | #endif 62 | 63 | 64 | 65 | /* 66 | * Initialize SD I/O card functions (before memory cards). The host 67 | * system and controller must support card interrupts in order to use 68 | * I/O functions. 69 | */ 70 | int 71 | sdmmc_io_enable(struct sdmmc_softc *sc) 72 | { 73 | u_int32_t host_ocr; 74 | u_int32_t card_ocr; 75 | 76 | /* Set host mode to SD "combo" card. */ 77 | SET(sc->sc_flags, SMF_SD_MODE|SMF_IO_MODE|SMF_MEM_MODE); 78 | 79 | /* Reset I/O functions. */ 80 | sdmmc_io_reset(sc); 81 | 82 | /* 83 | * Read the I/O OCR value, determine the number of I/O 84 | * functions and whether memory is also present (a "combo 85 | * card") by issuing CMD5. SD memory-only and MMC cards 86 | * do not respond to CMD5. 87 | */ 88 | if (sdmmc_io_send_op_cond(sc, 0, &card_ocr) != 0) { 89 | /* No SDIO card; switch to SD memory-only mode. */ 90 | CLR(sc->sc_flags, SMF_IO_MODE); 91 | return 0; 92 | } 93 | 94 | /* Parse the additional bits in the I/O OCR value. */ 95 | if (!ISSET(card_ocr, SD_IO_OCR_MEM_PRESENT)) { 96 | /* SDIO card without memory (not a "combo card"). */ 97 | DPRINTF(("%s: no memory present\n", DEVNAME(sc))); 98 | CLR(sc->sc_flags, SMF_MEM_MODE); 99 | } 100 | sc->sc_function_count = SD_IO_OCR_NUM_FUNCTIONS(card_ocr); 101 | if (sc->sc_function_count == 0) { 102 | /* Useless SDIO card without any I/O functions. */ 103 | DPRINTF(("%s: no I/O functions\n", DEVNAME(sc))); 104 | CLR(sc->sc_flags, SMF_IO_MODE); 105 | return 0; 106 | } 107 | card_ocr &= SD_IO_OCR_MASK; 108 | 109 | /* Set the lowest voltage supported by the card and host. */ 110 | host_ocr = rtsx_host_ocr(sc); 111 | if (sdmmc_set_bus_power(sc, host_ocr, card_ocr) != 0) { 112 | printf("%s: can't supply voltage requested by card\n", 113 | DEVNAME(sc)); 114 | return 1; 115 | } 116 | 117 | /* Send the new OCR value until all cards are ready. */ 118 | if (sdmmc_io_send_op_cond(sc, host_ocr, NULL) != 0) { 119 | printf("%s: can't send I/O OCR\n", DEVNAME(sc)); 120 | return 1; 121 | } 122 | return 0; 123 | } 124 | 125 | /* 126 | * Allocate sdmmc_function structures for SD card I/O function 127 | * (including function 0). 128 | */ 129 | void 130 | sdmmc_io_scan(struct sdmmc_softc *sc) 131 | { 132 | struct sdmmc_function *sf0, *sf; 133 | int i; 134 | 135 | sf0 = sdmmc_function_alloc(sc); 136 | sf0->number = 0; 137 | if (sdmmc_set_relative_addr(sc, sf0) != 0) { 138 | printf("%s: can't set I/O RCA\n", DEVNAME(sc)); 139 | SET(sf0->flags, SFF_ERROR); 140 | return; 141 | } 142 | sc->sc_fn0 = sf0; 143 | STAILQ_INSERT_TAIL(&sc->sf_head, sf0, sf_list); 144 | 145 | /* Verify that the RCA has been set by selecting the card. */ 146 | if (sdmmc_select_card(sc, sf0) != 0) { 147 | printf("%s: can't select I/O RCA %d\n", DEVNAME(sc), 148 | sf0->rca); 149 | SET(sf0->flags, SFF_ERROR); 150 | return; 151 | } 152 | 153 | for (i = 1; i <= sc->sc_function_count; i++) { 154 | sf = sdmmc_function_alloc(sc); 155 | sf->number = i; 156 | sf->rca = sf0->rca; 157 | 158 | STAILQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 159 | } 160 | } 161 | 162 | /* 163 | * Initialize SDIO card functions. 164 | */ 165 | int 166 | sdmmc_io_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 167 | { 168 | 169 | if (sdmmc_read_cis(sf, &sf->cis) != 0) { 170 | printf("%s: can't read CIS\n", DEVNAME(sc)); 171 | SET(sf->flags, SFF_ERROR); 172 | return 1; 173 | } 174 | 175 | sdmmc_check_cis_quirks(sf); 176 | 177 | if (sdmmc_verbose) 178 | sdmmc_print_cis(sf); 179 | 180 | if (sf->number == 0) { 181 | /* XXX respect host and card capabilities */ 182 | (void)rtsx_bus_clock(sc, 183 | 25000, SDMMC_TIMING_LEGACY); 184 | } 185 | 186 | return 0; 187 | } 188 | 189 | /* 190 | * Indicate whether the function is ready to operate. 191 | */ 192 | int 193 | sdmmc_io_function_ready(struct sdmmc_function *sf) 194 | { 195 | struct sdmmc_softc *sc = sf->sc; 196 | struct sdmmc_function *sf0 = sc->sc_fn0; 197 | u_int8_t rv; 198 | 199 | if (sf->number == 0) 200 | return 1; /* FN0 is always ready */ 201 | 202 | rv = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_READY); 203 | 204 | return (rv & (1 << sf->number)) != 0; 205 | } 206 | 207 | /* 208 | * Enable the I/O function. Return zero if the function was 209 | * enabled successfully. 210 | */ 211 | int 212 | sdmmc_io_function_enable(struct sdmmc_function *sf) 213 | { 214 | struct sdmmc_softc *sc = sf->sc; 215 | struct sdmmc_function *sf0 = sc->sc_fn0; 216 | u_int8_t rv; 217 | int retry = 5; 218 | 219 | if (sf->number == 0) 220 | return 0; /* FN0 is always enabled */ 221 | 222 | // XXX 223 | return ENOTSUP; 224 | } 225 | 226 | /* 227 | * Disable the I/O function. Return zero if the function was 228 | * disabled successfully. 229 | */ 230 | void 231 | sdmmc_io_function_disable(struct sdmmc_function *sf) 232 | { 233 | struct sdmmc_softc *sc = sf->sc; 234 | struct sdmmc_function *sf0 = sc->sc_fn0; 235 | u_int8_t rv; 236 | 237 | if (sf->number == 0) 238 | return; /* FN0 is always enabled */ 239 | 240 | rv = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_ENABLE); 241 | rv &= ~(1<number); 242 | sdmmc_io_write_1(sf0, SD_IO_CCCR_FN_ENABLE, rv); 243 | } 244 | 245 | void 246 | sdmmc_io_attach(struct sdmmc_softc *sc) 247 | { 248 | // XXX 249 | return; 250 | } 251 | 252 | int 253 | sdmmc_submatch(struct device *parent, void *match, void *aux) 254 | { 255 | // XXX 256 | return ENOTSUP; 257 | } 258 | 259 | int 260 | sdmmc_print(void *aux, const char *pnp) 261 | { 262 | // XXX 263 | return ENOTSUP; 264 | } 265 | 266 | void 267 | sdmmc_io_detach(struct sdmmc_softc *sc) 268 | { 269 | // XXX 270 | return; 271 | } 272 | 273 | int 274 | sdmmc_io_rw_direct(struct sdmmc_softc *sc, struct sdmmc_function *sf, 275 | int reg, u_char *datap, int arg) 276 | { 277 | struct sdmmc_command cmd; 278 | int error; 279 | 280 | /* Make sure the card is selected. */ 281 | if ((error = sdmmc_select_card(sc, sf)) != 0) { 282 | return error; 283 | } 284 | 285 | arg |= ((sf == NULL ? 0 : sf->number) & SD_ARG_CMD52_FUNC_MASK) << 286 | SD_ARG_CMD52_FUNC_SHIFT; 287 | arg |= (reg & SD_ARG_CMD52_REG_MASK) << 288 | SD_ARG_CMD52_REG_SHIFT; 289 | arg |= (*datap & SD_ARG_CMD52_DATA_MASK) << 290 | SD_ARG_CMD52_DATA_SHIFT; 291 | 292 | bzero(&cmd, sizeof cmd); 293 | cmd.c_opcode = SD_IO_RW_DIRECT; 294 | cmd.c_arg = arg; 295 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R5; 296 | 297 | error = sdmmc_mmc_command(sc, &cmd); 298 | *datap = SD_R5_DATA(cmd.c_resp); 299 | 300 | return error; 301 | } 302 | 303 | /* 304 | * Useful values of `arg' to pass in are either SD_ARG_CMD53_READ or 305 | * SD_ARG_CMD53_WRITE. SD_ARG_CMD53_INCREMENT may be ORed into `arg' 306 | * to access successive register locations instead of accessing the 307 | * same register many times. 308 | */ 309 | int 310 | sdmmc_io_rw_extended(struct sdmmc_softc *sc, struct sdmmc_function *sf, 311 | int reg, u_char *datap, int datalen, int arg) 312 | { 313 | struct sdmmc_command cmd; 314 | int error; 315 | 316 | #if 0 317 | /* Make sure the card is selected. */ 318 | if ((error = sdmmc_select_card(sc, sf)) != 0) { 319 | rw_exit(&sc->sc_lock); 320 | return error; 321 | } 322 | #endif 323 | 324 | arg |= ((sf == NULL ? 0 : sf->number) & SD_ARG_CMD53_FUNC_MASK) << 325 | SD_ARG_CMD53_FUNC_SHIFT; 326 | arg |= (reg & SD_ARG_CMD53_REG_MASK) << 327 | SD_ARG_CMD53_REG_SHIFT; 328 | arg |= (datalen & SD_ARG_CMD53_LENGTH_MASK) << 329 | SD_ARG_CMD53_LENGTH_SHIFT; 330 | 331 | bzero(&cmd, sizeof cmd); 332 | cmd.c_opcode = SD_IO_RW_EXTENDED; 333 | cmd.c_arg = arg; 334 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R5; 335 | cmd.c_data = datap; 336 | cmd.c_datalen = datalen; 337 | cmd.c_blklen = MIN(datalen, rtsx_host_maxblklen(sc)); 338 | 339 | if (!ISSET(arg, SD_ARG_CMD53_WRITE)) 340 | cmd.c_flags |= SCF_CMD_READ; 341 | 342 | error = sdmmc_mmc_command(sc, &cmd); 343 | 344 | return error; 345 | } 346 | 347 | u_int8_t 348 | sdmmc_io_read_1(struct sdmmc_function *sf, int reg) 349 | { 350 | u_int8_t data = 0; 351 | 352 | (void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data, 353 | SD_ARG_CMD52_READ); 354 | return data; 355 | } 356 | 357 | void 358 | sdmmc_io_write_1(struct sdmmc_function *sf, int reg, u_int8_t data) 359 | { 360 | (void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data, 361 | SD_ARG_CMD52_WRITE); 362 | } 363 | 364 | u_int16_t 365 | sdmmc_io_read_2(struct sdmmc_function *sf, int reg) 366 | { 367 | u_int16_t data = 0; 368 | 369 | (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 2, 370 | SD_ARG_CMD53_READ | SD_ARG_CMD53_INCREMENT); 371 | return data; 372 | } 373 | 374 | void 375 | sdmmc_io_write_2(struct sdmmc_function *sf, int reg, u_int16_t data) 376 | { 377 | 378 | (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 2, 379 | SD_ARG_CMD53_WRITE | SD_ARG_CMD53_INCREMENT); 380 | } 381 | 382 | u_int32_t 383 | sdmmc_io_read_4(struct sdmmc_function *sf, int reg) 384 | { 385 | u_int32_t data = 0; 386 | 387 | 388 | (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 4, 389 | SD_ARG_CMD53_READ | SD_ARG_CMD53_INCREMENT); 390 | return data; 391 | } 392 | 393 | void 394 | sdmmc_io_write_4(struct sdmmc_function *sf, int reg, u_int32_t data) 395 | { 396 | 397 | (void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 4, 398 | SD_ARG_CMD53_WRITE | SD_ARG_CMD53_INCREMENT); 399 | } 400 | 401 | int 402 | sdmmc_io_read_multi_1(struct sdmmc_function *sf, int reg, u_char *data, 403 | int datalen) 404 | { 405 | int error; 406 | 407 | while (datalen > SD_ARG_CMD53_LENGTH_MAX) { 408 | error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, 409 | SD_ARG_CMD53_LENGTH_MAX, SD_ARG_CMD53_READ); 410 | if (error) 411 | return error; 412 | data += SD_ARG_CMD53_LENGTH_MAX; 413 | datalen -= SD_ARG_CMD53_LENGTH_MAX; 414 | } 415 | 416 | return sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen, 417 | SD_ARG_CMD53_READ); 418 | } 419 | 420 | int 421 | sdmmc_io_write_multi_1(struct sdmmc_function *sf, int reg, u_char *data, 422 | int datalen) 423 | { 424 | int error; 425 | 426 | while (datalen > SD_ARG_CMD53_LENGTH_MAX) { 427 | error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, 428 | SD_ARG_CMD53_LENGTH_MAX, SD_ARG_CMD53_WRITE); 429 | if (error) 430 | return error; 431 | data += SD_ARG_CMD53_LENGTH_MAX; 432 | datalen -= SD_ARG_CMD53_LENGTH_MAX; 433 | } 434 | 435 | return sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen, 436 | SD_ARG_CMD53_WRITE); 437 | } 438 | 439 | int 440 | sdmmc_io_xchg(struct sdmmc_softc *sc, struct sdmmc_function *sf, 441 | int reg, u_char *datap) 442 | { 443 | 444 | return sdmmc_io_rw_direct(sc, sf, reg, datap, 445 | SD_ARG_CMD52_WRITE|SD_ARG_CMD52_EXCHANGE); 446 | } 447 | 448 | /* 449 | * Reset the I/O functions of the card. 450 | */ 451 | void 452 | sdmmc_io_reset(struct sdmmc_softc *sc) 453 | { 454 | u_int8_t data = CCCR_CTL_RES; 455 | 456 | if (sdmmc_io_rw_direct(sc, NULL, SD_IO_CCCR_CTL, (u_char *)&data, 457 | SD_ARG_CMD52_WRITE) == 0) 458 | sdmmc_delay(100000); 459 | } 460 | 461 | /* 462 | * Get or set the card's I/O OCR value (SDIO). 463 | */ 464 | int 465 | sdmmc_io_send_op_cond(struct sdmmc_softc *sc, u_int32_t ocr, u_int32_t *ocrp) 466 | { 467 | struct sdmmc_command cmd; 468 | int error; 469 | int i; 470 | 471 | /* 472 | * If we change the OCR value, retry the command until the OCR 473 | * we receive in response has the "CARD BUSY" bit set, meaning 474 | * that all cards are ready for identification. 475 | */ 476 | for (i = 0; i < 100; i++) { 477 | bzero(&cmd, sizeof cmd); 478 | cmd.c_opcode = SD_IO_SEND_OP_COND; 479 | cmd.c_arg = ocr; 480 | cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R4; 481 | 482 | error = sdmmc_mmc_command(sc, &cmd); 483 | if (error != 0) 484 | break; 485 | if (ISSET(MMC_R4(cmd.c_resp), SD_IO_OCR_MEM_READY) || 486 | ocr == 0) 487 | break; 488 | error = ETIMEDOUT; 489 | sdmmc_delay(10000); 490 | } 491 | if (error == 0 && ocrp != NULL) 492 | *ocrp = MMC_R4(cmd.c_resp); 493 | 494 | return error; 495 | } 496 | 497 | /* 498 | * Card interrupt handling 499 | */ 500 | 501 | void 502 | sdmmc_intr_enable(struct sdmmc_function *sf) 503 | { 504 | struct sdmmc_softc *sc = sf->sc; 505 | struct sdmmc_function *sf0 = sc->sc_fn0; 506 | u_int8_t imask; 507 | 508 | imask = sdmmc_io_read_1(sf0, SD_IO_CCCR_INT_ENABLE); 509 | imask |= 1 << sf->number; 510 | sdmmc_io_write_1(sf0, SD_IO_CCCR_INT_ENABLE, imask); 511 | } 512 | 513 | void 514 | sdmmc_intr_disable(struct sdmmc_function *sf) 515 | { 516 | struct sdmmc_softc *sc = sf->sc; 517 | struct sdmmc_function *sf0 = sc->sc_fn0; 518 | u_int8_t imask; 519 | 520 | imask = sdmmc_io_read_1(sf0, SD_IO_CCCR_INT_ENABLE); 521 | imask &= ~(1 << sf->number); 522 | sdmmc_io_write_1(sf0, SD_IO_CCCR_INT_ENABLE, imask); 523 | } 524 | 525 | /* 526 | * Establish a handler for the SDIO card interrupt. Because the 527 | * interrupt may be shared with different SDIO functions, multiple 528 | * handlers can be established. 529 | */ 530 | void * 531 | sdmmc_intr_establish(struct device *sdmmc, int (*fun)(void *), 532 | void *arg, const char *name) 533 | { 534 | // XXX 535 | return NULL; 536 | } 537 | 538 | /* 539 | * Disestablish the given handler. 540 | */ 541 | void 542 | sdmmc_intr_disestablish(void *cookie) 543 | { 544 | // XXX 545 | return; 546 | } 547 | 548 | /* 549 | * Call established SDIO card interrupt handlers. The host controller 550 | * must call this function from its own interrupt handler to handle an 551 | * SDIO interrupt from the card. 552 | */ 553 | void 554 | sdmmc_card_intr(struct device *sdmmc) 555 | { 556 | // XXX 557 | return ; 558 | } 559 | 560 | void 561 | sdmmc_intr_task(void *arg) 562 | { 563 | // XXX 564 | return; 565 | } 566 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmc_ioreg.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmc_ioreg.h,v 1.6 2016/04/23 14:15:59 kettenis Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | #ifndef _SDMMC_IOREG_H 20 | #define _SDMMC_IOREG_H 21 | 22 | /* SDIO commands */ /* response type */ 23 | #define SD_IO_SEND_OP_COND 5 /* R4 */ 24 | #define SD_IO_RW_DIRECT 52 /* R5 */ 25 | #define SD_IO_RW_EXTENDED 53 /* R5? */ 26 | 27 | /* CMD52 arguments */ 28 | #define SD_ARG_CMD52_READ (0<<31) 29 | #define SD_ARG_CMD52_WRITE (1<<31) 30 | #define SD_ARG_CMD52_FUNC_SHIFT 28 31 | #define SD_ARG_CMD52_FUNC_MASK 0x7 32 | #define SD_ARG_CMD52_EXCHANGE (1<<27) 33 | #define SD_ARG_CMD52_REG_SHIFT 9 34 | #define SD_ARG_CMD52_REG_MASK 0x1ffff 35 | #define SD_ARG_CMD52_DATA_SHIFT 0 36 | #define SD_ARG_CMD52_DATA_MASK 0xff 37 | #define SD_R5_DATA(resp) ((resp)[0] & 0xff) 38 | 39 | /* CMD53 arguments */ 40 | #define SD_ARG_CMD53_READ (0<<31) 41 | #define SD_ARG_CMD53_WRITE (1<<31) 42 | #define SD_ARG_CMD53_FUNC_SHIFT 28 43 | #define SD_ARG_CMD53_FUNC_MASK 0x7 44 | #define SD_ARG_CMD53_BLOCK_MODE (1<<27) 45 | #define SD_ARG_CMD53_INCREMENT (1<<26) 46 | #define SD_ARG_CMD53_REG_SHIFT 9 47 | #define SD_ARG_CMD53_REG_MASK 0x1ffff 48 | #define SD_ARG_CMD53_LENGTH_SHIFT 0 49 | #define SD_ARG_CMD53_LENGTH_MASK 0x1ff 50 | #define SD_ARG_CMD53_LENGTH_MAX 64 /* XXX should be 511? */ 51 | 52 | /* 48-bit response decoding (32 bits w/o CRC) */ 53 | #define MMC_R4(resp) ((resp)[0]) 54 | #define MMC_R5(resp) ((resp)[0]) 55 | 56 | /* SD R4 response (IO OCR) */ 57 | #define SD_IO_OCR_MEM_READY (1<<31) 58 | #define SD_IO_OCR_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3) 59 | /* XXX big fat memory present "flag" because we don't know better */ 60 | #define SD_IO_OCR_MEM_PRESENT (0xf<<24) 61 | #define SD_IO_OCR_MASK 0x00fffff0 62 | 63 | /* Card Common Control Registers (CCCR) */ 64 | #define SD_IO_CCCR_START 0x00000 65 | #define SD_IO_CCCR_SIZE 0x100 66 | #define SD_IO_CCCR_FN_ENABLE 0x02 67 | #define SD_IO_CCCR_FN_READY 0x03 68 | #define SD_IO_CCCR_INT_ENABLE 0x04 69 | #define SD_IO_CCCR_CTL 0x06 70 | #define CCCR_CTL_RES (1<<3) 71 | #define SD_IO_CCCR_BUS_WIDTH 0x07 72 | #define CCCR_BUS_WIDTH_1 (0<<0) 73 | #define CCCR_BUS_WIDTH_4 (2<<0) 74 | #define CCCR_BUS_WIDTH_8 (3<<0) 75 | #define SD_IO_CCCR_CISPTR 0x09 /* XXX 9-10, 10-11, or 9-12 */ 76 | 77 | /* Function Basic Registers (FBR) */ 78 | #define SD_IO_FBR_START 0x00100 79 | #define SD_IO_FBR_SIZE 0x00700 80 | 81 | /* Card Information Structure (CIS) */ 82 | #define SD_IO_CIS_START 0x01000 83 | #define SD_IO_CIS_SIZE 0x17000 84 | 85 | /* CIS tuple codes (based on PC Card 16) */ 86 | #define SD_IO_CISTPL_NULL 0x00 87 | #define SD_IO_CISTPL_VERS_1 0x15 88 | #define SD_IO_CISTPL_MANFID 0x20 89 | #define SD_IO_CISTPL_FUNCID 0x21 90 | #define SD_IO_CISTPL_FUNCE 0x22 91 | #define SD_IO_CISTPL_END 0xff 92 | 93 | /* CISTPL_FUNCID codes */ 94 | #define TPLFID_FUNCTION_SDIO 0x0c 95 | 96 | #endif 97 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmc_mem.cpp: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmc_mem.c,v 1.29 2016/05/05 20:40:48 kettenis Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | /* Routines for SD/MMC memory cards. */ 20 | 21 | #include 22 | #include 23 | #include 24 | #include 25 | 26 | #include "sdmmcchip.h" 27 | #include "sdmmcreg.h" 28 | #include "sdmmcvar.h" 29 | 30 | #include "Sinetek_rtsx.hpp" 31 | 32 | typedef struct __attribute__((packed, aligned(4))) { uint32_t _bits[512/32]; } sdmmc_bitfield512_t; 33 | 34 | void sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *); 35 | 36 | int sdmmc_decode_csd(struct sdmmc_softc *, sdmmc_response, 37 | struct sdmmc_function *); 38 | int sdmmc_decode_cid(struct sdmmc_softc *, sdmmc_response, 39 | struct sdmmc_function *); 40 | void sdmmc_print_cid(struct sdmmc_cid *); 41 | 42 | int sdmmc_mem_send_op_cond(struct sdmmc_softc *, u_int32_t, u_int32_t *); 43 | int sdmmc_mem_set_blocklen(struct sdmmc_softc *, struct sdmmc_function *); 44 | 45 | int sdmmc_mem_send_scr(struct sdmmc_softc *, uint32_t *); 46 | int sdmmc_mem_decode_scr(struct sdmmc_softc *, uint32_t *, 47 | struct sdmmc_function *); 48 | 49 | int sdmmc_mem_send_cxd_data(struct sdmmc_softc *, int, void *, size_t); 50 | int sdmmc_set_bus_width(struct sdmmc_function *, int); 51 | int sdmmc_mem_mmc_switch(struct sdmmc_function *, uint8_t, uint8_t, uint8_t); 52 | 53 | int sdmmc_mem_sd_init(struct sdmmc_softc *, struct sdmmc_function *); 54 | int sdmmc_mem_mmc_init(struct sdmmc_softc *, struct sdmmc_function *); 55 | //int sdmmc_mem_single_read_block(struct sdmmc_function *, int, u_char *, 56 | // size_t); 57 | int sdmmc_mem_read_block_subr(struct sdmmc_function *, 58 | int, u_char *, size_t); 59 | //int sdmmc_mem_single_write_block(struct sdmmc_function *, int, u_char *, 60 | // size_t); 61 | //int sdmmc_mem_write_block_subr(struct sdmmc_function *, bus_dmamap_t, 62 | // int, u_char *, size_t); 63 | 64 | #ifdef SDMMC_DEBUG 65 | #define DPRINTF(s) printf s 66 | #else 67 | #define DPRINTF(s) /**/ 68 | #endif 69 | 70 | /* 71 | * Initialize SD/MMC memory cards and memory in SDIO "combo" cards. 72 | */ 73 | int 74 | sdmmc_mem_enable(struct sdmmc_softc *sc) 75 | { 76 | u_int32_t host_ocr; 77 | u_int32_t card_ocr; 78 | 79 | /* Set host mode to SD "combo" card or SD memory-only. */ 80 | SET(sc->sc_flags, SMF_SD_MODE|SMF_MEM_MODE); 81 | 82 | /* Reset memory (*must* do that before CMD55 or CMD1). */ 83 | sdmmc_go_idle_state(sc); 84 | 85 | /* 86 | * Read the SD/MMC memory OCR value by issuing CMD55 followed 87 | * by ACMD41 to read the OCR value from memory-only SD cards. 88 | * MMC cards will not respond to CMD55 or ACMD41 and this is 89 | * how we distinguish them from SD cards. 90 | */ 91 | mmc_mode: 92 | if (sdmmc_mem_send_op_cond(sc, 0, &card_ocr) != 0) { 93 | if (ISSET(sc->sc_flags, SMF_SD_MODE) && 94 | !ISSET(sc->sc_flags, SMF_IO_MODE)) { 95 | /* Not a SD card, switch to MMC mode. */ 96 | CLR(sc->sc_flags, SMF_SD_MODE); 97 | goto mmc_mode; 98 | } 99 | if (!ISSET(sc->sc_flags, SMF_SD_MODE)) { 100 | DPRINTF(("%s: can't read memory OCR\n", 101 | DEVNAME(sc))); 102 | return 1; 103 | } else { 104 | /* Not a "combo" card. */ 105 | CLR(sc->sc_flags, SMF_MEM_MODE); 106 | return 0; 107 | } 108 | } 109 | 110 | /* Set the lowest voltage supported by the card and host. */ 111 | host_ocr = rtsx_host_ocr(sc); 112 | if (sdmmc_set_bus_power(sc, host_ocr, card_ocr) != 0) { 113 | DPRINTF(("%s: can't supply voltage requested by card\n", 114 | DEVNAME(sc))); 115 | return 1; 116 | } 117 | 118 | /* Tell the card(s) to enter the idle state (again). */ 119 | sdmmc_go_idle_state(sc); 120 | 121 | host_ocr &= card_ocr; /* only allow the common voltages */ 122 | 123 | if (sdmmc_send_if_cond(sc, card_ocr) == 0) 124 | host_ocr |= SD_OCR_SDHC_CAP; 125 | 126 | /* Send the new OCR value until all cards are ready. */ 127 | if (sdmmc_mem_send_op_cond(sc, host_ocr, NULL) != 0) { 128 | DPRINTF(("%s: can't send memory OCR\n", DEVNAME(sc))); 129 | return 1; 130 | } 131 | return 0; 132 | } 133 | 134 | /* 135 | * Read the CSD and CID from all cards and assign each card a unique 136 | * relative card address (RCA). CMD2 is ignored by SDIO-only cards. 137 | */ 138 | void 139 | sdmmc_mem_scan(struct sdmmc_softc *sc) 140 | { 141 | struct sdmmc_command cmd; 142 | struct sdmmc_function *sf; 143 | u_int16_t next_rca; 144 | int error; 145 | int i; 146 | 147 | /* 148 | * CMD2 is a broadcast command understood by SD cards and MMC 149 | * cards. All cards begin to respond to the command, but back 150 | * off if another card drives the CMD line to a different level. 151 | * Only one card will get its entire response through. That 152 | * card remains silent once it has been assigned a RCA. 153 | */ 154 | for (i = 0; i < 100; i++) { 155 | bzero(&cmd, sizeof cmd); 156 | cmd.c_opcode = MMC_ALL_SEND_CID; 157 | cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R2; 158 | 159 | error = sdmmc_mmc_command(sc, &cmd); 160 | if (error == ETIMEDOUT) { 161 | /* No more cards there. */ 162 | break; 163 | } else if (error != 0) { 164 | DPRINTF(("%s: can't read CID\n", DEVNAME(sc))); 165 | break; 166 | } 167 | 168 | /* In MMC mode, find the next available RCA. */ 169 | next_rca = 1; 170 | if (!ISSET(sc->sc_flags, SMF_SD_MODE)) 171 | STAILQ_FOREACH(sf, &sc->sf_head, sf_list) 172 | next_rca++; 173 | 174 | /* Allocate a sdmmc_function structure. */ 175 | sf = sdmmc_function_alloc(sc); 176 | sf->rca = next_rca; 177 | 178 | /* 179 | * Remember the CID returned in the CMD2 response for 180 | * later decoding. 181 | */ 182 | bcopy(cmd.c_resp, sf->raw_cid, sizeof sf->raw_cid); 183 | 184 | /* 185 | * Silence the card by assigning it a unique RCA, or 186 | * querying it for its RCA in the case of SD. 187 | */ 188 | if (sdmmc_set_relative_addr(sc, sf) != 0) { 189 | printf("%s: can't set mem RCA\n", DEVNAME(sc)); 190 | sdmmc_function_free(sf); 191 | break; 192 | } 193 | 194 | #if 0 195 | /* Verify that the RCA has been set by selecting the card. */ 196 | if (sdmmc_select_card(sc, sf) != 0) { 197 | printf("%s: can't select mem RCA %d\n", 198 | DEVNAME(sc), sf->rca); 199 | sdmmc_function_free(sf); 200 | break; 201 | } 202 | 203 | /* Deselect. */ 204 | (void)sdmmc_select_card(sc, NULL); 205 | #endif 206 | 207 | /* 208 | * If this is a memory-only card, the card responding 209 | * first becomes an alias for SDIO function 0. 210 | */ 211 | if (sc->sc_fn0 == NULL) 212 | sc->sc_fn0 = sf; 213 | 214 | STAILQ_INSERT_TAIL(&sc->sf_head, sf, sf_list); 215 | } 216 | 217 | /* 218 | * All cards are either inactive or awaiting further commands. 219 | * Read the CSDs and decode the raw CID for each card. 220 | */ 221 | STAILQ_FOREACH(sf, &sc->sf_head, sf_list) { 222 | bzero(&cmd, sizeof cmd); 223 | cmd.c_opcode = MMC_SEND_CSD; 224 | cmd.c_arg = MMC_ARG_RCA(sf->rca); 225 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R2; 226 | 227 | if (sdmmc_mmc_command(sc, &cmd) != 0) { 228 | SET(sf->flags, SFF_ERROR); 229 | continue; 230 | } 231 | 232 | if (sdmmc_decode_csd(sc, cmd.c_resp, sf) != 0 || 233 | sdmmc_decode_cid(sc, sf->raw_cid, sf) != 0) { 234 | SET(sf->flags, SFF_ERROR); 235 | continue; 236 | } 237 | 238 | #ifdef SDMMC_DEBUG 239 | printf("%s: CID: ", DEVNAME(sc)); 240 | sdmmc_print_cid(&sf->cid); 241 | #endif 242 | } 243 | } 244 | 245 | int 246 | sdmmc_decode_csd(struct sdmmc_softc *sc, sdmmc_response resp, 247 | struct sdmmc_function *sf) 248 | { 249 | struct sdmmc_csd *csd = &sf->csd; 250 | 251 | if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 252 | /* 253 | * CSD version 1.0 corresponds to SD system 254 | * specification version 1.0 - 1.10. (SanDisk, 3.5.3) 255 | */ 256 | csd->csdver = SD_CSD_CSDVER(resp); 257 | switch (csd->csdver) { 258 | case SD_CSD_CSDVER_2_0: 259 | sf->flags |= SFF_SDHC; 260 | csd->capacity = SD_CSD_V2_CAPACITY(resp); 261 | csd->read_bl_len = SD_CSD_V2_BL_LEN; 262 | break; 263 | case SD_CSD_CSDVER_1_0: 264 | csd->capacity = SD_CSD_CAPACITY(resp); 265 | csd->read_bl_len = SD_CSD_READ_BL_LEN(resp); 266 | break; 267 | default: 268 | printf("%s: unknown SD CSD structure version 0x%x\n", 269 | DEVNAME(sc), csd->csdver); 270 | return 1; 271 | break; 272 | } 273 | csd->ccc = SD_CSD_CCC(resp); 274 | } else { 275 | csd->csdver = MMC_CSD_CSDVER(resp); 276 | if (csd->csdver == MMC_CSD_CSDVER_1_0 || 277 | csd->csdver == MMC_CSD_CSDVER_2_0 || 278 | csd->csdver == MMC_CSD_CSDVER_EXT_CSD) { 279 | csd->mmcver = MMC_CSD_MMCVER(resp); 280 | csd->capacity = MMC_CSD_CAPACITY(resp); 281 | csd->read_bl_len = MMC_CSD_READ_BL_LEN(resp); 282 | } else { 283 | printf("%s: unknown MMC CSD structure version 0x%x\n", 284 | DEVNAME(sc), csd->csdver); 285 | return 1; 286 | } 287 | } 288 | csd->sector_size = MIN(1 << csd->read_bl_len, 289 | rtsx_host_maxblklen(sc)); 290 | if (csd->sector_size < (1<read_bl_len)) 291 | csd->capacity *= (1<read_bl_len) / 292 | csd->sector_size; 293 | 294 | return 0; 295 | } 296 | 297 | int 298 | sdmmc_decode_cid(struct sdmmc_softc *sc, sdmmc_response resp, 299 | struct sdmmc_function *sf) 300 | { 301 | struct sdmmc_cid *cid = &sf->cid; 302 | 303 | if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 304 | cid->mid = SD_CID_MID(resp); 305 | cid->oid = SD_CID_OID(resp); 306 | SD_CID_PNM_CPY(resp, cid->pnm); 307 | cid->rev = SD_CID_REV(resp); 308 | cid->psn = SD_CID_PSN(resp); 309 | cid->mdt = SD_CID_MDT(resp); 310 | } else { 311 | switch(sf->csd.mmcver) { 312 | case MMC_CSD_MMCVER_1_0: 313 | case MMC_CSD_MMCVER_1_4: 314 | cid->mid = MMC_CID_MID_V1(resp); 315 | MMC_CID_PNM_V1_CPY(resp, cid->pnm); 316 | cid->rev = MMC_CID_REV_V1(resp); 317 | cid->psn = MMC_CID_PSN_V1(resp); 318 | cid->mdt = MMC_CID_MDT_V1(resp); 319 | break; 320 | case MMC_CSD_MMCVER_2_0: 321 | case MMC_CSD_MMCVER_3_1: 322 | case MMC_CSD_MMCVER_4_0: 323 | cid->mid = MMC_CID_MID_V2(resp); 324 | cid->oid = MMC_CID_OID_V2(resp); 325 | MMC_CID_PNM_V2_CPY(resp, cid->pnm); 326 | cid->psn = MMC_CID_PSN_V2(resp); 327 | break; 328 | default: 329 | printf("%s: unknown MMC version %d\n", 330 | DEVNAME(sc), sf->csd.mmcver); 331 | return 1; 332 | } 333 | } 334 | return 0; 335 | } 336 | 337 | #ifdef SDMMC_DEBUG 338 | void 339 | sdmmc_print_cid(struct sdmmc_cid *cid) 340 | { 341 | printf("mid=0x%02x oid=0x%04x pnm=\"%s\" rev=0x%02x psn=0x%08x" 342 | " mdt=%03x\n", cid->mid, cid->oid, cid->pnm, cid->rev, cid->psn, 343 | cid->mdt); 344 | } 345 | #endif 346 | 347 | int 348 | sdmmc_mem_send_scr(struct sdmmc_softc *sc, uint32_t *scr) 349 | { 350 | struct sdmmc_command cmd; 351 | void *ptr = NULL; 352 | int datalen = 8; 353 | int error = 0; 354 | 355 | // ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 356 | ptr = new uint8_t [datalen] (); 357 | if (ptr == NULL) 358 | goto out; 359 | 360 | memset(&cmd, 0, sizeof(cmd)); 361 | cmd.c_data = ptr; 362 | cmd.c_datalen = datalen; 363 | cmd.c_blklen = datalen; 364 | cmd.c_arg = 0; 365 | cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 366 | cmd.c_opcode = SD_APP_SEND_SCR; 367 | 368 | error = sdmmc_app_command(sc, &cmd); 369 | if (error == 0) 370 | memcpy(scr, ptr, datalen); 371 | 372 | out: 373 | if (ptr != NULL) 374 | // free(ptr, M_DEVBUF, datalen); 375 | delete [] (uint8_t *) ptr; 376 | 377 | return error; 378 | } 379 | 380 | int 381 | sdmmc_mem_decode_scr(struct sdmmc_softc *sc, uint32_t *raw_scr, 382 | struct sdmmc_function *sf) 383 | { 384 | sdmmc_response resp; 385 | int ver; 386 | 387 | memset(resp, 0, sizeof(resp)); 388 | /* 389 | * Change the raw SCR to a response. 390 | */ 391 | resp[0] = OSSwapBigToHostInt32(raw_scr[1]) >> 8; // LSW 392 | resp[1] = OSSwapBigToHostInt32(raw_scr[0]); // MSW 393 | resp[0] |= (resp[1] & 0xff) << 24; 394 | resp[1] >>= 8; 395 | 396 | ver = SCR_STRUCTURE(resp); 397 | sf->scr.sd_spec = SCR_SD_SPEC(resp); 398 | sf->scr.bus_width = SCR_SD_BUS_WIDTHS(resp); 399 | 400 | DPRINTF(("%s: %s: %08x%08x ver=%d, spec=%d, bus width=%d\n", 401 | DEVNAME(sc), __func__, resp[1], resp[0], 402 | ver, sf->scr.sd_spec, sf->scr.bus_width)); 403 | 404 | if (ver != 0) { 405 | DPRINTF(("%s: unknown SCR structure version: %d\n", 406 | DEVNAME(sc), ver)); 407 | return EINVAL; 408 | } 409 | return 0; 410 | } 411 | 412 | int 413 | sdmmc_mem_send_cxd_data(struct sdmmc_softc *sc, int opcode, void *data, 414 | size_t datalen) 415 | { 416 | struct sdmmc_command cmd; 417 | void *ptr = NULL; 418 | int error = 0; 419 | 420 | // ptr = malloc(datalen, M_DEVBUF, M_NOWAIT | M_ZERO); 421 | ptr = new uint8_t[datalen] (); 422 | if (ptr == NULL) { 423 | error = ENOMEM; 424 | goto out; 425 | } 426 | 427 | memset(&cmd, 0, sizeof(cmd)); 428 | cmd.c_data = ptr; 429 | cmd.c_datalen = datalen; 430 | cmd.c_blklen = datalen; 431 | cmd.c_opcode = opcode; 432 | cmd.c_arg = 0; 433 | cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ; 434 | if (opcode == MMC_SEND_EXT_CSD) 435 | SET(cmd.c_flags, SCF_RSP_R1); 436 | else 437 | SET(cmd.c_flags, SCF_RSP_R2); 438 | 439 | error = sdmmc_mmc_command(sc, &cmd); 440 | if (error == 0) 441 | memcpy(data, ptr, datalen); 442 | 443 | out: 444 | if (ptr != NULL) 445 | // free(ptr, M_DEVBUF, 0); 446 | delete [] (uint8_t *) ptr; 447 | 448 | return error; 449 | } 450 | 451 | int 452 | sdmmc_set_bus_width(struct sdmmc_function *sf, int width) 453 | { 454 | struct sdmmc_softc *sc = sf->sc; 455 | struct sdmmc_command cmd; 456 | int error; 457 | 458 | memset(&cmd, 0, sizeof(cmd)); 459 | cmd.c_opcode = SD_APP_SET_BUS_WIDTH; 460 | cmd.c_flags = SCF_RSP_R1 | SCF_CMD_AC; 461 | 462 | switch (width) { 463 | case 1: 464 | cmd.c_arg = SD_ARG_BUS_WIDTH_1; 465 | break; 466 | 467 | case 4: 468 | cmd.c_arg = SD_ARG_BUS_WIDTH_4; 469 | break; 470 | 471 | default: 472 | return EINVAL; 473 | } 474 | 475 | error = sdmmc_app_command(sc, &cmd); 476 | if (error == 0) 477 | error = rtsx_bus_width(sc, width); 478 | return error; 479 | } 480 | 481 | int 482 | sdmmc_mem_sd_switch(struct sdmmc_function *sf, int mode, int group, 483 | int function, sdmmc_bitfield512_t *status) 484 | { 485 | struct sdmmc_softc *sc = sf->sc; 486 | struct sdmmc_command cmd; 487 | void *ptr = NULL; 488 | int gsft, error = 0; 489 | const int statlen = 64; 490 | 491 | if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 492 | !ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) 493 | return EINVAL; 494 | 495 | if (group <= 0 || group > 6 || 496 | function < 0 || function > 15) 497 | return EINVAL; 498 | 499 | gsft = (group - 1) << 2; 500 | 501 | // ptr = malloc(statlen, M_DEVBUF, M_NOWAIT | M_ZERO); 502 | ptr = new uint8_t[statlen] (); 503 | if (ptr == NULL) 504 | goto out; 505 | 506 | memset(&cmd, 0, sizeof(cmd)); 507 | cmd.c_data = ptr; 508 | cmd.c_datalen = statlen; 509 | cmd.c_blklen = statlen; 510 | cmd.c_opcode = SD_SEND_SWITCH_FUNC; 511 | cmd.c_arg = 512 | (!!mode << 31) | (function << gsft) | (0x00ffffff & ~(0xf << gsft)); 513 | cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 514 | 515 | error = sdmmc_mmc_command(sc, &cmd); 516 | if (error == 0) 517 | memcpy(status, ptr, statlen); 518 | 519 | out: 520 | if (ptr != NULL) 521 | // free(ptr, M_DEVBUF, statlen); 522 | delete [] (uint8_t *) ptr; 523 | 524 | if (error == 0) 525 | sdmmc_be512_to_bitfield512(status); 526 | 527 | return error; 528 | } 529 | 530 | int 531 | sdmmc_mem_mmc_switch(struct sdmmc_function *sf, uint8_t set, uint8_t index, 532 | uint8_t value) 533 | { 534 | struct sdmmc_softc *sc = sf->sc; 535 | struct sdmmc_command cmd; 536 | 537 | memset(&cmd, 0, sizeof(cmd)); 538 | cmd.c_opcode = MMC_SWITCH; 539 | cmd.c_arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 540 | (index << 16) | (value << 8) | set; 541 | cmd.c_flags = SCF_RSP_R1B | SCF_CMD_AC; 542 | 543 | return sdmmc_mmc_command(sc, &cmd); 544 | } 545 | 546 | /* 547 | * Initialize a SD/MMC memory card. 548 | */ 549 | int 550 | sdmmc_mem_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 551 | { 552 | int error = 0; 553 | 554 | if (sdmmc_select_card(sc, sf) != 0 || 555 | sdmmc_mem_set_blocklen(sc, sf) != 0) 556 | error = 1; 557 | 558 | if (ISSET(sc->sc_flags, SMF_SD_MODE)) 559 | error = sdmmc_mem_sd_init(sc, sf); 560 | else 561 | error = sdmmc_mem_mmc_init(sc, sf); 562 | 563 | return error; 564 | } 565 | 566 | /* make 512-bit BE quantity __bitfield()-compatible */ 567 | void 568 | sdmmc_be512_to_bitfield512(sdmmc_bitfield512_t *buf) { 569 | #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0])) 570 | size_t i; 571 | uint32_t tmp0, tmp1; 572 | const size_t bitswords = nitems(buf->_bits); 573 | for (i = 0; i < bitswords/2; i++) { 574 | tmp0 = buf->_bits[i]; 575 | tmp1 = buf->_bits[bitswords - 1 - i]; 576 | buf->_bits[i] = OSSwapBigToHostInt32(tmp1); 577 | buf->_bits[bitswords - 1 - i] = OSSwapBigToHostInt32(tmp0); 578 | } 579 | #undef nitems 580 | } 581 | 582 | int 583 | sdmmc_mem_sd_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 584 | { 585 | int support_func, best_func, error; 586 | sdmmc_bitfield512_t status; /* Switch Function Status */ 587 | uint32_t raw_scr[2]; 588 | 589 | /* 590 | * All SD cards are supposed to support Default Speed mode 591 | * with frequencies up to 25 MHz. Bump up the clock frequency 592 | * now as data transfers don't seem to work on the Realtek 593 | * RTS5229 host controller if it is running at a low clock 594 | * frequency. Reading the SCR requires a data transfer. 595 | */ 596 | error = rtsx_bus_clock(sc, SDMMC_SDCLK_25MHZ, 597 | SDMMC_TIMING_LEGACY); 598 | if (error) { 599 | printf("%s: can't change bus clock\n", DEVNAME(sc)); 600 | return error; 601 | } 602 | 603 | error = sdmmc_mem_send_scr(sc, raw_scr); 604 | if (error) { 605 | printf("%s: SD_SEND_SCR send failed\n", DEVNAME(sc)); 606 | return error; 607 | } 608 | error = sdmmc_mem_decode_scr(sc, raw_scr, sf); 609 | if (error) 610 | return error; 611 | 612 | if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE) && 613 | ISSET(sf->scr.bus_width, SCR_SD_BUS_WIDTHS_4BIT)) { 614 | DPRINTF(("%s: change bus width\n", DEVNAME(sc))); 615 | error = sdmmc_set_bus_width(sf, 4); 616 | if (error) { 617 | printf("%s: can't change bus width\n", DEVNAME(sc)); 618 | return error; 619 | } 620 | } 621 | 622 | best_func = 0; 623 | if (sf->scr.sd_spec >= SCR_SD_SPEC_VER_1_10 && 624 | ISSET(sf->csd.ccc, SD_CSD_CCC_SWITCH)) { 625 | DPRINTF(("%s: switch func mode 0\n", DEVNAME(sc))); 626 | error = sdmmc_mem_sd_switch(sf, 0, 1, 0, &status); 627 | if (error) { 628 | printf("%s: switch func mode 0 failed\n", DEVNAME(sc)); 629 | return error; 630 | } 631 | 632 | support_func = SFUNC_STATUS_GROUP(&status, 1); 633 | 634 | if (support_func & (1 << SD_ACCESS_MODE_SDR25)) 635 | best_func = 1; 636 | } 637 | 638 | if (best_func != 0) { 639 | DPRINTF(("%s: switch func mode 1(func=%d)\n", 640 | DEVNAME(sc), best_func)); 641 | error = 642 | sdmmc_mem_sd_switch(sf, 1, 1, best_func, &status); 643 | if (error) { 644 | printf("%s: switch func mode 1 failed:" 645 | " group 1 function %d(0x%2x)\n", 646 | DEVNAME(sc), best_func, support_func); 647 | return error; 648 | } 649 | 650 | /* Wait 400KHz x 8 clock (2.5us * 8 + slop) */ 651 | IODelay(25); 652 | 653 | /* High Speed mode, Frequency up to 50MHz. */ 654 | error = rtsx_bus_clock(sc, 655 | SDMMC_SDCLK_50MHZ, SDMMC_TIMING_HIGHSPEED); 656 | if (error) { 657 | printf("%s: can't change bus clock\n", DEVNAME(sc)); 658 | return error; 659 | } 660 | } 661 | 662 | return 0; 663 | } 664 | 665 | int 666 | sdmmc_mem_mmc_init(struct sdmmc_softc *sc, struct sdmmc_function *sf) 667 | { 668 | int width, value; 669 | int card_type; 670 | int error = 0; 671 | u_int8_t ext_csd[512]; 672 | int speed = 20000; 673 | int timing = SDMMC_TIMING_LEGACY; 674 | u_int32_t sectors = 0; 675 | 676 | if (sf->csd.mmcver >= MMC_CSD_MMCVER_4_0) { 677 | /* read EXT_CSD */ 678 | error = sdmmc_mem_send_cxd_data(sc, 679 | MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 680 | if (error != 0) { 681 | SET(sf->flags, SFF_ERROR); 682 | printf("%s: can't read EXT_CSD\n", DEVNAME(sc)); 683 | return error; 684 | } 685 | 686 | card_type = ext_csd[EXT_CSD_CARD_TYPE]; 687 | 688 | if (card_type & EXT_CSD_CARD_TYPE_F_52M_1_8V && 689 | ISSET(sc->sc_caps, SMC_CAPS_MMC_DDR52)) { 690 | speed = 52000; 691 | timing = SDMMC_TIMING_MMC_DDR52; 692 | } else if (card_type & EXT_CSD_CARD_TYPE_F_52M && 693 | ISSET(sc->sc_caps, SMC_CAPS_MMC_HIGHSPEED)) { 694 | speed = 52000; 695 | timing = SDMMC_TIMING_HIGHSPEED; 696 | } else if (card_type & EXT_CSD_CARD_TYPE_F_26M) { 697 | speed = 26000; 698 | } else { 699 | printf("%s: unknown CARD_TYPE 0x%x\n", DEVNAME(sc), 700 | ext_csd[EXT_CSD_CARD_TYPE]); 701 | } 702 | 703 | if (timing != SDMMC_TIMING_LEGACY) { 704 | /* switch to high speed timing */ 705 | error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 706 | EXT_CSD_HS_TIMING, EXT_CSD_HS_TIMING_HS); 707 | if (error != 0) { 708 | printf("%s: can't change high speed\n", 709 | DEVNAME(sc)); 710 | return error; 711 | } 712 | 713 | sdmmc_delay(10000); 714 | } 715 | 716 | error = rtsx_bus_clock(sc, speed, SDMMC_TIMING_HIGHSPEED); 717 | if (error != 0) { 718 | printf("%s: can't change bus clock\n", DEVNAME(sc)); 719 | return error; 720 | } 721 | 722 | if (timing != SDMMC_TIMING_LEGACY) { 723 | /* read EXT_CSD again */ 724 | error = sdmmc_mem_send_cxd_data(sc, 725 | MMC_SEND_EXT_CSD, ext_csd, sizeof(ext_csd)); 726 | if (error != 0) { 727 | printf("%s: can't re-read EXT_CSD\n", DEVNAME(sc)); 728 | return error; 729 | } 730 | if (ext_csd[EXT_CSD_HS_TIMING] != EXT_CSD_HS_TIMING_HS) { 731 | printf("%s, HS_TIMING set failed\n", DEVNAME(sc)); 732 | return EINVAL; 733 | } 734 | } 735 | 736 | if (ISSET(sc->sc_caps, SMC_CAPS_8BIT_MODE)) { 737 | width = 8; 738 | value = EXT_CSD_BUS_WIDTH_8; 739 | } else if (ISSET(sc->sc_caps, SMC_CAPS_4BIT_MODE)) { 740 | width = 4; 741 | value = EXT_CSD_BUS_WIDTH_4; 742 | } else { 743 | width = 1; 744 | value = EXT_CSD_BUS_WIDTH_1; 745 | } 746 | 747 | if (width != 1) { 748 | error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 749 | EXT_CSD_BUS_WIDTH, value); 750 | if (error == 0) 751 | error = rtsx_bus_width(sc, width); 752 | else { 753 | DPRINTF(("%s: can't change bus width" 754 | " (%d bit)\n", DEVNAME(sc), width)); 755 | return error; 756 | } 757 | 758 | /* XXXX: need bus test? (using by CMD14 & CMD19) */ 759 | sdmmc_delay(10000); 760 | } 761 | 762 | if (timing == SDMMC_TIMING_MMC_DDR52) { 763 | switch (width) { 764 | case 4: 765 | value = EXT_CSD_BUS_WIDTH_4_DDR; 766 | break; 767 | case 8: 768 | value = EXT_CSD_BUS_WIDTH_8_DDR; 769 | break; 770 | } 771 | 772 | error = sdmmc_mem_mmc_switch(sf, EXT_CSD_CMD_SET_NORMAL, 773 | EXT_CSD_BUS_WIDTH, value); 774 | if (error) { 775 | printf("%s: can't switch to DDR\n", 776 | DEVNAME(sc)); 777 | return error; 778 | } 779 | 780 | sdmmc_delay(10000); 781 | 782 | // error = sdmmc_chip_signal_voltage(sc->sct, sc->sch, 783 | // SDMMC_SIGNAL_VOLTAGE_180); 784 | // if (error) { 785 | // printf("%s: can't switch signalling voltage\n", 786 | // DEVNAME(sc)); 787 | // return error; 788 | // } 789 | printf("please implement sdmmc_chip_signal_voltage()\n"); 790 | 791 | error = rtsx_bus_clock(sc, speed, timing); 792 | if (error != 0) { 793 | printf("%s: can't change bus clock\n", DEVNAME(sc)); 794 | return error; 795 | } 796 | 797 | sdmmc_delay(10000); 798 | } 799 | 800 | sectors = ext_csd[EXT_CSD_SEC_COUNT + 0] << 0 | 801 | ext_csd[EXT_CSD_SEC_COUNT + 1] << 8 | 802 | ext_csd[EXT_CSD_SEC_COUNT + 2] << 16 | 803 | ext_csd[EXT_CSD_SEC_COUNT + 3] << 24; 804 | 805 | if (sectors > (2u * 1024 * 1024 * 1024) / 512) { 806 | sf->flags |= SFF_SDHC; 807 | sf->csd.capacity = sectors; 808 | } 809 | } 810 | 811 | return error; 812 | } 813 | 814 | /* 815 | * Get or set the card's memory OCR value (SD or MMC). 816 | */ 817 | int 818 | sdmmc_mem_send_op_cond(struct sdmmc_softc *sc, u_int32_t ocr, 819 | u_int32_t *ocrp) 820 | { 821 | struct sdmmc_command cmd; 822 | int error; 823 | int i; 824 | 825 | /* 826 | * If we change the OCR value, retry the command until the OCR 827 | * we receive in response has the "CARD BUSY" bit set, meaning 828 | * that all cards are ready for identification. 829 | */ 830 | for (i = 0; i < 100; i++) { 831 | bzero(&cmd, sizeof cmd); 832 | cmd.c_arg = ocr; 833 | cmd.c_flags = SCF_CMD_BCR | SCF_RSP_R3; 834 | 835 | if (ISSET(sc->sc_flags, SMF_SD_MODE)) { 836 | cmd.c_opcode = SD_APP_OP_COND; 837 | error = sdmmc_app_command(sc, &cmd); 838 | } else { 839 | cmd.c_arg &= ~MMC_OCR_ACCESS_MODE_MASK; 840 | cmd.c_arg |= MMC_OCR_SECTOR_MODE; 841 | cmd.c_opcode = MMC_SEND_OP_COND; 842 | error = sdmmc_mmc_command(sc, &cmd); 843 | } 844 | if (error != 0) 845 | break; 846 | if (ISSET(MMC_R3(cmd.c_resp), MMC_OCR_MEM_READY) || 847 | ocr == 0) 848 | break; 849 | error = ETIMEDOUT; 850 | sdmmc_delay(10000); 851 | } 852 | if (error == 0 && ocrp != NULL) 853 | *ocrp = MMC_R3(cmd.c_resp); 854 | 855 | return error; 856 | } 857 | 858 | /* 859 | * Set the read block length appropriately for this card, according to 860 | * the card CSD register value. 861 | */ 862 | int 863 | sdmmc_mem_set_blocklen(struct sdmmc_softc *sc, struct sdmmc_function *sf) 864 | { 865 | struct sdmmc_command cmd; 866 | 867 | bzero(&cmd, sizeof cmd); 868 | cmd.c_opcode = MMC_SET_BLOCKLEN; 869 | cmd.c_arg = sf->csd.sector_size; 870 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 871 | DPRINTF(("%s: read_bl_len=%d sector_size=%d\n", DEVNAME(sc), 872 | 1 << sf->csd.read_bl_len, sf->csd.sector_size)); 873 | 874 | return sdmmc_mmc_command(sc, &cmd); 875 | } 876 | 877 | int 878 | sdmmc_mem_read_block_subr(struct sdmmc_function *sf, 879 | int blkno, u_char *data, size_t datalen) 880 | { 881 | struct sdmmc_softc *sc = sf->sc; 882 | struct sdmmc_command cmd; 883 | int error; 884 | 885 | 886 | if ((error = sdmmc_select_card(sc, sf)) != 0) 887 | goto err; 888 | 889 | bzero(&cmd, sizeof cmd); 890 | cmd.c_data = data; 891 | cmd.c_datalen = datalen; 892 | cmd.c_blklen = sf->csd.sector_size; 893 | cmd.c_opcode = (datalen / cmd.c_blklen) > 1 ? 894 | MMC_READ_BLOCK_MULTIPLE : MMC_READ_BLOCK_SINGLE; 895 | if (sf->flags & SFF_SDHC) 896 | cmd.c_arg = blkno; 897 | else 898 | cmd.c_arg = blkno << 9; 899 | cmd.c_flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1; 900 | // cmd.c_dmamap = dmap; 901 | 902 | error = sdmmc_mmc_command(sc, &cmd); 903 | if (error != 0) 904 | goto err; 905 | 906 | if (ISSET(sc->sc_flags, SMF_STOP_AFTER_MULTIPLE) && 907 | cmd.c_opcode == MMC_READ_BLOCK_MULTIPLE) { 908 | bzero(&cmd, sizeof cmd); 909 | cmd.c_opcode = MMC_STOP_TRANSMISSION; 910 | cmd.c_arg = MMC_ARG_RCA(sf->rca); 911 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B; 912 | error = sdmmc_mmc_command(sc, &cmd); 913 | if (error != 0) 914 | goto err; 915 | } 916 | 917 | do { 918 | bzero(&cmd, sizeof cmd); 919 | cmd.c_opcode = MMC_SEND_STATUS; 920 | cmd.c_arg = MMC_ARG_RCA(sf->rca); 921 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 922 | error = sdmmc_mmc_command(sc, &cmd); 923 | if (error != 0) 924 | break; 925 | /* XXX time out */ 926 | } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 927 | 928 | err: 929 | return (error); 930 | } 931 | 932 | int 933 | sdmmc_mem_single_read_block(struct sdmmc_function *sf, int blkno, u_char *data, 934 | size_t datalen) 935 | { 936 | int error = 0; 937 | int i; 938 | 939 | for (i = 0; i < datalen / sf->csd.sector_size; i++) { 940 | error = sdmmc_mem_read_block_subr(sf, blkno + i, 941 | data + i * sf->csd.sector_size, sf->csd.sector_size); 942 | if (error) 943 | break; 944 | } 945 | 946 | return (error); 947 | } 948 | 949 | int 950 | sdmmc_mem_read_block(struct sdmmc_function *sf, int blkno, u_char *data, 951 | size_t datalen) 952 | { 953 | struct sdmmc_softc *sc = sf->sc; 954 | int error; 955 | 956 | if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 957 | error = sdmmc_mem_single_read_block(sf, blkno, data, datalen); 958 | goto out; 959 | } 960 | 961 | if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 962 | error = sdmmc_mem_read_block_subr(sf, blkno, 963 | data, datalen); 964 | goto out; 965 | } 966 | 967 | /* DMA transfer */ 968 | // XXX 969 | error = ENOTSUP; 970 | 971 | out: 972 | return (error); 973 | } 974 | 975 | int 976 | sdmmc_mem_write_block_subr(struct sdmmc_function *sf, void* dmap, 977 | int blkno, u_char *data, size_t datalen) 978 | { 979 | struct sdmmc_softc *sc = sf->sc; 980 | struct sdmmc_command cmd; 981 | int error; 982 | 983 | if ((error = sdmmc_select_card(sc, sf)) != 0) 984 | goto err; 985 | 986 | bzero(&cmd, sizeof cmd); 987 | cmd.c_data = data; 988 | cmd.c_datalen = datalen; 989 | cmd.c_blklen = sf->csd.sector_size; 990 | cmd.c_opcode = (datalen / cmd.c_blklen) > 1 ? 991 | MMC_WRITE_BLOCK_MULTIPLE : MMC_WRITE_BLOCK_SINGLE; 992 | if (sf->flags & SFF_SDHC) 993 | cmd.c_arg = blkno; 994 | else 995 | cmd.c_arg = blkno << 9; 996 | cmd.c_flags = SCF_CMD_ADTC | SCF_RSP_R1; 997 | // cmd.c_dmamap = dmap; 998 | 999 | error = sdmmc_mmc_command(sc, &cmd); 1000 | if (error != 0) 1001 | goto err; 1002 | 1003 | if (ISSET(sc->sc_flags, SMF_STOP_AFTER_MULTIPLE) && 1004 | cmd.c_opcode == MMC_WRITE_BLOCK_MULTIPLE) { 1005 | bzero(&cmd, sizeof cmd); 1006 | cmd.c_opcode = MMC_STOP_TRANSMISSION; 1007 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1B; 1008 | error = sdmmc_mmc_command(sc, &cmd); 1009 | if (error != 0) 1010 | goto err; 1011 | } 1012 | 1013 | do { 1014 | bzero(&cmd, sizeof cmd); 1015 | cmd.c_opcode = MMC_SEND_STATUS; 1016 | cmd.c_arg = MMC_ARG_RCA(sf->rca); 1017 | cmd.c_flags = SCF_CMD_AC | SCF_RSP_R1; 1018 | error = sdmmc_mmc_command(sc, &cmd); 1019 | if (error != 0) 1020 | break; 1021 | /* XXX time out */ 1022 | } while (!ISSET(MMC_R1(cmd.c_resp), MMC_R1_READY_FOR_DATA)); 1023 | 1024 | err: 1025 | return (error); 1026 | } 1027 | 1028 | int 1029 | sdmmc_mem_single_write_block(struct sdmmc_function *sf, int blkno, u_char *data, 1030 | size_t datalen) 1031 | { 1032 | int error = 0; 1033 | int i; 1034 | 1035 | for (i = 0; i < datalen / sf->csd.sector_size; i++) { 1036 | error = sdmmc_mem_write_block_subr(sf, NULL, blkno + i, 1037 | data + i * sf->csd.sector_size, sf->csd.sector_size); 1038 | if (error) 1039 | break; 1040 | } 1041 | 1042 | return (error); 1043 | } 1044 | 1045 | int 1046 | sdmmc_mem_write_block(struct sdmmc_function *sf, int blkno, u_char *data, 1047 | size_t datalen) 1048 | { 1049 | struct sdmmc_softc *sc = sf->sc; 1050 | int error; 1051 | 1052 | if (ISSET(sc->sc_caps, SMC_CAPS_SINGLE_ONLY)) { 1053 | error = sdmmc_mem_single_write_block(sf, blkno, data, datalen); 1054 | goto out; 1055 | } 1056 | 1057 | if (!ISSET(sc->sc_caps, SMC_CAPS_DMA)) { 1058 | error = sdmmc_mem_write_block_subr(sf, NULL, blkno, 1059 | data, datalen); 1060 | goto out; 1061 | } 1062 | 1063 | /* DMA transfer */ 1064 | // XXX 1065 | error = ENOTSUP; 1066 | 1067 | out: 1068 | return (error); 1069 | } 1070 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmcchip.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmcchip.h,v 1.9 2016/05/05 20:40:48 kettenis Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | #ifndef _SDMMC_CHIP_H_ 20 | #define _SDMMC_CHIP_H_ 21 | 22 | struct sdmmc_command; 23 | 24 | //typedef struct sdmmc_chip_functions *sdmmc_chipset_tag_t; 25 | //typedef void *sdmmc_chipset_handle_t; 26 | // 27 | //struct sdmmc_chip_functions { 28 | // /* host controller reset */ 29 | // int (*host_reset)(sdmmc_chipset_handle_t); 30 | // /* host capabilities */ 31 | // u_int32_t (*host_ocr)(sdmmc_chipset_handle_t); 32 | // int (*host_maxblklen)(sdmmc_chipset_handle_t); 33 | // /* card detection */ 34 | // int (*card_detect)(sdmmc_chipset_handle_t); 35 | // /* bus power and clock frequency */ 36 | // int (*bus_power)(sdmmc_chipset_handle_t, u_int32_t); 37 | // int (*bus_clock)(sdmmc_chipset_handle_t, int, int); 38 | // int (*bus_width)(sdmmc_chipset_handle_t, int); 39 | // /* command execution */ 40 | // void (*exec_command)(sdmmc_chipset_handle_t, 41 | // struct sdmmc_command *); 42 | // /* card interrupt */ 43 | // void (*card_intr_mask)(sdmmc_chipset_handle_t, int); 44 | // void (*card_intr_ack)(sdmmc_chipset_handle_t); 45 | // /* UHS functions */ 46 | // int (*signal_voltage)(sdmmc_chipset_handle_t, int); 47 | //}; 48 | 49 | ///* host controller reset */ 50 | //#define sdmmc_chip_host_reset(tag, handle) \ 51 | //((tag)->host_reset((handle))) 52 | ///* host capabilities */ 53 | //#define sdmmc_chip_host_ocr(tag, handle) \ 54 | //((tag)->host_ocr((handle))) 55 | //#define sdmmc_chip_host_maxblklen(tag, handle) \ 56 | //((tag)->host_maxblklen((handle))) 57 | ///* card detection */ 58 | //#define sdmmc_chip_card_detect(tag, handle) \ 59 | //((tag)->card_detect((handle))) 60 | ///* bus power and clock frequency */ 61 | //#define sdmmc_chip_bus_power(tag, handle, ocr) \ 62 | //((tag)->bus_power((handle), (ocr))) 63 | //#define sdmmc_chip_bus_clock(tag, handle, freq, timing) \ 64 | //((tag)->bus_clock((handle), (freq), (timing))) 65 | //#define sdmmc_chip_bus_width(tag, handle, width) \ 66 | //((tag)->bus_width((handle), (width))) 67 | ///* command execution */ 68 | //#define sdmmc_chip_exec_command(tag, handle, cmdp) \ 69 | //((tag)->exec_command((handle), (cmdp))) 70 | ///* card interrupt */ 71 | //#define sdmmc_chip_card_intr_mask(tag, handle, enable) \ 72 | //((tag)->card_intr_mask((handle), (enable))) 73 | //#define sdmmc_chip_card_intr_ack(tag, handle) \ 74 | //((tag)->card_intr_ack((handle))) 75 | ///* UHS functions */ 76 | //#define sdmmc_chip_signal_voltage(tag, handle, voltage) \ 77 | //((tag)->signal_voltage((handle), (voltage))) 78 | 79 | #define sdmmc_chipset_handle_t struct rtsx_softc * 80 | 81 | int rtsx_host_reset(sdmmc_chipset_handle_t); 82 | u_int32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 83 | int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 84 | int rtsx_card_detect(sdmmc_chipset_handle_t); 85 | int rtsx_bus_power(sdmmc_chipset_handle_t, u_int32_t); 86 | int rtsx_bus_clock(sdmmc_chipset_handle_t, int, int); 87 | int rtsx_bus_width(sdmmc_chipset_handle_t, int); 88 | void rtsx_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 89 | 90 | /* clock frequencies for sdmmc_chip_bus_clock() */ 91 | #define SDMMC_SDCLK_OFF 0 92 | #define SDMMC_SDCLK_400KHZ 400 93 | #define SDMMC_SDCLK_25MHZ 25000 94 | #define SDMMC_SDCLK_50MHZ 50000 95 | 96 | /* voltage levels for sdmmc_chip_signal_voltage() */ 97 | #define SDMMC_SIGNAL_VOLTAGE_330 0 98 | #define SDMMC_SIGNAL_VOLTAGE_180 1 99 | 100 | #define SDMMC_TIMING_LEGACY 0 101 | #define SDMMC_TIMING_HIGHSPEED 1 102 | #define SDMMC_TIMING_MMC_DDR52 2 103 | 104 | //struct sdmmcbus_attach_args { 105 | // const char *saa_busname; 106 | // sdmmc_chipset_tag_t sct; 107 | // sdmmc_chipset_handle_t sch; 108 | // bus_dma_tag_t dmat; 109 | // int flags; 110 | // int caps; 111 | // long max_xfer; 112 | //}; 113 | 114 | void sdmmc_needs_discover(struct device *); 115 | //void sdmmc_card_intr(struct device *); 116 | void sdmmc_delay(u_int); 117 | 118 | #endif 119 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmcdevs.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmcdevs.h,v 1.8 2007/05/11 17:16:35 mglocker Exp $ */ 2 | 3 | /* 4 | * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 5 | * 6 | * generated from: 7 | * OpenBSD: sdmmcdevs,v 1.8 2007/05/11 17:16:16 mglocker Exp 8 | */ 9 | 10 | /* 11 | * Copyright (c) 2006 Uwe Stuehler 12 | * 13 | * Permission to use, copy, modify, and distribute this software for any 14 | * purpose with or without fee is hereby granted, provided that the above 15 | * copyright notice and this permission notice appear in all copies. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 18 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 19 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 20 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 21 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 22 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 23 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 24 | */ 25 | 26 | /* 27 | * List of known SD card vendors 28 | */ 29 | 30 | #define SDMMC_VENDOR_CGUYS 0x0092 /* C-guys, Inc. */ 31 | #define SDMMC_VENDOR_TOSHIBA 0x0098 /* Toshiba */ 32 | #define SDMMC_VENDOR_SOCKETCOM 0x0104 /* Socket Communications, Inc. */ 33 | #define SDMMC_VENDOR_ATHEROS 0x0271 /* Atheros */ 34 | #define SDMMC_VENDOR_SYCHIP 0x02db /* SyChip Inc. */ 35 | #define SDMMC_VENDOR_SPECTEC 0x02fe /* Spectec Computer Co., Ltd */ 36 | #define SDMMC_VENDOR_GLOBALSAT 0x0501 /* Globalsat Technology Co. */ 37 | #define SDMMC_VENDOR_MEDIATEK 0x037a /* MediaTek Inc. */ 38 | #define SDMMC_VENDOR_ABOCOM 0x13d1 /* AboCom Systems, Inc. */ 39 | 40 | /* 41 | * List of known products, grouped by vendor 42 | */ 43 | 44 | /* AboCom Systems, Inc. */ 45 | #define SDMMC_CIS_ABOCOM_SDW11G { NULL, NULL, NULL, NULL } 46 | #define SDMMC_PRODUCT_ABOCOM_SDW11G 0xac02 47 | 48 | /* Atheros */ 49 | #define SDMMC_CIS_ATHEROS_AR6001_8 { NULL, NULL, NULL, NULL } 50 | #define SDMMC_PRODUCT_ATHEROS_AR6001_8 0x0108 51 | #define SDMMC_CIS_ATHEROS_AR6001_9 { NULL, NULL, NULL, NULL } 52 | #define SDMMC_PRODUCT_ATHEROS_AR6001_9 0x0109 53 | #define SDMMC_CIS_ATHEROS_AR6001_a { NULL, NULL, NULL, NULL } 54 | #define SDMMC_PRODUCT_ATHEROS_AR6001_a 0x010a 55 | #define SDMMC_CIS_ATHEROS_AR6001_b { NULL, NULL, NULL, NULL } 56 | #define SDMMC_PRODUCT_ATHEROS_AR6001_b 0x010b 57 | 58 | /* C-guys, Inc. */ 59 | #define SDMMC_CIS_CGUYS_TIACX100 { NULL, NULL, NULL, NULL } 60 | #define SDMMC_PRODUCT_CGUYS_TIACX100 0x0001 61 | #define SDMMC_CIS_CGUYS_SDFMRADIO2 { NULL, NULL, NULL, NULL } 62 | #define SDMMC_PRODUCT_CGUYS_SDFMRADIO2 0x0005 63 | #define SDMMC_CIS_CGUYS_SDFMRADIO { NULL, NULL, NULL, NULL } 64 | #define SDMMC_PRODUCT_CGUYS_SDFMRADIO 0x5544 65 | 66 | /* Globalsat Technology Co. */ 67 | #define SDMMC_CIS_GLOBALSAT_SD501 { NULL, NULL, NULL, NULL } 68 | #define SDMMC_PRODUCT_GLOBALSAT_SD501 0xf501 69 | 70 | /* MediaTek Inc. */ 71 | #define SDMMC_CIS_MEDIATEK_S2YWLAN { NULL, NULL, NULL, NULL } 72 | #define SDMMC_PRODUCT_MEDIATEK_S2YWLAN 0x5911 73 | 74 | /* Spectec Computer Co., Ltd */ 75 | #define SDMMC_CIS_SPECTEC_SDW820 { NULL, NULL, NULL, NULL } 76 | #define SDMMC_PRODUCT_SPECTEC_SDW820 0x2128 77 | 78 | /* SyChip Inc. */ 79 | #define SDMMC_CIS_SYCHIP_WLAN6060SD { NULL, NULL, NULL, NULL } 80 | #define SDMMC_PRODUCT_SYCHIP_WLAN6060SD 0x0002 81 | 82 | /* Toshiba */ 83 | #define SDMMC_CIS_TOSHIBA_SDBTCARD1 { NULL, NULL, NULL, NULL } 84 | #define SDMMC_PRODUCT_TOSHIBA_SDBTCARD1 0x0001 85 | #define SDMMC_CIS_TOSHIBA_SDBTCARD2 { NULL, NULL, NULL, NULL } 86 | #define SDMMC_PRODUCT_TOSHIBA_SDBTCARD2 0x0002 87 | #define SDMMC_CIS_TOSHIBA_SDBTCARD3 { NULL, NULL, NULL, NULL } 88 | #define SDMMC_PRODUCT_TOSHIBA_SDBTCARD3 0x0003 89 | 90 | /* Socket Communications, Inc. */ 91 | #define SDMMC_CIS_SOCKETCOM_SDSCANNER { NULL, NULL, NULL, NULL } 92 | #define SDMMC_PRODUCT_SOCKETCOM_SDSCANNER 0x005e 93 | #define SDMMC_CIS_SOCKETCOM_BTCARD { NULL, NULL, NULL, NULL } 94 | #define SDMMC_PRODUCT_SOCKETCOM_BTCARD 0x00c5 95 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmcreg.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmcreg.h,v 1.11 2016/05/05 11:01:08 kettenis Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | #ifndef _SDMMCREG_H_ 20 | #define _SDMMCREG_H_ 21 | 22 | #include 23 | #include 24 | 25 | /* MMC commands */ /* response type */ 26 | #define MMC_GO_IDLE_STATE 0 /* R0 */ 27 | #define MMC_SEND_OP_COND 1 /* R3 */ 28 | #define MMC_ALL_SEND_CID 2 /* R2 */ 29 | #define MMC_SET_RELATIVE_ADDR 3 /* R1 */ 30 | #define MMC_SWITCH 6 /* R1B */ 31 | #define MMC_SELECT_CARD 7 /* R1 */ 32 | #define MMC_SEND_EXT_CSD 8 /* R1 */ 33 | #define MMC_SEND_CSD 9 /* R2 */ 34 | #define MMC_STOP_TRANSMISSION 12 /* R1B */ 35 | #define MMC_SEND_STATUS 13 /* R1 */ 36 | #define MMC_SET_BLOCKLEN 16 /* R1 */ 37 | #define MMC_READ_BLOCK_SINGLE 17 /* R1 */ 38 | #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ 39 | #define MMC_SET_BLOCK_COUNT 23 /* R1 */ 40 | #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ 41 | #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ 42 | #define MMC_APP_CMD 55 /* R1 */ 43 | 44 | /* SD commands */ /* response type */ 45 | #define SD_SEND_RELATIVE_ADDR 3 /* R6 */ 46 | #define SD_SEND_SWITCH_FUNC 6 /* R1 */ 47 | #define SD_SEND_IF_COND 8 /* R7 */ 48 | 49 | /* SD application commands */ /* response type */ 50 | #define SD_APP_SET_BUS_WIDTH 6 /* R1 */ 51 | #define SD_APP_OP_COND 41 /* R3 */ 52 | #define SD_APP_SEND_SCR 51 /* R1 */ 53 | 54 | /* OCR bits */ 55 | #define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */ 56 | #define MMC_OCR_ACCESS_MODE_MASK 0x60000000 /* bits 30:29 */ 57 | #define MMC_OCR_SECTOR_MODE (1<<30) 58 | #define MMC_OCR_BYTE_MODE (1<<29) 59 | #define MMC_OCR_3_5V_3_6V (1<<23) 60 | #define MMC_OCR_3_4V_3_5V (1<<22) 61 | #define MMC_OCR_3_3V_3_4V (1<<21) 62 | #define MMC_OCR_3_2V_3_3V (1<<20) 63 | #define MMC_OCR_3_1V_3_2V (1<<19) 64 | #define MMC_OCR_3_0V_3_1V (1<<18) 65 | #define MMC_OCR_2_9V_3_0V (1<<17) 66 | #define MMC_OCR_2_8V_2_9V (1<<16) 67 | #define MMC_OCR_2_7V_2_8V (1<<15) 68 | #define MMC_OCR_2_6V_2_7V (1<<14) 69 | #define MMC_OCR_2_5V_2_6V (1<<13) 70 | #define MMC_OCR_2_4V_2_5V (1<<12) 71 | #define MMC_OCR_2_3V_2_4V (1<<11) 72 | #define MMC_OCR_2_2V_2_3V (1<<10) 73 | #define MMC_OCR_2_1V_2_2V (1<<9) 74 | #define MMC_OCR_2_0V_2_1V (1<<8) 75 | #define MMC_OCR_1_65V_1_95V (1<<7) 76 | 77 | #define SD_OCR_SDHC_CAP (1<<30) 78 | #define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */ 79 | 80 | /* R1 response type bits */ 81 | #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ 82 | #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ 83 | 84 | /* 48-bit response decoding (32 bits w/o CRC) */ 85 | #define MMC_R1(resp) ((resp)[0]) 86 | #define MMC_R3(resp) ((resp)[0]) 87 | #define SD_R6(resp) ((resp)[0]) 88 | 89 | /* RCA argument and response */ 90 | #define MMC_ARG_RCA(rca) ((rca) << 16) 91 | #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) 92 | 93 | /* bus width argument */ 94 | #define SD_ARG_BUS_WIDTH_1 0 95 | #define SD_ARG_BUS_WIDTH_4 2 96 | 97 | /* EXT_CSD fields */ 98 | #define EXT_CSD_BUS_WIDTH 183 /* WO */ 99 | #define EXT_CSD_HS_TIMING 185 /* R/W */ 100 | #define EXT_CSD_REV 192 /* RO */ 101 | #define EXT_CSD_STRUCTURE 194 /* RO */ 102 | #define EXT_CSD_CARD_TYPE 196 /* RO */ 103 | #define EXT_CSD_SEC_COUNT 212 /* RO */ 104 | 105 | /* EXT_CSD field definitions */ 106 | #define EXT_CSD_CMD_SET_NORMAL (1U << 0) 107 | #define EXT_CSD_CMD_SET_SECURE (1U << 1) 108 | #define EXT_CSD_CMD_SET_CPSECURE (1U << 2) 109 | 110 | /* EXT_CSD_HS_TIMING */ 111 | #define EXT_CSD_HS_TIMING_BC 0 112 | #define EXT_CSD_HS_TIMING_HS 1 113 | #define EXT_CSD_HS_TIMING_HS200 2 114 | #define EXT_CSD_HS_TIMING_HS400 3 115 | 116 | /* EXT_CSD_BUS_WIDTH */ 117 | #define EXT_CSD_BUS_WIDTH_1 0 118 | #define EXT_CSD_BUS_WIDTH_4 1 119 | #define EXT_CSD_BUS_WIDTH_8 2 120 | #define EXT_CSD_BUS_WIDTH_4_DDR 5 121 | #define EXT_CSD_BUS_WIDTH_8_DDR 6 122 | 123 | /* EXT_CSD_CARD_TYPE */ 124 | /* The only currently valid values for this field are 0x01, 0x03, 0x07, 125 | * 0x0B and 0x0F. */ 126 | #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) 127 | #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) 128 | #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) 129 | #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) 130 | #define EXT_CSD_CARD_TYPE_26M 0x01 131 | #define EXT_CSD_CARD_TYPE_52M 0x03 132 | #define EXT_CSD_CARD_TYPE_52M_V18 0x07 133 | #define EXT_CSD_CARD_TYPE_52M_V12 0x0b 134 | #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f 135 | 136 | /* MMC_SWITCH access mode */ 137 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 138 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ 139 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ 140 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 141 | 142 | /* MMC R2 response (CSD) */ 143 | #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 144 | #define MMC_CSD_CSDVER_1_0 1 145 | #define MMC_CSD_CSDVER_2_0 2 146 | #define MMC_CSD_CSDVER_EXT_CSD 3 147 | #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 148 | #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ 149 | #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ 150 | #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ 151 | #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ 152 | #define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */ 153 | #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 154 | #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 155 | #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ 156 | (MMC_CSD_C_SIZE_MULT((resp))+2)) 157 | #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 158 | 159 | /* MMC v1 R2 response (CID) */ 160 | #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) 161 | #define MMC_CID_PNM_V1_CPY(resp, pnm) \ 162 | do { \ 163 | (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 164 | (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 165 | (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 166 | (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 167 | (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 168 | (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 169 | (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ 170 | (pnm)[7] = '\0'; \ 171 | } while (0) 172 | #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) 173 | #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) 174 | #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) 175 | 176 | /* MMC v2 R2 response (CID) */ 177 | #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) 178 | #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) 179 | #define MMC_CID_PNM_V2_CPY(resp, pnm) \ 180 | do { \ 181 | (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 182 | (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 183 | (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 184 | (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 185 | (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 186 | (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 187 | (pnm)[6] = '\0'; \ 188 | } while (0) 189 | #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) 190 | 191 | /* SD R2 response (CSD) */ 192 | #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 193 | #define SD_CSD_CSDVER_1_0 0 194 | #define SD_CSD_CSDVER_2_0 1 195 | #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 196 | #define SD_CSD_TAAC_1_5_MSEC 0x26 197 | #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 198 | #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 199 | #define SD_CSD_SPEED_25_MHZ 0x32 200 | #define SD_CSD_SPEED_50_MHZ 0x5a 201 | #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) 202 | #define SD_CSD_CCC_BASIC (1 << 0) /* basic */ 203 | #define SD_CSD_CCC_BR (1 << 2) /* block read */ 204 | #define SD_CSD_CCC_BW (1 << 4) /* block write */ 205 | #define SD_CSD_CCC_ERACE (1 << 5) /* erase */ 206 | #define SD_CSD_CCC_WP (1 << 6) /* write protection */ 207 | #define SD_CSD_CCC_LC (1 << 7) /* lock card */ 208 | #define SD_CSD_CCC_AS (1 << 8) /*application specific*/ 209 | #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */ 210 | #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */ 211 | #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 212 | #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) 213 | #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) 214 | #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) 215 | #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) 216 | #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 217 | #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ 218 | (SD_CSD_C_SIZE_MULT((resp))+2)) 219 | #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) 220 | #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 221 | #define SD_CSD_V2_BL_LEN 0x9 /* 512 */ 222 | #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) 223 | #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) 224 | #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) 225 | #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) 226 | #define SD_CSD_VDD_RW_CURR_100mA 0x7 227 | #define SD_CSD_VDD_RW_CURR_80mA 0x6 228 | #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 229 | #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) 230 | #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ 231 | #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ 232 | #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) 233 | #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 234 | #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 235 | #define SD_CSD_RW_BL_LEN_2G 0xa 236 | #define SD_CSD_RW_BL_LEN_1G 0x9 237 | #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) 238 | #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) 239 | #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) 240 | #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) 241 | #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) 242 | #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) 243 | 244 | /* SD R2 response (CID) */ 245 | #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) 246 | #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) 247 | #define SD_CID_PNM_CPY(resp, pnm) \ 248 | do { \ 249 | (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 250 | (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 251 | (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 252 | (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 253 | (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 254 | (pnm)[5] = '\0'; \ 255 | } while (0) 256 | #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) 257 | #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) 258 | #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) 259 | 260 | /* SCR (SD Configuration Register) */ 261 | #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4) 262 | #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */ 263 | #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4) 264 | #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */ 265 | #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */ 266 | #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */ 267 | #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1) 268 | #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3) 269 | #define SCR_SD_SECURITY_NONE 0 /* no security */ 270 | #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */ 271 | #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */ 272 | #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4) 273 | #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */ 274 | #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */ 275 | #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1) 276 | #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4) 277 | #define SCR_SD_SPEC4(scr) MMC_RSP_BITS((scr), 42, 1) 278 | #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 8) 279 | #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1) 280 | #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1) 281 | #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32) 282 | 283 | /* Status of Switch Function */ 284 | #define SFUNC_STATUS_GROUP(status, group) \ 285 | (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16)) 286 | 287 | #define SD_ACCESS_MODE_SDR12 0 288 | #define SD_ACCESS_MODE_SDR25 1 289 | #define SD_ACCESS_MODE_SDR50 2 290 | #define SD_ACCESS_MODE_SDR104 3 291 | #define SD_ACCESS_MODE_DDR50 4 292 | 293 | /* Might be slow, but it should work on big and little endian systems. */ 294 | #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len)) 295 | static __inline int 296 | __bitfield(u_int32_t *src, int start, int len) 297 | { 298 | u_int8_t *sp; 299 | u_int32_t dst, mask; 300 | int shift, bs, bc; 301 | 302 | if (start < 0 || len < 0 || len > 32) 303 | return 0; 304 | 305 | dst = 0; 306 | mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX; 307 | shift = 0; 308 | 309 | while (len > 0) { 310 | sp = (u_int8_t *)src + start / 8; 311 | bs = start % 8; 312 | bc = 8 - bs; 313 | if (bc > len) 314 | bc = len; 315 | dst |= (*sp++ >> bs) << shift; 316 | shift += bc; 317 | start += bc; 318 | len -= bc; 319 | } 320 | 321 | dst &= mask; 322 | return (int)dst; 323 | } 324 | 325 | #endif 326 | -------------------------------------------------------------------------------- /Sinetek-rtsx/sdmmcvar.h: -------------------------------------------------------------------------------- 1 | /* $OpenBSD: sdmmcvar.h,v 1.26 2016/05/05 11:01:08 kettenis Exp $ */ 2 | 3 | /* 4 | * Copyright (c) 2006 Uwe Stuehler 5 | * 6 | * Permission to use, copy, modify, and distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | */ 18 | 19 | #ifndef _SDMMCVAR_H_ 20 | #define _SDMMCVAR_H_ 21 | 22 | #include 23 | 24 | #include "sdmmcchip.h" 25 | #include "sdmmcreg.h" 26 | 27 | #define sdmmc_softc rtsx_softc 28 | 29 | extern char * DEVNAME(struct sdmmc_softc *); 30 | 31 | #define DETACH_FORCE 0x01 /* force detachment; hardware gone */ 32 | #define SET(t, f) ((t) |= (f)) 33 | #define ISSET(t, f) ((t) & (f)) 34 | #define CLR(t, f) ((t) &= ~(f)) 35 | 36 | struct sdmmc_csd { 37 | int csdver; /* CSD structure format */ 38 | int mmcver; /* MMC version (for CID format) */ 39 | int capacity; /* total number of sectors */ 40 | int sector_size; /* sector size in bytes */ 41 | int read_bl_len; /* block length for reads */ 42 | int ccc; /* Card Command Class for SD */ 43 | /* ... */ 44 | }; 45 | 46 | struct sdmmc_cid { 47 | int mid; /* manufacturer identification number */ 48 | int oid; /* OEM/product identification number */ 49 | char pnm[8]; /* product name (MMC v1 has the longest) */ 50 | int rev; /* product revision */ 51 | int psn; /* product serial number */ 52 | int mdt; /* manufacturing date */ 53 | }; 54 | 55 | struct sdmmc_scr { 56 | int sd_spec; 57 | int bus_width; 58 | }; 59 | 60 | typedef u_int32_t sdmmc_response[4]; 61 | 62 | struct sdmmc_softc; 63 | 64 | struct sdmmc_task { 65 | void (*func)(void *arg); 66 | void *arg; 67 | int onqueue; 68 | struct sdmmc_softc *sc; 69 | TAILQ_ENTRY(sdmmc_task) next; 70 | }; 71 | 72 | #define sdmmc_init_task(xtask, xfunc, xarg) do { \ 73 | (xtask)->func = (xfunc); \ 74 | (xtask)->arg = (xarg); \ 75 | (xtask)->onqueue = 0; \ 76 | (xtask)->sc = NULL; \ 77 | } while (0) 78 | 79 | #define sdmmc_task_pending(xtask) ((xtask)->onqueue) 80 | 81 | struct sdmmc_command { 82 | struct sdmmc_task c_task; /* task queue entry */ 83 | u_int16_t c_opcode; /* SD or MMC command index */ 84 | u_int32_t c_arg; /* SD/MMC command argument */ 85 | sdmmc_response c_resp; /* response buffer */ 86 | // bus_dmamap_t c_dmamap; 87 | void *c_data; /* buffer to send or read into */ 88 | int c_datalen; /* length of data buffer */ 89 | int c_blklen; /* block length */ 90 | int c_flags; /* see below */ 91 | #define SCF_ITSDONE 0x0001 /* command is complete */ 92 | #define SCF_CMD(flags) ((flags) & 0x00f0) 93 | #define SCF_CMD_AC 0x0000 94 | #define SCF_CMD_ADTC 0x0010 95 | #define SCF_CMD_BC 0x0020 96 | #define SCF_CMD_BCR 0x0030 97 | #define SCF_CMD_READ 0x0040 /* read command (data expected) */ 98 | #define SCF_RSP_BSY 0x0100 99 | #define SCF_RSP_136 0x0200 100 | #define SCF_RSP_CRC 0x0400 101 | #define SCF_RSP_IDX 0x0800 102 | #define SCF_RSP_PRESENT 0x1000 103 | /* response types */ 104 | #define SCF_RSP_R0 0 /* none */ 105 | #define SCF_RSP_R1 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 106 | #define SCF_RSP_R1B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 107 | #define SCF_RSP_R2 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136) 108 | #define SCF_RSP_R3 (SCF_RSP_PRESENT) 109 | #define SCF_RSP_R4 (SCF_RSP_PRESENT) 110 | #define SCF_RSP_R5 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 111 | #define SCF_RSP_R5B (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY) 112 | #define SCF_RSP_R6 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 113 | #define SCF_RSP_R7 (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX) 114 | int c_error; /* errno value on completion */ 115 | 116 | /* Host controller owned fields for data xfer in progress */ 117 | int c_resid; /* remaining I/O */ 118 | u_char *c_buf; /* remaining data */ 119 | }; 120 | 121 | /* 122 | * Decoded PC Card 16 based Card Information Structure (CIS), 123 | * per card (function 0) and per function (1 and greater). 124 | */ 125 | struct sdmmc_cis { 126 | u_int16_t manufacturer; 127 | #define SDMMC_VENDOR_INVALID 0xffff 128 | u_int16_t product; 129 | #define SDMMC_PRODUCT_INVALID 0xffff 130 | u_int8_t function; 131 | #define SDMMC_FUNCTION_INVALID 0xff 132 | u_char cis1_major; 133 | u_char cis1_minor; 134 | char cis1_info_buf[256]; 135 | char *cis1_info[4]; 136 | }; 137 | 138 | /* 139 | * Structure describing either an SD card I/O function or a SD/MMC 140 | * memory card from a "stack of cards" that responded to CMD2. For a 141 | * combo card with one I/O function and one memory card, there will be 142 | * two of these structures allocated. Each card slot has such a list 143 | * of sdmmc_function structures. 144 | */ 145 | struct sdmmc_function { 146 | /* common members */ 147 | struct sdmmc_softc *sc; /* card slot softc */ 148 | u_int16_t rca; /* relative card address */ 149 | int flags; 150 | #define SFF_ERROR 0x0001 /* function is poo; ignore it */ 151 | #define SFF_SDHC 0x0002 /* SD High Capacity card */ 152 | STAILQ_ENTRY(sdmmc_function) sf_list; 153 | /* SD card I/O function members */ 154 | int number; /* I/O function number or -1 */ 155 | struct device *child; /* function driver */ 156 | struct sdmmc_cis cis; /* decoded CIS */ 157 | /* SD/MMC memory card members */ 158 | struct sdmmc_csd csd; /* decoded CSD value */ 159 | struct sdmmc_cid cid; /* decoded CID value */ 160 | sdmmc_response raw_cid; /* temp. storage for decoding */ 161 | struct sdmmc_scr scr; /* decoded SCR value */ 162 | }; 163 | 164 | /* 165 | * Structure describing a single SD/MMC/SDIO card slot. 166 | */ 167 | // XXX 168 | 169 | /* 170 | * Attach devices at the sdmmc bus. 171 | */ 172 | //struct sdmmc_attach_args { 173 | // struct scsi_link *scsi_link; /* XXX */ 174 | // struct sdmmc_function *sf; 175 | //}; 176 | 177 | //#define IPL_SDMMC IPL_BIO 178 | //#define splsdmmc() splbio() 179 | // 180 | //#define SDMMC_ASSERT_LOCKED(sc) \ 181 | //rw_assert_wrlock(&(sc)->sc_lock) 182 | 183 | void sdmmc_add_task(struct sdmmc_softc *, struct sdmmc_task *); 184 | void sdmmc_del_task(struct sdmmc_task *); 185 | 186 | struct sdmmc_function *sdmmc_function_alloc(struct sdmmc_softc *); 187 | void sdmmc_function_free(struct sdmmc_function *); 188 | int sdmmc_set_bus_power(struct sdmmc_softc *, u_int32_t, u_int32_t); 189 | int sdmmc_mmc_command(struct sdmmc_softc *, struct sdmmc_command *); 190 | int sdmmc_app_command(struct sdmmc_softc *, struct sdmmc_command *); 191 | void sdmmc_go_idle_state(struct sdmmc_softc *); 192 | int sdmmc_select_card(struct sdmmc_softc *, struct sdmmc_function *); 193 | int sdmmc_set_relative_addr(struct sdmmc_softc *, 194 | struct sdmmc_function *); 195 | int sdmmc_send_if_cond(struct sdmmc_softc *, uint32_t); 196 | 197 | //void sdmmc_intr_enable(struct sdmmc_function *); 198 | //void sdmmc_intr_disable(struct sdmmc_function *); 199 | //void *sdmmc_intr_establish(struct device *, int (*)(void *), 200 | // void *, const char *); 201 | //void sdmmc_intr_disestablish(void *); 202 | //void sdmmc_intr_task(void *); 203 | 204 | int sdmmc_io_enable(struct sdmmc_softc *); 205 | void sdmmc_io_scan(struct sdmmc_softc *); 206 | int sdmmc_io_init(struct sdmmc_softc *, struct sdmmc_function *); 207 | void sdmmc_io_attach(struct sdmmc_softc *); 208 | void sdmmc_io_detach(struct sdmmc_softc *); 209 | u_int8_t sdmmc_io_read_1(struct sdmmc_function *, int); 210 | u_int16_t sdmmc_io_read_2(struct sdmmc_function *, int); 211 | u_int32_t sdmmc_io_read_4(struct sdmmc_function *, int); 212 | int sdmmc_io_read_multi_1(struct sdmmc_function *, int, u_char *, int); 213 | void sdmmc_io_write_1(struct sdmmc_function *, int, u_int8_t); 214 | void sdmmc_io_write_2(struct sdmmc_function *, int, u_int16_t); 215 | void sdmmc_io_write_4(struct sdmmc_function *, int, u_int32_t); 216 | int sdmmc_io_write_multi_1(struct sdmmc_function *, int, u_char *, int); 217 | int sdmmc_io_function_ready(struct sdmmc_function *); 218 | int sdmmc_io_function_enable(struct sdmmc_function *); 219 | void sdmmc_io_function_disable(struct sdmmc_function *); 220 | 221 | int sdmmc_read_cis(struct sdmmc_function *, struct sdmmc_cis *); 222 | void sdmmc_print_cis(struct sdmmc_function *); 223 | void sdmmc_check_cis_quirks(struct sdmmc_function *); 224 | 225 | int sdmmc_mem_enable(struct sdmmc_softc *); 226 | void sdmmc_mem_scan(struct sdmmc_softc *); 227 | int sdmmc_mem_init(struct sdmmc_softc *, struct sdmmc_function *); 228 | int sdmmc_mem_read_block(struct sdmmc_function *, int, u_char *, size_t); 229 | int sdmmc_mem_write_block(struct sdmmc_function *, int, u_char *, size_t); 230 | 231 | #endif 232 | -------------------------------------------------------------------------------- /build/Debug/Sinetek-rtsx.kext/Contents/Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | BuildMachineOSBuild 6 | 16D32 7 | CFBundleDevelopmentRegion 8 | en 9 | CFBundleExecutable 10 | Sinetek-rtsx 11 | CFBundleIdentifier 12 | com.sinet3k.Sinetek-rtsx 13 | CFBundleInfoDictionaryVersion 14 | 6.0 15 | CFBundleName 16 | Sinetek-rtsx 17 | CFBundlePackageType 18 | KEXT 19 | CFBundleShortVersionString 20 | 1.0 21 | CFBundleSupportedPlatforms 22 | 23 | MacOSX 24 | 25 | CFBundleVersion 26 | 1 27 | DTCompiler 28 | com.apple.compilers.llvm.clang.1_0 29 | DTPlatformBuild 30 | 8C1002 31 | DTPlatformVersion 32 | GM 33 | DTSDKBuild 34 | 16C58 35 | DTSDKName 36 | macosx10.12 37 | DTXcode 38 | 0821 39 | DTXcodeBuild 40 | 8C1002 41 | IOKitPersonalities 42 | 43 | rtsx_softc 44 | 45 | CFBundleIdentifier 46 | com.sinet3k.Sinetek-rtsx 47 | IOClass 48 | rtsx_softc 49 | IOKitDebug 50 | 65535 51 | IOPCIMatch 52 | 0x522710EC 53 | IOProbeScore 54 | 1000 55 | IOProviderClass 56 | IOPCIDevice 57 | 58 | 59 | NSHumanReadableCopyright 60 | Copyright © 2017 sinetek. All rights reserved. 61 | OSBundleLibraries 62 | 63 | com.apple.iokit.IOPCIFamily 64 | 2.9 65 | com.apple.iokit.IOStorageFamily 66 | 2.1 67 | com.apple.kpi.bsd 68 | 16.4 69 | com.apple.kpi.iokit 70 | 16.4 71 | com.apple.kpi.libkern 72 | 16.4 73 | com.apple.kpi.mach 74 | 16.4 75 | com.apple.kpi.unsupported 76 | 8.0 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /build/Debug/Sinetek-rtsx.kext/Contents/MacOS/Sinetek-rtsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/philmb3487/Sinetek-rtsx/ee2cff796ecd038edfafa6a1d988c6b8e73af215/build/Debug/Sinetek-rtsx.kext/Contents/MacOS/Sinetek-rtsx -------------------------------------------------------------------------------- /build/Debug/Sinetek-rtsx.kext/Contents/_CodeSignature/CodeResources: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | files 6 | 7 | files2 8 | 9 | rules 10 | 11 | ^Resources/ 12 | 13 | ^Resources/.*\.lproj/ 14 | 15 | optional 16 | 17 | weight 18 | 1000 19 | 20 | ^Resources/.*\.lproj/locversion.plist$ 21 | 22 | omit 23 | 24 | weight 25 | 1100 26 | 27 | ^Resources/Base\.lproj/ 28 | 29 | weight 30 | 1010 31 | 32 | ^version.plist$ 33 | 34 | 35 | rules2 36 | 37 | .*\.dSYM($|/) 38 | 39 | weight 40 | 11 41 | 42 | ^(.*/)?\.DS_Store$ 43 | 44 | omit 45 | 46 | weight 47 | 2000 48 | 49 | ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ 50 | 51 | nested 52 | 53 | weight 54 | 10 55 | 56 | ^.* 57 | 58 | ^Info\.plist$ 59 | 60 | omit 61 | 62 | weight 63 | 20 64 | 65 | ^PkgInfo$ 66 | 67 | omit 68 | 69 | weight 70 | 20 71 | 72 | ^Resources/ 73 | 74 | weight 75 | 20 76 | 77 | ^Resources/.*\.lproj/ 78 | 79 | optional 80 | 81 | weight 82 | 1000 83 | 84 | ^Resources/.*\.lproj/locversion.plist$ 85 | 86 | omit 87 | 88 | weight 89 | 1100 90 | 91 | ^Resources/Base\.lproj/ 92 | 93 | weight 94 | 1010 95 | 96 | ^[^/]+$ 97 | 98 | nested 99 | 100 | weight 101 | 10 102 | 103 | ^embedded\.provisionprofile$ 104 | 105 | weight 106 | 20 107 | 108 | ^version\.plist$ 109 | 110 | weight 111 | 20 112 | 113 | 114 | 115 | 116 | -------------------------------------------------------------------------------- /build/Sinetek-rtsx.build/Debug/Sinetek-rtsx.build/DerivedSources/Sinetek-rtsx_info.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | extern kern_return_t _start(kmod_info_t *ki, void *data); 4 | extern kern_return_t _stop(kmod_info_t *ki, void *data); 5 | 6 | __attribute__((visibility("default"))) KMOD_EXPLICIT_DECL(com.sinet3k.Sinetek_rtsx, "1.0.0d1", _start, _stop) 7 | __private_extern__ kmod_start_func_t *_realmain = 0; 8 | __private_extern__ kmod_stop_func_t *_antimain = 0; 9 | __private_extern__ int _kext_apple_cc = __APPLE_CC__ ; 10 | -------------------------------------------------------------------------------- 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pamhxx{Sinetek-rtsx_info.c/Users/sinetek/Desktop/Sinetek-rtsx/build/Sinetek-rtsx.build/Debug/Sinetek-rtsx.build/DerivedSources/Sinetek-rtsx/Sinetek-rtsx_info.c -------------------------------------------------------------------------------- /build/Sinetek-rtsx.build/Debug/Sinetek-rtsx.build/Sinetek-rtsx-own-target-headers.hmap: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/philmb3487/Sinetek-rtsx/ee2cff796ecd038edfafa6a1d988c6b8e73af215/build/Sinetek-rtsx.build/Debug/Sinetek-rtsx.build/Sinetek-rtsx-own-target-headers.hmap -------------------------------------------------------------------------------- /build/Sinetek-rtsx.build/Debug/Sinetek-rtsx.build/Sinetek-rtsx-project-headers.hmap: -------------------------------------------------------------------------------- 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