├── OFDM_RX_802_11 ├── MY_SOURCES │ ├── icfo_known_coeff_rtl1.txt │ ├── icfo_known_coeff_rtl2.txt │ ├── ChEstEqu_lpre.txt │ ├── Synch_known_coeff_802_11.txt │ ├── Delay_reg.v │ ├── ML_tap.v │ ├── Interface_BB.v │ ├── Signed_Mult_tap.v │ ├── Delay2n.v │ ├── Acc_Sum.v │ ├── Appr_Mag.v │ ├── iCFO_Appr_Mag.v │ ├── Comp_Acc_Sum.v │ ├── DataSymDem.v │ ├── PhTrack_Est.v │ ├── Ch_buf.v │ ├── RemoveCP.v │ ├── FreComp_PhaseRotAcc.v │ ├── Phase_Acc.v │ ├── PhaseAddOffset.v │ ├── Signed_Correlator.v │ ├── Multiplierless_Correlator.v │ ├── Ch_EstEqu_tb.v │ ├── Freoff_Est_Comp.v │ ├── Coarse_Time_Synch.v │ ├── PhaseTrack_tb.v │ ├── Time_Synch.v │ ├── FFT.v │ ├── Fine_Time_Synch.v │ ├── FreComp.v │ ├── iCFO_EstComp.v │ ├── OFDM_RX_802_11.v │ ├── Synch_tb.v │ ├── Ch_EstEqu.v │ ├── PhaseTrack.v │ ├── Synch.v │ ├── OFDM_RX_tb.v │ └── iCFO_est.v ├── MATLAB │ ├── OFDM_RX_tb.m │ ├── OFDM_SYN_tb.m │ ├── SIM_thresold_Q.m │ ├── OFDM_ChEstEqu_tb.m │ ├── OFDM_RX_wr_dat_in.m │ ├── OFDM_PhaseTrack_tb.m │ ├── OFDM_ChEstEqu_wr_dat_in.m │ ├── OFDM_PhaseTrack_wr_dat_in.m │ ├── preamble_802_11.m │ └── pilots_802_11.m └── IPCORE │ ├── Ch_CmxMul.xco │ ├── mult.xco │ ├── Complex_Multiplier.xco │ ├── FreComp_PhaseRot.xco │ ├── FreComp_PhaseTrans.xco │ └── FFT_ipcore.xco ├── OFDM_TX_802_11 ├── MATLAB │ ├── OFDM_TX_tb.m │ ├── OFDM_TX_wr_dat_in.m │ ├── Pilots.m │ ├── preamble_802_11.m │ ├── pilots_802_11.m │ └── preamble_802_16.m ├── MY_SOURCES │ ├── Pilot_seq.txt │ ├── QAM16_Mod.v │ ├── QPSK_Mod.v │ ├── Pre.txt │ ├── Tx_Out.v │ ├── QAM64_Mod.v │ ├── OFDM_TX_802_11.v │ ├── Pilots_Insert.v │ ├── OFDM_TX_802_11_ppr_tb.v │ ├── IFFT_Mod.v │ ├── Pilots_Insert_tb.v │ ├── IFFT_Mod_tb.v │ ├── Tx_Out_tb.v │ └── OFDM_TX_tb.v ├── OFDM_TX_802_11.ucf └── IPCORE │ └── IFFT.xco └── README.md /OFDM_RX_802_11/MY_SOURCES/icfo_known_coeff_rtl1.txt: -------------------------------------------------------------------------------- 1 | 1 2 3 3 3 2 1 0 1 0 2 1 3 0 2 3 0 1 2 3 1 2 0 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https://raw.githubusercontent.com/phthinh/OFDM_802_11/HEAD/OFDM_RX_802_11/MATLAB/OFDM_RX_wr_dat_in.m -------------------------------------------------------------------------------- /OFDM_TX_802_11/MATLAB/OFDM_TX_wr_dat_in.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/phthinh/OFDM_802_11/HEAD/OFDM_TX_802_11/MATLAB/OFDM_TX_wr_dat_in.m -------------------------------------------------------------------------------- /OFDM_RX_802_11/MATLAB/OFDM_PhaseTrack_tb.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/phthinh/OFDM_802_11/HEAD/OFDM_RX_802_11/MATLAB/OFDM_PhaseTrack_tb.m -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/ChEstEqu_lpre.txt: -------------------------------------------------------------------------------- 1 | 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 -------------------------------------------------------------------------------- /OFDM_RX_802_11/MATLAB/OFDM_ChEstEqu_wr_dat_in.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/phthinh/OFDM_802_11/HEAD/OFDM_RX_802_11/MATLAB/OFDM_ChEstEqu_wr_dat_in.m -------------------------------------------------------------------------------- /OFDM_RX_802_11/MATLAB/OFDM_PhaseTrack_wr_dat_in.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/phthinh/OFDM_802_11/HEAD/OFDM_RX_802_11/MATLAB/OFDM_PhaseTrack_wr_dat_in.m -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Synch_known_coeff_802_11.txt: -------------------------------------------------------------------------------- 1 | 1 2 2 3 3 0 1 1 1 1 3 2 2 3 3 2 0 0 3 0 0 1 0 2 0 1 1 0 2 2 0 1 0 3 2 0 0 2 3 3 2 0 2 3 2 2 1 2 2 0 1 1 0 0 1 3 3 3 3 2 1 1 0 0 -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/Pilot_seq.txt: -------------------------------------------------------------------------------- 1 | 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 0 0 -------------------------------------------------------------------------------- /OFDM_TX_802_11/MATLAB/Pilots.m: -------------------------------------------------------------------------------- 1 | function [Pil] = Pilots(NDS) 2 | Pil = zeros(8,NDS); 3 | init = [0 0 1 1 1 1 1 1 1 1 1]; 4 | 5 | for ii = 1:1:NDS, 6 | Wk = init(11); 7 | Pil(1,ii)=1-2*(1-Wk); 8 | Pil(2,ii)=1-2*(1-Wk); 9 | Pil(6,ii)=1-2*(1-Wk); 10 | Pil(8,ii)=1-2*(1-Wk); 11 | 12 | Pil(3,ii)=1-2*Wk; 13 | Pil(4,ii)=1-2*Wk; 14 | Pil(5,ii)=1-2*Wk; 15 | Pil(7,ii)=1-2*Wk; 16 | init = [xor(init(9),Wk) init(1:10)]; 17 | end 18 | 19 | Pil = Pil ./ sqrt(2); -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Delay_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:07:38 04/18/2012 7 | // Design Name: 8 | // Module Name: Delay_reg 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Delay_reg #(parameter WIDTH = 32)( 22 | input clk,rst, 23 | input ena, 24 | input [WIDTH - 1:0] dat_in, 25 | output reg [WIDTH - 1:0] dat_out 26 | ); 27 | 28 | always @(posedge clk) begin 29 | if(rst) dat_out <= {WIDTH{1'b0}}; 30 | else if (ena) dat_out <= dat_in; 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/ML_tap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:02:39 04/18/2012 7 | // Design Name: 8 | // Module Name: ML_tap 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ML_tap #(parameter WIDTH =17)( 22 | input [WIDTH-1:0] ML_value1, ML_value2, 23 | input [ 1:0] known_coeff, 24 | output reg [WIDTH-1:0] ML_out 25 | ); 26 | 27 | always @(*) begin 28 | case (known_coeff) 29 | 2'b00: ML_out = 0; 30 | 2'b01: ML_out = ML_value1; // * 0.5 31 | 2'b10: ML_out = ML_value2; // * 1 32 | default: ML_out = 0; 33 | endcase 34 | end 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MATLAB/preamble_802_11.m: -------------------------------------------------------------------------------- 1 | short_sym = zeros(64,1); 2 | short_sym (5) = -1.472 - 1i*1.472; 3 | short_sym (9) = -1.472 - 1i*1.472; 4 | short_sym (13)= 1.472 + 1i*1.472; 5 | short_sym (17)= 1.472 + 1i*1.472; 6 | short_sym (21)= 1.472 + 1i*1.472; 7 | short_sym (25)= 1.472 + 1i*1.472; 8 | short_sym (41)= 1.472 + 1i*1.472; 9 | 10 | short_sym (45)= -1.472 - 1i*1.472; 11 | short_sym (49)= 1.472 + 1i*1.472; 12 | short_sym (53)= -1.472 - 1i*1.472; 13 | short_sym (57)= -1.472 - 1i*1.472; 14 | short_sym (61)= 1.472 + 1i*1.472; 15 | 16 | Tshort = ifft(short_sym,64); 17 | short_pre = [Tshort(49:64).' Tshort.' Tshort(49:64).' Tshort.']; 18 | %short_pre = short_pre ./ max(short_pre); 19 | long_sym = [0 1 -1 -1 1 1 -1 1 -1 1 -1 -1 -1 -1 -1 1 1 -1 -1 1 -1 1 -1 1 1 1 1 ... 20 | 0 0 0 0 0 0 0 0 0 0 0 ... 21 | 1 1 -1 -1 1 1 -1 1 -1 1 1 1 1 1 1 -1 -1 1 1 -1 1 -1 1 1 1 1 ].'; 22 | Tlong = ifft(long_sym,64); 23 | 24 | long_pre = [Tlong(33:64).' Tlong.' Tlong.']; 25 | %long_pre = long_pre ./ max(long_pre); -------------------------------------------------------------------------------- /OFDM_TX_802_11/MATLAB/preamble_802_11.m: -------------------------------------------------------------------------------- 1 | short_sym = zeros(64,1); 2 | short_sym (5) = -1.472 - 1i*1.472; 3 | short_sym (9) = -1.472 - 1i*1.472; 4 | short_sym (13)= 1.472 + 1i*1.472; 5 | short_sym (17)= 1.472 + 1i*1.472; 6 | short_sym (21)= 1.472 + 1i*1.472; 7 | short_sym (25)= 1.472 + 1i*1.472; 8 | short_sym (41)= 1.472 + 1i*1.472; 9 | 10 | short_sym (45)= -1.472 - 1i*1.472; 11 | short_sym (49)= 1.472 + 1i*1.472; 12 | short_sym (53)= -1.472 - 1i*1.472; 13 | short_sym (57)= -1.472 - 1i*1.472; 14 | short_sym (61)= 1.472 + 1i*1.472; 15 | 16 | Tshort = ifft(short_sym,64); 17 | short_pre = [Tshort(49:64).' Tshort.' Tshort(49:64).' Tshort.']; 18 | %short_pre = short_pre ./ max(short_pre); 19 | long_sym = [0 1 -1 -1 1 1 -1 1 -1 1 -1 -1 -1 -1 -1 1 1 -1 -1 1 -1 1 -1 1 1 1 1 ... 20 | 0 0 0 0 0 0 0 0 0 0 0 ... 21 | 1 1 -1 -1 1 1 -1 1 -1 1 1 1 1 1 1 -1 -1 1 1 -1 1 -1 1 1 1 1 ].'; 22 | Tlong = ifft(long_sym,64); 23 | 24 | long_pre = [Tlong(33:64).' Tlong.' Tlong.']; 25 | %long_pre = long_pre ./ max(long_pre); -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Interface_BB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:14:13 06/21/2013 7 | // Design Name: 8 | // Module Name: Interface_BB 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Interface_BB( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, // DAT_I_Im[31:16] DAT_I_Re[15:0] in format 5.11 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output [31:0] DAT_O, // DAT_O_Im[31:16] DAT_O_Re[15:0] in format 5.11 28 | output CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | assign DAT_O = DAT_I; 34 | assign WE_O = WE_I; 35 | assign STB_O = STB_I; 36 | assign CYC_O = CYC_I; 37 | assign ACK_O = ACK_I; 38 | endmodule 39 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MATLAB/pilots_802_11.m: -------------------------------------------------------------------------------- 1 | a =[ 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 ... 2 | 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 ... 3 | 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 0 0 0 0 ... 4 | 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 ... 5 | 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 1 1 ... 6 | 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 ... 7 | 1 1 1 1 1 1 1 ]; 8 | 9 | p_n =[ 1 1 1 1 -1 -1 -1 1 -1 -1 -1 -1 1 1 -1 1 -1 -1 1 1 ... 10 | -1 1 1 -1 1 1 1 1 1 1 -1 1 1 1 -1 1 1 -1 -1 1 ... 11 | 1 1 -1 1 -1 -1 -1 1 -1 1 -1 -1 1 -1 -1 1 1 1 1 1 ... 12 | -1 -1 1 1 -1 -1 1 -1 1 -1 1 1 -1 -1 -1 1 1 -1 -1 -1 ... 13 | -1 1 -1 -1 1 -1 1 1 1 1 -1 1 -1 1 -1 1 -1 -1 -1 -1 ... 14 | -1 1 -1 1 1 -1 1 -1 1 1 1 -1 -1 1 -1 -1 -1 1 1 1 ... 15 | -1 -1 -1 -1 -1 -1 -1 ]; 16 | 17 | P =[1; -1; 1; 1]; 18 | 19 | pils= repmat(P,1,length(p_n)) .* repmat(p_n, length(P),1); 20 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MATLAB/pilots_802_11.m: -------------------------------------------------------------------------------- 1 | a =[ 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 ... 2 | 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 ... 3 | 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 0 0 0 0 ... 4 | 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 ... 5 | 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 1 1 ... 6 | 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 ... 7 | 1 1 1 1 1 1 1 ]; 8 | 9 | p_n =[ 1 1 1 1 -1 -1 -1 1 -1 -1 -1 -1 1 1 -1 1 -1 -1 1 1 ... 10 | -1 1 1 -1 1 1 1 1 1 1 -1 1 1 1 -1 1 1 -1 -1 1 ... 11 | 1 1 -1 1 -1 -1 -1 1 -1 1 -1 -1 1 -1 -1 1 1 1 1 1 ... 12 | -1 -1 1 1 -1 -1 1 -1 1 -1 1 1 -1 -1 -1 1 1 -1 -1 -1 ... 13 | -1 1 -1 -1 1 -1 1 1 1 1 -1 1 -1 1 -1 1 -1 -1 -1 -1 ... 14 | -1 1 -1 1 1 -1 1 -1 1 1 1 -1 -1 1 -1 -1 -1 1 1 1 ... 15 | -1 -1 -1 -1 -1 -1 -1 ]; 16 | 17 | P =[1; -1; 1; 1]; 18 | 19 | pils= repmat(P,1,length(p_n)) .* repmat(p_n, length(P),1); 20 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Signed_Mult_tap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:02:39 04/18/2012 7 | // Design Name: 8 | // Module Name: ML_tap 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Signed_Mult_tap( 22 | input [1:0] rxin, //[1] :signed bit of imaginary part, [0] :signed bit of real part, 23 | input [1:0] preamble, //[1] :signed bit of imaginary part, [0] :signed bit of real part, 24 | output [1:0] mult_out_Re, mult_out_Im 25 | ); 26 | 27 | wire cmp1_Re = (rxin[0] == preamble[0]); 28 | wire cmp2_Re = (rxin[1] == preamble[1]); 29 | 30 | assign mult_out_Re[0] = (cmp1_Re == cmp2_Re); 31 | assign mult_out_Re[1] = ~(cmp1_Re | cmp2_Re); 32 | 33 | wire cmp1_Im = (rxin[1] == preamble[0]); 34 | wire cmp2_Im = (rxin[0] == preamble[1]); 35 | 36 | assign mult_out_Im[0] = ~( cmp1_Im == cmp2_Im); 37 | assign mult_out_Im[1] = ((~cmp1_Im) & cmp2_Im); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Delay2n.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:22:04 04/15/2012 7 | // Design Name: 8 | // Module Name: Delay64 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Delay2n #(parameter WIDTH = 32, D = 64, B = 6)( 22 | input clk, rst, ena, 23 | input [WIDTH-1:0] dat_in, 24 | output [WIDTH-1:0] dat_out 25 | ); 26 | reg [WIDTH-1:0] dat_ram [D-1:0]; 27 | reg [B-1:0] adr_cnt; 28 | reg dat_val; 29 | assign dat_out = (dat_val)? dat_ram[adr_cnt]: 0; 30 | //integer cnt; 31 | always@ (posedge clk)begin 32 | if(rst) begin 33 | adr_cnt <= 0; 34 | //for (cnt = 0; cnt < D; cnt = cnt+1) dat_ram[cnt] <= 0; 35 | end 36 | else if (ena) begin 37 | dat_ram[adr_cnt] <= dat_in; 38 | adr_cnt <= adr_cnt +1'b1; 39 | end 40 | end 41 | always@ (posedge clk)begin 42 | if(rst) dat_val <= 1'b0; 43 | else if (adr_cnt == {B{1'b1}}) dat_val <= 1'b1; 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Acc_Sum.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:26:36 04/15/2012 7 | // Design Name: 8 | // Module Name: Acc_Sum 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Acc_Sum( 22 | input clk,rst, 23 | input ena, 24 | input [16:0] a, 25 | input [16:0] a_d, 26 | output signed [23:0] sum_out 27 | ); 28 | 29 | reg [16:0] ia, ia_d; 30 | always @(posedge clk) 31 | begin 32 | if (rst) begin 33 | ia <= 17'd0; 34 | ia_d <= 17'd0; 35 | end 36 | else if(ena) begin 37 | ia <= a; 38 | ia_d <= a_d; 39 | end 40 | end 41 | 42 | reg [23:0] sum_reg; 43 | always @(posedge clk) 44 | begin 45 | if (rst) sum_reg <= 24'd0; 46 | else if(ena) sum_reg <= mov_sum; 47 | end 48 | 49 | wire signed [17:0] delay_sub = $signed({1'b0,ia}) - $signed({1'b0,ia_d}); 50 | wire signed [23:0] mov_sum = $signed(sum_reg) + $signed({{6{delay_sub[17]}},delay_sub}); 51 | 52 | assign sum_out = mov_sum; 53 | endmodule 54 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Appr_Mag.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:24:42 04/21/2012 7 | // Design Name: 8 | // Module Name: Appr_Mag 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Appr_Mag #(parameter WIDTH = 16)( 22 | input clk, rst, ena, 23 | input [WIDTH-1:0] real_in, imag_in, 24 | output [WIDTH:0] mag, 25 | output val 26 | 27 | ); 28 | 29 | reg [WIDTH-1:0] real_abs, imag_abs; 30 | reg ena_abs; 31 | always@(posedge clk) 32 | begin 33 | if(rst) begin 34 | ena_abs <= 1'b0; 35 | real_abs <= 0; 36 | imag_abs <= 0; 37 | end 38 | else if(ena) begin 39 | ena_abs <= 1'b1; 40 | real_abs <= (real_in[WIDTH-1])? (~real_in + 1'b1): real_in; 41 | imag_abs <= (imag_in[WIDTH-1])? (~imag_in + 1'b1): imag_in; 42 | end 43 | else ena_abs <= 1'b0; 44 | end 45 | 46 | assign mag = (real_abs > imag_abs)? (real_abs + (imag_abs>>1)): (imag_abs + (real_abs>>1)); 47 | assign val = ena_abs; 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/iCFO_Appr_Mag.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:33:35 09/21/2012 7 | // Design Name: 8 | // Module Name: Appr_Mag 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module iCFO_Appr_Mag #(parameter WIDTH = 16)( 22 | input clk, rst, ena, 23 | input [WIDTH-1:0] real_in, imag_in, 24 | output [WIDTH:0] mag, 25 | output val 26 | 27 | ); 28 | 29 | reg [WIDTH-1:0] real_abs, imag_abs; 30 | reg ena_abs; 31 | always@(posedge clk) 32 | begin 33 | if(rst) begin 34 | ena_abs <= 1'b0; 35 | real_abs <= 0; 36 | imag_abs <= 0; 37 | end 38 | else if(ena) begin 39 | ena_abs <= 1'b1; 40 | real_abs <= (real_in[WIDTH-1])? (~real_in + 1'b1): real_in; 41 | imag_abs <= (imag_in[WIDTH-1])? (~imag_in + 1'b1): imag_in; 42 | end 43 | else ena_abs <= 1'b0; 44 | end 45 | 46 | assign mag = (real_abs > imag_abs)? (real_abs + (imag_abs>>1)): (imag_abs + (real_abs>>1)); 47 | assign val = ena_abs; 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Comp_Acc_Sum.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:50:06 05/09/2012 7 | // Design Name: 8 | // Module Name: Comp_Acc_Sum 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Comp_Acc_Sum #(parameter WIDTH = 23)( 22 | input clk,rst, 23 | input ena, 24 | input [15:0] a_Re, a_Im, 25 | input [15:0] a_d_Re, a_d_Im, 26 | output signed [WIDTH-1:0] sum_out_Im, sum_out_Re 27 | ); 28 | 29 | reg [15:0] ia_Re, ia_Im, ia_d_Re, ia_d_Im; 30 | always @(posedge clk) 31 | begin 32 | if (rst) begin 33 | ia_Re <= 16'd0; 34 | ia_Im <= 16'd0; 35 | ia_d_Re <= 16'd0; 36 | ia_d_Im <= 16'd0; 37 | end 38 | else if(ena) begin 39 | ia_Re <= a_Re; 40 | ia_Im <= a_Im; 41 | ia_d_Re <= a_d_Re; 42 | ia_d_Im <= a_d_Im; 43 | end 44 | end 45 | 46 | reg [2*WIDTH-1:0] sum_reg; 47 | always @(posedge clk) 48 | begin 49 | if (rst) sum_reg <= {(2*WIDTH){1'b0}}; 50 | else if(ena) sum_reg <= {sum_out_Im, sum_out_Re}; 51 | end 52 | 53 | assign sum_out_Re = $signed(sum_reg[WIDTH-1:0]) + $signed({{(WIDTH-16){ia_Re[15]}},ia_Re}) - $signed({{(WIDTH-16){ia_d_Re[15]}},ia_d_Re}); 54 | assign sum_out_Im = $signed(sum_reg[2*WIDTH-1:WIDTH]) + $signed({{(WIDTH-16){ia_Im[15]}},ia_Im}) - $signed({{(WIDTH-16){ia_d_Im[15]}},ia_d_Im}); 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/DataSymDem.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:30:23 03/29/2012 7 | // Design Name: 8 | // Module Name: DataSymDem 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module DataSymDem( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output reg [7:0] DAT_O, 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | wire out_halt = STB_O & (~ACK_I); 34 | wire ena = (CYC_I) & STB_I & WE_I; 35 | assign ACK_O = ena &(~out_halt); 36 | 37 | reg CYC_I_pp; 38 | always @(posedge CLK_I or negedge RST_I) 39 | begin 40 | if (RST_I) CYC_I_pp <= 1'b0; 41 | else CYC_I_pp <= CYC_I; 42 | end 43 | 44 | 45 | wire [15:0] QPSK_Im = DAT_I[31:16]; 46 | wire [15:0] QPSK_Re = DAT_I[15:0]; 47 | reg [1:0] bits_dem; 48 | reg bits_dem_val; 49 | always @(posedge CLK_I) 50 | begin 51 | if(RST_I) begin 52 | bits_dem <= 2'b0; 53 | bits_dem_val <= 1'b0; 54 | end 55 | else if (~out_halt) begin 56 | if(ena) begin 57 | bits_dem[1] <= ~QPSK_Im[15]; 58 | bits_dem[0] <= ~QPSK_Re[15]; 59 | bits_dem_val <= 1'b1; 60 | end 61 | else bits_dem_val <= 1'b0; 62 | end 63 | end 64 | 65 | 66 | always @(posedge CLK_I) 67 | begin 68 | if(RST_I) begin 69 | STB_O <= 1'b0; 70 | DAT_O <= 32'b0; 71 | end 72 | else if(~out_halt) begin 73 | DAT_O <= {6'd0, bits_dem}; 74 | STB_O <= bits_dem_val; 75 | end 76 | end 77 | 78 | always @(posedge CLK_I) 79 | begin 80 | if(RST_I) CYC_O <= 1'b0; 81 | else if ((CYC_I) & bits_dem_val) CYC_O <= 1'b1; 82 | else if ((~CYC_I) & (~STB_O)) CYC_O <= 1'b0; 83 | end 84 | 85 | assign WE_O = STB_O; 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/IPCORE/Ch_CmxMul.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Wed May 08 06:37:24 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:cmpy:5.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Complex_Multiplier xilinx.com:ip:cmpy:5.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET aclken=true 43 | CSET aportwidth=16 44 | CSET aresetn=true 45 | CSET atuserwidth=1 46 | CSET bportwidth=16 47 | CSET btuserwidth=1 48 | CSET component_name=Ch_CmxMul 49 | CSET ctrltuserwidth=1 50 | CSET flowcontrol=NonBlocking 51 | CSET hasatlast=false 52 | CSET hasatuser=false 53 | CSET hasbtlast=false 54 | CSET hasbtuser=false 55 | CSET hasctrltlast=false 56 | CSET hasctrltuser=false 57 | CSET latencyconfig=Automatic 58 | CSET minimumlatency=6 59 | CSET multtype=Use_Mults 60 | CSET optimizegoal=Resources 61 | CSET outputwidth=33 62 | CSET outtlastbehv=Null 63 | CSET roundmode=Truncate 64 | # END Parameters 65 | # BEGIN Extra information 66 | MISC pkg_timestamp=2011-06-21T06:39:44.000Z 67 | # END Extra information 68 | GENERATE 69 | # CRC: f4f5db2b 70 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # IEEE 802.11 OFDM-based transceiver system 2 | This repos contains the implementation of IEEE 802.11 (i.e. Wifi) OFDM-based transceiver system. This is stored in 2 separate parts, i.e. transmitter (TX) and receiver (RX). 3 | 4 | Each part includes implementation files stored in **MY_SOURCES** and **IPCORE**, and simulation golden model stored in **MATLAB**. 5 | 6 | **MY_SOURCES** contains hdl files using verilog to implement the sub-modules (*.v) of systems and to make a testbench files (*_tb.v). There are some pre-computed cofficient sets defined by the standard (e.g. preamble) are stored in '*.txt' files. OFDM_TX_802_11.v and OFDM_RX_802_11.v are the top modules of transmitter and receiver systems, respectively. 7 | 8 | **IPCORE** contains the configured files of IPCores instantiated by impelemented systems. The IPCores are generated using ISE Design Tool. 9 | 10 | **MATLAB** contains matlab files that simulate 802.11 OFDM signals as a golden model for implementation. The matlab files are also used to generate test vector for testbench and verify the output files from testbench. 11 | 12 | #### Publications 13 | 14 | This implementation is presented in the paper below: 15 | 16 | - T. H. Pham, S. A. Fahmy and I. V. McLoughlin, "An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration," in IEEE Access, vol. 5, pp. 21002-21015, 2017. 17 | [doi: 10.1109/ACCESS.2017.2756914](http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8051045&isnumber=7859429) 18 | 19 | If you use this for research, please cite the paper: 20 | ``` 21 | @ARTICLE{Pham2017, 22 | author={T. H. Pham and S. A. Fahmy and I. V. McLoughlin}, 23 | journal={IEEE Access}, 24 | title={An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration}, 25 | year={2017}, 26 | volume={5}, 27 | number={}, 28 | pages={21002-21015}, 29 | keywords={Baseband;Field programmable gate arrays;Hardware;OFDM;Program processors;Standards;OFDM;cognitive radio;open wireless architecture;radio transceivers;reconfigurable architectures}, 30 | doi={10.1109/ACCESS.2017.2756914}, 31 | ISSN={}, 32 | month={},} 33 | ``` -------------------------------------------------------------------------------- /OFDM_TX_802_11/OFDM_TX_802_11.ucf: -------------------------------------------------------------------------------- 1 | 2 | #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2013/05/03 3 | NET "CLK_I" TNM_NET = CLK_I; 4 | TIMESPEC TS_CLK_I = PERIOD "CLK_I" 20 ns HIGH 50%; 5 | NET "ACK_I" OFFSET = IN 20 ns VALID 20 ns BEFORE "CLK_I" RISING; 6 | NET "CYC_I" OFFSET = IN 20 ns VALID 20 ns BEFORE "CLK_I" RISING; 7 | NET "RST_I" OFFSET = IN 20 ns VALID 20 ns BEFORE "CLK_I" RISING; 8 | NET "STB_I" OFFSET = IN 20 ns VALID 20 ns BEFORE "CLK_I" RISING; 9 | NET "WE_I" OFFSET = IN 20 ns VALID 20 ns BEFORE "CLK_I" RISING; 10 | INST "DAT_I<0>" TNM = DAT_I; 11 | INST "DAT_I<1>" TNM = DAT_I; 12 | #INST "DAT_I<2>" TNM = DAT_I; 13 | #INST "DAT_I<3>" TNM = DAT_I; 14 | #INST "DAT_I<4>" TNM = DAT_I; 15 | #INST "DAT_I<5>" TNM = DAT_I; 16 | TIMEGRP "DAT_I" OFFSET = IN 20 ns VALID 20 ns BEFORE "CLK_I" RISING; 17 | NET "ACK_O" OFFSET = OUT 20 ns AFTER "CLK_I"; 18 | NET "CYC_O" OFFSET = OUT 20 ns AFTER "CLK_I"; 19 | NET "STB_O" OFFSET = OUT 20 ns AFTER "CLK_I"; 20 | NET "WE_O" OFFSET = OUT 20 ns AFTER "CLK_I"; 21 | INST "DAT_O<0>" TNM = DAT_O; 22 | INST "DAT_O<1>" TNM = DAT_O; 23 | INST "DAT_O<2>" TNM = DAT_O; 24 | INST "DAT_O<3>" TNM = DAT_O; 25 | INST "DAT_O<4>" TNM = DAT_O; 26 | INST "DAT_O<5>" TNM = DAT_O; 27 | INST "DAT_O<6>" TNM = DAT_O; 28 | INST "DAT_O<7>" TNM = DAT_O; 29 | INST "DAT_O<8>" TNM = DAT_O; 30 | INST "DAT_O<9>" TNM = DAT_O; 31 | INST "DAT_O<10>" TNM = DAT_O; 32 | INST "DAT_O<11>" TNM = DAT_O; 33 | INST "DAT_O<12>" TNM = DAT_O; 34 | INST "DAT_O<13>" TNM = DAT_O; 35 | INST "DAT_O<14>" TNM = DAT_O; 36 | INST "DAT_O<15>" TNM = DAT_O; 37 | INST "DAT_O<16>" TNM = DAT_O; 38 | INST "DAT_O<17>" TNM = DAT_O; 39 | INST "DAT_O<18>" TNM = DAT_O; 40 | INST "DAT_O<19>" TNM = DAT_O; 41 | INST "DAT_O<20>" TNM = DAT_O; 42 | INST "DAT_O<21>" TNM = DAT_O; 43 | INST "DAT_O<22>" TNM = DAT_O; 44 | INST "DAT_O<23>" TNM = DAT_O; 45 | INST "DAT_O<24>" TNM = DAT_O; 46 | INST "DAT_O<25>" TNM = DAT_O; 47 | INST "DAT_O<26>" TNM = DAT_O; 48 | INST "DAT_O<27>" TNM = DAT_O; 49 | INST "DAT_O<28>" TNM = DAT_O; 50 | INST "DAT_O<29>" TNM = DAT_O; 51 | INST "DAT_O<30>" TNM = DAT_O; 52 | INST "DAT_O<31>" TNM = DAT_O; 53 | TIMEGRP "DAT_O" OFFSET = OUT 20 ns AFTER "CLK_I"; 54 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/IPCORE/mult.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Wed May 08 06:30:05 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:mult_gen:11.2 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Multiplier xilinx.com:ip:mult_gen:11.2 40 | # END Select 41 | # BEGIN Parameters 42 | CSET ccmimp=Distributed_Memory 43 | CSET clockenable=true 44 | CSET component_name=mult 45 | CSET constvalue=129 46 | CSET internaluser=0 47 | CSET multiplier_construction=Use_Mults 48 | CSET multtype=Parallel_Multiplier 49 | CSET optgoal=Speed 50 | CSET outputwidthhigh=33 51 | CSET outputwidthlow=0 52 | CSET pipestages=3 53 | CSET portatype=Unsigned 54 | CSET portawidth=17 55 | CSET portbtype=Unsigned 56 | CSET portbwidth=17 57 | CSET roundpoint=0 58 | CSET sclrcepriority=SCLR_Overrides_CE 59 | CSET syncclear=true 60 | CSET use_custom_output_width=false 61 | CSET userounding=false 62 | CSET zerodetect=false 63 | # END Parameters 64 | # BEGIN Extra information 65 | MISC pkg_timestamp=2011-06-21T06:26:54.000Z 66 | # END Extra information 67 | GENERATE 68 | # CRC: b6dfe1f5 69 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/IPCORE/Complex_Multiplier.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Wed May 08 06:28:44 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:cmpy:5.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Complex_Multiplier xilinx.com:ip:cmpy:5.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET aclken=false 43 | CSET aportwidth=16 44 | CSET aresetn=true 45 | CSET atuserwidth=1 46 | CSET bportwidth=16 47 | CSET btuserwidth=1 48 | CSET component_name=Complex_Multiplier 49 | CSET ctrltuserwidth=1 50 | CSET flowcontrol=NonBlocking 51 | CSET hasatlast=false 52 | CSET hasatuser=false 53 | CSET hasbtlast=false 54 | CSET hasbtuser=false 55 | CSET hasctrltlast=false 56 | CSET hasctrltuser=false 57 | CSET latencyconfig=Automatic 58 | CSET minimumlatency=6 59 | CSET multtype=Use_Mults 60 | CSET optimizegoal=Resources 61 | CSET outputwidth=33 62 | CSET outtlastbehv=Null 63 | CSET roundmode=Truncate 64 | # END Parameters 65 | # BEGIN Extra information 66 | MISC pkg_timestamp=2011-06-21T06:39:44.000Z 67 | # END Extra information 68 | GENERATE 69 | # CRC: 6b04a28f 70 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/IPCORE/FreComp_PhaseRot.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Wed May 08 06:30:43 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:cordic:4.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT CORDIC xilinx.com:ip:cordic:4.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET architectural_configuration=Parallel 43 | CSET ce=true 44 | CSET coarse_rotation=true 45 | CSET compensation_scaling=Embedded_Multiplier 46 | CSET component_name=FreComp_PhaseRot 47 | CSET data_format=SignedFraction 48 | CSET functional_selection=Rotate 49 | CSET input_width=16 50 | CSET iterations=0 51 | CSET nd=true 52 | CSET output_width=16 53 | CSET phase_format=Radians 54 | CSET phase_output=false 55 | CSET pipelining_mode=Maximum 56 | CSET precision=0 57 | CSET rdy=true 58 | CSET register_inputs=true 59 | CSET register_outputs=true 60 | CSET round_mode=Truncate 61 | CSET sclr=true 62 | CSET x_out=true 63 | CSET y_out=true 64 | # END Parameters 65 | # BEGIN Extra information 66 | MISC pkg_timestamp=2011-06-21T06:27:35.000Z 67 | # END Extra information 68 | GENERATE 69 | # CRC: 1d70b83f 70 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/IPCORE/FreComp_PhaseTrans.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Wed May 08 06:31:59 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:cordic:4.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT CORDIC xilinx.com:ip:cordic:4.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET architectural_configuration=Word_Serial 43 | CSET ce=false 44 | CSET coarse_rotation=true 45 | CSET compensation_scaling=No_Scale_Compensation 46 | CSET component_name=FreComp_PhaseTrans 47 | CSET data_format=SignedFraction 48 | CSET functional_selection=Translate 49 | CSET input_width=16 50 | CSET iterations=0 51 | CSET nd=true 52 | CSET output_width=16 53 | CSET phase_format=Radians 54 | CSET phase_output=true 55 | CSET pipelining_mode=Maximum 56 | CSET precision=0 57 | CSET rdy=true 58 | CSET register_inputs=true 59 | CSET register_outputs=true 60 | CSET round_mode=Truncate 61 | CSET sclr=true 62 | CSET x_out=false 63 | CSET y_out=false 64 | # END Parameters 65 | # BEGIN Extra information 66 | MISC pkg_timestamp=2011-06-21T06:27:35.000Z 67 | # END Extra information 68 | GENERATE 69 | # CRC: 609f8d4c 70 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/PhTrack_Est.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:28:32 11/10/2012 7 | // Design Name: 8 | // Module Name: Ph_Est 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PhTrack_Est( 22 | input clk, rst, start, datin_val, 23 | input [15:0] datin_Re, //Q 3.13 (Q10.6) 24 | input [15:0] datin_Im, //Q 3.13 (Q10.6) 25 | input [1:0] alloc_vec, 26 | output[15:0] ph_Re, 27 | output[15:0] ph_Im, 28 | output reg ph_oval 29 | ); 30 | wire P_pos = (alloc_vec == 2'b01); // positve pilot 31 | wire P_neg = (alloc_vec == 2'b10); // negative pilot 32 | wire [15:0] Pdiff_Re = (P_pos)? datin_Re :(P_neg)? (~datin_Re +1'b1): 16'd0; //different phase between transmitted and received pilots 33 | wire [15:0] Pdiff_Im = (P_pos)? datin_Im :(P_neg)? (~datin_Im +1'b1): 16'd0; 34 | 35 | reg [17:0] Pacc_Re, Pacc_Im; 36 | 37 | always @(posedge clk) begin 38 | if (rst) begin Pacc_Re <= 18'd0; 39 | Pacc_Im <= 18'd0; 40 | end 41 | else if (start) begin Pacc_Re <= 18'd0; 42 | Pacc_Im <= 18'd0; 43 | end 44 | else if (datin_val &(P_pos|P_neg)) begin Pacc_Re <= Pacc_Re + {{2{Pdiff_Re[15]}},Pdiff_Re}; 45 | Pacc_Im <= Pacc_Im + {{2{Pdiff_Im[15]}},Pdiff_Im}; 46 | end 47 | end 48 | 49 | reg [1:0] P_cnt; 50 | always @(posedge clk) begin 51 | if (rst) P_cnt <= 2'b0; 52 | else if (start) P_cnt <= 2'b0; 53 | else if (datin_val &(P_pos|P_neg)) P_cnt <= P_cnt + 1'b1; 54 | end 55 | 56 | always @(posedge clk) begin 57 | if (rst) ph_oval <= 1'b0; 58 | else if ((P_cnt == 2'b11)& datin_val &(P_pos|P_neg)) ph_oval <= 1'b1; 59 | else ph_oval <= 1'b0; 60 | end 61 | 62 | assign ph_Re = Pacc_Re[17:2]; //Q3.13; (Q10.6) 63 | assign ph_Im = Pacc_Im[17:2]; //Q3.13; (Q10.6) 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Ch_buf.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:06:18 11/10/2012 7 | // Design Name: 8 | // Module Name: Ch_buf 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ch_buf( 22 | input clk, rst, ena, start, 23 | input [31:0] datin, 24 | input [7:0] rd_addr, 25 | output [31:0] datout, 26 | output reg [7:0] dat_cnt, 27 | output almostfull, 28 | output full 29 | ); 30 | 31 | reg [31:0] rx_buf_mem [0:199]; 32 | reg [7:0] rx_buf_wrcnt; //write pointer of rx buffer 33 | reg [7:0] datin_cnt; 34 | 35 | always@(posedge clk) begin 36 | if (rst) dat_cnt <=8'd0; 37 | else if (ena & (~full)) dat_cnt <= dat_cnt + 1'b1; 38 | else if (~ena) dat_cnt <=8'd0; 39 | end 40 | 41 | reg car_val; // used carriers in OFDM symbol 42 | always@(posedge clk) begin 43 | if (rst) car_val <=8'd0; 44 | else if (start) car_val <=8'd0; 45 | else if (ena) begin 46 | if (dat_cnt == 8'd0) car_val <= 1'd1; 47 | else if (dat_cnt == 8'd100) car_val <= 1'd0; 48 | else if (dat_cnt == 8'd155) car_val <= 1'd1; 49 | else if (dat_cnt == 8'd255) car_val <= 1'd0; 50 | end 51 | end 52 | 53 | 54 | always@(posedge clk) begin 55 | if (rst) rx_buf_wrcnt <= 8'd0; 56 | else if (start) rx_buf_wrcnt <= 8'd0; 57 | else if (~full) 58 | if (ena & car_val & (rx_buf_wrcnt == 8'd199)) begin 59 | rx_buf_wrcnt <= 8'd0; 60 | rx_buf_mem[rx_buf_wrcnt] <= datin; 61 | end 62 | else if (ena & car_val) begin 63 | rx_buf_wrcnt <= rx_buf_wrcnt + 1'b1; 64 | rx_buf_mem[rx_buf_wrcnt] <= datin; 65 | end 66 | end 67 | assign datout = rx_buf_mem[rd_addr]; 68 | assign almostfull = ena & car_val & (rx_buf_wrcnt == 8'd180); 69 | assign full = ena & car_val & (rx_buf_wrcnt == rd_addr) & (~(rx_buf_wrcnt == 8'd0)); 70 | endmodule 71 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/RemoveCP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:28:19 03/29/2012 7 | // Design Name: 8 | // Module Name: RemoveCP 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module RemoveCP( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | parameter LCP = 16; 34 | parameter NFFT = 64; 35 | 36 | reg [9:0] dat_cnt; 37 | reg CYC_I_pp; 38 | always @(posedge CLK_I or negedge RST_I) 39 | begin 40 | if (RST_I) CYC_I_pp <= 1'b1; 41 | else CYC_I_pp <= CYC_I; 42 | end 43 | 44 | wire inCP = dat_cnt < LCP; 45 | wire infrm = dat_cnt < NFFT+LCP; 46 | always @(posedge CLK_I or negedge RST_I) 47 | begin 48 | if (RST_I) begin 49 | dat_cnt <= 10'd0; 50 | DAT_O <= 32'd0; 51 | STB_O <= 1'b0; 52 | end 53 | else if(CYC_I& (~CYC_I_pp)) dat_cnt <= (STB_I)?10'd1:10'd0; 54 | else if (CYC_I & STB_I & WE_I) begin 55 | if (inCP) begin 56 | STB_O <= 1'b0; 57 | dat_cnt <= dat_cnt + 1'b1; 58 | end 59 | else if (dat_cnt == LCP) begin 60 | STB_O <= 1'b1; 61 | DAT_O <= DAT_I; 62 | dat_cnt <= dat_cnt + 1'b1; 63 | end 64 | else if (infrm) begin 65 | STB_O <= STB_I; 66 | DAT_O <= (ACK_I)? DAT_I: DAT_O; 67 | dat_cnt <= (ACK_I)? (dat_cnt == NFFT+LCP-1)? 10'd0: (dat_cnt + 1'b1): dat_cnt; 68 | end 69 | end 70 | else begin 71 | dat_cnt <= 10'd0; 72 | DAT_O <= 32'd0; 73 | STB_O <= 1'b0; 74 | end 75 | end 76 | 77 | always @(posedge CLK_I or negedge RST_I) 78 | begin 79 | if (RST_I) CYC_O <= 1'b0; 80 | else if(dat_cnt == LCP) CYC_O <= 1'b1; 81 | else if((~CYC_I) & (~STB_O)) CYC_O <= 1'b0; 82 | end 83 | 84 | assign ACK_O = STB_I & (ACK_I|(~STB_O)); 85 | assign WE_O = STB_O; 86 | endmodule 87 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MATLAB/preamble_802_16.m: -------------------------------------------------------------------------------- 1 | function [DL_preamble, UL_preamble, pre64, pre128, peven] = preamble_802_16() 2 | CP = 32; 3 | 4 | pall= ... 5 | [ 1-1i, 1-1i,-1-1i, 1+1i, 1-1i, 1-1i,-1+1i, 1-1i, 1-1i, 1-1i, ... 6 | 1+1i,-1-1i, 1+1i, 1+1i,-1-1i, 1+1i,-1-1i,-1-1i, 1-1i,-1+1i, ... 7 | 1-1i, 1-1i,-1-1i, 1+1i, 1-1i, 1-1i,-1+1i, 1-1i, 1-1i, 1-1i, ... 8 | 1+1i,-1-1i, 1+1i, 1+1i,-1-1i, 1+1i,-1-1i,-1-1i, 1-1i,-1+1i, ... 9 | 1-1i, 1-1i,-1-1i, 1+1i, 1-1i, 1-1i,-1+1i, 1-1i, 1-1i, 1-1i, ... 10 | 1+1i,-1-1i, 1+1i, 1+1i,-1-1i, 1+1i,-1-1i,-1-1i, 1-1i,-1+1i, ... 11 | 1+1i, 1+1i, 1-1i,-1+1i, 1+1i, 1+1i,-1-1i, 1+1i, 1+1i, 1+1i, ... 12 | -1+1i, 1-1i,-1+1i,-1+1i, 1-1i,-1+1i, 1-1i, 1-1i, 1+1i,-1-1i, ... 13 | -1-1i,-1-1i,-1+1i, 1-1i,-1-1i,-1-1i, 1+1i,-1-1i,-1-1i,-1-1i, ... 14 | 1-1i,-1+1i, 1-1i, 1-1i,-1+1i, 1-1i,-1+1i,-1+1i,-1-1i, 1+1i, ... 15 | 0+0i, ... 16 | -1-1i, 1+1i,-1+1i,-1+1i,-1-1i, 1+1i, 1+1i, 1+1i,-1-1i, ... 17 | 1+1i, 1-1i, 1-1i, 1-1i,-1+1i,-1+1i,-1+1i,-1+1i, 1-1i,-1-1i, ... 18 | -1-1i,-1+1i, 1-1i, 1+1i, 1+1i,-1+1i, 1-1i, 1-1i, 1-1i,-1+1i, ... 19 | 1-1i,-1-1i,-1-1i,-1-1i, 1+1i, 1+1i, 1+1i, 1+1i,-1-1i,-1+1i, ... 20 | -1+1i, 1+1i,-1-1i, 1-1i, 1-1i, 1+1i,-1-1i,-1-1i,-1-1i, 1+1i, ... 21 | -1-1i,-1+1i,-1+1i,-1+1i, 1-1i, 1-1i, 1-1i, 1-1i,-1+1i, 1+1i, ... 22 | 1+1i,-1-1i, 1+1i,-1+1i,-1+1i,-1-1i, 1+1i, 1+1i, 1+1i,-1-1i, ... 23 | 1+1i, 1-1i, 1-1i, 1-1i,-1+1i,-1+1i,-1+1i,-1+1i, 1-1i,-1-1i, ... 24 | -1-1i, 1-1i,-1+1i,-1-1i,-1-1i, 1-1i,-1+1i,-1+1i,-1+1i, 1-1i, ... 25 | -1+1i, 1+1i, 1+1i, 1+1i,-1-1i,-1-1i,-1-1i,-1-1i, 1+1i, 1-1i, 1-1i]; 26 | 27 | p4_64_p = zeros(1,100); 28 | p4_64_n = zeros(1,100); 29 | k=1:1:25; 30 | p4_64_p(4*k) = 2.*( conj(pall(4*k+101)) ); 31 | p4_64_n(101-4*k)= 2.*( conj(pall(101-4*k)) ); 32 | p4_64 = [0, p4_64_p, zeros(1, 55) p4_64_n]; 33 | %preall = [0, pall(102:201), zeros(1, 55) pall(1:100)]; 34 | pre64 = ifft(p4_64,256); 35 | 36 | 37 | peven_p = zeros(1,100); 38 | peven_n = zeros(1,100); 39 | k=1:1:50; 40 | peven_p(2*k) = sqrt(2).*( (pall(2*k+101)) ); 41 | peven_n(101-2*k)= sqrt(2).*( (pall(101-2*k)) ); 42 | peven = [0, peven_p, zeros(1, 55) peven_n]; 43 | pre128 = ifft(peven,256); 44 | 45 | DL_preamble = [pre64(256-CP+1:256), pre64, pre128(256-CP+1:256), pre128]; 46 | UL_preamble = [pre128(256-CP+1:256), pre128]; 47 | 48 | %chk = [ preall.', peven.', p4_64.']; 49 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/FreComp_PhaseRotAcc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:33:54 04/07/2012 7 | // Design Name: 8 | // Module Name: FreComp_PhaseRotAcc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module FreComp_PhaseRotAcc( 22 | input clk, 23 | input rst, 24 | input ld, 25 | input acc, 26 | input ce, 27 | input [15:0] phase_ld, 28 | input [15:0] phase_in, 29 | output [15:0] phase_out, 30 | output reg phase_out_rdy 31 | ); 32 | parameter L = 6; //log2(64) 33 | parameter Pi = 16'h648B; //pi in 3Q16 (format 3.13) 34 | parameter ifre_off = 16'h096D; //pre integer frequency offset in 3Q16 (format 3.13) = -2*pi*n_off / NFFT; 35 | //n_off is chosen -12 to limit integer frequency offset -14 : 18 normalized frequency offset 36 | 37 | //reg phase_out_rdy; 38 | 39 | reg signed [15:0] phase_in_lat; 40 | reg signed [15:0] phase_rot; 41 | 42 | wire signed [15:0] phase_rot_acc = phase_rot + phase_in_lat; 43 | wire signed [15:0] phase_rot_adj1 = ($signed(phase_rot_acc >>> 1) - $signed(Pi)) <<1; 44 | wire signed [15:0] phase_rot_adj2 = ($signed(phase_rot_acc >>> 1) + $signed(Pi)) <<1; 45 | wire acc_gt_pi = ($signed(phase_rot_acc) > $signed(Pi)); 46 | wire acc_lt_pi = ($signed(phase_rot_acc) < $signed(-Pi)); 47 | 48 | 49 | always @(posedge clk) 50 | begin 51 | if(rst) phase_in_lat <= 16'd0; 52 | else if (ld) phase_in_lat <= $signed(ifre_off) + ($signed(phase_in) >>> L); 53 | end 54 | 55 | always @(posedge clk) 56 | begin 57 | if(rst) begin 58 | phase_rot <= 16'd0; 59 | phase_out_rdy <= 1'b0; 60 | end 61 | else if (ce) begin 62 | if (ld) begin 63 | phase_rot <= $signed(phase_ld); 64 | phase_out_rdy <= 1'b1; 65 | end 66 | else if (acc) begin 67 | if (acc_gt_pi) phase_rot <= phase_rot_adj1; 68 | else if (acc_lt_pi) phase_rot <= phase_rot_adj2; 69 | else phase_rot <= phase_rot_acc; 70 | phase_out_rdy <= 1'b1; 71 | end 72 | else phase_out_rdy <= 1'b0; 73 | end 74 | end 75 | 76 | assign phase_out = phase_rot; 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Phase_Acc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:33:54 04/07/2012 7 | // Design Name: 8 | // Module Name: FreComp_PhaseRotAcc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Phase_Acc( 22 | input clk, 23 | input rst, 24 | input ld, 25 | input acc, 26 | input ce, 27 | input [15:0] phase_in, 28 | output [15:0] phase_out, 29 | output reg phase_out_rdy 30 | ); 31 | parameter L = 6; //log2(64) 32 | parameter Pi = 16'h648B; //pi in 3Q16 (format 3.13) 33 | parameter ifre_off = 16'h0FB5; //pre integer frequency offset in 3Q16 (format 3.13) = -2*pi*n_off / NFFT; 34 | //n_off is chosen -20 to limit integer frequency offset smaller than 18 normalized frequency offset 35 | reg signed [15:0] phase_in_lat; 36 | reg signed [15:0] phase_rot; 37 | 38 | wire signed [15:0] phase_rot_acc = phase_rot + phase_in_lat; 39 | wire signed [15:0] phase_rot_adj1 = ($signed(phase_rot_acc >>> 1) - $signed(Pi)) <<1; 40 | wire signed [15:0] phase_rot_adj2 = ($signed(phase_rot_acc >>> 1) + $signed(Pi)) <<1; 41 | wire acc_gt_pi = ($signed(phase_rot_acc) > $signed(Pi)); 42 | wire acc_lt_pi = ($signed(phase_rot_acc) < $signed(-Pi)); 43 | 44 | wire [15:0] phase_in_rd = phase_in + {1'b1, {L-1{1'b0}}}; // rounding -1 -> 0 when shift L bits 45 | 46 | always @(posedge clk) 47 | begin 48 | if(rst) phase_in_lat <= 16'd0; 49 | else if (ld) phase_in_lat <= $signed(phase_in_rd) >>> L; 50 | end 51 | 52 | always @(posedge clk) 53 | begin 54 | if(rst) begin 55 | phase_rot <= 16'd0; 56 | phase_out_rdy <= 1'b0; 57 | end 58 | else if (ce) begin 59 | if (ld) begin 60 | phase_rot <= $signed(phase_in_rd) >>> L; 61 | phase_out_rdy <= 1'b1; 62 | end 63 | else if (acc) begin 64 | if (acc_gt_pi) phase_rot <= phase_rot_adj1; 65 | else if (acc_lt_pi) phase_rot <= phase_rot_adj2; 66 | else phase_rot <= phase_rot_acc; 67 | phase_out_rdy <= 1'b1; 68 | end 69 | else phase_out_rdy <= 1'b0; 70 | end 71 | end 72 | 73 | assign phase_out = phase_rot; 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/IPCORE/IFFT.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Mon Apr 22 06:18:45 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:xfft:8.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Fast_Fourier_Transform xilinx.com:ip:xfft:8.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET aclken=false 43 | CSET aresetn=true 44 | CSET butterfly_type=use_luts 45 | CSET channels=1 46 | CSET complex_mult_type=use_mults_resources 47 | CSET component_name=IFFT 48 | CSET cyclic_prefix_insertion=true 49 | CSET data_format=fixed_point 50 | CSET implementation_options=pipelined_streaming_io 51 | CSET input_width=16 52 | CSET memory_options_data=block_ram 53 | CSET memory_options_hybrid=false 54 | CSET memory_options_phase_factors=block_ram 55 | CSET memory_options_reorder=block_ram 56 | CSET number_of_stages_using_block_ram_for_data_and_phase_factors=1 57 | CSET output_ordering=natural_order 58 | CSET ovflo=false 59 | CSET phase_factor_width=16 60 | CSET rounding_modes=truncation 61 | CSET run_time_configurable_transform_length=false 62 | CSET scaling_options=scaled 63 | CSET target_clock_frequency=250 64 | CSET target_data_throughput=50 65 | CSET throttle_scheme=nonrealtime 66 | CSET transform_length=64 67 | CSET xk_index=true 68 | # END Parameters 69 | # BEGIN Extra information 70 | MISC pkg_timestamp=2011-06-21T06:36:08.000Z 71 | # END Extra information 72 | GENERATE 73 | # CRC: 213252c1 74 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/IPCORE/FFT_ipcore.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Mon Jul 01 03:06:48 2013 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:xfft:8.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx240t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Fast_Fourier_Transform xilinx.com:ip:xfft:8.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET aclken=false 43 | CSET aresetn=true 44 | CSET butterfly_type=use_luts 45 | CSET channels=1 46 | CSET complex_mult_type=use_mults_resources 47 | CSET component_name=FFT_ipcore 48 | CSET cyclic_prefix_insertion=false 49 | CSET data_format=fixed_point 50 | CSET implementation_options=pipelined_streaming_io 51 | CSET input_width=16 52 | CSET memory_options_data=block_ram 53 | CSET memory_options_hybrid=false 54 | CSET memory_options_phase_factors=block_ram 55 | CSET memory_options_reorder=block_ram 56 | CSET number_of_stages_using_block_ram_for_data_and_phase_factors=0 57 | CSET output_ordering=natural_order 58 | CSET ovflo=false 59 | CSET phase_factor_width=16 60 | CSET rounding_modes=truncation 61 | CSET run_time_configurable_transform_length=false 62 | CSET scaling_options=scaled 63 | CSET target_clock_frequency=250 64 | CSET target_data_throughput=50 65 | CSET throttle_scheme=nonrealtime 66 | CSET transform_length=64 67 | CSET xk_index=true 68 | # END Parameters 69 | # BEGIN Extra information 70 | MISC pkg_timestamp=2011-06-21T06:36:08.000Z 71 | # END Extra information 72 | GENERATE 73 | # CRC: 58e50250 74 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/PhaseAddOffset.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:09:57 04/29/2012 7 | // Design Name: 8 | // Module Name: PhaseAddOffset 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PhaseAddOffset( 22 | input clk, 23 | input rst, 24 | input ld, 25 | input [15:0] phase_in, // phase in from phase translation in format 3.13 26 | output reg [15:0] phase_out, // phase offset out for compensating short symbol in format 3.13 27 | output reg phase_out_rdy 28 | ); 29 | parameter Pi = 16'h648B; //pi in 3Q16 (format 3.13) 30 | parameter ifre_off_L = 19'h25B30; //pre integer frequency offset * M=64 in 6Q19 (format 6.13) = -(2*pi*n_off / NFFT) * M; 31 | //n_off is chosen -12 to limit frequency offset -14:18 normalized frequency offset 32 | reg ld_pp; 33 | 34 | always @(posedge clk) 35 | begin 36 | if(rst) ld_pp <= 1'b0; 37 | else ld_pp <= ld; 38 | end 39 | 40 | wire signed [19:0] adj_phase_in; // adjusted phase in for pre-added integer frequency offset; = angle(P) - 2*pi*n_off * L / NFFT = phase_in + ifre_off 41 | // in format 7.13 42 | assign adj_phase_in = $signed({{3{phase_in[15]}}, phase_in}) + $signed(ifre_off_L); 43 | reg signed [22:0] phase; // in format 10.13 44 | wire signed [22:0] phase_adj1 = ($signed(phase >>> 1) - $signed(Pi)) <<1; 45 | wire signed [22:0] phase_adj2 = ($signed(phase >>> 1) + $signed(Pi)) <<1; 46 | 47 | reg phase_adj_run; 48 | always @(posedge clk) 49 | begin 50 | if(rst) begin 51 | phase <= 25'd0; 52 | phase_out_rdy <= 1'b0; 53 | phase_out <= 16'd0; 54 | phase_adj_run <= 1'b0; 55 | end 56 | else if (ld & (~ld_pp))begin 57 | phase <= $signed({adj_phase_in, 2'd0}) + $signed({{3{adj_phase_in[19]}}, adj_phase_in[19:1]}); //= (angle(P)/L + 2*pi*n_off / NFFT)*288 58 | phase_out_rdy <= 1'b0; 59 | phase_adj_run <= 1'b1; 60 | end 61 | else if ($signed(phase) > $signed(Pi)) phase <= phase_adj1; 62 | else if ($signed(phase) < $signed(-Pi)) phase <= phase_adj2; 63 | else if (phase_adj_run) begin 64 | phase_out <= phase[15:0]; 65 | phase_out_rdy <= 1'b1; 66 | phase_adj_run <= 1'b0; 67 | end 68 | else phase_out_rdy <= 1'b0; 69 | end 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/QAM16_Mod.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:01:15 12/04/2012 7 | // Design Name: 8 | // Module Name: QPSK_Mod 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define Qn3 16'h8692 22 | `define Qn1 16'hD786 23 | `define Qp1 16'h287A 24 | `define Qp3 16'h796E 25 | 26 | module QAM16_Mod( 27 | input CLK_I, RST_I, 28 | input [5:0] DAT_I, 29 | input CYC_I, WE_I, STB_I, 30 | output ACK_O, 31 | 32 | output reg [31:0] DAT_O, 33 | output reg CYC_O, STB_O, 34 | output WE_O, 35 | input ACK_I 36 | ); 37 | 38 | reg [3:0] idat; 39 | reg ival; 40 | wire out_halt, ena; 41 | 42 | reg [15:0] datout_Re, datout_Im; 43 | 44 | assign out_halt = STB_O & (~ACK_I); 45 | assign ena = CYC_I & STB_I & WE_I; 46 | assign ACK_O = ena &(~out_halt); 47 | 48 | 49 | 50 | always @(posedge CLK_I) begin 51 | if(RST_I) idat<= 4'b0000; 52 | else if(ACK_O) idat <= DAT_I[3:0]; 53 | end 54 | 55 | always @(posedge CLK_I) begin 56 | if(RST_I) ival <= 1'b0; 57 | else if(ena) ival <= 1'b1; 58 | else ival <= 1'b0; 59 | end 60 | 61 | always @(posedge CLK_I) 62 | begin 63 | if(RST_I) begin 64 | STB_O <= 1'b0; 65 | DAT_O <= 32'b0; 66 | end 67 | else if(ival & (~out_halt)) begin 68 | DAT_O <= {datout_Im, datout_Re}; 69 | STB_O <= 1'b1; 70 | end 71 | else if(~ival) begin 72 | STB_O <= 1'b0; 73 | end 74 | end 75 | 76 | reg icyc; 77 | always @(posedge CLK_I) 78 | begin 79 | if(RST_I) icyc <= 1'b0; 80 | else icyc <= CYC_I; 81 | end 82 | always @(posedge CLK_I) 83 | begin 84 | if(RST_I) CYC_O <= icyc; 85 | else CYC_O <= icyc; 86 | end 87 | 88 | assign WE_O = STB_O; 89 | 90 | always @(*) begin 91 | case (idat[3:2]) 92 | 2'b00 : datout_Im = `Qn3; 93 | 2'b10 : datout_Im = `Qn1; 94 | 2'b11 : datout_Im = `Qp1; 95 | 2'b01 : datout_Im = `Qp3; 96 | default: datout_Im = 16'd0; 97 | endcase 98 | end 99 | 100 | always @(*) begin 101 | case (idat[1:0]) 102 | 2'b00 : datout_Re = `Qn3; 103 | 2'b10 : datout_Re = `Qn1; 104 | 2'b11 : datout_Re = `Qp1; 105 | 2'b01 : datout_Re = `Qp3; 106 | default: datout_Re = 16'd0; 107 | endcase 108 | end 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/QPSK_Mod.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:01:15 12/04/2012 7 | // Design Name: 8 | // Module Name: QPSK_Mod 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module QPSK_Mod( 22 | input CLK_I, RST_I, 23 | input [5:0] DAT_I, 24 | input CYC_I, WE_I, STB_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | reg [1:0] idat; 34 | reg ival; 35 | wire out_halt, ena; 36 | 37 | wire [15:0] datout_Re, datout_Im; 38 | 39 | assign out_halt = STB_O & (~ACK_I); 40 | assign ena = CYC_I & STB_I & WE_I; 41 | assign ACK_O = ena &(~out_halt); 42 | 43 | 44 | 45 | always @(posedge CLK_I) begin 46 | if(RST_I) idat<= 2'b00; 47 | else if(ACK_O) idat <= DAT_I[1:0]; 48 | end 49 | 50 | always @(posedge CLK_I) begin 51 | if(RST_I) ival <= 1'b0; 52 | else if(ena) ival <= 1'b1; 53 | else ival <= 1'b0; 54 | end 55 | 56 | always @(posedge CLK_I) 57 | begin 58 | if(RST_I) begin 59 | STB_O <= 1'b0; 60 | DAT_O <= 32'b0; 61 | end 62 | else if(ival & (~out_halt)) begin 63 | DAT_O <= {datout_Im, datout_Re}; 64 | STB_O <= 1'b1; 65 | end 66 | else if(~ival) begin 67 | STB_O <= 1'b0; 68 | end 69 | end 70 | 71 | reg icyc; 72 | always @(posedge CLK_I) 73 | begin 74 | if(RST_I) icyc <= 1'b0; 75 | else icyc <= CYC_I; 76 | end 77 | always @(posedge CLK_I) 78 | begin 79 | if(RST_I) CYC_O <= icyc; 80 | else CYC_O <= icyc; 81 | end 82 | 83 | assign WE_O = STB_O; 84 | 85 | /* 86 | always @* begin 87 | case(idat) 88 | 2'b11: begin 89 | datout_Re <= 16'h7FFF; 90 | datout_Im <= 16'h7FFF; 91 | end 92 | 2'b10: begin 93 | datout_Re <= 16'h8001; 94 | datout_Im <= 16'h7FFF; 95 | end 96 | 2'b01: begin 97 | datout_Re <= 16'h7FFF; 98 | datout_Im <= 16'h8001; 99 | end 100 | 2'b00: begin 101 | datout_Re <= 16'h8001; 102 | datout_Im <= 16'h8001; 103 | end 104 | default: begin 105 | datout_Re <= 16'hxxxx; 106 | datout_Im <= 16'hxxxx; 107 | end 108 | endcase 109 | end 110 | */ 111 | assign datout_Im = (idat[1])?16'h5A82:16'hA57E; 112 | assign datout_Re = (idat[0])?16'h5A82:16'hA57E; 113 | endmodule 114 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/Pre.txt: -------------------------------------------------------------------------------- 1 | 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d 5e305e3 4def0c f5f3fe47 fe611246 bc7 fe611246 f5f3fe47 4def0c 5e305e3 ef0c004d fe47f5f3 1246fe61 bc70000 1246fe61 fe47f5f3 ef0c004d ec00 f3820193 f2730bbd f143f43d f91effa4 97a099c 2a0efb4 21ff066 1350fb84 2caf8c6 f598f848 fe3108e7 f42e0a86 f7a7ef33 faf8f8ad f36904ba 8000800 860f43 eb70fd1f 1ea0782 77e0322 611ee7d eb80020 ff7a06d4 3500c7c d97fb18 710f143 b3a07a8 fc6e02b4 f5670c65 e3a0517 f67ff58 1400 f099ff58 f1c60517 a990c65 39202b4 f4c607a8 f8f0f143 f269fb18 fcb00c7c 8606d4 f1480020 f9efee7d f8820322 fe160782 1490fd1f ff7a0f43 f8000800 c9704ba 508f8ad 859ef33 bd20a86 1cf08e7 a68f848 fd36f8c6 ecb0fb84 fde1f066 fd60efb4 f686099c 6e2ffa4 ebdf43d d8d0bbd c7e0193 ec00 f3820193 f2730bbd f143f43d f91effa4 97a099c 2a0efb4 21ff066 1350fb84 2caf8c6 f598f848 fe3108e7 f42e0a86 f7a7ef33 faf8f8ad f36904ba 8000800 860f43 eb70fd1f 1ea0782 77e0322 611ee7d eb80020 ff7a06d4 3500c7c d97fb18 710f143 b3a07a8 fc6e02b4 f5670c65 e3a0517 f67ff58 1400 f099ff58 f1c60517 a990c65 39202b4 f4c607a8 f8f0f143 f269fb18 fcb00c7c 8606d4 f1480020 f9efee7d f8820322 fe160782 1490fd1f ff7a0f43 f8000800 c9704ba 508f8ad 859ef33 bd20a86 1cf08e7 a68f848 fd36f8c6 ecb0fb84 fde1f066 fd60efb4 f686099c 6e2ffa4 ebdf43d d8d0bbd c7e0193 ec00 f3820193 f2730bbd f143f43d f91effa4 97a099c 2a0efb4 21ff066 1350fb84 2caf8c6 f598f848 fe3108e7 f42e0a86 f7a7ef33 faf8f8ad f36904ba 8000800 860f43 eb70fd1f 1ea0782 77e0322 611ee7d eb80020 ff7a06d4 3500c7c d97fb18 710f143 b3a07a8 fc6e02b4 f5670c65 e3a0517 f67ff58 -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Signed_Correlator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:02:55 04/15/2012 7 | // Design Name: 8 | // Module Name: Multiplierless_Correlator 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Signed_Correlator( 22 | input clk,rst, 23 | input ena, 24 | input [1:0] CR_in, //[1] :signed bit of imaginary part, [0] :signed bit of real part, 25 | output [6:0] CR_out_Re, CR_out_Im 26 | ); 27 | 28 | 29 | reg [1:0] Synch_known_coeff [63:0]; //[1] :signed bit of imaginary part, [0] :signed bit of real part, 30 | initial $readmemh("./MY_SOURCES/Synch_known_coeff_802_11.txt", Synch_known_coeff); 31 | 32 | 33 | wire [1:0] iCR_in = CR_in; 34 | wire iena = ena; 35 | 36 | //============================================= 37 | 38 | wire [1:0] tap_out_Re [63:0]; 39 | wire [1:0] tap_out_Im [63:0]; 40 | genvar ML_cnt; 41 | generate 42 | for (ML_cnt=0; ML_cnt < 64; ML_cnt = ML_cnt + 1) 43 | begin: ML_assign 44 | Signed_Mult_tap Signed_Mult_tap_ins( 45 | .rxin(iCR_in), //[1:0] 46 | .preamble(Synch_known_coeff[ML_cnt][1:0]), //[1:0] 47 | .mult_out_Re(tap_out_Re[ML_cnt]), //[1:0] 48 | .mult_out_Im(tap_out_Im[ML_cnt]) //[1:0] 49 | ); 50 | end 51 | endgenerate 52 | 53 | //============================================= 54 | wire [6:0] add_out_Re [63:0]; //Add 55 | wire [6:0] add_out_Im [63:0]; //Add 56 | 57 | assign add_out_Re[0] = {{5{tap_out_Re[0][1]}}, tap_out_Re[0]}; 58 | assign add_out_Im[0] = {{5{tap_out_Im[0][1]}}, tap_out_Im[0]}; 59 | 60 | wire [6:0] reg_out_Re [62:0]; //Add Register 61 | wire [6:0] reg_out_Im [62:0]; //Add Register 62 | 63 | genvar cnt; 64 | generate 65 | for (cnt=0; cnt < 63; cnt = cnt + 1) 66 | begin: AddCmpReg_ins 67 | Delay_reg #(.WIDTH(7)) CR_Re_D( 68 | .clk(clk), .rst(rst), .ena(iena), 69 | .dat_in(add_out_Re[cnt][6:0]), 70 | .dat_out(reg_out_Re[cnt][6:0]) 71 | ); 72 | 73 | Delay_reg #(.WIDTH(7)) CR_Im_D( 74 | .clk(clk), .rst(rst), .ena(iena), 75 | .dat_in(add_out_Im[cnt][6:0]), 76 | .dat_out(reg_out_Im[cnt][6:0]) 77 | ); 78 | 79 | assign add_out_Re[cnt+1] = reg_out_Re[cnt] + {{5{tap_out_Re[cnt+1][1]}}, tap_out_Re[cnt+1]}; 80 | assign add_out_Im[cnt+1] = reg_out_Im[cnt] + {{5{tap_out_Im[cnt+1][1]}}, tap_out_Im[cnt+1]}; 81 | end 82 | endgenerate 83 | 84 | 85 | assign CR_out_Re = add_out_Re[63][6:0]; 86 | assign CR_out_Im = add_out_Im[63][6:0]; 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/Tx_Out.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:05:30 12/04/2012 7 | // Design Name: 8 | // Module Name: Tx_Out 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Tx_Out( 22 | 23 | input CLK_I, RST_I, 24 | input [31:0] DAT_I, 25 | input CYC_I, WE_I, STB_I, 26 | output ACK_O, 27 | 28 | output reg [31:0] DAT_O, 29 | output reg CYC_O, STB_O, 30 | output WE_O, 31 | input ACK_I 32 | ); 33 | 34 | reg [31:0] Pre[0:319]; 35 | initial $readmemh("./MY_SOURCES/Pre.txt", Pre); 36 | 37 | reg [31:0] idat; 38 | reg ival; 39 | wire out_halt, ena; 40 | 41 | reg [8:0] pre_cnt; 42 | reg pre_ena; 43 | reg dat_sym_ena; 44 | 45 | assign out_halt = STB_O & (~ACK_I); 46 | assign ena = CYC_I & STB_I & WE_I; 47 | assign ACK_O = ena & (~out_halt) & (dat_sym_ena); 48 | 49 | 50 | always @(posedge CLK_I) begin 51 | if(RST_I) idat <= 32'd0; 52 | else if(ACK_O) idat <= DAT_I; 53 | end 54 | 55 | always @(posedge CLK_I) begin 56 | if(RST_I) ival <= 1'b0; 57 | else if(ena) ival <= 1'b1; 58 | else ival <= 1'b0; 59 | end 60 | 61 | reg icyc; 62 | always @(posedge CLK_I) 63 | begin 64 | if(RST_I) icyc <= 1'b0; 65 | else icyc <= CYC_I; 66 | end 67 | always @(posedge CLK_I) 68 | begin 69 | if(RST_I) CYC_O <= icyc; 70 | else CYC_O <= icyc; 71 | end 72 | 73 | always @(posedge CLK_I) 74 | begin 75 | if(RST_I) pre_cnt <= 9'd0; 76 | else if (CYC_I & (~icyc)) pre_cnt <= 9'd0; 77 | else if (icyc & (~out_halt) & (~(pre_cnt == 9'd320))) pre_cnt <= pre_cnt + 1'b1; 78 | end 79 | 80 | always @(posedge CLK_I) 81 | begin 82 | if(RST_I) pre_ena <= 1'b0; 83 | else if (CYC_I & (~icyc)) pre_ena <= 1'b1; 84 | else if (CYC_O & (pre_cnt == 9'd319)) pre_ena <= 1'b0; 85 | end 86 | 87 | always @(posedge CLK_I) 88 | begin 89 | if(RST_I) dat_sym_ena <= 1'b0; 90 | else if (CYC_I & (~icyc)) dat_sym_ena <= 1'b0; 91 | else if (CYC_O & (pre_cnt == 9'd318)) dat_sym_ena <= 1'b1; 92 | else if (~CYC_O) dat_sym_ena <= 1'b0; 93 | end 94 | 95 | always @(posedge CLK_I) 96 | begin 97 | if(RST_I) begin 98 | STB_O <= 1'b0; 99 | DAT_O <= 32'b0; 100 | end 101 | else if(pre_ena & (~out_halt)) begin 102 | DAT_O <= Pre[pre_cnt]; 103 | STB_O <= 1'b1; 104 | end 105 | else if(ival & (~out_halt)) begin 106 | DAT_O <= idat; 107 | STB_O <= 1'b1; 108 | end 109 | else if(~ival) begin 110 | STB_O <= 1'b0; 111 | end 112 | end 113 | 114 | assign WE_O = STB_O; 115 | endmodule 116 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/QAM64_Mod.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:39:14 04/09/2013 7 | // Design Name: 8 | // Module Name: QAM64_Mod 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define Qn7 16'h8001 22 | `define Qn5 16'h9D3F 23 | `define Qn3 16'hC2BF 24 | `define Qn1 16'hEC40 25 | `define Qp1 16'h13C0 26 | `define Qp3 16'h3B41 27 | `define Qp5 16'h62C1 28 | `define Qp7 16'h7FFF 29 | 30 | module QAM64_Mod( 31 | input CLK_I, RST_I, 32 | input [5:0] DAT_I, 33 | input CYC_I, WE_I, STB_I, 34 | output ACK_O, 35 | 36 | output reg [31:0] DAT_O, 37 | output reg CYC_O, STB_O, 38 | output WE_O, 39 | input ACK_I 40 | ); 41 | 42 | reg [5:0] idat; 43 | reg ival; 44 | wire out_halt, ena; 45 | 46 | reg [15:0] datout_Re, datout_Im; 47 | 48 | assign out_halt = STB_O & (~ACK_I); 49 | assign ena = CYC_I & STB_I & WE_I; 50 | assign ACK_O = ena &(~out_halt); 51 | 52 | 53 | 54 | always @(posedge CLK_I) begin 55 | if(RST_I) idat<= 6'b000000; 56 | else if(ACK_O) idat <= DAT_I; 57 | end 58 | 59 | always @(posedge CLK_I) begin 60 | if(RST_I) ival <= 1'b0; 61 | else if(ena) ival <= 1'b1; 62 | else ival <= 1'b0; 63 | end 64 | 65 | always @(posedge CLK_I) 66 | begin 67 | if(RST_I) begin 68 | STB_O <= 1'b0; 69 | DAT_O <= 32'b0; 70 | end 71 | else if(ival & (~out_halt)) begin 72 | DAT_O <= {datout_Im, datout_Re}; 73 | STB_O <= 1'b1; 74 | end 75 | else if(~ival) begin 76 | STB_O <= 1'b0; 77 | end 78 | end 79 | 80 | reg icyc; 81 | always @(posedge CLK_I) 82 | begin 83 | if(RST_I) icyc <= 1'b0; 84 | else icyc <= CYC_I; 85 | end 86 | always @(posedge CLK_I) 87 | begin 88 | if(RST_I) CYC_O <= icyc; 89 | else CYC_O <= icyc; 90 | end 91 | 92 | assign WE_O = STB_O; 93 | 94 | always @(*) begin 95 | case (idat[5:3]) 96 | 3'b000 : datout_Im = `Qn7; 97 | 3'b100 : datout_Im = `Qn5; 98 | 3'b110 : datout_Im = `Qn3; 99 | 3'b010 : datout_Im = `Qn1; 100 | 3'b011 : datout_Im = `Qp1; 101 | 3'b111 : datout_Im = `Qp3; 102 | 3'b101 : datout_Im = `Qp5; 103 | 3'b001 : datout_Im = `Qp7; 104 | default: datout_Im = 16'd0; 105 | endcase 106 | end 107 | 108 | always @(*) begin 109 | case (idat[2:0]) 110 | 3'b000 : datout_Re = `Qn7; 111 | 3'b100 : datout_Re = `Qn5; 112 | 3'b110 : datout_Re = `Qn3; 113 | 3'b010 : datout_Re = `Qn1; 114 | 3'b011 : datout_Re = `Qp1; 115 | 3'b111 : datout_Re = `Qp3; 116 | 3'b101 : datout_Re = `Qp5; 117 | 3'b001 : datout_Re = `Qp7; 118 | default: datout_Re = 16'd0; 119 | endcase 120 | end 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/OFDM_TX_802_11.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:19:17 03/22/2013 7 | // Design Name: 8 | // Module Name: OFDM_TX_802_11 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module OFDM_TX_802_11( 22 | input CLK_I, RST_I, 23 | input [5:0] DAT_I, 24 | input CYC_I, WE_I, STB_I, 25 | output ACK_O, 26 | 27 | output [31:0] DAT_O, 28 | output CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | wire [31:0] DAT_Mod_DAT_O; 34 | wire DAT_Mod_WE_O; 35 | wire DAT_Mod_STB_O; 36 | wire DAT_Mod_CYC_O; 37 | wire DAT_Mod_ACK_I; 38 | QPSK_Mod DAT_Mod_Ins( 39 | .CLK_I(CLK_I), .RST_I(RST_I), 40 | .DAT_I(DAT_I), 41 | .WE_I (WE_I), 42 | .STB_I(STB_I), 43 | .CYC_I(CYC_I), 44 | .ACK_O(ACK_O), 45 | 46 | .DAT_O(DAT_Mod_DAT_O), 47 | .WE_O (DAT_Mod_WE_O ), 48 | .STB_O(DAT_Mod_STB_O), 49 | .CYC_O(DAT_Mod_CYC_O), 50 | .ACK_I(DAT_Mod_ACK_I) 51 | ); 52 | 53 | wire [31:0] Pilots_Insert_DAT_O; 54 | wire Pilots_Insert_WE_O; 55 | wire Pilots_Insert_STB_O; 56 | wire Pilots_Insert_CYC_O; 57 | wire Pilots_Insert_ACK_I; 58 | Pilots_Insert Pilots_Insert_Ins( 59 | .CLK_I(CLK_I), .RST_I(RST_I), 60 | .DAT_I(DAT_Mod_DAT_O), 61 | .WE_I (DAT_Mod_WE_O), 62 | .STB_I(DAT_Mod_STB_O), 63 | .CYC_I(DAT_Mod_CYC_O), 64 | .ACK_O(DAT_Mod_ACK_I), 65 | 66 | .DAT_O(Pilots_Insert_DAT_O), 67 | .WE_O (Pilots_Insert_WE_O ), 68 | .STB_O(Pilots_Insert_STB_O), 69 | .CYC_O(Pilots_Insert_CYC_O), 70 | .ACK_I(Pilots_Insert_ACK_I) 71 | ); 72 | 73 | 74 | wire [31:0] IFFT_Mod_DAT_O; 75 | wire IFFT_Mod_WE_O; 76 | wire IFFT_Mod_STB_O; 77 | wire IFFT_Mod_CYC_O; 78 | wire IFFT_Mod_ACK_I; 79 | IFFT_Mod IFFT_Mod_Ins( 80 | .CLK_I(CLK_I), .RST_I(RST_I), 81 | .DAT_I(Pilots_Insert_DAT_O), 82 | .WE_I (Pilots_Insert_WE_O), 83 | .STB_I(Pilots_Insert_STB_O), 84 | .CYC_I(Pilots_Insert_CYC_O), 85 | .ACK_O(Pilots_Insert_ACK_I), 86 | 87 | .DAT_O(IFFT_Mod_DAT_O), 88 | .WE_O (IFFT_Mod_WE_O ), 89 | .STB_O(IFFT_Mod_STB_O), 90 | .CYC_O(IFFT_Mod_CYC_O), 91 | .ACK_I(IFFT_Mod_ACK_I) 92 | ); 93 | 94 | 95 | wire [31:0] Tx_Out_DAT_O; 96 | wire Tx_Out_WE_O; 97 | wire Tx_Out_STB_O; 98 | wire Tx_Out_CYC_O; 99 | wire Tx_Out_ACK_I; 100 | Tx_Out Tx_Out_Ins( 101 | .CLK_I(CLK_I), .RST_I(RST_I), 102 | .DAT_I(IFFT_Mod_DAT_O), 103 | .WE_I (IFFT_Mod_WE_O), 104 | .STB_I(IFFT_Mod_STB_O), 105 | .CYC_I(IFFT_Mod_CYC_O), 106 | .ACK_O(IFFT_Mod_ACK_I), 107 | 108 | .DAT_O(Tx_Out_DAT_O), 109 | .WE_O (Tx_Out_WE_O ), 110 | .STB_O(Tx_Out_STB_O), 111 | .CYC_O(Tx_Out_CYC_O), 112 | .ACK_I(Tx_Out_ACK_I) 113 | ); 114 | 115 | assign Tx_Out_ACK_I = ACK_I; 116 | assign DAT_O = Tx_Out_DAT_O; 117 | assign WE_O = Tx_Out_WE_O; 118 | assign STB_O = Tx_Out_STB_O; 119 | assign CYC_O = Tx_Out_CYC_O; 120 | 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Multiplierless_Correlator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:02:55 04/15/2012 7 | // Design Name: 8 | // Module Name: Multiplierless_Correlator 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Multiplierless_Correlator #(parameter FBIT =7) //number of R Metric's frational bits) 22 | ( 23 | input clk,rst, 24 | input ena, 25 | input [15:0] CR_in, // in format(Q1.15) 26 | output reg [4+FBIT:0] CR_out // rounding R Metric in format 5.FBIT 27 | ); 28 | 29 | 30 | reg [3:0] Synch_known_coeff [63:0]; 31 | initial $readmemh("./MY_SOURCES/Synch_known_coeff_rtl.txt", Synch_known_coeff); 32 | 33 | 34 | //wire [15:0] iCR_in = CR_in; 35 | //wire iena = ena; 36 | reg [FBIT:0] iCR_in; // in format(Q1.FBIT) 37 | reg iena; 38 | always @(posedge clk) 39 | begin 40 | if (rst) begin 41 | iCR_in <= 8'd0; 42 | iena <= 1'b0; 43 | end 44 | else if(ena) begin 45 | iCR_in <= CR_in[15:15-FBIT]; 46 | iena <= 1'b1; 47 | end 48 | else iena <= 1'b0; 49 | end 50 | 51 | wire [FBIT:0] iCR_in_d64; // in format(Q1.FBIT) 52 | 53 | Delay2n #(.WIDTH(1+FBIT), .D(64), .B(6)) RX_delay64( 54 | .clk(clk), 55 | .rst(rst), 56 | .ena(iena), 57 | .dat_in(iCR_in), 58 | .dat_out(iCR_in_d64) 59 | ); 60 | 61 | wire [1+FBIT:0] fir_in = iCR_in + iCR_in_d64; // in format(Q2.FBIT) 62 | 63 | //============================================= 64 | wire [1+FBIT:0] ML_value1, ML_value2; 65 | assign ML_value1 = fir_in >> 1; 66 | assign ML_value2 = fir_in; 67 | 68 | wire [1+FBIT:0] ML_tap_out [63:0]; //Multipliless in format(Q2.FBIT) 69 | genvar ML_cnt; 70 | generate 71 | for (ML_cnt=0; ML_cnt < 64; ML_cnt = ML_cnt + 1) 72 | begin: ML_assign 73 | ML_tap #(.WIDTH(2+FBIT)) ML_tap_ins( 74 | .ML_value1(ML_value1), .ML_value2(ML_value2), //[16:0] 75 | .known_coeff(Synch_known_coeff[ML_cnt][1:0]), //[1:0] 76 | .ML_out(ML_tap_out[ML_cnt]) //[16:0] 77 | ); 78 | end 79 | endgenerate 80 | 81 | 82 | //============================================= 83 | wire [5+FBIT:0] add_out [63:0]; //Add in format(Q6.FBIT) 84 | assign add_out[0] = {{4{1'b0}},ML_tap_out[0]}; 85 | 86 | 87 | 88 | wire [4+FBIT:0] reg_out [62:0]; //Add Register in format(Q5.FBIT) 89 | 90 | genvar cnt; 91 | generate 92 | for (cnt=0; cnt < 63; cnt = cnt + 1) 93 | begin: AddCmpReg_ins 94 | Delay_reg #(.WIDTH(5+FBIT)) CRpc_Re_D( 95 | .clk(clk), .rst(rst), .ena(iena), 96 | .dat_in( add_out[cnt][4+FBIT:0]), 97 | .dat_out(reg_out[cnt][4+FBIT:0]) 98 | ); 99 | 100 | assign add_out[cnt+1] = reg_out[cnt] + {{3{1'b0}},ML_tap_out[cnt+1]}; 101 | end 102 | endgenerate 103 | 104 | //assign CR_out = add_out[63][13:0]; 105 | 106 | always @(posedge clk) 107 | begin 108 | if (rst) CR_out <= {(5+FBIT){1'b0}}; 109 | else if(iena) CR_out <= add_out[63][4+FBIT:0]; 110 | end 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Ch_EstEqu_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:31:44 06/23/2013 7 | // Design Name: 8 | // Module Name: Ch_EstEqu_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ch_EstEqu_tb( 22 | ); 23 | reg rst, clk; 24 | reg cyc_i; 25 | reg [31:0] dat_in; 26 | wire ack_o; 27 | 28 | wire [31:0] dat_out; 29 | wire we_o, stb_o, cyc_o; 30 | reg ack_i; 31 | 32 | wire stb_i = cyc_i; 33 | wire we_i = stb_i; 34 | Ch_EstEqu UUT( 35 | .CLK_I(clk), .RST_I(rst), 36 | .DAT_I(dat_in), 37 | .CYC_I(cyc_i), 38 | .WE_I(we_i), 39 | .STB_I(stb_i), 40 | .ACK_O(ack_o), 41 | 42 | .DAT_O(dat_out), 43 | .WE_O(we_o), 44 | .STB_O(stb_o), 45 | .CYC_O(cyc_o), 46 | .ACK_I(ack_i) 47 | ); 48 | parameter NSAM = 10*(64+16); 49 | reg [15:0] datin_Re [NSAM - 1:0]; 50 | reg [15:0] datin_Im [NSAM - 1:0]; 51 | integer ii; 52 | integer NLOP, Len, para_fin; 53 | 54 | 55 | initial begin 56 | rst = 1'b1; 57 | clk = 1'b0; 58 | cyc_i = 1'b0; 59 | ii = 0; 60 | dat_in = 32'd0; 61 | 62 | para_fin = $fopen("./MATLAB/RTL_ChEstEqu_datin_len.txt","r"); 63 | $fscanf(para_fin, "%d ", Len); 64 | $fclose(para_fin); 65 | 66 | 67 | $readmemh("./MATLAB/RTL_ChEstEqu_datin_Re.txt", datin_Re); 68 | $readmemh("./MATLAB/RTL_ChEstEqu_datin_Im.txt", datin_Im); 69 | #25rst = 1'b0; 70 | end 71 | 72 | always #10 clk = ~clk; 73 | 74 | reg wr_frm; 75 | initial begin 76 | wr_frm = 1'b0; 77 | wr_datin =1'b1; 78 | ack_i = 1'b1; 79 | #200 ii=0; 80 | wr_frm = 1'b1; 81 | end 82 | 83 | reg wr_datin, wr_frm_pp; 84 | 85 | always @(posedge clk) begin 86 | if(rst) begin 87 | ii <= 0; 88 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 89 | wr_frm_pp <= 1'b0; 90 | end 91 | else if(wr_frm) begin 92 | cyc_i <= 1'b1; 93 | 94 | if (ii < Len) begin 95 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 96 | ii <= ii+1; 97 | end 98 | else if (ii == Len) 99 | begin 100 | wr_frm <= 0; 101 | cyc_i <= 1'b0; 102 | end 103 | end 104 | end 105 | 106 | 107 | integer datout_Re_fo, datout_Im_fo, datout_cnt; 108 | 109 | initial begin 110 | datout_cnt = 0; 111 | datout_Re_fo = $fopen("./MATLAB/RTL_ChEstEqu_datout_Re.txt"); 112 | datout_Im_fo = $fopen("./MATLAB/RTL_ChEstEqu_datout_Im.txt"); 113 | forever begin 114 | @(posedge clk); 115 | if ((we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 116 | $fwrite(datout_Re_fo,"%d ",$signed(dat_out[15:0])); 117 | $fwrite(datout_Im_fo,"%d ",$signed(dat_out[31:16])); 118 | datout_cnt = datout_cnt + 1; 119 | end 120 | end 121 | end 122 | 123 | 124 | reg stop_chk; 125 | initial begin 126 | stop_chk = 1'b0; 127 | @(posedge cyc_o); 128 | @(negedge cyc_o); 129 | #300 stop_chk = 1'b1; 130 | end 131 | initial begin 132 | forever begin 133 | @(posedge clk); 134 | if (stop_chk) begin 135 | $fclose(datout_Re_fo); 136 | $fclose(datout_Im_fo); 137 | $stop; 138 | end 139 | end 140 | end 141 | 142 | endmodule 143 | 144 | 145 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Freoff_Est_Comp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:30:48 05/11/2012 7 | // Design Name: 8 | // Module Name: Freoff_Est_Comp 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Freoff_Est_Comp( 22 | input clk, rst, ena, ce, 23 | input [31:0] dat_in, 24 | input stb_in, 25 | input [22:0] P_Re, P_Im, 26 | output reg [31:0] dat_out, 27 | output reg out_val 28 | ); 29 | 30 | 31 | reg ena_pp; 32 | always @(posedge clk) 33 | begin 34 | if(rst) ena_pp <= 1'b0; 35 | else ena_pp <= ena; 36 | end 37 | 38 | wire phase_trans_rdy, phase_trans_rfd; 39 | wire [15:0] phase_trans_out; 40 | wire phase_trans_nd = ena & (~ena_pp); 41 | 42 | wire [15:0] phase_rot; 43 | wire phase_rot_nd; 44 | wire [15:0] phase_rot_xout, phase_rot_yout; 45 | wire phase_rot_rdy; 46 | 47 | FreComp_PhaseTrans Phase_Trans_ins ( 48 | .x_in(P_Re[22:7]), // input [15 : 0] x_in 49 | .y_in(P_Im[22:7]), // input [15 : 0] y_in 50 | .nd(phase_trans_nd), // input nd 51 | .phase_out(phase_trans_out),// output [15 : 0] phase_out in format 3.13 52 | .rdy(phase_trans_rdy), // output rdy 53 | .rfd(phase_trans_rfd), // output rfd 54 | .clk(clk), // input clk 55 | .sclr(rst) // input sclr 56 | ); 57 | 58 | wire phase_acc_ld = phase_trans_rdy; 59 | reg phase_acc_run; 60 | always @(posedge clk) 61 | begin 62 | if(rst) phase_acc_run <= 1'b0; 63 | else if(phase_trans_rdy) phase_acc_run <= 1'b1; 64 | else if(~ena) phase_acc_run <= 1'b0; 65 | end 66 | 67 | wire phase_acc_rdy; 68 | Phase_Acc Phase_Acc_ins( 69 | .clk(clk), //input clock 70 | .rst(rst), //input reset 71 | .ld(phase_acc_ld), 72 | .acc(phase_acc_run & stb_in), //input Accumulate phase 73 | .ce(ce), 74 | .phase_in(phase_trans_out), //input [15:0] phase input 75 | .phase_out(phase_rot), //output[15:0] phase output 76 | .phase_out_rdy(phase_acc_rdy) //output phase out ready 77 | ); 78 | 79 | 80 | assign phase_rot_nd = phase_acc_rdy & stb_in; 81 | wire [15:0] phase_rot_x_in = {dat_in[15], dat_in[15:1]}; //in format 2.14 82 | wire [15:0] phase_rot_y_in = {dat_in[31], dat_in[31:17]} ; //in format 2.14 83 | FreComp_PhaseRot Phase_Rot_ins ( 84 | .x_in(phase_rot_x_in), // input [15 : 0] x_in //in format 2.14 85 | .y_in(phase_rot_y_in), // input [15 : 0] y_in //in format 2.14 86 | .phase_in(phase_rot), // input [15 : 0] phase_in in format 3.13 87 | .nd(phase_rot_nd), // input nd 88 | .x_out(phase_rot_xout), // output [15 : 0] x_out //in format 2.14 89 | .y_out(phase_rot_yout), // output [15 : 0] y_out //in format 2.14 90 | .rdy(phase_rot_rdy), // output rdy 91 | .ce(ce), // input ce 92 | .clk(clk), // input clk 93 | .sclr(rst) // input sclr 94 | ); 95 | 96 | always @(posedge clk) 97 | begin 98 | if(rst) begin 99 | dat_out <= 32'b0; 100 | out_val <= 1'b0; 101 | end 102 | else if (phase_rot_rdy) begin 103 | dat_out <= {phase_rot_yout, phase_rot_xout}; 104 | out_val <= 1'b1; 105 | end 106 | else out_val <= 1'b0; 107 | end 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Coarse_Time_Synch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:19:17 05/14/2012 7 | // Design Name: 8 | // Module Name: Coast_Time_Synch 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Coarse_Time_Synch( 22 | input clk, rst, cyc_i, 23 | input ena, 24 | input [23:0] P_Metric_mag, 25 | input [23:0] R_Metric, 26 | output reg Freoff_Est_Comp_ena 27 | ); 28 | reg frm_dec; 29 | wire [23:0] R_Metric_thr = R_Metric >>1; 30 | 31 | reg [3:0] smooth_cnt; 32 | wire frm_dec_cmp = (P_Metric_mag > R_Metric_thr) & (|R_Metric_thr[23:8]); 33 | always @(posedge clk) begin 34 | if(rst) smooth_cnt <= 4'd0; 35 | else if (ena) begin 36 | if (frm_dec_cmp & (~(smooth_cnt == 4'b1111))) smooth_cnt <= smooth_cnt + 1'b1; 37 | end 38 | else smooth_cnt <= 4'd0; 39 | end 40 | 41 | always @(posedge clk) begin 42 | if(rst) frm_dec <= 1'b0; 43 | else if (smooth_cnt == 4'b1111) frm_dec <= 1'b1; 44 | else if (~cyc_i) frm_dec <= 1'b0; 45 | end 46 | 47 | wire plat_dec; 48 | wire signed [16:0] P_diff; 49 | wire [15:0] P_in; // 16 higher bits from P_Metric_mag 50 | wire [15:0] P_d64,P_d96; 51 | 52 | assign P_in = P_Metric_mag[23:8]; 53 | Delay2n #(.WIDTH(16), .D(64), .B(6)) P_delay64( 54 | .clk(clk), 55 | .rst(rst), 56 | .ena(frm_dec), 57 | .dat_in(P_in), 58 | .dat_out(P_d64) 59 | ); 60 | 61 | Delay2n #(.WIDTH(16), .D(32), .B(5)) P_delay32( 62 | .clk(clk), 63 | .rst(rst), 64 | .ena(frm_dec), 65 | .dat_in(P_d64), 66 | .dat_out(P_d96) 67 | ); 68 | 69 | assign P_diff = $signed({1'b0,P_in}) - $signed({1'b0,P_d96}); 70 | 71 | reg signed [16:0] ins_max; // instantaneous maxima 72 | reg signed [18:0] grp_max, P_diff_acc; // group maxima 73 | 74 | reg [1:0] grp_cnt; 75 | reg [2:0] ins_cnt; 76 | 77 | always@ (posedge clk)begin 78 | if(rst) grp_cnt <= 3'b000; 79 | else if (~cyc_i) grp_cnt <= 3'b000; 80 | else if (frm_dec) grp_cnt <= grp_cnt + 1'b1; 81 | end 82 | 83 | always@ (posedge clk)begin 84 | if(rst) P_diff_acc <= 19'd0; 85 | else if (grp_cnt == 2'b00) P_diff_acc <= {{2{P_diff[16]}},P_diff}; 86 | else if (frm_dec) P_diff_acc <= P_diff_acc + {{2{P_diff[16]}},P_diff}; 87 | end 88 | 89 | wire grp_cmp = (grp_max < P_diff_acc) & (grp_cnt == 2'b00); 90 | always@ (posedge clk)begin 91 | if(rst) grp_max <= 19'd0; 92 | else if (~cyc_i) grp_max <= 19'd0; 93 | else if (grp_cmp) grp_max <= P_diff_acc; 94 | end 95 | 96 | reg grp_cmp_lat; 97 | always@ (posedge clk)begin 98 | if(rst) grp_cmp_lat <= 1'b0; 99 | else if (grp_cnt == 2'b00) grp_cmp_lat <= (grp_max < P_diff_acc); 100 | end 101 | 102 | wire ins_cmp = (ins_max < P_diff); 103 | always@ (posedge clk)begin 104 | if(rst) ins_max <= 20'd0; 105 | else if (~cyc_i) ins_max <= 20'd0; 106 | else if (ins_cmp) ins_max <= P_diff; 107 | end 108 | 109 | always@ (posedge clk)begin 110 | if(rst) ins_cnt <= 3'b000; 111 | else if (~cyc_i) ins_cnt <= 3'b000; 112 | else if (ins_cmp) ins_cnt <= 3'b000; 113 | else if (frm_dec) ins_cnt <= ins_cnt + 1'b1; 114 | end 115 | 116 | assign plat_dec = (~grp_cmp_lat) & (ins_cnt == 3'b111); 117 | 118 | always@ (posedge clk)begin 119 | if(rst) Freoff_Est_Comp_ena <= 1'b0; 120 | else if (~cyc_i) Freoff_Est_Comp_ena <= 1'b0; 121 | else if (plat_dec) Freoff_Est_Comp_ena <= 1'b1; 122 | end 123 | endmodule 124 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/PhaseTrack_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:19:17 06/27/2013 7 | // Design Name: 8 | // Module Name: PhaseTrack_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PhaseTrack_tb(); 22 | reg rst, clk; 23 | reg cyc_i; 24 | reg [31:0] dat_in; 25 | wire ack_o; 26 | 27 | wire [31:0] dat_out; 28 | wire we_o, stb_o, cyc_o; 29 | reg ack_i; 30 | 31 | wire stb_i = cyc_i; 32 | wire we_i = stb_i; 33 | //reg [127:0] ALLOC_VEC; 34 | reg [103:0] ALLOC_VEC; 35 | 36 | PhaseTrack UUT( 37 | .CLK_I(clk), .RST_I(rst), 38 | .DAT_I(dat_in), 39 | .CYC_I(cyc_i), 40 | .WE_I(we_i), 41 | .STB_I(stb_i), 42 | .ACK_O(ack_o), 43 | 44 | .DAT_O(dat_out), 45 | .WE_O(we_o), 46 | .STB_O(stb_o), 47 | .CYC_O(cyc_o), 48 | .ACK_I(ack_i), 49 | .ALLOC_VEC(ALLOC_VEC), 50 | .VEC_LD() 51 | ); 52 | parameter NSAM = 10*(64+16); 53 | reg [15:0] datin_Re [NSAM - 1:0]; 54 | reg [15:0] datin_Im [NSAM - 1:0]; 55 | integer ii; 56 | integer NLOP, Len, para_fin; 57 | 58 | 59 | initial begin 60 | rst = 1'b1; 61 | clk = 1'b0; 62 | cyc_i = 1'b0; 63 | ii = 0; 64 | dat_in = 32'd0; 65 | // ALLOC_VEC={{6{2'b11}}, 2'b01, {13{2'b11}}, 2'b01, {5{2'b11}}, {11{2'b00}}, {5{2'b11}}, 2'b10, {13{2'b11}}, 2'b01, {6{2'b11}}, 2'b00}; 66 | ALLOC_VEC={{6{2'b11}}, 2'b01, {13{2'b11}}, 2'b01, {5{2'b11}}, {5{2'b11}}, 2'b10, {13{2'b11}}, 2'b01, {6{2'b11}}}; 67 | 68 | para_fin = $fopen("./MATLAB/RTL_PhaseTrack_datin_len.txt","r"); 69 | $fscanf(para_fin, "%d ", Len); 70 | $fclose(para_fin); 71 | 72 | 73 | $readmemh("./MATLAB/RTL_PhaseTrack_datin_Re.txt", datin_Re); 74 | $readmemh("./MATLAB/RTL_PhaseTrack_datin_Im.txt", datin_Im); 75 | #25rst = 1'b0; 76 | end 77 | 78 | always #10 clk = ~clk; 79 | 80 | reg wr_frm; 81 | initial begin 82 | wr_frm = 1'b0; 83 | wr_datin =1'b1; 84 | ack_i = 1'b1; 85 | #200 ii=0; 86 | wr_frm = 1'b1; 87 | end 88 | 89 | reg wr_datin, wr_frm_pp; 90 | 91 | always @(posedge clk) begin 92 | if(rst) begin 93 | ii <= 0; 94 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 95 | wr_frm_pp <= 1'b0; 96 | end 97 | else if(wr_frm) begin 98 | cyc_i <= 1'b1; 99 | 100 | if (ii < Len) begin 101 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 102 | ii <= ii+1; 103 | end 104 | else if (ii == Len) 105 | begin 106 | wr_frm <= 0; 107 | cyc_i <= 1'b0; 108 | end 109 | end 110 | end 111 | 112 | 113 | integer datout_Re_fo, datout_Im_fo, datout_cnt; 114 | 115 | initial begin 116 | datout_cnt = 0; 117 | datout_Re_fo = $fopen("./MATLAB/RTL_PhaseTrack_datout_Re.txt"); 118 | datout_Im_fo = $fopen("./MATLAB/RTL_PhaseTrack_datout_Im.txt"); 119 | forever begin 120 | @(posedge clk); 121 | if ((we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 122 | $fwrite(datout_Re_fo,"%d ",$signed(dat_out[15:0])); 123 | $fwrite(datout_Im_fo,"%d ",$signed(dat_out[31:16])); 124 | datout_cnt = datout_cnt + 1; 125 | end 126 | end 127 | end 128 | 129 | 130 | reg stop_chk; 131 | initial begin 132 | stop_chk = 1'b0; 133 | @(posedge cyc_o); 134 | @(negedge cyc_o); 135 | #300 stop_chk = 1'b1; 136 | end 137 | initial begin 138 | forever begin 139 | @(posedge clk); 140 | if (stop_chk) begin 141 | $fclose(datout_Re_fo); 142 | $fclose(datout_Im_fo); 143 | $stop; 144 | end 145 | end 146 | end 147 | 148 | endmodule 149 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Time_Synch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:34:21 04/20/2012 7 | // Design Name: 8 | // Module Name: Time_Synch 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Time_Synch( 22 | input clk, rst, syn_run, 23 | input metric_val, 24 | input [21:0] P_Metric_Re,P_Metric_Im, 25 | input [21:0] R_Metric, 26 | input [3:0] SNR, 27 | 28 | output syn_done, 29 | output reg [31:0] FRE_O 30 | ); 31 | parameter SYN_VAL = 6'd56; 32 | 33 | 34 | reg [16:0] Synch_thres_coeff [15:0]; // threshold in format 2.15 35 | initial $readmemh("./MY_SOURCES/RTL_Synch_thres_coeff_q05.txt", Synch_thres_coeff); 36 | 37 | wire ena = metric_val & syn_run; 38 | 39 | wire [16:0] thres_coeff = Synch_thres_coeff[SNR]; 40 | wire [33:0] mult_thres_out; // output of multiplying to threshold in format 9.25 41 | mult thres_mult_ins ( 42 | .clk(clk), // input clk 43 | .sclr(rst), // input sclr 44 | .ce(ena), // input ce 45 | .a(R_Metric[21:5]), // input [16 : 0] a in format 7.10 46 | .b(thres_coeff), // input [16 : 0] b 47 | .p(mult_thres_out) // output [33 : 0] p 48 | ); 49 | wire [22:0] R_Metric_thr = mult_thres_out[32:10]; // R metric multipies threshold in format 8.15 50 | 51 | wire [22:0] P_Metric_mag; 52 | wire appr_mag_val; 53 | Appr_Mag P_Metic_mag_ins( 54 | .clk(clk), .rst(rst), .ena(ena), 55 | .real_in(P_Metric_Re), 56 | .imag_in(P_Metric_Im), 57 | .mag(P_Metric_mag), // magnitute of P metric in format 8.15 58 | .val(appr_mag_val) 59 | ); 60 | 61 | wire [7:0] R_Metric_d64; //reduced bit R_metric delay 64 in format 7.1 62 | Delay2n #(.WIDTH(8), .D(64), .B(6)) RX_delay64( 63 | .clk(clk), .rst(rst), .ena(ena), 64 | .dat_in(R_Metric[21:14]), 65 | .dat_out(R_Metric_d64) 66 | ); 67 | 68 | reg cmp_metric; 69 | always@(posedge clk) 70 | begin 71 | if (rst) cmp_metric = 1'b0; 72 | else if (appr_mag_val & (P_Metric_mag > R_Metric_thr)) cmp_metric = 1'b1; 73 | else if (~syn_run) cmp_metric = 1'b0; 74 | end 75 | 76 | reg [6:0] find_peak_cnt; 77 | wire find_peak_ena = (~find_peak_cnt[6]) & cmp_metric & syn_run; 78 | always@(posedge clk) 79 | begin 80 | if (rst) find_peak_cnt = 7'b1; 81 | else if (~syn_run) find_peak_cnt = 7'b1; 82 | else if (find_peak_ena) find_peak_cnt = find_peak_cnt + 1'b1; 83 | 84 | end 85 | 86 | wire [22:0] add_metric = R_Metric[21:0] + {R_Metric_d64,14'd0}; 87 | reg peak_dec; 88 | reg [22:0] peak_add_metric; 89 | always@(posedge clk) 90 | begin 91 | if (rst) begin 92 | FRE_O <= 32'd0; 93 | peak_dec <= 1'b0; 94 | peak_add_metric <= 23'd0; 95 | end 96 | else if (find_peak_ena) begin 97 | if (peak_add_metric < add_metric) begin 98 | FRE_O = {P_Metric_Im[21:6],P_Metric_Re[21:6]}; 99 | peak_add_metric <= add_metric; 100 | peak_dec <= 1'b1; 101 | end 102 | else peak_dec <= 1'b0; 103 | end 104 | else begin 105 | peak_dec <= 1'b0; 106 | peak_add_metric <= 23'd0; 107 | end 108 | end 109 | 110 | 111 | reg [5:0] syn_cnt; 112 | wire syn_cnt_run = ~(syn_cnt == 6'd0); 113 | always@(posedge clk) 114 | begin 115 | if (rst) syn_cnt <= 6'd0; 116 | if (~ syn_run) syn_cnt <= 6'd0; 117 | else if (find_peak_ena & (~syn_cnt_run)) syn_cnt <= 6'b1; 118 | else if (syn_cnt == SYN_VAL) syn_cnt <= 6'b0; 119 | else if (syn_cnt_run & peak_dec) syn_cnt <= 6'b1; 120 | else if (syn_cnt_run) syn_cnt <= syn_cnt + 1'b1; 121 | 122 | end 123 | 124 | assign syn_done = (syn_cnt == SYN_VAL) & (~find_peak_ena); 125 | endmodule 126 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/FFT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:54:50 03/29/2012 7 | // Design Name: 8 | // Module Name: FFT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module FFT( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, // DAT_I_Im[31:16] DAT_I_Re[15:0] in format 2.14 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, // DAT_O_Im[31:16] DAT_O_Re[15:0] in format 5.11 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | wire s_dat_val, s_dat_rdy; 34 | wire m_dat_val, m_dat_rdy, m_dat_tlast; 35 | wire [7:0] m_index; 36 | wire event_status_channel_halt, event_data_in_channel_halt,event_data_out_channel_halt; 37 | wire aresetn; 38 | wire frame_start; 39 | wire [31:0] fft_datout; 40 | assign aresetn = ~RST_I; 41 | FFT_ipcore FFT_ins ( 42 | .aclk(CLK_I), // input aclk 43 | .aresetn(aresetn), // input aresetn 44 | //.s_axis_config_tdata(16'h0157), // input [15 : 0] s_axis_config_tdata; scale: shift right 9 bits : 2, 2, 2, 3 45 | .s_axis_config_tdata(8'h2B), // input [15 : 0] s_axis_config_tdata; scale: shift right 3 bits : 0, 1, 1, 1 46 | .s_axis_config_tvalid(1'b1), // input s_axis_config_tvalid 47 | .s_axis_config_tready(), // ouput s_axis_config_tready 48 | .s_axis_data_tdata(DAT_I[31:0]), // input [31 : 0] s_axis_data_tdata 49 | .s_axis_data_tvalid(s_dat_val), // input s_axis_data_tvalid 50 | .s_axis_data_tready(s_dat_rdy), // ouput s_axis_data_tready 51 | .s_axis_data_tlast(1'b0), // input s_axis_data_tlast 52 | .m_axis_data_tdata(fft_datout), // ouput [31 : 0] m_axis_data_tdata in format 5.11 53 | .m_axis_data_tuser(m_index[7:0]), // ouput [7 : 0] m_axis_data_tuser 54 | .m_axis_data_tvalid(m_dat_val), // ouput m_axis_data_tvalid 55 | .m_axis_data_tready(m_dat_rdy), // input m_axis_data_tready 56 | .m_axis_data_tlast(m_dat_tlast), // ouput m_axis_data_tlast 57 | .event_frame_started(frame_start), // ouput event_frame_started 58 | .event_tlast_unexpected(), // ouput event_tlast_unexpected 59 | .event_tlast_missing(), // ouput event_tlast_missing 60 | .event_status_channel_halt(event_status_channel_halt), // ouput event_status_channel_halt 61 | .event_data_in_channel_halt(event_data_in_channel_halt), // ouput event_data_in_channel_halt 62 | .event_data_out_channel_halt(event_data_out_channel_halt)); // ouput event_data_out_channel_halt 63 | 64 | assign s_dat_val = (CYC_I)&&(STB_I)&&(WE_I); 65 | assign ACK_O = s_dat_rdy; 66 | assign m_dat_rdy = ~(STB_O & (~ACK_I)); 67 | 68 | reg data_tlast_pp; 69 | always @(posedge CLK_I) 70 | begin 71 | if(RST_I) data_tlast_pp <= 1'b0; 72 | else data_tlast_pp <= m_dat_tlast; 73 | end 74 | 75 | reg [3:0] frm_cnt; 76 | always @(posedge CLK_I) 77 | begin 78 | if(RST_I) frm_cnt <= 1'b0; 79 | else if(frame_start &(~m_dat_tlast)) frm_cnt <= frm_cnt + 1'b1; 80 | else if((~frame_start)& m_dat_tlast) frm_cnt <= frm_cnt - 1'b1; 81 | end 82 | 83 | always @(posedge CLK_I) 84 | begin 85 | if(RST_I) CYC_O <= 1'b0; 86 | else if (m_dat_val) CYC_O <= 1'b1; 87 | else if (data_tlast_pp & (~m_dat_val) & (~CYC_I) & (frm_cnt == 4'd0)) CYC_O <= 1'b0; 88 | end 89 | 90 | always @(posedge CLK_I) 91 | begin 92 | if(RST_I) DAT_O <= 32'd0; 93 | else if (m_dat_rdy) DAT_O <= {fft_datout[31:16], fft_datout[15:0]}; 94 | end 95 | 96 | always @(posedge CLK_I) 97 | begin 98 | if(RST_I) STB_O <= 1'b0; 99 | else if (m_dat_rdy) STB_O <= m_dat_val; 100 | end 101 | assign WE_O = STB_O; 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/Pilots_Insert.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:02:46 12/04/2012 7 | // Design Name: 8 | // Module Name: Pilots_Insert 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Pilots_Insert( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, 24 | input CYC_I, WE_I, STB_I, 25 | output ACK_O, 26 | 27 | output [31:0] DAT_O, 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | parameter P_P = 16'h7fff; // +1 in Q1.15 33 | parameter P_N = 16'h8001; // -1 in Q1.15 34 | reg Pil [0:127]; // signed bit of real part of pilots, 35 | initial $readmemh("./MY_SOURCES/Pilot_seq.txt", Pil); 36 | 37 | reg [31:0] idat; 38 | reg [31:0] odat; 39 | reg ival; 40 | wire out_halt, ena; 41 | wire datout_ack; 42 | 43 | 44 | reg [5:0] dat_cnt; 45 | reg [6:0] pilot_cnt; 46 | reg pil_insert_ena; 47 | reg nul_insert_ena; //inserting null symbol for guarding. 48 | wire[15:0] pil_Re; 49 | 50 | 51 | assign out_halt = STB_O & (~ACK_I); 52 | assign datout_ack = STB_O & ACK_I; 53 | assign ena = CYC_I & STB_I & WE_I; 54 | assign ACK_O = ena & (~out_halt) & (~pil_insert_ena) & (~nul_insert_ena); 55 | 56 | always @(posedge CLK_I) begin 57 | if(RST_I) idat<= 2'b00; 58 | else if(ACK_O) idat <= DAT_I; 59 | end 60 | always @(posedge CLK_I) begin 61 | if(RST_I) ival <= 1'b0; 62 | else if(ena) ival <= 1'b1; 63 | else ival <= 1'b0; 64 | end 65 | 66 | always @(posedge CLK_I) 67 | begin 68 | if(RST_I) STB_O <= 1'b0; 69 | else if(ival|pil_insert_ena|nul_insert_ena) STB_O <= 1'b1; 70 | else if(~ival) STB_O <= 1'b0; 71 | end 72 | 73 | always @(posedge CLK_I) 74 | begin 75 | if(RST_I) odat <= 32'b0; 76 | else if(ival & (~out_halt) & (~nul_insert_ena)) odat <= (pil_insert_ena)? {16'd0, pil_Re} : idat; 77 | end 78 | 79 | reg icyc; 80 | always @(posedge CLK_I) 81 | begin 82 | if(RST_I) icyc <= 1'b0; 83 | else icyc <= CYC_I; 84 | end 85 | always @(posedge CLK_I) 86 | begin 87 | if(RST_I) CYC_O <= icyc; 88 | else CYC_O <= icyc; 89 | end 90 | assign DAT_O = (nul_insert_ena)? 32'd0: odat; 91 | assign WE_O = STB_O; 92 | 93 | always@(posedge CLK_I) 94 | begin 95 | if(RST_I) dat_cnt <= 6'd0; 96 | else if(CYC_I & (~icyc)) dat_cnt <= 6'd0; 97 | else if(datout_ack) dat_cnt <= dat_cnt + 1'b1; 98 | end 99 | 100 | always@(posedge CLK_I) 101 | begin 102 | if(RST_I) pilot_cnt <= 7'd0; 103 | else if(CYC_I & (~icyc)) pilot_cnt <= 7'd0; 104 | else if(pil_insert_ena & (~out_halt)) pilot_cnt <= pilot_cnt + 1'b1; 105 | end 106 | 107 | assign pil_Re = (Pil[pilot_cnt])? P_N : P_P; 108 | 109 | always@(dat_cnt) begin 110 | pil_insert_ena = 1'b0; 111 | // nul_insert_ena = 1'b0; 112 | case (dat_cnt) 113 | //8'd0: nul_insert_ena = 1'b1; 114 | 6'd6, 6'd20, 6'd42, 6'd56: pil_insert_ena = 1'b1; 115 | 116 | default: begin 117 | pil_insert_ena = 1'b0; 118 | //nul_insert_ena = 1'b0; 119 | end 120 | endcase 121 | end 122 | 123 | always@(posedge CLK_I) 124 | begin 125 | if(RST_I) nul_insert_ena = 1'b0; 126 | else if(CYC_I & (~icyc)) nul_insert_ena = 1'b0; 127 | else if(icyc & (~CYC_O)) nul_insert_ena = 1'b1; 128 | else if(datout_ack & (dat_cnt == 6'd0)) nul_insert_ena = 1'b0; 129 | else if(datout_ack & (dat_cnt == 6'd26)) nul_insert_ena = 1'b1; 130 | else if(datout_ack & (dat_cnt == 6'd37)) nul_insert_ena = 1'b0; 131 | else if(icyc & datout_ack & (dat_cnt == 8'd63)) nul_insert_ena = 1'b1; 132 | end 133 | 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/OFDM_TX_802_11_ppr_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:33:46 05/03/2013 7 | // Design Name: 8 | // Module Name: OFDM_TX_802_11_ppr_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module OFDM_TX_802_11_ppr_tb( 22 | ); 23 | reg rst, clk; 24 | reg we_i, stb_i, cyc_i; 25 | reg [5:0] dat_in; 26 | reg ack_i; 27 | wire ack_o; 28 | wire [31:0] dat_out; 29 | wire we_o, stb_o, cyc_o; 30 | 31 | OFDM_TX_802_11 UUT( 32 | .CLK_I(clk), .RST_I(rst), 33 | .DAT_I(dat_in), 34 | .WE_I(we_i), 35 | .STB_I(stb_i), 36 | .CYC_I(cyc_i), 37 | .ACK_O(ack_o), 38 | .DAT_O(dat_out), 39 | .WE_O (we_o), 40 | .STB_O(stb_o), 41 | .CYC_O(cyc_o), 42 | .ACK_I(ack_i) 43 | ); 44 | 45 | parameter NSAM = 10*(256+32); 46 | reg [5:0] datin [NSAM - 1:0]; 47 | integer ii, lop_cnt; 48 | integer Len, NLOP, para_fin; 49 | 50 | 51 | initial begin 52 | rst = 1'b1; 53 | clk = 1'b0; 54 | we_i = 1'b0; 55 | stb_i = 1'b0; 56 | cyc_i = 1'b0; 57 | ii = 0; 58 | dat_in = 6'd0; 59 | 60 | para_fin = $fopen("./MATLAB/OFDM_TX_bit_symbols_Len.txt","r"); 61 | $fscanf(para_fin, "%d ", Len); 62 | $fscanf(para_fin, "%d ", NLOP); 63 | $fclose(para_fin); 64 | 65 | $readmemh("./MATLAB/RTL_OFDM_TX_bit_symbols.txt", datin); 66 | 67 | #25rst = 1'b0; 68 | end 69 | 70 | always #10 clk = ~clk; 71 | 72 | reg wr_datin, wr_frm_pp; 73 | 74 | reg wr_frm; 75 | initial begin 76 | wr_frm = 1'b0; 77 | wr_datin = 1'b1; 78 | ack_i = 1'b1; 79 | lop_cnt = 0; 80 | #600; 81 | forever begin 82 | @(posedge clk); 83 | 84 | if (~(lop_cnt == NLOP)) begin 85 | ii=0; 86 | wr_frm = 1'b1; 87 | dat_in <= datin[ii + lop_cnt*Len]; 88 | @(negedge cyc_o); 89 | #600; 90 | lop_cnt = lop_cnt +1; 91 | end 92 | end 93 | end 94 | 95 | 96 | always @(posedge clk) begin 97 | if(rst) begin 98 | ii <= 0; 99 | dat_in <= datin[ii + lop_cnt*Len]; 100 | wr_frm_pp <= 1'b0; 101 | end 102 | else if(wr_frm) begin 103 | cyc_i <= 1'b1; 104 | wr_frm_pp <= wr_frm; 105 | 106 | if (~wr_datin) begin 107 | stb_i <= 1'b0; 108 | cyc_i <= 1'b0; 109 | we_i <= 1'b0; 110 | end 111 | else if (~wr_frm_pp) begin 112 | wr_frm_pp <= wr_frm; 113 | ii <= ii+1; 114 | stb_i <= 1'b1; 115 | cyc_i <= 1'b1; 116 | we_i <= 1'b1; 117 | end 118 | else if ((ii == Len)&(ack_o)) begin 119 | we_i <= 1'b0; 120 | stb_i <= 1'b0; 121 | cyc_i <= 1'b0; 122 | wr_frm <= 1'b0; 123 | end 124 | else if (ack_o) begin 125 | //dat_in <= dat_in + 1'b1; 126 | dat_in <= datin[ii + lop_cnt*Len]; 127 | ii <= ii+1; 128 | stb_i <= 1'b1; 129 | cyc_i <= 1'b1; 130 | we_i <= 1'b1; 131 | end 132 | end 133 | else begin 134 | wr_frm_pp <= wr_frm; 135 | we_i <= 1'b0; 136 | stb_i <= 1'b0; 137 | cyc_i <= 1'b0; 138 | end 139 | 140 | end 141 | 142 | integer datout_Re_fo, datout_Im_fo, datout_cnt; 143 | integer Pilots_Insert_Re_fo, Pilots_Insert_Im_fo; 144 | integer IFFT_Mod_Re_fo, IFFT_Mod_Im_fo; 145 | initial begin 146 | datout_cnt = 0; 147 | datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_TX_datout_Re.txt"); 148 | datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_TX_datout_Im.txt"); 149 | 150 | forever begin 151 | @(posedge clk); 152 | if ((we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 153 | $fwrite(datout_Re_fo,"%d ",$signed(dat_out[15:0])); 154 | $fwrite(datout_Im_fo,"%d ",$signed(dat_out[31:16])); 155 | datout_cnt = datout_cnt + 1; 156 | end 157 | end 158 | end 159 | 160 | 161 | reg stop_chk; 162 | initial begin 163 | stop_chk = 1'b0; 164 | //#30000 stop_chk = 1'b1; 165 | forever begin 166 | @(posedge clk); 167 | if (lop_cnt == NLOP) begin 168 | #100; 169 | stop_chk = 1'b1; 170 | end 171 | end 172 | end 173 | initial begin 174 | forever begin 175 | @(posedge clk); 176 | if (stop_chk) begin 177 | $fclose(datout_Re_fo); 178 | $fclose(datout_Im_fo); 179 | 180 | $stop; 181 | end 182 | end 183 | end 184 | 185 | endmodule 186 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Fine_Time_Synch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:21:43 04/23/2012 7 | // Design Name: 8 | // Module Name: Synch_out 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Fine_Time_Synch( 22 | input clk, rst, 23 | input cyc_i, 24 | input stb_i, 25 | output ack_o, 26 | output reg [31:0] dat_out, 27 | output reg cyc_o, stb_o, 28 | output we_o, 29 | input ack_i, 30 | 31 | input [31:0] dat_in, 32 | input dat_in_val, 33 | //input CR_ena, 34 | // input [6:0] CR_out_Re, CR_out_Im, 35 | 36 | output reg time_syn_run, 37 | output out_halt 38 | ); 39 | 40 | 41 | reg time_syn_done; 42 | 43 | wire fine_Time_ena = dat_in_val & time_syn_run; 44 | 45 | reg cyc_i_pp; 46 | always @(posedge clk)begin 47 | if(rst) cyc_i_pp <= 1'b0; 48 | else cyc_i_pp <= cyc_i; 49 | end 50 | 51 | always @(posedge clk)begin 52 | if(rst) time_syn_run <= 1'b0; 53 | else if (cyc_i & (~cyc_i_pp)) time_syn_run <= 1'b1; 54 | else if (time_syn_done) time_syn_run <= 1'b0; 55 | end 56 | 57 | wire [1:0] CR_in = {dat_in[31], dat_in[15]}; 58 | wire [6:0] CR_out_Re, CR_out_Im; 59 | 60 | Signed_Correlator Signed_Correlator_ins( 61 | .clk(clk), .rst(rst), 62 | .ena(fine_Time_ena), 63 | .CR_in(CR_in), //[1] :signed bit of imaginary part, [0] :signed bit of real part, 64 | .CR_out_Re(CR_out_Re), 65 | .CR_out_Im(CR_out_Im) 66 | ); 67 | 68 | 69 | reg CR_mag_run; 70 | always @(posedge clk)begin 71 | if(rst) CR_mag_run <= 1'b0; 72 | else if (fine_Time_ena) CR_mag_run <= 1'b1; 73 | else CR_mag_run <= 1'b0; 74 | end 75 | 76 | wire [7:0] CR_out_mag; 77 | Appr_Mag #(.WIDTH(7)) CR_out_mag_ins( 78 | .clk(clk), .rst(rst), .ena(CR_mag_run), 79 | .real_in(CR_out_Re), 80 | .imag_in(CR_out_Im), 81 | .mag(CR_out_mag), 82 | .val(CR_out_mag_val) 83 | ); 84 | 85 | 86 | 87 | reg [6:0] CR_peak_dec_cnt; // counter for cross-corelation peak detect in 128 sample 88 | always @(posedge clk)begin 89 | if(rst) CR_peak_dec_cnt <= 7'b0; 90 | else if (cyc_i & (~cyc_i_pp)) CR_peak_dec_cnt <= 7'b0; 91 | else if (fine_Time_ena) CR_peak_dec_cnt <= CR_peak_dec_cnt + 1'b1; 92 | end 93 | reg CR_peak_dec_ena; 94 | always @(posedge clk)begin 95 | if(rst) CR_peak_dec_ena <= 1'b0; 96 | else if (CR_peak_dec_cnt == 7'd63) CR_peak_dec_ena <= 1'b1; 97 | else if (CR_peak_dec_cnt == 7'd95) CR_peak_dec_ena <= 1'b0; 98 | end 99 | 100 | reg [7:0] CR_max; 101 | wire CR_cmp = (CR_max < CR_out_mag); 102 | always @(posedge clk)begin 103 | if(rst) CR_max <= 8'd0; 104 | else if (cyc_i & (~cyc_i_pp)) CR_max <= 8'b0; 105 | else if (CR_peak_dec_ena & CR_cmp) CR_max <= CR_out_mag; 106 | end 107 | 108 | reg [4:0] syn_cnt; // counter for delay 15 samples after the peak of CR to determine the first point of last long preabmble 109 | always @(posedge clk)begin 110 | if(rst) syn_cnt <= 5'b01111; 111 | else if (CR_peak_dec_cnt == 7'd63) syn_cnt <= 5'b10000; 112 | else if (CR_peak_dec_ena & CR_cmp) syn_cnt <= 5'b10000; 113 | else if (CR_out_mag_val & (syn_cnt[4])) syn_cnt <= syn_cnt + 1'b1; 114 | else if (~cyc_i) syn_cnt <= 5'b01111; 115 | end 116 | 117 | wire syn_dec = (syn_cnt == 5'b11110); 118 | always @(posedge clk)begin 119 | if(rst) time_syn_done <= 1'b0; 120 | else if (cyc_i & (~cyc_i_pp)) time_syn_done <= 1'b0; 121 | else if (syn_dec) time_syn_done <= 1'b1; 122 | else if (~cyc_i & (~dat_in_val) ) time_syn_done <= 1'b0; 123 | end 124 | 125 | always @(posedge clk)begin 126 | if(rst) begin 127 | dat_out <= 32'b0; 128 | cyc_o <= 1'b0; 129 | stb_o <= 1'b0; 130 | end 131 | else if ((~out_halt) & time_syn_done) begin 132 | cyc_o <= 1'b1; 133 | dat_out <= dat_in; 134 | stb_o <= dat_in_val; 135 | end 136 | else if (~cyc_i & (~dat_in_val)) begin 137 | cyc_o <= 1'b0; 138 | stb_o <= 1'b0; 139 | end 140 | end 141 | assign out_halt = stb_o & (~ack_i); 142 | assign ack_o = (cyc_i & stb_i & (~out_halt)); 143 | assign we_o = stb_o; 144 | endmodule 145 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/FreComp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:26:29 03/29/2012 7 | // Design Name: 8 | // Module Name: FreComp 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module FreComp( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, // DAT_I_Im[31:16] DAT_I_Re[15:0] in format 1.15 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | input [31:0] FRE_I, // P[d] metric P_Im[31:16] P_Re[15:0] in format 2.14 28 | input FRE_I_nd, 29 | 30 | output reg [31:0] DAT_O, // DAT_O_Im[31:16] DAT_O_Re[15:0] in format 2.14 31 | output reg CYC_O, STB_O, 32 | output WE_O, 33 | input ACK_I 34 | ); 35 | 36 | 37 | wire phase_trans_rdy, phase_trans_rfd; 38 | wire [15:0] phase_trans_out; 39 | 40 | //wire phase_offs_rdy; 41 | //wire [15:0] phase_offs_out; 42 | 43 | wire [15:0] phase_rot; 44 | wire phase_rot_nd; 45 | 46 | wire [15:0] phase_rot_xout, phase_rot_yout; 47 | wire phase_rot_rdy; 48 | 49 | 50 | wire out_halt = STB_O & (~ACK_I); 51 | wire datin_ena = CYC_I & STB_I & WE_I; 52 | 53 | assign ACK_O = datin_ena &(~out_halt); 54 | 55 | reg CYC_I_pp; 56 | always @(posedge CLK_I or posedge RST_I) 57 | begin 58 | if(RST_I) CYC_I_pp <= 1'b0; 59 | else CYC_I_pp <= CYC_I; 60 | end 61 | 62 | 63 | FreComp_PhaseTrans FreComp_PhaseTrans_ins ( 64 | .x_in(FRE_I[15:0]), // input [15 : 0] x_in 65 | .y_in(FRE_I[31:16]), // input [15 : 0] y_in 66 | .nd(FRE_I_nd), // input nd 67 | .phase_out(phase_trans_out),// output [15 : 0] phase_out in format 3.13 68 | .rdy(phase_trans_rdy), // output rdy 69 | .rfd(phase_trans_rfd), // output rfd 70 | .clk(CLK_I), // input clk 71 | .sclr(RST_I) // input sclr 72 | ); 73 | 74 | /*PhaseAddOffset PhaseAddOffset_ins( 75 | .clk(CLK_I), 76 | .rst(RST_I), 77 | .ld(phase_trans_rdy), 78 | .phase_in(phase_trans_out), // phase in from phase translation in format 3.13 79 | .phase_out(phase_offs_out), // phase offset out for compensating short symbol in format 3.13 80 | .phase_out_rdy(phase_offs_rdy) ); 81 | */ 82 | 83 | wire acc = datin_ena; 84 | wire phase_acc_rdy; 85 | FreComp_PhaseRotAcc FreComp_PhaseRotAcc_ins( 86 | .clk(CLK_I), //input clock 87 | .rst(RST_I), //input reset 88 | //.ld(phase_offs_rdy), //input load initial phase 89 | .ld(phase_trans_rdy), 90 | .acc(acc), //input Accumulate phase 91 | .ce(~out_halt), 92 | //.phase_ld(phase_offs_out), //input [15:0] phase offset input 93 | .phase_ld(16'd0), //input [15:0] phase offset input 94 | .phase_in(phase_trans_out), //input [15:0] phase input 95 | .phase_out(phase_rot), //output[15:0] phase output 96 | .phase_out_rdy(phase_acc_rdy) //output phase out ready 97 | ); 98 | 99 | assign phase_rot_nd = datin_ena; 100 | wire phase_rot_ce = (~out_halt); 101 | wire [15:0] phase_rot_x_in = {DAT_I[15], DAT_I[15:1]}; //in format 2.14 102 | wire [15:0] phase_rot_y_in = {DAT_I[31], DAT_I[31:17]} ; //in format 2.14 103 | FreComp_PhaseRot FreComp_PhaseRot_ins ( 104 | .x_in(phase_rot_x_in), // input [15 : 0] x_in 105 | .y_in(phase_rot_y_in), // input [15 : 0] y_in 106 | .phase_in(phase_rot), // input [15 : 0] phase_in in format 3.13 107 | .nd(phase_rot_nd), // input nd 108 | .x_out(phase_rot_xout), // output [15 : 0] x_out 109 | .y_out(phase_rot_yout), // output [15 : 0] y_out 110 | .rdy(phase_rot_rdy), // output rdy 111 | .ce(phase_rot_ce), // input ce 112 | .clk(CLK_I), // input clk 113 | .sclr(RST_I) // input sclr 114 | ); 115 | 116 | always @(posedge CLK_I or posedge RST_I) 117 | begin 118 | if(RST_I) CYC_O <= 1'b0; 119 | else if (phase_rot_rdy &(CYC_I)) CYC_O <= 1'b1; 120 | else if ((~CYC_I) & (~STB_O)) CYC_O <= 1'b0; 121 | end 122 | 123 | always @(posedge CLK_I or posedge RST_I) 124 | begin 125 | if(RST_I) begin 126 | STB_O <= 1'b0; 127 | DAT_O <= 32'b0; 128 | end 129 | else if (~out_halt) begin 130 | DAT_O <= {phase_rot_yout, phase_rot_xout}; 131 | STB_O <= phase_rot_rdy; 132 | end 133 | // else if (~phase_rot_rdy) begin 134 | // DAT_O <= 32'd0; 135 | // STB_O <= 1'b0; 136 | // end 137 | end 138 | assign WE_O = STB_O; 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/IFFT_Mod.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:04:08 12/04/2012 7 | // Design Name: 8 | // Module Name: IFFT_Mod 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: This module uses the IFFT IP core to modulate the data symbol in OFDM system 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module IFFT_Mod( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, 24 | input CYC_I, WE_I, STB_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | reg [31:0] idat; 33 | //reg [31:0] odat; 34 | reg ival; 35 | reg icyc; 36 | wire out_halt, ena; 37 | wire datout_ack; 38 | reg process_done; // assert when IFFT's procees has done and begin tranmitting data symbol. 39 | //reg [5:0] d_cnt; //delay counter to delay generating the preamble in order to wait for IFFT computation 40 | 41 | wire s_dat_val, s_dat_rdy; 42 | wire m_dat_val, m_dat_rdy, m_dat_tlast; 43 | wire [7:0] m_index; 44 | wire event_status_channel_halt, event_data_in_channel_halt,event_data_out_channel_halt; 45 | wire aresetn; 46 | //wire frame_start; 47 | wire [31:0] fft_datout; 48 | 49 | assign out_halt = STB_O & (~ACK_I); 50 | assign datout_ack = STB_O & ACK_I; 51 | assign ena = CYC_I & STB_I & WE_I; 52 | assign ACK_O = ena & (~out_halt) & (s_dat_rdy) ; 53 | 54 | always @(posedge CLK_I) begin 55 | if(RST_I) idat<= 32'd0; 56 | else if(ACK_O) idat <= DAT_I; 57 | end 58 | always @(posedge CLK_I) begin 59 | if(RST_I) ival <= 1'b0; 60 | else if(ena) ival <= 1'b1; 61 | else ival <= 1'b0; 62 | end 63 | 64 | always @(posedge CLK_I) 65 | begin 66 | if(RST_I) icyc <= 1'b0; 67 | else icyc <= CYC_I; 68 | end 69 | always @(posedge CLK_I) 70 | begin 71 | if(RST_I) CYC_O <= 1'b0; 72 | else if(CYC_I &(~icyc)) CYC_O <= 1'b1; 73 | else if((~CYC_I) &(~m_dat_val) & process_done) CYC_O <= 1'b0; 74 | end 75 | 76 | always @(posedge CLK_I) 77 | begin 78 | if(RST_I) process_done <= 1'b0; 79 | else if(CYC_I &(~icyc)) process_done <= 1'b0; 80 | else if(m_dat_val) process_done <= 1'b1; 81 | end 82 | 83 | always @(posedge CLK_I) 84 | begin 85 | if(RST_I) DAT_O <= 32'd0; 86 | else if (m_dat_rdy & (~out_halt)) DAT_O <= fft_datout; 87 | end 88 | always @(posedge CLK_I) 89 | begin 90 | if(RST_I) STB_O <= 1'b0; 91 | else if (m_dat_rdy & (~out_halt)) STB_O <= m_dat_val; 92 | end 93 | assign WE_O = STB_O; 94 | 95 | 96 | assign aresetn = ~RST_I; 97 | assign s_dat_val = ival & (~out_halt); 98 | assign m_dat_rdy = ~out_halt; 99 | 100 | IFFT IFFT_Ins( 101 | .aclk(CLK_I), // input aclk 102 | //.aclken(aclken), // input aclken 103 | .aresetn(aresetn), // input aresetn 104 | .s_axis_config_tdata(16'h3610), // input [23 : 0] s_axis_config_tdata: [14:9] scale; [8]fwd_inv; [5:0]: cp_len 105 | // scale: shift right 6 bits : 0, 1, 2, 3, inv = 0 106 | // config_tdata = 0000 0011 0110 0001 0000 107 | .s_axis_config_tvalid(1'b1), // input s_axis_config_tvalid 108 | .s_axis_config_tready(), // ouput s_axis_config_tready 109 | .s_axis_data_tdata(idat), // input [31 : 0] s_axis_data_tdata 110 | .s_axis_data_tvalid(s_dat_val), // input s_axis_data_tvalid 111 | .s_axis_data_tready(s_dat_rdy), // ouput s_axis_data_tready 112 | .s_axis_data_tlast(1'b0), // input s_axis_data_tlast 113 | .m_axis_data_tdata(fft_datout), // ouput [31 : 0] m_axis_data_tdata 114 | .m_axis_data_tvalid(m_dat_val), // ouput m_axis_data_tvalid 115 | .m_axis_data_tready(m_dat_rdy), // input m_axis_data_tready 116 | .m_axis_data_tlast(m_dat_tlast), // ouput m_axis_data_tlast 117 | .event_frame_started(event_frame_started), // ouput event_frame_started 118 | .event_tlast_unexpected(), // ouput event_tlast_unexpected 119 | .event_tlast_missing(), // ouput event_tlast_missing 120 | .event_status_channel_halt(event_status_channel_halt), // ouput event_status_channel_halt 121 | .event_data_in_channel_halt(event_data_in_channel_halt), // ouput event_data_in_channel_halt 122 | .event_data_out_channel_halt(event_data_out_channel_halt)); // ouput event_data_out_channel_halt 123 | endmodule 124 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/iCFO_EstComp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:15:58 09/18/2012 7 | // Design Name: 8 | // Module Name: iCFO 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module iCFO_EstComp( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, // DAT_I_Im[31:16] DAT_I_Re[15:0] in format 5.11 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, // DAT_O_Im[31:16] DAT_O_Re[15:0] in format 5.11 28 | output reg CYC_O, STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | reg iCFO_ena, datsym_ena; 34 | wire [2:0] ifoff; 35 | wire iCFO_val; 36 | 37 | reg [31:0] iCFO_buf_comp [0:255]; 38 | reg [7:0] dat_cnt; 39 | reg [7:0] buf_wraddr; 40 | reg buf_wrfull; 41 | wire [7:0] buf_rdaddr; 42 | reg [7:0] buf_rdcnt; 43 | reg [7:0] buf_rdaddr_offset; 44 | reg buf_rdena; 45 | reg [31:0] idat; 46 | reg iena; 47 | wire istart, out_halt, datin_val; 48 | 49 | 50 | assign datin_val = (CYC_I) & STB_I & (WE_I); 51 | assign out_halt = STB_O & (~ACK_I); 52 | assign ACK_O = datin_val & (~out_halt); 53 | assign istart = CYC_I & (~CYC_I_pp); 54 | 55 | reg CYC_I_pp; 56 | always @(posedge CLK_I) begin 57 | if(RST_I) CYC_I_pp <= 1'b1; 58 | else CYC_I_pp <= CYC_I; 59 | end 60 | always @(posedge CLK_I) begin 61 | if(RST_I) idat <= 32'd0; 62 | else if (ACK_O) idat <= DAT_I; 63 | end 64 | always @(posedge CLK_I) begin 65 | if(RST_I) iena <= 1'b0; 66 | else if (ACK_O) iena <= 1'b1; 67 | else iena <= 1'b0; 68 | end 69 | 70 | always @(posedge CLK_I) begin 71 | if(RST_I) dat_cnt <= 8'd0; 72 | else if (istart) dat_cnt <= 8'd0; 73 | else if (ACK_O) dat_cnt <= dat_cnt + 1'b1; 74 | end 75 | 76 | always @(posedge CLK_I) begin 77 | if(RST_I) iCFO_ena <= 1'b0; 78 | else if (istart) iCFO_ena <= 1'b0; 79 | else if (ACK_O & (~datsym_ena)) iCFO_ena <= 1'b1; 80 | else if (dat_cnt == 8'd255) iCFO_ena <= 1'b0; 81 | end 82 | 83 | always @(posedge CLK_I) begin 84 | if(RST_I) datsym_ena <= 1'b0; 85 | else if (istart) datsym_ena <= 1'b0; 86 | else if (dat_cnt == 8'd255) datsym_ena <= 1'b1; 87 | end 88 | 89 | always @(posedge CLK_I) begin 90 | if (iena) iCFO_buf_comp[buf_wraddr] <= idat; 91 | end 92 | 93 | always @(posedge CLK_I) begin 94 | if(RST_I) buf_wraddr <= 8'd0; 95 | else if (istart) buf_wraddr <= 8'd0; 96 | else if ((dat_cnt == 8'd255) & ACK_O) buf_wraddr <= buf_wraddr + {3'b000,ifoff,2'b00}; 97 | else if (iena) buf_wraddr <= buf_wraddr + 1'b1; 98 | end 99 | 100 | always @(posedge CLK_I) begin 101 | if(RST_I) buf_wrfull <= 1'b0; 102 | else if (istart) buf_wrfull <= 1'b0; 103 | else if ((dat_cnt == 8'd255) & (iena)) buf_wrfull <= 1'b1; 104 | else if (buf_wrfull & iCFO_val ) buf_wrfull <= 1'b0; 105 | 106 | end 107 | 108 | always @(posedge CLK_I) begin 109 | if(RST_I) buf_rdena <= 1'b0; 110 | else if (istart) buf_rdena <= 1'b0; 111 | else if (buf_wrfull & iCFO_val) buf_rdena <= 1'b1; 112 | else if (buf_rdcnt == 8'd255) buf_rdena <= 1'b0; 113 | end 114 | 115 | always @(posedge CLK_I) begin 116 | if(RST_I) buf_rdaddr_offset <= 8'd0; 117 | else if (istart) buf_rdaddr_offset <= 8'd0; 118 | else if (buf_wrfull & iCFO_val) buf_rdaddr_offset <= buf_wraddr + {3'b000,ifoff,2'b00}; 119 | end 120 | 121 | always @(posedge CLK_I) begin 122 | if(RST_I) buf_rdcnt <= 8'd0; 123 | else if (istart) buf_rdcnt <= 8'd0; 124 | else if (buf_rdena &(~out_halt)) buf_rdcnt <= buf_rdcnt + 1'b1; 125 | end 126 | 127 | assign buf_rdaddr = buf_rdcnt + buf_rdaddr_offset; 128 | 129 | iCFO_est iCFO_Est_ins( 130 | .clk(CLK_I), .rst(RST_I), .ena_i(iCFO_ena), 131 | .sb_dat_i({idat[31],idat[15]}), //signed bit symbol:[1] :signed bit of imaginary part, [0] :signed bit of real part, 132 | .stb_i(STB_I), 133 | .dat_cnt(dat_cnt), 134 | .ifoff(ifoff), 135 | .dat_out_val(iCFO_val) 136 | ); 137 | 138 | always @(posedge CLK_I) begin 139 | if(RST_I) begin 140 | DAT_O <= 32'd0; 141 | STB_O <= 1'b0; 142 | end 143 | else if(buf_rdena) begin 144 | STB_O <= 1'b1; 145 | if ((~out_halt)) DAT_O <= iCFO_buf_comp[buf_rdaddr]; 146 | end 147 | else STB_O <= 1'b0; 148 | end 149 | 150 | reg frm_fin; 151 | always @(posedge CLK_I) begin 152 | if(RST_I) frm_fin <= 1'b0; 153 | else if (istart) frm_fin <= 1'b0; 154 | else if ((buf_rdcnt == 8'd255) &(buf_rdcnt == 8'd255) & (~CYC_I)) frm_fin <= 1'b1; 155 | end 156 | 157 | always @(posedge CLK_I) begin 158 | if(RST_I) CYC_O <= 1'b0; 159 | else if(istart) CYC_O <= 1'b1; 160 | else if(frm_fin) CYC_O <= 1'b0; 161 | end 162 | assign WE_O = CYC_O; 163 | 164 | 165 | 166 | endmodule 167 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/Pilots_Insert_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:54:49 12/05/2012 7 | // Design Name: 8 | // Module Name: Pilots_Insert_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Pilots_Insert_tb( 22 | ); 23 | 24 | reg rst, clk; 25 | reg we_i, stb_i, cyc_i; 26 | reg [31:0] dat_in; 27 | wire ack_o; 28 | 29 | 30 | wire [31:0] dat_out; 31 | wire we_o, stb_o, cyc_o; 32 | reg ack_i; 33 | 34 | Pilots_Insert UUT( 35 | .CLK_I(clk), .RST_I(rst), 36 | .DAT_I(dat_in), 37 | .WE_I(we_i), 38 | .STB_I(stb_i), 39 | .CYC_I(cyc_i), 40 | .ACK_O(ack_o), 41 | .DAT_O(dat_out), 42 | .WE_O(we_o), 43 | .STB_O(stb_o), 44 | .CYC_O(cyc_o), 45 | .ACK_I(ack_i) 46 | ); 47 | 48 | parameter NSAM = 10*(256+32); 49 | //reg [31:0] datin [NSAM - 1:0]; 50 | integer ii; 51 | integer Len, para_fin; 52 | 53 | 54 | initial begin 55 | rst = 1'b1; 56 | clk = 1'b0; 57 | we_i = 1'b0; 58 | stb_i = 1'b0; 59 | cyc_i = 1'b0; 60 | ii = 0; 61 | dat_in = 32'd0; 62 | 63 | // para_fin = $fopen("../../MATLAB/OFDM_SYS_tb/RemoveCP_tb/RemoveCP_datin_len.txt","r"); 64 | // $fscanf(para_fin, "%d ", Len); 65 | // $fclose(para_fin); 66 | Len = 400; 67 | // $readmemh("../../MATLAB/OFDM_SYS_tb/RemoveCP_tb/RTL_RemoveCP_datin.txt", datin); 68 | 69 | #25rst = 1'b0; 70 | end 71 | 72 | always #10 clk = ~clk; 73 | 74 | reg wr_datin, wr_frm_pp; 75 | 76 | reg wr_frm; 77 | initial begin 78 | wr_frm = 1'b0; 79 | wr_datin =1'b1; 80 | ack_i =1'b1; 81 | #200 ii=0; 82 | wr_frm = 1'b1; 83 | end 84 | 85 | 86 | always @(posedge clk) begin 87 | if(rst) begin 88 | ii <= 0; 89 | dat_in <= 32'd1; 90 | wr_frm_pp <= 1'b0; 91 | end 92 | else if(wr_frm) begin 93 | cyc_i <= 1'b1; 94 | wr_frm_pp <= wr_frm; 95 | 96 | if (~wr_datin) begin 97 | stb_i <= 1'b0; 98 | cyc_i <= 1'b0; 99 | we_i <= 1'b0; 100 | end 101 | else if (~wr_frm_pp) begin 102 | wr_frm_pp <= wr_frm; 103 | ii <= ii+1; 104 | stb_i <= 1'b1; 105 | cyc_i <= 1'b1; 106 | we_i <= 1'b1; 107 | end 108 | else if ((ii == Len)&(ack_o)) begin 109 | we_i <= 1'b0; 110 | stb_i <= 1'b0; 111 | cyc_i <= 1'b0; 112 | wr_frm <= 1'b0; 113 | end 114 | else if (ack_o) begin 115 | dat_in <= dat_in + 1'b1; 116 | ii <= ii+1; 117 | stb_i <= 1'b1; 118 | cyc_i <= 1'b1; 119 | we_i <= 1'b1; 120 | end 121 | end 122 | else begin 123 | wr_frm_pp <= wr_frm; 124 | we_i <= 1'b0; 125 | stb_i <= 1'b0; 126 | cyc_i <= 1'b0; 127 | end 128 | 129 | end 130 | 131 | /* 132 | initial begin 133 | wr_datin =1'b1; 134 | @(posedge ack_o); 135 | #210; 136 | wr_datin =1'b0; 137 | #100; 138 | wr_datin =1'b1; 139 | #400; 140 | wr_datin =1'b0; 141 | #200; 142 | wr_datin =1'b1; 143 | #300; 144 | wr_datin =1'b0; 145 | #100; 146 | wr_datin =1'b1; 147 | end 148 | 149 | 150 | initial begin 151 | ack_i =1'b0; 152 | @(posedge stb_o); 153 | #5; 154 | ack_i =1'b0; 155 | #100; 156 | ack_i =1'b1; 157 | #500; 158 | ack_i =1'b0; 159 | #200; 160 | ack_i =1'b1; 161 | #300; 162 | ack_i =1'b0; 163 | #700; 164 | ack_i =1'b1; 165 | end 166 | */ 167 | /* 168 | integer datout_fo, datout_cnt; 169 | 170 | initial begin 171 | datout_cnt = 0; 172 | datout_fo = $fopen("../../MATLAB/OFDM_SYS_tb/RemoveCP/RTL_RemoveCP_datout.txt"); 173 | forever begin 174 | @(posedge clk); 175 | if ((~we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 176 | $fwrite(datout_fo,"%d ",$signed(dat_out)); 177 | datout_cnt = datout_cnt + 1; 178 | end 179 | end 180 | end 181 | */ 182 | 183 | initial begin 184 | ack_i = 0; 185 | forever begin 186 | @(posedge clk); 187 | if (stb_o) begin 188 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 189 | ack_i = 1'b1; 190 | end 191 | end 192 | end 193 | 194 | initial begin 195 | forever begin 196 | @(posedge clk); 197 | if (dat_in == 31'd193) begin 198 | ack_i = 1'b0; 199 | #645 ack_i = 1'b1; 200 | end 201 | end 202 | end 203 | 204 | initial begin 205 | forever begin 206 | @(posedge clk); 207 | if (dat_in == 31'd80) begin 208 | ack_i = 1'b0; 209 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 210 | ack_i = 1'b1; 211 | end 212 | end 213 | end 214 | 215 | reg stop_chk; 216 | initial begin 217 | stop_chk = 1'b0; 218 | #10000 stop_chk = 1'b1; 219 | end 220 | initial begin 221 | forever begin 222 | @(posedge clk); 223 | if (stop_chk) begin 224 | //$fclose(datout_fo); 225 | $stop; 226 | end 227 | end 228 | end 229 | 230 | endmodule 231 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/OFDM_RX_802_11.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:56:39 04/15/2013 7 | // Design Name: 8 | // Module Name: OFDM_RX_802_16 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module OFDM_RX_802_11( 22 | input CLK_I, RST_I, 23 | input [15:0] I_CH_I, 24 | input [15:0] Q_CH_I, 25 | input CYC_I, WE_I, STB_I, 26 | output ACK_O, 27 | 28 | input [3:0] SNR, 29 | 30 | output [7:0] DAT_O, 31 | output CYC_O, STB_O, 32 | output WE_O, 33 | input ACK_I 34 | ); 35 | 36 | wire [31:0] Synch_DAT_O; 37 | wire Synch_WE_O; 38 | wire Synch_STB_O; 39 | wire Synch_CYC_O; 40 | wire Synch_ACK_I; 41 | //wire [31:0] FRE_O; 42 | //wire FRE_O_val; 43 | Synch Synch_ins( 44 | .CLK_I(CLK_I), .RST_I(RST_I), 45 | .DAT_I({Q_CH_I,I_CH_I}), 46 | .STB_I(STB_I), 47 | .CYC_I(CYC_I), 48 | .ACK_O(ACK_O), 49 | 50 | .DAT_O(Synch_DAT_O), 51 | .WE_O (Synch_WE_O ), 52 | .STB_O(Synch_STB_O), 53 | .CYC_O(Synch_CYC_O), 54 | .ACK_I(Synch_ACK_I) 55 | 56 | // .SNR(SNR), //Signal to Noise Ratio 57 | // .FRE_O(FRE_O), 58 | // .FRE_O_val(FRE_O_val) 59 | ); 60 | /* 61 | wire [31:0] FreComp_DAT_O; 62 | wire FreComp_WE_O; 63 | wire FreComp_STB_O; 64 | wire FreComp_CYC_O; 65 | wire FreComp_ACK_I; 66 | FreComp FreComp_ins( 67 | .CLK_I(CLK_I), .RST_I(RST_I), 68 | .DAT_I(Synch_DAT_O), 69 | .WE_I (Synch_WE_O), 70 | .STB_I(Synch_STB_O), 71 | .CYC_I(Synch_CYC_O), 72 | .ACK_O(Synch_ACK_I), 73 | 74 | .DAT_O(FreComp_DAT_O), 75 | .WE_O (FreComp_WE_O ), 76 | .STB_O(FreComp_STB_O), 77 | .CYC_O(FreComp_CYC_O), 78 | .ACK_I(FreComp_ACK_I), 79 | 80 | .FRE_I(FRE_O), 81 | .FRE_I_nd(FRE_O_val) 82 | ); 83 | */ 84 | wire [31:0] RemoveCP_DAT_O; 85 | wire RemoveCP_WE_O; 86 | wire RemoveCP_STB_O; 87 | wire RemoveCP_CYC_O; 88 | wire RemoveCP_ACK_I; 89 | RemoveCP RemoveCP_ins( 90 | .CLK_I(CLK_I), .RST_I(RST_I), 91 | .DAT_I(Synch_DAT_O), 92 | .WE_I (Synch_WE_O), 93 | .STB_I(Synch_STB_O), 94 | .CYC_I(Synch_CYC_O), 95 | .ACK_O(Synch_ACK_I), 96 | 97 | .DAT_O(RemoveCP_DAT_O), 98 | .WE_O (RemoveCP_WE_O ), 99 | .STB_O(RemoveCP_STB_O), 100 | .CYC_O(RemoveCP_CYC_O), 101 | .ACK_I(RemoveCP_ACK_I) 102 | ); 103 | 104 | 105 | wire [31:0] FFT_Demod_DAT_O; 106 | wire FFT_Demod_WE_O; 107 | wire FFT_Demod_STB_O; 108 | wire FFT_Demod_CYC_O; 109 | wire FFT_Demod_ACK_I; 110 | FFT FFT_Demod_ins( 111 | .CLK_I(CLK_I), .RST_I(RST_I), 112 | .DAT_I(RemoveCP_DAT_O), 113 | .WE_I (RemoveCP_WE_O), 114 | .STB_I(RemoveCP_STB_O), 115 | .CYC_I(RemoveCP_CYC_O), 116 | .ACK_O(RemoveCP_ACK_I), 117 | 118 | .DAT_O(FFT_Demod_DAT_O), 119 | .WE_O (FFT_Demod_WE_O ), 120 | .STB_O(FFT_Demod_STB_O), 121 | .CYC_O(FFT_Demod_CYC_O), 122 | .ACK_I(FFT_Demod_ACK_I) 123 | ); 124 | 125 | 126 | wire [31:0] iCFO_EstComp_DAT_O; 127 | wire iCFO_EstComp_WE_O; 128 | wire iCFO_EstComp_STB_O; 129 | wire iCFO_EstComp_CYC_O; 130 | wire iCFO_EstComp_ACK_I; 131 | //iCFO_EstComp iCFO_EstComp_ins( 132 | Interface_BB iCFO_EstComp_ins( 133 | .CLK_I(CLK_I), .RST_I(RST_I), 134 | .DAT_I(FFT_Demod_DAT_O), 135 | .WE_I (FFT_Demod_WE_O), 136 | .STB_I(FFT_Demod_STB_O), 137 | .CYC_I(FFT_Demod_CYC_O), 138 | .ACK_O(FFT_Demod_ACK_I), 139 | 140 | .DAT_O(iCFO_EstComp_DAT_O), 141 | .WE_O (iCFO_EstComp_WE_O ), 142 | .STB_O(iCFO_EstComp_STB_O), 143 | .CYC_O(iCFO_EstComp_CYC_O), 144 | .ACK_I(iCFO_EstComp_ACK_I) 145 | ); 146 | 147 | wire [31:0] Ch_EstEqu_DAT_O; 148 | wire Ch_EstEqu_WE_O; 149 | wire Ch_EstEqu_STB_O; 150 | wire Ch_EstEqu_CYC_O; 151 | wire Ch_EstEqu_ACK_I; 152 | Ch_EstEqu Ch_EstEqu_ins( 153 | .CLK_I(CLK_I), .RST_I(RST_I), 154 | .DAT_I(iCFO_EstComp_DAT_O), 155 | .WE_I (iCFO_EstComp_WE_O), 156 | .STB_I(iCFO_EstComp_STB_O), 157 | .CYC_I(iCFO_EstComp_CYC_O), 158 | .ACK_O(iCFO_EstComp_ACK_I), 159 | 160 | .DAT_O(Ch_EstEqu_DAT_O), 161 | .WE_O (Ch_EstEqu_WE_O ), 162 | .STB_O(Ch_EstEqu_STB_O), 163 | .CYC_O(Ch_EstEqu_CYC_O), 164 | .ACK_I(Ch_EstEqu_ACK_I) 165 | ); 166 | 167 | wire [31:0] PhaseTrack_DAT_O; 168 | wire PhaseTrack_WE_O; 169 | wire PhaseTrack_STB_O; 170 | wire PhaseTrack_CYC_O; 171 | wire PhaseTrack_ACK_I; 172 | PhaseTrack PhaseTrack_ins( 173 | .CLK_I(CLK_I), .RST_I(RST_I), 174 | .DAT_I(Ch_EstEqu_DAT_O), 175 | .WE_I (Ch_EstEqu_WE_O), 176 | .STB_I(Ch_EstEqu_STB_O), 177 | .CYC_I(Ch_EstEqu_CYC_O), 178 | .ACK_O(Ch_EstEqu_ACK_I), 179 | 180 | .DAT_O(PhaseTrack_DAT_O), 181 | .WE_O (PhaseTrack_WE_O ), 182 | .STB_O(PhaseTrack_STB_O), 183 | .CYC_O(PhaseTrack_CYC_O), 184 | .ACK_I(PhaseTrack_ACK_I), 185 | .ALLOC_VEC({{6{2'b11}}, 2'b01, {13{2'b11}}, 2'b01, {5{2'b11}}, {5{2'b11}}, 2'b10, {13{2'b11}}, 2'b01, {6{2'b11}}}) 186 | 187 | ); 188 | 189 | wire [7:0] DataSymDem_DAT_O; 190 | wire DataSymDem_WE_O; 191 | wire DataSymDem_STB_O; 192 | wire DataSymDem_CYC_O; 193 | wire DataSymDem_ACK_I; 194 | DataSymDem DataSymDem_ins( 195 | .CLK_I(CLK_I), .RST_I(RST_I), 196 | .DAT_I(PhaseTrack_DAT_O), 197 | .WE_I (PhaseTrack_WE_O), 198 | .STB_I(PhaseTrack_STB_O), 199 | .CYC_I(PhaseTrack_CYC_O), 200 | .ACK_O(PhaseTrack_ACK_I), 201 | 202 | .DAT_O(DataSymDem_DAT_O), 203 | .WE_O (DataSymDem_WE_O ), 204 | .STB_O(DataSymDem_STB_O), 205 | .CYC_O(DataSymDem_CYC_O), 206 | .ACK_I(DataSymDem_ACK_I) 207 | ); 208 | 209 | assign DataSymDem_ACK_I = ACK_I; 210 | assign DAT_O = DataSymDem_DAT_O; 211 | assign WE_O = DataSymDem_WE_O; 212 | assign STB_O = DataSymDem_STB_O; 213 | assign CYC_O = DataSymDem_CYC_O; 214 | 215 | 216 | endmodule 217 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Synch_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:34:26 04/19/2012 7 | // Design Name: 8 | // Module Name: Synch_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Synch_tb( 22 | ); 23 | reg rst, clk; 24 | reg cyc_i; 25 | reg [31:0] dat_in; 26 | 27 | wire ack_o; 28 | wire [43:0] p_metric; 29 | wire [21:0] r_metric; 30 | wire [31:0] fre_o; 31 | reg [3:0] SNR; 32 | 33 | wire [31:0] dat_out; 34 | wire we_o, stb_o, cyc_o; 35 | reg ack_i; 36 | 37 | wire stb_i = cyc_i; 38 | 39 | Synch UUT( 40 | .CLK_I(clk), .RST_I(rst), 41 | .DAT_I(dat_in), 42 | .CYC_I(cyc_i), 43 | .STB_I(stb_i), 44 | .ACK_O(ack_o), 45 | 46 | .DAT_O(dat_out), 47 | .WE_O(we_o), 48 | .STB_O(stb_o), 49 | .CYC_O(cyc_o), 50 | .ACK_I(ack_i) 51 | 52 | //.SNR(SNR) 53 | 54 | ); 55 | parameter NSAM = 10*(256+32); 56 | reg [15:0] datin_Re [NSAM - 1:0]; 57 | reg [15:0] datin_Im [NSAM - 1:0]; 58 | integer ii; 59 | integer NLOP, Len, para_fin; 60 | 61 | 62 | initial begin 63 | rst = 1'b1; 64 | clk = 1'b0; 65 | cyc_i = 1'b0; 66 | ii = 0; 67 | dat_in = 32'd0; 68 | 69 | para_fin = $fopen("./MATLAB/RTL_OFDM_RX_datin_len.txt","r"); 70 | $fscanf(para_fin, "%d ", NLOP); 71 | $fscanf(para_fin, "%d ", Len); 72 | $fscanf(para_fin, "%d ", SNR); 73 | $fclose(para_fin); 74 | 75 | 76 | $readmemh("./MATLAB/RTL_OFDM_RX_datin_Re.txt", datin_Re); 77 | $readmemh("./MATLAB/RTL_OFDM_RX_datin_Im.txt", datin_Im); 78 | #25rst = 1'b0; 79 | end 80 | 81 | always #10 clk = ~clk; 82 | 83 | reg wr_frm; 84 | initial begin 85 | wr_frm = 1'b0; 86 | wr_datin =1'b1; 87 | ack_i = 1'b1; 88 | #200 ii=0; 89 | wr_frm = 1'b1; 90 | end 91 | 92 | reg wr_datin, wr_frm_pp; 93 | 94 | always @(posedge clk) begin 95 | if(rst) begin 96 | ii <= 0; 97 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 98 | wr_frm_pp <= 1'b0; 99 | end 100 | else if(wr_frm) begin 101 | cyc_i <= 1'b1; 102 | 103 | if (ii < Len) begin 104 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 105 | ii <= ii+1; 106 | end 107 | else if (ii == Len) 108 | begin 109 | wr_frm <= 0; 110 | cyc_i <= 1'b0; 111 | end 112 | end 113 | end 114 | 115 | 116 | integer datout_Re_fo, datout_Im_fo, datout_cnt; 117 | 118 | initial begin 119 | datout_cnt = 0; 120 | datout_Re_fo = $fopen("./MATLAB/RTL_Synch_datout_Re.txt"); 121 | datout_Im_fo = $fopen("./MATLAB/RTL_Synch_datout_Im.txt"); 122 | forever begin 123 | @(posedge clk); 124 | if ((we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 125 | $fwrite(datout_Re_fo,"%d ",$signed(dat_out[15:0])); 126 | $fwrite(datout_Im_fo,"%d ",$signed(dat_out[31:16])); 127 | datout_cnt = datout_cnt + 1; 128 | end 129 | end 130 | end 131 | /* 132 | wire [15:0] ACR_mult_Re = UUT.ACRMult_Re; 133 | wire [15:0] ACR_mult_Im = UUT.ACRMult_Im; 134 | wire [15:0] ABS_rxin = UUT.rx_abs;*/ 135 | 136 | wire [21:0] P_metric_Re = UUT.P_Re; 137 | wire [21:0] P_metric_Im = UUT.P_Im; 138 | wire [21:0] R_metric = UUT.R_Metric; 139 | wire metric_rd = UUT.CM_val; 140 | 141 | /*wire [21:0] R_Metric_thr = UUT.Coarse_Time_Synch_ins.R_Metric_thr; 142 | wire [22:0] P_Metric_mag = UUT.P_Metric_mag; 143 | wire appr_mag_val = UUT.P_Metric_mag_val;*/ 144 | 145 | wire [7:0] CR_out_mag = UUT.Fine_Time_Synch_ins.CR_out_mag; 146 | wire CR_out_mag_val = UUT.Fine_Time_Synch_ins.CR_out_mag_val; 147 | 148 | 149 | integer P_metric_Re_fo, P_metric_Im_fo, R_metric_fo, metric_cnt; 150 | integer ACR_mult_Re_fo, ACR_mult_Im_fo; 151 | integer ABS_rxin_fo; 152 | integer R_metric_thr_fo, P_metric_mag_fo; 153 | integer CR_out_mag_fo; 154 | initial begin 155 | /*ACR_mult_Re_fo = $fopen("./MATLAB/RTL_Synch_ACR_mult_Re.txt"); 156 | ACR_mult_Im_fo = $fopen("./MATLAB/RTL_Synch_ACR_mult_Im.txt"); 157 | ABS_rxin_fo = $fopen("./MATLAB/RTL_Synch_ABS_rxin.txt");*/ 158 | P_metric_Re_fo = $fopen("./MATLAB/RTL_Synch_P_metric_Re.txt"); 159 | P_metric_Im_fo = $fopen("./MATLAB/RTL_Synch_P_metric_Im.txt"); 160 | R_metric_fo = $fopen("./MATLAB/RTL_Synch_R_metric.txt"); 161 | metric_cnt = 0; 162 | //P_metric_mag_fo = $fopen("./MATLAB/RTL_Synch_P_Metric_mag.txt"); 163 | //R_metric_thr_fo = $fopen("./MATLAB/RTL_Synch_R_Metric_thr.txt"); 164 | CR_out_mag_fo = $fopen("./MATLAB/RTL_Synch_CR_out_mag.txt"); 165 | 166 | 167 | forever begin 168 | @(posedge clk); 169 | if (metric_rd) begin 170 | /*$fwrite(ACR_mult_Re_fo,"%d ", $signed(ACR_mult_Re)); 171 | $fwrite(ACR_mult_Im_fo,"%d ", $signed(ACR_mult_Im)); 172 | $fwrite(ABS_rxin_fo, "%d ", ABS_rxin); */ 173 | $fwrite(P_metric_Re_fo,"%d ", $signed(P_metric_Re)); 174 | $fwrite(P_metric_Im_fo,"%d ", $signed(P_metric_Im)); 175 | $fwrite(R_metric_fo, "%d ", R_metric); 176 | metric_cnt = metric_cnt +1; 177 | end 178 | /*if(appr_mag_val) begin 179 | $fwrite(P_metric_mag_fo,"%d ", P_Metric_mag); 180 | $fwrite(R_metric_thr_fo,"%d ", R_Metric_thr); 181 | end*/ 182 | 183 | if(CR_out_mag_val) begin 184 | $fwrite(CR_out_mag_fo,"%d ", CR_out_mag); 185 | end 186 | end 187 | end 188 | 189 | reg stop_chk; 190 | initial begin 191 | stop_chk = 1'b0; 192 | #30000 stop_chk = 1'b1; 193 | end 194 | initial begin 195 | forever begin 196 | @(posedge clk); 197 | if (stop_chk) begin 198 | /*$fclose(ACR_mult_Re_fo); 199 | $fclose(ACR_mult_Im_fo); 200 | $fclose(ABS_rxin_fo);*/ 201 | $fclose(P_metric_Re_fo); 202 | $fclose(P_metric_Im_fo); 203 | $fclose(R_metric_fo); 204 | /*$fclose(P_metric_mag_fo); 205 | $fclose(R_metric_thr_fo);*/ 206 | $fclose(CR_out_mag_fo); 207 | 208 | $fclose(datout_Re_fo); 209 | $fclose(datout_Im_fo); 210 | $stop; 211 | end 212 | end 213 | end 214 | 215 | endmodule 216 | 217 | 218 | 219 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/IFFT_Mod_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:42:03 12/06/2012 7 | // Design Name: 8 | // Module Name: IFFT_Mod_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module IFFT_Mod_tb( 22 | ); 23 | 24 | reg rst, clk; 25 | reg we_i, stb_i, cyc_i; 26 | reg [31:0] dat_in; 27 | reg ack_i; 28 | 29 | wire [31:0] Pilots_Insert_dat_out; 30 | wire Pilots_Insert_we_o; 31 | wire Pilots_Insert_stb_o; 32 | wire Pilots_Insert_cyc_o; 33 | 34 | wire Pilots_Insert_ack_o; 35 | wire Pilots_Insert_ack_i; 36 | 37 | Pilots_Insert Pilots_Insert_UUT( 38 | .CLK_I(clk), .RST_I(rst), 39 | .DAT_I(dat_in), 40 | .WE_I(we_i), 41 | .STB_I(stb_i), 42 | .CYC_I(cyc_i), 43 | .ACK_O(Pilots_Insert_ack_o), 44 | .DAT_O(Pilots_Insert_dat_out), 45 | .WE_O (Pilots_Insert_we_o), 46 | .STB_O(Pilots_Insert_stb_o), 47 | .CYC_O(Pilots_Insert_cyc_o), 48 | .ACK_I(Pilots_Insert_ack_i) 49 | ); 50 | 51 | 52 | wire [31:0] IFFT_Mod_dat_in = Pilots_Insert_dat_out; 53 | wire IFFT_Mod_we_i = Pilots_Insert_we_o; 54 | wire IFFT_Mod_stb_i = Pilots_Insert_stb_o; 55 | wire IFFT_Mod_cyc_i = Pilots_Insert_cyc_o; 56 | wire IFFT_Mod_ack_i = ack_i; 57 | wire IFFT_Mod_ack_o; 58 | assign Pilots_Insert_ack_i = IFFT_Mod_ack_o; 59 | wire [31:0] IFFT_Mod_dat_out; 60 | wire IFFT_Mod_we_o; 61 | wire IFFT_Mod_stb_o; 62 | wire IFFT_Mod_cyc_o; 63 | 64 | IFFT_Mod UUT( 65 | .CLK_I(clk), .RST_I(rst), 66 | .DAT_I(IFFT_Mod_dat_in), 67 | .WE_I (IFFT_Mod_we_i), 68 | .STB_I(IFFT_Mod_stb_i), 69 | .CYC_I(IFFT_Mod_cyc_i), 70 | .ACK_O(IFFT_Mod_ack_o), 71 | .DAT_O(IFFT_Mod_dat_out), 72 | .WE_O (IFFT_Mod_we_o), 73 | .STB_O(IFFT_Mod_stb_o), 74 | .CYC_O(IFFT_Mod_cyc_o), 75 | .ACK_I(IFFT_Mod_ack_i) 76 | ); 77 | 78 | parameter NSAM = 10*(256+32); 79 | //reg [31:0] datin [NSAM - 1:0]; 80 | integer ii; 81 | integer Len, para_fin; 82 | 83 | 84 | initial begin 85 | rst = 1'b1; 86 | clk = 1'b0; 87 | we_i = 1'b0; 88 | stb_i = 1'b0; 89 | cyc_i = 1'b0; 90 | ii = 0; 91 | dat_in = 32'd0; 92 | 93 | // para_fin = $fopen("../../MATLAB/OFDM_SYS_tb/RemoveCP_tb/RemoveCP_datin_len.txt","r"); 94 | // $fscanf(para_fin, "%d ", Len); 95 | // $fclose(para_fin); 96 | Len = 576; 97 | // $readmemh("../../MATLAB/OFDM_SYS_tb/RemoveCP_tb/RTL_RemoveCP_datin.txt", datin); 98 | 99 | #25rst = 1'b0; 100 | end 101 | 102 | always #10 clk = ~clk; 103 | 104 | reg wr_datin, wr_frm_pp; 105 | 106 | reg wr_frm; 107 | initial begin 108 | wr_frm = 1'b0; 109 | wr_datin =1'b1; 110 | ack_i =1'b1; 111 | #200 ii=0; 112 | wr_frm = 1'b1; 113 | end 114 | 115 | 116 | always @(posedge clk) begin 117 | if(rst) begin 118 | ii <= 0; 119 | dat_in <= 32'd1; 120 | wr_frm_pp <= 1'b0; 121 | end 122 | else if(wr_frm) begin 123 | cyc_i <= 1'b1; 124 | wr_frm_pp <= wr_frm; 125 | 126 | if (~wr_datin) begin 127 | stb_i <= 1'b0; 128 | cyc_i <= 1'b0; 129 | we_i <= 1'b0; 130 | end 131 | else if (~wr_frm_pp) begin 132 | wr_frm_pp <= wr_frm; 133 | ii <= ii+1; 134 | stb_i <= 1'b1; 135 | cyc_i <= 1'b1; 136 | we_i <= 1'b1; 137 | end 138 | else if ((ii == Len)&(Pilots_Insert_ack_o)) begin 139 | we_i <= 1'b0; 140 | stb_i <= 1'b0; 141 | cyc_i <= 1'b0; 142 | wr_frm <= 1'b0; 143 | end 144 | else if (Pilots_Insert_ack_o) begin 145 | dat_in <= dat_in + 1'b1; 146 | ii <= ii+1; 147 | stb_i <= 1'b1; 148 | cyc_i <= 1'b1; 149 | we_i <= 1'b1; 150 | end 151 | end 152 | else begin 153 | wr_frm_pp <= wr_frm; 154 | we_i <= 1'b0; 155 | stb_i <= 1'b0; 156 | cyc_i <= 1'b0; 157 | end 158 | 159 | end 160 | 161 | /* 162 | initial begin 163 | wr_datin =1'b1; 164 | @(posedge ack_o); 165 | #210; 166 | wr_datin =1'b0; 167 | #100; 168 | wr_datin =1'b1; 169 | #400; 170 | wr_datin =1'b0; 171 | #200; 172 | wr_datin =1'b1; 173 | #300; 174 | wr_datin =1'b0; 175 | #100; 176 | wr_datin =1'b1; 177 | end 178 | 179 | 180 | initial begin 181 | ack_i =1'b0; 182 | @(posedge stb_o); 183 | #5; 184 | ack_i =1'b0; 185 | #100; 186 | ack_i =1'b1; 187 | #500; 188 | ack_i =1'b0; 189 | #200; 190 | ack_i =1'b1; 191 | #300; 192 | ack_i =1'b0; 193 | #700; 194 | ack_i =1'b1; 195 | end 196 | */ 197 | /* 198 | integer datout_fo, datout_cnt; 199 | 200 | initial begin 201 | datout_cnt = 0; 202 | datout_fo = $fopen("../../MATLAB/OFDM_SYS_tb/RemoveCP/RTL_RemoveCP_datout.txt"); 203 | forever begin 204 | @(posedge clk); 205 | if ((~we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 206 | $fwrite(datout_fo,"%d ",$signed(dat_out)); 207 | datout_cnt = datout_cnt + 1; 208 | end 209 | end 210 | end 211 | */ 212 | 213 | /*initial begin 214 | ack_i = 0; 215 | forever begin 216 | @(posedge clk); 217 | if (stb_o) begin 218 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 219 | ack_i = 1'b1; 220 | end 221 | end 222 | end 223 | initial begin 224 | forever begin 225 | @(posedge clk); 226 | if (dat_in == 31'd193) begin 227 | ack_i = 1'b0; 228 | #645 ack_i = 1'b1; 229 | end 230 | end 231 | end 232 | initial begin 233 | forever begin 234 | @(posedge clk); 235 | if (dat_in == 31'd80) begin 236 | ack_i = 1'b0; 237 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 238 | ack_i = 1'b1; 239 | end 240 | end 241 | end 242 | */ 243 | 244 | reg stop_chk; 245 | initial begin 246 | stop_chk = 1'b0; 247 | #30000 stop_chk = 1'b1; 248 | end 249 | initial begin 250 | forever begin 251 | @(posedge clk); 252 | if (stop_chk) begin 253 | //$fclose(datout_fo); 254 | $stop; 255 | end 256 | end 257 | end 258 | 259 | endmodule 260 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Ch_EstEqu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:44:28 11/06/2012 7 | // Design Name: 8 | // Module Name: Ch_EstEqu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ch_EstEqu( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, // DAT_I_Im[31:16] DAT_I_Re[15:0] in format 1.15 (Q5.11) 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, // DAT_O_Im[31:16] DAT_O_Re[15:0] in format 3.13 (Q10.6) 28 | output reg CYC_O,STB_O, 29 | output WE_O, 30 | input ACK_I 31 | ); 32 | 33 | parameter LP_P = 16'h3fff; // +1 in Q2.14 34 | parameter LP_N = 16'hc001; // -1 in Q2.14 35 | reg [1:0] lp [0:51]; //[1] :signed bit of imaginary part, [0] :signed bit of real part of long preamble, 36 | initial $readmemh("./MY_SOURCES/ChEstEqu_lpre.txt", lp); 37 | //reg [7:0] reorder [0:199]; //[1] :signed bit of imaginary part, [0] :signed bit of real part of long preamble, 38 | //initial $readmemh("./MY_SOURCES/reorder_map.txt", reorder); 39 | 40 | reg [31:0] idat; 41 | reg iena; 42 | wire istart, out_halt, datin_val; 43 | 44 | assign datin_val = (WE_I) & STB_I & CYC_I; 45 | assign out_halt = STB_O & (~ACK_I); 46 | assign ACK_O = datin_val & (~out_halt); 47 | assign istart = CYC_I & (~CYC_I_pp); 48 | 49 | reg CYC_I_pp; 50 | always @(posedge CLK_I) begin 51 | if(RST_I) CYC_I_pp <= 1'b1; 52 | else CYC_I_pp <= CYC_I; 53 | end 54 | always @(posedge CLK_I) begin 55 | if(RST_I) idat <= 32'd0; 56 | else if (ACK_O) idat <= DAT_I; 57 | end 58 | always @(posedge CLK_I) begin 59 | if(RST_I) iena <= 1'b0; 60 | else if (ACK_O) iena <= 1'b1; 61 | else iena <= 1'b0; 62 | end 63 | 64 | 65 | wire [31:0] lg_pre; 66 | wire [5:0] pre_rdcnt; 67 | 68 | reg [31:0] ch_cof_mem [0:51]; 69 | wire [31:0] ch_cof; 70 | wire [5:0] ch_cof_rdcnt; 71 | reg [5:0] ch_cof_wrcnt; 72 | 73 | wire ch_est; 74 | reg ch_equ; 75 | 76 | wire [31:0] Ch_CmxMul_A; //[31:16]: imaginary part, [15:0]: real part 77 | wire [31:0] Ch_CmxMul_B; //[31:16]: imaginary part, [15:0]: real part 78 | wire [79:0] Ch_CmxMul_dout; //[72:40]: imaginary part, [32:0]: real part 79 | wire Ch_CmxMul_ival; 80 | wire Ch_CmxMul_oval; 81 | 82 | wire [15:0] mult_Re; 83 | wire [15:0] mult_Im; 84 | 85 | 86 | reg [5:0] dat_cnt; 87 | always@(posedge CLK_I) begin 88 | if (RST_I) dat_cnt <=6'd0; 89 | else if (iena) dat_cnt <= dat_cnt + 1'b1; 90 | else if (istart) dat_cnt <=6'd0; 91 | end 92 | 93 | reg car_val; // used carriers in OFDM symbol 94 | always@(posedge CLK_I) begin 95 | if (RST_I) car_val <= 1'b0; 96 | else if (istart) car_val <= 1'b0; 97 | else if (iena) begin 98 | if (dat_cnt == 6'd0) car_val <= 1'b1; 99 | else if (dat_cnt == 6'd26) car_val <= 1'b0; 100 | else if (dat_cnt == 6'd37) car_val <= 1'b1; 101 | else if (dat_cnt == 6'd63) car_val <= 1'b0; 102 | end 103 | end 104 | 105 | assign ch_est = iena & (~ch_equ); 106 | always@(posedge CLK_I) begin 107 | if (RST_I) ch_equ <= 1'b0; 108 | else if (istart) ch_equ <= 1'b0; 109 | else if (iena & (dat_cnt == 6'd63)) ch_equ <= 1'b1; 110 | else if (~CYC_I) ch_equ <= 1'b0; 111 | end 112 | 113 | reg [5:0] car_cnt; 114 | always@(posedge CLK_I) begin 115 | if (RST_I) car_cnt <= 6'd0; 116 | else if (istart) car_cnt <= 6'd0; 117 | else if (iena & (car_cnt == 6'd51)) car_cnt <= 6'd0; 118 | else if (iena & car_val) car_cnt <= car_cnt + 1'b1; 119 | 120 | end 121 | 122 | assign pre_rdcnt = (ch_est)? car_cnt :6'd0; 123 | //assign lg_pre[31:16] = (lp[pre_rdcnt][1])? LP_N: LP_P; 124 | assign lg_pre[31:16] = 16'd0; 125 | assign lg_pre[15:0] = (lp[pre_rdcnt][0])? LP_N: LP_P; 126 | 127 | assign ch_cof = ch_cof_mem[ch_cof_rdcnt]; 128 | assign ch_cof_rdcnt = (ch_equ)? car_cnt:6'd0; 129 | always@(posedge CLK_I) begin 130 | if (RST_I) ch_cof_wrcnt <= 6'd0; 131 | else if (istart) ch_cof_wrcnt <= 6'd0; 132 | else if (Ch_CmxMul_oval & (~(ch_cof_wrcnt == 6'd52))) begin 133 | ch_cof_mem[ch_cof_wrcnt] <= {mult_Im, mult_Re}; 134 | ch_cof_wrcnt <= ch_cof_wrcnt + 1'b1; 135 | end 136 | end 137 | 138 | assign mult_Re = Ch_CmxMul_dout[30:15]; // Q6.10 - Q10.6 139 | assign mult_Im = Ch_CmxMul_dout[70:55]; // Q6.10 - Q10.6 140 | 141 | assign Ch_CmxMul_A[15:0] = idat[15:0]; 142 | assign Ch_CmxMul_A[31:16] = (ch_est)? (~idat[31:16] + 1'b1) : idat[31:16]; 143 | assign Ch_CmxMul_B = (ch_est)? lg_pre : ch_cof; 144 | assign Ch_CmxMul_ival = car_val; 145 | 146 | Ch_CmxMul Ch_CmxMul_ins( 147 | .aclk(CLK_I), // input aclk 148 | .aresetn(~RST_I), // input aresetn 149 | .aclken(~out_halt), // input aclken 150 | .s_axis_a_tvalid(Ch_CmxMul_ival), // input s_axis_a_tvalid 151 | .s_axis_a_tdata(Ch_CmxMul_A), // input [31 : 0] s_axis_a_tdata 152 | .s_axis_b_tvalid(Ch_CmxMul_ival), // input s_axis_b_tvalid 153 | .s_axis_b_tdata(Ch_CmxMul_B), // input [31 : 0] s_axis_b_tdata 154 | .m_axis_dout_tvalid(Ch_CmxMul_oval), // ouput m_axis_dout_tvalid 155 | .m_axis_dout_tdata(Ch_CmxMul_dout)); // ouput [79 : 0] m_axis_dout_tdata 156 | 157 | 158 | reg [5:0] ch_equ_delay; // because of multiplier latency. 159 | always @(posedge CLK_I) begin 160 | if(RST_I) ch_equ_delay <= 6'd0; 161 | else if (CYC_O) ch_equ_delay <= {ch_equ, ch_equ_delay[5:1]}; 162 | end 163 | wire ch_equ_oval = ch_equ_delay[0]; 164 | 165 | always @(posedge CLK_I) begin 166 | if(RST_I) CYC_O <= 1'b0; 167 | else if (ch_equ) CYC_O <= 1'b1; 168 | else if(~ch_equ_oval) CYC_O <= 1'b0; 169 | end 170 | assign WE_O = CYC_O; 171 | 172 | always @(posedge CLK_I) begin 173 | if(RST_I) begin 174 | DAT_O <= 32'd0; 175 | STB_O <= 1'b0; 176 | end 177 | else if(ch_equ_oval & Ch_CmxMul_oval) begin 178 | STB_O <= 1'b1; 179 | if ((~out_halt)) DAT_O <= {mult_Im, mult_Re}; // Q3.13 (Q10.6) 180 | end 181 | else STB_O <= 1'b0; 182 | end 183 | 184 | 185 | endmodule 186 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/PhaseTrack.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:58:32 11/10/2012 7 | // Design Name: 8 | // Module Name: Ch_PhaseTrack 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PhaseTrack( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, // DAT_I_Im[31:16] DAT_I_Re[15:0] in Q3.13 (Q10.6) 24 | input WE_I, STB_I, CYC_I, 25 | output ACK_O, 26 | 27 | output reg [31:0] DAT_O, // DAT_I_Im[31:16] DAT_I_Re[15:0] in Q3.13 (Q10.6) 28 | output reg CYC_O,STB_O, 29 | output WE_O, 30 | input ACK_I, 31 | 32 | // input [127:0] ALLOC_VEC, 33 | input [103:0] ALLOC_VEC, 34 | output VEC_LD 35 | ); 36 | 37 | reg [31:0] idat; 38 | reg iena; 39 | wire istart, out_halt, datin_val; 40 | 41 | assign datin_val = (WE_I) & STB_I & CYC_I; 42 | assign out_halt = STB_O & (~ACK_I); 43 | assign ACK_O = datin_val &(~out_halt); 44 | assign istart = CYC_I & (~CYC_I_pp); 45 | 46 | reg CYC_I_pp; 47 | always @(posedge CLK_I) begin 48 | if(RST_I) CYC_I_pp <= 1'b1; 49 | else CYC_I_pp <= CYC_I; 50 | end 51 | always @(posedge CLK_I) begin 52 | if(RST_I) idat <= 32'd0; 53 | else if ( ACK_O ) idat <= DAT_I; 54 | end 55 | always @(posedge CLK_I) begin 56 | if(RST_I) iena <= 1'b0; 57 | else if (datin_val) iena <= 1'b1; 58 | else iena <= 1'b0; 59 | end 60 | 61 | 62 | wire [15:0] Ph_Re; 63 | wire [15:0] Ph_Im; 64 | wire Ph_est_val; 65 | 66 | 67 | wire [31:0] Ph_CmxMul_A; //[31:16]: imaginary part, [15:0]: real part 68 | wire [31:0] Ph_CmxMul_B; //[31:16]: imaginary part, [15:0]: real part 69 | wire [79:0] Ph_CmxMul_dout; //[72:40]: imaginary part, [32:0]: real part 70 | wire Ph_CmxMul_ival; 71 | wire Ph_CmxMul_oval; 72 | 73 | reg [5:0] dat_cnt; 74 | always@(posedge CLK_I) begin 75 | if (RST_I) dat_cnt <= 6'd0; 76 | else if (istart) dat_cnt <= 6'd0; 77 | else if (dat_cnt == 6'd51) dat_cnt <= 6'd0; 78 | else if (iena) dat_cnt <= dat_cnt + 1'b1; 79 | end 80 | 81 | //reg [127:0] alloc_reg; 82 | reg [103:0] alloc_reg; 83 | 84 | always@(posedge CLK_I) 85 | begin 86 | if(RST_I) alloc_reg <= 103'd0; 87 | else if(CYC_I & (~CYC_I_pp)) alloc_reg <= ALLOC_VEC; 88 | // else if(dat_cnt == 6'd63) alloc_reg <= ALLOC_VEC; 89 | else if(dat_cnt == 6'd51) alloc_reg <= ALLOC_VEC; 90 | end 91 | 92 | wire car_act = alloc_reg[{dat_cnt,1'b1}] | alloc_reg[{dat_cnt,1'b0}]; // carrier is active 93 | 94 | reg [5:0] buf_rdcnt; 95 | //reg [32:0] dat_buf [0:63]; //[32]: allocation bit; [31:16]: imaginary part; [15:0]: real part 96 | reg [32:0] dat_buf [0:51]; //[32]: allocation bit; [31:16]: imaginary part; [15:0]: real part 97 | 98 | always@(posedge CLK_I) begin 99 | if (RST_I) dat_buf[dat_cnt] <= 33'd0; 100 | else if (iena) dat_buf[dat_cnt] <= {car_act, idat}; 101 | end 102 | 103 | 104 | assign Ph_start = iena & (dat_cnt == 6'd0); 105 | PhTrack_Est Ph_Est_ins( 106 | .clk(CLK_I), .rst(RST_I), .start(Ph_start), .datin_val(iena), 107 | .datin_Re(idat[15:0]), 108 | .datin_Im(idat[31:16]), 109 | .alloc_vec({alloc_reg[{dat_cnt,1'b1}], alloc_reg[{dat_cnt,1'b0}]}), 110 | .ph_Re(Ph_Re), 111 | .ph_Im(Ph_Im), 112 | .ph_oval(Ph_est_val) 113 | ); 114 | 115 | 116 | reg Ph_comp_ena; 117 | reg [15:0] Ph_comp_Re, Ph_comp_Im; 118 | 119 | always@(posedge CLK_I) begin 120 | if (RST_I) begin 121 | Ph_comp_ena <= 1'b0; 122 | Ph_comp_Re <= 16'd0; 123 | Ph_comp_Im <= 16'd0; 124 | end 125 | else if (Ph_est_val) begin 126 | Ph_comp_ena <= 1'b1; 127 | Ph_comp_Re <= Ph_Re; 128 | Ph_comp_Im <= Ph_Im; 129 | end 130 | // else if (buf_rdcnt == 6'd63) Ph_comp_ena <= 1'b0; 131 | else if (buf_rdcnt == 6'd51) Ph_comp_ena <= 1'b0; 132 | end 133 | 134 | always@(posedge CLK_I) begin 135 | if (RST_I) buf_rdcnt <= 6'd0; 136 | else if ((buf_rdcnt == 6'd51) &(~out_halt)) buf_rdcnt <= 6'd0; 137 | else if (Ph_comp_ena &(~out_halt)) buf_rdcnt <= buf_rdcnt + 1'b1; 138 | end 139 | 140 | assign Ph_CmxMul_A = dat_buf[buf_rdcnt][31:0]; // Q3.13 (Q10.6) 141 | assign Ph_CmxMul_B[15:0] = Ph_comp_Re; // Q1.15 : Q3.13 (Q10.6) 142 | assign Ph_CmxMul_B[31:16] = (~Ph_comp_Im + 1'b1); //imaginary part of pilot is zero. 143 | 144 | assign Ph_CmxMul_ival = Ph_comp_ena & dat_buf[buf_rdcnt][32]; 145 | 146 | Ch_CmxMul Ph_CmxMul_ins( 147 | .aclk(CLK_I), // input aclk 148 | .aresetn(~RST_I), // input aresetn 149 | .aclken(1'b1), // input aclken 150 | .s_axis_a_tvalid(Ph_CmxMul_ival), // input s_axis_a_tvalid 151 | .s_axis_a_tdata(Ph_CmxMul_A), // input [31 : 0] s_axis_a_tdata 152 | .s_axis_b_tvalid(Ph_CmxMul_ival), // input s_axis_b_tvalid 153 | .s_axis_b_tdata(Ph_CmxMul_B), // input [31 : 0] s_axis_b_tdata 154 | .m_axis_dout_tvalid(Ph_CmxMul_oval), // ouput m_axis_dout_tvalid 155 | .m_axis_dout_tdata(Ph_CmxMul_dout)); // ouput [79 : 0] m_axis_dout_tdata [32:0]:real part; [72:40]:imaginary part. 156 | 157 | 158 | 159 | reg [5:0] ph_track_delay; // because of multiplier latency. 160 | always @(posedge CLK_I) begin 161 | if(RST_I) ph_track_delay <= 6'd0; 162 | else if (CYC_O) ph_track_delay <= {Ph_CmxMul_ival, ph_track_delay[5:1]}; 163 | end 164 | wire ph_track_oval = ph_track_delay[0]; 165 | 166 | always @(posedge CLK_I) begin 167 | if(RST_I) CYC_O <= 1'b0; 168 | else if (Ph_CmxMul_ival) CYC_O <= 1'b1; 169 | else if((~(ph_track_oval|CYC_I)) &(buf_rdcnt == 6'd0)) CYC_O <= 1'b0; 170 | end 171 | assign WE_O = CYC_O; 172 | 173 | always @(posedge CLK_I) begin 174 | if(RST_I) begin 175 | DAT_O <= 32'd0; 176 | STB_O <= 1'b0; 177 | end 178 | else if (~out_halt) begin 179 | if(Ph_CmxMul_oval) begin 180 | STB_O <= 1'b1; 181 | // DAT_O <= {Ph_CmxMul_dout[70:55], Ph_CmxMul_dout[30:15]}; //Q3.13 (Q10.6) 182 | // DAT_O <= {Ph_CmxMul_dout[61:46], Ph_CmxMul_dout[21:6]}; //Q3.13 (Q10.6) 183 | DAT_O <= {Ph_CmxMul_dout[67:52], Ph_CmxMul_dout[27:12]}; //Q3.13 (Q16.0) 184 | end 185 | else STB_O <= 1'b0; 186 | end 187 | end 188 | 189 | endmodule 190 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/Tx_Out_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:27:07 12/18/2012 7 | // Design Name: 8 | // Module Name: Tx_Out_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Tx_Out_tb( 22 | ); 23 | 24 | reg rst, clk; 25 | reg we_i, stb_i, cyc_i; 26 | reg [31:0] dat_in; 27 | reg ack_i; 28 | 29 | wire [31:0] Pilots_Insert_dat_out; 30 | wire Pilots_Insert_we_o; 31 | wire Pilots_Insert_stb_o; 32 | wire Pilots_Insert_cyc_o; 33 | 34 | wire Pilots_Insert_ack_o; 35 | wire Pilots_Insert_ack_i; 36 | 37 | Pilots_Insert Pilots_Insert_UUT( 38 | .CLK_I(clk), .RST_I(rst), 39 | .DAT_I(dat_in), 40 | .WE_I(we_i), 41 | .STB_I(stb_i), 42 | .CYC_I(cyc_i), 43 | .ACK_O(Pilots_Insert_ack_o), 44 | .DAT_O(Pilots_Insert_dat_out), 45 | .WE_O (Pilots_Insert_we_o), 46 | .STB_O(Pilots_Insert_stb_o), 47 | .CYC_O(Pilots_Insert_cyc_o), 48 | .ACK_I(Pilots_Insert_ack_i) 49 | ); 50 | 51 | 52 | wire [31:0] IFFT_Mod_dat_in = Pilots_Insert_dat_out; 53 | wire IFFT_Mod_we_i = Pilots_Insert_we_o; 54 | wire IFFT_Mod_stb_i = Pilots_Insert_stb_o; 55 | wire IFFT_Mod_cyc_i = Pilots_Insert_cyc_o; 56 | wire IFFT_Mod_ack_i; 57 | wire IFFT_Mod_ack_o; 58 | assign Pilots_Insert_ack_i = IFFT_Mod_ack_o; 59 | wire [31:0] IFFT_Mod_dat_out; 60 | wire IFFT_Mod_we_o; 61 | wire IFFT_Mod_stb_o; 62 | wire IFFT_Mod_cyc_o; 63 | 64 | IFFT_Mod IFFT_Mod_UUT( 65 | .CLK_I(clk), .RST_I(rst), 66 | .DAT_I(IFFT_Mod_dat_in), 67 | .WE_I (IFFT_Mod_we_i), 68 | .STB_I(IFFT_Mod_stb_i), 69 | .CYC_I(IFFT_Mod_cyc_i), 70 | .ACK_O(IFFT_Mod_ack_o), 71 | .DAT_O(IFFT_Mod_dat_out), 72 | .WE_O (IFFT_Mod_we_o), 73 | .STB_O(IFFT_Mod_stb_o), 74 | .CYC_O(IFFT_Mod_cyc_o), 75 | .ACK_I(IFFT_Mod_ack_i) 76 | ); 77 | 78 | wire [31:0] Tx_Out_dat_in = IFFT_Mod_dat_out; 79 | wire Tx_Out_we_i = IFFT_Mod_we_o; 80 | wire Tx_Out_stb_i = IFFT_Mod_stb_o; 81 | wire Tx_Out_cyc_i = IFFT_Mod_cyc_o; 82 | wire Tx_Out_ack_i = ack_i; 83 | wire Tx_Out_ack_o; 84 | assign IFFT_Mod_ack_i = Tx_Out_ack_o; 85 | wire [31:0] Tx_Out_dat_out; 86 | wire Tx_Out_we_o; 87 | wire Tx_Out_stb_o; 88 | wire Tx_Out_cyc_o; 89 | 90 | Tx_Out UUT( 91 | .CLK_I(clk), .RST_I(rst), 92 | .DAT_I(Tx_Out_dat_in), 93 | .WE_I (Tx_Out_we_i), 94 | .STB_I(Tx_Out_stb_i), 95 | .CYC_I(Tx_Out_cyc_i), 96 | .ACK_O(Tx_Out_ack_o), 97 | .DAT_O(Tx_Out_dat_out), 98 | .WE_O (Tx_Out_we_o), 99 | .STB_O(Tx_Out_stb_o), 100 | .CYC_O(Tx_Out_cyc_o), 101 | .ACK_I(Tx_Out_ack_i) 102 | ); 103 | 104 | parameter NSAM = 10*(256+32); 105 | //reg [31:0] datin [NSAM - 1:0]; 106 | integer ii; 107 | integer Len, para_fin; 108 | 109 | 110 | initial begin 111 | rst = 1'b1; 112 | clk = 1'b0; 113 | we_i = 1'b0; 114 | stb_i = 1'b0; 115 | cyc_i = 1'b0; 116 | ii = 0; 117 | dat_in = 32'd0; 118 | 119 | Len = 384; 120 | 121 | #25rst = 1'b0; 122 | end 123 | 124 | always #10 clk = ~clk; 125 | 126 | reg wr_datin, wr_frm_pp; 127 | 128 | reg wr_frm; 129 | initial begin 130 | wr_frm = 1'b0; 131 | wr_datin =1'b1; 132 | ack_i =1'b1; 133 | #200 ii=0; 134 | wr_frm = 1'b1; 135 | end 136 | 137 | 138 | always @(posedge clk) begin 139 | if(rst) begin 140 | ii <= 0; 141 | dat_in <= 32'd1; 142 | wr_frm_pp <= 1'b0; 143 | end 144 | else if(wr_frm) begin 145 | cyc_i <= 1'b1; 146 | wr_frm_pp <= wr_frm; 147 | 148 | if (~wr_datin) begin 149 | stb_i <= 1'b0; 150 | cyc_i <= 1'b0; 151 | we_i <= 1'b0; 152 | end 153 | else if (~wr_frm_pp) begin 154 | wr_frm_pp <= wr_frm; 155 | ii <= ii+1; 156 | stb_i <= 1'b1; 157 | cyc_i <= 1'b1; 158 | we_i <= 1'b1; 159 | end 160 | else if ((ii == Len)&(Pilots_Insert_ack_o)) begin 161 | we_i <= 1'b0; 162 | stb_i <= 1'b0; 163 | cyc_i <= 1'b0; 164 | wr_frm <= 1'b0; 165 | end 166 | else if (Pilots_Insert_ack_o) begin 167 | dat_in <= dat_in + 1'b1; 168 | ii <= ii+1; 169 | stb_i <= 1'b1; 170 | cyc_i <= 1'b1; 171 | we_i <= 1'b1; 172 | end 173 | end 174 | else begin 175 | wr_frm_pp <= wr_frm; 176 | we_i <= 1'b0; 177 | stb_i <= 1'b0; 178 | cyc_i <= 1'b0; 179 | end 180 | 181 | end 182 | 183 | /* 184 | initial begin 185 | wr_datin =1'b1; 186 | @(posedge ack_o); 187 | #210; 188 | wr_datin =1'b0; 189 | #100; 190 | wr_datin =1'b1; 191 | #400; 192 | wr_datin =1'b0; 193 | #200; 194 | wr_datin =1'b1; 195 | #300; 196 | wr_datin =1'b0; 197 | #100; 198 | wr_datin =1'b1; 199 | end 200 | 201 | 202 | initial begin 203 | ack_i =1'b0; 204 | @(posedge stb_o); 205 | #5; 206 | ack_i =1'b0; 207 | #100; 208 | ack_i =1'b1; 209 | #500; 210 | ack_i =1'b0; 211 | #200; 212 | ack_i =1'b1; 213 | #300; 214 | ack_i =1'b0; 215 | #700; 216 | ack_i =1'b1; 217 | end 218 | */ 219 | /* 220 | integer datout_fo, datout_cnt; 221 | 222 | initial begin 223 | datout_cnt = 0; 224 | datout_fo = $fopen("../../MATLAB/OFDM_SYS_tb/RemoveCP/RTL_RemoveCP_datout.txt"); 225 | forever begin 226 | @(posedge clk); 227 | if ((~we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 228 | $fwrite(datout_fo,"%d ",$signed(dat_out)); 229 | datout_cnt = datout_cnt + 1; 230 | end 231 | end 232 | end 233 | */ 234 | 235 | /*initial begin 236 | ack_i = 0; 237 | forever begin 238 | @(posedge clk); 239 | if (stb_o) begin 240 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 241 | ack_i = 1'b1; 242 | end 243 | end 244 | end 245 | initial begin 246 | forever begin 247 | @(posedge clk); 248 | if (dat_in == 31'd193) begin 249 | ack_i = 1'b0; 250 | #645 ack_i = 1'b1; 251 | end 252 | end 253 | end 254 | initial begin 255 | forever begin 256 | @(posedge clk); 257 | if (dat_in == 31'd80) begin 258 | ack_i = 1'b0; 259 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 260 | ack_i = 1'b1; 261 | end 262 | end 263 | end 264 | */ 265 | 266 | reg stop_chk; 267 | initial begin 268 | stop_chk = 1'b0; 269 | #30000 stop_chk = 1'b1; 270 | end 271 | initial begin 272 | forever begin 273 | @(posedge clk); 274 | if (stop_chk) begin 275 | //$fclose(datout_fo); 276 | $stop; 277 | end 278 | end 279 | end 280 | 281 | endmodule 282 | 283 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/Synch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:24:15 03/29/2012 7 | // Design Name: 8 | // Module Name: Synch 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Synch( 22 | input CLK_I, RST_I, 23 | input [31:0] DAT_I, 24 | input CYC_I, 25 | input STB_I, 26 | output ACK_O, 27 | 28 | output [31:0] DAT_O, 29 | output WE_O, STB_O, CYC_O, 30 | input ACK_I 31 | ); 32 | 33 | reg [2:0] cyc_i_pp; 34 | always @(posedge CLK_I) begin 35 | if(RST_I) cyc_i_pp <= 3'b00; 36 | else cyc_i_pp <= {cyc_i_pp[1:0], CYC_I}; 37 | end 38 | wire nfrm_rst = ({cyc_i_pp, CYC_I} == 4'b0001)|(({cyc_i_pp, CYC_I} == 4'b0011)); 39 | 40 | //wire [15:0] thres; //timing metric threshold 41 | wire out_halt; 42 | reg [15:0] rx_Re, rx_Im; 43 | reg iena; 44 | 45 | always @(posedge CLK_I) begin 46 | if(RST_I | nfrm_rst) begin 47 | rx_Re <= 16'd0; 48 | rx_Im <= 16'd0; 49 | iena <= 1'b0; 50 | end 51 | else if (CYC_I & STB_I & (~out_halt)) begin 52 | rx_Re <= DAT_I[15:0]; 53 | rx_Im <= DAT_I[31:16]; 54 | iena <= 1'b1; 55 | end 56 | else iena <= 1'b0; 57 | end 58 | 59 | 60 | wire time_syn_run; 61 | wire [31:0] syn_dat; //[31:16]: imaginary part; [15:0]: real part in format 2.14 62 | 63 | //================================ Calculate P metric ==============================// 64 | wire [15:0] rx_Im_d16,rx_Re_d16; 65 | Delay2n #(.WIDTH(32), .D(16), .B(4)) RX_delay64( 66 | .clk(CLK_I), 67 | .rst(RST_I | nfrm_rst), 68 | .ena(iena), 69 | .dat_in({rx_Im,rx_Re}), 70 | .dat_out({rx_Im_d16,rx_Re_d16}) 71 | ); 72 | 73 | wire [15:0] rx_Im_conj; 74 | assign rx_Im_conj = (~rx_Im) + 1'b1; 75 | 76 | wire [15:0] ACRMult_Re, ACRMult_Im; 77 | wire [79:0] CM_out; 78 | wire CM_val; 79 | 80 | Complex_Multiplier ACR_Mult_ins ( 81 | .aclk(CLK_I), // input aclk 82 | .aresetn(~(RST_I | nfrm_rst)), // input aresetn 83 | .s_axis_a_tvalid(iena), // input s_axis_a_tvalid 84 | .s_axis_a_tdata({rx_Im_conj, rx_Re}), // input [31 : 0] s_axis_a_tdata 85 | .s_axis_b_tvalid(iena), // input s_axis_b_tvalid 86 | .s_axis_b_tdata({rx_Im_d16, rx_Re_d16}), // input [31 : 0] s_axis_b_tdata 87 | .m_axis_dout_tvalid(CM_val), // ouput m_axis_dout_tvalid 88 | .m_axis_dout_tdata(CM_out[79:0]) // ouput [79 : 0] m_axis_dout_tdata: real = [32:0]; image = [79:40]; 89 | ); 90 | assign ACRMult_Re = CM_out[30:15]; // rounding output in format 1.15 91 | assign ACRMult_Im = CM_out[70:55]; 92 | 93 | wire [15:0] ACRMult_Re_d64, ACRMult_Im_d64; 94 | Delay2n #(.WIDTH(32), .D(64), .B(6)) ACR_delay64( 95 | .clk(CLK_I), 96 | .rst(RST_I | nfrm_rst), 97 | .ena(CM_val), 98 | .dat_in({ACRMult_Im, ACRMult_Re}), 99 | .dat_out({ACRMult_Im_d64,ACRMult_Re_d64}) 100 | ); 101 | 102 | wire [15:0] ACRMult_Re_d96, ACRMult_Im_d96; 103 | Delay2n #(.WIDTH(32), .D(32), .B(5)) ACR_delay32( 104 | .clk(CLK_I), 105 | .rst(RST_I | nfrm_rst), 106 | .ena(CM_val), 107 | .dat_in({ACRMult_Im_d64, ACRMult_Re_d64}), 108 | .dat_out({ACRMult_Im_d96,ACRMult_Re_d96}) 109 | ); 110 | 111 | 112 | wire [22:0] P_Re, P_Im; // rounding P_Metric in format 8.15 113 | Comp_Acc_Sum #(.WIDTH(23)) P_Acc_Sum_ins( 114 | .clk(CLK_I), 115 | .rst(RST_I | nfrm_rst), 116 | .ena(CM_val), 117 | .a_Re(ACRMult_Re), 118 | .a_Im(ACRMult_Im), 119 | .a_d_Re(ACRMult_Re_d96), 120 | .a_d_Im(ACRMult_Im_d96), 121 | .sum_out_Re(P_Re), 122 | .sum_out_Im(P_Im) 123 | ); 124 | 125 | assign P_Metric = {P_Im, P_Re}; 126 | //================================ End P metric ===================================// 127 | 128 | //================================ Calculate R metric ==============================// 129 | wire [79:0] ABSrx_out; 130 | wire [16:0] rx_abs; // rounding output of ABS in format 2.15 131 | wire ABSrx_val; 132 | wire [23:0] R_Metric; // rounding R Metric in format 9.15 133 | 134 | Complex_Multiplier ABSrx_ins ( 135 | .aclk(CLK_I), // input aclk 136 | .aresetn(~(RST_I | nfrm_rst)), // input aresetn 137 | .s_axis_a_tvalid(iena), // input s_axis_a_tvalid 138 | .s_axis_a_tdata({rx_Im_conj, rx_Re}), // input [31 : 0] s_axis_a_tdata 139 | .s_axis_b_tvalid(iena), // input s_axis_b_tvalid 140 | .s_axis_b_tdata({rx_Im, rx_Re}), // input [31 : 0] s_axis_b_tdata 141 | .m_axis_dout_tvalid(ABSrx_val), // ouput m_axis_dout_tvalid 142 | .m_axis_dout_tdata(ABSrx_out) // ouput [79 : 0] m_axis_dout_tdata 143 | ); 144 | assign rx_abs = ABSrx_out[31:15]; // rounding output of ABS in format 2.15 145 | 146 | wire [16:0] rx_abs_d64; 147 | Delay2n #(.WIDTH(17), .D(64), .B(6)) rx_abs_delay128( 148 | .clk(CLK_I), 149 | .rst(RST_I | nfrm_rst), 150 | .ena(ABSrx_val), 151 | .dat_in(rx_abs), 152 | .dat_out(rx_abs_d64) 153 | ); 154 | 155 | wire [16:0] rx_abs_d96; 156 | Delay2n #(.WIDTH(17), .D(32), .B(5)) rx_abs_delay32( 157 | .clk(CLK_I), 158 | .rst(RST_I | nfrm_rst), 159 | .ena(ABSrx_val), 160 | .dat_in(rx_abs_d64), 161 | .dat_out(rx_abs_d96) 162 | ); 163 | 164 | Acc_Sum R_Acc_Sum_ins( 165 | .clk(CLK_I), 166 | .rst(RST_I | nfrm_rst), 167 | .ena(ABSrx_val), 168 | .a(rx_abs), 169 | .a_d(rx_abs_d96), 170 | .sum_out(R_Metric) // rounding R Metric in format 9.15 171 | ); 172 | //================================== End R metric ==================================// 173 | 174 | 175 | wire [23:0] P_Metric_mag; 176 | wire P_Metric_mag_val; 177 | Appr_Mag #(.WIDTH(23))P_Metic_mag_ins( 178 | .clk(CLK_I), .rst(RST_I | nfrm_rst), .ena(CM_val), 179 | .real_in(P_Re), 180 | .imag_in(P_Im), 181 | .mag(P_Metric_mag), // magnitute of P metric in format 9.15 182 | .val(P_Metric_mag_val) 183 | ); 184 | 185 | wire Freoff_Est_Comp_ena; 186 | Coarse_Time_Synch Coarse_Time_Synch_ins( 187 | .clk(CLK_I), .rst(RST_I | nfrm_rst), .cyc_i(CYC_I), 188 | .ena((time_syn_run & P_Metric_mag_val)), 189 | .P_Metric_mag(P_Metric_mag), 190 | .R_Metric(R_Metric), 191 | .Freoff_Est_Comp_ena(Freoff_Est_Comp_ena) 192 | ); 193 | 194 | wire Freoff_Est_Comp_val; 195 | Freoff_Est_Comp Freoff_Est_Comp_ins( 196 | .clk(CLK_I), .rst(RST_I | nfrm_rst), 197 | .ena(Freoff_Est_Comp_ena), 198 | .ce(~out_halt), 199 | .dat_in({rx_Im,rx_Re}), //[31:16]: imaginary part; [15:0]: real part in format 1.15 200 | .stb_in(iena), 201 | .P_Re(P_Re), 202 | .P_Im(P_Im), 203 | .dat_out(syn_dat), //[31:16]: imaginary part; [15:0]: real part in format 2.14 204 | .out_val(Freoff_Est_Comp_val) 205 | ); 206 | 207 | //wire Fine_Time_ena = Freoff_Est_Comp_val & time_syn_run; 208 | Fine_Time_Synch Fine_Time_Synch_ins( 209 | .clk(CLK_I), .rst(RST_I | nfrm_rst), 210 | .cyc_i(CYC_I), 211 | .stb_i(STB_I), 212 | .ack_o(ACK_O), 213 | .dat_out(DAT_O), //[31:16]: imaginary part; [15:0]: real part in format 2.14 214 | .we_o(WE_O), 215 | .stb_o(STB_O), 216 | .cyc_o(CYC_O), 217 | .ack_i(ACK_I), 218 | 219 | .dat_in(syn_dat), //[31:16]: imaginary part; [15:0]: real part in format 2.14 220 | .dat_in_val(Freoff_Est_Comp_val), 221 | 222 | .time_syn_run(time_syn_run), 223 | .out_halt(out_halt) 224 | ); 225 | 226 | endmodule 227 | -------------------------------------------------------------------------------- /OFDM_TX_802_11/MY_SOURCES/OFDM_TX_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:19:08 12/19/2012 7 | // Design Name: 8 | // Module Name: OFDM_TX_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module OFDM_TX_tb( 22 | ); 23 | reg rst, clk; 24 | reg we_i, stb_i, cyc_i; 25 | reg [5:0] dat_in; 26 | reg ack_i; 27 | wire ack_o; 28 | wire [31:0] dat_out; 29 | wire we_o, stb_o, cyc_o; 30 | 31 | OFDM_TX_802_11 UUT( 32 | .CLK_I(clk), .RST_I(rst), 33 | .DAT_I(dat_in), 34 | .WE_I(we_i), 35 | .STB_I(stb_i), 36 | .CYC_I(cyc_i), 37 | .ACK_O(ack_o), 38 | .DAT_O(dat_out), 39 | .WE_O (we_o), 40 | .STB_O(stb_o), 41 | .CYC_O(cyc_o), 42 | .ACK_I(ack_i) 43 | ); 44 | 45 | wire [31:0] DAT_Mod_dat_out = UUT.DAT_Mod_Ins.DAT_O; 46 | wire DAT_Mod_we_o = UUT.DAT_Mod_Ins.WE_O; 47 | wire DAT_Mod_stb_o = UUT.DAT_Mod_Ins.STB_O; 48 | wire DAT_Mod_cyc_o = UUT.DAT_Mod_Ins.CYC_O; 49 | wire DAT_Mod_ack_o = UUT.DAT_Mod_Ins.ACK_O; 50 | 51 | wire [31:0] Pilots_Insert_dat_out = UUT.Pilots_Insert_Ins.DAT_O; 52 | wire Pilots_Insert_we_o = UUT.Pilots_Insert_Ins.WE_O; 53 | wire Pilots_Insert_stb_o = UUT.Pilots_Insert_Ins.STB_O; 54 | wire Pilots_Insert_cyc_o = UUT.Pilots_Insert_Ins.CYC_O; 55 | wire Pilots_Insert_ack_o = UUT.Pilots_Insert_Ins.ACK_O; 56 | 57 | wire [31:0] IFFT_Mod_dat_out = UUT.IFFT_Mod_Ins.DAT_O; 58 | wire IFFT_Mod_we_o = UUT.IFFT_Mod_Ins.WE_O; 59 | wire IFFT_Mod_stb_o = UUT.IFFT_Mod_Ins.STB_O; 60 | wire IFFT_Mod_cyc_o = UUT.IFFT_Mod_Ins.CYC_O; 61 | wire IFFT_Mod_ack_o = UUT.IFFT_Mod_Ins.ACK_O; 62 | 63 | wire IFFT_Mod_ack_i = UUT.IFFT_Mod_Ins.ACK_I; 64 | 65 | parameter NSAM = 10*(256+32); 66 | reg [5:0] datin [NSAM - 1:0]; 67 | integer ii, lop_cnt; 68 | integer Len, NLOP, para_fin; 69 | 70 | 71 | initial begin 72 | rst = 1'b1; 73 | clk = 1'b0; 74 | we_i = 1'b0; 75 | stb_i = 1'b0; 76 | cyc_i = 1'b0; 77 | ii = 0; 78 | dat_in = 6'd0; 79 | 80 | para_fin = $fopen("./MATLAB/OFDM_TX_bit_symbols_Len.txt","r"); 81 | $fscanf(para_fin, "%d ", Len); 82 | $fscanf(para_fin, "%d ", NLOP); 83 | $fclose(para_fin); 84 | 85 | $readmemh("./MATLAB/RTL_OFDM_TX_bit_symbols.txt", datin); 86 | 87 | #25rst = 1'b0; 88 | end 89 | 90 | always #10 clk = ~clk; 91 | 92 | reg wr_datin, wr_frm_pp; 93 | 94 | reg wr_frm; 95 | initial begin 96 | wr_frm = 1'b0; 97 | wr_datin = 1'b1; 98 | ack_i = 1'b1; 99 | lop_cnt = 0; 100 | #600; 101 | forever begin 102 | @(posedge clk); 103 | 104 | if (~(lop_cnt == NLOP)) begin 105 | ii=0; 106 | wr_frm = 1'b1; 107 | dat_in <= datin[ii + lop_cnt*Len]; 108 | @(negedge cyc_o); 109 | #600; 110 | lop_cnt = lop_cnt +1; 111 | end 112 | end 113 | end 114 | 115 | 116 | always @(posedge clk) begin 117 | if(rst) begin 118 | ii <= 0; 119 | dat_in <= datin[ii + lop_cnt*Len]; 120 | wr_frm_pp <= 1'b0; 121 | end 122 | else if(wr_frm) begin 123 | cyc_i <= 1'b1; 124 | wr_frm_pp <= wr_frm; 125 | 126 | if (~wr_datin) begin 127 | stb_i <= 1'b0; 128 | cyc_i <= 1'b0; 129 | we_i <= 1'b0; 130 | end 131 | else if (~wr_frm_pp) begin 132 | wr_frm_pp <= wr_frm; 133 | ii <= ii+1; 134 | stb_i <= 1'b1; 135 | cyc_i <= 1'b1; 136 | we_i <= 1'b1; 137 | end 138 | else if ((ii == Len)&(ack_o)) begin 139 | we_i <= 1'b0; 140 | stb_i <= 1'b0; 141 | cyc_i <= 1'b0; 142 | wr_frm <= 1'b0; 143 | end 144 | else if (ack_o) begin 145 | //dat_in <= dat_in + 1'b1; 146 | dat_in <= datin[ii + lop_cnt*Len]; 147 | ii <= ii+1; 148 | stb_i <= 1'b1; 149 | cyc_i <= 1'b1; 150 | we_i <= 1'b1; 151 | end 152 | end 153 | else begin 154 | wr_frm_pp <= wr_frm; 155 | we_i <= 1'b0; 156 | stb_i <= 1'b0; 157 | cyc_i <= 1'b0; 158 | end 159 | 160 | end 161 | 162 | /* 163 | initial begin 164 | wr_datin =1'b1; 165 | @(posedge ack_o); 166 | #210; 167 | wr_datin =1'b0; 168 | #100; 169 | wr_datin =1'b1; 170 | #400; 171 | wr_datin =1'b0; 172 | #200; 173 | wr_datin =1'b1; 174 | #300; 175 | wr_datin =1'b0; 176 | #100; 177 | wr_datin =1'b1; 178 | end 179 | 180 | 181 | initial begin 182 | ack_i =1'b0; 183 | @(posedge stb_o); 184 | #5; 185 | ack_i =1'b0; 186 | #100; 187 | ack_i =1'b1; 188 | #500; 189 | ack_i =1'b0; 190 | #200; 191 | ack_i =1'b1; 192 | #300; 193 | ack_i =1'b0; 194 | #700; 195 | ack_i =1'b1; 196 | end 197 | */ 198 | 199 | integer datout_Re_fo, datout_Im_fo, datout_cnt; 200 | integer Pilots_Insert_Re_fo, Pilots_Insert_Im_fo; 201 | integer IFFT_Mod_Re_fo, IFFT_Mod_Im_fo; 202 | initial begin 203 | datout_cnt = 0; 204 | datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_TX_datout_Re.txt"); 205 | datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_TX_datout_Im.txt"); 206 | 207 | Pilots_Insert_Re_fo = $fopen("./MATLAB/RTL_OFDM_TX_Pilots_Insert_Re.txt"); 208 | Pilots_Insert_Im_fo = $fopen("./MATLAB/RTL_OFDM_TX_Pilots_Insert_Im.txt"); 209 | 210 | IFFT_Mod_Re_fo = $fopen("./MATLAB/RTL_OFDM_TX_IFFT_Mod_Re.txt"); 211 | IFFT_Mod_Im_fo = $fopen("./MATLAB/RTL_OFDM_TX_IFFT_Mod_Im.txt"); 212 | 213 | forever begin 214 | @(posedge clk); 215 | if ((we_o)&&(stb_o)&&(cyc_o)&&(ack_i)) begin 216 | $fwrite(datout_Re_fo,"%d ",$signed(dat_out[15:0])); 217 | $fwrite(datout_Im_fo,"%d ",$signed(dat_out[31:16])); 218 | datout_cnt = datout_cnt + 1; 219 | end 220 | if ((Pilots_Insert_we_o)&&(Pilots_Insert_stb_o)&&(Pilots_Insert_cyc_o)&&(IFFT_Mod_ack_o)) begin 221 | $fwrite(Pilots_Insert_Re_fo,"%d ",$signed(Pilots_Insert_dat_out[15:0])); 222 | $fwrite(Pilots_Insert_Im_fo,"%d ",$signed(Pilots_Insert_dat_out[31:16])); 223 | //datout_cnt = datout_cnt + 1; 224 | end 225 | if ((IFFT_Mod_we_o)&&(IFFT_Mod_stb_o)&&(IFFT_Mod_cyc_o)&&(IFFT_Mod_ack_i)) begin 226 | $fwrite(IFFT_Mod_Re_fo,"%d ",$signed(IFFT_Mod_dat_out[15:0])); 227 | $fwrite(IFFT_Mod_Im_fo,"%d ",$signed(IFFT_Mod_dat_out[31:16])); 228 | //datout_cnt = datout_cnt + 1; 229 | end 230 | end 231 | end 232 | 233 | 234 | /*initial begin 235 | ack_i = 0; 236 | forever begin 237 | @(posedge clk); 238 | if (stb_o) begin 239 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 240 | ack_i = 1'b1; 241 | end 242 | end 243 | end 244 | initial begin 245 | forever begin 246 | @(posedge clk); 247 | if (dat_in == 31'd193) begin 248 | ack_i = 1'b0; 249 | #645 ack_i = 1'b1; 250 | end 251 | end 252 | end 253 | initial begin 254 | forever begin 255 | @(posedge clk); 256 | if (dat_in == 31'd80) begin 257 | ack_i = 1'b0; 258 | @(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk);@(posedge clk); 259 | ack_i = 1'b1; 260 | end 261 | end 262 | end 263 | */ 264 | 265 | reg stop_chk; 266 | initial begin 267 | stop_chk = 1'b0; 268 | //#30000 stop_chk = 1'b1; 269 | forever begin 270 | @(posedge clk); 271 | if (lop_cnt == NLOP) begin 272 | #100; 273 | stop_chk = 1'b1; 274 | end 275 | end 276 | end 277 | initial begin 278 | forever begin 279 | @(posedge clk); 280 | if (stop_chk) begin 281 | $fclose(datout_Re_fo); 282 | $fclose(datout_Im_fo); 283 | 284 | $fclose(Pilots_Insert_Re_fo); 285 | $fclose(Pilots_Insert_Im_fo); 286 | 287 | $fclose(IFFT_Mod_Re_fo); 288 | $fclose(IFFT_Mod_Im_fo); 289 | $stop; 290 | end 291 | end 292 | end 293 | 294 | endmodule 295 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/OFDM_RX_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:29:43 04/26/2012 7 | // Design Name: 8 | // Module Name: OFDM_RX_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module OFDM_RX_tb( 22 | ); 23 | 24 | reg rst, clk; 25 | reg cyc_i; 26 | reg stb_i; 27 | reg [31:0] dat_in; 28 | 29 | wire ack_o; 30 | wire [43:0] p_metric; 31 | wire [21:0] r_metric; 32 | reg [3:0] SNR; 33 | 34 | wire [7:0] dat_out; 35 | wire we_o, stb_o, cyc_o; 36 | reg ack_i; 37 | 38 | 39 | 40 | OFDM_RX_802_11 UUT( 41 | .CLK_I(clk), .RST_I(rst), 42 | .Q_CH_I(dat_in[31:16]), 43 | .I_CH_I(dat_in[15:0]), 44 | .CYC_I(cyc_i), 45 | .STB_I(stb_i), 46 | .ACK_O(ack_o), 47 | 48 | .DAT_O(dat_out), 49 | .WE_O(we_o), 50 | .STB_O(stb_o), 51 | .CYC_O(cyc_o), 52 | .ACK_I(ack_i), 53 | 54 | .SNR(SNR) 55 | 56 | ); 57 | 58 | 59 | 60 | parameter NSAM = 30*(256+32); 61 | reg [15:0] datin_Re [NSAM - 1:0]; 62 | reg [15:0] datin_Im [NSAM - 1:0]; 63 | integer lop_cnt, ii; 64 | integer NLOP, Flen, Toff, para_fin; 65 | 66 | 67 | initial begin 68 | rst = 1'b1; 69 | clk = 1'b0; 70 | cyc_i = 1'b0; 71 | 72 | dat_in = 32'd0; 73 | 74 | para_fin = $fopen("./MATLAB/RTL_OFDM_RX_datin_len.txt","r"); 75 | $fscanf(para_fin, "%d ", NLOP); 76 | $fscanf(para_fin, "%d ", Flen); 77 | $fscanf(para_fin, "%d ", SNR); 78 | $fscanf(para_fin, "%d ", Toff); 79 | $fclose(para_fin); 80 | 81 | 82 | $readmemh("./MATLAB/RTL_OFDM_RX_datin_Re.txt", datin_Re); 83 | $readmemh("./MATLAB/RTL_OFDM_RX_datin_Im.txt", datin_Im); 84 | #25rst = 1'b0; 85 | end 86 | 87 | always #10 clk = ~clk; 88 | 89 | reg wr_frm; 90 | initial begin 91 | wr_frm = 1'b0; 92 | wr_datin =1'b1; 93 | ack_i = 1'b1; 94 | ii = 0; 95 | lop_cnt = 0; 96 | #200; 97 | forever begin 98 | @(posedge clk); 99 | if (~(lop_cnt == NLOP)) begin 100 | dat_in <= {datin_Im[ii], datin_Re[ii]}; 101 | wr_frm = 1'b1; 102 | @(negedge cyc_o); 103 | #200; 104 | ii = ii+1; 105 | lop_cnt = lop_cnt + 1; 106 | end 107 | end 108 | end 109 | 110 | reg wr_datin, wr_frm_pp; 111 | 112 | always @(posedge clk) begin 113 | if(rst) begin 114 | ii <= 0; 115 | //dat_in <= {datin_Im[ii], datin_Re[ii]}; 116 | wr_frm_pp <= 1'b0; 117 | end 118 | else begin 119 | 120 | if(wr_frm) begin 121 | cyc_i <= 1'b1; 122 | wr_frm_pp <= wr_frm; 123 | 124 | if (~wr_datin) begin 125 | stb_i <= 1'b0; 126 | end 127 | else if (~wr_frm_pp) begin 128 | wr_frm_pp <= wr_frm; 129 | stb_i <= 1'b1; 130 | end 131 | else if ((ii == ((Flen)*(lop_cnt+1) -1))&(ack_o)) begin 132 | cyc_i <= 1'b0; 133 | stb_i <= 1'b0; 134 | wr_frm <= 1'b0; 135 | end 136 | else begin 137 | stb_i <= 1'b1; 138 | end 139 | end 140 | else begin 141 | wr_frm_pp <= wr_frm; 142 | cyc_i <= 1'b0; 143 | stb_i <= 1'b0; 144 | end 145 | 146 | if (stb_i & ack_o & (ii < ((Flen)*(lop_cnt+1) -1))) begin 147 | dat_in <= {datin_Im[ii + 1], datin_Re[ii + 1]}; 148 | ii <= ii+1; 149 | end 150 | end 151 | end 152 | 153 | 154 | integer datout_fo, datout_cnt; 155 | 156 | initial begin 157 | datout_cnt = 0; 158 | datout_fo = $fopen("./MATLAB/RTL_OFDM_RX_datout.txt"); 159 | forever begin 160 | @(posedge clk); 161 | if ((stb_o)&&(cyc_o)&&(ack_i)) begin 162 | $fwrite(datout_fo,"%d ",$signed(dat_out[7:0])); 163 | datout_cnt = datout_cnt + 1; 164 | end 165 | end 166 | end 167 | 168 | 169 | // Synch =============================================================================== 170 | wire [31:0] Synch_datout = UUT.Synch_ins.DAT_O; 171 | wire Synch_stb_o = UUT.Synch_ins.STB_O; 172 | wire Synch_we_o = UUT.Synch_ins.WE_O; 173 | wire Synch_ack_o = UUT.Synch_ins.ACK_O; 174 | 175 | 176 | // FreComp =============================================================================== 177 | //wire [31:0] FreComp_datout = UUT.FreComp_ins.DAT_O; 178 | //wire FreComp_stb_o = UUT.FreComp_ins.STB_O; 179 | //wire FreComp_we_o = UUT.FreComp_ins.WE_O; 180 | //wire FreComp_ack_o = UUT.FreComp_ins.ACK_O; 181 | //wire [15:0] FreComp_phase_rot = UUT.FreComp_ins.phase_rot; 182 | //wire FreComp_phase_acc_rdy = UUT.FreComp_ins.phase_acc_rdy; 183 | //wire FreComp_phase_acc_ce = (~UUT.FreComp_ins.out_halt); 184 | // RemoveCP =============================================================================== 185 | wire [31:0] RemoveCP_datout = UUT.RemoveCP_ins.DAT_O; 186 | wire RemoveCP_stb_o = UUT.RemoveCP_ins.STB_O; 187 | wire RemoveCP_we_o = UUT.RemoveCP_ins.WE_O; 188 | wire RemoveCP_ack_o = UUT.RemoveCP_ins.ACK_O; 189 | // FFT =============================================================================== 190 | wire [31:0] FFT_datout = UUT.FFT_Demod_ins.DAT_O; 191 | wire FFT_stb_o = UUT.FFT_Demod_ins.STB_O; 192 | wire FFT_we_o = UUT.FFT_Demod_ins.WE_O; 193 | wire FFT_ack_o = UUT.FFT_Demod_ins.ACK_O; 194 | 195 | // iCFO_EstComp =============================================================================== 196 | wire [31:0] iCFO_EstComp_datout = UUT.iCFO_EstComp_ins.DAT_O; 197 | wire iCFO_EstComp_stb_o = UUT.iCFO_EstComp_ins.STB_O; 198 | wire iCFO_EstComp_we_o = UUT.iCFO_EstComp_ins.WE_O; 199 | wire iCFO_EstComp_ack_o = UUT.iCFO_EstComp_ins.ACK_O; 200 | 201 | // Ch_EstEqu =============================================================================== 202 | wire [31:0] Ch_EstEqu_datout = UUT.Ch_EstEqu_ins.DAT_O; 203 | wire Ch_EstEqu_stb_o = UUT.Ch_EstEqu_ins.STB_O; 204 | wire Ch_EstEqu_we_o = UUT.Ch_EstEqu_ins.WE_O; 205 | wire Ch_EstEqu_ack_i = UUT.Ch_EstEqu_ins.ACK_I; 206 | // PhaseTrack =============================================================================== 207 | wire [31:0] PhaseTrack_datout = UUT.PhaseTrack_ins.DAT_O; 208 | wire PhaseTrack_stb_o = UUT.PhaseTrack_ins.STB_O; 209 | wire PhaseTrack_we_o = UUT.PhaseTrack_ins.WE_O; 210 | wire PhaseTrack_ack_i = UUT.PhaseTrack_ins.ACK_I; 211 | 212 | integer Synch_datout_Re_fo, FreComp_datout_Re_fo, RemoveCP_datout_Re_fo, FFT_datout_Re_fo, iCFO_EstComp_datout_Re_fo, Ch_EstEqu_datout_Re_fo, PhaseTrack_datout_Re_fo; 213 | integer Synch_datout_Im_fo, FreComp_datout_Im_fo, RemoveCP_datout_Im_fo, FFT_datout_Im_fo, iCFO_EstComp_datout_Im_fo, Ch_EstEqu_datout_Im_fo, PhaseTrack_datout_Im_fo; 214 | integer FreComp_phase_rot_fo; 215 | integer Synch_datout_cnt, FreComp_datout_cnt, RemoveCP_datout_cnt, FFT_datout_cnt, temp_fo; 216 | 217 | initial begin 218 | Synch_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_Synch_datout_Re.txt"); 219 | Synch_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_Synch_datout_Im.txt"); 220 | // FreComp_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_FreComp_datout_Re.txt"); 221 | // FreComp_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_FreComp_datout_Im.txt"); 222 | // FreComp_phase_rot_fo = $fopen("./MATLAB/RTL_OFDM_RX_FreComp_phase_rot.txt"); 223 | RemoveCP_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_RemoveCP_datout_Re.txt"); 224 | RemoveCP_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_RemoveCP_datout_Im.txt"); 225 | FFT_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_FFT_datout_Re.txt"); 226 | FFT_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_FFT_datout_Im.txt"); 227 | iCFO_EstComp_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_iCFO_EstComp_datout_Re.txt"); 228 | iCFO_EstComp_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_iCFO_EstComp_datout_Im.txt"); 229 | Ch_EstEqu_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_Ch_EstEqu_datout_Re.txt"); 230 | Ch_EstEqu_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_Ch_EstEqu_datout_Im.txt"); 231 | PhaseTrack_datout_Re_fo = $fopen("./MATLAB/RTL_OFDM_RX_PhaseTrack_datout_Re.txt"); 232 | PhaseTrack_datout_Im_fo = $fopen("./MATLAB/RTL_OFDM_RX_PhaseTrack_datout_Im.txt"); 233 | temp_fo = $fopen("./MATLAB/temp.txt"); 234 | 235 | Synch_datout_cnt = 0; 236 | FreComp_datout_cnt = 0; 237 | RemoveCP_datout_cnt = 0; 238 | FFT_datout_cnt = 0; 239 | forever begin 240 | @(posedge clk); 241 | if (Synch_stb_o) begin 242 | $fwrite(Synch_datout_Re_fo,"%d ", $signed(Synch_datout[15:0])); 243 | $fwrite(Synch_datout_Im_fo,"%d ", $signed(Synch_datout[31:16])); 244 | Synch_datout_cnt = Synch_datout_cnt+1; 245 | end 246 | // if (FreComp_stb_o) begin 247 | // $fwrite(FreComp_datout_Re_fo,"%d ", $signed(FreComp_datout[15:0])); 248 | // $fwrite(FreComp_datout_Im_fo,"%d ", $signed(FreComp_datout[31:16])); 249 | // FreComp_datout_cnt = FreComp_datout_cnt+1; 250 | // end 251 | // if (FreComp_phase_acc_rdy & FreComp_phase_acc_ce) begin 252 | // $fwrite(FreComp_phase_rot_fo,"%d ",$signed(FreComp_phase_rot)); 253 | // end 254 | if (RemoveCP_stb_o) begin 255 | $fwrite(RemoveCP_datout_Re_fo,"%d ", $signed(RemoveCP_datout[15:0])); 256 | $fwrite(RemoveCP_datout_Im_fo,"%d ", $signed(RemoveCP_datout[31:16])); 257 | RemoveCP_datout_cnt = RemoveCP_datout_cnt + 1; 258 | end 259 | if (FFT_stb_o) begin 260 | $fwrite(FFT_datout_Re_fo,"%d ", $signed(FFT_datout[15:0])); 261 | $fwrite(FFT_datout_Im_fo,"%d ", $signed(FFT_datout[31:16])); 262 | FFT_datout_cnt = FFT_datout_cnt+1; 263 | end 264 | if (iCFO_EstComp_stb_o) begin 265 | $fwrite(iCFO_EstComp_datout_Re_fo,"%d ", $signed(iCFO_EstComp_datout[15:0])); 266 | $fwrite(iCFO_EstComp_datout_Im_fo,"%d ", $signed(iCFO_EstComp_datout[31:16])); 267 | end 268 | if (Ch_EstEqu_stb_o & Ch_EstEqu_ack_i) begin 269 | $fwrite(Ch_EstEqu_datout_Re_fo,"%d ", $signed(Ch_EstEqu_datout[15:0])); 270 | $fwrite(Ch_EstEqu_datout_Im_fo,"%d ", $signed(Ch_EstEqu_datout[31:16])); 271 | end 272 | if (PhaseTrack_stb_o) begin 273 | $fwrite(PhaseTrack_datout_Re_fo,"%d ", $signed(PhaseTrack_datout[15:0])); 274 | $fwrite(PhaseTrack_datout_Im_fo,"%d ", $signed(PhaseTrack_datout[31:16])); 275 | end 276 | 277 | end 278 | end 279 | 280 | reg stop_chk; 281 | initial begin 282 | stop_chk = 1'b0; 283 | forever begin 284 | @(posedge clk); 285 | if (lop_cnt == NLOP) begin 286 | #400; 287 | stop_chk = 1'b1; 288 | end 289 | end 290 | end 291 | initial begin 292 | forever begin 293 | @(posedge clk); 294 | if (stop_chk) begin 295 | $fclose(Synch_datout_Re_fo); 296 | $fclose(Synch_datout_Im_fo); 297 | // $fclose(FreComp_datout_Re_fo); 298 | // $fclose(FreComp_datout_Im_fo); 299 | // $fclose(FreComp_phase_rot_fo); 300 | $fclose(RemoveCP_datout_Re_fo); 301 | $fclose(RemoveCP_datout_Im_fo); 302 | $fclose(FFT_datout_Re_fo); 303 | $fclose(FFT_datout_Im_fo); 304 | $fclose(iCFO_EstComp_datout_Re_fo); 305 | $fclose(iCFO_EstComp_datout_Im_fo); 306 | $fclose(Ch_EstEqu_datout_Re_fo); 307 | $fclose(Ch_EstEqu_datout_Im_fo); 308 | $fclose(PhaseTrack_datout_Re_fo); 309 | $fclose(PhaseTrack_datout_Im_fo); 310 | $fclose(temp_fo); 311 | $fclose(datout_fo); 312 | $stop; 313 | end 314 | end 315 | end 316 | 317 | endmodule 318 | -------------------------------------------------------------------------------- /OFDM_RX_802_11/MY_SOURCES/iCFO_est.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:18:57 09/18/2012 7 | // Design Name: 8 | // Module Name: iCFO_est 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module iCFO_est( 22 | input clk, rst, ena_i, 23 | input [1:0] sb_dat_i, //signed bit symbol:[1] :signed bit of imaginary part, [0] :signed bit of real part, 24 | input stb_i, 25 | input [7:0] dat_cnt, 26 | output reg [2:0] ifoff, 27 | output reg dat_out_val 28 | ); 29 | 30 | reg [1:0] sp1 [0:22]; //[1] :signed bit of imaginary part, [0] :signed bit of real part, 31 | initial $readmemh("./MY_SOURCES/icfo_known_coeff_rtl1.txt", sp1); 32 | 33 | reg [1:0] sp2 [0:22]; //[1] :signed bit of imaginary part, [0] :signed bit of real part, 34 | initial $readmemh("./MY_SOURCES/icfo_known_coeff_rtl2.txt", sp2); 35 | 36 | reg [31:0] rot_reg ; 37 | reg [1:0] iCR_in; 38 | wire CR_abs_done; 39 | 40 | //============================================= 41 | wire [7:0] datin_cnt; 42 | assign datin_cnt = (ena_i)? dat_cnt : 8'd255; 43 | /* 44 | always@(posedge clk) begin 45 | if (rst) datin_cnt <=8'd0; 46 | else if (ena_i & stb_i) datin_cnt <= datin_cnt + 1'b1; 47 | else if (~ena_i) datin_cnt <=8'd0; 48 | end 49 | */ 50 | reg sp_ena1, sp_ena2; // selected pilots enable 51 | 52 | always@(datin_cnt) begin 53 | case (datin_cnt) 54 | 8'd0, 8'd4, 8'd8, 8'd12, 8'd16, 8'd20, 8'd24, 8'd28, 8'd32, 8'd36, 8'd40, 8'd44, 8'd48, 8'd52, 8'd56, 8'd60: 55 | begin sp_ena1 = 1'b1; 56 | sp_ena2 = 1'b0; 57 | end 58 | 8'd184, 8'd188, 8'd192, 8'd196, 8'd200, 8'd204, 8'd208, 8'd212, 8'd216, 8'd220, 8'd224, 8'd228, 8'd232, 8'd236, 8'd240, 8'd244: 59 | begin sp_ena1 = 1'b0; 60 | sp_ena2 = 1'b1; 61 | end 62 | default: begin sp_ena1 = 1'b0; 63 | sp_ena2 = 1'b0; 64 | end 65 | endcase 66 | end 67 | wire sp_ena = sp_ena1 | sp_ena2; 68 | reg ld_Ri; 69 | always@(posedge clk) begin 70 | if (rst) ld_Ri <= 1'b0; 71 | else if (ena_i) ld_Ri <= sp_ena; 72 | else ld_Ri <= 1'b0; 73 | end 74 | 75 | reg compute_ena1, compute_ena2; 76 | always@(posedge clk) begin 77 | if (rst) compute_ena1 <= 1'b0; 78 | else if (ena_i && (datin_cnt == 8'd0)) compute_ena1 <= 1'b1; 79 | else if (datin_cnt == 8'd64) compute_ena1 <= 1'b0; 80 | end 81 | always@(posedge clk) begin 82 | if (rst) compute_ena2 <= 1'b0; 83 | else if (datin_cnt == 8'd184) compute_ena2 <= 1'b1; 84 | else if (datin_cnt == 8'd248) compute_ena2 <= 1'b0; 85 | end 86 | 87 | wire compute_ena = compute_ena1|compute_ena2; 88 | 89 | 90 | reg [45:0] sp1_reg, sp2_reg; 91 | always@(posedge clk) begin 92 | if (rst) sp1_reg <= 46'd0; 93 | else if (~ena_i) sp1_reg <= {sp1[22],sp1[0],sp1[1],sp1[2],sp1[3],sp1[4],sp1[5],sp1[6],sp1[7],sp1[8],sp1[9],sp1[10],sp1[11],sp1[12],sp1[13],sp1[14],sp1[15],sp1[16],sp1[17],sp1[18],sp1[19],sp1[20],sp1[21]}; 94 | else if (sp_ena1) sp1_reg <= {sp1_reg[43:0], sp1_reg[45:44]}; 95 | end 96 | 97 | always@(posedge clk) begin 98 | if (rst) sp2_reg <= 46'd0; 99 | else if (~ena_i) sp2_reg <= {sp2[22],sp2[0],sp2[1],sp2[2],sp2[3],sp2[4],sp2[5],sp2[6],sp2[7],sp2[8],sp2[9],sp2[10],sp2[11],sp2[12],sp2[13],sp2[14],sp2[15],sp2[16],sp2[17],sp2[18],sp2[19],sp2[20],sp2[21]}; 100 | else if (sp_ena2) sp2_reg <= {sp2_reg[43:0], sp2_reg[45:44]}; 101 | end 102 | 103 | 104 | reg [1:0] datin_pp; 105 | always@(posedge clk) begin 106 | if (rst) datin_pp <= 2'b00; 107 | else if (ena_i & stb_i) datin_pp <= sb_dat_i; 108 | end 109 | 110 | always@(posedge clk) begin 111 | if (rst) iCR_in <= 2'b00; 112 | else if (ld_Ri) iCR_in <= datin_pp; 113 | end 114 | 115 | reg [1:0] sb_mult_mux1; 116 | always@(datin_cnt[1:0] or compute_ena1 or compute_ena2 or sp1_reg[45:38] or sp2_reg[45:38] ) begin 117 | case (datin_cnt[1:0]) 118 | 2'b01: sb_mult_mux1 = (compute_ena1)? sp1_reg[45:44]:(compute_ena2)?sp2_reg[45:44]:2'b00; 119 | 2'b10: sb_mult_mux1 = (compute_ena1)? sp1_reg[43:42]:(compute_ena2)?sp2_reg[43:42]:2'b00; 120 | 2'b11: sb_mult_mux1 = (compute_ena1)? sp1_reg[41:40]:(compute_ena2)?sp2_reg[41:40]:2'b00; 121 | 2'b00: sb_mult_mux1 = (compute_ena1)? sp1_reg[39:38]:(compute_ena2)?sp2_reg[39:38]:2'b00; 122 | default: sb_mult_mux1 = 2'b00; 123 | endcase 124 | end 125 | reg [1:0] sb_mult_mux2; 126 | always@(datin_cnt[1:0] or compute_ena1 or compute_ena2 or sp1_reg[37:30] or sp2_reg[37:30] ) begin 127 | case (datin_cnt[1:0]) 128 | 2'b01: sb_mult_mux2 = (compute_ena1)? sp1_reg[37:36]:(compute_ena2)?sp2_reg[37:36]:2'b00; 129 | 2'b10: sb_mult_mux2 = (compute_ena1)? sp1_reg[35:34]:(compute_ena2)?sp2_reg[35:34]:2'b00; 130 | 2'b11: sb_mult_mux2 = (compute_ena1)? sp1_reg[33:32]:(compute_ena2)?sp2_reg[33:32]:2'b00; 131 | 2'b00: sb_mult_mux2 = (compute_ena1)? sp1_reg[31:30]:(compute_ena2)?sp2_reg[31:30]:2'b00; 132 | default: sb_mult_mux2 = 2'b00; 133 | endcase 134 | end 135 | 136 | reg [5:0] sb_xcor_Re [0:7]; 137 | reg [5:0] sb_xcor_Im [0:7]; 138 | 139 | reg [5:0] sum_mux_Re1, sum_mux_Im1; 140 | always@(datin_cnt[1:0]) begin 141 | case (datin_cnt[1:0]) 142 | 2'b01: begin 143 | sum_mux_Re1 = sb_xcor_Re[7]; 144 | sum_mux_Im1 = sb_xcor_Im[7]; 145 | end 146 | 2'b10: begin 147 | sum_mux_Re1 = sb_xcor_Re[6]; 148 | sum_mux_Im1 = sb_xcor_Im[6]; 149 | end 150 | 2'b11: begin 151 | sum_mux_Re1 = sb_xcor_Re[5]; 152 | sum_mux_Im1 = sb_xcor_Im[5]; 153 | end 154 | 2'b00: begin 155 | sum_mux_Re1 = sb_xcor_Re[4]; 156 | sum_mux_Im1 = sb_xcor_Im[4]; 157 | end 158 | default: begin 159 | sum_mux_Re1 = 6'd0; 160 | sum_mux_Im1 = 6'd0; 161 | end 162 | endcase 163 | end 164 | 165 | reg [5:0] sum_mux_Re2, sum_mux_Im2; 166 | always@(datin_cnt[1:0]) begin 167 | case (datin_cnt[1:0]) 168 | 2'b01: begin 169 | sum_mux_Re2 = sb_xcor_Re[3]; 170 | sum_mux_Im2 = sb_xcor_Im[3]; 171 | end 172 | 2'b10: begin 173 | sum_mux_Re2 = sb_xcor_Re[2]; 174 | sum_mux_Im2 = sb_xcor_Im[2]; 175 | end 176 | 2'b11: begin 177 | sum_mux_Re2 = sb_xcor_Re[1]; 178 | sum_mux_Im2 = sb_xcor_Im[1]; 179 | end 180 | 2'b00: begin 181 | sum_mux_Re2 = sb_xcor_Re[0]; 182 | sum_mux_Im2 = sb_xcor_Im[0]; 183 | end 184 | default: begin 185 | sum_mux_Re2 = 6'd0; 186 | sum_mux_Im2 = 6'd0; 187 | end 188 | endcase 189 | end 190 | 191 | reg [1:0] sb_mult_coeff1, sb_mult_coeff2; 192 | reg [5:0] sum_in_Re1, sum_in_Im1, sum_in_Re2, sum_in_Im2; 193 | 194 | always@(posedge clk) begin 195 | if (rst) begin 196 | sb_mult_coeff1 <= 2'b00; 197 | sb_mult_coeff2 <= 2'b00; 198 | sum_in_Re1 <= 6'd0; 199 | sum_in_Im1 <= 6'd0; 200 | sum_in_Re2 <= 6'd0; 201 | sum_in_Im2 <= 6'd0; 202 | end 203 | else if (compute_ena)begin 204 | sb_mult_coeff1 <= sb_mult_mux1; 205 | sb_mult_coeff2 <= sb_mult_mux2; 206 | sum_in_Re1 <= sum_mux_Re1; 207 | sum_in_Im1 <= sum_mux_Im1; 208 | sum_in_Re2 <= sum_mux_Re2; 209 | sum_in_Im2 <= sum_mux_Im2; 210 | end 211 | end 212 | 213 | //============================================= 214 | 215 | wire [1:0] mult_out_Re1, mult_out_Re2; 216 | wire [1:0] mult_out_Im1, mult_out_Im2; 217 | 218 | Signed_Mult_tap Signed_Mult_tap_ins1( 219 | .rxin(iCR_in), //[1:0] 220 | .preamble(sb_mult_coeff1[1:0]), //[1:0] 221 | .mult_out_Re(mult_out_Re1[1:0]), //[1:0] 222 | .mult_out_Im(mult_out_Im1[1:0]) //[1:0] 223 | ); 224 | 225 | Signed_Mult_tap Signed_Mult_tap_ins2( 226 | .rxin(iCR_in), //[1:0] 227 | .preamble(sb_mult_coeff2[1:0]), //[1:0] 228 | .mult_out_Re(mult_out_Re2[1:0]), //[1:0] 229 | .mult_out_Im(mult_out_Im2[1:0]) //[1:0] 230 | ); 231 | 232 | 233 | wire [5:0] tap_out_Re1 = sum_in_Re1 + {{4{mult_out_Re1[1]}}, mult_out_Re1}; 234 | wire [5:0] tap_out_Im1 = sum_in_Im1 + {{4{mult_out_Im1[1]}}, mult_out_Im1}; 235 | wire [5:0] tap_out_Re2 = sum_in_Re2 + {{4{mult_out_Re2[1]}}, mult_out_Re2}; 236 | wire [5:0] tap_out_Im2 = sum_in_Im2 + {{4{mult_out_Im2[1]}}, mult_out_Im2}; 237 | 238 | reg sum_acc_ena; 239 | always@(posedge clk) begin 240 | if (rst) sum_acc_ena <= 1'b0; 241 | else sum_acc_ena <= compute_ena; 242 | end 243 | 244 | always@(posedge clk) begin 245 | if (rst) begin 246 | sb_xcor_Re[7] <= 6'd0; 247 | sb_xcor_Im[7] <= 6'd0; 248 | end 249 | else if (CR_abs_done) begin 250 | sb_xcor_Re[7] <= 6'd0; 251 | sb_xcor_Im[7] <= 6'd0; 252 | end 253 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b10)) begin 254 | sb_xcor_Re[7] <= tap_out_Re1; 255 | sb_xcor_Im[7] <= tap_out_Im1; 256 | end 257 | end 258 | always@(posedge clk) begin 259 | if (rst) begin 260 | sb_xcor_Re[6] <= 6'd0; 261 | sb_xcor_Im[6] <= 6'd0; 262 | end 263 | else if (CR_abs_done) begin 264 | sb_xcor_Re[6] <= 6'd0; 265 | sb_xcor_Im[6] <= 6'd0; 266 | end 267 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b11)) begin 268 | sb_xcor_Re[6] <= tap_out_Re1; 269 | sb_xcor_Im[6] <= tap_out_Im1; 270 | end 271 | end 272 | always@(posedge clk) begin 273 | if (rst) begin 274 | sb_xcor_Re[5] <= 6'd0; 275 | sb_xcor_Im[5] <= 6'd0; 276 | end 277 | else if (CR_abs_done) begin 278 | sb_xcor_Re[5] <= 6'd0; 279 | sb_xcor_Im[5] <= 6'd0; 280 | end 281 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b00)) begin 282 | sb_xcor_Re[5] <= tap_out_Re1; 283 | sb_xcor_Im[5] <= tap_out_Im1; 284 | end 285 | end 286 | always@(posedge clk) begin 287 | if (rst) begin 288 | sb_xcor_Re[4] <= 6'd0; 289 | sb_xcor_Im[4] <= 6'd0; 290 | end 291 | else if (CR_abs_done) begin 292 | sb_xcor_Re[4] <= 6'd0; 293 | sb_xcor_Im[4] <= 6'd0; 294 | end 295 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b01)) begin 296 | sb_xcor_Re[4] <= tap_out_Re1; 297 | sb_xcor_Im[4] <= tap_out_Im1; 298 | end 299 | end 300 | 301 | always@(posedge clk) begin 302 | if (rst) begin 303 | sb_xcor_Re[3] <= 6'd0; 304 | sb_xcor_Im[3] <= 6'd0; 305 | end 306 | else if (CR_abs_done) begin 307 | sb_xcor_Re[3] <= 6'd0; 308 | sb_xcor_Im[3] <= 6'd0; 309 | end 310 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b10)) begin 311 | sb_xcor_Re[3] <= tap_out_Re2; 312 | sb_xcor_Im[3] <= tap_out_Im2; 313 | end 314 | end 315 | always@(posedge clk) begin 316 | if (rst) begin 317 | sb_xcor_Re[2] <= 6'd0; 318 | sb_xcor_Im[2] <= 6'd0; 319 | end 320 | else if (CR_abs_done) begin 321 | sb_xcor_Re[2] <= 6'd0; 322 | sb_xcor_Im[2] <= 6'd0; 323 | end 324 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b11)) begin 325 | sb_xcor_Re[2] <= tap_out_Re2; 326 | sb_xcor_Im[2] <= tap_out_Im2; 327 | end 328 | end 329 | always@(posedge clk) begin 330 | if (rst) begin 331 | sb_xcor_Re[1] <= 6'd0; 332 | sb_xcor_Im[1] <= 6'd0; 333 | end 334 | else if (CR_abs_done) begin 335 | sb_xcor_Re[1] <= 6'd0; 336 | sb_xcor_Im[1] <= 6'd0; 337 | end 338 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b00)) begin 339 | sb_xcor_Re[1] <= tap_out_Re2; 340 | sb_xcor_Im[1] <= tap_out_Im2; 341 | end 342 | end 343 | always@(posedge clk) begin 344 | if (rst) begin 345 | sb_xcor_Re[0] <= 6'd0; 346 | sb_xcor_Im[0] <= 6'd0; 347 | end 348 | else if (CR_abs_done) begin 349 | sb_xcor_Re[0] <= 6'd0; 350 | sb_xcor_Im[0] <= 6'd0; 351 | end 352 | else if (sum_acc_ena & (datin_cnt[1:0] == 2'b01)) begin 353 | sb_xcor_Re[0] <= tap_out_Re2; 354 | sb_xcor_Im[0] <= tap_out_Im2; 355 | end 356 | end 357 | 358 | //================================================================== 359 | reg [2:0] XCR_cnt; 360 | reg XCR_val; 361 | always@(posedge clk) begin 362 | if (rst) begin XCR_cnt <= 3'd0; XCR_val<= 1'b0; end 363 | else if (datin_cnt == 8'd249) begin XCR_cnt <= 3'd7; XCR_val<= 1'b1; end 364 | else if (~(XCR_cnt == 3'd0)) begin XCR_cnt <= XCR_cnt - 1'b1; XCR_val<= 1'b1; end 365 | else XCR_val<= 1'b0; 366 | end 367 | reg [5:0] CR_Re,CR_Im; 368 | always@(XCR_cnt) begin 369 | case (XCR_cnt) 370 | 3'b000: begin 371 | CR_Re = sb_xcor_Re[7]; 372 | CR_Im = sb_xcor_Im[7]; 373 | end 374 | 3'b001: begin 375 | CR_Re = sb_xcor_Re[6]; 376 | CR_Im = sb_xcor_Im[6]; 377 | end 378 | 3'b010: begin 379 | CR_Re = sb_xcor_Re[5]; 380 | CR_Im = sb_xcor_Im[5]; 381 | end 382 | 3'b011: begin 383 | CR_Re = sb_xcor_Re[4]; 384 | CR_Im = sb_xcor_Im[4]; 385 | end 386 | 3'b100: begin 387 | CR_Re = sb_xcor_Re[3]; 388 | CR_Im = sb_xcor_Im[3]; 389 | end 390 | 3'b101: begin 391 | CR_Re = sb_xcor_Re[2]; 392 | CR_Im = sb_xcor_Im[2]; 393 | end 394 | 3'b110: begin 395 | CR_Re = sb_xcor_Re[1]; 396 | CR_Im = sb_xcor_Im[1]; 397 | end 398 | 3'b111: begin 399 | CR_Re = sb_xcor_Re[0]; 400 | CR_Im = sb_xcor_Im[0]; 401 | end 402 | default: begin 403 | CR_Re = sb_xcor_Re[0]; 404 | CR_Im = sb_xcor_Im[0]; 405 | end 406 | endcase 407 | end 408 | 409 | wire [6:0] CR_abs; 410 | wire CR_abs_val; 411 | iCFO_Appr_Mag #(.WIDTH(6)) CR_out_mag_ins( 412 | .clk(clk), .rst(rst), .ena(XCR_val), 413 | .real_in(CR_Re), 414 | .imag_in(CR_Im), 415 | .mag(CR_abs), 416 | .val(CR_abs_val) 417 | ); 418 | 419 | //================================================================== 420 | reg [6:0] CR_max; 421 | reg CR_abs_val_pp; 422 | reg [2:0] ifoff_cnt; 423 | always@(posedge clk) begin 424 | if (rst) CR_abs_val_pp <= 1'b0; 425 | else CR_abs_val_pp <= CR_abs_val; 426 | end 427 | assign CR_abs_done = (~CR_abs_val) & CR_abs_val_pp; 428 | 429 | always@(posedge clk) begin 430 | if (rst) begin 431 | ifoff <= 3'b000; 432 | CR_max <= 9'd0; 433 | dat_out_val <= 1'b0; 434 | ifoff_cnt <= 3'b000; 435 | end 436 | else if (ena_i && (datin_cnt == 8'd1)) begin 437 | ifoff <= 3'b000; 438 | CR_max <= 9'd0; 439 | dat_out_val <= 1'b0; 440 | ifoff_cnt <= 3'b000; 441 | end 442 | else if (CR_abs_val) begin 443 | 444 | ifoff_cnt <= ifoff_cnt + 1'b1; 445 | 446 | if (CR_max < CR_abs) begin 447 | ifoff <= ifoff_cnt; 448 | CR_max <= CR_abs; 449 | end 450 | end 451 | else if (CR_abs_done) dat_out_val <= 1'b1; 452 | end 453 | 454 | endmodule 455 | 456 | --------------------------------------------------------------------------------