├── .gitignore ├── .gitmodules ├── .gtkwaverc ├── .travis.yml ├── LICENSE ├── Makefile ├── README.md ├── log.md ├── src ├── SuperStack.v ├── SuperStack.vh ├── cpu.v ├── cpu.vh ├── genrom.v ├── opcodes.vh ├── stack.v └── stack.vh └── test ├── SuperStack_tb.gtkw ├── SuperStack_tb.v ├── assert.vh ├── cpu ├── block.hex ├── block_tb.v ├── br.hex ├── br_if.hex ├── br_if_tb.v ├── br_table1.hex ├── br_table1_tb.v ├── br_table2.hex ├── br_table2_tb.v ├── br_table3.hex ├── br_table3_tb.v ├── br_tb.v ├── call1.hex ├── call1_tb.v ├── call2.hex ├── call2_tb.v ├── cpu_tb.gtkw ├── drop.hex ├── drop_tb.v ├── else1.hex ├── else1_tb.v ├── else2.hex ├── else2_tb.v ├── f32.const.hex ├── f32.const_tb.v ├── f32.demote-f64.hex ├── f32.demote-f64_tb.v ├── f32.reinterpret-i32.hex ├── f32.reinterpret-i32_tb.v ├── f64.const.hex ├── f64.const_tb.v ├── f64.reinterpret-i64.hex ├── f64.reinterpret-i64_tb.v ├── get_local1.hex ├── get_local1_tb.v ├── get_local2.hex ├── get_local2_tb.v ├── i32.add.hex ├── i32.add_tb.v ├── i32.const.hex ├── i32.const_tb.v ├── i32.eq1.hex ├── i32.eq1_tb.v ├── i32.eq2.hex ├── i32.eq2_tb.v ├── i32.eqz1.hex ├── i32.eqz1_tb.v ├── i32.eqz2.hex ├── i32.eqz2_tb.v ├── i32.ne1.hex ├── i32.ne1_tb.v ├── i32.ne2.hex ├── i32.ne2_tb.v ├── i32.reinterpret-f32.hex ├── i32.reinterpret-f32_tb.v ├── i32.sub.hex ├── i32.sub_tb.v ├── i32.wrap-i64.hex ├── i32.wrap-i64_tb.v ├── i64.add.hex ├── i64.add_tb.v ├── i64.const.hex ├── i64.const_tb.v ├── i64.eq1.hex ├── i64.eq1_tb.v ├── i64.eq2.hex ├── i64.eq2_tb.v ├── i64.eqz1.hex ├── i64.eqz1_tb.v ├── i64.eqz2.hex ├── i64.eqz2_tb.v ├── i64.ne1.hex ├── i64.ne1_tb.v ├── i64.ne2.hex ├── i64.ne2_tb.v ├── i64.reinterpret-f64.hex ├── i64.reinterpret-f64_tb.v ├── i64.sub.hex ├── i64.sub_tb.v ├── if1.hex ├── if1_tb.v ├── if2.hex ├── if2_tb.v ├── loop.hex ├── loop_tb.v ├── return.hex ├── return_tb.v ├── select1.hex ├── select1_tb.v ├── select2.hex ├── select2_tb.v ├── select3.hex ├── select3_tb.v ├── set_local.hex ├── set_local_tb.v ├── tee_local.hex └── tee_local_tb.v ├── genrom.hex ├── genrom_tb.gtkw ├── genrom_tb.v ├── stack_tb.gtkw └── stack_tb.v /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "vendor/LEB128"] 2 | path = vendor/LEB128 3 | url = https://github.com/piranna/LEB128.git 4 | [submodule "vendor/fpu"] 5 | path = vendor/fpu 6 | url = https://github.com/piranna/fpu.git 7 | -------------------------------------------------------------------------------- /.gtkwaverc: -------------------------------------------------------------------------------- 1 | splash_disable on 2 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | language: verilog 2 | dist: trusty 3 | addons: 4 | apt: 5 | sources: 6 | - sourceline: 'deb http://es.archive.ubuntu.com/ubuntu/ yakkety main universe' 7 | packages: 8 | - make 9 | - iverilog 10 | script: make test 11 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | {one line to give the program's name and a brief idea of what it does.} 635 | Copyright (C) {year} {name of author} 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | {project} Copyright (C) {year} {fullname} 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | SHELL=/bin/bash -o pipefail 2 | 3 | SRC = src 4 | BUILD = build 5 | 6 | NAME = wasmachine 7 | DEPS = $(SRC)/genrom.v $(SRC)/$(NAME).v 8 | 9 | VENDOR_DEPS = -y vendor/fpu/double_to_float \ 10 | -y vendor/fpu/float_to_double \ 11 | -y vendor/LEB128 12 | 13 | IVERILOG = iverilog -g2005-sv -I $(SRC) -y $(SRC) $(VENDOR_DEPS) $(parameters) 14 | GTKWAVE = gtkwave 15 | VVP = vvp -N 16 | 17 | RED=\033[0;31m 18 | GREEN=\033[0;32m 19 | NC=\033[0m 20 | 21 | ECHO = echo -e 22 | 23 | 24 | all: test $(NAME).bin 25 | 26 | 27 | clean: 28 | rm -rf *.bin *.txt *.blif $(BUILD) *~ 29 | 30 | update-dependencies: 31 | git submodule update --remote 32 | 33 | 34 | .PHONY: all clean update-dependencies 35 | 36 | ifndef VERBOSE 37 | .SILENT: 38 | endif 39 | 40 | 41 | # 42 | # General test objectives 43 | # 44 | test : test/stack test/SuperStack test/genrom test/cpu 45 | test/genrom : $(BUILD)/genrom_tb.vcd 46 | test/stack : $(BUILD)/stack_tb.vcd 47 | test/SuperStack: $(BUILD)/SuperStack_tb.vcd 48 | test/% : $(BUILD)/%_tb.vcd 49 | 50 | $(BUILD)/%_tb.vcd: $(BUILD)/%_tb 51 | ( \ 52 | cd $(BUILD) && $(VVP) ../$< | \ 53 | (grep -v -e "opened for output" \ 54 | -e "Not enough words in the file for the requested range" \ 55 | || true) \ 56 | ) \ 57 | && $(ECHO) "$(GREEN)ok$(NC)" \ 58 | || ($(ECHO) "$(RED)FAIL$(NC)" && exit 1) 59 | 60 | $(BUILD)/%_tb: test/%_tb.v $(SRC)/%.v test/assert.vh 61 | $(ECHO) -n $<"... " 62 | mkdir -p $(@D) 63 | $(IVERILOG) -I test $< -o $@ 64 | 65 | view/%: test/% 66 | $(GTKWAVE) $(BUILD)/$(@F)_tb.vcd test/$(@F)_tb.gtkw 67 | 68 | 69 | # cpu 70 | test/cpu: test/cpu/control_flow_operators test/cpu/call_operators \ 71 | test/cpu/parametric_operators test/cpu/variable_access \ 72 | test/cpu/constants test/cpu/comparison_operators \ 73 | test/cpu/numeric_operators test/cpu/conversions \ 74 | test/cpu/reinterpretations 75 | 76 | test/cpu/control_flow_operators: test/cpu/block test/cpu/loop test/cpu/if \ 77 | test/cpu/else test/cpu/br test/cpu/br_if \ 78 | test/cpu/br_table test/cpu/return 79 | test/cpu/block: $(BUILD)/cpu/block_tb.vcd 80 | test/cpu/loop: $(BUILD)/cpu/loop_tb.vcd 81 | test/cpu/if: test/cpu/if1 test/cpu/if2 82 | test/cpu/if1: $(BUILD)/cpu/if1_tb.vcd 83 | test/cpu/if2: $(BUILD)/cpu/if2_tb.vcd 84 | test/cpu/else: test/cpu/else1 test/cpu/else2 85 | test/cpu/else1: $(BUILD)/cpu/else1_tb.vcd 86 | test/cpu/else2: $(BUILD)/cpu/else2_tb.vcd 87 | test/cpu/br: $(BUILD)/cpu/br_tb.vcd 88 | test/cpu/br_if: $(BUILD)/cpu/br_if_tb.vcd 89 | test/cpu/br_table: test/cpu/br_table1 test/cpu/br_table2 test/cpu/br_table3 90 | test/cpu/br_table1: $(BUILD)/cpu/br_table1_tb.vcd 91 | test/cpu/br_table2: $(BUILD)/cpu/br_table2_tb.vcd 92 | test/cpu/br_table3: $(BUILD)/cpu/br_table3_tb.vcd 93 | test/cpu/return: $(BUILD)/cpu/return_tb.vcd 94 | 95 | test/cpu/call_operators: test/cpu/call 96 | test/cpu/call : test/cpu/call1 test/cpu/call2 97 | test/cpu/call1: $(BUILD)/cpu/call1_tb.vcd 98 | test/cpu/call2: $(BUILD)/cpu/call2_tb.vcd 99 | 100 | test/cpu/parametric_operators: test/cpu/drop test/cpu/select 101 | test/cpu/drop : $(BUILD)/cpu/drop_tb.vcd 102 | test/cpu/select : test/cpu/select1 test/cpu/select2 test/cpu/select3 103 | test/cpu/select1: $(BUILD)/cpu/select1_tb.vcd 104 | test/cpu/select2: $(BUILD)/cpu/select2_tb.vcd 105 | test/cpu/select3: $(BUILD)/cpu/select3_tb.vcd 106 | 107 | test/cpu/variable_access: test/cpu/get_local1 test/cpu/get_local2 \ 108 | test/cpu/set_local test/cpu/tee_local 109 | test/cpu/get_local1: $(BUILD)/cpu/get_local1_tb.vcd 110 | test/cpu/get_local2: $(BUILD)/cpu/get_local2_tb.vcd 111 | test/cpu/set_local: $(BUILD)/cpu/set_local_tb.vcd 112 | test/cpu/tee_local: $(BUILD)/cpu/tee_local_tb.vcd 113 | 114 | test/cpu/constants: test/cpu/f32.const test/cpu/f64.const test/cpu/i32.const \ 115 | test/cpu/i64.const 116 | test/cpu/f32.const: $(BUILD)/cpu/f32.const_tb.vcd 117 | test/cpu/f64.const: $(BUILD)/cpu/f64.const_tb.vcd 118 | test/cpu/i32.const: $(BUILD)/cpu/i32.const_tb.vcd 119 | test/cpu/i64.const: $(BUILD)/cpu/i64.const_tb.vcd 120 | 121 | test/cpu/comparison_operators: test/cpu/i32.eqz test/cpu/i32.eq \ 122 | test/cpu/i32.ne test/cpu/i64.eqz \ 123 | test/cpu/i64.eq test/cpu/i64.ne 124 | test/cpu/i32.eqz : test/cpu/i32.eqz1 test/cpu/i32.eqz2 125 | test/cpu/i32.eqz1: $(BUILD)/cpu/i32.eqz1_tb.vcd 126 | test/cpu/i32.eqz2: $(BUILD)/cpu/i32.eqz2_tb.vcd 127 | test/cpu/i32.eq : test/cpu/i32.eq1 test/cpu/i32.eq2 128 | test/cpu/i32.eq1: $(BUILD)/cpu/i32.eq1_tb.vcd 129 | test/cpu/i32.eq2: $(BUILD)/cpu/i32.eq2_tb.vcd 130 | test/cpu/i32.ne : test/cpu/i32.ne1 test/cpu/i32.ne2 131 | test/cpu/i32.ne1: $(BUILD)/cpu/i32.ne1_tb.vcd 132 | test/cpu/i32.ne2: $(BUILD)/cpu/i32.ne2_tb.vcd 133 | test/cpu/i64.eqz : test/cpu/i64.eqz1 test/cpu/i64.eqz2 134 | test/cpu/i64.eqz1: $(BUILD)/cpu/i64.eqz1_tb.vcd 135 | test/cpu/i64.eqz2: $(BUILD)/cpu/i64.eqz2_tb.vcd 136 | test/cpu/i64.eq : test/cpu/i64.eq1 test/cpu/i64.eq2 137 | test/cpu/i64.eq1: $(BUILD)/cpu/i64.eq1_tb.vcd 138 | test/cpu/i64.eq2: $(BUILD)/cpu/i64.eq2_tb.vcd 139 | test/cpu/i64.ne : test/cpu/i64.ne1 test/cpu/i64.ne2 140 | test/cpu/i64.ne1: $(BUILD)/cpu/i64.ne1_tb.vcd 141 | test/cpu/i64.ne2: $(BUILD)/cpu/i64.ne2_tb.vcd 142 | 143 | test/cpu/numeric_operators: test/cpu/i32.add test/cpu/i32.sub test/cpu/i64.add \ 144 | test/cpu/i64.sub 145 | test/cpu/i32.add: $(BUILD)/cpu/i32.add_tb.vcd 146 | test/cpu/i32.sub: $(BUILD)/cpu/i32.sub_tb.vcd 147 | test/cpu/i64.add: $(BUILD)/cpu/i64.add_tb.vcd 148 | test/cpu/i64.sub: $(BUILD)/cpu/i64.sub_tb.vcd 149 | 150 | test/cpu/conversions: test/cpu/f32.demote-f64 151 | test/cpu/f32.demote-f64: $(BUILD)/cpu/f32.demote-f64_tb.vcd 152 | 153 | test/cpu/conversions: test/cpu/i32.wrap-i64 154 | test/cpu/i32.wrap-i64: $(BUILD)/cpu/i32.wrap-i64_tb.vcd 155 | 156 | test/cpu/reinterpretations: test/cpu/i32.reinterpret-f32 \ 157 | test/cpu/i64.reinterpret-f64 \ 158 | test/cpu/f32.reinterpret-i32 \ 159 | test/cpu/f64.reinterpret-i64 160 | test/cpu/i32.reinterpret-f32: $(BUILD)/cpu/i32.reinterpret-f32_tb.vcd 161 | test/cpu/i64.reinterpret-f64: $(BUILD)/cpu/i64.reinterpret-f64_tb.vcd 162 | test/cpu/f32.reinterpret-i32: $(BUILD)/cpu/f32.reinterpret-i32_tb.vcd 163 | test/cpu/f64.reinterpret-i64: $(BUILD)/cpu/f64.reinterpret-i64_tb.vcd 164 | 165 | 166 | $(BUILD)/cpu/%_tb.vcd: $(BUILD)/cpu/%_tb $(BUILD)/cpu/%.hex 167 | ( \ 168 | cd $(BUILD)/cpu && $(VVP) ../../$< | \ 169 | (grep -v -e "opened for output" \ 170 | -e "Not enough words in the file for the requested range" \ 171 | || true) \ 172 | ) \ 173 | && $(ECHO) "$(GREEN)ok$(NC)" \ 174 | || ($(ECHO) "$(RED)FAIL$(NC)" && exit 1) 175 | 176 | $(BUILD)/cpu/%.hex: 177 | mkdir -p $(@D) 178 | cp test/cpu/$(@F) $(BUILD)/cpu 179 | 180 | $(BUILD)/cpu/%_tb: test/cpu/%_tb.v $(SRC)/cpu.v test/assert.vh 181 | $(ECHO) -n $<"... " 182 | mkdir -p $(@D) 183 | $(IVERILOG) -I test $< -o $@ 184 | 185 | view/cpu/%: test/cpu/% 186 | $(GTKWAVE) $(BUILD)/cpu/$(@F)_tb.vcd test/cpu/cpu_tb.gtkw 187 | 188 | 189 | # genrom 190 | $(BUILD)/genrom_tb.vcd: $(BUILD)/genrom_tb 191 | cp test/genrom.hex $(BUILD) 192 | ( \ 193 | cd $(BUILD) && $(VVP) ../$< | \ 194 | (grep -v -e "opened for output" \ 195 | -e "Not enough words in the file for the requested range" \ 196 | || true) \ 197 | ) \ 198 | && $(ECHO) "$(GREEN)ok$(NC)" \ 199 | || ($(ECHO) "$(RED)FAIL$(NC)" && exit 1) 200 | 201 | 202 | #------------------------------ 203 | #-- Sintesis completa 204 | #------------------------------ 205 | $(NAME).bin: resources/$(NAME).pcf $(DEPS) test/prog.list 206 | 207 | #-- Sintesis 208 | yosys -p "synth_ice40 -blif $(NAME).blif" $(DEPS) 209 | 210 | #-- Place & route 211 | arachne-pnr -d 1k -p resources/$(NAME).pcf $(NAME).blif -o $(NAME).txt 212 | 213 | #-- Generar binario final, listo para descargar en fgpa 214 | icepack $(NAME).txt $(NAME).bin 215 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | [![Build Status](https://travis-ci.org/piranna/wasmachine.svg?branch=master)](https://travis-ci.org/piranna/wasmachine) 2 | 3 | # wasmachine 4 | 5 | Put WebAssembly in your washing machine 6 | 7 | `wasmachine` is an implementation of the [WebAssembly](http://webassembly.org) specification in a FPGA. 8 | It follows a sequential 6-steps design. 9 | 10 | Currently it's in an initial state but is able to exec some basic commands. 11 | 12 | ## Features 13 | 14 | - Stack-based (calls, blocks and operands), variable-length CISC architecture 15 | following the WebAssembly spec design 16 | - Implemented an "expanded" version of the binary format 17 | - Inlined destination of blocks and branches labels 18 | - Decoded LEB128 targets for `br_table` 19 | - Strict type-checking on runtime 20 | - Optionally disable floating point, memory and 64 bits operations at instance 21 | time to generate a simpler core for smaller FPGAs 22 | 23 | ## Keynotes 24 | 25 | - [NodeJS Madrid](https://www.todojs.com/web-assembly-workshop-by-dan-callahan) 26 | (ad-hoc spontaneous keynote at end of the main one :-P) 27 | 28 | ## Roadmap 29 | 30 | 1. ~Implement integer mathematical operations~ 31 | 2. ~Support for functions calling~ 32 | 3. Add a 64 bits FPU for the floating point operations 33 | 4. Memory-based operations 34 | 5. Modules loader in RAM 35 | 6. ~Replace usage of ROM for modules on RAM~ 36 | 7. Accept call of functions from outside 37 | 8. Use a pipelined design 38 | 39 | ## External dependencies 40 | 41 | - [LEB128](https://github.com/piranna/LEB128) 42 | - [fpu](https://github.com/dawsonjon/fpu) 43 | 44 | They can be automatically upgraded executing 45 | 46 | ```sh 47 | make update-dependencies 48 | ``` 49 | 50 | ## Testing 51 | 52 | If you want to test all the modules at once with all the features enabled (the 53 | default build configuration), simply exec: 54 | 55 | ```sh 56 | make test 57 | ``` 58 | 59 | You can also test the modules disabling some features using the `parameters` 60 | argument, that will be directly passed to the `iverilog` executable: 61 | 62 | ```sh 63 | make test parameters='-Pcpu_tb.HAS_FPU=0 -Pcpu_tb.USE_64B=0' 64 | ``` 65 | -------------------------------------------------------------------------------- /log.md: -------------------------------------------------------------------------------- 1 | # 2017-03-01 2 | 3 | `-I` option of `iverilog` allow to define include folders. It allow to be 4 | separated from the argument although manual page seems to say other thing. 5 | 6 | `iverilog` generate "executable" script files for the `vvp` command that's the 7 | one that effectively run the simulation, so probably there could be an option to 8 | define some devices (like a serial port) and interactuate with it. 9 | 10 | # 2017-03-02 11 | 12 | Since `Makefile` instructions are executed verbatin, you can use shell comments 13 | to print some text to `stdout`. 14 | 15 | # 2017-03-03 16 | 17 | Verilog `vcc` is the command with the simulation runtime. Its `-N` flag makes 18 | the simulation to exit when invoking the `$stop` command with `1` as error code. 19 | 20 | Icarus Verilog support `__FILE__` and `__LINE__` statements (http://stackoverflow.com/a/12953585/586382). 21 | There's a test suite at https://github.com/steveicarus/ivtest 22 | 23 | # 2017-03-05 24 | 25 | FPUs implemented in Verilog: 26 | - https://opencores.org/project,fpu 27 | - https://github.com/dawsonjon/fpu 28 | 29 | [Chips: design components in C, design FPGAs in Python](http://dawsonjon.github.io/Chips-2.0/home/index.html) 30 | 31 | # 2017-03-07 32 | 33 | `-y` option of `iverilog` allow to define library folders, to search for modules 34 | that otherwise it would error as not found. 35 | 36 | # 2017-03-09 37 | 38 | `-g2005-sv` flag enable support for SystemVerilog 39 | 40 | To make `-y` option to work, modules has to have the same name and 41 | capitalization that the filename of the file that host them. 42 | 43 | Icarus Verilog is forcing to define registers as input and output of modules, 44 | so it's needed two tick to access ROM data, one to define address and another to 45 | read it. It must to be a solution for that, maybe using combinational logic. 46 | Seems the `logic` type autodetect if should be a `wire` or a `reg`. 47 | 48 | # 2017-03-11 49 | 50 | Stack operation at the end of the pipeline are processed while the opcode of the 51 | next instruction is being fetch to earn some CPU cycles. 52 | 53 | [WebAssembly Explorer](http://mbebenita.github.io/WasmExplorer/) 54 | [WasmFiddle](https://wasdk.github.io/WasmFiddle/?) 55 | 56 | # 2017-03-12 57 | 58 | It's needed to decide what to do when fetching extra bytes from ROM beyond its 59 | actual size. Error, zeros, or unset bits? 60 | 61 | # 2017-03-13 62 | 63 | To identify the end of a WebAssembly module, we'll use at its end a custom empty 64 | section. This means that just two zero bytes will be appended, and we'll get the 65 | same effect when reading from a previously zeroed memory. When loading from a 66 | serial line we could use other methods to identify module EOL. 67 | 68 | Sync `=` asignation can be used when the asigned data will be used on the same 69 | cycle, async `<=` asignation is not warranted when it will be done during that 70 | cycle. 71 | 72 | # 2017-03-15 73 | 74 | Max length of inmediate values is 10 bytes (`i64.const` and `memory_immediate`, 75 | made of two `varuint32` fields). `br_table` has a variable length inmediate with 76 | the fields `target_count`, `target_table` (variable 0-n) and `default_target`, 77 | so just 5 or 10 bytes would be enought. 78 | 79 | [Machine Learning in FPGAs](http://cadlab.cs.ucla.edu/~cong/slides/HALO15_keynote.pdf) 80 | 81 | # 2017-03-16 82 | 83 | [WebAssembly S-expressions](https://developer.mozilla.org/en-US/docs/WebAssembly/Understanding_the_text_format) 84 | 85 | # 2017-03-23 86 | 87 | [FPGAs documentation and projects](http://www.fpga4fun.com) 88 | [Arcade machines implemented on FPGAs](http://www.fpgaarcade.com/) 89 | 90 | # 2017-03-24 91 | 92 | On Travis-CI, Ubuntu `precise` is used by default. To use a newer one set 93 | `dist: trusty` on the `.travis.yml` file, and later add a `sourceline` for the 94 | origin: 95 | 96 | ```yaml 97 | language: verilog 98 | dist: trusty 99 | addons: 100 | apt: 101 | sources: 102 | - sourceline: 'deb http://es.archive.ubuntu.com/ubuntu/ yakkety main universe' 103 | packages: 104 | - iverilog 105 | script: make test 106 | ``` 107 | 108 | Alternatively you can use another distro like `dist: yakkety`, but since it 109 | doesn't has oficial support by Travis team, it will run containerized in Docker. 110 | In that case, it's needed to add `sudo: false` too to be able to install `apt` 111 | packages, but I was unsuccessfull doing so. 112 | 113 | For function calling, since we need to put the arguments on the SuperStack we 114 | have two alternatives: 115 | 116 | 1. raise the underflow limit over the arguments, having an empty stack and 117 | fetching the values with negative indexes (counting them from the signature) 118 | so they get protected of excesive dropping, and when returning do the reset 119 | under the arguments and set the result there 120 | 2. set the underflow limit under the arguments, having them on the stack and 121 | access with positive indexes (arg 0 is index 0 on stack) and returning would 122 | be just a reset and set the result value, but this would allow to overwrite 123 | the arguments by badly designed code... 124 | 125 | # 2017-03-27 126 | 127 | [covered](http://covered.sourceforge.net/) 128 | [In detail info](http://www.testbench.in/TB_24_ABOUT_CODE_COVERAGE.html) about 129 | what means to do code coverage on Verilog and Hardware Definition Languages. 130 | 131 | > "VERIFICATION IS NOT COMPLETED EVEN AFTER 100% CODE COVERAGE" 132 | 133 | ```sh 134 | covered score -t SuperStack_tb -v test/SuperStack_tb.v -vcd build/SuperStack_tb.vcd -I src/ -I test/ 135 | ``` 136 | 137 | # 2017-03-28 138 | 139 | https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf 140 | 141 | For loops and conditionals, we could use a hash table being the instruction 142 | address the key and the value being the destination address, or modify the code 143 | and add custom explicit `jmp` or `goto` instructions. 144 | 145 | `block`s loop forever? https://github.com/WebAssembly/design/issues/261 146 | https://github.com/WebAssembly/design/issues/261#issuecomment-128989537 147 | 148 | # 2017-03-29 149 | 150 | Infinite loops and branch backwards can be implemented with current functions 151 | mechanism, since we already know where they are generated. 152 | 153 | Branch forwards (`if`s, `br`s) could be implemented with a pre-scanned table of 154 | key-values, with addresses pointing to their forward labels (`else`, `end`...). 155 | Since addresses are incremental and static, they can be check in order so no 156 | need to look-up for them, just having a pointer to the next one that needs to be 157 | checked against for based on the current Program Counter. Problems would arise 158 | when PC move backwards (a `loop` or a function call, for example), so pointer 159 | would need to be searched again. This can be done asyncronous and/or in parallel 160 | to regular execution, but maybe would need a flag to set it's not yet ready to 161 | stop execution in case a conditional is find again until it can be evaluated. 162 | 163 | `if` conditionals just only need two `jmp`, one to the address after `else`, and 164 | one from `else` to the address after `end`. 165 | 166 | Verilog support loops, so it could be possible to do an async checker to look on 167 | a map for the instruction address and its destination. 168 | 169 | # 2017-03-30 170 | 171 | Floating point operations are `eq`, `ne`, `lt`, `gt`, `le`, `ge`, `abs`, `neg`, 172 | `ceil`, `floor`, `trunc`, `nearest`, `sqrt`, `add`, `sub`, `mul`, `div`, `min`, 173 | `max` and `copysign`, both for 32 and 64 bits. 174 | Floating point conversions are `float2int` and `int2float` both signed and 175 | unsigned, and 32-to-64 and 64-to-32. 176 | 177 | # 2017-04-02 178 | 179 | Can be branch out of `if` blocks? And from functions? 180 | 181 | [Destructure a wire using binding](http://electronics.stackexchange.com/a/49669) 182 | 183 | GtkWave allow to disable initial splash setting it on a RC file with the 184 | `splash_disable` option. It uses negated logic. 185 | 186 | ```sh 187 | npm access grant read-write nodeos:developers nodeos-barebones 188 | ``` 189 | 190 | # 2017-04-03 191 | 192 | `cpu` can have an `op` input to define what to do, controled by `wasmachine`. 193 | Ops can be to set the PC to the `start` function or read from the stack the 194 | values of a multi-valued return function. 195 | 196 | Loader would have two main tasks, as a decoder of LEB128 values on the module 197 | structure and organice its elements for easy and fast access, and generation of 198 | the jump-forward tables. While doing that tasks it will enable the cpu reset 199 | line so it doesn't execute instructions. 200 | 201 | The need of a wasted cycle is because we are using clock signals on the ROM and 202 | the stacks, so their operation doesn't start until the next tick. Since ROM is 203 | just read-only it would be possible to remove that requeriment and make it just 204 | combinational (and maybe for RAM too for read operations), but for stack will be 205 | more difficult due to so much control logic they have inside, specially 206 | SuperStack. 207 | 208 | # 2017-04-04 209 | 210 | [Associative arrays in SystemVerilog](http://vlsi.pro/system-verilog-associative-arrays/) 211 | 212 | Associative arrays `key_type` [can be defined with `typedef`](http://www.testbench.in/SV_12_ASSOCIATIVE_ARRAYS.html): 213 | 214 | ```verilog 215 | typedef bit signed [4:1] Nibble; 216 | int array_name [ Nibble ]; // Signed packed array 217 | ``` 218 | 219 | [Online Verilog simulator](https://www.edaplayground.com/x/2Qn) 220 | 221 | # 2017-04-05 222 | 223 | Branches can be done using a "extended" version of WebAssembly where block 224 | opcodes accept a second argument with the end address of the block, so it have 225 | the performance advantages of the ad-hoc `jmp` opcode but using less memory and 226 | without the exploit security issue. `if` conditionals would need a third 227 | argument with the address of the `else` block so it can jump there; in case it's 228 | no available it could be zero or the address of the end of the `if` block, but 229 | in both cases it must be checked to don't create a call stack slice. 230 | 231 | `return` can be invoked from inside some nested blocks, so it will be needed a 232 | third stack to store the slice where they are defined and by-pass them. 233 | 234 | `br_table` also requires "extended" WebAssembly, by decoding the LEB128 values 235 | of the table entries. This way they can be accessed directly by their offset. 236 | 237 | # 2017-04-06 238 | 239 | https://github.com/WebAssembly/design/issues/1034 240 | 241 | # 2017-04-08 242 | 243 | Function arguments and local variables live in the same memory space, accessing 244 | them with the `get_local()` and `set_local()` functions, being local variables 245 | after function arguments. Since we are storing function arguments on the stack 246 | itself and protected by `underflow_limit`, a simple (but maybe performance 247 | suboptimal) solution would be add local variables there when calling the 248 | `set_local()` function, moving up all the current stack slices. This way, when 249 | returning the function call, the local variables will dissapear the same way it 250 | happens with the function arguments. 251 | 252 | It's possible to assign data to an array selection, but needs to be double 253 | packet (bi-dimensional) instead of an array of registers. Selection range needs 254 | to be constant. Alternative is to use a `loop` for. 255 | 256 | # 2017-04-10 257 | 258 | Local variables are at function level, so they need to be stored at the blocks 259 | stack. 260 | 261 | Function call arguments are set as stack values, so instead of copy them to the 262 | local function variables, it could be check based on the number of arguments of 263 | the function itself if they must be accessed from the stack or from the local 264 | variables storage. 265 | 266 | Loader will not have direct access to the CPU. Instead, a Controller module will 267 | keep the CPU reset line enabled while not executing a function. Controller will 268 | have a queue of user requests or events to feed the CPU. It will also monitor 269 | the loader until a (new) module gets loaded and add itself a request to exec the 270 | `start` function in case one is defined in the module. 271 | 272 | # 2017-04-12 273 | 274 | https://github.com/WebAssembly/design/issues/1037 275 | 276 | # 2017-04-15 277 | 278 | `br_table` could be optimized by replacing the labels by their actual (relative) 279 | address, since they can't bypass function calls. 280 | Function calls could be optimized by inlining the function metadata instead of 281 | needing to search it on the functions table. 282 | 283 | We need to move branches code to independent module and import it, both for 284 | clean-up and removal of duplicated code, and easier maintenance and testing. 285 | Easiest one would be just to import them in place, but it's not a real module... 286 | 287 | We are using absolute addresses since they will be inlined "on the fly" to their 288 | actual locations and this prevent us of needed to calculate the actual address 289 | on runtime and we don't need Position Independent Code (PIC), but maybe it would 290 | make sense to use relative addresses instead, not only for easier debugging but 291 | also to allow to directly eXecute-in-Place (XiP) extended WebAssembly code, both 292 | from storage and/or ROM. 293 | 294 | https://github.com/steveicarus/iverilog/issues/155 295 | 296 | # 2017-05-16 297 | 298 | Since we are already using our own instructions set (extended WebAssembly), we 299 | could go all down the road and fully define the opcode and/or instructions 300 | format to optimice decoding, replacing the big `case` statement by a small 301 | combinational circuit by using prefixes in the opcode format, or also split the 302 | decoding in several parallel `always` processes, checking and executing just 303 | only the one that matches. 304 | 305 | # 2017-04-17 306 | 307 | http://www.xess.com/shop/product/xula-200/ 308 | 309 | # 2017-04-20 310 | 311 | Olimex board has a SRAM of 10ns time access, and a clock tick of 100MHz. This is 312 | on purposse so the clock period is the same as the SRAM time access, so it can 313 | be read and written sync'ed in a single tick. General CPU clock will need to be 314 | divided and slowered, but a memory controller would be running at the RAM speed 315 | to fetch and buffer the data. 316 | 317 | WASD acronim is still not related to WebAssembly in any known way, and are the 318 | keyboard letters used for games in 90's. Cool for the WebAssembly Extended 319 | format or for a videogames console :-P 320 | 321 | # 2017-04-21 322 | 323 | MemoryController can have queued requests, but changuing from read to write will 324 | need a missed tick to allow to read the data and don't overwrite it. 325 | 326 | When not operating on the memory, disable the `chip select` line to allow it to 327 | enter on energy saving mode. 328 | 329 | # 2017-04-22 330 | 331 | https://github.com/knielsen/ice40_viewer 332 | https://github.com/drom/icedrom 333 | 334 | https://www.reddit.com/r/yosys/comments/4g5mvm/find_path_between_two_regs/ 335 | 336 | # 2017-04-23 337 | 338 | `for` loops with non-constant limits are not sintetizable since they are 339 | un-rolled, so we can't zeroed stack slices for functions initialization. One 340 | alternative would be to set explicitly the zeroes on extended WebAssembly as if 341 | they were function arguments, but this would increase a lot the usage of program 342 | RAM. Another alternatives would be to not zeroed fields, but this goes against 343 | the specification, and use a bitmap of setted slices would complicate things a 344 | bit and also it would be needed someway to set them too... 345 | 346 | Timing the stack shows it uses almost all the logic blocks instead of memory 347 | ones and also is very slow (49MHz), so it needs to find how to use BRAM. Also a 348 | simple clock divisor is someone slow (456MHz), so maybe it's a limitation of the 349 | FPGA or the toolchain itself... 350 | 351 | # 2017-04-24 352 | 353 | ICE40 BRAMs can be directly invoked, but also they should be already sintetized 354 | automatically... 355 | 356 | Reset of adjacent registers in a registers array would be done with several 357 | parallel resets created using `for`, each one for a group of size power of two, 358 | and later using ones or others based on the zeroes and ones of the register 359 | holding the number of registers to be resetted. Base address for each one of the 360 | blocks would need to be set independently and in cascade. Problem with that, 361 | that this can't be used for RAM memory, so another solution would need to be 362 | found... :-/ 363 | 364 | Develop tool to show source code lines describing the critical path, so it can 365 | be optimized. It can be an automation of instructions found at 366 | https://www.reddit.com/r/yosys/comments/4g5mvm/find_path_between_two_regs/d2gcetp/ 367 | 368 | https://www.reddit.com/r/yosys/comments/61z3e7/liberty_libraries/ 369 | 370 | https://github.com/cliffordwolf/yosys/issues/335 371 | 372 | # 2017-04-25 373 | 374 | [Signed comparison in Verilog](http://excamera.com/sphinx/fpga-verilog-sign.html) 375 | 376 | http://icoboard.org/ 377 | 378 | Data probably would need to be padded on BRAMs for faster access if it's not 379 | already done by the compiler itself... 380 | 381 | Singed operations need that BOTH operators are signed. 382 | 383 | # 2017-04-26 384 | 385 | If we consider that both call and block stacks could have the same depth, then 386 | they could be joined in a single stack similar to how databases tables are 387 | "normalized", earning some BRAM memory by not duplicating the fields needed to 388 | manage the operators stack. 389 | 390 | Pipelined designs are implemented using several `always` statements in parallel, 391 | one for each of the stages, and using registers to pass the values to the next 392 | ones and control if workflow should be stopped. 393 | 394 | Of all the possible optimizations, probably the best one is to define and use 395 | our own opcodes format, using fixed prefixes for similar operations. This would 396 | allow to don't need to decode the full opcode previously to process them but 397 | instead simply check the type of the operation and delegate it to its specific 398 | component, that being simpler would also make it easier to test and optimice. 399 | Drawback would be that opcodes would not be so much packed and need to use 400 | several bytes for their identifier. 401 | 402 | Another possible optimization would be to fully decode the LEB128 fields, this 403 | would waste more RAM memory (except on the cases of big numbers, where it would 404 | be reduced) but would earn some logic levels and make some paths shorter. 405 | 406 | http://www.chunder.com/ozinferno/ 407 | https://en.wikipedia.org/wiki/Stack_machine#Able_to_use_Out-of-Order_Execution 408 | [Treegraph-based Instruction Scheduling for Stack-based Virtual Machines](http://www.sciencedirect.com/science/article/pii/S1571066111001538) 409 | 410 | # 2017-04-27 411 | 412 | CPU could be pipelined by adding guards to access to the elements that would 413 | need several cycles, like the stack or memory or FPU, so pipeline gets stalled 414 | until they get available. For elements with a constant delay, this could be 415 | implemented with a counter decreased each cycle like POSIX semaphores, and for 416 | non constant ones then it would be a flag. Obviously, if we manage to make 417 | memory and/or stack to work in a single cycle, the guard would not be needed. 418 | The FPU would need to stall the full CPU until it gets finished since it needs 419 | to write to the stack, but maybe it would be possible to use the same stack 420 | guard. All the operations would be pipelined (also return from blocks and 421 | functions) except the ones that change the Program Counter, that would need to 422 | cancel the next operations and the memory buffer. 423 | 424 | Outputs of ROM and stacks could be in some cases combinational, leading to fetch 425 | then in the next cycle after writting (don't need for an extra one to fetch the 426 | data) and also to shorter paths. 427 | 428 | Async asignations are being done when going out of the `always` block. 429 | 430 | Warning: Replacing memory \stack with list of registers. See src/SuperStack.v:47, src/SuperStack.v:97 431 | 432 | ```verilog 433 | out <= stack[index-1]; 434 | stack[index] = data; 435 | ``` 436 | 437 | https://www.reddit.com/r/yosys/comments/2kgfdr/incorrect_synthesis_results_for_multiport/cln0vnm/ 438 | 439 | http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf 440 | 441 | # 2017-04-28 442 | 443 | Stacks status would be splitted in two fields, status and error. This way would 444 | allow to simplify and speed up its code by not needing blocking assignments and 445 | use instead constant ones and/or several `always` blocks, but at the same time 446 | would allow a better identification of when an actual error has occured. Output 447 | of stack values and for `UNDERFLOW_GET` would also splitted instead of reused, 448 | leading to better isolation and also allow to do the same improvements too. 449 | 450 | # 2017-04-29 451 | 452 | By disabling the filling of zeroes we improve performance more than twice (25-60 453 | MHz) almost up to the regular stack (70 MHz). Alternatives would be to do the 454 | zeroed in parallel by preserving someway the base address for each group, or 455 | using a bitmap of the setted variables on each call slice, or do the zeroed in 456 | several cycles by using a requests queue. 457 | 458 | When using blocking assigment and reuse of `index` on stack `POP` the frequency 459 | was up to 78.72 MHz, while using nonblocking and duplicated code it lowered down 460 | to 75.08 MHz. On the other hand, using nonblocking assigment and another 461 | `always` block it raised up to 80.23 MHz. All of them simulating for HX8k. 462 | 463 | # 2017-04-30 464 | 465 | CPU synth speed (hx8k): 466 | 467 | HAS_FPU | HAS_RAM | USE_64B 468 | ============================= 469 | No | No | No | 54.17 MHz 470 | No | No | Yes | Failed 471 | Yes | No | No | 54.17 MHz 472 | Yes | Yes | Yes | Failed 473 | 474 | In the successful cases, the longest path has 6 logic levels and it's related to 475 | decodification of LEB128 i64 values (i0[7] -> o[24]). 476 | 477 | In the cases where it failed, it lasted several minutes versus the few seconds 478 | it lasted in the other cases, and it was when executing `berkeley-abc` with the 479 | next output: 480 | 481 | ``` 482 | Running ABC command: berkeley-abc -s -f /abc.script 2>&1 483 | ABC: ABC command line: "source /abc.script". 484 | ABC: 485 | ABC: + read_blif /input.blif 486 | ABC: + read_lut /lutdefs.txt 487 | ABC: + strash 488 | ABC: + dc2 489 | ABC: + scorr 490 | ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 491 | ABC: + ifraig 492 | ABC: + retime -o 493 | ABC: + strash 494 | ABC: + dch -f 495 | ABC: + if 496 | ABC: + mfs 497 | ABC: + lutpack 498 | ABC: berkeley-abc: src/opt/lpk/lpkCore.c:471: Lpk_ResynthesizeNodeNew: Assertion `Abc_ObjLevel(pObjNew) <= Required' failed. 499 | ABC: Aborted (core dumped) 500 | ERROR: ABC: execution of command "berkeley-abc -s -f /tmp/yosys-abc-PzfHLu/abc.script 2>&1" failed: return code 134. 501 | ``` 502 | 503 | Seems it's related to the long paths needed for the synthetization of a 64 bits 504 | divisor, that `berkeley-abc` is not able to fully manage so long paths. 505 | 506 | https://github.com/WebAssembly/design/issues/1050 507 | 508 | https://github.com/kanaka/wac 509 | 510 | # 2017-05-01 511 | 512 | [Update BRAM without regenerate net list](http://stackoverflow.com/a/36858486/586382) 513 | 514 | According to http://stackoverflow.com/a/41509289/586382, seems that the BRAM 515 | inference just only replace an array of registers and their manipulation with 516 | its equivalent code using the correct simulation model just like a preprocessor, 517 | there's no magic or configuration involved and both are interchangeable. 518 | 519 | http://stackoverflow.com/questions/41499494/how-can-i-use-ice40-4k-block-ram-in-512x8-read-mode-with-icestorm?rq=1#comment74479435_41509289 520 | 521 | # 2017-05-04 522 | 523 | Iverilog `-P.=` allow to set parameters from command 524 | line. 525 | 526 | `==` compares only `0`'s and `1`'s, giving undefined if any bit is `x` or `z`. 527 | `===` compares also the `x` and `z` bits. 528 | -------------------------------------------------------------------------------- /src/SuperStack.v: -------------------------------------------------------------------------------- 1 | /* 2 | * SuperStack 3 | * 4 | * (c) 2017 - Jesús Leganés-Combarro 'piranna' 5 | * 6 | * Based on https://github.com/whitequark/bfcpu2/blob/master/verilog/Stack.v 7 | */ 8 | 9 | `include "SuperStack.vh" 10 | 11 | 12 | `default_nettype none 13 | 14 | module SuperStack 15 | #( 16 | parameter WIDTH = 8, // bits 17 | parameter DEPTH = 3, // frames (exponential) 18 | parameter ZEROED_SLICES = 0 19 | ) 20 | ( 21 | input clk, 22 | input reset, 23 | 24 | input [ 2:0] op, // none / push / pop / replace / 25 | // index_reset / index_push / 26 | // underflow_get / underflow_set 27 | input [WIDTH-1:0] data, // Data to be inserted on the stack 28 | input [DEPTH :0] offset, // position of getter/setter/new index 29 | input [DEPTH :0] underflow_limit, // Depth of underflow error 30 | input [DEPTH :0] upper_limit, // Underflow get/set upper limit 31 | input [DEPTH :0] lower_limit, // Underflow get/set lower limit 32 | input dropTos, 33 | output reg [DEPTH :0] index = 0, // Current top of stack position 34 | output [WIDTH-1:0] out, // top of stack 35 | output [WIDTH-1:0] out1, 36 | output [WIDTH-1:0] out2, 37 | 38 | output reg [WIDTH-1:0] getter, // Output of getter 39 | 40 | output reg [1:0] status = `EMPTY, // none / empty / full / underflow 41 | output reg [1:0] error = `NONE // none / underflow / overflow 42 | ); 43 | 44 | localparam MAX_STACK = (1 << DEPTH+1) - 1; 45 | 46 | reg [WIDTH-1:0] stack [0:MAX_STACK-1]; 47 | 48 | assign out = stack[index-1]; 49 | assign out1 = stack[index-2]; 50 | assign out2 = stack[index-3]; 51 | 52 | // Adjust status when index or underflow limit or stack content has¡ve changed 53 | always @* begin 54 | if(index == MAX_STACK) 55 | status <= `FULL; 56 | else if(index == underflow_limit) 57 | status <= `EMPTY; 58 | else if(index < underflow_limit) 59 | status <= `UNDERFLOW; 60 | else 61 | status <= `NONE; 62 | end 63 | 64 | /** 65 | * Fill the stack slices with zeroes if new index is greater than current one 66 | */ 67 | task zeroedIndex; 68 | reg [$clog2(DEPTH+1):0] i; 69 | reg [ DEPTH :0] j; 70 | reg [ DEPTH :0] o = 0; 71 | reg [ DEPTH :0] slice; 72 | 73 | // By disabling the filling of zeroes we improve performance more than twice 74 | // (25-60 MHz) almost up to the regular stack (70 MHz). Alternatives would 75 | // be to do the zeroed in parallel by preserving someway the base address 76 | // for each group, or using a bitmap of the setted variables on each call 77 | // slice, or do the zeroed in several cycles by using a requests queue. 78 | if(ZEROED_SLICES && index < offset) begin 79 | slice = offset - index; 80 | 81 | for(i=0; i < DEPTH+1; i = i + 1) 82 | if(slice[i]) 83 | for(j=0; j < 2**i; j = j + 1) begin 84 | stack[index+o] = 0; 85 | o = o + 1; 86 | end 87 | end 88 | endtask 89 | 90 | always @(posedge clk) begin 91 | error <= `NONE; 92 | 93 | if(reset) 94 | index <= 0; 95 | 96 | else 97 | case(op) 98 | `PUSH: 99 | begin 100 | // Stack is full 101 | if (index == MAX_STACK) 102 | error <= `OVERFLOW; 103 | 104 | // Push data to ToS 105 | else begin 106 | stack[index] <= data; 107 | 108 | index <= index + 1; 109 | end 110 | end 111 | 112 | `POP: 113 | begin 114 | if (index-data <= underflow_limit) 115 | error <= `UNDERFLOW; 116 | 117 | else 118 | index <= index - (1+data); 119 | end 120 | 121 | `REPLACE: 122 | begin 123 | if (index <= underflow_limit) 124 | error <= `UNDERFLOW; 125 | 126 | else 127 | stack[index-1] <= data; 128 | end 129 | 130 | `INDEX_RESET: 131 | begin 132 | zeroedIndex(); 133 | 134 | index <= offset; 135 | end 136 | 137 | `INDEX_RESET_AND_PUSH: 138 | begin 139 | // New index is equal to MAX_STACK, raise error 140 | if (offset == MAX_STACK) 141 | error <= `OVERFLOW; 142 | 143 | else begin 144 | zeroedIndex(); 145 | 146 | stack[offset] <= data; 147 | 148 | index <= offset+1; 149 | end 150 | end 151 | 152 | `UNDERFLOW_GET: 153 | begin 154 | if (upper_limit - lower_limit <= offset) 155 | error <= `BAD_OFFSET; 156 | 157 | else 158 | getter <= stack[lower_limit + offset]; 159 | end 160 | 161 | `UNDERFLOW_SET: 162 | begin 163 | if (upper_limit - lower_limit <= offset) 164 | error <= `BAD_OFFSET; 165 | 166 | else if(dropTos && index == underflow_limit) 167 | error <= `UNDERFLOW; 168 | 169 | else begin 170 | stack[lower_limit + offset] <= data; 171 | 172 | if(dropTos) index <= index - 1; 173 | end 174 | end 175 | endcase 176 | end 177 | 178 | endmodule 179 | -------------------------------------------------------------------------------- /src/SuperStack.vh: -------------------------------------------------------------------------------- 1 | `include "stack.vh" 2 | 3 | // Operations 4 | `define INDEX_RESET 4 5 | `define INDEX_RESET_AND_PUSH 5 6 | `define UNDERFLOW_GET 6 7 | `define UNDERFLOW_SET 7 8 | 9 | // Errors 10 | `define BAD_OFFSET 3 11 | -------------------------------------------------------------------------------- /src/cpu.vh: -------------------------------------------------------------------------------- 1 | // Types 2 | `define i32 (HAS_FPU ? (USE_64B ? 2'b00 : 1'b0) : (USE_64B ? 1'b0 : 2'bx)) 3 | `define i64 (HAS_FPU ? (USE_64B ? 2'b01 : 1'b0) : (USE_64B ? 1'b1 : 2'bx)) 4 | `define f32 (HAS_FPU ? (USE_64B ? 2'b10 : 1'b1) : (USE_64B ? 1'b0 : 2'bx)) 5 | `define f64 (HAS_FPU ? (USE_64B ? 2'b11 : 1'b1) : (USE_64B ? 1'b1 : 2'bx)) 6 | 7 | // Traps 8 | `define NONE 0 9 | `define ENDED 1 10 | `define STACK_EMPTY 2 11 | `define STACK_ERROR 3 12 | `define BLOCK_STACK_EMPTY 4 13 | `define BLOCK_STACK_ERROR 5 14 | `define CALL_STACK_ERROR 6 15 | `define MEM_ERROR 7 16 | `define UNREACHABLE 8 17 | `define BAD_BLOCK_TYPE 9 18 | `define TYPE_MISMATCH 10 19 | `define UNKOWN_OPCODE 11 20 | `define TYPES_MISMATCH 12 21 | `define NO_FPU 13 22 | `define NO_RAM 14 23 | `define NO_64B 15 24 | 25 | // blocks 26 | `define block 2'h0 27 | `define block_loop 2'h1 28 | `define block_if 2'h2 29 | -------------------------------------------------------------------------------- /src/genrom.v: -------------------------------------------------------------------------------- 1 | /** 2 | * Generic ROM memory 3 | * 4 | * (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan) 5 | * GPL license 6 | * 7 | * Memory with the next parameters: 8 | * - AW: Number of bits for directions 9 | * - DW: Number of bits for data 10 | * - ROMFILE: File to be used to load the memory 11 | */ 12 | 13 | module genrom #( // Parameters 14 | parameter AW = 4, // Address width in bits 15 | parameter DW = 8, // Data witdh in bits 16 | parameter EXTRA = 4 17 | ) 18 | ( // Ports 19 | input clk, // Global clock signal 20 | input wire [ AW :0] addr, // Address 21 | input wire [ EXTRA-1:0] extra, // Length of data to be fetch 22 | input wire [ AW :0] lower_bound, 23 | input wire [ AW :0] upper_bound, 24 | output reg [2**EXTRA*DW-1:0] data=0, // Output data 25 | output reg error=0 // none / out of limits 26 | ); 27 | 28 | // Parameter: name of the file with the ROM content 29 | parameter ROMFILE = "prog.list"; 30 | 31 | // Calc the number of total positions of memory 32 | localparam NPOS = 1 << (AW+1); 33 | 34 | // Memory 35 | reg [DW-1: 0] rom [0: NPOS-1]; 36 | 37 | // Read the memory 38 | always @(posedge clk) begin 39 | error <= addr < lower_bound || addr > upper_bound; 40 | 41 | case (extra) 42 | 0: data <= rom[addr ]; 43 | 1: data <= {rom[addr ], rom[addr+ 1]}; 44 | 2: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2]}; 45 | 3: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3]}; 46 | 4: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 47 | rom[addr+ 4]}; 48 | 5: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 49 | rom[addr+ 4], rom[addr+ 5]}; 50 | 6: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 51 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6]}; 52 | 7: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 53 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7]}; 54 | 8: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 55 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 56 | rom[addr+ 8]}; 57 | 9: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 58 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 59 | rom[addr+ 8], rom[addr+ 9]}; 60 | 10: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 61 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 62 | rom[addr+ 8], rom[addr+ 9], rom[addr+10]}; 63 | 11: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 64 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 65 | rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11]}; 66 | 12: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 67 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 68 | rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11], 69 | rom[addr+12]}; 70 | 13: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 71 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 72 | rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11], 73 | rom[addr+12], rom[addr+13]}; 74 | 14: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 75 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 76 | rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11], 77 | rom[addr+12], rom[addr+13], rom[addr+14]}; 78 | 15: data <= {rom[addr ], rom[addr+ 1], rom[addr+ 2], rom[addr+ 3], 79 | rom[addr+ 4], rom[addr+ 5], rom[addr+ 6], rom[addr+ 7], 80 | rom[addr+ 8], rom[addr+ 9], rom[addr+10], rom[addr+11], 81 | rom[addr+12], rom[addr+13], rom[addr+14], rom[addr+15]}; 82 | endcase 83 | end 84 | 85 | // Load in memory the `ROMFILE` file. Values must be given in hexadecimal 86 | initial begin 87 | $readmemh(ROMFILE, rom); 88 | end 89 | 90 | endmodule 91 | -------------------------------------------------------------------------------- /src/opcodes.vh: -------------------------------------------------------------------------------- 1 | // Control flow operators 2 | `define op_unreachable 8'h00 3 | `define op_nop 8'h01 4 | `define op_block 8'h02 5 | `define op_loop 8'h03 6 | `define op_if 8'h04 7 | `define op_else 8'h05 8 | `define op_end 8'h0b 9 | `define op_br 8'h0c 10 | `define op_br_if 8'h0d 11 | `define op_br_table 8'h0e 12 | `define op_return 8'h0f 13 | 14 | // Call operators 15 | `define op_call 8'h10 16 | 17 | // Parametric operators 18 | `define op_drop 8'h1a 19 | `define op_select 8'h1b 20 | 21 | // Variable access 22 | `define op_get_local 8'h20 23 | `define op_set_local 8'h21 24 | `define op_tee_local 8'h22 25 | 26 | // Memory-related operators 27 | 28 | // Constants 29 | `define op_i32_const 8'h41 30 | `define op_i64_const 8'h42 31 | `define op_f32_const 8'h43 32 | `define op_f64_const 8'h44 33 | 34 | // Comparison operators 35 | `define op_i32_eqz 8'h45 36 | `define op_i32_eq 8'h46 37 | `define op_i32_ne 8'h47 38 | `define op_i32_lt_s 8'h48 39 | `define op_i32_lt_u 8'h49 40 | `define op_i32_gt_s 8'h4a 41 | `define op_i32_gt_u 8'h4b 42 | `define op_i32_le_s 8'h4c 43 | `define op_i32_le_u 8'h4d 44 | `define op_i32_ge_s 8'h4e 45 | `define op_i32_ge_u 8'h4f 46 | `define op_i64_eqz 8'h50 47 | `define op_i64_eq 8'h51 48 | `define op_i64_ne 8'h52 49 | `define op_i64_lt_s 8'h53 50 | `define op_i64_lt_u 8'h54 51 | `define op_i64_gt_s 8'h55 52 | `define op_i64_gt_u 8'h56 53 | `define op_i64_le_s 8'h57 54 | `define op_i64_le_u 8'h58 55 | `define op_i64_ge_s 8'h59 56 | `define op_i64_ge_u 8'h5a 57 | 58 | // Numeric operators 59 | `define op_i32_clz 8'h67 60 | `define op_i32_ctz 8'h68 61 | `define op_i32_popcnt 8'h69 62 | `define op_i32_add 8'h6a 63 | `define op_i32_sub 8'h6b 64 | `define op_i32_mul 8'h6c 65 | `define op_i32_div_s 8'h6d 66 | `define op_i32_div_u 8'h6e 67 | `define op_i32_rem_s 8'h6f 68 | `define op_i32_rem_u 8'h70 69 | `define op_i32_and 8'h71 70 | `define op_i32_or 8'h72 71 | `define op_i32_xor 8'h73 72 | `define op_i32_shl 8'h74 73 | `define op_i32_shr_s 8'h75 74 | `define op_i32_shr_u 8'h76 75 | `define op_i32_rotl 8'h77 76 | `define op_i32_rotr 8'h78 77 | `define op_i64_clz 8'h79 78 | `define op_i64_ctz 8'h7a 79 | `define op_i64_popcnt 8'h7b 80 | `define op_i64_add 8'h7c 81 | `define op_i64_sub 8'h7d 82 | `define op_i64_mul 8'h7e 83 | `define op_i64_div_s 8'h7f 84 | `define op_i64_div_u 8'h80 85 | `define op_i64_rem_s 8'h81 86 | `define op_i64_rem_u 8'h82 87 | `define op_i64_and 8'h83 88 | `define op_i64_or 8'h84 89 | `define op_i64_xor 8'h85 90 | `define op_i64_shl 8'h86 91 | `define op_i64_shr_s 8'h87 92 | `define op_i64_shr_u 8'h88 93 | `define op_i64_rotl 8'h89 94 | `define op_i64_rotr 8'h8a 95 | 96 | // Conversions 97 | `define op_i32_wrap_i64 8'ha7 98 | `define op_i64_extend_s_i32 8'hac 99 | `define op_i64_extend_u_i32 8'had 100 | `define op_f32_demote_f64 8'hb6 101 | `define op_f64_promote_f32 8'hbb 102 | 103 | // Reinterpretations 104 | `define op_i32_reinterpret_f32 8'hbc 105 | `define op_i64_reinterpret_f64 8'hbd 106 | `define op_f32_reinterpret_i32 8'hbe 107 | `define op_f64_reinterpret_i64 8'hbf 108 | -------------------------------------------------------------------------------- /src/stack.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Stack 3 | * 4 | * (c) 2017 - Jesús Leganés-Combarro 'piranna' 5 | * 6 | * Based on https://github.com/whitequark/bfcpu2/blob/master/verilog/Stack.v 7 | */ 8 | 9 | `include "stack.vh" 10 | 11 | 12 | `default_nettype none 13 | 14 | module stack 15 | #( 16 | parameter WIDTH = 8, // bits 17 | parameter DEPTH = 3 // frames (exponential) 18 | ) 19 | ( 20 | input clk, 21 | input reset, 22 | 23 | input [ 1:0] op, // none / push / pop / replace 24 | input [WIDTH-1:0] data, // Data to be inserted on the stack 25 | output [WIDTH-1:0] tos, // What's currently on the Top of Stack 26 | 27 | output reg [1:0] status = `EMPTY, // none / empty / full / underflow 28 | output reg [1:0] error = `NONE // none / underflow / overflow 29 | ); 30 | 31 | localparam MAX_STACK = (1 << DEPTH+1) - 1; 32 | 33 | reg [WIDTH-1:0] stack [0:MAX_STACK-1]; 34 | reg [ DEPTH:0] index = 0; 35 | 36 | assign tos = stack[index-1]; 37 | 38 | // Adjust status when index has changed 39 | always @* begin 40 | if(index == MAX_STACK) 41 | status <= `FULL; 42 | else if(index == 0) 43 | status <= `EMPTY; 44 | else 45 | status <= `NONE; 46 | end 47 | 48 | always @(posedge clk) begin 49 | error <= `NONE; 50 | 51 | if (reset) 52 | index <= 0; 53 | 54 | else 55 | case(op) 56 | `PUSH: 57 | begin 58 | // Stack is full 59 | if (index == MAX_STACK) 60 | error <= `OVERFLOW; 61 | 62 | // Push data to ToS 63 | else begin 64 | stack[index] <= data; 65 | 66 | index <= index + 1; 67 | end 68 | end 69 | 70 | `POP: 71 | begin 72 | if (index-data <= 0) 73 | error <= `UNDERFLOW; 74 | 75 | else 76 | index <= index - (1+data); 77 | end 78 | 79 | `REPLACE: 80 | begin 81 | if (index == 0) 82 | error <= `UNDERFLOW; 83 | 84 | else 85 | stack[index-1] <= data; 86 | end 87 | endcase 88 | end 89 | 90 | endmodule 91 | -------------------------------------------------------------------------------- /src/stack.vh: -------------------------------------------------------------------------------- 1 | `define NONE 0 2 | 3 | // Operations 4 | `define PUSH 1 5 | `define POP 2 6 | `define REPLACE 3 7 | 8 | // Status 9 | `define UNDERFLOW 1 10 | `define EMPTY 2 11 | `define FULL 3 12 | 13 | // Errors 14 | `define OVERFLOW 2 15 | -------------------------------------------------------------------------------- /test/SuperStack_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI 3 | [*] Mon Apr 10 22:39:35 2017 4 | [*] 5 | [dumpfile] "/home/piranna/github/wasmachine/build/SuperStack_tb.vcd" 6 | [dumpfile_mtime] "Mon Apr 10 22:38:10 2017" 7 | [dumpfile_size] 2756 8 | [savefile] "/home/piranna/github/wasmachine/test/SuperStack_tb.gtkw" 9 | [timestart] 14 10 | [size] 1366 720 11 | [pos] -1 -1 12 | *-3.136468 31 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] SuperStack_tb. 14 | [treeopen] SuperStack_tb.dut. 15 | [sst_width] 213 16 | [signals_width] 217 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 293 19 | @28 20 | SuperStack_tb.clk 21 | SuperStack_tb.reset 22 | @200 23 | - 24 | @28 25 | SuperStack_tb.op[2:0] 26 | @22 27 | SuperStack_tb.data[7:0] 28 | @28 29 | SuperStack_tb.offset[1:0] 30 | SuperStack_tb.underflow_limit[1:0] 31 | @29 32 | SuperStack_tb.upper_limit[1:0] 33 | @200 34 | - 35 | @28 36 | SuperStack_tb.index[1:0] 37 | @22 38 | SuperStack_tb.out[7:0] 39 | SuperStack_tb.out1[7:0] 40 | SuperStack_tb.out2[7:0] 41 | @c00028 42 | SuperStack_tb.status[2:0] 43 | @28 44 | (0)SuperStack_tb.status[2:0] 45 | (1)SuperStack_tb.status[2:0] 46 | (2)SuperStack_tb.status[2:0] 47 | @1401200 48 | -group_end 49 | @200 50 | - 51 | @28 52 | SuperStack_tb.dut.getStatus.getStatus[2:0] 53 | [pattern_trace] 1 54 | [pattern_trace] 0 55 | -------------------------------------------------------------------------------- /test/SuperStack_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "SuperStack.vh" 4 | 5 | 6 | module SuperStack_tb(); 7 | 8 | parameter WIDTH = 8; 9 | parameter DEPTH = 1; // frames (exponential) 10 | 11 | localparam MAX_STACK = (1 << DEPTH+1) - 1; 12 | 13 | reg clk = 0; 14 | reg reset; 15 | reg [ 2:0] op; 16 | reg [WIDTH-1:0] data; 17 | reg [DEPTH :0] offset; 18 | reg [DEPTH :0] underflow_limit=0; 19 | reg [DEPTH :0] upper_limit=0; 20 | wire [DEPTH :0] index; 21 | wire [WIDTH-1:0] out; 22 | wire [WIDTH-1:0] out1; 23 | wire [WIDTH-1:0] out2; 24 | wire [WIDTH-1:0] getter; 25 | wire [ 1:0] status; 26 | wire [ 1:0] error; 27 | 28 | SuperStack #( 29 | .WIDTH(WIDTH), 30 | .DEPTH(DEPTH), 31 | .ZEROED_SLICES(1) 32 | ) 33 | dut( 34 | .clk(clk), 35 | .reset(reset), 36 | .op(op), 37 | .data(data), 38 | .offset(offset), 39 | .underflow_limit(underflow_limit), 40 | .upper_limit(upper_limit), 41 | .lower_limit(2'b0), 42 | .dropTos(1'b0), 43 | .index(index), 44 | .out(out), 45 | .out1(out1), 46 | .out2(out2), 47 | .getter(getter), 48 | .status(status), 49 | .error(error) 50 | ); 51 | 52 | always #1 clk = ~clk; 53 | 54 | initial begin 55 | $dumpfile("SuperStack_tb.vcd"); 56 | $dumpvars(0, SuperStack_tb); 57 | 58 | // `status` is `empty` by default 59 | `assert(status, `EMPTY); 60 | 61 | // Underflow 62 | op <= `POP; 63 | data <= 0; 64 | #2 65 | `assert(error, `UNDERFLOW); 66 | 67 | // Push 68 | op <= `PUSH; 69 | data <= 0; 70 | #2 71 | `assert(status, `NONE); 72 | `assert(out , 8'h00); 73 | 74 | op <= `PUSH; 75 | data <= 1; 76 | #2 77 | `assert(status, `NONE); 78 | `assert(out , 8'h01); 79 | `assert(out1 , 8'h00); 80 | 81 | op <= `PUSH; 82 | data <= 2; 83 | #2 84 | `assert(status, `FULL); 85 | `assert(out , 8'h02); 86 | `assert(out1 , 8'h01); 87 | `assert(out2 , 8'h00); 88 | 89 | // Top of Stack 90 | op <= `NONE; 91 | #2 92 | `assert(status, `FULL); 93 | `assert(out , 8'h02); 94 | `assert(out1 , 8'h01); 95 | `assert(out2 , 8'h00); 96 | 97 | // Overflow 98 | op <= `PUSH; 99 | data <= 3; 100 | #2 101 | `assert(error, `OVERFLOW); 102 | `assert(out , 8'h02); 103 | `assert(out1 , 8'h01); 104 | `assert(out2 , 8'h00); 105 | 106 | // Pop 107 | op <= `POP; 108 | data <= 0; 109 | #2 110 | `assert(status, `NONE); 111 | `assert(out , 8'h01); 112 | `assert(out1 , 8'h00); 113 | 114 | op <= `POP; 115 | data <= 0; 116 | #2 117 | `assert(status, `NONE); 118 | `assert(out , 8'h00); 119 | 120 | op <= `POP; 121 | data <= 0; 122 | #2 123 | `assert(status, `EMPTY); 124 | 125 | // Replace 126 | op <= `REPLACE; 127 | data <= 4; 128 | #2 129 | `assert(error, `UNDERFLOW); 130 | 131 | op <= `PUSH; 132 | data <= 5; 133 | #2 134 | `assert(status, `NONE); 135 | `assert(out , 8'h05); 136 | 137 | op <= `REPLACE; 138 | data <= 6; 139 | #2 140 | `assert(status, `NONE); 141 | `assert(out , 8'h06); 142 | 143 | op <= `NONE; 144 | #2 145 | `assert(status, `NONE); 146 | `assert(out , 8'h06); 147 | 148 | // Reset 149 | reset <= 1; 150 | #2 151 | reset <= 0; 152 | `assert(status, `EMPTY); 153 | `assert(index , 0); 154 | 155 | // 156 | // Underflow limit 157 | // 158 | 159 | // Underflow after change limit 160 | op <= `NONE; 161 | underflow_limit <= 1; 162 | #2 163 | `assert(status, `UNDERFLOW); 164 | // `assert(out , 8'h06); 165 | `assert(index , 0); 166 | 167 | // Push data while we are under the underflow limit... 168 | // and get an empty stack! Magic! :-P 169 | op <= `PUSH; 170 | data <= 8; 171 | #2 172 | `assert(status, `EMPTY); 173 | `assert(out , 8'h08); 174 | `assert(index , 1); 175 | 176 | // Reset with underflow limit set 177 | op <= `PUSH; 178 | data <= 9; 179 | #2 180 | `assert(status, `NONE); 181 | `assert(out , 8'h09); 182 | `assert(out1 , 8'h08); 183 | `assert(index , 2); 184 | 185 | op <= `INDEX_RESET; 186 | offset <= 1; 187 | #2 188 | `assert(status, `EMPTY); 189 | `assert(out , 8'h08); 190 | `assert(index , 1); 191 | 192 | // Get underflow error when underflow limit is not zero (data is protected) 193 | op <= `POP; 194 | data <= 0; 195 | #2 196 | op <= `NONE; 197 | `assert(error, `UNDERFLOW); 198 | `assert(out , 8'h08); 199 | `assert(index, 1); 200 | 201 | // Reset underflow limit, and now we can access the data 202 | underflow_limit <= 0; 203 | #2 204 | `assert(status, `NONE); 205 | `assert(out , 8'h08); 206 | `assert(index , 1); 207 | 208 | // Get empty when index get zero 209 | op <= `POP; 210 | data <= 0; 211 | #2 212 | `assert(status, `EMPTY); 213 | `assert(index , 0); 214 | 215 | // Underflow reset push 216 | op <= `INDEX_RESET_AND_PUSH; 217 | data <= 10; 218 | underflow_limit <= 2; 219 | offset <= 0; 220 | #2 221 | `assert(status, `UNDERFLOW); 222 | `assert(out , 8'h0a); 223 | `assert(index , 1); 224 | 225 | op <= `INDEX_RESET_AND_PUSH; 226 | data <= 11; 227 | underflow_limit <= 0; 228 | #2 229 | `assert(status, `NONE); 230 | `assert(out , 8'h0b); 231 | `assert(index , 1); 232 | 233 | // Underfow set 234 | op <= `UNDERFLOW_SET; 235 | data <= 12; 236 | underflow_limit <= 1; 237 | offset <= 0; 238 | #2 239 | `assert(error, `BAD_OFFSET); 240 | `assert(out , 8'h0b); 241 | `assert(index, 1); 242 | 243 | upper_limit <= 1; 244 | #2 245 | `assert(status, `EMPTY); 246 | `assert(out , 8'h0c); 247 | `assert(index , 1); 248 | 249 | op <= `NONE; 250 | #2 251 | `assert(status, `EMPTY); 252 | `assert(index , 1); 253 | 254 | op <= `PUSH; 255 | data <= 13; 256 | #2 257 | `assert(status, `NONE); 258 | `assert(out , 8'h0d); 259 | `assert(index , 2); 260 | 261 | // Underfow get 262 | offset <= 0; 263 | op <= `UNDERFLOW_GET; 264 | #2 265 | `assert(status, `NONE); 266 | `assert(getter, 8'h0c); 267 | `assert(index , 2); 268 | 269 | offset <= 1; 270 | op <= `UNDERFLOW_GET; 271 | #2 272 | `assert(error, `BAD_OFFSET); 273 | `assert(index, 2); 274 | 275 | // Reset index over current one and fill with zeroes 276 | op <= `INDEX_RESET; 277 | offset <= 3; 278 | #2 279 | `assert(status, `FULL); 280 | `assert(out , 8'h00); 281 | `assert(out1 , 8'h0d); 282 | `assert(out2 , 8'h0c); 283 | `assert(index , 3); 284 | 285 | $finish; 286 | end 287 | 288 | endmodule 289 | -------------------------------------------------------------------------------- /test/assert.vh: -------------------------------------------------------------------------------- 1 | /** 2 | * Based on code from http://stackoverflow.com/a/31302223/586382 3 | */ 4 | `define assert(signal, value) \ 5 | if (signal !== value) begin \ 6 | `ifdef __LINE__ \ 7 | $display("ASSERTION FAILED in %m:%d: signal != value", `__LINE__); \ 8 | `else \ 9 | $display("ASSERTION FAILED in %m: signal != value"); \ 10 | `endif \ 11 | $stop; \ 12 | end 13 | -------------------------------------------------------------------------------- /test/cpu/block.hex: -------------------------------------------------------------------------------- 1 | 02 7e 00 00 00 09 // block 2 | 42 2a // i64.const 42 3 | 0b // end 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/block_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 3; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("block.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("block_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 42); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/br.hex: -------------------------------------------------------------------------------- 1 | 02 7e 00 00 00 0d // block 2 | 42 2a // i64.const 42 3 | 0c 00 // br 0 4 | 42 15 // i64.const 21 5 | 0b // end 6 | 0b // end 7 | -------------------------------------------------------------------------------- /test/cpu/br_if.hex: -------------------------------------------------------------------------------- 1 | 02 7e 00 00 00 0f // block 2 | 42 2a // i64.const 42 3 | 41 01 // i32.const 1 4 | 0d 00 // br_if 0 5 | 42 15 // i64.const 21 6 | 0b // end 7 | 0b // end 8 | -------------------------------------------------------------------------------- /test/cpu/br_if_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 3; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("br_if.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | reg reset = 0; 47 | wire [63:0] result; 48 | wire result_empty; 49 | wire [ 3:0] trap; 50 | 51 | cpu #( 52 | .MEM_DEPTH(MEM_ADDR) 53 | ) 54 | dut 55 | ( 56 | .clk(clk), 57 | .reset(reset), 58 | .result(result), 59 | .result_empty(result_empty), 60 | .trap(trap), 61 | .mem_addr(mem_addr), 62 | .mem_extra(mem_extra), 63 | .mem_data(mem_data), 64 | .mem_error(mem_error) 65 | ); 66 | 67 | always #1 clk = ~clk; 68 | 69 | initial begin 70 | $dumpfile("br_if_tb.vcd"); 71 | $dumpvars(0, cpu_tb); 72 | 73 | #30 74 | `assert(result, 42); 75 | `assert(result_empty, 0); 76 | `assert(trap, `ENDED); 77 | 78 | $finish; 79 | end 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /test/cpu/br_table1.hex: -------------------------------------------------------------------------------- 1 | 02 7e 00 00 00 2d // block 2 | 02 7e 00 00 00 29 // block 3 | 02 7e 00 00 00 25 // block 4 | 42 03 // i64.const 3 5 | 6 | 41 00 // i32.const 0 7 | 0e 02 // br_table 2 8 | 00 00 00 02 // 2 9 | 00 00 00 01 // 1 10 | 00 00 00 00 // default - 0 11 | 0b // end 12 | 13 | 42 05 // i64.const 5 14 | 7c // i64.add 15 | 0b // end 16 | 17 | 42 04 // i64.const 4 18 | 7c // i64.add 19 | 0b // end 20 | 21 | 0b // end 22 | -------------------------------------------------------------------------------- /test/cpu/br_table1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("br_table1.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("br_table1_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #50 82 | `assert(result, 3); 83 | `assert(result_type, `i64); 84 | `assert(result_empty, 0); 85 | `assert(trap, `ENDED); 86 | end 87 | else begin 88 | #24 89 | `assert(trap, `NO_64B); 90 | end 91 | 92 | $finish; 93 | end 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /test/cpu/br_table2.hex: -------------------------------------------------------------------------------- 1 | 02 7e 00 00 00 2d // block 2 | 02 7e 00 00 00 29 // block 3 | 02 7e 00 00 00 25 // block 4 | 42 03 // i64.const 3 5 | 6 | 41 01 // i32.const 1 7 | 0e 02 // br_table 2 8 | 00 00 00 02 // 2 9 | 00 00 00 01 // 1 10 | 00 00 00 00 // default - 0 11 | 0b // end 12 | 13 | 42 05 // i64.const 5 14 | 7c // i64.add 15 | 0b // end 16 | 17 | 42 04 // i64.const 4 18 | 7c // i64.add 19 | 0b // end 20 | 21 | 0b // end 22 | -------------------------------------------------------------------------------- /test/cpu/br_table2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("br_table2.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("br_table2_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #72 82 | `assert(result, 7); 83 | `assert(result_type, `i64); 84 | `assert(result_empty, 0); 85 | `assert(trap, `ENDED); 86 | end 87 | else begin 88 | #24 89 | `assert(trap, `NO_64B); 90 | end 91 | 92 | $finish; 93 | end 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /test/cpu/br_table3.hex: -------------------------------------------------------------------------------- 1 | 02 7e 00 00 00 2d // block 2 | 02 7e 00 00 00 29 // block 3 | 02 7e 00 00 00 25 // block 4 | 42 03 // i64.const 3 5 | 6 | 41 03 // i32.const 3 - use default 7 | 0e 02 // br_table 2 8 | 00 00 00 02 // 2 9 | 00 00 00 01 // 1 10 | 00 00 00 00 // default - 0 11 | 0b // end 12 | 13 | 42 05 // i64.const 5 14 | 7c // i64.add 15 | 0b // end 16 | 17 | 42 04 // i64.const 4 18 | 7c // i64.add 19 | 0b // end 20 | 21 | 0b // end 22 | -------------------------------------------------------------------------------- /test/cpu/br_table3_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("br_table3.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("br_table3_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #90 82 | `assert(result, 12); 83 | `assert(result_type, `i64); 84 | `assert(result_empty, 0); 85 | `assert(trap, `ENDED); 86 | end 87 | else begin 88 | #24 89 | `assert(trap, `NO_64B); 90 | end 91 | 92 | $finish; 93 | end 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /test/cpu/br_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 3; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("br.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | reg reset = 0; 47 | wire [63:0] result; 48 | wire result_empty; 49 | wire [ 3:0] trap; 50 | 51 | cpu #( 52 | .MEM_DEPTH(MEM_ADDR) 53 | ) 54 | dut 55 | ( 56 | .clk(clk), 57 | .reset(reset), 58 | .result(result), 59 | .result_empty(result_empty), 60 | .trap(trap), 61 | .mem_addr(mem_addr), 62 | .mem_extra(mem_extra), 63 | .mem_data(mem_data), 64 | .mem_error(mem_error) 65 | ); 66 | 67 | always #1 clk = ~clk; 68 | 69 | initial begin 70 | $dumpfile("br_tb.vcd"); 71 | $dumpvars(0, cpu_tb); 72 | 73 | #24 74 | `assert(result, 42); 75 | `assert(result_empty, 0); 76 | `assert(trap, `ENDED); 77 | 78 | $finish; 79 | end 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /test/cpu/call1.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 02 // 2 functions 3 | 00 00 00 1e 7e 00 00 00 00 00 00 00 00 // function 0 / i64 / 0 / 0 4 | 00 00 00 21 7e 00 00 00 00 00 00 00 00 // function 1 / i64 / 0 / 0 5 | 6 | // function 0 7 | 42 2a // i64.const 42 8 | 0b // end 9 | 10 | // function 1 11 | 10 00 // call 0 12 | 0b // end 13 | -------------------------------------------------------------------------------- /test/cpu/call1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | localparam STACK_DEPTH = 7; 18 | 19 | reg [ MEM_ADDR :0] mem_addr; 20 | reg [ MEM_EXTRA-1:0] mem_extra; 21 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 22 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 23 | wire [2**MEM_EXTRA*8-1:0] mem_data; 24 | wire mem_error; 25 | 26 | genrom #( 27 | .ROMFILE("call1.hex"), 28 | .AW(MEM_ADDR), 29 | .DW(8), 30 | .EXTRA(MEM_EXTRA) 31 | ) 32 | ROM ( 33 | .clk(clk), 34 | .addr(mem_addr), 35 | .extra(mem_extra), 36 | .lower_bound(rom_lower_bound), 37 | .upper_bound(rom_upper_bound), 38 | .data(mem_data), 39 | .error(mem_error) 40 | ); 41 | 42 | 43 | // 44 | // CPU 45 | // 46 | 47 | parameter HAS_FPU = 1; 48 | parameter USE_64B = 1; 49 | 50 | reg reset = 1; 51 | reg [ MEM_ADDR:0] pc = 33; 52 | reg [STACK_DEPTH:0] index = 0; 53 | wire [ 63:0] result; 54 | wire [ 1:0] result_type; 55 | wire result_empty; 56 | wire [ 3:0] trap; 57 | 58 | cpu #( 59 | .HAS_FPU(HAS_FPU), 60 | .USE_64B(USE_64B), 61 | .MEM_DEPTH(MEM_ADDR), 62 | .STACK_DEPTH(STACK_DEPTH) 63 | ) 64 | dut 65 | ( 66 | .clk(clk), 67 | .reset(reset), 68 | .pc(pc), 69 | .index(index), 70 | .result(result), 71 | .result_type(result_type), 72 | .result_empty(result_empty), 73 | .trap(trap), 74 | .mem_addr(mem_addr), 75 | .mem_extra(mem_extra), 76 | .mem_data(mem_data), 77 | .mem_error(mem_error) 78 | ); 79 | 80 | always #1 clk = ~clk; 81 | 82 | initial begin 83 | $dumpfile("call1_tb.vcd"); 84 | $dumpvars(0, cpu_tb); 85 | 86 | #1 87 | reset <= 0; 88 | 89 | if(USE_64B) begin 90 | #29 91 | `assert(result, 42); 92 | `assert(result_type, `i64); 93 | `assert(result_empty, 0); 94 | end 95 | else begin 96 | #17 97 | `assert(trap, `NO_64B); 98 | end 99 | 100 | $finish; 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /test/cpu/call2.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 02 // 2 functions 3 | 00 00 00 1e 7e 00 00 00 00 00 00 00 00 // function 0 / i64 / 0 / 0 4 | 00 00 00 21 7e 00 00 00 00 00 00 00 00 // function 1 / i64 / 0 / 0 5 | 6 | // function 0 7 | 42 02 // i64.const 2 8 | 0b // end 9 | 10 | // function 1 11 | 42 01 // i64.const 1 12 | 10 00 // call 0 13 | 7c // i64.add 14 | 0b // end 15 | -------------------------------------------------------------------------------- /test/cpu/call2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | localparam STACK_DEPTH = 7; 18 | 19 | reg [ MEM_ADDR :0] mem_addr; 20 | reg [ MEM_EXTRA-1:0] mem_extra; 21 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 22 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 23 | wire [2**MEM_EXTRA*8-1:0] mem_data; 24 | wire mem_error; 25 | 26 | genrom #( 27 | .ROMFILE("call2.hex"), 28 | .AW(MEM_ADDR), 29 | .DW(8), 30 | .EXTRA(MEM_EXTRA) 31 | ) 32 | ROM ( 33 | .clk(clk), 34 | .addr(mem_addr), 35 | .extra(mem_extra), 36 | .lower_bound(rom_lower_bound), 37 | .upper_bound(rom_upper_bound), 38 | .data(mem_data), 39 | .error(mem_error) 40 | ); 41 | 42 | 43 | // 44 | // CPU 45 | // 46 | 47 | parameter HAS_FPU = 1; 48 | parameter USE_64B = 1; 49 | 50 | reg reset = 1; 51 | reg [ MEM_ADDR:0] pc = 33; 52 | reg [STACK_DEPTH:0] index = 0; 53 | wire [ 63:0] result; 54 | wire [ 1:0] result_type; 55 | wire result_empty; 56 | wire [ 3:0] trap; 57 | 58 | cpu #( 59 | .HAS_FPU(HAS_FPU), 60 | .USE_64B(USE_64B), 61 | .MEM_DEPTH(MEM_ADDR), 62 | .STACK_DEPTH(STACK_DEPTH) 63 | ) 64 | dut 65 | ( 66 | .clk(clk), 67 | .reset(reset), 68 | .pc(pc), 69 | .index(index), 70 | .result(result), 71 | .result_type(result_type), 72 | .result_empty(result_empty), 73 | .trap(trap), 74 | .mem_addr(mem_addr), 75 | .mem_extra(mem_extra), 76 | .mem_data(mem_data), 77 | .mem_error(mem_error) 78 | ); 79 | 80 | always #1 clk = ~clk; 81 | 82 | initial begin 83 | $dumpfile("call2_tb.vcd"); 84 | $dumpvars(0, cpu_tb); 85 | 86 | #1 87 | reset <= 0; 88 | 89 | if(USE_64B) begin 90 | #45 91 | `assert(result, 3); 92 | `assert(result_type, `i64); 93 | `assert(result_empty, 0); 94 | end 95 | else begin 96 | #17 97 | `assert(trap, `NO_64B); 98 | end 99 | 100 | $finish; 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /test/cpu/cpu_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI 3 | [*] Mon Apr 17 19:44:19 2017 4 | [*] 5 | [dumpfile] "/home/piranna/github/wasmachine/build/cpu/block_tb.vcd" 6 | [dumpfile_mtime] "Mon Apr 17 19:43:10 2017" 7 | [dumpfile_size] 12313 8 | [savefile] "/home/piranna/github/wasmachine/test/cpu/cpu_tb.gtkw" 9 | [timestart] 0 10 | [size] 1366 720 11 | [pos] -1 -1 12 | *-2.901924 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] cpu_tb. 14 | [treeopen] cpu_tb.dut. 15 | [treeopen] cpu_tb.dut.blockStack. 16 | [treeopen] cpu_tb.dut.leb128. 17 | [treeopen] cpu_tb.dut.stack. 18 | [sst_width] 213 19 | [signals_width] 342 20 | [sst_expanded] 1 21 | [sst_vpaned_height] 293 22 | @28 23 | cpu_tb.dut.clk 24 | cpu_tb.dut.reset 25 | @201 26 | - 27 | @28 28 | cpu_tb.dut.step[2:0] 29 | @22 30 | cpu_tb.dut.opcode[7:0] 31 | cpu_tb.trap[3:0] 32 | @200 33 | -result 34 | @22 35 | cpu_tb.result[63:0] 36 | @28 37 | cpu_tb.result_empty 38 | @200 39 | -Stack 40 | @28 41 | cpu_tb.dut.stack_op[2:0] 42 | @22 43 | cpu_tb.dut.stack_data[65:0] 44 | cpu_tb.dut.stack_index[7:0] 45 | cpu_tb.dut.stack_offset[7:0] 46 | cpu_tb.dut.stack_underflow[7:0] 47 | cpu_tb.dut.stack_upper[7:0] 48 | cpu_tb.dut.stack_lower[7:0] 49 | cpu_tb.dut.stack_out[65:0] 50 | cpu_tb.dut.stack_out1[65:0] 51 | cpu_tb.dut.stack_out2[65:0] 52 | @28 53 | cpu_tb.dut.stack_status[2:0] 54 | @200 55 | -Block stack 56 | @28 57 | cpu_tb.dut.blockStack_op[2:0] 58 | cpu_tb.dut.blockStack_out_type[1:0] 59 | @22 60 | cpu_tb.dut.blockStack_out_index[7:0] 61 | cpu_tb.dut.blockStack_index[3:0] 62 | cpu_tb.dut.blockStack_underflow[3:0] 63 | @28 64 | cpu_tb.dut.blockStack_status[2:0] 65 | @200 66 | -Call stack 67 | @22 68 | cpu_tb.dut.callStack_out_blockIndex[3:0] 69 | cpu_tb.dut.callStack_out_blockUnderflow[3:0] 70 | cpu_tb.dut.callStack_out_upper[7:0] 71 | cpu_tb.dut.callStack_out_lower[7:0] 72 | @28 73 | cpu_tb.dut.callStack_status[1:0] 74 | cpu_tb.dut.callStack.index[1:0] 75 | @200 76 | -LEB128 77 | @22 78 | cpu_tb.dut.leb128_out[63:0] 79 | cpu_tb.dut.leb128_len[3:0] 80 | @200 81 | -Double to Float 82 | @22 83 | cpu_tb.dut.d2f.a[63:0] 84 | @28 85 | cpu_tb.dut.double_to_float_a_ack 86 | cpu_tb.dut.double_to_float_a_stb 87 | @22 88 | cpu_tb.dut.double_to_float_z[31:0] 89 | @28 90 | cpu_tb.dut.double_to_float_z_stb 91 | cpu_tb.dut.double_to_float_z_ack 92 | [pattern_trace] 1 93 | [pattern_trace] 0 94 | -------------------------------------------------------------------------------- /test/cpu/drop.hex: -------------------------------------------------------------------------------- 1 | 42 2a // i64.const 42 - The answer to Life, Universe and Everything else 2 | 1a // drop 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/drop_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 3; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("drop.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("drop_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #18 72 | `assert(result_empty, 1); 73 | 74 | $finish; 75 | end 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /test/cpu/else1.hex: -------------------------------------------------------------------------------- 1 | 41 00 // i32.const 0 - false 2 | 04 7f 00 00 00 12 00 00 00 0f // if i32 3 | 41 02 // i32.const 2 4 | 05 // else 5 | 41 03 // i32.const 3 6 | 0b // end 7 | 8 | 0b // end 9 | -------------------------------------------------------------------------------- /test/cpu/else1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 5; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("else1.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("else1_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #30 81 | `assert(result, 3); 82 | `assert(result_type, `i32); 83 | `assert(result_empty, 0); 84 | `assert(trap, `ENDED); 85 | 86 | $finish; 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /test/cpu/else2.hex: -------------------------------------------------------------------------------- 1 | 41 01 // i32.const 1 - true 2 | 04 7f 00 00 00 12 00 00 00 0f // if i32 3 | 41 02 // i32.const 2 4 | 05 // else 5 | 41 03 // i32.const 3 6 | 0b // end 7 | 8 | 0b // end 9 | -------------------------------------------------------------------------------- /test/cpu/else2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 5; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("else2.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("else2_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #30 81 | `assert(result, 2); 82 | `assert(result_type, `i32); 83 | `assert(result_empty, 0); 84 | `assert(trap, `ENDED); 85 | 86 | $finish; 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /test/cpu/f32.const.hex: -------------------------------------------------------------------------------- 1 | 43 c0 00 00 00 // f32.const -2 2 | 0b // end 3 | -------------------------------------------------------------------------------- /test/cpu/f32.const_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("f32.const.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("f32.const_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #12 72 | `assert(result, 32'hc0000000); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/f32.demote-f64.hex: -------------------------------------------------------------------------------- 1 | 44 c0 00 00 00 00 00 00 00 // f64.const -1073741824 2 | b6 // f32.demote/f64 -2 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/f32.demote-f64_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("f32.demote-f64.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | wire [63:0] result; 50 | wire [ 1:0] result_type; 51 | wire result_empty; 52 | wire [ 3:0] trap; 53 | 54 | cpu #( 55 | .HAS_FPU(HAS_FPU), 56 | .USE_64B(USE_64B), 57 | .MEM_DEPTH(MEM_ADDR) 58 | ) 59 | dut 60 | ( 61 | .clk(clk), 62 | .result(result), 63 | .result_type(result_type), 64 | .result_empty(result_empty), 65 | .trap(trap), 66 | .mem_addr(mem_addr), 67 | .mem_extra(mem_extra), 68 | .mem_data(mem_data), 69 | .mem_error(mem_error) 70 | ); 71 | 72 | always #1 clk = ~clk; 73 | 74 | initial begin 75 | $dumpfile("f32.demote-f64_tb.vcd"); 76 | $dumpvars(0, cpu_tb); 77 | 78 | if(HAS_FPU && USE_64B) begin 79 | #26 80 | `assert(result, 32'hc0000000); 81 | `assert(result_type, `f32); 82 | `assert(result_empty, 0); 83 | end 84 | else if(HAS_FPU) begin 85 | #12 86 | `assert(trap, `NO_64B); 87 | end 88 | else begin 89 | #12 90 | `assert(trap, `NO_FPU); 91 | end 92 | 93 | $finish; 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /test/cpu/f32.reinterpret-i32.hex: -------------------------------------------------------------------------------- 1 | 41 80 80 80 80 0c // i32.const -1073741824 2 | be // f32.reinterpret/i32 -2 3 | 0b // end 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | -------------------------------------------------------------------------------- /test/cpu/f32.reinterpret-i32_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("f32.reinterpret-i32.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("f32.reinterpret-i32_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #30 81 | `assert(result, 32'hc0000000); 82 | `assert(result_type, `f32); 83 | `assert(result_empty, 0); 84 | 85 | $finish; 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /test/cpu/f64.const.hex: -------------------------------------------------------------------------------- 1 | 44 c0 00 00 00 00 00 00 00 // f64.const -2 2 | 0b // end 3 | -------------------------------------------------------------------------------- /test/cpu/f64.const_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("f64.const.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("f64.const_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #12 72 | `assert(result, 64'hc000000000000000); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/f64.reinterpret-i64.hex: -------------------------------------------------------------------------------- 1 | 42 80 80 80 80 80 80 80 80 c0 01 // i64.const -1073741824 2 | bf // f64.reinterpret/i64 -2 3 | 0b // end 4 | 00 5 | 00 6 | 00 7 | -------------------------------------------------------------------------------- /test/cpu/f64.reinterpret-i64_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("f64.reinterpret-i64.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("f64.reinterpret-i64_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #18 82 | `assert(result, 64'hc000000000000000); 83 | `assert(result_type, `f64); 84 | `assert(result_empty, 0); 85 | end 86 | else begin 87 | #12 88 | `assert(trap, `NO_64B); 89 | end 90 | 91 | $finish; 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /test/cpu/get_local1.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 02 // 2 functions 3 | 00 00 00 1e 7e 00 00 00 01 00 00 00 01 // function 0 / i64 / 1 / 1 4 | 00 00 00 21 7e 00 00 00 00 00 00 00 00 // function 1 / i64 / 0 / 0 5 | 6 | // function 0 7 | 20 00 // get_local 0 8 | 0b // end 9 | 10 | // function 1 11 | 42 01 // i64.const 1 12 | 10 00 // call 0 13 | 42 01 // i64.const 1 14 | 7c // i64.add 15 | 0b // end 16 | -------------------------------------------------------------------------------- /test/cpu/get_local1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | localparam STACK_DEPTH = 7; 18 | 19 | reg [ MEM_ADDR :0] mem_addr; 20 | reg [ MEM_EXTRA-1:0] mem_extra; 21 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 22 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 23 | wire [2**MEM_EXTRA*8-1:0] mem_data; 24 | wire mem_error; 25 | 26 | genrom #( 27 | .ROMFILE("get_local1.hex"), 28 | .AW(MEM_ADDR), 29 | .DW(8), 30 | .EXTRA(MEM_EXTRA) 31 | ) 32 | ROM ( 33 | .clk(clk), 34 | .addr(mem_addr), 35 | .extra(mem_extra), 36 | .lower_bound(rom_lower_bound), 37 | .upper_bound(rom_upper_bound), 38 | .data(mem_data), 39 | .error(mem_error) 40 | ); 41 | 42 | 43 | // 44 | // CPU 45 | // 46 | 47 | parameter HAS_FPU = 1; 48 | parameter USE_64B = 1; 49 | 50 | reg reset = 1; 51 | reg [ MEM_ADDR:0] pc = 33; 52 | reg [STACK_DEPTH:0] index = 0; 53 | wire [ 63:0] result; 54 | wire [ 1:0] result_type; 55 | wire result_empty; 56 | wire [ 3:0] trap; 57 | 58 | cpu #( 59 | .HAS_FPU(HAS_FPU), 60 | .USE_64B(USE_64B), 61 | .MEM_DEPTH(MEM_ADDR), 62 | .STACK_DEPTH(STACK_DEPTH) 63 | ) 64 | dut 65 | ( 66 | .clk(clk), 67 | .reset(reset), 68 | .pc(pc), 69 | .index(index), 70 | .result(result), 71 | .result_type(result_type), 72 | .result_empty(result_empty), 73 | .trap(trap), 74 | .mem_addr(mem_addr), 75 | .mem_extra(mem_extra), 76 | .mem_data(mem_data), 77 | .mem_error(mem_error) 78 | ); 79 | 80 | always #1 clk = ~clk; 81 | 82 | initial begin 83 | $dumpfile("get_local1_tb.vcd"); 84 | $dumpvars(0, cpu_tb); 85 | 86 | #1 87 | reset <= 0; 88 | 89 | if(USE_64B) begin 90 | #55 91 | `assert(result, 2); 92 | `assert(result_type, `i64); 93 | `assert(result_empty, 0); 94 | end 95 | else begin 96 | #12 97 | `assert(trap, `NO_64B); 98 | end 99 | 100 | $finish; 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /test/cpu/get_local2.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 03 // 3 functions 3 | 00 00 00 2b 7e 00 00 00 01 00 00 00 01 // function 0 / i64 / 1 / 1 4 | 00 00 00 2e 7e 00 00 00 01 00 00 00 01 // function 1 / i64 / 1 / 1 5 | 00 00 00 3c 7e 00 00 00 00 00 00 00 00 // function 2 / i64 / 0 / 0 6 | 7 | // function 0 8 | 20 00 // get_local 0 9 | 0b // end 10 | 11 | // function 0 12 | 20 00 // get_local 0 13 | 42 02 // i64.const 2 14 | 10 00 // call 0 15 | 7c // i64.add 16 | 0b // end 17 | 18 | // function 2 19 | 42 01 // i64.const 1 20 | 10 01 // call 1 21 | 42 01 // i64.const 1 22 | 7c // i64.add 23 | 0b // end 24 | -------------------------------------------------------------------------------- /test/cpu/get_local2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | localparam STACK_DEPTH = 7; 18 | 19 | reg [ MEM_ADDR :0] mem_addr; 20 | reg [ MEM_EXTRA-1:0] mem_extra; 21 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 22 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 23 | wire [2**MEM_EXTRA*8-1:0] mem_data; 24 | wire mem_error; 25 | 26 | genrom #( 27 | .ROMFILE("get_local2.hex"), 28 | .AW(MEM_ADDR), 29 | .DW(8), 30 | .EXTRA(MEM_EXTRA) 31 | ) 32 | ROM ( 33 | .clk(clk), 34 | .addr(mem_addr), 35 | .extra(mem_extra), 36 | .lower_bound(rom_lower_bound), 37 | .upper_bound(rom_upper_bound), 38 | .data(mem_data), 39 | .error(mem_error) 40 | ); 41 | 42 | 43 | // 44 | // CPU 45 | // 46 | 47 | parameter HAS_FPU = 1; 48 | parameter USE_64B = 1; 49 | 50 | reg reset = 1; 51 | reg [ MEM_ADDR:0] pc = 54; 52 | reg [STACK_DEPTH:0] index = 0; 53 | wire [ 63:0] result; 54 | wire [ 1:0] result_type; 55 | wire result_empty; 56 | wire [ 3:0] trap; 57 | 58 | cpu #( 59 | .HAS_FPU(HAS_FPU), 60 | .USE_64B(USE_64B), 61 | .MEM_DEPTH(MEM_ADDR), 62 | .STACK_DEPTH(STACK_DEPTH) 63 | ) 64 | dut 65 | ( 66 | .clk(clk), 67 | .reset(reset), 68 | .pc(pc), 69 | .index(index), 70 | .result(result), 71 | .result_type(result_type), 72 | .result_empty(result_empty), 73 | .trap(trap), 74 | .mem_addr(mem_addr), 75 | .mem_extra(mem_extra), 76 | .mem_data(mem_data), 77 | .mem_error(mem_error) 78 | ); 79 | 80 | always #1 clk = ~clk; 81 | 82 | initial begin 83 | $dumpfile("get_local2_tb.vcd"); 84 | $dumpvars(0, cpu_tb); 85 | 86 | #1 87 | reset <= 0; 88 | 89 | if(USE_64B) begin 90 | #97 91 | `assert(result, 4); 92 | `assert(result_type, `i64); 93 | `assert(result_empty, 0); 94 | end 95 | else begin 96 | #12 97 | `assert(trap, `NO_64B); 98 | end 99 | 100 | $finish; 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /test/cpu/i32.add.hex: -------------------------------------------------------------------------------- 1 | 41 01 // i64.const 1 2 | 41 02 // i64.const 2 3 | 6a // i64.add 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i32.add_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i32.add.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i32.add_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #24 81 | `assert(result, 3); 82 | `assert(result_type, `i32); 83 | `assert(result_empty, 0); 84 | 85 | $finish; 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /test/cpu/i32.const.hex: -------------------------------------------------------------------------------- 1 | 41 2a // i32.const 42 - The answer to Life, Universe and Everything else 2 | 0b // end 3 | -------------------------------------------------------------------------------- /test/cpu/i32.const_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.const.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.const_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #12 72 | `assert(result, 42); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.eq1.hex: -------------------------------------------------------------------------------- 1 | 41 2a // i32.const 42 2 | 41 2a // i32.const 42 3 | 46 // i32.eq - true 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i32.eq1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.eq1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.eq1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.eq2.hex: -------------------------------------------------------------------------------- 1 | 41 01 // i32.const 1 2 | 41 02 // i32.const 2 3 | 46 // i32.eq - false 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i32.eq2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 3; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.eq2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.eq2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 0); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.eqz1.hex: -------------------------------------------------------------------------------- 1 | 41 00 // i32.const 00 - true 2 | 45 // i32.eqz 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/i32.eqz1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.eqz1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.eqz1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #18 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.eqz2.hex: -------------------------------------------------------------------------------- 1 | 41 01 // i32.const 01 - false 2 | 45 // i32.eqz 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/i32.eqz2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.eqz2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.eqz2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #18 72 | `assert(result, 0); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.ne1.hex: -------------------------------------------------------------------------------- 1 | 41 00 // i32.const 0 2 | 41 00 // i32.const 0 3 | 47 // i32.ne - false 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i32.ne1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.ne1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.ne1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 0); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.ne2.hex: -------------------------------------------------------------------------------- 1 | 41 00 // i32.const 0 2 | 41 01 // i32.const 1 3 | 47 // i32.ne - true 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i32.ne2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i32.ne2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i32.ne2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i32.reinterpret-f32.hex: -------------------------------------------------------------------------------- 1 | 43 c0 00 00 00 // f32.const -2 2 | bc // i32.reinterpret/f32 -1073741824 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/i32.reinterpret-f32_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i32.reinterpret-f32.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i32.reinterpret-f32_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(HAS_FPU) begin 81 | #18 82 | `assert(result, 32'hc0000000); 83 | `assert(result_type, `i32); 84 | `assert(result_empty, 0); 85 | end 86 | else begin 87 | #12 88 | `assert(trap, `NO_FPU); 89 | end 90 | 91 | $finish; 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /test/cpu/i32.sub.hex: -------------------------------------------------------------------------------- 1 | 41 03 // i32.const 3 2 | 41 02 // i32.const 2 3 | 6b // i32.sub 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i32.sub_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i32.sub.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i32.sub_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #24 81 | `assert(result, 1); 82 | `assert(result_type, `i32); 83 | `assert(result_empty, 0); 84 | 85 | $finish; 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /test/cpu/i32.wrap-i64.hex: -------------------------------------------------------------------------------- 1 | 42 2a // i64.const 42 - The answer to Life, Universe and Everything else 2 | a7 // i32.wrap/i64 3 | 0b // end 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | -------------------------------------------------------------------------------- /test/cpu/i32.wrap-i64_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i32.wrap-i64.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i32.wrap-i64_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #22 82 | `assert(result, 42); 83 | `assert(result_type, `i32); 84 | `assert(result_empty, 0); 85 | `assert(trap, `ENDED); 86 | end 87 | else begin 88 | #12 89 | `assert(trap, `NO_64B); 90 | end 91 | 92 | $finish; 93 | end 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /test/cpu/i64.add.hex: -------------------------------------------------------------------------------- 1 | 42 01 // i64.const 1 2 | 42 02 // i64.const 2 3 | 7c // i64.add 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i64.add_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i64.add.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i64.add_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #24 82 | `assert(result, 3); 83 | `assert(result_type, `i64); 84 | `assert(result_empty, 0); 85 | end 86 | else begin 87 | #12 88 | `assert(trap, `NO_64B); 89 | end 90 | 91 | $finish; 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /test/cpu/i64.const.hex: -------------------------------------------------------------------------------- 1 | 42 2a // i64.const 42 - The answer to Life, Universe and Everything else 2 | 0b // end 3 | -------------------------------------------------------------------------------- /test/cpu/i64.const_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.const.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.const_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #12 72 | `assert(result, 42); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.eq1.hex: -------------------------------------------------------------------------------- 1 | 42 00 // i64.const 0 2 | 42 00 // i64.const 0 3 | 51 // i64.eq - true 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i64.eq1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.eq1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.eq1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.eq2.hex: -------------------------------------------------------------------------------- 1 | 42 00 // i64.const 0 2 | 42 01 // i64.const 1 3 | 51 // i64.eq - false 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i64.eq2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.eq2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.eq2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 0); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.eqz1.hex: -------------------------------------------------------------------------------- 1 | 42 00 // i64.const 00 - true 2 | 50 // i64.eqz 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/i64.eqz1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 3; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.eqz1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.eqz1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #18 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.eqz2.hex: -------------------------------------------------------------------------------- 1 | 42 01 // i64.const 01 - false 2 | 50 // i64.eqz 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/i64.eqz2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.eqz2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.eqz2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #18 72 | `assert(result, 0); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.ne1.hex: -------------------------------------------------------------------------------- 1 | 42 00 // i64.const 0 2 | 42 00 // i64.const 0 3 | 52 // i64.ne - false 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i64.ne1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.ne1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.ne1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 0); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.ne2.hex: -------------------------------------------------------------------------------- 1 | 42 00 // i64.const 0 2 | 42 01 // i64.const 1 3 | 52 // i64.ne - true 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i64.ne2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("i64.ne2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("i64.ne2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #24 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/i64.reinterpret-f64.hex: -------------------------------------------------------------------------------- 1 | 44 c0 00 00 00 00 00 00 00 // f64.const -2 2 | bd // i64.reinterpret/f64 -1073741824 3 | 0b // end 4 | 00 5 | 00 6 | 00 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | -------------------------------------------------------------------------------- /test/cpu/i64.reinterpret-f64_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i64.reinterpret-f64.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i64.reinterpret-f64_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(HAS_FPU && USE_64B) begin 81 | #30 82 | `assert(result, 64'hc000000000000000); 83 | `assert(result_type, `i64); 84 | `assert(result_empty, 0); 85 | end 86 | else if(HAS_FPU) begin 87 | #12 88 | `assert(trap, `NO_64B); 89 | end 90 | else begin 91 | #12 92 | `assert(trap, `NO_FPU); 93 | end 94 | 95 | $finish; 96 | end 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /test/cpu/i64.sub.hex: -------------------------------------------------------------------------------- 1 | 42 03 // i64.const 3 2 | 42 02 // i64.const 2 3 | 7d // i64.sub 4 | 0b // end 5 | -------------------------------------------------------------------------------- /test/cpu/i64.sub_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("i64.sub.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("i64.sub_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | if(USE_64B) begin 81 | #24 82 | `assert(result, 1); 83 | `assert(result_type, `i64); 84 | `assert(result_empty, 0); 85 | end 86 | else begin 87 | #12 88 | `assert(trap, `NO_64B); 89 | end 90 | 91 | $finish; 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /test/cpu/if1.hex: -------------------------------------------------------------------------------- 1 | 41 00 // i32.const 0 - false 2 | 04 7f 00 00 00 10 00 00 00 00 // if i32 3 | 41 02 // i32.const 2 4 | 0f // return 5 | 0b // end 6 | 7 | 41 03 // i32.const 3 8 | 0b // end 9 | -------------------------------------------------------------------------------- /test/cpu/if1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 5; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("if1.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("if1_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #24 81 | `assert(result, 3); 82 | `assert(result_type, `i32); 83 | `assert(result_empty, 0); 84 | 85 | $finish; 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /test/cpu/if2.hex: -------------------------------------------------------------------------------- 1 | 41 01 // i32.const 1 - true 2 | 04 7f 00 00 00 10 00 00 00 00 // if i32 3 | 41 02 // i32.const 2 4 | 0f // return 5 | 0b // end 6 | 7 | 41 03 // i32.const 3 8 | 0b // end 9 | -------------------------------------------------------------------------------- /test/cpu/if2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 5; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("if2.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | reg reset = 0; 50 | wire [63:0] result; 51 | wire [ 1:0] result_type; 52 | wire result_empty; 53 | wire [ 3:0] trap; 54 | 55 | cpu #( 56 | .HAS_FPU(HAS_FPU), 57 | .USE_64B(USE_64B), 58 | .MEM_DEPTH(MEM_ADDR) 59 | ) 60 | dut 61 | ( 62 | .clk(clk), 63 | .reset(reset), 64 | .result(result), 65 | .result_type(result_type), 66 | .result_empty(result_empty), 67 | .trap(trap), 68 | .mem_addr(mem_addr), 69 | .mem_extra(mem_extra), 70 | .mem_data(mem_data), 71 | .mem_error(mem_error) 72 | ); 73 | 74 | always #1 clk = ~clk; 75 | 76 | initial begin 77 | $dumpfile("if2_tb.vcd"); 78 | $dumpvars(0, cpu_tb); 79 | 80 | #24 81 | `assert(result, 2); 82 | `assert(result_type, `i32); 83 | `assert(result_empty, 0); 84 | 85 | $finish; 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /test/cpu/loop.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 01 // 1 function 3 | 00 00 00 11 7f 00 00 00 00 00 00 00 01 // function 0 / i32 / 0 / 1 4 | 5 | // function 0 6 | 02 40 00 00 00 29 // block 7 | 03 40 // loop 8 | 20 00 // get_local 0 9 | 41 03 // i32.const 3 10 | 46 // i32.eq 11 | 0d 01 // br_if 1 12 | 13 | 20 00 // get_local 0 14 | 41 01 // i32.const 1 15 | 6a // i32.add 16 | 21 00 // set_local 0 17 | 0b // end 18 | 0b // end 19 | 20 00 // get_local 0 20 | 21 | 0b // end 22 | -------------------------------------------------------------------------------- /test/cpu/loop_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 6; 14 | localparam MEM_EXTRA = 4; 15 | localparam STACK_DEPTH = 7; 16 | 17 | reg [ MEM_ADDR :0] mem_addr; 18 | reg [ MEM_EXTRA-1:0] mem_extra; 19 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 20 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 21 | wire [2**MEM_EXTRA*8-1:0] mem_data; 22 | wire mem_error; 23 | 24 | genrom #( 25 | .ROMFILE("loop.hex"), 26 | .AW(MEM_ADDR), 27 | .DW(8), 28 | .EXTRA(MEM_EXTRA) 29 | ) 30 | ROM ( 31 | .clk(clk), 32 | .addr(mem_addr), 33 | .extra(mem_extra), 34 | .lower_bound(rom_lower_bound), 35 | .upper_bound(rom_upper_bound), 36 | .data(mem_data), 37 | .error(mem_error) 38 | ); 39 | 40 | 41 | // 42 | // CPU 43 | // 44 | 45 | reg reset = 1; 46 | reg [ MEM_ADDR:0] pc = 17; 47 | reg [STACK_DEPTH:0] index = 1; 48 | wire [ 63:0] result; 49 | wire [ 1:0] result_type; 50 | wire result_empty; 51 | wire [ 3:0] trap; 52 | 53 | cpu #( 54 | .MEM_DEPTH(MEM_ADDR), 55 | .STACK_DEPTH(STACK_DEPTH) 56 | ) 57 | dut 58 | ( 59 | .clk(clk), 60 | .reset(reset), 61 | .pc(pc), 62 | .index(index), 63 | .result(result), 64 | .result_type(result_type), 65 | .result_empty(result_empty), 66 | .trap(trap), 67 | .mem_addr(mem_addr), 68 | .mem_extra(mem_extra), 69 | .mem_data(mem_data), 70 | .mem_error(mem_error) 71 | ); 72 | 73 | always #1 clk = ~clk; 74 | 75 | initial begin 76 | $dumpfile("loop_tb.vcd"); 77 | $dumpvars(0, cpu_tb); 78 | 79 | #1 80 | reset <= 0; 81 | 82 | #247 83 | `assert(result, 3); 84 | `assert(result_empty, 0); 85 | 86 | $finish; 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /test/cpu/return.hex: -------------------------------------------------------------------------------- 1 | 42 2a // i64.const 42 2 | 0f // return 3 | 0b // end 4 | -------------------------------------------------------------------------------- /test/cpu/return_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("return.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | parameter HAS_FPU = 1; 47 | parameter USE_64B = 1; 48 | 49 | wire [63:0] result; 50 | wire [ 1:0] result_type; 51 | wire result_empty; 52 | wire [ 3:0] trap; 53 | 54 | cpu #( 55 | .HAS_FPU(HAS_FPU), 56 | .USE_64B(USE_64B), 57 | .MEM_DEPTH(MEM_ADDR) 58 | ) 59 | dut 60 | ( 61 | .clk(clk), 62 | .reset(reset), 63 | .result(result), 64 | .result_type(result_type), 65 | .result_empty(result_empty), 66 | .trap(trap), 67 | .mem_addr(mem_addr), 68 | .mem_extra(mem_extra), 69 | .mem_data(mem_data), 70 | .mem_error(mem_error) 71 | ); 72 | 73 | always #1 clk = ~clk; 74 | 75 | initial begin 76 | $dumpfile("return_tb.vcd"); 77 | $dumpvars(0, cpu_tb); 78 | 79 | if(USE_64B) begin 80 | #12 81 | `assert(result, 42); 82 | `assert(result_type, `i64); 83 | `assert(result_empty, 0); 84 | end 85 | else begin 86 | #12 87 | `assert(trap, `NO_64B); 88 | end 89 | 90 | $finish; 91 | end 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /test/cpu/select1.hex: -------------------------------------------------------------------------------- 1 | 42 02 // i64.const 2 2 | 42 01 // i64.const 1 3 | 41 01 // i32.const 1 - true 4 | 1b // select 5 | 0b // end 6 | -------------------------------------------------------------------------------- /test/cpu/select1_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("select1.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("select1_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #30 72 | `assert(result, 1); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/select2.hex: -------------------------------------------------------------------------------- 1 | 42 02 // i64.const 2 2 | 42 01 // i64.const 1 3 | 41 00 // i32.const 0 - false 4 | 1b // select 5 | 0b // end 6 | -------------------------------------------------------------------------------- /test/cpu/select2_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module cpu_tb(); 5 | 6 | reg clk = 0; 7 | 8 | 9 | // 10 | // ROM 11 | // 12 | 13 | localparam MEM_ADDR = 4; 14 | localparam MEM_EXTRA = 4; 15 | 16 | reg [ MEM_ADDR :0] mem_addr; 17 | reg [ MEM_EXTRA-1:0] mem_extra; 18 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 19 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 20 | wire [2**MEM_EXTRA*8-1:0] mem_data; 21 | wire mem_error; 22 | 23 | genrom #( 24 | .ROMFILE("select2.hex"), 25 | .AW(MEM_ADDR), 26 | .DW(8), 27 | .EXTRA(MEM_EXTRA) 28 | ) 29 | ROM ( 30 | .clk(clk), 31 | .addr(mem_addr), 32 | .extra(mem_extra), 33 | .lower_bound(rom_lower_bound), 34 | .upper_bound(rom_upper_bound), 35 | .data(mem_data), 36 | .error(mem_error) 37 | ); 38 | 39 | 40 | // 41 | // CPU 42 | // 43 | 44 | reg reset = 0; 45 | wire [63:0] result; 46 | wire result_empty; 47 | wire [ 3:0] trap; 48 | 49 | cpu #( 50 | .MEM_DEPTH(MEM_ADDR) 51 | ) 52 | dut 53 | ( 54 | .clk(clk), 55 | .reset(reset), 56 | .result(result), 57 | .result_empty(result_empty), 58 | .trap(trap), 59 | .mem_addr(mem_addr), 60 | .mem_extra(mem_extra), 61 | .mem_data(mem_data), 62 | .mem_error(mem_error) 63 | ); 64 | 65 | always #1 clk = ~clk; 66 | 67 | initial begin 68 | $dumpfile("select2_tb.vcd"); 69 | $dumpvars(0, cpu_tb); 70 | 71 | #30 72 | `assert(result, 2); 73 | `assert(result_empty, 0); 74 | 75 | $finish; 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /test/cpu/select3.hex: -------------------------------------------------------------------------------- 1 | 42 02 // i64.const 2 2 | 41 01 // i32.const 1 - type of both operators must match 3 | 41 00 // i32.const 0 - false 4 | 1b // select 5 | 0b // end 6 | -------------------------------------------------------------------------------- /test/cpu/select3_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 4; 16 | localparam MEM_EXTRA = 4; 17 | 18 | reg [ MEM_ADDR :0] mem_addr; 19 | reg [ MEM_EXTRA-1:0] mem_extra; 20 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 21 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 22 | wire [2**MEM_EXTRA*8-1:0] mem_data; 23 | wire mem_error; 24 | 25 | genrom #( 26 | .ROMFILE("select3.hex"), 27 | .AW(MEM_ADDR), 28 | .DW(8), 29 | .EXTRA(MEM_EXTRA) 30 | ) 31 | ROM ( 32 | .clk(clk), 33 | .addr(mem_addr), 34 | .extra(mem_extra), 35 | .lower_bound(rom_lower_bound), 36 | .upper_bound(rom_upper_bound), 37 | .data(mem_data), 38 | .error(mem_error) 39 | ); 40 | 41 | 42 | // 43 | // CPU 44 | // 45 | 46 | reg reset = 0; 47 | wire [63:0] result; 48 | wire result_empty; 49 | wire [ 3:0] trap; 50 | 51 | cpu #( 52 | .MEM_DEPTH(MEM_ADDR) 53 | ) 54 | dut 55 | ( 56 | .clk(clk), 57 | .reset(reset), 58 | .result(result), 59 | .result_empty(result_empty), 60 | .trap(trap), 61 | .mem_addr(mem_addr), 62 | .mem_extra(mem_extra), 63 | .mem_data(mem_data), 64 | .mem_error(mem_error) 65 | ); 66 | 67 | always #1 clk = ~clk; 68 | 69 | initial begin 70 | $dumpfile("select3_tb.vcd"); 71 | $dumpvars(0, cpu_tb); 72 | 73 | #24 74 | `assert(trap, `TYPES_MISMATCH); 75 | 76 | $finish; 77 | end 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /test/cpu/set_local.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 01 // 1 function 3 | 00 00 00 11 7e 00 00 00 00 00 00 00 01 // function 0 / i64 / 0 / 1 4 | 5 | // function 0 6 | 42 01 // i64.const 1 7 | 21 00 // set_local 0 8 | 42 02 // i64.const 2 9 | 20 00 // get_local 0 10 | 7c // i64.add 11 | 0b // end 12 | -------------------------------------------------------------------------------- /test/cpu/set_local_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | localparam STACK_DEPTH = 7; 18 | 19 | reg [ MEM_ADDR :0] mem_addr; 20 | reg [ MEM_EXTRA-1:0] mem_extra; 21 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 22 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 23 | wire [2**MEM_EXTRA*8-1:0] mem_data; 24 | wire mem_error; 25 | 26 | genrom #( 27 | .ROMFILE("set_local.hex"), 28 | .AW(MEM_ADDR), 29 | .DW(8), 30 | .EXTRA(MEM_EXTRA) 31 | ) 32 | ROM ( 33 | .clk(clk), 34 | .addr(mem_addr), 35 | .extra(mem_extra), 36 | .lower_bound(rom_lower_bound), 37 | .upper_bound(rom_upper_bound), 38 | .data(mem_data), 39 | .error(mem_error) 40 | ); 41 | 42 | 43 | // 44 | // CPU 45 | // 46 | 47 | parameter HAS_FPU = 1; 48 | parameter USE_64B = 1; 49 | 50 | reg reset = 1; 51 | reg [ MEM_ADDR:0] pc = 17; 52 | reg [STACK_DEPTH:0] index = 1; 53 | wire [ 63:0] result; 54 | wire [ 1:0] result_type; 55 | wire result_empty; 56 | wire [ 3:0] trap; 57 | 58 | cpu #( 59 | .HAS_FPU(HAS_FPU), 60 | .USE_64B(USE_64B), 61 | .MEM_DEPTH(MEM_ADDR), 62 | .STACK_DEPTH(STACK_DEPTH) 63 | ) 64 | dut 65 | ( 66 | .clk(clk), 67 | .reset(reset), 68 | .pc(pc), 69 | .index(index), 70 | .result(result), 71 | .result_type(result_type), 72 | .result_empty(result_empty), 73 | .trap(trap), 74 | .mem_addr(mem_addr), 75 | .mem_extra(mem_extra), 76 | .mem_data(mem_data), 77 | .mem_error(mem_error) 78 | ); 79 | 80 | always #1 clk = ~clk; 81 | 82 | initial begin 83 | $dumpfile("set_local_tb.vcd"); 84 | $dumpvars(0, cpu_tb); 85 | 86 | #1 87 | reset <= 0; 88 | 89 | if(USE_64B) begin 90 | #45 91 | `assert(result, 3); 92 | `assert(result_type, `i64); 93 | `assert(result_empty, 0); 94 | end 95 | else begin 96 | #12 97 | `assert(trap, `NO_64B); 98 | end 99 | 100 | $finish; 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /test/cpu/tee_local.hex: -------------------------------------------------------------------------------- 1 | // Functions index 2 | 00 00 00 01 // 1 function 3 | 00 00 00 11 7e 00 00 00 00 00 00 00 01 // function 0 / i64 / 0 / 1 4 | 5 | // function 0 6 | 42 01 // i64.const 1 7 | 22 00 // tee_local 0 8 | 20 00 // get_local 0 9 | 7c // i64.add 10 | 0b // end 11 | -------------------------------------------------------------------------------- /test/cpu/tee_local_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "cpu.vh" 4 | 5 | 6 | module cpu_tb(); 7 | 8 | reg clk = 0; 9 | 10 | 11 | // 12 | // ROM 13 | // 14 | 15 | localparam MEM_ADDR = 6; 16 | localparam MEM_EXTRA = 4; 17 | localparam STACK_DEPTH = 7; 18 | 19 | reg [ MEM_ADDR :0] mem_addr; 20 | reg [ MEM_EXTRA-1:0] mem_extra; 21 | reg [ MEM_ADDR :0] rom_lower_bound = 0; 22 | reg [ MEM_ADDR :0] rom_upper_bound = ~0; 23 | wire [2**MEM_EXTRA*8-1:0] mem_data; 24 | wire mem_error; 25 | 26 | genrom #( 27 | .ROMFILE("tee_local.hex"), 28 | .AW(MEM_ADDR), 29 | .DW(8), 30 | .EXTRA(MEM_EXTRA) 31 | ) 32 | ROM ( 33 | .clk(clk), 34 | .addr(mem_addr), 35 | .extra(mem_extra), 36 | .lower_bound(rom_lower_bound), 37 | .upper_bound(rom_upper_bound), 38 | .data(mem_data), 39 | .error(mem_error) 40 | ); 41 | 42 | 43 | // 44 | // CPU 45 | // 46 | 47 | parameter HAS_FPU = 1; 48 | parameter USE_64B = 1; 49 | 50 | reg reset = 1; 51 | reg [ MEM_ADDR:0] pc = 17; 52 | reg [STACK_DEPTH:0] index = 1; 53 | wire [ 63:0] result; 54 | wire [ 1:0] result_type; 55 | wire result_empty; 56 | wire [ 3:0] trap; 57 | 58 | cpu #( 59 | .HAS_FPU(HAS_FPU), 60 | .USE_64B(USE_64B), 61 | .MEM_DEPTH(MEM_ADDR), 62 | .STACK_DEPTH(STACK_DEPTH) 63 | ) 64 | dut 65 | ( 66 | .clk(clk), 67 | .reset(reset), 68 | .pc(pc), 69 | .index(index), 70 | .result(result), 71 | .result_type(result_type), 72 | .result_empty(result_empty), 73 | .trap(trap), 74 | .mem_addr(mem_addr), 75 | .mem_extra(mem_extra), 76 | .mem_data(mem_data), 77 | .mem_error(mem_error) 78 | ); 79 | 80 | always #1 clk = ~clk; 81 | 82 | initial begin 83 | $dumpfile("tee_local_tb.vcd"); 84 | $dumpvars(0, cpu_tb); 85 | 86 | #1 87 | reset <= 0; 88 | 89 | if(USE_64B) begin 90 | #39 91 | `assert(result, 2); 92 | `assert(result_type, `i64); 93 | `assert(result_empty, 0); 94 | end 95 | else begin 96 | #12 97 | `assert(trap, `NO_64B); 98 | end 99 | 100 | $finish; 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /test/genrom.hex: -------------------------------------------------------------------------------- 1 | 81 //-- [00] LEDS 0x1 2 | 00 //-- [01] WAIT 3 | 82 //-- [02] LEDS 0x2 4 | 00 //-- [03] WAIT 5 | 84 //-- [04] LEDS 0x4 6 | 00 //-- [05] WAIT 7 | 88 //-- [06] LEDS 0x8 8 | 00 //-- [07] WAIT 9 | 81 //-- [08] LEDS 0x1 10 | 40 //-- [09] HALT 11 | -------------------------------------------------------------------------------- /test/genrom_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI 3 | [*] Sat Mar 25 12:31:54 2017 4 | [*] 5 | [dumpfile] "/home/piranna/github/wasmachine/build/genrom_tb.vcd" 6 | [dumpfile_mtime] "Sat Mar 25 12:30:42 2017" 7 | [dumpfile_size] 1581 8 | [savefile] "/home/piranna/github/wasmachine/test/genrom_tb.gtkw" 9 | [timestart] 0 10 | [size] 1366 720 11 | [pos] -1 -30 12 | *-1.845623 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] genrom_tb. 14 | [sst_width] 213 15 | [signals_width] 158 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 196 18 | @28 19 | genrom_tb.clk 20 | @200 21 | - 22 | @22 23 | genrom_tb.addr[3:0] 24 | genrom_tb.extra[3:0] 25 | @200 26 | - 27 | @22 28 | genrom_tb.lower_bound[3:0] 29 | genrom_tb.upper_bound[3:0] 30 | @201 31 | - 32 | @22 33 | genrom_tb.data[127:0] 34 | @28 35 | genrom_tb.error 36 | [pattern_trace] 1 37 | [pattern_trace] 0 38 | -------------------------------------------------------------------------------- /test/genrom_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | 4 | module genrom_tb(); 5 | 6 | parameter AW = 4; 7 | parameter DW = 8; 8 | parameter EXTRA = 4; 9 | 10 | reg clk = 0; 11 | logic[ AW:0] addr; 12 | logic[ EXTRA-1:0] extra; 13 | logic[ AW:0] lower_bound=0; 14 | logic[ AW:0] upper_bound=9; 15 | wire [DW*2**EXTRA-1:0] data; 16 | wire error; 17 | 18 | genrom #( 19 | .AW(AW), 20 | .DW(DW), 21 | .ROMFILE("genrom.hex") 22 | ) 23 | dut( 24 | .clk(clk), 25 | .addr(addr), 26 | .extra(extra), 27 | .lower_bound(lower_bound), 28 | .upper_bound(upper_bound), 29 | .data(data), 30 | .error(error) 31 | ); 32 | 33 | always #1 clk = ~clk; 34 | 35 | initial begin 36 | $dumpfile("genrom_tb.vcd"); 37 | $dumpvars(0, genrom_tb); 38 | 39 | addr <= 0; 40 | extra <= 0; 41 | #2 42 | `assert(error, 0); 43 | `assert(data , 128'h81); 44 | 45 | addr <= 1; 46 | extra <= 1; 47 | #2 48 | `assert(error, 0); 49 | `assert(data , 128'h0082); 50 | 51 | addr <= 3; 52 | extra <= 3; 53 | #2 54 | `assert(error, 0); 55 | `assert(data , 128'h00840088); 56 | 57 | addr <= 0; 58 | extra <= 4; 59 | #2 60 | `assert(error, 0); 61 | `assert(data , 128'h8100820084); 62 | 63 | addr <= 0; 64 | extra <= 7; 65 | #2 66 | `assert(error, 0); 67 | `assert(data , 128'h8100820084008800); 68 | 69 | addr <= 0; 70 | extra <= 15; 71 | #2 72 | `assert(error, 0); 73 | `assert(data , 128'h81008200840088008140xxxxxxxxxxxx); 74 | 75 | addr <= 9; 76 | extra <= 0; 77 | #2 78 | `assert(error, 0); 79 | 80 | addr <= 10; 81 | extra <= 0; 82 | #2 83 | `assert(error, 1); 84 | 85 | $finish; 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /test/stack_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI 3 | [*] Mon Apr 3 21:30:53 2017 4 | [*] 5 | [dumpfile] "/home/piranna/github/wasmachine/build/stack_tb.vcd" 6 | [dumpfile_mtime] "Mon Apr 3 21:30:07 2017" 7 | [dumpfile_size] 1200 8 | [savefile] "/home/piranna/github/wasmachine/test/stack_tb.gtkw" 9 | [timestart] 0 10 | [size] 1366 720 11 | [pos] -1 -1 12 | *-2.696093 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] Stack_tb. 14 | [sst_width] 213 15 | [signals_width] 209 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 293 18 | @28 19 | Stack_tb.dut.clk 20 | Stack_tb.dut.reset 21 | @200 22 | - 23 | @28 24 | Stack_tb.dut.op[1:0] 25 | @22 26 | Stack_tb.dut.data[7:0] 27 | @200 28 | - 29 | @22 30 | Stack_tb.dut.tos[7:0] 31 | @28 32 | Stack_tb.dut.status[1:0] 33 | @200 34 | - 35 | @28 36 | Stack_tb.dut.index[1:0] 37 | [pattern_trace] 1 38 | [pattern_trace] 0 39 | -------------------------------------------------------------------------------- /test/stack_tb.v: -------------------------------------------------------------------------------- 1 | `include "assert.vh" 2 | 3 | `include "stack.vh" 4 | 5 | 6 | module Stack_tb(); 7 | 8 | parameter WIDTH = 8; 9 | parameter DEPTH = 1; // frames (exponential) 10 | 11 | localparam MAX_STACK = (1 << DEPTH+1) - 1; 12 | 13 | reg clk = 0; 14 | reg reset; 15 | reg [ 1:0] op; 16 | reg [WIDTH-1:0] data; 17 | wire [WIDTH-1:0] tos; 18 | wire [1:0] status; 19 | wire [1:0] error; 20 | 21 | stack #( 22 | .WIDTH(WIDTH), 23 | .DEPTH(DEPTH) 24 | ) 25 | dut( 26 | .clk(clk), 27 | .reset(reset), 28 | .op(op), 29 | .data(data), 30 | .tos(tos), 31 | .status(status), 32 | .error(error) 33 | ); 34 | 35 | always #1 clk = ~clk; 36 | 37 | initial begin 38 | $dumpfile("stack_tb.vcd"); 39 | $dumpvars(0, Stack_tb); 40 | 41 | // `status` is `empty` by default 42 | `assert(status, `EMPTY); 43 | 44 | // Underflow 45 | op <= `POP; 46 | data <= 0; 47 | #2 48 | `assert(error, `UNDERFLOW); 49 | 50 | // Push 51 | op <= `PUSH; 52 | data <= 0; 53 | #2 54 | `assert(status, `NONE); 55 | `assert(tos , 8'h00); 56 | 57 | op <= `PUSH; 58 | data <= 1; 59 | #2 60 | `assert(status, `NONE); 61 | `assert(tos , 8'h01); 62 | 63 | op <= `PUSH; 64 | data <= 2; 65 | #2 66 | `assert(status, `FULL); 67 | `assert(tos , 8'h02); 68 | 69 | // Top of Stack 70 | op <= `NONE; 71 | #2 72 | `assert(status, `FULL); 73 | `assert(tos , 8'h02); 74 | 75 | // Overflow 76 | op <= `PUSH; 77 | data <= 3; 78 | #2 79 | `assert(error, `OVERFLOW); 80 | `assert(tos , 8'h02); 81 | 82 | // Pop 83 | op <= `POP; 84 | data <= 0; 85 | #2 86 | `assert(status, `NONE); 87 | `assert(tos , 8'h01); 88 | 89 | op <= `POP; 90 | data <= 0; 91 | #2 92 | `assert(status, `NONE); 93 | `assert(tos , 8'h00); 94 | 95 | op <= `POP; 96 | data <= 0; 97 | #2 98 | `assert(status, `EMPTY); 99 | 100 | // Replace 101 | op <= `REPLACE; 102 | data <= 4; 103 | #2 104 | `assert(error, `UNDERFLOW); 105 | 106 | op <= `PUSH; 107 | data <= 5; 108 | #2 109 | `assert(status, `NONE); 110 | `assert(tos , 8'h05); 111 | 112 | op <= `REPLACE; 113 | data <= 6; 114 | #2 115 | `assert(status, `NONE); 116 | `assert(tos , 8'h06); 117 | 118 | op <= `NONE; 119 | #2 120 | `assert(status, `NONE); 121 | `assert(tos , 8'h06); 122 | 123 | // Reset 124 | reset <= 1; 125 | #2 126 | reset <= 0; 127 | `assert(status, `EMPTY); 128 | 129 | $finish; 130 | end 131 | 132 | endmodule 133 | --------------------------------------------------------------------------------