├── .gitmodules ├── README.md ├── hw ├── .gitignore ├── src │ ├── bd │ │ └── system │ │ │ ├── hdl │ │ │ └── system_wrapper.v │ │ │ ├── ip │ │ │ ├── system_auto_pc_2 │ │ │ │ ├── system_auto_pc_2.xci │ │ │ │ └── system_auto_pc_2.xml │ │ │ ├── system_auto_pc_5 │ │ │ │ ├── system_auto_pc_5.xci │ │ │ │ └── system_auto_pc_5.xml │ │ │ ├── system_auto_pc_6 │ │ │ │ ├── system_auto_pc_6.xci │ │ │ │ └── system_auto_pc_6.xml │ │ │ ├── system_axi_interconnect_0_2 │ │ │ │ ├── system_axi_interconnect_0_2.xci │ │ │ │ └── system_axi_interconnect_0_2.xml │ │ │ ├── system_axi_interconnect_1_3 │ │ │ │ ├── system_axi_interconnect_1_3.xci │ │ │ │ └── system_axi_interconnect_1_3.xml │ │ │ ├── system_proc_sys_reset_0_1 │ │ │ │ ├── system_proc_sys_reset_0_1.xci │ │ │ │ └── system_proc_sys_reset_0_1.xml │ │ │ └── system_processing_system7_0_0 │ │ │ │ ├── system_processing_system7_0_0.xci │ │ │ │ └── system_processing_system7_0_0.xml │ │ │ ├── system.bd │ │ │ ├── system.bxml │ │ │ ├── system_ooc.xdc │ │ │ └── ui │ │ │ └── bd_c954508f.ui │ ├── constrs │ │ └── base.xdc │ └── verilog │ │ ├── Slave.v │ │ ├── fifos.v │ │ └── system_wrapper.v └── zybo_refchip.tcl └── sd_image ├── boot.bin ├── devicetree.dtb ├── riscv ├── root_spike.bin └── vmlinux ├── uImage └── uramdisk.image.gz /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "u-boot-Digilent-Dev"] 2 | path = u-boot-Digilent-Dev 3 | url = https://github.com/ucb-bar/u-boot-Digilent-Dev.git 4 | [submodule "Linux-Digilent-Dev"] 5 | path = Linux-Digilent-Dev 6 | url = https://github.com/ucb-bar/Linux-Digilent-Dev.git 7 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | zynq-fpga 2 | ========= 3 | 4 | This repo contains the software and instructions necessary to run a RISC-V Rocket Core on the Digilent Zybo board. 5 | 6 | Setup 7 | -------------- 8 | 9 | ### Method 1 \(Quick\): 10 | 11 | Step 1: Copy everything from the `sd_image` directory to the root of your 12 | microsd card. 13 | 14 | Jump to the "Booting Up and interacting with the RISC-V Rocket core" section 15 | to continue. 16 | 17 | ### Method 2 \(Build From Scratch\): 18 | 19 | You may also build the system from scratch. These instructions have been tested with Vivado 2013.4 and Xilinx SDK 2013.4. 20 | 21 | As a quick summary, here's what the Zybo will do when booting: 22 | 23 | 1) Impact the Rocket Core onto the zynq's programmable logic and configure the 24 | on-board ARM core. These come from the `system_wrapper.bit` file, which will be 25 | part of `boot.bin` on the sd card. 26 | 27 | 2) Run the First Stage BootLoader (FSBL), which is part of boot.bin which we will eventually create. 28 | 29 | 3) The FSBL will start u-Boot, which sets up the environment for linux on the ARM core. 30 | 31 | 4) Finally, u-Boot will start our linux image (uImage) on the ARM core. 32 | This requires a custom devicetree.dtb file, which we will compile shortly. 33 | 34 | We'll now go ahead and build each of these components. 35 | 36 | ####Step 0: 37 | 38 | Make sure you've sourced the settings for Vivado as necessary on your system. 39 | 40 | ####Step 1: Building the Vivado Project 41 | 42 | $ git clone git@github.com:ucb-bar/zybo.git 43 | $ cd zybo/hw 44 | $ vivado -mode tcl -source zybo_refchip.tcl 45 | $ cd zybo_bsd 46 | $ vivado ./zybo_bsd.xpr 47 | 48 | Once in Vivado, first hit "Generate Block Design" -> system.bd, then hit "Open Block Design" -> system.bd. 49 | 50 | Then, run Generate Bitstream (it should step through Synthesis and Implementation automatically). 51 | While this is running, you can go ahead and follow steps 3 and 4 to build u-boot and Linux (but not the FSBL). 52 | 53 | Once bitstream generation in vivado finishes, make sure that "Open Implemented Design" is selected and hit "OK". 54 | After the implemented design is open, we can export the project to the Xilinx SDK. 55 | To do so, hit File -> Export -> "Export Hardware for SDK...". 56 | 57 | In the dialog that pops up, make sure that Source is selected as "system.bd". 58 | You can leave "Export to" and "Workspace" as their defaults, which should be 59 | ``. The rest of the tutorial assumes that this is the case. 60 | Finally, make sure that "Export Hardware", "Include bitstream", and "Launch SDK" 61 | are all checked. Then click OK. Once the SDK launches, feel free to exit Vivado. 62 | 63 | In case the SDK fails to launch, the command to do so is: 64 | 65 | $ xsdk -bit [ZYBO REPO LOCATION]/hw/zybo_bsd/zybo_bsd.sdk/SDK/SDK_Export/hw/system_wrapper.bit -workspace [ZYBO REPO LOCATION]/hw/zybo_bsd/zybo_bsd.sdk/SDK/SDK_Export -hwspec [ZYBO_REPO_LOCATION]/hw/zybo_bsd/zybo_bsd.sdk/SDK/SDK_Export/hw/system.xml 66 | 67 | ####Step 2: Building the First-Stage BootLoader (FSBL) in Xilinx SDK 68 | 69 | Now, we'll use the SDK to build the FSBL: 70 | 71 | Inside the SDK, hit File -> New -> Project. In the window that pops up, expand 72 | the Xilinx node in the tree of options and click "Application Project". 73 | 74 | In the following window, enter "FSBL" as the Project name and ensure that 75 | Hardware Platform under Target Hardware is set to `hw_platform_0` and that the 76 | Processor is set to `ps7_cortexa9_0`. Under Target Software, ensure that OS 77 | Platform is set to standalone, Language is set to C, and Board Support Package 78 | is set to Create New, with "FSBL_bsp" as the name. 79 | 80 | After you hit next, you'll be presented with a menu with available templates. 81 | Select "Zynq FSBL" and click finish. Once you do so, you should see compilation 82 | in progress in the console. Wait until "Build Finished" appears. Do not exit 83 | Xilinx SDK yet, we'll come back to it in a couple of steps to package up 84 | `boot.bin`. 85 | 86 | ####Step 3: Build u-boot for the zybo: 87 | 88 | 89 | First, you'll want to grab the u-boot source for the Zybo. Since things tend to 90 | shift around in Digilent's repos, we've made a fork to ensure a stable base for 91 | this guide. This copy of the repo also contains a modified copy of the default 92 | zybo u-boot configuration to support the RISC-V Rocket core. The repo is already 93 | present as a submodule, so you'll need to initialize it (this will also download 94 | the linux source for you, which you'll need in Step 5): 95 | 96 | [From inside the zybo repo] 97 | $ git submodule update --init 98 | 99 | Next, we'll go ahead and build u-boot. To do so, enter the following: 100 | 101 | $ cd u-boot-Digilent-Dev 102 | $ make CROSS_COMPILE=arm-xilinx-linux-gnueabi- zynq_zybo_config 103 | $ make CROSS_COMPILE=arm-xilinx-linux-gnueabi- 104 | 105 | Once the build completes, the file we need is called "u-boot", but we need to 106 | rename it. Run the following to do so: 107 | 108 | $ mv u-boot u-boot.elf 109 | 110 | #### Step 4: Create boot.bin 111 | 112 | At this point, we'll package up the 3 main files we've built so far: 113 | `system_wrapper.bit`, the FSBL binary, and the `u-boot.elf` binary. To do so, 114 | return to the Xilinx SDK and select "Create Zynq Boot Image" from the 115 | "Xilinx Tools" menu. 116 | 117 | In the window that appears, choose an output location for the `boot.bif` file 118 | we'll create. Do not check "Use Authentication" or "Use Encryption". Also set 119 | an output path for `boot.bin` at the bottom (it will likely be called 120 | `output.bin` by default). Now, in the Boot Image Partitions area, hit Add. 121 | 122 | In the window that pops up, ensure that Partition type is set as bootloader and 123 | click browse. The file we're looking for is called `FSBL.elf`. If you've followed 124 | these instructions exactly, it will be located in: 125 | 126 | [ZYBO REPO LOCATION]/hw/zybo_bsd/zybo_bsd.sdk/SDK/SDK_Export/FSBL/Debug/FSBL.elf 127 | 128 | Once you've located the file, click OK. 129 | 130 | Next we'll add the bit file containing our design (with the Rocket core). Click 131 | add once again. This time, Partition type should be set as datafile. Navigate 132 | to the following directory to choose your bit file: 133 | 134 | [ZYBO REPO LOCATION]/hw/zybo_bsd/zybo_bsd.sdk/SDK/SDK_Export/hw_platform_0/system_wrapper.bit 135 | 136 | Once you've located the file, click OK. 137 | 138 | Finally, we'll add in u-boot. Again, click Add and ensure that Partition type 139 | is set to datafile in the window that appears. Now, click browse and select 140 | `u-boot.elf` located in: 141 | 142 | [ZYBO REPO LOCATION]/u-boot-Digilent-Dev/u-boot.elf 143 | 144 | Once you've located the file, click OK and hit Create Image in the 145 | Create Zynq Boot Image window. Copy the generated boot.bin file to your sd card. 146 | You may now close the Xilinx SDK window. 147 | 148 | #### Step 5: Build Linux Kernel uImage 149 | 150 | Next, we'll move on to building the Linux Kernel uImage. Again, to keep our 151 | dependencies in-order, we've created a fork of the Digilent linux repo and 152 | added a modified dts file to support Rocket's Host-Target Interface (HTIF). 153 | When you ran `git submodule update --init` back in step 3, the source for 154 | linux was pulled into `[ZYBO REPO LOCATION]/Linux-Digilent-Dev`. Enter that 155 | directory and do the following to build linux: 156 | 157 | $ make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig 158 | $ make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- 159 | 160 | This will produce a zImage file, however we need a uImage. In order to build a 161 | uImage, the Makefile needs to be able to run the `mkimage` program found in 162 | `u-boot-Digilent-Dev/tools`. Thus, we'll have to add it to our path: 163 | 164 | $ export PATH=$PATH:[ZYBO REPO LOCATION]/u-boot-Digilent-Dev/tools 165 | $ make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- UIMAGE_LOADADDR=0x8000 uImage 166 | 167 | This will produce the file 168 | `[ZYBO REPO LOCATION]/Linux-Digilent-Dev/arch/arm/boot/uImage`. Copy this file 169 | to your sdcard. 170 | 171 | Next, we'll compile our device tree, so that the kernel knows where our devices 172 | are. The copy of linux in this repo already contains a modified device tree to 173 | support the HTIF infrastructure that Rocket needs. To compile it, run the 174 | following from inside `[ZYBO REPO LOCATION]/Linux-Digilent-Dev/`. 175 | 176 | $ ./scripts/dtc/dtc -I dts -O dtb -o devicetree.dtb arch/arm/boot/dts/zynq-zybo.dts 177 | 178 | This will produce a `devicetree.dtb` file, which you should copy to your sdcard. 179 | 180 | Finally, copy the uramdisk.image.gz file from `[ZYBO REPO LOCATION]/sd_image/` 181 | to your sd card. This is the root filesystem for ARM linux, which contains a 182 | copy of riscv-fesvr (frontend server) that will interact with our Rocket core 183 | on the programmable logic. If you'd like to modify this ramdisk, see Appendix A 184 | at the bottom of this document. 185 | 186 | At this point, there should be 4 files on your sd card. Continue to the 187 | "Booting Up and interacting with the RISC-V Rocket core" section. 188 | 189 | Booting Up and Interacting with the RISC-V Core 190 | -------------- 191 | 192 | Finally, copy the sd_image/riscv directory to your sd card. This contains 193 | a copy of the linux kernel compiled for RISC-V, along with an appropriate 194 | root filesystem. At this point, the directory structure of your sd card 195 | should match the following: 196 | 197 | SD_ROOT/ 198 | |-> riscv/ 199 | |-> root_spike.bin 200 | |-> vmlinux 201 | |-> boot.bin 202 | |-> devicetree.dtb 203 | |-> uImage 204 | |-> uramdisk.image.gz 205 | 206 | Insert the microsd card in your zybo. At this point you have two options for 207 | logging in: 208 | 209 | 1) USB-UART 210 | 211 | To connect over usb, do the following (the text following tty. may vary): 212 | 213 | $ screen /dev/tty.usbserial-210279575138B 115200,cs8,-parenb,-cstopb 214 | 215 | 2) Telnet 216 | 217 | You may also connect over telnet using ethernet. The default IP address is 218 | `192.168.192.5`: 219 | 220 | $ telnet 192.168.192.5 221 | 222 | In either case, you'll eventually be prompted to login to the ARM system. Both the 223 | username and password are `root`. 224 | 225 | Once you're in, you'll need to mount the sd card so that we can access the files 226 | necessary to boot linux on the Rocket core. Do the following: 227 | 228 | $ mkdir /sdcard 229 | $ mount /dev/mmcblk0p1 /sdcard 230 | 231 | Finally, we can go ahead and boot linux on the Rocket core: 232 | 233 | $ ./fesvr-zedboard +disk=/sdcard/riscv/root_spike.bin /sdcard/riscv/vmlinux 234 | 235 | Appendices 236 | -------------- 237 | 238 | ### Appendix A: Modifying the rootfs: 239 | 240 | The RAMDisk that holds linux (uramdisk.image.gz) is a gzipped cpio archive 241 | with a u-boot header for the zybo. To open it up (will need sudo): 242 | 243 | $ dd if=sd_image/uramdisk.image.gz bs=64 skip=1 of=uramdisk.cpio.gz 244 | $ mkdir ramdisk 245 | $ gunzip -c uramdisk.cpio.gz | sudo sh -c 'cd ramdisk/ && cpio -i' 246 | 247 | When changing or adding files, be sure to keep track of owners, groups, and 248 | permissions. When you are done, to package it back up: 249 | 250 | $ sh -c 'cd ramdisk/ && sudo find . | sudo cpio -H newc -o' | gzip -9 > uramdisk.cpio.gz 251 | $ mkimage -A arm -O linux -T ramdisk -d uramdisk.cpio.gz uramdisk.image.gz 252 | 253 | ### Appendix B: Building Slave.v from reference-chip 254 | 255 | The copy of Slave.v in this repo was built from https://github.com/ucb-bar/reference-chip/tree/b121a85780639eae87469c335c9cc853ce827cab 256 | 257 | The following changes were made to allow the design to fit on the Zybo: 258 | 259 | 1) Remove Rocket's uarch counters: 260 | 261 | [Inside Rocket] 262 | 263 | diff --git a/src/main/scala/csr.scala b/src/main/scala/csr.scala 264 | index 2169055..158b749 100644 265 | --- a/src/main/scala/csr.scala 266 | +++ b/src/main/scala/csr.scala 267 | @@ -47,7 +47,7 @@ class CSRFileIO(implicit conf: RocketConfiguration) extends Bundle { 268 | val evec = UInt(OUTPUT, conf.as.vaddrBits+1) 269 | val exception = Bool(INPUT) 270 | val retire = UInt(INPUT, log2Up(1+conf.retireWidth)) 271 | - val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth))) 272 | +// val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth))) 273 | val cause = UInt(INPUT, conf.xprlen) 274 | val badvaddr_wen = Bool(INPUT) 275 | val pc = UInt(INPUT, conf.as.vaddrBits+1) 276 | @@ -78,7 +78,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module 277 | val reg_status = Reg(new Status) // reset down below 278 | val reg_time = WideCounter(conf.xprlen) 279 | val reg_instret = WideCounter(conf.xprlen, io.retire) 280 | - val reg_uarch_counters = io.uarch_counters.map(WideCounter(conf.xprlen, _)) 281 | +// val reg_uarch_counters = io.uarch_counters.map(WideCounter(conf.xprlen, _)) 282 | val reg_fflags = Reg(UInt(width = 5)) 283 | val reg_frm = Reg(UInt(width = 3)) 284 | 285 | @@ -192,8 +192,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module 286 | CSRs.tohost -> reg_tohost, 287 | CSRs.fromhost -> reg_fromhost) 288 | 289 | - for (i <- 0 until reg_uarch_counters.size) 290 | - read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i) 291 | +// for (i <- 0 until reg_uarch_counters.size) 292 | +// read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i) 293 | 294 | io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) 295 | 296 | diff --git a/src/main/scala/dpath.scala b/src/main/scala/dpath.scala 297 | index ea6b59c..b5f143a 100644 298 | --- a/src/main/scala/dpath.scala 299 | +++ b/src/main/scala/dpath.scala 300 | @@ -182,7 +182,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module 301 | pcr.io.rocc <> io.rocc 302 | pcr.io.pc := wb_reg_pc 303 | io.ctrl.csr_replay := pcr.io.replay 304 | - pcr.io.uarch_counters.foreach(_ := Bool(false)) 305 | +// pcr.io.uarch_counters.foreach(_ := Bool(false)) 306 | 307 | io.ptw.ptbr := pcr.io.ptbr 308 | io.ptw.invalidate := pcr.io.fatc 309 | 310 | 2) Modify L2CoherenceAgentConfiguration: 311 | 312 | [Inside reference-chip] 313 | diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala 314 | index 7f4df49..799ab2a 100644 315 | --- a/src/main/scala/fpga.scala 316 | +++ b/src/main/scala/fpga.scala 317 | @@ -85,7 +85,7 @@ class FPGATop extends Module { 318 | writeMaskBits = WRITE_MASK_BITS, 319 | wordAddrBits = SUBWORD_ADDR_BITS, 320 | atomicOpBits = ATOMIC_OP_BITS) 321 | - implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) 322 | + implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 4) 323 | implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) 324 | implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = OFFSET_BITS) 325 | -------------------------------------------------------------------------------- /hw/.gitignore: -------------------------------------------------------------------------------- 1 | vivado* 2 | zybo_bsd 3 | *.log 4 | -------------------------------------------------------------------------------- /hw/src/bd/system/hdl/system_wrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | 3 | module system_wrapper 4 | (DDR_addr, 5 | DDR_ba, 6 | DDR_cas_n, 7 | DDR_ck_n, 8 | DDR_ck_p, 9 | DDR_cke, 10 | DDR_cs_n, 11 | DDR_dm, 12 | DDR_dq, 13 | DDR_dqs_n, 14 | DDR_dqs_p, 15 | DDR_odt, 16 | DDR_ras_n, 17 | DDR_reset_n, 18 | DDR_we_n, 19 | FCLK_RESET0_N, 20 | FIXED_IO_ddr_vrn, 21 | FIXED_IO_ddr_vrp, 22 | FIXED_IO_mio, 23 | FIXED_IO_ps_clk, 24 | FIXED_IO_ps_porb, 25 | FIXED_IO_ps_srstb, 26 | M_AXI_araddr, 27 | M_AXI_arburst, 28 | M_AXI_arcache, 29 | M_AXI_arid, 30 | M_AXI_arlen, 31 | M_AXI_arlock, 32 | M_AXI_arprot, 33 | M_AXI_arqos, 34 | M_AXI_arready, 35 | M_AXI_arregion, 36 | M_AXI_arsize, 37 | M_AXI_arvalid, 38 | M_AXI_awaddr, 39 | M_AXI_awburst, 40 | M_AXI_awcache, 41 | M_AXI_awid, 42 | M_AXI_awlen, 43 | M_AXI_awlock, 44 | M_AXI_awprot, 45 | M_AXI_awqos, 46 | M_AXI_awready, 47 | M_AXI_awregion, 48 | M_AXI_awsize, 49 | M_AXI_awvalid, 50 | M_AXI_bid, 51 | M_AXI_bready, 52 | M_AXI_bresp, 53 | M_AXI_bvalid, 54 | M_AXI_rdata, 55 | M_AXI_rid, 56 | M_AXI_rlast, 57 | M_AXI_rready, 58 | M_AXI_rresp, 59 | M_AXI_rvalid, 60 | M_AXI_wdata, 61 | M_AXI_wlast, 62 | M_AXI_wready, 63 | M_AXI_wstrb, 64 | M_AXI_wvalid, 65 | S_AXI_araddr, 66 | S_AXI_arburst, 67 | S_AXI_arcache, 68 | S_AXI_arid, 69 | S_AXI_arlen, 70 | S_AXI_arlock, 71 | S_AXI_arprot, 72 | S_AXI_arqos, 73 | S_AXI_arready, 74 | S_AXI_arregion, 75 | S_AXI_arsize, 76 | S_AXI_arvalid, 77 | S_AXI_awaddr, 78 | S_AXI_awburst, 79 | S_AXI_awcache, 80 | S_AXI_awid, 81 | S_AXI_awlen, 82 | S_AXI_awlock, 83 | S_AXI_awprot, 84 | S_AXI_awqos, 85 | S_AXI_awready, 86 | S_AXI_awregion, 87 | S_AXI_awsize, 88 | S_AXI_awvalid, 89 | S_AXI_bid, 90 | S_AXI_bready, 91 | S_AXI_bresp, 92 | S_AXI_bvalid, 93 | S_AXI_rdata, 94 | S_AXI_rid, 95 | S_AXI_rlast, 96 | S_AXI_rready, 97 | S_AXI_rresp, 98 | S_AXI_rvalid, 99 | S_AXI_wdata, 100 | S_AXI_wlast, 101 | S_AXI_wready, 102 | S_AXI_wstrb, 103 | S_AXI_wvalid, 104 | ext_clk_in); 105 | inout [14:0]DDR_addr; 106 | inout [2:0]DDR_ba; 107 | inout DDR_cas_n; 108 | inout DDR_ck_n; 109 | inout DDR_ck_p; 110 | inout DDR_cke; 111 | inout DDR_cs_n; 112 | inout [3:0]DDR_dm; 113 | inout [31:0]DDR_dq; 114 | inout [3:0]DDR_dqs_n; 115 | inout [3:0]DDR_dqs_p; 116 | inout DDR_odt; 117 | inout DDR_ras_n; 118 | inout DDR_reset_n; 119 | inout DDR_we_n; 120 | output FCLK_RESET0_N; 121 | inout FIXED_IO_ddr_vrn; 122 | inout FIXED_IO_ddr_vrp; 123 | inout [53:0]FIXED_IO_mio; 124 | inout FIXED_IO_ps_clk; 125 | inout FIXED_IO_ps_porb; 126 | inout FIXED_IO_ps_srstb; 127 | output [31:0]M_AXI_araddr; 128 | output [1:0]M_AXI_arburst; 129 | output [3:0]M_AXI_arcache; 130 | output [11:0]M_AXI_arid; 131 | output [7:0]M_AXI_arlen; 132 | output [0:0]M_AXI_arlock; 133 | output [2:0]M_AXI_arprot; 134 | output [3:0]M_AXI_arqos; 135 | input M_AXI_arready; 136 | output [3:0]M_AXI_arregion; 137 | output [2:0]M_AXI_arsize; 138 | output M_AXI_arvalid; 139 | output [31:0]M_AXI_awaddr; 140 | output [1:0]M_AXI_awburst; 141 | output [3:0]M_AXI_awcache; 142 | output [11:0]M_AXI_awid; 143 | output [7:0]M_AXI_awlen; 144 | output [0:0]M_AXI_awlock; 145 | output [2:0]M_AXI_awprot; 146 | output [3:0]M_AXI_awqos; 147 | input M_AXI_awready; 148 | output [3:0]M_AXI_awregion; 149 | output [2:0]M_AXI_awsize; 150 | output M_AXI_awvalid; 151 | input [11:0]M_AXI_bid; 152 | output M_AXI_bready; 153 | input [1:0]M_AXI_bresp; 154 | input M_AXI_bvalid; 155 | input [31:0]M_AXI_rdata; 156 | input [11:0]M_AXI_rid; 157 | input M_AXI_rlast; 158 | output M_AXI_rready; 159 | input [1:0]M_AXI_rresp; 160 | input M_AXI_rvalid; 161 | output [31:0]M_AXI_wdata; 162 | output M_AXI_wlast; 163 | input M_AXI_wready; 164 | output [3:0]M_AXI_wstrb; 165 | output M_AXI_wvalid; 166 | input [31:0]S_AXI_araddr; 167 | input [1:0]S_AXI_arburst; 168 | input [3:0]S_AXI_arcache; 169 | input [5:0]S_AXI_arid; 170 | input [7:0]S_AXI_arlen; 171 | input [0:0]S_AXI_arlock; 172 | input [2:0]S_AXI_arprot; 173 | input [3:0]S_AXI_arqos; 174 | output S_AXI_arready; 175 | input [3:0]S_AXI_arregion; 176 | input [2:0]S_AXI_arsize; 177 | input S_AXI_arvalid; 178 | input [31:0]S_AXI_awaddr; 179 | input [1:0]S_AXI_awburst; 180 | input [3:0]S_AXI_awcache; 181 | input [5:0]S_AXI_awid; 182 | input [7:0]S_AXI_awlen; 183 | input [0:0]S_AXI_awlock; 184 | input [2:0]S_AXI_awprot; 185 | input [3:0]S_AXI_awqos; 186 | output S_AXI_awready; 187 | input [3:0]S_AXI_awregion; 188 | input [2:0]S_AXI_awsize; 189 | input S_AXI_awvalid; 190 | output [5:0]S_AXI_bid; 191 | input S_AXI_bready; 192 | output [1:0]S_AXI_bresp; 193 | output S_AXI_bvalid; 194 | output [63:0]S_AXI_rdata; 195 | output [5:0]S_AXI_rid; 196 | output S_AXI_rlast; 197 | input S_AXI_rready; 198 | output [1:0]S_AXI_rresp; 199 | output S_AXI_rvalid; 200 | input [63:0]S_AXI_wdata; 201 | input S_AXI_wlast; 202 | output S_AXI_wready; 203 | input [7:0]S_AXI_wstrb; 204 | input S_AXI_wvalid; 205 | input ext_clk_in; 206 | 207 | wire [14:0]DDR_addr; 208 | wire [2:0]DDR_ba; 209 | wire DDR_cas_n; 210 | wire DDR_ck_n; 211 | wire DDR_ck_p; 212 | wire DDR_cke; 213 | wire DDR_cs_n; 214 | wire [3:0]DDR_dm; 215 | wire [31:0]DDR_dq; 216 | wire [3:0]DDR_dqs_n; 217 | wire [3:0]DDR_dqs_p; 218 | wire DDR_odt; 219 | wire DDR_ras_n; 220 | wire DDR_reset_n; 221 | wire DDR_we_n; 222 | wire FCLK_RESET0_N; 223 | wire FIXED_IO_ddr_vrn; 224 | wire FIXED_IO_ddr_vrp; 225 | wire [53:0]FIXED_IO_mio; 226 | wire FIXED_IO_ps_clk; 227 | wire FIXED_IO_ps_porb; 228 | wire FIXED_IO_ps_srstb; 229 | wire [31:0]M_AXI_araddr; 230 | wire [1:0]M_AXI_arburst; 231 | wire [3:0]M_AXI_arcache; 232 | wire [11:0]M_AXI_arid; 233 | wire [7:0]M_AXI_arlen; 234 | wire [0:0]M_AXI_arlock; 235 | wire [2:0]M_AXI_arprot; 236 | wire [3:0]M_AXI_arqos; 237 | wire M_AXI_arready; 238 | wire [3:0]M_AXI_arregion; 239 | wire [2:0]M_AXI_arsize; 240 | wire M_AXI_arvalid; 241 | wire [31:0]M_AXI_awaddr; 242 | wire [1:0]M_AXI_awburst; 243 | wire [3:0]M_AXI_awcache; 244 | wire [11:0]M_AXI_awid; 245 | wire [7:0]M_AXI_awlen; 246 | wire [0:0]M_AXI_awlock; 247 | wire [2:0]M_AXI_awprot; 248 | wire [3:0]M_AXI_awqos; 249 | wire M_AXI_awready; 250 | wire [3:0]M_AXI_awregion; 251 | wire [2:0]M_AXI_awsize; 252 | wire M_AXI_awvalid; 253 | wire [11:0]M_AXI_bid; 254 | wire M_AXI_bready; 255 | wire [1:0]M_AXI_bresp; 256 | wire M_AXI_bvalid; 257 | wire [31:0]M_AXI_rdata; 258 | wire [11:0]M_AXI_rid; 259 | wire M_AXI_rlast; 260 | wire M_AXI_rready; 261 | wire [1:0]M_AXI_rresp; 262 | wire M_AXI_rvalid; 263 | wire [31:0]M_AXI_wdata; 264 | wire M_AXI_wlast; 265 | wire M_AXI_wready; 266 | wire [3:0]M_AXI_wstrb; 267 | wire M_AXI_wvalid; 268 | wire [31:0]S_AXI_araddr; 269 | wire [1:0]S_AXI_arburst; 270 | wire [3:0]S_AXI_arcache; 271 | wire [5:0]S_AXI_arid; 272 | wire [7:0]S_AXI_arlen; 273 | wire [0:0]S_AXI_arlock; 274 | wire [2:0]S_AXI_arprot; 275 | wire [3:0]S_AXI_arqos; 276 | wire S_AXI_arready; 277 | wire [3:0]S_AXI_arregion; 278 | wire [2:0]S_AXI_arsize; 279 | wire S_AXI_arvalid; 280 | wire [31:0]S_AXI_awaddr; 281 | wire [1:0]S_AXI_awburst; 282 | wire [3:0]S_AXI_awcache; 283 | wire [5:0]S_AXI_awid; 284 | wire [7:0]S_AXI_awlen; 285 | wire [0:0]S_AXI_awlock; 286 | wire [2:0]S_AXI_awprot; 287 | wire [3:0]S_AXI_awqos; 288 | wire S_AXI_awready; 289 | wire [3:0]S_AXI_awregion; 290 | wire [2:0]S_AXI_awsize; 291 | wire S_AXI_awvalid; 292 | wire [5:0]S_AXI_bid; 293 | wire S_AXI_bready; 294 | wire [1:0]S_AXI_bresp; 295 | wire S_AXI_bvalid; 296 | wire [63:0]S_AXI_rdata; 297 | wire [5:0]S_AXI_rid; 298 | wire S_AXI_rlast; 299 | wire S_AXI_rready; 300 | wire [1:0]S_AXI_rresp; 301 | wire S_AXI_rvalid; 302 | wire [63:0]S_AXI_wdata; 303 | wire S_AXI_wlast; 304 | wire S_AXI_wready; 305 | wire [7:0]S_AXI_wstrb; 306 | wire S_AXI_wvalid; 307 | wire ext_clk_in; 308 | 309 | system system_i 310 | (.DDR_addr(DDR_addr), 311 | .DDR_ba(DDR_ba), 312 | .DDR_cas_n(DDR_cas_n), 313 | .DDR_ck_n(DDR_ck_n), 314 | .DDR_ck_p(DDR_ck_p), 315 | .DDR_cke(DDR_cke), 316 | .DDR_cs_n(DDR_cs_n), 317 | .DDR_dm(DDR_dm), 318 | .DDR_dq(DDR_dq), 319 | .DDR_dqs_n(DDR_dqs_n), 320 | .DDR_dqs_p(DDR_dqs_p), 321 | .DDR_odt(DDR_odt), 322 | .DDR_ras_n(DDR_ras_n), 323 | .DDR_reset_n(DDR_reset_n), 324 | .DDR_we_n(DDR_we_n), 325 | .FCLK_RESET0_N(FCLK_RESET0_N), 326 | .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), 327 | .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), 328 | .FIXED_IO_mio(FIXED_IO_mio), 329 | .FIXED_IO_ps_clk(FIXED_IO_ps_clk), 330 | .FIXED_IO_ps_porb(FIXED_IO_ps_porb), 331 | .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), 332 | .M_AXI_araddr(M_AXI_araddr), 333 | .M_AXI_arburst(M_AXI_arburst), 334 | .M_AXI_arcache(M_AXI_arcache), 335 | .M_AXI_arid(M_AXI_arid), 336 | .M_AXI_arlen(M_AXI_arlen), 337 | .M_AXI_arlock(M_AXI_arlock), 338 | .M_AXI_arprot(M_AXI_arprot), 339 | .M_AXI_arqos(M_AXI_arqos), 340 | .M_AXI_arready(M_AXI_arready), 341 | .M_AXI_arregion(M_AXI_arregion), 342 | .M_AXI_arsize(M_AXI_arsize), 343 | .M_AXI_arvalid(M_AXI_arvalid), 344 | .M_AXI_awaddr(M_AXI_awaddr), 345 | .M_AXI_awburst(M_AXI_awburst), 346 | .M_AXI_awcache(M_AXI_awcache), 347 | .M_AXI_awid(M_AXI_awid), 348 | .M_AXI_awlen(M_AXI_awlen), 349 | .M_AXI_awlock(M_AXI_awlock), 350 | .M_AXI_awprot(M_AXI_awprot), 351 | .M_AXI_awqos(M_AXI_awqos), 352 | .M_AXI_awready(M_AXI_awready), 353 | .M_AXI_awregion(M_AXI_awregion), 354 | .M_AXI_awsize(M_AXI_awsize), 355 | .M_AXI_awvalid(M_AXI_awvalid), 356 | .M_AXI_bid(M_AXI_bid), 357 | .M_AXI_bready(M_AXI_bready), 358 | .M_AXI_bresp(M_AXI_bresp), 359 | .M_AXI_bvalid(M_AXI_bvalid), 360 | .M_AXI_rdata(M_AXI_rdata), 361 | .M_AXI_rid(M_AXI_rid), 362 | .M_AXI_rlast(M_AXI_rlast), 363 | .M_AXI_rready(M_AXI_rready), 364 | .M_AXI_rresp(M_AXI_rresp), 365 | .M_AXI_rvalid(M_AXI_rvalid), 366 | .M_AXI_wdata(M_AXI_wdata), 367 | .M_AXI_wlast(M_AXI_wlast), 368 | .M_AXI_wready(M_AXI_wready), 369 | .M_AXI_wstrb(M_AXI_wstrb), 370 | .M_AXI_wvalid(M_AXI_wvalid), 371 | .S_AXI_araddr(S_AXI_araddr), 372 | .S_AXI_arburst(S_AXI_arburst), 373 | .S_AXI_arcache(S_AXI_arcache), 374 | .S_AXI_arid(S_AXI_arid), 375 | .S_AXI_arlen(S_AXI_arlen), 376 | .S_AXI_arlock(S_AXI_arlock), 377 | .S_AXI_arprot(S_AXI_arprot), 378 | .S_AXI_arqos(S_AXI_arqos), 379 | .S_AXI_arready(S_AXI_arready), 380 | .S_AXI_arregion(S_AXI_arregion), 381 | .S_AXI_arsize(S_AXI_arsize), 382 | .S_AXI_arvalid(S_AXI_arvalid), 383 | .S_AXI_awaddr(S_AXI_awaddr), 384 | .S_AXI_awburst(S_AXI_awburst), 385 | .S_AXI_awcache(S_AXI_awcache), 386 | .S_AXI_awid(S_AXI_awid), 387 | .S_AXI_awlen(S_AXI_awlen), 388 | .S_AXI_awlock(S_AXI_awlock), 389 | .S_AXI_awprot(S_AXI_awprot), 390 | .S_AXI_awqos(S_AXI_awqos), 391 | .S_AXI_awready(S_AXI_awready), 392 | .S_AXI_awregion(S_AXI_awregion), 393 | .S_AXI_awsize(S_AXI_awsize), 394 | .S_AXI_awvalid(S_AXI_awvalid), 395 | .S_AXI_bid(S_AXI_bid), 396 | .S_AXI_bready(S_AXI_bready), 397 | .S_AXI_bresp(S_AXI_bresp), 398 | .S_AXI_bvalid(S_AXI_bvalid), 399 | .S_AXI_rdata(S_AXI_rdata), 400 | .S_AXI_rid(S_AXI_rid), 401 | .S_AXI_rlast(S_AXI_rlast), 402 | .S_AXI_rready(S_AXI_rready), 403 | .S_AXI_rresp(S_AXI_rresp), 404 | .S_AXI_rvalid(S_AXI_rvalid), 405 | .S_AXI_wdata(S_AXI_wdata), 406 | .S_AXI_wlast(S_AXI_wlast), 407 | .S_AXI_wready(S_AXI_wready), 408 | .S_AXI_wstrb(S_AXI_wstrb), 409 | .S_AXI_wvalid(S_AXI_wvalid), 410 | .ext_clk_in(ext_clk_in)); 411 | endmodule 412 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_auto_pc_2/system_auto_pc_2.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | system_auto_pc_2 10 | 11 | 12 | AXI4 13 | AXI3 14 | READ_WRITE 15 | 2 16 | 32 17 | 64 18 | 6 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | system_auto_pc_2 25 | zynq 26 | 1 27 | 0 28 | 0 29 | 6 30 | 32 31 | 64 32 | 1 33 | 1 34 | 0 35 | 1 36 | 1 37 | 1 38 | 1 39 | 1 40 | 2 41 | zynq 42 | xc7z010 43 | clg400 44 | -1 45 | C 46 | 47 | VERILOG 48 | MIXED 49 | TRUE 50 | TRUE 51 | /scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myipasdf_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myip_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/lib 52 | 53 | TRUE 54 | 2013.4 55 | 1 56 | OUT_OF_CONTEXT 57 | . 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_auto_pc_5/system_auto_pc_5.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | system_auto_pc_5 10 | 11 | 12 | AXI3 13 | AXI4 14 | READ_WRITE 15 | 2 16 | 32 17 | 32 18 | 12 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | system_auto_pc_5 25 | zynq 26 | 0 27 | 1 28 | 0 29 | 12 30 | 32 31 | 32 32 | 1 33 | 1 34 | 0 35 | 1 36 | 1 37 | 1 38 | 1 39 | 1 40 | 2 41 | zynq 42 | xc7z010 43 | clg400 44 | -1 45 | C 46 | 47 | VERILOG 48 | MIXED 49 | TRUE 50 | TRUE 51 | /scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myipasdf_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myip_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/lib 52 | 53 | TRUE 54 | 2013.4 55 | 1 56 | OUT_OF_CONTEXT 57 | . 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_auto_pc_6/system_auto_pc_6.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | system_auto_pc_6 10 | 11 | 12 | AXI4 13 | AXI3 14 | READ_WRITE 15 | 2 16 | 32 17 | 64 18 | 6 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | system_auto_pc_6 25 | zynq 26 | 1 27 | 0 28 | 0 29 | 6 30 | 32 31 | 64 32 | 1 33 | 1 34 | 0 35 | 1 36 | 1 37 | 1 38 | 1 39 | 1 40 | 2 41 | zynq 42 | xc7z010 43 | clg400 44 | -1 45 | C 46 | 47 | VERILOG 48 | MIXED 49 | TRUE 50 | TRUE 51 | /scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myipasdf_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myip_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/lib 52 | 53 | TRUE 54 | 2013.4 55 | 1 56 | OUT_OF_CONTEXT 57 | . 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_axi_interconnect_0_2/system_axi_interconnect_0_2.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | system_axi_interconnect_0_2 10 | 11 | 12 | 1 13 | 1 14 | 0 15 | 0 16 | 0 17 | 32 18 | 0 19 | 2 20 | 2 21 | 2 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 0 31 | 0 32 | 0 33 | 0 34 | 0 35 | 0 36 | 0 37 | 0 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 0 44 | 0 45 | 0 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 0 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 0 65 | 0 66 | 0 67 | 0 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | 0 74 | 0 75 | 0 76 | 0 77 | 0 78 | 0 79 | 0 80 | 0 81 | 0 82 | 0 83 | 0 84 | 0 85 | 0 86 | 0 87 | 0 88 | 0 89 | 0 90 | 0 91 | 0 92 | 0 93 | 0 94 | 0 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 0 101 | 0 102 | 0 103 | 0 104 | 0 105 | 0 106 | 0 107 | 0 108 | 0 109 | 0 110 | 0 111 | 0 112 | 0 113 | 0 114 | 0 115 | 0 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | 0 128 | 0 129 | 0 130 | 0 131 | 0 132 | 0 133 | 0 134 | 0 135 | 0 136 | 0 137 | 0 138 | 0 139 | 0 140 | 0 141 | 0 142 | 0 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 0 151 | 0 152 | 0 153 | 0 154 | 0 155 | 0 156 | 0 157 | 0 158 | 0 159 | 0 160 | 0 161 | 0 162 | 0 163 | 0 164 | 0 165 | 0 166 | 0 167 | 0 168 | 0 169 | 0 170 | 0 171 | 0 172 | 0 173 | 0 174 | 0 175 | 0 176 | 0 177 | 0 178 | 0 179 | 0 180 | 0 181 | 0 182 | 0 183 | 0 184 | 0 185 | 0 186 | 0 187 | 0 188 | 0 189 | 0 190 | 0 191 | 0 192 | 0 193 | 0 194 | 0 195 | 0 196 | 0 197 | 0 198 | 0 199 | 0 200 | 0 201 | 0 202 | 0 203 | 0 204 | 0 205 | 0 206 | 0 207 | 0 208 | 0 209 | 0 210 | 0 211 | 0 212 | 0 213 | 0 214 | 0 215 | 0 216 | 0 217 | 0 218 | 0 219 | 0 220 | 0 221 | 0 222 | 0 223 | 0 224 | 0 225 | 0 226 | 0 227 | 0 228 | 0 229 | 0 230 | 0 231 | 0 232 | 0 233 | 0 234 | 0 235 | 0 236 | 0 237 | 0 238 | 0 239 | 0 240 | 0 241 | 0 242 | 0 243 | 0 244 | 0 245 | 0 246 | 0 247 | 0 248 | 0 249 | 0 250 | 0 251 | 0 252 | 0 253 | 0 254 | 0 255 | 0 256 | 0 257 | 0 258 | 0 259 | 0 260 | 0 261 | 0 262 | 0 263 | 0 264 | 0 265 | 0 266 | 0 267 | 0 268 | 0 269 | 0 270 | 0 271 | 0 272 | 0 273 | 0 274 | 0 275 | 0 276 | 0 277 | 0 278 | 0 279 | 0 280 | 0 281 | 0 282 | 0 283 | 0 284 | 0 285 | 0 286 | 0 287 | 0 288 | 0 289 | 0 290 | 0 291 | 0 292 | 0 293 | 0 294 | 0 295 | 0 296 | 0 297 | 0 298 | 0 299 | 0 300 | 0 301 | 0 302 | 0 303 | 0 304 | 0 305 | 0 306 | 0 307 | 0 308 | 0 309 | 0 310 | system_axi_interconnect_0_2 311 | zynq 312 | xc7z010 313 | clg400 314 | -1 315 | C 316 | 317 | VERILOG 318 | MIXED 319 | TRUE 320 | TRUE 321 | /scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myipasdf_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myip_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/lib 322 | 323 | TRUE 324 | 2013.4 325 | 1 326 | GLOBAL 327 | . 328 | 329 | 330 | 331 | 332 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_axi_interconnect_1_3/system_axi_interconnect_1_3.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | system_axi_interconnect_1_3 10 | 11 | 12 | 1 13 | 1 14 | 0 15 | 0 16 | 0 17 | 32 18 | 0 19 | 2 20 | 2 21 | 2 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 0 31 | 0 32 | 0 33 | 0 34 | 0 35 | 0 36 | 0 37 | 0 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 0 44 | 0 45 | 0 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 0 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 0 65 | 0 66 | 0 67 | 0 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | 0 74 | 0 75 | 0 76 | 0 77 | 0 78 | 0 79 | 0 80 | 0 81 | 0 82 | 0 83 | 0 84 | 0 85 | 0 86 | 0 87 | 0 88 | 0 89 | 0 90 | 0 91 | 0 92 | 0 93 | 0 94 | 0 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 0 101 | 0 102 | 0 103 | 0 104 | 0 105 | 0 106 | 0 107 | 0 108 | 0 109 | 0 110 | 0 111 | 0 112 | 0 113 | 0 114 | 0 115 | 0 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | 0 128 | 0 129 | 0 130 | 0 131 | 0 132 | 0 133 | 0 134 | 0 135 | 0 136 | 0 137 | 0 138 | 0 139 | 0 140 | 0 141 | 0 142 | 0 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 0 151 | 0 152 | 0 153 | 0 154 | 0 155 | 0 156 | 0 157 | 0 158 | 0 159 | 0 160 | 0 161 | 0 162 | 0 163 | 0 164 | 0 165 | 0 166 | 0 167 | 0 168 | 0 169 | 0 170 | 0 171 | 0 172 | 0 173 | 0 174 | 0 175 | 0 176 | 0 177 | 0 178 | 0 179 | 0 180 | 0 181 | 0 182 | 0 183 | 0 184 | 0 185 | 0 186 | 0 187 | 0 188 | 0 189 | 0 190 | 0 191 | 0 192 | 0 193 | 0 194 | 0 195 | 0 196 | 0 197 | 0 198 | 0 199 | 0 200 | 0 201 | 0 202 | 0 203 | 0 204 | 0 205 | 0 206 | 0 207 | 0 208 | 0 209 | 0 210 | 0 211 | 0 212 | 0 213 | 0 214 | 0 215 | 0 216 | 0 217 | 0 218 | 0 219 | 0 220 | 0 221 | 0 222 | 0 223 | 0 224 | 0 225 | 0 226 | 0 227 | 0 228 | 0 229 | 0 230 | 0 231 | 0 232 | 0 233 | 0 234 | 0 235 | 0 236 | 0 237 | 0 238 | 0 239 | 0 240 | 0 241 | 0 242 | 0 243 | 0 244 | 0 245 | 0 246 | 0 247 | 0 248 | 0 249 | 0 250 | 0 251 | 0 252 | 0 253 | 0 254 | 0 255 | 0 256 | 0 257 | 0 258 | 0 259 | 0 260 | 0 261 | 0 262 | 0 263 | 0 264 | 0 265 | 0 266 | 0 267 | 0 268 | 0 269 | 0 270 | 0 271 | 0 272 | 0 273 | 0 274 | 0 275 | 0 276 | 0 277 | 0 278 | 0 279 | 0 280 | 0 281 | 0 282 | 0 283 | 0 284 | 0 285 | 0 286 | 0 287 | 0 288 | 0 289 | 0 290 | 0 291 | 0 292 | 0 293 | 0 294 | 0 295 | 0 296 | 0 297 | 0 298 | 0 299 | 0 300 | 0 301 | 0 302 | 0 303 | 0 304 | 0 305 | 0 306 | 0 307 | 0 308 | 0 309 | 0 310 | system_axi_interconnect_1_3 311 | zynq 312 | xc7z010 313 | clg400 314 | -1 315 | C 316 | 317 | VERILOG 318 | MIXED 319 | TRUE 320 | TRUE 321 | /scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myipasdf_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myip_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/lib 322 | 323 | TRUE 324 | 2013.4 325 | 1 326 | GLOBAL 327 | . 328 | 329 | 330 | 331 | 332 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_proc_sys_reset_0_1/system_proc_sys_reset_0_1.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | system_proc_sys_reset_0_1 10 | 11 | 12 | 1 13 | 1 14 | 1 15 | 1 16 | 0 17 | 0 18 | 4 19 | 4 20 | system_proc_sys_reset_0_1 21 | false 22 | Custom 23 | zynq 24 | 4 25 | 4 26 | 0 27 | 0 28 | 1 29 | 1 30 | 1 31 | 1 32 | zynq 33 | xc7z010 34 | clg400 35 | -1 36 | C 37 | 38 | VERILOG 39 | MIXED 40 | TRUE 41 | TRUE 42 | /scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myipasdf_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/myip_1.0;/scratch/skarandikar/zybo_test_system2/zybo_base_systemMOD/source/vivado/hw/lib 43 | 44 | TRUE 45 | 2013.4 46 | 3 47 | OUT_OF_CONTEXT 48 | . 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /hw/src/bd/system/ip/system_proc_sys_reset_0_1/system_proc_sys_reset_0_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | customized_ip 5 | system_proc_sys_reset_0_1 6 | 1.0 7 | 8 | 9 | clock 10 | Clock 11 | 12 | 13 | 14 | 15 | 16 | 17 | CLK 18 | 19 | 20 | slowest_sync_clk 21 | 22 | 23 | 24 | 25 | 26 | ASSOCIATED_RESET 27 | mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset 28 | 29 | 30 | 31 | 32 | ext_reset 33 | Ext_Reset 34 | 35 | 36 | 37 | 38 | 39 | 40 | RST 41 | 42 | 43 | ext_reset_in 44 | 45 | 46 | 47 | 48 | 49 | BOARD.ASSOCIATED_PARAM 50 | RESET_BOARD_INTERFACE 51 | 52 | 53 | 54 | required 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | aux_reset 63 | aux_reset 64 | 65 | 66 | 67 | 68 | 69 | 70 | RST 71 | 72 | 73 | aux_reset_in 74 | 75 | 76 | 77 | 78 | 79 | dbg_reset 80 | DBG_Reset 81 | 82 | 83 | 84 | 85 | 86 | 87 | RST 88 | 89 | 90 | mb_debug_sys_rst 91 | 92 | 93 | 94 | 95 | 96 | POLARITY 97 | ACTIVE_HIGH 98 | 99 | 100 | 101 | 102 | mb_rst 103 | MB_rst 104 | 105 | 106 | 107 | 108 | 109 | 110 | RST 111 | 112 | 113 | mb_reset 114 | 115 | 116 | 117 | 118 | 119 | POLARITY 120 | ACTIVE_HIGH 121 | 122 | 123 | TYPE 124 | PROCESSOR 125 | 126 | 127 | 128 | 129 | bus_struct_reset 130 | bus_struct_reset 131 | 132 | 133 | 134 | 135 | 136 | 137 | RST 138 | 139 | 140 | bus_struct_reset 141 | 142 | 143 | 144 | 145 | 146 | POLARITY 147 | ACTIVE_HIGH 148 | 149 | 150 | TYPE 151 | INTERCONNECT 152 | 153 | 154 | 155 | 156 | interconnect_low_rst 157 | interconnect_low_rst 158 | 159 | 160 | 161 | 162 | 163 | 164 | RST 165 | 166 | 167 | interconnect_aresetn 168 | 169 | 170 | 171 | 172 | 173 | POLARITY 174 | ACTIVE_LOW 175 | 176 | 177 | TYPE 178 | INTERCONNECT 179 | 180 | 181 | 182 | 183 | peripheral_high_rst 184 | peripheral_high_rst 185 | 186 | 187 | 188 | 189 | 190 | 191 | RST 192 | 193 | 194 | peripheral_reset 195 | 196 | 197 | 198 | 199 | 200 | POLARITY 201 | ACTIVE_HIGH 202 | 203 | 204 | TYPE 205 | PERIPHERAL 206 | 207 | 208 | 209 | 210 | peripheral_low_rst 211 | peripheral_low_rst 212 | 213 | 214 | 215 | 216 | 217 | 218 | RST 219 | 220 | 221 | peripheral_aresetn 222 | 223 | 224 | 225 | 226 | 227 | POLARITY 228 | ACTIVE_LOW 229 | 230 | 231 | TYPE 232 | PERIPHERAL 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | slowest_sync_clk 241 | 242 | in 243 | 244 | 245 | std_logic 246 | dummy_view 247 | 248 | 249 | 250 | 251 | 252 | 253 | true 254 | 255 | 256 | 257 | 258 | 259 | ext_reset_in 260 | 261 | in 262 | 263 | 264 | std_logic 265 | dummy_view 266 | 267 | 268 | 269 | 270 | 271 | 272 | true 273 | 274 | 275 | 276 | 277 | 278 | aux_reset_in 279 | 280 | in 281 | 282 | 283 | std_logic 284 | dummy_view 285 | 286 | 287 | 288 | 1 289 | 290 | 291 | 292 | 293 | 294 | true 295 | 296 | 297 | 298 | 299 | 300 | mb_debug_sys_rst 301 | 302 | in 303 | 304 | 305 | std_logic 306 | dummy_view 307 | 308 | 309 | 310 | 0 311 | 312 | 313 | 314 | 315 | 316 | true 317 | 318 | 319 | 320 | 321 | 322 | dcm_locked 323 | 324 | in 325 | 326 | 327 | std_logic 328 | dummy_view 329 | 330 | 331 | 332 | 0x1 333 | 334 | 335 | 336 | 337 | mb_reset 338 | 339 | out 340 | 341 | 342 | std_logic 343 | dummy_view 344 | 345 | 346 | 347 | 0x0 348 | 349 | 350 | 351 | 352 | 353 | true 354 | 355 | 356 | 357 | 358 | 359 | bus_struct_reset 360 | 361 | out 362 | 363 | 0 364 | 0 365 | 366 | 367 | 368 | std_logic_vector 369 | dummy_view 370 | 371 | 372 | 373 | 0 374 | 375 | 376 | 377 | 378 | 379 | true 380 | 381 | 382 | 383 | 384 | 385 | peripheral_reset 386 | 387 | out 388 | 389 | 0 390 | 0 391 | 392 | 393 | 394 | std_logic_vector 395 | dummy_view 396 | 397 | 398 | 399 | 0 400 | 401 | 402 | 403 | 404 | 405 | true 406 | 407 | 408 | 409 | 410 | 411 | interconnect_aresetn 412 | 413 | out 414 | 415 | 0 416 | 0 417 | 418 | 419 | 420 | std_logic_vector 421 | dummy_view 422 | 423 | 424 | 425 | 1 426 | 427 | 428 | 429 | 430 | 431 | true 432 | 433 | 434 | 435 | 436 | 437 | peripheral_aresetn 438 | 439 | out 440 | 441 | 0 442 | 0 443 | 444 | 445 | 446 | std_logic_vector 447 | dummy_view 448 | 449 | 450 | 451 | 1 452 | 453 | 454 | 455 | 456 | 457 | true 458 | 459 | 460 | 461 | 462 | 463 | 464 | 465 | C_FAMILY 466 | zynq 467 | 468 | 469 | C_EXT_RST_WIDTH 470 | Ext Rst Width 471 | 4 472 | 473 | 474 | C_AUX_RST_WIDTH 475 | Aux Rst Width 476 | 4 477 | 478 | 479 | C_EXT_RESET_HIGH 480 | Ext Reset High 481 | 0 482 | 483 | 484 | C_AUX_RESET_HIGH 485 | Aux Reset High 486 | 0 487 | 488 | 489 | C_NUM_BUS_RST 490 | No. of Bus Reset (Active High) 491 | 1 492 | 493 | 494 | C_NUM_PERP_RST 495 | No. of Peripheral Reset (Active High) 496 | 1 497 | 498 | 499 | C_NUM_INTERCONNECT_ARESETN 500 | No. of Interconnect Reset (Active Low) 501 | 1 502 | 503 | 504 | C_NUM_PERP_ARESETN 505 | No. of Peripheral Reset (Active Low) 506 | 1 507 | 508 | 509 | 510 | 511 | 512 | choices_0 513 | 0 514 | 1 515 | 516 | 517 | choices_1 518 | 0 519 | 1 520 | 521 | 522 | choices_2 523 | Custom 524 | 525 | 526 | Processor Reset System 527 | 528 | 529 | C_NUM_PERP_ARESETN 530 | No. of Peripheral Reset (Active Low) 531 | 1 532 | 533 | 534 | C_NUM_INTERCONNECT_ARESETN 535 | No. of Interconnect Reset (Active Low) 536 | 1 537 | 538 | 539 | C_NUM_PERP_RST 540 | No. of Peripheral Reset (Active High) 541 | 1 542 | 543 | 544 | C_NUM_BUS_RST 545 | No. of Bus Reset (Active High) 546 | 1 547 | 548 | 549 | C_AUX_RESET_HIGH 550 | Aux Reset High 551 | 0 552 | 553 | 554 | C_EXT_RESET_HIGH 555 | Ext Reset High 556 | 0 557 | 558 | 559 | C_AUX_RST_WIDTH 560 | Aux Rst Width 561 | 4 562 | 563 | 564 | C_EXT_RST_WIDTH 565 | Ext Rst Width 566 | 4 567 | 568 | 569 | Component_Name 570 | system_proc_sys_reset_0_1 571 | 572 | 573 | USE_BOARD_FLOW 574 | Generate Board based IO Constraints 575 | false 576 | 577 | 578 | RESET_BOARD_INTERFACE 579 | Custom 580 | 581 | 582 | 583 | 584 | 585 | artix7 586 | artix7l 587 | aartix7 588 | qartix7 589 | kintex7 590 | kintex7l 591 | qkintex7 592 | qkintex7l 593 | virtex7 594 | qvirtex7 595 | zynq 596 | qzynq 597 | azynq 598 | virtex8 599 | kintex8 600 | 601 | 602 | /Embedded_Processing/Clock_&_Reset 603 | 604 | Processor System Reset 605 | http://www.xilinx.com 606 | 3 607 | 608 | xilinx.com:ip:proc_sys_reset:4.00.a 609 | 610 | 2013-12-02T19:25:24Z 611 | 612 | 613 | 2013.4 614 | 615 | 616 | 617 | -------------------------------------------------------------------------------- /hw/src/bd/system/system.bxml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Composite Fileset 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | -------------------------------------------------------------------------------- /hw/src/bd/system/system_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | #create_clock -name clock_name -period 10 [get_ports clock_name] 10 | ################################################################################ 11 | create_clock -name ext_clk_in -period 40 [get_ports ext_clk_in] 12 | create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0] 13 | 14 | ################################################################################ -------------------------------------------------------------------------------- /hw/src/bd/system/ui/bd_c954508f.ui: -------------------------------------------------------------------------------- 1 | { 2 | guistr: "# # String gsaved with Nlview version 6.3.3 2013-08-16 bk=1.2871 VDI=33 GEI=35 3 | # -string -flagsOSRD 4 | preplace port DDR -pg 1 -y 60 -defaultsOSRD 5 | preplace port FCLK_RESET0_N -pg 1 -y 320 -defaultsOSRD 6 | preplace port S_AXI -pg 1 -y 50 -defaultsOSRD 7 | preplace port M_AXI -pg 1 -y 200 -defaultsOSRD 8 | preplace port FIXED_IO -pg 1 -y 80 -defaultsOSRD 9 | preplace port ext_clk_in -pg 1 -y 230 -defaultsOSRD 10 | preplace inst proc_sys_reset_0 -pg 1 -lvl 1 -y 330 -defaultsOSRD 11 | preplace inst axi_interconnect_0 -pg 1 -lvl 4 -y 200 -defaultsOSRD 12 | preplace inst axi_interconnect_1 -pg 1 -lvl 2 -y 110 -defaultsOSRD 13 | preplace inst processing_system7_0 -pg 1 -lvl 3 -y 120 -defaultsOSRD 14 | preplace netloc S_AXI_1 1 0 2 NJ 50 N 15 | preplace netloc processing_system7_0_DDR 1 3 2 N 60 NJ 16 | preplace netloc processing_system7_0_M_AXI_GP0 1 3 1 N 17 | preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 5 140 240 NJ 250 NJ 250 1170 320 NJ 18 | preplace netloc proc_sys_reset_0_interconnect_aresetn 1 1 3 480 260 NJ 260 1180 19 | preplace netloc processing_system7_0_FIXED_IO 1 3 2 N 80 NJ 20 | preplace netloc axi_interconnect_0_M00_AXI 1 4 1 N 21 | preplace netloc proc_sys_reset_0_peripheral_aresetn 1 1 3 500 270 NJ 270 1200 22 | preplace netloc axi_interconnect_1_M00_AXI 1 2 1 N 23 | preplace netloc ext_clk_in_1 1 0 4 130 230 490 230 740 240 1190 24 | levelinfo -pg 1 110 310 620 960 1320 1470 25 | ", 26 | } 27 | { 28 | da_axi4_cnt: "2", 29 | } -------------------------------------------------------------------------------- /hw/src/constrs/base.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN L16 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk] 4 | -------------------------------------------------------------------------------- /hw/src/verilog/fifos.v: -------------------------------------------------------------------------------- 1 | // fifo queues 2 | 3 | module fifo_8x5 ( 4 | input clk, 5 | input reset, 6 | input wren, 7 | input rden, 8 | input [4:0] din, 9 | output reg empty, 10 | output reg full, 11 | output [4:0] dout 12 | ); 13 | 14 | reg [4:0] data [0:7]; 15 | reg [2:0] raddr, waddr; 16 | wire [2:0] waddr_next, raddr_next; 17 | wire write = wren && (rden || !full); 18 | wire read = rden && !empty; 19 | 20 | assign waddr_next = write ? waddr + 1'b1 : waddr; 21 | assign raddr_next = read ? raddr + 1'b1 : raddr; 22 | assign dout = data[raddr]; 23 | 24 | always @(posedge clk) 25 | begin 26 | if (reset) 27 | begin 28 | empty <= 1'b1; 29 | full <= 1'b0; 30 | raddr <= 3'd0; 31 | waddr <= 3'd0; 32 | end 33 | else 34 | begin 35 | waddr <= waddr_next; 36 | raddr <= raddr_next; 37 | if (write) 38 | data[waddr] <= din; 39 | 40 | if (read && raddr_next == waddr_next && !full) 41 | empty <= 1'b1; 42 | else if (write && !read) 43 | empty <= 1'b0; 44 | 45 | if (write && raddr_next == waddr_next) 46 | full <= 1'b1; 47 | else if (read && !write) 48 | full <= 1'b0; 49 | 50 | end 51 | end 52 | endmodule 53 | 54 | module fifo_32x32 ( 55 | input clk, 56 | input reset, 57 | input wren, 58 | input rden, 59 | input [31:0] din, 60 | output reg empty, 61 | output reg full, 62 | output [31:0] dout, 63 | output [4:0] count 64 | ); 65 | 66 | reg [31:0] data [0:31]; 67 | reg [4:0] raddr, waddr, cnt; 68 | wire [4:0] waddr_next, raddr_next; 69 | wire write = wren && (rden || !full); 70 | wire read = rden && !empty; 71 | 72 | assign waddr_next = write ? waddr + 1'b1 : waddr; 73 | assign raddr_next = read ? raddr + 1'b1 : raddr; 74 | assign dout = data[raddr]; 75 | assign count = cnt; 76 | 77 | always @(posedge clk) 78 | begin 79 | if (reset) 80 | begin 81 | empty <= 1'b1; 82 | full <= 1'b0; 83 | raddr <= 5'd0; 84 | waddr <= 5'd0; 85 | cnt <= 5'd0; 86 | end 87 | else 88 | begin 89 | waddr <= waddr_next; 90 | raddr <= raddr_next; 91 | if (write) 92 | data[waddr] <= din; 93 | 94 | if (read && raddr_next == waddr_next && !full) 95 | empty <= 1'b1; 96 | else if (write && !read) 97 | empty <= 1'b0; 98 | 99 | if (write && raddr_next == waddr_next) 100 | full <= 1'b1; 101 | else if (read && !write) 102 | full <= 1'b0; 103 | 104 | if (write ^ read) 105 | cnt <= write ? cnt + 1 : cnt - 1; 106 | 107 | end 108 | end 109 | endmodule 110 | -------------------------------------------------------------------------------- /hw/src/verilog/system_wrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | 3 | module system_wrapper 4 | (DDR_addr, 5 | DDR_ba, 6 | DDR_cas_n, 7 | DDR_ck_n, 8 | DDR_ck_p, 9 | DDR_cke, 10 | DDR_cs_n, 11 | DDR_dm, 12 | DDR_dq, 13 | DDR_dqs_n, 14 | DDR_dqs_p, 15 | DDR_odt, 16 | DDR_ras_n, 17 | DDR_reset_n, 18 | DDR_we_n, 19 | FIXED_IO_ddr_vrn, 20 | FIXED_IO_ddr_vrp, 21 | FIXED_IO_mio, 22 | FIXED_IO_ps_clk, 23 | FIXED_IO_ps_porb, 24 | FIXED_IO_ps_srstb, 25 | clk); 26 | 27 | inout [14:0]DDR_addr; 28 | inout [2:0]DDR_ba; 29 | inout DDR_cas_n; 30 | inout DDR_ck_n; 31 | inout DDR_ck_p; 32 | inout DDR_cke; 33 | inout DDR_cs_n; 34 | inout [3:0]DDR_dm; 35 | inout [31:0]DDR_dq; 36 | inout [3:0]DDR_dqs_n; 37 | inout [3:0]DDR_dqs_p; 38 | inout DDR_odt; 39 | inout DDR_ras_n; 40 | inout DDR_reset_n; 41 | inout DDR_we_n; 42 | 43 | inout FIXED_IO_ddr_vrn; 44 | inout FIXED_IO_ddr_vrp; 45 | inout [53:0]FIXED_IO_mio; 46 | inout FIXED_IO_ps_clk; 47 | inout FIXED_IO_ps_porb; 48 | inout FIXED_IO_ps_srstb; 49 | input clk; 50 | 51 | wire FCLK_RESET0_N; 52 | 53 | wire [31:0]M_AXI_araddr; 54 | wire [1:0]M_AXI_arburst; 55 | wire [7:0]M_AXI_arlen; 56 | wire M_AXI_arready; 57 | wire [2:0]M_AXI_arsize; 58 | wire M_AXI_arvalid; 59 | wire [31:0]M_AXI_awaddr; 60 | wire [1:0]M_AXI_awburst; 61 | wire [7:0]M_AXI_awlen; 62 | wire [3:0]M_AXI_wstrb; 63 | wire M_AXI_awready; 64 | wire [2:0]M_AXI_awsize; 65 | wire M_AXI_awvalid; 66 | wire M_AXI_bready; 67 | wire M_AXI_bvalid; 68 | wire [31:0]M_AXI_rdata; 69 | wire M_AXI_rlast; 70 | wire M_AXI_rready; 71 | wire M_AXI_rvalid; 72 | wire [31:0]M_AXI_wdata; 73 | wire M_AXI_wlast; 74 | wire M_AXI_wready; 75 | wire M_AXI_wvalid; 76 | wire [11:0] M_AXI_arid, M_AXI_awid; // outputs from ARM core 77 | wire [11:0] M_AXI_bid, M_AXI_rid; // inputs to ARM core 78 | 79 | wire [4:0] raddr, waddr; 80 | reg [4:0] raddr_r, waddr_r; 81 | reg [11:0] arid_r, awid_r; 82 | reg [15:0] host_out_bits_r; 83 | 84 | wire host_in_fifo_full, host_in_fifo_empty, host_in_fifo_rden, host_in_fifo_wren; 85 | wire host_out_fifo_full, host_out_fifo_empty, host_out_fifo_wren, host_out_fifo_rden; 86 | wire [31:0] host_in_fifo_dout, host_out_fifo_dout; 87 | wire [5:0] host_out_fifo_count; 88 | reg host_out_count, host_in_count; 89 | 90 | wire [31:0]S_AXI_addr; 91 | wire S_AXI_arready; 92 | wire S_AXI_arvalid; 93 | wire S_AXI_awready; 94 | wire S_AXI_awvalid; 95 | wire S_AXI_bready; 96 | wire S_AXI_bvalid; 97 | wire [1:0]S_AXI_bresp; 98 | wire [63:0]S_AXI_rdata; 99 | wire S_AXI_rlast; 100 | reg S_AXI_rlast_r; 101 | wire S_AXI_rready; 102 | wire S_AXI_rvalid; 103 | wire [63:0]S_AXI_wdata; 104 | wire S_AXI_wlast; 105 | wire S_AXI_wready; 106 | wire S_AXI_wvalid; 107 | wire [5:0] S_AXI_arid, S_AXI_awid; // inputs to ARM core 108 | wire [5:0] S_AXI_bid, S_AXI_rid; // outputs from ARM core 109 | 110 | wire mem_req_cmd_val, mem_req_cmd_rdy, mem_req_cmd_rw, mem_req_data_val, mem_req_data_rdy; 111 | wire mem_resp_val,mem_resp_rdy; 112 | wire [4:0] mem_req_tag, mem_resp_tag; 113 | wire [25:0] mem_req_addr; 114 | wire [127:0] mem_req_data_bits; 115 | reg [63:0] mem_resp_data_buf; 116 | 117 | wire reset, reset_cpu; 118 | 119 | wire host_in_valid, host_in_ready, host_out_ready, host_out_valid; 120 | wire [15:0] host_in_bits, host_out_bits; 121 | wire host_clk; 122 | wire gclk_i, gclk_fbout, host_clk_i, mmcm_locked; 123 | 124 | system system_i 125 | (.DDR_addr(DDR_addr), 126 | .DDR_ba(DDR_ba), 127 | .DDR_cas_n(DDR_cas_n), 128 | .DDR_ck_n(DDR_ck_n), 129 | .DDR_ck_p(DDR_ck_p), 130 | .DDR_cke(DDR_cke), 131 | .DDR_cs_n(DDR_cs_n), 132 | .DDR_dm(DDR_dm), 133 | .DDR_dq(DDR_dq), 134 | .DDR_dqs_n(DDR_dqs_n), 135 | .DDR_dqs_p(DDR_dqs_p), 136 | .DDR_odt(DDR_odt), 137 | .DDR_ras_n(DDR_ras_n), 138 | .DDR_reset_n(DDR_reset_n), 139 | .DDR_we_n(DDR_we_n), 140 | .FCLK_RESET0_N(FCLK_RESET0_N), 141 | .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), 142 | .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), 143 | .FIXED_IO_mio(FIXED_IO_mio), 144 | .FIXED_IO_ps_clk(FIXED_IO_ps_clk), 145 | .FIXED_IO_ps_porb(FIXED_IO_ps_porb), 146 | .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), 147 | // master AXI interface (zynq = master, fpga = slave) 148 | .M_AXI_araddr(M_AXI_araddr), 149 | .M_AXI_arburst(M_AXI_arburst), // burst type 150 | .M_AXI_arcache(), 151 | .M_AXI_arid(M_AXI_arid), 152 | .M_AXI_arlen(M_AXI_arlen), // burst length (#transfers) 153 | .M_AXI_arlock(), 154 | .M_AXI_arprot(), 155 | .M_AXI_arqos(), 156 | .M_AXI_arready(M_AXI_arready), 157 | .M_AXI_arregion(), 158 | .M_AXI_arsize(M_AXI_arsize), // burst size (bits/transfer) 159 | .M_AXI_arvalid(M_AXI_arvalid), 160 | // 161 | .M_AXI_awaddr(M_AXI_awaddr), 162 | .M_AXI_awburst(M_AXI_awburst), 163 | .M_AXI_awcache(), 164 | .M_AXI_awid(M_AXI_awid), 165 | .M_AXI_awlen(M_AXI_awlen), 166 | .M_AXI_awlock(), 167 | .M_AXI_awprot(), 168 | .M_AXI_awqos(), 169 | .M_AXI_awready(M_AXI_awready), 170 | .M_AXI_awregion(), 171 | .M_AXI_awsize(M_AXI_awsize), 172 | .M_AXI_awvalid(M_AXI_awvalid), 173 | // 174 | .M_AXI_bid(M_AXI_bid), 175 | .M_AXI_bready(M_AXI_bready), 176 | .M_AXI_bresp(2'b00), 177 | .M_AXI_bvalid(M_AXI_bvalid), 178 | // 179 | .M_AXI_rdata(M_AXI_rdata), 180 | .M_AXI_rid(M_AXI_rid), 181 | .M_AXI_rlast(M_AXI_rlast), 182 | .M_AXI_rready(M_AXI_rready), 183 | .M_AXI_rresp(), 184 | .M_AXI_rvalid(M_AXI_rvalid), 185 | // 186 | .M_AXI_wdata(M_AXI_wdata), 187 | .M_AXI_wlast(M_AXI_wlast), 188 | .M_AXI_wready(M_AXI_wready), 189 | .M_AXI_wstrb(M_AXI_wstrb), 190 | .M_AXI_wvalid(M_AXI_wvalid), 191 | // slave AXI interface (fpga = master, zynq = slave) 192 | // connected directly to DDR controller to handle test chip mem 193 | .S_AXI_araddr(S_AXI_addr), 194 | .S_AXI_arburst(2'b01), // type INCR 195 | .S_AXI_arcache(4'b0011), 196 | .S_AXI_arid(S_AXI_arid), 197 | .S_AXI_arlen(8'd7), // burst length = 8 transfers 198 | .S_AXI_arlock(1'b0), 199 | .S_AXI_arprot(3'b000), 200 | .S_AXI_arqos(4'b0000), 201 | .S_AXI_arready(S_AXI_arready), 202 | .S_AXI_arregion(4'b0000), 203 | .S_AXI_arsize(3'b011), // burst size = 64 bits/beat 204 | .S_AXI_arvalid(S_AXI_arvalid), 205 | // 206 | .S_AXI_awaddr(S_AXI_addr), 207 | .S_AXI_awburst(2'b01), 208 | .S_AXI_awcache(4'b0011), 209 | .S_AXI_awid(S_AXI_awid), 210 | .S_AXI_awlen(8'd7), // burst length = 8 transfers 211 | .S_AXI_awlock(1'b0), 212 | .S_AXI_awprot(3'b000), 213 | .S_AXI_awqos(4'b0000), 214 | .S_AXI_awready(S_AXI_awready), 215 | .S_AXI_awregion(4'b0000), 216 | .S_AXI_awsize(3'b011), 217 | .S_AXI_awvalid(S_AXI_awvalid), 218 | // 219 | .S_AXI_bid(S_AXI_bid), 220 | .S_AXI_bready(S_AXI_bready), 221 | .S_AXI_bresp(), 222 | .S_AXI_bvalid(S_AXI_bvalid), 223 | // 224 | .S_AXI_rid(S_AXI_rid), 225 | .S_AXI_rdata(S_AXI_rdata), 226 | .S_AXI_rlast(S_AXI_rlast), 227 | .S_AXI_rready(S_AXI_rready), 228 | .S_AXI_rresp(), 229 | .S_AXI_rvalid(S_AXI_rvalid), 230 | // 231 | .S_AXI_wdata(S_AXI_wdata), 232 | .S_AXI_wlast(S_AXI_wlast), 233 | .S_AXI_wready(S_AXI_wready), 234 | .S_AXI_wstrb(8'hff), 235 | .S_AXI_wvalid(S_AXI_wvalid), 236 | .ext_clk_in(host_clk) 237 | ); 238 | 239 | `define DCOUNT_ADDR 5'h00 240 | `define RFIFO_ADDR 5'h01 241 | 242 | `define WFIFO_ADDR 5'h00 243 | `define RESET_ADDR 5'h1f 244 | 245 | // HTIF interface between ARM and reference chip on FPGA via memory mapped registers 246 | // 2 read addresses : 1 for FIFO data count (0x0), 1 for FIFO data (0x1) 247 | // 2 write addresses: 1 for FIFO data (0x0), 1 for reset (0x31) 248 | 249 | // host_in (from ARM to fpga) 250 | 251 | assign waddr = M_AXI_awaddr[6:2]; 252 | assign raddr = M_AXI_araddr[6:2]; 253 | 254 | fifo_32x32 host_in_fifo ( 255 | .clk(host_clk), 256 | .reset(reset), 257 | .din(M_AXI_wdata), 258 | .wren(host_in_fifo_wren), 259 | .rden(host_in_fifo_rden), 260 | .dout(host_in_fifo_dout), 261 | .full(host_in_fifo_full), 262 | .empty(host_in_fifo_empty), 263 | .count() 264 | ); 265 | 266 | assign host_in_valid = !host_in_fifo_empty; 267 | assign host_in_fifo_rden = host_in_count && host_in_valid && host_in_ready; 268 | assign host_in_bits = !host_in_count ? host_in_fifo_dout[15:0] : host_in_fifo_dout[31:16]; 269 | 270 | // host_out (from FPGA to ARM) 271 | 272 | assign host_out_ready = !host_out_fifo_full; 273 | assign host_out_fifo_wren = (host_out_count == 1'b1); 274 | assign host_out_fifo_rden = M_AXI_rvalid && M_AXI_rready && (raddr_r == `RFIFO_ADDR); 275 | 276 | fifo_32x32 host_out_fifo ( 277 | .clk(host_clk), 278 | .reset(reset), 279 | .din({host_out_bits, host_out_bits_r}), 280 | .wren(host_out_fifo_wren), 281 | .rden(host_out_fifo_rden), 282 | .dout(host_out_fifo_dout), 283 | .full(host_out_fifo_full), 284 | .empty(host_out_fifo_empty), 285 | .count(host_out_fifo_count) 286 | ); 287 | 288 | assign reset = !FCLK_RESET0_N || !mmcm_locked; 289 | 290 | parameter st_rd_idle = 1'b0; 291 | parameter st_rd_read = 1'b1; 292 | 293 | reg st_rd = st_rd_idle; 294 | 295 | parameter st_wr_idle = 2'd0; 296 | parameter st_wr_write = 2'd1; 297 | parameter st_wr_ack = 2'd2; 298 | 299 | reg [1:0] st_wr = st_wr_idle; 300 | 301 | always @(posedge host_clk) 302 | begin 303 | 304 | if (reset) 305 | begin 306 | host_out_bits_r <= 16'd0; 307 | host_out_count <= 1'd0; 308 | host_in_count <= 1'd0; 309 | raddr_r <= 5'd0; 310 | waddr_r <= 5'd0; 311 | arid_r <= 12'd0; 312 | awid_r <= 12'd0; 313 | st_rd <= st_rd_idle; 314 | st_wr <= st_wr_idle; 315 | end 316 | else 317 | begin 318 | if (host_out_valid) 319 | begin 320 | host_out_bits_r <= host_out_bits; 321 | host_out_count <= host_out_count + 1; 322 | end 323 | if (host_in_valid && host_in_ready) 324 | host_in_count <= host_in_count + 1; 325 | 326 | // state machine to handle reads from AXI master (ARM) 327 | case (st_rd) 328 | st_rd_idle : begin 329 | if (M_AXI_arvalid) 330 | begin 331 | st_rd <= st_rd_read; 332 | raddr_r <= raddr; 333 | arid_r <= M_AXI_arid; 334 | end 335 | end 336 | st_rd_read : begin 337 | if (M_AXI_rready) 338 | st_rd <= st_rd_idle; 339 | end 340 | endcase 341 | 342 | // state machine to handle writes from AXI master 343 | case (st_wr) 344 | st_wr_idle : begin 345 | if (M_AXI_awvalid && M_AXI_wvalid) 346 | begin 347 | st_wr <= st_wr_write; 348 | waddr_r <= waddr; 349 | awid_r <= M_AXI_awid; 350 | end 351 | end 352 | st_wr_write : begin 353 | if (!host_in_fifo_full || (waddr_r == `RESET_ADDR)) 354 | st_wr <= st_wr_ack; 355 | end 356 | st_wr_ack : begin 357 | if (M_AXI_bready) 358 | st_wr <= st_wr_idle; 359 | end 360 | endcase 361 | 362 | end 363 | end 364 | 365 | assign M_AXI_arready = (st_rd == st_rd_idle); 366 | assign M_AXI_rvalid = (st_rd == st_rd_read); 367 | assign M_AXI_rlast = (st_rd == st_rd_read); 368 | assign M_AXI_rdata = (raddr_r == `DCOUNT_ADDR) ? {26'd0, host_out_fifo_count} : host_out_fifo_dout; 369 | assign M_AXI_rid = arid_r; 370 | 371 | wire do_write = (st_wr == st_wr_write); 372 | assign M_AXI_awready = do_write; 373 | assign M_AXI_wready = do_write; 374 | assign host_in_fifo_wren = do_write && (waddr_r == `WFIFO_ADDR); 375 | assign reset_cpu = do_write && (waddr_r == `RESET_ADDR); 376 | 377 | assign M_AXI_bvalid = (st_wr == st_wr_ack); 378 | assign M_AXI_bid = awid_r; 379 | 380 | // interface between test chip mem interface and zynq DDR via HP0 AXI port 381 | parameter st_IDLE = 2'b00; 382 | parameter st_READ = 2'b01; 383 | parameter st_START_WRITE = 2'b10; 384 | parameter st_WRITE = 2'b11; 385 | // parameter st_WRITE_ACK = 3'b100; 386 | 387 | reg [1:0] state_r = st_IDLE; // for poweron global set/reset 388 | reg [2:0] write_count = 3'd0; 389 | reg read_count = 1'b0; 390 | 391 | always @(posedge host_clk) 392 | begin 393 | if (reset) 394 | begin 395 | state_r <= st_IDLE; 396 | write_count <= 3'd0; 397 | read_count <= 1'b0; 398 | mem_resp_data_buf <= 64'd0; 399 | S_AXI_rlast_r <= 1'b0; 400 | end 401 | else 402 | S_AXI_rlast_r <= S_AXI_rlast && S_AXI_rvalid; 403 | if (S_AXI_rvalid) 404 | begin 405 | read_count <= read_count + 1; 406 | mem_resp_data_buf <= S_AXI_rdata; 407 | end 408 | 409 | case (state_r) 410 | st_IDLE : begin 411 | if (mem_req_cmd_val && !mem_req_cmd_rw) 412 | state_r <= st_READ; 413 | else if (mem_req_cmd_val && mem_req_cmd_rw && mem_req_data_val) 414 | state_r <= st_START_WRITE; 415 | end 416 | st_READ : begin 417 | if (S_AXI_arready) 418 | state_r <= st_IDLE; 419 | end 420 | st_START_WRITE : begin 421 | if (S_AXI_awready) 422 | state_r <= st_WRITE; 423 | end 424 | st_WRITE : begin 425 | if (S_AXI_wready && mem_req_data_val) 426 | begin 427 | write_count <= write_count + 1; 428 | if (write_count == 3'd7) 429 | // state_r <= st_WRITE_ACK; 430 | state_r <= st_IDLE; 431 | end 432 | end 433 | // st_WRITE_ACK : begin 434 | // if (S_AXI_bvalid) 435 | // state_r <= st_IDLE; 436 | // end 437 | // default : begin // Fault Recovery 438 | // <= ; 439 | // end 440 | endcase 441 | end 442 | 443 | assign S_AXI_awvalid = (state_r == st_START_WRITE); 444 | assign S_AXI_arvalid = (state_r == st_READ); 445 | assign mem_req_cmd_rdy = ((state_r == st_START_WRITE) && S_AXI_awready) || ((state_r == st_READ) && S_AXI_arready); 446 | assign S_AXI_wvalid = (state_r == st_WRITE) && mem_req_data_val; 447 | assign S_AXI_wlast = (state_r == st_WRITE) && (write_count == 3'd7); 448 | 449 | assign S_AXI_rready = 1'b1; 450 | assign mem_resp_val = read_count; // FIXME: assuming mem_resp_rdy is always 1 (i think its OK) 451 | 452 | assign mem_req_data_rdy = (state_r == st_WRITE) && write_count[0] && S_AXI_wready; 453 | assign S_AXI_addr = {4'h1, mem_req_addr[21:0], 6'd0}; 454 | assign S_AXI_wdata = write_count[0] ? mem_req_data_bits[127:64] : mem_req_data_bits[63:0]; 455 | assign S_AXI_bready = 1'b1; //(state_r == st_WRITE_ACK); 456 | 457 | /* 458 | fifo_8x5 tag_queue ( 459 | .clk(host_clk), 460 | .reset(reset), 461 | .din(mem_req_tag), 462 | .wren(S_AXI_arvalid & S_AXI_arready), 463 | .rden(S_AXI_rlast_r), 464 | .dout(mem_resp_tag), 465 | .full(), 466 | .empty() 467 | ); 468 | */ 469 | 470 | assign S_AXI_arid = {1'b0, mem_req_tag}; 471 | assign S_AXI_awid = 6'd0; 472 | assign mem_resp_tag = S_AXI_rid[4:0]; 473 | 474 | FPGATop top( 475 | .clk(host_clk), 476 | .reset(reset_cpu), 477 | //.io_host_clk( ) 478 | //.io_host_clk_edge( ) 479 | .io_host_in_ready( host_in_ready ), 480 | .io_host_in_valid( host_in_valid ), 481 | .io_host_in_bits( host_in_bits ), 482 | .io_host_out_ready( host_out_ready ), 483 | .io_host_out_valid( host_out_valid ), 484 | .io_host_out_bits( host_out_bits ), 485 | //.io_host_debug_stats_pcr( ) 486 | .io_mem_req_cmd_ready( mem_req_cmd_rdy ), 487 | .io_mem_req_cmd_valid( mem_req_cmd_val ), 488 | .io_mem_req_cmd_bits_addr( mem_req_addr ), 489 | .io_mem_req_cmd_bits_tag( mem_req_tag ), 490 | .io_mem_req_cmd_bits_rw( mem_req_cmd_rw ), 491 | .io_mem_req_data_ready( mem_req_data_rdy ), 492 | .io_mem_req_data_valid( mem_req_data_val ), 493 | .io_mem_req_data_bits_data( mem_req_data_bits ), 494 | .io_mem_resp_ready( mem_resp_rdy ), 495 | .io_mem_resp_valid( mem_resp_val ), 496 | .io_mem_resp_bits_data( {S_AXI_rdata, mem_resp_data_buf} ), 497 | .io_mem_resp_bits_tag( mem_resp_tag ) 498 | ); 499 | 500 | IBUFG ibufg_gclk (.I(clk), .O(gclk_i)); 501 | BUFG bufg_host_clk (.I(host_clk_i), .O(host_clk)); 502 | 503 | MMCME2_BASE #( 504 | .BANDWIDTH("OPTIMIZED"), 505 | .CLKFBOUT_MULT_F(8.0), 506 | .CLKFBOUT_PHASE(0.0), 507 | .CLKIN1_PERIOD(8.0), 508 | .CLKOUT1_DIVIDE(1), 509 | .CLKOUT2_DIVIDE(1), 510 | .CLKOUT3_DIVIDE(1), 511 | .CLKOUT4_DIVIDE(1), 512 | .CLKOUT5_DIVIDE(1), 513 | .CLKOUT6_DIVIDE(1), 514 | .CLKOUT0_DIVIDE_F(40.0), 515 | .CLKOUT0_DUTY_CYCLE(0.5), 516 | .CLKOUT1_DUTY_CYCLE(0.5), 517 | .CLKOUT2_DUTY_CYCLE(0.5), 518 | .CLKOUT3_DUTY_CYCLE(0.5), 519 | .CLKOUT4_DUTY_CYCLE(0.5), 520 | .CLKOUT5_DUTY_CYCLE(0.5), 521 | .CLKOUT6_DUTY_CYCLE(0.5), 522 | .CLKOUT0_PHASE(0.0), 523 | .CLKOUT1_PHASE(0.0), 524 | .CLKOUT2_PHASE(0.0), 525 | .CLKOUT3_PHASE(0.0), 526 | .CLKOUT4_PHASE(0.0), 527 | .CLKOUT5_PHASE(0.0), 528 | .CLKOUT6_PHASE(0.0), 529 | .CLKOUT4_CASCADE("FALSE"), 530 | .DIVCLK_DIVIDE(1), 531 | .REF_JITTER1(0.0), 532 | .STARTUP_WAIT("FALSE") 533 | ) MMCME2_BASE_inst ( 534 | .CLKOUT0(host_clk_i), 535 | .CLKOUT0B(), 536 | .CLKOUT1(), 537 | .CLKOUT1B(), 538 | .CLKOUT2(), 539 | .CLKOUT2B(), 540 | .CLKOUT3(), 541 | .CLKOUT3B(), 542 | .CLKOUT4(), 543 | .CLKOUT5(), 544 | .CLKOUT6(), 545 | .CLKFBOUT(gclk_fbout), 546 | .CLKFBOUTB(), 547 | .LOCKED(mmcm_locked), 548 | .CLKIN1(gclk_i), 549 | .PWRDWN(1'b0), 550 | .RST(1'b0), 551 | .CLKFBIN(gclk_fbout)); 552 | 553 | endmodule 554 | 555 | -------------------------------------------------------------------------------- /hw/zybo_refchip.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado (TM) v2013.4 (64-bit) 3 | # 4 | # zybo_refchip.tcl: Tcl script for re-creating project 'zybo_bsd' 5 | # 6 | # Generated by Vivado on Fri Aug 01 10:36:13 PDT 2014 7 | # IP Build 208076 on Mon Dec 2 12:38:17 MST 2013 8 | # 9 | # This file contains the Vivado Tcl commands for re-creating the project to the state* 10 | # when this script was generated. In order to re-create the project, please source this 11 | # file in the Vivado Tcl Shell. 12 | # 13 | # * Note that the runs in the created project will be configured the same way as the 14 | # original project, however they will not be launched automatically. To regenerate the 15 | # run results please launch the synthesis/implementation runs as needed. 16 | # 17 | #***************************************************************************************** 18 | # NOTE: In order to use this script for source control purposes, please make sure that the 19 | # following files are added to the source control system:- 20 | # 21 | # 1. This project restoration tcl script (zybo_refchip.tcl) that was generated. 22 | # 23 | # 2. The following source(s) files that were local or imported into the original project. 24 | # (Please see the '$orig_proj_dir' variable setting below at the start of the script) 25 | # 26 | # "/scratch/skarandikar/zybo_test_system2_WORKON_WORKING/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/sources_1/imports/zybo_base_systemMOD/Slave.v" 27 | # "/scratch/skarandikar/zybo_test_system2_WORKON_WORKING/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/sources_1/imports/zybo_base_systemMOD/fifos.v" 28 | # "/scratch/skarandikar/zybo_test_system2_WORKON_WORKING/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/system.bd" 29 | # "/scratch/skarandikar/zybo_test_system2_WORKON_WORKING/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/sources_1/imports/hdl/system_wrapper.v" 30 | # "/scratch/skarandikar/zybo_test_system2_WORKON_WORKING/zybo_base_systemMOD/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/constrs_1/new/base.xdc" 31 | # 32 | # 3. The following remote source files that were added to the original project:- 33 | # 34 | # 35 | # 36 | #***************************************************************************************** 37 | 38 | # Set the original project directory path for adding/importing sources in the new project 39 | set orig_proj_dir "./" 40 | 41 | # Create project 42 | create_project zybo_bsd ./zybo_bsd 43 | 44 | # Set the directory path for the new project 45 | set proj_dir [get_property directory [current_project]] 46 | 47 | # Set project properties 48 | set obj [get_projects zybo_bsd] 49 | set_property "part" "xc7z010clg400-1" $obj 50 | set_property "simulator_language" "Mixed" $obj 51 | 52 | # Create 'sources_1' fileset (if not found) 53 | if {[string equal [get_filesets sources_1] ""]} { 54 | create_fileset -srcset sources_1 55 | } 56 | 57 | # Add files to 'sources_1' fileset 58 | set obj [get_filesets sources_1] 59 | set files [list \ 60 | "[file normalize "$orig_proj_dir/src/bd/system/system.bd"]"\ 61 | ] 62 | add_files -norecurse -fileset $obj $files 63 | 64 | # Import local files from the original project 65 | set files [list \ 66 | "[file normalize "$orig_proj_dir/src/verilog/Slave.v"]"\ 67 | "[file normalize "$orig_proj_dir/src/verilog/fifos.v"]"\ 68 | "[file normalize "$orig_proj_dir/src/verilog/system_wrapper.v"]"\ 69 | ] 70 | set imported_files [import_files -fileset sources_1 $files] 71 | 72 | # Set 'sources_1' fileset file properties for remote files 73 | # None 74 | 75 | # Set 'sources_1' fileset file properties for local files 76 | # None 77 | 78 | # Set 'sources_1' fileset properties 79 | set obj [get_filesets sources_1] 80 | set_property "top" "system_wrapper" $obj 81 | 82 | # Create 'constrs_1' fileset (if not found) 83 | if {[string equal [get_filesets constrs_1] ""]} { 84 | create_fileset -constrset constrs_1 85 | } 86 | 87 | # Add files to 'constrs_1' fileset 88 | set obj [get_filesets constrs_1] 89 | set files [list \ 90 | "[file normalize "$orig_proj_dir/src/constrs/base.xdc"]"\ 91 | ] 92 | add_files -norecurse -fileset $obj $files 93 | 94 | 95 | # Set 'constrs_1' fileset file properties for remote files 96 | set file "$orig_proj_dir/src/constrs/base.xdc" 97 | set file [file normalize $file] 98 | set file_obj [get_files -of_objects constrs_1 [list "*$file"]] 99 | set_property "file_type" "XDC" $file_obj 100 | 101 | # Set 'constrs_1' fileset file properties for local files 102 | #set file "new/base.xdc" 103 | #set file_obj [get_files -of_objects constrs_1 [list "*$file"]] 104 | #set_property "file_type" "XDC" $file_obj 105 | 106 | # Set 'constrs_1' fileset properties 107 | set obj [get_filesets constrs_1] 108 | set_property "target_constrs_file" "$orig_proj_dir/src/constrs/base.xdc" $obj 109 | 110 | # Create 'sim_1' fileset (if not found) 111 | if {[string equal [get_filesets sim_1] ""]} { 112 | create_fileset -simset sim_1 113 | } 114 | 115 | # Add files to 'sim_1' fileset 116 | set obj [get_filesets sim_1] 117 | # Empty (no sources present) 118 | 119 | # Set 'sim_1' fileset properties 120 | set obj [get_filesets sim_1] 121 | set_property "top" "system_wrapper" $obj 122 | 123 | # Create 'synth_1' run (if not found) 124 | if {[string equal [get_runs synth_1] ""]} { 125 | create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2013} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 126 | } 127 | set obj [get_runs synth_1] 128 | set_property "needs_refresh" "1" $obj 129 | set_property "part" "xc7z010clg400-1" $obj 130 | 131 | # Create 'impl_1' run (if not found) 132 | if {[string equal [get_runs impl_1] ""]} { 133 | create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2013} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 134 | } 135 | set obj [get_runs impl_1] 136 | set_property "needs_refresh" "1" $obj 137 | set_property "part" "xc7z010clg400-1" $obj 138 | 139 | puts "INFO: Project created:zybo_bsd" 140 | 141 | puts "About to generate IP" 142 | reset_target all [get_files "$orig_proj_dir/src/bd/system/system.bd"] 143 | generate_target all [get_files "$orig_proj_dir/src/bd/system/system.bd"] 144 | -------------------------------------------------------------------------------- /sd_image/boot.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pkorolov/zynq-fpga/4c6fa890dcb4b807bdd70f222412b401f46f46e3/sd_image/boot.bin -------------------------------------------------------------------------------- /sd_image/devicetree.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pkorolov/zynq-fpga/4c6fa890dcb4b807bdd70f222412b401f46f46e3/sd_image/devicetree.dtb -------------------------------------------------------------------------------- /sd_image/riscv/root_spike.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pkorolov/zynq-fpga/4c6fa890dcb4b807bdd70f222412b401f46f46e3/sd_image/riscv/root_spike.bin -------------------------------------------------------------------------------- /sd_image/riscv/vmlinux: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pkorolov/zynq-fpga/4c6fa890dcb4b807bdd70f222412b401f46f46e3/sd_image/riscv/vmlinux -------------------------------------------------------------------------------- /sd_image/uImage: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pkorolov/zynq-fpga/4c6fa890dcb4b807bdd70f222412b401f46f46e3/sd_image/uImage -------------------------------------------------------------------------------- /sd_image/uramdisk.image.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pkorolov/zynq-fpga/4c6fa890dcb4b807bdd70f222412b401f46f46e3/sd_image/uramdisk.image.gz --------------------------------------------------------------------------------