├── .gitignore ├── 6502-test-code ├── AllSuiteA.asm ├── AllSuiteA.bin ├── Makefile ├── apple1basic.bin ├── apple1monitor.bin ├── test-illegal-opcode-xaa-michael-steil.asm ├── test-illegal-opcode-xaa-michael-steil.bin ├── test1.asm ├── test1.bin ├── test2.asm ├── test2.bin ├── test3.asm └── test3.bin ├── LICENSE ├── Makefile ├── README ├── iverilog ├── 4004 │ ├── Makefile │ ├── test1.asm │ └── test1.lst ├── 6502 │ ├── Makefile │ └── test_6502.lxt └── .gitignore ├── masks ├── 4001 │ ├── 4001-klayout-screenshot.png │ ├── 4001.cif │ ├── 4001.ext │ ├── 4001.gds │ ├── 4001.spice │ ├── 4001.svg │ ├── Makefile │ ├── contact.bmp │ ├── contact.png │ ├── diffusion.bmp │ ├── diffusion.png │ ├── i4001-diffusion.bmp │ ├── i4001-metal.bmp │ ├── i4001-poly.bmp │ ├── i4001-vias.bmp │ ├── metal.bmp │ ├── metal.png │ ├── pads.txt │ ├── poly.bmp │ └── poly.png ├── 4002 │ ├── 4002-klayout-screenshot.png │ ├── 4002.cif │ ├── 4002.ext │ ├── 4002.gds │ ├── 4002.spice │ ├── 4002.svg │ ├── Makefile │ ├── contact.bmp │ ├── contact.png │ ├── diffusion.bmp │ ├── diffusion.png │ ├── i4002-diffusion.bmp │ ├── i4002-metal.bmp │ ├── i4002-poly.bmp │ ├── i4002-vias.bmp │ ├── metal.bmp │ ├── metal.png │ ├── pads.txt │ ├── poly.bmp │ └── poly.png ├── 4003 │ ├── 4003-klayout-screenshot.png │ ├── 4003-reduced.spice │ ├── 4003.cif │ ├── 4003.ext │ ├── 4003.gds │ ├── 4003.spice │ ├── 4003.svg │ ├── Makefile │ ├── contact.bmp │ ├── contact.png │ ├── diffusion.bmp │ ├── diffusion.png │ ├── i4003-diffusion.bmp │ ├── i4003-metal.bmp │ ├── i4003-poly.bmp │ ├── i4003-signals.txt │ ├── i4003-vias.bmp │ ├── lajos-4003-layout-netlist.txt │ ├── lajos-4003.spice │ ├── metal.bmp │ ├── metal.png │ ├── pads.txt │ ├── pins.txt │ ├── poly.bmp │ ├── poly.png │ └── translate.py ├── 4004 │ ├── 4004-klayout-screenshot.png │ ├── 4004-nmos-buried-stacked.tech │ ├── 4004-reduced.spice │ ├── 4004-run.spice │ ├── 4004-system.spice │ ├── 4004.cif │ ├── 4004.ext │ ├── 4004.gds │ ├── 4004.spice │ ├── 4004.svg │ ├── Makefile │ ├── buried.bmp │ ├── buried.png │ ├── chip.tech │ ├── contact.bmp │ ├── contact.png │ ├── diffusion.bmp │ ├── diffusion.png │ ├── i4004-contacts.bmp │ ├── i4004-diffusion.bmp │ ├── i4004-metal.bmp │ ├── i4004-poly.bmp │ ├── i4004-signals.txt │ ├── i4004-vias.bmp │ ├── lajos-4004-layout-netlist.txt │ ├── lajos-4004.spice │ ├── metal.bmp │ ├── metal.png │ ├── nodes.txt │ ├── pads.txt │ ├── pins.txt │ ├── poly.bmp │ ├── poly.png │ └── translate.py ├── 6502 │ ├── 6502-klayout-screenshot.png │ ├── 6502-nmos.tech │ ├── 6502-run.spice │ ├── 6502-system.spice │ ├── 6502.cif │ ├── 6502.ext │ ├── 6502.gds │ ├── 6502.spice │ ├── 6502.svg │ ├── 6502Node-subsplits.svg │ ├── 6502Node.svg │ ├── Makefile │ ├── README │ ├── apply-tweak.py │ ├── buried.png │ ├── buried.polygon │ ├── chip.tech │ ├── contact.png │ ├── contact.polygon │ ├── dep │ ├── diffusion.png │ ├── diffusion.polygon │ ├── diffusion.tweak │ ├── implant.png │ ├── implant.polygon │ ├── make_implant_polygons.py │ ├── mark_new_depletion.py │ ├── metal.png │ ├── metal.polygon │ ├── nodes.txt │ ├── pads.txt │ ├── poly.png │ ├── poly.polygon │ ├── polygon2label.py │ ├── pullups.js │ └── spice_readfile.m ├── 6800 │ ├── 6800-klayout-screenshot.png │ ├── 6800-nmos.tech │ ├── 6800.cif │ ├── 6800.ext │ ├── 6800.gds │ ├── 6800.spice │ ├── Makefile │ ├── buried.png │ ├── buried.svg │ ├── chip.tech │ ├── contact.png │ ├── contact.svg │ ├── diffusion.png │ ├── diffusion.svg │ ├── jorge-6800.spice │ ├── mc6800a-layout-notes.txt │ ├── mc6800a-layout.svg │ ├── metal.png │ ├── metal.svg │ ├── poly.png │ ├── poly.svg │ └── spice-netlist.txt ├── .gitignore ├── Makefile ├── README ├── hp35-bitmap-tools │ ├── Makefile │ ├── contact.png │ ├── diffusion.png │ ├── gate.png │ ├── gimp-extract-layers.py │ ├── implant.png │ ├── masks_to_netlist.py │ ├── metal.png │ ├── netlist.txt │ ├── netlist.v │ ├── netlist_to_verilog.py │ ├── pad.png │ ├── pins.txt │ └── testbench.v ├── rules.make └── tools │ ├── .gitignore │ ├── fix_spice_comments.py │ ├── lajos2nodes.py │ ├── lajos2spice.py │ ├── make-composite-svg.py │ ├── mask_util.py │ ├── png2cif.py │ ├── png2gds.py │ ├── polygon2png.py │ ├── spice-reduce.py │ └── svg2png.py ├── netlist-translation ├── .gitignore ├── 6502-from-javascript.spice ├── Makefile ├── js2spice.py ├── netlist.py ├── netlist_import.py ├── netlist_util.py ├── translate.py ├── verilog.py └── verilog_gen.py ├── support ├── README ├── klayout-nmos.lyp └── potrace-1.9-optimal-polygon.patch ├── targets ├── digilent-s3e-starter │ ├── .gitignore │ ├── Makefile │ ├── chip.ucf │ ├── chip.v │ ├── impact.bat │ ├── rom.py │ ├── rom.v │ ├── rs232_test.v │ ├── system.v │ ├── test.v │ ├── uart.v │ ├── uart_transceiver.v │ └── woz-monitor-and-basic-image ├── godil_6502 │ ├── .gitignore │ ├── Makefile │ ├── chip.ucf │ ├── chip.v │ └── godil.v └── godil_6507 │ ├── .gitignore │ ├── Makefile │ ├── chip.bit │ ├── chip.mcs │ ├── chip.ucf │ ├── chip.v │ └── godil.v ├── verilator ├── .gitignore ├── Makefile └── sim_main.cpp ├── verilog ├── chip_4003.v ├── chip_4004.v ├── chip_6502.v ├── chip_6507.v ├── clocks_4004.v ├── clocks_6502.v ├── common.h ├── models.v ├── ram_6502.v ├── rom_4004.v ├── test_4004.v ├── test_6502.v └── top.v └── visual6502 ├── README ├── nodenames.js ├── pins.txt ├── segdefs.js └── transdefs.js /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | -------------------------------------------------------------------------------- /6502-test-code/AllSuiteA.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/AllSuiteA.bin -------------------------------------------------------------------------------- /6502-test-code/Makefile: -------------------------------------------------------------------------------- 1 | AllSuiteA.bin: AllSuiteA.asm 2 | acme -o AllSuiteA.bin AllSuiteA.asm 3 | 4 | test1.bin: test1.asm 5 | acme -o test1.bin test1.asm 6 | 7 | test2.bin: test2.asm 8 | acme -o test2.bin test2.asm 9 | 10 | test3.bin: test3.asm 11 | acme -o test3.bin test3.asm 12 | 13 | test-illegal-opcode-xaa-michael-steil.bin: test-illegal-opcode-xaa-michael-steil.asm 14 | acme -o test-illegal-opcode-xaa-michael-steil.bin test-illegal-opcode-xaa-michael-steil.asm 15 | 16 | clean: 17 | rm -f AllSuiteA.bin test1.bin 18 | -------------------------------------------------------------------------------- /6502-test-code/apple1basic.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/apple1basic.bin -------------------------------------------------------------------------------- /6502-test-code/apple1monitor.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/apple1monitor.bin -------------------------------------------------------------------------------- /6502-test-code/test-illegal-opcode-xaa-michael-steil.asm: -------------------------------------------------------------------------------- 1 | *= $ffe0 2 | start: lda #$00 ; a9 00 3 | !8 $a2 4 | !8 $ff 5 | !8 $8b 6 | !8 $ff 7 | sta $0180 ; 8d 80 01 8 | loop: jmp loop 9 | 10 | *= $fffc 11 | !16 start 12 | -------------------------------------------------------------------------------- /6502-test-code/test-illegal-opcode-xaa-michael-steil.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/test-illegal-opcode-xaa-michael-steil.bin -------------------------------------------------------------------------------- /6502-test-code/test1.asm: -------------------------------------------------------------------------------- 1 | *= $fff0 2 | start: lda #$34 3 | loop: sta $58 4 | adc #$03 5 | jmp loop 6 | 7 | *= $fffc 8 | !16 start 9 | -------------------------------------------------------------------------------- /6502-test-code/test1.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/test1.bin -------------------------------------------------------------------------------- /6502-test-code/test2.asm: -------------------------------------------------------------------------------- 1 | *= $0000 2 | start: lda #$34 3 | loop: sta $58 4 | adc #$03 5 | jmp loop 6 | -------------------------------------------------------------------------------- /6502-test-code/test2.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/test2.bin -------------------------------------------------------------------------------- /6502-test-code/test3.asm: -------------------------------------------------------------------------------- 1 | *= $fff0 2 | start: lda #$34 3 | sta $d012 4 | loop: jmp loop 5 | 6 | *= $fffc 7 | !16 start 8 | -------------------------------------------------------------------------------- /6502-test-code/test3.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/6502-test-code/test3.bin -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Analysis code and target code is GPLv2, generated models (such as chip_6502.v) is LGPL. 2 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | demo: 2 | (cd verilator ; make sim ; make run_basic) 3 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | Tools for translating transistor netlists to HDL in a style that 2 | supports switch-level emulation. 3 | 4 | To run the apple1basic demo, install verilator and then do a "make 5 | demo". The verilator translation and C++ compile will take several 6 | minutes, and the apple1basic code, the statement "PRINT 1234/7", will 7 | take an additional several minutes before the response is given on the 8 | console. 9 | 10 | See verilator/sim_main.cpp for the simulation code. The 6502 model 11 | itself is in verilog/chip_6502.v. 12 | -------------------------------------------------------------------------------- /iverilog/.gitignore: -------------------------------------------------------------------------------- 1 | a.out 2 | -------------------------------------------------------------------------------- /iverilog/4004/Makefile: -------------------------------------------------------------------------------- 1 | VSRC = ../../verilog/{test_4004.v,chip_4004.v,clocks_4004.v,models.v,rom_4004.v} 2 | VFLAGS = -Wall 3 | 4 | test: 5 | iverilog $(VFLAGS) -DW=6 -DMAXTICKS=10000000 -DQUARTERCYCLE=250 -I../../verilog $(VSRC) 6 | ./a.out -lxt2 7 | 8 | clean: 9 | rm -f a.out *.lxt 10 | -------------------------------------------------------------------------------- /iverilog/4004/test1.asm: -------------------------------------------------------------------------------- 1 | ldm 3 2 | xch 2 3 | ldm 9 4 | loop: add 2 5 | jun loop 6 | -------------------------------------------------------------------------------- /iverilog/4004/test1.lst: -------------------------------------------------------------------------------- 1 | D3 ldm 3 2 | B2 xch 2 3 | D9 ldm 9 4 | 82 loop: add 2 5 | 40 03 jun loop 6 | -------------------------------------------------------------------------------- /iverilog/6502/Makefile: -------------------------------------------------------------------------------- 1 | VSRC = ../../verilog/{test_6502.v,chip_6502.v,clocks_6502.v,ram_6502.v,models.v} 2 | VFLAGS = -Wall 3 | 4 | test_allasm: 5 | iverilog $(VFLAGS) -DW=6 -DMAXTICKS=10000000 -DHALFCYCLE=25 -DDISPLAY_WRITES -DCODE=\"../../6502-test-code/AllSuiteA.bin\" -DCODE_START=4000 -DRESET=4000 -I../../verilog $(VSRC) 6 | 7 | test1: 8 | iverilog $(VFLAGS) -DW=6 -DMAXTICKS=80000 -DHALFCYCLE=25 -DDISPLAY_WRITES -DCODE=\"../../6502-test-code/test1.bin\" -DCODE_START=FFF0 -DRESET=FFF0 -I../../verilog $(VSRC) 9 | 10 | test-illegal-opcode-xaa-michael-steil: 11 | iverilog $(VFLAGS) -DW=6 -DMAXTICKS=50000 -DHALFCYCLE=25 -DDISPLAY_WRITES -DCODE=\"../../6502-test-code/test-illegal-opcode-xaa-michael-steil.bin\" -DCODE_START=FFE0 -DRESET=FFE0 -I../../verilog $(VSRC) 12 | ./a.out -lxt2 13 | gtkwave test_6502.lxt 14 | 15 | clean: 16 | rm -f a.out *.lxt 17 | -------------------------------------------------------------------------------- /iverilog/6502/test_6502.lxt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/iverilog/6502/test_6502.lxt -------------------------------------------------------------------------------- /masks/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.log2 3 | *.feedback 4 | *.vec.svg 5 | -------------------------------------------------------------------------------- /masks/4001/4001-klayout-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/4001-klayout-screenshot.png -------------------------------------------------------------------------------- /masks/4001/4001.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/4001.gds -------------------------------------------------------------------------------- /masks/4001/Makefile: -------------------------------------------------------------------------------- 1 | include ../rules.make 2 | 3 | all: 4001.gds 4001.cif 4001.svg 4001.spice 4 | 5 | PNGS = contact.png diffusion.png metal.png poly.png 6 | NAME = 4001 7 | # scale (in microns per pixel) of the png files (must be a multiple of 0.002): 8 | SCALE = 1.480 9 | 10 | 4001.svg: contact.vec.svg diffusion.vec.svg metal.vec.svg poly.vec.svg 11 | ../tools/make-composite-svg.py 2712 1768 >4001.svg 12 | 13 | 4001.cif: $(PNGS) pads.txt 14 | ../tools/png2cif.py $(NAME) $(SCALE) >4001.cif 15 | 16 | 4001.gds: $(PNGS) 17 | ../tools/png2gds.py $(NAME) $(SCALE) >4001.gds 18 | 19 | clean: 20 | rm -f $(PNGS) *.cif *.gds *~ 21 | rm -f 4001.spice 4001.ext 4001.feedback 22 | rm -f magic.log magic.log2 23 | rm -f ext2spice.log ext2spice.log2 24 | rm -f *.vec.svg 25 | rm -f 4001.svg 26 | -------------------------------------------------------------------------------- /masks/4001/contact.bmp: -------------------------------------------------------------------------------- 1 | i4001-vias.bmp -------------------------------------------------------------------------------- /masks/4001/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/contact.png -------------------------------------------------------------------------------- /masks/4001/diffusion.bmp: -------------------------------------------------------------------------------- 1 | i4001-diffusion.bmp -------------------------------------------------------------------------------- /masks/4001/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/diffusion.png -------------------------------------------------------------------------------- /masks/4001/i4001-diffusion.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/i4001-diffusion.bmp -------------------------------------------------------------------------------- /masks/4001/i4001-metal.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/i4001-metal.bmp -------------------------------------------------------------------------------- /masks/4001/i4001-poly.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/i4001-poly.bmp -------------------------------------------------------------------------------- /masks/4001/i4001-vias.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/i4001-vias.bmp -------------------------------------------------------------------------------- /masks/4001/metal.bmp: -------------------------------------------------------------------------------- 1 | i4001-metal.bmp -------------------------------------------------------------------------------- /masks/4001/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/metal.png -------------------------------------------------------------------------------- /masks/4001/pads.txt: -------------------------------------------------------------------------------- 1 | d0 2611 708 NM ; pin 1 2 | d1 2610 365 NM ; pin 2 3 | d2 2150 131 NM ; pin 3 4 | d3 1639 132 NM ; pin 4 5 | GND! 1198 130 NM ; pin 5 6 | clk1 688 101 NM ; pin 6 7 | clk2 247 101 NM ; pin 7 8 | sync 149 480 NM ; pin 8 9 | reset 112 1492 NM ; pin 9 10 | cl 532 1663 NM ; pin 10 11 | cm 884 1661 NM ; pin 11 12 | Vdd! 1241 1662 NM ; pin 12 13 | io3 1674 1662 NM ; pin 13 14 | io2 2047 1662 NM ; pin 14 15 | io1 2600 1483 NM ; pin 15 16 | io0 2610 1183 NM ; pin 16 17 | GND! 2609 954 NM 18 | -------------------------------------------------------------------------------- /masks/4001/poly.bmp: -------------------------------------------------------------------------------- 1 | i4001-poly.bmp -------------------------------------------------------------------------------- /masks/4001/poly.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4001/poly.png -------------------------------------------------------------------------------- /masks/4002/4002-klayout-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/4002-klayout-screenshot.png -------------------------------------------------------------------------------- /masks/4002/4002.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/4002.gds -------------------------------------------------------------------------------- /masks/4002/Makefile: -------------------------------------------------------------------------------- 1 | include ../rules.make 2 | 3 | all: 4002.gds 4002.cif 4002.svg 4002.spice 4 | 5 | PNGS = contact.png diffusion.png metal.png poly.png 6 | NAME = 4002 7 | # scale (in microns per pixel) of the png files (must be a multiple of 0.002): 8 | SCALE = 1.270 9 | 10 | 4002.svg: contact.vec.svg diffusion.vec.svg metal.vec.svg poly.vec.svg 11 | ../tools/make-composite-svg.py 2176 2552 >4002.svg 12 | 13 | 4002.cif: $(PNGS) pads.txt 14 | ../tools/png2cif.py $(NAME) $(SCALE) >4002.cif 15 | 16 | 4002.gds: $(PNGS) 17 | ../tools/png2gds.py $(NAME) $(SCALE) >4002.gds 18 | 19 | clean: 20 | rm -f $(PNGS) *.cif *.gds *~ 21 | rm -f 4002.spice 4002.ext 4002.feedback 22 | rm -f magic.log magic.log2 23 | rm -f ext2spice.log ext2spice.log2 24 | rm -f *.vec.svg 25 | rm -f 4002.svg 26 | -------------------------------------------------------------------------------- /masks/4002/contact.bmp: -------------------------------------------------------------------------------- 1 | i4002-vias.bmp -------------------------------------------------------------------------------- /masks/4002/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/contact.png -------------------------------------------------------------------------------- /masks/4002/diffusion.bmp: -------------------------------------------------------------------------------- 1 | i4002-diffusion.bmp -------------------------------------------------------------------------------- /masks/4002/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/diffusion.png -------------------------------------------------------------------------------- /masks/4002/i4002-diffusion.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/i4002-diffusion.bmp -------------------------------------------------------------------------------- /masks/4002/i4002-metal.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/i4002-metal.bmp -------------------------------------------------------------------------------- /masks/4002/i4002-poly.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/i4002-poly.bmp -------------------------------------------------------------------------------- /masks/4002/i4002-vias.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/i4002-vias.bmp -------------------------------------------------------------------------------- /masks/4002/metal.bmp: -------------------------------------------------------------------------------- 1 | i4002-metal.bmp -------------------------------------------------------------------------------- /masks/4002/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/metal.png -------------------------------------------------------------------------------- /masks/4002/pads.txt: -------------------------------------------------------------------------------- 1 | d0 960 101 NM ; pin 1 2 | d1 699 100 NM ; pin 2 3 | d2 92 738 NM ; pin 3 4 | d3 92 1378 NM ; pin 4 5 | GND! 93 1665 NM ; pin 5 6 | clk1 93 2053 NM ; pin 6 7 | clk2 470 2467 NM ; pin 7 8 | GND! 746 2467 NM 9 | sync 1061 2467 NM ; pin 8 10 | reset 1284 2467 NM ; pin 9 11 | p0 1709 2467 NM ; pin 10 12 | cm 2090 1411 NM ; pin 11 13 | Vdd! 2086 1184 NM ; pin 12 14 | o3 2086 1011 NM ; pin 13 15 | o2 2086 653 NM ; pin 14 16 | o1 1872 102 NM ; pin 15 17 | o0 1510 108 NM ; pin 16 18 | -------------------------------------------------------------------------------- /masks/4002/poly.bmp: -------------------------------------------------------------------------------- 1 | i4002-poly.bmp -------------------------------------------------------------------------------- /masks/4002/poly.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4002/poly.png -------------------------------------------------------------------------------- /masks/4003/4003-klayout-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/4003-klayout-screenshot.png -------------------------------------------------------------------------------- /masks/4003/4003.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/4003.gds -------------------------------------------------------------------------------- /masks/4003/Makefile: -------------------------------------------------------------------------------- 1 | include ../rules.make 2 | 3 | all: 4003.gds 4003.cif 4003.svg 4003.spice 4 | 5 | PNGS = contact.png diffusion.png metal.png poly.png 6 | NAME = 4003 7 | # scale (in microns per pixel) of the png files (must be a multiple of 0.002): 8 | SCALE = 0.830 9 | 10 | 4003.svg: contact.vec.svg diffusion.vec.svg metal.vec.svg poly.vec.svg 11 | ../tools/make-composite-svg.py 2328 1456 >4003.svg 12 | 13 | 4003.cif: $(PNGS) pads.txt 14 | ../tools/png2cif.py $(NAME) $(SCALE) >4003.cif 15 | 16 | 4003.gds: $(PNGS) 17 | ../tools/png2gds.py $(NAME) $(SCALE) >4003.gds 18 | 19 | extract: 4003.spice 20 | <4003.spice ../tools/spice-reduce.py >4003-reduced.spice 21 | python ./translate.py 22 | 23 | clean: 24 | rm -f $(PNGS) *.cif *.gds *~ 25 | rm -f 4003.spice 4003.ext 4003.feedback 26 | rm -f magic.log magic.log2 27 | rm -f ext2spice.log ext2spice.log2 28 | rm -f *.vec.svg 29 | rm -f 4003.svg 30 | -------------------------------------------------------------------------------- /masks/4003/contact.bmp: -------------------------------------------------------------------------------- 1 | i4003-vias.bmp -------------------------------------------------------------------------------- /masks/4003/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/contact.png -------------------------------------------------------------------------------- /masks/4003/diffusion.bmp: -------------------------------------------------------------------------------- 1 | i4003-diffusion.bmp -------------------------------------------------------------------------------- /masks/4003/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/diffusion.png -------------------------------------------------------------------------------- /masks/4003/i4003-diffusion.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/i4003-diffusion.bmp -------------------------------------------------------------------------------- /masks/4003/i4003-metal.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/i4003-metal.bmp -------------------------------------------------------------------------------- /masks/4003/i4003-poly.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/i4003-poly.bmp -------------------------------------------------------------------------------- /masks/4003/i4003-signals.txt: -------------------------------------------------------------------------------- 1 | 1,30,27,Q3,+ 2 | 1,468,27,Q2,+ 3 | 1,939,27,GND,+ 4 | 1,1234,27,Q1,+ 5 | 1,1538,28,Q0,+ 6 | 1,2152,28,DATA,+ 7 | 1,365,65,S00007,- 8 | 1,1927,66,VDD,+ 9 | 1,1827,75,N0040,+ 10 | 1,856,89,S00010,- 11 | 1,340,90,S00011,- 12 | 1,689,90,S00012,- 13 | 1,732,90,S00013,- 14 | 1,793,90,S00014,- 15 | 1,1965,90,N0037,+ 16 | 1,1883,103,N0038,+ 17 | 1,1935,103,N0031,+ 18 | 1,1964,186,N0032,+ 19 | 1,213,296,Q4,+ 20 | 1,1900,308,N0027,+ 21 | 1,1955,351,N0029,+ 22 | 1,360,360,N0127,+ 23 | 1,939,360,N0089,+ 24 | 1,1518,360,N0049,+ 25 | 1,648,361,N0109,+ 26 | 1,1227,361,N0069,+ 27 | 1,569,414,N0137,+ 28 | 1,671,414,N0110,+ 29 | 1,699,414,N0021,+ 30 | 1,858,414,N0119,+ 31 | 1,962,414,N0090,+ 32 | 1,1147,414,N0099,+ 33 | 1,1249,414,N0070,+ 34 | 1,382,415,N0128,+ 35 | 1,1437,415,N0079,+ 36 | 1,1538,415,N0050,+ 37 | 1,1726,415,N0059,+ 38 | 1,2001,421,N0024,+ 39 | 1,2167,435,CLOCK,+ 40 | 1,2009,498,N0022,+ 41 | 1,578,549,N0123,+ 42 | 1,625,549,N0107,+ 43 | 1,868,549,N0103,+ 44 | 1,915,549,N0087,+ 45 | 1,1156,549,N0083,+ 46 | 1,1203,549,N0067,+ 47 | 1,1446,549,N0063,+ 48 | 1,1493,549,N0047,+ 49 | 1,1841,549,N0019,+ 50 | 1,700,554,N0113,+ 51 | 1,990,554,N0093,+ 52 | 1,1279,554,N0073,+ 53 | 1,1569,554,N0053,+ 54 | 1,411,555,N0131,+ 55 | 1,477,556,N0121,+ 56 | 1,1634,556,N0041,+ 57 | 1,766,557,N0101,+ 58 | 1,1056,557,N0081,+ 59 | 1,1344,557,N0061,+ 60 | 1,577,580,N0134,+ 61 | 1,868,580,N0116,+ 62 | 1,1156,580,N0096,+ 63 | 1,1446,581,N0076,+ 64 | 1,1730,649,N0043,+ 65 | 1,388,656,N0126,+ 66 | 1,1729,680,N0056,+ 67 | 1,1771,680,N0020,+ 68 | 1,1271,708,N0039,+ 69 | 1,1820,766,N0030,+ 70 | 1,337,784,N0058,+ 71 | 1,371,784,N0046,+ 72 | 1,1992,801,N0035,+ 73 | 1,1830,812,N0034,+ 74 | 1,437,817,N0048,+ 75 | 1,845,817,N0068,+ 76 | 1,1016,817,N0088,+ 77 | 1,1305,817,N0108,+ 78 | 1,1594,817,N0036,+ 79 | 1,590,893,N0044,+ 80 | 1,623,893,N0078,+ 81 | 1,879,893,N0064,+ 82 | 1,912,893,N0098,+ 83 | 1,1168,893,N0084,+ 84 | 1,1201,893,N0118,+ 85 | 1,1458,893,N0104,+ 86 | 1,1492,893,N0136,+ 87 | 1,1603,895,N0026,+ 88 | 1,1928,902,N0028,+ 89 | 1,2152,912,EN,+ 90 | 1,501,919,N0054,+ 91 | 1,790,919,N0074,+ 92 | 1,1079,919,N0094,+ 93 | 1,1368,919,N0114,+ 94 | 1,1658,919,N0132,+ 95 | 1,623,921,N0066,+ 96 | 1,913,921,N0086,+ 97 | 1,1201,921,N0106,+ 98 | 1,1491,921,N0125,+ 99 | 1,1968,926,N0017,+ 100 | 1,30,995,Q5,+ 101 | 1,1878,1035,OUT,+ 102 | 1,350,1051,N0060,+ 103 | 1,537,1051,N0052,+ 104 | 1,827,1051,N0072,+ 105 | 1,1116,1051,N0092,+ 106 | 1,641,1052,N0080,+ 107 | 1,929,1052,N0100,+ 108 | 1,1215,1052,N0120,+ 109 | 1,1404,1052,N0112,+ 110 | 1,1507,1052,N0138,+ 111 | 1,1693,1052,N0130,+ 112 | 1,1896,1083,N0018,+ 113 | 1,488,1087,N0051,+ 114 | 1,780,1087,N0071,+ 115 | 1,1067,1087,N0091,+ 116 | 1,1354,1087,N0111,+ 117 | 1,1646,1087,N0129,+ 118 | 1,747,1144,Q6,+ 119 | 1,1035,1144,Q7,+ 120 | 1,1321,1144,Q8,+ 121 | 1,1612,1144,Q9,+ 122 | 1,611,1261,S00122,- 123 | 1,880,1263,S00123,- 124 | 1,611,1291,S00124,- 125 | 1,641,1291,S00125,- 126 | 1,1863,1299,S00126,- 127 | 1,641,1397,S00127,- 128 | 1,686,1397,S00128,- 129 | 2,342,55,S00129,- 130 | 2,342,79,S00130,- 131 | 3,341,66,S00131,- 132 | 3,352,90,S00132,- 133 | 3,1383,578,N0062,+ 134 | 3,1671,578,N0042,+ 135 | 3,513,579,N0122,+ 136 | 3,803,579,N0102,+ 137 | 3,1091,579,N0082,+ 138 | 3,1769,614,N0023,+ 139 | 3,477,631,N0133,+ 140 | 3,766,631,N0115,+ 141 | 3,1056,631,N0095,+ 142 | 3,1345,631,N0075,+ 143 | 3,1634,631,N0055,+ 144 | 3,985,839,N0097,+ 145 | 3,1274,839,N0117,+ 146 | 3,1564,839,N0135,+ 147 | 3,1871,839,N0033,+ 148 | 3,406,840,N0057,+ 149 | 3,695,840,N0077,+ 150 | 3,1006,891,N0085,+ 151 | 3,1293,891,N0105,+ 152 | 3,1583,891,N0124,+ 153 | 3,426,892,N0045,+ 154 | 3,716,892,N0065,+ 155 | 3,1775,896,N0025,+ 156 | -------------------------------------------------------------------------------- /masks/4003/i4003-vias.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/i4003-vias.bmp -------------------------------------------------------------------------------- /masks/4003/lajos-4003.spice: -------------------------------------------------------------------------------- 1 | * SPICE3 converted from Lajos's format 2 | 3 | M0 VDD VDD N0037 GND efet 4 | M1 VDD VDD N0040 GND efet 5 | M2 GND N0031 N0037 GND efet 6 | M3 GND N0038 N0040 GND efet 7 | M4 VDD VDD N0038 GND efet 8 | M5 N0038 N0037 GND GND efet 9 | M6 N0031 N0032 GND GND efet 10 | M7 N0031 N0029 GND GND efet 11 | M8 GND N0031 N0032 GND efet 12 | M9 GND GND DATA GND efet 13 | M10 GND N0137 Q4 GND efet 14 | M11 GND N0119 Q3 GND efet 15 | M12 GND N0099 Q2 GND efet 16 | M13 GND N0079 Q1 GND efet 17 | M14 GND N0059 Q0 GND efet 18 | M15 N0032 N0027 GND GND efet 19 | M16 N0127 N0128 GND GND efet 20 | M17 N0109 N0110 GND GND efet 21 | M18 N0089 N0090 GND GND efet 22 | M19 N0069 N0070 GND GND efet 23 | M20 N0049 N0050 GND GND efet 24 | M21 VDD VDD N0031 GND efet 25 | M22 VDD VDD N0032 GND efet 26 | M23 GND N0027 N0029 GND efet 27 | M24 N0127 N0021 GND GND efet 28 | M25 N0109 N0021 GND GND efet 29 | M26 N0089 N0021 GND GND efet 30 | M27 N0069 N0021 GND GND efet 31 | M28 N0049 N0021 GND GND efet 32 | M29 VDD VDD N0029 GND efet 33 | M30 N0027 N0024 GND GND efet 34 | M31 GND GND CLOCK GND efet 35 | M32 N0059 N0049 GND GND efet 36 | M33 N0137 N0127 GND GND efet 37 | M34 N0119 N0109 GND GND efet 38 | M35 N0099 N0089 GND GND efet 39 | M36 N0079 N0069 GND GND efet 40 | M37 N0024 N0022 GND GND efet 41 | M38 VDD VDD N0027 GND efet 42 | M39 VDD VDD N0127 GND efet 43 | M40 VDD VDD N0109 GND efet 44 | M41 VDD VDD N0089 GND efet 45 | M42 VDD VDD N0069 GND efet 46 | M43 VDD VDD N0049 GND efet 47 | M44 VDD VDD N0119 GND efet 48 | M45 VDD VDD N0099 GND efet 49 | M46 VDD VDD N0079 GND efet 50 | M47 VDD VDD N0059 GND efet 51 | M48 VDD VDD N0137 GND efet 52 | M49 VDD N0049 Q0 GND efet 53 | M50 VDD N0127 Q4 GND efet 54 | M51 VDD N0109 Q3 GND efet 55 | M52 VDD N0089 Q2 GND efet 56 | M53 VDD N0069 Q1 GND efet 57 | M54 VDD VDD N0024 GND efet 58 | M55 VDD VDD N0019 GND efet 59 | M56 VDD VDD N0121 GND efet 60 | M57 VDD VDD N0101 GND efet 61 | M58 VDD VDD N0081 GND efet 62 | M59 VDD VDD N0061 GND efet 63 | M60 VDD VDD N0041 GND efet 64 | M61 N0121 N0040 N0128 GND efet 65 | M62 N0101 N0040 N0110 GND efet 66 | M63 N0081 N0040 N0090 GND efet 67 | M64 N0061 N0040 N0070 GND efet 68 | M65 N0041 N0040 N0050 GND efet 69 | M66 N0107 N0032 N0123 GND efet 70 | M67 N0087 N0032 N0103 GND efet 71 | M68 N0067 N0032 N0083 GND efet 72 | M69 N0047 N0032 N0063 GND efet 73 | M70 GND N0019 N0022 GND efet 74 | M71 N0131 N0040 N0121 GND efet 75 | M72 N0113 N0040 N0101 GND efet 76 | M73 N0093 N0040 N0081 GND efet 77 | M74 N0073 N0040 N0061 GND efet 78 | M75 N0053 N0040 N0041 GND efet 79 | M76 N0042 N0031 N0041 GND efet 80 | M77 N0122 N0031 N0121 GND efet 81 | M78 N0102 N0031 N0101 GND efet 82 | M79 N0082 N0031 N0081 GND efet 83 | M80 N0062 N0031 N0061 GND efet 84 | M81 GND CLOCK N0019 GND efet 85 | M82 N0101 N0032 N0134 GND efet 86 | M83 N0081 N0032 N0116 GND efet 87 | M84 N0061 N0032 N0096 GND efet 88 | M85 N0041 N0032 N0076 GND efet 89 | M86 GND N0123 N0122 GND efet 90 | M87 GND N0103 N0102 GND efet 91 | M88 GND N0083 N0082 GND efet 92 | M89 GND N0063 N0062 GND efet 93 | M90 GND N0047 N0041 GND efet 94 | M91 GND N0043 N0042 GND efet 95 | M92 GND N0126 N0121 GND efet 96 | M93 GND N0107 N0101 GND efet 97 | M94 GND N0087 N0081 GND efet 98 | M95 GND N0067 N0061 GND efet 99 | M96 N0020 DATA GND GND efet 100 | M97 VDD VDD N0023 GND efet 101 | M98 N0055 N0056 GND GND efet 102 | M99 N0133 N0134 GND GND efet 103 | M100 N0115 N0116 GND GND efet 104 | M101 N0095 N0096 GND GND efet 105 | M102 N0075 N0076 GND GND efet 106 | M103 N0047 N0053 GND GND efet 107 | M104 N0126 N0131 GND GND efet 108 | M105 N0107 N0113 GND GND efet 109 | M106 N0087 N0093 GND GND efet 110 | M107 N0067 N0073 GND GND efet 111 | M108 GND N0020 N0023 GND efet 112 | M109 N0087 N0031 N0095 GND efet 113 | M110 N0067 N0031 N0075 GND efet 114 | M111 N0047 N0031 N0055 GND efet 115 | M112 N0126 N0031 N0133 GND efet 116 | M113 N0107 N0031 N0115 GND efet 117 | M114 N0023 N0032 N0043 GND efet 118 | M115 N0126 N0039 GND GND efet 119 | M116 GND N0039 N0107 GND efet 120 | M117 GND N0039 N0087 GND efet 121 | M118 GND N0039 N0067 GND efet 122 | M119 GND N0039 N0047 GND efet 123 | M120 VDD VDD N0126 GND efet 124 | M121 VDD VDD N0107 GND efet 125 | M122 VDD VDD N0087 GND efet 126 | M123 VDD VDD N0067 GND efet 127 | M124 VDD VDD N0047 GND efet 128 | M125 N0020 N0032 N0056 GND efet 129 | M126 VDD VDD N0022 GND efet 130 | M127 VDD VDD N0020 GND efet 131 | M128 VDD VDD N0048 GND efet 132 | M129 VDD VDD N0068 GND efet 133 | M130 VDD VDD N0088 GND efet 134 | M131 VDD VDD N0108 GND efet 135 | M132 VDD VDD N0036 GND efet 136 | M133 VDD VDD N0039 GND efet 137 | M134 GND N0034 N0039 GND efet 138 | M135 VDD VDD N0030 GND efet 139 | M136 N0058 N0032 N0121 GND efet 140 | M137 N0046 N0032 N0126 GND efet 141 | M138 VDD VDD N0034 GND efet 142 | M139 N0034 N0030 GND GND efet 143 | M140 GND N0027 N0030 GND efet 144 | M141 N0048 N0039 GND GND efet 145 | M142 N0068 N0039 GND GND efet 146 | M143 N0088 N0039 GND GND efet 147 | M144 N0108 N0039 GND GND efet 148 | M145 N0036 N0039 GND GND efet 149 | M146 VDD VDD N0035 GND efet 150 | M147 N0097 N0031 N0088 GND efet 151 | M148 N0117 N0031 N0108 GND efet 152 | M149 N0135 N0031 N0036 GND efet 153 | M150 N0033 N0034 N0030 GND efet 154 | M151 N0057 N0031 N0048 GND efet 155 | M152 N0077 N0031 N0068 GND efet 156 | M153 GND N0132 N0036 GND efet 157 | M154 GND N0058 N0057 GND efet 158 | M155 GND N0035 N0033 GND efet 159 | M156 GND N0054 N0048 GND efet 160 | M157 GND N0078 N0077 GND efet 161 | M158 GND N0074 N0068 GND efet 162 | M159 GND N0098 N0097 GND efet 163 | M160 GND N0094 N0088 GND efet 164 | M161 GND N0118 N0117 GND efet 165 | M162 GND N0114 N0108 GND efet 166 | M163 GND N0136 N0135 GND efet 167 | M164 N0028 N0017 GND GND efet 168 | M165 N0085 N0086 GND GND efet 169 | M166 N0105 N0106 GND GND efet 170 | M167 N0124 N0125 GND GND efet 171 | M168 N0045 N0046 GND GND efet 172 | M169 N0065 N0066 GND GND efet 173 | M170 N0044 N0048 GND GND efet 174 | M171 N0064 N0068 GND GND efet 175 | M172 N0084 N0088 GND GND efet 176 | M173 N0104 N0108 GND GND efet 177 | M174 N0026 N0036 GND GND efet 178 | M175 N0025 N0032 GND GND efet 179 | M176 N0017 N0028 GND GND efet 180 | M177 N0078 N0032 N0044 GND efet 181 | M178 N0098 N0032 N0064 GND efet 182 | M179 N0118 N0032 N0084 GND efet 183 | M180 N0136 N0032 N0104 GND efet 184 | M181 N0044 N0031 N0045 GND efet 185 | M182 N0064 N0031 N0065 GND efet 186 | M183 N0084 N0031 N0085 GND efet 187 | M184 N0104 N0031 N0105 GND efet 188 | M185 N0026 N0031 N0124 GND efet 189 | M186 N0028 N0036 N0025 GND efet 190 | M187 N0017 N0026 N0025 GND efet 191 | M188 N0044 N0040 N0054 GND efet 192 | M189 N0064 N0040 N0074 GND efet 193 | M190 N0084 N0040 N0094 GND efet 194 | M191 N0104 N0040 N0114 GND efet 195 | M192 N0026 N0040 N0132 GND efet 196 | M193 N0066 N0032 N0048 GND efet 197 | M194 N0086 N0032 N0068 GND efet 198 | M195 N0106 N0032 N0088 GND efet 199 | M196 N0125 N0032 N0108 GND efet 200 | M197 VDD VDD N0028 GND efet 201 | M198 VDD VDD N0026 GND efet 202 | M199 VDD VDD N0044 GND efet 203 | M200 VDD VDD N0064 GND efet 204 | M201 VDD VDD N0084 GND efet 205 | M202 VDD VDD N0104 GND efet 206 | M203 VDD VDD N0017 GND efet 207 | M204 N0130 N0040 N0026 GND efet 208 | M205 N0052 N0040 N0044 GND efet 209 | M206 N0072 N0040 N0064 GND efet 210 | M207 N0092 N0040 N0084 GND efet 211 | M208 N0112 N0040 N0104 GND efet 212 | M209 VDD VDD N0021 GND efet 213 | M210 VDD VDD N0100 GND efet 214 | M211 VDD VDD N0120 GND efet 215 | M212 VDD VDD N0138 GND efet 216 | M213 OUT N0017 VDD GND efet 217 | M214 VDD VDD N0060 GND efet 218 | M215 VDD VDD N0080 GND efet 219 | M216 VDD VDD N0091 GND efet 220 | M217 VDD VDD N0111 GND efet 221 | M218 VDD VDD N0129 GND efet 222 | M219 VDD VDD N0051 GND efet 223 | M220 VDD VDD N0071 GND efet 224 | M221 Q5 N0051 VDD GND efet 225 | M222 Q6 N0071 VDD GND efet 226 | M223 Q7 N0091 VDD GND efet 227 | M224 Q8 N0111 VDD GND efet 228 | M225 Q9 N0129 VDD GND efet 229 | M226 GND N0051 N0060 GND efet 230 | M227 GND N0071 N0080 GND efet 231 | M228 GND N0091 N0100 GND efet 232 | M229 GND N0111 N0120 GND efet 233 | M230 GND N0129 N0138 GND efet 234 | M231 GND EN N0021 GND efet 235 | M232 VDD VDD N0018 GND efet 236 | M233 GND N0018 OUT GND efet 237 | M234 Q5 N0060 GND GND efet 238 | M235 GND N0021 N0051 GND efet 239 | M236 GND N0052 N0051 GND efet 240 | M237 Q6 N0080 GND GND efet 241 | M238 GND N0021 N0071 GND efet 242 | M239 GND N0072 N0071 GND efet 243 | M240 Q7 N0100 GND GND efet 244 | M241 GND N0021 N0091 GND efet 245 | M242 GND N0092 N0091 GND efet 246 | M243 Q8 N0120 GND GND efet 247 | M244 Q9 N0138 GND GND efet 248 | M245 GND N0021 N0129 GND efet 249 | M246 GND N0130 N0129 GND efet 250 | M247 GND N0021 N0111 GND efet 251 | M248 GND N0112 N0111 GND efet 252 | M249 GND N0017 N0018 GND efet 253 | M250 GND GND EN GND efet 254 | -------------------------------------------------------------------------------- /masks/4003/metal.bmp: -------------------------------------------------------------------------------- 1 | i4003-metal.bmp -------------------------------------------------------------------------------- /masks/4003/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/metal.png -------------------------------------------------------------------------------- /masks/4003/pads.txt: -------------------------------------------------------------------------------- 1 | cp 2226 685 NM ; pin 1 2 | data_in 2226 96 NM ; pin 2 3 | q0 1615 97 NM ; pin 3 4 | q1 1309 96 NM ; pin 4 5 | GND! 1011 96 NM ; pin 5 6 | q2 541 97 NM ; pin 6 7 | q3 102 97 NM ; pin 7 8 | q4 103 402 NM ; pin 8 9 | GND! 104 738 NM 10 | q5 104 1066 NM ; pin 9 11 | q6 104 1336 NM ; pin 10 12 | q7 493 1335 NM ; pin 11 13 | q8 1012 1333 NM ; pin 12 14 | q9 1311 1331 NM ; pin 13 15 | Vdd! 1606 1330 NM ; pin 14 16 | serial_out 2227 1335 NM ; pin 15 17 | e 2227 982 NM ; pin 16 18 | -------------------------------------------------------------------------------- /masks/4003/pins.txt: -------------------------------------------------------------------------------- 1 | cp input 2 | data_in input 3 | e input 4 | q0 output 5 | q1 output 6 | q2 output 7 | q3 output 8 | q4 output 9 | q5 output 10 | q6 output 11 | q7 output 12 | q8 output 13 | q9 output 14 | serial_out output 15 | -------------------------------------------------------------------------------- /masks/4003/poly.bmp: -------------------------------------------------------------------------------- 1 | i4003-poly.bmp -------------------------------------------------------------------------------- /masks/4003/poly.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4003/poly.png -------------------------------------------------------------------------------- /masks/4003/translate.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | # 4 | # Translate the 4003 netlist into a Verilog model 5 | # 6 | # Copyright (c) 2011 Peter Monta 7 | # March 2011 8 | # 9 | 10 | import sys 11 | from netlist_import import * 12 | from verilog import * 13 | from netlist_util import * 14 | 15 | # 16 | # main program 17 | # 18 | 19 | p = read_netlist_from_spice('4003-reduced.spice') 20 | print_summary(p) 21 | 22 | #clean_netlist(p) 23 | #print_summary(p) 24 | 25 | #detect_gates(p) 26 | #print_summary(p) 27 | #print_gate_stats(p) 28 | 29 | #detect_latches(p) 30 | #print_summary(p) 31 | 32 | #detect_inverters(p) 33 | #print_summary(p) 34 | #detect_inverters(p) 35 | #print_summary(p) 36 | #detect_inverters(p) 37 | #print_summary(p) 38 | #detect_inverters(p) 39 | #print_summary(p) 40 | 41 | #detect_muxes(p) 42 | #print_summary(p) 43 | 44 | #print_netlist(p,'netlist.txt') 45 | print_verilog_spice_netlist(p,'../../verilog/chip_4003.v','chip_4003') 46 | -------------------------------------------------------------------------------- /masks/4004/4004-klayout-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/4004-klayout-screenshot.png -------------------------------------------------------------------------------- /masks/4004/4004-nmos-buried-stacked.tech: -------------------------------------------------------------------------------- 1 | # 2 | # Technology file for Intel i4004 3 | # 4 | # Peter Monta 5 | # March 2011 6 | # 7 | 8 | tech 9 | format 30 10 | 4004-nmos-buried-stacked 11 | end 12 | 13 | version 14 | version 0.1 15 | description "NMOS for the Intel i4004 with stacked buried contacts" 16 | end 17 | 18 | planes 19 | active 20 | metal 21 | end 22 | 23 | types 24 | active polysilicon,poly 25 | active diffusion,diff 26 | active fet 27 | active poly_metal_contact,pmc 28 | active diff_metal_contact,dmc 29 | active buried_contact,bc 30 | active triple_contact,tc 31 | metal metal 32 | end 33 | 34 | contact 35 | poly_metal_contact poly metal 36 | diff_metal_contact diff metal 37 | triple_contact buried metal 38 | end 39 | 40 | styles 41 | styletype mos 42 | polysilicon 1 43 | diffusion 2 44 | fet 6 7 45 | poly_metal_contact 1 20 32 46 | diff_metal_contact 2 20 32 47 | buried_contact 6 33 48 | triple_contact 34 49 | metal 20 50 | end 51 | 52 | compose 53 | compose fet poly diff 54 | decompose bc poly diff 55 | end 56 | 57 | connect 58 | poly fet,pmc,bc,tc 59 | diff dmc,bc,tc 60 | fet pmc,bc,tc 61 | # fet dmc? 62 | pmc dmc,bc,tc 63 | dmc bc,tc 64 | bc tc 65 | metal pmc,dmc,tc 66 | end 67 | 68 | cifoutput 69 | style default 70 | scalefactor 200 100 71 | layer NP poly,pmc,fet,bc,tc 72 | labels poly,fet,bc,tc 73 | layer ND diff,dmc,fet,bc,tc 74 | labels diff 75 | layer NM metal,pmc,dmc,tc 76 | labels metal,pmc,dmc 77 | layer NC dmc,pmc,tc 78 | layer NB bc 79 | end 80 | 81 | cifinput 82 | style default 83 | scalefactor 200 84 | layer poly NP 85 | labels NP 86 | layer diff ND 87 | labels ND 88 | layer metal NM 89 | labels NM 90 | layer fet NP 91 | and ND 92 | layer pmc NC 93 | and NM 94 | and NP 95 | layer dmc NC 96 | and NM 97 | and ND 98 | layer bc NB 99 | and NP 100 | and ND 101 | layer tc NB 102 | and NP 103 | and ND 104 | and NC 105 | and NM 106 | end 107 | 108 | drc 109 | end 110 | 111 | extract 112 | style default 113 | 114 | lambda 200 115 | step 100 116 | 117 | resist poly,pmc/active,fet,bc 30000 118 | resist diff,dmc/active 10000 119 | resist metal 30 120 | 121 | areacap poly,fet 200 122 | # fixme: fet capacitance is already in spice model, should be zero here? 123 | areacap metal 120 124 | areacap diff 400 125 | areacap bc,tc 600 126 | areacap dmc/active 520 127 | areacap pmc/active 320 128 | 129 | # perimcap diff,dmc/diff,bc,tc space,fet 200 130 | 131 | fet fet diff,dmc,bc,tc 2 efet GND! 0 0 132 | end 133 | -------------------------------------------------------------------------------- /masks/4004/4004-run.spice: -------------------------------------------------------------------------------- 1 | * top-level ngspice script 2 | 3 | .control 4 | source 4004-system.spice 5 | tran 5ns 240us 6 | write 4004-spice-rawfile.raw 7 | .endc 8 | 9 | .end 10 | -------------------------------------------------------------------------------- /masks/4004/4004-system.spice: -------------------------------------------------------------------------------- 1 | * 4004 circuit simulation 2 | 3 | * FET models 4 | 5 | .model efet NMOS level=1 vt0=1.0 6 | 7 | * handle floating nodes 8 | 9 | .option rshunt = 1.0e12 10 | 11 | * supply voltages 12 | 13 | v0 gnd! 0 dc 0 14 | v1 Vdd 0 dc 15 15 | 16 | * pull up the data bus to supply 0x00 for reads (after PMOS "inversion") and allow writes to be seen 17 | 18 | r0 db0 Vdd 10k 19 | r1 db1 Vdd 10k 20 | r2 db2 Vdd 10k 21 | r3 db3 Vdd 10k 22 | r4 db4 Vdd 10k 23 | r5 db5 Vdd 10k 24 | r6 db6 Vdd 10k 25 | r7 db7 Vdd 10k 26 | 27 | * pin settings, reset pulse, clock waveform 28 | 29 | v10 reset 0 pulse (0 15 40u 5n 5n) 30 | v11 test 0 dc 0 31 | v12 clk1 0 pulse (0 15 0u 5n 5n 3u 8u) 32 | v13 clk2 0 pulse (0 15 4u 5n 5n 3u 8u) 33 | 34 | * the 4004 model 35 | 36 | .include "4004.spice" 37 | 38 | .end 39 | -------------------------------------------------------------------------------- /masks/4004/4004.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/4004.gds -------------------------------------------------------------------------------- /masks/4004/Makefile: -------------------------------------------------------------------------------- 1 | include ../rules.make 2 | 3 | all: 4004.gds 4004.cif 4004.svg 4004.spice lajos-4004.spice translate 4 | 5 | PNGS = buried.png contact.png diffusion.png metal.png poly.png 6 | NAME = 4004 7 | # scale (in microns per pixel) of the png files (must be a multiple of 0.002): 8 | SCALE = 1.450 9 | 10 | 4004.svg: buried.vec.svg contact.vec.svg diffusion.vec.svg metal.vec.svg poly.vec.svg 11 | ../tools/make-composite-svg.py 1968 2706 >4004.svg 12 | 13 | sim: 4004-run.spice 4004-system.spice 4004.spice 14 | ngspice --batch 4004-run.spice 15 | 16 | 4004.cif: $(PNGS) nodes.txt pads.txt 17 | ../tools/png2cif.py $(NAME) $(SCALE) >4004.cif 18 | 19 | nodes.txt: i4004-signals.txt 20 | ../tools/lajos2nodes.py nodes.txt 21 | 22 | 4004.gds: $(PNGS) 23 | ../tools/png2gds.py $(NAME) $(SCALE) >4004.gds 24 | 25 | translate: 4004.spice 26 | <4004.spice ../tools/spice-reduce.py >4004-reduced.spice 27 | PYTHONPATH=../../netlist-translation python ./translate.py 28 | 29 | lajos-4004.spice: lajos-4004-layout-netlist.txt 30 | ../tools/lajos2spice.py lajos-4004.spice 31 | 32 | clean: 33 | rm -f $(PNGS) *.cif *.gds *~ 34 | rm -f 4004.spice 4004.ext 4004.feedback 35 | rm -f magic.log magic.log2 36 | rm -f ext2spice.log ext2spice.log2 37 | rm -f nodes.txt 38 | rm -f lajos-4004.spice 39 | rm -f 4004-reduced.spice 40 | rm -f *.vec.svg 41 | rm -f 4004.svg 42 | -------------------------------------------------------------------------------- /masks/4004/buried.bmp: -------------------------------------------------------------------------------- 1 | i4004-contacts.bmp -------------------------------------------------------------------------------- /masks/4004/buried.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/buried.png -------------------------------------------------------------------------------- /masks/4004/chip.tech: -------------------------------------------------------------------------------- 1 | 4004-nmos-buried-stacked.tech -------------------------------------------------------------------------------- /masks/4004/contact.bmp: -------------------------------------------------------------------------------- 1 | i4004-vias.bmp -------------------------------------------------------------------------------- /masks/4004/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/contact.png -------------------------------------------------------------------------------- /masks/4004/diffusion.bmp: -------------------------------------------------------------------------------- 1 | i4004-diffusion.bmp -------------------------------------------------------------------------------- /masks/4004/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/diffusion.png -------------------------------------------------------------------------------- /masks/4004/i4004-contacts.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/i4004-contacts.bmp -------------------------------------------------------------------------------- /masks/4004/i4004-diffusion.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/i4004-diffusion.bmp -------------------------------------------------------------------------------- /masks/4004/i4004-metal.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/i4004-metal.bmp -------------------------------------------------------------------------------- /masks/4004/i4004-poly.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/i4004-poly.bmp -------------------------------------------------------------------------------- /masks/4004/i4004-vias.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/i4004-vias.bmp -------------------------------------------------------------------------------- /masks/4004/metal.bmp: -------------------------------------------------------------------------------- 1 | i4004-metal.bmp -------------------------------------------------------------------------------- /masks/4004/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/metal.png -------------------------------------------------------------------------------- /masks/4004/pads.txt: -------------------------------------------------------------------------------- 1 | d0 799 2621 NM ; pin 1 2 | d1 1283 2623 NM ; pin 2 3 | d2 1898 2438 NM ; pin 3 4 | d3 1905 1974 NM ; pin 4 5 | GND! 1900 611 NM ; pin 5 6 | clk1 1903 314 NM ; pin 6 7 | clk2 1611 84 NM ; pin 7 8 | GND! 1266 84 NM 9 | sync 1057 80 NM ; pin 8 10 | reset 637 81 NM ; pin 9 11 | test 260 81 NM ; pin 10 12 | cm_rom 69 421 NM ; pin 11 13 | Vdd! 68 1481 NM ; pin 12 14 | cm_ram3 71 1837 NM ; pin 13 15 | cm_ram2 73 2143 NM ; pin 14 16 | cm_ram1 210 2622 NM ; pin 15 17 | cm_ram0 550 2619 NM ; pin 16 18 | -------------------------------------------------------------------------------- /masks/4004/pins.txt: -------------------------------------------------------------------------------- 1 | clk1 input 2 | clk2 input 3 | sync output 4 | reset input 5 | test input 6 | d0 bidirectional 7 | d1 bidirectional 8 | d2 bidirectional 9 | d3 bidirectional 10 | cm_rom output 11 | cm_ram3 output 12 | cm_ram2 output 13 | cm_ram1 output 14 | cm_ram0 output 15 | -------------------------------------------------------------------------------- /masks/4004/poly.bmp: -------------------------------------------------------------------------------- 1 | i4004-poly.bmp -------------------------------------------------------------------------------- /masks/4004/poly.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/4004/poly.png -------------------------------------------------------------------------------- /masks/4004/translate.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | # 4 | # Translate the 4003 netlist into a Verilog model 5 | # 6 | # Copyright (c) 2011 Peter Monta 7 | # March 2011 8 | # 9 | 10 | import sys 11 | from netlist_import import * 12 | from verilog import * 13 | from netlist_util import * 14 | 15 | # 16 | # main program 17 | # 18 | 19 | p = read_netlist_from_spice('4004-reduced.spice') 20 | print_summary(p) 21 | 22 | clean_netlist(p) 23 | print_summary(p) 24 | 25 | detect_gates(p) 26 | print_summary(p) 27 | print_gate_stats(p) 28 | 29 | ###detect_latches(p) 30 | ###print_summary(p) 31 | 32 | ###detect_inverters(p) 33 | ###print_summary(p) 34 | #detect_inverters(p) 35 | #print_summary(p) 36 | #detect_inverters(p) 37 | #print_summary(p) 38 | #detect_inverters(p) 39 | #print_summary(p) 40 | 41 | #detect_muxes(p) 42 | #print_summary(p) 43 | 44 | #print_netlist(p,'netlist.txt') 45 | print_verilog_spice_netlist(p,'../../verilog/chip_4004.v','chip_4004') 46 | -------------------------------------------------------------------------------- /masks/6502/6502-klayout-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/6502-klayout-screenshot.png -------------------------------------------------------------------------------- /masks/6502/6502-nmos.tech: -------------------------------------------------------------------------------- 1 | tech 2 | 6502-nmos 3 | end 4 | 5 | planes 6 | poly_diff,diff,active 7 | metal 8 | end 9 | 10 | types 11 | active polysilicon,poly,red 12 | active diffusion,diff,green 13 | metal metal,blue 14 | active poly_metal_contact,pmc 15 | active diff_metal_contact,dmc 16 | active enhancement_fet,efet 17 | active depletion_fet,dfet 18 | active depletion_capacitor,dcap 19 | active buried_contact,bc 20 | metal glass_contact,glass 21 | end 22 | 23 | styles 24 | styletype mos 25 | 26 | polysilicon 1 27 | diffusion 2 28 | metal 20 29 | enhancement_fet 6 30 | enhancement_fet 7 31 | depletion_fet 6 32 | depletion_fet 10 33 | depletion_capacitor 6 34 | depletion_capacitor 11 35 | buried_contact 6 36 | buried_contact 33 37 | poly_metal_contact 1 38 | poly_metal_contact 20 39 | poly_metal_contact 32 40 | diff_metal_contact 2 41 | diff_metal_contact 20 42 | diff_metal_contact 32 43 | glass_contact 20 44 | glass_contact 34 45 | 46 | error_s 42 47 | error_p 42 48 | error_ps 42 49 | 50 | magnet 39 51 | fence 38 52 | rotate 37 53 | end 54 | 55 | contact 56 | pmc poly metal 57 | dmc diff metal 58 | end 59 | 60 | compose 61 | compose efet poly diff 62 | decompose dfet poly diff 63 | decompose dcap poly diff 64 | decompose bc poly diff 65 | erase glass metal space 66 | end 67 | 68 | connect 69 | poly pmc,efet,dfet,dcap,bc 70 | diff bc,dmc 71 | efet pmc,dmc,bc,dfet,dcap 72 | dfet pmc,dmc,bc,dcap 73 | dcap pmc,dmc,bc 74 | pmc dmc,bc 75 | dmc bc 76 | metal glass,pmc,dmc 77 | glass pmc,dmc 78 | end 79 | 80 | cifoutput 81 | style lambda=2 82 | scalefactor 200 100 83 | layer NP poly,pmc,efet,dfet,dcap,bc 84 | labels poly,efet,dfet,dcap,bc 85 | calma 1 1 86 | layer ND diff,dmc,efet,dfet,dcap,bc 87 | labels diff 88 | calma 2 1 89 | layer NM metal,pmc,dmc,glass 90 | labels metal,pmc,dmc,glass 91 | calma 3 1 92 | layer NI 93 | bloat-or dfet,dcap * 200 diff,bc 400 94 | grow 100 95 | shrink 100 96 | calma 4 1 97 | layer NC dmc 98 | squares 400 99 | calma 5 1 100 | layer NC pmc 101 | squares 400 102 | calma 6 1 103 | layer NG glass 104 | calma 7 1 105 | layer NB 106 | bloat-or bc * 200 diff,dmc 400 dfet 0 107 | grow 100 108 | shrink 100 109 | calma 8 1 110 | end 111 | 112 | cifinput 113 | style lambda=2 114 | scalefactor 200 115 | layer poly NP 116 | labels NP 117 | layer diff ND 118 | labels ND 119 | layer metal NM 120 | labels NM 121 | layer efet NP 122 | and ND 123 | layer dfet NI 124 | and NP 125 | and ND 126 | layer pmc NC 127 | and NM 128 | and NP 129 | layer dmc NC 130 | and NM 131 | and ND 132 | layer bc NB 133 | and NP 134 | and ND 135 | layer glass NG 136 | end 137 | 138 | mzrouter 139 | style irouter 140 | layer metal 32 32 256 1 141 | layer poly 64 64 256 1 142 | contact pmc metal poly 1024 143 | end 144 | 145 | drc 146 | end 147 | 148 | extract 149 | style default 150 | lambda 200 151 | 152 | step 100 153 | 154 | resist poly,pmc/poly,efet,dfet,bc 30000 155 | resist diff,dmc/poly 10000 156 | resist metal,glass 30 157 | 158 | areacap poly,efet,dfet 200 159 | areacap metal,glass 120 160 | areacap diff 400 161 | areacap bc 600 162 | areacap dmc/poly 520 163 | areacap pmc/poly 320 164 | 165 | perimc diff,dmc/poly,bc space,dfet,efet 200 166 | 167 | fet efet diff 2 efet GND! 0 0 168 | fet dfet diff,bc 2 dfet GND! 0 0 169 | fet dcap diff,bc 1 dcap GND! 0 0 170 | end 171 | 172 | wiring 173 | contact pmc 4 metal 0 poly 0 174 | contact dmc 4 metal 0 diff 0 175 | contact bc 2 poly 0 diff 0 176 | end 177 | 178 | router 179 | layer1 metal 3 metal,pmc/metal,dmc/metal,glass 3 180 | layer2 poly 2 poly,efet,dfet,dcap,pmc,bc 2 diff,dmc 1 181 | contacts pmc 4 182 | gridspacing 7 183 | end 184 | 185 | plowing 186 | fixed efet,dfet,dcap,bc,glass 187 | covered efet,dfet,dcap,bc 188 | drag efet,dfet,dcap,bc 189 | end 190 | 191 | plot 192 | style versatec 193 | 194 | dfet,dcap \ 195 | 07c0 0f80 1f00 3e00 \ 196 | 7c00 f800 f001 e003 \ 197 | c007 800f 001f 003e \ 198 | 00c7 00f8 01f0 03e0 199 | 200 | efet,dcap \ 201 | 1f00 0f80 07c0 03e0 \ 202 | 01f0 00f8 007c 003e \ 203 | 001f 800f c007 e003 \ 204 | f001 f800 7c00 3e00 205 | 206 | bc \ 207 | c3c3 c3c3 0000 0000 \ 208 | 0000 0000 c3c3 c3c3 \ 209 | c3c3 c3c3 0000 0000 \ 210 | 0000 0000 c3c3 c3c3 211 | 212 | glass \ 213 | 0040 0080 0100 0200 \ 214 | 0400 0800 1000 2000 \ 215 | 4000 8000 0001 0002 \ 216 | 0004 0008 0010 0020 217 | 218 | diff,dmc,efet,dfet,dcap,bc \ 219 | 0000 4242 6666 0000 \ 220 | 0000 2424 6666 0000 \ 221 | 0000 4242 6666 0000 \ 222 | 0000 2424 6666 0000 223 | 224 | poly,pmc,efet,dfet,dcap,bc \ 225 | 0808 0400 0202 0101 \ 226 | 8080 4000 2020 1010 \ 227 | 0808 0004 0202 0101 \ 228 | 8080 0040 2020 1010 229 | 230 | metal,dmc,pmc,glass \ 231 | 8080 0000 0000 0000 \ 232 | 0808 0000 0000 0000 \ 233 | 8080 0000 0000 0000 \ 234 | 0808 0000 0000 0000 235 | 236 | glass \ 237 | 0000 0000 1c1c 3e3e \ 238 | 3636 3e3e 1c1c 0000 \ 239 | 0000 0000 1c1c 3e3e \ 240 | 3636 3e3e 1c1c 0000 241 | 242 | pmc,dmc X 243 | bc B 244 | 245 | style gremlin 246 | dfet,dcap 9 247 | efet,dcap 10 248 | bc 11 249 | glass 12 250 | diff,dmc/active,efet,dfet,dcap,bc 17 251 | poly,pmc/active,efet,dfet,dcap,bc 19 252 | metal,dmc,pmc,glass 22 253 | pmc,dmc X 254 | bc B 255 | end 256 | # * rcsid "$Header: nmos.tech,v 4.16 89/09/15 21:31:54 arnold Exp $" 257 | -------------------------------------------------------------------------------- /masks/6502/6502-run.spice: -------------------------------------------------------------------------------- 1 | * top-level ngspice script 2 | 3 | .control 4 | source 6502-system.spice 5 | tran 2ns 150us 6 | write 6502-spice-rawfile.raw 7 | .endc 8 | 9 | .end 10 | -------------------------------------------------------------------------------- /masks/6502/6502-system.spice: -------------------------------------------------------------------------------- 1 | * 6502 circuit simulation 2 | 3 | * FET models 4 | 5 | .model efet NMOS level=1 vt0=1.0 6 | .model dfet NMOS level=1 vt0=-3.0 7 | 8 | * handle floating nodes 9 | 10 | .option rshunt = 1.0e12 11 | 12 | * supply voltages 13 | 14 | v0 gnd! 0 dc 0 15 | v1 Vdd 0 dc 5 16 | 17 | * pull down the data bus to supply 0x00 for reads and allow writes to be seen 18 | 19 | r0 db0 0 10k 20 | r1 db1 0 10k 21 | r2 db2 0 10k 22 | r3 db3 0 10k 23 | r4 db4 0 10k 24 | r5 db5 0 10k 25 | r6 db6 0 10k 26 | r7 db7 0 10k 27 | 28 | * pin settings, reset pulse, clock waveform 29 | 30 | v10 res 0 pulse (0 5 20u 2n 2n) 31 | v11 so 0 dc 0 32 | v12 rdy 0 dc 5 33 | v13 nmi 0 dc 5 34 | v14 irq 0 dc 5 35 | v15 clk0 0 pulse (0 5 10n 2n 2n 2u 4u) 36 | 37 | * the 6502 model 38 | 39 | .include "6502.spice" 40 | 41 | .end 42 | -------------------------------------------------------------------------------- /masks/6502/6502.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/6502.gds -------------------------------------------------------------------------------- /masks/6502/Makefile: -------------------------------------------------------------------------------- 1 | include ../rules.make 2 | 3 | all: 6502.cif 6502.gds 6502.spice 4 | 5 | PNGS = buried.png contact.png diffusion.png metal.png poly.png implant.png 6 | NAME = 6502 7 | # scale (in microns per pixel) of the png files (must be a multiple of 0.002): 8 | SCALE = 0.940 9 | 10 | sim: 6502-run.spice 6502-system.spice 6502.spice 11 | ngspice --batch 6502-run.spice 12 | 13 | nodes.txt: 6502Node-subsplits.svg 14 | ./polygon2label.py <6502Node-subsplits.svg >nodes.txt 15 | 16 | 6502.cif: $(PNGS) nodes.txt pads.txt 17 | ../tools/png2cif.py $(NAME) $(SCALE) >6502.cif 18 | 19 | 6502.gds: $(PNGS) 20 | ../tools/png2gds.py $(NAME) $(SCALE) >6502.gds 21 | 22 | implant.polygon: pullups.js 23 | ./make_implant_polygons.py implant.polygon 24 | 25 | clean: 26 | rm -f $(PNGS) *.cif *.gds *.ext *~ 27 | rm -f 6502.spice 6502.ext 6502.feedback 28 | rm -f magic.log magic.log2 29 | rm -f ext2spice.log ext2spice.log2 30 | rm -f nodes.txt 31 | rm -f 6502-spice-rawfile.raw 32 | rm -f implant.polygon 33 | -------------------------------------------------------------------------------- /masks/6502/README: -------------------------------------------------------------------------------- 1 | Data sources: 2 | 3 | 6502.svg, 6502Node.svg, pullups.js: Barry Silverman (derived from polygon data) 4 | dep: Segher Boessenkool (list of probable additional depletion transistors) 5 | 6 | notes on chip scale: 7 | 8 | slide 20 in SIGGRAPH presentation: 9 | ~820 pixels per inch, derived from pin spacing of 0.1" and 0.6" 10 | results in a 6502 die size of 3.28 mm by 3.66 mm 11 | 12 | high-res 6502 photos: 13 | about 0.73 microns per pixel 14 | 15 | bitmap scale: 16 | about 0.94 microns per pixel 17 | -------------------------------------------------------------------------------- /masks/6502/apply-tweak.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | import string 5 | import re 6 | 7 | def read_tweaks(filename): 8 | tlist = [] 9 | f = open(filename,"r") 10 | for x in f.readlines(): 11 | s = string.split(x) 12 | tlist.append((s[0],s[1])) 13 | f.close() 14 | return tlist 15 | 16 | z = re.compile(r'.*points="(.*)".*') 17 | t = z.match(s) 18 | t = t.group(1) 19 | t = string.replace(t,',',' ') 20 | r = string.split(t,' ') 21 | n = len(r)/2 22 | p = [] 23 | for i in xrange(0,n): 24 | x = int(r[2*i]) 25 | y = int(r[2*i+1]) 26 | p.append((x,y)) 27 | if s.count('black'): # 'negative polygon' 28 | color = 1 29 | else: 30 | color = 0 31 | return p,color 32 | 33 | 34 | tlist = read_tweaks(sys.argv[1]) 35 | 36 | x = sys.stdin.read() 37 | 38 | for (old,new) in tlist: 39 | n = x.count(old) 40 | if n!=1: 41 | sys.stderr.write('not exactly one instance of '+old+'\n') 42 | sys.exit(1) 43 | x = x.replace(old,new) 44 | 45 | sys.stdout.write(x) 46 | -------------------------------------------------------------------------------- /masks/6502/buried.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/buried.png -------------------------------------------------------------------------------- /masks/6502/chip.tech: -------------------------------------------------------------------------------- 1 | 6502-nmos.tech -------------------------------------------------------------------------------- /masks/6502/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/contact.png -------------------------------------------------------------------------------- /masks/6502/dep: -------------------------------------------------------------------------------- 1 | upnode n322 \ A DEP 2 | upnode n999 \ A DEP 3 | upnode n475 \ A DEP 4 | upnode n855 \ A DEP 5 | upnode n1468 \ DPC DEP 6 | upnode n801 \ DPC DEP 7 | upnode n710 \ phi1 DEP 8 | upnode n417 \ SYNC DEP 9 | upnode n1191 \ A DEP 10 | upnode n1608 \ A DEP 11 | upnode n414 \ DPC DEP 12 | upnode n994 \ A DEP 13 | upnode n7 \ D DEP 14 | upnode n48 \ DPC DEP 15 | upnode n210 \ A DEP 16 | upnode n863 \ DPC DEP 17 | upnode n359 \ A DEP 18 | upnode n1072 \ D DEP 19 | upnode n140 \ DPC DEP 20 | upnode n1666 \ DPC DEP 21 | upnode n86 \ A DEP 22 | upnode n654 \ DPC DEP 23 | upnode n1417 \ PHI1 DEP 24 | upnode n549 \ DPC DEP 25 | upnode n102 \ R/#W DEP 26 | upnode n203 \ DPC DEP 27 | upnode n639 \ DPC DEP 28 | upnode n1068 \ DPC DEP 29 | upnode n1247 \ #phi1 DEP 30 | upnode n325 \ DPC DEP 31 | upnode n1479 \ A DEP 32 | upnode n1564 \ DPC DEP 33 | upnode n1331 \ DPC DEP 34 | upnode n676 \ A DEP 35 | upnode n1100 \ A DEP 36 | upnode n869 \ A DEP 37 | upnode n859 \ DPC DEP 38 | upnode n1536 \ #T0 DEP 39 | upnode n1201 \ DPC DEP 40 | upnode n898 \ DPC DEP 41 | upnode n66 \ A DEP 42 | upnode n1186 \ DPC DEP 43 | upnode n1639 \ A DEP 44 | upnode n1698 \ DPC DEP 45 | upnode n1235 \ DPC DEP 46 | upnode n138 \ A DEP 47 | upnode n437 \ DPC DEP 48 | upnode n1105 \ phi1 DEP 49 | upnode n1060 \ DPC DEP 50 | upnode n1696 \ R/#W DEP 51 | upnode n1633 \ A DEP 52 | upnode n1015 \ DPC DEP 53 | upnode n353 \ TRI DEP 54 | upnode n135 \ PHI2 DEP 55 | upnode n214 \ DPC DEP 56 | upnode n247 \ DPC DEP 57 | upnode n1163 \ PHI1 DEP 58 | upnode n283 \ DPC DEP 59 | upnode n1467 \ phi2 DEP 60 | upnode n1152 \ A DEP 61 | upnode n1700 \ DPC DEP 62 | upnode n1140 \ A DEP 63 | upnode n821 \ DPC DEP 64 | upnode n659 \ A DEP 65 | upnode n471 \ D DEP 66 | upnode n59 \ DPC DEP 67 | upnode n1545 \ A DEP 68 | upnode n963 \ A DEP 69 | upnode n1263 \ DPC DEP 70 | upnode n826 \ A DEP 71 | upnode n794 \ D DEP 72 | upnode n373 \ D DEP 73 | upnode n43 \ #phi1 DEP 74 | upnode n741 \ DPC DEP 75 | upnode n1254 \ A DEP 76 | upnode n9 \ DEAD PLA DEP 77 | upnode n634 \ A DEP 78 | upnode n1325 \ D DEP 79 | upnode n41 \ DPC DEP 80 | upnode n534 \ DPC DEP 81 | upnode n1076 \ D DEP 82 | upnode n984 \ DPC DEP 83 | upnode n642 \ A DEP 84 | upnode n42 \ D DEP 85 | upnode n298 \ D DEP 86 | upnode n574 \ DPC DEP 87 | upnode n1501 \ D DEP 88 | upnode n1296 \ A DEP 89 | upnode n171 \ A DEP 90 | upnode n129 \ DPC DEP 91 | upnode n438 \ DPC DEP 92 | upnode n421 \ PHI2 DEP 93 | upnode n874 \ DPC DEP 94 | upnode n943 \ phi2 DEP 95 | upnode n1041 \ A DEP 96 | upnode n381 \ A DEP 97 | upnode n147 \ D DEP 98 | upnode n37 \ D DEP 99 | upnode n520 \ D DEP 100 | upnode n362 \ DPC DEP 101 | upnode n643 \ D DEP 102 | upnode n798 \ D DEP 103 | upnode n248 \ RDY DEP 104 | upnode n635 \ A DEP 105 | upnode n612 \ D DEP 106 | upnode n921 \ DPC DEP 107 | -------------------------------------------------------------------------------- /masks/6502/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/diffusion.png -------------------------------------------------------------------------------- /masks/6502/diffusion.tweak: -------------------------------------------------------------------------------- 1 | 1129,383 1129,384 2 | 2952,377 2952,378 3 | 529,654 529,655 4 | 543,654 543,655 5 | 694,654 694,655 6 | 708,654 708,655 7 | 849,654 849,655 8 | 864,654 864,655 9 | 2002,703 2002,704 10 | 2016,703 2016,704 11 | 529,747 529,748 12 | 543,747 543,748 13 | 548,747 548,748 14 | 752,746 752,747 15 | 766,746 766,747 16 | 791,747 791,748 17 | 805,747 805,748 18 | 1789,749 1789,750 19 | 1802,749 1802,750 20 | 1886,749 1886,750 21 | 1905,749 1905,750 22 | 1919,749 1919,750 23 | 1925,750 1925,751 24 | 1939,750 1939,751 25 | 2088,750 2088,751 26 | 2102,750 2102,751 27 | 2603,751 2603,752 28 | 2617,751 2617,752 29 | 2825,751 2825,752 30 | 2839,751 2839,752 31 | 868,793 868,794 32 | 882,793 882,794 33 | 1944,796 1944,797 34 | 1958,796 1958,797 35 | 3000,798 3000,799 36 | 3014,798 3014,799 37 | 790,840 790,841 38 | 805,840 805,841 39 | 1052,840 1052,841 40 | 1066,840 1066,841 41 | 1847,886 1847,887 42 | 1958,887 1958,888 43 | 1964,887 1964,888 44 | 3000,889 3000,890 45 | 3014,889 3014,890 46 | 2560,2595 2560,2596 47 | 2648,2595 2648,2596 48 | -------------------------------------------------------------------------------- /masks/6502/implant.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/implant.png -------------------------------------------------------------------------------- /masks/6502/make_implant_polygons.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | 5 | def print_polygon(g): 6 | x1,x2,y1,y2 = g 7 | x1 = (4*x1/10) + 160 8 | x2 = (4*x2/10) + 160 9 | y1 = (4*(10000-y1)/10) 10 | y2 = (4*(10000-y2)/10) 11 | if x1>x2: 12 | x1,x2 = x2,x1 13 | if y1>y2: 14 | y1,y2 = y2,y1 15 | x1,x2 = x1-2 , x2+2 16 | y1,y2 = y1-2 , y2+2 17 | print '' % (x1,y1,x2,y1,x2,y2,x1,y2) 18 | 19 | for p in sys.stdin.readlines(): 20 | if p[0]!='[': 21 | continue 22 | p = eval(p[:-3]) 23 | gate = p[4] 24 | print_polygon(gate) 25 | -------------------------------------------------------------------------------- /masks/6502/mark_new_depletion.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | import string 5 | import re 6 | 7 | subs = {'vcc':'Vdd!', 'vss':'GND!'} 8 | 9 | nodenames = {} 10 | 11 | def sanitize(s): 12 | s = s.replace(r'.',r'_') 13 | s = s.replace(r'/',r'_') 14 | s = s.replace(r'+',r'_') 15 | s = s.replace(r'-',r'_') 16 | s = s.replace(r'#',r'n') 17 | s = s.replace(r'(',r'_') 18 | s = s.replace(r')',r'_') 19 | if s[0] in ['0','1','2','3','4','5','6','7','8','9']: 20 | s = 'n_' + s 21 | if nodenames.has_key(s): 22 | s = nodenames[s] 23 | if subs.has_key(s): 24 | s = subs[s] 25 | return s 26 | 27 | def read_nodenames(filename): 28 | r = [] 29 | f = open(filename,'r') 30 | for x in f.readlines(): 31 | m = re.match(r"(\w+):[ ]*(\d+),.*",x) 32 | if not m: 33 | m = re.match(r'"(.+)":[ ]*(\d+),.*',x) 34 | if m: 35 | name = sanitize(m.group(1)) 36 | node = sanitize(m.group(2)) 37 | if name[0]=='t': 38 | name = '_'+name 39 | nodenames[node] = name 40 | f.close() 41 | 42 | def dep_nodes(): 43 | r = [] 44 | f = open("dep") 45 | for x in f.readlines(): 46 | x = string.split(x) 47 | node = x[1] 48 | node = node[1:] 49 | node = sanitize(node) 50 | r.append(node) 51 | f.close() 52 | return r 53 | 54 | read_nodenames("../../visual6502/nodenames.js") 55 | deps = dep_nodes() 56 | 57 | for x in sys.stdin.readlines(): 58 | if x[0]=='M': 59 | y = string.split(x) 60 | g,s,d = y[2],y[1],y[3] 61 | if d!='Vdd': 62 | s,d = d,s 63 | if d=='Vdd' and s in deps: 64 | x = x.replace('efet','dfet') 65 | sys.stdout.write(x) 66 | -------------------------------------------------------------------------------- /masks/6502/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/metal.png -------------------------------------------------------------------------------- /masks/6502/pads.txt: -------------------------------------------------------------------------------- 1 | GND! 1487 133 NM ; pin 1 2 | pad_rdy 1308 131 NM ; pin 2 3 | pad_clk1out 943 134 NM ; pin 3 4 | pad_irq 764 130 NM ; pin 4 5 | pad_nc1 585 131 NM 6 | pad_nmi 314 129 NM ; pin 6 7 | pad_sync 428 1442 NM ; pin 7 8 | Vdd! 428 1757 NM ; pin 8 9 | pad_ab0 309 2037 NM ; pin 9 10 | pad_ab1 309 2583 NM ; pin 10 11 | pad_ab2 309 2781 NM ; pin 11 12 | pad_ab3 309 2980 NM ; pin 12 13 | pad_ab4 309 3178 NM ; pin 13 14 | pad_ab5 309 3375 NM ; pin 14 15 | pad_ab6 309 3579 NM ; pin 15 16 | pad_ab7 420 3866 NM ; pin 16 17 | pad_ab8 843 3866 NM ; pin 17 18 | pad_ab9 1028 3863 NM ; pin 18 19 | pad_ab10 1422 3866 NM ; pin 19 20 | pad_ab11 1607 3864 NM ; pin 20 21 | GND! 1881 3864 NM ; pin 21 22 | pad_ab12 2153 3867 NM ; pin 22 23 | pad_ab13 2338 3866 NM ; pin 23 24 | pad_ab14 2735 3867 NM ; pin 24 25 | pad_ab15 3044 3869 NM ; pin 25 26 | pad_db7 3691 3811 NM ; pin 26 27 | pad_db6 3691 3611 NM ; pin 27 28 | pad_db5 3691 3400 NM ; pin 28 29 | pad_db4 3691 3201 NM ; pin 29 30 | pad_db3 3695 2803 NM ; pin 30 31 | pad_db2 3694 2624 NM ; pin 31 32 | pad_db1 3694 2447 NM ; pin 32 33 | pad_db0 3700 331 NM ; pin 33 34 | pad_rw 3700 136 NM ; pin 34 35 | pad_nc2 3260 138 NM 36 | pad_clk0 3076 136 NM ; pin 37 37 | pad_so 2238 138 NM ; pin 38 38 | pad_clk2out 1842 134 NM ; pin 39 39 | pad_res 1663 135 NM ; pin 40 40 | 41 | testpad_1 260 2161 NM 42 | testpad_2 340 2161 NM 43 | testpad_3 260 2240 NM 44 | testpad_4 341 2236 NM 45 | testpad_5 260 2314 NM 46 | testpad_6 339 2312 NM 47 | testpad_7 259 2386 NM 48 | testpad_8 340 2386 NM 49 | 50 | testpad_9 3689 2944 NM 51 | testpad_10 3690 3068 NM 52 | -------------------------------------------------------------------------------- /masks/6502/poly.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6502/poly.png -------------------------------------------------------------------------------- /masks/6502/polygon2label.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import re 4 | import string 5 | #import cairo 6 | 7 | subs = {'vcc':'Vdd!', 'vss':'GND!'} 8 | 9 | nodenames = {} 10 | 11 | def sanitize(s): 12 | s = s.replace(r'.',r'_') 13 | s = s.replace(r'/',r'_') 14 | s = s.replace(r'+',r'_') 15 | s = s.replace(r'-',r'_') 16 | s = s.replace(r'#',r'n') 17 | s = s.replace(r'(',r'_') 18 | s = s.replace(r')',r'_') 19 | if s[0] in ['0','1','2','3','4','5','6','7','8','9']: 20 | s = 'n_' + s 21 | if nodenames.has_key(s): 22 | s = nodenames[s] 23 | if subs.has_key(s): 24 | s = subs[s] 25 | return s 26 | 27 | def read_nodenames(filename): 28 | r = [] 29 | f = open(filename,'r') 30 | for x in f.readlines(): 31 | m = re.match(r"(\w+):[ ]*(\d+),.*",x) 32 | if not m: 33 | m = re.match(r'"(.+)":[ ]*(\d+),.*',x) 34 | if m: 35 | name = sanitize(m.group(1)) 36 | node = sanitize(m.group(2)) 37 | if name[0]=='t': 38 | name = '_'+name 39 | nodenames[node] = name 40 | f.close() 41 | 42 | def interior_point(p): 43 | return p[0] 44 | 45 | def parse_polygon(t): 46 | t = string.replace(t,',',' ') 47 | r = string.split(t,' ') 48 | n = len(r)/2 49 | p = [] 50 | for i in xrange(0,n): 51 | x = int(r[2*i]) 52 | y = int(r[2*i+1]) 53 | p.append((x,y)) 54 | return p 55 | 56 | def print_label(p,name,layer): 57 | (x,y) = p 58 | print '%s %d %d %s' % (name,x,y,layer) 59 | 60 | import sys 61 | 62 | read_nodenames("../../visual6502/nodenames.js") 63 | 64 | n = set([]) 65 | 66 | for m in re.finditer(r'([0-9]*)',sys.stdin.read()): 67 | p = m.group(1) 68 | node = sanitize(m.group(2)) 69 | if node not in n: 70 | n.add(node) 71 | print_label(interior_point(parse_polygon(p)),node,"ND") 72 | -------------------------------------------------------------------------------- /masks/6502/spice_readfile.m: -------------------------------------------------------------------------------- 1 | ## Copyright (C) 2005 Werner Hoch 2 | ## 3 | ## Octave is free software; you can redistribute it and/or modify it 4 | ## under the terms of the GNU General Public License as published by 5 | ## the Free Software Foundation; either version 2, or (at your option) 6 | ## any later version. 7 | ## 8 | ## Octave is distributed in the hope that it will be useful, but 9 | ## WITHOUT ANY WARRANTY; without even the implied warranty of 10 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 | ## General Public License for more details. 12 | ## 13 | ## You should have received a copy of the GNU General Public License 14 | ## along with Octave; see the file COPYING. If not, write to the Free 15 | ## Software Foundation, 59 Temple Place - Suite 330, Boston, MA 16 | ## 02111-1307, USA. 17 | 18 | ## -*- texinfo -*- 19 | ## @deftypefn {Function File} {[@var{data}, @var{colnames}, @var{struct}] =} spice_readfile (@var{x}, @var{mode}) 20 | ## Import a spice rawfile into octave. 21 | ## @var{data} holds the data of the spice file 22 | ## @var{colnames} cell that holds the column names (node names) of the data 23 | ## @var{struct} contains the whole header of the rawfile 24 | ## @var{filename} name of the spice rawfile 25 | ## @var{mode} mode name for future extensions 26 | ## @end deftypefn 27 | 28 | ## Author: Werner Hoch 29 | ## Description: importfilter for spice rawfiles 30 | 31 | function [data,colnames,struct] = spice_readfile(filename, mode) 32 | ## error handling 33 | if (nargin < 1) 34 | usage("spice_readfile(filename[,mode])"); 35 | endif 36 | 37 | if (nargin == 1) 38 | mode=0; 39 | endif 40 | 41 | if (mode > 1) 42 | error("spice_readfile: mode must be lower than 2"); 43 | endif 44 | 45 | [fid,msg]=fopen(filename,"r"); 46 | if (fid == -1) 47 | error("spice_readfile: file reading failed"); 48 | endif 49 | 50 | ## defaultvalues 51 | realflag=1; ## number type is real, not complex 52 | paddedflag=1; ## with zeros padded data 53 | binaryflag=1; ## binary data type 54 | s.no_points=0; 55 | s.no_variables=0; 56 | s.dimensions=0; 57 | s.commands={}; 58 | s.options={}; 59 | 60 | ## read the file header of the file 61 | ## these are colonseperated key/value pairs 62 | while ((line=fgets(fid)) != -1) 63 | line=deblank(strjust(line,"left")); 64 | linelength=length(line); 65 | 66 | if (linelength >= length("title:") && strcmp(lower(line(1:6)),"title:")) 67 | if (linelength==6) 68 | s.title=""; 69 | else 70 | s.title=deblank(strjust(line(7:length(line)),"left")); 71 | endif 72 | endif 73 | 74 | if (linelength >= length("date:") && strcmp(lower(line(1:5)),"date:")) 75 | if (linelength==5) 76 | s.date=""; 77 | else 78 | s.date=deblank(strjust(line(6:length(line)),"left")); 79 | endif 80 | endif 81 | 82 | if (linelength >= length("plotname:") 83 | && strcmp(lower(line(1:9)),"plotname:")) 84 | if (linelength==9) 85 | s.plotname=""; 86 | else 87 | s.plotname=deblank(strjust(line(10:length(line)),"left")) 88 | endif 89 | endif 90 | 91 | if (linelength >= length("flags:") 92 | && strcmp(lower(line(1:6)),"flags:")) 93 | if (linelength==6) 94 | s.flags={}; 95 | warning("spice_readfile: no flag given in file"); 96 | else 97 | [str{1},str{2},str{3},n]=sscanf(line(7:linelength)," %s %s %s","C"); 98 | s.flags=str(1,1:n); 99 | if (length(s.flags) > 2) 100 | warning("spice_readfile: to many flags given in file"); 101 | endif 102 | for i = 1:n 103 | if (strcmp(s.flags{i},"real")) 104 | realflag=1; 105 | elseif (strcmp(s.flags{i},"complex")) 106 | realflag=0; 107 | elseif (strcmp(s.flags{i},"padded")) 108 | paddedflag=1; 109 | elseif (strcmp(s.flag{i},"unpadded")) 110 | paddedflag=0; 111 | warning("spice_readfile: unpadded data not handled yet"); 112 | else 113 | warning("spice_readfile: unknown flag %s",s.flags{i}); 114 | endif 115 | endfor 116 | endif 117 | endif 118 | 119 | if (linelength >= length("no. variables:") 120 | && strcmp(lower(line(1:14)),"no. variables:")) 121 | if (linelength>14) 122 | [s.no_variables,n]=sscanf(line(15:linelength)," %d","C"); 123 | endif 124 | endif 125 | 126 | if (linelength >= length("no. points:") 127 | && strcmp(lower(line(1:11)),"no. points:")) 128 | if (linelength>11) 129 | [s.no_points,n]=sscanf(line(12:linelength)," %d","C"); 130 | endif 131 | endif 132 | 133 | if (linelength >= length("dimensions:") 134 | && strcmp(lower(line(1:11)),"dimensions:")) 135 | if (linelength>11) 136 | [s.dimensions,n]=sscanf(line(12:linelength)," %d,",[1,inf]); 137 | warning("spice_readfile: multiple dimensions not implemented yet"); 138 | endif 139 | endif 140 | 141 | if (linelength >= length("command:") 142 | && strcmp(lower(line(1:8)),"command:")) 143 | if (linelength>8) 144 | s.commands{length(s.commands)+1}=deblank(strjust(line(9:linelength), 145 | "left")); 146 | endif 147 | endif 148 | 149 | if (linelength >= length("option:") 150 | && strcmp(lower(line(1:7)),"option:")) 151 | if (linelength>7) 152 | s.options{length(s.commands)+1}=deblank(strjust(line(8:linelength), 153 | "left")); 154 | endif 155 | endif 156 | 157 | if (linelength >= length("variables:") 158 | && strcmp(lower(line(1:10)),"variables:")) 159 | s.variables=cell(s.no_variables,8); 160 | for i = 1:s.no_variables 161 | line = fgets(fid); 162 | [str{1},str{2},str{3},str{4},str{5},str{6},str{7},str{8},str{9},n]= \ 163 | sscanf(line," %s %s %s %s %s %s %s %s %s","C"); 164 | if (n < 3) 165 | error("spice_readfile: to few variable tokens given"); 166 | elseif (n > 8) 167 | warning("spice_readfile: to many variable tokens given"); 168 | n=8 169 | endif 170 | s.variables(i,1:n)=str(1:n); 171 | endfor 172 | endif 173 | 174 | if (strcmp(lower(line(1:7)),"values:")) 175 | binaryflag=0; 176 | ## data section begins, leave the header scanner 177 | break; 178 | endif 179 | if (strcmp(lower(line(1:7)),"binary:")) 180 | binaryflag=1; 181 | ## data section begins, leave the header scanner 182 | break; 183 | endif 184 | endwhile 185 | 186 | ## FIXME: unpadded data is not handled 187 | if (binaryflag==1 && realflag==1) 188 | data=fread(fid,[s.no_variables,inf],"float64",0); 189 | data=data'; 190 | elseif (binaryflag==0 && realflag==1) 191 | data=fscanf(fid," %e",[s.no_variables+1,inf]); 192 | data=data(2:s.no_variables+1,:)'; 193 | elseif (binaryflag==1 && realflag==0) 194 | data=fread(fid,[2*s.no_variables,inf],"float64",0); 195 | ## convert data from real and imaginary to complex 196 | data=data'; ## change row/columns before combining to complex 197 | for n = 1:s.no_variables 198 | data(:,n)=data(:,2*n-1)+1i.*data(:,2*n); 199 | endfor 200 | data=data(:,1:s.no_variables); 201 | else ## (binaryflag==0 && realflag==0) 202 | data=[]; 203 | while (1) 204 | [nr,n]=fscanf(fid,"%d","C"); 205 | if (n != 1) 206 | break; 207 | endif 208 | [vals,n]=fscanf(fid,"%e,%e",[2,s.no_variables]); 209 | if (n != 2*s.no_variables) 210 | break; 211 | else 212 | data=[data;vals(1,:)+1i*vals(2,:)]; ## !!slow implementation 213 | endif 214 | endwhile 215 | endif 216 | 217 | ## put the values together 218 | struct=s; 219 | colnames=s.variables(1:s.no_variables,2); 220 | fclose(fid); 221 | endfunction 222 | 223 | 224 | -------------------------------------------------------------------------------- /masks/6800/6800-klayout-screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/6800-klayout-screenshot.png -------------------------------------------------------------------------------- /masks/6800/6800-nmos.tech: -------------------------------------------------------------------------------- 1 | tech 2 | 6800-nmos 3 | end 4 | 5 | planes 6 | poly_diff,diff,active 7 | metal 8 | end 9 | 10 | types 11 | active polysilicon,poly,red 12 | active diffusion,diff,green 13 | metal metal,blue 14 | active poly_metal_contact,pmc 15 | active diff_metal_contact,dmc 16 | active enhancement_fet,efet 17 | active depletion_fet,dfet 18 | active depletion_capacitor,dcap 19 | active buried_contact,bc 20 | metal glass_contact,glass 21 | end 22 | 23 | styles 24 | styletype mos 25 | 26 | polysilicon 1 27 | diffusion 2 28 | metal 20 29 | enhancement_fet 6 30 | enhancement_fet 7 31 | depletion_fet 6 32 | depletion_fet 10 33 | depletion_capacitor 6 34 | depletion_capacitor 11 35 | buried_contact 6 36 | buried_contact 33 37 | poly_metal_contact 1 38 | poly_metal_contact 20 39 | poly_metal_contact 32 40 | diff_metal_contact 2 41 | diff_metal_contact 20 42 | diff_metal_contact 32 43 | glass_contact 20 44 | glass_contact 34 45 | 46 | error_s 42 47 | error_p 42 48 | error_ps 42 49 | 50 | magnet 39 51 | fence 38 52 | rotate 37 53 | end 54 | 55 | contact 56 | pmc poly metal 57 | dmc diff metal 58 | end 59 | 60 | compose 61 | compose efet poly diff 62 | decompose dfet poly diff 63 | decompose dcap poly diff 64 | decompose bc poly diff 65 | erase glass metal space 66 | end 67 | 68 | connect 69 | poly pmc,efet,dfet,dcap,bc 70 | diff bc,dmc 71 | efet pmc,dmc,bc,dfet,dcap 72 | dfet pmc,dmc,bc,dcap 73 | dcap pmc,dmc,bc 74 | pmc dmc,bc 75 | dmc bc 76 | metal glass,pmc,dmc 77 | glass pmc,dmc 78 | end 79 | 80 | cifoutput 81 | style lambda=2 82 | scalefactor 200 100 83 | layer NP poly,pmc,efet,dfet,dcap,bc 84 | labels poly,efet,dfet,dcap,bc 85 | calma 1 1 86 | layer ND diff,dmc,efet,dfet,dcap,bc 87 | labels diff 88 | calma 2 1 89 | layer NM metal,pmc,dmc,glass 90 | labels metal,pmc,dmc,glass 91 | calma 3 1 92 | layer NI 93 | bloat-or dfet,dcap * 200 diff,bc 400 94 | grow 100 95 | shrink 100 96 | calma 4 1 97 | layer NC dmc 98 | squares 400 99 | calma 5 1 100 | layer NC pmc 101 | squares 400 102 | calma 6 1 103 | layer NG glass 104 | calma 7 1 105 | layer NB 106 | bloat-or bc * 200 diff,dmc 400 dfet 0 107 | grow 100 108 | shrink 100 109 | calma 8 1 110 | end 111 | 112 | cifinput 113 | style lambda=2 114 | scalefactor 200 115 | layer poly NP 116 | labels NP 117 | layer diff ND 118 | labels ND 119 | layer metal NM 120 | labels NM 121 | layer efet NP 122 | and ND 123 | layer dfet NI 124 | and NP 125 | and ND 126 | layer pmc NC 127 | and NM 128 | and NP 129 | layer dmc NC 130 | and NM 131 | and ND 132 | layer bc NB 133 | and NP 134 | and ND 135 | layer glass NG 136 | end 137 | 138 | mzrouter 139 | style irouter 140 | layer metal 32 32 256 1 141 | layer poly 64 64 256 1 142 | contact pmc metal poly 1024 143 | end 144 | 145 | drc 146 | end 147 | 148 | extract 149 | style default 150 | lambda 200 151 | 152 | step 100 153 | 154 | resist poly,pmc/poly,efet,dfet,bc 30000 155 | resist diff,dmc/poly 10000 156 | resist metal,glass 30 157 | 158 | areacap poly,efet,dfet 200 159 | areacap metal,glass 120 160 | areacap diff 400 161 | areacap bc 600 162 | areacap dmc/poly 520 163 | areacap pmc/poly 320 164 | 165 | perimc diff,dmc/poly,bc space,dfet,efet 200 166 | 167 | fet efet diff 2 efet GND! 0 0 168 | fet dfet diff,bc 2 dfet GND! 0 0 169 | fet dcap diff,bc 1 dcap GND! 0 0 170 | end 171 | 172 | wiring 173 | contact pmc 4 metal 0 poly 0 174 | contact dmc 4 metal 0 diff 0 175 | contact bc 2 poly 0 diff 0 176 | end 177 | 178 | router 179 | layer1 metal 3 metal,pmc/metal,dmc/metal,glass 3 180 | layer2 poly 2 poly,efet,dfet,dcap,pmc,bc 2 diff,dmc 1 181 | contacts pmc 4 182 | gridspacing 7 183 | end 184 | 185 | plowing 186 | fixed efet,dfet,dcap,bc,glass 187 | covered efet,dfet,dcap,bc 188 | drag efet,dfet,dcap,bc 189 | end 190 | 191 | plot 192 | style versatec 193 | 194 | dfet,dcap \ 195 | 07c0 0f80 1f00 3e00 \ 196 | 7c00 f800 f001 e003 \ 197 | c007 800f 001f 003e \ 198 | 00c7 00f8 01f0 03e0 199 | 200 | efet,dcap \ 201 | 1f00 0f80 07c0 03e0 \ 202 | 01f0 00f8 007c 003e \ 203 | 001f 800f c007 e003 \ 204 | f001 f800 7c00 3e00 205 | 206 | bc \ 207 | c3c3 c3c3 0000 0000 \ 208 | 0000 0000 c3c3 c3c3 \ 209 | c3c3 c3c3 0000 0000 \ 210 | 0000 0000 c3c3 c3c3 211 | 212 | glass \ 213 | 0040 0080 0100 0200 \ 214 | 0400 0800 1000 2000 \ 215 | 4000 8000 0001 0002 \ 216 | 0004 0008 0010 0020 217 | 218 | diff,dmc,efet,dfet,dcap,bc \ 219 | 0000 4242 6666 0000 \ 220 | 0000 2424 6666 0000 \ 221 | 0000 4242 6666 0000 \ 222 | 0000 2424 6666 0000 223 | 224 | poly,pmc,efet,dfet,dcap,bc \ 225 | 0808 0400 0202 0101 \ 226 | 8080 4000 2020 1010 \ 227 | 0808 0004 0202 0101 \ 228 | 8080 0040 2020 1010 229 | 230 | metal,dmc,pmc,glass \ 231 | 8080 0000 0000 0000 \ 232 | 0808 0000 0000 0000 \ 233 | 8080 0000 0000 0000 \ 234 | 0808 0000 0000 0000 235 | 236 | glass \ 237 | 0000 0000 1c1c 3e3e \ 238 | 3636 3e3e 1c1c 0000 \ 239 | 0000 0000 1c1c 3e3e \ 240 | 3636 3e3e 1c1c 0000 241 | 242 | pmc,dmc X 243 | bc B 244 | 245 | style gremlin 246 | dfet,dcap 9 247 | efet,dcap 10 248 | bc 11 249 | glass 12 250 | diff,dmc/active,efet,dfet,dcap,bc 17 251 | poly,pmc/active,efet,dfet,dcap,bc 19 252 | metal,dmc,pmc,glass 22 253 | pmc,dmc X 254 | bc B 255 | end 256 | # * rcsid "$Header: nmos.tech,v 4.16 89/09/15 21:31:54 arnold Exp $" 257 | -------------------------------------------------------------------------------- /masks/6800/6800.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/6800.gds -------------------------------------------------------------------------------- /masks/6800/Makefile: -------------------------------------------------------------------------------- 1 | include ../rules.make 2 | 3 | all: 6800.cif 6800.gds 6800.spice 4 | 5 | PNGS = buried.png contact.png diffusion.png metal.png poly.png 6 | NAME = 6800 7 | # scale (in microns per pixel) of the png files (must be a multiple of 0.002): 8 | SCALE = 1.000 9 | 10 | poly.png: poly.svg 11 | pbmmake -white 3 3 >t3.pbm 12 | <$< ../tools/svg2png.py 6500 6280 13 | $@ 14 | rm -f out.png 15 | rm -f t3.pbm 16 | 17 | diffusion.png: diffusion.svg 18 | pbmmake -white 3 3 >t3.pbm 19 | <$< ../tools/svg2png.py 6500 6280 20 | $@ 21 | rm -f out.png 22 | rm -f t3.pbm 23 | 24 | 6800.cif: $(PNGS) 25 | ../tools/png2cif.py $(NAME) $(SCALE) >6800.cif 26 | 27 | 6800.gds: $(PNGS) 28 | ../tools/png2gds.py $(NAME) $(SCALE) >6800.gds 29 | 30 | clean: 31 | rm -f $(PNGS) *.cif *.gds *.ext *~ 32 | rm -f 6800.spice 6800.ext 6800.feedback 33 | rm -f magic.log magic.log2 34 | rm -f ext2spice.log ext2spice.log2 35 | -------------------------------------------------------------------------------- /masks/6800/buried.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/buried.png -------------------------------------------------------------------------------- /masks/6800/chip.tech: -------------------------------------------------------------------------------- 1 | 6800-nmos.tech -------------------------------------------------------------------------------- /masks/6800/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/contact.png -------------------------------------------------------------------------------- /masks/6800/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/diffusion.png -------------------------------------------------------------------------------- /masks/6800/jorge-6800.spice: -------------------------------------------------------------------------------- 1 | spice-netlist.txt -------------------------------------------------------------------------------- /masks/6800/mc6800a-layout-notes.txt: -------------------------------------------------------------------------------- 1 | 2 | Attached in the archive are files that are the result of reverse engineering a MC6800A die. This was done based on microphotos taken and stitched by members of the Visual 6502 team. Included is the extracted layout in SVG form, and the netlist in Spice like compatible format. The Layout is included in PDF form as well, but note that colors and transparency styles might be slightly different. 3 | 4 | 5 | Circuit notes: 6 | 7 | There seems to be at least one case with charge sharing. I remember the conversation about this happening in the 6502, and I understand that the simulator currently make a simple shortcut favoring a positive charge in these cases. I don't think this will work here. Simulation would need to consider which "side" has the bigger capacitance. This data is currently not provided in the netlist. 8 | 9 | The data bus input buffers use a strange "refresh" logic. The latch is not completely dynamic, but it is not a standard static latch either. The feedback is applied only when the data latched is a logic one. This is implemented with a conditional enhancement pullup. I assume the idea is that a dynamic cell with a logic one would eventually discharge, but a logic zero would never recharge itself? From the point of view of simulation, this is one of the few cases where it is critical to realize it is an enhacement, and not a depletion FET pullup. 10 | 11 | The register file also use an unusual static feedback logic. The feedback to the latch is enabled all the time, only that it goes through a resisitive (long channel) transistor. So that when a new value is being latched, it overrides the weak feedback. Otherwise, the weak feedback is enough for refreshing the static latch. 12 | 13 | The transistor count matches our earlier assumption. It is indeed ~5100 (including multiple fingers), with about 1000 being pullups. So the 4000 figure in the original enhancement load version didn't count the pullups. 14 | 15 | 16 | 17 | SVG layout notes: 18 | 19 | There was no attempt to reproduce the exact shape of the metal contacts accurately. They are just an ideal circle, all of the same size. 20 | 21 | All metal polygons are in the same layer/group. Power rails are not separated. 22 | 23 | I didn't bother including all the test polygons that aren't part of the circuit. I did care to include the marks that identify the die. 24 | 25 | 26 | 27 | Simulation notes: 28 | 29 | There is a small problem to provide files for visual simulation. I understand that there is currently no way to describe polygons with holes. So this should be fixed, or I might try some cheating, by converting a polygon with holes, into multiple adjacent ones without holes. 30 | 31 | I understand that simulation would also need to be enhanced for the resistive feedback. And we also need to somehow mark these transistors as having the higher resistance. 32 | 33 | I performed just a basic, minimal, testing with actual code. 34 | 35 | 36 | Jorge Cwik 37 | -------------------------------------------------------------------------------- /masks/6800/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/metal.png -------------------------------------------------------------------------------- /masks/6800/poly.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/6800/poly.png -------------------------------------------------------------------------------- /masks/Makefile: -------------------------------------------------------------------------------- 1 | all: 2 | ( cd 4001 ; make ) 3 | ( cd 4002 ; make ) 4 | ( cd 4003 ; make ) 5 | ( cd 4004 ; make ) 6 | ( cd 6502 ; make ) 7 | 8 | clean: 9 | ( cd 4001 ; make clean ) 10 | ( cd 4002 ; make clean ) 11 | ( cd 4003 ; make clean ) 12 | ( cd 4004 ; make clean ) 13 | ( cd 6502 ; make clean ) 14 | -------------------------------------------------------------------------------- /masks/README: -------------------------------------------------------------------------------- 1 | Source data: 2 | 3 | 6502: 4 | 5 | http://www.visual6502.org 6 | 7 | 4001, 4002, 4003, 4004: 8 | 9 | http://www.4004.com 10 | http://www.4004.com/2009/i400x_analyzer20091114.zip 11 | 12 | 4004 die size: 13 | http://www.tomshardware.com/forum/298905-28-intel-4004 14 | http://t1.gstatic.com/images?q=tbn:ANd9GcS4bS76Y7aJZjaLz6W0qEReU_7AJX9aK2H9MfwYFgdYNQkpAQNp 15 | the wafers are 300 mm and 50.8 mm 16 | the chip dimensions from scribe line to scribe line are about 2.95 mm by 4.04 mm give or take ~1% 17 | 18 | 4001 die size: 19 | http://www.cpu-zone.com/4001/Intel%204001%20wafer.JPG 20 | http://www.cpu-zone.com/4001.htm 21 | the wafer is 3 inch (76.2 mm) 22 | the chip dimensions from scribe line to scribe line are about 2.62 mm by 4.02 mm give or take ~1% 23 | 24 | 4002 and 4003 image scales: 25 | can't find any wafer or die-with-package shots 26 | derived assuming their pad dimensions are the same as 4004 and 4001 (~123 microns) 27 | 28 | 6800: 29 | posting to 6502hackers by jorge@rahul.net on 2011-03-27 30 | files included here: 31 | mc6800a-layout-notes.txt 32 | mc6800a-layout.svg 33 | spice-netlist.txt 34 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/Makefile: -------------------------------------------------------------------------------- 1 | all: netlist.v 2 | 3 | netlist.txt: pins.txt metal.png diffusion.png contact.png gate.png implant.png 4 | ./masks_to_netlist.py pins.txt metal.png diffusion.png contact.png gate.png implant.png >netlist.txt 5 | 6 | netlist.v: netlist.txt 7 | ./netlist_to_verilog.py netlist.v 8 | 9 | sim: testbench.v netlist.v 10 | iverilog testbench.v netlist.v 11 | ./a.out 12 | 13 | clean: 14 | rm -f netlist.txt netlist.v a.out *~ 15 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/contact.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/hp35-bitmap-tools/contact.png -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/diffusion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/hp35-bitmap-tools/diffusion.png -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/gate.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/hp35-bitmap-tools/gate.png -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/gimp-extract-layers.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # place this in your ~/.gimp-2.6/plug-ins directory 4 | 5 | from gimpfu import * 6 | 7 | def extract_layers(timg, tdrawable): 8 | x = timg.width 9 | y = timg.height 10 | 11 | layer = {} 12 | for l in timg.layers: 13 | layer[l.name] = l 14 | 15 | for x in ['metal','diffusion','gate','contact','implant','pad']: 16 | timg.active_layer = layer[x] 17 | pdb.gimp_edit_copy(timg.active_layer) 18 | img = pdb.gimp_edit_paste_as_new() 19 | img.disable_undo() 20 | pdb.gimp_image_convert_grayscale(img) 21 | pdb.gimp_image_flatten(img) 22 | pdb.gimp_threshold(img.layers[0],0,127) 23 | filename = x+'.png' 24 | pdb.gimp_file_save(img, img.active_layer, filename, filename) 25 | 26 | register( 27 | "extract_layers", 28 | "Extract individual layers from a multilayer image", 29 | "Extract individual layers from a multilayer image", 30 | "Peter Monta", 31 | "Peter Monta", 32 | "2010", 33 | "/_Xtns/_Extract Layers", 34 | "", 35 | [], 36 | [], 37 | extract_layers) 38 | 39 | main() 40 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/implant.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/hp35-bitmap-tools/implant.png -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/masks_to_netlist.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | # 4 | # masks_to_netlist.py pins.txt metal.png diffusion.png contact.png gate.png implant.png >netlist.txt 5 | # 6 | # Convert mask images to a transistor netlist. Currently specific to PMOS or NMOS metal-gate processes. 7 | # 8 | # Peter Monta 9 | # November 2010 10 | # 11 | 12 | import scipy 13 | from scipy import ndimage 14 | import readmagick 15 | import sys 16 | import string 17 | 18 | # 19 | # read the list of pins. Each line is of the form " ". 20 | # 21 | 22 | pins = {} 23 | 24 | f = open(sys.argv[1],"r") 25 | for x in f.readlines(): 26 | l = string.split(x) 27 | name,x,y = l[0],int(l[1]),int(l[2]) 28 | pins[name] = (x,y) 29 | f.close() 30 | 31 | # 32 | # read in the mask bitmaps and label them 33 | # 34 | 35 | metal,metal_n = ndimage.label(readmagick.readimg(sys.argv[2])) 36 | diffusion,diffusion_n = ndimage.label(readmagick.readimg(sys.argv[3])) 37 | contact,contact_n = ndimage.label(readmagick.readimg(sys.argv[4])) 38 | gate,gate_n = ndimage.label(readmagick.readimg(sys.argv[5])) 39 | implant,implant_n = ndimage.label(readmagick.readimg(sys.argv[6])) 40 | 41 | print '# metal: %d objects' % metal_n 42 | print '# diffusion: %d objects' % diffusion_n 43 | print '# contact: %d objects' % contact_n 44 | print '# gate: %d objects' % gate_n 45 | print '# implant: %d objects' % implant_n 46 | 47 | # 48 | # emit "pin" objects that intersect metal or diffusion 49 | # 50 | 51 | for p in pins.keys(): 52 | x,y = pins[p] 53 | node = metal[y][x] 54 | prefix = 'm' 55 | if node==0: 56 | node = diffusion[y][x] 57 | prefix = 'd' 58 | print 'p %s %s%d' % (p,prefix,node) 59 | 60 | # 61 | # emit "contact" objects by intersecting contact layer with metal and diffusion 62 | # 63 | 64 | contacts = {} 65 | 66 | for j,c in enumerate(ndimage.find_objects(contact)): 67 | i = j+1 68 | contact_mask = contact[c]==i 69 | metal_objs = set((contact_mask*metal[c]).flat) - set([0]) 70 | diffusion_objs = set((contact_mask*diffusion[c]).flat) - set([0]) 71 | if len(metal_objs)!=1 or len(diffusion_objs)!=1: 72 | print '# invalid contact %d: intersects metal %s and diffusion %s' % (i,str(metal_objs),str(diffusion_objs)) 73 | continue 74 | metal_i,diffusion_i = metal_objs.pop(),diffusion_objs.pop() 75 | contacts[i] = (metal_i,diffusion_i) 76 | print 'c m%d d%d' % (metal_i,diffusion_i) 77 | 78 | # 79 | # emit "transistor" objects by intersecting gate layer with diffusion and implant 80 | # 81 | 82 | transistors = {} 83 | 84 | for j,c in enumerate(ndimage.find_objects(gate)): 85 | i = j+1 86 | gate_mask = gate[c]==i 87 | metal_objs = set((gate_mask*metal[c]).flat) - set([0]) 88 | if len(metal_objs)!=1: 89 | print '# invalid gate %d: intersects metal %s' % (i,str(metal_objs)) 90 | continue 91 | metal_i = metal_objs.pop() 92 | implant_objs = set((gate_mask*implant[c]).flat) 93 | if len(implant_objs)!=1: 94 | print '# invalid gate %d: intersects implant %s' % (i,str(implant_objs)) 95 | continue 96 | implant_i = implant_objs.pop() 97 | transistor_type = 'e' if implant_i==0 else 'd' 98 | diffusion_objs = set((gate_mask*diffusion[c]).flat) - set([0]) 99 | if len(diffusion_objs)==1: 100 | print '# gate %d has single diffusion (MOS capacitor?)' % i 101 | continue 102 | elif len(diffusion_objs)!=2: 103 | print '# invalid gate %d: intersects diffusion %s' % (i,str(diffusion_objs)) 104 | continue 105 | gate_i = metal_i 106 | source_i = diffusion_objs.pop() 107 | drain_i = diffusion_objs.pop() 108 | transistors[i] = (gate_i,source_i,drain_i,transistor_type) 109 | print 't m%d d%d d%d %s' % (gate_i,source_i,drain_i,transistor_type) 110 | 111 | # 112 | # print orphans 113 | # 114 | 115 | r_metal = set(range(1,metal_n+1)) 116 | r_diffusion = set(range(1,diffusion_n+1)) 117 | r_contact = set(range(1,contact_n+1)) 118 | r_gate = set(range(1,gate_n+1)) 119 | 120 | for c in contacts.keys(): 121 | r_contact.discard(c) 122 | metal_i,diffusion_i = contacts[c] 123 | r_metal.discard(metal_i) 124 | r_diffusion.discard(diffusion_i) 125 | 126 | for g in transistors.keys(): 127 | r_gate.discard(g) 128 | (gate,source,drain,transistor_type) = transistors[g] 129 | r_metal.discard(gate) 130 | r_diffusion.discard(source) 131 | r_diffusion.discard(drain) 132 | 133 | print '# metal orphans: ',r_metal 134 | print '# diffusion orphans: ',r_diffusion 135 | print '# contact orphans: ',r_contact 136 | print '# gate orphans: ',r_gate 137 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/metal.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/hp35-bitmap-tools/metal.png -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/netlist.txt: -------------------------------------------------------------------------------- 1 | # metal: 109 objects 2 | # diffusion: 122 objects 3 | # contact: 160 objects 4 | # gate: 168 objects 5 | # implant: 0 objects 6 | p Vss m3 7 | p phi1 m2 8 | p Gnd2 m11 9 | p sync d1 10 | p z4 m69 11 | p phi2 m1 12 | p Gnd m39 13 | p y1 m109 14 | p y0 m95 15 | p x0 m67 16 | p x1 m77 17 | p z0 m94 18 | p z1 m88 19 | p z2 m78 20 | p z3 m74 21 | c m1 d2 22 | c m2 d3 23 | c m5 d4 24 | c m4 d5 25 | c m6 d7 26 | c m7 d8 27 | c m7 d10 28 | c m8 d11 29 | c m3 d12 30 | c m11 d14 31 | c m9 d13 32 | c m13 d17 33 | c m12 d18 34 | c m13 d15 35 | c m14 d13 36 | c m10 d21 37 | c m5 d20 38 | c m15 d22 39 | c m3 d9 40 | c m16 d23 41 | c m17 d2 42 | c m18 d24 43 | c m3 d25 44 | c m20 d22 45 | c m19 d26 46 | c m21 d3 47 | c m3 d27 48 | c m3 d16 49 | c m23 d26 50 | c m24 d31 51 | c m27 d28 52 | c m26 d1 53 | c m25 d32 54 | c m29 d29 55 | c m30 d33 56 | c m3 d30 57 | c m31 d5 58 | c m32 d7 59 | c m34 d18 60 | c m35 d23 61 | c m33 d11 62 | c m3 d6 63 | c m39 d37 64 | c m40 d36 65 | c m42 d31 66 | c m41 d39 67 | c m18 d40 68 | c m3 d34 69 | c m36 d39 70 | c m37 d38 71 | c m28 d8 72 | c m38 d20 73 | c m46 d21 74 | c m45 d15 75 | c m43 d41 76 | c m18 d35 77 | c m47 d19 78 | c m11 d43 79 | c m3 d46 80 | c m39 d49 81 | c m51 d48 82 | c m44 d45 83 | c m50 d44 84 | c m31 d47 85 | c m47 d51 86 | c m52 d52 87 | c m39 d42 88 | c m53 d53 89 | c m54 d56 90 | c m3 d50 91 | c m39 d54 92 | c m49 d53 93 | c m39 d55 94 | c m48 d59 95 | c m56 d56 96 | c m39 d60 97 | c m57 d58 98 | c m58 d61 99 | c m3 d62 100 | c m11 d64 101 | c m39 d57 102 | c m35 d65 103 | c m60 d66 104 | c m59 d63 105 | c m61 d67 106 | c m62 d68 107 | c m64 d68 108 | c m3 d70 109 | c m65 d66 110 | c m63 d71 111 | c m67 d73 112 | c m66 d72 113 | c m39 d74 114 | c m3 d75 115 | c m34 d76 116 | c m55 d76 117 | c m69 d72 118 | c m39 d77 119 | c m71 d78 120 | c m72 d76 121 | c m70 d73 122 | c m3 d79 123 | c m74 d78 124 | c m73 d80 125 | c m76 d81 126 | c m68 d82 127 | c m3 d69 128 | c m77 d80 129 | c m78 d81 130 | c m33 d84 131 | c m32 d86 132 | c m3 d83 133 | c m31 d85 134 | c m35 d88 135 | c m79 d87 136 | c m80 d90 137 | c m39 d89 138 | c m82 d88 139 | c m22 d91 140 | c m75 d92 141 | c m83 d84 142 | c m85 d93 143 | c m84 d93 144 | c m3 d94 145 | c m87 d86 146 | c m87 d96 147 | c m88 d90 148 | c m89 d98 149 | c m3 d99 150 | c m3 d95 151 | c m90 d100 152 | c m21 d100 153 | c m92 d101 154 | c m86 d102 155 | c m94 d98 156 | c m93 d103 157 | c m3 d107 158 | c m81 d104 159 | c m100 d86 160 | c m99 d85 161 | c m97 d103 162 | c m95 d110 163 | c m91 d111 164 | c m101 d113 165 | c m98 d108 166 | c m102 d109 167 | c m104 d105 168 | c m103 d97 169 | c m105 d115 170 | c m107 d112 171 | c m39 d114 172 | c m106 d106 173 | c m105 d116 174 | c m27 d117 175 | c m108 d112 176 | c m109 d121 177 | c m109 d119 178 | c m39 d122 179 | c m39 d118 180 | c m39 d120 181 | t m6 d4 d6 e 182 | t m8 d4 d6 e 183 | t m10 d9 d15 e 184 | t m9 d13 d14 e 185 | t m10 d8 d9 e 186 | t m13 d9 d19 e 187 | t m12 d16 d10 e 188 | t m12 d12 d13 e 189 | t m14 d16 d17 e 190 | t m15 d22 d14 e 191 | t m16 d16 d17 e 192 | t m19 d26 d14 e 193 | t m20 d16 d10 e 194 | t m16 d22 d30 e 195 | t m21 d24 d29 e 196 | t m22 d28 d30 e 197 | t m22 d4 d6 e 198 | t m4 d26 d30 e 199 | t m24 d14 d31 e 200 | t m26 d32 d34 e 201 | t m25 d32 d37 e 202 | t m29 d9 d33 e 203 | t m28 d25 d35 e 204 | t m17 d33 d36 e 205 | t m36 d38 d30 e 206 | t m38 d27 d21 e 207 | t m37 d37 d38 e 208 | t m6 d30 d31 e 209 | t m30 d33 d42 e 210 | t m41 d43 d39 e 211 | t m27 d30 d39 e 212 | t m16 d30 d39 e 213 | # gate 33 has single diffusion (MOS capacitor?) 214 | t m43 d48 d34 e 215 | t m44 d30 d38 e 216 | t m21 d41 d38 e 217 | t m48 d46 d39 e 218 | t m47 d40 d9 e 219 | t m40 d50 d44 e 220 | t m22 d45 d46 e 221 | t m20 d45 d46 e 222 | t m28 d8 d54 e 223 | t m38 d20 d54 e 224 | t m46 d21 d54 e 225 | t m17 d48 d47 e 226 | t m18 d35 d54 e 227 | t m45 d15 d55 e 228 | t m47 d19 d55 e 229 | # gate 49 has single diffusion (MOS capacitor?) 230 | # gate 50 has single diffusion (MOS capacitor?) 231 | t m49 d43 d53 e 232 | t m44 d49 d45 e 233 | t m21 d44 d52 e 234 | t m51 d48 d49 e 235 | t m50 d57 d44 e 236 | t m50 d9 d51 e 237 | t m48 d53 d46 e 238 | # gate 58 has single diffusion (MOS capacitor?) 239 | t m55 d50 d58 e 240 | t m54 d50 d58 e 241 | t m52 d50 d63 e 242 | t m6 d59 d62 e 243 | t m56 d56 d60 e 244 | t m25 d56 d62 e 245 | t m53 d56 d62 e 246 | t m8 d59 d62 e 247 | t m4 d59 d62 e 248 | t m21 d58 d61 e 249 | t m20 d56 d62 e 250 | t m12 d59 d62 e 251 | t m57 d58 d60 e 252 | t m48 d64 d59 e 253 | t m59 d57 d63 e 254 | t m60 d66 d60 e 255 | t m16 d66 d62 e 256 | t m61 d67 d60 e 257 | t m25 d66 d62 e 258 | t m8 d68 d62 e 259 | t m17 d65 d67 e 260 | t m53 d66 d62 e 261 | t m58 d67 d70 e 262 | t m63 d73 d69 e 263 | t m17 d63 d71 e 264 | t m64 d64 d68 e 265 | t m27 d72 d75 e 266 | t m4 d72 d75 e 267 | t m20 d72 d75 e 268 | t m62 d72 d75 e 269 | t m42 d72 d75 e 270 | t m66 d72 d74 e 271 | t m14 d72 d75 e 272 | t m68 d76 d70 e 273 | t m70 d73 d77 e 274 | t m22 d75 d78 e 275 | t m16 d75 d78 e 276 | t m23 d75 d78 e 277 | t m42 d75 d78 e 278 | t m14 d75 d78 e 279 | t m62 d75 d78 e 280 | t m71 d74 d78 e 281 | t m72 d74 d76 e 282 | t m73 d80 d77 e 283 | t m75 d79 d87 e 284 | t m76 d81 d74 e 285 | t m22 d81 d83 e 286 | t m12 d81 d83 e 287 | t m20 d81 d83 e 288 | t m4 d81 d83 e 289 | t m62 d81 d83 e 290 | t m6 d81 d83 e 291 | t m70 d80 d69 e 292 | t m17 d82 d87 e 293 | t m79 d89 d87 e 294 | t m16 d90 d83 e 295 | t m81 d97 d69 e 296 | t m53 d90 d83 e 297 | t m27 d90 d83 e 298 | t m80 d89 d90 e 299 | t m83 d89 d84 e 300 | t m21 d92 d84 e 301 | t m84 d89 d93 e 302 | # gate 122 has single diffusion (MOS capacitor?) 303 | t m27 d93 d94 e 304 | t m53 d93 d94 e 305 | t m20 d93 d94 e 306 | t m86 d84 d95 e 307 | t m17 d97 d91 e 308 | # gate 128 has single diffusion (MOS capacitor?) 309 | t m89 d89 d98 e 310 | t m91 d101 d95 e 311 | t m85 d98 d94 e 312 | t m93 d89 d103 e 313 | t m17 d96 d106 e 314 | t m92 d89 d101 e 315 | t m82 d105 d99 e 316 | t m90 d104 d105 e 317 | t m16 d107 d103 e 318 | t m53 d107 d103 e 319 | t m95 d107 d103 e 320 | t m17 d101 d102 e 321 | # gate 141 has single diffusion (MOS capacitor?) 322 | t m4 d112 d107 e 323 | t m21 d108 d109 e 324 | t m25 d107 d110 e 325 | t m97 d105 d99 e 326 | t m16 d112 d107 e 327 | t m98 d106 d99 e 328 | t m14 d112 d107 e 329 | t m27 d112 d107 e 330 | t m101 d113 d114 e 331 | t m95 d114 d110 e 332 | t m42 d112 d107 e 333 | t m8 d112 d107 e 334 | t m21 d113 d111 e 335 | t m100 d115 d95 e 336 | t m106 d120 d106 e 337 | t m107 d112 d114 e 338 | t m108 d107 d119 e 339 | t m105 d113 d95 e 340 | t m105 d114 d116 e 341 | t m27 d117 d118 e 342 | t m99 d109 d95 e 343 | t m104 d105 d122 e 344 | t m102 d120 d109 e 345 | t m103 d97 d122 e 346 | t m109 d121 d114 e 347 | t m65 d109 d95 e 348 | t m65 d116 d95 e 349 | # metal orphans: set([96]) 350 | # diffusion orphans: set([]) 351 | # contact orphans: set([]) 352 | # gate orphans: set([33, 49, 50, 58, 122, 128, 141]) 353 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/netlist.v: -------------------------------------------------------------------------------- 1 | module hp35_rom_control1(input clk, input sync, output x0,x1,y0,y1,z0,z1,z2,z3,z4); 2 | 3 | wire n_433,n_432,n_416,n_378,n_353,n_435,n_414,n_438; 4 | wire n_371,n_359,n_415,y0,y1,n_341,n_389,n_362; 5 | wire n_361,n_367,n_340,n_407,n_401,n_424,n_440,n_427; 6 | wire n_420,n_422,n_409,z4,x0,x1,z0,z1; 7 | wire z2,z3,n_392,n_393,n_391,n_396,n_395,n_399; 8 | 9 | reg n_430,n_428,n_429,n_426,n_377,n_421,n_408,n_348; 10 | 11 | assign n_371 = ~n_401; 12 | assign n_340 = ~(n_435 | n_430 | n_393); 13 | assign n_396 = ~(n_430 | n_367); 14 | assign n_440 = ~n_435; 15 | assign n_435 = ~(n_428 | n_426 | n_433 | n_420); 16 | assign n_416 = ~n_430; 17 | assign n_367 = ~(y0 | n_440 | n_430); 18 | assign n_353 = ~(n_438 | n_420); 19 | assign n_432 = ~(n_416 | n_440 | n_393); 20 | assign n_415 = ~n_426; 21 | assign n_409 = ~(n_359 | n_389); 22 | assign z0 = ~n_432; 23 | assign n_395 = ~(n_426 | n_422); 24 | assign n_389 = ~(n_416 | n_420 | n_414); 25 | assign n_420 = ~n_348; 26 | assign n_427 = ~(n_428 | n_433 | n_429); 27 | assign n_414 = ~n_427; 28 | assign z2 = ~(n_428 | n_416 | n_420 | n_429 | n_424 | n_426); 29 | assign z4 = ~(n_392 | n_407 | n_424 | n_393 | n_416 | n_426); 30 | assign x1 = ~x0; 31 | assign n_341 = ~(n_340 | n_362); 32 | assign z3 = ~(n_429 | n_430 | n_415 | n_407 | n_392 | n_424); 33 | assign y0 = ~n_378; 34 | assign n_422 = ~(n_440 | n_378 | n_430); 35 | assign n_399 = ~(n_433 | n_426 | n_407 | n_430 | n_392 | n_393); 36 | assign n_438 = ~(n_440 | n_378 | n_416); 37 | assign n_433 = ~n_377; 38 | assign n_401 = ~(n_428 | n_422); 39 | assign z1 = ~(n_440 | n_393 | n_430); 40 | assign n_424 = ~n_433; 41 | assign n_362 = ~(n_416 | n_429); 42 | assign n_392 = ~n_420; 43 | assign n_361 = ~n_408; 44 | assign x0 = ~n_421; 45 | assign n_391 = ~(n_430 | n_392 | n_414); 46 | assign n_359 = ~(n_391 | n_361); 47 | assign y1 = ~n_399; 48 | assign n_393 = ~n_429; 49 | assign n_407 = ~n_428; 50 | assign n_378 = ~sync; 51 | 52 | always @(posedge clk) begin 53 | n_430 <= n_353; 54 | n_421 <= n_361; 55 | n_408 <= n_409; 56 | n_348 <= n_433; 57 | n_426 <= n_341; 58 | n_377 <= n_371; 59 | n_428 <= n_395; 60 | n_429 <= n_396; 61 | end 62 | endmodule 63 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/netlist_to_verilog.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | # 4 | # netlist_to_verilog.py netlist.v 5 | # 6 | # Convert a transistor netlist to a Verilog module. Detects two-phase latches and NOR gates. 7 | # 8 | # Peter Monta 9 | # November 2010 10 | # 11 | 12 | import sys 13 | import string 14 | 15 | d_components = {} 16 | d_nodes = {} 17 | d_ctype = {} 18 | 19 | def add(c,ctype,nodes): 20 | for n in nodes: 21 | if d_components.has_key(n): 22 | d_components[n].append(c) 23 | else: 24 | d_components[n] = [c] 25 | d_nodes[c] = nodes 26 | d_ctype[c] = ctype 27 | 28 | def remove(c): 29 | nodes = d_nodes[c] 30 | del d_nodes[c] 31 | del d_ctype[c] 32 | for n in nodes: 33 | for (i,cc) in enumerate(d_components[n]): 34 | if cc==c: 35 | del d_components[n][i] 36 | 37 | def add_node(n): 38 | d_components[n] = [] 39 | 40 | nc = 0 41 | def new_name(prefix): 42 | global nc 43 | x = nc 44 | nc = nc + 1 45 | return '%s_%d' % (prefix,x) 46 | 47 | def coalesce_contacts(pin_names): 48 | for c in d_nodes.keys(): 49 | if d_ctype[c]=='c': 50 | old1,old2 = d_nodes[c] 51 | if old1==old2: 52 | print 'circular contact',old1 53 | continue 54 | if old1 in pin_names and old2 in pin_names: 55 | print 'pins %s and %s conflict: they are the same node' % (old1,old2) 56 | if old1 in pin_names: 57 | new = old1 58 | elif old2 in pin_names: 59 | new = old2 60 | else: 61 | new = new_name('n') 62 | c1,c2 = d_components[old1],d_components[old2] 63 | del d_components[old1] 64 | del d_components[old2] 65 | del d_nodes[c] 66 | del d_ctype[c] 67 | d_components[new] = [] 68 | for r in c1+c2: 69 | if r==c: 70 | continue 71 | if not r in d_components[new]: 72 | d_components[new].append(r) 73 | for index,item in enumerate(d_nodes[r]): 74 | if item==old1 or item==old2: 75 | d_nodes[r][index] = new 76 | 77 | def coalesce_pins(): 78 | pin_names = [] 79 | for c in d_nodes.keys(): 80 | if d_ctype[c]=='p': 81 | new,old = d_nodes[c] 82 | pin_names.append(new) 83 | c1 = d_components[old] 84 | del d_components[old] 85 | del d_nodes[c] 86 | del d_ctype[c] 87 | d_components[new] = [] 88 | for r in c1: 89 | if r==c: 90 | continue 91 | if not r in d_components[new]: 92 | d_components[new].append(r) 93 | for index,item in enumerate(d_nodes[r]): 94 | if item==old: 95 | d_nodes[r][index] = new 96 | return pin_names 97 | 98 | def alias(old,new): 99 | c1 = d_components[old] 100 | del d_components[old] 101 | d_components[new] = list(set(d_components[new]+c1)) 102 | for r in c1: 103 | for index,item in enumerate(d_nodes[r]): 104 | if item==old: 105 | d_nodes[r][index] = new 106 | 107 | def detect_pullups(): 108 | for c in d_nodes.keys(): 109 | if d_ctype[c]!='t': 110 | continue 111 | x = d_nodes[c] 112 | if (x[0]==x[1] and x[2]=='Vdd') or (x[0]==x[2] and x[1]=='Vdd'): 113 | remove(c) 114 | add(new_name('r'),'pullup',[x[0]]) 115 | 116 | def list_components_with_node(n): 117 | r = [] 118 | for c in d_nodes.keys(): 119 | if n in d_nodes[c]: 120 | r.append(c) 121 | return r 122 | 123 | def find_unique_component(type,node): 124 | r = [] 125 | for c in d_nodes.keys(): 126 | if d_ctype[c]!=type: 127 | continue 128 | if node in d_nodes[c]: 129 | r.append(c) 130 | if len(r)==1: 131 | return r[0] 132 | return None 133 | 134 | def find_components(type,node): 135 | r = [] 136 | for c in d_nodes.keys(): 137 | if d_ctype[c]!=type: 138 | continue 139 | if node in d_nodes[c]: 140 | r.append(c) 141 | return r 142 | 143 | def find_t_drain(gate_node,node): 144 | r = [] 145 | for c in d_nodes.keys(): 146 | if d_ctype[c]!='t': 147 | continue 148 | (gate,source,drain) = d_nodes[c] 149 | if gate!=gate_node: 150 | continue 151 | if source==node or drain==node: 152 | r.append(c) 153 | if len(r)==1: 154 | return r[0] 155 | return None 156 | 157 | def find_sd_components(node): 158 | r = [] 159 | for c in d_nodes.keys(): 160 | if d_ctype[c]!='t': 161 | continue 162 | (gate,source,drain) = d_nodes[c] 163 | if source==node or drain==node: 164 | r.append(c) 165 | return r 166 | 167 | def detect_latches(): 168 | for c in d_nodes.keys(): 169 | if not d_ctype.has_key(c): 170 | continue 171 | 172 | if d_ctype[c]!='t': 173 | continue 174 | (gate,source,drain) = d_nodes[c] 175 | 176 | the_pulldown = c 177 | 178 | if drain=='Vss': 179 | source,drain = drain,source 180 | inverter_node = drain 181 | 182 | the_pullup = find_unique_component('pullup',inverter_node) 183 | if not the_pullup: 184 | continue 185 | 186 | the_phi2 = find_t_drain('phi2',inverter_node) 187 | if not the_phi2: 188 | continue 189 | 190 | the_phi1 = find_t_drain('phi1',gate) 191 | if not the_phi1: 192 | continue 193 | 194 | (g,s,d) = d_nodes[the_phi1] 195 | if s==gate: 196 | s,d = d,s 197 | input_node = s 198 | 199 | (g,s,d) = d_nodes[the_phi2] 200 | if s==inverter_node: 201 | s,d = d,s 202 | output_node = s 203 | 204 | remove(the_phi1) 205 | remove(the_phi2) 206 | remove(the_pullup) 207 | remove(the_pulldown) 208 | add(new_name('latch'),'latch',[output_node,input_node]) 209 | 210 | def detect_gates(): 211 | for c in d_nodes.keys(): 212 | if not d_ctype.has_key(c): 213 | continue 214 | 215 | if d_ctype[c]!='pullup': 216 | continue 217 | node = d_nodes[c][0] 218 | 219 | x = find_sd_components(node) 220 | gates = [] 221 | for cc in x: 222 | (g,s,d) = d_nodes[cc] 223 | gates.append(g) 224 | 225 | add(new_name('g'),'nor',[node]+gates) 226 | for old_c in x: 227 | remove(old_c) 228 | remove(c) 229 | 230 | def print_netlist(): 231 | print 'components with node lists and type:' 232 | for c in d_nodes.keys(): 233 | print c,d_nodes[c],d_ctype[c] 234 | print 'nodes with component lists:' 235 | for c in d_components.keys(): 236 | print c,d_components[c] 237 | 238 | def print_nor(c,nodes): 239 | if len(nodes)==2: 240 | print ' assign %s = ~%s;' % (nodes[0],nodes[1]) 241 | else: 242 | print ' assign %s = ~(%s);' % (nodes[0],string.join(nodes[1:],' | ')) 243 | 244 | def print_latch(c,nodes): 245 | n_out,n_in = nodes[0],nodes[1] 246 | print ' %s <= %s;' % (n_out,n_in) 247 | 248 | def pretty_print(x,prefix): 249 | per_line = 8 250 | for i in xrange(0,int(len(x)/per_line)): 251 | print ' %s %s;' % (prefix,string.join(x[per_line*i:per_line*(i+1)],',')) 252 | 253 | def print_wires_and_regs(): 254 | wires = set([]) 255 | regs = set([]) 256 | for c in d_nodes.keys(): 257 | if d_ctype[c]=='latch': 258 | nodes = d_nodes[c] 259 | n_out,n_in = nodes[0],nodes[1] 260 | wires.add(n_in) 261 | regs.add(n_out) 262 | elif d_ctype[c]=='nor': 263 | nodes = d_nodes[c] 264 | wires.add(nodes[0]) 265 | pretty_print(list(wires),'wire'); 266 | print '' 267 | pretty_print(list(regs),'reg'); 268 | print '' 269 | 270 | def print_verilog_netlist(): 271 | print 'module hp35_rom_control1(input clk, input sync, output x0,x1,y0,y1,z0,z1,z2,z3,z4);' 272 | print '' 273 | print_wires_and_regs() 274 | for c in d_nodes.keys(): 275 | if d_ctype[c]=='nor': 276 | print_nor(c,d_nodes[c]) 277 | print '' 278 | print ' always @(posedge clk) begin' 279 | for c in d_nodes.keys(): 280 | if d_ctype[c]=='latch': 281 | print_latch(c,d_nodes[c]) 282 | print ' end' 283 | print 'endmodule' 284 | 285 | # 286 | # main program 287 | # 288 | 289 | for x in sys.stdin.readlines(): 290 | y = string.split(x) 291 | if not y: 292 | continue 293 | if y[0]=='p' or y[0]=='c': 294 | add(new_name(y[0]),y[0],[y[1],y[2]]) 295 | elif y[0]=='t': 296 | add(new_name(y[0]),'t',[y[1],y[2],y[3]]) 297 | 298 | pin_names = coalesce_pins() 299 | coalesce_contacts(pin_names) 300 | add_node('Vdd') 301 | alias('Gnd','Vdd') 302 | alias('Gnd2','Vdd') 303 | 304 | detect_pullups() 305 | detect_latches() 306 | detect_gates() 307 | 308 | print_verilog_netlist() 309 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/pad.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/masks/hp35-bitmap-tools/pad.png -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/pins.txt: -------------------------------------------------------------------------------- 1 | sync 50 578 2 | phi2 66 616 3 | phi1 106 614 4 | Vss 146 614 5 | Gnd 663 1422 6 | x0 640 944 7 | x1 654 1058 8 | y0 2474 1490 9 | y1 2506 1486 10 | z0 2656 1486 11 | z1 2691 1486 12 | z2 2724 1486 13 | z3 2758 1486 14 | z4 2793 1486 15 | Gnd2 2829 1486 16 | -------------------------------------------------------------------------------- /masks/hp35-bitmap-tools/testbench.v: -------------------------------------------------------------------------------- 1 | module main(); 2 | wire clk; 3 | 4 | wire sync; 5 | wire x0,x1,y0,y1,z0,z1,z2,z3,z4; 6 | 7 | clock_source c(clk); 8 | sync_source s(clk, sync); 9 | 10 | hp35_rom_control1 dut(clk, sync, x0,x1,y0,y1,z0,z1,z2,z3,z4); 11 | 12 | wire [7:0] state={dut.n_430,dut.n_428,dut.n_429,dut.n_426,dut.n_377,dut.n_421,dut.n_408,dut.n_348}; 13 | 14 | always @(posedge clk) 15 | $display("sync:%d state:%b %d %d %d %d %d %d %d %d %d",sync,state,x0,x1,y0,y1,z0,z1,z2,z3,z4); 16 | 17 | initial #30000 $finish; 18 | 19 | endmodule 20 | 21 | module clock_source(output clk); 22 | reg clk; 23 | initial begin 24 | clk = 0; 25 | forever #5 clk = ~clk; 26 | end 27 | endmodule 28 | 29 | module sync_source(input clk, output sync); 30 | reg [5:0] c; 31 | initial 32 | c = 0; 33 | always @(posedge clk) 34 | c <= (c==6'd55) ? 0 : c+1; 35 | // assign sync = !((c>=45) && (c<55)); 36 | assign sync = (c>=45) && (c<55); 37 | endmodule 38 | -------------------------------------------------------------------------------- /masks/rules.make: -------------------------------------------------------------------------------- 1 | .PRECIOUS: %.ext 2 | 3 | %.spice: %.ext 4 | ext2spice $* >ext2spice.log 2>ext2spice.log2 5 | ../tools/fix_spice_comments.py <$*.spice >temp1.spice 6 | bash -c 'if [ -f ./mark_new_depletion.py ]; then (./mark_new_depletion.py temp2.spice); else mv temp1.spice temp2.spice; fi' 7 | rm -f temp1.spice 8 | mv temp2.spice $*.spice 9 | 10 | %.ext: %.cif 11 | echo 'scalegrid 1 2000' >magic.script 12 | echo 'snap internal' >>magic.script 13 | echo -n 'cif read ' >>magic.script 14 | echo '$<' >>magic.script 15 | echo 'extract' >>magic.script 16 | echo -n 'feedback save ' >>magic.script 17 | echo '$*.feedback' >>magic.script 18 | echo 'quit -noprompt' >>magic.script 19 | magic -T chip.tech -dnull -noconsole magic.log 2>magic.log2 20 | rm -f magic.script 21 | rm -f \(UNNAMED\).ext 22 | 23 | %.png: %.polygon 24 | bash -c 'if [ -f $*.tweak ]; then (./apply-tweak.py $*.tweak <$< >temp.polygon); else cp $< temp.polygon; fi' 25 | $@ 27 | rm -f temp.polygon out.png 28 | 29 | %.png: %.svg 30 | <$< ../tools/svg2png.py 6500 6280 31 | $@ 32 | rm -f out.png 33 | 34 | %.vec.svg: %.png 35 | <$< pngtopnm | pamflip -topbottom | potrace --unit 1 --debug 4 -b svg >$@ 36 | 37 | %.png: %.bmp 38 | # pbmmake -white 3 3 >t3.pbm 39 | # <$< bmptoppm | ppmtopgm | pamthreshold -simple -threshold=0.5 | pamenlarge 3 | pgmmorphconv -dilate t3.pbm | pnmtopng >$@ 40 | # rm -f t3.pbm 41 | <$< bmptoppm | ppmtopgm | pamthreshold -simple -threshold=0.5 | pnmtopng >$@ 42 | -------------------------------------------------------------------------------- /masks/tools/.gitignore: -------------------------------------------------------------------------------- 1 | *.pyc 2 | -------------------------------------------------------------------------------- /masks/tools/fix_spice_comments.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | 5 | for x in sys.stdin.readlines(): 6 | x = x.replace(r'**FLOATING',r';**FLOATING') 7 | sys.stdout.write(x) 8 | -------------------------------------------------------------------------------- /masks/tools/lajos2nodes.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | import string 5 | 6 | def sanitize(s): 7 | s = s.replace(r'.',r'__') 8 | s = s.replace(r'/',r'_') 9 | s = s.replace(r'+',r'_') 10 | s = s.replace(r'-',r'_') 11 | s = s.replace(r'#',r'n') 12 | s = s.replace(r'(',r'_') 13 | s = s.replace(r')',r'_') 14 | s = s.replace(r'&',r'_') 15 | s = s.replace(r'~',r'_') 16 | return s 17 | 18 | translate_layer = { '1':'NM', '2':'NP', '3':'ND' } 19 | 20 | names = {} 21 | 22 | for x in sys.stdin.readlines(): 23 | if x[-1]=='\n': 24 | x = x[:-1] 25 | if x[-1]=='\r': 26 | x = x[:-1] 27 | if x[0]==';': 28 | continue 29 | r = string.split(x,',') 30 | layer,x,y,name = r[0],int(r[1]),int(r[2]),r[3] 31 | layer = translate_layer[layer] 32 | name = sanitize(name) 33 | if names.has_key(name): 34 | print 'collision: ',name 35 | names[name] = 1 36 | print '%s %d %d %s' % (name,x,y,layer) 37 | -------------------------------------------------------------------------------- /masks/tools/lajos2spice.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | import string 5 | 6 | print "* SPICE3 converted from Lajos's format" 7 | print '' 8 | 9 | i = 0 10 | 11 | for x in sys.stdin.readlines(): 12 | r = string.split(x,',') 13 | if r[0]=='T': 14 | g = r[4] 15 | s = r[5] 16 | d = r[6] 17 | print 'M%d %s %s %s GND efet' % (i,s,g,d) 18 | i = i + 1 19 | elif r[0]=='R': 20 | g = r[4] 21 | s = r[4] 22 | d = r[5] 23 | print 'M%d %s %s %s GND efet' % (i,s,g,d) 24 | i = i + 1 25 | elif r[0]=='C': 26 | pass 27 | else: 28 | print 'unknown component %s' % r[0] 29 | -------------------------------------------------------------------------------- /masks/tools/make-composite-svg.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import sys 4 | import re 5 | 6 | def print_svg_header(X,Y): 7 | s = """ 8 | 10 | 13 | 14 | Created by potrace 1.9, written by Peter Selinger 2001-2010 15 | """ % (X,Y,X,Y) 16 | sys.stdout.write(s) 17 | 18 | def print_svg_footer(): 19 | s = "" 20 | sys.stdout.write(s) 21 | 22 | def read_svg_group(filename): 23 | try: 24 | f = open(filename,"r") 25 | except: 26 | return None 27 | s = f.read() 28 | f.close() 29 | m = re.search(r'(.*?)',s,re.DOTALL); 30 | return m.group(1) 31 | 32 | # 33 | # main program 34 | # 35 | 36 | X = int(sys.argv[1]) 37 | Y = int(sys.argv[2]) 38 | 39 | print_svg_header(X,Y) 40 | 41 | props = { "diffusion":("0.5","#80ff80","Diff"), 42 | "buried":("0.5","#c0c0c0","Buried"), 43 | "poly":("0.5","#ff8080","Poly"), 44 | "contact":("0.75","#404040","Contacts"), 45 | "metal":("0.5","#8080ff","Metal") } 46 | 47 | for i in ["diffusion","buried","poly","contact","metal"]: 48 | opacity,color,svg_name = props[i] 49 | s = read_svg_group(i+".vec.svg") 50 | if s: 51 | sys.stdout.write('' % (svg_name,opacity,color)) 52 | sys.stdout.write(s) 53 | sys.stdout.write('') 54 | 55 | print_svg_footer() 56 | -------------------------------------------------------------------------------- /masks/tools/mask_util.py: -------------------------------------------------------------------------------- 1 | from scipy import * 2 | 3 | def extract_box(img,y): 4 | height,width = img.shape 5 | while y]*>',sys.stdin.read()): 126 | y = y.group(0) 127 | p = parse_polygon(y) 128 | if p: 129 | draw_polygon(ctx,p,0,scale) 130 | else: 131 | p = parse_rect(y) 132 | if p: 133 | draw_polygon(ctx,p,0,scale) 134 | else: 135 | p = parse_contact(y) 136 | if p: 137 | draw_polygon(ctx,p,0,scale) 138 | else: 139 | p = parse_path(y) 140 | if p: 141 | draw_path(ctx,p,0,scale) 142 | else: 143 | print 'unknown element type: '+y 144 | 145 | surface.write_to_png("out.png") 146 | -------------------------------------------------------------------------------- /netlist-translation/.gitignore: -------------------------------------------------------------------------------- 1 | *.pyc 2 | -------------------------------------------------------------------------------- /netlist-translation/Makefile: -------------------------------------------------------------------------------- 1 | all: 2 | ./translate.py 3 | 4 | clean: 5 | rm -f *~ *.pyc 6 | -------------------------------------------------------------------------------- /netlist-translation/js2spice.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | from netlist_import import * 4 | from netlist_util import * 5 | 6 | p = read_netlist_from_javascript(dir='../visual6502',remove_dups=False,remove_shorts=False) 7 | print_spice_netlist(p,'6502-from-javascript.spice') 8 | -------------------------------------------------------------------------------- /netlist-translation/netlist.py: -------------------------------------------------------------------------------- 1 | # Simple netlist class 2 | # 3 | # Copyright (c) 2010 Peter Monta 4 | 5 | # 6 | # Nodes serve as both components (transitors, gates, etc.) and wires. 7 | # 8 | 9 | class node: 10 | def __init__(self,c,ntype): 11 | self._name = c 12 | self._ntype = ntype 13 | self._neighbors = {} 14 | self.data = {} 15 | self.p = 0 16 | 17 | def __str__(self): 18 | return self._name 19 | 20 | def __repr__(self): 21 | return self._name 22 | 23 | def __getitem__(self, port): 24 | return self._neighbors[port] 25 | 26 | def add(self,port,n): 27 | if not port: 28 | port = 'port_%d' % self.p 29 | self.p = self.p + 1 30 | self._neighbors[port] = n 31 | 32 | def remove(self,port): 33 | del self._neighbors[port] 34 | 35 | def ports(self): 36 | return self._neighbors.keys() 37 | 38 | def name(self): 39 | return self._name 40 | 41 | def ntype(self): 42 | return self._ntype 43 | 44 | def neighbors(self): 45 | return self._neighbors.values() 46 | 47 | def set_type(self,new_type): 48 | self._ntype = new_type 49 | 50 | # 51 | # A netlist is just a collection of nodes indexed by name 52 | # 53 | 54 | class netlist: 55 | def __init__(self): 56 | self._nodes = {} 57 | 58 | def add_node(self, c, ntype): 59 | if self._nodes.has_key(c): 60 | n = self._nodes[c] 61 | if n.ntype()!=ntype: 62 | print 'type conflict when adding node',c,ntype,n.ntype() 63 | return n 64 | n = node(c,ntype) 65 | self._nodes[c] = n 66 | return n 67 | 68 | def remove_node(self, c): 69 | for n in c.neighbors(): 70 | unlink(n,c) 71 | del self._nodes[c.name()] 72 | 73 | def nodes(self): 74 | return self._nodes.values() 75 | 76 | def __getitem__(self, key): 77 | return self._nodes[key] 78 | 79 | def __contains__(self, item): 80 | return self._nodes.has_key(item) 81 | 82 | # 83 | # Utility functions for nodes and netlists 84 | # 85 | 86 | def link(c1, port1, c2, port2): 87 | c1.add(port1,c2) 88 | c2.add(port2,c1) 89 | 90 | def unlink(c1, c2): 91 | for p in c1.ports(): 92 | if c1[p]==c2: 93 | c1.remove(p) 94 | for p in c2.ports(): 95 | if c2[p]==c1: 96 | c2.remove(p) 97 | -------------------------------------------------------------------------------- /netlist-translation/netlist_import.py: -------------------------------------------------------------------------------- 1 | # Import the visual6502 netlist files 2 | # 3 | # Copyright (c) 2010 Peter Monta 4 | 5 | import re 6 | import string 7 | from netlist import * 8 | from netlist_util import * 9 | 10 | # 11 | # transform a nodenames.js name into a valid HDL instance name 12 | # 13 | 14 | nodenames = {} 15 | 16 | def sanitize(s): 17 | s = s.replace(r'.',r'_') 18 | s = s.replace(r'/',r'_') 19 | s = s.replace(r'+',r'_') 20 | s = s.replace(r'-',r'_') 21 | s = s.replace(r'#',r'n') 22 | s = s.replace(r'(',r'_') 23 | s = s.replace(r')',r'_') 24 | s = s.replace(r'~',r'_') 25 | s = s.replace(r'&',r'_') 26 | if s[0] in ['0','1','2','3','4','5','6','7','8','9']: 27 | s = 'n_' + s 28 | if nodenames.has_key(s): 29 | return nodenames[s] 30 | return s 31 | 32 | # 33 | # read in the Javascript-format netlists 34 | # 35 | 36 | def read_nodenames(filename): 37 | r = [] 38 | f = open(filename,'r') 39 | for x in f.readlines(): 40 | m = re.match(r"(\w+):[ ]*(\d+),.*",x) 41 | if not m: 42 | m = re.match(r'"(.+)":[ ]*(\d+),.*',x) 43 | if m: 44 | name = sanitize(m.group(1)) 45 | node = sanitize(m.group(2)) 46 | if name[0]=='t': 47 | name = '_'+name 48 | nodenames[node] = name 49 | f.close() 50 | 51 | def read_transdefs(filename,remove_shorts=True): 52 | r = [] 53 | f = open(filename,'r') 54 | for x in f.readlines(): 55 | m = re.match(r".*'(\w+)', (\d+), (\d+), (\d+).*",x) 56 | if m: 57 | name = sanitize(m.group(1)) 58 | gate = sanitize(m.group(2)) 59 | source = sanitize(m.group(3)) 60 | drain = sanitize(m.group(4)) 61 | if remove_shorts and source==drain: 62 | print 'omitting %s, source tied to drain' % name 63 | else: 64 | r.append((name,gate,source,drain)) 65 | f.close() 66 | return r 67 | 68 | def read_segdefs(filename): 69 | pullups = set([]) 70 | r = [] 71 | f = open(filename,'r') 72 | for x in f.readlines(): 73 | m = re.match(r"\[[ ]*(\d+),'(.)'.*",x) 74 | if m: 75 | node = sanitize(m.group(1)) 76 | pullup = m.group(2) 77 | if pullup=='-' and node in pullups: 78 | print 'pullup conflict on node %s' % node 79 | if pullup=='+' and not node in pullups: 80 | r.append(node) 81 | pullups.add(node) 82 | f.close() 83 | return r 84 | 85 | def read_pins(filename): 86 | r = [] 87 | f = open(filename,'r') 88 | i = 0 89 | for x in f.readlines(): 90 | if x=='' or x[0]=='#': 91 | continue 92 | m = string.split(x) 93 | name = m[0] 94 | ptype = m[1] 95 | r.append((i,name,ptype)) 96 | i = i + 1 97 | f.close() 98 | return r 99 | 100 | def remove_duplicates(transdefs): 101 | r = [] 102 | td = {} 103 | duplicates = 0 104 | for t in transdefs: 105 | name,g,s,d = t 106 | if s>d: 107 | key = (g,s,d) 108 | else: 109 | key = (g,d,s) 110 | if not td.has_key(key): 111 | r.append(t) 112 | td[key] = 1 113 | else: 114 | duplicates = duplicates + 1 115 | if duplicates>0: 116 | print 'removed %d duplicate transistors' % duplicates 117 | return r 118 | 119 | def read_netlist_from_javascript(dir,remove_dups=True,remove_shorts=True): 120 | p = netlist() 121 | 122 | read_nodenames(dir+'/nodenames.js') 123 | 124 | transdefs = read_transdefs(dir+'/transdefs.js',remove_shorts) 125 | pullups = read_segdefs(dir+'/segdefs.js') 126 | pins = read_pins(dir+'/pins.txt') 127 | 128 | if remove_dups: 129 | transdefs = remove_duplicates(transdefs) 130 | 131 | for (name,g,s,d) in transdefs: 132 | ng = p.add_node(g,'node_analog') 133 | ns = p.add_node(s,'node_analog') 134 | nd = p.add_node(d,'node_analog') 135 | nt = p.add_node(name,'t') 136 | port = new_name('in') 137 | link(nt,port,ng,None) 138 | link(nt,'s',ns,None) 139 | link(nt,'d',nd,None) 140 | nt.data['function'] = port 141 | 142 | for name in pullups: 143 | np = p.add_node(new_name('pullup'),'pullup') 144 | link(np,'s',p[name],None) 145 | 146 | for (i,name,pin_type) in pins: 147 | np = p.add_node(new_name('pin'),'pin_'+pin_type) 148 | link(np,'pin',p[name],None) 149 | np.data['index'] = i 150 | np.data['name'] = name 151 | 152 | return p 153 | 154 | def read_spice_lines(filename): 155 | r = [] 156 | f = open(filename,'r') 157 | header = f.readline() 158 | for s in f.readlines(): 159 | if not s: 160 | continue 161 | if s=='\n': 162 | continue 163 | if s[0]=='+': 164 | continue 165 | r.append(s) 166 | return r 167 | 168 | def read_netlist_from_spice(filename): 169 | p = netlist() 170 | 171 | pins = read_pins('pins.txt') 172 | 173 | for t in read_spice_lines(filename): 174 | v = string.split(t) 175 | name = v[0] 176 | if name[0]=='M': 177 | g,s,d = sanitize(v[2]),sanitize(v[1]),sanitize(v[3]) 178 | # print g,s,d 179 | if g=='vcc' and s=='vcc' and d=='vcc': 180 | continue 181 | if s=='vcc': 182 | s,d = d,s 183 | if g=='vcc' and d=='vcc': 184 | pullup = p.add_node(s,'node_analog') 185 | np = p.add_node(new_name('pullup'),'pullup') 186 | link(np,'s',pullup,None) 187 | else: 188 | ng = p.add_node(g,'node_analog') 189 | ns = p.add_node(s,'node_analog') 190 | nd = p.add_node(d,'node_analog') 191 | nt = p.add_node('t'+name,'t') 192 | port = new_name('in') 193 | link(nt,port,ng,None) 194 | link(nt,'s',ns,None) 195 | link(nt,'d',nd,None) 196 | nt.data['function'] = port 197 | elif name[0]=='C': 198 | continue 199 | else: 200 | print 'unrecognized spice line: %s' % t 201 | 202 | for (i,name,pin_type) in pins: 203 | np = p.add_node(new_name('pin'),'pin_'+pin_type) 204 | link(np,'pin',p[name],None) 205 | np.data['index'] = i 206 | np.data['name'] = name 207 | 208 | return p 209 | -------------------------------------------------------------------------------- /netlist-translation/translate.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | # 4 | # Translate the 6502 netlist into a Verilog model 5 | # 6 | # Copyright (c) 2010 Peter Monta 7 | # November 2010 8 | # 9 | 10 | import sys 11 | from netlist_import import * 12 | from verilog import * 13 | from netlist_util import * 14 | 15 | # 16 | # main program 17 | # 18 | 19 | p = read_netlist_from_javascript(dir='../visual6502') 20 | print_summary(p) 21 | clean_netlist(p) 22 | print_summary(p) 23 | 24 | detect_gates(p) 25 | print_summary(p) 26 | #print_gate_stats(p) 27 | 28 | detect_latches(p) 29 | print_summary(p) 30 | 31 | detect_inverters(p) 32 | print_summary(p) 33 | detect_inverters(p) 34 | print_summary(p) 35 | detect_inverters(p) 36 | print_summary(p) 37 | detect_inverters(p) 38 | print_summary(p) 39 | 40 | detect_muxes(p) 41 | print_summary(p) 42 | 43 | #print_netlist(p,'netlist.txt') 44 | print_verilog_spice_netlist(p,'../verilog/chip_6502.v','chip_6502') 45 | -------------------------------------------------------------------------------- /netlist-translation/verilog.py: -------------------------------------------------------------------------------- 1 | import string 2 | from verilog_gen import * 3 | from netlist_util import * 4 | 5 | # 6 | # translate a netlist into a Verilog module 7 | # 8 | 9 | def print_verilog_spice_netlist(p,filename,verilog_module_name): 10 | f = open(filename,"w") 11 | 12 | # verilog header 13 | 14 | f.write('`include "common.h"\n') 15 | f.write('\n') 16 | f.write('module %s(\n' % verilog_module_name) 17 | f.write(' input eclk, ereset,\n') 18 | 19 | # ports 20 | 21 | f.write(string.join(pin_list(p),',\n')) 22 | f.write('\n);\n') 23 | f.write('\n') 24 | 25 | # Verilog functions (for readability) 26 | 27 | f.write(' function v; // convert an analog node value to 2-level\n'); 28 | f.write(' input [`W-1:0] x;\n'); 29 | f.write(' begin\n'); 30 | f.write(' v = ~x[`W-1];\n'); 31 | f.write(' end\n'); 32 | f.write(' endfunction\n'); 33 | f.write('\n'); 34 | 35 | f.write(' function [`W-1:0] a; // convert a 2-level node value to analog\n'); 36 | f.write(' input x;\n'); 37 | f.write(' begin\n'); 38 | f.write(' a = x ? `HI2 : `LO2;\n'); 39 | f.write(' end\n'); 40 | f.write(' endfunction\n'); 41 | f.write('\n'); 42 | 43 | # wires 44 | 45 | for c in p.nodes(): 46 | t = c.ntype() 47 | if t=='node_analog': 48 | sn = c.name() 49 | if sn=='vss' or sn=='vcc': 50 | continue 51 | wires = [] 52 | for port in c.ports(): 53 | if drives(c[port],c): 54 | wires.append('%s_%s' % (sn,port)) 55 | wires.append('%s_v' % sn) 56 | f.write(' wire signed [`W-1:0] %s;\n' % string.join(wires,', ')) 57 | f.write('\n') 58 | 59 | for c in p.nodes(): 60 | t = c.ntype() 61 | if t=='node_digital': 62 | sn = c.name() 63 | if sn=='vss' or sn=='vcc': 64 | continue 65 | f.write(' wire %s_v;\n' % sn) 66 | f.write('\n') 67 | 68 | # input pins 69 | 70 | for c in p.nodes(): 71 | if c.ntype()=='pin_input': 72 | n = c['pin'] 73 | port = find_port(n,c) 74 | f.write(' spice_pin_input %s(%s, %s_v, %s_%s);\n' % (c,c.data['name'],n,n,port)) 75 | f.write('\n') 76 | 77 | # output pins 78 | 79 | for c in p.nodes(): 80 | if c.ntype()=='pin_output': 81 | n = c['pin'] 82 | if n.ntype()=='node_analog': 83 | s = '%s_v' % n 84 | else: 85 | s = 'a(%s_v)' % n 86 | f.write(' spice_pin_output %s(%s, %s);\n' % (c,c.data['name'],s)) 87 | f.write('\n') 88 | 89 | # bidirectional pins 90 | 91 | for c in p.nodes(): 92 | if c.ntype()=='pin_bidirectional': 93 | n = c['pin'] 94 | port = find_port(n,c) 95 | f.write(' spice_pin_bidirectional %s(%s_i, %s_o, %s_t, %s_v, %s_%s);\n' % (c,c.data['name'],c.data['name'],c.data['name'],n,n,port)) 96 | f.write('\n') 97 | 98 | # transistors / transistor series-parallel networks 99 | 100 | for c in p.nodes(): 101 | if c.ntype()=='t': 102 | s,d = c['s'],c['d'] 103 | if s.name()=='vcc' or d.name()=='vss': 104 | s,d = d,s 105 | if d.name()=='vcc': 106 | v_s = '%s_v' % s.name() 107 | i_s = '%s_%s' % (s.name(),find_port(s,c)) 108 | f.write(' spice_transistor_nmos_vdd %s(%s, %s, %s);\n' % (c,t_function(c,c.data['function']),v_s,i_s)) 109 | elif s.name()=='vss': 110 | v_d = '%s_v' % d.name() 111 | i_d = '%s_%s' % (d.name(),find_port(d,c)) 112 | f.write(' spice_transistor_nmos_gnd %s(%s, %s, %s);\n' % (c,t_function(c,c.data['function']),v_d,i_d)) 113 | else: 114 | if s.ntype()=='node_analog': 115 | v_s = '%s_v' % s.name() 116 | i_s = '%s_%s' % (s.name(),find_port(s,c)) 117 | else: 118 | v_s = 'a(%s_v)' % s.name() 119 | i_s = new_name('temp') 120 | f.write(' wire [`W-1:0] %s;\n' % i_s) 121 | if d.ntype()=='node_analog': 122 | v_d = '%s_v' % d.name() 123 | i_d = '%s_%s' % (d.name(),find_port(d,c)) 124 | else: 125 | v_d = 'a(%s_v)' % d.name() 126 | i_d = new_name('temp') 127 | f.write(' wire [`W-1:0] %s;\n' % i_d) 128 | f.write(' spice_transistor_nmos %s(%s, %s, %s, %s, %s);\n' % (c,t_function(c,c.data['function']),v_s,v_d,i_s,i_d)) 129 | f.write('\n') 130 | 131 | # pullups 132 | 133 | for c in p.nodes(): 134 | if c.ntype()=='pullup': 135 | n = c['s'] 136 | i = find_port(n,c) 137 | f.write(' spice_pullup %s(%s_v, %s_%s);\n' % (c,n,n,i)) 138 | f.write('\n') 139 | 140 | # latches 141 | 142 | for c in p.nodes(): 143 | if c.ntype()=='latch': 144 | l_g = t_function(c,c.data['function']) 145 | if c['din'].name()=='vss' or c['din'].name()=='vcc': 146 | print 'latch has input of vss or vcc, skipping' 147 | continue 148 | l_in = binarize(c['din']) 149 | l_out = '%s_v' % c['dout'].name() 150 | f.write(' spice_latch %s(eclk,ereset, %s, %s, %s);\n' % (c,l_g,l_in,l_out)) 151 | f.write('\n') 152 | 153 | # gates 154 | 155 | for c in p.nodes(): 156 | if c.ntype()=='gate': 157 | gate_in = '~(%s)' % t_function(c,c.data['function']) 158 | gate_out = '%s_v' % c['dout'].name() 159 | f.write(' assign %s = %s;\n' % (gate_out,gate_in)) 160 | f.write('\n') 161 | 162 | # multiplexers 163 | 164 | mux_sizes = set([]) 165 | 166 | for c in p.nodes(): 167 | if c.ntype()!='mux': 168 | continue 169 | s = len(c.data['functions']) 170 | mux_sizes.add(s) 171 | clks = [] 172 | for fn in c.data['functions']: 173 | clks.append(t_function(c,fn)) 174 | xs = [] 175 | for i in xrange(0,s): 176 | xs.append(binarize(c['x%d'%i])) 177 | dout = c['dout'] 178 | f.write(' spice_mux_%d %s(eclk, ereset, %s, %s, %s_v);\n' % (s,c,string.join(clks,','),string.join(xs,','),dout)); 179 | f.write('\n'); 180 | 181 | # nodes 182 | 183 | node_sizes = set([]) 184 | 185 | for n in p.nodes(): 186 | if n.ntype()!='node_analog': 187 | continue 188 | sn = n.name() 189 | if sn=='vss' or sn=='vcc': 190 | continue 191 | drivers = [] 192 | for port in n.ports(): 193 | if drives(n[port],n): 194 | drivers.append(port) 195 | l = len(drivers) 196 | node_sizes.add(l) 197 | f.write(' spice_node_%d n_%s(eclk, ereset, ' % (l,sn)) 198 | for k in drivers: 199 | f.write('%s_%s,' % (sn,k)) 200 | f.write(' ') 201 | f.write('%s_v' % sn) 202 | f.write(');\n') 203 | f.write('\n') 204 | 205 | # footer 206 | 207 | f.write('endmodule\n') 208 | f.write('\n') 209 | 210 | # node modules 211 | 212 | gen0(f) 213 | f.write('\n') 214 | if 0 in node_sizes: 215 | node_sizes.remove(0) 216 | for s in node_sizes: 217 | gen(f,s) 218 | f.write('\n') 219 | 220 | # mux modules 221 | 222 | for s in mux_sizes: 223 | gen_mux(f,s) 224 | f.write('\n') 225 | -------------------------------------------------------------------------------- /netlist-translation/verilog_gen.py: -------------------------------------------------------------------------------- 1 | import string 2 | 3 | def pin_verilog(s): 4 | i,name,pin_type = s 5 | if pin_type=='pin_output': 6 | return [' output %s' % name] 7 | elif pin_type=='pin_input': 8 | return [' input %s' % name] 9 | elif pin_type=='pin_bidirectional': 10 | return [' input %s_i' % name,' output %s_o' % name,' output %s_t' % name] 11 | 12 | # list of Verilog pin strings in their original pins.txt order 13 | 14 | def pin_list(p): 15 | r = [] 16 | for c in p.nodes(): 17 | t = c.ntype() 18 | if t=='pin_output' or t=='pin_input' or t=='pin_bidirectional': 19 | r.append((c.data['index'],c.data['name'],t)) 20 | r.sort() 21 | return reduce(lambda x,y:x+y,map(pin_verilog,r),[]) 22 | 23 | # 24 | # generate a Verilog model of an analog node 25 | # 26 | 27 | def glist(x,s): 28 | r = [] 29 | for i in xrange(0,s): 30 | r.append('%s%d'%(x,i)) 31 | return r 32 | 33 | def gen(f,s): 34 | f.write('module spice_node_%d(input eclk,ereset, input signed [`W-1:0] %s, output reg signed [`W-1:0] v);\n' % (s,string.join(glist('i',s),','))) 35 | f.write(' wire signed [`W-1:0] i = %s;\n' % string.join(glist('i',s),'+')) 36 | f.write('\n') 37 | f.write(' always @(posedge eclk)\n') 38 | f.write(' if (ereset)\n') 39 | f.write(' v <= 0;\n') 40 | f.write(' else\n') 41 | f.write(' v <= v + i;\n') 42 | f.write('\n') 43 | f.write('endmodule\n') 44 | 45 | def gen0(f): 46 | f.write('module spice_node_0(input eclk,ereset, output signed [`W-1:0] v);\n') 47 | f.write(' assign v = 0;\n') 48 | f.write('endmodule\n') 49 | 50 | def nodelist_index(p,n,c): 51 | x = p.components(n) 52 | return x.index(c) 53 | 54 | def t_function(c,s): 55 | if type(s)==type(""): 56 | node = c[s] 57 | if node.ntype()=='node_analog': 58 | return 'v(%s_v)' % node 59 | else: 60 | return '%s_v' % node 61 | else: 62 | op = s[0] 63 | if op=='and': 64 | j = '&' 65 | else: 66 | j = '|' 67 | return '(%s)' % string.join(map(lambda x:t_function(c,x),s[1:]),j) 68 | 69 | def binarize(n): 70 | if n.name()=='vss': 71 | return "1'b0" 72 | elif n.name()=='vcc': 73 | return "1'b1" 74 | elif n.ntype()=='node_analog': 75 | return 'v(%s_v)' % n.name() 76 | else: 77 | return '%s_v' % n.name() 78 | 79 | def gen_mux(f,s): 80 | clk_list = string.join(glist('clk',s),',') 81 | x_list = string.join(glist('x',s),',') 82 | f.write('module spice_mux_%d(input eclk,ereset, input %s, input %s, output reg y);\n' % (s,clk_list,x_list)) 83 | for i in xrange(0,s): 84 | f.write(' wire c%d,z%d;\n' % (i,i)); 85 | f.write('\n'); 86 | f.write(' assign c0 = clk0;\n') 87 | f.write(' assign z0 = x0;\n') 88 | f.write('\n'); 89 | for i in xrange(0,s-1): 90 | f.write(' mux_cascade m%d(c%d, z%d, clk%d, x%d, c%d, z%d);\n' % (i,i,i,i+1,i+1,i+1,i+1)) 91 | f.write('\n'); 92 | f.write(' wire clk = c%d;\n' % (s-1)); 93 | f.write(' wire x = z%d;\n' % (s-1)); 94 | f.write('\n'); 95 | f.write(' always @(posedge eclk)\n'); 96 | f.write(' if (ereset)\n'); 97 | f.write(' y <= 0;\n'); 98 | f.write(' else begin\n'); 99 | f.write(' if (clk)\n'); 100 | f.write(' y <= x;\n'); 101 | f.write(' end\n'); 102 | f.write('\n'); 103 | f.write('endmodule\n'); 104 | -------------------------------------------------------------------------------- /support/README: -------------------------------------------------------------------------------- 1 | klayout-nmos.lyp 2 | Layer properties (colors and transparency) for klayout. Specified Mead-and-Conway-like colors 3 | for NMOS GDSII files. To load this file automatically, see 4 | http://klayout.de/forum/comments.php?DiscussionID=102&page=1#Item_0 5 | Other helpful settings for klayout: 6 | In File->Setup: 7 | Application->Layer List: use klayout-nmos.lyp as default layer table 8 | Display->General: use 2x oversampling for a nicer display 9 | Display->Background: uncheck "Show Ruler" 10 | Navigation->New Cell: check "Select all hierarchy levels" 11 | 12 | potrace-1.9-optimal-polygon 13 | patch to potrace 1.9 to output optimal polygons (before adjustment and smoothing) to SVG. 14 | -------------------------------------------------------------------------------- /support/klayout-nmos.lyp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | #afff80 5 | #afff80 6 | 0 7 | 0 8 | I0 9 | true 10 | true 11 | 12 | false 13 | 0 14 | diffusion 15 | 1/0@1 16 | 17 | 18 | #ffc280 19 | #ffc280 20 | 0 21 | 0 22 | I0 23 | true 24 | true 25 | 26 | false 27 | 0 28 | implant 29 | 2/0@1 30 | 31 | 32 | #c0c0c0 33 | #c0c0c0 34 | 0 35 | 0 36 | I0 37 | true 38 | true 39 | 40 | false 41 | 0 42 | buried 43 | 3/0@1 44 | 45 | 46 | #ff80a8 47 | #ff80a8 48 | 0 49 | 0 50 | I0 51 | true 52 | true 53 | 54 | false 55 | 0 56 | poly 57 | 4/0@1 58 | 59 | 60 | #606060 61 | #606060 62 | 0 63 | 0 64 | I0 65 | true 66 | true 67 | 68 | false 69 | 0 70 | contact 71 | 5/0@1 72 | 73 | 74 | #80a8ff 75 | #80a8ff 76 | 0 77 | 0 78 | I0 79 | true 80 | true 81 | 82 | false 83 | 0 84 | metal 85 | 6/0@1 86 | 87 | 88 | 89 | -------------------------------------------------------------------------------- /support/potrace-1.9-optimal-polygon.patch: -------------------------------------------------------------------------------- 1 | diff -ur potrace-1.9-original/src/backend_svg.c potrace-1.9/src/backend_svg.c 2 | --- potrace-1.9-original/src/backend_svg.c 2010-12-15 21:47:19.000000000 -0800 3 | +++ potrace-1.9/src/backend_svg.c 2011-04-02 05:55:02.000000000 -0700 4 | @@ -191,6 +191,22 @@ 5 | return 0; 6 | } 7 | 8 | +void svg_optimal_polygon(FILE* fout, point_t *pt, int *po, int m, int abs) { 9 | + int i; 10 | + if (abs) { 11 | + svg_moveto(fout, dpoint(pt[po[0]])); 12 | + for (i=1; i=0; i--) { 18 | + svg_lineto(fout, dpoint(pt[po[i]])); 19 | + } 20 | + } 21 | + shiptoken(fout, "z"); 22 | +} 23 | + 24 | static void write_paths_opaque(FILE *fout, potrace_path_t *tree) { 25 | potrace_path_t *p, *q; 26 | int c; 27 | @@ -204,7 +220,9 @@ 28 | column = c; 29 | newline = 1; 30 | lastop = 0; 31 | - if (info.debug == 1) { 32 | + if (info.debug == 4) { 33 | + svg_optimal_polygon(fout, p->priv->pt, p->priv->po, p->priv->m, 1); 34 | + } else if (info.debug == 1) { 35 | svg_jaggy_path(fout, p->priv->pt, p->priv->len, 1); 36 | } else { 37 | svg_path(fout, &p->curve, 1); 38 | @@ -215,7 +233,9 @@ 39 | column = c; 40 | newline = 1; 41 | lastop = 0; 42 | - if (info.debug == 1) { 43 | + if (info.debug == 4) { 44 | + svg_optimal_polygon(fout, q->priv->pt, q->priv->po, q->priv->m, 1); 45 | + } else if (info.debug == 1) { 46 | svg_jaggy_path(fout, q->priv->pt, q->priv->len, 1); 47 | } else { 48 | svg_path(fout, &q->curve, 1); 49 | @@ -246,13 +266,17 @@ 50 | column = c; 51 | newline = 1; 52 | lastop = 0; 53 | - if (info.debug == 1) { 54 | + if (info.debug == 4) { 55 | + svg_optimal_polygon(fout, p->priv->pt, p->priv->po, p->priv->m, 1); 56 | + } else if (info.debug == 1) { 57 | svg_jaggy_path(fout, p->priv->pt, p->priv->len, 1); 58 | } else { 59 | svg_path(fout, &p->curve, 1); 60 | } 61 | for (q=p->childlist; q; q=q->sibling) { 62 | - if (info.debug == 1) { 63 | + if (info.debug == 4) { 64 | + svg_optimal_polygon(fout, q->priv->pt, q->priv->po, q->priv->m, 0); 65 | + } else if (info.debug == 1) { 66 | svg_jaggy_path(fout, q->priv->pt, q->priv->len, 0); 67 | } else { 68 | svg_path(fout, &q->curve, 0); 69 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/.gitignore: -------------------------------------------------------------------------------- 1 | # Simulation output 2 | 3 | a.out 4 | test_sys.lxt 5 | 6 | # Xilinx cruft 7 | 8 | _xmsgs 9 | xlnx_auto_0_xdb 10 | xst 11 | 12 | *.bgn 13 | *.bit 14 | *.bld 15 | *.drc 16 | *.map 17 | *.mrp 18 | *.ncd 19 | *.ngc 20 | *.ngd 21 | *.ngm 22 | *.pad 23 | *.par 24 | *.pcf 25 | *.ptwx 26 | *.unroutes 27 | *.xpi 28 | 29 | *_bitgen.xwbt 30 | *_ngdbuild.xrpt 31 | *_pad.csv 32 | *_pad.txt 33 | *_summary.xml 34 | *_usage.xml 35 | *_xst.xrpt 36 | *_map.xrpt 37 | *_par.xrpt 38 | 39 | _impactbatch.log 40 | netlist.lst 41 | usage_statistics_webtalk.html 42 | webtalk.log 43 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/Makefile: -------------------------------------------------------------------------------- 1 | DEVICE=xc3s500e-4fg320 2 | 3 | all: 4 | echo "run -ifn chip.v -ifmt Verilog -top system -ofn chip -p ${DEVICE}" | xst 5 | ngdbuild -p ${DEVICE} -uc chip.ucf chip 6 | map -w -timing -p ${DEVICE} chip.ngd chip.pcf 7 | par -w chip.ncd chip.ncd chip.pcf 8 | bitgen -g StartupClk:JtagClk -g GTS_cycle:3 -g LCK_cycle:4 -g GWE_cycle:5 -g DONE_cycle:6 -w chip.ncd chip.bit chip.pcf 9 | 10 | prog: 11 | impact -batch impact.bat 12 | 13 | clean: 14 | rm -rf xst _xmsgs xlnx_auto_0_xdb 15 | rm -f *~ 16 | rm -f *.bgn *.bld *.drc *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.pad *.par *.pcf *.ptwx *.unroutes *.xpi 17 | rm -f *_bitgen.xwbt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_summary.xml *_usage.xml 18 | rm -f *_xst.xrpt *_map.xrpt *_par.xrpt 19 | rm -f _impactbatch.log netlist.lst usage_statistics_webtalk.html webtalk.log 20 | rm -f a.out *.lxt 21 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/chip.ucf: -------------------------------------------------------------------------------- 1 | # Clock period constraint. 2 | 3 | net clk_50mhz period = 20ns; # on-board 50 MHz crystal oscillator 4 | 5 | # 6 | # Digilent Spartan-3E Starter Board pins 7 | # 8 | 9 | net "clk_50mhz" loc = "c9" | iostandard = LVCMOS33 ; 10 | 11 | net "led<7>" loc = "f9" | iostandard = LVTTL | slew = slow | drive = 8 ; 12 | net "led<6>" loc = "e9" | iostandard = LVTTL | slew = slow | drive = 8 ; 13 | net "led<5>" loc = "d11" | iostandard = LVTTL | slew = slow | drive = 8 ; 14 | net "led<4>" loc = "c11" | iostandard = LVTTL | slew = slow | drive = 8 ; 15 | net "led<3>" loc = "f11" | iostandard = LVTTL | slew = slow | drive = 8 ; 16 | net "led<2>" loc = "e11" | iostandard = LVTTL | slew = slow | drive = 8 ; 17 | net "led<1>" loc = "e12" | iostandard = LVTTL | slew = slow | drive = 8 ; 18 | net "led<0>" loc = "f12" | iostandard = LVTTL | slew = slow | drive = 8 ; 19 | 20 | net "rs232_dce_rxd" loc = "r7" | iostandard = LVTTL ; 21 | net "rs232_dce_txd" loc = "m14" | iostandard = LVTTL | drive = 8 | slew = slow ; 22 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/chip.v: -------------------------------------------------------------------------------- 1 | `define HALFCYCLE 25 2 | `define W 6 3 | 4 | `include "../../verilog/chip_6502.v" 5 | `include "../../verilog/models.v" 6 | `include "../../verilog/clocks_6502.v" 7 | `include "system.v" 8 | `include "uart.v" 9 | `include "uart_transceiver.v" 10 | `include "rom.v" 11 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/impact.bat: -------------------------------------------------------------------------------- 1 | setmode -bscan 2 | setcable -p auto 3 | identify 4 | assignFile -p 1 -file chip.bit 5 | program -p 1 6 | quit 7 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/rom.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import string 3 | 4 | addr = 0 5 | 6 | for x in sys.stdin.readlines(): 7 | t = string.split(x) 8 | t = t[1:] 9 | for byte in t: 10 | print " 13'd%d: x = 8'h%s;" % (addr,byte) 11 | addr = addr + 1 12 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/rs232_test.v: -------------------------------------------------------------------------------- 1 | module rs232_test( 2 | input clk,reset, 3 | input [7:0] rx_data, 4 | input rx_flag, 5 | output reg rx_ack, 6 | output [7:0] tx_data, 7 | input tx_flag, 8 | output reg tx_wr 9 | ); 10 | 11 | reg [7:0] d; 12 | assign tx_data = d+1; 13 | 14 | reg [2:0] state; 15 | 16 | always @(posedge clk) 17 | if (reset) begin 18 | state <= 0; 19 | rx_ack <= 0; 20 | tx_wr <= 0; 21 | end else 22 | case (state) 23 | 3'd0: if (rx_flag) begin d <= rx_data; rx_ack <= 1; state <= 3'd1; end 24 | 3'd1: begin rx_ack <= 0; state <= 3'd2; end 25 | 3'd2: if (tx_flag) begin tx_wr <= 1; state <= 3'd3; end 26 | 3'd3: begin tx_wr <= 0; state <= 3'd0; end 27 | endcase 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/system.v: -------------------------------------------------------------------------------- 1 | // Top-level module for Digilent Spartan-3E starter board 2 | 3 | module system( 4 | input clk_50mhz, 5 | output [7:0] led, 6 | input rs232_dce_rxd, 7 | output rs232_dce_txd 8 | ); 9 | 10 | wire [15:0] ab; 11 | wire [7:0] db_i; 12 | wire [7:0] db_o; 13 | wire [7:0] db_t; // not yet properly set by the 6502 model; instead use rw for the three-state enable for all db pins 14 | 15 | // create an emulation clock from clk_50mhz 16 | 17 | wire eclk, ereset; 18 | 19 | clock_and_reset _clk(clk_50mhz, eclk, ereset); 20 | 21 | // synthesize the 6502 external clock and reset 22 | 23 | wire res, clk0; 24 | 25 | clocks_6502 _clocks_6502(eclk,ereset, res, clk0); 26 | 27 | wire so = 1'b0; 28 | wire rdy = 1'b1; 29 | wire nmi = 1'b1; 30 | wire irq = 1'b1; 31 | 32 | // instantiate the 6502 model 33 | 34 | chip_6502 _chip_6502(eclk, ereset, 35 | ab[0], ab[1], ab[2], ab[3], ab[4], ab[5], ab[6], ab[7], ab[8], ab[9], ab[10], ab[11], ab[12], ab[13], ab[14], ab[15], 36 | db_i[0], db_o[0], db_t[0], db_i[1], db_o[1], db_t[1], db_i[2], db_o[2], db_t[2], db_i[3], db_o[3], db_t[3], 37 | db_i[4], db_o[4], db_t[4], db_i[5], db_o[5], db_t[5], db_i[6], db_o[6], db_t[6], db_i[7], db_o[7], db_t[7], 38 | res, rw, sync, so, clk0, clk1out, clk2out, rdy, nmi, irq); 39 | 40 | // address decoding 41 | 42 | wire [7:0] keyboard_data; 43 | wire keyboard_flag; 44 | wire [7:0] display_data; 45 | wire display_ready; 46 | wire [7:0] db_rom; 47 | wire [7:0] db_ram; 48 | 49 | wire [3:0] page = ab[15:12]; 50 | assign db_i = 51 | (page==4'he || page==4'hf) ? db_rom : 52 | (ab[15]==1'b0) ? db_ram : 53 | (ab==16'hd010) ? {1'b1,keyboard_data[6:0]} : 54 | (ab==16'hd011) ? {keyboard_flag,7'd0} : 55 | ((ab==16'hd012)||(ab==16'hd0f2)) ? {!display_ready,display_data[6:0]} : 8'd0; 56 | 57 | // I/O strobes 58 | 59 | reg clk2out1; 60 | always @(posedge eclk) 61 | clk2out1 <= clk2out; 62 | 63 | wire wr = !rw & clk2out1 & !clk2out; 64 | wire rd = rw & clk2out1 & !clk2out; 65 | 66 | wire wr_ram = (ab[15]==1'b0) && wr; 67 | wire rd_keyboard = (ab==16'hd010) && rd; 68 | wire wr_display = ((ab==16'hd012)||(ab==16'hd0f2)) && wr; 69 | wire wr_leds = (ab==16'ha000) && wr; 70 | 71 | // ROM 72 | 73 | rom_6502 _rom_6502(eclk, ereset, 74 | ab, db_rom); 75 | 76 | // RAM 77 | 78 | ram_6502 _ram_6502(eclk, ereset, 79 | ab, db_ram, wr_ram, db_o); 80 | 81 | // RS-232 transceiver 82 | 83 | wire [7:0] rx_data; 84 | wire rx_flag; 85 | wire rx_ack; 86 | wire [7:0] tx_data; 87 | wire tx_flag; 88 | wire tx_wr; 89 | 90 | uart _uart(eclk, ereset, 91 | rs232_dce_rxd, rs232_dce_txd, 92 | rx_data, rx_flag, rx_ack, 93 | tx_data, tx_flag, tx_wr); 94 | 95 | // Apple 1 keyboard 96 | 97 | keyboard_6502 _keyboard_6502(eclk, ereset, 98 | rx_data, rx_flag, rx_ack, 99 | rd_keyboard, keyboard_data, keyboard_flag); 100 | 101 | // Apple 1 display 102 | 103 | display_6502 _display_6502(eclk, ereset, 104 | tx_data, tx_flag, tx_wr, 105 | wr_display, db_o, display_data, display_ready); 106 | 107 | // on-board LEDs 108 | 109 | leds _leds(eclk, ereset, 110 | led, 111 | wr_leds, db_o); 112 | 113 | endmodule 114 | 115 | // 116 | // SoC peripherals 117 | // 118 | 119 | module keyboard_6502( 120 | input eclk,ereset, 121 | input [7:0] rx_data, 122 | input rx_flag, 123 | output rx_ack, 124 | input rd_keyboard, 125 | output [7:0] keyboard_data, 126 | output keyboard_flag 127 | ); 128 | 129 | assign rx_ack = rd_keyboard; 130 | assign keyboard_data = {rx_data[7:6],rx_data[6] ? 1'b0 : rx_data[5],rx_data[4:0]}; // force incoming keyboard data to upper case 131 | assign keyboard_flag = rx_flag; 132 | 133 | endmodule 134 | 135 | module display_6502( 136 | input eclk,ereset, 137 | output [7:0] tx_data, 138 | input tx_flag, 139 | output reg tx_wr, 140 | input wr_display, 141 | input [7:0] db_o, 142 | output reg [7:0] display_data, 143 | output display_ready 144 | ); 145 | 146 | assign tx_data = {1'b0,display_data[6:0]}; 147 | 148 | always @(posedge eclk) 149 | if (ereset) 150 | tx_wr <= 0; 151 | else 152 | tx_wr <= wr_display; 153 | 154 | always @(posedge eclk) 155 | if (ereset) 156 | display_data <= 0; 157 | else if (wr_display) 158 | display_data <= db_o; 159 | 160 | assign display_ready = tx_flag; 161 | 162 | endmodule 163 | 164 | // 165 | // Generate an emulation clock and an internally generated synchronous reset. 166 | // For now just use the board's native 50 MHz; later can use a DCM to multiply up 167 | // to something higher. 168 | // 169 | 170 | module clock_and_reset( 171 | input clk_50mhz, 172 | output eclk, 173 | output ereset 174 | ); 175 | 176 | wire _clk_50mhz; 177 | wire clk_5625mhz; 178 | 179 | IBUFG i0(.I(clk_50mhz), .O(_clk_50mhz)); 180 | dcm_fx #(9,8) _dcm(_clk_50mhz, clk_5625mhz); 181 | BUFG b0(.I(clk_5625mhz), .O(eclk)); 182 | 183 | reg [7:0] r = 8'd0; 184 | 185 | always @(posedge eclk) 186 | r <= {r[6:0], 1'b1}; 187 | 188 | assign ereset = ~r[7]; 189 | 190 | endmodule 191 | 192 | module dcm_fx( 193 | input clk_in, 194 | output clk_out 195 | ); 196 | 197 | parameter N = 2; 198 | parameter D = 1; 199 | 200 | DCM_SP #( 201 | .CLKFX_DIVIDE(D), // Can be any integer from 1 to 32 202 | .CLKFX_MULTIPLY(N), // Can be any integer from 2 to 32 203 | .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE 204 | ) DCM_SP_inst ( 205 | .CLKFX(clk_out), // DCM CLK synthesis out (M/D) 206 | .CLKIN(clk_in) // Clock input (from IBUFG, BUFG or DCM) 207 | ); 208 | 209 | endmodule 210 | 211 | // 212 | // 32K RAM 213 | // 214 | 215 | module ram_6502( 216 | input eclk,ereset, 217 | input [15:0] ab, 218 | output reg [7:0] d, 219 | input wr, 220 | input [7:0] din 221 | ); 222 | 223 | reg [7:0] mem[0:32767]; 224 | 225 | always @(posedge eclk) 226 | d <= mem[ab[14:0]]; 227 | 228 | always @(posedge eclk) 229 | if (wr) 230 | mem[ab[14:0]] <= din; 231 | 232 | endmodule 233 | 234 | // 235 | // 8 LEDs as an output port 236 | // 237 | 238 | module leds( 239 | input eclk, ereset, 240 | output reg [7:0] led, 241 | input wr_leds, 242 | input [7:0] din 243 | ); 244 | 245 | always @(posedge eclk) 246 | if (ereset) 247 | led <= 0; 248 | else if (wr_leds) 249 | led <= din; 250 | 251 | endmodule 252 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/test.v: -------------------------------------------------------------------------------- 1 | module test(); 2 | reg clk; 3 | 4 | initial begin 5 | clk = 0; 6 | forever #5 clk = ~clk; 7 | end 8 | 9 | wire [7:0] led; 10 | wire rx; 11 | wire tx; 12 | 13 | system _system(clk, led, rx, tx); 14 | 15 | initial begin 16 | $dumpfile("test_sys.lxt"); 17 | $dumpvars(0,test); 18 | #400000; 19 | $finish(); 20 | end 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/uart.v: -------------------------------------------------------------------------------- 1 | // wrapper for uart_transceiver.v 2 | 3 | module uart( 4 | input clk,reset, 5 | input rs232_rxd, 6 | output rs232_txd, 7 | output reg [7:0] rx_data, 8 | output reg rx_flag, 9 | input rx_ack, 10 | input [7:0] tx_data, 11 | output reg tx_flag, 12 | input tx_wr 13 | ); 14 | 15 | wire [7:0] rx_d; 16 | 17 | // wire [15:0] divisor = 16'd163; // 19200 baud at 50 MHz, 0.15 percent error 18 | wire [15:0] divisor = 16'd183; // 19200 baud at 56.25 MHz 19 | 20 | uart_transceiver _uart_transceiver(.sys_clk(clk), .sys_rst(reset), 21 | .uart_rx(rs232_rxd), .uart_tx(rs232_txd), 22 | .divisor(divisor), 23 | .rx_data(rx_d), .rx_done(rx_done), 24 | .tx_data(tx_data), .tx_wr(tx_wr), .tx_done(tx_done)); 25 | 26 | // RX 27 | 28 | always @(posedge clk) 29 | if (reset) 30 | rx_flag <= 0; 31 | else begin 32 | if (rx_done) begin 33 | rx_flag <= 1; 34 | rx_data <= rx_d; 35 | end else if (rx_ack) 36 | rx_flag <= 0; 37 | end 38 | 39 | // TX 40 | 41 | reg [1:0] tx_state; 42 | 43 | always @(posedge clk) 44 | if (reset) begin 45 | tx_state <= 0; 46 | tx_flag <= 1; 47 | end else 48 | case (tx_state) 49 | 2'd0: if (tx_wr) begin tx_flag <= 0; tx_state <= 2'd1; end 50 | 2'd1: if (tx_done) tx_state <= 2'd2; 51 | 2'd2: if (!tx_done) begin tx_flag <= 1; tx_state <= 2'd0; end 52 | endcase 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /targets/digilent-s3e-starter/uart_transceiver.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Milkymist VJ SoC 3 | * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq 4 | * Copyright (C) 2007 Das Labor 5 | * 6 | * This program is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation, version 3 of the License. 9 | * 10 | * This program is distributed in the hope that it will be useful, 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | * GNU General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | module uart_transceiver( 20 | input sys_rst, 21 | input sys_clk, 22 | 23 | input uart_rx, 24 | output reg uart_tx, 25 | 26 | input [15:0] divisor, 27 | 28 | output reg [7:0] rx_data, 29 | output reg rx_done, 30 | 31 | input [7:0] tx_data, 32 | input tx_wr, 33 | output reg tx_done 34 | ); 35 | 36 | //----------------------------------------------------------------- 37 | // enable16 generator 38 | //----------------------------------------------------------------- 39 | reg [15:0] enable16_counter; 40 | 41 | wire enable16; 42 | assign enable16 = (enable16_counter == 16'd0); 43 | 44 | always @(posedge sys_clk) begin 45 | if(sys_rst) 46 | enable16_counter <= divisor - 16'b1; 47 | else begin 48 | enable16_counter <= enable16_counter - 16'd1; 49 | if(enable16) 50 | enable16_counter <= divisor - 16'b1; 51 | end 52 | end 53 | 54 | //----------------------------------------------------------------- 55 | // Synchronize uart_rx 56 | //----------------------------------------------------------------- 57 | reg uart_rx1; 58 | reg uart_rx2; 59 | 60 | always @(posedge sys_clk) begin 61 | uart_rx1 <= uart_rx; 62 | uart_rx2 <= uart_rx1; 63 | end 64 | 65 | //----------------------------------------------------------------- 66 | // UART RX Logic 67 | //----------------------------------------------------------------- 68 | reg rx_busy; 69 | reg [3:0] rx_count16; 70 | reg [3:0] rx_bitcount; 71 | reg [7:0] rx_reg; 72 | 73 | always @(posedge sys_clk) begin 74 | if(sys_rst) begin 75 | rx_done <= 1'b0; 76 | rx_busy <= 1'b0; 77 | rx_count16 <= 4'd0; 78 | rx_bitcount <= 4'd0; 79 | end else begin 80 | rx_done <= 1'b0; 81 | 82 | if(enable16) begin 83 | if(~rx_busy) begin // look for start bit 84 | if(~uart_rx2) begin // start bit found 85 | rx_busy <= 1'b1; 86 | rx_count16 <= 4'd7; 87 | rx_bitcount <= 4'd0; 88 | end 89 | end else begin 90 | rx_count16 <= rx_count16 + 4'd1; 91 | 92 | if(rx_count16 == 4'd0) begin // sample 93 | rx_bitcount <= rx_bitcount + 4'd1; 94 | 95 | if(rx_bitcount == 4'd0) begin // verify startbit 96 | if(uart_rx2) 97 | rx_busy <= 1'b0; 98 | end else if(rx_bitcount == 4'd9) begin 99 | rx_busy <= 1'b0; 100 | if(uart_rx2) begin // stop bit ok 101 | rx_data <= rx_reg; 102 | rx_done <= 1'b1; 103 | end // ignore RX error 104 | end else 105 | rx_reg <= {uart_rx2, rx_reg[7:1]}; 106 | end 107 | end 108 | end 109 | end 110 | end 111 | 112 | //----------------------------------------------------------------- 113 | // UART TX Logic 114 | //----------------------------------------------------------------- 115 | reg tx_busy; 116 | reg [3:0] tx_bitcount; 117 | reg [3:0] tx_count16; 118 | reg [7:0] tx_reg; 119 | 120 | always @(posedge sys_clk) begin 121 | if(sys_rst) begin 122 | tx_done <= 1'b0; 123 | tx_busy <= 1'b0; 124 | uart_tx <= 1'b1; 125 | end else begin 126 | tx_done <= 1'b0; 127 | if(tx_wr) begin 128 | tx_reg <= tx_data; 129 | tx_bitcount <= 4'd0; 130 | tx_count16 <= 4'd1; 131 | tx_busy <= 1'b1; 132 | uart_tx <= 1'b0; 133 | `ifdef SIMULATION 134 | $display("UART: %c", tx_data); 135 | `endif 136 | end else if(enable16 && tx_busy) begin 137 | tx_count16 <= tx_count16 + 4'd1; 138 | 139 | if(tx_count16 == 4'd0) begin 140 | tx_bitcount <= tx_bitcount + 4'd1; 141 | 142 | if(tx_bitcount == 4'd8) begin 143 | uart_tx <= 1'b1; 144 | end else if(tx_bitcount == 4'd9) begin 145 | uart_tx <= 1'b1; 146 | tx_busy <= 1'b0; 147 | tx_done <= 1'b1; 148 | end else begin 149 | uart_tx <= tx_reg[0]; 150 | tx_reg <= {1'b0, tx_reg[7:1]}; 151 | end 152 | end 153 | end 154 | end 155 | end 156 | 157 | endmodule 158 | -------------------------------------------------------------------------------- /targets/godil_6502/.gitignore: -------------------------------------------------------------------------------- 1 | # Xilinx cruft 2 | 3 | _xmsgs 4 | xlnx_auto_0_xdb 5 | xst 6 | 7 | *.bgn 8 | *.bit 9 | *.bld 10 | *.cfi 11 | *.drc 12 | *.map 13 | *.mcs 14 | *.mrp 15 | *.ncd 16 | *.ngc 17 | *.ngd 18 | *.ngm 19 | *.pad 20 | *.par 21 | *.pcf 22 | *.prm 23 | *.ptwx 24 | *.unroutes 25 | *.xpi 26 | 27 | *_bitgen.xwbt 28 | *_ngdbuild.xrpt 29 | *_pad.csv 30 | *_pad.txt 31 | *_summary.xml 32 | *_usage.xml 33 | *_xst.xrpt 34 | *_map.xrpt 35 | *_par.xrpt 36 | 37 | _impactbatch.log 38 | _impact.cmd 39 | _impact.log 40 | netlist.lst 41 | usage_statistics_webtalk.html 42 | webtalk.log 43 | -------------------------------------------------------------------------------- /targets/godil_6502/Makefile: -------------------------------------------------------------------------------- 1 | DEVICE=xc3s500e-4vq100 2 | 3 | all: 4 | echo "run -ifn chip.v -ifmt Verilog -top godil40_xc3s500e -ofn chip -p ${DEVICE}" | xst 5 | ngdbuild -p ${DEVICE} -uc chip.ucf chip 6 | map -w -timing -p ${DEVICE} chip.ngd chip.pcf 7 | par -w chip.ncd chip.ncd chip.pcf 8 | bitgen -g StartupClk:JtagClk -g GTS_cycle:3 -g LCK_cycle:4 -g GWE_cycle:5 -g DONE_cycle:6 -w chip.ncd chip.bit chip.pcf 9 | promgen -w -u 0 chip.bit -p mcs 10 | 11 | clean: 12 | rm -rf xst _xmsgs xlnx_auto_0_xdb 13 | rm -f *~ 14 | rm -f *.bgn *.bld *.drc *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.pad *.par *.pcf *.ptwx *.unroutes *.xpi 15 | rm -f *.cfi *.prm 16 | rm -f _impact.cmd _impact.log 17 | rm -f *_bitgen.xwbt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_summary.xml *_usage.xml 18 | rm -f *_xst.xrpt *_map.xrpt *_par.xrpt 19 | rm -f _impactbatch.log netlist.lst usage_statistics_webtalk.html webtalk.log 20 | -------------------------------------------------------------------------------- /targets/godil_6502/chip.ucf: -------------------------------------------------------------------------------- 1 | # Clock period constraint. 2 | # Ignore godil's 49.152 MHz crystal oscillator for now; instead use the 3 | # incoming clk0 from the host system and multiply it by about 60 using DCMs. 4 | # For concreteness, Use Apple II's clock of nominally 14.31818 MHz divided by 14 5 | 6 | #net clk0 period = 977.777ns; # 1.022727 MHz clk0 (6502 pin 37) from host system 7 | 8 | net "clk_49152mhz" loc = "p89" | iostandard = LVCMOS33 ; 9 | 10 | # inputs only 11 | #NET m49 LOC=P89 | IOSTANDARD = LVCMOS33 ; 12 | #NET sw1 LOC=P39 | IOSTANDARD = LVCMOS33 ; 13 | #NET sw2 LOC=P69 | IOSTANDARD = LVCMOS33 | PULLUP ; 14 | #NET c13 LOC=P38 | IOSTANDARD = LVCMOS33 | PULLUP ; 15 | #NET d13 LOC=P88 | IOSTANDARD = LVCMOS33 | PULLUP ; 16 | #NET sout LOC=P13 | IOSTANDARD = LVCMOS33 | PULLUP ; 17 | #NET rts LOC=P30 | IOSTANDARD = LVCMOS33 | PULLUP ; 18 | 19 | # I/O's for uart & spi flash 20 | NET led<0> LOC=P43 | IOSTANDARD = LVCMOS33 ; // sin 21 | NET led<1> LOC=P25 | IOSTANDARD = LVCMOS33 ; // cts 22 | #NET cso LOC=P24 | IOSTANDARD = LVCMOS33 ; 23 | #NET vs2 LOC=P47 | IOSTANDARD = LVCMOS33 ; 24 | 25 | # I/O's for test connector 26 | #NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 27 | #NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 28 | #NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 29 | #NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 30 | #NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 31 | #NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 32 | #NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 33 | 34 | # I/O's for DIL / main connector 35 | # 6502 pinout 36 | 37 | #NET pin<1> LOC=P16 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 1 is Vss 38 | NET rdy LOC=P95 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 2 39 | NET clk1out LOC=P18 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 3 40 | NET irq LOC=P17 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 4 41 | #NET pin<5> LOC=P94 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 5 is NC 42 | NET nmi LOC=P22 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 6 43 | NET sync LOC=P23 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 7 44 | #NET pin<8> LOC=P33 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 8 is Vcc 45 | NET ab<0> LOC=P32 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 9 46 | NET ab<1> LOC=P34 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 10 47 | NET ab<2> LOC=P40 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 11 48 | NET ab<3> LOC=P41 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 12 49 | NET ab<4> LOC=P36 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 13 50 | NET ab<5> LOC=P35 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 14 51 | NET ab<6> LOC=P53 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 15 52 | NET ab<7> LOC=P54 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 16 53 | NET ab<8> LOC=P57 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 17 54 | NET ab<9> LOC=P58 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 18 55 | NET ab<10> LOC=P60 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 19 56 | NET ab<11> LOC=P61 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 20 57 | #NET pin<21> LOC=P67 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 21 is Vss 58 | NET ab<12> LOC=P68 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 22 59 | NET ab<13> LOC=P70 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 23 60 | NET ab<14> LOC=P71 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 24 61 | NET ab<15> LOC=P86 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 25 62 | NET db<7> LOC=P84 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 26 63 | NET db<6> LOC=P83 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 27 64 | NET db<5> LOC=P78 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 28 65 | NET db<4> LOC=P79 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 29 66 | NET db<3> LOC=P85 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 30 67 | NET db<2> LOC=P92 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 31 68 | NET db<1> LOC=P98 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 32 69 | NET db<0> LOC=P3 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 33 70 | NET rw LOC=P2 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 34 71 | #NET pin<35> LOC=P4 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 35 is NC 72 | #NET pin<36> LOC=P5 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 36 is NC 73 | NET clk0 LOC=P90 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 37 74 | NET so LOC=P9 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 38 75 | NET clk2out LOC=P10 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 39 76 | NET res LOC=P11 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 40 77 | 78 | # unused I/Os 79 | 80 | #NET pin_c1 LOC=P26 | IOSTANDARD = LVCMOS33 | PULLUP ; 81 | #NET pin_a2 LOC=P15 | IOSTANDARD = LVCMOS33 | PULLUP ; 82 | #NET pin_a24 LOC=P62 | IOSTANDARD = LVCMOS33 | PULLUP ; 83 | #NET pin_c25 LOC=P63 | IOSTANDARD = LVCMOS33 | PULLUP ; 84 | 85 | #NET pin_d1 LOC=P91 | IOSTANDARD = LVCMOS33 | PULLUP ; 86 | #NET pin_b2 LOC=P12 | IOSTANDARD = LVCMOS33 | PULLUP ; 87 | #NET pin_b24 LOC=P66 | IOSTANDARD = LVCMOS33 | PULLUP ; 88 | #NET pin_d25 LOC=P65 | IOSTANDARD = LVCMOS33 | PULLUP ; 89 | -------------------------------------------------------------------------------- /targets/godil_6502/chip.v: -------------------------------------------------------------------------------- 1 | `define W 6 2 | 3 | `include "../../verilog/chip_6502.v" 4 | `include "../../verilog/models.v" 5 | `include "godil.v" 6 | -------------------------------------------------------------------------------- /targets/godil_6502/godil.v: -------------------------------------------------------------------------------- 1 | // Top-level module for GODIL40_XC3S500E board 2 | 3 | module godil40_xc3s500e( 4 | input clk_49152mhz, 5 | // start of 6502 pins on DIL40 connector 6 | output [15:0] ab, 7 | inout [7:0] db, 8 | input res, 9 | output rw, 10 | output sync, 11 | input so, 12 | input clk0, 13 | output clk1out, 14 | output clk2out, 15 | input rdy, 16 | input nmi, 17 | input irq, 18 | // end of 6502 pins on DIL40 connector 19 | output [1:0] led 20 | ); 21 | 22 | // handle three-state data bus 23 | 24 | wire [7:0] db_i; 25 | wire [7:0] db_o; 26 | wire [7:0] db_t; // not yet properly set by the 6502 model; instead use rw for the three-state enable for all db pins 27 | 28 | assign db_i = db; 29 | assign db = rw ? 8'bz : db_o; 30 | 31 | // create an emulation clock from clk_49152mhz 32 | 33 | wire eclk, ereset; 34 | 35 | clock_and_reset _clk(clk_49152mhz, eclk, ereset); 36 | 37 | // blink an LED using eclk 38 | 39 | blink #(26) _blink0(eclk, led[0]); 40 | 41 | assign led[1] = !res; 42 | 43 | // instantiate the 6502 model 44 | 45 | chip_6502 _chip_6502(eclk, ereset, 46 | ab[0], ab[1], ab[2], ab[3], ab[4], ab[5], ab[6], ab[7], ab[8], ab[9], ab[10], ab[11], ab[12], ab[13], ab[14], ab[15], 47 | db_i[0], db_o[0], db_t[0], db_i[1], db_o[1], db_t[1], db_i[2], db_o[2], db_t[2], db_i[3], db_o[3], db_t[3], 48 | db_i[4], db_o[4], db_t[4], db_i[5], db_o[5], db_t[5], db_i[6], db_o[6], db_t[6], db_i[7], db_o[7], db_t[7], 49 | res, rw, sync, so, clk0, clk1out, clk2out, rdy, nmi, irq); 50 | 51 | endmodule 52 | 53 | // 54 | // Make emulation clock from on-board 49.152 MHz oscillator 55 | // 56 | 57 | module clock_and_reset( 58 | input clk_in, 59 | output eclk, 60 | output ereset 61 | ); 62 | 63 | wire clk_56mhz; 64 | dcm_mult #(8,7) _dcm0(clk_in, clk_56mhz); 65 | BUFG b0(.I(clk_56mhz), .O(eclk)); 66 | 67 | reg [7:0] r = 8'd0; 68 | 69 | always @(posedge eclk) 70 | r <= {r[6:0], 1'b1}; 71 | 72 | assign ereset = ~r[7]; 73 | 74 | endmodule 75 | 76 | module dcm_mult( 77 | input clk_in, 78 | output clk_out 79 | ); 80 | 81 | parameter N = 2; 82 | parameter D = 2; 83 | 84 | wire clk_m; 85 | 86 | DCM_SP #( 87 | .CLKFX_DIVIDE(D), // Can be any integer from 1 to 32 88 | .CLKFX_MULTIPLY(N), // Can be any integer from 2 to 32 89 | .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE 90 | ) DCM_SP_inst ( 91 | .CLKFX(clk_out), // DCM CLK synthesis out (M/D) 92 | .CLKIN(clk_in) // Clock input (from IBUFG, BUFG or DCM) 93 | ); 94 | 95 | endmodule 96 | 97 | module blink( 98 | input clk, 99 | output led 100 | ); 101 | 102 | parameter W = 8; 103 | 104 | reg [W-1:0] c; 105 | 106 | always @(posedge clk) 107 | c <= c + 1; 108 | 109 | assign led = c[W-1]; 110 | 111 | endmodule 112 | -------------------------------------------------------------------------------- /targets/godil_6507/.gitignore: -------------------------------------------------------------------------------- 1 | # Xilinx cruft 2 | 3 | _xmsgs 4 | xlnx_auto_0_xdb 5 | xst 6 | 7 | *.bgn 8 | *.bld 9 | *.cfi 10 | *.drc 11 | *.map 12 | *.mrp 13 | *.ncd 14 | *.ngc 15 | *.ngd 16 | *.ngm 17 | *.pad 18 | *.par 19 | *.pcf 20 | *.prm 21 | *.psr 22 | *.ptwx 23 | *.twr 24 | *.twx 25 | *.unroutes 26 | *.xpi 27 | 28 | *_bitgen.xwbt 29 | *_ngdbuild.xrpt 30 | *_pad.csv 31 | *_pad.txt 32 | *_summary.xml 33 | *_usage.xml 34 | *_xst.xrpt 35 | *_map.xrpt 36 | *_par.xrpt 37 | 38 | _impactbatch.log 39 | _impact.cmd 40 | _impact.log 41 | netlist.lst 42 | usage_statistics_webtalk.html 43 | webtalk.log 44 | -------------------------------------------------------------------------------- /targets/godil_6507/Makefile: -------------------------------------------------------------------------------- 1 | DEVICE=xc3s500e-4vq100 2 | 3 | all: 4 | echo "run -ifn chip.v -ifmt Verilog -top godil40_xc3s500e -ofn chip -p ${DEVICE}" | xst 5 | ngdbuild -p ${DEVICE} -uc chip.ucf chip 6 | map -w -timing -detail -ol high -p ${DEVICE} chip.ngd chip.pcf 7 | par -w -ol high chip.ncd chip.ncd chip.pcf 8 | trce -v 20 chip.ncd chip.pcf 9 | bitgen -g StartupClk:CClk -g GTS_cycle:3 -g LCK_cycle:4 -g GWE_cycle:5 -g DONE_cycle:6 -w chip.ncd chip.bit chip.pcf 10 | promgen -w -spi -p mcs -s 4096 -u 0 chip.bit 11 | 12 | clean: 13 | rm -rf xst _xmsgs xlnx_auto_0_xdb 14 | rm -f *~ 15 | rm -f *.bgn *.bld *.drc *.map *.mrp *.ncd *.ngc *.ngd *.ngm *.pad *.par *.pcf *.ptwx *.unroutes *.xpi 16 | rm -f *.cfi *.prm 17 | rm -f _impact.cmd _impact.log 18 | rm -f *_bitgen.xwbt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_summary.xml *_usage.xml 19 | rm -f *_xst.xrpt *_map.xrpt *_par.xrpt 20 | rm -f _impactbatch.log netlist.lst usage_statistics_webtalk.html webtalk.log 21 | rm -f *.psr *.twr *.twx 22 | rm -f output.txt 23 | -------------------------------------------------------------------------------- /targets/godil_6507/chip.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pmonta/FPGA-netlist-tools/6bdbdf93db27e00356f0707dcc04fba3c5d2d865/targets/godil_6507/chip.bit -------------------------------------------------------------------------------- /targets/godil_6507/chip.ucf: -------------------------------------------------------------------------------- 1 | # Clock period constraint. 2 | # Ignore godil's 49.152 MHz crystal oscillator for now; instead use the 3 | # incoming clk0 from the host system and multiply it by about 60 using DCMs. 4 | # For concreteness, Use Apple II's clock of nominally 14.31818 MHz divided by 14 5 | 6 | #net clk0 period = 838.095ns; # 1.1931818 MHz clk0 (fsc/3) (6507 pin xx) from host system 7 | net clk_49152mhz period = 20.345ns; 8 | 9 | net "clk_49152mhz" loc = "p89" | iostandard = LVCMOS33 ; 10 | 11 | # inputs only 12 | #NET m49 LOC=P89 | IOSTANDARD = LVCMOS33 ; 13 | #NET sw1 LOC=P39 | IOSTANDARD = LVCMOS33 ; 14 | #NET sw2 LOC=P69 | IOSTANDARD = LVCMOS33 | PULLUP ; 15 | #NET c13 LOC=P38 | IOSTANDARD = LVCMOS33 | PULLUP ; 16 | #NET d13 LOC=P88 | IOSTANDARD = LVCMOS33 | PULLUP ; 17 | #NET sout LOC=P13 | IOSTANDARD = LVCMOS33 | PULLUP ; 18 | #NET rts LOC=P30 | IOSTANDARD = LVCMOS33 | PULLUP ; 19 | 20 | # I/O's for uart & spi flash 21 | NET led<0> LOC=P43 | IOSTANDARD = LVCMOS33 ; // sin 22 | NET led<1> LOC=P25 | IOSTANDARD = LVCMOS33 ; // cts 23 | #NET cso LOC=P24 | IOSTANDARD = LVCMOS33 ; 24 | #NET vs2 LOC=P47 | IOSTANDARD = LVCMOS33 ; 25 | 26 | # I/O's for test connector 27 | #NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 28 | #NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 29 | #NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 30 | #NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 31 | #NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 32 | #NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 33 | #NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; 34 | 35 | # I/O's for DIL / main connector 36 | # 6502 pinout 37 | 38 | #NET x LOC=P16 | IOSTANDARD = LVCMOS33 | PULLUP ; # 39 | #NET x LOC=P95 | IOSTANDARD = LVCMOS33 | PULLUP ; # 40 | #NET x LOC=P18 | IOSTANDARD = LVCMOS33 | PULLUP ; # 41 | NET res LOC=P17 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 1 42 | #NET Vss LOC=P94 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 2 is Vss 43 | NET rdy LOC=P22 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 3 44 | #NET Vcc LOC=P23 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 4 is Vcc 45 | NET ab<0> LOC=P33 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 5 46 | NET ab<1> LOC=P32 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 6 47 | NET ab<2> LOC=P34 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 7 48 | NET ab<3> LOC=P40 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 8 49 | NET ab<4> LOC=P41 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 9 50 | NET ab<5> LOC=P36 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 10 51 | NET ab<6> LOC=P35 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 11 52 | NET ab<7> LOC=P53 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 12 53 | NET ab<8> LOC=P54 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 13 54 | NET ab<9> LOC=P57 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 14 55 | #NET x LOC=P58 | IOSTANDARD = LVCMOS33 | PULLUP ; # 56 | #NET x LOC=P60 | IOSTANDARD = LVCMOS33 | PULLUP ; # 57 | #NET x LOC=P61 | IOSTANDARD = LVCMOS33 | PULLUP ; # 58 | #NET x LOC=P67 | IOSTANDARD = LVCMOS33 | PULLUP ; # 59 | #NET x LOC=P68 | IOSTANDARD = LVCMOS33 | PULLUP ; # 60 | #NET x LOC=P70 | IOSTANDARD = LVCMOS33 | PULLUP ; # 61 | NET ab<10> LOC=P71 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 15 62 | NET ab<11> LOC=P86 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 16 63 | NET ab<12> LOC=P84 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 17 64 | NET db<7> LOC=P83 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 18 65 | NET db<6> LOC=P78 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 19 66 | NET db<5> LOC=P79 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 20 67 | NET db<4> LOC=P85 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 21 68 | NET db<3> LOC=P92 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 22 69 | NET db<2> LOC=P98 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 23 70 | NET db<1> LOC=P3 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 24 71 | NET db<0> LOC=P2 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 25 72 | NET rw LOC=P4 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 26 73 | NET clk0 LOC=P5 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 27 74 | NET clk2out LOC=P90 | IOSTANDARD = LVCMOS33 | PULLUP ; # pin 28 75 | #NET x LOC=P9 | IOSTANDARD = LVCMOS33 | PULLUP ; # 76 | #NET x LOC=P10 | IOSTANDARD = LVCMOS33 | PULLUP ; # 77 | #NET x LOC=P11 | IOSTANDARD = LVCMOS33 | PULLUP ; # 78 | 79 | # unused I/Os 80 | 81 | #NET pin_c1 LOC=P26 | IOSTANDARD = LVCMOS33 | PULLUP ; 82 | #NET pin_a2 LOC=P15 | IOSTANDARD = LVCMOS33 | PULLUP ; 83 | #NET pin_a24 LOC=P62 | IOSTANDARD = LVCMOS33 | PULLUP ; 84 | #NET pin_c25 LOC=P63 | IOSTANDARD = LVCMOS33 | PULLUP ; 85 | 86 | #NET pin_d1 LOC=P91 | IOSTANDARD = LVCMOS33 | PULLUP ; 87 | #NET pin_b2 LOC=P12 | IOSTANDARD = LVCMOS33 | PULLUP ; 88 | #NET pin_b24 LOC=P66 | IOSTANDARD = LVCMOS33 | PULLUP ; 89 | #NET pin_d25 LOC=P65 | IOSTANDARD = LVCMOS33 | PULLUP ; 90 | -------------------------------------------------------------------------------- /targets/godil_6507/chip.v: -------------------------------------------------------------------------------- 1 | `define W 6 2 | 3 | `include "../../verilog/chip_6507.v" 4 | `include "../../verilog/chip_6502.v" 5 | `include "../../verilog/models.v" 6 | `include "godil.v" 7 | -------------------------------------------------------------------------------- /targets/godil_6507/godil.v: -------------------------------------------------------------------------------- 1 | // Top-level module for GODIL40_XC3S500E board 2 | 3 | module godil40_xc3s500e( 4 | input clk_49152mhz, 5 | // start of 6507 pins on DIL40 connector (using the center 28 pins) 6 | output [12:0] ab, 7 | inout [7:0] db, 8 | input res, 9 | output rw, 10 | input clk0, 11 | output clk2out, 12 | input rdy, 13 | // end of 6507 pins on DIL40 connector (using the center 28 pins) 14 | output [1:0] led 15 | ); 16 | 17 | // handle three-state data bus 18 | 19 | wire [7:0] db_i; 20 | wire [7:0] db_o; 21 | wire [7:0] db_t; // not yet properly set by the 6502 model; instead use rw for the three-state enable for all db pins 22 | 23 | assign db_i = db; 24 | assign db = rw ? 8'bz : db_o; 25 | 26 | // create an emulation clock from clk_49152mhz 27 | 28 | wire eclk, ereset; 29 | 30 | clock_and_reset _clk(clk_49152mhz, eclk, ereset); 31 | 32 | // blink an LED using eclk 33 | 34 | blink #(26) _blink0(eclk, led[0]); 35 | 36 | assign led[1] = !res; 37 | 38 | // instantiate the 6502 model 39 | 40 | chip_6507 _chip_6507(eclk, ereset, 41 | ab, db_i, db_o, res, rw, clk0, clk2out, rdy); 42 | 43 | endmodule 44 | 45 | // 46 | // Make emulation clock from on-board 49.152 MHz oscillator 47 | // 48 | 49 | module clock_and_reset( 50 | input clk_in, 51 | output eclk, 52 | output ereset 53 | ); 54 | 55 | wire clk_65mhz; 56 | dcm_mult #(3,2) _dcm0(clk_in, clk_65mhz); 57 | BUFG b0(.I(clk_65mhz), .O(eclk)); 58 | 59 | reg [7:0] r = 8'd0; 60 | 61 | always @(posedge eclk) 62 | r <= {r[6:0], 1'b1}; 63 | 64 | assign ereset = ~r[7]; 65 | 66 | endmodule 67 | 68 | module dcm_mult( 69 | input clk_in, 70 | output clk_out 71 | ); 72 | 73 | parameter N = 2; 74 | parameter D = 2; 75 | 76 | wire clk_m; 77 | 78 | DCM_SP #( 79 | .CLKFX_DIVIDE(D), // Can be any integer from 1 to 32 80 | .CLKFX_MULTIPLY(N), // Can be any integer from 2 to 32 81 | .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE 82 | ) DCM_SP_inst ( 83 | .CLKFX(clk_out), // DCM CLK synthesis out (M/D) 84 | .CLKIN(clk_in) // Clock input (from IBUFG, BUFG or DCM) 85 | ); 86 | 87 | endmodule 88 | 89 | module blink( 90 | input clk, 91 | output led 92 | ); 93 | 94 | parameter W = 8; 95 | 96 | reg [W-1:0] c; 97 | 98 | always @(posedge clk) 99 | c <= c + 1; 100 | 101 | assign led = c[W-1]; 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /verilator/.gitignore: -------------------------------------------------------------------------------- 1 | obj_dir 2 | -------------------------------------------------------------------------------- /verilator/Makefile: -------------------------------------------------------------------------------- 1 | sim: 2 | verilator -DW=6 -DHALFCYCLE=25 --cc ../verilog/top.v --top-module main -I../verilog --exe sim_main.cpp 3 | # (cd obj_dir ; make -f Vmain.mk ) 4 | (cd obj_dir ; make OPT_FAST="-O2" -f Vmain.mk ) 5 | 6 | run_monitor: 7 | (cd obj_dir ; ./Vmain -code ../../6502-test-code/apple1monitor.bin -code_start 65280) 8 | 9 | run_basic: 10 | (cd obj_dir ; ./Vmain -code ../../6502-test-code/apple1basic.bin -code_start 57344 -reset_vector 57344) 11 | 12 | clean: 13 | rm -rf obj_dir 14 | -------------------------------------------------------------------------------- /verilator/sim_main.cpp: -------------------------------------------------------------------------------- 1 | // Main program for verilator 6502 simulation; includes "driver" for Apple 1 I/O 2 | // (simple fixed strings for the moment on input; should fix this to use a socket 3 | // for console I/O) 4 | // 5 | // Copyright (c) 2010 Peter Monta 6 | 7 | #include 8 | #include 9 | #include 10 | #include 11 | 12 | #include "Vmain.h" 13 | #include "verilated.h" 14 | 15 | #include "Vmain_main.h" 16 | #include "Vmain_ram_6502.h" 17 | 18 | Vmain* top; 19 | 20 | void read_binary_file(char* filename,int start_addr) 21 | { ifstream myfile; 22 | char c; 23 | int addr; 24 | 25 | myfile.open(filename, ios::in | ios::binary); 26 | if (!myfile) { 27 | cerr << "error opening code file" << endl; 28 | return; } 29 | addr = start_addr; 30 | cout << "starting address: " << hex << addr << endl << flush; 31 | while (1) { 32 | myfile.read(&c,1); 33 | if (!myfile) 34 | break; 35 | top->v->_ram_6502->mem[addr++] = (int)((unsigned char)c); } 36 | myfile.close(); 37 | cout << "ending address: " << hex << addr << endl << flush; 38 | } 39 | 40 | void set_reset_vector(int x) 41 | { top->v->_ram_6502->mem[0xfffc] = x&0xff; 42 | top->v->_ram_6502->mem[0xfffd] = (x>>8)&0xff; 43 | cout << "reset vector: " << hex << x << endl << flush; } 44 | 45 | unsigned int main_time = 0; 46 | 47 | //char* x = "0FFF0.FFFF\r"; 48 | char* x = "0PRINT 1234/7\r"; 49 | int xi = 0; 50 | //int xmax = 11; 51 | int xmax = 14; 52 | 53 | void handle_io(Vmain* top) 54 | { int display_flag,display_byte; 55 | int key_ready; 56 | 57 | display_flag = top->v->_ram_6502->display_flag; 58 | display_byte = top->v->_ram_6502->display_byte; 59 | if (display_flag) { 60 | if (display_byte==0x0d) 61 | display_byte = 0x0a; 62 | cout << char(display_byte) << flush; 63 | // cout << "<" << int(display_byte) << ">" << flush; 64 | top->v->_ram_6502->display_flag = 0; } 65 | 66 | key_ready = top->v->_ram_6502->key_ready; 67 | if ((!key_ready) && (xiv->_ram_6502->mem[0xd010] = x[xi++] | 0x80; 70 | top->v->_ram_6502->key_ready = 1; } 71 | 72 | } 73 | 74 | int status_address = 0; 75 | char code_filename[100]; 76 | int code_start; 77 | int do_reset_vector = 0; 78 | int reset_vector; 79 | 80 | void args(int argc, char* argv[]) 81 | { int i; 82 | for (i=0; iv->ab) << "]" << flush; } 96 | 97 | int main(int argc, char **argv, char **env) 98 | { Verilated::commandArgs(argc, argv); 99 | args(argc, argv); 100 | 101 | top = new Vmain; 102 | 103 | read_binary_file(code_filename,code_start); 104 | if (do_reset_vector) 105 | set_reset_vector(reset_vector); 106 | 107 | top->v->eclk = 0; 108 | top->v->ereset = 1; 109 | top->eval(); 110 | 111 | while (!Verilated::gotFinish()) { 112 | if (main_time>200) 113 | top->v->ereset = 0; 114 | top->v->eclk = 1; 115 | top->eval(); 116 | main_time++; 117 | if (main_time>20000) 118 | handle_io(top); 119 | top->v->eclk = 0; 120 | top->eval(); 121 | main_time++; 122 | if (main_time>20000) 123 | handle_io(top); 124 | if ((main_time%180000)==0) 125 | status(top); 126 | } 127 | 128 | exit(0); } 129 | -------------------------------------------------------------------------------- /verilog/chip_6507.v: -------------------------------------------------------------------------------- 1 | module chip_6507( 2 | input eclk, ereset, 3 | output [12:0] ab, 4 | input [7:0] db_i, 5 | output [7:0] db_o, 6 | input res, 7 | output rw, 8 | input clk0, 9 | output clk2out, 10 | input rdy 11 | ); 12 | 13 | wire [7:0] db_t; 14 | 15 | wire sync; 16 | wire so = 1'b1; 17 | wire clk1out; 18 | wire nmi = 1'b1; 19 | wire irq = 1'b1; 20 | 21 | wire _a13, _a14, _a15; 22 | 23 | chip_6502 _chip_6502( 24 | eclk, ereset, 25 | ab[0], ab[1], ab[2], ab[3], ab[4], ab[5], ab[6], ab[7], 26 | ab[8], ab[9], ab[10], ab[11], ab[12], _a13, _a14, _a15, 27 | db_i[0], db_o[0], db_t[0], 28 | db_i[1], db_o[1], db_t[1], 29 | db_i[2], db_o[2], db_t[2], 30 | db_i[3], db_o[3], db_t[3], 31 | db_i[4], db_o[4], db_t[4], 32 | db_i[5], db_o[5], db_t[5], 33 | db_i[6], db_o[6], db_t[6], 34 | db_i[7], db_o[7], db_t[7], 35 | res, rw, sync, so, clk0, clk1out, clk2out, rdy, nmi, irq); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /verilog/clocks_4004.v: -------------------------------------------------------------------------------- 1 | // Generate reset and clk1 and clk2 for the 4004 core 2 | // 3 | // Copyright (c) 2011 Peter Monta 4 | 5 | module clocks_4004( 6 | input eclk, ereset, 7 | output reg reset, 8 | output clk1, 9 | output clk2 10 | ); 11 | 12 | reg [19:0] c; 13 | reg [7:0] i; 14 | reg [1:0] p; 15 | 16 | always @(posedge eclk) 17 | if (ereset) begin 18 | c <= 0; 19 | reset <= 1; 20 | p <= 0; 21 | i <= 0; 22 | end else begin 23 | c <= c + 1; 24 | if (c==20'd700000) 25 | reset <= 0; 26 | if (i==8'd`QUARTERCYCLE-1) begin 27 | i <= 0; 28 | p <= p+1; 29 | end else 30 | i <= i + 1; 31 | end 32 | 33 | assign clk1 = p==2'd0; 34 | assign clk2 = p==2'd2; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /verilog/clocks_6502.v: -------------------------------------------------------------------------------- 1 | // Generate reset and clk0 for the 6502 core 2 | // 3 | // Copyright (c) 2010 Peter Monta 4 | 5 | module clocks_6502(input eclk, ereset, output reg res, output reg clk0); 6 | reg [10:0] c; 7 | reg [7:0] i; 8 | 9 | always @(posedge eclk) 10 | if (ereset) begin 11 | c <= 0; 12 | res <= 0; 13 | clk0 <= 0; 14 | i <= 0; 15 | end else begin 16 | c <= c + 1; 17 | if (c==11'd2047) 18 | res <= 1; 19 | if (i==8'd`HALFCYCLE-1) begin 20 | i <= 0; 21 | clk0 <= ~clk0; 22 | end else 23 | i <= i + 1; 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /verilog/common.h: -------------------------------------------------------------------------------- 1 | // Common defines for 6502 Verilog 2 | // 3 | // Copyright (c) 2010 Peter Monta 4 | 5 | // precision of voltage, current variables is W bits (two's complement); 6 | // definition of `W is from Makefile 7 | 8 | // levels for HI and LO 9 | 10 | `define HI (`W'd3<<(`W-3)) 11 | `define LO (-(`W'd2<<(`W-3))) 12 | 13 | `define HI2 (`W'd2<<(`W-4)) 14 | `define LO2 (-(`W'd2<<(`W-4))) 15 | -------------------------------------------------------------------------------- /verilog/models.v: -------------------------------------------------------------------------------- 1 | // Models for transistors and nodes 2 | // 3 | // Copyright (c) 2010 Peter Monta 4 | 5 | `include "common.h" 6 | 7 | module spice_pin_input(input p, input signed [`W-1:0] v, output signed [`W-1:0] i); 8 | wire [`W-1:0] vp = p ? `HI : `LO; 9 | wire [`W:0] dv = {vp[`W-1],vp} - {v[`W-1],v}; 10 | assign i = {{2{dv[`W]}},dv[`W:3]}; 11 | endmodule 12 | 13 | module spice_pin_output(output p, input signed [`W-1:0] v); 14 | assign p = ~v[`W-1]; 15 | endmodule 16 | 17 | module spice_pin_bidirectional(input p_i, output p_o, output p_t, input signed [`W-1:0] v, output signed [`W-1:0] i); 18 | assign p_o = ~v[`W-1]; 19 | wire [`W-1:0] vp = p_i ? `HI : `LO; 20 | wire [`W:0] dv = {vp[`W-1],vp} - {v[`W-1],v}; 21 | assign i = {{3{dv[`W]}},dv[`W:4]}; 22 | assign p_t = 0; //fixme 23 | endmodule 24 | 25 | module spice_transistor_nmos(input g, input signed [`W-1:0] vs,vd, output signed [`W-1:0] is,id); 26 | wire signed [`W:0] vsd = {vd[`W-1],vd} - {vs[`W-1],vs}; 27 | wire signed [`W-1:0] isd = {vsd[`W],vsd[`W:2]}; 28 | wire signed [`W-1:0] i = g ? isd : 0; 29 | assign is = i; 30 | assign id = -i; 31 | endmodule 32 | 33 | module spice_transistor_nmos_vdd(input g, input signed [`W-1:0] vs, output signed [`W-1:0] is); 34 | wire signed [`W-1:0] vd = `HI; 35 | wire signed [`W:0] vsd = {vd[`W-1],vd} - {vs[`W-1],vs}; 36 | wire signed [`W-1:0] isd = {{2{vsd[`W]}},vsd[`W:3]}; // heuristic for 6502: transistors that connect to vdd should be weaker 37 | assign is = g ? isd : `W'd0; 38 | endmodule 39 | 40 | module spice_transistor_nmos_gnd(input g, input signed [`W-1:0] vd, output signed [`W-1:0] id); 41 | wire signed [2:0] lo = 3'b110; 42 | wire signed [2:0] vdtop = lo - {vd[`W-1],vd[`W-1:`W-2]}; 43 | wire signed [`W:0] vsd = {vdtop,~vd[`W-3:0]}; 44 | wire signed [`W-1:0] i = {vsd[`W],vsd[`W:2]}; 45 | assign id = g ? i : `W'd0; 46 | endmodule 47 | 48 | module spice_pullup(input signed [`W-1:0] v, output signed [`W-1:0] i); 49 | // wire signed [2:0] hi = 3'b000; 50 | // wire signed [2:0] vdtop = hi - {v[`W-1],v[`W-1:`W-2]}; 51 | // wire signed [`W:0] dv = {vdtop,~v[`W-3:0]}; 52 | wire signed [`W-1:0] hi = `HI; 53 | wire signed [`W:0] dv = {hi[`W-1],hi} - {v[`W-1],v}; 54 | assign i = {{3{dv[`W]}},dv[`W:4]}; 55 | endmodule 56 | 57 | module spice_latch(input eclk,ereset, input g, input in, output reg out); 58 | 59 | always @(posedge eclk) 60 | if (ereset) begin 61 | out <= 0; 62 | end else begin 63 | if (g) 64 | out <= in; 65 | end 66 | 67 | endmodule 68 | 69 | module spice_latch_delay(input eclk,ereset, input g, input in, output reg out); 70 | 71 | reg in1,in2,in3,in4; 72 | 73 | always @(posedge eclk) 74 | if (ereset) begin 75 | out <= 0; 76 | {in1,in2,in3,in4} <= 0; 77 | end else begin 78 | {in1,in2,in3,in4} <= {in,in1,in2,in3}; 79 | if (g) 80 | out <= in4; 81 | end 82 | 83 | endmodule 84 | 85 | module mux_cascade(input c0,v0,c1,v1, output c, output reg v); 86 | assign c = c0 | c1; 87 | always @* 88 | case ({c0,c1}) 89 | 2'b10: v = v0; 90 | 2'b01: v = v1; 91 | 2'b11: v = ((v0==1'b0)|(v1==1'b0)) ? 0 : 1; 92 | default: v = 0; 93 | endcase 94 | endmodule 95 | -------------------------------------------------------------------------------- /verilog/ram_6502.v: -------------------------------------------------------------------------------- 1 | // RAM and peripherals for 6502 test system 2 | // fixme: separate peripherals into separate modules 3 | // 4 | // Copyright (c) 2010 Peter Monta 5 | 6 | module ram_6502(input eclk,ereset, input clk, input [15:0] a, output reg [7:0] dout, input [7:0] din, input rw); 7 | reg [7:0] mem[0:65535] /*verilator public*/; 8 | 9 | `ifndef verilator 10 | integer i; 11 | integer fp; 12 | integer pc; 13 | integer c; 14 | reg [15:0] reset; 15 | initial begin 16 | for (i=0; i<65536; i=i+1) 17 | mem[i] = 0; 18 | #4000; 19 | for (i=0; i<65536; i=i+1) 20 | mem[i] = 0; 21 | pc = 16'h`CODE_START; 22 | fp = $fopen(`CODE,"r"); 23 | c = $fgetc(fp); 24 | while (c!==32'hffffffff) begin 25 | mem[pc] = c; 26 | pc = pc + 1; 27 | c = $fgetc(fp); 28 | end 29 | reset = 16'h`RESET; 30 | mem[16'hfffc] = reset[7:0]; 31 | mem[16'hfffd] = reset[15:8]; 32 | $display($time,,"done initializing RAM; last address 0x%04x",pc); 33 | end 34 | `endif 35 | 36 | reg key_ready /*verilator public*/; 37 | reg display_ready; 38 | reg display_first; 39 | reg display_flag /*verilator public*/; 40 | reg [7:0] display_byte /*verilator public*/; 41 | 42 | reg clk1; 43 | 44 | always @(posedge eclk) 45 | if (ereset) begin 46 | dout <= 0; 47 | clk1 <= 0; 48 | key_ready <= 0; 49 | display_ready <= 1; 50 | display_first <= 1; 51 | display_flag <= 0; 52 | display_byte <= 8'd0; 53 | end else begin 54 | clk1 <= clk; 55 | dout <= (a==16'hd011) ? {key_ready,7'd0} : ((a==16'hd012)||(a==16'hd0f2)) ? {!display_ready,mem[a][6:0]} : mem[a]; 56 | // dout <= (a==16'hd011) ? {key_ready,mem[a][6:0]} : mem[a]; 57 | 58 | if (!clk && clk1 && rw) begin //reads 59 | if (a==16'hd011) begin 60 | // $display("read d011; clearing flag"); 61 | key_ready <= 0; 62 | end 63 | // if (a==16'hd012) begin 64 | // $display("read d012; value is 0x%02x 0x%02x",mem[a],dout); 65 | // end 66 | end 67 | 68 | if (!clk && clk1 && !rw) begin // writes 69 | `ifdef DISPLAY_WRITES 70 | $display("mem[%04x] <- %02x",a,din); 71 | `endif 72 | mem[a] <= din; 73 | if ((a==16'hd012)||(a==16'hd0f2)) begin // fixme: separate peripheral code from generic RAM code 74 | if (!display_first) begin 75 | display_byte <= din&8'h7f; 76 | display_flag <= 1; 77 | end 78 | display_first <= 0; 79 | end 80 | end 81 | end 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /verilog/rom_4004.v: -------------------------------------------------------------------------------- 1 | module rom_4004( 2 | input eclk, ereset, 3 | input clk1, clk2, sync, cm_rom, 4 | input [3:0] db, 5 | output [3:0] db_rom 6 | ); 7 | 8 | reg [11:0] a; 9 | reg [7:0] d; 10 | 11 | always @(a) 12 | case (a[3:0]) 13 | 4'd0: d = 8'hd5; 14 | 4'd1: d = 8'hd6; 15 | 4'd2: d = 8'hf2; 16 | 4'd3: d = 8'hf2; 17 | 4'd4: d = 8'hf2; 18 | 4'd5: d = 8'hf2; 19 | 4'd6: d = 8'hf2; 20 | 4'd7: d = 8'h40; 21 | 4'd8: d = 8'h06; 22 | 4'd9: d = 8'h00; 23 | 4'd10: d = 8'h00; 24 | 4'd11: d = 8'h00; 25 | 4'd12: d = 8'h00; 26 | 4'd13: d = 8'h00; 27 | 4'd14: d = 8'h00; 28 | 4'd15: d = 8'h00; 29 | endcase 30 | 31 | reg [2:0] c,c1; 32 | reg clk1p; 33 | reg clk2p; 34 | reg [7:0] d1; 35 | 36 | always @(posedge eclk) 37 | if (ereset) begin 38 | c <= 0; 39 | c1 <= 0; 40 | clk1p <= 0; 41 | clk2p <= 0; 42 | a <= 0; 43 | end else begin 44 | clk1p <= clk1; 45 | clk2p <= clk2; 46 | if (clk2 & !clk2p) begin 47 | c <= sync ? 0 : c+1; 48 | if (c==3'd0) 49 | a[3:0] <= db; 50 | if (c==3'd1) 51 | a[7:4] <= db; 52 | if (c==3'd2) 53 | a[11:8] <= db; 54 | end 55 | if (clk1 & !clk1p) begin 56 | c1 <= c; 57 | d1 <= d; 58 | end 59 | end 60 | 61 | assign db_rom = (c1==3'd3) ? d1[7:4] : (c1==3'd4) ? d1[3:0] : 4'h0; 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /verilog/test_4004.v: -------------------------------------------------------------------------------- 1 | // Top-level test SoC for 4004 core, clocks, ROM, RAM 2 | // 3 | // Copyright (c) 2011 Peter Monta 4 | 5 | module main(); 6 | wire eclk /*verilator public*/; 7 | wire ereset /*verilator public*/; 8 | 9 | `ifndef verilator 10 | clk_reset_gen _clk_reset_gen(eclk, ereset); 11 | `endif 12 | 13 | wire clk1, clk2, sync, reset, test; 14 | wire [3:0] db_i; 15 | wire [3:0] db_o; 16 | wire [3:0] db_t; 17 | wire cm_rom, cm_ram3, cm_ram2, cm_ram1, cm_ram0; 18 | 19 | assign test = 1; 20 | 21 | clocks_4004 _clocks_4004(eclk, ereset, reset, clk1, clk2); 22 | 23 | wire [3:0] db_rom; 24 | 25 | rom_4004 _rom_4004(eclk, ereset, clk1, clk2, sync, cm_rom, db_o, db_rom); 26 | 27 | assign db_i = db_rom; 28 | 29 | chip_4004 _chip_4004(eclk, ereset, 30 | clk1, clk2, sync, reset, test, 31 | db_i[0], db_o[0], db_t[0], db_i[1], db_o[1], db_t[1], db_i[2], db_o[2], db_t[2], db_i[3], db_o[3], db_t[3], 32 | cm_rom, cm_ram3, cm_ram2, cm_ram1, cm_ram0); 33 | 34 | `ifndef verilator 35 | initial begin 36 | $dumpfile("test_4004.lxt"); 37 | $dumpvars(0,main); 38 | #`MAXTICKS; 39 | $finish(); 40 | end 41 | `endif 42 | 43 | endmodule 44 | 45 | `ifndef verilator 46 | module clk_reset_gen(output reg clk, reset); 47 | initial begin 48 | reset = 1; 49 | #1000; 50 | reset = 0; 51 | end 52 | 53 | initial begin 54 | clk = 0; 55 | forever #5 clk = ~clk; 56 | end 57 | 58 | endmodule 59 | `endif 60 | -------------------------------------------------------------------------------- /verilog/test_6502.v: -------------------------------------------------------------------------------- 1 | // Top-level test SoC for 6502 core, RAM, peripherals, clocks 2 | // 3 | // Copyright (c) 2010 Peter Monta 4 | 5 | module main(); 6 | wire eclk /*verilator public*/; 7 | wire ereset /*verilator public*/; 8 | 9 | `ifndef verilator 10 | clk_reset_gen _clk_reset_gen(eclk, ereset); 11 | `endif 12 | 13 | wire [15:0] ab /*verilator public*/; 14 | wire [7:0] db_i; 15 | wire [7:0] db_o; 16 | wire [7:0] db_t; 17 | wire res, rw, sync, so, clk0, clk1out, clk2out, rdy, nmi, irq; 18 | 19 | assign so = 0; 20 | assign rdy = 1; 21 | assign nmi = 1; 22 | assign irq = 1; 23 | 24 | clocks_6502 _clocks_6502(eclk, ereset, res, clk0); 25 | 26 | chip_6502 _chip_6502(eclk, ereset, 27 | ab[0], ab[1], ab[2], ab[3], ab[4], ab[5], ab[6], ab[7], ab[8], ab[9], ab[10], ab[11], ab[12], ab[13], ab[14], ab[15], 28 | db_i[0], db_o[0], db_t[0], db_i[1], db_o[1], db_t[1], db_i[2], db_o[2], db_t[2], db_i[3], db_o[3], db_t[3], 29 | db_i[4], db_o[4], db_t[4], db_i[5], db_o[5], db_t[5], db_i[6], db_o[6], db_t[6], db_i[7], db_o[7], db_t[7], 30 | res, rw, sync, so, clk0, clk1out, clk2out, rdy, nmi, irq); 31 | 32 | ram_6502 _ram_6502(eclk, ereset, clk2out, ab, db_i, db_o, rw); 33 | 34 | `ifndef verilator 35 | initial begin 36 | $dumpfile("test_6502.lxt"); 37 | $dumpvars(0,main); 38 | #`MAXTICKS; 39 | $finish(); 40 | end 41 | `endif 42 | 43 | endmodule 44 | 45 | `ifndef verilator 46 | module clk_reset_gen(output reg clk, reset); 47 | initial begin 48 | reset = 1; 49 | #1000; 50 | reset = 0; 51 | end 52 | 53 | initial begin 54 | clk = 0; 55 | forever #5 clk = ~clk; 56 | end 57 | 58 | endmodule 59 | `endif 60 | -------------------------------------------------------------------------------- /verilog/top.v: -------------------------------------------------------------------------------- 1 | `include "chip_6502.v" 2 | `include "ram_6502.v" 3 | `include "clocks_6502.v" 4 | `include "test_6502.v" 5 | `include "models.v" 6 | -------------------------------------------------------------------------------- /visual6502/README: -------------------------------------------------------------------------------- 1 | These files are from the Visual 6502 project's JavaScript simulator: 2 | 3 | http://visual6502.org 4 | 5 | with the exception of the pins.txt file, which establishes the HDL port 6 | list and the type of each port (input, output, or bidirectional). 7 | -------------------------------------------------------------------------------- /visual6502/pins.txt: -------------------------------------------------------------------------------- 1 | ab0 output 2 | ab1 output 3 | ab2 output 4 | ab3 output 5 | ab4 output 6 | ab5 output 7 | ab6 output 8 | ab7 output 9 | ab8 output 10 | ab9 output 11 | ab10 output 12 | ab11 output 13 | ab12 output 14 | ab13 output 15 | ab14 output 16 | ab15 output 17 | db0 bidirectional 18 | db1 bidirectional 19 | db2 bidirectional 20 | db3 bidirectional 21 | db4 bidirectional 22 | db5 bidirectional 23 | db6 bidirectional 24 | db7 bidirectional 25 | res input 26 | rw output 27 | sync output 28 | so input 29 | clk0 input 30 | clk1out output 31 | clk2out output 32 | rdy input 33 | nmi input 34 | irq input 35 | --------------------------------------------------------------------------------