├── LICENSE ├── README.md ├── bench-cm0 ├── Makefile ├── core.c ├── curve9767.c ├── curve9767.h ├── ecdh.c ├── hash.c ├── inner.h ├── keygen.c ├── ops_arm.c ├── ops_cm0.s ├── samd20e18.ld ├── scalar_arm.c ├── scalar_cm0.s ├── sha3.c ├── sha3.h ├── sign.c ├── sysinc │ ├── CMSIS │ │ ├── core_cm0plus.h │ │ ├── core_cmFunc.h │ │ └── core_cmInstr.h │ ├── component │ │ ├── ac.h │ │ ├── adc.h │ │ ├── dac.h │ │ ├── dsu.h │ │ ├── eic.h │ │ ├── evsys.h │ │ ├── gclk.h │ │ ├── nvmctrl.h │ │ ├── pac.h │ │ ├── pm.h │ │ ├── port.h │ │ ├── rtc.h │ │ ├── sercom.h │ │ ├── sysctrl.h │ │ ├── tc.h │ │ └── wdt.h │ ├── instance │ │ ├── ac.h │ │ ├── adc.h │ │ ├── dac.h │ │ ├── dsu.h │ │ ├── eic.h │ │ ├── evsys.h │ │ ├── gclk.h │ │ ├── nvmctrl.h │ │ ├── pac0.h │ │ ├── pac1.h │ │ ├── pac2.h │ │ ├── pm.h │ │ ├── port.h │ │ ├── rtc.h │ │ ├── sercom0.h │ │ ├── sercom1.h │ │ ├── sercom2.h │ │ ├── sercom3.h │ │ ├── sercom4.h │ │ ├── sercom5.h │ │ ├── sysctrl.h │ │ ├── tc0.h │ │ ├── tc1.h │ │ ├── tc2.h │ │ ├── tc3.h │ │ ├── tc4.h │ │ ├── tc5.h │ │ ├── tc6.h │ │ ├── tc7.h │ │ └── wdt.h │ ├── pio │ │ └── samd20e18.h │ └── samd20e18.h └── timing.c ├── bench-cm4 ├── Makefile ├── curve9767.c ├── curve9767.h ├── ecdh.c ├── hash.c ├── inner.h ├── keygen.c ├── ops_arm.c ├── ops_cm4.s ├── scalar_arm.c ├── scalar_cm4.s ├── sha3.h ├── sha3_cm4.c ├── sign.c ├── stm32f4-discovery.ld └── timing.c ├── doc ├── curve9767.pdf ├── curve9767.tex └── llncs.cls ├── extra ├── findcurve.gp ├── findprime.sage ├── mktests.sage └── test-vectors.txt └── src ├── Makefile ├── Makefile.avx2 ├── Makefile.cm0 ├── Makefile.cm4 ├── curve9767.c ├── curve9767.h ├── ecdh.c ├── hash.c ├── inner.h ├── keygen.c ├── ops_arm.c ├── ops_avx2.c ├── ops_cm0.s ├── ops_cm4.s ├── ops_ref.c ├── scalar_amd64.c ├── scalar_arm.c ├── scalar_cm0.s ├── scalar_cm4.s ├── scalar_ref.c ├── sha3.c ├── sha3.h ├── sha3_cm4.c ├── sign.c ├── speed_amd64.c ├── speed_ref.c └── test_curve9767.c /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Thomas Pornin 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /bench-cm0/Makefile: -------------------------------------------------------------------------------- 1 | CC = arm-none-eabi-gcc 2 | CFLAGS = -Wall -Wextra -Wshadow -ggdb3 -Os $(ARCHFLAGS) -D__SAMD20E18__ -DDONT_USE_CMSIS_INIT -DCF_SIDE_CHANNEL_PROTECTION=0 -DCORTEX_M0 3 | LD = arm-none-eabi-gcc 4 | LDFLAGS = -Wl,--gc-sections $(ARCHFLAGS) 5 | LDLIBS = -Wl,--start-group -lgcc -lnosys -Wl,--end-group 6 | ARCHFLAGS = -mthumb -mlong-calls -mcpu=cortex-m0plus 7 | LINKER_SCRIPT = samd20e18.ld 8 | 9 | OBJS = core.o curve9767.o ecdh.o hash.o keygen.o ops_arm.o ops_cm0.o scalar_cm0.o scalar_arm.o sha3.o sign.o timing.o 10 | 11 | all: benchmark.elf 12 | 13 | clean: 14 | -rm -f benchmark.elf $(OBJS) 15 | 16 | benchmark.elf: $(OBJS) 17 | $(LD) $(LDFLAGS) -T$(LINKER_SCRIPT) -o benchmark.elf $(OBJS) $(LDLIBS) 18 | 19 | core.o: core.c 20 | $(CC) $(CFLAGS) -c -o core.o core.c 21 | 22 | curve9767.o: curve9767.c curve9767.h inner.h sha3.h 23 | $(CC) $(CFLAGS) -c -o curve9767.o curve9767.c 24 | 25 | ecdh.o: ecdh.c curve9767.h inner.h sha3.h 26 | $(CC) $(CFLAGS) -c -o ecdh.o ecdh.c 27 | 28 | hash.o: hash.c curve9767.h inner.h sha3.h 29 | $(CC) $(CFLAGS) -c -o hash.o hash.c 30 | 31 | keygen.o: keygen.c curve9767.h inner.h sha3.h 32 | $(CC) $(CFLAGS) -c -o keygen.o keygen.c 33 | 34 | ops_arm.o: ops_arm.c curve9767.h inner.h sha3.h 35 | $(CC) $(CFLAGS) -c -o ops_arm.o ops_arm.c 36 | 37 | ops_cm0.o: ops_cm0.s 38 | $(CC) $(CFLAGS) -c -o ops_cm0.o ops_cm0.s 39 | 40 | scalar_arm.o: scalar_arm.c curve9767.h inner.h sha3.h 41 | $(CC) $(CFLAGS) -c -o scalar_arm.o scalar_arm.c 42 | 43 | scalar_cm0.o: scalar_cm0.s 44 | $(CC) $(CFLAGS) -c -o scalar_cm0.o scalar_cm0.s 45 | 46 | sha3.o: sha3.c sha3.h 47 | $(CC) $(CFLAGS) -c -o sha3.o sha3.c 48 | 49 | sign.o: sign.c curve9767.h inner.h sha3.h 50 | $(CC) $(CFLAGS) -c -o sign.o sign.c 51 | 52 | timing.o: timing.c curve9767.h inner.h sha3.h 53 | $(CC) $(CFLAGS) -c -o timing.o timing.c 54 | -------------------------------------------------------------------------------- /bench-cm0/curve9767.c: -------------------------------------------------------------------------------- 1 | ../src/curve9767.c -------------------------------------------------------------------------------- /bench-cm0/curve9767.h: -------------------------------------------------------------------------------- 1 | ../src/curve9767.h -------------------------------------------------------------------------------- /bench-cm0/ecdh.c: -------------------------------------------------------------------------------- 1 | ../src/ecdh.c -------------------------------------------------------------------------------- /bench-cm0/hash.c: -------------------------------------------------------------------------------- 1 | ../src/hash.c -------------------------------------------------------------------------------- /bench-cm0/inner.h: -------------------------------------------------------------------------------- 1 | ../src/inner.h -------------------------------------------------------------------------------- /bench-cm0/keygen.c: -------------------------------------------------------------------------------- 1 | ../src/keygen.c -------------------------------------------------------------------------------- /bench-cm0/ops_arm.c: -------------------------------------------------------------------------------- 1 | ../src/ops_arm.c -------------------------------------------------------------------------------- /bench-cm0/ops_cm0.s: -------------------------------------------------------------------------------- 1 | ../src/ops_cm0.s -------------------------------------------------------------------------------- /bench-cm0/samd20e18.ld: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Linker script for running in internal FLASH on the SAMD20E18 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | 30 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 31 | OUTPUT_ARCH(arm) 32 | SEARCH_DIR(.) 33 | 34 | /* Memory Spaces Definitions */ 35 | MEMORY 36 | { 37 | rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 38 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 39 | } 40 | 41 | /* The stack size used by the application. NOTE: you need to adjust according to your application. */ 42 | STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000; 43 | 44 | /* Section Definitions */ 45 | SECTIONS 46 | { 47 | .text : 48 | { 49 | . = ALIGN(4); 50 | _sfixed = .; 51 | KEEP(*(.vectors .vectors.*)) 52 | *(.text .text.* .gnu.linkonce.t.*) 53 | *(.glue_7t) *(.glue_7) 54 | *(.rodata .rodata* .gnu.linkonce.r.*) 55 | *(.ARM.extab* .gnu.linkonce.armextab.*) 56 | 57 | /* Support C constructors, and C destructors in both user code 58 | and the C library. This also provides support for C++ code. */ 59 | . = ALIGN(4); 60 | KEEP(*(.init)) 61 | . = ALIGN(4); 62 | __preinit_array_start = .; 63 | KEEP (*(.preinit_array)) 64 | __preinit_array_end = .; 65 | 66 | . = ALIGN(4); 67 | __init_array_start = .; 68 | KEEP (*(SORT(.init_array.*))) 69 | KEEP (*(.init_array)) 70 | __init_array_end = .; 71 | 72 | . = ALIGN(4); 73 | KEEP (*crtbegin.o(.ctors)) 74 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 75 | KEEP (*(SORT(.ctors.*))) 76 | KEEP (*crtend.o(.ctors)) 77 | 78 | . = ALIGN(4); 79 | KEEP(*(.fini)) 80 | 81 | . = ALIGN(4); 82 | __fini_array_start = .; 83 | KEEP (*(.fini_array)) 84 | KEEP (*(SORT(.fini_array.*))) 85 | __fini_array_end = .; 86 | 87 | KEEP (*crtbegin.o(.dtors)) 88 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 89 | KEEP (*(SORT(.dtors.*))) 90 | KEEP (*crtend.o(.dtors)) 91 | 92 | . = ALIGN(4); 93 | _efixed = .; /* End of text section */ 94 | } > rom 95 | 96 | /* .ARM.exidx is sorted, so has to go in its own output section. */ 97 | PROVIDE_HIDDEN (__exidx_start = .); 98 | .ARM.exidx : 99 | { 100 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 101 | } > rom 102 | PROVIDE_HIDDEN (__exidx_end = .); 103 | 104 | . = ALIGN(4); 105 | _etext = .; 106 | 107 | .data : AT (_etext) 108 | { 109 | . = ALIGN(4); 110 | _sdata = .; 111 | *(.data .data.*); 112 | . = ALIGN(4); 113 | _edata = .; 114 | } > ram 115 | 116 | /* .bss section which is used for uninitialized data */ 117 | .bss (NOLOAD) : 118 | { 119 | . = ALIGN(4); 120 | _sbss = . ; 121 | _szero = .; 122 | *(.bss .bss.*) 123 | *(COMMON) 124 | . = ALIGN(4); 125 | _ebss = . ; 126 | _ezero = .; 127 | } > ram 128 | 129 | /* stack section */ 130 | .stack (NOLOAD): 131 | { 132 | . = ALIGN(8); 133 | _sstack = .; 134 | . = . + STACK_SIZE; 135 | . = ALIGN(8); 136 | _estack = .; 137 | } > ram 138 | 139 | . = ALIGN(4); 140 | _end = . ; 141 | } 142 | -------------------------------------------------------------------------------- /bench-cm0/scalar_arm.c: -------------------------------------------------------------------------------- 1 | ../src/scalar_arm.c -------------------------------------------------------------------------------- /bench-cm0/scalar_cm0.s: -------------------------------------------------------------------------------- 1 | ../src/scalar_cm0.s -------------------------------------------------------------------------------- /bench-cm0/sha3.c: -------------------------------------------------------------------------------- 1 | ../src/sha3.c -------------------------------------------------------------------------------- /bench-cm0/sha3.h: -------------------------------------------------------------------------------- 1 | ../src/sha3.h -------------------------------------------------------------------------------- /bench-cm0/sign.c: -------------------------------------------------------------------------------- 1 | ../src/sign.c -------------------------------------------------------------------------------- /bench-cm0/sysinc/component/pac.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Component description for PAC 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_PAC_COMPONENT_ 30 | #define _SAMD20_PAC_COMPONENT_ 31 | 32 | /* ========================================================================== */ 33 | /** SOFTWARE API DEFINITION FOR PAC */ 34 | /* ========================================================================== */ 35 | /** \addtogroup SAMD20_PAC Peripheral Access Controller */ 36 | /*@{*/ 37 | 38 | #define PAC_U2211 39 | #define REV_PAC 0x101 40 | 41 | /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ 42 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 | typedef union { 44 | struct { 45 | uint32_t :1; /*!< bit: 0 Reserved */ 46 | uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ 47 | } bit; /*!< Structure used for bit access */ 48 | uint32_t reg; /*!< Type used for register access */ 49 | } PAC_WPCLR_Type; 50 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 | 52 | #define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */ 53 | #define PAC_WPCLR_RESETVALUE _U(0x00000000); /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */ 54 | 55 | #define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */ 56 | #define PAC_WPCLR_WP_Msk (_U(0x7FFFFFFF) << PAC_WPCLR_WP_Pos) 57 | #define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)) 58 | #define PAC_WPCLR_MASK _U(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */ 59 | 60 | /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ 61 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 | typedef union { 63 | struct { 64 | uint32_t :1; /*!< bit: 0 Reserved */ 65 | uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ 66 | } bit; /*!< Structure used for bit access */ 67 | uint32_t reg; /*!< Type used for register access */ 68 | } PAC_WPSET_Type; 69 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 | 71 | #define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */ 72 | #define PAC_WPSET_RESETVALUE _U(0x00000000); /**< \brief (PAC_WPSET reset_value) Write Protection Set */ 73 | 74 | #define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */ 75 | #define PAC_WPSET_WP_Msk (_U(0x7FFFFFFF) << PAC_WPSET_WP_Pos) 76 | #define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)) 77 | #define PAC_WPSET_MASK _U(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */ 78 | 79 | /** \brief PAC hardware registers */ 80 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 81 | typedef struct { 82 | __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ 83 | __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ 84 | } Pac; 85 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 | 87 | /*@}*/ 88 | 89 | #endif /* _SAMD20_PAC_COMPONENT_ */ 90 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/ac.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for AC 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_AC_INSTANCE_ 30 | #define _SAMD20_AC_INSTANCE_ 31 | 32 | /* ========== Register definition for AC peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_AC_CTRLA (0x42004400) /**< \brief (AC) Control A */ 35 | #define REG_AC_CTRLB (0x42004401) /**< \brief (AC) Control B */ 36 | #define REG_AC_EVCTRL (0x42004402) /**< \brief (AC) Event Control */ 37 | #define REG_AC_INTENCLR (0x42004404) /**< \brief (AC) Interrupt Enable Clear */ 38 | #define REG_AC_INTENSET (0x42004405) /**< \brief (AC) Interrupt Enable Set */ 39 | #define REG_AC_INTFLAG (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */ 40 | #define REG_AC_STATUSA (0x42004408) /**< \brief (AC) Status A */ 41 | #define REG_AC_STATUSB (0x42004409) /**< \brief (AC) Status B */ 42 | #define REG_AC_STATUSC (0x4200440A) /**< \brief (AC) Status C */ 43 | #define REG_AC_WINCTRL (0x4200440C) /**< \brief (AC) Window Control */ 44 | #define REG_AC_COMPCTRL0 (0x42004410) /**< \brief (AC) Comparator Control 0 */ 45 | #define REG_AC_COMPCTRL1 (0x42004414) /**< \brief (AC) Comparator Control 1 */ 46 | #define REG_AC_SCALER0 (0x42004420) /**< \brief (AC) Scaler 0 */ 47 | #define REG_AC_SCALER1 (0x42004421) /**< \brief (AC) Scaler 1 */ 48 | #else 49 | #define REG_AC_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */ 50 | #define REG_AC_CTRLB (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */ 51 | #define REG_AC_EVCTRL (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */ 52 | #define REG_AC_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */ 53 | #define REG_AC_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */ 54 | #define REG_AC_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */ 55 | #define REG_AC_STATUSA (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */ 56 | #define REG_AC_STATUSB (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */ 57 | #define REG_AC_STATUSC (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */ 58 | #define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */ 59 | #define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */ 60 | #define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */ 61 | #define REG_AC_SCALER0 (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */ 62 | #define REG_AC_SCALER1 (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */ 63 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 | 65 | /* ========== Instance parameters for AC peripheral ========== */ 66 | #define AC_CMP_NUM 2 // Number of comparators 67 | #define AC_GCLK_ID_ANA 25 // Index of Generic Clock for analog 68 | #define AC_GCLK_ID_DIG 24 // Index of Generic Clock for digital 69 | #define AC_NUM_CMP 2 70 | #define AC_PAIRS 1 // Number of pairs of comparators 71 | 72 | #endif /* _SAMD20_AC_INSTANCE_ */ 73 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/adc.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for ADC 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_ADC_INSTANCE_ 30 | #define _SAMD20_ADC_INSTANCE_ 31 | 32 | /* ========== Register definition for ADC peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_ADC_CTRLA (0x42004000) /**< \brief (ADC) Control A */ 35 | #define REG_ADC_REFCTRL (0x42004001) /**< \brief (ADC) Reference Control */ 36 | #define REG_ADC_AVGCTRL (0x42004002) /**< \brief (ADC) Average Control */ 37 | #define REG_ADC_SAMPCTRL (0x42004003) /**< \brief (ADC) Sampling Time Control */ 38 | #define REG_ADC_CTRLB (0x42004004) /**< \brief (ADC) Control B */ 39 | #define REG_ADC_WINCTRL (0x42004008) /**< \brief (ADC) Window Monitor Control */ 40 | #define REG_ADC_SWTRIG (0x4200400C) /**< \brief (ADC) Software Trigger */ 41 | #define REG_ADC_INPUTCTRL (0x42004010) /**< \brief (ADC) Inputs Control */ 42 | #define REG_ADC_EVCTRL (0x42004014) /**< \brief (ADC) Event Control */ 43 | #define REG_ADC_INTENCLR (0x42004016) /**< \brief (ADC) Interrupt Enable Clear */ 44 | #define REG_ADC_INTENSET (0x42004017) /**< \brief (ADC) Interrupt Enable Set */ 45 | #define REG_ADC_INTFLAG (0x42004018) /**< \brief (ADC) Interrupt Flag Status and Clear */ 46 | #define REG_ADC_STATUS (0x42004019) /**< \brief (ADC) Status */ 47 | #define REG_ADC_RESULT (0x4200401A) /**< \brief (ADC) Result */ 48 | #define REG_ADC_WINLT (0x4200401C) /**< \brief (ADC) Window Monitor Lower Threshold */ 49 | #define REG_ADC_WINUT (0x42004020) /**< \brief (ADC) Window Monitor Upper Threshold */ 50 | #define REG_ADC_GAINCORR (0x42004024) /**< \brief (ADC) Gain Correction */ 51 | #define REG_ADC_OFFSETCORR (0x42004026) /**< \brief (ADC) Offset Correction */ 52 | #define REG_ADC_CALIB (0x42004028) /**< \brief (ADC) Calibration */ 53 | #define REG_ADC_DBGCTRL (0x4200402A) /**< \brief (ADC) Debug Control */ 54 | #else 55 | #define REG_ADC_CTRLA (*(RwReg8 *)0x42004000UL) /**< \brief (ADC) Control A */ 56 | #define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001UL) /**< \brief (ADC) Reference Control */ 57 | #define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002UL) /**< \brief (ADC) Average Control */ 58 | #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003UL) /**< \brief (ADC) Sampling Time Control */ 59 | #define REG_ADC_CTRLB (*(RwReg16*)0x42004004UL) /**< \brief (ADC) Control B */ 60 | #define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008UL) /**< \brief (ADC) Window Monitor Control */ 61 | #define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CUL) /**< \brief (ADC) Software Trigger */ 62 | #define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010UL) /**< \brief (ADC) Inputs Control */ 63 | #define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014UL) /**< \brief (ADC) Event Control */ 64 | #define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016UL) /**< \brief (ADC) Interrupt Enable Clear */ 65 | #define REG_ADC_INTENSET (*(RwReg8 *)0x42004017UL) /**< \brief (ADC) Interrupt Enable Set */ 66 | #define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018UL) /**< \brief (ADC) Interrupt Flag Status and Clear */ 67 | #define REG_ADC_STATUS (*(RoReg8 *)0x42004019UL) /**< \brief (ADC) Status */ 68 | #define REG_ADC_RESULT (*(RoReg16*)0x4200401AUL) /**< \brief (ADC) Result */ 69 | #define REG_ADC_WINLT (*(RwReg16*)0x4200401CUL) /**< \brief (ADC) Window Monitor Lower Threshold */ 70 | #define REG_ADC_WINUT (*(RwReg16*)0x42004020UL) /**< \brief (ADC) Window Monitor Upper Threshold */ 71 | #define REG_ADC_GAINCORR (*(RwReg16*)0x42004024UL) /**< \brief (ADC) Gain Correction */ 72 | #define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026UL) /**< \brief (ADC) Offset Correction */ 73 | #define REG_ADC_CALIB (*(RwReg16*)0x42004028UL) /**< \brief (ADC) Calibration */ 74 | #define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AUL) /**< \brief (ADC) Debug Control */ 75 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 | 77 | /* ========== Instance parameters for ADC peripheral ========== */ 78 | #define ADC_EXTCHANNEL_MSB 19 // Number of external channels 79 | #define ADC_GCLK_ID 23 // Index of Generic Clock 80 | #define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield 81 | #define ADC_RESULT_MSB 15 // Size of Result 82 | 83 | #endif /* _SAMD20_ADC_INSTANCE_ */ 84 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/dac.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for DAC 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_DAC_INSTANCE_ 30 | #define _SAMD20_DAC_INSTANCE_ 31 | 32 | /* ========== Register definition for DAC peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_DAC_CTRLA (0x42004800) /**< \brief (DAC) Control A */ 35 | #define REG_DAC_CTRLB (0x42004801) /**< \brief (DAC) Control B */ 36 | #define REG_DAC_EVCTRL (0x42004802) /**< \brief (DAC) Event Control */ 37 | #define REG_DAC_INTENCLR (0x42004804) /**< \brief (DAC) Interrupt Enable Clear */ 38 | #define REG_DAC_INTENSET (0x42004805) /**< \brief (DAC) Interrupt Enable Set */ 39 | #define REG_DAC_INTFLAG (0x42004806) /**< \brief (DAC) Interrupt Flag Status and Clear */ 40 | #define REG_DAC_STATUS (0x42004807) /**< \brief (DAC) Status */ 41 | #define REG_DAC_DATA (0x42004808) /**< \brief (DAC) Data */ 42 | #define REG_DAC_DATABUF (0x4200480C) /**< \brief (DAC) Data Buffer */ 43 | #else 44 | #define REG_DAC_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (DAC) Control A */ 45 | #define REG_DAC_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (DAC) Control B */ 46 | #define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (DAC) Event Control */ 47 | #define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (DAC) Interrupt Enable Clear */ 48 | #define REG_DAC_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (DAC) Interrupt Enable Set */ 49 | #define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (DAC) Interrupt Flag Status and Clear */ 50 | #define REG_DAC_STATUS (*(RoReg8 *)0x42004807UL) /**< \brief (DAC) Status */ 51 | #define REG_DAC_DATA (*(RwReg16*)0x42004808UL) /**< \brief (DAC) Data */ 52 | #define REG_DAC_DATABUF (*(RwReg16*)0x4200480CUL) /**< \brief (DAC) Data Buffer */ 53 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 | 55 | /* ========== Instance parameters for DAC peripheral ========== */ 56 | #define DAC_GCLK_ID 26 57 | 58 | #endif /* _SAMD20_DAC_INSTANCE_ */ 59 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/dsu.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for DSU 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_DSU_INSTANCE_ 30 | #define _SAMD20_DSU_INSTANCE_ 31 | 32 | /* ========== Register definition for DSU peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ 35 | #define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ 36 | #define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ 37 | #define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ 38 | #define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ 39 | #define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ 40 | #define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ 41 | #define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ 42 | #define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ 43 | #define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */ 44 | #define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */ 45 | #define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 46 | #define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 47 | #define REG_DSU_END (0x41003008) /**< \brief (DSU) Coresight ROM Table End */ 48 | #define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) Coresight ROM Table Memory Type */ 49 | #define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ 50 | #define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */ 51 | #define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */ 52 | #define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */ 53 | #define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ 54 | #define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ 55 | #define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ 56 | #define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ 57 | #define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ 58 | #define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ 59 | #define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ 60 | #define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ 61 | #else 62 | #define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ 63 | #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ 64 | #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ 65 | #define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ 66 | #define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ 67 | #define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ 68 | #define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ 69 | #define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ 70 | #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ 71 | #define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */ 72 | #define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */ 73 | #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 74 | #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 75 | #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table End */ 76 | #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table Memory Type */ 77 | #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ 78 | #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */ 79 | #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */ 80 | #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */ 81 | #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ 82 | #define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ 83 | #define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ 84 | #define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ 85 | #define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ 86 | #define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ 87 | #define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ 88 | #define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ 89 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 | 91 | /* ========== Instance parameters for DSU peripheral ========== */ 92 | #define DSU_CLK_HSB_ID 3 93 | 94 | #endif /* _SAMD20_DSU_INSTANCE_ */ 95 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/eic.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for EIC 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_EIC_INSTANCE_ 30 | #define _SAMD20_EIC_INSTANCE_ 31 | 32 | /* ========== Register definition for EIC peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_EIC_CTRL (0x40001800) /**< \brief (EIC) Control */ 35 | #define REG_EIC_STATUS (0x40001801) /**< \brief (EIC) Status */ 36 | #define REG_EIC_NMICTRL (0x40001802) /**< \brief (EIC) Non-Maskable Interrupt Control */ 37 | #define REG_EIC_NMIFLAG (0x40001803) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 38 | #define REG_EIC_EVCTRL (0x40001804) /**< \brief (EIC) Event Control */ 39 | #define REG_EIC_INTENCLR (0x40001808) /**< \brief (EIC) Interrupt Enable Clear */ 40 | #define REG_EIC_INTENSET (0x4000180C) /**< \brief (EIC) Interrupt Enable Set */ 41 | #define REG_EIC_INTFLAG (0x40001810) /**< \brief (EIC) Interrupt Flag Status and Clear */ 42 | #define REG_EIC_WAKEUP (0x40001814) /**< \brief (EIC) Wake-Up Enable */ 43 | #define REG_EIC_CONFIG0 (0x40001818) /**< \brief (EIC) Configuration 0 */ 44 | #define REG_EIC_CONFIG1 (0x4000181C) /**< \brief (EIC) Configuration 1 */ 45 | #else 46 | #define REG_EIC_CTRL (*(RwReg8 *)0x40001800UL) /**< \brief (EIC) Control */ 47 | #define REG_EIC_STATUS (*(RoReg8 *)0x40001801UL) /**< \brief (EIC) Status */ 48 | #define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802UL) /**< \brief (EIC) Non-Maskable Interrupt Control */ 49 | #define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 50 | #define REG_EIC_EVCTRL (*(RwReg *)0x40001804UL) /**< \brief (EIC) Event Control */ 51 | #define REG_EIC_INTENCLR (*(RwReg *)0x40001808UL) /**< \brief (EIC) Interrupt Enable Clear */ 52 | #define REG_EIC_INTENSET (*(RwReg *)0x4000180CUL) /**< \brief (EIC) Interrupt Enable Set */ 53 | #define REG_EIC_INTFLAG (*(RwReg *)0x40001810UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ 54 | #define REG_EIC_WAKEUP (*(RwReg *)0x40001814UL) /**< \brief (EIC) Wake-Up Enable */ 55 | #define REG_EIC_CONFIG0 (*(RwReg *)0x40001818UL) /**< \brief (EIC) Configuration 0 */ 56 | #define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CUL) /**< \brief (EIC) Configuration 1 */ 57 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 | 59 | /* ========== Instance parameters for EIC peripheral ========== */ 60 | #define EIC_CONFIG_NUM 2 // Number of CONFIG registers 61 | #define EIC_EXTINT_NUM 16 // Number of External Interrupts 62 | #define EIC_GCLK_ID 3 // Index of Generic Clock 63 | #define EIC_NUMBER_OF_CONFIG_REGS 2 // Number of CONFIG registers (obsolete) 64 | #define EIC_NUMBER_OF_INTERRUPTS 16 // Number of External Interrupts (obsolete) 65 | 66 | #endif /* _SAMD20_EIC_INSTANCE_ */ 67 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/evsys.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for EVSYS 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_EVSYS_INSTANCE_ 30 | #define _SAMD20_EVSYS_INSTANCE_ 31 | 32 | /* ========== Register definition for EVSYS peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_EVSYS_CTRL (0x42000400) /**< \brief (EVSYS) Control */ 35 | #define REG_EVSYS_CHANNEL (0x42000404) /**< \brief (EVSYS) Channel */ 36 | #define REG_EVSYS_USER (0x42000408) /**< \brief (EVSYS) User Multiplexer */ 37 | #define REG_EVSYS_CHSTATUS (0x4200040C) /**< \brief (EVSYS) Channel Status */ 38 | #define REG_EVSYS_INTENCLR (0x42000410) /**< \brief (EVSYS) Interrupt Enable Clear */ 39 | #define REG_EVSYS_INTENSET (0x42000414) /**< \brief (EVSYS) Interrupt Enable Set */ 40 | #define REG_EVSYS_INTFLAG (0x42000418) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ 41 | #else 42 | #define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400UL) /**< \brief (EVSYS) Control */ 43 | #define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404UL) /**< \brief (EVSYS) Channel */ 44 | #define REG_EVSYS_USER (*(RwReg16*)0x42000408UL) /**< \brief (EVSYS) User Multiplexer */ 45 | #define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CUL) /**< \brief (EVSYS) Channel Status */ 46 | #define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410UL) /**< \brief (EVSYS) Interrupt Enable Clear */ 47 | #define REG_EVSYS_INTENSET (*(RwReg *)0x42000414UL) /**< \brief (EVSYS) Interrupt Enable Set */ 48 | #define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ 49 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 | 51 | /* ========== Instance parameters for EVSYS peripheral ========== */ 52 | #define EVSYS_CHANNELS 8 // Number of Channels 53 | #define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel 54 | #define EVSYS_CHANNELS_MSB 7 // Number of Channels - 1 55 | #define EVSYS_EXTEVT_NUM // Number of External Event Generators 56 | #define EVSYS_EXT_EVT_MSB 0 // Number of External Event Generators - 1 57 | #define EVSYS_GCLK_ID_0 4 58 | #define EVSYS_GCLK_ID_1 5 59 | #define EVSYS_GCLK_ID_2 6 60 | #define EVSYS_GCLK_ID_3 7 61 | #define EVSYS_GCLK_ID_4 8 62 | #define EVSYS_GCLK_ID_5 9 63 | #define EVSYS_GCLK_ID_6 10 64 | #define EVSYS_GCLK_ID_7 11 65 | #define EVSYS_GCLK_ID_LSB 4 66 | #define EVSYS_GCLK_ID_MSB 11 67 | #define EVSYS_GCLK_ID_SIZE 8 68 | #define EVSYS_GENERATORS 59 // Total Number of Event Generators 69 | #define EVSYS_GENERATORS_BITS 6 // Number of bits to select Event Generator 70 | #define EVSYS_USERS 14 // Total Number of Event Users 71 | #define EVSYS_USERS_BITS 4 // Number of bits to select Event User 72 | 73 | // GENERATORS 74 | #define EVSYS_ID_GEN_RTC_CMP_0 1 75 | #define EVSYS_ID_GEN_RTC_CMP_1 2 76 | #define EVSYS_ID_GEN_RTC_OVF 3 77 | #define EVSYS_ID_GEN_RTC_PER_0 4 78 | #define EVSYS_ID_GEN_RTC_PER_1 5 79 | #define EVSYS_ID_GEN_RTC_PER_2 6 80 | #define EVSYS_ID_GEN_RTC_PER_3 7 81 | #define EVSYS_ID_GEN_RTC_PER_4 8 82 | #define EVSYS_ID_GEN_RTC_PER_5 9 83 | #define EVSYS_ID_GEN_RTC_PER_6 10 84 | #define EVSYS_ID_GEN_RTC_PER_7 11 85 | #define EVSYS_ID_GEN_EIC_EXTINT_0 12 86 | #define EVSYS_ID_GEN_EIC_EXTINT_1 13 87 | #define EVSYS_ID_GEN_EIC_EXTINT_2 14 88 | #define EVSYS_ID_GEN_EIC_EXTINT_3 15 89 | #define EVSYS_ID_GEN_EIC_EXTINT_4 16 90 | #define EVSYS_ID_GEN_EIC_EXTINT_5 17 91 | #define EVSYS_ID_GEN_EIC_EXTINT_6 18 92 | #define EVSYS_ID_GEN_EIC_EXTINT_7 19 93 | #define EVSYS_ID_GEN_EIC_EXTINT_8 20 94 | #define EVSYS_ID_GEN_EIC_EXTINT_9 21 95 | #define EVSYS_ID_GEN_EIC_EXTINT_10 22 96 | #define EVSYS_ID_GEN_EIC_EXTINT_11 23 97 | #define EVSYS_ID_GEN_EIC_EXTINT_12 24 98 | #define EVSYS_ID_GEN_EIC_EXTINT_13 25 99 | #define EVSYS_ID_GEN_EIC_EXTINT_14 26 100 | #define EVSYS_ID_GEN_EIC_EXTINT_15 27 101 | #define EVSYS_ID_GEN_TC0_OVF 28 102 | #define EVSYS_ID_GEN_TC0_MCX_0 29 103 | #define EVSYS_ID_GEN_TC0_MCX_1 30 104 | #define EVSYS_ID_GEN_TC1_OVF 31 105 | #define EVSYS_ID_GEN_TC1_MCX_0 32 106 | #define EVSYS_ID_GEN_TC1_MCX_1 33 107 | #define EVSYS_ID_GEN_TC2_OVF 34 108 | #define EVSYS_ID_GEN_TC2_MCX_0 35 109 | #define EVSYS_ID_GEN_TC2_MCX_1 36 110 | #define EVSYS_ID_GEN_TC3_OVF 37 111 | #define EVSYS_ID_GEN_TC3_MCX_0 38 112 | #define EVSYS_ID_GEN_TC3_MCX_1 39 113 | #define EVSYS_ID_GEN_TC4_OVF 40 114 | #define EVSYS_ID_GEN_TC4_MCX_0 41 115 | #define EVSYS_ID_GEN_TC4_MCX_1 42 116 | #define EVSYS_ID_GEN_TC5_OVF 43 117 | #define EVSYS_ID_GEN_TC5_MCX_0 44 118 | #define EVSYS_ID_GEN_TC5_MCX_1 45 119 | #define EVSYS_ID_GEN_TC6_OVF 46 120 | #define EVSYS_ID_GEN_TC6_MCX_0 47 121 | #define EVSYS_ID_GEN_TC6_MCX_1 48 122 | #define EVSYS_ID_GEN_TC7_OVF 49 123 | #define EVSYS_ID_GEN_TC7_MCX_0 50 124 | #define EVSYS_ID_GEN_TC7_MCX_1 51 125 | #define EVSYS_ID_GEN_ADC_RESRDY 52 126 | #define EVSYS_ID_GEN_ADC_WINMON 53 127 | #define EVSYS_ID_GEN_AC_COMP_0 54 128 | #define EVSYS_ID_GEN_AC_COMP_1 55 129 | #define EVSYS_ID_GEN_AC_WIN_0 56 130 | #define EVSYS_ID_GEN_DAC_EMPTY 57 131 | 132 | // USERS 133 | #define EVSYS_ID_USER_TC0_EVU 0 134 | #define EVSYS_ID_USER_TC1_EVU 1 135 | #define EVSYS_ID_USER_TC2_EVU 2 136 | #define EVSYS_ID_USER_TC3_EVU 3 137 | #define EVSYS_ID_USER_TC4_EVU 4 138 | #define EVSYS_ID_USER_TC5_EVU 5 139 | #define EVSYS_ID_USER_TC6_EVU 6 140 | #define EVSYS_ID_USER_TC7_EVU 7 141 | #define EVSYS_ID_USER_ADC_START 8 142 | #define EVSYS_ID_USER_ADC_SYNC 9 143 | #define EVSYS_ID_USER_AC_SOC_0 10 144 | #define EVSYS_ID_USER_AC_SOC_1 11 145 | #define EVSYS_ID_USER_DAC_START 12 146 | 147 | #endif /* _SAMD20_EVSYS_INSTANCE_ */ 148 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/gclk.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for GCLK 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_GCLK_INSTANCE_ 30 | #define _SAMD20_GCLK_INSTANCE_ 31 | 32 | /* ========== Register definition for GCLK peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */ 35 | #define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */ 36 | #define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */ 37 | #define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */ 38 | #define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */ 39 | #else 40 | #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */ 41 | #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */ 42 | #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */ 43 | #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */ 44 | #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */ 45 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 46 | 47 | /* ========== Instance parameters for GCLK peripheral ========== */ 48 | #define GCLK_GENDIV_BITS 16 49 | #define GCLK_GEN_NUM 8 // Number of Generic Clock Generators 50 | #define GCLK_GEN_NUM_MSB 7 // Number of Generic Clock Generators - 1 51 | #define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1 52 | #define GCLK_NUM 28 // Number of Generic Clock Users 53 | #define GCLK_SOURCE_DFLL48M 7 54 | #define GCLK_SOURCE_FDPLL 55 | #define GCLK_SOURCE_GCLKGEN1 2 56 | #define GCLK_SOURCE_GCLKIN 1 57 | #define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources 58 | #define GCLK_SOURCE_OSCULP32K 3 59 | #define GCLK_SOURCE_OSC8M 6 60 | #define GCLK_SOURCE_OSC32K 4 61 | #define GCLK_SOURCE_XOSC 0 62 | #define GCLK_SOURCE_XOSC32K 5 63 | 64 | #endif /* _SAMD20_GCLK_INSTANCE_ */ 65 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/nvmctrl.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for NVMCTRL 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_NVMCTRL_INSTANCE_ 30 | #define _SAMD20_NVMCTRL_INSTANCE_ 31 | 32 | /* ========== Register definition for NVMCTRL peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ 35 | #define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ 36 | #define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ 37 | #define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 38 | #define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */ 39 | #define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 40 | #define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */ 41 | #define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */ 42 | #define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */ 43 | #else 44 | #define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ 45 | #define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */ 46 | #define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ 47 | #define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 48 | #define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */ 49 | #define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 50 | #define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */ 51 | #define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */ 52 | #define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */ 53 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 | 55 | /* ========== Instance parameters for NVMCTRL peripheral ========== */ 56 | #define NVMCTRL_AUX0_ADDRESS 0x00804000 57 | #define NVMCTRL_AUX1_ADDRESS 0x00806000 58 | #define NVMCTRL_AUX2_ADDRESS 0x00808000 59 | #define NVMCTRL_AUX3_ADDRESS 0x0080A000 60 | #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register 61 | #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF 62 | #define NVMCTRL_FLASH_SIZE 262144 63 | #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 64 | #define NVMCTRL_PAGE_HW 32 65 | #define NVMCTRL_PAGE_SIZE 64 66 | #define NVMCTRL_PAGE_W 16 67 | #define NVMCTRL_PMSB 3 68 | #define NVMCTRL_PSZ_BITS 6 69 | #define NVMCTRL_ROW_PAGES 4 70 | #define NVMCTRL_ROW_SIZE 256 71 | #define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 72 | #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 73 | #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 74 | #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF 75 | 76 | #endif /* _SAMD20_NVMCTRL_INSTANCE_ */ 77 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/pac0.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PAC0 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_PAC0_INSTANCE_ 30 | #define _SAMD20_PAC0_INSTANCE_ 31 | 32 | /* ========== Register definition for PAC0 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_PAC0_WPCLR (0x40000000) /**< \brief (PAC0) Write Protection Clear */ 35 | #define REG_PAC0_WPSET (0x40000004) /**< \brief (PAC0) Write Protection Set */ 36 | #else 37 | #define REG_PAC0_WPCLR (*(RwReg *)0x40000000UL) /**< \brief (PAC0) Write Protection Clear */ 38 | #define REG_PAC0_WPSET (*(RwReg *)0x40000004UL) /**< \brief (PAC0) Write Protection Set */ 39 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 40 | 41 | /* ========== Instance parameters for PAC0 peripheral ========== */ 42 | #define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset 43 | 44 | #endif /* _SAMD20_PAC0_INSTANCE_ */ 45 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/pac1.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PAC1 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_PAC1_INSTANCE_ 30 | #define _SAMD20_PAC1_INSTANCE_ 31 | 32 | /* ========== Register definition for PAC1 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_PAC1_WPCLR (0x41000000) /**< \brief (PAC1) Write Protection Clear */ 35 | #define REG_PAC1_WPSET (0x41000004) /**< \brief (PAC1) Write Protection Set */ 36 | #else 37 | #define REG_PAC1_WPCLR (*(RwReg *)0x41000000UL) /**< \brief (PAC1) Write Protection Clear */ 38 | #define REG_PAC1_WPSET (*(RwReg *)0x41000004UL) /**< \brief (PAC1) Write Protection Set */ 39 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 40 | 41 | /* ========== Instance parameters for PAC1 peripheral ========== */ 42 | #define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset 43 | 44 | #endif /* _SAMD20_PAC1_INSTANCE_ */ 45 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/pac2.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PAC2 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_PAC2_INSTANCE_ 30 | #define _SAMD20_PAC2_INSTANCE_ 31 | 32 | /* ========== Register definition for PAC2 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_PAC2_WPCLR (0x42000000) /**< \brief (PAC2) Write Protection Clear */ 35 | #define REG_PAC2_WPSET (0x42000004) /**< \brief (PAC2) Write Protection Set */ 36 | #else 37 | #define REG_PAC2_WPCLR (*(RwReg *)0x42000000UL) /**< \brief (PAC2) Write Protection Clear */ 38 | #define REG_PAC2_WPSET (*(RwReg *)0x42000004UL) /**< \brief (PAC2) Write Protection Set */ 39 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 40 | 41 | /* ========== Instance parameters for PAC2 peripheral ========== */ 42 | #define PAC2_WPROT_DEFAULT_VAL 0x00100000 // PAC protection mask at reset 43 | 44 | #endif /* _SAMD20_PAC2_INSTANCE_ */ 45 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/pm.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PM 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_PM_INSTANCE_ 30 | #define _SAMD20_PM_INSTANCE_ 31 | 32 | /* ========== Register definition for PM peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_PM_CTRL (0x40000400) /**< \brief (PM) Control */ 35 | #define REG_PM_SLEEP (0x40000401) /**< \brief (PM) Sleep Mode */ 36 | #define REG_PM_CPUSEL (0x40000408) /**< \brief (PM) CPU Clock Select */ 37 | #define REG_PM_APBASEL (0x40000409) /**< \brief (PM) APBA Clock Select */ 38 | #define REG_PM_APBBSEL (0x4000040A) /**< \brief (PM) APBB Clock Select */ 39 | #define REG_PM_APBCSEL (0x4000040B) /**< \brief (PM) APBC Clock Select */ 40 | #define REG_PM_AHBMASK (0x40000414) /**< \brief (PM) AHB Mask */ 41 | #define REG_PM_APBAMASK (0x40000418) /**< \brief (PM) APBA Mask */ 42 | #define REG_PM_APBBMASK (0x4000041C) /**< \brief (PM) APBB Mask */ 43 | #define REG_PM_APBCMASK (0x40000420) /**< \brief (PM) APBC Mask */ 44 | #define REG_PM_INTENCLR (0x40000434) /**< \brief (PM) Interrupt Enable Clear */ 45 | #define REG_PM_INTENSET (0x40000435) /**< \brief (PM) Interrupt Enable Set */ 46 | #define REG_PM_INTFLAG (0x40000436) /**< \brief (PM) Interrupt Flag Status and Clear */ 47 | #define REG_PM_RCAUSE (0x40000438) /**< \brief (PM) Reset Cause */ 48 | #else 49 | #define REG_PM_CTRL (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control */ 50 | #define REG_PM_SLEEP (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Mode */ 51 | #define REG_PM_CPUSEL (*(RwReg8 *)0x40000408UL) /**< \brief (PM) CPU Clock Select */ 52 | #define REG_PM_APBASEL (*(RwReg8 *)0x40000409UL) /**< \brief (PM) APBA Clock Select */ 53 | #define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) APBB Clock Select */ 54 | #define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BUL) /**< \brief (PM) APBC Clock Select */ 55 | #define REG_PM_AHBMASK (*(RwReg *)0x40000414UL) /**< \brief (PM) AHB Mask */ 56 | #define REG_PM_APBAMASK (*(RwReg *)0x40000418UL) /**< \brief (PM) APBA Mask */ 57 | #define REG_PM_APBBMASK (*(RwReg *)0x4000041CUL) /**< \brief (PM) APBB Mask */ 58 | #define REG_PM_APBCMASK (*(RwReg *)0x40000420UL) /**< \brief (PM) APBC Mask */ 59 | #define REG_PM_INTENCLR (*(RwReg8 *)0x40000434UL) /**< \brief (PM) Interrupt Enable Clear */ 60 | #define REG_PM_INTENSET (*(RwReg8 *)0x40000435UL) /**< \brief (PM) Interrupt Enable Set */ 61 | #define REG_PM_INTFLAG (*(RwReg8 *)0x40000436UL) /**< \brief (PM) Interrupt Flag Status and Clear */ 62 | #define REG_PM_RCAUSE (*(RoReg8 *)0x40000438UL) /**< \brief (PM) Reset Cause */ 63 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 | 65 | /* ========== Instance parameters for PM peripheral ========== */ 66 | #define PM_CTRL_MCSEL_DFLL48M 3 67 | #define PM_CTRL_MCSEL_GCLK 0 68 | #define PM_CTRL_MCSEL_OSC8M 1 69 | #define PM_CTRL_MCSEL_XOSC 2 70 | #define PM_PM_CLK_APB_NUM 2 71 | #define PM_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset 72 | 73 | #endif /* _SAMD20_PM_INSTANCE_ */ 74 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/port.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PORT 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_PORT_INSTANCE_ 30 | #define _SAMD20_PORT_INSTANCE_ 31 | 32 | /* ========== Register definition for PORT peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_PORT_DIR0 (0x41004400) /**< \brief (PORT) Data Direction 0 */ 35 | #define REG_PORT_DIRCLR0 (0x41004404) /**< \brief (PORT) Data Direction Clear 0 */ 36 | #define REG_PORT_DIRSET0 (0x41004408) /**< \brief (PORT) Data Direction Set 0 */ 37 | #define REG_PORT_DIRTGL0 (0x4100440C) /**< \brief (PORT) Data Direction Toggle 0 */ 38 | #define REG_PORT_OUT0 (0x41004410) /**< \brief (PORT) Data Output Value 0 */ 39 | #define REG_PORT_OUTCLR0 (0x41004414) /**< \brief (PORT) Data Output Value Clear 0 */ 40 | #define REG_PORT_OUTSET0 (0x41004418) /**< \brief (PORT) Data Output Value Set 0 */ 41 | #define REG_PORT_OUTTGL0 (0x4100441C) /**< \brief (PORT) Data Output Value Toggle 0 */ 42 | #define REG_PORT_IN0 (0x41004420) /**< \brief (PORT) Data Input Value 0 */ 43 | #define REG_PORT_CTRL0 (0x41004424) /**< \brief (PORT) Control 0 */ 44 | #define REG_PORT_WRCONFIG0 (0x41004428) /**< \brief (PORT) Write Configuration 0 */ 45 | #define REG_PORT_PMUX0 (0x41004430) /**< \brief (PORT) Peripheral Multiplexing 0 */ 46 | #define REG_PORT_PINCFG0 (0x41004440) /**< \brief (PORT) Pin Configuration 0 */ 47 | #define REG_PORT_DIR1 (0x41004480) /**< \brief (PORT) Data Direction 1 */ 48 | #define REG_PORT_DIRCLR1 (0x41004484) /**< \brief (PORT) Data Direction Clear 1 */ 49 | #define REG_PORT_DIRSET1 (0x41004488) /**< \brief (PORT) Data Direction Set 1 */ 50 | #define REG_PORT_DIRTGL1 (0x4100448C) /**< \brief (PORT) Data Direction Toggle 1 */ 51 | #define REG_PORT_OUT1 (0x41004490) /**< \brief (PORT) Data Output Value 1 */ 52 | #define REG_PORT_OUTCLR1 (0x41004494) /**< \brief (PORT) Data Output Value Clear 1 */ 53 | #define REG_PORT_OUTSET1 (0x41004498) /**< \brief (PORT) Data Output Value Set 1 */ 54 | #define REG_PORT_OUTTGL1 (0x4100449C) /**< \brief (PORT) Data Output Value Toggle 1 */ 55 | #define REG_PORT_IN1 (0x410044A0) /**< \brief (PORT) Data Input Value 1 */ 56 | #define REG_PORT_CTRL1 (0x410044A4) /**< \brief (PORT) Control 1 */ 57 | #define REG_PORT_WRCONFIG1 (0x410044A8) /**< \brief (PORT) Write Configuration 1 */ 58 | #define REG_PORT_PMUX1 (0x410044B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ 59 | #define REG_PORT_PINCFG1 (0x410044C0) /**< \brief (PORT) Pin Configuration 1 */ 60 | #else 61 | #define REG_PORT_DIR0 (*(RwReg *)0x41004400UL) /**< \brief (PORT) Data Direction 0 */ 62 | #define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404UL) /**< \brief (PORT) Data Direction Clear 0 */ 63 | #define REG_PORT_DIRSET0 (*(RwReg *)0x41004408UL) /**< \brief (PORT) Data Direction Set 0 */ 64 | #define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CUL) /**< \brief (PORT) Data Direction Toggle 0 */ 65 | #define REG_PORT_OUT0 (*(RwReg *)0x41004410UL) /**< \brief (PORT) Data Output Value 0 */ 66 | #define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414UL) /**< \brief (PORT) Data Output Value Clear 0 */ 67 | #define REG_PORT_OUTSET0 (*(RwReg *)0x41004418UL) /**< \brief (PORT) Data Output Value Set 0 */ 68 | #define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ 69 | #define REG_PORT_IN0 (*(RoReg *)0x41004420UL) /**< \brief (PORT) Data Input Value 0 */ 70 | #define REG_PORT_CTRL0 (*(RwReg *)0x41004424UL) /**< \brief (PORT) Control 0 */ 71 | #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428UL) /**< \brief (PORT) Write Configuration 0 */ 72 | #define REG_PORT_PMUX0 (*(RwReg *)0x41004430UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ 73 | #define REG_PORT_PINCFG0 (*(RwReg *)0x41004440UL) /**< \brief (PORT) Pin Configuration 0 */ 74 | #define REG_PORT_DIR1 (*(RwReg *)0x41004480UL) /**< \brief (PORT) Data Direction 1 */ 75 | #define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484UL) /**< \brief (PORT) Data Direction Clear 1 */ 76 | #define REG_PORT_DIRSET1 (*(RwReg *)0x41004488UL) /**< \brief (PORT) Data Direction Set 1 */ 77 | #define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CUL) /**< \brief (PORT) Data Direction Toggle 1 */ 78 | #define REG_PORT_OUT1 (*(RwReg *)0x41004490UL) /**< \brief (PORT) Data Output Value 1 */ 79 | #define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494UL) /**< \brief (PORT) Data Output Value Clear 1 */ 80 | #define REG_PORT_OUTSET1 (*(RwReg *)0x41004498UL) /**< \brief (PORT) Data Output Value Set 1 */ 81 | #define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ 82 | #define REG_PORT_IN1 (*(RoReg *)0x410044A0UL) /**< \brief (PORT) Data Input Value 1 */ 83 | #define REG_PORT_CTRL1 (*(RwReg *)0x410044A4UL) /**< \brief (PORT) Control 1 */ 84 | #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8UL) /**< \brief (PORT) Write Configuration 1 */ 85 | #define REG_PORT_PMUX1 (*(RwReg *)0x410044B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ 86 | #define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0UL) /**< \brief (PORT) Pin Configuration 1 */ 87 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 | 89 | /* ========== Instance parameters for PORT peripheral ========== */ 90 | #define PORT_BITS 64 // Number of PORT pins 91 | #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for DIR of all pins 92 | #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins 93 | #define PORT_DRVSTR 1 // DRVSTR supported 94 | #define PORT_DRVSTR_DEFAULT_VAL { 0xDBFFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins 95 | #define PORT_DRVSTR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins 96 | #define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000 } 97 | #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for INEN of all pins 98 | #define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins 99 | #define PORT_ODRAIN 0 // ODRAIN supported 100 | #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins 101 | #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins 102 | #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for OUT of all pins 103 | #define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins 104 | #define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins 105 | #define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins 106 | #define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins 107 | #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins 108 | #define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins 109 | #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins 110 | #define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins 111 | #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins 112 | #define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins 113 | #define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins 114 | #define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins 115 | #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins 116 | #define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins 117 | #define PORT_SLEWLIM 0 // SLEWLIM supported 118 | #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins 119 | #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins 120 | 121 | #endif /* _SAMD20_PORT_INSTANCE_ */ 122 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/rtc.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for RTC 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_RTC_INSTANCE_ 30 | #define _SAMD20_RTC_INSTANCE_ 31 | 32 | /* ========== Register definition for RTC peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_RTC_READREQ (0x40001402) /**< \brief (RTC) Read Request */ 35 | #define REG_RTC_STATUS (0x4000140A) /**< \brief (RTC) Status */ 36 | #define REG_RTC_DBGCTRL (0x4000140B) /**< \brief (RTC) Debug Control */ 37 | #define REG_RTC_FREQCORR (0x4000140C) /**< \brief (RTC) Frequency Correction */ 38 | #define REG_RTC_MODE0_CTRL (0x40001400) /**< \brief (RTC) MODE0 Control */ 39 | #define REG_RTC_MODE0_EVCTRL (0x40001404) /**< \brief (RTC) MODE0 Event Control */ 40 | #define REG_RTC_MODE0_INTENCLR (0x40001406) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ 41 | #define REG_RTC_MODE0_INTENSET (0x40001407) /**< \brief (RTC) MODE0 Interrupt Enable Set */ 42 | #define REG_RTC_MODE0_INTFLAG (0x40001408) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ 43 | #define REG_RTC_MODE0_COUNT (0x40001410) /**< \brief (RTC) MODE0 Counter Value */ 44 | #define REG_RTC_MODE0_COMP0 (0x40001418) /**< \brief (RTC) MODE0 Compare 0 Value */ 45 | #define REG_RTC_MODE1_CTRL (0x40001400) /**< \brief (RTC) MODE1 Control */ 46 | #define REG_RTC_MODE1_EVCTRL (0x40001404) /**< \brief (RTC) MODE1 Event Control */ 47 | #define REG_RTC_MODE1_INTENCLR (0x40001406) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ 48 | #define REG_RTC_MODE1_INTENSET (0x40001407) /**< \brief (RTC) MODE1 Interrupt Enable Set */ 49 | #define REG_RTC_MODE1_INTFLAG (0x40001408) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ 50 | #define REG_RTC_MODE1_COUNT (0x40001410) /**< \brief (RTC) MODE1 Counter Value */ 51 | #define REG_RTC_MODE1_PER (0x40001414) /**< \brief (RTC) MODE1 Counter Period */ 52 | #define REG_RTC_MODE1_COMP0 (0x40001418) /**< \brief (RTC) MODE1 Compare 0 Value */ 53 | #define REG_RTC_MODE1_COMP1 (0x4000141A) /**< \brief (RTC) MODE1 Compare 1 Value */ 54 | #define REG_RTC_MODE2_CTRL (0x40001400) /**< \brief (RTC) MODE2 Control */ 55 | #define REG_RTC_MODE2_EVCTRL (0x40001404) /**< \brief (RTC) MODE2 Event Control */ 56 | #define REG_RTC_MODE2_INTENCLR (0x40001406) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ 57 | #define REG_RTC_MODE2_INTENSET (0x40001407) /**< \brief (RTC) MODE2 Interrupt Enable Set */ 58 | #define REG_RTC_MODE2_INTFLAG (0x40001408) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ 59 | #define REG_RTC_MODE2_CLOCK (0x40001410) /**< \brief (RTC) MODE2 Clock Value */ 60 | #define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ 61 | #define REG_RTC_MODE2_ALARM_MASK0 (0x4000141C) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ 62 | #else 63 | #define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */ 64 | #define REG_RTC_STATUS (*(RwReg8 *)0x4000140AUL) /**< \brief (RTC) Status */ 65 | #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BUL) /**< \brief (RTC) Debug Control */ 66 | #define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CUL) /**< \brief (RTC) Frequency Correction */ 67 | #define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */ 68 | #define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control */ 69 | #define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ 70 | #define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ 71 | #define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ 72 | #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE0 Counter Value */ 73 | #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE0 Compare 0 Value */ 74 | #define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */ 75 | #define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control */ 76 | #define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ 77 | #define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ 78 | #define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ 79 | #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value */ 80 | #define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period */ 81 | #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Value */ 82 | #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Value */ 83 | #define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */ 84 | #define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE2 Event Control */ 85 | #define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ 86 | #define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ 87 | #define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ 88 | #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE2 Clock Value */ 89 | #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ 90 | #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CUL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ 91 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 92 | 93 | /* ========== Instance parameters for RTC peripheral ========== */ 94 | #define RTC_ALARM_NUM 1 // Number of Alarms 95 | #define RTC_COMP16_NUM 2 // Number of 16-bit Comparators 96 | #define RTC_COMP32_NUM 1 // Number of 32-bit Comparators 97 | #define RTC_GCLK_ID 2 // Index of Generic Clock 98 | #define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete) 99 | #define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete) 100 | #define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete) 101 | 102 | #endif /* _SAMD20_RTC_INSTANCE_ */ 103 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sercom0.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SERCOM0 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SERCOM0_INSTANCE_ 30 | #define _SAMD20_SERCOM0_INSTANCE_ 31 | 32 | /* ========== Register definition for SERCOM0 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SERCOM0_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CM Control A */ 35 | #define REG_SERCOM0_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CM Control B */ 36 | #define REG_SERCOM0_I2CM_DBGCTRL (0x42000808) /**< \brief (SERCOM0) I2CM Debug Control */ 37 | #define REG_SERCOM0_I2CM_BAUD (0x4200080A) /**< \brief (SERCOM0) I2CM Baud Rate */ 38 | #define REG_SERCOM0_I2CM_INTENCLR (0x4200080C) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ 39 | #define REG_SERCOM0_I2CM_INTENSET (0x4200080D) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ 40 | #define REG_SERCOM0_I2CM_INTFLAG (0x4200080E) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ 41 | #define REG_SERCOM0_I2CM_STATUS (0x42000810) /**< \brief (SERCOM0) I2CM Status */ 42 | #define REG_SERCOM0_I2CM_ADDR (0x42000814) /**< \brief (SERCOM0) I2CM Address */ 43 | #define REG_SERCOM0_I2CM_DATA (0x42000818) /**< \brief (SERCOM0) I2CM Data */ 44 | #define REG_SERCOM0_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CS Control A */ 45 | #define REG_SERCOM0_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CS Control B */ 46 | #define REG_SERCOM0_I2CS_INTENCLR (0x4200080C) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ 47 | #define REG_SERCOM0_I2CS_INTENSET (0x4200080D) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ 48 | #define REG_SERCOM0_I2CS_INTFLAG (0x4200080E) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ 49 | #define REG_SERCOM0_I2CS_STATUS (0x42000810) /**< \brief (SERCOM0) I2CS Status */ 50 | #define REG_SERCOM0_I2CS_ADDR (0x42000814) /**< \brief (SERCOM0) I2CS Address */ 51 | #define REG_SERCOM0_I2CS_DATA (0x42000818) /**< \brief (SERCOM0) I2CS Data */ 52 | #define REG_SERCOM0_SPI_CTRLA (0x42000800) /**< \brief (SERCOM0) SPI Control A */ 53 | #define REG_SERCOM0_SPI_CTRLB (0x42000804) /**< \brief (SERCOM0) SPI Control B */ 54 | #define REG_SERCOM0_SPI_DBGCTRL (0x42000808) /**< \brief (SERCOM0) SPI Debug Control */ 55 | #define REG_SERCOM0_SPI_BAUD (0x4200080A) /**< \brief (SERCOM0) SPI Baud Rate */ 56 | #define REG_SERCOM0_SPI_INTENCLR (0x4200080C) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ 57 | #define REG_SERCOM0_SPI_INTENSET (0x4200080D) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ 58 | #define REG_SERCOM0_SPI_INTFLAG (0x4200080E) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ 59 | #define REG_SERCOM0_SPI_STATUS (0x42000810) /**< \brief (SERCOM0) SPI Status */ 60 | #define REG_SERCOM0_SPI_ADDR (0x42000814) /**< \brief (SERCOM0) SPI Address */ 61 | #define REG_SERCOM0_SPI_DATA (0x42000818) /**< \brief (SERCOM0) SPI Data */ 62 | #define REG_SERCOM0_USART_CTRLA (0x42000800) /**< \brief (SERCOM0) USART Control A */ 63 | #define REG_SERCOM0_USART_CTRLB (0x42000804) /**< \brief (SERCOM0) USART Control B */ 64 | #define REG_SERCOM0_USART_DBGCTRL (0x42000808) /**< \brief (SERCOM0) USART Debug Control */ 65 | #define REG_SERCOM0_USART_BAUD (0x4200080A) /**< \brief (SERCOM0) USART Baud */ 66 | #define REG_SERCOM0_USART_INTENCLR (0x4200080C) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ 67 | #define REG_SERCOM0_USART_INTENSET (0x4200080D) /**< \brief (SERCOM0) USART Interrupt Enable Set */ 68 | #define REG_SERCOM0_USART_INTFLAG (0x4200080E) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ 69 | #define REG_SERCOM0_USART_STATUS (0x42000810) /**< \brief (SERCOM0) USART Status */ 70 | #define REG_SERCOM0_USART_DATA (0x42000818) /**< \brief (SERCOM0) USART Data */ 71 | #else 72 | #define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CM Control A */ 73 | #define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CM Control B */ 74 | #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) I2CM Debug Control */ 75 | #define REG_SERCOM0_I2CM_BAUD (*(RwReg16*)0x4200080AUL) /**< \brief (SERCOM0) I2CM Baud Rate */ 76 | #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ 77 | #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ 78 | #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ 79 | #define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) I2CM Status */ 80 | #define REG_SERCOM0_I2CM_ADDR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Address */ 81 | #define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Data */ 82 | #define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CS Control A */ 83 | #define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CS Control B */ 84 | #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ 85 | #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ 86 | #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ 87 | #define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) I2CS Status */ 88 | #define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000814UL) /**< \brief (SERCOM0) I2CS Address */ 89 | #define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Data */ 90 | #define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) SPI Control A */ 91 | #define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) SPI Control B */ 92 | #define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) SPI Debug Control */ 93 | #define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080AUL) /**< \brief (SERCOM0) SPI Baud Rate */ 94 | #define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ 95 | #define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ 96 | #define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ 97 | #define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) SPI Status */ 98 | #define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000814UL) /**< \brief (SERCOM0) SPI Address */ 99 | #define REG_SERCOM0_SPI_DATA (*(RwReg16*)0x42000818UL) /**< \brief (SERCOM0) SPI Data */ 100 | #define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) USART Control A */ 101 | #define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) USART Control B */ 102 | #define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000808UL) /**< \brief (SERCOM0) USART Debug Control */ 103 | #define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080AUL) /**< \brief (SERCOM0) USART Baud */ 104 | #define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ 105 | #define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x4200080DUL) /**< \brief (SERCOM0) USART Interrupt Enable Set */ 106 | #define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ 107 | #define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x42000810UL) /**< \brief (SERCOM0) USART Status */ 108 | #define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000818UL) /**< \brief (SERCOM0) USART Data */ 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 | 111 | /* ========== Instance parameters for SERCOM0 peripheral ========== */ 112 | #define SERCOM0_GCLK_ID_CORE 13 113 | #define SERCOM0_GCLK_ID_SLOW 12 114 | #define SERCOM0_INT_MSB 3 115 | #define SERCOM0_PMSB 3 116 | 117 | #endif /* _SAMD20_SERCOM0_INSTANCE_ */ 118 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sercom1.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SERCOM1 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SERCOM1_INSTANCE_ 30 | #define _SAMD20_SERCOM1_INSTANCE_ 31 | 32 | /* ========== Register definition for SERCOM1 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SERCOM1_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CM Control A */ 35 | #define REG_SERCOM1_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CM Control B */ 36 | #define REG_SERCOM1_I2CM_DBGCTRL (0x42000C08) /**< \brief (SERCOM1) I2CM Debug Control */ 37 | #define REG_SERCOM1_I2CM_BAUD (0x42000C0A) /**< \brief (SERCOM1) I2CM Baud Rate */ 38 | #define REG_SERCOM1_I2CM_INTENCLR (0x42000C0C) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ 39 | #define REG_SERCOM1_I2CM_INTENSET (0x42000C0D) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ 40 | #define REG_SERCOM1_I2CM_INTFLAG (0x42000C0E) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ 41 | #define REG_SERCOM1_I2CM_STATUS (0x42000C10) /**< \brief (SERCOM1) I2CM Status */ 42 | #define REG_SERCOM1_I2CM_ADDR (0x42000C14) /**< \brief (SERCOM1) I2CM Address */ 43 | #define REG_SERCOM1_I2CM_DATA (0x42000C18) /**< \brief (SERCOM1) I2CM Data */ 44 | #define REG_SERCOM1_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CS Control A */ 45 | #define REG_SERCOM1_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CS Control B */ 46 | #define REG_SERCOM1_I2CS_INTENCLR (0x42000C0C) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ 47 | #define REG_SERCOM1_I2CS_INTENSET (0x42000C0D) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ 48 | #define REG_SERCOM1_I2CS_INTFLAG (0x42000C0E) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ 49 | #define REG_SERCOM1_I2CS_STATUS (0x42000C10) /**< \brief (SERCOM1) I2CS Status */ 50 | #define REG_SERCOM1_I2CS_ADDR (0x42000C14) /**< \brief (SERCOM1) I2CS Address */ 51 | #define REG_SERCOM1_I2CS_DATA (0x42000C18) /**< \brief (SERCOM1) I2CS Data */ 52 | #define REG_SERCOM1_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM1) SPI Control A */ 53 | #define REG_SERCOM1_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM1) SPI Control B */ 54 | #define REG_SERCOM1_SPI_DBGCTRL (0x42000C08) /**< \brief (SERCOM1) SPI Debug Control */ 55 | #define REG_SERCOM1_SPI_BAUD (0x42000C0A) /**< \brief (SERCOM1) SPI Baud Rate */ 56 | #define REG_SERCOM1_SPI_INTENCLR (0x42000C0C) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ 57 | #define REG_SERCOM1_SPI_INTENSET (0x42000C0D) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ 58 | #define REG_SERCOM1_SPI_INTFLAG (0x42000C0E) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ 59 | #define REG_SERCOM1_SPI_STATUS (0x42000C10) /**< \brief (SERCOM1) SPI Status */ 60 | #define REG_SERCOM1_SPI_ADDR (0x42000C14) /**< \brief (SERCOM1) SPI Address */ 61 | #define REG_SERCOM1_SPI_DATA (0x42000C18) /**< \brief (SERCOM1) SPI Data */ 62 | #define REG_SERCOM1_USART_CTRLA (0x42000C00) /**< \brief (SERCOM1) USART Control A */ 63 | #define REG_SERCOM1_USART_CTRLB (0x42000C04) /**< \brief (SERCOM1) USART Control B */ 64 | #define REG_SERCOM1_USART_DBGCTRL (0x42000C08) /**< \brief (SERCOM1) USART Debug Control */ 65 | #define REG_SERCOM1_USART_BAUD (0x42000C0A) /**< \brief (SERCOM1) USART Baud */ 66 | #define REG_SERCOM1_USART_INTENCLR (0x42000C0C) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ 67 | #define REG_SERCOM1_USART_INTENSET (0x42000C0D) /**< \brief (SERCOM1) USART Interrupt Enable Set */ 68 | #define REG_SERCOM1_USART_INTFLAG (0x42000C0E) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ 69 | #define REG_SERCOM1_USART_STATUS (0x42000C10) /**< \brief (SERCOM1) USART Status */ 70 | #define REG_SERCOM1_USART_DATA (0x42000C18) /**< \brief (SERCOM1) USART Data */ 71 | #else 72 | #define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CM Control A */ 73 | #define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CM Control B */ 74 | #define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C08UL) /**< \brief (SERCOM1) I2CM Debug Control */ 75 | #define REG_SERCOM1_I2CM_BAUD (*(RwReg16*)0x42000C0AUL) /**< \brief (SERCOM1) I2CM Baud Rate */ 76 | #define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ 77 | #define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C0DUL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ 78 | #define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ 79 | #define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C10UL) /**< \brief (SERCOM1) I2CM Status */ 80 | #define REG_SERCOM1_I2CM_ADDR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CM Address */ 81 | #define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CM Data */ 82 | #define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CS Control A */ 83 | #define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CS Control B */ 84 | #define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ 85 | #define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C0DUL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ 86 | #define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ 87 | #define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C10UL) /**< \brief (SERCOM1) I2CS Status */ 88 | #define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C14UL) /**< \brief (SERCOM1) I2CS Address */ 89 | #define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CS Data */ 90 | #define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) SPI Control A */ 91 | #define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) SPI Control B */ 92 | #define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C08UL) /**< \brief (SERCOM1) SPI Debug Control */ 93 | #define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0AUL) /**< \brief (SERCOM1) SPI Baud Rate */ 94 | #define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ 95 | #define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C0DUL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ 96 | #define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ 97 | #define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C10UL) /**< \brief (SERCOM1) SPI Status */ 98 | #define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C14UL) /**< \brief (SERCOM1) SPI Address */ 99 | #define REG_SERCOM1_SPI_DATA (*(RwReg16*)0x42000C18UL) /**< \brief (SERCOM1) SPI Data */ 100 | #define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) USART Control A */ 101 | #define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) USART Control B */ 102 | #define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C08UL) /**< \brief (SERCOM1) USART Debug Control */ 103 | #define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0AUL) /**< \brief (SERCOM1) USART Baud */ 104 | #define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ 105 | #define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C0DUL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ 106 | #define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ 107 | #define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C10UL) /**< \brief (SERCOM1) USART Status */ 108 | #define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C18UL) /**< \brief (SERCOM1) USART Data */ 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 | 111 | /* ========== Instance parameters for SERCOM1 peripheral ========== */ 112 | #define SERCOM1_GCLK_ID_CORE 14 113 | #define SERCOM1_GCLK_ID_SLOW 12 114 | #define SERCOM1_INT_MSB 3 115 | #define SERCOM1_PMSB 3 116 | 117 | #endif /* _SAMD20_SERCOM1_INSTANCE_ */ 118 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sercom2.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SERCOM2 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SERCOM2_INSTANCE_ 30 | #define _SAMD20_SERCOM2_INSTANCE_ 31 | 32 | /* ========== Register definition for SERCOM2 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SERCOM2_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CM Control A */ 35 | #define REG_SERCOM2_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CM Control B */ 36 | #define REG_SERCOM2_I2CM_DBGCTRL (0x42001008) /**< \brief (SERCOM2) I2CM Debug Control */ 37 | #define REG_SERCOM2_I2CM_BAUD (0x4200100A) /**< \brief (SERCOM2) I2CM Baud Rate */ 38 | #define REG_SERCOM2_I2CM_INTENCLR (0x4200100C) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ 39 | #define REG_SERCOM2_I2CM_INTENSET (0x4200100D) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ 40 | #define REG_SERCOM2_I2CM_INTFLAG (0x4200100E) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ 41 | #define REG_SERCOM2_I2CM_STATUS (0x42001010) /**< \brief (SERCOM2) I2CM Status */ 42 | #define REG_SERCOM2_I2CM_ADDR (0x42001014) /**< \brief (SERCOM2) I2CM Address */ 43 | #define REG_SERCOM2_I2CM_DATA (0x42001018) /**< \brief (SERCOM2) I2CM Data */ 44 | #define REG_SERCOM2_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CS Control A */ 45 | #define REG_SERCOM2_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CS Control B */ 46 | #define REG_SERCOM2_I2CS_INTENCLR (0x4200100C) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ 47 | #define REG_SERCOM2_I2CS_INTENSET (0x4200100D) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ 48 | #define REG_SERCOM2_I2CS_INTFLAG (0x4200100E) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ 49 | #define REG_SERCOM2_I2CS_STATUS (0x42001010) /**< \brief (SERCOM2) I2CS Status */ 50 | #define REG_SERCOM2_I2CS_ADDR (0x42001014) /**< \brief (SERCOM2) I2CS Address */ 51 | #define REG_SERCOM2_I2CS_DATA (0x42001018) /**< \brief (SERCOM2) I2CS Data */ 52 | #define REG_SERCOM2_SPI_CTRLA (0x42001000) /**< \brief (SERCOM2) SPI Control A */ 53 | #define REG_SERCOM2_SPI_CTRLB (0x42001004) /**< \brief (SERCOM2) SPI Control B */ 54 | #define REG_SERCOM2_SPI_DBGCTRL (0x42001008) /**< \brief (SERCOM2) SPI Debug Control */ 55 | #define REG_SERCOM2_SPI_BAUD (0x4200100A) /**< \brief (SERCOM2) SPI Baud Rate */ 56 | #define REG_SERCOM2_SPI_INTENCLR (0x4200100C) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ 57 | #define REG_SERCOM2_SPI_INTENSET (0x4200100D) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ 58 | #define REG_SERCOM2_SPI_INTFLAG (0x4200100E) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ 59 | #define REG_SERCOM2_SPI_STATUS (0x42001010) /**< \brief (SERCOM2) SPI Status */ 60 | #define REG_SERCOM2_SPI_ADDR (0x42001014) /**< \brief (SERCOM2) SPI Address */ 61 | #define REG_SERCOM2_SPI_DATA (0x42001018) /**< \brief (SERCOM2) SPI Data */ 62 | #define REG_SERCOM2_USART_CTRLA (0x42001000) /**< \brief (SERCOM2) USART Control A */ 63 | #define REG_SERCOM2_USART_CTRLB (0x42001004) /**< \brief (SERCOM2) USART Control B */ 64 | #define REG_SERCOM2_USART_DBGCTRL (0x42001008) /**< \brief (SERCOM2) USART Debug Control */ 65 | #define REG_SERCOM2_USART_BAUD (0x4200100A) /**< \brief (SERCOM2) USART Baud */ 66 | #define REG_SERCOM2_USART_INTENCLR (0x4200100C) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ 67 | #define REG_SERCOM2_USART_INTENSET (0x4200100D) /**< \brief (SERCOM2) USART Interrupt Enable Set */ 68 | #define REG_SERCOM2_USART_INTFLAG (0x4200100E) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ 69 | #define REG_SERCOM2_USART_STATUS (0x42001010) /**< \brief (SERCOM2) USART Status */ 70 | #define REG_SERCOM2_USART_DATA (0x42001018) /**< \brief (SERCOM2) USART Data */ 71 | #else 72 | #define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CM Control A */ 73 | #define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CM Control B */ 74 | #define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001008UL) /**< \brief (SERCOM2) I2CM Debug Control */ 75 | #define REG_SERCOM2_I2CM_BAUD (*(RwReg16*)0x4200100AUL) /**< \brief (SERCOM2) I2CM Baud Rate */ 76 | #define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ 77 | #define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x4200100DUL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ 78 | #define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ 79 | #define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42001010UL) /**< \brief (SERCOM2) I2CM Status */ 80 | #define REG_SERCOM2_I2CM_ADDR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Address */ 81 | #define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Data */ 82 | #define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CS Control A */ 83 | #define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CS Control B */ 84 | #define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ 85 | #define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x4200100DUL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ 86 | #define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ 87 | #define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42001010UL) /**< \brief (SERCOM2) I2CS Status */ 88 | #define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001014UL) /**< \brief (SERCOM2) I2CS Address */ 89 | #define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Data */ 90 | #define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) SPI Control A */ 91 | #define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) SPI Control B */ 92 | #define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001008UL) /**< \brief (SERCOM2) SPI Debug Control */ 93 | #define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100AUL) /**< \brief (SERCOM2) SPI Baud Rate */ 94 | #define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ 95 | #define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x4200100DUL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ 96 | #define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ 97 | #define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42001010UL) /**< \brief (SERCOM2) SPI Status */ 98 | #define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001014UL) /**< \brief (SERCOM2) SPI Address */ 99 | #define REG_SERCOM2_SPI_DATA (*(RwReg16*)0x42001018UL) /**< \brief (SERCOM2) SPI Data */ 100 | #define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) USART Control A */ 101 | #define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) USART Control B */ 102 | #define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001008UL) /**< \brief (SERCOM2) USART Debug Control */ 103 | #define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100AUL) /**< \brief (SERCOM2) USART Baud */ 104 | #define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ 105 | #define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x4200100DUL) /**< \brief (SERCOM2) USART Interrupt Enable Set */ 106 | #define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ 107 | #define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42001010UL) /**< \brief (SERCOM2) USART Status */ 108 | #define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001018UL) /**< \brief (SERCOM2) USART Data */ 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 | 111 | /* ========== Instance parameters for SERCOM2 peripheral ========== */ 112 | #define SERCOM2_GCLK_ID_CORE 15 113 | #define SERCOM2_GCLK_ID_SLOW 12 114 | #define SERCOM2_INT_MSB 3 115 | #define SERCOM2_PMSB 3 116 | 117 | #endif /* _SAMD20_SERCOM2_INSTANCE_ */ 118 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sercom3.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SERCOM3 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SERCOM3_INSTANCE_ 30 | #define _SAMD20_SERCOM3_INSTANCE_ 31 | 32 | /* ========== Register definition for SERCOM3 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SERCOM3_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CM Control A */ 35 | #define REG_SERCOM3_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CM Control B */ 36 | #define REG_SERCOM3_I2CM_DBGCTRL (0x42001408) /**< \brief (SERCOM3) I2CM Debug Control */ 37 | #define REG_SERCOM3_I2CM_BAUD (0x4200140A) /**< \brief (SERCOM3) I2CM Baud Rate */ 38 | #define REG_SERCOM3_I2CM_INTENCLR (0x4200140C) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ 39 | #define REG_SERCOM3_I2CM_INTENSET (0x4200140D) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ 40 | #define REG_SERCOM3_I2CM_INTFLAG (0x4200140E) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ 41 | #define REG_SERCOM3_I2CM_STATUS (0x42001410) /**< \brief (SERCOM3) I2CM Status */ 42 | #define REG_SERCOM3_I2CM_ADDR (0x42001414) /**< \brief (SERCOM3) I2CM Address */ 43 | #define REG_SERCOM3_I2CM_DATA (0x42001418) /**< \brief (SERCOM3) I2CM Data */ 44 | #define REG_SERCOM3_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CS Control A */ 45 | #define REG_SERCOM3_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CS Control B */ 46 | #define REG_SERCOM3_I2CS_INTENCLR (0x4200140C) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ 47 | #define REG_SERCOM3_I2CS_INTENSET (0x4200140D) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ 48 | #define REG_SERCOM3_I2CS_INTFLAG (0x4200140E) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ 49 | #define REG_SERCOM3_I2CS_STATUS (0x42001410) /**< \brief (SERCOM3) I2CS Status */ 50 | #define REG_SERCOM3_I2CS_ADDR (0x42001414) /**< \brief (SERCOM3) I2CS Address */ 51 | #define REG_SERCOM3_I2CS_DATA (0x42001418) /**< \brief (SERCOM3) I2CS Data */ 52 | #define REG_SERCOM3_SPI_CTRLA (0x42001400) /**< \brief (SERCOM3) SPI Control A */ 53 | #define REG_SERCOM3_SPI_CTRLB (0x42001404) /**< \brief (SERCOM3) SPI Control B */ 54 | #define REG_SERCOM3_SPI_DBGCTRL (0x42001408) /**< \brief (SERCOM3) SPI Debug Control */ 55 | #define REG_SERCOM3_SPI_BAUD (0x4200140A) /**< \brief (SERCOM3) SPI Baud Rate */ 56 | #define REG_SERCOM3_SPI_INTENCLR (0x4200140C) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ 57 | #define REG_SERCOM3_SPI_INTENSET (0x4200140D) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ 58 | #define REG_SERCOM3_SPI_INTFLAG (0x4200140E) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ 59 | #define REG_SERCOM3_SPI_STATUS (0x42001410) /**< \brief (SERCOM3) SPI Status */ 60 | #define REG_SERCOM3_SPI_ADDR (0x42001414) /**< \brief (SERCOM3) SPI Address */ 61 | #define REG_SERCOM3_SPI_DATA (0x42001418) /**< \brief (SERCOM3) SPI Data */ 62 | #define REG_SERCOM3_USART_CTRLA (0x42001400) /**< \brief (SERCOM3) USART Control A */ 63 | #define REG_SERCOM3_USART_CTRLB (0x42001404) /**< \brief (SERCOM3) USART Control B */ 64 | #define REG_SERCOM3_USART_DBGCTRL (0x42001408) /**< \brief (SERCOM3) USART Debug Control */ 65 | #define REG_SERCOM3_USART_BAUD (0x4200140A) /**< \brief (SERCOM3) USART Baud */ 66 | #define REG_SERCOM3_USART_INTENCLR (0x4200140C) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ 67 | #define REG_SERCOM3_USART_INTENSET (0x4200140D) /**< \brief (SERCOM3) USART Interrupt Enable Set */ 68 | #define REG_SERCOM3_USART_INTFLAG (0x4200140E) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ 69 | #define REG_SERCOM3_USART_STATUS (0x42001410) /**< \brief (SERCOM3) USART Status */ 70 | #define REG_SERCOM3_USART_DATA (0x42001418) /**< \brief (SERCOM3) USART Data */ 71 | #else 72 | #define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CM Control A */ 73 | #define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CM Control B */ 74 | #define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001408UL) /**< \brief (SERCOM3) I2CM Debug Control */ 75 | #define REG_SERCOM3_I2CM_BAUD (*(RwReg16*)0x4200140AUL) /**< \brief (SERCOM3) I2CM Baud Rate */ 76 | #define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ 77 | #define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x4200140DUL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ 78 | #define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ 79 | #define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x42001410UL) /**< \brief (SERCOM3) I2CM Status */ 80 | #define REG_SERCOM3_I2CM_ADDR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Address */ 81 | #define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Data */ 82 | #define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CS Control A */ 83 | #define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CS Control B */ 84 | #define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ 85 | #define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x4200140DUL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ 86 | #define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ 87 | #define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x42001410UL) /**< \brief (SERCOM3) I2CS Status */ 88 | #define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001414UL) /**< \brief (SERCOM3) I2CS Address */ 89 | #define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Data */ 90 | #define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) SPI Control A */ 91 | #define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) SPI Control B */ 92 | #define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001408UL) /**< \brief (SERCOM3) SPI Debug Control */ 93 | #define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140AUL) /**< \brief (SERCOM3) SPI Baud Rate */ 94 | #define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ 95 | #define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x4200140DUL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ 96 | #define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ 97 | #define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x42001410UL) /**< \brief (SERCOM3) SPI Status */ 98 | #define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001414UL) /**< \brief (SERCOM3) SPI Address */ 99 | #define REG_SERCOM3_SPI_DATA (*(RwReg16*)0x42001418UL) /**< \brief (SERCOM3) SPI Data */ 100 | #define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) USART Control A */ 101 | #define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) USART Control B */ 102 | #define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001408UL) /**< \brief (SERCOM3) USART Debug Control */ 103 | #define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140AUL) /**< \brief (SERCOM3) USART Baud */ 104 | #define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ 105 | #define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x4200140DUL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ 106 | #define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ 107 | #define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x42001410UL) /**< \brief (SERCOM3) USART Status */ 108 | #define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001418UL) /**< \brief (SERCOM3) USART Data */ 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 | 111 | /* ========== Instance parameters for SERCOM3 peripheral ========== */ 112 | #define SERCOM3_GCLK_ID_CORE 16 113 | #define SERCOM3_GCLK_ID_SLOW 12 114 | #define SERCOM3_INT_MSB 3 115 | #define SERCOM3_PMSB 3 116 | 117 | #endif /* _SAMD20_SERCOM3_INSTANCE_ */ 118 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sercom4.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SERCOM4 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SERCOM4_INSTANCE_ 30 | #define _SAMD20_SERCOM4_INSTANCE_ 31 | 32 | /* ========== Register definition for SERCOM4 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SERCOM4_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CM Control A */ 35 | #define REG_SERCOM4_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CM Control B */ 36 | #define REG_SERCOM4_I2CM_DBGCTRL (0x42001808) /**< \brief (SERCOM4) I2CM Debug Control */ 37 | #define REG_SERCOM4_I2CM_BAUD (0x4200180A) /**< \brief (SERCOM4) I2CM Baud Rate */ 38 | #define REG_SERCOM4_I2CM_INTENCLR (0x4200180C) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ 39 | #define REG_SERCOM4_I2CM_INTENSET (0x4200180D) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ 40 | #define REG_SERCOM4_I2CM_INTFLAG (0x4200180E) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ 41 | #define REG_SERCOM4_I2CM_STATUS (0x42001810) /**< \brief (SERCOM4) I2CM Status */ 42 | #define REG_SERCOM4_I2CM_ADDR (0x42001814) /**< \brief (SERCOM4) I2CM Address */ 43 | #define REG_SERCOM4_I2CM_DATA (0x42001818) /**< \brief (SERCOM4) I2CM Data */ 44 | #define REG_SERCOM4_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CS Control A */ 45 | #define REG_SERCOM4_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CS Control B */ 46 | #define REG_SERCOM4_I2CS_INTENCLR (0x4200180C) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ 47 | #define REG_SERCOM4_I2CS_INTENSET (0x4200180D) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ 48 | #define REG_SERCOM4_I2CS_INTFLAG (0x4200180E) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ 49 | #define REG_SERCOM4_I2CS_STATUS (0x42001810) /**< \brief (SERCOM4) I2CS Status */ 50 | #define REG_SERCOM4_I2CS_ADDR (0x42001814) /**< \brief (SERCOM4) I2CS Address */ 51 | #define REG_SERCOM4_I2CS_DATA (0x42001818) /**< \brief (SERCOM4) I2CS Data */ 52 | #define REG_SERCOM4_SPI_CTRLA (0x42001800) /**< \brief (SERCOM4) SPI Control A */ 53 | #define REG_SERCOM4_SPI_CTRLB (0x42001804) /**< \brief (SERCOM4) SPI Control B */ 54 | #define REG_SERCOM4_SPI_DBGCTRL (0x42001808) /**< \brief (SERCOM4) SPI Debug Control */ 55 | #define REG_SERCOM4_SPI_BAUD (0x4200180A) /**< \brief (SERCOM4) SPI Baud Rate */ 56 | #define REG_SERCOM4_SPI_INTENCLR (0x4200180C) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ 57 | #define REG_SERCOM4_SPI_INTENSET (0x4200180D) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ 58 | #define REG_SERCOM4_SPI_INTFLAG (0x4200180E) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ 59 | #define REG_SERCOM4_SPI_STATUS (0x42001810) /**< \brief (SERCOM4) SPI Status */ 60 | #define REG_SERCOM4_SPI_ADDR (0x42001814) /**< \brief (SERCOM4) SPI Address */ 61 | #define REG_SERCOM4_SPI_DATA (0x42001818) /**< \brief (SERCOM4) SPI Data */ 62 | #define REG_SERCOM4_USART_CTRLA (0x42001800) /**< \brief (SERCOM4) USART Control A */ 63 | #define REG_SERCOM4_USART_CTRLB (0x42001804) /**< \brief (SERCOM4) USART Control B */ 64 | #define REG_SERCOM4_USART_DBGCTRL (0x42001808) /**< \brief (SERCOM4) USART Debug Control */ 65 | #define REG_SERCOM4_USART_BAUD (0x4200180A) /**< \brief (SERCOM4) USART Baud */ 66 | #define REG_SERCOM4_USART_INTENCLR (0x4200180C) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ 67 | #define REG_SERCOM4_USART_INTENSET (0x4200180D) /**< \brief (SERCOM4) USART Interrupt Enable Set */ 68 | #define REG_SERCOM4_USART_INTFLAG (0x4200180E) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ 69 | #define REG_SERCOM4_USART_STATUS (0x42001810) /**< \brief (SERCOM4) USART Status */ 70 | #define REG_SERCOM4_USART_DATA (0x42001818) /**< \brief (SERCOM4) USART Data */ 71 | #else 72 | #define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CM Control A */ 73 | #define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CM Control B */ 74 | #define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001808UL) /**< \brief (SERCOM4) I2CM Debug Control */ 75 | #define REG_SERCOM4_I2CM_BAUD (*(RwReg16*)0x4200180AUL) /**< \brief (SERCOM4) I2CM Baud Rate */ 76 | #define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ 77 | #define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ 78 | #define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ 79 | #define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x42001810UL) /**< \brief (SERCOM4) I2CM Status */ 80 | #define REG_SERCOM4_I2CM_ADDR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Address */ 81 | #define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Data */ 82 | #define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CS Control A */ 83 | #define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CS Control B */ 84 | #define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ 85 | #define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ 86 | #define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ 87 | #define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x42001810UL) /**< \brief (SERCOM4) I2CS Status */ 88 | #define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001814UL) /**< \brief (SERCOM4) I2CS Address */ 89 | #define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Data */ 90 | #define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) SPI Control A */ 91 | #define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) SPI Control B */ 92 | #define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001808UL) /**< \brief (SERCOM4) SPI Debug Control */ 93 | #define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180AUL) /**< \brief (SERCOM4) SPI Baud Rate */ 94 | #define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ 95 | #define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ 96 | #define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ 97 | #define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x42001810UL) /**< \brief (SERCOM4) SPI Status */ 98 | #define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001814UL) /**< \brief (SERCOM4) SPI Address */ 99 | #define REG_SERCOM4_SPI_DATA (*(RwReg16*)0x42001818UL) /**< \brief (SERCOM4) SPI Data */ 100 | #define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) USART Control A */ 101 | #define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) USART Control B */ 102 | #define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001808UL) /**< \brief (SERCOM4) USART Debug Control */ 103 | #define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180AUL) /**< \brief (SERCOM4) USART Baud */ 104 | #define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ 105 | #define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x4200180DUL) /**< \brief (SERCOM4) USART Interrupt Enable Set */ 106 | #define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ 107 | #define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x42001810UL) /**< \brief (SERCOM4) USART Status */ 108 | #define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001818UL) /**< \brief (SERCOM4) USART Data */ 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 | 111 | /* ========== Instance parameters for SERCOM4 peripheral ========== */ 112 | #define SERCOM4_GCLK_ID_CORE 17 113 | #define SERCOM4_GCLK_ID_SLOW 12 114 | #define SERCOM4_INT_MSB 3 115 | #define SERCOM4_PMSB 3 116 | 117 | #endif /* _SAMD20_SERCOM4_INSTANCE_ */ 118 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sercom5.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SERCOM5 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SERCOM5_INSTANCE_ 30 | #define _SAMD20_SERCOM5_INSTANCE_ 31 | 32 | /* ========== Register definition for SERCOM5 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SERCOM5_I2CM_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CM Control A */ 35 | #define REG_SERCOM5_I2CM_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CM Control B */ 36 | #define REG_SERCOM5_I2CM_DBGCTRL (0x42001C08) /**< \brief (SERCOM5) I2CM Debug Control */ 37 | #define REG_SERCOM5_I2CM_BAUD (0x42001C0A) /**< \brief (SERCOM5) I2CM Baud Rate */ 38 | #define REG_SERCOM5_I2CM_INTENCLR (0x42001C0C) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ 39 | #define REG_SERCOM5_I2CM_INTENSET (0x42001C0D) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ 40 | #define REG_SERCOM5_I2CM_INTFLAG (0x42001C0E) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ 41 | #define REG_SERCOM5_I2CM_STATUS (0x42001C10) /**< \brief (SERCOM5) I2CM Status */ 42 | #define REG_SERCOM5_I2CM_ADDR (0x42001C14) /**< \brief (SERCOM5) I2CM Address */ 43 | #define REG_SERCOM5_I2CM_DATA (0x42001C18) /**< \brief (SERCOM5) I2CM Data */ 44 | #define REG_SERCOM5_I2CS_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CS Control A */ 45 | #define REG_SERCOM5_I2CS_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CS Control B */ 46 | #define REG_SERCOM5_I2CS_INTENCLR (0x42001C0C) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ 47 | #define REG_SERCOM5_I2CS_INTENSET (0x42001C0D) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ 48 | #define REG_SERCOM5_I2CS_INTFLAG (0x42001C0E) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ 49 | #define REG_SERCOM5_I2CS_STATUS (0x42001C10) /**< \brief (SERCOM5) I2CS Status */ 50 | #define REG_SERCOM5_I2CS_ADDR (0x42001C14) /**< \brief (SERCOM5) I2CS Address */ 51 | #define REG_SERCOM5_I2CS_DATA (0x42001C18) /**< \brief (SERCOM5) I2CS Data */ 52 | #define REG_SERCOM5_SPI_CTRLA (0x42001C00) /**< \brief (SERCOM5) SPI Control A */ 53 | #define REG_SERCOM5_SPI_CTRLB (0x42001C04) /**< \brief (SERCOM5) SPI Control B */ 54 | #define REG_SERCOM5_SPI_DBGCTRL (0x42001C08) /**< \brief (SERCOM5) SPI Debug Control */ 55 | #define REG_SERCOM5_SPI_BAUD (0x42001C0A) /**< \brief (SERCOM5) SPI Baud Rate */ 56 | #define REG_SERCOM5_SPI_INTENCLR (0x42001C0C) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ 57 | #define REG_SERCOM5_SPI_INTENSET (0x42001C0D) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ 58 | #define REG_SERCOM5_SPI_INTFLAG (0x42001C0E) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ 59 | #define REG_SERCOM5_SPI_STATUS (0x42001C10) /**< \brief (SERCOM5) SPI Status */ 60 | #define REG_SERCOM5_SPI_ADDR (0x42001C14) /**< \brief (SERCOM5) SPI Address */ 61 | #define REG_SERCOM5_SPI_DATA (0x42001C18) /**< \brief (SERCOM5) SPI Data */ 62 | #define REG_SERCOM5_USART_CTRLA (0x42001C00) /**< \brief (SERCOM5) USART Control A */ 63 | #define REG_SERCOM5_USART_CTRLB (0x42001C04) /**< \brief (SERCOM5) USART Control B */ 64 | #define REG_SERCOM5_USART_DBGCTRL (0x42001C08) /**< \brief (SERCOM5) USART Debug Control */ 65 | #define REG_SERCOM5_USART_BAUD (0x42001C0A) /**< \brief (SERCOM5) USART Baud */ 66 | #define REG_SERCOM5_USART_INTENCLR (0x42001C0C) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ 67 | #define REG_SERCOM5_USART_INTENSET (0x42001C0D) /**< \brief (SERCOM5) USART Interrupt Enable Set */ 68 | #define REG_SERCOM5_USART_INTFLAG (0x42001C0E) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ 69 | #define REG_SERCOM5_USART_STATUS (0x42001C10) /**< \brief (SERCOM5) USART Status */ 70 | #define REG_SERCOM5_USART_DATA (0x42001C18) /**< \brief (SERCOM5) USART Data */ 71 | #else 72 | #define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CM Control A */ 73 | #define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CM Control B */ 74 | #define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C08UL) /**< \brief (SERCOM5) I2CM Debug Control */ 75 | #define REG_SERCOM5_I2CM_BAUD (*(RwReg16*)0x42001C0AUL) /**< \brief (SERCOM5) I2CM Baud Rate */ 76 | #define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ 77 | #define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C0DUL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ 78 | #define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ 79 | #define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C10UL) /**< \brief (SERCOM5) I2CM Status */ 80 | #define REG_SERCOM5_I2CM_ADDR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Address */ 81 | #define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Data */ 82 | #define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CS Control A */ 83 | #define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CS Control B */ 84 | #define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ 85 | #define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C0DUL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ 86 | #define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ 87 | #define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C10UL) /**< \brief (SERCOM5) I2CS Status */ 88 | #define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Address */ 89 | #define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Data */ 90 | #define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) SPI Control A */ 91 | #define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) SPI Control B */ 92 | #define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C08UL) /**< \brief (SERCOM5) SPI Debug Control */ 93 | #define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0AUL) /**< \brief (SERCOM5) SPI Baud Rate */ 94 | #define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ 95 | #define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C0DUL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ 96 | #define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ 97 | #define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C10UL) /**< \brief (SERCOM5) SPI Status */ 98 | #define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C14UL) /**< \brief (SERCOM5) SPI Address */ 99 | #define REG_SERCOM5_SPI_DATA (*(RwReg16*)0x42001C18UL) /**< \brief (SERCOM5) SPI Data */ 100 | #define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) USART Control A */ 101 | #define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) USART Control B */ 102 | #define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C08UL) /**< \brief (SERCOM5) USART Debug Control */ 103 | #define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0AUL) /**< \brief (SERCOM5) USART Baud */ 104 | #define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ 105 | #define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C0DUL) /**< \brief (SERCOM5) USART Interrupt Enable Set */ 106 | #define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ 107 | #define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C10UL) /**< \brief (SERCOM5) USART Status */ 108 | #define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C18UL) /**< \brief (SERCOM5) USART Data */ 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 | 111 | /* ========== Instance parameters for SERCOM5 peripheral ========== */ 112 | #define SERCOM5_GCLK_ID_CORE 18 113 | #define SERCOM5_GCLK_ID_SLOW 12 114 | #define SERCOM5_INT_MSB 3 115 | #define SERCOM5_PMSB 3 116 | 117 | #endif /* _SAMD20_SERCOM5_INSTANCE_ */ 118 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/sysctrl.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for SYSCTRL 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_SYSCTRL_INSTANCE_ 30 | #define _SAMD20_SYSCTRL_INSTANCE_ 31 | 32 | /* ========== Register definition for SYSCTRL peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_SYSCTRL_INTENCLR (0x40000800) /**< \brief (SYSCTRL) Interrupt Enable Clear */ 35 | #define REG_SYSCTRL_INTENSET (0x40000804) /**< \brief (SYSCTRL) Interrupt Enable Set */ 36 | #define REG_SYSCTRL_INTFLAG (0x40000808) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ 37 | #define REG_SYSCTRL_PCLKSR (0x4000080C) /**< \brief (SYSCTRL) Power and Clocks Status */ 38 | #define REG_SYSCTRL_XOSC (0x40000810) /**< \brief (SYSCTRL) XOSC Control */ 39 | #define REG_SYSCTRL_XOSC32K (0x40000814) /**< \brief (SYSCTRL) XOSC32K Control */ 40 | #define REG_SYSCTRL_OSC32K (0x40000818) /**< \brief (SYSCTRL) OSC32K Control */ 41 | #define REG_SYSCTRL_OSCULP32K (0x4000081C) /**< \brief (SYSCTRL) OSCULP32K Control */ 42 | #define REG_SYSCTRL_OSC8M (0x40000820) /**< \brief (SYSCTRL) OSC8M Control A */ 43 | #define REG_SYSCTRL_DFLLCTRL (0x40000824) /**< \brief (SYSCTRL) DFLL Config */ 44 | #define REG_SYSCTRL_DFLLVAL (0x40000828) /**< \brief (SYSCTRL) DFLL Calibration Value */ 45 | #define REG_SYSCTRL_DFLLMUL (0x4000082C) /**< \brief (SYSCTRL) DFLL Multiplier */ 46 | #define REG_SYSCTRL_DFLLSYNC (0x40000830) /**< \brief (SYSCTRL) DFLL Synchronization */ 47 | #define REG_SYSCTRL_BOD33 (0x40000834) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ 48 | #define REG_SYSCTRL_VREG (0x4000083C) /**< \brief (SYSCTRL) VREG Control */ 49 | #define REG_SYSCTRL_VREF (0x40000840) /**< \brief (SYSCTRL) VREF Control A */ 50 | #else 51 | #define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800UL) /**< \brief (SYSCTRL) Interrupt Enable Clear */ 52 | #define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804UL) /**< \brief (SYSCTRL) Interrupt Enable Set */ 53 | #define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808UL) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ 54 | #define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CUL) /**< \brief (SYSCTRL) Power and Clocks Status */ 55 | #define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810UL) /**< \brief (SYSCTRL) XOSC Control */ 56 | #define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814UL) /**< \brief (SYSCTRL) XOSC32K Control */ 57 | #define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818UL) /**< \brief (SYSCTRL) OSC32K Control */ 58 | #define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CUL) /**< \brief (SYSCTRL) OSCULP32K Control */ 59 | #define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820UL) /**< \brief (SYSCTRL) OSC8M Control A */ 60 | #define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824UL) /**< \brief (SYSCTRL) DFLL Config */ 61 | #define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828UL) /**< \brief (SYSCTRL) DFLL Calibration Value */ 62 | #define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CUL) /**< \brief (SYSCTRL) DFLL Multiplier */ 63 | #define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830UL) /**< \brief (SYSCTRL) DFLL Synchronization */ 64 | #define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834UL) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ 65 | #define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CUL) /**< \brief (SYSCTRL) VREG Control */ 66 | #define REG_SYSCTRL_VREF (*(RwReg *)0x40000840UL) /**< \brief (SYSCTRL) VREF Control A */ 67 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 | 69 | /* ========== Instance parameters for SYSCTRL peripheral ========== */ 70 | #define SYSCTRL_BGAP_CALIB_MSB 11 71 | #define SYSCTRL_BOD33_CALIB_MSB 5 72 | #define SYSCTRL_DFLL48M_COARSE_MSB 4 73 | #define SYSCTRL_DFLL48M_FINE_MSB 7 74 | #define SYSCTRL_GCLK_ID_DFLL48 0 75 | #define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 76 | #define SYSCTRL_POR33_ENTEST_MSB 1 77 | #define SYSCTRL_ULPVREF_DIVLEV_MSB 3 78 | #define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 79 | #define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 80 | #define SYSCTRL_VREF_CONTROL_MSB 48 81 | #define SYSCTRL_VREF_STATUS_MSB 7 82 | #define SYSCTRL_VREG_LEVEL_MSB 2 83 | #define SYSCTRL_BOD12_VERSION 0x111 84 | #define SYSCTRL_BOD33_VERSION 0x111 85 | #define SYSCTRL_DFLL48M_VERSION 0x211 86 | #define SYSCTRL_GCLK_VERSION 0x210 87 | #define SYSCTRL_OSCULP32K_VERSION 0x111 88 | #define SYSCTRL_OSC8M_VERSION 0x120 89 | #define SYSCTRL_OSC32K_VERSION 0x1101 90 | #define SYSCTRL_VREF_VERSION 0x200 91 | #define SYSCTRL_VREG_VERSION 0x201 92 | #define SYSCTRL_XOSC_VERSION 0x1101 93 | #define SYSCTRL_XOSC32K_VERSION 0x1101 94 | 95 | #endif /* _SAMD20_SYSCTRL_INSTANCE_ */ 96 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc0.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC0 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC0_INSTANCE_ 30 | #define _SAMD20_TC0_INSTANCE_ 31 | 32 | /* ========== Register definition for TC0 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC0_CTRLA (0x42002000) /**< \brief (TC0) Control A */ 35 | #define REG_TC0_READREQ (0x42002002) /**< \brief (TC0) Read Request */ 36 | #define REG_TC0_CTRLBCLR (0x42002004) /**< \brief (TC0) Control B Clear */ 37 | #define REG_TC0_CTRLBSET (0x42002005) /**< \brief (TC0) Control B Set */ 38 | #define REG_TC0_CTRLC (0x42002006) /**< \brief (TC0) Control C */ 39 | #define REG_TC0_DBGCTRL (0x42002008) /**< \brief (TC0) Debug Control */ 40 | #define REG_TC0_EVCTRL (0x4200200A) /**< \brief (TC0) Event Control */ 41 | #define REG_TC0_INTENCLR (0x4200200C) /**< \brief (TC0) Interrupt Enable Clear */ 42 | #define REG_TC0_INTENSET (0x4200200D) /**< \brief (TC0) Interrupt Enable Set */ 43 | #define REG_TC0_INTFLAG (0x4200200E) /**< \brief (TC0) Interrupt Flag Status and Clear */ 44 | #define REG_TC0_STATUS (0x4200200F) /**< \brief (TC0) Status */ 45 | #define REG_TC0_COUNT16_COUNT (0x42002010) /**< \brief (TC0) COUNT16 Counter Value */ 46 | #define REG_TC0_COUNT16_CC0 (0x42002018) /**< \brief (TC0) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC0_COUNT16_CC1 (0x4200201A) /**< \brief (TC0) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC0_COUNT32_COUNT (0x42002010) /**< \brief (TC0) COUNT32 Counter Value */ 49 | #define REG_TC0_COUNT32_CC0 (0x42002018) /**< \brief (TC0) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC0_COUNT32_CC1 (0x4200201C) /**< \brief (TC0) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC0_COUNT8_COUNT (0x42002010) /**< \brief (TC0) COUNT8 Counter Value */ 52 | #define REG_TC0_COUNT8_PER (0x42002014) /**< \brief (TC0) COUNT8 Period Value */ 53 | #define REG_TC0_COUNT8_CC0 (0x42002018) /**< \brief (TC0) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC0_COUNT8_CC1 (0x42002019) /**< \brief (TC0) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC0_CTRLA (*(RwReg16*)0x42002000UL) /**< \brief (TC0) Control A */ 57 | #define REG_TC0_READREQ (*(RwReg16*)0x42002002UL) /**< \brief (TC0) Read Request */ 58 | #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */ 59 | #define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */ 60 | #define REG_TC0_CTRLC (*(RwReg8 *)0x42002006UL) /**< \brief (TC0) Control C */ 61 | #define REG_TC0_DBGCTRL (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Debug Control */ 62 | #define REG_TC0_EVCTRL (*(RwReg16*)0x4200200AUL) /**< \brief (TC0) Event Control */ 63 | #define REG_TC0_INTENCLR (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Interrupt Enable Clear */ 64 | #define REG_TC0_INTENSET (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Interrupt Enable Set */ 65 | #define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200EUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ 66 | #define REG_TC0_STATUS (*(RoReg8 *)0x4200200FUL) /**< \brief (TC0) Status */ 67 | #define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002010UL) /**< \brief (TC0) COUNT16 Counter Value */ 68 | #define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x42002018UL) /**< \brief (TC0) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201AUL) /**< \brief (TC0) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002010UL) /**< \brief (TC0) COUNT32 Counter Value */ 71 | #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x42002018UL) /**< \brief (TC0) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002010UL) /**< \brief (TC0) COUNT8 Counter Value */ 74 | #define REG_TC0_COUNT8_PER (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Period Value */ 75 | #define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x42002018UL) /**< \brief (TC0) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x42002019UL) /**< \brief (TC0) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC0 peripheral ========== */ 80 | #define TC0_CC8_NUM 2 81 | #define TC0_CC16_NUM 2 82 | #define TC0_CC32_NUM 2 83 | #define TC0_DITHERING_EXT 0 84 | #define TC0_GCLK_ID 19 85 | #define TC0_MASTER 1 86 | #define TC0_OW_NUM 2 87 | #define TC0_PERIOD_EXT 0 88 | #define TC0_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC0_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc1.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC1 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC1_INSTANCE_ 30 | #define _SAMD20_TC1_INSTANCE_ 31 | 32 | /* ========== Register definition for TC1 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC1_CTRLA (0x42002400) /**< \brief (TC1) Control A */ 35 | #define REG_TC1_READREQ (0x42002402) /**< \brief (TC1) Read Request */ 36 | #define REG_TC1_CTRLBCLR (0x42002404) /**< \brief (TC1) Control B Clear */ 37 | #define REG_TC1_CTRLBSET (0x42002405) /**< \brief (TC1) Control B Set */ 38 | #define REG_TC1_CTRLC (0x42002406) /**< \brief (TC1) Control C */ 39 | #define REG_TC1_DBGCTRL (0x42002408) /**< \brief (TC1) Debug Control */ 40 | #define REG_TC1_EVCTRL (0x4200240A) /**< \brief (TC1) Event Control */ 41 | #define REG_TC1_INTENCLR (0x4200240C) /**< \brief (TC1) Interrupt Enable Clear */ 42 | #define REG_TC1_INTENSET (0x4200240D) /**< \brief (TC1) Interrupt Enable Set */ 43 | #define REG_TC1_INTFLAG (0x4200240E) /**< \brief (TC1) Interrupt Flag Status and Clear */ 44 | #define REG_TC1_STATUS (0x4200240F) /**< \brief (TC1) Status */ 45 | #define REG_TC1_COUNT16_COUNT (0x42002410) /**< \brief (TC1) COUNT16 Counter Value */ 46 | #define REG_TC1_COUNT16_CC0 (0x42002418) /**< \brief (TC1) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC1_COUNT16_CC1 (0x4200241A) /**< \brief (TC1) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC1_COUNT32_COUNT (0x42002410) /**< \brief (TC1) COUNT32 Counter Value */ 49 | #define REG_TC1_COUNT32_CC0 (0x42002418) /**< \brief (TC1) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC1_COUNT32_CC1 (0x4200241C) /**< \brief (TC1) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC1_COUNT8_COUNT (0x42002410) /**< \brief (TC1) COUNT8 Counter Value */ 52 | #define REG_TC1_COUNT8_PER (0x42002414) /**< \brief (TC1) COUNT8 Period Value */ 53 | #define REG_TC1_COUNT8_CC0 (0x42002418) /**< \brief (TC1) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC1_COUNT8_CC1 (0x42002419) /**< \brief (TC1) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC1_CTRLA (*(RwReg16*)0x42002400UL) /**< \brief (TC1) Control A */ 57 | #define REG_TC1_READREQ (*(RwReg16*)0x42002402UL) /**< \brief (TC1) Read Request */ 58 | #define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TC1) Control B Clear */ 59 | #define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TC1) Control B Set */ 60 | #define REG_TC1_CTRLC (*(RwReg8 *)0x42002406UL) /**< \brief (TC1) Control C */ 61 | #define REG_TC1_DBGCTRL (*(RwReg8 *)0x42002408UL) /**< \brief (TC1) Debug Control */ 62 | #define REG_TC1_EVCTRL (*(RwReg16*)0x4200240AUL) /**< \brief (TC1) Event Control */ 63 | #define REG_TC1_INTENCLR (*(RwReg8 *)0x4200240CUL) /**< \brief (TC1) Interrupt Enable Clear */ 64 | #define REG_TC1_INTENSET (*(RwReg8 *)0x4200240DUL) /**< \brief (TC1) Interrupt Enable Set */ 65 | #define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240EUL) /**< \brief (TC1) Interrupt Flag Status and Clear */ 66 | #define REG_TC1_STATUS (*(RoReg8 *)0x4200240FUL) /**< \brief (TC1) Status */ 67 | #define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002410UL) /**< \brief (TC1) COUNT16 Counter Value */ 68 | #define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x42002418UL) /**< \brief (TC1) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241AUL) /**< \brief (TC1) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002410UL) /**< \brief (TC1) COUNT32 Counter Value */ 71 | #define REG_TC1_COUNT32_CC0 (*(RwReg *)0x42002418UL) /**< \brief (TC1) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC1_COUNT32_CC1 (*(RwReg *)0x4200241CUL) /**< \brief (TC1) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002410UL) /**< \brief (TC1) COUNT8 Counter Value */ 74 | #define REG_TC1_COUNT8_PER (*(RwReg8 *)0x42002414UL) /**< \brief (TC1) COUNT8 Period Value */ 75 | #define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x42002418UL) /**< \brief (TC1) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x42002419UL) /**< \brief (TC1) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC1 peripheral ========== */ 80 | #define TC1_CC8_NUM 2 81 | #define TC1_CC16_NUM 2 82 | #define TC1_CC32_NUM 2 83 | #define TC1_DITHERING_EXT 0 84 | #define TC1_GCLK_ID 19 85 | #define TC1_MASTER 0 86 | #define TC1_OW_NUM 2 87 | #define TC1_PERIOD_EXT 0 88 | #define TC1_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC1_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc2.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC2 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC2_INSTANCE_ 30 | #define _SAMD20_TC2_INSTANCE_ 31 | 32 | /* ========== Register definition for TC2 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC2_CTRLA (0x42002800) /**< \brief (TC2) Control A */ 35 | #define REG_TC2_READREQ (0x42002802) /**< \brief (TC2) Read Request */ 36 | #define REG_TC2_CTRLBCLR (0x42002804) /**< \brief (TC2) Control B Clear */ 37 | #define REG_TC2_CTRLBSET (0x42002805) /**< \brief (TC2) Control B Set */ 38 | #define REG_TC2_CTRLC (0x42002806) /**< \brief (TC2) Control C */ 39 | #define REG_TC2_DBGCTRL (0x42002808) /**< \brief (TC2) Debug Control */ 40 | #define REG_TC2_EVCTRL (0x4200280A) /**< \brief (TC2) Event Control */ 41 | #define REG_TC2_INTENCLR (0x4200280C) /**< \brief (TC2) Interrupt Enable Clear */ 42 | #define REG_TC2_INTENSET (0x4200280D) /**< \brief (TC2) Interrupt Enable Set */ 43 | #define REG_TC2_INTFLAG (0x4200280E) /**< \brief (TC2) Interrupt Flag Status and Clear */ 44 | #define REG_TC2_STATUS (0x4200280F) /**< \brief (TC2) Status */ 45 | #define REG_TC2_COUNT16_COUNT (0x42002810) /**< \brief (TC2) COUNT16 Counter Value */ 46 | #define REG_TC2_COUNT16_CC0 (0x42002818) /**< \brief (TC2) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC2_COUNT16_CC1 (0x4200281A) /**< \brief (TC2) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC2_COUNT32_COUNT (0x42002810) /**< \brief (TC2) COUNT32 Counter Value */ 49 | #define REG_TC2_COUNT32_CC0 (0x42002818) /**< \brief (TC2) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC2_COUNT32_CC1 (0x4200281C) /**< \brief (TC2) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC2_COUNT8_COUNT (0x42002810) /**< \brief (TC2) COUNT8 Counter Value */ 52 | #define REG_TC2_COUNT8_PER (0x42002814) /**< \brief (TC2) COUNT8 Period Value */ 53 | #define REG_TC2_COUNT8_CC0 (0x42002818) /**< \brief (TC2) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC2_COUNT8_CC1 (0x42002819) /**< \brief (TC2) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC2_CTRLA (*(RwReg16*)0x42002800UL) /**< \brief (TC2) Control A */ 57 | #define REG_TC2_READREQ (*(RwReg16*)0x42002802UL) /**< \brief (TC2) Read Request */ 58 | #define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TC2) Control B Clear */ 59 | #define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TC2) Control B Set */ 60 | #define REG_TC2_CTRLC (*(RwReg8 *)0x42002806UL) /**< \brief (TC2) Control C */ 61 | #define REG_TC2_DBGCTRL (*(RwReg8 *)0x42002808UL) /**< \brief (TC2) Debug Control */ 62 | #define REG_TC2_EVCTRL (*(RwReg16*)0x4200280AUL) /**< \brief (TC2) Event Control */ 63 | #define REG_TC2_INTENCLR (*(RwReg8 *)0x4200280CUL) /**< \brief (TC2) Interrupt Enable Clear */ 64 | #define REG_TC2_INTENSET (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Interrupt Enable Set */ 65 | #define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280EUL) /**< \brief (TC2) Interrupt Flag Status and Clear */ 66 | #define REG_TC2_STATUS (*(RoReg8 *)0x4200280FUL) /**< \brief (TC2) Status */ 67 | #define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002810UL) /**< \brief (TC2) COUNT16 Counter Value */ 68 | #define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x42002818UL) /**< \brief (TC2) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281AUL) /**< \brief (TC2) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002810UL) /**< \brief (TC2) COUNT32 Counter Value */ 71 | #define REG_TC2_COUNT32_CC0 (*(RwReg *)0x42002818UL) /**< \brief (TC2) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC2_COUNT32_CC1 (*(RwReg *)0x4200281CUL) /**< \brief (TC2) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002810UL) /**< \brief (TC2) COUNT8 Counter Value */ 74 | #define REG_TC2_COUNT8_PER (*(RwReg8 *)0x42002814UL) /**< \brief (TC2) COUNT8 Period Value */ 75 | #define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x42002818UL) /**< \brief (TC2) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x42002819UL) /**< \brief (TC2) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC2 peripheral ========== */ 80 | #define TC2_CC8_NUM 2 81 | #define TC2_CC16_NUM 2 82 | #define TC2_CC32_NUM 2 83 | #define TC2_DITHERING_EXT 0 84 | #define TC2_GCLK_ID 20 85 | #define TC2_MASTER 1 86 | #define TC2_OW_NUM 2 87 | #define TC2_PERIOD_EXT 0 88 | #define TC2_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC2_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc3.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC3 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC3_INSTANCE_ 30 | #define _SAMD20_TC3_INSTANCE_ 31 | 32 | /* ========== Register definition for TC3 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */ 35 | #define REG_TC3_READREQ (0x42002C02) /**< \brief (TC3) Read Request */ 36 | #define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */ 37 | #define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */ 38 | #define REG_TC3_CTRLC (0x42002C06) /**< \brief (TC3) Control C */ 39 | #define REG_TC3_DBGCTRL (0x42002C08) /**< \brief (TC3) Debug Control */ 40 | #define REG_TC3_EVCTRL (0x42002C0A) /**< \brief (TC3) Event Control */ 41 | #define REG_TC3_INTENCLR (0x42002C0C) /**< \brief (TC3) Interrupt Enable Clear */ 42 | #define REG_TC3_INTENSET (0x42002C0D) /**< \brief (TC3) Interrupt Enable Set */ 43 | #define REG_TC3_INTFLAG (0x42002C0E) /**< \brief (TC3) Interrupt Flag Status and Clear */ 44 | #define REG_TC3_STATUS (0x42002C0F) /**< \brief (TC3) Status */ 45 | #define REG_TC3_COUNT16_COUNT (0x42002C10) /**< \brief (TC3) COUNT16 Counter Value */ 46 | #define REG_TC3_COUNT16_CC0 (0x42002C18) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC3_COUNT16_CC1 (0x42002C1A) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC3_COUNT32_COUNT (0x42002C10) /**< \brief (TC3) COUNT32 Counter Value */ 49 | #define REG_TC3_COUNT32_CC0 (0x42002C18) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC3_COUNT32_CC1 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC3_COUNT8_COUNT (0x42002C10) /**< \brief (TC3) COUNT8 Counter Value */ 52 | #define REG_TC3_COUNT8_PER (0x42002C14) /**< \brief (TC3) COUNT8 Period Value */ 53 | #define REG_TC3_COUNT8_CC0 (0x42002C18) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC3_COUNT8_CC1 (0x42002C19) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC3_CTRLA (*(RwReg16*)0x42002C00UL) /**< \brief (TC3) Control A */ 57 | #define REG_TC3_READREQ (*(RwReg16*)0x42002C02UL) /**< \brief (TC3) Read Request */ 58 | #define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */ 59 | #define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */ 60 | #define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06UL) /**< \brief (TC3) Control C */ 61 | #define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Debug Control */ 62 | #define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AUL) /**< \brief (TC3) Event Control */ 63 | #define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Interrupt Enable Clear */ 64 | #define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Interrupt Enable Set */ 65 | #define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ 66 | #define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FUL) /**< \brief (TC3) Status */ 67 | #define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10UL) /**< \brief (TC3) COUNT16 Counter Value */ 68 | #define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18UL) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AUL) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10UL) /**< \brief (TC3) COUNT32 Counter Value */ 71 | #define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18UL) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10UL) /**< \brief (TC3) COUNT8 Counter Value */ 74 | #define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Period Value */ 75 | #define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18UL) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19UL) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC3 peripheral ========== */ 80 | #define TC3_CC8_NUM 2 81 | #define TC3_CC16_NUM 2 82 | #define TC3_CC32_NUM 2 83 | #define TC3_DITHERING_EXT 0 84 | #define TC3_GCLK_ID 20 85 | #define TC3_MASTER 0 86 | #define TC3_OW_NUM 2 87 | #define TC3_PERIOD_EXT 0 88 | #define TC3_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC3_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc4.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC4 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC4_INSTANCE_ 30 | #define _SAMD20_TC4_INSTANCE_ 31 | 32 | /* ========== Register definition for TC4 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC4_CTRLA (0x42003000) /**< \brief (TC4) Control A */ 35 | #define REG_TC4_READREQ (0x42003002) /**< \brief (TC4) Read Request */ 36 | #define REG_TC4_CTRLBCLR (0x42003004) /**< \brief (TC4) Control B Clear */ 37 | #define REG_TC4_CTRLBSET (0x42003005) /**< \brief (TC4) Control B Set */ 38 | #define REG_TC4_CTRLC (0x42003006) /**< \brief (TC4) Control C */ 39 | #define REG_TC4_DBGCTRL (0x42003008) /**< \brief (TC4) Debug Control */ 40 | #define REG_TC4_EVCTRL (0x4200300A) /**< \brief (TC4) Event Control */ 41 | #define REG_TC4_INTENCLR (0x4200300C) /**< \brief (TC4) Interrupt Enable Clear */ 42 | #define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */ 43 | #define REG_TC4_INTFLAG (0x4200300E) /**< \brief (TC4) Interrupt Flag Status and Clear */ 44 | #define REG_TC4_STATUS (0x4200300F) /**< \brief (TC4) Status */ 45 | #define REG_TC4_COUNT16_COUNT (0x42003010) /**< \brief (TC4) COUNT16 Counter Value */ 46 | #define REG_TC4_COUNT16_CC0 (0x42003018) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC4_COUNT16_CC1 (0x4200301A) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC4_COUNT32_COUNT (0x42003010) /**< \brief (TC4) COUNT32 Counter Value */ 49 | #define REG_TC4_COUNT32_CC0 (0x42003018) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC4_COUNT32_CC1 (0x4200301C) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC4_COUNT8_COUNT (0x42003010) /**< \brief (TC4) COUNT8 Counter Value */ 52 | #define REG_TC4_COUNT8_PER (0x42003014) /**< \brief (TC4) COUNT8 Period Value */ 53 | #define REG_TC4_COUNT8_CC0 (0x42003018) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC4_COUNT8_CC1 (0x42003019) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC4_CTRLA (*(RwReg16*)0x42003000UL) /**< \brief (TC4) Control A */ 57 | #define REG_TC4_READREQ (*(RwReg16*)0x42003002UL) /**< \brief (TC4) Read Request */ 58 | #define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004UL) /**< \brief (TC4) Control B Clear */ 59 | #define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005UL) /**< \brief (TC4) Control B Set */ 60 | #define REG_TC4_CTRLC (*(RwReg8 *)0x42003006UL) /**< \brief (TC4) Control C */ 61 | #define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008UL) /**< \brief (TC4) Debug Control */ 62 | #define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AUL) /**< \brief (TC4) Event Control */ 63 | #define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CUL) /**< \brief (TC4) Interrupt Enable Clear */ 64 | #define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set */ 65 | #define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EUL) /**< \brief (TC4) Interrupt Flag Status and Clear */ 66 | #define REG_TC4_STATUS (*(RoReg8 *)0x4200300FUL) /**< \brief (TC4) Status */ 67 | #define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010UL) /**< \brief (TC4) COUNT16 Counter Value */ 68 | #define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018UL) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AUL) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010UL) /**< \brief (TC4) COUNT32 Counter Value */ 71 | #define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018UL) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CUL) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010UL) /**< \brief (TC4) COUNT8 Counter Value */ 74 | #define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014UL) /**< \brief (TC4) COUNT8 Period Value */ 75 | #define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018UL) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019UL) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC4 peripheral ========== */ 80 | #define TC4_CC8_NUM 2 81 | #define TC4_CC16_NUM 2 82 | #define TC4_CC32_NUM 2 83 | #define TC4_DITHERING_EXT 0 84 | #define TC4_GCLK_ID 21 85 | #define TC4_MASTER 1 86 | #define TC4_OW_NUM 2 87 | #define TC4_PERIOD_EXT 0 88 | #define TC4_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC4_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc5.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC5 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC5_INSTANCE_ 30 | #define _SAMD20_TC5_INSTANCE_ 31 | 32 | /* ========== Register definition for TC5 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC5_CTRLA (0x42003400) /**< \brief (TC5) Control A */ 35 | #define REG_TC5_READREQ (0x42003402) /**< \brief (TC5) Read Request */ 36 | #define REG_TC5_CTRLBCLR (0x42003404) /**< \brief (TC5) Control B Clear */ 37 | #define REG_TC5_CTRLBSET (0x42003405) /**< \brief (TC5) Control B Set */ 38 | #define REG_TC5_CTRLC (0x42003406) /**< \brief (TC5) Control C */ 39 | #define REG_TC5_DBGCTRL (0x42003408) /**< \brief (TC5) Debug Control */ 40 | #define REG_TC5_EVCTRL (0x4200340A) /**< \brief (TC5) Event Control */ 41 | #define REG_TC5_INTENCLR (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */ 42 | #define REG_TC5_INTENSET (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */ 43 | #define REG_TC5_INTFLAG (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */ 44 | #define REG_TC5_STATUS (0x4200340F) /**< \brief (TC5) Status */ 45 | #define REG_TC5_COUNT16_COUNT (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */ 46 | #define REG_TC5_COUNT16_CC0 (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC5_COUNT16_CC1 (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC5_COUNT32_COUNT (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */ 49 | #define REG_TC5_COUNT32_CC0 (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC5_COUNT32_CC1 (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC5_COUNT8_COUNT (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */ 52 | #define REG_TC5_COUNT8_PER (0x42003414) /**< \brief (TC5) COUNT8 Period Value */ 53 | #define REG_TC5_COUNT8_CC0 (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC5_COUNT8_CC1 (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC5_CTRLA (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */ 57 | #define REG_TC5_READREQ (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */ 58 | #define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */ 59 | #define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */ 60 | #define REG_TC5_CTRLC (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */ 61 | #define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */ 62 | #define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */ 63 | #define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */ 64 | #define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */ 65 | #define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */ 66 | #define REG_TC5_STATUS (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */ 67 | #define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */ 68 | #define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */ 71 | #define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */ 74 | #define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */ 75 | #define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC5 peripheral ========== */ 80 | #define TC5_CC8_NUM 2 81 | #define TC5_CC16_NUM 2 82 | #define TC5_CC32_NUM 2 83 | #define TC5_DITHERING_EXT 0 84 | #define TC5_GCLK_ID 21 85 | #define TC5_MASTER 0 86 | #define TC5_OW_NUM 2 87 | #define TC5_PERIOD_EXT 0 88 | #define TC5_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC5_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc6.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC6 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC6_INSTANCE_ 30 | #define _SAMD20_TC6_INSTANCE_ 31 | 32 | /* ========== Register definition for TC6 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC6_CTRLA (0x42003800) /**< \brief (TC6) Control A */ 35 | #define REG_TC6_READREQ (0x42003802) /**< \brief (TC6) Read Request */ 36 | #define REG_TC6_CTRLBCLR (0x42003804) /**< \brief (TC6) Control B Clear */ 37 | #define REG_TC6_CTRLBSET (0x42003805) /**< \brief (TC6) Control B Set */ 38 | #define REG_TC6_CTRLC (0x42003806) /**< \brief (TC6) Control C */ 39 | #define REG_TC6_DBGCTRL (0x42003808) /**< \brief (TC6) Debug Control */ 40 | #define REG_TC6_EVCTRL (0x4200380A) /**< \brief (TC6) Event Control */ 41 | #define REG_TC6_INTENCLR (0x4200380C) /**< \brief (TC6) Interrupt Enable Clear */ 42 | #define REG_TC6_INTENSET (0x4200380D) /**< \brief (TC6) Interrupt Enable Set */ 43 | #define REG_TC6_INTFLAG (0x4200380E) /**< \brief (TC6) Interrupt Flag Status and Clear */ 44 | #define REG_TC6_STATUS (0x4200380F) /**< \brief (TC6) Status */ 45 | #define REG_TC6_COUNT16_COUNT (0x42003810) /**< \brief (TC6) COUNT16 Counter Value */ 46 | #define REG_TC6_COUNT16_CC0 (0x42003818) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC6_COUNT16_CC1 (0x4200381A) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC6_COUNT32_COUNT (0x42003810) /**< \brief (TC6) COUNT32 Counter Value */ 49 | #define REG_TC6_COUNT32_CC0 (0x42003818) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC6_COUNT32_CC1 (0x4200381C) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC6_COUNT8_COUNT (0x42003810) /**< \brief (TC6) COUNT8 Counter Value */ 52 | #define REG_TC6_COUNT8_PER (0x42003814) /**< \brief (TC6) COUNT8 Period Value */ 53 | #define REG_TC6_COUNT8_CC0 (0x42003818) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC6_COUNT8_CC1 (0x42003819) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC6_CTRLA (*(RwReg16*)0x42003800UL) /**< \brief (TC6) Control A */ 57 | #define REG_TC6_READREQ (*(RwReg16*)0x42003802UL) /**< \brief (TC6) Read Request */ 58 | #define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC6) Control B Clear */ 59 | #define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC6) Control B Set */ 60 | #define REG_TC6_CTRLC (*(RwReg8 *)0x42003806UL) /**< \brief (TC6) Control C */ 61 | #define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808UL) /**< \brief (TC6) Debug Control */ 62 | #define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AUL) /**< \brief (TC6) Event Control */ 63 | #define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CUL) /**< \brief (TC6) Interrupt Enable Clear */ 64 | #define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DUL) /**< \brief (TC6) Interrupt Enable Set */ 65 | #define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EUL) /**< \brief (TC6) Interrupt Flag Status and Clear */ 66 | #define REG_TC6_STATUS (*(RoReg8 *)0x4200380FUL) /**< \brief (TC6) Status */ 67 | #define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810UL) /**< \brief (TC6) COUNT16 Counter Value */ 68 | #define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818UL) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AUL) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810UL) /**< \brief (TC6) COUNT32 Counter Value */ 71 | #define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818UL) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CUL) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810UL) /**< \brief (TC6) COUNT8 Counter Value */ 74 | #define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814UL) /**< \brief (TC6) COUNT8 Period Value */ 75 | #define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818UL) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819UL) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC6 peripheral ========== */ 80 | #define TC6_CC8_NUM 2 81 | #define TC6_CC16_NUM 2 82 | #define TC6_CC32_NUM 2 83 | #define TC6_DITHERING_EXT 0 84 | #define TC6_GCLK_ID 22 85 | #define TC6_MASTER 1 86 | #define TC6_OW_NUM 2 87 | #define TC6_PERIOD_EXT 0 88 | #define TC6_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC6_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/tc7.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for TC7 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_TC7_INSTANCE_ 30 | #define _SAMD20_TC7_INSTANCE_ 31 | 32 | /* ========== Register definition for TC7 peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_TC7_CTRLA (0x42003C00) /**< \brief (TC7) Control A */ 35 | #define REG_TC7_READREQ (0x42003C02) /**< \brief (TC7) Read Request */ 36 | #define REG_TC7_CTRLBCLR (0x42003C04) /**< \brief (TC7) Control B Clear */ 37 | #define REG_TC7_CTRLBSET (0x42003C05) /**< \brief (TC7) Control B Set */ 38 | #define REG_TC7_CTRLC (0x42003C06) /**< \brief (TC7) Control C */ 39 | #define REG_TC7_DBGCTRL (0x42003C08) /**< \brief (TC7) Debug Control */ 40 | #define REG_TC7_EVCTRL (0x42003C0A) /**< \brief (TC7) Event Control */ 41 | #define REG_TC7_INTENCLR (0x42003C0C) /**< \brief (TC7) Interrupt Enable Clear */ 42 | #define REG_TC7_INTENSET (0x42003C0D) /**< \brief (TC7) Interrupt Enable Set */ 43 | #define REG_TC7_INTFLAG (0x42003C0E) /**< \brief (TC7) Interrupt Flag Status and Clear */ 44 | #define REG_TC7_STATUS (0x42003C0F) /**< \brief (TC7) Status */ 45 | #define REG_TC7_COUNT16_COUNT (0x42003C10) /**< \brief (TC7) COUNT16 Counter Value */ 46 | #define REG_TC7_COUNT16_CC0 (0x42003C18) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ 47 | #define REG_TC7_COUNT16_CC1 (0x42003C1A) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ 48 | #define REG_TC7_COUNT32_COUNT (0x42003C10) /**< \brief (TC7) COUNT32 Counter Value */ 49 | #define REG_TC7_COUNT32_CC0 (0x42003C18) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ 50 | #define REG_TC7_COUNT32_CC1 (0x42003C1C) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ 51 | #define REG_TC7_COUNT8_COUNT (0x42003C10) /**< \brief (TC7) COUNT8 Counter Value */ 52 | #define REG_TC7_COUNT8_PER (0x42003C14) /**< \brief (TC7) COUNT8 Period Value */ 53 | #define REG_TC7_COUNT8_CC0 (0x42003C18) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ 54 | #define REG_TC7_COUNT8_CC1 (0x42003C19) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ 55 | #else 56 | #define REG_TC7_CTRLA (*(RwReg16*)0x42003C00UL) /**< \brief (TC7) Control A */ 57 | #define REG_TC7_READREQ (*(RwReg16*)0x42003C02UL) /**< \brief (TC7) Read Request */ 58 | #define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04UL) /**< \brief (TC7) Control B Clear */ 59 | #define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05UL) /**< \brief (TC7) Control B Set */ 60 | #define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06UL) /**< \brief (TC7) Control C */ 61 | #define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08UL) /**< \brief (TC7) Debug Control */ 62 | #define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AUL) /**< \brief (TC7) Event Control */ 63 | #define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC7) Interrupt Enable Clear */ 64 | #define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC7) Interrupt Enable Set */ 65 | #define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EUL) /**< \brief (TC7) Interrupt Flag Status and Clear */ 66 | #define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FUL) /**< \brief (TC7) Status */ 67 | #define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10UL) /**< \brief (TC7) COUNT16 Counter Value */ 68 | #define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18UL) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ 69 | #define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AUL) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ 70 | #define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10UL) /**< \brief (TC7) COUNT32 Counter Value */ 71 | #define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18UL) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ 72 | #define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CUL) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ 73 | #define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10UL) /**< \brief (TC7) COUNT8 Counter Value */ 74 | #define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14UL) /**< \brief (TC7) COUNT8 Period Value */ 75 | #define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ 76 | #define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ 77 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 | 79 | /* ========== Instance parameters for TC7 peripheral ========== */ 80 | #define TC7_CC8_NUM 2 81 | #define TC7_CC16_NUM 2 82 | #define TC7_CC32_NUM 2 83 | #define TC7_DITHERING_EXT 0 84 | #define TC7_GCLK_ID 22 85 | #define TC7_MASTER 0 86 | #define TC7_OW_NUM 2 87 | #define TC7_PERIOD_EXT 0 88 | #define TC7_SHADOW_EXT 0 89 | 90 | #endif /* _SAMD20_TC7_INSTANCE_ */ 91 | -------------------------------------------------------------------------------- /bench-cm0/sysinc/instance/wdt.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for WDT 5 | * 6 | * Copyright (c) 2016 Atmel Corporation, 7 | * a wholly owned subsidiary of Microchip Technology Inc. 8 | * 9 | * \asf_license_start 10 | * 11 | * \page License 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the "License"); 14 | * you may not use this file except in compliance with the License. 15 | * You may obtain a copy of the Licence at 16 | * 17 | * http://www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | * \asf_license_stop 26 | * 27 | */ 28 | 29 | #ifndef _SAMD20_WDT_INSTANCE_ 30 | #define _SAMD20_WDT_INSTANCE_ 31 | 32 | /* ========== Register definition for WDT peripheral ========== */ 33 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 | #define REG_WDT_CTRL (0x40001000) /**< \brief (WDT) Control */ 35 | #define REG_WDT_CONFIG (0x40001001) /**< \brief (WDT) Configuration */ 36 | #define REG_WDT_EWCTRL (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */ 37 | #define REG_WDT_INTENCLR (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */ 38 | #define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ 39 | #define REG_WDT_INTFLAG (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */ 40 | #define REG_WDT_STATUS (0x40001007) /**< \brief (WDT) Status */ 41 | #define REG_WDT_CLEAR (0x40001008) /**< \brief (WDT) Clear */ 42 | #else 43 | #define REG_WDT_CTRL (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */ 44 | #define REG_WDT_CONFIG (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */ 45 | #define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */ 46 | #define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */ 47 | #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */ 48 | #define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ 49 | #define REG_WDT_STATUS (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */ 50 | #define REG_WDT_CLEAR (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */ 51 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 | 53 | /* ========== Instance parameters for WDT peripheral ========== */ 54 | #define WDT_GCLK_ID 1 // Index of Generic Clock 55 | 56 | #endif /* _SAMD20_WDT_INSTANCE_ */ 57 | -------------------------------------------------------------------------------- /bench-cm4/Makefile: -------------------------------------------------------------------------------- 1 | CC = arm-none-eabi-gcc 2 | CFLAGS = -Wall -Wextra -std=c99 -ggdb3 -Os $(ARCHFLAGS) -fno-common -ffunction-sections -fdata-sections -I $(INCDIR) -DSTM32F4 3 | LD = arm-none-eabi-gcc 4 | LDFLAGS = -L$(LIBDIR) --static -nostartfiles -T$(LDSCRIPT) -ggdb3 $(ARCHFLAGS) -Wl,--gc-sections 5 | LDLIBS = -lopencm3_stm32f4 -Wl,--start-group -lc -lgcc -lm -lnosys -Wl,--end-group 6 | ARCHFLAGS = -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 7 | 8 | INCDIR = ../libopencm3/include 9 | LIBDIR = ../libopencm3/lib 10 | LDSCRIPT = stm32f4-discovery.ld 11 | 12 | OBJ = curve9767.o ecdh.o hash.o keygen.o ops_arm.o scalar_arm.o scalar_cm4.o ops_cm4.o sha3_cm4.o sign.o timing.o 13 | 14 | all: timing.elf 15 | 16 | timing.elf: $(OBJ) 17 | $(LD) $(LDFLAGS) -o timing.elf $(OBJ) $(LDLIBS) 18 | 19 | clean: 20 | -rm -f timing.elf $(OBJ) 21 | 22 | timing.o: timing.c curve9767.h inner.h sha3.h 23 | $(CC) $(CFLAGS) -c -o timing.o timing.c 24 | 25 | curve9767.o: curve9767.c curve9767.h inner.h sha3.h 26 | $(CC) $(CFLAGS) -c -o curve9767.o curve9767.c 27 | 28 | ecdh.o: ecdh.c curve9767.h inner.h sha3.h 29 | $(CC) $(CFLAGS) -c -o ecdh.o ecdh.c 30 | 31 | hash.o: hash.c curve9767.h inner.h sha3.h 32 | $(CC) $(CFLAGS) -c -o hash.o hash.c 33 | 34 | keygen.o: keygen.c curve9767.h inner.h sha3.h 35 | $(CC) $(CFLAGS) -c -o keygen.o keygen.c 36 | 37 | ops_arm.o: ops_arm.c curve9767.h inner.h sha3.h 38 | $(CC) $(CFLAGS) -c -o ops_arm.o ops_arm.c 39 | 40 | ops_cm4.o: ops_cm4.s 41 | $(CC) $(CFLAGS) -c -o ops_cm4.o ops_cm4.s 42 | 43 | scalar_arm.o: scalar_arm.c curve9767.h inner.h sha3.h 44 | $(CC) $(CFLAGS) -c -o scalar_arm.o scalar_arm.c 45 | 46 | scalar_cm4.o: scalar_cm4.s 47 | $(CC) $(CFLAGS) -c -o scalar_cm4.o scalar_cm4.s 48 | 49 | sha3_cm4.o: sha3_cm4.c sha3.h 50 | $(CC) $(CFLAGS) -c -o sha3_cm4.o sha3_cm4.c 51 | 52 | sign.o: sign.c curve9767.h inner.h sha3.h 53 | $(CC) $(CFLAGS) -c -o sign.o sign.c 54 | -------------------------------------------------------------------------------- /bench-cm4/curve9767.c: -------------------------------------------------------------------------------- 1 | ../src/curve9767.c -------------------------------------------------------------------------------- /bench-cm4/curve9767.h: -------------------------------------------------------------------------------- 1 | ../src/curve9767.h -------------------------------------------------------------------------------- /bench-cm4/ecdh.c: -------------------------------------------------------------------------------- 1 | ../src/ecdh.c -------------------------------------------------------------------------------- /bench-cm4/hash.c: -------------------------------------------------------------------------------- 1 | ../src/hash.c -------------------------------------------------------------------------------- /bench-cm4/inner.h: -------------------------------------------------------------------------------- 1 | ../src/inner.h -------------------------------------------------------------------------------- /bench-cm4/keygen.c: -------------------------------------------------------------------------------- 1 | ../src/keygen.c -------------------------------------------------------------------------------- /bench-cm4/ops_arm.c: -------------------------------------------------------------------------------- 1 | ../src/ops_arm.c -------------------------------------------------------------------------------- /bench-cm4/ops_cm4.s: -------------------------------------------------------------------------------- 1 | ../src/ops_cm4.s -------------------------------------------------------------------------------- /bench-cm4/scalar_arm.c: -------------------------------------------------------------------------------- 1 | ../src/scalar_arm.c -------------------------------------------------------------------------------- /bench-cm4/scalar_cm4.s: -------------------------------------------------------------------------------- 1 | ../src/scalar_cm4.s -------------------------------------------------------------------------------- /bench-cm4/sha3.h: -------------------------------------------------------------------------------- 1 | ../src/sha3.h -------------------------------------------------------------------------------- /bench-cm4/sha3_cm4.c: -------------------------------------------------------------------------------- 1 | ../src/sha3_cm4.c -------------------------------------------------------------------------------- /bench-cm4/sign.c: -------------------------------------------------------------------------------- 1 | ../src/sign.c -------------------------------------------------------------------------------- /bench-cm4/stm32f4-discovery.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the libopencm3 project. 3 | * 4 | * Copyright (C) 2009 Uwe Hermann 5 | * Copyright (C) 2011 Stephen Caudle 6 | * 7 | * This library is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU Lesser General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This library is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU Lesser General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU Lesser General Public License 18 | * along with this library. If not, see . 19 | */ 20 | 21 | /* Linker script for ST STM32F4DISCOVERY (STM32F407G-DISC1, 1024K flash, 192K RAM). */ 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K 27 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K 28 | 29 | /* 30 | * The CCM is an extra 64 kB block at 0x10000000, accessible only 31 | * by the CPU, not by peripherals. 32 | */ 33 | } 34 | 35 | /* Include the common ld script. */ 36 | INCLUDE ../libopencm3/lib/cortex-m-generic.ld 37 | -------------------------------------------------------------------------------- /doc/curve9767.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pornin/curve9767/58f46524005ad09bc706c2443b37d41284a0ea09/doc/curve9767.pdf -------------------------------------------------------------------------------- /extra/findcurve.gp: -------------------------------------------------------------------------------- 1 | /* 2 | * Enumerate all curves y^2 = x^3-3*x+B in GF(9767^19) with prime order, 3 | * and B having minimal Hamming weight. 4 | * 5 | * This script runs with pari-gp 2.11.2, with the seadata-small.tgz 6 | * package installed (for efficient curve point counting with SEA). 7 | * See: 8 | * https://pari.math.u-bordeaux.fr/ 9 | * https://pari.math.u-bordeaux.fr/packages.html 10 | * 11 | * 12 | * Let p = 9767 and q = 9767^19. Note that p is prime and p = 1 mod 19. 13 | * We define the finite field GF(q) by taking GF(p)[z] (univariate 14 | * polynomials with coefficients in GF(p)) modulo the irreducible 15 | * polynomial z^19-2. We want to search for all elliptic curves of 16 | * equation y^2 = x^3 - 3*x + B, such that B = b*z^i for some b in GF(p) 17 | * and 0 <= i <= 18. We want curves with prime order. 18 | * 19 | * If i = 0, then the curve is also defined over GF(p) with an order close 20 | * to p, which will divide the order of the curve over GF(q); thus, this 21 | * cannot yield a curve with prime order. We therefore require 1 <= i <= 18. 22 | * 23 | * The Frobenius operator phi(x) = x^p is an automorphism over GF(q); that 24 | * is, phi(x+y) = phi(x) + phi(y) and phi(x*y) = phi(x) * phi(y) for all 25 | * x and y in GF(q). Moreover, with our field definition with the modulus 26 | * z^19-2, we have, for all c in GF(p) and 0 <= i <= 18: 27 | * phi(c*z^i) = (2^(i*(p-1)/19))*c*z^i 28 | * Note that 2^(i*(p-1)/19) is one of the 19th roots of 1 in GF(p). 29 | * 30 | * Applying phi() on the curve equation, we obtain an isomorphism from curve: 31 | * y^2 = x^3 - 3*x + b*z^i 32 | * to curve: 33 | * y^2 = x^3 - 3*x + (2^(i*(p-1)/19))*b*z^i 34 | * We get further isomorphic curves by repeatedly applying phi; since 35 | * phi^19(x) = x, this yields a set of 19 isomorphic curves. 36 | * 37 | * This means that we can test for only one curve among the 19th; the other 38 | * 18 curves have exactly the same order. Whenever we consider a value B, 39 | * we check whether there is a B*w which is smaller, for some w which is 40 | * a 19th root of 1 in GF(p); if one of the B*w is smaller, then that B 41 | * is skipped. 42 | * 43 | * 44 | * This script takes about 1 hour and 40 minutes to fully run on a 45 | * machine with an Intel Xeon E3-1220 V2 at 3.10 GHz, with 8 GM of RAM, 46 | * running Linux in 64-bit mode. It finds 23 curves (23 sets of 19 47 | * curves, taking into account the Frobenius automorphism) with a prime 48 | * order, two of which being twist of each other. 49 | * 50 | * The 23 curves are for the following values of B: 51 | * 52 | * 450*z^2 603*z^2 665*z^5 751*z^5 287*z^6 100*z^8 359*z^8 53 | * 303*z^9 359*z^9 519*z^9 2048*z^9 34*z^10 380*z^10 53*z^12 54 | * 287*z^12 776*z^13 1751*z^13 458*z^14 489*z^14 1088*z^15 411*z^16 55 | * 1152*z^16 129*z^18 56 | * 57 | * The two curves for B = 359*z^9 and B = 2048*z^9 are quadratic twists of 58 | * each other. Their respective orders are: 59 | * 60 | * 359*z^9 -> 6389436622109970582043832278503799542456269640437724557045939388995057075711 61 | * 2048*z^9 -> 6389436622109970582043832278503799542449455630003248488928817956373993578097 62 | */ 63 | 64 | /* We need some extra RAM for curve point counting. */ 65 | default(parisizemax, 100000000) 66 | 67 | /* Finite field definitions. */ 68 | p = 9767 69 | q = p^19 70 | z = ffgen(x^19-Mod(2, p), 'z) 71 | 72 | /* 19-th roots of unity in GF(p). */ 73 | rr = polrootsmod(x^19-1, p) 74 | 75 | /* Check whether a base field element c is "minimal" in the set of 76 | values c*w for all 19th roots of 1 in GF(p). Minimality is expressed 77 | with the cmp() function. */ 78 | isminimal19(b) = 79 | { 80 | for (i = 1, 19, 81 | if (cmp(rr[i] * b, b) < 0, 82 | return(0))); 83 | return(1); 84 | } 85 | 86 | /* Test whether the curve y^2 = x^3 - 3*x + B has prime order. If the 87 | order is prime, then it is returned; otherwise, 0 is returned. */ 88 | testcurve(B) = 89 | { 90 | /* If x^3 - 3*x + B is not irreducible, then there is at least 91 | one point with y = 0, which then has order 2, and the curve 92 | order is even (hence not prime). */ 93 | if (!polisirreducible(x^3-3*x+B), 94 | return(0)); 95 | 96 | /* Count points with SEA. The ellsea() function will usually abort 97 | early and return 0 if the order is not prime. */ 98 | my(E = ellinit([-3, B])); 99 | my(n = ellsea(E, 1)); 100 | if (!isprime(n), return(0)); 101 | return(n); 102 | } 103 | 104 | /* Enumerate all curves y^2 = x^3 - 3*x + b*z^i, and check which one is 105 | prime. */ 106 | findcurves() = 107 | { 108 | for (i = 1, 18, 109 | print("Trying b*z^", i); 110 | for (c = 1, p - 1, 111 | /* Skip values which are non-minimal in the set 112 | of c*w for w a 19th-root of 1. */ 113 | my(b = Mod(c, p)); 114 | if (!isminimal19(b), next); 115 | 116 | /* Try B. */ 117 | my(B = b*z^i); 118 | my(n = testcurve(B)); 119 | if (!n, next); 120 | print("PRIME: ", B, " -> ", n); 121 | 122 | /* If the twisted curve also has prime order, 123 | report it (it will appear in the list as well). */ 124 | my(nt = 2*(q+1) - n); 125 | if (isprime(nt), 126 | print("TWIST OK: ", -B, " -> ", nt)))); 127 | } 128 | 129 | findcurves() 130 | quit 131 | -------------------------------------------------------------------------------- /extra/findprime.sage: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env sage 2 | 3 | import sys 4 | import hashlib 5 | from sage.all import * 6 | 7 | # For degree n (prime) and constant c (2 or more), find the largest prime 8 | # p such that: 9 | # p >= 5 10 | # p >= min_p 11 | # 2 <= c <= p-2 12 | # (1+c*(n-1))*p^2 + (2^16-1)*p < 2^32+2^16 13 | # z^n-c is irreducible over GF(p)[z] 14 | # If there is no solution, then 0 is returned. 15 | def find_best_prime_spec(n, c, min_p): 16 | if min_p == 0: 17 | min_p = 5 18 | if min_p < c + 2: 19 | min_p = c + 2 20 | lim = 2^32 + 2^16 21 | e = 1 + c*(n-1) 22 | max_p = int(sqrt((2^32 + 2^16) / e)) 23 | p = max_p - (max_p % n) + 1 24 | if (p % 2) == 0: 25 | p = p - n 26 | while p >= min_p: 27 | if c >= p-1: 28 | return 0 29 | if (e*p^2 + (2^16 - 1)*p) < (2^32 + 2^16) and is_prime(p): 30 | K = Zmod(p) 31 | R = PolynomialRing(K, 'z') 32 | z = R.gen() 33 | if (z^n - K(c)).is_irreducible(): 34 | return p 35 | p = p - 2*n 36 | return 0 37 | 38 | # Given degree n, find and print the best constant c and prime p that 39 | # fulfills the criteria (see find_best_prime_spec()) and maximize p^n. 40 | def find_best_prime(n): 41 | c = 2 42 | best_c = 0 43 | best_p = 0 44 | best_q = 0 45 | while true: 46 | p = find_best_prime_spec(n, c, best_p) 47 | if p == 0: 48 | if best_p != 0: 49 | print "n=%d -> p=%d c=%d log2(q)=%.3f" % (n, best_p, best_c, (log(best_q)/log(2)).n(60)) 50 | return 51 | q = p^n 52 | if q > best_q: 53 | best_c = c 54 | best_p = p 55 | best_q = q 56 | c = c + 1 57 | 58 | # Try all prime degrees n, starting at 11. We know that there can be no 59 | # solution for n >= 1291. 60 | for n in range(11, 1291): 61 | if is_prime(n): 62 | find_best_prime(n) 63 | -------------------------------------------------------------------------------- /src/Makefile: -------------------------------------------------------------------------------- 1 | CC = clang 2 | CFLAGS = -Wall -Wextra -Wshadow -Wundef -O3 3 | LD = clang 4 | LDFLAGS = 5 | LIBS = 6 | 7 | OBJ = curve9767.o ecdh.o hash.o keygen.o ops_ref.o scalar_ref.o sha3.o sign.o 8 | OBJTEST = test_curve9767.o 9 | OBJSPEED = speed_ref.o 10 | 11 | all: test_curve9767 speed_curve9767 12 | 13 | test_curve9767: $(OBJ) $(OBJTEST) 14 | $(LD) $(LDFLAGS) -o test_curve9767 $(OBJ) $(OBJTEST) $(LIBS) 15 | 16 | speed_curve9767: $(OBJ) $(OBJSPEED) 17 | $(LD) $(LDFLAGS) -o speed_curve9767 $(OBJ) $(OBJSPEED) $(LIBS) 18 | 19 | clean: 20 | -rm -f test_curve9767 speed_curve9767 $(OBJ) $(OBJTEST) $(OBJSPEED) 21 | 22 | curve9767.o: curve9767.c curve9767.h inner.h sha3.h 23 | $(CC) $(CFLAGS) -c -o curve9767.o curve9767.c 24 | 25 | ecdh.o: ecdh.c curve9767.h inner.h sha3.h 26 | $(CC) $(CFLAGS) -c -o ecdh.o ecdh.c 27 | 28 | hash.o: hash.c curve9767.h inner.h sha3.h 29 | $(CC) $(CFLAGS) -c -o hash.o hash.c 30 | 31 | keygen.o: keygen.c curve9767.h inner.h sha3.h 32 | $(CC) $(CFLAGS) -c -o keygen.o keygen.c 33 | 34 | ops_ref.o: ops_ref.c curve9767.h inner.h sha3.h 35 | $(CC) $(CFLAGS) -c -o ops_ref.o ops_ref.c 36 | 37 | scalar_ref.o: scalar_ref.c curve9767.h inner.h sha3.h 38 | $(CC) $(CFLAGS) -c -o scalar_ref.o scalar_ref.c 39 | 40 | sha3.o: sha3.c sha3.h 41 | $(CC) $(CFLAGS) -c -o sha3.o sha3.c 42 | 43 | sign.o: sign.c curve9767.h inner.h sha3.h 44 | $(CC) $(CFLAGS) -c -o sign.o sign.c 45 | 46 | speed_ref.o: speed_ref.c curve9767.h inner.h sha3.h 47 | $(CC) $(CFLAGS) -c -o speed_ref.o speed_ref.c 48 | 49 | test_curve9767.o: test_curve9767.c curve9767.h inner.h sha3.h 50 | $(CC) $(CFLAGS) -c -o test_curve9767.o test_curve9767.c 51 | -------------------------------------------------------------------------------- /src/Makefile.avx2: -------------------------------------------------------------------------------- 1 | CC = clang 2 | CFLAGS = -Wall -Wextra -Wshadow -Wundef -O3 -mavx2 -mlzcnt 3 | LD = clang 4 | LDFLAGS = 5 | LIBS = 6 | 7 | OBJ = curve9767.o ecdh.o hash.o keygen.o ops_avx2.o scalar_amd64.o sha3.o sign.o 8 | OBJTEST = test_curve9767.o 9 | OBJSPEED = speed_amd64.o 10 | 11 | all: test_curve9767 speed_curve9767 12 | 13 | test_curve9767: $(OBJ) $(OBJTEST) 14 | $(LD) $(LDFLAGS) -o test_curve9767 $(OBJ) $(OBJTEST) $(LIBS) 15 | 16 | speed_curve9767: $(OBJ) $(OBJSPEED) 17 | $(LD) $(LDFLAGS) -o speed_curve9767 $(OBJ) $(OBJSPEED) $(LIBS) 18 | 19 | clean: 20 | -rm -f test_curve9767 speed_curve9767 $(OBJ) $(OBJTEST) $(OBJSPEED) 21 | 22 | curve9767.o: curve9767.c curve9767.h inner.h sha3.h 23 | $(CC) $(CFLAGS) -c -o curve9767.o curve9767.c 24 | 25 | ecdh.o: ecdh.c curve9767.h inner.h sha3.h 26 | $(CC) $(CFLAGS) -c -o ecdh.o ecdh.c 27 | 28 | hash.o: hash.c curve9767.h inner.h sha3.h 29 | $(CC) $(CFLAGS) -c -o hash.o hash.c 30 | 31 | keygen.o: keygen.c curve9767.h inner.h sha3.h 32 | $(CC) $(CFLAGS) -c -o keygen.o keygen.c 33 | 34 | ops_avx2.o: ops_avx2.c curve9767.h inner.h sha3.h 35 | $(CC) $(CFLAGS) -c -o ops_avx2.o ops_avx2.c 36 | 37 | scalar_amd64.o: scalar_amd64.c curve9767.h inner.h sha3.h 38 | $(CC) $(CFLAGS) -c -o scalar_amd64.o scalar_amd64.c 39 | 40 | sha3.o: sha3.c sha3.h 41 | $(CC) $(CFLAGS) -c -o sha3.o sha3.c 42 | 43 | sign.o: sign.c curve9767.h inner.h sha3.h 44 | $(CC) $(CFLAGS) -c -o sign.o sign.c 45 | 46 | speed_amd64.o: speed_amd64.c curve9767.h inner.h sha3.h 47 | $(CC) $(CFLAGS) -c -o speed_amd64.o speed_amd64.c 48 | 49 | test_curve9767.o: test_curve9767.c curve9767.h inner.h sha3.h 50 | $(CC) $(CFLAGS) -c -o test_curve9767.o test_curve9767.c 51 | -------------------------------------------------------------------------------- /src/Makefile.cm0: -------------------------------------------------------------------------------- 1 | CC = arm-linux-gcc 2 | CFLAGS = -Wall -Wextra -Wshadow -Wundef -Os -mcpu=cortex-m0plus 3 | LD = arm-linux-gcc 4 | LDFLAGS = 5 | LIBS = 6 | 7 | OBJ = curve9767.o ecdh.o hash.o keygen.o ops_arm.o ops_cm0.o scalar_arm.o scalar_cm0.o sha3.o sign.o test_curve9767.o 8 | 9 | test_curve9767: $(OBJ) 10 | $(LD) $(LDFLAGS) -o test_curve9767 $(OBJ) $(LIBS) 11 | 12 | clean: 13 | -rm -f test_curve9767 test_curve9767.gdb $(OBJ) 14 | 15 | curve9767.o: curve9767.c curve9767.h inner.h sha3.h 16 | $(CC) $(CFLAGS) -c -o curve9767.o curve9767.c 17 | 18 | ecdh.o: ecdh.c curve9767.h inner.h sha3.h 19 | $(CC) $(CFLAGS) -c -o ecdh.o ecdh.c 20 | 21 | hash.o: hash.c curve9767.h inner.h sha3.h 22 | $(CC) $(CFLAGS) -c -o hash.o hash.c 23 | 24 | keygen.o: keygen.c curve9767.h inner.h sha3.h 25 | $(CC) $(CFLAGS) -c -o keygen.o keygen.c 26 | 27 | ops_arm.o: ops_arm.c curve9767.h inner.h sha3.h 28 | $(CC) $(CFLAGS) -c -o ops_arm.o ops_arm.c 29 | 30 | ops_cm0.o: ops_cm0.s 31 | $(CC) $(CFLAGS) -c -o ops_cm0.o ops_cm0.s 32 | 33 | scalar_arm.o: scalar_arm.c curve9767.h inner.h sha3.h 34 | $(CC) $(CFLAGS) -c -o scalar_arm.o scalar_arm.c 35 | 36 | scalar_cm0.o: scalar_cm0.s 37 | $(CC) $(CFLAGS) -c -o scalar_cm0.o scalar_cm0.s 38 | 39 | sha3.o: sha3.c sha3.h 40 | $(CC) $(CFLAGS) -c -o sha3.o sha3.c 41 | 42 | sign.o: sign.c curve9767.h inner.h sha3.h 43 | $(CC) $(CFLAGS) -c -o sign.o sign.c 44 | 45 | test_curve9767.o: test_curve9767.c curve9767.h inner.h sha3.h 46 | $(CC) $(CFLAGS) -c -o test_curve9767.o test_curve9767.c 47 | -------------------------------------------------------------------------------- /src/Makefile.cm4: -------------------------------------------------------------------------------- 1 | CC = arm-linux-gcc 2 | CFLAGS = -Wall -Wextra -Wshadow -Wundef -Os -mcpu=cortex-m4 3 | LD = arm-linux-gcc 4 | LDFLAGS = 5 | LIBS = 6 | 7 | OBJ = curve9767.o ecdh.o hash.o keygen.o ops_arm.o scalar_arm.o scalar_cm4.o ops_cm4.o sha3_cm4.o sign.o test_curve9767.o 8 | 9 | test_curve9767: $(OBJ) 10 | $(LD) $(LDFLAGS) -o test_curve9767 $(OBJ) $(LIBS) 11 | 12 | clean: 13 | -rm -f test_curve9767 test_curve9767.gdb $(OBJ) 14 | 15 | curve9767.o: curve9767.c curve9767.h inner.h sha3.h 16 | $(CC) $(CFLAGS) -c -o curve9767.o curve9767.c 17 | 18 | ecdh.o: ecdh.c curve9767.h inner.h sha3.h 19 | $(CC) $(CFLAGS) -c -o ecdh.o ecdh.c 20 | 21 | hash.o: hash.c curve9767.h inner.h sha3.h 22 | $(CC) $(CFLAGS) -c -o hash.o hash.c 23 | 24 | keygen.o: keygen.c curve9767.h inner.h sha3.h 25 | $(CC) $(CFLAGS) -c -o keygen.o keygen.c 26 | 27 | ops_arm.o: ops_arm.c curve9767.h inner.h sha3.h 28 | $(CC) $(CFLAGS) -c -o ops_arm.o ops_arm.c 29 | 30 | ops_cm4.o: ops_cm4.s 31 | $(CC) $(CFLAGS) -c -o ops_cm4.o ops_cm4.s 32 | 33 | scalar_arm.o: scalar_arm.c curve9767.h inner.h sha3.h 34 | $(CC) $(CFLAGS) -c -o scalar_arm.o scalar_arm.c 35 | 36 | scalar_cm4.o: scalar_cm4.s 37 | $(CC) $(CFLAGS) -c -o scalar_cm4.o scalar_cm4.s 38 | 39 | sha3_cm4.o: sha3_cm4.c sha3.h 40 | $(CC) $(CFLAGS) -c -o sha3_cm4.o sha3_cm4.c 41 | 42 | sign.o: sign.c curve9767.h inner.h sha3.h 43 | $(CC) $(CFLAGS) -c -o sign.o sign.c 44 | 45 | test_curve9767.o: test_curve9767.c curve9767.h inner.h sha3.h 46 | $(CC) $(CFLAGS) -c -o test_curve9767.o test_curve9767.c 47 | -------------------------------------------------------------------------------- /src/curve9767.c: -------------------------------------------------------------------------------- 1 | #include "inner.h" 2 | 3 | /* ====================================================================== */ 4 | 5 | /* see curve9767.h */ 6 | int 7 | curve9767_point_encode(void *dst, const curve9767_point *Q) 8 | { 9 | int i; 10 | uint8_t *buf; 11 | uint8_t m; 12 | 13 | curve9767_inner_gf_encode(dst, Q->x); 14 | buf = dst; 15 | buf[31] |= curve9767_inner_gf_is_neg(Q->y) << 6; 16 | m = (uint8_t)-Q->neutral; 17 | for (i = 0; i < 31; i ++) { 18 | buf[i] |= m; 19 | } 20 | buf[31] |= m & 0x7F; 21 | return 1 - Q->neutral; 22 | } 23 | 24 | /* see curve9767.h */ 25 | int 26 | curve9767_point_encode_X(void *dst, const curve9767_point *Q) 27 | { 28 | int i; 29 | uint8_t *buf; 30 | uint8_t m; 31 | 32 | curve9767_inner_gf_encode(dst, Q->x); 33 | buf = dst; 34 | m = (uint8_t)-Q->neutral; 35 | for (i = 0; i < 31; i ++) { 36 | buf[i] |= m; 37 | } 38 | buf[31] |= m & 0x3F; 39 | return 1 - Q->neutral; 40 | } 41 | 42 | /* see curve9767.h */ 43 | int 44 | curve9767_point_decode(curve9767_point *Q, const void *src) 45 | { 46 | uint32_t tb, r; 47 | 48 | /* 49 | * Check that the top bit of the top byte is 0. 50 | */ 51 | tb = ((const uint8_t *)src)[31]; 52 | r = 1 - (tb >> 7); 53 | 54 | /* 55 | * Decode the X coordinate. 56 | */ 57 | r &= curve9767_inner_gf_decode(Q->x, src); 58 | 59 | /* 60 | * Obtain the Y coordinate. 61 | */ 62 | r &= curve9767_inner_make_y(Q->y, Q->x, (tb >> 6) & 0x01); 63 | 64 | /* 65 | * If one of the step failed, then the value is turned into the 66 | * point-at-infinity. 67 | */ 68 | Q->neutral = 1 - r; 69 | return r; 70 | } 71 | 72 | /* see curve9767.h */ 73 | void 74 | curve9767_point_neg(curve9767_point *Q2, const curve9767_point *Q1) 75 | { 76 | if (Q2 != Q1) { 77 | Q2->neutral = Q1->neutral; 78 | memcpy(Q2->x, Q1->x, sizeof Q1->x); 79 | } 80 | curve9767_inner_gf_neg(Q2->y, Q1->y); 81 | } 82 | 83 | /* see curve9767.h */ 84 | void 85 | curve9767_point_sub(curve9767_point *Q3, 86 | const curve9767_point *Q1, const curve9767_point *Q2) 87 | { 88 | curve9767_point T; 89 | 90 | curve9767_point_neg(&T, Q2); 91 | curve9767_point_add(Q3, Q1, &T); 92 | } 93 | -------------------------------------------------------------------------------- /src/ecdh.c: -------------------------------------------------------------------------------- 1 | #include "inner.h" 2 | 3 | #define DOM_ECDH "curve9767-ecdh:" 4 | #define DOM_ECDH_FAIL "curve9767-ecdh-failed:" 5 | 6 | /* see curve9767.h */ 7 | void 8 | curve9767_ecdh_keygen(curve9767_scalar *s, uint8_t encoded_Q[32], 9 | const void *seed, size_t seed_len) 10 | { 11 | if (encoded_Q == NULL) { 12 | curve9767_keygen(s, NULL, NULL, seed, seed_len); 13 | } else { 14 | curve9767_point Q; 15 | 16 | curve9767_keygen(s, NULL, &Q, seed, seed_len); 17 | curve9767_point_encode(encoded_Q, &Q); 18 | } 19 | } 20 | 21 | /* see curve9767.h */ 22 | int 23 | curve9767_ecdh_recv(void *shared_secret, size_t shared_secret_len, 24 | const curve9767_scalar *s, const uint8_t encoded_Q2[32]) 25 | { 26 | uint8_t pm[32], tmp[32]; 27 | curve9767_point Q2; 28 | uint32_t r; 29 | shake_context sc; 30 | int i; 31 | 32 | /* 33 | * Decode input point, do the point multiplication, and encode 34 | * the result into the pre-master array. 35 | */ 36 | r = curve9767_point_decode(&Q2, encoded_Q2); 37 | curve9767_point_mul(&Q2, &Q2, s); 38 | curve9767_point_encode_X(pm, &Q2); 39 | 40 | /* 41 | * Compute the alternate pre-master secret, to be used in case 42 | * of failure (r == 0). 43 | */ 44 | curve9767_scalar_encode(tmp, s); 45 | shake_init(&sc, 256); 46 | shake_inject(&sc, DOM_ECDH_FAIL, strlen(DOM_ECDH_FAIL)); 47 | shake_inject(&sc, tmp, 32); 48 | shake_inject(&sc, encoded_Q2, 32); 49 | shake_flip(&sc); 50 | shake_extract(&sc, tmp, 32); 51 | 52 | /* 53 | * Replace the pre-master with the alternate one, if the point 54 | * decoding process failed. 55 | */ 56 | for (i = 0; i < 32; i ++) { 57 | pm[i] ^= (uint8_t)((r - 1) & (pm[i] ^ tmp[i])); 58 | } 59 | 60 | /* 61 | * Compute the shared secret. 62 | */ 63 | shake_init(&sc, 256); 64 | shake_inject(&sc, DOM_ECDH, strlen(DOM_ECDH)); 65 | shake_inject(&sc, pm, 32); 66 | shake_flip(&sc); 67 | shake_extract(&sc, shared_secret, shared_secret_len); 68 | 69 | return (int)r; 70 | } 71 | -------------------------------------------------------------------------------- /src/hash.c: -------------------------------------------------------------------------------- 1 | #include "inner.h" 2 | #include "sha3.h" 3 | 4 | /* see curve9767.h */ 5 | void 6 | curve9767_hash_to_curve(curve9767_point *Q, shake_context *sc) 7 | { 8 | /* 9 | * We obtain 96 bytes from the SHAKE context, split into two 10 | * 48-byte seeds. Each seed is mapped to a field element, and 11 | * Icart's map is used to convert that element to a curve 12 | * point. Finally, the two points are added together. 13 | */ 14 | uint8_t seed[96]; 15 | field_element u; 16 | curve9767_point T; 17 | 18 | shake_extract(sc, seed, sizeof seed); 19 | curve9767_inner_gf_map_to_base(u.v, seed); 20 | curve9767_inner_Icart_map(Q, u.v); 21 | curve9767_inner_gf_map_to_base(u.v, seed + 48); 22 | curve9767_inner_Icart_map(&T, u.v); 23 | curve9767_point_add(Q, Q, &T); 24 | } 25 | -------------------------------------------------------------------------------- /src/keygen.c: -------------------------------------------------------------------------------- 1 | #include "inner.h" 2 | 3 | #define DOM_KEYGEN "curve9767-keygen:" 4 | 5 | /* see curve9767.h */ 6 | void 7 | curve9767_keygen(curve9767_scalar *s, uint8_t t[32], curve9767_point *Q, 8 | const void *seed, size_t seed_len) 9 | { 10 | shake_context sc; 11 | uint8_t tmp[64]; 12 | curve9767_scalar s2; 13 | 14 | shake_init(&sc, 256); 15 | shake_inject(&sc, DOM_KEYGEN, strlen(DOM_KEYGEN)); 16 | shake_inject(&sc, seed, seed_len); 17 | shake_flip(&sc); 18 | 19 | shake_extract(&sc, tmp, 64); 20 | if (s == NULL && Q != NULL) { 21 | s = &s2; 22 | } 23 | if (s != NULL) { 24 | curve9767_scalar_decode_reduce(s, tmp, 64); 25 | curve9767_scalar_condcopy(s, &curve9767_scalar_one, 26 | curve9767_scalar_is_zero(s)); 27 | } 28 | 29 | if (t != NULL) { 30 | shake_extract(&sc, t, 32); 31 | } 32 | 33 | if (Q != NULL) { 34 | curve9767_point_mulgen(Q, s); 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /src/sha3.h: -------------------------------------------------------------------------------- 1 | #ifndef SHA3_H__ 2 | #define SHA3_H__ 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | /* 9 | * Context for a SHAKE computation. Contents are opaque. 10 | * Contents are pure data with no pointer; they need not be released 11 | * explicitly and don't reference any other allocated resource. The 12 | * caller is responsible for allocating the context structure itself, 13 | * typically on the stack. 14 | * A running state can be cloned by copying the structure; this is 15 | * useful if "partial hashes" (hash of data processed so far) are 16 | * needed, without preventing injecting extra bytes later on. 17 | */ 18 | typedef struct { 19 | uint64_t A[25]; 20 | size_t dptr, rate; 21 | } shake_context; 22 | 23 | /* 24 | * Initialize a SHAKE context to its initial state. The state is 25 | * then ready to receive data (with shake_inject()). 26 | * 27 | * The "size" parameter should be 128 for SHAKE128, 256 for SHAKE256. 28 | * This is half of the internal parameter known as "capacity" (SHAKE128 29 | * works on an internal 256-bit capacity, SHAKE256 uses a 512-bit 30 | * capacity). 31 | */ 32 | void shake_init(shake_context *sc, unsigned size); 33 | 34 | /* 35 | * Inject some data bytes into the SHAKE context ("absorb" operation). 36 | * This function can be called several times, to inject several chunks 37 | * of data of arbitrary length. 38 | */ 39 | void shake_inject(shake_context *sc, const void *data, size_t len); 40 | 41 | /* 42 | * Flip the SHAKE state to output mode. After this call, shake_inject() 43 | * can no longer be called on the context, but shake_extract() can be 44 | * called. 45 | * 46 | * Flipping is one-way; a given context can be converted back to input 47 | * mode only by initializing it again, which forgets all previously 48 | * injected data. 49 | */ 50 | void shake_flip(shake_context *sc); 51 | 52 | /* 53 | * Extract bytes from the SHAKE context ("squeeze" operation). The 54 | * context must have been flipped to output mode (with shake_flip()). 55 | * Arbitrary amounts of data can be extracted, in one or several calls 56 | * to this function. 57 | */ 58 | void shake_extract(shake_context *sc, void *out, size_t len); 59 | 60 | /* 61 | * Context for SHA3 computations. Contents are opaque. 62 | * A running state can be cloned by copying the structure; this is 63 | * useful if "partial hashes" (hash of data processed so far) are 64 | * needed, without preventing injecting extra bytes later on. 65 | */ 66 | typedef shake_context sha3_context; 67 | 68 | /* 69 | * Initialize a SHA3 context, for a given output size (in bits), e.g. 70 | * set size to 256 for SHA3-256. 71 | */ 72 | void sha3_init(sha3_context *sc, unsigned size); 73 | 74 | /* 75 | * Update a SHA3 context with some bytes. 76 | */ 77 | void sha3_update(sha3_context *sc, const void *in, size_t len); 78 | 79 | /* 80 | * Finalize a SHA3 computation. The hash output is written in dst[], 81 | * with a size that depends on the one provided when the context was 82 | * last initialized. 83 | * 84 | * The context is modified. If a new hash must be computed, the context 85 | * must first be reinitialized explicitly. 86 | */ 87 | void sha3_close(sha3_context *sc, void *out); 88 | 89 | #ifdef __cplusplus 90 | } 91 | #endif 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /src/sign.c: -------------------------------------------------------------------------------- 1 | #include "inner.h" 2 | 3 | #define DOM_SIGN_K "curve9767-sign-k:" 4 | #define DOM_SIGN_E "curve9767-sign-e:" 5 | 6 | static void 7 | make_k(curve9767_scalar *k, const uint8_t t[32], 8 | const char *hash_oid, const void *hv, size_t hv_len) 9 | { 10 | shake_context sc; 11 | uint8_t tmp[64]; 12 | 13 | shake_init(&sc, 256); 14 | shake_inject(&sc, DOM_SIGN_K, strlen(DOM_SIGN_K)); 15 | shake_inject(&sc, t, 32); 16 | shake_inject(&sc, hash_oid, strlen(hash_oid)); 17 | shake_inject(&sc, ":", 1); 18 | shake_inject(&sc, hv, hv_len); 19 | shake_flip(&sc); 20 | shake_extract(&sc, tmp, 64); 21 | curve9767_scalar_decode_reduce(k, tmp, 64); 22 | curve9767_scalar_condcopy(k, &curve9767_scalar_one, 23 | curve9767_scalar_is_zero(k)); 24 | } 25 | 26 | static void 27 | make_e(curve9767_scalar *e, const uint8_t c[32], const curve9767_point *Q, 28 | const char *hash_oid, const void *hv, size_t hv_len) 29 | { 30 | shake_context sc; 31 | uint8_t tmp[64]; 32 | 33 | shake_init(&sc, 256); 34 | shake_inject(&sc, DOM_SIGN_E, strlen(DOM_SIGN_E)); 35 | shake_inject(&sc, c, 32); 36 | curve9767_point_encode(tmp, Q); 37 | shake_inject(&sc, tmp, 32); 38 | shake_inject(&sc, hash_oid, strlen(hash_oid)); 39 | shake_inject(&sc, ":", 1); 40 | shake_inject(&sc, hv, hv_len); 41 | shake_flip(&sc); 42 | shake_extract(&sc, tmp, 64); 43 | curve9767_scalar_decode_reduce(e, tmp, 64); 44 | } 45 | 46 | /* see curve9767.h */ 47 | void 48 | curve9767_sign_generate(void *sig, 49 | const curve9767_scalar *s, const uint8_t t[32], 50 | const curve9767_point *Q, 51 | const char *hash_oid, const void *hv, size_t hv_len) 52 | { 53 | curve9767_scalar k, e; 54 | curve9767_point C; 55 | uint8_t tmp[64]; 56 | 57 | make_k(&k, t, hash_oid, hv, hv_len); 58 | curve9767_point_mulgen(&C, &k); 59 | curve9767_point_encode(tmp, &C); 60 | make_e(&e, tmp, Q, hash_oid, hv, hv_len); 61 | curve9767_scalar_mul(&e, &e, s); 62 | curve9767_scalar_add(&e, &e, &k); 63 | curve9767_scalar_encode(tmp + 32, &e); 64 | memcpy(sig, tmp, 64); 65 | } 66 | 67 | /* see curve9767.h */ 68 | int 69 | curve9767_sign_verify(const void *sig, 70 | const curve9767_point *Q, 71 | const char *hash_oid, const void *hv, size_t hv_len) 72 | { 73 | curve9767_scalar d, e; 74 | curve9767_point C; 75 | uint32_t r, w; 76 | const uint8_t *buf; 77 | uint8_t tmp[32]; 78 | int i; 79 | 80 | buf = sig; 81 | r = curve9767_scalar_decode_strict(&d, buf + 32, 32); 82 | make_e(&e, buf, Q, hash_oid, hv, hv_len); 83 | curve9767_scalar_neg(&e, &e); 84 | curve9767_point_mul_mulgen_add(&C, Q, &e, &d); 85 | curve9767_point_encode(tmp, &C); 86 | w = 0; 87 | for (i = 0; i < 32; i ++) { 88 | w |= tmp[i] ^ buf[i]; 89 | } 90 | return r & ((w - 1) >> 31); 91 | } 92 | 93 | /* see curve9767.h */ 94 | int 95 | curve9767_sign_verify_vartime(const void *sig, 96 | const curve9767_point *Q, 97 | const char *hash_oid, const void *hv, size_t hv_len) 98 | { 99 | curve9767_scalar d, e; 100 | curve9767_point C; 101 | const uint8_t *buf; 102 | 103 | buf = sig; 104 | if (!curve9767_point_decode(&C, buf)) { 105 | return 0; 106 | } 107 | if (!curve9767_scalar_decode_strict(&d, buf + 32, 32)) { 108 | return 0; 109 | } 110 | make_e(&e, buf, Q, hash_oid, hv, hv_len); 111 | curve9767_scalar_neg(&e, &e); 112 | return curve9767_point_verify_mul_mulgen_add_vartime(Q, &e, &d, &C); 113 | } 114 | --------------------------------------------------------------------------------