├── MAINFILE.qsf ├── MAINFILE.qws ├── MAINFILE.v ├── MAINFILE.v.bak ├── README.md ├── c5_pin_model_dump.txt ├── commandSelector.v ├── db ├── MAINFILE.(0).cnf.cdb ├── MAINFILE.(0).cnf.hdb ├── MAINFILE.(1).cnf.cdb ├── MAINFILE.(1).cnf.hdb ├── MAINFILE.(10).cnf.cdb ├── MAINFILE.(10).cnf.hdb ├── MAINFILE.(11).cnf.cdb ├── MAINFILE.(11).cnf.hdb ├── MAINFILE.(12).cnf.cdb ├── MAINFILE.(12).cnf.hdb ├── MAINFILE.(13).cnf.cdb ├── MAINFILE.(13).cnf.hdb ├── MAINFILE.(14).cnf.cdb ├── MAINFILE.(14).cnf.hdb ├── MAINFILE.(15).cnf.cdb ├── MAINFILE.(15).cnf.hdb ├── MAINFILE.(16).cnf.cdb ├── MAINFILE.(16).cnf.hdb ├── MAINFILE.(17).cnf.cdb ├── MAINFILE.(17).cnf.hdb ├── MAINFILE.(18).cnf.cdb ├── MAINFILE.(18).cnf.hdb ├── MAINFILE.(19).cnf.cdb ├── MAINFILE.(19).cnf.hdb ├── MAINFILE.(2).cnf.cdb ├── MAINFILE.(2).cnf.hdb ├── MAINFILE.(3).cnf.cdb ├── MAINFILE.(3).cnf.hdb ├── MAINFILE.(4).cnf.cdb ├── MAINFILE.(4).cnf.hdb ├── MAINFILE.(5).cnf.cdb ├── MAINFILE.(5).cnf.hdb ├── MAINFILE.(6).cnf.cdb ├── MAINFILE.(6).cnf.hdb ├── a_gray2bin_g9b.tdf ├── a_graycounter_bcc.tdf ├── a_graycounter_fu6.tdf ├── alt_synch_pipe_0ol.tdf ├── alt_synch_pipe_1ol.tdf ├── altsyncram_vra1.tdf ├── cmpr_1v5.tdf ├── dcfifo_70p1.tdf ├── dffpipe_gd9.tdf ├── dffpipe_hd9.tdf └── dffpipe_id9.tdf ├── incremental_db ├── README └── compiled_partitions │ ├── MAINFILE.db_info │ ├── MAINFILE.root_partition.cmp.ammdb │ ├── MAINFILE.root_partition.cmp.cdb │ ├── MAINFILE.root_partition.cmp.dfp │ ├── MAINFILE.root_partition.cmp.hbdb.cdb │ ├── MAINFILE.root_partition.cmp.hbdb.hdb │ ├── MAINFILE.root_partition.cmp.hbdb.sig │ ├── MAINFILE.root_partition.cmp.hdb │ ├── MAINFILE.root_partition.cmp.logdb │ ├── MAINFILE.root_partition.cmp.rcfdb │ ├── MAINFILE.root_partition.map.cdb │ ├── MAINFILE.root_partition.map.dpi │ ├── MAINFILE.root_partition.map.hbdb.cdb │ ├── MAINFILE.root_partition.map.hbdb.hb_info │ ├── MAINFILE.root_partition.map.hbdb.hdb │ ├── MAINFILE.root_partition.map.hbdb.sig │ ├── MAINFILE.root_partition.map.hdb │ ├── MAINFILE.root_partition.map.kpt │ ├── MAINFILE.rrp.hdb │ └── MAINFILE.rrs.cdb ├── ip ├── PWM_Geneator.v ├── ServoControl.v ├── ServoControl.v.bak ├── UI.v └── UI.v.bak ├── motorControl.qpf ├── motorControl.qsf ├── output_files ├── MAINFILE.asm.rpt ├── MAINFILE.done ├── MAINFILE.fit.rpt ├── MAINFILE.fit.smsg ├── MAINFILE.fit.summary ├── MAINFILE.flow.rpt ├── MAINFILE.jdi ├── MAINFILE.map.rpt ├── MAINFILE.map.summary ├── MAINFILE.pin ├── MAINFILE.sld ├── MAINFILE.sof ├── MAINFILE.sta.rpt └── MAINFILE.sta.summary └── uart ├── async_receiver.v ├── async_receiver.v.bak ├── async_transmitter.v ├── uart_control.v ├── uart_control.v.bak ├── uart_fifo.cnx └── uart_fifo.v /MAINFILE.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 21 | # Date created = 23:19:48 October 25, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # MAINFILE_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEBA6U23I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY MAINFILE 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:19:48 OCTOBER 25, 2018" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 50 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 51 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 53 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 54 | set_global_assignment -name VERILOG_FILE MAINFILE.v 55 | set_global_assignment -name VERILOG_FILE ip/UI.v 56 | set_global_assignment -name VERILOG_FILE ip/ServoControl.v 57 | set_global_assignment -name VERILOG_FILE ip/PWM_Geneator.v 58 | set_global_assignment -name VERILOG_FILE uart/uart_fifo.v 59 | set_global_assignment -name VERILOG_FILE uart/uart_control.v 60 | set_global_assignment -name VERILOG_FILE uart/async_transmitter.v 61 | set_global_assignment -name VERILOG_FILE uart/async_receiver.v 62 | set_global_assignment -name VERILOG_FILE commandSelector.v 63 | set_location_assignment PIN_AF4 -to BT_KEY 64 | set_location_assignment PIN_AD17 -to BT_UART_TX 65 | set_location_assignment PIN_V11 -to FPGA_CLK1_50 66 | set_location_assignment PIN_C12 -to BT_UART_RX 67 | set_location_assignment PIN_Y13 -to FPGA_CLK2_50 68 | set_location_assignment PIN_E11 -to FPGA_CLK3_50 69 | set_location_assignment PIN_AF28 -to GPIO_1[5] 70 | set_location_assignment PIN_AG28 -to GPIO_1[4] 71 | set_location_assignment PIN_AD26 -to GPIO_1[3] 72 | set_location_assignment PIN_AA15 -to GPIO_1[2] 73 | set_location_assignment PIN_AC24 -to GPIO_1[1] 74 | set_location_assignment PIN_Y15 -to GPIO_1[0] 75 | set_location_assignment PIN_AH16 -to KEY[1] 76 | set_location_assignment PIN_AH17 -to KEY[0] 77 | set_location_assignment PIN_AA23 -to LED[7] 78 | set_location_assignment PIN_Y16 -to LED[6] 79 | set_location_assignment PIN_AE26 -to LED[5] 80 | set_location_assignment PIN_AF26 -to LED[4] 81 | set_location_assignment PIN_V15 -to LED[3] 82 | set_location_assignment PIN_V16 -to LED[2] 83 | set_location_assignment PIN_AA24 -to LED[1] 84 | set_location_assignment PIN_W15 -to LED[0] 85 | set_location_assignment PIN_W20 -to SW[3] 86 | set_location_assignment PIN_W21 -to SW[2] 87 | set_location_assignment PIN_W24 -to SW[1] 88 | set_location_assignment PIN_Y24 -to SW[0] 89 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BT_KEY 90 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BT_UART_RX 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BT_UART_TX 92 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 94 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] 96 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] 114 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] 115 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /MAINFILE.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/powerplayer9/Voice-Based-Motor-Control/623afa38b3a6c0c4f1ee6d5691df55cc80f3a0f9/MAINFILE.qws -------------------------------------------------------------------------------- /MAINFILE.v: -------------------------------------------------------------------------------- 1 | 2 | //======================================================= 3 | // This code is generated by Terasic System Builder 4 | //======================================================= 5 | 6 | module MAINFILE( 7 | 8 | 9 | 10 | //////////// CLOCK ////////// 11 | input FPGA_CLK1_50, 12 | input FPGA_CLK2_50, 13 | input FPGA_CLK3_50, 14 | 15 | 16 | //////////// KEY ////////// 17 | input [1:0] KEY, 18 | // input [1:0] KEYMOTOR, 19 | 20 | //////////// LED ////////// 21 | output [7:0] LED, 22 | 23 | //////////// SW ////////// 24 | input [3:0] SW, 25 | 26 | //////////// GPIO_0, GPIO connect to RFS ////////// 27 | inout BT_KEY, 28 | input BT_UART_RX, 29 | output BT_UART_TX, 30 | 31 | //////////// Motor Control ////////// 32 | inout [5:0] GPIO_1 33 | 34 | ); 35 | 36 | 37 | 38 | //======================================================= 39 | // REG/WIRE declarations 40 | //======================================================= 41 | 42 | wire rts; // request to send 43 | wire cts; // clear to send 44 | wire rxd; 45 | wire txd; 46 | wire [7:0] uart_data; 47 | wire rdempty; 48 | wire write; 49 | reg read; 50 | reg cnt; 51 | wire [7:0] LEDFake; 52 | wire [7:0] command; // output from bluetooth to input to motor module 53 | //======================================================= 54 | // Structural coding 55 | //======================================================= 56 | 57 | // UART Controller 58 | uart_control UART0( 59 | 60 | .clk(FPGA_CLK1_50), 61 | .reset_n(KEY[0]), 62 | 63 | // rx 64 | .read(read), 65 | .readdata(uart_data), 66 | .rdempty(rdempty), 67 | // 68 | .uart_clk_25m(cnt), 69 | .uart_rx(BT_UART_RX) 70 | 71 | ); 72 | 73 | //read 74 | always@(posedge FPGA_CLK1_50) 75 | begin 76 | if (~rdempty) 77 | read <= 1; 78 | else 79 | read <= 0; 80 | end 81 | assign write = ( read & (~rdempty) ); 82 | 83 | 84 | commandSelector c0 (FPGA_CLK1_50, 85 | KEY[0], 86 | write, 87 | uart_data, 88 | LED, 89 | command 90 | ); 91 | 92 | ServoControl S0(FPGA_CLK1_50, 93 | FPGA_CLK2_50, 94 | FPGA_CLK3_50, 95 | command, 96 | LEDFake, 97 | SW, 98 | GPIO_1 99 | ); 100 | 101 | always@(posedge FPGA_CLK1_50) 102 | cnt <= cnt + 1; 103 | 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /MAINFILE.v.bak: -------------------------------------------------------------------------------- 1 | 2 | //======================================================= 3 | // This code is generated by Terasic System Builder 4 | //======================================================= 5 | 6 | module MAINFILE( 7 | 8 | 9 | 10 | //////////// CLOCK ////////// 11 | input FPGA_CLK1_50, 12 | input FPGA_CLK2_50, 13 | input FPGA_CLK3_50, 14 | 15 | 16 | //////////// KEY ////////// 17 | input [1:0] KEY, 18 | // input [1:0] KEYMOTOR, 19 | 20 | //////////// LED ////////// 21 | output reg [7:0] LED, 22 | 23 | //////////// SW ////////// 24 | input [3:0] SW, 25 | 26 | //////////// GPIO_0, GPIO connect to RFS ////////// 27 | inout BT_KEY, 28 | input BT_UART_RX, 29 | output BT_UART_TX, 30 | 31 | //////////// Motor Control ////////// 32 | inout [5:0] GPIO_1 33 | 34 | ); 35 | 36 | 37 | 38 | //======================================================= 39 | // REG/WIRE declarations 40 | //======================================================= 41 | 42 | wire rts; // request to send 43 | wire cts; // clear to send 44 | wire rxd; 45 | wire txd; 46 | wire [7:0] uart_data; 47 | wire rdempty; 48 | wire write; 49 | reg read; 50 | reg cnt; 51 | wire [7:0] LEDFake; 52 | reg [7:0] command; // output from bluetooth to input to motor module 53 | //======================================================= 54 | // Structural coding 55 | //======================================================= 56 | 57 | // UART Controller 58 | uart_control UART0( 59 | 60 | .clk(FPGA_CLK1_50), 61 | .reset_n(KEY[0]), 62 | 63 | // rx 64 | .read(read), 65 | .readdata(uart_data), 66 | .rdempty(rdempty), 67 | // 68 | .uart_clk_25m(cnt), 69 | .uart_rx(BT_UART_RX) 70 | 71 | ); 72 | 73 | //read 74 | always@(posedge FPGA_CLK1_50) 75 | begin 76 | if (~rdempty) 77 | read <= 1; 78 | else 79 | read <= 0; 80 | end 81 | assign write = ( read & (~rdempty) ); 82 | 83 | 84 | commandSelector c0 (FPGA_CLK1_50, 85 | KEY[0], 86 | write, 87 | uart_data, 88 | LED, 89 | command 90 | ); 91 | 92 | ServoControl S0(FPGA_CLK1_50, 93 | FPGA_CLK2_50, 94 | FPGA_CLK3_50, 95 | command, 96 | LEDFake, 97 | SW, 98 | GPIO_1 99 | ); 100 | 101 | always@(posedge FPGA_CLK1_50) 102 | cnt <= cnt + 1; 103 | 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Voice-Based-Motor-Control 2 | A verilog HDL based project to control a servomotor with voice commands from an android phone. 3 | 4 | The project is implemented on an **ALtera DE10-Nano board**. 5 | 6 | The Bluetooth connectivity with the Android phone was done using [**terasIC RFS card**](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=65&No=1025). 7 | 8 | The motor control was based on PWM signals passed via a [**terasIC servo motor card**](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=149&No=1028) for voltage regulation. 9 | 10 | The Android app used for this project --> [**BluetoothVoiceServo**](https://github.com/sidpethe/BluetoothVoiceServo) 11 | -------------------------------------------------------------------------------- /c5_pin_model_dump.txt: -------------------------------------------------------------------------------- 1 | io_4iomodule_c5_index: 55gpio_index: 2 2 | io_4iomodule_c5_index: 54gpio_index: 465 3 | io_4iomodule_c5_index: 33gpio_index: 6 4 | io_4iomodule_c5_index: 51gpio_index: 461 5 | io_4iomodule_c5_index: 27gpio_index: 10 6 | io_4iomodule_c5_index: 57gpio_index: 457 7 | io_4iomodule_c5_index: 34gpio_index: 14 8 | io_4iomodule_c5_index: 28gpio_index: 453 9 | io_4iomodule_c5_index: 26gpio_index: 19 10 | io_4iomodule_c5_index: 47gpio_index: 449 11 | io_4iomodule_c5_index: 29gpio_index: 22 12 | io_4iomodule_c5_index: 3gpio_index: 445 13 | io_4iomodule_c5_index: 16gpio_index: 27 14 | io_4iomodule_c5_index: 6gpio_index: 441 15 | io_4iomodule_c5_index: 50gpio_index: 30 16 | io_4iomodule_c5_index: 35gpio_index: 437 17 | io_4iomodule_c5_index: 7gpio_index: 35 18 | io_4iomodule_c5_index: 53gpio_index: 433 19 | io_4iomodule_c5_index: 12gpio_index: 38 20 | io_4iomodule_c5_index: 1gpio_index: 429 21 | io_4iomodule_c5_index: 22gpio_index: 43 22 | io_4iomodule_c5_index: 8gpio_index: 425 23 | io_4iomodule_c5_index: 20gpio_index: 46 24 | io_4iomodule_c5_index: 30gpio_index: 421 25 | io_4iomodule_c5_index: 2gpio_index: 51 26 | io_4iomodule_c5_index: 31gpio_index: 417 27 | io_4iomodule_c5_index: 39gpio_index: 54 28 | io_4iomodule_c5_index: 18gpio_index: 413 29 | io_4iomodule_c5_index: 10gpio_index: 59 30 | io_4iomodule_c5_index: 42gpio_index: 409 31 | io_4iomodule_c5_index: 5gpio_index: 62 32 | io_4iomodule_c5_index: 24gpio_index: 405 33 | io_4iomodule_c5_index: 37gpio_index: 67 34 | io_4iomodule_c5_index: 13gpio_index: 401 35 | io_4iomodule_c5_index: 0gpio_index: 70 36 | io_4iomodule_c5_index: 44gpio_index: 397 37 | io_4iomodule_c5_index: 38gpio_index: 75 38 | io_4iomodule_c5_index: 52gpio_index: 393 39 | io_4iomodule_c5_index: 32gpio_index: 78 40 | io_4iomodule_c5_index: 56gpio_index: 389 41 | io_4iomodule_a_index: 13gpio_index: 385 42 | io_4iomodule_c5_index: 4gpio_index: 83 43 | io_4iomodule_c5_index: 23gpio_index: 86 44 | io_4iomodule_a_index: 15gpio_index: 381 45 | io_4iomodule_a_index: 8gpio_index: 377 46 | io_4iomodule_c5_index: 46gpio_index: 91 47 | io_4iomodule_a_index: 5gpio_index: 373 48 | io_4iomodule_a_index: 11gpio_index: 369 49 | io_4iomodule_c5_index: 41gpio_index: 94 50 | io_4iomodule_a_index: 3gpio_index: 365 51 | io_4iomodule_c5_index: 25gpio_index: 99 52 | io_4iomodule_a_index: 7gpio_index: 361 53 | io_4iomodule_c5_index: 9gpio_index: 102 54 | io_4iomodule_a_index: 0gpio_index: 357 55 | io_4iomodule_c5_index: 14gpio_index: 107 56 | io_4iomodule_a_index: 12gpio_index: 353 57 | io_4iomodule_c5_index: 45gpio_index: 110 58 | io_4iomodule_c5_index: 17gpio_index: 115 59 | io_4iomodule_a_index: 4gpio_index: 349 60 | io_4iomodule_c5_index: 36gpio_index: 118 61 | io_4iomodule_a_index: 10gpio_index: 345 62 | io_4iomodule_a_index: 16gpio_index: 341 63 | io_4iomodule_c5_index: 15gpio_index: 123 64 | io_4iomodule_a_index: 14gpio_index: 337 65 | io_4iomodule_c5_index: 43gpio_index: 126 66 | io_4iomodule_c5_index: 19gpio_index: 131 67 | io_4iomodule_a_index: 1gpio_index: 333 68 | io_4iomodule_c5_index: 59gpio_index: 134 69 | io_4iomodule_a_index: 2gpio_index: 329 70 | io_4iomodule_a_index: 9gpio_index: 325 71 | io_4iomodule_c5_index: 48gpio_index: 139 72 | io_4iomodule_a_index: 6gpio_index: 321 73 | io_4iomodule_a_index: 17gpio_index: 317 74 | io_4iomodule_c5_index: 40gpio_index: 142 75 | io_4iomodule_c5_index: 11gpio_index: 147 76 | io_4iomodule_c5_index: 58gpio_index: 150 77 | io_4iomodule_c5_index: 21gpio_index: 155 78 | io_4iomodule_c5_index: 49gpio_index: 158 79 | io_4iomodule_h_c5_index: 0gpio_index: 161 80 | io_4iomodule_h_c5_index: 6gpio_index: 165 81 | io_4iomodule_h_c5_index: 10gpio_index: 169 82 | io_4iomodule_h_c5_index: 3gpio_index: 173 83 | io_4iomodule_h_c5_index: 8gpio_index: 176 84 | io_4iomodule_h_c5_index: 11gpio_index: 180 85 | io_4iomodule_h_c5_index: 7gpio_index: 184 86 | io_4iomodule_h_c5_index: 5gpio_index: 188 87 | io_4iomodule_h_c5_index: 1gpio_index: 192 88 | io_4iomodule_h_c5_index: 2gpio_index: 196 89 | io_4iomodule_h_c5_index: 9gpio_index: 200 90 | io_4iomodule_h_c5_index: 4gpio_index: 204 91 | io_4iomodule_h_index: 15gpio_index: 208 92 | io_4iomodule_h_index: 1gpio_index: 212 93 | io_4iomodule_h_index: 3gpio_index: 216 94 | io_4iomodule_h_index: 2gpio_index: 220 95 | io_4iomodule_h_index: 11gpio_index: 224 96 | io_4iomodule_vref_h_index: 1gpio_index: 228 97 | io_4iomodule_h_index: 20gpio_index: 231 98 | io_4iomodule_h_index: 8gpio_index: 235 99 | io_4iomodule_h_index: 6gpio_index: 239 100 | io_4iomodule_h_index: 10gpio_index: 243 101 | io_4iomodule_h_index: 23gpio_index: 247 102 | io_4iomodule_h_index: 7gpio_index: 251 103 | io_4iomodule_h_index: 22gpio_index: 255 104 | io_4iomodule_h_index: 5gpio_index: 259 105 | io_4iomodule_h_index: 24gpio_index: 263 106 | io_4iomodule_h_index: 0gpio_index: 267 107 | io_4iomodule_h_index: 13gpio_index: 271 108 | io_4iomodule_h_index: 21gpio_index: 275 109 | io_4iomodule_h_index: 16gpio_index: 279 110 | io_4iomodule_vref_h_index: 0gpio_index: 283 111 | io_4iomodule_h_index: 12gpio_index: 286 112 | io_4iomodule_h_index: 4gpio_index: 290 113 | io_4iomodule_h_index: 19gpio_index: 294 114 | io_4iomodule_h_index: 18gpio_index: 298 115 | io_4iomodule_h_index: 17gpio_index: 302 116 | io_4iomodule_h_index: 25gpio_index: 306 117 | io_4iomodule_h_index: 14gpio_index: 310 118 | io_4iomodule_h_index: 9gpio_index: 314 119 | -------------------------------------------------------------------------------- /commandSelector.v: -------------------------------------------------------------------------------- 1 | module commandSelector( 2 | input FPGA_CLK1_50, 3 | input KEY, 4 | input write, 5 | input uart_data, 6 | 7 | output reg LED, 8 | output reg [7:0] command 9 | 10 | ); 11 | 12 | 13 | always@(posedge FPGA_CLK1_50 or negedge KEY) 14 | begin 15 | if(!KEY) 16 | LED <= 0; 17 | else if(KEY & write) 18 | begin 19 | case(uart_data) 20 | 10'h30:command <= 8'd0; 21 | 10'h31:command <= 8'd1; 22 | 10'h32:command <= 8'd2; 23 | 10'h33:command <= 8'd3; 24 | 10'h34:command <= 8'd4; 25 | 10'h35:command <= 8'd5; 26 | 10'h36:command <= 8'd6; 27 | 10'h37:command <= 8'd7; 28 | 10'h38:command <= 8'd8; 29 | 10'h39:command <= 8'd9; 30 | default : command <= command; 31 | endcase 32 | 33 | end 34 | else 35 | LED <= LED; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /db/MAINFILE.(0).cnf.cdb: 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All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN a_gray2bin_g9b 23 | ( 24 | bin[8..0] : output; 25 | gray[8..0] : input; 26 | ) 27 | VARIABLE 28 | xor0 : WIRE; 29 | xor1 : WIRE; 30 | xor2 : WIRE; 31 | xor3 : WIRE; 32 | xor4 : WIRE; 33 | xor5 : WIRE; 34 | xor6 : WIRE; 35 | xor7 : WIRE; 36 | 37 | BEGIN 38 | bin[] = ( gray[8..8], xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0); 39 | xor0 = (gray[0..0] $ xor1); 40 | xor1 = (gray[1..1] $ xor2); 41 | xor2 = (gray[2..2] $ xor3); 42 | xor3 = (gray[3..3] $ xor4); 43 | xor4 = (gray[4..4] $ xor5); 44 | xor5 = (gray[5..5] $ xor6); 45 | xor6 = (gray[6..6] $ xor7); 46 | xor7 = (gray[8..8] $ gray[7..7]); 47 | END; 48 | --VALID FILE 49 | -------------------------------------------------------------------------------- /db/a_graycounter_bcc.tdf: -------------------------------------------------------------------------------- 1 | --a_graycounter DEVICE_FAMILY="Cyclone V" PVALUE=1 WIDTH=9 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=S102 2 | --VERSION_BEGIN 18.0 cbx_a_gray2bin 2018:04:24:18:04:18:SJ cbx_a_graycounter 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = reg 12 22 | OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=S102;{-to counter8a0} POWER_UP_LEVEL=HIGH;{-to parity9} POWER_UP_LEVEL=HIGH"; 23 | 24 | SUBDESIGN a_graycounter_bcc 25 | ( 26 | aclr : input; 27 | clock : input; 28 | cnt_en : input; 29 | q[8..0] : output; 30 | ) 31 | VARIABLE 32 | counter8a0 : dffeas 33 | WITH ( 34 | power_up = "high" 35 | ); 36 | counter8a1 : dffeas; 37 | counter8a2 : dffeas; 38 | counter8a3 : dffeas; 39 | counter8a4 : dffeas; 40 | counter8a5 : dffeas; 41 | counter8a6 : dffeas; 42 | counter8a7 : dffeas; 43 | counter8a8 : dffeas; 44 | parity9 : dffeas 45 | WITH ( 46 | power_up = "high" 47 | ); 48 | sub_parity10a[1..0] : dffeas; 49 | cntr_cout[8..0] : WIRE; 50 | parity_cout : WIRE; 51 | sclr : NODE; 52 | updown : NODE; 53 | 54 | BEGIN 55 | counter8a[8..0].clk = clock; 56 | counter8a[8..1].clrn = (! aclr); 57 | counter8a[8..0].d = ( (counter8a[8].q $ cntr_cout[7..7]), (counter8a[7].q $ (counter8a[6].q & cntr_cout[6..6])), (counter8a[6].q $ (counter8a[5].q & cntr_cout[5..5])), (counter8a[5].q $ (counter8a[4].q & cntr_cout[4..4])), (counter8a[4].q $ (counter8a[3].q & cntr_cout[3..3])), (counter8a[3].q $ (counter8a[2].q & cntr_cout[2..2])), (counter8a[2].q $ (counter8a[1].q & cntr_cout[1..1])), (counter8a[1].q $ (counter8a[0].q & cntr_cout[0..0])), ((cnt_en & (counter8a[0].q $ (! parity_cout))) # ((! cnt_en) & counter8a[0].q))); 58 | counter8a[0].prn = (! aclr); 59 | counter8a[8..0].sclr = sclr; 60 | parity9.clk = clock; 61 | parity9.d = ((cnt_en & (sub_parity10a[0..0].q $ sub_parity10a[1..1].q)) # ((! cnt_en) & parity9.q)); 62 | parity9.prn = (! aclr); 63 | parity9.sclr = sclr; 64 | sub_parity10a[].clk = ( clock, clock); 65 | sub_parity10a[].clrn = ( (! aclr), (! aclr)); 66 | sub_parity10a[].d = ( ((cnt_en & ((counter8a[6..6].q $ counter8a[7..7].q) $ counter8a[8..8].q)) # ((! cnt_en) & sub_parity10a[1].q)), ((cnt_en & (((((counter8a[0..0].q $ counter8a[1..1].q) $ counter8a[2..2].q) $ counter8a[3..3].q) $ counter8a[4..4].q) $ counter8a[5..5].q)) # ((! cnt_en) & sub_parity10a[0].q))); 67 | sub_parity10a[].sclr = ( sclr, sclr); 68 | cntr_cout[] = ( B"0", (cntr_cout[6..6] & (! counter8a[6].q)), (cntr_cout[5..5] & (! counter8a[5].q)), (cntr_cout[4..4] & (! counter8a[4].q)), (cntr_cout[3..3] & (! counter8a[3].q)), (cntr_cout[2..2] & (! counter8a[2].q)), (cntr_cout[1..1] & (! counter8a[1].q)), (cntr_cout[0..0] & (! counter8a[0].q)), (cnt_en & parity_cout)); 69 | parity_cout = (((! parity9.q) $ updown) & cnt_en); 70 | q[] = counter8a[8..0].q; 71 | sclr = GND; 72 | updown = VCC; 73 | END; 74 | --VALID FILE 75 | -------------------------------------------------------------------------------- /db/a_graycounter_fu6.tdf: -------------------------------------------------------------------------------- 1 | --a_graycounter DEVICE_FAMILY="Cyclone V" PVALUE=1 WIDTH=9 aclr clock cnt_en q 2 | --VERSION_BEGIN 18.0 cbx_a_gray2bin 2018:04:24:18:04:18:SJ cbx_a_graycounter 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = reg 12 22 | OPTIONS ALTERA_INTERNAL_OPTION = "{-to counter5a0} POWER_UP_LEVEL=HIGH;{-to parity6} POWER_UP_LEVEL=HIGH"; 23 | 24 | SUBDESIGN a_graycounter_fu6 25 | ( 26 | aclr : input; 27 | clock : input; 28 | cnt_en : input; 29 | q[8..0] : output; 30 | ) 31 | VARIABLE 32 | counter5a0 : dffeas 33 | WITH ( 34 | power_up = "high" 35 | ); 36 | counter5a1 : dffeas; 37 | counter5a2 : dffeas; 38 | counter5a3 : dffeas; 39 | counter5a4 : dffeas; 40 | counter5a5 : dffeas; 41 | counter5a6 : dffeas; 42 | counter5a7 : dffeas; 43 | counter5a8 : dffeas; 44 | parity6 : dffeas 45 | WITH ( 46 | power_up = "high" 47 | ); 48 | sub_parity7a[1..0] : dffeas; 49 | cntr_cout[8..0] : WIRE; 50 | parity_cout : WIRE; 51 | sclr : NODE; 52 | updown : NODE; 53 | 54 | BEGIN 55 | counter5a[8..0].clk = clock; 56 | counter5a[8..1].clrn = (! aclr); 57 | counter5a[8..0].d = ( (counter5a[8].q $ cntr_cout[7..7]), (counter5a[7].q $ (counter5a[6].q & cntr_cout[6..6])), (counter5a[6].q $ (counter5a[5].q & cntr_cout[5..5])), (counter5a[5].q $ (counter5a[4].q & cntr_cout[4..4])), (counter5a[4].q $ (counter5a[3].q & cntr_cout[3..3])), (counter5a[3].q $ (counter5a[2].q & cntr_cout[2..2])), (counter5a[2].q $ (counter5a[1].q & cntr_cout[1..1])), (counter5a[1].q $ (counter5a[0].q & cntr_cout[0..0])), ((cnt_en & (counter5a[0].q $ (! parity_cout))) # ((! cnt_en) & counter5a[0].q))); 58 | counter5a[0].prn = (! aclr); 59 | counter5a[8..0].sclr = sclr; 60 | parity6.clk = clock; 61 | parity6.d = ((cnt_en & (sub_parity7a[0..0].q $ sub_parity7a[1..1].q)) # ((! cnt_en) & parity6.q)); 62 | parity6.prn = (! aclr); 63 | parity6.sclr = sclr; 64 | sub_parity7a[].clk = ( clock, clock); 65 | sub_parity7a[].clrn = ( (! aclr), (! aclr)); 66 | sub_parity7a[].d = ( ((cnt_en & ((counter5a[6..6].q $ counter5a[7..7].q) $ counter5a[8..8].q)) # ((! cnt_en) & sub_parity7a[1].q)), ((cnt_en & (((((counter5a[0..0].q $ counter5a[1..1].q) $ counter5a[2..2].q) $ counter5a[3..3].q) $ counter5a[4..4].q) $ counter5a[5..5].q)) # ((! cnt_en) & sub_parity7a[0].q))); 67 | sub_parity7a[].sclr = ( sclr, sclr); 68 | cntr_cout[] = ( B"0", (cntr_cout[6..6] & (! counter5a[6].q)), (cntr_cout[5..5] & (! counter5a[5].q)), (cntr_cout[4..4] & (! counter5a[4].q)), (cntr_cout[3..3] & (! counter5a[3].q)), (cntr_cout[2..2] & (! counter5a[2].q)), (cntr_cout[1..1] & (! counter5a[1].q)), (cntr_cout[0..0] & (! counter5a[0].q)), (cnt_en & parity_cout)); 69 | parity_cout = (((! parity6.q) $ updown) & cnt_en); 70 | q[] = counter5a[8..0].q; 71 | sclr = GND; 72 | updown = VCC; 73 | END; 74 | --VALID FILE 75 | -------------------------------------------------------------------------------- /db/alt_synch_pipe_0ol.tdf: -------------------------------------------------------------------------------- 1 | --dffpipe DELAY=2 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW 2 | --VERSION_BEGIN 18.0 cbx_a_gray2bin 2018:04:24:18:04:18:SJ cbx_a_graycounter 2018:04:24:18:04:18:SJ cbx_altdpram 2018:04:24:18:04:18:SJ cbx_altera_counter 2018:04:24:18:04:18:SJ cbx_altera_gray_counter 2018:04:24:18:04:18:SJ cbx_altera_syncram 2018:04:24:18:04:18:SJ cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_dcfifo 2018:04:24:18:04:18:SJ cbx_fifo_common 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_scfifo 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | FUNCTION dffpipe_hd9 (clock, clrn, d[8..0]) 21 | RETURNS ( q[8..0]); 22 | 23 | --synthesis_resources = reg 18 24 | OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW"; 25 | 26 | SUBDESIGN alt_synch_pipe_0ol 27 | ( 28 | clock : input; 29 | clrn : input; 30 | d[8..0] : input; 31 | q[8..0] : output; 32 | ) 33 | VARIABLE 34 | dffpipe13 : dffpipe_hd9; 35 | 36 | BEGIN 37 | dffpipe13.clock = clock; 38 | dffpipe13.clrn = clrn; 39 | dffpipe13.d[] = d[]; 40 | q[] = dffpipe13.q[]; 41 | END; 42 | --VALID FILE 43 | -------------------------------------------------------------------------------- /db/alt_synch_pipe_1ol.tdf: -------------------------------------------------------------------------------- 1 | --dffpipe DELAY=2 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW 2 | --VERSION_BEGIN 18.0 cbx_a_gray2bin 2018:04:24:18:04:18:SJ cbx_a_graycounter 2018:04:24:18:04:18:SJ cbx_altdpram 2018:04:24:18:04:18:SJ cbx_altera_counter 2018:04:24:18:04:18:SJ cbx_altera_gray_counter 2018:04:24:18:04:18:SJ cbx_altera_syncram 2018:04:24:18:04:18:SJ cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_dcfifo 2018:04:24:18:04:18:SJ cbx_fifo_common 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_scfifo 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | FUNCTION dffpipe_id9 (clock, clrn, d[8..0]) 21 | RETURNS ( q[8..0]); 22 | 23 | --synthesis_resources = reg 18 24 | OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW"; 25 | 26 | SUBDESIGN alt_synch_pipe_1ol 27 | ( 28 | clock : input; 29 | clrn : input; 30 | d[8..0] : input; 31 | q[8..0] : output; 32 | ) 33 | VARIABLE 34 | dffpipe16 : dffpipe_id9; 35 | 36 | BEGIN 37 | dffpipe16.clock = clock; 38 | dffpipe16.clrn = clrn; 39 | dffpipe16.d[] = d[]; 40 | q[] = dffpipe16.q[]; 41 | END; 42 | --VALID FILE 43 | -------------------------------------------------------------------------------- /db/altsyncram_vra1.tdf: -------------------------------------------------------------------------------- 1 | --altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_B="CLEAR1" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_ECC="FALSE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=8 WIDTHAD_B=8 aclr1 address_a address_b addressstall_b clock0 clock1 data_a q_b wren_a 2 | --VERSION_BEGIN 18.0 cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 21 | WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) 22 | RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 23 | 24 | --synthesis_resources = M10K 1 25 | OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 26 | 27 | SUBDESIGN altsyncram_vra1 28 | ( 29 | aclr1 : input; 30 | address_a[7..0] : input; 31 | address_b[7..0] : input; 32 | addressstall_b : input; 33 | clock0 : input; 34 | clock1 : input; 35 | data_a[7..0] : input; 36 | q_b[7..0] : output; 37 | wren_a : input; 38 | ) 39 | VARIABLE 40 | ram_block11a0 : cyclonev_ram_block 41 | WITH ( 42 | CLK0_CORE_CLOCK_ENABLE = "ena0", 43 | CLK0_INPUT_CLOCK_ENABLE = "none", 44 | CLK1_CORE_CLOCK_ENABLE = "none", 45 | CLK1_INPUT_CLOCK_ENABLE = "none", 46 | CONNECTIVITY_CHECKING = "OFF", 47 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 48 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 49 | OPERATION_MODE = "dual_port", 50 | PORT_A_ADDRESS_WIDTH = 8, 51 | PORT_A_DATA_WIDTH = 1, 52 | PORT_A_FIRST_ADDRESS = 0, 53 | PORT_A_FIRST_BIT_NUMBER = 0, 54 | PORT_A_LAST_ADDRESS = 255, 55 | PORT_A_LOGICAL_RAM_DEPTH = 256, 56 | PORT_A_LOGICAL_RAM_WIDTH = 8, 57 | PORT_B_ADDRESS_CLEAR = "clear1", 58 | PORT_B_ADDRESS_CLOCK = "clock1", 59 | PORT_B_ADDRESS_WIDTH = 8, 60 | PORT_B_DATA_OUT_CLEAR = "none", 61 | PORT_B_DATA_WIDTH = 1, 62 | PORT_B_FIRST_ADDRESS = 0, 63 | PORT_B_FIRST_BIT_NUMBER = 0, 64 | PORT_B_LAST_ADDRESS = 255, 65 | PORT_B_LOGICAL_RAM_DEPTH = 256, 66 | PORT_B_LOGICAL_RAM_WIDTH = 8, 67 | PORT_B_READ_ENABLE_CLOCK = "clock1", 68 | RAM_BLOCK_TYPE = "AUTO" 69 | ); 70 | ram_block11a1 : cyclonev_ram_block 71 | WITH ( 72 | CLK0_CORE_CLOCK_ENABLE = "ena0", 73 | CLK0_INPUT_CLOCK_ENABLE = "none", 74 | CLK1_CORE_CLOCK_ENABLE = "none", 75 | CLK1_INPUT_CLOCK_ENABLE = "none", 76 | CONNECTIVITY_CHECKING = "OFF", 77 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 78 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 79 | OPERATION_MODE = "dual_port", 80 | PORT_A_ADDRESS_WIDTH = 8, 81 | PORT_A_DATA_WIDTH = 1, 82 | PORT_A_FIRST_ADDRESS = 0, 83 | PORT_A_FIRST_BIT_NUMBER = 1, 84 | PORT_A_LAST_ADDRESS = 255, 85 | PORT_A_LOGICAL_RAM_DEPTH = 256, 86 | PORT_A_LOGICAL_RAM_WIDTH = 8, 87 | PORT_B_ADDRESS_CLEAR = "clear1", 88 | PORT_B_ADDRESS_CLOCK = "clock1", 89 | PORT_B_ADDRESS_WIDTH = 8, 90 | PORT_B_DATA_OUT_CLEAR = "none", 91 | PORT_B_DATA_WIDTH = 1, 92 | PORT_B_FIRST_ADDRESS = 0, 93 | PORT_B_FIRST_BIT_NUMBER = 1, 94 | PORT_B_LAST_ADDRESS = 255, 95 | PORT_B_LOGICAL_RAM_DEPTH = 256, 96 | PORT_B_LOGICAL_RAM_WIDTH = 8, 97 | PORT_B_READ_ENABLE_CLOCK = "clock1", 98 | RAM_BLOCK_TYPE = "AUTO" 99 | ); 100 | ram_block11a2 : cyclonev_ram_block 101 | WITH ( 102 | CLK0_CORE_CLOCK_ENABLE = "ena0", 103 | CLK0_INPUT_CLOCK_ENABLE = "none", 104 | CLK1_CORE_CLOCK_ENABLE = "none", 105 | CLK1_INPUT_CLOCK_ENABLE = "none", 106 | CONNECTIVITY_CHECKING = "OFF", 107 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 108 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 109 | OPERATION_MODE = "dual_port", 110 | PORT_A_ADDRESS_WIDTH = 8, 111 | PORT_A_DATA_WIDTH = 1, 112 | PORT_A_FIRST_ADDRESS = 0, 113 | PORT_A_FIRST_BIT_NUMBER = 2, 114 | PORT_A_LAST_ADDRESS = 255, 115 | PORT_A_LOGICAL_RAM_DEPTH = 256, 116 | PORT_A_LOGICAL_RAM_WIDTH = 8, 117 | PORT_B_ADDRESS_CLEAR = "clear1", 118 | PORT_B_ADDRESS_CLOCK = "clock1", 119 | PORT_B_ADDRESS_WIDTH = 8, 120 | PORT_B_DATA_OUT_CLEAR = "none", 121 | PORT_B_DATA_WIDTH = 1, 122 | PORT_B_FIRST_ADDRESS = 0, 123 | PORT_B_FIRST_BIT_NUMBER = 2, 124 | PORT_B_LAST_ADDRESS = 255, 125 | PORT_B_LOGICAL_RAM_DEPTH = 256, 126 | PORT_B_LOGICAL_RAM_WIDTH = 8, 127 | PORT_B_READ_ENABLE_CLOCK = "clock1", 128 | RAM_BLOCK_TYPE = "AUTO" 129 | ); 130 | ram_block11a3 : cyclonev_ram_block 131 | WITH ( 132 | CLK0_CORE_CLOCK_ENABLE = "ena0", 133 | CLK0_INPUT_CLOCK_ENABLE = "none", 134 | CLK1_CORE_CLOCK_ENABLE = "none", 135 | CLK1_INPUT_CLOCK_ENABLE = "none", 136 | CONNECTIVITY_CHECKING = "OFF", 137 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 138 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 139 | OPERATION_MODE = "dual_port", 140 | PORT_A_ADDRESS_WIDTH = 8, 141 | PORT_A_DATA_WIDTH = 1, 142 | PORT_A_FIRST_ADDRESS = 0, 143 | PORT_A_FIRST_BIT_NUMBER = 3, 144 | PORT_A_LAST_ADDRESS = 255, 145 | PORT_A_LOGICAL_RAM_DEPTH = 256, 146 | PORT_A_LOGICAL_RAM_WIDTH = 8, 147 | PORT_B_ADDRESS_CLEAR = "clear1", 148 | PORT_B_ADDRESS_CLOCK = "clock1", 149 | PORT_B_ADDRESS_WIDTH = 8, 150 | PORT_B_DATA_OUT_CLEAR = "none", 151 | PORT_B_DATA_WIDTH = 1, 152 | PORT_B_FIRST_ADDRESS = 0, 153 | PORT_B_FIRST_BIT_NUMBER = 3, 154 | PORT_B_LAST_ADDRESS = 255, 155 | PORT_B_LOGICAL_RAM_DEPTH = 256, 156 | PORT_B_LOGICAL_RAM_WIDTH = 8, 157 | PORT_B_READ_ENABLE_CLOCK = "clock1", 158 | RAM_BLOCK_TYPE = "AUTO" 159 | ); 160 | ram_block11a4 : cyclonev_ram_block 161 | WITH ( 162 | CLK0_CORE_CLOCK_ENABLE = "ena0", 163 | CLK0_INPUT_CLOCK_ENABLE = "none", 164 | CLK1_CORE_CLOCK_ENABLE = "none", 165 | CLK1_INPUT_CLOCK_ENABLE = "none", 166 | CONNECTIVITY_CHECKING = "OFF", 167 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 168 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 169 | OPERATION_MODE = "dual_port", 170 | PORT_A_ADDRESS_WIDTH = 8, 171 | PORT_A_DATA_WIDTH = 1, 172 | PORT_A_FIRST_ADDRESS = 0, 173 | PORT_A_FIRST_BIT_NUMBER = 4, 174 | PORT_A_LAST_ADDRESS = 255, 175 | PORT_A_LOGICAL_RAM_DEPTH = 256, 176 | PORT_A_LOGICAL_RAM_WIDTH = 8, 177 | PORT_B_ADDRESS_CLEAR = "clear1", 178 | PORT_B_ADDRESS_CLOCK = "clock1", 179 | PORT_B_ADDRESS_WIDTH = 8, 180 | PORT_B_DATA_OUT_CLEAR = "none", 181 | PORT_B_DATA_WIDTH = 1, 182 | PORT_B_FIRST_ADDRESS = 0, 183 | PORT_B_FIRST_BIT_NUMBER = 4, 184 | PORT_B_LAST_ADDRESS = 255, 185 | PORT_B_LOGICAL_RAM_DEPTH = 256, 186 | PORT_B_LOGICAL_RAM_WIDTH = 8, 187 | PORT_B_READ_ENABLE_CLOCK = "clock1", 188 | RAM_BLOCK_TYPE = "AUTO" 189 | ); 190 | ram_block11a5 : cyclonev_ram_block 191 | WITH ( 192 | CLK0_CORE_CLOCK_ENABLE = "ena0", 193 | CLK0_INPUT_CLOCK_ENABLE = "none", 194 | CLK1_CORE_CLOCK_ENABLE = "none", 195 | CLK1_INPUT_CLOCK_ENABLE = "none", 196 | CONNECTIVITY_CHECKING = "OFF", 197 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 198 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 199 | OPERATION_MODE = "dual_port", 200 | PORT_A_ADDRESS_WIDTH = 8, 201 | PORT_A_DATA_WIDTH = 1, 202 | PORT_A_FIRST_ADDRESS = 0, 203 | PORT_A_FIRST_BIT_NUMBER = 5, 204 | PORT_A_LAST_ADDRESS = 255, 205 | PORT_A_LOGICAL_RAM_DEPTH = 256, 206 | PORT_A_LOGICAL_RAM_WIDTH = 8, 207 | PORT_B_ADDRESS_CLEAR = "clear1", 208 | PORT_B_ADDRESS_CLOCK = "clock1", 209 | PORT_B_ADDRESS_WIDTH = 8, 210 | PORT_B_DATA_OUT_CLEAR = "none", 211 | PORT_B_DATA_WIDTH = 1, 212 | PORT_B_FIRST_ADDRESS = 0, 213 | PORT_B_FIRST_BIT_NUMBER = 5, 214 | PORT_B_LAST_ADDRESS = 255, 215 | PORT_B_LOGICAL_RAM_DEPTH = 256, 216 | PORT_B_LOGICAL_RAM_WIDTH = 8, 217 | PORT_B_READ_ENABLE_CLOCK = "clock1", 218 | RAM_BLOCK_TYPE = "AUTO" 219 | ); 220 | ram_block11a6 : cyclonev_ram_block 221 | WITH ( 222 | CLK0_CORE_CLOCK_ENABLE = "ena0", 223 | CLK0_INPUT_CLOCK_ENABLE = "none", 224 | CLK1_CORE_CLOCK_ENABLE = "none", 225 | CLK1_INPUT_CLOCK_ENABLE = "none", 226 | CONNECTIVITY_CHECKING = "OFF", 227 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 228 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 229 | OPERATION_MODE = "dual_port", 230 | PORT_A_ADDRESS_WIDTH = 8, 231 | PORT_A_DATA_WIDTH = 1, 232 | PORT_A_FIRST_ADDRESS = 0, 233 | PORT_A_FIRST_BIT_NUMBER = 6, 234 | PORT_A_LAST_ADDRESS = 255, 235 | PORT_A_LOGICAL_RAM_DEPTH = 256, 236 | PORT_A_LOGICAL_RAM_WIDTH = 8, 237 | PORT_B_ADDRESS_CLEAR = "clear1", 238 | PORT_B_ADDRESS_CLOCK = "clock1", 239 | PORT_B_ADDRESS_WIDTH = 8, 240 | PORT_B_DATA_OUT_CLEAR = "none", 241 | PORT_B_DATA_WIDTH = 1, 242 | PORT_B_FIRST_ADDRESS = 0, 243 | PORT_B_FIRST_BIT_NUMBER = 6, 244 | PORT_B_LAST_ADDRESS = 255, 245 | PORT_B_LOGICAL_RAM_DEPTH = 256, 246 | PORT_B_LOGICAL_RAM_WIDTH = 8, 247 | PORT_B_READ_ENABLE_CLOCK = "clock1", 248 | RAM_BLOCK_TYPE = "AUTO" 249 | ); 250 | ram_block11a7 : cyclonev_ram_block 251 | WITH ( 252 | CLK0_CORE_CLOCK_ENABLE = "ena0", 253 | CLK0_INPUT_CLOCK_ENABLE = "none", 254 | CLK1_CORE_CLOCK_ENABLE = "none", 255 | CLK1_INPUT_CLOCK_ENABLE = "none", 256 | CONNECTIVITY_CHECKING = "OFF", 257 | LOGICAL_RAM_NAME = "ALTSYNCRAM", 258 | MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 259 | OPERATION_MODE = "dual_port", 260 | PORT_A_ADDRESS_WIDTH = 8, 261 | PORT_A_DATA_WIDTH = 1, 262 | PORT_A_FIRST_ADDRESS = 0, 263 | PORT_A_FIRST_BIT_NUMBER = 7, 264 | PORT_A_LAST_ADDRESS = 255, 265 | PORT_A_LOGICAL_RAM_DEPTH = 256, 266 | PORT_A_LOGICAL_RAM_WIDTH = 8, 267 | PORT_B_ADDRESS_CLEAR = "clear1", 268 | PORT_B_ADDRESS_CLOCK = "clock1", 269 | PORT_B_ADDRESS_WIDTH = 8, 270 | PORT_B_DATA_OUT_CLEAR = "none", 271 | PORT_B_DATA_WIDTH = 1, 272 | PORT_B_FIRST_ADDRESS = 0, 273 | PORT_B_FIRST_BIT_NUMBER = 7, 274 | PORT_B_LAST_ADDRESS = 255, 275 | PORT_B_LOGICAL_RAM_DEPTH = 256, 276 | PORT_B_LOGICAL_RAM_WIDTH = 8, 277 | PORT_B_READ_ENABLE_CLOCK = "clock1", 278 | RAM_BLOCK_TYPE = "AUTO" 279 | ); 280 | address_a_wire[7..0] : WIRE; 281 | address_b_wire[7..0] : WIRE; 282 | 283 | BEGIN 284 | ram_block11a[7..0].clk0 = clock0; 285 | ram_block11a[7..0].clk1 = clock1; 286 | ram_block11a[7..0].clr1 = aclr1; 287 | ram_block11a[7..0].ena0 = wren_a; 288 | ram_block11a[7..0].portaaddr[] = ( address_a_wire[7..0]); 289 | ram_block11a[0].portadatain[] = ( data_a[0..0]); 290 | ram_block11a[1].portadatain[] = ( data_a[1..1]); 291 | ram_block11a[2].portadatain[] = ( data_a[2..2]); 292 | ram_block11a[3].portadatain[] = ( data_a[3..3]); 293 | ram_block11a[4].portadatain[] = ( data_a[4..4]); 294 | ram_block11a[5].portadatain[] = ( data_a[5..5]); 295 | ram_block11a[6].portadatain[] = ( data_a[6..6]); 296 | ram_block11a[7].portadatain[] = ( data_a[7..7]); 297 | ram_block11a[7..0].portawe = wren_a; 298 | ram_block11a[7..0].portbaddr[] = ( address_b_wire[7..0]); 299 | ram_block11a[7..0].portbaddrstall = addressstall_b; 300 | ram_block11a[7..0].portbre = B"11111111"; 301 | address_a_wire[] = address_a[]; 302 | address_b_wire[] = address_b[]; 303 | q_b[] = ( ram_block11a[7..0].portbdataout[0..0]); 304 | END; 305 | --VALID FILE 306 | -------------------------------------------------------------------------------- /db/cmpr_1v5.tdf: -------------------------------------------------------------------------------- 1 | --lpm_compare DEVICE_FAMILY="Cyclone V" LPM_WIDTH=9 aeb dataa datab 2 | --VERSION_BEGIN 18.0 cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN cmpr_1v5 23 | ( 24 | aeb : output; 25 | dataa[8..0] : input; 26 | datab[8..0] : input; 27 | ) 28 | VARIABLE 29 | aeb_result_wire[0..0] : WIRE; 30 | aneb_result_wire[0..0] : WIRE; 31 | data_wire[24..0] : WIRE; 32 | eq_wire : WIRE; 33 | 34 | BEGIN 35 | aeb = eq_wire; 36 | aeb_result_wire[] = (! aneb_result_wire[]); 37 | aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]); 38 | data_wire[] = ( datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[23..23] $ data_wire[24..24]), ((data_wire[19..19] $ data_wire[20..20]) # (data_wire[21..21] $ data_wire[22..22])), ((data_wire[15..15] $ data_wire[16..16]) # (data_wire[17..17] $ data_wire[18..18])), ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), data_wire[6..6], (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5])); 39 | eq_wire = aeb_result_wire[]; 40 | END; 41 | --VALID FILE 42 | -------------------------------------------------------------------------------- /db/dcfifo_70p1.tdf: -------------------------------------------------------------------------------- 1 | --dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="ON" LPM_WIDTH=8 LPM_WIDTH_R=8 LPM_WIDTHU=8 LPM_WIDTHU_R=8 OVERFLOW_CHECKING="ON" RDSYNC_DELAYPIPE=4 UNDERFLOW_CHECKING="ON" USE_EAB="ON" WRITE_ACLR_SYNCH="OFF" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 2 | --VERSION_BEGIN 18.0 cbx_a_gray2bin 2018:04:24:18:04:18:SJ cbx_a_graycounter 2018:04:24:18:04:18:SJ cbx_altdpram 2018:04:24:18:04:18:SJ cbx_altera_counter 2018:04:24:18:04:18:SJ cbx_altera_gray_counter 2018:04:24:18:04:18:SJ cbx_altera_syncram 2018:04:24:18:04:18:SJ cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_dcfifo 2018:04:24:18:04:18:SJ cbx_fifo_common 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_scfifo 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | FUNCTION a_gray2bin_g9b (gray[8..0]) 21 | RETURNS ( bin[8..0]); 22 | FUNCTION a_graycounter_fu6 (aclr, clock, cnt_en) 23 | RETURNS ( q[8..0]); 24 | FUNCTION a_graycounter_bcc (aclr, clock, cnt_en) 25 | RETURNS ( q[8..0]); 26 | FUNCTION altsyncram_vra1 (aclr1, address_a[7..0], address_b[7..0], addressstall_b, clock0, clock1, data_a[7..0], wren_a) 27 | RETURNS ( q_b[7..0]); 28 | FUNCTION dffpipe_gd9 (clock, clrn, d[8..0]) 29 | RETURNS ( q[8..0]); 30 | FUNCTION alt_synch_pipe_0ol (clock, clrn, d[8..0]) 31 | RETURNS ( q[8..0]); 32 | FUNCTION alt_synch_pipe_1ol (clock, clrn, d[8..0]) 33 | RETURNS ( q[8..0]); 34 | FUNCTION cmpr_1v5 (dataa[8..0], datab[8..0]) 35 | RETURNS ( aeb); 36 | 37 | --synthesis_resources = lut 10 M10K 1 reg 105 38 | OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe_id9:dffpipe16|dffe17a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe16|dffe17a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_hd9:dffpipe13|dffe14a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe13|dffe14a* """; 39 | 40 | SUBDESIGN dcfifo_70p1 41 | ( 42 | aclr : input; 43 | data[7..0] : input; 44 | q[7..0] : output; 45 | rdclk : input; 46 | rdempty : output; 47 | rdreq : input; 48 | rdusedw[7..0] : output; 49 | wrclk : input; 50 | wrfull : output; 51 | wrreq : input; 52 | ) 53 | VARIABLE 54 | rdptr_g_gray2bin : a_gray2bin_g9b; 55 | rs_dgwp_gray2bin : a_gray2bin_g9b; 56 | rdptr_g1p : a_graycounter_fu6; 57 | wrptr_g1p : a_graycounter_bcc; 58 | fifo_ram : altsyncram_vra1; 59 | delayed_wrptr_g[8..0] : dffe; 60 | rdptr_g[8..0] : dffe; 61 | wrptr_g[8..0] : dffe 62 | WITH ( 63 | power_up = "low" 64 | ); 65 | rs_brp : dffpipe_gd9; 66 | rs_bwp : dffpipe_gd9; 67 | rs_dgwp : alt_synch_pipe_0ol; 68 | ws_dgrp : alt_synch_pipe_1ol; 69 | rdusedw_sub_dataa[8..0] : WIRE; 70 | rdusedw_sub_datab[8..0] : WIRE; 71 | rdusedw_sub_result[8..0] : WIRE; 72 | rdempty_eq_comp : cmpr_1v5; 73 | wrfull_eq_comp : cmpr_1v5; 74 | int_rdempty : WIRE; 75 | int_wrfull : WIRE; 76 | ram_address_a[7..0] : WIRE; 77 | ram_address_b[7..0] : WIRE; 78 | valid_rdreq : WIRE; 79 | valid_wrreq : WIRE; 80 | wrptr_gs[8..0] : WIRE; 81 | 82 | BEGIN 83 | rdptr_g_gray2bin.gray[8..0] = rdptr_g[8..0].q; 84 | rs_dgwp_gray2bin.gray[8..0] = rs_dgwp.q[8..0]; 85 | rdptr_g1p.aclr = aclr; 86 | rdptr_g1p.clock = rdclk; 87 | rdptr_g1p.cnt_en = valid_rdreq; 88 | wrptr_g1p.aclr = aclr; 89 | wrptr_g1p.clock = wrclk; 90 | wrptr_g1p.cnt_en = valid_wrreq; 91 | fifo_ram.aclr1 = aclr; 92 | fifo_ram.address_a[] = ram_address_a[]; 93 | fifo_ram.address_b[] = ram_address_b[]; 94 | fifo_ram.addressstall_b = (! valid_rdreq); 95 | fifo_ram.clock0 = wrclk; 96 | fifo_ram.clock1 = rdclk; 97 | fifo_ram.data_a[] = data[]; 98 | fifo_ram.wren_a = valid_wrreq; 99 | delayed_wrptr_g[].clk = wrclk; 100 | delayed_wrptr_g[].clrn = (! aclr); 101 | delayed_wrptr_g[].d = wrptr_g[].q; 102 | rdptr_g[].clk = rdclk; 103 | rdptr_g[].clrn = (! aclr); 104 | rdptr_g[].d = rdptr_g1p.q[]; 105 | rdptr_g[].ena = valid_rdreq; 106 | wrptr_g[].clk = wrclk; 107 | wrptr_g[].clrn = (! aclr); 108 | wrptr_g[].d = wrptr_g1p.q[]; 109 | wrptr_g[].ena = valid_wrreq; 110 | rs_brp.clock = rdclk; 111 | rs_brp.clrn = (! aclr); 112 | rs_brp.d[] = rdptr_g_gray2bin.bin[]; 113 | rs_bwp.clock = rdclk; 114 | rs_bwp.clrn = (! aclr); 115 | rs_bwp.d[] = rs_dgwp_gray2bin.bin[]; 116 | rs_dgwp.clock = rdclk; 117 | rs_dgwp.clrn = (! aclr); 118 | rs_dgwp.d[] = delayed_wrptr_g[].q; 119 | ws_dgrp.clock = wrclk; 120 | ws_dgrp.clrn = (! aclr); 121 | ws_dgrp.d[] = rdptr_g[].q; 122 | rdusedw_sub_result[] = rdusedw_sub_dataa[] - rdusedw_sub_datab[]; 123 | rdusedw_sub_dataa[] = rs_bwp.q[]; 124 | rdusedw_sub_datab[] = rs_brp.q[]; 125 | rdempty_eq_comp.dataa[] = rs_dgwp.q[]; 126 | rdempty_eq_comp.datab[] = rdptr_g[].q; 127 | wrfull_eq_comp.dataa[] = ws_dgrp.q[]; 128 | wrfull_eq_comp.datab[] = wrptr_gs[]; 129 | int_rdempty = rdempty_eq_comp.aeb; 130 | int_wrfull = wrfull_eq_comp.aeb; 131 | q[] = fifo_ram.q_b[]; 132 | ram_address_a[] = ( (wrptr_g[8..8].q $ wrptr_g[7..7].q), wrptr_g[6..0].q); 133 | ram_address_b[] = ( (rdptr_g1p.q[8..8] $ rdptr_g1p.q[7..7]), rdptr_g1p.q[6..0]); 134 | rdempty = int_rdempty; 135 | rdusedw[] = ( rdusedw_sub_result[7..0]); 136 | valid_rdreq = (rdreq & (! int_rdempty)); 137 | valid_wrreq = (wrreq & (! int_wrfull)); 138 | wrfull = int_wrfull; 139 | wrptr_gs[] = ( (! wrptr_g[8..8].q), (! wrptr_g[7..7].q), wrptr_g[6..0].q); 140 | END; 141 | --VALID FILE 142 | -------------------------------------------------------------------------------- /db/dffpipe_gd9.tdf: -------------------------------------------------------------------------------- 1 | --dffpipe DELAY=1 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 2 | --VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = reg 9 22 | OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; 23 | 24 | SUBDESIGN dffpipe_gd9 25 | ( 26 | clock : input; 27 | clrn : input; 28 | d[8..0] : input; 29 | q[8..0] : output; 30 | ) 31 | VARIABLE 32 | dffe12a[8..0] : dffe; 33 | ena : NODE; 34 | prn : NODE; 35 | sclr : NODE; 36 | 37 | BEGIN 38 | dffe12a[].clk = clock; 39 | dffe12a[].clrn = clrn; 40 | dffe12a[].d = (d[] & (! sclr)); 41 | dffe12a[].ena = ena; 42 | dffe12a[].prn = prn; 43 | ena = VCC; 44 | prn = VCC; 45 | q[] = dffe12a[].q; 46 | sclr = GND; 47 | END; 48 | --VALID FILE 49 | -------------------------------------------------------------------------------- /db/dffpipe_hd9.tdf: -------------------------------------------------------------------------------- 1 | --dffpipe DELAY=2 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 2 | --VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = reg 18 22 | OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; 23 | 24 | SUBDESIGN dffpipe_hd9 25 | ( 26 | clock : input; 27 | clrn : input; 28 | d[8..0] : input; 29 | q[8..0] : output; 30 | ) 31 | VARIABLE 32 | dffe14a[8..0] : dffe; 33 | dffe15a[8..0] : dffe; 34 | ena : NODE; 35 | prn : NODE; 36 | sclr : NODE; 37 | 38 | BEGIN 39 | dffe14a[].clk = clock; 40 | dffe14a[].clrn = clrn; 41 | dffe14a[].d = (d[] & (! sclr)); 42 | dffe14a[].ena = ena; 43 | dffe14a[].prn = prn; 44 | dffe15a[].clk = clock; 45 | dffe15a[].clrn = clrn; 46 | dffe15a[].d = (dffe14a[].q & (! sclr)); 47 | dffe15a[].ena = ena; 48 | dffe15a[].prn = prn; 49 | ena = VCC; 50 | prn = VCC; 51 | q[] = dffe15a[].q; 52 | sclr = GND; 53 | END; 54 | --VALID FILE 55 | -------------------------------------------------------------------------------- /db/dffpipe_id9.tdf: -------------------------------------------------------------------------------- 1 | --dffpipe DELAY=2 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF 2 | --VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 6 | -- Your use of Intel Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Intel Program License 12 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 13 | -- the Intel FPGA IP License Agreement, or other applicable license 14 | -- agreement, including, without limitation, that your use is for 15 | -- the sole purpose of programming logic devices manufactured by 16 | -- Intel and sold by Intel or its authorized distributors. Please 17 | -- refer to the applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = reg 18 22 | OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; 23 | 24 | SUBDESIGN dffpipe_id9 25 | ( 26 | clock : input; 27 | clrn : input; 28 | d[8..0] : input; 29 | q[8..0] : output; 30 | ) 31 | VARIABLE 32 | dffe17a[8..0] : dffe; 33 | dffe18a[8..0] : dffe; 34 | ena : NODE; 35 | prn : NODE; 36 | sclr : NODE; 37 | 38 | BEGIN 39 | dffe17a[].clk = clock; 40 | dffe17a[].clrn = clrn; 41 | dffe17a[].d = (d[] & (! sclr)); 42 | dffe17a[].ena = ena; 43 | dffe17a[].prn = prn; 44 | dffe18a[].clk = clock; 45 | dffe18a[].clrn = clrn; 46 | dffe18a[].d = (dffe17a[].q & (! sclr)); 47 | dffe18a[].ena = ena; 48 | dffe18a[].prn = prn; 49 | ena = VCC; 50 | prn = VCC; 51 | q[] = dffe18a[].q; 52 | sclr = GND; 53 | END; 54 | --VALID FILE 55 | -------------------------------------------------------------------------------- /incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/MAINFILE.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 2 | Version_Index = 469919232 3 | Creation_Time = Thu Oct 25 23:28:08 2018 4 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/MAINFILE.root_partition.cmp.ammdb: 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input [31:0] total_dur; 17 | 18 | output reg PWM; 19 | reg [31:0] tick; 20 | 21 | always @ (posedge clk or negedge reset_n) 22 | begin 23 | if (~reset_n) 24 | begin 25 | tick <= 0; 26 | end 27 | else if (tick >= total_dur) 28 | begin 29 | tick <= 0; 30 | end 31 | else 32 | tick <= tick + 1; 33 | end 34 | 35 | 36 | always @ (posedge clk or negedge reset_n) 37 | begin 38 | if (~reset_n) 39 | PWM <= 0; 40 | else 41 | PWM <= (tick < high_dur)?1'b1:1'b0;//duck die width(5us)250 42 | end 43 | 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /ip/ServoControl.v: -------------------------------------------------------------------------------- 1 | 2 | //======================================================= 3 | // This code is generated by Terasic System Builder 4 | //======================================================= 5 | 6 | module ServoControl( 7 | 8 | //////////// CLOCK ////////// 9 | input FPGA_CLK1_50, 10 | input FPGA_CLK2_50, 11 | input FPGA_CLK3_50, 12 | 13 | //////////// KEY ////////// 14 | input [7:0] KEY, 15 | 16 | //////////// LED ////////// 17 | output [7:0] LED, 18 | 19 | //////////// SW ////////// 20 | input [3:0] SW, 21 | 22 | 23 | //////////// GPIO_1, GPIO connect to GPIO Default ////////// 24 | inout [5:0] GPIO_1 25 | ); 26 | 27 | 28 | //======================================================= 29 | // REG/WIRE declarations 30 | //======================================================= 31 | wire [7:0] Angle; 32 | wire Pwm_0; 33 | wire RESET_N; 34 | 35 | //======================================================= 36 | // Structural coding 37 | //======================================================= 38 | assign GPIO_1[0] = Pwm_0; 39 | assign GPIO_1[2] = Pwm_0; 40 | assign GPIO_1[4] = Pwm_0; 41 | 42 | 43 | assign RESET_N = 1;// ~SW[2]; 44 | 45 | UI h0( 46 | 47 | .iClk ( FPGA_CLK1_50 ), 48 | .iRst_n( RESET_N ), 49 | .iKey ( KEY[7:0]), 50 | .iSW ( SW[1:0] ), 51 | .oAngle( Angle ) 52 | 53 | ); 54 | 55 | 56 | 57 | 58 | `define DUR_CLOCK_NUM ( 50000000/50) // clock count in 20 ms 59 | `define DEGREE_MAX ( `DUR_CLOCK_NUM*25/200) // 2.5 ms 125000 60 | `define DEGREE_MIN ( `DUR_CLOCK_NUM*5/200) // 0.5 ms 25000 61 | wire [31:0] PwmAngle; 62 | assign PwmAngle = (((`DEGREE_MAX - `DEGREE_MIN)/180)*Angle)+`DEGREE_MIN; 63 | 64 | 65 | PWM_Geneator p0( 66 | .clk ( FPGA_CLK1_50 ), 67 | .reset_n ( RESET_N ), 68 | // 69 | .high_dur ( PwmAngle ), 70 | .total_dur( `DUR_CLOCK_NUM ), 71 | // 72 | .PWM ( Pwm_0 ) 73 | ); 74 | 75 | 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /ip/ServoControl.v.bak: -------------------------------------------------------------------------------- 1 | 2 | //======================================================= 3 | // This code is generated by Terasic System Builder 4 | //======================================================= 5 | 6 | module DE10_NANO_SMK_RTL( 7 | 8 | //////////// CLOCK ////////// 9 | input FPGA_CLK1_50, 10 | input FPGA_CLK2_50, 11 | input FPGA_CLK3_50, 12 | 13 | //////////// KEY ////////// 14 | input [1:0] KEY, 15 | 16 | //////////// LED ////////// 17 | output [7:0] LED, 18 | 19 | //////////// SW ////////// 20 | input [3:0] SW, 21 | 22 | //////////// GPIO_0, GPIO connect to GPIO Default ////////// 23 | inout [35:0] GPIO_0, 24 | 25 | //////////// GPIO_1, GPIO connect to GPIO Default ////////// 26 | inout [35:0] GPIO_1 27 | ); 28 | 29 | 30 | //======================================================= 31 | // REG/WIRE declarations 32 | //======================================================= 33 | wire [7:0] Angle; 34 | wire Pwm_0; 35 | wire RESET_N; 36 | 37 | //======================================================= 38 | // Structural coding 39 | //======================================================= 40 | assign GPIO_1[0] = Pwm_0; 41 | assign GPIO_1[2] = Pwm_0; 42 | assign GPIO_1[4] = Pwm_0; 43 | 44 | assign LED [0] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 45 | assign LED [1] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 46 | assign LED [2] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 47 | assign LED [3] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 48 | assign LED [4] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 49 | assign LED [5] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 50 | assign LED [6] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 51 | assign LED [7] = (Angle == 8'd180)?1'b1:(Angle == 0)?1'b0:Pwm_0; 52 | 53 | assign RESET_N = 1;// ~SW[2]; 54 | 55 | UI h0( 56 | 57 | .iClk ( FPGA_CLK1_50 ), 58 | .iRst_n( RESET_N ), 59 | .iKey ( KEY[1:0]), 60 | .iSW ( SW[1:0] ), 61 | .oAngle( Angle ) 62 | 63 | ); 64 | 65 | 66 | 67 | 68 | `define DUR_CLOCK_NUM ( 50000000/50) // clock count in 20 ms 69 | `define DEGREE_MAX ( `DUR_CLOCK_NUM*25/200) // 2.5 ms 125000 70 | `define DEGREE_MIN ( `DUR_CLOCK_NUM*5/200) // 0.5 ms 25000 71 | wire [31:0] PwmAngle; 72 | assign PwmAngle = (((`DEGREE_MAX - `DEGREE_MIN)/180)*Angle)+`DEGREE_MIN; 73 | 74 | 75 | PWM_Geneator p0( 76 | .clk ( FPGA_CLK1_50 ), 77 | .reset_n ( RESET_N ), 78 | // 79 | .high_dur ( PwmAngle ), 80 | .total_dur( `DUR_CLOCK_NUM ), 81 | // 82 | .PWM ( Pwm_0 ) 83 | ); 84 | 85 | 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /ip/UI.v: -------------------------------------------------------------------------------- 1 | module UI( iClk,iRst_n,iKey,iSW, 2 | oAngle, oClock 3 | ); 4 | 5 | input iClk; 6 | input iRst_n; 7 | input [7:0] iKey; // input key for rith or left 8 | input [1:0] iSW; // speed control 9 | output reg [7:0] oAngle; // Orientation angle 10 | output reg [7:0] oClock; // Orientation angle 11 | 12 | `define AdjAngle 5 // base movement step 13 | `define MAX_Angle 180 14 | `define MIN_Angle 0 15 | reg [2:0] speed; // ??? 16 | reg [7:0] tAngle; // Target Angle 17 | reg [21:0] count; 18 | 19 | 20 | 21 | always@(posedge iClk or negedge iRst_n) 22 | begin 23 | if(!iRst_n) 24 | begin 25 | oAngle <= 8'd60; 26 | speed <= 3'b010; 27 | count <= 0; 28 | end 29 | else 30 | begin 31 | case(iKey) 32 | 33 | 34 | // Position Control 35 | 8'd0:begin 36 | tAngle <= 0; 37 | end 38 | 8'd1:begin 39 | tAngle <= 30; 40 | end 41 | 8'd2:begin 42 | tAngle <= 60; 43 | end 44 | 8'd3:begin 45 | tAngle <= 90; 46 | end 47 | 8'd4:begin 48 | tAngle <= 120; 49 | end 50 | 8'd5:begin 51 | tAngle <= 150; 52 | end 53 | 8'd6:begin 54 | tAngle <= 180; 55 | end 56 | 57 | // Speed Control 58 | 8'd7:begin 59 | speed <= 3'b000; 60 | end 61 | 8'd8:begin 62 | speed <= 3'b001; 63 | end 64 | 8'd9:begin 65 | speed <= 3'b111; 66 | end 67 | 68 | default:begin 69 | speed <= 3'b010; 70 | tAngle <= 8'd60; 71 | end 72 | endcase 73 | 74 | 75 | 76 | if (oAngle == tAngle) 77 | begin 78 | oAngle <= tAngle; 79 | end 80 | else if (oAngle < tAngle) 81 | begin 82 | if(count[21] & (oAngle != `MAX_Angle)) 83 | begin 84 | count <= 0; 85 | oAngle <= oAngle + `AdjAngle; 86 | end 87 | else 88 | count <= count + speed + 1; 89 | end 90 | else if (oAngle > tAngle) 91 | begin 92 | if(count[21] & (oAngle != `MIN_Angle)) 93 | begin 94 | count <= 0; 95 | oAngle <= oAngle - `AdjAngle; 96 | end 97 | else 98 | count <= count + speed + 1; 99 | end 100 | 101 | end 102 | end 103 | 104 | endmodule -------------------------------------------------------------------------------- /ip/UI.v.bak: -------------------------------------------------------------------------------- 1 | module UI( iClk,iRst_n,iKey,iSW, 2 | oAngle 3 | ); 4 | 5 | input iClk; 6 | input iRst_n; 7 | input [1:0] iKey; // input key for rith or left 8 | input [1:0] iSW; // speed control 9 | output reg [7:0] oAngle; // Orientation angle 10 | 11 | `define AdjAngle 5 // base movement step 12 | `define MAX_Angle 180 13 | `define MIN_Angle 0 14 | reg [21:0] count; // ??? 15 | 16 | 17 | 18 | always@(posedge iClk or negedge iRst_n) 19 | begin 20 | if(!iRst_n) 21 | begin 22 | oAngle <= 8'd60; 23 | count <= 0; 24 | end 25 | else 26 | begin 27 | case(iKey) 28 | 2'b10:begin 29 | //if(count[21] & (oAngle != `MAX_Angle)) 30 | //begin 31 | //count <= 0; 32 | oAngle <= 45; //oAngle + `AdjAngle; 33 | //end 34 | //else 35 | //count <= count + iSW + 1; 36 | end 37 | 2'b01:begin 38 | //if(count[21] & (oAngle != `MIN_Angle)) 39 | //begin 40 | // count <= 0; 41 | oAngle <= 180;//oAngle - `AdjAngle; 42 | // end 43 | //else 44 | // count <= count + iSW + 1; 45 | end 46 | 2'b00:begin 47 | oAngle <= 8'd90; 48 | end 49 | 50 | default: count <= 0; 51 | endcase 52 | end 53 | end 54 | 55 | endmodule -------------------------------------------------------------------------------- /motorControl.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 21 | # Date created = 23:19:48 October 25, 2018 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "23:19:48 October 25, 2018" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "MAINFILE" 31 | -------------------------------------------------------------------------------- /motorControl.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "Cyclone V" 6 | set_global_assignment -name DEVICE 5CSEBA6U23I7 7 | set_global_assignment -name TOP_LEVEL_ENTITY MAINFILE 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.0.2" 9 | set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:03:46 MAY 31,2017" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 14 | 15 | 16 | #============================================================ 17 | # KEY 18 | #============================================================ 19 | set_location_assignment PIN_AH17 -to KEY[0] 20 | set_location_assignment PIN_AH16 -to KEY[1] 21 | 22 | #============================================================ 23 | # LED 24 | #============================================================ 25 | set_location_assignment PIN_W15 -to LED[0] 26 | set_location_assignment PIN_AA24 -to LED[1] 27 | set_location_assignment PIN_V16 -to LED[2] 28 | set_location_assignment PIN_V15 -to LED[3] 29 | set_location_assignment PIN_AF26 -to LED[4] 30 | set_location_assignment PIN_AE26 -to LED[5] 31 | set_location_assignment PIN_Y16 -to LED[6] 32 | set_location_assignment PIN_AA23 -to LED[7] 33 | 34 | #============================================================ 35 | # SW 36 | #============================================================ 37 | set_location_assignment PIN_Y24 -to SW[0] 38 | set_location_assignment PIN_W24 -to SW[1] 39 | set_location_assignment PIN_W21 -to SW[2] 40 | set_location_assignment PIN_W20 -to SW[3] 41 | 42 | #============================================================ 43 | # GPIO_0, GPIO connect to RFS - RF and Sensor 44 | #============================================================ 45 | set_location_assignment PIN_AF4 -to BT_KEY 46 | set_location_assignment PIN_C12 -to BT_UART_RX 47 | 48 | 49 | #============================================================ 50 | # End of pin assignments by Terasic System Builder 51 | #============================================================ 52 | 53 | 54 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 55 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 56 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 57 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 58 | set_global_assignment -name VERILOG_FILE ip/ServoControl.v 59 | set_global_assignment -name VERILOG_FILE ip/UI.v 60 | set_global_assignment -name VERILOG_FILE ip/PWM_Geneator.v 61 | set_global_assignment -name VERILOG_FILE uart/uart_fifo.v 62 | set_global_assignment -name VERILOG_FILE uart/uart_control.v 63 | set_global_assignment -name VERILOG_FILE uart/async_transmitter.v 64 | set_global_assignment -name VERILOG_FILE uart/async_receiver.v 65 | set_global_assignment -name VERILOG_FILE DE10_NANO_Bluetooth_Slave.v 66 | set_global_assignment -name SDC_FILE DE10_NANO_Bluetooth_Slave.SDC 67 | set_location_assignment PIN_Y15 -to GPIO_1[0] 68 | set_location_assignment PIN_AC24 -to GPIO_1[1] 69 | set_location_assignment PIN_AA15 -to GPIO_1[2] 70 | set_location_assignment PIN_AD26 -to GPIO_1[3] 71 | set_location_assignment PIN_AG28 -to GPIO_1[4] 72 | set_location_assignment PIN_AE25 -to GPIO_1[6] 73 | set_location_assignment PIN_AF28 -to GPIO_1[5] 74 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 75 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 76 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 77 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 78 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 79 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 80 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 81 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 82 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] 83 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] 84 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] 85 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] 86 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] 87 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] 88 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] 89 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] 90 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] 92 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] 94 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BT_KEY 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BT_UART_RX 96 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] 102 | set_global_assignment -name VERILOG_FILE dataEncoder.v 103 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /output_files/MAINFILE.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for MAINFILE 2 | Thu Oct 25 23:28:59 2018 3 | Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: E:/Education/ANU/OneDrive - Australian National University/ENGN8537 Embedded Sys nd Real Time DSP/Project/Coding/Final/output_files/MAINFILE.sof 14 | 6. Assembler Messages 15 | 16 | 17 | 18 | ---------------- 19 | ; Legal Notice ; 20 | ---------------- 21 | Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | Your use of Intel Corporation's design tools, logic functions 23 | and other software and tools, and its AMPP partner logic 24 | functions, and any output files from any of the foregoing 25 | (including device programming or simulation files), and any 26 | associated documentation or information are expressly subject 27 | to the terms and conditions of the Intel Program License 28 | Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | the Intel FPGA IP License Agreement, or other applicable license 30 | agreement, including, without limitation, that your use is for 31 | the sole purpose of programming logic devices manufactured by 32 | Intel and sold by Intel or its authorized distributors. Please 33 | refer to the applicable agreement for further details. 34 | 35 | 36 | 37 | +---------------------------------------------------------------+ 38 | ; Assembler Summary ; 39 | +-----------------------+---------------------------------------+ 40 | ; Assembler Status ; Successful - Thu Oct 25 23:28:59 2018 ; 41 | ; Revision Name ; MAINFILE ; 42 | ; Top-level Entity Name ; MAINFILE ; 43 | ; Family ; Cyclone V ; 44 | ; Device ; 5CSEBA6U23I7 ; 45 | +-----------------------+---------------------------------------+ 46 | 47 | 48 | +----------------------------------+ 49 | ; Assembler Settings ; 50 | +--------+---------+---------------+ 51 | ; Option ; Setting ; Default Value ; 52 | +--------+---------+---------------+ 53 | 54 | 55 | +--------------------------------------------------------------------------------------------------------------------------------------------------+ 56 | ; Assembler Generated Files ; 57 | +--------------------------------------------------------------------------------------------------------------------------------------------------+ 58 | ; File Name ; 59 | +--------------------------------------------------------------------------------------------------------------------------------------------------+ 60 | ; E:/Education/ANU/OneDrive - Australian National University/ENGN8537 Embedded Sys nd Real Time DSP/Project/Coding/Final/output_files/MAINFILE.sof ; 61 | +--------------------------------------------------------------------------------------------------------------------------------------------------+ 62 | 63 | 64 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 65 | ; Assembler Device Options: E:/Education/ANU/OneDrive - Australian National University/ENGN8537 Embedded Sys nd Real Time DSP/Project/Coding/Final/output_files/MAINFILE.sof ; 66 | +----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ 67 | ; Option ; Setting ; 68 | +----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ 69 | ; JTAG usercode ; 0x00B1848C ; 70 | ; Checksum ; 0x00B1848C ; 71 | +----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ 72 | 73 | 74 | +--------------------+ 75 | ; Assembler Messages ; 76 | +--------------------+ 77 | Info: ******************************************************************* 78 | Info: Running Quartus Prime Assembler 79 | Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 80 | Info: Processing started: Thu Oct 25 23:28:52 2018 81 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off motorControl -c MAINFILE 82 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 83 | Info (115030): Assembler is generating device programming files 84 | Info: Quartus Prime Assembler was successful. 0 errors, 1 warning 85 | Info: Peak virtual memory: 4851 megabytes 86 | Info: Processing ended: Thu Oct 25 23:28:59 2018 87 | Info: Elapsed time: 00:00:07 88 | Info: Total CPU time (on all processors): 00:00:07 89 | 90 | 91 | -------------------------------------------------------------------------------- /output_files/MAINFILE.done: -------------------------------------------------------------------------------- 1 | Thu Oct 25 23:37:34 2018 2 | -------------------------------------------------------------------------------- /output_files/MAINFILE.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176236): Started Fast Input/Output/OE register processing 2 | Extra Info (176237): Finished Fast Input/Output/OE register processing 3 | Extra Info (176238): Start inferring scan chains for DSP blocks 4 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 5 | Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density 6 | Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks 7 | -------------------------------------------------------------------------------- /output_files/MAINFILE.fit.summary: -------------------------------------------------------------------------------- 1 | I/O Assignment Analysis Status : Successful - Thu Oct 25 23:37:17 2018 2 | Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Lite Edition 3 | Revision Name : MAINFILE 4 | Top-level Entity Name : MAINFILE 5 | Family : Cyclone V 6 | Device : 5CSEBA6U23I7 7 | Timing Models : Final 8 | Total pins : 26 / 314 ( 8 % ) 9 | Total virtual pins : 0 10 | Total PLLs : 0 / 6 ( 0 % ) 11 | Total DLLs : 0 / 4 ( 0 % ) 12 | -------------------------------------------------------------------------------- /output_files/MAINFILE.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for MAINFILE 2 | Thu Oct 25 23:37:17 2018 3 | Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 2018 Intel Corporation. All rights reserved. 25 | Your use of Intel Corporation's design tools, logic functions 26 | and other software and tools, and its AMPP partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Intel Program License 31 | Subscription Agreement, the Intel Quartus Prime License Agreement, 32 | the Intel FPGA IP License Agreement, or other applicable license 33 | agreement, including, without limitation, that your use is for 34 | the sole purpose of programming logic devices manufactured by 35 | Intel and sold by Intel or its authorized distributors. Please 36 | refer to the applicable agreement for further details. 37 | 38 | 39 | 40 | +-------------------------------------------------------------------------------+ 41 | ; Flow Summary ; 42 | +---------------------------------+---------------------------------------------+ 43 | ; Flow Status ; Successful - Thu Oct 25 23:37:17 2018 ; 44 | ; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Lite Edition ; 45 | ; Revision Name ; MAINFILE ; 46 | ; Top-level Entity Name ; MAINFILE ; 47 | ; Family ; Cyclone V ; 48 | ; Device ; 5CSEBA6U23I7 ; 49 | ; Timing Models ; Final ; 50 | ; Logic utilization (in ALMs) ; 56 / 41,910 ( < 1 % ) ; 51 | ; Total registers ; 63 ; 52 | ; Total pins ; 26 / 314 ( 8 % ) ; 53 | ; Total virtual pins ; 0 ; 54 | ; Total block memory bits ; 0 / 5,662,720 ( 0 % ) ; 55 | ; Total DSP Blocks ; 1 / 112 ( < 1 % ) ; 56 | ; Total HSSI RX PCSs ; 0 ; 57 | ; Total HSSI PMA RX Deserializers ; 0 ; 58 | ; Total HSSI TX PCSs ; 0 ; 59 | ; Total HSSI PMA TX Serializers ; 0 ; 60 | ; Total PLLs ; 0 / 6 ( 0 % ) ; 61 | ; Total DLLs ; 0 / 4 ( 0 % ) ; 62 | +---------------------------------+---------------------------------------------+ 63 | 64 | 65 | +-----------------------------------------+ 66 | ; Flow Settings ; 67 | +-------------------+---------------------+ 68 | ; Option ; Setting ; 69 | +-------------------+---------------------+ 70 | ; Start date & time ; 10/25/2018 23:27:57 ; 71 | ; Main task ; Compilation ; 72 | ; Revision Name ; MAINFILE ; 73 | +-------------------+---------------------+ 74 | 75 | 76 | +-------------------------------------------------------------------------------------------------------------------------+ 77 | ; Flow Non-Default Global Settings ; 78 | +-------------------------------------+----------------------------------------+---------------+-------------+------------+ 79 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 80 | +-------------------------------------+----------------------------------------+---------------+-------------+------------+ 81 | ; COMPILER_SIGNATURE_ID ; 189794991065907.154047047713724 ; -- ; -- ; -- ; 82 | ; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ; 83 | ; MIN_CORE_JUNCTION_TEMP ; -40 ; -- ; -- ; -- ; 84 | ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; 85 | ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; 86 | ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; 87 | ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; 88 | ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; 89 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 90 | +-------------------------------------+----------------------------------------+---------------+-------------+------------+ 91 | 92 | 93 | +-----------------------------------------------------------------------------------------------------------------------------+ 94 | ; Flow Elapsed Time ; 95 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 96 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 97 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 98 | ; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 4868 MB ; 00:00:27 ; 99 | ; Fitter ; 00:00:40 ; 1.0 ; 6664 MB ; 00:01:13 ; 100 | ; Assembler ; 00:00:07 ; 1.0 ; 4851 MB ; 00:00:07 ; 101 | ; Timing Analyzer ; 00:00:07 ; 1.1 ; 5194 MB ; 00:00:06 ; 102 | ; I/O Assignment Analysis ; 00:00:15 ; 1.0 ; 5490 MB ; 00:00:15 ; 103 | ; I/O Assignment Analysis ; 00:00:15 ; 1.0 ; 5481 MB ; 00:00:15 ; 104 | ; Total ; 00:01:37 ; -- ; -- ; 00:02:23 ; 105 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 106 | 107 | 108 | +---------------------------------------------------------------------------------------+ 109 | ; Flow OS Summary ; 110 | +-------------------------+------------------+------------+------------+----------------+ 111 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 112 | +-------------------------+------------------+------------+------------+----------------+ 113 | ; Analysis & Synthesis ; JAVED ; Windows 10 ; 10.0 ; x86_64 ; 114 | ; Fitter ; JAVED ; Windows 10 ; 10.0 ; x86_64 ; 115 | ; Assembler ; JAVED ; Windows 10 ; 10.0 ; x86_64 ; 116 | ; Timing Analyzer ; JAVED ; Windows 10 ; 10.0 ; x86_64 ; 117 | ; I/O Assignment Analysis ; JAVED ; Windows 10 ; 10.0 ; x86_64 ; 118 | ; I/O Assignment Analysis ; JAVED ; Windows 10 ; 10.0 ; x86_64 ; 119 | +-------------------------+------------------+------------+------------+----------------+ 120 | 121 | 122 | ------------ 123 | ; Flow Log ; 124 | ------------ 125 | quartus_map --read_settings_files=on --write_settings_files=off motorControl -c MAINFILE 126 | quartus_fit --read_settings_files=off --write_settings_files=off motorControl -c MAINFILE 127 | quartus_asm --read_settings_files=off --write_settings_files=off motorControl -c MAINFILE 128 | quartus_sta motorControl -c MAINFILE 129 | quartus_fit --read_settings_files=on --write_settings_files=off motorControl -c MAINFILE --plan 130 | quartus_fit --read_settings_files=on --write_settings_files=off motorControl -c MAINFILE --plan 131 | 132 | 133 | 134 | -------------------------------------------------------------------------------- /output_files/MAINFILE.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /output_files/MAINFILE.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Thu Oct 25 23:28:09 2018 2 | Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Lite Edition 3 | Revision Name : MAINFILE 4 | Top-level Entity Name : MAINFILE 5 | Family : Cyclone V 6 | Logic utilization (in ALMs) : N/A 7 | Total registers : 63 8 | Total pins : 26 9 | Total virtual pins : 0 10 | Total block memory bits : 0 11 | Total DSP Blocks : 1 12 | Total HSSI RX PCSs : 0 13 | Total HSSI PMA RX Deserializers : 0 14 | Total HSSI TX PCSs : 0 15 | Total HSSI PMA TX Serializers : 0 16 | Total PLLs : 0 17 | Total DLLs : 0 18 | -------------------------------------------------------------------------------- /output_files/MAINFILE.pin: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details. 14 | -- 15 | -- This is a Quartus Prime output file. It is for reporting purposes only, and is 16 | -- not intended for use as a Quartus Prime input file. This file cannot be used 17 | -- to make Quartus Prime pin assignments - for instructions on how to make pin 18 | -- assignments, please see Quartus Prime help. 19 | --------------------------------------------------------------------------------- 20 | 21 | 22 | 23 | --------------------------------------------------------------------------------- 24 | -- NC : No Connect. This pin has no internal connection to the device. 25 | -- DNU : Do Not Use. This pin MUST NOT be connected. 26 | -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device. 27 | -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V). 28 | -- VCCIO : Dedicated power pin, which MUST be connected to VCC 29 | -- of its bank. 30 | -- Bank 3A: 2.5V 31 | -- Bank 3B: 3.3V 32 | -- Bank 4A: 3.3V 33 | -- Bank 5A: 3.3V 34 | -- Bank 5B: 3.3V 35 | -- Bank 6B: 2.5V 36 | -- Bank 6A: 2.5V 37 | -- Bank 7A: 2.5V 38 | -- Bank 7B: 2.5V 39 | -- Bank 7C: 2.5V 40 | -- Bank 7D: 2.5V 41 | -- Bank 8A: 3.3V 42 | -- Bank 9A: Dedicated configuration pins only, no VCCIO required. 43 | -- RREF : External reference resistor for the quad, MUST be connected to 44 | -- GND via a 2k Ohm resistor. 45 | -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. 46 | -- It can also be used to report unused dedicated pins. The connection 47 | -- on the board for unused dedicated pins depends on whether this will 48 | -- be used in a future design. One example is device migration. When 49 | -- using device migration, refer to the device pin-tables. If it is a 50 | -- GND pin in the pin table or if it will not be used in a future design 51 | -- for another purpose the it MUST be connected to GND. If it is an unused 52 | -- dedicated pin, then it can be connected to a valid signal on the board 53 | -- (low, high, or toggling) if that signal is required for a different 54 | -- revision of the design. 55 | -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. 56 | -- This pin should be connected to GND. It may also be connected to a 57 | -- valid signal on the board (low, high, or toggling) if that signal 58 | -- is required for a different revision of the design. 59 | -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND 60 | -- or leave it unconnected. 61 | -- RESERVED : Unused I/O pin, which MUST be left unconnected. 62 | -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. 63 | -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. 64 | -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. 65 | -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. 66 | -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin 67 | -- must not be connected. 68 | --------------------------------------------------------------------------------- 69 | 70 | 71 | 72 | --------------------------------------------------------------------------------- 73 | -- Pin directions (input, output or bidir) are based on device operating in user mode. 74 | --------------------------------------------------------------------------------- 75 | 76 | Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition 77 | CHIP "MAINFILE" ASSIGNED TO AN: 5CSEBA6U23I7 78 | 79 | Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment 80 | ------------------------------------------------------------------------------------------------------------- 81 | DNU : A2 : : : : : 82 | GND : A3 : gnd : : : : 83 | RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 7C : 84 | RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 7C : 85 | RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 7B : 86 | RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7B : 87 | RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7B : 88 | RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7B : 89 | GND : A10 : gnd : : : : 90 | RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7B : 91 | RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7B : 92 | RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7B : 93 | RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7B : 94 | RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7B : 95 | RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7B : 96 | RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A : 97 | RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A : 98 | RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A : 99 | RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7A : 100 | RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A : 101 | RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A : 102 | HPS_nRST : A23 : : : : 7A : 103 | RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 6A : 104 | RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 6A : 105 | RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 6A : 106 | RESERVED_INPUT_WITH_WEAK_PULLUP : A27 : : : : 6A : 107 | GND : AA1 : gnd : : : : 108 | GND : AA2 : gnd : : : : 109 | GND : AA3 : gnd : : : : 110 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3A : 111 | VCCIO3A : AA5 : power : : 2.5V : 3A : 112 | nCSO, DATA4 : AA6 : : : : 3A : 113 | DCLK : AA8 : : : : 3A : 114 | GND : AA9 : gnd : : : : 115 | VCCPD3A : AA10 : power : : 2.5V : 3A : 116 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 3A : 117 | VCCIO3B : AA12 : power : : 3.3V : 3B : 118 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4A : 119 | VCCPD3B4A : AA14 : power : : 3.3V : 3B, 4A : 120 | GPIO_1[2] : AA15 : bidir : 3.3-V LVTTL : : 4A : Y 121 | VCCIO4A : AA16 : power : : 3.3V : 4A : 122 | GND : AA17 : gnd : : : : 123 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : 124 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A : 125 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 5A : 126 | VCCA_FPLL : AA21 : power : : 2.5V : : 127 | LED[7] : AA23 : output : 3.3-V LVTTL : : 5A : Y 128 | LED[1] : AA24 : output : 3.3-V LVTTL : : 5A : Y 129 | VREFB5BN0 : AA25 : power : : : 5B : 130 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : 131 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA27 : : : : 6B : 132 | RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 6B : 133 | GND : AB1 : gnd : : : : 134 | GND : AB2 : gnd : : : : 135 | GND : AB3 : gnd : : : : 136 | RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3A : 137 | TCK : AB5 : input : : : 3A : 138 | AS_DATA3, DATA3 : AB6 : : : : 3A : 139 | RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A : 140 | GND : AB24 : gnd : : : : 141 | RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B : 142 | RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B : 143 | GND : AB27 : gnd : : : : 144 | RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 6B : 145 | GND : AC1 : gnd : : : : 146 | GND : AC2 : gnd : : : : 147 | GND : AC3 : gnd : : : : 148 | RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 3A : 149 | AS_DATA2, DATA2 : AC5 : : : : 3A : 150 | AS_DATA1, DATA1 : AC6 : : : : 3A : 151 | TMS : AC7 : input : : : 3A : 152 | VCC_AUX : AC8 : power : : 2.5V : : 153 | VCC_AUX : AC21 : power : : 2.5V : : 154 | RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A : 155 | RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A : 156 | GPIO_1[1] : AC24 : bidir : 3.3-V LVTTL : : 5A : Y 157 | VCCIO5A : AC25 : power : : 3.3V : 5A : 158 | VREFB5AN0 : AC26 : power : : : 5A : 159 | RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 6B : 160 | RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 6B : 161 | DNU : AD1 : : : : : 162 | DNU : AD2 : : : : : 163 | GND : AD3 : gnd : : : : 164 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3A : 165 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3A : 166 | GND : AD6 : gnd : : : : 167 | AS_DATA0, ASDO, DATA0 : AD7 : : : : 3A : 168 | GND : AD8 : gnd : : : : 169 | VCCPD3B4A : AD9 : power : : 3.3V : 3B, 4A : 170 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3B : 171 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3B : 172 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3B : 173 | VCCPD3B4A : AD13 : power : : 3.3V : 3B, 4A : 174 | GND : AD14 : gnd : : : : 175 | VCC_AUX : AD15 : power : : 2.5V : : 176 | VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A : 177 | BT_UART_TX : AD17 : output : 3.3-V LVTTL : : 4A : Y 178 | VCCPD3B4A : AD18 : power : : 3.3V : 3B, 4A : 179 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A : 180 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : 181 | VCCPD3B4A : AD21 : power : : 3.3V : 3B, 4A : 182 | GND : AD22 : gnd : : : : 183 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A : 184 | VCCPGM : AD24 : power : : 1.8V/2.5V/3.0V/3.3V : : 185 | GND : AD25 : gnd : : : : 186 | GPIO_1[3] : AD26 : bidir : 3.3-V LVTTL : : 5A : Y 187 | VCCIO6B_HPS : AD27 : power : : 2.5V : 6B : 188 | RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 6B : 189 | GND : AE1 : gnd : : : : 190 | GND : AE2 : gnd : : : : 191 | GND : AE3 : gnd : : : : 192 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3B : 193 | VREFB3AN0 : AE5 : power : : : 3A : 194 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3A : 195 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3B : 196 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : 197 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : 198 | VCCIO3B : AE10 : power : : 3.3V : 3B : 199 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3B : 200 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3B : 201 | VCCIO3B : AE13 : power : : 3.3V : 3B : 202 | DNU : AE14 : : : : : 203 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : 204 | GND : AE16 : gnd : : : : 205 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A : 206 | GND : AE18 : gnd : : : : 207 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : 208 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : 209 | VCCIO4A : AE21 : power : : 3.3V : 4A : 210 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A : 211 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : 212 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : 213 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 5A : 214 | LED[5] : AE26 : output : 3.3-V LVTTL : : 5A : Y 215 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 6B : 216 | RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 6B : 217 | GND : AF1 : gnd : : : : 218 | GND : AF2 : gnd : : : : 219 | GND : AF3 : gnd : : : : 220 | BT_KEY : AF4 : bidir : 3.3-V LVTTL : : 3B : Y 221 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3B : 222 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : 223 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : 224 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : 225 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : 226 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3B : 227 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B : 228 | VREFB3BN0 : AF12 : power : : : 3B : 229 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : 230 | VCCIO4A : AF14 : power : : 3.3V : 4A : 231 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4A : 232 | VREFB4AN0 : AF16 : power : : : 4A : 233 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : 234 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : 235 | VCCIO4A : AF19 : power : : 3.3V : 4A : 236 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A : 237 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : 238 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : 239 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : 240 | GND : AF24 : gnd : : : : 241 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A : 242 | LED[4] : AF26 : output : 3.3-V LVTTL : : 5A : Y 243 | RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 4A : 244 | GPIO_1[5] : AF28 : bidir : 3.3-V LVTTL : : 4A : Y 245 | GND : AG1 : gnd : : : : 246 | GND : AG2 : gnd : : : : 247 | GND : AG3 : gnd : : : : 248 | VCCIO3B : AG4 : power : : 3.3V : 3B : 249 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3B : 250 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3B : 251 | GND : AG7 : gnd : : : : 252 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 4A : 253 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG9 : : : : 4A : 254 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 4A : 255 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 4A : 256 | VCCIO4A : AG12 : power : : 3.3V : 4A : 257 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 4A : 258 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG14 : : : : 4A : 259 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 4A : 260 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A : 261 | GND : AG17 : gnd : : : : 262 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A : 263 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4A : 264 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A : 265 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A : 266 | VCCIO4A : AG22 : power : : 3.3V : 4A : 267 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A : 268 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG24 : : : : 4A : 269 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A : 270 | RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A : 271 | GND : AG27 : gnd : : : : 272 | GPIO_1[4] : AG28 : bidir : 3.3-V LVTTL : : 4A : Y 273 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3B : 274 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3B : 275 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3B : 276 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3B : 277 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3B : 278 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 4A : 279 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 4A : 280 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 4A : 281 | GND : AH10 : gnd : : : : 282 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 4A : 283 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 4A : 284 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 4A : 285 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 4A : 286 | VCCIO4A : AH15 : power : : 3.3V : 4A : 287 | KEY[1] : AH16 : input : 3.3-V LVTTL : : 4A : Y 288 | KEY[0] : AH17 : input : 3.3-V LVTTL : : 4A : Y 289 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A : 290 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A : 291 | GND : AH20 : gnd : : : : 292 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4A : 293 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A : 294 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A : 295 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A : 296 | VCCIO4A : AH25 : power : : 3.3V : 4A : 297 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4A : 298 | RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A : 299 | GND : B1 : : : : : 300 | DNU : B2 : : : : : 301 | GND : B3 : gnd : : : : 302 | RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 7C : 303 | GND : B5 : gnd : : : : 304 | RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 7C : 305 | GND : B7 : gnd : : : : 306 | RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7C : 307 | RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7C : 308 | VCCIO7C_HPS : B10 : power : : 2.5V : 7C : 309 | RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7C : 310 | RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7C : 311 | VCCIO7B_HPS : B13 : power : : 2.5V : 7B : 312 | RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7B : 313 | GND : B15 : gnd : : : : 314 | RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7A : 315 | GND : B17 : gnd : : : : 316 | RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7A : 317 | RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A : 318 | GND : B20 : gnd : : : : 319 | RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A : 320 | GND : B22 : gnd : : : : 321 | HPS_TDO : B23 : : : : 7A : 322 | RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 6A : 323 | GND : B25 : gnd : : : : 324 | RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A : 325 | GND : B27 : gnd : : : : 326 | RESERVED_INPUT_WITH_WEAK_PULLUP : B28 : : : : 6A : 327 | GND : C1 : gnd : : : : 328 | GND : C2 : gnd : : : : 329 | GND : C3 : gnd : : : : 330 | RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 7D : 331 | RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 7D : 332 | RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 7D : 333 | RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 7D : 334 | RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 7D : 335 | RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7D : 336 | RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7D : 337 | GND : C11 : gnd : : : : 338 | BT_UART_RX : C12 : input : 3.3-V LVTTL : : 8A : Y 339 | RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7C : 340 | RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7B : 341 | RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7B : 342 | RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7A : 343 | RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A : 344 | RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A : 345 | RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A : 346 | VCCIO7A_HPS : C20 : power : : 2.5V : 7A : 347 | RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7A : 348 | HPS_TRST : C22 : : : : 7A : 349 | HPS_TMS : C23 : : : : 7A : 350 | RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 6A : 351 | VCCIO6A_HPS : C25 : power : : 2.5V : 6A : 352 | RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 6A : 353 | VCCIO6A_HPS : C27 : power : : 2.5V : 6A : 354 | RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A : 355 | DNU : D1 : : : : : 356 | DNU : D2 : : : : : 357 | GND : D3 : gnd : : : : 358 | RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 7D : 359 | RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 7D : 360 | VCCIO7D_HPS : D6 : power : : 2.5V : 7D : 361 | VCCBAT : D7 : power : : 1.2V : : 362 | RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8A : 363 | VREFB8AN0 : D9 : power : : : 8A : 364 | GND : D10 : gnd : : : : 365 | RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A : 366 | RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A : 367 | GND : D13 : gnd : : : : 368 | RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7C : 369 | RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7B : 370 | GND : D16 : gnd : : : : 371 | RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7B : 372 | VCCIO7A_HPS : D18 : power : : 2.5V : 7A : 373 | VREFB7A7B7C7DN0_HPS : D19 : power : : : 7A, 7B, 7C, 7D : 374 | HPS_CLK2 : D20 : : : : 7A : 375 | GND : D21 : : : : 7A : 376 | HPS_TDI : D22 : : : : 7A : 377 | DNU : D23 : : : : : 378 | RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 6A : 379 | HPS_RZQ_0 : D25 : : : : 6A : 380 | RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A : 381 | RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6A : 382 | RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6A : 383 | GND : E1 : gnd : : : : 384 | GND : E2 : gnd : : : : 385 | GND : E3 : gnd : : : : 386 | RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 7D : 387 | RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 7D : 388 | nCE : E6 : : : : 9A : 389 | VCCIO8A : E7 : power : : 3.3V : 8A : 390 | RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A : 391 | GND : E9 : gnd : : : : 392 | VCCPD8A : E10 : power : : 3.3V : 8A : 393 | FPGA_CLK3_50 : E11 : input : 3.3-V LVTTL : : 8A : Y 394 | DNU : E12 : : : : : 395 | VCCPD7D_HPS : E13 : power : : 2.5V : 7D : 396 | VCCPD7C_HPS : E14 : power : : 2.5V : 7C : 397 | VCC_AUX : E15 : power : : 2.5V : : 398 | RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7B : 399 | VCCPD7B_HPS : E17 : power : : 2.5V : 7B : 400 | HPS_PORSEL : E18 : : : : 7A : 401 | GND : E19 : gnd : : : : 402 | HPS_CLK1 : E20 : : : : 7A : 403 | VCCPD7A_HPS : E21 : power : : 2.5V : 7A : 404 | GND : E22 : gnd : : : : 405 | GND : E23 : : : : 7A : 406 | GND : E24 : gnd : : : : 407 | RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A : 408 | RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A : 409 | GND : E27 : gnd : : : : 410 | RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A : 411 | GND : F1 : gnd : : : : 412 | GND : F2 : gnd : : : : 413 | GND : F3 : gnd : : : : 414 | RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 7D : 415 | RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 7D : 416 | GND : F6 : : : : 9A : 417 | nCONFIG : F7 : : : : 9A : 418 | VCC_AUX : F8 : power : : 2.5V : : 419 | VCC_AUX_SHARED : F21 : power : : 2.5V : : 420 | VCCRSTCLK_HPS : F22 : power : : 1.8V/2.5V/3.0V/3.3V : : 421 | GND : F23 : : : : 7A : 422 | RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A : 423 | RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6A : 424 | RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A : 425 | VCCIO6A_HPS : F27 : power : : 2.5V : 6A : 426 | RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A : 427 | GND : G1 : gnd : : : : 428 | GND : G2 : gnd : : : : 429 | GND : G3 : gnd : : : : 430 | RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 7D : 431 | VCCIO7D_HPS : G5 : power : : 2.5V : 7D : 432 | MSEL2 : G6 : : : : 9A : 433 | RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6A : 434 | VCCIO6A_HPS : G24 : power : : 2.5V : 6A : 435 | RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A : 436 | RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A : 437 | RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A : 438 | RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A : 439 | DNU : H1 : : : : : 440 | DNU : H2 : : : : : 441 | GND : H3 : gnd : : : : 442 | GND : H4 : gnd : : : : 443 | GND : H5 : gnd : : : : 444 | GND : H6 : gnd : : : : 445 | nSTATUS : H8 : : : : 9A : 446 | MSEL1 : H9 : : : : 9A : 447 | VCCPGM : H10 : power : : 1.8V/2.5V/3.0V/3.3V : : 448 | GND : H11 : gnd : : : : 449 | RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7C : 450 | RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7C : 451 | VCCIO7B_HPS : H14 : power : : 2.5V : 7B : 452 | GND : H15 : gnd : : : : 453 | RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7B : 454 | RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A : 455 | GND : H18 : gnd : : : : 456 | HPS_nPOR : H19 : : : : 7A : 457 | GND : H20 : gnd : : : : 458 | VCCIO6A_HPS : H21 : power : : 2.5V : 6A : 459 | VCCPLL_HPS : H23 : power : : 2.5V : : 460 | GND : H24 : gnd : : : : 461 | RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A : 462 | VCCIO6A_HPS : H26 : power : : 2.5V : 6A : 463 | GND : H27 : gnd : : : : 464 | RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A : 465 | GND : J1 : gnd : : : : 466 | GND : J2 : gnd : : : : 467 | GND : J3 : gnd : : : : 468 | VCCA_FPLL : J4 : power : : 2.5V : : 469 | GND : J5 : gnd : : : : 470 | CONF_DONE : J8 : : : : 9A : 471 | GND : J9 : gnd : : : : 472 | MSEL0 : J10 : : : : 9A : 473 | VCC : J11 : power : : 1.1V : : 474 | RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7B : 475 | RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7B : 476 | RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 7B : 477 | RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7B : 478 | RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7B : 479 | RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7A : 480 | RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 7A : 481 | VCCRSTCLK_HPS : J19 : : : : 7A : 482 | RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A : 483 | RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A : 484 | RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A : 485 | RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A : 486 | RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A : 487 | RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A : 488 | RESERVED_INPUT_WITH_WEAK_PULLUP : J28 : : : : 6A : 489 | GND : K1 : gnd : : : : 490 | GND : K2 : gnd : : : : 491 | GND : K3 : gnd : : : : 492 | GND : K4 : gnd : : : : 493 | VCCA_FPLL : K5 : power : : 2.5V : : 494 | GND : K8 : gnd : : : : 495 | MSEL4 : K9 : : : : 9A : 496 | MSEL3 : K10 : : : : 9A : 497 | GND : K11 : gnd : : : : 498 | GND : K12 : gnd : : : : 499 | VCC : K13 : power : : 1.1V : : 500 | GND : K14 : gnd : : : : 501 | VCC : K15 : power : : 1.1V : : 502 | GND : K16 : gnd : : : : 503 | VCC_HPS : K17 : power : : 1.1V : : 504 | RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 7A : 505 | HPS_TCK : K19 : : : : 7A : 506 | GND : K20 : gnd : : : : 507 | VCCPD6A6B_HPS : K21 : power : : 2.5V : 6A, 6B : 508 | VCCPD6A6B_HPS : K24 : power : : 2.5V : 6A, 6B : 509 | RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A : 510 | RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A : 511 | RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A : 512 | RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A : 513 | GND : L1 : gnd : : : : 514 | GND : L2 : gnd : : : : 515 | GND : L3 : gnd : : : : 516 | VCC : L4 : power : : 1.1V : : 517 | GND : L5 : gnd : : : : 518 | GND : L8 : gnd : : : : 519 | GND : L9 : gnd : : : : 520 | GND : L10 : gnd : : : : 521 | VCC : L11 : power : : 1.1V : : 522 | VCC : L12 : power : : 1.1V : : 523 | GND : L13 : gnd : : : : 524 | VCC : L14 : power : : 1.1V : : 525 | GND : L15 : gnd : : : : 526 | VCC_HPS : L16 : power : : 1.1V : : 527 | GND : L17 : gnd : : : : 528 | VCC_HPS : L18 : power : : 1.1V : : 529 | GND : L19 : gnd : : : : 530 | RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6A : 531 | RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6A : 532 | GND : L24 : gnd : : : : 533 | RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A : 534 | VCCIO6A_HPS : L26 : power : : 2.5V : 6A : 535 | GND : L27 : gnd : : : : 536 | RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A : 537 | DNU : M1 : : : : : 538 | DNU : M2 : : : : : 539 | GND : M3 : gnd : : : : 540 | VCCA_FPLL : M4 : power : : 2.5V : : 541 | VCC : M5 : power : : 1.1V : : 542 | GND : M8 : gnd : : : : 543 | VCC : M9 : power : : 1.1V : : 544 | GND : M10 : gnd : : : : 545 | GND : M11 : gnd : : : : 546 | VCC : M12 : power : : 1.1V : : 547 | VCC : M13 : power : : 1.1V : : 548 | GND : M14 : gnd : : : : 549 | VCC : M15 : power : : 1.1V : : 550 | GND : M16 : gnd : : : : 551 | VCC_HPS : M17 : power : : 1.1V : : 552 | VCC_HPS : M18 : power : : 1.1V : : 553 | VCC_HPS : M19 : power : : 1.1V : : 554 | GND : M20 : gnd : : : : 555 | VCCIO6A_HPS : M21 : power : : 2.5V : 6A : 556 | VCCPD6A6B_HPS : M24 : power : : 2.5V : 6A, 6B : 557 | RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A : 558 | RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A : 559 | RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A : 560 | RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A : 561 | GND : N1 : gnd : : : : 562 | GND : N2 : gnd : : : : 563 | GND : N3 : gnd : : : : 564 | GND : N4 : gnd : : : : 565 | VCC : N5 : power : : 1.1V : : 566 | GND : N8 : gnd : : : : 567 | VCC : N9 : power : : 1.1V : : 568 | VCC : N10 : power : : 1.1V : : 569 | VCC : N11 : power : : 1.1V : : 570 | VCC : N12 : power : : 1.1V : : 571 | GND : N13 : gnd : : : : 572 | VCC : N14 : power : : 1.1V : : 573 | GND : N15 : gnd : : : : 574 | VCC_HPS : N16 : power : : 1.1V : : 575 | GND : N17 : gnd : : : : 576 | VCC_HPS : N18 : power : : 1.1V : : 577 | GND : N19 : gnd : : : : 578 | RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A : 579 | RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6A : 580 | RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6B : 581 | RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6B : 582 | RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6B : 583 | RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B : 584 | RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6A : 585 | GND : P1 : gnd : : : : 586 | GND : P2 : gnd : : : : 587 | GND : P3 : gnd : : : : 588 | VCCA_FPLL : P4 : power : : 2.5V : : 589 | GND : P5 : gnd : : : : 590 | GND : P8 : gnd : : : : 591 | GND : P9 : gnd : : : : 592 | GND : P10 : gnd : : : : 593 | VCC : P11 : power : : 1.1V : : 594 | GND : P12 : gnd : : : : 595 | VCC : P13 : power : : 1.1V : : 596 | VCC : P14 : power : : 1.1V : : 597 | VCC : P15 : power : : 1.1V : : 598 | GND : P16 : gnd : : : : 599 | VCC_HPS : P17 : power : : 1.1V : : 600 | GND : P18 : gnd : : : : 601 | VCC_HPS : P19 : power : : 1.1V : : 602 | GND : P20 : gnd : : : : 603 | VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B : 604 | VCCPD6A6B_HPS : P24 : power : : 2.5V : 6A, 6B : 605 | GND : P25 : gnd : : : : 606 | RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B : 607 | VCCIO6B_HPS : P27 : power : : 2.5V : 6B : 608 | RESERVED_INPUT_WITH_WEAK_PULLUP : P28 : : : : 6A : 609 | GND : R1 : gnd : : : : 610 | GND : R2 : gnd : : : : 611 | GND : R3 : gnd : : : : 612 | VCCA_FPLL : R4 : power : : 2.5V : : 613 | VCC : R5 : power : : 1.1V : : 614 | GND : R8 : gnd : : : : 615 | VCC : R9 : power : : 1.1V : : 616 | VCC : R10 : power : : 1.1V : : 617 | GND : R11 : gnd : : : : 618 | VCC : R12 : power : : 1.1V : : 619 | GND : R13 : gnd : : : : 620 | VCC : R14 : power : : 1.1V : : 621 | GND : R15 : gnd : : : : 622 | RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 6A : 623 | RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 6A : 624 | RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6A : 625 | RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6A : 626 | RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 6A : 627 | RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6A : 628 | RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B : 629 | RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 6B : 630 | RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B : 631 | RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B : 632 | RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B : 633 | DNU : T1 : : : : : 634 | DNU : T2 : : : : : 635 | GND : T3 : gnd : : : : 636 | VCC : T4 : power : : 1.1V : : 637 | VCC : T5 : power : : 1.1V : : 638 | RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A : 639 | VCC : T9 : power : : 1.1V : : 640 | GND : T10 : gnd : : : : 641 | RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B : 642 | RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B : 643 | RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B : 644 | GND : T14 : gnd : : : : 645 | VCC : T15 : power : : 1.1V : : 646 | RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 6B : 647 | RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 6B : 648 | RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 6B : 649 | RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 6B : 650 | RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 6B : 651 | VCCIO6B_HPS : T21 : power : : 2.5V : 6B : 652 | RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B : 653 | VCCIO6B_HPS : T25 : power : : 2.5V : 6B : 654 | RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B : 655 | RESERVED_INPUT_WITH_WEAK_PULLUP : T27 : : : : 6B : 656 | RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B : 657 | GND : U1 : gnd : : : : 658 | GND : U2 : gnd : : : : 659 | GND : U3 : gnd : : : : 660 | VCCA_FPLL : U4 : power : : 2.5V : : 661 | GND : U5 : gnd : : : : 662 | DNU : U8 : : : : : 663 | RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3A : 664 | RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3A : 665 | RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : 666 | GND : U12 : gnd : : : : 667 | RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4A : 668 | RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A : 669 | RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 6B : 670 | RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 6B : 671 | GND : U17 : gnd : : : : 672 | VCCIO6B_HPS : U18 : power : : 2.5V : 6B : 673 | RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 6B : 674 | GND : U20 : gnd : : : : 675 | VCC_HPS : U21 : power : : 1.1V : : 676 | GND : U24 : gnd : : : : 677 | RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B : 678 | VCC : U26 : power : : 1.1V : : 679 | GND : U27 : gnd : : : : 680 | RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B : 681 | GND : V1 : gnd : : : : 682 | GND : V2 : gnd : : : : 683 | GND : V3 : gnd : : : : 684 | GND : V4 : gnd : : : : 685 | GND : V5 : gnd : : : : 686 | GND : V8 : gnd : : : : 687 | GND : V9 : gnd : : : : 688 | RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3A : 689 | FPGA_CLK1_50 : V11 : input : 3.3-V LVTTL : : 3B : Y 690 | RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 3B : 691 | RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : 692 | GND : V14 : gnd : : : : 693 | LED[3] : V15 : output : 3.3-V LVTTL : : 5A : Y 694 | LED[2] : V16 : output : 3.3-V LVTTL : : 5A : Y 695 | RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 6B : 696 | RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 6B : 697 | RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 6B : 698 | RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B : 699 | GND : V21 : gnd : : : : 700 | RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 6B : 701 | RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 6B : 702 | GND : V26 : gnd : : : : 703 | RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B : 704 | RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B : 705 | GND : W1 : gnd : : : : 706 | GND : W2 : gnd : : : : 707 | GND : W3 : gnd : : : : 708 | GND : W4 : gnd : : : : 709 | VCCA_FPLL : W5 : power : : 2.5V : : 710 | RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : 711 | VCCIO3A : W9 : power : : 2.5V : 3A : 712 | TDI : W10 : input : : : 3A : 713 | RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : 714 | RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 3B : 715 | VCCIO4A : W13 : power : : 3.3V : 4A : 716 | RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4A : 717 | LED[0] : W15 : output : 3.3-V LVTTL : : 5A : Y 718 | GND : W16 : gnd : : : : 719 | VCCIO5A : W17 : power : : 3.3V : 5A : 720 | GND : W18 : gnd : : : : 721 | VCCPD5B : W19 : power : : 3.3V : 5B : 722 | SW[3] : W20 : input : 3.3-V LVTTL : : 5B : Y 723 | SW[2] : W21 : input : 3.3-V LVTTL : : 5B : Y 724 | SW[1] : W24 : input : 3.3-V LVTTL : : 5B : Y 725 | VCCIO5B : W25 : power : : 3.3V : 5B : 726 | RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B : 727 | VCCIO6B_HPS : W27 : power : : 2.5V : 6B : 728 | RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 6B : 729 | DNU : Y1 : : : : : 730 | DNU : Y2 : : : : : 731 | GND : Y3 : gnd : : : : 732 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3A : 733 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3A : 734 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : 735 | TDO : Y9 : output : : : 3A : 736 | VCCPGM : Y10 : power : : 1.8V/2.5V/3.0V/3.3V : : 737 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3A : 738 | GND : Y12 : gnd : : : : 739 | FPGA_CLK2_50 : Y13 : input : 3.3-V LVTTL : : 4A : Y 740 | GND : Y14 : gnd : : : : 741 | GPIO_1[0] : Y15 : bidir : 3.3-V LVTTL : : 4A : Y 742 | LED[6] : Y16 : output : 3.3-V LVTTL : : 5A : Y 743 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 5A : 744 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 5A : 745 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 5A : 746 | GND : Y20 : gnd : : : : 747 | VCCPD5A : Y21 : power : : 3.3V : 5A : 748 | SW[0] : Y24 : input : 3.3-V LVTTL : : 5B : Y 749 | GND : Y25 : gnd : : : : 750 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 6B : 751 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 6B : 752 | RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B : 753 | -------------------------------------------------------------------------------- /output_files/MAINFILE.sld: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /output_files/MAINFILE.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/powerplayer9/Voice-Based-Motor-Control/623afa38b3a6c0c4f1ee6d5691df55cc80f3a0f9/output_files/MAINFILE.sof -------------------------------------------------------------------------------- /output_files/MAINFILE.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow 1100mV 100C Model Setup 'FPGA_CLK1_50' 6 | Slack : -6.669 7 | TNS : -263.937 8 | 9 | Type : Slow 1100mV 100C Model Hold 'FPGA_CLK1_50' 10 | Slack : 0.414 11 | TNS : 0.000 12 | 13 | Type : Slow 1100mV 100C Model Minimum Pulse Width 'FPGA_CLK1_50' 14 | Slack : -2.225 15 | TNS : -76.486 16 | 17 | Type : Slow 1100mV -40C Model Setup 'FPGA_CLK1_50' 18 | Slack : -7.049 19 | TNS : -254.252 20 | 21 | Type : Slow 1100mV -40C Model Hold 'FPGA_CLK1_50' 22 | Slack : 0.435 23 | TNS : 0.000 24 | 25 | Type : Slow 1100mV -40C Model Minimum Pulse Width 'FPGA_CLK1_50' 26 | Slack : -2.225 27 | TNS : -78.542 28 | 29 | Type : Fast 1100mV 100C Model Setup 'FPGA_CLK1_50' 30 | Slack : -2.524 31 | TNS : -92.457 32 | 33 | Type : Fast 1100mV 100C Model Hold 'FPGA_CLK1_50' 34 | Slack : 0.201 35 | TNS : 0.000 36 | 37 | Type : Fast 1100mV 100C Model Minimum Pulse Width 'FPGA_CLK1_50' 38 | Slack : -1.702 39 | TNS : -20.941 40 | 41 | Type : Fast 1100mV -40C Model Setup 'FPGA_CLK1_50' 42 | Slack : -2.302 43 | TNS : -70.850 44 | 45 | Type : Fast 1100mV -40C Model Hold 'FPGA_CLK1_50' 46 | Slack : 0.181 47 | TNS : 0.000 48 | 49 | Type : Fast 1100mV -40C Model Minimum Pulse Width 'FPGA_CLK1_50' 50 | Slack : -1.702 51 | TNS : -21.269 52 | 53 | ------------------------------------------------------------ 54 | -------------------------------------------------------------------------------- /uart/async_receiver.v: -------------------------------------------------------------------------------- 1 | // RS-232 RX module 2 | // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 3 | 4 | module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle); 5 | input clk, RxD; 6 | output RxD_data_ready; // onc clock pulse when RxD_data is valid 7 | output [7:0] RxD_data; 8 | 9 | parameter ClkFrequency = 25000000; // 25MHz 10 | parameter Baud = 115200;//baud rate setting9600 11 | 12 | // We also detect if a gap occurs in the received stream of characters 13 | // That can be useful if multiple characters are sent in burst 14 | // so that multiple characters can be treated as a "packet" 15 | output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high) 16 | output RxD_idle; // no data is being received 17 | 18 | // Baud generator (we use 8 times oversampling) 19 | parameter Baud8 = Baud*8; 20 | parameter Baud8GeneratorAccWidth = 16; 21 | wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7); 22 | reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc; 23 | always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc; 24 | wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth]; 25 | 26 | //////////////////////////// 27 | reg [1:0] RxD_sync_inv; 28 | always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD}; 29 | // we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup 30 | 31 | reg [1:0] RxD_cnt_inv; 32 | reg RxD_bit_inv; 33 | 34 | always @(posedge clk) 35 | if(Baud8Tick) 36 | begin 37 | if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1; 38 | else 39 | if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1; 40 | 41 | if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0; 42 | else 43 | if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1; 44 | end 45 | 46 | reg [3:0] state; 47 | reg [3:0] bit_spacing; 48 | 49 | // "next_bit" controls when the data sampling occurs 50 | // depending on how noisy the RxD is, different values might work better 51 | // with a clean connection, values from 8 to 11 work 52 | wire next_bit = (bit_spacing==4'd11); 53 | 54 | always @(posedge clk) 55 | if(state==0) 56 | bit_spacing <= 4'b0000; 57 | else 58 | if(Baud8Tick) 59 | bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000}; 60 | 61 | always @(posedge clk) 62 | if(Baud8Tick) 63 | case(state) 64 | 4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found? 65 | 4'b1000: if(next_bit) state <= 4'b1001; // bit 0 66 | 4'b1001: if(next_bit) state <= 4'b1010; // bit 1 67 | 4'b1010: if(next_bit) state <= 4'b1011; // bit 2 68 | 4'b1011: if(next_bit) state <= 4'b1100; // bit 3 69 | 4'b1100: if(next_bit) state <= 4'b1101; // bit 4 70 | 4'b1101: if(next_bit) state <= 4'b1110; // bit 5 71 | 4'b1110: if(next_bit) state <= 4'b1111; // bit 6 72 | 4'b1111: if(next_bit) state <= 4'b0001; // bit 7 73 | 4'b0001: if(next_bit) state <= 4'b0000; // stop bit 74 | default: state <= 4'b0000; 75 | endcase 76 | 77 | reg [7:0]RxD_data; 78 | always @(posedge RxD_data_ready) RxD_data=RxD_data_r; 79 | 80 | 81 | reg [7:0] RxD_data_r; 82 | always @(posedge clk) 83 | if(Baud8Tick && next_bit && state[3]) RxD_data_r <= {~RxD_bit_inv, RxD_data_r[7:1]}; 84 | 85 | reg RxD_data_ready, RxD_data_error; 86 | always @(posedge clk) 87 | begin 88 | RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received 89 | RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received 90 | end 91 | 92 | reg [4:0] gap_count; 93 | always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5'h01; 94 | assign RxD_idle = gap_count[4]; 95 | reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F); 96 | 97 | endmodule -------------------------------------------------------------------------------- /uart/async_receiver.v.bak: -------------------------------------------------------------------------------- 1 | // RS-232 RX module 2 | // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 3 | 4 | module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle); 5 | input clk, RxD; 6 | output RxD_data_ready; // onc clock pulse when RxD_data is valid 7 | output [7:0] RxD_data; 8 | 9 | parameter ClkFrequency = 25000000; // 25MHz 10 | parameter Baud = 115200;//baud rate setting9600 11 | 12 | // We also detect if a gap occurs in the received stream of characters 13 | // That can be useful if multiple characters are sent in burst 14 | // so that multiple characters can be treated as a "packet" 15 | output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high) 16 | output RxD_idle; // no data is being received 17 | 18 | // Baud generator (we use 8 times oversampling) 19 | parameter Baud8 = Baud*8; 20 | parameter Baud8GeneratorAccWidth = 16; 21 | wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7); 22 | reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc; 23 | always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc; 24 | wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth]; 25 | 26 | //////////////////////////// 27 | reg [1:0] RxD_sync_inv; 28 | always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD}; 29 | // we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup 30 | 31 | reg [1:0] RxD_cnt_inv; 32 | reg RxD_bit_inv; 33 | 34 | always @(posedge clk) 35 | if(Baud8Tick) 36 | begin 37 | if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1; 38 | else 39 | if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1; 40 | 41 | if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0; 42 | else 43 | if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1; 44 | end 45 | 46 | reg [3:0] state; 47 | reg [3:0] bit_spacing; 48 | 49 | // "next_bit" controls when the data sampling occurs 50 | // depending on how noisy the RxD is, different values might work better 51 | // with a clean connection, values from 8 to 11 work 52 | wire next_bit = (bit_spacing==4'd11); 53 | 54 | always @(posedge clk) 55 | if(state==0) 56 | bit_spacing <= 4'b0000; 57 | else 58 | if(Baud8Tick) 59 | bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000}; 60 | 61 | always @(posedge clk) 62 | if(Baud8Tick) 63 | case(state) 64 | 4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found? 65 | 4'b1000: if(next_bit) state <= 4'b1001; // bit 0 66 | 4'b1001: if(next_bit) state <= 4'b1010; // bit 1 67 | 4'b1010: if(next_bit) state <= 4'b1011; // bit 2 68 | 4'b1011: if(next_bit) state <= 4'b1100; // bit 3 69 | 4'b1100: if(next_bit) state <= 4'b1101; // bit 4 70 | 4'b1101: if(next_bit) state <= 4'b1110; // bit 5 71 | 4'b1110: if(next_bit) state <= 4'b1111; // bit 6 72 | 4'b1111: if(next_bit) state <= 4'b0001; // bit 7 73 | 4'b0001: if(next_bit) state <= 4'b0000; // stop bit 74 | default: state <= 4'b0000; 75 | endcase 76 | 77 | reg [7:0]RxD_data; 78 | always @(posedge RxD_data_ready) RxD_data=RxD_data_r; 79 | 80 | 81 | reg [7:0] RxD_data_r; 82 | always @(posedge clk) 83 | if(Baud8Tick && next_bit && state[3]) RxD_data_r <= {~RxD_bit_inv, RxD_data_r[7:1]}; 84 | 85 | reg RxD_data_ready, RxD_data_error; 86 | always @(posedge clk) 87 | begin 88 | RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received 89 | RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received 90 | end 91 | 92 | reg [4:0] gap_count; 93 | always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 5'h01; 94 | assign RxD_idle = gap_count[4]; 95 | reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F); 96 | 97 | endmodule -------------------------------------------------------------------------------- /uart/async_transmitter.v: -------------------------------------------------------------------------------- 1 | // RS-232 TX module 2 | // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 3 | 4 | //`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations) 5 | 6 | module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy); 7 | input clk, TxD_start; 8 | input [7:0] TxD_data; 9 | output TxD, TxD_busy; 10 | 11 | parameter ClkFrequency = 25000000; // 25MHz 12 | parameter Baud = 115200;//baud rate setting; 13 | parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted 14 | 15 | // Baud generator 16 | parameter BaudGeneratorAccWidth = 16; 17 | reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; 18 | `ifdef DEBUG 19 | wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000; 20 | `else 21 | wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4); 22 | `endif 23 | 24 | wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; 25 | wire TxD_busy; 26 | always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; 27 | 28 | // Transmitter state machine 29 | reg [3:0] state; 30 | wire TxD_ready = (state==0); 31 | assign TxD_busy = ~TxD_ready; 32 | 33 | reg [7:0] TxD_dataReg; 34 | always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data; 35 | wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data; 36 | 37 | always @(posedge clk) 38 | case(state) 39 | 4'b0000: if(TxD_start)state <= 4'b0001; 40 | 4'b0001: if(BaudTick) state <= 4'b0100; 41 | 4'b0100: if(BaudTick) state <= 4'b1000; // start 42 | 4'b1000: if(BaudTick) state <= 4'b1001; // bit 0 43 | 4'b1001: if(BaudTick) state <= 4'b1010; // bit 1 44 | 4'b1010: if(BaudTick) state <= 4'b1011; // bit 2 45 | 4'b1011: if(BaudTick) state <= 4'b1100; // bit 3 46 | 4'b1100: if(BaudTick) state <= 4'b1101; // bit 4 47 | 4'b1101: if(BaudTick) state <= 4'b1110; // bit 5 48 | 4'b1110: if(BaudTick) state <= 4'b1111; // bit 6 49 | 4'b1111: if(BaudTick) state <= 4'b0010; // bit 7 50 | 4'b0010: if(BaudTick) state <= 4'b0011; // stop1 51 | 4'b0011: if(BaudTick) state <= 4'b0000; // stop2 52 | default: if(BaudTick) state <= 4'b0000; 53 | endcase 54 | 55 | // Output mux 56 | reg muxbit; 57 | always @( * ) 58 | case(state[2:0]) 59 | 3'd0: muxbit <= TxD_dataD[0]; 60 | 3'd1: muxbit <= TxD_dataD[1]; 61 | 3'd2: muxbit <= TxD_dataD[2]; 62 | 3'd3: muxbit <= TxD_dataD[3]; 63 | 3'd4: muxbit <= TxD_dataD[4]; 64 | 3'd5: muxbit <= TxD_dataD[5]; 65 | 3'd6: muxbit <= TxD_dataD[6]; 66 | 3'd7: muxbit <= TxD_dataD[7]; 67 | endcase 68 | 69 | // Put together the start, data and stop bits 70 | reg TxD; 71 | always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free 72 | 73 | endmodule -------------------------------------------------------------------------------- /uart/uart_control.v: -------------------------------------------------------------------------------- 1 | module uart_control( 2 | clk, 3 | reset_n, 4 | 5 | // rx 6 | read, 7 | readdata, 8 | rdempty, 9 | // 10 | uart_clk_25m, 11 | uart_rx 12 | ); 13 | 14 | //============================== 15 | 16 | input clk; 17 | input reset_n; 18 | 19 | input read; 20 | output [7:0] readdata; 21 | output rdempty; 22 | 23 | 24 | input uart_clk_25m; 25 | input uart_rx; 26 | 27 | 28 | //========= uart rx ===================== 29 | 30 | // 31 | wire rx_fifo_read_ack; 32 | wire [7:0] rx_fifo_read_data; 33 | wire rx_fifo_rdempty; 34 | 35 | assign rdempty = rx_fifo_rdempty; 36 | assign readdata = rx_fifo_read_data; 37 | assign rx_fifo_read_ack = read; 38 | 39 | // 40 | wire [7:0] rx_fifo_write_data; 41 | wire rx_fifo_write; 42 | wire rx_fifo_wrfull; 43 | 44 | 45 | // 46 | uart_fifo uart_fifo_rx( 47 | .aclr(~reset_n), 48 | // write 49 | .data(rx_fifo_write_data), 50 | .wrclk(uart_clk_25m), 51 | .wrreq(rx_fifo_write), 52 | .wrfull(rx_fifo_wrfull), 53 | // read 54 | .rdclk(clk), 55 | .rdreq(rx_fifo_read_ack), 56 | .q(rx_fifo_read_data), 57 | .rdempty(rx_fifo_rdempty), 58 | ); 59 | 60 | 61 | // 62 | reg rx_read; 63 | wire [7:0] rx_data; 64 | wire rx_ready; 65 | always @ (posedge uart_clk_25m or negedge reset_n) 66 | begin 67 | if (!reset_n) 68 | rx_read <= 1'b0; 69 | else if (rx_ready && !rx_fifo_wrfull) // && !rx_read) 70 | rx_read <= 1'b1; 71 | else 72 | rx_read <= 1'b0; 73 | end 74 | 75 | 76 | assign rx_fifo_write = rx_read; 77 | assign rx_fifo_write_data = rx_data; 78 | 79 | // 80 | 81 | async_receiver rx( 82 | .clk(uart_clk_25m), 83 | .RxD(uart_rx), 84 | .RxD_data_ready(rx_ready), 85 | .RxD_data(rx_data), 86 | .RxD_endofpacket(), 87 | .RxD_idle() 88 | ); 89 | 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /uart/uart_control.v.bak: -------------------------------------------------------------------------------- 1 | module uart_control( 2 | clk, 3 | reset_n, 4 | // tx 5 | write, 6 | writedata, 7 | wrfull, 8 | // rx 9 | read, 10 | readdata, 11 | rdempty, 12 | // 13 | uart_clk_25m, 14 | uart_tx, 15 | uart_rx 16 | ); 17 | 18 | //============================== 19 | 20 | input clk; 21 | input reset_n; 22 | input write; 23 | input [7:0] writedata; 24 | output wrfull; 25 | input read; 26 | output [7:0] readdata; 27 | output rdempty; 28 | 29 | 30 | input uart_clk_25m; 31 | output uart_tx; 32 | input uart_rx; 33 | 34 | //========= tx ===================== 35 | // write 36 | wire tx_fifo_wrfull; 37 | wire tx_fifo_write; 38 | wire [7:0] tx_fifo_write_data; 39 | 40 | assign wrfull = tx_fifo_wrfull; 41 | assign tx_fifo_write = write; 42 | assign tx_fifo_write_data = writedata; 43 | 44 | // read 45 | wire tx_fifo_read_ack; 46 | wire [7:0] tx_fifo_read_data; 47 | wire tx_fifo_rdempty; 48 | 49 | 50 | // 51 | uart_fifo uart_fifo_tx( 52 | .aclr(~reset_n), 53 | // write 54 | .data(tx_fifo_write_data), 55 | .wrclk(clk), 56 | .wrreq(tx_fifo_write), 57 | .wrfull(tx_fifo_wrfull), 58 | // read 59 | .rdclk(uart_clk_25m), 60 | .rdreq(tx_fifo_read_ack), 61 | .q(tx_fifo_read_data), 62 | .rdempty(tx_fifo_rdempty) 63 | ); 64 | 65 | 66 | reg tx_start; 67 | wire [7:0] tx_data; 68 | wire tx_busy; 69 | 70 | assign tx_fifo_read_ack = tx_start; 71 | assign tx_data = tx_fifo_read_data; 72 | 73 | always @ (posedge uart_clk_25m or negedge reset_n) 74 | begin 75 | if (!reset_n) 76 | tx_start <= 1'b0; 77 | else if (!tx_busy && !tx_fifo_rdempty && !tx_start) 78 | tx_start <= 1'b1; 79 | else 80 | tx_start <= 1'b0; 81 | end 82 | 83 | async_transmitter tx( 84 | .clk(uart_clk_25m), 85 | .TxD_start(tx_start), 86 | .TxD_data(tx_data), 87 | .TxD(uart_tx), 88 | .TxD_busy(tx_busy) 89 | ); 90 | 91 | 92 | //========= uart rx ===================== 93 | 94 | // 95 | wire rx_fifo_read_ack; 96 | wire [7:0] rx_fifo_read_data; 97 | wire rx_fifo_rdempty; 98 | 99 | assign rdempty = rx_fifo_rdempty; 100 | assign readdata = rx_fifo_read_data; 101 | assign rx_fifo_read_ack = read; 102 | 103 | // 104 | wire [7:0] rx_fifo_write_data; 105 | wire rx_fifo_write; 106 | wire rx_fifo_wrfull; 107 | 108 | 109 | // 110 | uart_fifo uart_fifo_rx( 111 | .aclr(~reset_n), 112 | // write 113 | .data(rx_fifo_write_data), 114 | .wrclk(uart_clk_25m), 115 | .wrreq(rx_fifo_write), 116 | .wrfull(rx_fifo_wrfull), 117 | // read 118 | .rdclk(clk), 119 | .rdreq(rx_fifo_read_ack), 120 | .q(rx_fifo_read_data), 121 | .rdempty(rx_fifo_rdempty), 122 | ); 123 | 124 | 125 | // 126 | reg rx_read; 127 | wire [7:0] rx_data; 128 | wire rx_ready; 129 | always @ (posedge uart_clk_25m or negedge reset_n) 130 | begin 131 | if (!reset_n) 132 | rx_read <= 1'b0; 133 | else if (rx_ready && !rx_fifo_wrfull) // && !rx_read) 134 | rx_read <= 1'b1; 135 | else 136 | rx_read <= 1'b0; 137 | end 138 | 139 | 140 | assign rx_fifo_write = rx_read; 141 | assign rx_fifo_write_data = rx_data; 142 | 143 | // 144 | 145 | async_receiver rx( 146 | .clk(uart_clk_25m), 147 | .RxD(uart_rx), 148 | .RxD_data_ready(rx_ready), 149 | .RxD_data(rx_data), 150 | .RxD_endofpacket(), 151 | .RxD_idle() 152 | ); 153 | 154 | 155 | endmodule 156 | -------------------------------------------------------------------------------- /uart/uart_fifo.cnx: -------------------------------------------------------------------------------- 1 | VERSION: WM1.0 2 | MODULE: dcfifo 3 | PRIVATE: AlmostEmpty NUMERIC "0" 4 | PRIVATE: AlmostEmptyThr NUMERIC "-1" 5 | PRIVATE: AlmostFull NUMERIC "0" 6 | PRIVATE: AlmostFullThr NUMERIC "-1" 7 | PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 8 | PRIVATE: Clock NUMERIC "4" 9 | PRIVATE: Depth NUMERIC "256" 10 | PRIVATE: Empty NUMERIC "1" 11 | PRIVATE: Full NUMERIC "1" 12 | PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 13 | PRIVATE: LE_BasedFIFO NUMERIC "0" 14 | PRIVATE: LegacyRREQ NUMERIC "0" 15 | PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 16 | PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 17 | PRIVATE: Optimize NUMERIC "0" 18 | PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 19 | PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 20 | PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 21 | PRIVATE: UsedW NUMERIC "1" 22 | PRIVATE: Width NUMERIC "8" 23 | PRIVATE: dc_aclr NUMERIC "1" 24 | PRIVATE: diff_widths NUMERIC "0" 25 | PRIVATE: msb_usedw NUMERIC "0" 26 | PRIVATE: output_width NUMERIC "8" 27 | PRIVATE: rsEmpty NUMERIC "1" 28 | PRIVATE: rsFull NUMERIC "0" 29 | PRIVATE: rsUsedW NUMERIC "1" 30 | PRIVATE: sc_aclr NUMERIC "0" 31 | PRIVATE: sc_sclr NUMERIC "0" 32 | PRIVATE: wsEmpty NUMERIC "0" 33 | PRIVATE: wsFull NUMERIC "1" 34 | PRIVATE: wsUsedW NUMERIC "0" 35 | CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 36 | CONSTANT: LPM_NUMWORDS NUMERIC "256" 37 | CONSTANT: LPM_SHOWAHEAD STRING "ON" 38 | CONSTANT: LPM_TYPE STRING "dcfifo" 39 | CONSTANT: LPM_WIDTH NUMERIC "8" 40 | CONSTANT: LPM_WIDTHU NUMERIC "8" 41 | CONSTANT: OVERFLOW_CHECKING STRING "ON" 42 | CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 43 | CONSTANT: UNDERFLOW_CHECKING STRING "ON" 44 | CONSTANT: USE_EAB STRING "ON" 45 | CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 46 | CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 47 | USED_PORT: aclr 0 0 0 0 INPUT GND aclr 48 | USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] 49 | USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] 50 | USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk 51 | USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty 52 | USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq 53 | USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0] 54 | USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk 55 | USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull 56 | USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq 57 | CONNECT: @data 0 0 8 0 data 0 0 8 0 58 | CONNECT: q 0 0 8 0 @q 0 0 8 0 59 | CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 60 | CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 61 | CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 62 | CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 63 | CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 64 | CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0 65 | CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 66 | CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 67 | LIBRARY: altera_mf altera_mf.altera_mf_components.all 68 | GEN_FILE: TYPE_NORMAL uart_fifo.v TRUE 69 | GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE 70 | GEN_FILE: TYPE_NORMAL uart_fifo.cmp FALSE 71 | GEN_FILE: TYPE_NORMAL uart_fifo.bsf TRUE FALSE 72 | GEN_FILE: TYPE_NORMAL uart_fifo_inst.v FALSE 73 | GEN_FILE: TYPE_NORMAL uart_fifo_bb.v FALSE 74 | GEN_FILE: TYPE_NORMAL uart_fifo_waveforms.html TRUE 75 | GEN_FILE: TYPE_NORMAL uart_fifo_wave*.jpg FALSE 76 | LIB_FILE: altera_mf 77 | 78 | LICENSE_ID: "DEVICE_FAMILY_Cyclone 10 LP" 01818924A5241715226A 79 | LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 01818924A5241715226A 80 | LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 01818924C5241715226K 81 | LICENSE_ID: "DEVICE_FAMILY_MAX V" 01818924S5241715226K 82 | LICENSE_ID: "DEVICE_FAMILY_Arria II GX" 01818924M5241715226W 83 | LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 01818924A5241715226A 84 | LICENSE_ID: "DEVICE_FAMILY_MAX II" 01818924O5241715226E 85 | LICENSE_ID: "DEVICE_FAMILY_MAX 10" 01818924O5241715226E 86 | LICENSE_ID: "FEATURE_STRATIXGX_DPA" 01818924O5241715226A 87 | LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 01818924C5241715226K 88 | 89 | 90 | SUPPORTED_DEVICE_FAMILY: "Cyclone 10 LP" 91 | SUPPORTED_DEVICE_FAMILY: "Cyclone IV E" 92 | SUPPORTED_DEVICE_FAMILY: "Cyclone V" 93 | SUPPORTED_DEVICE_FAMILY: "MAX V" 94 | SUPPORTED_DEVICE_FAMILY: "Arria II GX" 95 | SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX" 96 | SUPPORTED_DEVICE_FAMILY: "MAX II" 97 | SUPPORTED_DEVICE_FAMILY: "MAX 10" 98 | SUPPORTED_DEVICE_FAMILY: "Cyclone III" 99 | 100 | WIZARD_TITLE: "FIFO" 101 | QUARTUS_VERSION: "Version 18.0" 102 | QUARTUS_SVERSION: "18.0.0 Build 614 04/24/2018 SJ Lite Edition:04/24/2018" 103 | QUARTUS_BUILD_DATE: "04/24/2018" 104 | ALTERA_COPYRIGHT: "Copyright (C) 2018 Intel Corporation. All rights reserved." 105 | RESC_INFO: ON 106 | 107 | 108 | HELP_MENU_ITEM: FALSE "IUG$Single and Dual-Clock FIFO Megafunctions User Guide$http://www.altera.com/literature/ug/ug_fifo.pdf" 109 | -------------------------------------------------------------------------------- /uart/uart_fifo.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: uart_fifo.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 8.0 Build 231 07/10/2008 SP 1 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2008 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module uart_fifo ( 40 | aclr, 41 | data, 42 | rdclk, 43 | rdreq, 44 | wrclk, 45 | wrreq, 46 | q, 47 | rdempty, 48 | rdusedw, 49 | wrfull); 50 | 51 | input aclr; 52 | input [7:0] data; 53 | input rdclk; 54 | input rdreq; 55 | input wrclk; 56 | input wrreq; 57 | output [7:0] q; 58 | output rdempty; 59 | output [7:0] rdusedw; 60 | output wrfull; 61 | 62 | wire sub_wire0; 63 | wire sub_wire1; 64 | wire [7:0] sub_wire2; 65 | wire [7:0] sub_wire3; 66 | wire rdempty = sub_wire0; 67 | wire wrfull = sub_wire1; 68 | wire [7:0] q = sub_wire2[7:0]; 69 | wire [7:0] rdusedw = sub_wire3[7:0]; 70 | 71 | dcfifo dcfifo_component ( 72 | .wrclk (wrclk), 73 | .rdreq (rdreq), 74 | .aclr (aclr), 75 | .rdclk (rdclk), 76 | .wrreq (wrreq), 77 | .data (data), 78 | .rdempty (sub_wire0), 79 | .wrfull (sub_wire1), 80 | .q (sub_wire2), 81 | .rdusedw (sub_wire3) 82 | // synopsys translate_off 83 | , 84 | .rdfull (), 85 | .wrempty (), 86 | .wrusedw () 87 | // synopsys translate_on 88 | ); 89 | defparam 90 | dcfifo_component.intended_device_family = "Cyclone III", 91 | dcfifo_component.lpm_numwords = 256, 92 | dcfifo_component.lpm_showahead = "ON", 93 | dcfifo_component.lpm_type = "dcfifo", 94 | dcfifo_component.lpm_width = 8, 95 | dcfifo_component.lpm_widthu = 8, 96 | dcfifo_component.overflow_checking = "ON", 97 | dcfifo_component.rdsync_delaypipe = 4, 98 | dcfifo_component.underflow_checking = "ON", 99 | dcfifo_component.use_eab = "ON", 100 | dcfifo_component.write_aclr_synch = "OFF", 101 | dcfifo_component.wrsync_delaypipe = 4; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 110 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 111 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 112 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 113 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 114 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 115 | // Retrieval info: PRIVATE: Depth NUMERIC "256" 116 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 117 | // Retrieval info: PRIVATE: Full NUMERIC "1" 118 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 119 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 120 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" 121 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 122 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 123 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 124 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 125 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 126 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 127 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 128 | // Retrieval info: PRIVATE: Width NUMERIC "8" 129 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 130 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 131 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 132 | // Retrieval info: PRIVATE: output_width NUMERIC "8" 133 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 134 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 135 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" 136 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 137 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 138 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 139 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 140 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" 141 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 142 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" 143 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" 144 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 145 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" 146 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" 147 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 148 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 149 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 150 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 151 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 152 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 153 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr 154 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] 155 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] 156 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk 157 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty 158 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq 159 | // Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0] 160 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk 161 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull 162 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq 163 | // Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 164 | // Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 165 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 166 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 167 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 168 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 169 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 170 | // Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0 171 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 172 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 173 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.v TRUE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.cmp FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.bsf TRUE FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_inst.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_bb.v FALSE 180 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_waveforms.html TRUE 181 | // Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_wave*.jpg FALSE 182 | // Retrieval info: LIB_FILE: altera_mf 183 | --------------------------------------------------------------------------------