├── .gitattributes ├── .github └── FUNDING.yml ├── .gitignore ├── CONTRIBUTING.md ├── LICENSE ├── README.md ├── ROADMAP.md ├── demos ├── ad-astra │ ├── README.md │ ├── lint.sh │ ├── res │ │ ├── font_unscii_16x16_hiragana.mem │ │ ├── font_unscii_8x8_latin_uc.mem │ │ └── greet.mem │ ├── sprite.sv │ ├── starfield.sv │ └── xc7 │ │ ├── arty.xdc │ │ ├── sprite_tb.sv │ │ ├── starfield_tb.sv │ │ ├── top_greet.sv │ │ ├── top_greet_v1.sv │ │ ├── top_hello_en.sv │ │ ├── top_hello_jp.sv │ │ ├── top_lfsr.sv │ │ ├── top_space_f.sv │ │ ├── top_starfields.sv │ │ └── vivado │ │ ├── create_project.tcl │ │ ├── sprite_tb_behav.wcfg │ │ └── starfield_tb_behav.wcfg ├── castle-drawing │ ├── README.md │ ├── lint.sh │ ├── render_castle.sv │ ├── sim │ │ ├── Makefile │ │ ├── main_castle.cpp │ │ └── top_castle.sv │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_castle.sv │ │ └── vivado │ │ └── create_project.tcl ├── life-on-screen │ ├── README.md │ ├── lib │ │ └── display │ │ │ ├── framebuffer_bram.sv │ │ │ └── linebuffer.sv │ ├── life.sv │ ├── lint.sh │ ├── res │ │ ├── life_palette.mem │ │ ├── seed │ │ │ ├── empty_64x48.mem │ │ │ ├── glider_64x48.mem │ │ │ ├── gosper_gun_64x48.mem │ │ │ └── simple_64x48.mem │ │ └── test │ │ │ ├── beacon.mem │ │ │ ├── beehive.mem │ │ │ ├── blinker.mem │ │ │ ├── block.mem │ │ │ ├── empty.mem │ │ │ ├── glider.mem │ │ │ ├── loaf.mem │ │ │ └── toad.mem │ └── xc7 │ │ ├── arty.xdc │ │ ├── life_tb.sv │ │ ├── top_life.sv │ │ └── vivado │ │ ├── create_project.tcl │ │ └── life_tb_behav.wcfg ├── mandelbrot │ ├── README.md │ ├── lint.sh │ ├── mandelbrot.sv │ ├── render_mandel.sv │ ├── verilator-sdl │ │ ├── Makefile │ │ ├── main_mandel.cpp │ │ └── top_mandel.sv │ ├── xc7-dvi │ │ ├── nexys-video │ │ │ ├── create_project.tcl │ │ │ └── nexys-video.xdc │ │ └── top_mandel.sv │ └── xc7-vga │ │ ├── arty-a7-35 │ │ ├── arty-a7-35.xdc │ │ └── create_project.tcl │ │ └── top_mandel.sv ├── rasterbars │ ├── README.md │ ├── lint.sh │ ├── rasterbar.sv │ ├── render_rasterbars.sv │ ├── sim │ │ ├── Makefile │ │ ├── main_rasterbars.cpp │ │ └── top_rasterbars.sv │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_rasterbars.sv │ │ └── vivado │ │ └── create_project.tcl └── sinescroll │ ├── README.md │ ├── lint.sh │ ├── render_sinescroll.sv │ ├── res │ ├── fonts │ │ └── outline-font-32x32.mem │ └── text │ │ └── greet.mem │ ├── sim │ ├── Makefile │ ├── main_sinescroll.cpp │ └── top_sinescroll.sv │ └── xc7 │ ├── arty.xdc │ ├── top_sinescroll.sv │ └── vivado │ └── create_project.tcl ├── doc └── img │ ├── 2d-shapes-sim.png │ ├── 2d-shapes.jpg │ ├── animated-shapes.png │ ├── castle-sim.png │ ├── flag_ethiopia.png │ ├── fpga-ad-astra-banner.png │ ├── fpga-ad-astra.png │ ├── fpga-graphics-banner.png │ ├── framebuffers-fizzle.png │ ├── framebuffers.png │ ├── hardware-sprites.png │ ├── life-on-screen.png │ ├── lines-and-triangles-sim.png │ ├── lines-and-triangles.jpg │ ├── palettes-16.png │ ├── pong-verilator-sdl.png │ ├── pong.png │ ├── rasterbars-sim.png │ ├── rasterbars.png │ ├── sea-of-chaos.png │ ├── sinescroll-sim.png │ └── verilator-polynomial.png ├── graphics ├── 2d-shapes │ ├── 160x90 │ │ ├── render_circles.sv │ │ ├── render_circles_fill.sv │ │ ├── render_cube_fill.sv │ │ ├── render_rects.sv │ │ ├── render_rects_fill.sv │ │ └── render_triangles_fill.sv │ ├── 320x180 │ │ ├── render_circles.sv │ │ ├── render_circles_fill.sv │ │ ├── render_cube_fill.sv │ │ ├── render_rects.sv │ │ ├── render_rects_fill.sv │ │ └── render_triangles_fill.sv │ ├── README.md │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ └── top_demo.sv │ ├── lint.sh │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_demo.cpp │ │ └── top_demo.sv │ ├── xc7-dvi │ │ ├── 2d-shapes-bitstreams.zip │ │ ├── nexys_video.xdc │ │ ├── top_demo.sv │ │ └── vivado │ │ │ └── create_project.tcl │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_demo.sv │ │ └── vivado │ │ └── create_project.tcl ├── README.md ├── animated-shapes │ ├── 160x90 │ │ ├── render_cube_shatter.sv │ │ ├── render_square_colr.sv │ │ └── render_teleport.sv │ ├── 320x180 │ │ ├── render_cube_shatter.sv │ │ ├── render_square_colr.sv │ │ └── render_teleport.sv │ ├── README.md │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ ├── top_demo.sv │ │ └── top_demo_sb.sv │ ├── lint.sh │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_demo.cpp │ │ ├── main_demo_sb.cpp │ │ ├── top_demo.sv │ │ └── top_demo_sb.sv │ ├── xc7-dvi │ │ ├── animated-shapes-bitstreams.zip │ │ ├── nexys_video.xdc │ │ ├── top_demo.sv │ │ ├── top_demo_sb.sv │ │ └── vivado │ │ │ └── create_project.tcl │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_demo.sv │ │ ├── top_demo_sb.sv │ │ └── vivado │ │ └── create_project.tcl ├── fpga-graphics │ ├── README.md │ ├── ecp5 │ │ ├── Makefile │ │ ├── top_colour.sv │ │ ├── top_flag_ethiopia.sv │ │ ├── top_flag_sweden.sv │ │ ├── top_square.sv │ │ └── ulx3s.lpf │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ ├── top_colour.sv │ │ ├── top_flag_ethiopia.sv │ │ ├── top_flag_sweden.sv │ │ └── top_square.sv │ ├── lint.sh │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_colour.cpp │ │ ├── main_flag_ethiopia.cpp │ │ ├── main_flag_sweden.cpp │ │ ├── main_square.cpp │ │ ├── top_colour.sv │ │ ├── top_flag_ethiopia.sv │ │ ├── top_flag_sweden.sv │ │ └── top_square.sv │ ├── simple_480p.sv │ ├── simple_720p.sv │ ├── xc7-dvi │ │ ├── fpga-graphics-bitstreams.zip │ │ ├── nexys_video.xdc │ │ ├── simple_720p_tb.sv │ │ ├── top_colour.sv │ │ ├── top_flag_ethiopia.sv │ │ ├── top_flag_sweden.sv │ │ ├── top_square.sv │ │ └── vivado │ │ │ ├── create_project.tcl │ │ │ └── simple_720p_tb_behav.wcfg │ └── xc7 │ │ ├── arty.xdc │ │ ├── simple_480p_tb.sv │ │ ├── top_colour.sv │ │ ├── top_flag_ethiopia.sv │ │ ├── top_flag_sweden.sv │ │ ├── top_square.sv │ │ └── vivado │ │ ├── create_project.tcl │ │ └── simple_480p_tb_behav.wcfg ├── framebuffers │ ├── README.md │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ ├── top_david_16colr.sv │ │ ├── top_david_fizzle.sv │ │ ├── top_david_mono.sv │ │ └── top_david_scale.sv │ ├── lint.sh │ ├── res │ │ └── david │ │ │ ├── david.mem │ │ │ ├── david.png │ │ │ ├── david_1bit.mem │ │ │ ├── david_1bit.png │ │ │ ├── david_preview.png │ │ │ └── david_test.mem │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_david_16colr.cpp │ │ ├── main_david_fizzle.cpp │ │ ├── main_david_mono.cpp │ │ ├── main_david_mono_draw.cpp │ │ ├── main_david_scale.cpp │ │ ├── top_david_16colr.sv │ │ ├── top_david_fizzle.sv │ │ ├── top_david_mono.sv │ │ └── top_david_scale.sv │ ├── xc7-dvi │ │ ├── framebuffers-bitstreams.zip │ │ ├── nexys_video.xdc │ │ ├── top_david_16colr.sv │ │ ├── top_david_fizzle.sv │ │ ├── top_david_mono.sv │ │ ├── top_david_scale.sv │ │ └── vivado │ │ │ └── create_project.tcl │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_david_16colr.sv │ │ ├── top_david_fizzle.sv │ │ ├── top_david_mono.sv │ │ ├── top_david_scale.sv │ │ └── vivado │ │ └── create_project.tcl ├── hardware-sprites │ ├── README.md │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ ├── top_hedgehog.sv │ │ ├── top_hourglass.sv │ │ ├── top_tinyf_inline.sv │ │ ├── top_tinyf_move.sv │ │ ├── top_tinyf_rom.sv │ │ └── top_tinyf_scale.sv │ ├── lint.sh │ ├── res │ │ ├── palettes │ │ │ └── hedgehog_4b.mem │ │ └── sprites │ │ │ ├── hedgehog.mem │ │ │ ├── hourglass.mem │ │ │ └── letter_f.mem │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_hedgehog.cpp │ │ ├── main_hourglass.cpp │ │ ├── main_tinyf_inline.cpp │ │ ├── main_tinyf_move.cpp │ │ ├── main_tinyf_rom.cpp │ │ ├── main_tinyf_scale.cpp │ │ ├── top_hedgehog.sv │ │ ├── top_hourglass.sv │ │ ├── top_tinyf_inline.sv │ │ ├── top_tinyf_move.sv │ │ ├── top_tinyf_rom.sv │ │ └── top_tinyf_scale.sv │ ├── sprite.sv │ ├── sprite_inline.sv │ ├── sprite_rom.sv │ ├── xc7-dvi │ │ ├── hardware-sprites-bitstreams.zip │ │ ├── nexys_video.xdc │ │ ├── top_hedgehog.sv │ │ ├── top_hourglass.sv │ │ ├── top_tinyf_inline.sv │ │ ├── top_tinyf_move.sv │ │ ├── top_tinyf_rom.sv │ │ ├── top_tinyf_scale.sv │ │ └── vivado │ │ │ └── create_project.tcl │ └── xc7 │ │ ├── arty.xdc │ │ ├── sprite_inline_tb.sv │ │ ├── sprite_rom_tb.sv │ │ ├── sprite_tb.sv │ │ ├── top_hedgehog.sv │ │ ├── top_hourglass.sv │ │ ├── top_tinyf_inline.sv │ │ ├── top_tinyf_move.sv │ │ ├── top_tinyf_rom.sv │ │ ├── top_tinyf_scale.sv │ │ └── vivado │ │ ├── create_project.tcl │ │ ├── sprite_inline_tb_behav.wcfg │ │ ├── sprite_rom_tb_behav.wcfg │ │ └── sprite_tb_behav.wcfg ├── lines-and-triangles │ ├── 160x90 │ │ ├── render_cube.sv │ │ ├── render_edge.sv │ │ ├── render_line.sv │ │ └── render_triangles.sv │ ├── 320x180 │ │ ├── render_cube.sv │ │ ├── render_edge.sv │ │ ├── render_line.sv │ │ └── render_triangles.sv │ ├── README.md │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ └── top_demo.sv │ ├── lint.sh │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_demo.cpp │ │ └── top_demo.sv │ ├── xc7-dvi │ │ ├── lines-and-triangles-bitstreams.zip │ │ ├── nexys_video.xdc │ │ ├── top_demo.sv │ │ └── vivado │ │ │ └── create_project.tcl │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_demo.sv │ │ └── vivado │ │ └── create_project.tcl ├── pong │ ├── README.md │ ├── ice40 │ │ ├── Makefile │ │ ├── icebreaker.pcf │ │ └── top_pong.sv │ ├── lint.sh │ ├── sim │ │ ├── Makefile │ │ ├── README.md │ │ ├── main_pong.cpp │ │ └── top_pong.sv │ ├── simple_480p.sv │ ├── simple_720p.sv │ ├── simple_score.sv │ ├── xc7-dvi │ │ ├── nexys_video.xdc │ │ ├── pong-bitstreams.zip │ │ ├── top_pong.sv │ │ └── vivado │ │ │ ├── build.tcl │ │ │ └── create_project.tcl │ └── xc7 │ │ ├── arty.xdc │ │ ├── top_pong.sv │ │ └── vivado │ │ ├── build.tcl │ │ └── create_project.tcl └── racing-the-beam │ ├── README.md │ ├── ecp5 │ ├── Makefile │ ├── top_bounce.sv │ ├── top_colour_cycle.sv │ ├── top_hello.sv │ ├── top_hitomezashi.sv │ ├── top_rasterbars.sv │ └── ulx3s.lpf │ ├── ice40 │ ├── Makefile │ ├── icebreaker.pcf │ ├── top_bounce.sv │ ├── top_colour_cycle.sv │ ├── top_hello.sv │ ├── top_hitomezashi.sv │ └── top_rasterbars.sv │ ├── lint.sh │ ├── sim │ ├── Makefile │ ├── README.md │ ├── main_bounce.cpp │ ├── main_colour_cycle.cpp │ ├── main_hello.cpp │ ├── main_hitomezashi.cpp │ ├── main_rasterbars.cpp │ ├── top_bounce.sv │ ├── top_colour_cycle.sv │ ├── top_hello.sv │ ├── top_hitomezashi.sv │ └── top_rasterbars.sv │ ├── simple_480p.sv │ ├── simple_720p.sv │ ├── xc7-dvi │ ├── nexys_video.xdc │ ├── racing-the-beam-bitstreams.zip │ ├── top_bounce.sv │ ├── top_colour_cycle.sv │ ├── top_hello.sv │ ├── top_hitomezashi.sv │ ├── top_rasterbars.sv │ └── vivado │ │ └── create_project.tcl │ └── xc7 │ ├── arty.xdc │ ├── top_bounce.sv │ ├── top_colour_cycle.sv │ ├── top_hello.sv │ ├── top_hitomezashi.sv │ ├── top_rasterbars.sv │ └── vivado │ └── create_project.tcl ├── hello ├── README.md ├── hello-arty │ ├── A │ │ ├── arty.xdc │ │ └── top.sv │ ├── B │ │ ├── arty.xdc │ │ └── top.sv │ ├── C │ │ ├── arty.xdc │ │ └── top.sv │ ├── D │ │ ├── arty.xdc │ │ └── top.sv │ ├── E │ │ ├── arty.xdc │ │ └── top.sv │ ├── F │ │ ├── arty.xdc │ │ └── top.sv │ ├── G │ │ ├── arty.xdc │ │ └── top.sv │ ├── H │ │ ├── arty.xdc │ │ └── top.sv │ ├── I │ │ ├── arty.xdc │ │ ├── pwm.sv │ │ └── top.sv │ ├── J │ │ ├── arty.xdc │ │ ├── pwm.sv │ │ └── top.sv │ ├── K │ │ ├── arty.xdc │ │ ├── debounce.sv │ │ └── top.sv │ ├── L │ │ ├── arty.xdc │ │ ├── pwm.sv │ │ └── top.sv │ └── README.md └── hello-nexys │ ├── A │ ├── nexys.xdc │ └── top.sv │ ├── B │ ├── nexys.xdc │ └── top.sv │ ├── C │ ├── nexys.xdc │ └── top.sv │ ├── D │ ├── nexys.xdc │ └── top.sv │ ├── E │ ├── nexys.xdc │ └── top.sv │ ├── F │ ├── nexys.xdc │ └── top.sv │ ├── G │ ├── nexys.xdc │ └── top.sv │ ├── H │ ├── nexys.xdc │ └── top.sv │ ├── I │ ├── nexys.xdc │ ├── pwm.sv │ └── top.sv │ └── README.md ├── lib ├── README.md ├── clock │ ├── README.md │ ├── ecp5 │ │ └── clock2_gen.v │ ├── ice40 │ │ └── clock_480p.sv │ ├── xc7 │ │ ├── clock_1080p.sv │ │ ├── clock_480p.sv │ │ ├── clock_720p.sv │ │ ├── clock_sys.sv │ │ ├── clock_tb.sv │ │ ├── vivado │ │ │ ├── clock_tb_behav.wcfg │ │ │ └── xd_tb_behav.wcfg │ │ └── xd_tb.sv │ └── xd.sv ├── display │ ├── README.md │ ├── bitmap_addr.sv │ ├── clut_simple.sv │ ├── display_1080p.sv │ ├── display_24x18.sv │ ├── display_480p.sv │ ├── display_720p.sv │ ├── ecp5 │ │ └── dvi_generator.sv │ ├── linebuffer_simple.sv │ ├── tmds_encoder_dvi.sv │ └── xc7 │ │ ├── bitmap_addr_tb.sv │ │ ├── clut_simple_tb.sv │ │ ├── display_480p_tb.sv │ │ ├── display_720p_tb.sv │ │ ├── dvi_generator.sv │ │ ├── linebuffer_simple_tb.sv │ │ ├── oserdes_10b.sv │ │ ├── tmds_out.sv │ │ └── vivado │ │ ├── clut_simple_tb_behav.wcfg │ │ ├── display_480p_tb_behav.wcfg │ │ ├── display_720p_tb_behav.wcfg │ │ └── linebuffer_simple_tb_behav.wcfg ├── essential │ ├── README.md │ ├── debounce.sv │ └── xc7 │ │ └── async_reset.sv ├── graphics │ ├── README.md │ ├── draw_char.sv │ ├── draw_circle.sv │ ├── draw_circle_fill.sv │ ├── draw_line.sv │ ├── draw_line_1d.sv │ ├── draw_rectangle.sv │ ├── draw_rectangle_fill.sv │ ├── draw_triangle.sv │ ├── draw_triangle_fill.sv │ ├── get_glyph_line.sv │ └── xc7 │ │ ├── draw_char_tb.sv │ │ ├── draw_circle_tb.sv │ │ ├── draw_line_1d_tb.sv │ │ ├── draw_line_tb.sv │ │ ├── draw_rectangle_fill_tb.sv │ │ ├── draw_rectangle_tb.sv │ │ ├── draw_triangle_fill_tb.sv │ │ ├── draw_triangle_tb.sv │ │ ├── get_glyph_line_tb.sv │ │ └── vivado │ │ ├── draw_circle_tb_behav.wcfg │ │ ├── draw_line_1d_tb_behav.wcfg │ │ ├── draw_line_tb_behav.wcfg │ │ ├── draw_rectangle_fill_tb_behav.wcfg │ │ ├── draw_rectangle_tb_behav.wcfg │ │ ├── draw_triangle_fill_tb_behav.wcfg │ │ └── draw_triangle_tb_behav.wcfg ├── maths │ ├── README.md │ ├── div.sv │ ├── divu.sv │ ├── divu_int.sv │ ├── lfsr.sv │ ├── mul.sv │ ├── res │ │ └── sine_table_64x8.mem │ ├── sine_table.sv │ ├── sqrt.sv │ ├── sqrt_int.sv │ ├── test │ │ ├── Makefile │ │ ├── div.gtkw │ │ ├── div.mk │ │ ├── div.py │ │ ├── divu.gtkw │ │ ├── divu.mk │ │ ├── divu.py │ │ ├── divu_int.gtkw │ │ ├── divu_int.mk │ │ ├── divu_int.py │ │ ├── mul.gtkw │ │ ├── mul.mk │ │ └── mul.py │ └── xc7 │ │ ├── clog2_tb.sv │ │ ├── lfsr_tb.sv │ │ ├── sine_table_tb.sv │ │ ├── sqrt_int_tb.sv │ │ ├── sqrt_tb.sv │ │ └── vivado │ │ ├── lfsr_tb_behav.wcfg │ │ └── sine_table_tb_behav.wcfg ├── memory │ ├── README.md │ ├── bram_sdp.sv │ ├── ice40 │ │ ├── spram.sv │ │ └── spram_nibble.sv │ ├── rom_async.sv │ └── rom_sync.sv ├── null │ ├── ice40 │ │ ├── SB_IO.sv │ │ ├── SB_PLL40_PAD.sv │ │ └── SB_SPRAM256KA.sv │ └── xc7 │ │ ├── BUFG.sv │ │ ├── MMCME2_BASE.sv │ │ ├── OBUFDS.sv │ │ └── OSERDESE2.sv ├── res │ ├── fonts │ │ ├── font_empty.mem │ │ ├── font_unifont_8x16.mem │ │ ├── font_unscii_8x16.mem │ │ ├── font_unscii_8x8.mem │ │ └── unifont-licences │ │ │ ├── LICENSE.txt │ │ │ ├── OFL-1.1.txt │ │ │ └── README.md │ ├── palettes │ │ ├── README.md │ │ ├── antiquity16_4b.mem │ │ ├── fading16_4b.mem │ │ ├── grey16_4b.mem │ │ ├── greyinvert16_4b.mem │ │ ├── pico8_4b.mem │ │ ├── sepia16_4b.mem │ │ ├── sweetie16_4b.mem │ │ ├── teleport16_4b.mem │ │ └── teleport4_4b.mem │ └── test │ │ ├── test_box_12x9.mem │ │ ├── test_box_160x120.mem │ │ ├── test_box_db_12x9.mem │ │ ├── test_box_mono_160x120.mem │ │ ├── test_clear_12x9.mem │ │ └── test_palette.mem └── uart │ ├── README.md │ ├── examples │ ├── arty.xdc │ └── top_uart.sv │ ├── uart_baud.sv │ ├── uart_rx.sv │ └── uart_tx.sv └── maths └── demo ├── README.md ├── func_circle.sv ├── func_cubed.sv ├── func_polynomial.sv ├── func_squared.sv ├── ice40 ├── Makefile ├── icebreaker.pcf └── top_graphing.sv ├── lint.sh ├── sim ├── README.md ├── main_graphing.cpp └── top_graphing.sv ├── xc7-hd ├── nexys_video.xdc ├── top_graphing.sv └── vivado │ └── create_project.tcl └── xc7 ├── arty.xdc ├── top_graphing.sv └── vivado └── create_project.tcl /.gitattributes: -------------------------------------------------------------------------------- 1 | * text=auto eol=lf 2 | *.{cmd,[cC][mM][dD]} text eol=crlf 3 | *.{bat,[bB][aA][tT]} text eol=crlf 4 | -------------------------------------------------------------------------------- /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | github: [WillGreen] # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2] 4 | patreon: # Replace with a single Patreon username 5 | open_collective: # Replace with a single Open Collective username 6 | ko_fi: # Replace with a single Ko-fi username 7 | tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel 8 | community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry 9 | liberapay: # Replace with a single Liberapay username 10 | issuehunt: # Replace with a single IssueHunt username 11 | otechie: # Replace with a single Otechie username 12 | custom: # Replace with up to 4 custom sponsorship URLs e.g., ['link1', 'link2'] 13 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Xilinx Vivado 2 | *.cache 3 | *.hw 4 | *.ip_user_files 5 | *.runs 6 | *.sim 7 | *.srcs 8 | *.Xil 9 | *.xpr 10 | webtalk.* 11 | 12 | # iCE40 13 | *yosys.log 14 | *.bin 15 | *.rpt 16 | 17 | # ECP5 18 | *yosys.log 19 | *.bit 20 | *.svf 21 | 22 | # Verilator 23 | obj_dir 24 | 25 | # cocotb 26 | results*.xml 27 | sim_build* 28 | __pycache__ 29 | *.vcd 30 | 31 | # Mac 32 | .DS_Store 33 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing to Project F 2 | 3 | Project F welcomes contributions from beginners and experts alike. We have a few simple policies to ensure new designs are compatible with the project goals. This document is a draft; we will expand it as needed. 4 | 5 | ## Simple 6 | 7 | Our designs are self-contained and simple to understand. Complex or overly clever designs are unlikely to be accepted. 8 | 9 | ## Universal 10 | 11 | Avoid vendor-specific IP. We want our designs to work on as many FPGAs as possible. See [FPGA Architecture](README.md#fpga-architecture) for examples of acceptable vendor-specific functionality. 12 | 13 | ## Development Language 14 | 15 | Write your designs in SystemVerilog and follow the style of existing modules. Familiarise yourself with a few modules from the library before submitting a PR. 16 | 17 | SystemVerilog has many valuable additions over older Verilog standards, but we restrict ourselves to simple, widely-supported SV features. See [SystemVerilog Features](README.md#systemverilog) for what's currently allowed. 18 | 19 | ## Additional Dev Boards 20 | 21 | While we love to see Project F designs ported to new dev boards, we only accept new ports into the repo if we can test them. Otherwise, we won't be able to maintain your code after it's merged. If you want us to mention a fork, talk to us on the [Project F discussion forum](https://github.com/projf/projf-explore/discussions), and we'll consider linking to it from the Project F blog and docs. 22 | 23 | ## Linting 24 | 25 | Designs must pass a Verilator lint with: `verilator --lint-only -Wall` 26 | 27 | ## Discuss Significant Changes 28 | 29 | Use the [Project F discussion forum](https://github.com/projf/projf-explore/discussions) to discuss significant changes before submitting a PR. 30 | 31 | ## Small PRs 32 | 33 | Please keep your PRs small. Submitting tens of new files or changes together makes testing and merging almost impossible. 34 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Will Green, Project F 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /ROADMAP.md: -------------------------------------------------------------------------------- 1 | # Project F Roadmap 2 | 3 | This doc summarises forthcoming work on Project F. 4 | 5 | Until then, check out the latest [Project F News](https://projectf.io/tags/news/). 6 | 7 | * Maths and Algorithms 8 | * Verilog Vectors and Arrays (in progress) 9 | * Revised Intro to Fixed-Point (coming soon) 10 | * _more maths in 2023_ 11 | * Board Support 12 | * Nexys Video support for _FPGA Graphics_ (in progress) 13 | * Demos 14 | * Port remaining _All You Need Effects_ to Arty 15 | * _more demo effects in 2023_ 16 | * Future Ideas (TBC) 17 | * RISC-V CPU Designs 18 | * memory-mapped I/O 19 | * cocotb 20 | * Serial Protocols (UART, PS/2, SPI, I2C) 21 | * Audio Synth 22 | * 3D Graphics 23 | * Other Languages: Amaranth HDL, SpinalHDL etc. 24 | * Formal Verification 25 | 26 | See [About Project F](https://projectf.io/about/) and the repo [README](README.md) for an introduction to Project F. 27 | -------------------------------------------------------------------------------- /demos/ad-astra/README.md: -------------------------------------------------------------------------------- 1 | # Ad Astra 2 | 3 | These SystemVerilog examples use starfields and hardware sprites to build up a simple greetings demo. The final demo is in file `top_greet.sv`. 4 | 5 | I created Ad Astra in 2018; it was my first FPGA demo, but I didn't release it at a party (for one thing it has no music). 6 | This version remains similar to the original source, but has some minor updates to work with the Project F Verilog library. 7 | 8 | This demo has an associated Project F blog post: [Ad Astra](https://projectf.io/posts/fpga-ad-astra/). 9 | New to FPGA graphics design? Check out [Beginning FPGA Graphics](https://projectf.io/posts/fpga-graphics/). 10 | 11 | _NB. The included fonts are distributed under different licences: see the individual font files for details._ 12 | 13 | Included demos: 14 | 15 | * `top_lfsr` - simple background using a linear feedback register (LFSR) 16 | * `top_starfield` - layered starfields using multiple LFSRs 17 | * `top_space_f` - 'F' character overlaid on starfield using sprite 18 | * `top_hello_en` - multiple sprites spell "Hello" on starfield 19 | * `top_hello_jp` - multiple sprites spell "こんにちは" on starfield 20 | * `top_greet_v1` - greetings to open source hardware projects 21 | * `top_greet` - greetings to open source hardware projects with copper colours 22 | 23 | ![](../../doc/img/fpga-ad-astra.png?raw=true "") 24 | 25 | _Greetings generated by an Artix-7 FPGA._ 26 | 27 | ## Arty Build 28 | 29 | To create a Vivado project for the Digilent Arty ([original](https://digilent.com/reference/programmable-logic/arty/reference-manual) or [A7-35T](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console: 30 | 31 | ```tcl 32 | cd projf-explore/demos/ad-astra/xc7/vivado 33 | source ./create_project.tcl 34 | ``` 35 | 36 | You can then build `top_greet`, `top_hello_jp` etc. as you would for any Vivado project. 37 | -------------------------------------------------------------------------------- /demos/ad-astra/starfield.sv: -------------------------------------------------------------------------------- 1 | // Project F: Ad Astra - Starfield 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io/posts/fpga-ad-astra/ 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module starfield #( 9 | parameter H=800, 10 | parameter V=525, 11 | parameter INC=-1, 12 | parameter SEED=21'h1FFFFF, 13 | parameter MASK=21'hFFF 14 | ) ( 15 | input wire logic clk, // clock 16 | input wire logic en, // enable 17 | input wire logic rst, // reset 18 | output logic sf_on, // star on 19 | output logic [7:0] sf_star // star brightness 20 | ); 21 | 22 | localparam RST_CNT = H * V + INC - 1; // counter starts at zero, so sub 1 23 | logic [20:0] sf_reg, sf_cnt; 24 | 25 | always_ff @(posedge clk) begin 26 | if (en) begin 27 | sf_cnt <= sf_cnt + 1; 28 | /* verilator lint_off WIDTH */ 29 | if (sf_cnt == RST_CNT) sf_cnt <= 0; 30 | /* verilator lint_on WIDTH */ 31 | end 32 | if (rst) sf_cnt <= 0; 33 | end 34 | 35 | // select some bits to form stars 36 | always_comb begin 37 | sf_on = &{sf_reg | MASK}; 38 | sf_star = sf_reg[7:0]; 39 | end 40 | 41 | lfsr #( 42 | .LEN(21), 43 | .TAPS(21'b101000000000000000000) 44 | ) lsfr_sf ( 45 | .clk, 46 | .rst(sf_cnt == 21'b0), 47 | .en, 48 | .seed(SEED), 49 | .sreg(sf_reg) 50 | ); 51 | endmodule 52 | -------------------------------------------------------------------------------- /demos/ad-astra/xc7/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Ad Astra - Arty A7-35T Board Constraints 2 | ## (C)2022 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-ad-astra/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst_n}]; 15 | 16 | ## VGA Pmod on Header JB/JC 17 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {vga_hsync}]; 18 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {vga_vsync}]; 19 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {vga_r[0]}]; 20 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {vga_r[1]}]; 21 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {vga_r[2]}]; 22 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {vga_r[3]}]; 23 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {vga_g[0]}]; 24 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {vga_g[1]}]; 25 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {vga_g[2]}]; 26 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {vga_g[3]}]; 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {vga_b[0]}]; 28 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {vga_b[1]}]; 29 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {vga_b[2]}]; 30 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {vga_b[3]}]; 31 | -------------------------------------------------------------------------------- /demos/ad-astra/xc7/starfield_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F: Ad Astra - Starfield Testbench 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io/posts/fpga-ad-astra/ 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module starfield_tb(); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | 12 | logic rst; 13 | logic clk_100m; 14 | 15 | // starfields 16 | logic sf_on; 17 | logic [7:0] sf_star; 18 | 19 | starfield starfield_inst ( 20 | .clk(clk_100m), 21 | .en(1'b1), 22 | .rst, 23 | .sf_on(sf_on), 24 | .sf_star(sf_star) 25 | ); 26 | 27 | // generate clock 28 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 29 | 30 | initial begin 31 | rst = 1; 32 | clk_100m = 1; 33 | 34 | #100 rst = 0; 35 | #4_200_000 $finish; 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /demos/ad-astra/xc7/vivado/starfield_tb_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | rst 25 | rst 26 | 27 | 28 | clk_100m 29 | clk_100m 30 | 31 | 32 | sf_on 33 | sf_on 34 | 35 | 36 | sf_star[7:0] 37 | sf_star[7:0] 38 | UNSIGNEDDECRADIX 39 | 40 | 41 | -------------------------------------------------------------------------------- /demos/castle-drawing/README.md: -------------------------------------------------------------------------------- 1 | # Castle Drawing 2 | 3 | This SystemVerilog drawing demo uses shapes to build a simple castle and rainbow in 16 colours. 4 | 5 | This design has an associated Project F blog post: [Castle Drawing](https://projectf.io/posts/castle-drawing/). 6 | New to FPGA graphics design? Check out [Beginning FPGA Graphics](https://projectf.io/posts/fpga-graphics/). 7 | 8 | ![](../../doc/img/castle-sim.png?raw=true "") 9 | 10 | _Castle drawn by Verilator/SDL sim._ 11 | 12 | ## Arty Build 13 | 14 | To create a Vivado project for the Digilent Arty ([original](https://digilent.com/reference/programmable-logic/arty/reference-manual) or [A7-35T](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console: 15 | 16 | ```tcl 17 | cd projf-explore/demos/castle-drawing/xc7/vivado 18 | source ./create_project.tcl 19 | ``` 20 | 21 | You can then build `top_castle` as you would for any Vivado project. 22 | 23 | ## Verilator 24 | 25 | ### Tested Versions 26 | 27 | This simulation have been tested with: 28 | 29 | * Verilator 4.038 (Ubuntu 22.04 amd64) 30 | * Verilator 5.006 (macOS 13 arm64) 31 | 32 | ### Verilator Build 33 | 34 | If this is the first time you've used Verilator and SDL, you need to [install dependencies](https://projectf.io/posts/verilog-sim-verilator-sdl/#installing-dependencies). 35 | 36 | Make sure you're in the sim directory `projf-explore/demos/castle-drawing/sim`. 37 | 38 | Build the demo: 39 | 40 | ```shell 41 | make 42 | ``` 43 | 44 | Run the simulation executable from `obj_dir`: 45 | 46 | ```shell 47 | ./obj_dir/castle 48 | ``` 49 | 50 | You can quit the simulation by pressing the **Q** key. 51 | 52 | ### Fullscreen Mode 53 | 54 | To run in fullscreen mode, edit `main_castle.cpp` so that `FULLSCREEN = true`, then rebuild. 55 | -------------------------------------------------------------------------------- /demos/castle-drawing/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Castle Drawing- Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/castle-drawing/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | # Project F Verilog Library 10 | PROJF_LIBS += -I../../../lib/clock 11 | PROJF_LIBS += -I../../../lib/display 12 | PROJF_LIBS += -I../../../lib/graphics 13 | PROJF_LIBS += -I../../../lib/memory 14 | 15 | castle: castle.exe 16 | 17 | %.exe: %.mk 18 | make -C ./obj_dir -f Vtop_$< 19 | 20 | %.mk: top_%.sv 21 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 22 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 23 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 24 | 25 | all: castle 26 | 27 | clean: 28 | rm -rf ./obj_dir 29 | 30 | .PHONY: all clean 31 | -------------------------------------------------------------------------------- /demos/life-on-screen/README.md: -------------------------------------------------------------------------------- 1 | # Life on Screen 2 | 3 | This SystemVerilog demo effect uses an (old) framebuffer to render Conway's Game of Life. 4 | 5 | This design has an associated Project F blog post: [Life on Screen](https://projectf.io/posts/life-on-screen/). 6 | New to FPGA graphics design? Check out [Beginning FPGA Graphics](https://projectf.io/posts/fpga-graphics/). 7 | 8 | ![](../../doc/img/life-on-screen.png?raw=true "") 9 | 10 | _Gosper glider gun generated by an Artix-7 FPGA._ 11 | 12 | ## Arty Build 13 | 14 | To create a Vivado project for the Digilent Arty ([original](https://digilent.com/reference/programmable-logic/arty/reference-manual) or [A7-35T](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console: 15 | 16 | ```tcl 17 | cd projf-explore/demos/life-on-screen/xc7/vivado 18 | source ./create_project.tcl 19 | ``` 20 | 21 | You can then build `top_life` as you would for any Vivado project. 22 | -------------------------------------------------------------------------------- /demos/life-on-screen/lint.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Project F: Lint Script 4 | # (C)2023 Will Green, open source software released under the MIT License 5 | # Learn more at https://projectf.io/posts/verilog-lint-with-verilator/ 6 | 7 | # NB. This demo uses local framebuffer & linebuffer modules. 8 | 9 | DIR=`dirname $0` 10 | LIB="${DIR}/../../lib" 11 | 12 | # Xilinx 7 Series (VGA Output) 13 | if [ -d "${DIR}/xc7" ]; then 14 | echo "## Linting top modules in ${DIR}/xc7" 15 | for f in ${DIR}/xc7/top_*\.*v; do 16 | echo "## Checking ${f}"; 17 | verilator --lint-only -Wall -I${DIR} -I${DIR}/xc7 \ 18 | -I${LIB}/clock -I${LIB}/clock/xc7 \ 19 | -I${LIB}/display -I${LIB}/display/xc7 \ 20 | -I${LIB}/essential -I${LIB}/essential/xc7 \ 21 | -I${LIB}/graphics -I${LIB}/graphics/xc7 \ 22 | -I${LIB}/maths -I${LIB}/maths/xc7 \ 23 | -I${LIB}/memory -I${LIB}/memory/xc7 \ 24 | -I${DIR}/lib/display \ 25 | -I${LIB}/null/xc7 $f; 26 | done 27 | fi 28 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/life_palette.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Life Palette (2 bit) 2 | // Learn more at https://projectf.io 3 | 000 // 0 - black 4 | FFF // 1 - white 5 | FA0 // 2 - orange 6 | 0E3 // 3 - green 7 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/beacon.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Beacon (Oscillator) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 1 1 0 0 0 0 7 | 0 0 1 1 0 0 0 0 8 | 0 0 0 0 1 1 0 0 9 | 0 0 0 0 1 1 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 1 1 0 0 0 0 15 | 0 0 1 1 0 0 0 0 16 | 0 0 0 0 1 1 0 0 17 | 0 0 0 0 1 1 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 20 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/beehive.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Beehive (Still Life) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 0 1 1 0 0 0 7 | 0 0 1 0 0 1 0 0 8 | 0 0 0 1 1 0 0 0 9 | 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 0 1 1 0 0 0 15 | 0 0 1 0 0 1 0 0 16 | 0 0 0 1 1 0 0 0 17 | 0 0 0 0 0 0 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 20 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/blinker.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Blinker (Oscillator) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 0 1 0 0 0 0 7 | 0 0 0 1 0 0 0 0 8 | 0 0 0 1 0 0 0 0 9 | 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 0 1 0 0 0 0 15 | 0 0 0 1 0 0 0 0 16 | 0 0 0 1 0 0 0 0 17 | 0 0 0 0 0 0 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 20 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/block.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Block (Still Life) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 0 1 1 0 0 0 7 | 0 0 0 1 1 0 0 0 8 | 0 0 0 0 0 0 0 0 9 | 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 0 1 1 0 0 0 15 | 0 0 0 1 1 0 0 0 16 | 0 0 0 0 0 0 0 0 17 | 0 0 0 0 0 0 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 20 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/empty.mem: -------------------------------------------------------------------------------- 1 | // Project F: Empty 2 | // 6x6 world with 1 cell of padding (8x8) 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 0 0 0 0 0 0 7 | 0 0 0 0 0 0 0 0 8 | 0 0 0 0 0 0 0 0 9 | 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 13 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/glider.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Glider (Spaceship) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 1 0 0 0 0 0 7 | 0 0 0 1 1 0 0 0 8 | 0 0 1 1 0 0 0 0 9 | 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 1 0 0 0 0 0 15 | 0 0 0 1 1 0 0 0 16 | 0 0 1 1 0 0 0 0 17 | 0 0 0 0 0 0 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 20 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/loaf.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Loaf (Still Life) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 0 1 1 0 0 0 7 | 0 0 1 0 0 1 0 0 8 | 0 0 0 1 0 1 0 0 9 | 0 0 0 0 1 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 0 1 1 0 0 0 15 | 0 0 1 0 0 1 0 0 16 | 0 0 0 1 0 1 0 0 17 | 0 0 0 0 1 0 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 20 | -------------------------------------------------------------------------------- /demos/life-on-screen/res/test/toad.mem: -------------------------------------------------------------------------------- 1 | // Project F: Life on Screen - Test: Toad (Oscillator) 2 | // 6x6 world with 1 cell of padding (8x8) - duplicated to fill sim buffer 3 | // Learn more at https://projectf.io 4 | 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 6 | 0 0 0 1 1 1 0 0 7 | 0 0 1 1 1 0 0 0 8 | 0 0 0 0 0 0 0 0 9 | 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 12 | 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 14 | 0 0 0 1 1 1 0 0 15 | 0 0 1 1 1 0 0 0 16 | 0 0 0 0 0 0 0 0 17 | 0 0 0 0 0 0 0 0 18 | 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 -------------------------------------------------------------------------------- /demos/mandelbrot/verilator-sdl/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Verilator/SDL Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | 4 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 5 | SDL_CFLAGS = `sdl2-config --cflags` 6 | SDL_LDFLAGS = `sdl2-config --libs` 7 | 8 | # Project F Verilog Library 9 | PROJF_LIBS += -I../../../lib/clock 10 | PROJF_LIBS += -I../../../lib/display 11 | PROJF_LIBS += -I../../../lib/essential 12 | PROJF_LIBS += -I../../../lib/graphics 13 | PROJF_LIBS += -I../../../lib/maths 14 | PROJF_LIBS += -I../../../lib/memory 15 | 16 | mandel: mandel.exe 17 | 18 | %.exe: %.mk 19 | make -C ./obj_dir -f Vtop_$< 20 | 21 | %.mk: top_%.sv 22 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 23 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 24 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 25 | 26 | all: mandel 27 | 28 | clean: 29 | rm -rf ./obj_dir 30 | 31 | .PHONY: all clean 32 | -------------------------------------------------------------------------------- /demos/rasterbars/README.md: -------------------------------------------------------------------------------- 1 | # Rasterbars 2 | 3 | Design from the demo "All You Need" by Chapterhouse released at Revision 2022 (with minor emendations). 4 | 5 | This demo effect has an associated Project F blog post: [Rasterbars](https://projectf.io/posts/rasterbars/). 6 | New to FPGA graphics design? Check out [Beginning FPGA Graphics](https://projectf.io/posts/fpga-graphics/). 7 | 8 | ![](../../doc/img/rasterbars-sim.png?raw=true "") 9 | 10 | _Rasters with Verilator/SDL sim._ 11 | 12 | ## Arty Build 13 | 14 | To create a Vivado project for the Digilent Arty ([original](https://digilent.com/reference/programmable-logic/arty/reference-manual) or [A7-35T](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console: 15 | 16 | ```tcl 17 | cd projf-explore/demos/rasterbars/xc7/vivado 18 | source ./create_project.tcl 19 | ``` 20 | 21 | You can then build `top_rasterbars` as you would for any Vivado project. 22 | 23 | ## Verilator 24 | 25 | ### Tested Versions 26 | 27 | This simulation have been tested with: 28 | 29 | * Verilator 4.038 (Ubuntu 22.04 amd64) 30 | * Verilator 5.006 (macOS 13 arm64) 31 | 32 | ### Verilator Build 33 | 34 | If this is the first time you've used Verilator and SDL, you need to [install dependencies](https://projectf.io/posts/verilog-sim-verilator-sdl/#installing-dependencies). 35 | 36 | Make sure you're in the sim directory `projf-explore/demos/rasterbars/sim`. 37 | 38 | Build the demo: 39 | 40 | ```shell 41 | make 42 | ``` 43 | 44 | Run the simulation executable from `obj_dir`: 45 | 46 | ```shell 47 | ./obj_dir/rasterbars 48 | ``` 49 | 50 | You can quit the simulation by pressing the **Q** key. 51 | 52 | ### Fullscreen Mode 53 | 54 | To run in fullscreen mode, edit `main_rasterbars.cpp` so that `FULLSCREEN = true`, then rebuild. 55 | -------------------------------------------------------------------------------- /demos/rasterbars/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Rasterbars - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/rasterbars/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | # Project F Verilog Library 10 | PROJF_LIBS += -I../../../lib/clock 11 | PROJF_LIBS += -I../../../lib/display 12 | PROJF_LIBS += -I../../../lib/graphics 13 | PROJF_LIBS += -I../../../lib/maths 14 | PROJF_LIBS += -I../../../lib/memory 15 | 16 | rasterbars: rasterbars.exe 17 | 18 | %.exe: %.mk 19 | make -C ./obj_dir -f Vtop_$< 20 | 21 | %.mk: top_%.sv 22 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 23 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 24 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 25 | 26 | all: rasterbars 27 | 28 | clean: 29 | rm -rf ./obj_dir 30 | 31 | .PHONY: all clean 32 | -------------------------------------------------------------------------------- /demos/rasterbars/xc7/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Rasterbars - Arty A7-35T Board Constraints 2 | ## (C)2022 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/rasterbars/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst_n}]; 15 | 16 | ## VGA Pmod on Header JB/JC 17 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {vga_hsync}]; 18 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {vga_vsync}]; 19 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {vga_r[0]}]; 20 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {vga_r[1]}]; 21 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {vga_r[2]}]; 22 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {vga_r[3]}]; 23 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {vga_g[0]}]; 24 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {vga_g[1]}]; 25 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {vga_g[2]}]; 26 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {vga_g[3]}]; 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {vga_b[0]}]; 28 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {vga_b[1]}]; 29 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {vga_b[2]}]; 30 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {vga_b[3]}]; 31 | -------------------------------------------------------------------------------- /demos/sinescroll/README.md: -------------------------------------------------------------------------------- 1 | # Sine Scroller 2 | 3 | Design from the demo "All You Need" by Chapterhouse released at Revision 2022 (with minor emendations). 4 | 5 | This demo effect has an associated Project F blog post: [Sine Scroller](https://projectf.io/posts/sinescroll/). 6 | New to FPGA graphics design? Check out [Beginning FPGA Graphics](https://projectf.io/posts/fpga-graphics/). 7 | 8 | ![](../../doc/img/sinescroll-sim.png?raw=true "") 9 | 10 | _Scrolling with Verilator/SDL sim._ 11 | 12 | ## Arty Build 13 | 14 | To create a Vivado project for the Digilent Arty ([original](https://digilent.com/reference/programmable-logic/arty/reference-manual) or [A7-35T](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console: 15 | 16 | ```tcl 17 | cd projf-explore/demos/sinescroll/xc7/vivado 18 | source ./create_project.tcl 19 | ``` 20 | 21 | You can then build `top_sinescroll` as you would for any Vivado project. 22 | 23 | ## Verilator 24 | 25 | ### Tested Versions 26 | 27 | This simulation have been tested with: 28 | 29 | * Verilator 4.038 (Ubuntu 22.04 amd64) 30 | * Verilator 5.006 (macOS 13 arm64) 31 | 32 | ### Verilator Build 33 | 34 | If this is the first time you've used Verilator and SDL, you need to [install dependencies](https://projectf.io/posts/verilog-sim-verilator-sdl/#installing-dependencies). 35 | 36 | Make sure you're in the sim directory `projf-explore/demos/sinescroll/sim`. 37 | 38 | Build the demo: 39 | 40 | ```shell 41 | make 42 | ``` 43 | 44 | Run the simulation executable from `obj_dir`: 45 | 46 | ```shell 47 | ./obj_dir/sinescroll 48 | ``` 49 | 50 | You can quit the simulation by pressing the **Q** key. 51 | 52 | ### Fullscreen Mode 53 | 54 | To run in fullscreen mode, edit `main_sinescroll.cpp` so that `FULLSCREEN = true`, then rebuild. 55 | -------------------------------------------------------------------------------- /demos/sinescroll/res/text/greet.mem: -------------------------------------------------------------------------------- 1 | // Project F: Sine Scroll Greetings ROM 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io/posts/sinescroll/ 4 | 5 | 41 4C 4C 20 59 4F 55 20 4E 45 45 44 2E 2E 2E 20 49 53 20 4C 55 54 53 21 20 41 4E 20 46 50 47 41 20 44 45 4D 4F 20 46 4F 52 20 52 45 56 49 53 49 4F 4E 20 32 30 32 32 20 42 59 20 43 48 41 50 54 45 52 48 4F 55 53 45 6 | -------------------------------------------------------------------------------- /demos/sinescroll/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Sine Scroller - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/sinescroll/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | # Project F Verilog Library 10 | PROJF_LIBS += -I../../../lib/clock 11 | PROJF_LIBS += -I../../../lib/display 12 | PROJF_LIBS += -I../../../lib/graphics 13 | PROJF_LIBS += -I../../../lib/maths 14 | PROJF_LIBS += -I../../../lib/memory 15 | 16 | sinescroll: sinescroll.exe 17 | 18 | %.exe: %.mk 19 | make -C ./obj_dir -f Vtop_$< 20 | 21 | %.mk: top_%.sv 22 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 23 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 24 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 25 | 26 | all: sinescroll 27 | 28 | clean: 29 | rm -rf ./obj_dir 30 | 31 | .PHONY: all clean 32 | -------------------------------------------------------------------------------- /doc/img/2d-shapes-sim.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/doc/img/2d-shapes-sim.png -------------------------------------------------------------------------------- /doc/img/2d-shapes.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/doc/img/2d-shapes.jpg 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https://projectf.io/posts/fpga-shapes/ 4 | 5 | # render module version 6 | RENDER_MODS = 160x90 7 | 8 | # configuration 9 | SHELL = /bin/sh 10 | FPGA_PKG = sg48 11 | FPGA_TYPE = up5k 12 | PCF = icebreaker.pcf 13 | 14 | # included modules 15 | PATH_LIB = ../../../lib 16 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 17 | ADD_SRC += ${PATH_LIB}/clock/xd.sv 18 | ADD_SRC += ${PATH_LIB}/display/bitmap_addr.sv 19 | ADD_SRC += ${PATH_LIB}/display/clut_simple.sv 20 | ADD_SRC += ${PATH_LIB}/display/display_480p.sv 21 | ADD_SRC += ${PATH_LIB}/display/linebuffer_simple.sv 22 | ADD_SRC += ${PATH_LIB}/graphics/draw_*.sv 23 | ADD_SRC += ${PATH_LIB}/memory/bram_sdp.sv 24 | ADD_SRC += ../${RENDER_MODS}/render_*.sv 25 | 26 | demo: demo.rpt demo.bin 27 | 28 | %.json: top_%.sv $(ADD_SRC) 29 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 30 | 31 | %.asc: %.json 32 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 33 | 34 | %.rpt: %.asc 35 | icetime -d ${FPGA_TYPE} -mtr $@ $< 36 | 37 | %.bin: %.asc 38 | icepack $< $(subst top_,,$@) 39 | 40 | all: demo 41 | 42 | clean: 43 | rm -f *.json *.asc *.rpt *.bin *yosys.log 44 | 45 | .PHONY: all clean 46 | -------------------------------------------------------------------------------- /graphics/2d-shapes/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: 2D Shapes - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-shapes/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/2d-shapes/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: 2D Shapes - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-shapes/ 4 | 5 | # render module version 6 | RENDER_MODS = '320x180' 7 | 8 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 9 | SDL_CFLAGS = `sdl2-config --cflags` 10 | SDL_LDFLAGS = `sdl2-config --libs` 11 | 12 | # Project F Verilog Library 13 | PROJF_LIBS += -I../../../lib/clock 14 | PROJF_LIBS += -I../../../lib/display 15 | PROJF_LIBS += -I../../../lib/graphics 16 | PROJF_LIBS += -I../../../lib/memory 17 | 18 | demo: demo.exe 19 | 20 | %.exe: %.mk 21 | make -C ./obj_dir -f Vtop_$< 22 | 23 | %.mk: top_%.sv 24 | verilator ${VFLAGS} -I.. -I../${RENDER_MODS} ${PROJF_LIBS} \ 25 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 26 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 27 | 28 | all: demo 29 | 30 | clean: 31 | rm -rf ./obj_dir 32 | 33 | .PHONY: all clean 34 | -------------------------------------------------------------------------------- /graphics/2d-shapes/xc7-dvi/2d-shapes-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/2d-shapes/xc7-dvi/2d-shapes-bitstreams.zip -------------------------------------------------------------------------------- /graphics/2d-shapes/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: 2D Shapes - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-shapes/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Pixel Clock is async to System Clock 14 | set_clock_groups -name SysPixel -asynchronous \ 15 | -group [get_clocks -of_objects [get_pins clock_sys_inst/MMCME2_BASE_inst/CLKOUT0]] \ 16 | -group [get_clocks -of_objects [get_pins clock_pix_inst/MMCME2_BASE_inst/CLKOUT1]]; 17 | 18 | ## Buttons 19 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 20 | 21 | ## HDMI Source 22 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 23 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 24 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 25 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 26 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 27 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 28 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 29 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 30 | -------------------------------------------------------------------------------- /graphics/animated-shapes/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Animated Shapes - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/animated-shapes/ 4 | 5 | # render module version 6 | RENDER_MODS = 160x90 7 | 8 | # configuration 9 | SHELL = /bin/sh 10 | FPGA_PKG = sg48 11 | FPGA_TYPE = up5k 12 | PCF = icebreaker.pcf 13 | 14 | # included modules 15 | PATH_LIB = ../../../lib 16 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 17 | ADD_SRC += ${PATH_LIB}/clock/xd.sv 18 | ADD_SRC += ${PATH_LIB}/display/bitmap_addr.sv 19 | ADD_SRC += ${PATH_LIB}/display/clut_simple.sv 20 | ADD_SRC += ${PATH_LIB}/display/display_480p.sv 21 | ADD_SRC += ${PATH_LIB}/display/linebuffer_simple.sv 22 | ADD_SRC += ${PATH_LIB}/graphics/draw_*.sv 23 | ADD_SRC += ${PATH_LIB}/memory/bram_sdp.sv 24 | ADD_SRC += ../${RENDER_MODS}/render_*.sv 25 | 26 | demo: demo.rpt demo.bin 27 | demo_sb: demo_sb.rpt demo_sb.bin 28 | 29 | %.json: top_%.sv $(ADD_SRC) 30 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 31 | 32 | %.asc: %.json 33 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 34 | 35 | %.rpt: %.asc 36 | icetime -d ${FPGA_TYPE} -mtr $@ $< 37 | 38 | %.bin: %.asc 39 | icepack $< $(subst top_,,$@) 40 | 41 | all: demo demo_sb 42 | 43 | clean: 44 | rm -f *.json *.asc *.rpt *.bin *yosys.log 45 | 46 | .PHONY: all clean 47 | -------------------------------------------------------------------------------- /graphics/animated-shapes/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: Animated Shapes - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/animated-shapes/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/animated-shapes/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Animated Shapes - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/animated-shapes/ 4 | 5 | # render module version 6 | RENDER_MODS = '320x180' 7 | 8 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 9 | SDL_CFLAGS = `sdl2-config --cflags` 10 | SDL_LDFLAGS = `sdl2-config --libs` 11 | 12 | # Project F Verilog Library 13 | PROJF_LIBS += -I../../../lib/clock 14 | PROJF_LIBS += -I../../../lib/display 15 | PROJF_LIBS += -I../../../lib/graphics 16 | PROJF_LIBS += -I../../../lib/memory 17 | 18 | demo: demo.exe 19 | demo_sb: demo_sb.exe 20 | 21 | %.exe: %.mk 22 | make -C ./obj_dir -f Vtop_$< 23 | 24 | %.mk: top_%.sv 25 | verilator ${VFLAGS} -I.. -I../${RENDER_MODS} ${PROJF_LIBS} \ 26 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 27 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 28 | 29 | all: demo demo_sb 30 | 31 | clean: 32 | rm -rf ./obj_dir 33 | 34 | .PHONY: all clean 35 | -------------------------------------------------------------------------------- /graphics/animated-shapes/xc7-dvi/animated-shapes-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/animated-shapes/xc7-dvi/animated-shapes-bitstreams.zip -------------------------------------------------------------------------------- /graphics/animated-shapes/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Animated Shapes - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/animated-shapes/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Pixel Clock is async to System Clock 14 | set_clock_groups -name SysPixel -asynchronous \ 15 | -group [get_clocks -of_objects [get_pins clock_sys_inst/MMCME2_BASE_inst/CLKOUT0]] \ 16 | -group [get_clocks -of_objects [get_pins clock_pix_inst/MMCME2_BASE_inst/CLKOUT1]]; 17 | 18 | ## Buttons 19 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 20 | 21 | ## HDMI Source 22 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 23 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 24 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 25 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 26 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 27 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 28 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 29 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 30 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/ecp5/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - ULX3S Makefile 2 | ## Copyright Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | ## FPGA IC (enable one) 6 | # FPGA_TYPE = 12k # LFE5U-12 7 | # FPGA_TYPE = 25k # LFE5U-25 8 | # FPGA_TYPE = 45k # LFE5U-45 9 | FPGA_TYPE = 85k # LFE5U-85 10 | 11 | ## configuration 12 | SHELL = /bin/sh 13 | FPGA_PKG = CABGA381 # IC package 14 | FPGA_SPEED = 8 # FPGA speed grade (6,7,8) - all parts seem fine with fastest speed 15 | LPF = ulx3s.lpf # pins and constraints 16 | TARGET_FREQ = 74 # target frequency (MHz) for 1280x720 17 | 18 | # included modules 19 | PATH_LIB = ../../../lib 20 | ADD_SRC += ${PATH_LIB}/clock/ecp5/clock2_gen.v 21 | ADD_SRC += ${PATH_LIB}/display/ecp5/dvi_generator.sv 22 | ADD_SRC += ${PATH_LIB}/display/tmds_encoder_dvi.sv 23 | ADD_SRC += ../simple_720p.sv 24 | 25 | square: square.bit square.svf 26 | flag_ethiopia: flag_ethiopia.bit flag_ethiopia.svf 27 | flag_sweden: flag_sweden.bit flag_sweden.svf 28 | colour: colour.bit colour.svf 29 | 30 | # synthesis 31 | %.json: top_%.sv $(ADD_SRC) 32 | yosys -ql $(basename $@)-yosys.log -p 'synth_ecp5 -top top_$(basename $@) -json $@' $< $(ADD_SRC) 33 | 34 | # place and route 35 | %.config: %.json 36 | nextpnr-ecp5 --${FPGA_TYPE} --package ${FPGA_PKG} --freq ${TARGET_FREQ} --speed ${FPGA_SPEED} --json $< --textcfg $@ --lpf ${LPF} 37 | 38 | # pack bitstream 39 | %.bit: %.config 40 | ecppack --compress $< $@ 41 | 42 | # pack SVF (Serial Vector Format) 43 | %.svf: %.config 44 | ecppack --compress --input $< --svf $@ 45 | 46 | all: square flag_ethiopia flag_sweden colour 47 | 48 | clean: 49 | rm -f *.json *.config *.bit .*.d *.svf *yosys.log 50 | 51 | .PHONY: all clean 52 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/ecp5/ulx3s.lpf: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - ULX3S Board Constraints 2 | ## Copyright Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | BLOCK RESETPATHS; 6 | BLOCK ASYNCPATHS; 7 | 8 | ## Board Clock: 25 MHz 9 | LOCATE COMP "clk_25m" SITE "G2"; 10 | IOBUF PORT "clk_25m" PULLMODE=NONE IO_TYPE=LVCMOS33; 11 | FREQUENCY PORT "clk_25m" 25 MHZ; 12 | 13 | ## Buttons 14 | LOCATE COMP "btn_rst_n" SITE "D6"; # use B0 for reset 15 | IOBUF PORT "btn_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 16 | 17 | ## HDMI-compatible connector (AKA GPDI) 18 | # NB. IO_TYPE=LVCMOS33D generates gpdi_dn from gpdi_dp 19 | LOCATE COMP "gpdi_dp[0]" SITE "A16"; # channel 0 + 20 | LOCATE COMP "gpdi_dn[0]" SITE "B16"; # channel 0 - 21 | LOCATE COMP "gpdi_dp[1]" SITE "A14"; # channel 1 + 22 | LOCATE COMP "gpdi_dn[1]" SITE "C14"; # channel 1 - 23 | LOCATE COMP "gpdi_dp[2]" SITE "A12"; # channel 2 + 24 | LOCATE COMP "gpdi_dn[2]" SITE "A13"; # channel 2 - 25 | LOCATE COMP "gpdi_dp[3]" SITE "A17"; # clock + 26 | LOCATE COMP "gpdi_dn[3]" SITE "B18"; # clock - 27 | IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; 28 | IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; 29 | IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; 30 | IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; 31 | IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; 32 | IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; 33 | IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; 34 | IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; 35 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - iCEBreaker Makefile 2 | ## Copyright Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | # configuration 6 | SHELL = /bin/sh 7 | FPGA_PKG = sg48 8 | FPGA_TYPE = up5k 9 | PCF = icebreaker.pcf 10 | 11 | # included modules 12 | PATH_LIB = ../../../lib 13 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 14 | ADD_SRC += ../simple_480p.sv 15 | 16 | square: square.rpt square.bin 17 | flag_ethiopia: flag_ethiopia.rpt flag_ethiopia.bin 18 | flag_sweden: flag_sweden.rpt flag_sweden.bin 19 | colour: colour.rpt colour.bin 20 | 21 | # synthesis 22 | %.json: top_%.sv $(ADD_SRC) 23 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 24 | 25 | # place and route 26 | %.asc: %.json 27 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 28 | 29 | # timing 30 | %.rpt: %.asc 31 | icetime -d ${FPGA_TYPE} -mtr $@ $< 32 | 33 | # pack bitstream 34 | %.bin: %.asc 35 | icepack $< $(subst top_,,$@) 36 | 37 | all: square flag_ethiopia flag_sweden colour 38 | 39 | clean: 40 | rm -f *.json *.asc *.rpt *.bin *yosys.log 41 | 42 | .PHONY: all clean 43 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | square: square.exe 10 | flag_ethiopia: flag_ethiopia.exe 11 | flag_sweden: flag_sweden.exe 12 | colour: colour.exe 13 | 14 | %.exe: %.mk 15 | make -C ./obj_dir -f Vtop_$< 16 | 17 | %.mk: top_%.sv 18 | verilator ${VFLAGS} -I.. \ 19 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 20 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 21 | 22 | all: square flag_ethiopia flag_sweden colour 23 | 24 | clean: 25 | rm -rf ./obj_dir 26 | 27 | .PHONY: all clean 28 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/xc7-dvi/fpga-graphics-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/fpga-graphics/xc7-dvi/fpga-graphics-bitstreams.zip -------------------------------------------------------------------------------- /graphics/fpga-graphics/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, Open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 15 | 16 | ## HDMI Source 17 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 18 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 19 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 20 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 21 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 22 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 23 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 24 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 25 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/xc7-dvi/simple_720p_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F: FPGA Graphics - Simple 1280x720p60 Display Test Bench (XC7) 2 | // (C)2023 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module simple_720p_tb(); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | parameter CORDW = 12; // screen coordinate width in bits 12 | 13 | logic rst; 14 | logic clk_100m; 15 | 16 | // generate pixel clock 17 | logic clk_pix; // pixel clock 18 | logic clk_pix_5x; // 5x pixel clock for 10:1 DDR SerDes 19 | logic clk_pix_locked; // pixel clock locked? 20 | clock_720p clock_pix_inst ( 21 | .clk_100m, 22 | .rst(rst), 23 | .clk_pix, 24 | .clk_pix_5x, 25 | .clk_pix_locked 26 | ); 27 | 28 | // display sync signals and coordinates 29 | logic [CORDW-1:0] sx, sy; 30 | logic hsync, vsync, de; 31 | simple_720p display_inst ( 32 | .clk_pix, 33 | .rst_pix(!clk_pix_locked), // wait for clock lock 34 | .sx, 35 | .sy, 36 | .hsync, 37 | .vsync, 38 | .de 39 | ); 40 | 41 | // generate clock 42 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 43 | 44 | initial begin 45 | rst = 1; 46 | clk_100m = 1; 47 | 48 | #100 rst = 0; 49 | #20_000_000 $finish; // 18 ms (one frame is 16.7 ms) 50 | end 51 | endmodule 52 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/xc7/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Graphics - Arty A7-35T Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst_n}]; 15 | 16 | ## VGA Pmod on Header JB/JC 17 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {vga_hsync}]; 18 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {vga_vsync}]; 19 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {vga_r[0]}]; 20 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {vga_r[1]}]; 21 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {vga_r[2]}]; 22 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {vga_r[3]}]; 23 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {vga_g[0]}]; 24 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {vga_g[1]}]; 25 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {vga_g[2]}]; 26 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {vga_g[3]}]; 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {vga_b[0]}]; 28 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {vga_b[1]}]; 29 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {vga_b[2]}]; 30 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {vga_b[3]}]; 31 | -------------------------------------------------------------------------------- /graphics/fpga-graphics/xc7/simple_480p_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F: FPGA Graphics - Simple 640x480p60 Display Test Bench (XC7) 2 | // (C)2023 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io/posts/fpga-graphics/ 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module simple_480p_tb(); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | parameter CORDW = 10; // screen coordinate width in bits 12 | 13 | logic rst; 14 | logic clk_100m; 15 | 16 | // generate pixel clock 17 | logic clk_pix; // pixel clock 18 | logic clk_pix_5x; // 5x pixel clock for 10:1 DDR SerDes 19 | logic clk_pix_locked; // pixel clock locked? 20 | clock_480p clock_pix_inst ( 21 | .clk_100m, 22 | .rst(rst), 23 | .clk_pix, 24 | .clk_pix_5x, 25 | .clk_pix_locked 26 | ); 27 | 28 | // display sync signals and coordinates 29 | logic [CORDW-1:0] sx, sy; 30 | logic hsync, vsync, de; 31 | simple_480p display_inst ( 32 | .clk_pix, 33 | .rst_pix(!clk_pix_locked), // wait for clock lock 34 | .sx, 35 | .sy, 36 | .hsync, 37 | .vsync, 38 | .de 39 | ); 40 | 41 | // generate clock 42 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 43 | 44 | initial begin 45 | rst = 1; 46 | clk_100m = 1; 47 | 48 | #100 rst = 0; 49 | #20_000_000 $finish; // 18 ms (one frame is 16.7 ms) 50 | end 51 | endmodule 52 | -------------------------------------------------------------------------------- /graphics/framebuffers/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Framebuffers - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/framebuffers/ 4 | 5 | # configuration 6 | SHELL = /bin/sh 7 | FPGA_PKG = sg48 8 | FPGA_TYPE = up5k 9 | PCF = icebreaker.pcf 10 | 11 | # included modules 12 | PATH_LIB = ../../../lib 13 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 14 | ADD_SRC += ${PATH_LIB}/clock/xd.sv 15 | ADD_SRC += ${PATH_LIB}/display/clut_simple.sv 16 | ADD_SRC += ${PATH_LIB}/display/display_480p.sv 17 | ADD_SRC += ${PATH_LIB}/display/linebuffer_simple.sv 18 | ADD_SRC += ${PATH_LIB}/maths/lfsr.sv 19 | ADD_SRC += ${PATH_LIB}/memory/bram_sdp.sv 20 | 21 | david_mono: david_mono.rpt david_mono.bin 22 | david_16colr: david_16colr.rpt david_16colr.bin 23 | david_scale: david_scale.rpt david_scale.bin 24 | david_fizzle: david_fizzle.rpt david_fizzle.bin 25 | 26 | %.json: top_%.sv $(ADD_SRC) 27 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 28 | 29 | %.asc: %.json 30 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 31 | 32 | %.rpt: %.asc 33 | icetime -d ${FPGA_TYPE} -mtr $@ $< 34 | 35 | %.bin: %.asc 36 | icepack $< $(subst top_,,$@) 37 | 38 | all: david_mono david_16colr david_scale david_fizzle 39 | 40 | clean: 41 | rm -f *.json *.asc *.rpt *.bin *yosys.log 42 | 43 | .PHONY: all clean 44 | -------------------------------------------------------------------------------- /graphics/framebuffers/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: Framebuffers - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/framebuffers/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/framebuffers/res/david/david.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/framebuffers/res/david/david.png -------------------------------------------------------------------------------- /graphics/framebuffers/res/david/david_1bit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/framebuffers/res/david/david_1bit.png -------------------------------------------------------------------------------- /graphics/framebuffers/res/david/david_preview.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/framebuffers/res/david/david_preview.png -------------------------------------------------------------------------------- /graphics/framebuffers/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Framebuffers - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/framebuffers/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | # Project F Verilog Library 10 | PROJF_LIBS += -I../../../lib/clock 11 | PROJF_LIBS += -I../../../lib/display 12 | PROJF_LIBS += -I../../../lib/maths 13 | PROJF_LIBS += -I../../../lib/memory 14 | 15 | david_mono: david_mono.exe 16 | david_16colr: david_16colr.exe 17 | david_scale: david_scale.exe 18 | david_fizzle: david_fizzle.exe 19 | 20 | %.exe: %.mk 21 | make -C ./obj_dir -f Vtop_$< 22 | 23 | %.mk: top_%.sv 24 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 25 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 26 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 27 | 28 | all: david_mono david_16colr david_scale david_fizzle 29 | 30 | clean: 31 | rm -rf ./obj_dir 32 | 33 | .PHONY: all clean 34 | -------------------------------------------------------------------------------- /graphics/framebuffers/xc7-dvi/framebuffers-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/framebuffers/xc7-dvi/framebuffers-bitstreams.zip -------------------------------------------------------------------------------- /graphics/framebuffers/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Framebuffers - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/framebuffers/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Pixel Clock is async to System Clock 14 | set_clock_groups -name SysPixel -asynchronous \ 15 | -group [get_clocks -of_objects [get_pins clock_sys_inst/MMCME2_BASE_inst/CLKOUT0]] \ 16 | -group [get_clocks -of_objects [get_pins clock_pix_inst/MMCME2_BASE_inst/CLKOUT1]]; 17 | 18 | ## Buttons 19 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 20 | 21 | ## HDMI Source 22 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 23 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 24 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 25 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 26 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 27 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 28 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 29 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 30 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Hardware Sprites - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | # configuration 6 | SHELL = /bin/sh 7 | FPGA_PKG = sg48 8 | FPGA_TYPE = up5k 9 | PCF = icebreaker.pcf 10 | 11 | # included modules 12 | PATH_LIB = ../../../lib 13 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 14 | ADD_SRC += ${PATH_LIB}/display/clut_simple.sv 15 | ADD_SRC += ${PATH_LIB}/display/display_480p.sv 16 | ADD_SRC += ${PATH_LIB}/memory/bram_sdp.sv 17 | ADD_SRC += ${PATH_LIB}/memory/rom_async.sv 18 | ADD_SRC += ../sprite_inline.sv 19 | ADD_SRC += ../sprite_rom.sv 20 | ADD_SRC += ../sprite.sv 21 | 22 | tinyf_inline: tinyf_inline.rpt tinyf_inline.bin 23 | tinyf_rom: tinyf_rom.rpt tinyf_rom.bin 24 | tinyf_scale: tinyf_scale.rpt tinyf_scale.bin 25 | tinyf_move: tinyf_move.rpt tinyf_move.bin 26 | hourglass: hourglass.rpt hourglass.bin 27 | hedgehog: hedgehog.rpt hedgehog.bin 28 | 29 | %.json: top_%.sv $(ADD_SRC) 30 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 31 | 32 | %.asc: %.json 33 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 34 | 35 | %.rpt: %.asc 36 | icetime -d ${FPGA_TYPE} -mtr $@ $< 37 | 38 | %.bin: %.asc 39 | icepack $< $(subst top_,,$@) 40 | 41 | all: tinyf_inline tinyf_rom tinyf_scale tinyf_move hourglass hedgehog 42 | 43 | clean: 44 | rm -f *.json *.asc *.rpt *.bin *yosys.log 45 | 46 | .PHONY: all clean 47 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: Hardware Sprites - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/res/palettes/hedgehog_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F: Hardware Sprites - Hedgehog Palette (12-bit output) 2 | // Adapted from Team17 game Superfrog for demonstration purposes 3 | // Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | CCC // 0 6 | AAA // 1 7 | 888 // 2 8 | 874 // 3 9 | 763 // 4 10 | 651 // 5 11 | 540 // 6 12 | 330 // 7 13 | 111 // 8 14 | F0F // 9 - transparent 15 | 000 // A - unused 16 | 000 // B - unused 17 | 000 // C - unused 18 | 000 // D - unused 19 | 000 // E - unused 20 | 000 // F - unused 21 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/res/sprites/hedgehog.mem: -------------------------------------------------------------------------------- 1 | // Project F: Hardware Sprites - Hedgehog 32x20 pixels with 4-bit indexed colour 2 | // Adapted from Team17 game Superfrog for demonstration purposes 3 | // Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | 9 9 9 9 9 9 9 9 9 9 9 9 8 9 9 9 8 9 9 9 8 9 9 9 9 9 9 9 9 9 9 9 6 | 9 9 9 9 9 9 9 9 9 9 9 8 6 8 9 8 6 8 9 9 8 9 9 9 8 9 9 9 9 9 9 9 7 | 9 9 9 9 9 9 9 9 8 8 9 8 6 8 9 8 6 8 9 8 6 8 9 8 6 8 9 9 9 9 9 9 8 | 9 9 9 9 9 9 9 9 8 6 8 9 8 6 8 8 3 8 9 8 3 8 9 5 6 8 9 9 8 8 9 9 9 | 9 9 9 9 9 9 9 9 8 6 8 8 8 4 6 8 3 8 8 8 3 8 7 4 8 9 9 8 6 8 9 9 10 | 9 9 9 9 9 8 8 8 9 8 6 8 8 4 4 8 8 8 8 8 8 8 4 5 8 9 8 6 4 8 9 9 11 | 9 9 9 9 9 9 8 8 8 8 3 6 8 8 4 8 8 6 6 8 6 6 6 8 8 8 6 4 8 9 9 9 12 | 9 9 9 9 8 8 8 8 8 8 6 3 8 8 6 6 8 6 3 8 6 3 6 8 6 8 4 8 9 9 9 9 13 | 9 9 9 8 0 8 0 0 2 8 8 8 8 8 7 7 7 7 7 7 7 8 8 6 4 6 8 8 9 8 9 9 14 | 9 9 9 8 8 8 8 2 0 2 8 8 7 8 7 7 6 6 7 7 7 7 7 8 8 8 8 8 8 5 8 9 15 | 9 9 9 8 8 8 8 8 0 0 8 7 7 8 7 7 3 6 7 7 3 7 7 7 6 6 5 5 4 8 9 9 16 | 9 9 8 8 8 8 8 8 0 0 7 7 7 7 8 7 7 7 6 6 6 6 6 4 4 6 6 7 7 8 9 9 17 | 9 8 8 5 8 2 8 2 0 2 7 6 6 7 7 8 8 8 8 7 7 7 7 7 7 7 7 7 7 8 9 9 18 | 8 1 8 8 7 8 0 0 2 8 7 5 5 5 6 6 7 7 7 8 8 8 8 7 7 6 6 6 6 8 9 9 19 | 8 8 8 8 4 7 8 8 8 7 7 5 5 5 4 4 4 4 5 5 5 6 7 8 8 6 6 6 7 8 9 9 20 | 8 5 4 4 4 4 4 5 5 5 6 5 5 5 4 4 4 4 4 5 5 6 6 7 8 7 7 7 7 8 9 9 21 | 9 8 5 4 4 4 4 4 6 6 6 6 5 5 5 5 4 5 5 5 6 7 6 6 6 8 7 7 8 9 9 9 22 | 9 9 8 8 8 8 8 8 5 5 5 6 6 8 7 6 5 5 6 7 8 5 5 5 5 8 8 8 9 9 9 9 23 | 9 9 9 9 9 9 9 8 8 5 3 5 5 8 8 8 8 8 8 8 8 5 5 3 7 8 8 9 9 9 9 9 24 | 9 9 9 9 9 9 9 8 8 8 3 3 5 8 9 9 9 9 9 9 8 5 3 3 8 8 8 9 9 9 9 9 25 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/res/sprites/hourglass.mem: -------------------------------------------------------------------------------- 1 | // Project F: Hardware Sprites - Hourglass 8x8 pixels with 4-bit indexed colour 2 | // Made available under the CC-0 license (Public Domain) 3 | // Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | 0 0 0 0 0 0 0 0 6 | F 1 1 1 1 1 1 F 7 | F F 2 2 2 2 F F 8 | F F F 3 3 F F F 9 | F F F 4 4 F F F 10 | F F 5 5 5 5 F F 11 | F 6 6 6 6 6 6 F 12 | 7 7 7 7 7 7 7 7 13 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/res/sprites/letter_f.mem: -------------------------------------------------------------------------------- 1 | // Project F: Hardware Sprites - Letter "F" 8x8 pixels 2 | // Made available under the CC-0 license (Public Domain) 3 | // Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | 1 1 1 1 1 1 0 0 6 | 1 1 0 0 0 0 0 0 7 | 1 1 0 0 0 0 0 0 8 | 1 1 1 1 1 0 0 0 9 | 1 1 0 0 0 0 0 0 10 | 1 1 0 0 0 0 0 0 11 | 1 1 0 0 0 0 1 1 12 | 0 0 0 0 0 0 1 1 13 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Hardware Sprites - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | # Project F Verilog Library 10 | PROJF_LIBS += -I../../../lib/display 11 | PROJF_LIBS += -I../../../lib/memory 12 | 13 | tinyf_inline: tinyf_inline.exe 14 | tinyf_rom: tinyf_rom.exe 15 | tinyf_scale: tinyf_scale.exe 16 | tinyf_move: tinyf_move.exe 17 | hourglass: hourglass.exe 18 | hedgehog: hedgehog.exe 19 | 20 | %.exe: %.mk 21 | make -C ./obj_dir -f Vtop_$< 22 | 23 | %.mk: top_%.sv 24 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 25 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 26 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 27 | 28 | all: tinyf_inline tinyf_rom tinyf_scale tinyf_move hourglass hedgehog 29 | 30 | clean: 31 | rm -rf ./obj_dir 32 | 33 | .PHONY: all clean 34 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/xc7-dvi/hardware-sprites-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/hardware-sprites/xc7-dvi/hardware-sprites-bitstreams.zip -------------------------------------------------------------------------------- /graphics/hardware-sprites/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hardware Sprites - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 15 | 16 | ## HDMI Source 17 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 18 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 19 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 20 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 21 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 22 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 23 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 24 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 25 | -------------------------------------------------------------------------------- /graphics/hardware-sprites/xc7/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hardware Sprites - Arty A7-35T Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/hardware-sprites/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst_n}]; 15 | 16 | ## VGA Pmod on Header JB/JC 17 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {vga_hsync}]; 18 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {vga_vsync}]; 19 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {vga_r[0]}]; 20 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {vga_r[1]}]; 21 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {vga_r[2]}]; 22 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {vga_r[3]}]; 23 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {vga_g[0]}]; 24 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {vga_g[1]}]; 25 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {vga_g[2]}]; 26 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {vga_g[3]}]; 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {vga_b[0]}]; 28 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {vga_b[1]}]; 29 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {vga_b[2]}]; 30 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {vga_b[3]}]; 31 | -------------------------------------------------------------------------------- /graphics/lines-and-triangles/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Lines and Triangles - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/lines-and-triangles/ 4 | 5 | # render module version 6 | RENDER_MODS = 160x90 7 | 8 | # configuration 9 | SHELL = /bin/sh 10 | FPGA_PKG = sg48 11 | FPGA_TYPE = up5k 12 | PCF = icebreaker.pcf 13 | 14 | # included modules 15 | PATH_LIB = ../../../lib 16 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 17 | ADD_SRC += ${PATH_LIB}/clock/xd.sv 18 | ADD_SRC += ${PATH_LIB}/display/bitmap_addr.sv 19 | ADD_SRC += ${PATH_LIB}/display/clut_simple.sv 20 | ADD_SRC += ${PATH_LIB}/display/display_480p.sv 21 | ADD_SRC += ${PATH_LIB}/display/linebuffer_simple.sv 22 | ADD_SRC += ${PATH_LIB}/graphics/draw_*.sv 23 | ADD_SRC += ${PATH_LIB}/memory/bram_sdp.sv 24 | ADD_SRC += ../${RENDER_MODS}/render_*.sv 25 | 26 | demo: demo.rpt demo.bin 27 | 28 | %.json: top_%.sv $(ADD_SRC) 29 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 30 | 31 | %.asc: %.json 32 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 33 | 34 | %.rpt: %.asc 35 | icetime -d ${FPGA_TYPE} -mtr $@ $< 36 | 37 | %.bin: %.asc 38 | icepack $< $(subst top_,,$@) 39 | 40 | all: demo 41 | 42 | clean: 43 | rm -f *.json *.asc *.rpt *.bin *yosys.log 44 | 45 | .PHONY: all clean 46 | -------------------------------------------------------------------------------- /graphics/lines-and-triangles/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: Lines and Triangles - iCEBreaker Board Constraints (DVI) 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/lines-and-triangles/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/lines-and-triangles/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Lines and Triangles - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/lines-and-triangles/ 4 | 5 | # render module version 6 | RENDER_MODS = '320x180' 7 | 8 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 9 | SDL_CFLAGS = `sdl2-config --cflags` 10 | SDL_LDFLAGS = `sdl2-config --libs` 11 | 12 | # Project F Verilog Library 13 | PROJF_LIBS += -I../../../lib/clock 14 | PROJF_LIBS += -I../../../lib/display 15 | PROJF_LIBS += -I../../../lib/graphics 16 | PROJF_LIBS += -I../../../lib/memory 17 | 18 | demo: demo.exe 19 | 20 | %.exe: %.mk 21 | make -C ./obj_dir -f Vtop_$< 22 | 23 | %.mk: top_%.sv 24 | verilator ${VFLAGS} -I.. -I../${RENDER_MODS} ${PROJF_LIBS} \ 25 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 26 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 27 | 28 | all: demo 29 | 30 | clean: 31 | rm -rf ./obj_dir 32 | 33 | .PHONY: all clean 34 | -------------------------------------------------------------------------------- /graphics/lines-and-triangles/xc7-dvi/lines-and-triangles-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/lines-and-triangles/xc7-dvi/lines-and-triangles-bitstreams.zip -------------------------------------------------------------------------------- /graphics/lines-and-triangles/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Lines and Triangles - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/lines-and-triangles/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Pixel Clock is async to System Clock 14 | set_clock_groups -name SysPixel -asynchronous \ 15 | -group [get_clocks -of_objects [get_pins clock_sys_inst/MMCME2_BASE_inst/CLKOUT0]] \ 16 | -group [get_clocks -of_objects [get_pins clock_pix_inst/MMCME2_BASE_inst/CLKOUT1]]; 17 | 18 | ## Buttons 19 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 20 | 21 | ## HDMI Source 22 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 23 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 24 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 25 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 26 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 27 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 28 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 29 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 30 | -------------------------------------------------------------------------------- /graphics/pong/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Pong - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-pong/ 4 | 5 | # configuration 6 | SHELL = /bin/sh 7 | FPGA_PKG = sg48 8 | FPGA_TYPE = up5k 9 | PCF = icebreaker.pcf 10 | 11 | # included modules 12 | PATH_LIB = ../../../lib 13 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 14 | ADD_SRC += ${PATH_LIB}/essential/debounce.sv 15 | ADD_SRC += ../simple_480p.sv 16 | ADD_SRC += ../simple_score.sv 17 | 18 | pong: pong.rpt pong.bin 19 | 20 | %.json: top_%.sv $(ADD_SRC) 21 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 22 | 23 | %.asc: %.json 24 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 25 | 26 | %.rpt: %.asc 27 | icetime -d ${FPGA_TYPE} -mtr $@ $< 28 | 29 | %.bin: %.asc 30 | icepack $< $(subst top_,,$@) 31 | 32 | all: pong 33 | 34 | clean: 35 | rm -f *.json *.asc *.rpt *.bin *yosys.log 36 | 37 | .PHONY: all clean 38 | -------------------------------------------------------------------------------- /graphics/pong/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Pong - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-pong/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | set_io -nowarn btn_fire 19 12 | set_io -nowarn btn_up 18 13 | set_io -nowarn btn_dn 20 14 | 15 | ## 12-bit DVI Pmod on Pmod 1A/1B 16 | set_io -nowarn dvi_clk 38 17 | set_io -nowarn dvi_hsync 31 18 | set_io -nowarn dvi_vsync 28 19 | set_io -nowarn dvi_de 32 20 | set_io -nowarn dvi_r[0] 48 21 | set_io -nowarn dvi_r[1] 2 22 | set_io -nowarn dvi_r[2] 3 23 | set_io -nowarn dvi_r[3] 4 24 | set_io -nowarn dvi_g[0] 44 25 | set_io -nowarn dvi_g[1] 45 26 | set_io -nowarn dvi_g[2] 46 27 | set_io -nowarn dvi_g[3] 47 28 | set_io -nowarn dvi_b[0] 34 29 | set_io -nowarn dvi_b[1] 36 30 | set_io -nowarn dvi_b[2] 42 31 | set_io -nowarn dvi_b[3] 43 32 | -------------------------------------------------------------------------------- /graphics/pong/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Pong - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-pong/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | # Project F Library Path 10 | PROJF_LIBS = -I../../../lib/essential 11 | 12 | pong: pong.exe 13 | 14 | %.exe: %.mk 15 | make -C ./obj_dir -f Vtop_$< 16 | 17 | %.mk: top_%.sv 18 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 19 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 20 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 21 | 22 | all: pong 23 | 24 | clean: 25 | rm -rf ./obj_dir 26 | 27 | .PHONY: all clean 28 | -------------------------------------------------------------------------------- /graphics/pong/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: FPGA Pong - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/fpga-pong/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 15 | set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS12} [get_ports {btn_fire}]; 16 | set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS12} [get_ports {btn_up}]; 17 | set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS12} [get_ports {btn_dn}]; 18 | 19 | ## HDMI Source 20 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 21 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 22 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 23 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 24 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 25 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 26 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 27 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 28 | -------------------------------------------------------------------------------- /graphics/pong/xc7-dvi/pong-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/pong/xc7-dvi/pong-bitstreams.zip -------------------------------------------------------------------------------- /graphics/pong/xc7-dvi/vivado/build.tcl: -------------------------------------------------------------------------------- 1 | # Project F: FPGA Pong - Vivado Build Script (XC7 DVI) 2 | # (C)2023 Will Green, open source hardware released under the MIT License 3 | # Learn more at https://projectf.io/posts/fpga-pong/ 4 | 5 | # Using this script: 6 | # 1. Add Vivado env to shell: . /opt/Xilinx/Vivado/2022.2/settings64.sh 7 | # 2. Run build script: vivado -mode batch -nolog -nojournal -source build.tcl 8 | # 3. Program board: openFPGALoader -b nexysVideo ../pong.bit 9 | 10 | # build settings 11 | set design_name "pong" 12 | set arch "xc7-dvi" 13 | set board_name "nexys_video" 14 | set fpga_part "xc7a200tsbg484-1" 15 | 16 | # set reference directories for source files 17 | set lib_dir [file normalize "./../../../../lib"] 18 | set origin_dir [file normalize "./../../"] 19 | 20 | # read design sources 21 | read_verilog -sv "${lib_dir}/clock/xc7/clock_720p.sv" 22 | read_verilog -sv "${lib_dir}/display/tmds_encoder_dvi.sv" 23 | read_verilog -sv "${lib_dir}/display/xc7/dvi_generator.sv" 24 | read_verilog -sv "${lib_dir}/display/xc7/oserdes_10b.sv" 25 | read_verilog -sv "${lib_dir}/display/xc7/tmds_out.sv" 26 | read_verilog -sv "${lib_dir}/essential/xc7/async_reset.sv" 27 | read_verilog -sv "${lib_dir}/essential/debounce.sv" 28 | read_verilog -sv "${origin_dir}/${arch}/top_${design_name}.sv" 29 | read_verilog -sv "${origin_dir}/simple_720p.sv" 30 | read_verilog -sv "${origin_dir}/simple_score.sv" 31 | 32 | # read constraints 33 | read_xdc "${origin_dir}/${arch}/${board_name}.xdc" 34 | 35 | # synth 36 | synth_design -top "top_${design_name}" -part ${fpga_part} 37 | 38 | # place and route 39 | opt_design 40 | place_design 41 | route_design 42 | 43 | # write bitstream 44 | write_bitstream -force "${origin_dir}/${arch}/${design_name}.bit" 45 | -------------------------------------------------------------------------------- /graphics/pong/xc7/vivado/build.tcl: -------------------------------------------------------------------------------- 1 | # Project F: FPGA Pong - Vivado Build Script (XC7 VGA) 2 | # (C)2023 Will Green, open source hardware released under the MIT License 3 | # Learn more at https://projectf.io/posts/fpga-pong/ 4 | 5 | # Using this script: 6 | # 1. Add Vivado env to shell: . /opt/Xilinx/Vivado/2022.2/settings64.sh 7 | # 2. Run build script: vivado -mode batch -nolog -nojournal -source build.tcl 8 | # 3. Program board: openFPGALoader -b arty ../pong.bit 9 | 10 | # build settings 11 | set design_name "pong" 12 | set arch "xc7" 13 | set board_name "arty" 14 | set fpga_part "xc7a35ticsg324-1L" 15 | 16 | # set reference directories for source files 17 | set lib_dir [file normalize "./../../../../lib"] 18 | set origin_dir [file normalize "./../../"] 19 | 20 | # read design sources 21 | read_verilog -sv "${lib_dir}/clock/xc7/clock_480p.sv" 22 | read_verilog -sv "${lib_dir}/essential/debounce.sv" 23 | read_verilog -sv "${origin_dir}/${arch}/top_${design_name}.sv" 24 | read_verilog -sv "${origin_dir}/simple_480p.sv" 25 | read_verilog -sv "${origin_dir}/simple_score.sv" 26 | 27 | # read constraints 28 | read_xdc "${origin_dir}/${arch}/${board_name}.xdc" 29 | 30 | # synth 31 | synth_design -top "top_${design_name}" -part ${fpga_part} 32 | 33 | # place and route 34 | opt_design 35 | place_design 36 | route_design 37 | 38 | # write bitstream 39 | write_bitstream -force "${origin_dir}/${arch}/${design_name}.bit" 40 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/ecp5/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - ULX3S Makefile 2 | ## Copyright Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | ## FPGA IC (enable one) 6 | # FPGA_TYPE = 12k # LFE5U-12 7 | # FPGA_TYPE = 25k # LFE5U-25 8 | # FPGA_TYPE = 45k # LFE5U-45 9 | FPGA_TYPE = 85k # LFE5U-85 10 | 11 | ## configuration 12 | SHELL = /bin/sh 13 | FPGA_PKG = CABGA381 # IC package 14 | FPGA_SPEED = 8 # FPGA speed grade (6,7,8) - all parts seem fine with fastest speed 15 | LPF = ulx3s.lpf # pins and constraints 16 | TARGET_FREQ = 74 # target frequency (MHz) for 1280x720 17 | 18 | # included modules 19 | PATH_LIB = ../../../lib 20 | ADD_SRC += ${PATH_LIB}/clock/ecp5/clock2_gen.v 21 | ADD_SRC += ${PATH_LIB}/display/ecp5/dvi_generator.sv 22 | ADD_SRC += ${PATH_LIB}/display/tmds_encoder_dvi.sv 23 | ADD_SRC += ../simple_720p.sv 24 | 25 | rasterbars: rasterbars.bit rasterbars.svf 26 | hitomezashi: hitomezashi.bit hitomezashi.svf 27 | hello: hello.bit hello.svf 28 | colour_cycle: colour_cycle.bit colour_cycle.svf 29 | bounce: bounce.bit bounce.svf 30 | 31 | # synthesis 32 | %.json: top_%.sv $(ADD_SRC) 33 | yosys -ql $(basename $@)-yosys.log -p 'synth_ecp5 -top top_$(basename $@) -json $@' $< $(ADD_SRC) 34 | 35 | # place and route 36 | %.config: %.json 37 | nextpnr-ecp5 --${FPGA_TYPE} --package ${FPGA_PKG} --freq ${TARGET_FREQ} --speed ${FPGA_SPEED} --json $< --textcfg $@ --lpf ${LPF} 38 | 39 | # pack bitstream 40 | %.bit: %.config 41 | ecppack --compress $< $@ 42 | 43 | # pack SVF (Serial Vector Format) 44 | %.svf: %.config 45 | ecppack --compress --input $< --svf $@ 46 | 47 | all: rasterbars hitomezashi hello colour_cycle bounce 48 | 49 | clean: 50 | rm -f *.json *.config *.bit .*.d *.svf *yosys.log 51 | 52 | .PHONY: all clean 53 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/ecp5/ulx3s.lpf: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - ULX3S Board Constraints 2 | ## Copyright Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | BLOCK RESETPATHS; 6 | BLOCK ASYNCPATHS; 7 | 8 | ## Board Clock: 25 MHz 9 | LOCATE COMP "clk_25m" SITE "G2"; 10 | IOBUF PORT "clk_25m" PULLMODE=NONE IO_TYPE=LVCMOS33; 11 | FREQUENCY PORT "clk_25m" 25 MHZ; 12 | 13 | ## Buttons 14 | LOCATE COMP "btn_rst_n" SITE "D6"; # use B0 for reset 15 | IOBUF PORT "btn_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 16 | 17 | ## HDMI-compatible connector (AKA GPDI) 18 | # NB. IO_TYPE=LVCMOS33D generates gpdi_dn from gpdi_dp 19 | LOCATE COMP "gpdi_dp[0]" SITE "A16"; # channel 0 + 20 | LOCATE COMP "gpdi_dn[0]" SITE "B16"; # channel 0 - 21 | LOCATE COMP "gpdi_dp[1]" SITE "A14"; # channel 1 + 22 | LOCATE COMP "gpdi_dn[1]" SITE "C14"; # channel 1 - 23 | LOCATE COMP "gpdi_dp[2]" SITE "A12"; # channel 2 + 24 | LOCATE COMP "gpdi_dn[2]" SITE "A13"; # channel 2 - 25 | LOCATE COMP "gpdi_dp[3]" SITE "A17"; # clock + 26 | LOCATE COMP "gpdi_dn[3]" SITE "B18"; # clock - 27 | IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; 28 | IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; 29 | IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; 30 | IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; 31 | IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; 32 | IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; 33 | IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; 34 | IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; 35 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | # configuration 6 | SHELL = /bin/sh 7 | FPGA_PKG = sg48 8 | FPGA_TYPE = up5k 9 | PCF = icebreaker.pcf 10 | 11 | # included modules 12 | PATH_LIB = ../../../lib 13 | ADD_SRC += ${PATH_LIB}/clock/ice40/clock_480p.sv 14 | ADD_SRC += ../simple_480p.sv 15 | 16 | rasterbars: rasterbars.rpt rasterbars.bin 17 | hitomezashi: hitomezashi.rpt hitomezashi.bin 18 | hello: hello.rpt hello.bin 19 | colour_cycle: colour_cycle.rpt colour_cycle.bin 20 | bounce: bounce.rpt bounce.bin 21 | 22 | %.json: top_%.sv $(ADD_SRC) 23 | yosys -ql $(basename $@)-yosys.log -p 'synth_ice40 -abc9 -device u -top top_$(basename $@) -json $@' $< $(ADD_SRC) 24 | 25 | %.asc: %.json 26 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 27 | 28 | %.rpt: %.asc 29 | icetime -d ${FPGA_TYPE} -mtr $@ $< 30 | 31 | %.bin: %.asc 32 | icepack $< $(subst top_,,$@) 33 | 34 | all: rasterbars hitomezashi hello colour_cycle bounce 35 | 36 | clean: 37 | rm -f *.json *.asc *.rpt *.bin *yosys.log 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/sim/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - Verilator Sim Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | VFLAGS = -O3 --x-assign fast --x-initial fast --noassert 6 | SDL_CFLAGS = `sdl2-config --cflags` 7 | SDL_LDFLAGS = `sdl2-config --libs` 8 | 9 | rasterbars: rasterbars.exe 10 | hitomezashi: hitomezashi.exe 11 | hello: hello.exe 12 | colour_cycle: colour_cycle.exe 13 | bounce: bounce.exe 14 | 15 | %.exe: %.mk 16 | make -C ./obj_dir -f Vtop_$< 17 | 18 | %.mk: top_%.sv 19 | verilator ${VFLAGS} -I.. ${PROJF_LIBS} \ 20 | -cc $< --exe main_$(basename $@).cpp -o $(basename $@) \ 21 | -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" 22 | 23 | all: rasterbars hitomezashi hello colour_cycle bounce 24 | 25 | clean: 26 | rm -rf ./obj_dir 27 | 28 | .PHONY: all clean 29 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/xc7-dvi/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 15 | 16 | ## HDMI Source 17 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 18 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 19 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 20 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 21 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 22 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 23 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 24 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 25 | -------------------------------------------------------------------------------- /graphics/racing-the-beam/xc7-dvi/racing-the-beam-bitstreams.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/projf/projf-explore/8c101525e62f751e3b50c60e3c0127fa401ec69c/graphics/racing-the-beam/xc7-dvi/racing-the-beam-bitstreams.zip -------------------------------------------------------------------------------- /graphics/racing-the-beam/xc7/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Racing the Beam - Arty A7-35T Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io/posts/racing-the-beam/ 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst_n}]; 15 | 16 | ## VGA Pmod on Header JB/JC 17 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {vga_hsync}]; 18 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {vga_vsync}]; 19 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {vga_r[0]}]; 20 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {vga_r[1]}]; 21 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {vga_r[2]}]; 22 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {vga_r[3]}]; 23 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {vga_g[0]}]; 24 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {vga_g[1]}]; 25 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {vga_g[2]}]; 26 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {vga_g[3]}]; 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {vga_b[0]}]; 28 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {vga_b[1]}]; 29 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {vga_b[2]}]; 30 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {vga_b[3]}]; 31 | -------------------------------------------------------------------------------- /hello/README.md: -------------------------------------------------------------------------------- 1 | # Hello FPGA from Project F 2 | 3 | Project F brings FPGAs to life with exciting [open-source](LICENSE) designs you can build on. 4 | Learn more at [projectf.io](https://projectf.io/) and follow [@WillFlux](https://mastodon.social/@WillFlux) for updates. 5 | 6 | Hello is a three-part introduction to FPGA development with Verilog; currently available for two boards: the Arty A7 and Nexys Video. 7 | 8 | * **Hello Arty**: [Designs](hello-arty) - [Blog 1](https://projectf.io/posts/hello-arty-1/) - [Blog 2](https://projectf.io/posts/hello-arty-2/) - [Blog 3](https://projectf.io/posts/hello-arty-3/) 9 | * **Hello Nexys**: [Designs](hello-nexys) - [Blog 1](https://projectf.io/posts/hello-nexys-1/) - [Blog 2](https://projectf.io/posts/hello-nexys-2/) 10 | 11 | For other designs from Project F, see the main [README](../README.md) or visit [projectf.io](https://projectf.io/). 12 | -------------------------------------------------------------------------------- /hello/hello-arty/A/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty A - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | # I/O Pins 10 | set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {sw}]; 11 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led}]; 12 | -------------------------------------------------------------------------------- /hello/hello-arty/A/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty A - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic sw, 10 | output logic led 11 | ); 12 | 13 | always_comb begin 14 | led = sw; 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /hello/hello-arty/B/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty B - Vivado Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Slide Switches 10 | set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]; 11 | set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/B/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty B - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic [1:0] sw, 10 | output logic [3:0] led 11 | ); 12 | 13 | always_comb begin 14 | if (sw[0]) begin 15 | led[1:0] = 2'b11; 16 | end else begin 17 | led[1:0] = 2'b00; 18 | end 19 | 20 | if (sw[1]) begin 21 | led[3:2] = 2'b11; 22 | end else begin 23 | led[3:2] = 2'b00; 24 | end 25 | end 26 | endmodule -------------------------------------------------------------------------------- /hello/hello-arty/C/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty C - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Slide Switches 10 | set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]; 11 | set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/C/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty C - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic [1:0] sw, 10 | output logic [3:0] led 11 | ); 12 | 13 | always_comb begin 14 | led[1:0] = sw[0] ? 2'b11 : 2'b00; 15 | led[3:2] = sw[1] ? 2'b11 : 2'b00; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /hello/hello-arty/D/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty D - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Slide Switches 10 | set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]; 11 | set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]; 12 | set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {sw[2]}]; 13 | set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports {sw[3]}]; 14 | 15 | ## Buttons 16 | set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}]; 17 | set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports {btn[1]}]; 18 | set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS33} [get_ports {btn[2]}]; 19 | set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS33} [get_ports {btn[3]}]; 20 | 21 | ## LEDs 22 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 23 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 24 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 25 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 26 | -------------------------------------------------------------------------------- /hello/hello-arty/D/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty D - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic [3:0] sw, 10 | input wire logic [3:0] btn, 11 | output logic [3:0] led 12 | ); 13 | 14 | always_comb begin 15 | if (sw[0] == 0 && sw[1] == 1) begin 16 | led[3:0] = btn[0] ? 4'b1001 : 4'b0110; 17 | end else begin 18 | led[3:0] = 4'b0000; 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /hello/hello-arty/E/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty E - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/E/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty E - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | logic [31:0] cnt = 0; // 32-bit counter 14 | 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | led[0] <= cnt[26]; 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /hello/hello-arty/F/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty F - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/F/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty F - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | logic [31:0] cnt = 0; // 32-bit counter 14 | 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | led[0] <= cnt[26]; 18 | led[1] <= cnt[24]; 19 | led[2] <= cnt[22]; 20 | led[3] <= cnt[20]; 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /hello/hello-arty/G/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty G - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/G/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty G - Top 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | localparam DIV_BY = 27'd100_000_000; 14 | 15 | logic stb; 16 | logic [26:0] cnt = 0; 17 | always_ff @(posedge clk) begin 18 | if (cnt != DIV_BY-1) begin 19 | stb <= 0; 20 | cnt <= cnt + 1; 21 | end else begin 22 | stb <= 1; 23 | cnt <= 0; 24 | end 25 | end 26 | 27 | always_ff @(posedge clk) begin 28 | if (stb) led <= led + 1; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /hello/hello-arty/H/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty H - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/H/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty H - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | logic [7:0] cnt = 0; 14 | logic [7:0] duty = 8'd5; 15 | 16 | always_ff @(posedge clk) begin 17 | cnt <= cnt + 1; 18 | led[3:0] <= (cnt < duty) ? 4'b1111 : 4'b0000; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /hello/hello-arty/I/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty I - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/I/pwm.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty I - Pulse Width Modulation 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module pwm ( 9 | input wire logic clk, 10 | input wire logic [7:0] duty, 11 | output logic pwm_out 12 | ); 13 | 14 | logic [7:0] cnt = 8'b0; 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | end 18 | 19 | always_comb begin 20 | pwm_out = (cnt < duty); 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /hello/hello-arty/I/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty I - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | pwm pwm_led_0 (.clk, .duty(4), .pwm_out(led[0])); 14 | pwm pwm_led_1 (.clk, .duty(16), .pwm_out(led[1])); 15 | pwm pwm_led_2 (.clk, .duty(64), .pwm_out(led[2])); 16 | pwm pwm_led_3 (.clk, .duty(255), .pwm_out(led[3])); 17 | endmodule 18 | -------------------------------------------------------------------------------- /hello/hello-arty/J/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty J - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## RGB LEDs 14 | set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {led_r[0]}]; 15 | set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_g[0]}]; 16 | set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {led_b[0]}]; 17 | set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_r[1]}]; 18 | set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_g[1]}]; 19 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_b[1]}]; 20 | set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_r[2]}]; 21 | set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_g[2]}]; 22 | set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_b[2]}]; 23 | set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_r[3]}]; 24 | set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_g[3]}]; 25 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_b[3]}]; 26 | -------------------------------------------------------------------------------- /hello/hello-arty/J/pwm.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty J - Pulse Width Modulation 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module pwm ( 9 | input wire logic clk, 10 | input wire logic [7:0] duty, 11 | output logic pwm_out 12 | ); 13 | 14 | logic [7:0] cnt = 8'b0; 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | end 18 | 19 | always_comb begin 20 | pwm_out = (cnt < duty); 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /hello/hello-arty/J/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty J - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led_r, 11 | output logic [3:0] led_g, 12 | output logic [3:0] led_b 13 | ); 14 | 15 | pwm pwm_led_r0 (.clk, .duty(0), .pwm_out(led_r[0])); 16 | pwm pwm_led_g0 (.clk, .duty(64), .pwm_out(led_g[0])); 17 | pwm pwm_led_b0 (.clk, .duty(64), .pwm_out(led_b[0])); 18 | endmodule 19 | -------------------------------------------------------------------------------- /hello/hello-arty/K/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty K - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS33} [get_ports {btn_ctrl}]; 15 | set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports {btn_0}]; 16 | set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports {btn_1}]; 17 | 18 | ## LEDs 19 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}]; 20 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}]; 21 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}]; 22 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}]; 23 | -------------------------------------------------------------------------------- /hello/hello-arty/K/debounce.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty K - Debounce 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module debounce ( 9 | input wire logic clk, // clock 10 | input wire logic in, // signal input 11 | output logic out, // signal output (debounced) 12 | output logic onup // on up (one tick) 13 | ); 14 | 15 | // sync with clock and combat metastability 16 | logic sync_0, sync_1; 17 | always_ff @(posedge clk) sync_0 <= in; 18 | always_ff @(posedge clk) sync_1 <= sync_0; 19 | 20 | logic [19:0] cnt; // 2^20 = 10 ms counter at 100 MHz 21 | logic idle, max; 22 | always_comb begin 23 | idle = (out == sync_1); 24 | max = &cnt; 25 | onup = ~idle & max & out; 26 | end 27 | 28 | always_ff @(posedge clk) begin 29 | if (idle) begin 30 | cnt <= 0; 31 | end else begin 32 | cnt <= cnt + 1; 33 | if (max) out <= ~out; 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /hello/hello-arty/L/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Arty L - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## RGB LEDs 14 | set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {led_main_r}]; 15 | set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_main_g}]; 16 | set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_side_r}]; 17 | set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_side_g}]; 18 | -------------------------------------------------------------------------------- /hello/hello-arty/L/pwm.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Arty L - Pulse Width Modulation 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module pwm ( 9 | input wire logic clk, 10 | input wire logic [7:0] duty, 11 | output logic pwm_out 12 | ); 13 | 14 | logic [7:0] cnt = 8'b0; 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | end 18 | 19 | always_comb begin 20 | pwm_out = (cnt < duty); 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /hello/hello-arty/README.md: -------------------------------------------------------------------------------- 1 | # Hello Arty from Project F 2 | 3 | Hello Arty is a three-part introduction to FPGA development with Verilog and the Digilent Arty A7 board. 4 | This series is also available for the [Nexys Video](../hello-nexys). 5 | 6 | * [Hello Arty - Part 1](https://projectf.io/posts/hello-arty-1/) 7 | * [A source](A/) 8 | * [B source](B/) 9 | * [C source](C/) 10 | * [D source](D/) 11 | * [Hello Arty - Part 2](https://projectf.io/posts/hello-arty-2/) 12 | * [E source](E/) 13 | * [F source](F/) 14 | * [G source](G/) 15 | * [H source](H/) 16 | * [I source](I/) 17 | * [J source](J/) 18 | * [Hello Arty - Part 3](https://projectf.io/posts/hello-arty-3/) 19 | * [K source](K/) 20 | * [L source](L/) 21 | 22 | For other designs from Project F, see the main [README](../../README.md) or visit [projectf.io](https://projectf.io/). 23 | -------------------------------------------------------------------------------- /hello/hello-nexys/A/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys A - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | # I/O Pins 10 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {sw}]; 11 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led}]; 12 | -------------------------------------------------------------------------------- /hello/hello-nexys/A/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys A - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic sw, 10 | output logic led 11 | ); 12 | 13 | always_comb begin 14 | led = sw; 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /hello/hello-nexys/B/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys B - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Slide Switches 10 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]; 11 | set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/B/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys B - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic [1:0] sw, 10 | output logic [3:0] led 11 | ); 12 | 13 | always_comb begin 14 | if (sw[0]) begin 15 | led[1:0] = 2'b11; 16 | end else begin 17 | led[1:0] = 2'b00; 18 | end 19 | 20 | if (sw[1]) begin 21 | led[3:2] = 2'b11; 22 | end else begin 23 | led[3:2] = 2'b00; 24 | end 25 | end 26 | endmodule 27 | -------------------------------------------------------------------------------- /hello/hello-nexys/C/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys C - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Slide Switches 10 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]; 11 | set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/C/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys C - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic [3:0] sw, 10 | input wire logic btnc, btnd, btnl, btnr, btnu, 11 | output logic [3:0] led 12 | ); 13 | 14 | always_comb begin 15 | if (sw[0] == 0 && sw[1] == 1) begin 16 | led[3:0] = btn[0] ? 4'b1001 : 4'b0110; 17 | end else begin 18 | led[3:0] = 4'b0000; 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /hello/hello-nexys/D/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys D - Board Constraints 2 | ## (C)2020 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Slide Switches 10 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]; 11 | set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]; 12 | set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]; 13 | set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]; 14 | 15 | ## Buttons 16 | set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS12} [get_ports {btnc}]; 17 | set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS12} [get_ports {btnd}]; 18 | set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS12} [get_ports {btnl}]; 19 | set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS12} [get_ports {btnr}]; 20 | set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS12} [get_ports {btnu}]; 21 | 22 | ## LEDs 23 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 24 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 25 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 26 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 27 | -------------------------------------------------------------------------------- /hello/hello-nexys/D/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys D - Top 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic [3:0] sw, 10 | input wire logic btnc, btnd, btnl, btnr, btnu, 11 | output logic [3:0] led 12 | ); 13 | 14 | always_comb begin 15 | if (sw[0] == 0 && sw[1] == 1) begin 16 | led[3:0] = btnc ? 4'b1001 : 4'b0110; 17 | end else begin 18 | led[3:0] = 4'b0000; 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /hello/hello-nexys/E/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys E - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/E/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys E - Top 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | logic [31:0] cnt = 0; // 32-bit counter 14 | 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | led[0] <= cnt[26]; 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /hello/hello-nexys/F/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys F - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/F/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys F - Top 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | logic [31:0] cnt = 0; // 32-bit counter 14 | 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | led[0] <= cnt[26]; 18 | led[1] <= cnt[24]; 19 | led[2] <= cnt[22]; 20 | led[3] <= cnt[20]; 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /hello/hello-nexys/G/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys G - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/G/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys G - Top 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | localparam DIV_BY = 27'd100_000_000; // 100 million 14 | 15 | logic stb; 16 | logic [26:0] cnt = 0; 17 | always_ff @(posedge clk) begin 18 | if (cnt != DIV_BY-1) begin 19 | stb <= 0; 20 | cnt <= cnt + 1; 21 | end else begin 22 | stb <= 1; 23 | cnt <= 0; 24 | end 25 | end 26 | 27 | always_ff @(posedge clk) begin 28 | if (stb) led <= led + 1; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /hello/hello-nexys/H/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys H - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/H/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys H - Top 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | logic [7:0] cnt = 0; 14 | logic [7:0] duty = 8'd5; 15 | 16 | always_ff @(posedge clk) begin 17 | cnt <= cnt + 1; 18 | led[3:0] <= (cnt < duty) ? 4'b1111 : 4'b0000; 19 | end 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /hello/hello-nexys/I/nexys.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Hello Nexys I - Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk}]; 12 | 13 | ## LEDs 14 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {led[0]}]; 15 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {led[1]}]; 16 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {led[2]}]; 17 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports {led[3]}]; 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/I/pwm.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys I - Pulse Width Modulation 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module pwm ( 9 | input wire logic clk, 10 | input wire logic [7:0] duty, 11 | output logic pwm_out 12 | ); 13 | 14 | logic [7:0] cnt = 8'b0; 15 | always_ff @(posedge clk) begin 16 | cnt <= cnt + 1; 17 | end 18 | 19 | always_comb begin 20 | pwm_out = (cnt < duty); 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /hello/hello-nexys/I/top.sv: -------------------------------------------------------------------------------- 1 | // Project F: Hello Nexys I - Top 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module top ( 9 | input wire logic clk, 10 | output logic [3:0] led 11 | ); 12 | 13 | pwm pwm_led_0 (.clk, .duty(4), .pwm_out(led[0])); 14 | pwm pwm_led_1 (.clk, .duty(16), .pwm_out(led[1])); 15 | pwm pwm_led_2 (.clk, .duty(64), .pwm_out(led[2])); 16 | pwm pwm_led_3 (.clk, .duty(255), .pwm_out(led[3])); 17 | endmodule 18 | -------------------------------------------------------------------------------- /hello/hello-nexys/README.md: -------------------------------------------------------------------------------- 1 | # Hello Nexys from Project F 2 | 3 | Hello Nexys is a three-part introduction to FPGA development with Verilog and the Digilent Nexys Video board. 4 | This series is also available for the [Arty A7](../hello-arty). 5 | 6 | * [Hello Nexys - Part 1](https://projectf.io/posts/hello-nexys-1/) 7 | * [A source](A/) 8 | * [B source](B/) 9 | * [C source](C/) 10 | * [D source](D/) 11 | * [Hello Nexys - Part 2](https://projectf.io/posts/hello-nexys-2/) 12 | * [E source](E/) 13 | * [F source](F/) 14 | * [G source](G/) 15 | * [H source](H/) 16 | * [I source](I/) 17 | * Hello Nexys - Part 3 (not currently available) 18 | 19 | For other designs from Project F, see the main [README](../../README.md) or visit [projectf.io](https://projectf.io/). 20 | -------------------------------------------------------------------------------- /lib/clock/ice40/clock_480p.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - 640x480p60 Clock Generation (iCE40) 2 | // Copyright Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | // Generate 25.125 MHz (640x480 59.8 Hz) with 12 MHz input clock 9 | // iCE40 PLLs are documented in Lattice TN1251 and ICE Technology Library 10 | 11 | module clock_480p ( 12 | input wire logic clk_12m, // input clock (12 MHz) 13 | input wire logic rst, // reset 14 | output logic clk_pix, // pixel clock 15 | output logic clk_pix_locked // pixel clock locked? 16 | ); 17 | 18 | localparam FEEDBACK_PATH="SIMPLE"; 19 | localparam DIVR=4'b0000; 20 | localparam DIVF=7'b1000010; 21 | localparam DIVQ=3'b101; 22 | localparam FILTER_RANGE=3'b001; 23 | 24 | logic locked; 25 | SB_PLL40_PAD #( 26 | .FEEDBACK_PATH(FEEDBACK_PATH), 27 | .DIVR(DIVR), 28 | .DIVF(DIVF), 29 | .DIVQ(DIVQ), 30 | .FILTER_RANGE(FILTER_RANGE) 31 | ) SB_PLL40_PAD_inst ( 32 | .PACKAGEPIN(clk_12m), 33 | .PLLOUTGLOBAL(clk_pix), // use global clock network 34 | .RESETB(rst), 35 | .BYPASS(1'b0), 36 | .LOCK(locked) 37 | ); 38 | 39 | // ensure clock lock is synced with pixel clock 40 | logic locked_sync_0; 41 | always_ff @(posedge clk_pix) begin 42 | locked_sync_0 <= locked; 43 | clk_pix_locked <= locked_sync_0; 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /lib/clock/xc7/clock_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Clock Generation Test Bench (XC7) 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module clock_tb (); 9 | 10 | parameter CLK_PERIOD = 10; 11 | 12 | logic rst, clk_100m; 13 | 14 | // 640x480p60 clocks 15 | logic clk_480p, clk_480p_5x; 16 | logic clk_locked_480p; 17 | 18 | clock_480p clock_480p_inst ( 19 | .clk_100m, 20 | .rst, 21 | .clk_pix(clk_480p), 22 | .clk_pix_5x(clk_480p_5x), 23 | .clk_pix_locked(clk_locked_480p) 24 | ); 25 | 26 | // 1280x720p60 clocks 27 | logic clk_720p, clk_720p_5x; 28 | logic clk_locked_720p; 29 | 30 | clock_720p clock_720p_inst ( 31 | .clk_100m, 32 | .rst, 33 | .clk_pix(clk_720p), 34 | .clk_pix_5x(clk_720p_5x), 35 | .clk_pix_locked(clk_locked_720p) 36 | ); 37 | 38 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 39 | 40 | initial begin 41 | clk_100m = 1; 42 | rst = 1; 43 | #100 44 | rst = 0; 45 | 46 | #12000 47 | $finish; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /lib/clock/xd.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Clock Domain Crossing (CDC) for Flag 2 | // (C)2022 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module xd ( 9 | input wire logic clk_src, // source domain clock 10 | input wire logic clk_dst, // destination domain clock 11 | input wire logic flag_src, // flag in source domain 12 | output logic flag_dst // flag in destination domain 13 | ); 14 | 15 | // toggle reg when pulse received in source domain 16 | logic toggle_src = 1'b0; 17 | always_ff @(posedge clk_src) toggle_src <= toggle_src ^ flag_src; 18 | 19 | // cross to destination domain via shift reg 20 | logic [3:0] shr_dst = 4'b0; 21 | always_ff @(posedge clk_dst) shr_dst <= {shr_dst[2:0], toggle_src}; 22 | 23 | // output pulse when transition occurs 24 | always_comb flag_dst = shr_dst[3] ^ shr_dst[2]; 25 | endmodule 26 | -------------------------------------------------------------------------------- /lib/display/bitmap_addr.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Bitmap Address 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | // three-cycle address calculation 9 | // NB. doesn't handle coordinate wrapping using offsets 10 | 11 | module bitmap_addr #( 12 | parameter CORDW=16, // signed coordinate width (bits) 13 | parameter ADDRW=24 // address width (bits) 14 | ) ( 15 | input wire logic clk, // clock 16 | input wire logic signed [CORDW-1:0] bmpw, // bitmap width 17 | input wire logic signed [CORDW-1:0] bmph, // bitmap height 18 | input wire logic signed [CORDW-1:0] x, // horizontal pixel coordinate 19 | input wire logic signed [CORDW-1:0] y, // vertical pixel coordinate 20 | input wire logic signed [CORDW-1:0] offx, // horizontal offset 21 | input wire logic signed [CORDW-1:0] offy, // vertical offset 22 | output logic [ADDRW-1:0] addr, // pixel memory address 23 | output logic clip // pixel coordinate outside bitmap 24 | ); 25 | 26 | logic signed [CORDW-1:0] addr_y1, addr_x1, addr_x2; 27 | logic [ADDRW-1:0] addr_mul; 28 | logic clip_t1; // clip check temporary 29 | 30 | always_ff @(posedge clk) begin 31 | // step 1 32 | addr_y1 <= y + offy; 33 | addr_x1 <= x + offx; 34 | 35 | // step 2 36 | /* verilator lint_off WIDTH */ 37 | addr_mul <= bmpw * addr_y1; 38 | /* verilator lint_on WIDTH */ 39 | addr_x2 <= addr_x1; 40 | clip_t1 <= (addr_x1 < 0 || addr_x1 > bmpw-1 || addr_y1 < 0 || addr_y1 > bmph-1); 41 | 42 | // step 3 43 | clip <= clip_t1; 44 | /* verilator lint_off WIDTH */ 45 | addr <= addr_mul + addr_x2; 46 | /* verilator lint_on WIDTH */ 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /lib/display/clut_simple.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Simple Colour Lookup Table 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module clut_simple #( 9 | parameter COLRW=12, // colour output width (bits) 10 | parameter CIDXW=4, // colour index width (bits) 11 | parameter F_PAL="" // init file for colour palette 12 | ) ( 13 | input wire logic clk_write, // write clock 14 | input wire logic clk_read, // read clock 15 | input wire logic we, // write enable 16 | input wire logic [CIDXW-1:0] cidx_write, // colour index to write 17 | input wire logic [CIDXW-1:0] cidx_read, // colour index to read 18 | input wire logic [COLRW-1:0] colr_in, // write colour 19 | output logic [COLRW-1:0] colr_out // read colour 20 | ); 21 | 22 | bram_sdp #( 23 | .WIDTH(COLRW), 24 | .DEPTH(2**CIDXW), 25 | .INIT_F(F_PAL) 26 | ) bram_clut ( 27 | .clk_write, 28 | .clk_read, 29 | .we, 30 | .addr_write(cidx_write), 31 | .addr_read(cidx_read), 32 | .data_in(colr_in), 33 | .data_out(colr_out) 34 | ); 35 | endmodule 36 | -------------------------------------------------------------------------------- /lib/display/xc7/bitmap_addr_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Bitmap Address Test Bench (XC7) 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module bitmap_addr_tb(); 9 | endmodule 10 | -------------------------------------------------------------------------------- /lib/display/xc7/display_480p_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - 640x480p60 Display Test Bench (XC7) 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module display_480p_tb(); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | localparam CORDW = 16; // screen coordinate width in bits 12 | 13 | logic rst; 14 | logic clk_100m; 15 | 16 | // generate pixel clocks 17 | logic clk_pix; // pixel clock 18 | logic clk_pix_locked; // pixel clock locked? 19 | clock_480p clock_pix_inst ( 20 | .clk_100m, 21 | .rst, 22 | .clk_pix, 23 | .clk_pix_5x(), 24 | .clk_pix_locked 25 | ); 26 | 27 | // reset in pixel clock domain 28 | logic rst_pix; 29 | always_comb rst_pix = !clk_pix_locked; // wait for clock lock 30 | 31 | // display sync signals and coordinates 32 | logic signed [CORDW-1:0] sx, sy; 33 | logic hsync, vsync; 34 | logic de, frame, line; 35 | display_480p #(.CORDW(CORDW)) display_inst ( 36 | .clk_pix, 37 | .rst_pix, 38 | .sx, 39 | .sy, 40 | .hsync, 41 | .vsync, 42 | .de, 43 | .frame, 44 | .line 45 | ); 46 | 47 | // generate clock 48 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 49 | 50 | initial begin 51 | rst = 1; 52 | clk_100m = 1; 53 | 54 | #100 rst = 0; 55 | #18_000_000 $finish; // 18 ms (one frame is ~16.7 ms) 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /lib/display/xc7/display_720p_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - 1280x720p60 Display Test Bench (XC7) 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module display_720p_tb(); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | localparam CORDW = 16; // screen coordinate width in bits 12 | 13 | logic rst; 14 | logic clk_100m; 15 | 16 | // generate pixel clocks 17 | logic clk_pix; // pixel clock 18 | logic clk_pix_locked; // pixel clock locked? 19 | clock_720p clock_pix_inst ( 20 | .clk_100m, 21 | .rst, 22 | .clk_pix, 23 | .clk_pix_5x(), 24 | .clk_pix_locked 25 | ); 26 | 27 | // reset in pixel clock domain 28 | logic rst_pix; 29 | always_comb rst_pix = !clk_pix_locked; // wait for clock lock 30 | 31 | // display sync signals and coordinates 32 | logic signed [CORDW-1:0] sx, sy; 33 | logic hsync, vsync; 34 | logic de, frame, line; 35 | display_720p #(.CORDW(CORDW)) display_inst ( 36 | .clk_pix, 37 | .rst_pix, 38 | .sx, 39 | .sy, 40 | .hsync, 41 | .vsync, 42 | .de, 43 | .frame, 44 | .line 45 | ); 46 | 47 | // generate clock 48 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 49 | 50 | initial begin 51 | rst = 1; 52 | clk_100m = 1; 53 | 54 | #100 rst = 0; 55 | #18_000_000 $finish; // 18 ms (one frame is ~16.7 ms) 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /lib/display/xc7/tmds_out.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - XC7 TMDS Signal Output 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | // OBUFDS is documented in Xilinx UG471 9 | 10 | module tmds_out ( 11 | input wire logic tmds, // TMDS signal 12 | output logic pin_p, // positive differential signal pin 13 | output logic pin_n // negative differential signal pin 14 | ); 15 | 16 | OBUFDS #(.IOSTANDARD("TMDS_33")) 17 | tmds_obufds (.I(tmds), .O(pin_p), .OB(pin_n)); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /lib/essential/README.md: -------------------------------------------------------------------------------- 1 | # Essential - Verilog Library 2 | 3 | Essential Verilog designs from [Project F](https://projectf.io) that don't fit in another category. You can freely build on these [MIT licensed](../../LICENSE) designs. Get an overview of the whole lib from the [Verilog Library blog](https://projectf.io/verilog-lib/). 4 | 5 | ## Verilog Modules 6 | 7 | * [debounce.sv](debounce.sv) - button debouncing 8 | * [xc7/async_reset.sv](xc7/async_reset.sv) - asynchronous reset for Xilinx 7 Series 9 | 10 | Locate Vivado test benches in the [xc7](xc7) directory. 11 | Find other modules in the [Library](../). 12 | 13 | ## Blog Posts 14 | 15 | Button debouncing is used in [Hello Arty Part 3](https://projectf.io/posts/hello-arty-3/) and [Pong](https://projectf.io/posts/fpga-pong/). 16 | 17 | ## SystemVerilog? 18 | 19 | These modules use a little SystemVerilog to make Verilog more pleasant, see the main [Library README](../README.md#systemverilog) for details. 20 | -------------------------------------------------------------------------------- /lib/essential/debounce.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Button Debounce 2 | // (C)2020 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module debounce ( 9 | input wire logic clk, // clock 10 | input wire logic in, // signal input 11 | output logic out, // signal output (debounced) 12 | output logic ondn, // on down (one tick) 13 | output logic onup // on up (one tick) 14 | ); 15 | 16 | // sync with clock and combat metastability 17 | logic sync_0, sync_1; 18 | always_ff @(posedge clk) sync_0 <= in; 19 | always_ff @(posedge clk) sync_1 <= sync_0; 20 | 21 | logic [17:0] cnt; // 2^18 = 2.6 ms counter at 100 MHz 22 | logic idle, max; 23 | always_comb begin 24 | idle = (out == sync_1); 25 | max = &cnt; 26 | ondn = ~idle & max & ~out; 27 | onup = ~idle & max & out; 28 | end 29 | 30 | always_ff @(posedge clk) begin 31 | if (idle) begin 32 | cnt <= 0; 33 | end else begin 34 | cnt <= cnt + 1; 35 | if (max) out <= ~out; 36 | end 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /lib/essential/xc7/async_reset.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Async Reset 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module async_reset ( 9 | input wire logic clk, // clock 10 | input wire logic rst_in, // reset 11 | output logic rst_out // output reset 12 | ); 13 | 14 | (* ASYNC_REG = "TRUE" *) logic [1:0] rst_shf; // reset shift reg 15 | 16 | initial rst_out = 1'b1; // start off with reset asserted 17 | initial rst_shf = 2'b11; // and reset shift reg populated 18 | 19 | always_ff @(posedge clk or posedge rst_in) begin 20 | /* verilator lint_off SYNCASYNCNET */ 21 | if (rst_in) {rst_out, rst_shf} <= 3'b111; 22 | else {rst_out, rst_shf} <= {rst_shf, 1'b0}; 23 | /* verilator lint_on SYNCASYNCNET */ 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /lib/graphics/get_glyph_line.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Get Glyph Line 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module get_glyph_line #( 9 | parameter WIDTH=8, // glyph width in pixels 10 | parameter HEIGHT=16, // glyph height in pixels 11 | parameter COUNT=256, // number of characters in font 12 | parameter OFFSET=0, // glyph ROM offset 13 | parameter FONT_FILE="", // file to load glyphs from 14 | parameter LSB=0 // first font pixel in LSB 15 | ) ( 16 | input wire logic clk, // clock 17 | input wire logic rst, // reset 18 | input wire logic [7:0] ucp, // Unicode code point (0-255 only) 19 | input wire logic [$clog2(HEIGHT)-1:0] line_id, // glyph line to get 20 | output logic [WIDTH-1:0] glyph_line // glyph pixel line 21 | ); 22 | 23 | // font glyph ROM - line of glyph pixels at each location 24 | localparam DEPTH = HEIGHT * COUNT; 25 | logic [$clog2(DEPTH)-1:0] rom_addr; 26 | logic [WIDTH-1:0] rom_data; 27 | rom_sync #( 28 | .WIDTH(WIDTH), 29 | .DEPTH(DEPTH), 30 | .INIT_F(FONT_FILE) 31 | ) glyph_rom ( 32 | .clk, 33 | .addr(rom_addr), 34 | .data(rom_data) 35 | ); 36 | 37 | integer i; // for bit reversal 38 | 39 | always_ff @(posedge clk) begin 40 | /* verilator lint_off WIDTH */ 41 | rom_addr <= (ucp - OFFSET) * HEIGHT + line_id; 42 | /* verilator lint_on WIDTH */ 43 | if (LSB) begin 44 | glyph_line <= rom_data; 45 | end else begin // reverse if MSB is left-most pixel 46 | for (i=0; i%b Done=%b", $time, x, y, drawing, done); 40 | end 41 | 42 | initial begin 43 | rst = 1; 44 | clk = 1; 45 | #100 rst = 0; 46 | oe = 1; 47 | 48 | #10 $display("case 1: (10,8) -> (20,15)"); 49 | x0 = 8'd10; 50 | y0 = 8'd08; 51 | x1 = 8'd20; 52 | y1 = 8'd15; 53 | start = 1; 54 | #10 start = 0; 55 | 56 | #1500 $display("case 2: (20,15) -> (10,8)"); 57 | x0 = 8'd10; 58 | y0 = 8'd08; 59 | x1 = 8'd20; 60 | y1 = 8'd15; 61 | start = 1; 62 | #10 start = 0; 63 | 64 | #1500 $finish; 65 | end 66 | endmodule 67 | -------------------------------------------------------------------------------- /lib/graphics/xc7/draw_rectangle_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F: 2D Shapes - Draw Rectangle Test Bench 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module draw_rectangle_tb (); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | 12 | logic rst; 13 | logic clk; 14 | 15 | localparam CORDW = 8; 16 | logic [CORDW-1:0] x, y; 17 | logic [CORDW-1:0] x0, y0, x1, y1; 18 | logic start, oe, drawing, busy, done; 19 | draw_rectangle #(.CORDW(CORDW)) draw_rectangle_inst ( 20 | .clk, 21 | .rst, 22 | .start, 23 | .oe, 24 | .x0, 25 | .y0, 26 | .x1, 27 | .y1, 28 | .x, 29 | .y, 30 | .drawing, 31 | .busy, 32 | .done 33 | ); 34 | 35 | // generate clock 36 | always #(CLK_PERIOD / 2) clk = ~clk; 37 | 38 | initial begin 39 | $monitor("\t%d:\t(%d, %d) >%b Done=%b", $time, x, y, drawing, done); 40 | end 41 | 42 | initial begin 43 | rst = 1; 44 | clk = 1; 45 | #100 rst = 0; 46 | oe = 1; 47 | 48 | #10 $display("case 1: (10,10) (60,40)"); 49 | x0 = 8'd10; 50 | y0 = 8'd10; 51 | x1 = 8'd60; 52 | y1 = 8'd40; 53 | start = 1; 54 | #10 start = 0; 55 | 56 | #2000 $finish; 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /lib/maths/lfsr.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Galois Linear-Feedback Shift Register 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | // NB. Ensure reset is asserted for one or more cycles before enable 9 | 10 | module lfsr #( 11 | parameter LEN=8, // shift register length 12 | parameter TAPS=8'b10111000 // XOR taps 13 | ) ( 14 | input wire logic clk, // clock 15 | input wire logic rst, // reset 16 | input wire logic en, // enable 17 | input wire logic [LEN-1:0] seed, // seed (uses default seed if zero) 18 | output logic [LEN-1:0] sreg // lfsr output 19 | ); 20 | 21 | always_ff @(posedge clk) begin 22 | if (en) sreg <= {1'b0, sreg[LEN-1:1]} ^ (sreg[0] ? TAPS : {LEN{1'b0}}); 23 | if (rst) sreg <= (seed != 0) ? seed : {LEN{1'b1}}; 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /lib/maths/test/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F Library - Maths Test Bench Makefile 2 | ## (C)2023 Will Green, open source software released under the MIT License 3 | ## Learn more at https://projectf.io/verilog-lib/ 4 | 5 | div: 6 | make -f div.mk 7 | 8 | divu: 9 | make -f divu.mk 10 | 11 | divu_int: 12 | make -f divu_int.mk 13 | 14 | mul: 15 | make -f mul.mk 16 | 17 | all: div divu divu_int mul 18 | 19 | clean: 20 | make -f div.mk clean 21 | make -f divu.mk clean 22 | make -f divu_int.mk clean 23 | make -f mul.mk clean 24 | rm -f results*.xml 25 | rm -rf __pycache__ 26 | rm -rf sim_build 27 | 28 | .PHONY: all clean 29 | -------------------------------------------------------------------------------- /lib/maths/test/div.gtkw: -------------------------------------------------------------------------------- 1 | [*] div gtkwave config 2 | [dumpfile] "div.vcd" 3 | [savefile] "div.gtkw" 4 | [timestart] 0 5 | [size] 1599 871 6 | [pos] -1 -1 7 | *-16.835270 112004 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 | [sst_width] 193 9 | [signals_width] 184 10 | [sst_expanded] 1 11 | [sst_vpaned_height] 260 12 | @28 13 | div.clk 14 | div.rst 15 | div.start 16 | div.busy 17 | div.done 18 | div.valid 19 | div.dbz 20 | div.ovf 21 | @40000420 22 | [fpshift_count] 4 23 | div.a[8:0] 24 | [fpshift_count] 4 25 | div.b[8:0] 26 | @40000421 27 | [fpshift_count] 4 28 | div.val[8:0] 29 | [pattern_trace] 1 30 | [pattern_trace] 0 31 | -------------------------------------------------------------------------------- /lib/maths/test/div.mk: -------------------------------------------------------------------------------- 1 | ## Project F Library - div cocotb Test Bench Makefile 2 | ## (C)2023 Will Green, open source software released under the MIT License 3 | ## Learn more at https://projectf.io/verilog-lib/ 4 | 5 | SIM ?= icarus 6 | TOPLEVEL_LANG ?= verilog 7 | 8 | DUT = div 9 | VERILOG_SOURCES += $(PWD)/../${DUT}.sv 10 | TOPLEVEL = ${DUT} 11 | MODULE = ${DUT} 12 | 13 | # pass Verilog module parameters to Icarus Verilog 14 | COMPILE_ARGS += -P${DUT}.WIDTH=9 -P${DUT}.FBITS=4 15 | 16 | # each test Makefile needs its own build dir and results file 17 | COCOTB_RESULTS_FILE = results_${DUT}.xml 18 | SIM_BUILD = sim_build_${DUT} 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | -------------------------------------------------------------------------------- /lib/maths/test/divu.gtkw: -------------------------------------------------------------------------------- 1 | [*] divu gtkwave config 2 | [dumpfile] "divu.vcd" 3 | [savefile] "divu.gtkw" 4 | [timestart] 0 5 | [size] 1631 886 6 | [pos] -1 -1 7 | *-15.410237 86800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 | [sst_width] 193 9 | [signals_width] 178 10 | [sst_expanded] 1 11 | [sst_vpaned_height] 270 12 | @28 13 | divu.clk 14 | divu.rst 15 | divu.start 16 | divu.busy 17 | divu.done 18 | divu.valid 19 | divu.dbz 20 | divu.ovf 21 | @29 22 | divu.a[7:0] 23 | divu.b[7:0] 24 | divu.c[7:0] 25 | [pattern_trace] 1 26 | [pattern_trace] 0 27 | -------------------------------------------------------------------------------- /lib/maths/test/divu.mk: -------------------------------------------------------------------------------- 1 | ## Project F Library - divu cocotb Test Bench Makefile 2 | ## (C)2023 Will Green, open source software released under the MIT License 3 | ## Learn more at https://projectf.io/verilog-lib/ 4 | 5 | SIM ?= icarus 6 | TOPLEVEL_LANG ?= verilog 7 | 8 | DUT = divu 9 | VERILOG_SOURCES += $(PWD)/../${DUT}.sv 10 | TOPLEVEL = ${DUT} 11 | MODULE = ${DUT} 12 | 13 | # pass Verilog module parameters to Icarus Verilog 14 | COMPILE_ARGS += -P${DUT}.WIDTH=8 -P${DUT}.FBITS=4 15 | 16 | # each test Makefile needs its own build dir and results file 17 | COCOTB_RESULTS_FILE = results_${DUT}.xml 18 | SIM_BUILD = sim_build_${DUT} 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | -------------------------------------------------------------------------------- /lib/maths/test/divu_int.gtkw: -------------------------------------------------------------------------------- 1 | [*] divu_int gtkwave config 2 | [dumpfile] "divu_int.vcd" 3 | [savefile] "divu_int.gtkw" 4 | [timestart] 0 5 | [size] 1666 893 6 | [pos] -1 -1 7 | *-14.891823 29600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 | [sst_width] 193 9 | [signals_width] 217 10 | [sst_expanded] 1 11 | [sst_vpaned_height] 270 12 | @28 13 | divu_int.clk 14 | divu_int.rst 15 | divu_int.busy 16 | divu_int.done 17 | divu_int.valid 18 | divu_int.dbz 19 | @29 20 | divu_int.a[7:0] 21 | divu_int.b[7:0] 22 | divu_int.c[7:0] 23 | divu_int.r[7:0] 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /lib/maths/test/divu_int.mk: -------------------------------------------------------------------------------- 1 | ## Project F Library - divu_int cocotb Test Bench Makefile 2 | ## (C)2023 Will Green, open source software released under the MIT License 3 | ## Learn more at https://projectf.io/verilog-lib/ 4 | 5 | SIM ?= icarus 6 | TOPLEVEL_LANG ?= verilog 7 | 8 | DUT = divu_int 9 | VERILOG_SOURCES += $(PWD)/../${DUT}.sv 10 | TOPLEVEL = ${DUT} 11 | MODULE = ${DUT} 12 | 13 | # pass Verilog module parameters to Icarus Verilog 14 | COMPILE_ARGS += -P${DUT}.WIDTH=8 15 | 16 | # each test Makefile needs its own build dir and results file 17 | COCOTB_RESULTS_FILE = results_${DUT}.xml 18 | SIM_BUILD = sim_build_${DUT} 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | -------------------------------------------------------------------------------- /lib/maths/test/mul.gtkw: -------------------------------------------------------------------------------- 1 | [*] mul gtkwave config 2 | [dumpfile] "mul.vcd" 3 | [savefile] "mul.gtkw" 4 | [timestart] 0 5 | [size] 1614 841 6 | [pos] -1 -1 7 | *-15.336948 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 | [sst_width] 193 9 | [signals_width] 98 10 | [sst_expanded] 1 11 | [sst_vpaned_height] 252 12 | @28 13 | mul.clk 14 | mul.rst 15 | mul.start 16 | mul.busy 17 | mul.done 18 | mul.valid 19 | mul.ovf 20 | @29 21 | mul.a[8:0] 22 | mul.b[8:0] 23 | mul.val[8:0] 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /lib/maths/test/mul.mk: -------------------------------------------------------------------------------- 1 | ## Project F Library - mul cocotb Test Bench Makefile 2 | ## (C)2023 Will Green, open source software released under the MIT License 3 | ## Learn more at https://projectf.io/verilog-lib/ 4 | 5 | SIM ?= icarus 6 | TOPLEVEL_LANG ?= verilog 7 | 8 | DUT = mul 9 | VERILOG_SOURCES += $(PWD)/../${DUT}.sv 10 | TOPLEVEL = ${DUT} 11 | MODULE = ${DUT} 12 | 13 | # pass Verilog module parameters to Icarus Verilog 14 | COMPILE_ARGS += -P${DUT}.WIDTH=9 -P${DUT}.FBITS=4 15 | 16 | # each test Makefile needs its own build dir and results file 17 | COCOTB_RESULTS_FILE = results_${DUT}.xml 18 | SIM_BUILD = sim_build_${DUT} 19 | 20 | # include cocotb's make rules to take care of the simulator setup 21 | include $(shell cocotb-config --makefiles)/Makefile.sim 22 | -------------------------------------------------------------------------------- /lib/maths/xc7/clog2_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - $clog2 Test Bench (XC7) 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | module clog2_tb(); 6 | 7 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 8 | 9 | logic clk; 10 | logic rst; 11 | logic [7:0] num, clog_num; 12 | 13 | always_ff @(posedge clk) begin 14 | num <= num + 1; 15 | if (rst) num <= 0; 16 | end 17 | 18 | always_comb clog_num = $clog2(num); 19 | 20 | always #(CLK_PERIOD / 2) clk = ~clk; 21 | 22 | initial $monitor("$clog2(%d) = %d", num, clog_num); 23 | 24 | initial begin 25 | clk = 1; 26 | rst = 1; 27 | 28 | #100 rst = 0; 29 | #2560 $finish(); 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /lib/maths/xc7/lfsr_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Galois Linear-Feedback Shift Register Test Bench (XC7) 2 | // (C)2022 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module lfsr_tb(); 9 | 10 | parameter CLK_PERIOD = 10; // 10 ns == 100 MHz 11 | parameter LEN = 8; 12 | parameter TAPS = 8'b10111000; 13 | logic rst; 14 | logic clk_100m; 15 | logic en; 16 | logic [LEN-1:0] seed; 17 | logic [LEN-1:0] sreg; 18 | 19 | lfsr #( 20 | .LEN(LEN), 21 | .TAPS(TAPS) 22 | ) lfsr_inst ( 23 | .clk(clk_100m), 24 | .rst, 25 | .en, 26 | .seed, 27 | .sreg 28 | ); 29 | 30 | // generate clock 31 | always #(CLK_PERIOD / 2) clk_100m = ~clk_100m; 32 | 33 | initial begin 34 | rst = 1; 35 | seed = '1; 36 | clk_100m = 1; 37 | 38 | #100 rst = 0; 39 | en = 1; 40 | #10000 $finish; 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /lib/maths/xc7/sqrt_int_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Square Root (Integer) Test Bench (XC7) 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module sqrt_int_tb(); 9 | 10 | parameter CLK_PERIOD = 10; 11 | parameter WIDTH = 8; 12 | 13 | logic clk; 14 | logic start; // start signal 15 | logic busy; // calculation in progress 16 | logic valid; // root and rem are valid 17 | logic [WIDTH-1:0] rad; // radicand 18 | logic [WIDTH-1:0] root; // root 19 | logic [WIDTH-1:0] rem; // remainder 20 | 21 | sqrt_int #(.WIDTH(WIDTH)) sqrt_inst (.*); 22 | 23 | always #(CLK_PERIOD / 2) clk = ~clk; 24 | 25 | initial begin 26 | $monitor("\t%d:\tsqrt(%d) =%d (rem =%d) (V=%b)", $time, rad, root, rem, valid); 27 | end 28 | 29 | initial begin 30 | clk = 1; 31 | 32 | #100 rad = 8'b00000000; // 0 33 | start = 1; 34 | #10 start = 0; 35 | 36 | #50 rad = 8'b00000001; // 1 37 | start = 1; 38 | #10 start = 0; 39 | 40 | #50 rad = 8'b01111001; // 121 41 | start = 1; 42 | #10 start = 0; 43 | 44 | #50 rad = 8'b01010001; // 81 45 | start = 1; 46 | #10 start = 0; 47 | 48 | #50 rad = 8'b01011010; // 90 49 | start = 1; 50 | #10 start = 0; 51 | 52 | #50 rad = 8'b11111111; // 255 53 | start = 1; 54 | #10 start = 0; 55 | 56 | #50 $finish; 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /lib/maths/xc7/sqrt_tb.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Square Root (Fixed-Point) Test Bench (XC7) 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module sqrt_tb(); 9 | 10 | parameter CLK_PERIOD = 10; 11 | parameter WIDTH = 16; 12 | parameter FBITS = 8; 13 | parameter SF = 2.0**-8.0; // Q8.8 scaling factor is 2^-8 14 | 15 | logic clk; 16 | logic start; // start signal 17 | logic busy; // calculation in progress 18 | logic valid; // root and rem are valid 19 | logic [WIDTH-1:0] rad; // radicand 20 | logic [WIDTH-1:0] root; // root 21 | logic [WIDTH-1:0] rem; // remainder 22 | 23 | sqrt #(.WIDTH(WIDTH), .FBITS(FBITS)) sqrt_inst (.*); 24 | 25 | always #(CLK_PERIOD / 2) clk = ~clk; 26 | 27 | initial begin 28 | $monitor("\t%d:\tsqrt(%f) = %b (%f) (rem = %b) (V=%b)", 29 | $time, $itor(rad*SF), root, $itor(root*SF), rem, valid); 30 | end 31 | 32 | initial begin 33 | clk = 1; 34 | 35 | #100 rad = 16'b1110_1000_1001_0000; // 232.56250000 36 | start = 1; 37 | #10 start = 0; 38 | 39 | #120 rad = 16'b0000_0000_0100_0000; // 0.25 40 | start = 1; 41 | #10 start = 0; 42 | 43 | #120 rad = 16'b0000_0010_0000_0000; // 2.0 44 | start = 1; 45 | #10 start = 0; 46 | #120 $finish; 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /lib/maths/xc7/vivado/lfsr_tb_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | rst 25 | rst 26 | 27 | 28 | clk_100m 29 | clk_100m 30 | 31 | 32 | en 33 | en 34 | 35 | 36 | sreg[7:0] 37 | sreg[7:0] 38 | UNSIGNEDDECRADIX 39 | 40 | 41 | -------------------------------------------------------------------------------- /lib/memory/README.md: -------------------------------------------------------------------------------- 1 | # Memory - Verilog Library 2 | 3 | Memory Verilog designs from [Project F](https://projectf.io), including ROM, block ram, and SPRAM. You can freely build on these [MIT licensed](../../LICENSE) designs. Get an overview of the whole lib from the [Verilog Library blog](https://projectf.io/verilog-lib/). 4 | 5 | ## Verilog Modules 6 | 7 | * [rom_async.sv](rom_async.sv) - asynchronous ROM in logic (no clock) 8 | * [rom_sync.sv](rom_sync.sv) - synchronous ROM in logic (uses clock) 9 | * [bram_sdp.sv](bram_sdp.sv) - simple dual-port block RAM (one read port, one write port) 10 | * [ice40/spram.sv](ice40/spram.sv) - iCE40 single port RAM (16-bit data width) 11 | * [ice40/spram_nibble.sv](ice40/spram_nibble.sv) - iCE40 single port RAM (4-bit data width) 12 | 13 | Find other modules in the [Library](../). 14 | 15 | ## Blog Posts 16 | 17 | The following blog posts document and make use of these memory modules: 18 | 19 | * Practical ROM usage: [Hardware Spites](https://projectf.io/posts/hardware-sprites/) 20 | * Practical BRAM usage: [Lines & Triangles](https://projectf.io/posts/lines-and-triangles/) 21 | * [SPRAM on iCE40 FPGA](https://projectf.io/posts/spram-ice40-fpga/) - learn how to use SPRAM with Yosys and contrast it with Block RAM 22 | * [Initialize Memory in Verilog](https://projectf.io/posts/initialize-memory-in-verilog/) - use `$readmemh` and `$readmemb` to initialize the contents of ROM or RAM 23 | 24 | ## Memory Modules Interface 25 | 26 | These memory modules share similar parameters: 27 | 28 | * `WIDTH` - data width in bits (may be renamed `DATAW` in future) 29 | * `DEPTH` - memory depth (number of elements) 30 | * `INIT_F` - data file to load into memory at initialization 31 | * `ADDRW` - address width; by default this is calculated with `$clog2(DEPTH)` 32 | 33 | ## SystemVerilog? 34 | 35 | These modules use a little SystemVerilog to make Verilog more pleasant, see the main [Library README](../README.md#systemverilog) for details. 36 | -------------------------------------------------------------------------------- /lib/memory/bram_sdp.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Simple Dual-Port Block RAM 2 | // (C)2022 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module bram_sdp #( 9 | parameter WIDTH=8, 10 | parameter DEPTH=256, 11 | parameter INIT_F="", 12 | localparam ADDRW=$clog2(DEPTH) 13 | ) ( 14 | input wire logic clk_write, // write clock (port a) 15 | input wire logic clk_read, // read clock (port b) 16 | input wire logic we, // write enable (port a) 17 | input wire logic [ADDRW-1:0] addr_write, // write address (port a) 18 | input wire logic [ADDRW-1:0] addr_read, // read address (port b) 19 | input wire logic [WIDTH-1:0] data_in, // data in (port a) 20 | output logic [WIDTH-1:0] data_out // data out (port b) 21 | ); 22 | 23 | logic [WIDTH-1:0] memory [DEPTH]; 24 | 25 | initial begin 26 | if (INIT_F != 0) begin 27 | $display("Load init file '%s' into bram_sdp.", INIT_F); 28 | $readmemh(INIT_F, memory); 29 | end 30 | end 31 | 32 | // Port A: Sync Write 33 | always_ff @(posedge clk_write) begin 34 | if (we) memory[addr_write] <= data_in; 35 | end 36 | 37 | // Port B: Sync Read 38 | always_ff @(posedge clk_read) begin 39 | data_out <= memory[addr_read]; 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /lib/memory/ice40/spram.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Single Port RAM (iCE40) 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | // iCE40 SPRAM is documented in Lattice TN-02022: iCE40 SPRAM Usage Guide 9 | 10 | module spram #( 11 | localparam WIDTH=16, // fixed data width: 16 bits 12 | localparam DEPTH=16384, // fixed depth: 16K 13 | localparam ADDRW=$clog2(DEPTH) 14 | ) ( 15 | input wire logic clk, 16 | input wire logic [3:0] we, 17 | input wire logic [ADDRW-1:0] addr, 18 | input wire logic [WIDTH-1:0] data_in, 19 | output logic [WIDTH-1:0] data_out 20 | ); 21 | 22 | SB_SPRAM256KA spram_inst ( 23 | .ADDRESS(addr), 24 | .DATAIN(data_in), 25 | .MASKWREN(we), 26 | .WREN(|we), 27 | .CHIPSELECT(1'b1), 28 | .CLOCK(clk), 29 | .STANDBY(1'b0), 30 | .SLEEP(1'b0), 31 | .POWEROFF(1'b1), 32 | .DATAOUT(data_out) 33 | ); 34 | endmodule 35 | -------------------------------------------------------------------------------- /lib/memory/rom_async.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Asynchronous ROM 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module rom_async #( 9 | parameter WIDTH=8, 10 | parameter DEPTH=256, 11 | parameter INIT_F="", 12 | localparam ADDRW=$clog2(DEPTH) 13 | ) ( 14 | input wire logic [ADDRW-1:0] addr, 15 | output logic [WIDTH-1:0] data 16 | ); 17 | 18 | logic [WIDTH-1:0] memory [DEPTH]; 19 | 20 | initial begin 21 | if (INIT_F != 0) begin 22 | $display("Create rom_async with init file '%s'.", INIT_F); 23 | $readmemh(INIT_F, memory); 24 | end 25 | end 26 | 27 | always_comb data = memory[addr]; 28 | endmodule 29 | -------------------------------------------------------------------------------- /lib/memory/rom_sync.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Synchronous ROM 2 | // (C)2021 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module rom_sync #( 9 | parameter WIDTH=8, 10 | parameter DEPTH=256, 11 | parameter INIT_F="", 12 | localparam ADDRW=$clog2(DEPTH) 13 | ) ( 14 | input wire logic clk, 15 | input wire logic [ADDRW-1:0] addr, 16 | output logic [WIDTH-1:0] data 17 | ); 18 | 19 | logic [WIDTH-1:0] memory [DEPTH]; 20 | 21 | initial begin 22 | if (INIT_F != 0) begin 23 | $display("Create rom_sync with init file '%s'.", INIT_F); 24 | $readmemh(INIT_F, memory); 25 | end 26 | end 27 | 28 | always_ff @(posedge clk) begin 29 | data <= memory[addr]; 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /lib/null/ice40/SB_IO.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for iCE40 SB_IO 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module SB_IO #( 13 | parameter PIN_TYPE 14 | ) ( 15 | output logic PACKAGE_PIN, 16 | input wire logic OUTPUT_CLK, 17 | input wire logic D_OUT_0, 18 | input wire logic D_OUT_1 19 | ); 20 | 21 | // NULL MODULE 22 | 23 | endmodule 24 | /* verilator lint_on UNDRIVEN */ 25 | /* verilator lint_on UNUSED */ 26 | -------------------------------------------------------------------------------- /lib/null/ice40/SB_PLL40_PAD.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for iCE40 SB_PLL40_PAD 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module SB_PLL40_PAD #( 13 | parameter FEEDBACK_PATH, 14 | parameter DIVR, 15 | parameter DIVF, 16 | parameter DIVQ, 17 | parameter FILTER_RANGE 18 | ) ( 19 | input wire logic PACKAGEPIN, 20 | input wire logic RESETB, 21 | input wire logic BYPASS, 22 | output logic PLLOUTGLOBAL, 23 | output logic LOCK 24 | ); 25 | 26 | // NULL MODULE 27 | 28 | endmodule 29 | /* verilator lint_on UNDRIVEN */ 30 | /* verilator lint_on UNUSED */ 31 | -------------------------------------------------------------------------------- /lib/null/ice40/SB_SPRAM256KA.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for iCE40 SB_SPRAM256KA 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module SB_SPRAM256KA ( 13 | input wire logic [13:0] ADDRESS, 14 | input wire logic [15:0] DATAIN, 15 | input wire logic [3:0] MASKWREN, 16 | input wire logic WREN, 17 | input wire logic CHIPSELECT, 18 | input wire logic CLOCK, 19 | input wire logic STANDBY, 20 | input wire logic SLEEP, 21 | input wire logic POWEROFF, 22 | output logic [15:0] DATAOUT 23 | ); 24 | 25 | // NULL MODULE 26 | 27 | endmodule 28 | /* verilator lint_on UNDRIVEN */ 29 | /* verilator lint_on UNUSED */ 30 | -------------------------------------------------------------------------------- /lib/null/xc7/BUFG.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for Xilinx 7 Series BUFG 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module BUFG ( 13 | 14 | input wire logic I, 15 | output logic O 16 | ); 17 | 18 | // NULL MODULE 19 | 20 | endmodule 21 | /* verilator lint_on UNDRIVEN */ 22 | /* verilator lint_on UNUSED */ 23 | -------------------------------------------------------------------------------- /lib/null/xc7/MMCME2_BASE.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for Xilinx 7 Series MMCME2_BASE 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module MMCME2_BASE #( 13 | parameter CLKFBOUT_MULT_F, 14 | parameter CLKIN1_PERIOD, 15 | parameter CLKOUT0_DIVIDE_F, 16 | parameter CLKOUT1_DIVIDE, 17 | parameter DIVCLK_DIVIDE 18 | ) ( 19 | input wire logic CLKIN1, 20 | input wire logic PWRDWN, 21 | input wire logic RST, 22 | input wire logic CLKFBIN, 23 | output logic CLKOUT0, 24 | output logic CLKOUT0B, 25 | output logic CLKOUT1, 26 | output logic CLKOUT1B, 27 | output logic CLKOUT2, 28 | output logic CLKOUT2B, 29 | output logic CLKOUT3, 30 | output logic CLKOUT3B, 31 | output logic CLKOUT4, 32 | output logic CLKOUT5, 33 | output logic CLKOUT6, 34 | output logic CLKFBOUT, 35 | output logic CLKFBOUTB, 36 | output logic LOCKED 37 | ); 38 | 39 | // NULL MODULE 40 | 41 | endmodule 42 | /* verilator lint_on UNDRIVEN */ 43 | /* verilator lint_on UNUSED */ 44 | -------------------------------------------------------------------------------- /lib/null/xc7/OBUFDS.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for Xilinx 7 Series OBUFDS 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module OBUFDS #( 13 | parameter IOSTANDARD 14 | ) ( 15 | input wire logic I, 16 | output logic O, 17 | output logic OB 18 | ); 19 | 20 | // NULL MODULE 21 | 22 | endmodule 23 | /* verilator lint_on UNDRIVEN */ 24 | /* verilator lint_on UNUSED */ 25 | -------------------------------------------------------------------------------- /lib/null/xc7/OSERDESE2.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - Null Module for Xilinx 7 Series OSERDESE2 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | // NB. For Verilator linting - don't include in synthesis 6 | 7 | `default_nettype none 8 | `timescale 1ns / 1ps 9 | 10 | /* verilator lint_off UNUSED */ 11 | /* verilator lint_off UNDRIVEN */ 12 | module OSERDESE2 #( 13 | parameter SERDES_MODE, 14 | parameter DATA_WIDTH, 15 | parameter TRISTATE_WIDTH, 16 | parameter DATA_RATE_OQ, 17 | parameter DATA_RATE_TQ 18 | ) ( 19 | input wire logic CLK, 20 | input wire logic CLKDIV, 21 | input wire logic D1, 22 | input wire logic D2, 23 | input wire logic D3, 24 | input wire logic D4, 25 | input wire logic D5, 26 | input wire logic D6, 27 | input wire logic D7, 28 | input wire logic D8, 29 | input wire logic OCE, 30 | input wire logic RST, 31 | input wire logic SHIFTIN1, 32 | input wire logic SHIFTIN2, 33 | input wire logic T1, 34 | input wire logic T2, 35 | input wire logic T3, 36 | input wire logic T4, 37 | input wire logic TBYTEIN, 38 | input wire logic TCE, 39 | output logic OFB, 40 | output logic OQ, 41 | output logic SHIFTOUT1, 42 | output logic SHIFTOUT2, 43 | output logic TBYTEOUT, 44 | output logic TFB, 45 | output logic TQ 46 | ); 47 | 48 | // NULL MODULE 49 | 50 | endmodule 51 | /* verilator lint_on UNDRIVEN */ 52 | /* verilator lint_on UNUSED */ 53 | -------------------------------------------------------------------------------- /lib/res/fonts/unifont-licences/README.md: -------------------------------------------------------------------------------- 1 | # Font Licences 2 | 3 | Licences in this directory only apply to font resources based on GNU Unifont. 4 | Individual font files clearly state if these licences cover them. 5 | 6 | The primary Project F MIT licence covers other content. 7 | See the LICENSE file at the root of this project for details. 8 | -------------------------------------------------------------------------------- /lib/res/palettes/README.md: -------------------------------------------------------------------------------- 1 | # Colour Palettes 2 | 3 | This folder contains colour palettes in `$readmemh` format. See the blog post on [display signals and colour lookup tables](https://projectf.io/posts/display-signals/) for advice on using palettes. 4 | 5 | _More details to follow._ 6 | 7 | ## 16 Colour Palettes 8 | 9 | ![](../../../doc/img/palettes-16.png?raw=true "") 10 | -------------------------------------------------------------------------------- /lib/res/palettes/antiquity16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Antiquity16 Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | // 4-bit per channel version created by Project F from ILTA original 6 | // Palette source: https://lospec.com/palette-list/antiquity16 7 | 8 | 222 322 432 743 B75 FA7 FC8 675 995 789 9AB E65 F87 D63 EA3 FEA 9 | -------------------------------------------------------------------------------- /lib/res/palettes/fading16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Fading 16 Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | // 4-bit per channel version created by Project F from CalmRadish original 6 | // Palette source: https://lospec.com/palette-list/fading-16 7 | 8 | DDA CB8 C86 A55 745 544 556 687 9A8 655 988 BA9 886 BA6 876 B96 9 | -------------------------------------------------------------------------------- /lib/res/palettes/grey16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Greyscale 16 Colour Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | 000 111 222 333 444 555 666 777 888 999 AAA BBB CCC DDD EEE FFF 6 | -------------------------------------------------------------------------------- /lib/res/palettes/greyinvert16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Greyscale Inverted 16 Colour Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | FFF EEE DDD CCC BBB AAA 999 888 777 666 555 444 333 222 111 000 6 | -------------------------------------------------------------------------------- /lib/res/palettes/pico8_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - PICO-8 Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | // 4-bit per channel version created by Project F from Lexaloffle original 6 | // Palette source: https://lospec.com/palette-list/pico-8 7 | 8 | 000 235 825 085 B53 655 CCC FFF F05 FA0 FF2 0E3 3BF 87A F7B FCA 9 | -------------------------------------------------------------------------------- /lib/res/palettes/sepia16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Sepia 16 Colour Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | 000 100 210 321 432 543 654 765 876 987 A98 BA9 CBA DCB EDC FED 6 | -------------------------------------------------------------------------------- /lib/res/palettes/sweetie16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Sweetie 16 Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | // 4-bit per channel version created by Project F from GrafxKid original 6 | // Palette source: https://lospec.com/palette-list/sweetie-16 7 | 8 | 223 626 B45 F85 FD7 AF7 4B6 278 337 46D 4AF 7FF FFF 9BC 578 345 9 | -------------------------------------------------------------------------------- /lib/res/palettes/teleport16_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Teleport 16 Colour Palette 2 | // 16 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | 825 B15 F05 F52 FA0 FC1 FF2 7E2 0E3 0B4 085 19A 3BF 59C 87A 847 6 | -------------------------------------------------------------------------------- /lib/res/palettes/teleport4_4b.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Teleport 4 Colour Palette 2 | // 4 Colours with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | 825 B15 F05 F52 6 | -------------------------------------------------------------------------------- /lib/res/test/test_box_12x9.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Test Box 12x9 Image (4-bit) 2 | // Learn more at https://projectf.io 3 | 6 3 3 3 3 3 3 3 3 3 3 A 4 | 3 E E E E E E E E E E 4 5 | 3 E E E E E E E E E E 4 6 | 3 E E E E E E E E E E 4 7 | 3 E E E E E E E E E E 4 8 | 3 E E E E E E E E E E 4 9 | 3 E E E E E E E E E E 4 10 | 3 E E E E E E E E E E 4 11 | 6 3 3 3 3 3 3 3 3 3 3 A 12 | -------------------------------------------------------------------------------- /lib/res/test/test_box_db_12x9.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Test Box Double Buffered 12x9 Image (4-bit) 2 | // Learn more at https://projectf.io 3 | 6 3 3 3 3 3 3 3 3 3 3 A 4 | 3 E E E E E E E E E E 4 5 | 3 E E E E E E E E E E 4 6 | 3 E E E E E E E E E E 4 7 | 3 E E E E E E E E E E 4 8 | 3 E E E E E E E E E E 4 9 | 3 E E E E E E E E E E 4 10 | 3 E E E E E E E E E E 4 11 | 6 3 3 3 3 3 3 3 3 3 3 A 12 | 0 0 0 0 0 0 0 0 0 0 0 0 13 | 0 0 0 0 0 0 0 0 0 0 0 0 14 | 0 0 0 0 0 0 0 0 0 0 0 0 15 | 0 0 0 0 0 0 0 0 0 0 0 0 16 | 0 0 0 0 0 0 0 0 0 0 0 0 17 | 0 0 0 0 0 0 0 0 0 0 0 0 18 | 0 0 0 0 0 0 0 0 0 0 0 0 19 | 0 0 0 0 0 0 0 0 0 0 0 0 20 | 0 0 0 0 0 0 0 0 0 0 0 0 21 | -------------------------------------------------------------------------------- /lib/res/test/test_clear_12x9.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Test Clear 12x9 Image (0-bit) 2 | // Learn more at https://projectf.io 3 | 0 0 0 0 0 0 0 0 0 0 0 0 4 | 0 0 0 0 0 0 0 0 0 0 0 0 5 | 0 0 0 0 0 0 0 0 0 0 0 0 6 | 0 0 0 0 0 0 0 0 0 0 0 0 7 | 0 0 0 0 0 0 0 0 0 0 0 0 8 | 0 0 0 0 0 0 0 0 0 0 0 0 9 | 0 0 0 0 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 0 0 0 0 11 | 0 0 0 0 0 0 0 0 0 0 0 0 12 | -------------------------------------------------------------------------------- /lib/res/test/test_palette.mem: -------------------------------------------------------------------------------- 1 | // Project F Library - Test 16 Colour Palette 2 | // PICO-8 Palette with 4 bits per channel 3 | // Learn more at https://projectf.io 4 | 5 | 000 // 0 - black 6 | 235 // 1 - dark-blue 7 | 825 // 2 - dark-purple 8 | 085 // 3 - dark-green 9 | B53 // 4 - brown 10 | 655 // 5 - dark-grey 11 | CCC // 6 - light-grey 12 | FFF // 7 - white 13 | F05 // 8 - red 14 | FA0 // 9 - orange 15 | FF2 // A - yellow 16 | 0E3 // B - green 17 | 3BF // C - blue 18 | 87A // D - indigo 19 | F7B // E - pink 20 | FCA // F - peach 21 | -------------------------------------------------------------------------------- /lib/uart/README.md: -------------------------------------------------------------------------------- 1 | # UART - Verilog Library 2 | 3 | A UART was one of the first SystemVerilog designs I created. These designs are not polished, but I hope you find them useful. You can freely build on these [MIT licensed](../../LICENSE) designs. Get an overview of the whole lib from the [Verilog Library blog](https://projectf.io/verilog-lib/). 4 | 5 | ## Verilog Modules 6 | 7 | * [uart_baud.sv](uart_baud.sv) - UART baud rate generator 8 | * [uart_rx.sv](uart_rx.sv) - UART receiver (to FPGA) 9 | * [uart_tx.sv](uart_tx.sv) - UART transmitter (from FPGA) 10 | 11 | ### Test Benches 12 | 13 | _Test benches still need to be added for UART._ 14 | 15 | ### Examples 16 | 17 | * [top_uart.sv](examples/top_uart.sv) - echo example at 9600 baud (8N1) 18 | 19 | _NB. Transmit and receive are from the point of view of the FPGA._ 20 | 21 | ## Blog Posts 22 | 23 | No Project F blog posts reference these modules as yet. 24 | 25 | ## SystemVerilog? 26 | 27 | These modules use a little SystemVerilog to make Verilog more pleasant, see the main [Library README](../README.md#systemverilog) for details. 28 | -------------------------------------------------------------------------------- /lib/uart/examples/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F Library - UART Examples: Arty A7-35T Board Constraints 2 | ## (C)2021 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst}]; 15 | 16 | # UART 17 | set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {uart_tx}]; 18 | set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports {uart_rx}]; 19 | -------------------------------------------------------------------------------- /lib/uart/uart_baud.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - UART Baud Generator 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | // baud generator: 100 MHz -> 153,600 (16 x 9,600) 9 | // 100 MHz / 153,600 = 651.04; 2^24/651.04 = 25,770 10 | 11 | module uart_baud #( 12 | parameter CNT_W=24, // counter width 13 | parameter CNT_INC=24'd25770 // counter increment 14 | ) ( 15 | input wire logic clk, 16 | input wire logic rst, 17 | output logic stb_baud, // baud strobe 18 | output logic stb_sample // over-sampling baud strobe 19 | ); 20 | 21 | logic [CNT_W+3:0] cnt; 22 | logic [CNT_W-1:0] cnt_16x; 23 | 24 | always_ff @(posedge clk) begin 25 | {stb_baud, cnt} <= cnt + {4'b0000, CNT_INC}; 26 | 27 | if (rst) begin 28 | stb_baud <= 1'b0; 29 | cnt <= {CNT_W+4{1'b0}}; 30 | end 31 | end 32 | 33 | always_ff @(posedge clk) begin 34 | {stb_sample, cnt_16x} <= cnt_16x + CNT_INC; 35 | 36 | if (rst) begin 37 | stb_sample <= 1'b0; 38 | cnt_16x <= {CNT_W{1'b0}}; 39 | end 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /lib/uart/uart_tx.sv: -------------------------------------------------------------------------------- 1 | // Project F Library - UART 8N1 Transmitter 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module uart_tx ( 9 | input wire logic clk, 10 | input wire logic rst, 11 | input wire logic stb_baud, // baud strobe 12 | input wire logic tx_start, // start transmission 13 | input wire logic [7:0] data_in, // data to transmit 14 | output logic data_out, // serial data out 15 | output logic tx_busy, // busy with transmission 16 | output logic tx_next // ready for next data in 17 | ); 18 | 19 | enum {IDLE, START, DATA, STOP} state, state_next; 20 | logic [2:0] data_idx, data_idx_next; // eight data bits: 0-7 21 | localparam LAST_BIT = 3'd7; 22 | 23 | always_ff @(posedge clk) begin 24 | if (stb_baud) begin 25 | state <= state_next; 26 | data_idx <= data_idx_next; 27 | end 28 | if (rst) begin 29 | state <= IDLE; 30 | data_idx <= 0; 31 | end 32 | end 33 | 34 | always_comb begin 35 | data_out = 1'b1; 36 | state_next = IDLE; 37 | data_idx_next = 0; 38 | 39 | case(state) 40 | IDLE: state_next = (tx_start) ? START : IDLE; 41 | STOP: state_next = IDLE; 42 | START: begin 43 | data_out = 0; 44 | state_next = DATA; 45 | end 46 | DATA: begin 47 | data_out = data_in[data_idx]; 48 | data_idx_next = data_idx + 1; 49 | state_next = (data_idx == LAST_BIT) ? STOP : DATA; 50 | end 51 | endcase 52 | end 53 | 54 | always_comb begin 55 | tx_busy = (state != IDLE); 56 | tx_next = (state == STOP); // safe to update data_in 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /maths/demo/func_circle.sv: -------------------------------------------------------------------------------- 1 | // Project F: Maths Demo - Function: Circle 2 | // (C)2023 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module func_circle #( 9 | CORDW=8, // signed coordinate width (bits) 10 | RADIUS=128 // circle radius 11 | ) ( 12 | input wire clk, 13 | input wire signed [CORDW-1:0] x, 14 | input wire signed [CORDW-1:0] y, 15 | output logic r 16 | ); 17 | 18 | // // v1: simple version (latency: 2 cycles) 19 | // logic signed [2*CORDW:0] circle; // addition of two squares, so twice as wide 20 | // always_ff @(posedge clk) begin 21 | // circle <= x*x + y*y; 22 | // r <= (circle < RADIUS * RADIUS) ? 1 : 0; 23 | // end 24 | 25 | // v2: extra pipeline stages (latency: 4 cycles) 26 | logic [2*CORDW-1:0] x_squared, x_squared_p1; 27 | logic [2*CORDW-1:0] y_squared, y_squared_p1; 28 | logic signed [2*CORDW:0] circle; // addition of two squares, so twice as wide 29 | always_ff @(posedge clk) begin 30 | x_squared_p1 <= x*x; 31 | x_squared <= x_squared_p1; 32 | 33 | y_squared_p1 <= y*y; 34 | y_squared <= y_squared_p1; 35 | 36 | circle <= x_squared + y_squared; 37 | r <= (circle < RADIUS * RADIUS) ? 1 : 0; 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /maths/demo/func_cubed.sv: -------------------------------------------------------------------------------- 1 | // Project F: Maths Demo - Function: Cubed 2 | // (C)2023 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module func_cubed #( 9 | CORDW=8, // signed coordinate width (bits) 10 | Y_SCALE=16384 // increase y-scale so we can see more on-screen 11 | ) ( 12 | input wire clk, 13 | input wire signed [CORDW-1:0] x, 14 | input wire signed [CORDW-1:0] y, 15 | output logic r 16 | ); 17 | 18 | // // v1: simple version (latency: 2 cycles) 19 | // logic signed [3*CORDW-1:0] x_cubed, y_scaled; 20 | // always_ff @(posedge clk) begin 21 | // y_scaled <= Y_SCALE * y; 22 | // x_cubed <= x*x*x; 23 | // r <= (x_cubed < y_scaled) ? 1 : 0; 24 | // end 25 | 26 | // v2: extra pipeline stages (latency: 5 cycles) 27 | logic signed [2*CORDW-1:0] x_squared, x_squared_p1; 28 | logic signed [3*CORDW-1:0] x_cubed_p1, x_cubed; 29 | logic signed [3*CORDW-1:0] y_scaled, y_scaled_p1, y_scaled_p2, y_scaled_p3; 30 | always_ff @(posedge clk) begin 31 | y_scaled_p3 <= Y_SCALE * y; 32 | y_scaled_p2 <= y_scaled_p3; 33 | y_scaled_p1 <= y_scaled_p2; 34 | y_scaled <= y_scaled_p1; 35 | 36 | x_squared_p1 <= x*x; 37 | x_squared <= x_squared_p1; 38 | x_cubed_p1 <= x*x_squared; 39 | x_cubed <= x_cubed_p1; 40 | 41 | r <= (x_cubed < y_scaled) ? 1 : 0; 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /maths/demo/func_polynomial.sv: -------------------------------------------------------------------------------- 1 | // Project F: Maths Demo - Function: x⁴−x² 2 | // (C)2023 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module func_polynomial #( 9 | CORDW=8, // signed coordinate width (bits) 10 | Y_SCALE=2**24 // increase y-scale so we can see more on-screen 11 | ) ( 12 | input wire clk, 13 | input wire signed [CORDW-1:0] x, 14 | input wire signed [CORDW-1:0] y, 15 | output logic r 16 | ); 17 | 18 | // // v1: simple version (latency: 2 cycles) 19 | // logic signed [4*CORDW-1:0] x_poly, y_scaled; 20 | // always_ff @(posedge clk) begin 21 | // y_scaled <= Y_SCALE * y; 22 | // x_poly <= x*x*x*x - 2**16 * x*x; 23 | // r <= (x_poly < y_scaled) ? 1 : 0; 24 | // end 25 | 26 | // v2: extra pipeline stages (latency: 6 cycles) 27 | logic signed [2*CORDW-1:0] x_squared, x_squared_p1, x_squared_p2, x_squared_p3; 28 | logic signed [4*CORDW-1:0] x_fourth, x_fourth_p1, x_poly; 29 | logic signed [4*CORDW-1:0] y_scaled, y_scaled_p1, y_scaled_p2, y_scaled_p3, y_scaled_p4; 30 | always_ff @(posedge clk) begin 31 | y_scaled_p4 <= Y_SCALE * y; 32 | y_scaled_p3 <= y_scaled_p4; 33 | y_scaled_p2 <= y_scaled_p3; 34 | y_scaled_p1 <= y_scaled_p2; 35 | y_scaled <= y_scaled_p1; 36 | 37 | x_squared_p3 <= x*x; 38 | x_squared_p2 <= x_squared_p3; 39 | x_squared_p1 <= x_squared_p2; 40 | x_squared <= x_squared_p1; 41 | 42 | x_fourth_p1 <= x_squared_p2 * x_squared_p2; 43 | x_fourth <= x_fourth_p1; 44 | 45 | x_poly <= x_fourth - 2**16 * x_squared; 46 | r <= (x_poly < y_scaled) ? 1 : 0; 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /maths/demo/func_squared.sv: -------------------------------------------------------------------------------- 1 | // Project F: Maths Demo - Function: Squared 2 | // (C)2023 Will Green, open source hardware released under the MIT License 3 | // Learn more at https://projectf.io 4 | 5 | `default_nettype none 6 | `timescale 1ns / 1ps 7 | 8 | module func_squared #( 9 | CORDW=8, // signed coordinate width (bits) 10 | Y_SCALE=256 // increase y-scale so we can see more on-screen 11 | ) ( 12 | input wire clk, 13 | input wire signed [CORDW-1:0] x, 14 | input wire signed [CORDW-1:0] y, 15 | output logic r 16 | ); 17 | 18 | // // v1: simple version (latency: 2 cycles) 19 | // logic signed [2*CORDW-1:0] x_squared; 20 | // logic signed [2*CORDW-1:0] y_scaled; 21 | // always_ff @(posedge clk) begin 22 | // y_scaled <= Y_SCALE * y; 23 | // x_squared <= x*x; 24 | // r <= (x_squared < y_scaled) ? 1 : 0; 25 | // end 26 | 27 | // v2: extra pipeline stages (latency: 3 cycles) 28 | logic signed [2*CORDW-1:0] x_squared, x_squared_p1; 29 | logic signed [2*CORDW-1:0] y_scaled, y_scaled_p1; 30 | always_ff @(posedge clk) begin 31 | y_scaled_p1 <= Y_SCALE * y; 32 | y_scaled <= y_scaled_p1; 33 | 34 | x_squared_p1 <= x*x; 35 | x_squared <= x_squared_p1; 36 | 37 | r <= (x_squared < y_scaled) ? 1 : 0; 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /maths/demo/ice40/Makefile: -------------------------------------------------------------------------------- 1 | ## Project F: Maths Demo - iCEBreaker Makefile 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | # configuration 6 | SHELL = /bin/sh 7 | FPGA_PKG = sg48 8 | FPGA_TYPE = up5k 9 | PCF = icebreaker.pcf 10 | 11 | # included modules 12 | PATH_LIB = ../../../lib 13 | ADD_SRC = ${PATH_LIB}/clock/ice40/clock_480p.sv 14 | ADD_SRC += ${PATH_LIB}/display/display_480p.sv 15 | ADD_SRC += ../func_circle.sv ../func_cubed.sv 16 | ADD_SRC += ../func_polynomial.sv ../func_squared.sv 17 | 18 | top_graphing: top_graphing.rpt top_graphing.bin 19 | 20 | %.json: %.sv $(ADD_SRC) 21 | yosys -ql $(subst .json,,$@)-yosys.log -p 'synth_ice40 -dsp -abc2 -top $(subst .json,,$@) -json $@' $< $(ADD_SRC) 22 | 23 | %.asc: %.json 24 | nextpnr-ice40 --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@ 25 | 26 | %.rpt: %.asc 27 | icetime -d ${FPGA_TYPE} -mtr $@ $< 28 | 29 | %.bin: %.asc 30 | icepack $< $@ 31 | 32 | clean: 33 | rm -f top*.json top*.asc top*.rpt top*.bin top*yosys.log 34 | 35 | all: top_graphing 36 | 37 | .PHONY: all clean 38 | -------------------------------------------------------------------------------- /maths/demo/ice40/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | ## Project F: Maths Demo - iCEBreaker Board Constraints (DVI) 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## Board Clock: 12 MHz 6 | set_frequency clk_12m 12 7 | set_io -nowarn clk_12m 35 8 | 9 | ## Buttons 10 | set_io -nowarn btn_rst 10 11 | 12 | ## 12-bit DVI Pmod on Pmod 1A/1B 13 | set_io -nowarn dvi_clk 38 14 | set_io -nowarn dvi_hsync 31 15 | set_io -nowarn dvi_vsync 28 16 | set_io -nowarn dvi_de 32 17 | set_io -nowarn dvi_r[0] 48 18 | set_io -nowarn dvi_r[1] 2 19 | set_io -nowarn dvi_r[2] 3 20 | set_io -nowarn dvi_r[3] 4 21 | set_io -nowarn dvi_g[0] 44 22 | set_io -nowarn dvi_g[1] 45 23 | set_io -nowarn dvi_g[2] 46 24 | set_io -nowarn dvi_g[3] 47 25 | set_io -nowarn dvi_b[0] 34 26 | set_io -nowarn dvi_b[1] 36 27 | set_io -nowarn dvi_b[2] 42 28 | set_io -nowarn dvi_b[3] 43 29 | -------------------------------------------------------------------------------- /maths/demo/xc7-hd/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Maths Demo - Nexys Video Board Constraints 2 | ## (C)2023 Will Green, Open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports {btn_rst_n}]; 15 | 16 | ## HDMI Source 17 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_p}]; 18 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_clk_n}]; 19 | set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_p}]; 20 | set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch0_n}]; 21 | set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_p}]; 22 | set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch1_n}]; 23 | set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_p}]; 24 | set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_ch2_n}]; 25 | -------------------------------------------------------------------------------- /maths/demo/xc7/arty.xdc: -------------------------------------------------------------------------------- 1 | ## Project F: Maths Demo - Arty A7-35T Board Constraints 2 | ## (C)2023 Will Green, open source hardware released under the MIT License 3 | ## Learn more at https://projectf.io 4 | 5 | ## FPGA Configuration I/O Options 6 | set_property CONFIG_VOLTAGE 3.3 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | 9 | ## Board Clock: 100 MHz 10 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_100m}]; 11 | create_clock -name clk_100m -period 10.00 [get_ports {clk_100m}]; 12 | 13 | ## Buttons 14 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {btn_rst_n}]; 15 | 16 | ## VGA Pmod on Header JB/JC 17 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {vga_hsync}]; 18 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {vga_vsync}]; 19 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {vga_r[0]}]; 20 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {vga_r[1]}]; 21 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {vga_r[2]}]; 22 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {vga_r[3]}]; 23 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {vga_g[0]}]; 24 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {vga_g[1]}]; 25 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {vga_g[2]}]; 26 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {vga_g[3]}]; 27 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {vga_b[0]}]; 28 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {vga_b[1]}]; 29 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {vga_b[2]}]; 30 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {vga_b[3]}]; 31 | --------------------------------------------------------------------------------