├── .clang-format ├── .envrc ├── .gitignore ├── .mxproject ├── CMakeLists.txt ├── Core ├── Inc │ ├── gpio.h │ ├── main.h │ ├── stm32f4xx_hal_conf.h │ └── stm32f4xx_it.h └── Src │ ├── gpio.c │ ├── main.c │ ├── stm32f4xx_hal_msp.c │ ├── stm32f4xx_it.c │ └── system_stm32f4xx.c ├── CubeMX ├── Makefile ├── STM32F407VGTx_FLASH.ld └── startup_stm32f407xx.s ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F4xx │ │ │ └── Include │ │ │ ├── stm32f407xx.h │ │ │ ├── stm32f4xx.h │ │ │ └── system_stm32f4xx.h │ └── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h └── STM32F4xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f4xx_hal.h │ ├── stm32f4xx_hal_cortex.h │ ├── stm32f4xx_hal_def.h │ ├── stm32f4xx_hal_dma.h │ ├── stm32f4xx_hal_dma_ex.h │ ├── stm32f4xx_hal_exti.h │ ├── stm32f4xx_hal_flash.h │ ├── stm32f4xx_hal_flash_ex.h │ ├── stm32f4xx_hal_flash_ramfunc.h │ ├── stm32f4xx_hal_gpio.h │ ├── stm32f4xx_hal_gpio_ex.h │ ├── stm32f4xx_hal_pwr.h │ ├── stm32f4xx_hal_pwr_ex.h │ ├── stm32f4xx_hal_rcc.h │ ├── stm32f4xx_hal_rcc_ex.h │ ├── stm32f4xx_hal_tim.h │ └── stm32f4xx_hal_tim_ex.h │ └── Src │ ├── stm32f4xx_hal.c │ ├── stm32f4xx_hal_cortex.c │ ├── stm32f4xx_hal_dma.c │ ├── stm32f4xx_hal_dma_ex.c │ ├── stm32f4xx_hal_exti.c │ ├── stm32f4xx_hal_flash.c │ ├── stm32f4xx_hal_flash_ex.c │ ├── stm32f4xx_hal_flash_ramfunc.c │ ├── stm32f4xx_hal_gpio.c │ ├── stm32f4xx_hal_pwr.c │ ├── stm32f4xx_hal_pwr_ex.c │ ├── stm32f4xx_hal_rcc.c │ ├── stm32f4xx_hal_rcc_ex.c │ ├── stm32f4xx_hal_tim.c │ └── stm32f4xx_hal_tim_ex.c ├── Makefile ├── Project ├── projectMain.cpp └── projectMain.h ├── README.md ├── STM32-project-template.ioc ├── default.nix └── gcc-arm-none-eabi.cmake /.clang-format: -------------------------------------------------------------------------------- 1 | --- 2 | Language: Cpp 3 | # BasedOnStyle: Microsoft 4 | AccessModifierOffset: -4 5 | AlignAfterOpenBracket: AlwaysBreak 6 | AlignConsecutiveMacros: false 7 | AlignConsecutiveAssignments: false 8 | AlignConsecutiveDeclarations: false 9 | AlignEscapedNewlines: Right 10 | AlignOperands: AlignAfterOperator 11 | AlignTrailingComments: true 12 | AllowAllArgumentsOnNextLine: true 13 | AllowAllConstructorInitializersOnNextLine: true 14 | AllowAllParametersOfDeclarationOnNextLine: true 15 | AllowShortBlocksOnASingleLine: Never 16 | AllowShortCaseLabelsOnASingleLine: false 17 | AllowShortFunctionsOnASingleLine: None 18 | AllowShortLambdasOnASingleLine: All 19 | AllowShortIfStatementsOnASingleLine: Never 20 | AllowShortLoopsOnASingleLine: false 21 | AlwaysBreakAfterDefinitionReturnType: None 22 | AlwaysBreakAfterReturnType: None 23 | AlwaysBreakBeforeMultilineStrings: true 24 | AlwaysBreakTemplateDeclarations: true 25 | BinPackArguments: false 26 | BinPackParameters: false 27 | BreakBeforeBraces: Allman 28 | BraceWrapping: 29 | AfterCaseLabel: true 30 | AfterClass: true 31 | AfterControlStatement: true 32 | AfterEnum: true 33 | AfterFunction: true 34 | AfterNamespace: true 35 | AfterObjCDeclaration: true 36 | AfterStruct: true 37 | AfterUnion: true 38 | AfterExternBlock: true 39 | BeforeCatch: true 40 | BeforeElse: true 41 | IndentBraces: false 42 | SplitEmptyFunction: true 43 | SplitEmptyRecord: true 44 | SplitEmptyNamespace: true 45 | BreakBeforeBinaryOperators: NonAssignment 46 | BreakBeforeInheritanceComma: true 47 | BreakInheritanceList: BeforeColon 48 | BreakBeforeTernaryOperators: true 49 | BreakConstructorInitializersBeforeComma: true 50 | BreakConstructorInitializers: BeforeColon 51 | BreakAfterJavaFieldAnnotations: false 52 | BreakStringLiterals: true 53 | ColumnLimit: 95 54 | CommentPragmas: '^ IWYU pragma:' 55 | CompactNamespaces: false 56 | ConstructorInitializerAllOnOneLineOrOnePerLine: false 57 | ConstructorInitializerIndentWidth: 4 58 | ContinuationIndentWidth: 4 59 | Cpp11BracedListStyle: true 60 | DeriveLineEnding: false 61 | DerivePointerAlignment: false 62 | DisableFormat: false 63 | ExperimentalAutoDetectBinPacking: false 64 | FixNamespaceComments: true 65 | ForEachMacros: 66 | - foreach 67 | - Q_FOREACH 68 | - BOOST_FOREACH 69 | IncludeBlocks: Preserve 70 | IncludeCategories: 71 | - Regex: '^"(llvm|llvm-c|clang|clang-c)/' 72 | Priority: 2 73 | SortPriority: 0 74 | - Regex: '^(<|"(gtest|gmock|isl|json)/)' 75 | Priority: 3 76 | SortPriority: 0 77 | - Regex: '.*' 78 | Priority: 1 79 | SortPriority: 0 80 | IncludeIsMainRegex: '(Test)?$' 81 | IncludeIsMainSourceRegex: '' 82 | IndentCaseLabels: false 83 | IndentGotoLabels: true 84 | IndentPPDirectives: None 85 | IndentWidth: 4 86 | IndentWrappedFunctionNames: false 87 | JavaScriptQuotes: Leave 88 | JavaScriptWrapImports: true 89 | KeepEmptyLinesAtTheStartOfBlocks: true 90 | MacroBlockBegin: '' 91 | MacroBlockEnd: '' 92 | MaxEmptyLinesToKeep: 1 93 | NamespaceIndentation: None 94 | ObjCBinPackProtocolList: Auto 95 | ObjCBlockIndentWidth: 2 96 | ObjCSpaceAfterProperty: false 97 | ObjCSpaceBeforeProtocolList: true 98 | PenaltyBreakAssignment: 2 99 | PenaltyBreakBeforeFirstCallParameter: 19 100 | PenaltyBreakComment: 300 101 | PenaltyBreakFirstLessLess: 120 102 | PenaltyBreakString: 1000 103 | PenaltyBreakTemplateDeclaration: 10 104 | PenaltyExcessCharacter: 1000000 105 | PenaltyReturnTypeOnItsOwnLine: 1000 106 | PointerAlignment: Left 107 | ReflowComments: true 108 | SortIncludes: true 109 | SortUsingDeclarations: true 110 | SpaceAfterCStyleCast: false 111 | SpaceAfterLogicalNot: false 112 | SpaceAfterTemplateKeyword: true 113 | SpaceBeforeAssignmentOperators: true 114 | SpaceBeforeCpp11BracedList: false 115 | SpaceBeforeCtorInitializerColon: true 116 | SpaceBeforeInheritanceColon: true 117 | SpaceBeforeParens: ControlStatements 118 | SpaceBeforeRangeBasedForLoopColon: true 119 | SpaceInEmptyBlock: false 120 | SpaceInEmptyParentheses: false 121 | SpacesBeforeTrailingComments: 1 122 | SpacesInAngles: false 123 | SpacesInConditionalStatement: false 124 | SpacesInContainerLiterals: true 125 | SpacesInCStyleCastParentheses: false 126 | SpacesInParentheses: false 127 | SpacesInSquareBrackets: false 128 | SpaceBeforeSquareBrackets: false 129 | Standard: Latest 130 | StatementMacros: 131 | - Q_UNUSED 132 | - QT_REQUIRE_VERSION 133 | TabWidth: 4 134 | UseCRLF: false 135 | UseTab: Never 136 | ... 137 | 138 | -------------------------------------------------------------------------------- /.envrc: -------------------------------------------------------------------------------- 1 | use_nix 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | # GIT 4 | !.gitignore 5 | !README.md 6 | 7 | # NIX 8 | !default.nix 9 | !.envrc 10 | 11 | # TOOLS 12 | !Makefile 13 | !CMakeLists.txt 14 | !gcc-arm-none-eabi.cmake 15 | !.clang-format 16 | 17 | # EXAMPLE 18 | !Core 19 | !Drivers 20 | !CubeMX 21 | !Project 22 | !STM32-project-template.ioc 23 | !.mxproject 24 | -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousGenFiles] 2 | AdvancedFolderStructure=true 3 | HeaderFileListSize=4 4 | HeaderFiles#0=/home/matej/Privat_projects/STM32-project-template/Core/Inc/gpio.h 5 | HeaderFiles#1=/home/matej/Privat_projects/STM32-project-template/Core/Inc/stm32f4xx_it.h 6 | HeaderFiles#2=/home/matej/Privat_projects/STM32-project-template/Core/Inc/stm32f4xx_hal_conf.h 7 | HeaderFiles#3=/home/matej/Privat_projects/STM32-project-template/Core/Inc/main.h 8 | HeaderFolderListSize=1 9 | HeaderPath#0=/home/matej/Privat_projects/STM32-project-template/Core/Inc 10 | HeaderFiles=; 11 | SourceFileListSize=4 12 | SourceFiles#0=/home/matej/Privat_projects/STM32-project-template/Core/Src/gpio.c 13 | SourceFiles#1=/home/matej/Privat_projects/STM32-project-template/Core/Src/stm32f4xx_it.c 14 | SourceFiles#2=/home/matej/Privat_projects/STM32-project-template/Core/Src/stm32f4xx_hal_msp.c 15 | SourceFiles#3=/home/matej/Privat_projects/STM32-project-template/Core/Src/main.c 16 | SourceFolderListSize=1 17 | SourcePath#0=/home/matej/Privat_projects/STM32-project-template/Core/Src 18 | SourceFiles=; 19 | 20 | [PreviousLibFiles] 21 | LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_gcc.h; 22 | 23 | [PreviousUsedMakefileFiles] 24 | SourceFiles=../Core/Src/main.c;../Core/Src/gpio.c;../Core/Src/stm32f4xx_it.c;../Core/Src/stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../Core/Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../Core/Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; 25 | HeaderPath=../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../Core/Inc; 26 | CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; 27 | 28 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # STM32 Minimal CMake project for C/C++ projects 2 | cmake_minimum_required(VERSION 3.12) 3 | ############################################################################### 4 | # Set project name and source code folder location 5 | project(sample-f407vg) 6 | set(PROJECT_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Project) 7 | 8 | option(DUMP_ASM "Create full assembly of final executable" OFF) 9 | 10 | # Set microcontroller information 11 | set(MCU_FAMILY STM32F4xx) 12 | set(MCU_MODEL STM32F407xx) 13 | set(CPU_PARAMETERS 14 | -mcpu=cortex-m4 15 | -mthumb 16 | -mfpu=fpv4-sp-d16 17 | -mfloat-abi=hard) 18 | 19 | set(STARTUP_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/CubeMX/startup_stm32f407xx.s) 20 | set(MCU_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/CubeMX/STM32F407VGTx_FLASH.ld) 21 | 22 | ############################################################################### 23 | set(EXECUTABLE ${CMAKE_PROJECT_NAME}) 24 | 25 | enable_language(C CXX ASM) 26 | set(CMAKE_C_STANDARD 11) 27 | set(CMAKE_C_STANDARD_REQUIRED ON) 28 | set(CMAKE_C_EXTENSIONS ON) 29 | set(CMAKE_CXX_STANDARD 20) 30 | set(CMAKE_CXX_STANDARD_REQUIRED ON) 31 | set(CMAKE_CXX_EXTENSIONS ON) 32 | 33 | ############################################################################### 34 | set(STM32CUBEMX_INCLUDE_DIRECTORIES 35 | ${CMAKE_CURRENT_SOURCE_DIR}/Core/Inc 36 | ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/${MCU_FAMILY}_HAL_Driver/Inc 37 | ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/${MCU_FAMILY}_HAL_Driver/Inc/Legacy 38 | ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/CMSIS/Device/ST/${MCU_FAMILY}/Include 39 | ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/CMSIS/Include) 40 | 41 | set(PROJECT_INCLUDE_DIRECTORIES ${CMAKE_CURRENT_SOURCE_DIR}) 42 | 43 | file(GLOB_RECURSE STM32CUBEMX_SOURCES CONFIGURE_DEPENDS 44 | ${CMAKE_CURRENT_SOURCE_DIR}/Core/*.c 45 | ${CMAKE_CURRENT_SOURCE_DIR}/Drivers/*.c) 46 | 47 | file(GLOB_RECURSE PROJECT_SOURCES CONFIGURE_DEPENDS 48 | ${PROJECT_DIR}/*.cpp 49 | ${PROJECT_DIR}/*.c) 50 | 51 | add_executable(${EXECUTABLE} 52 | ${STM32CUBEMX_SOURCES} 53 | ${PROJECT_SOURCES} 54 | ${STARTUP_SCRIPT}) 55 | 56 | target_compile_definitions(${EXECUTABLE} PRIVATE 57 | #$<$:DEBUG> 58 | ${MCU_MODEL} 59 | USE_HAL_DRIVER) 60 | 61 | target_include_directories(${EXECUTABLE} SYSTEM PRIVATE 62 | ${STM32CUBEMX_INCLUDE_DIRECTORIES}) 63 | 64 | target_include_directories(${EXECUTABLE} PRIVATE 65 | ${PROJECT_INCLUDE_DIRECTORIES}) 66 | ############################################################################### 67 | target_compile_options(${EXECUTABLE} PRIVATE 68 | ${CPU_PARAMETERS} 69 | -Wall 70 | -Wextra 71 | -Wpedantic 72 | -Wshadow 73 | -Wdouble-promotion 74 | -Wformat=2 -Wformat-truncation 75 | -Wundef 76 | -fno-common 77 | -Wno-unused-parameter 78 | $<$: 79 | -Wconversion # STM libraries! 80 | -Wno-volatile 81 | -Wold-style-cast 82 | -Wuseless-cast 83 | -Wsuggest-override> 84 | $<$:-Og -g3 -ggdb> 85 | $<$:-Og -g0>) 86 | 87 | target_link_options(${EXECUTABLE} PRIVATE 88 | -T${MCU_LINKER_SCRIPT} 89 | ${CPU_PARAMETERS} 90 | -Wl,-Map=${CMAKE_PROJECT_NAME}.map 91 | --specs=nosys.specs 92 | -Wl,--start-group 93 | -lc 94 | -lm 95 | -lstdc++ 96 | -Wl,--end-group 97 | -Wl,--print-memory-usage) 98 | 99 | # The last command can take a couple of seconds on larger project, usefull for debugging 100 | add_custom_command(TARGET ${EXECUTABLE} POST_BUILD 101 | COMMAND ${CMAKE_SIZE} $ 102 | COMMAND ${CMAKE_OBJCOPY} -O ihex $ ${EXECUTABLE}.hex 103 | COMMAND ${CMAKE_OBJCOPY} -O binary $ ${EXECUTABLE}.bin) 104 | 105 | if (${DUMP_ASM}) 106 | add_custom_command(TARGET ${EXECUTABLE} POST_BUILD 107 | COMMAND ${CMAKE_OBJDUMP} -D $ > ${EXECUTABLE}.s) 108 | endif() 109 | -------------------------------------------------------------------------------- /Core/Inc/gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file gpio.h 4 | * @brief This file contains all the function prototypes for 5 | * the gpio.c file 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __GPIO_H__ 21 | #define __GPIO_H__ 22 | 23 | #ifdef __cplusplus 24 | extern "C" 25 | { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "main.h" 30 | 31 | /* USER CODE BEGIN Includes */ 32 | 33 | /* USER CODE END Includes */ 34 | 35 | /* USER CODE BEGIN Private defines */ 36 | 37 | /* USER CODE END Private defines */ 38 | 39 | void MX_GPIO_Init(void); 40 | 41 | /* USER CODE BEGIN Prototypes */ 42 | 43 | /* USER CODE END Prototypes */ 44 | 45 | #ifdef __cplusplus 46 | } 47 | #endif 48 | #endif /*__ GPIO_H__ */ 49 | 50 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 51 | -------------------------------------------------------------------------------- /Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MAIN_H 24 | #define __MAIN_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" 28 | { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f4xx_hal.h" 33 | 34 | /* Private includes ----------------------------------------------------------*/ 35 | /* USER CODE BEGIN Includes */ 36 | 37 | /* USER CODE END Includes */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* USER CODE BEGIN ET */ 41 | 42 | /* USER CODE END ET */ 43 | 44 | /* Exported constants --------------------------------------------------------*/ 45 | /* USER CODE BEGIN EC */ 46 | 47 | /* USER CODE END EC */ 48 | 49 | /* Exported macro ------------------------------------------------------------*/ 50 | /* USER CODE BEGIN EM */ 51 | 52 | /* USER CODE END EM */ 53 | 54 | /* Exported functions prototypes ---------------------------------------------*/ 55 | void Error_Handler(void); 56 | 57 | /* USER CODE BEGIN EFP */ 58 | 59 | /* USER CODE END EFP */ 60 | 61 | /* Private defines -----------------------------------------------------------*/ 62 | /* USER CODE BEGIN Private defines */ 63 | 64 | /* USER CODE END Private defines */ 65 | 66 | #ifdef __cplusplus 67 | } 68 | #endif 69 | 70 | #endif /* __MAIN_H */ 71 | 72 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 73 | -------------------------------------------------------------------------------- /Core/Inc/stm32f4xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f4xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F4xx_IT_H 23 | #define __STM32F4xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" 27 | { 28 | #endif 29 | 30 | /* Private includes ----------------------------------------------------------*/ 31 | /* USER CODE BEGIN Includes */ 32 | 33 | /* USER CODE END Includes */ 34 | 35 | /* Exported types ------------------------------------------------------------*/ 36 | /* USER CODE BEGIN ET */ 37 | 38 | /* USER CODE END ET */ 39 | 40 | /* Exported constants --------------------------------------------------------*/ 41 | /* USER CODE BEGIN EC */ 42 | 43 | /* USER CODE END EC */ 44 | 45 | /* Exported macro ------------------------------------------------------------*/ 46 | /* USER CODE BEGIN EM */ 47 | 48 | /* USER CODE END EM */ 49 | 50 | /* Exported functions prototypes ---------------------------------------------*/ 51 | void NMI_Handler(void); 52 | void HardFault_Handler(void); 53 | void MemManage_Handler(void); 54 | void BusFault_Handler(void); 55 | void UsageFault_Handler(void); 56 | void SVC_Handler(void); 57 | void DebugMon_Handler(void); 58 | void PendSV_Handler(void); 59 | void SysTick_Handler(void); 60 | /* USER CODE BEGIN EFP */ 61 | 62 | /* USER CODE END EFP */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32F4xx_IT_H */ 69 | 70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 71 | -------------------------------------------------------------------------------- /Core/Src/gpio.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file gpio.c 4 | * @brief This file provides code for the configuration 5 | * of all used GPIO pins. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "gpio.h" 22 | 23 | /* USER CODE BEGIN 0 */ 24 | 25 | /* USER CODE END 0 */ 26 | 27 | /*----------------------------------------------------------------------------*/ 28 | /* Configure GPIO */ 29 | /*----------------------------------------------------------------------------*/ 30 | /* USER CODE BEGIN 1 */ 31 | 32 | /* USER CODE END 1 */ 33 | 34 | /** Configure pins as 35 | * Analog 36 | * Input 37 | * Output 38 | * EVENT_OUT 39 | * EXTI 40 | */ 41 | void MX_GPIO_Init(void) 42 | { 43 | 44 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 45 | 46 | /* GPIO Ports Clock Enable */ 47 | __HAL_RCC_GPIOH_CLK_ENABLE(); 48 | __HAL_RCC_GPIOD_CLK_ENABLE(); 49 | 50 | /*Configure GPIO pin Output Level */ 51 | HAL_GPIO_WritePin(GPIOD, GPIO_PIN_15, GPIO_PIN_RESET); 52 | 53 | /*Configure GPIO pin : PD15 */ 54 | GPIO_InitStruct.Pin = GPIO_PIN_15; 55 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 56 | GPIO_InitStruct.Pull = GPIO_NOPULL; 57 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 58 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 59 | } 60 | 61 | /* USER CODE BEGIN 2 */ 62 | 63 | /* USER CODE END 2 */ 64 | 65 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 66 | -------------------------------------------------------------------------------- /Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "gpio.h" 23 | 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | #include 27 | /* USER CODE END Includes */ 28 | 29 | /* Private typedef -----------------------------------------------------------*/ 30 | /* USER CODE BEGIN PTD */ 31 | 32 | /* USER CODE END PTD */ 33 | 34 | /* Private define ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN PD */ 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | 45 | /* USER CODE BEGIN PV */ 46 | 47 | /* USER CODE END PV */ 48 | 49 | /* Private function prototypes -----------------------------------------------*/ 50 | void SystemClock_Config(void); 51 | /* USER CODE BEGIN PFP */ 52 | 53 | /* USER CODE END PFP */ 54 | 55 | /* Private user code ---------------------------------------------------------*/ 56 | /* USER CODE BEGIN 0 */ 57 | 58 | /* USER CODE END 0 */ 59 | 60 | /** 61 | * @brief The application entry point. 62 | * @retval int 63 | */ 64 | int main(void) 65 | { 66 | /* USER CODE BEGIN 1 */ 67 | 68 | /* USER CODE END 1 */ 69 | 70 | /* MCU Configuration--------------------------------------------------------*/ 71 | 72 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 73 | HAL_Init(); 74 | 75 | /* USER CODE BEGIN Init */ 76 | 77 | /* USER CODE END Init */ 78 | 79 | /* Configure the system clock */ 80 | SystemClock_Config(); 81 | 82 | /* USER CODE BEGIN SysInit */ 83 | 84 | /* USER CODE END SysInit */ 85 | 86 | /* Initialize all configured peripherals */ 87 | MX_GPIO_Init(); 88 | /* USER CODE BEGIN 2 */ 89 | projectMain(); 90 | /* USER CODE END 2 */ 91 | 92 | /* Infinite loop */ 93 | /* USER CODE BEGIN WHILE */ 94 | while (1) 95 | { 96 | /* USER CODE END WHILE */ 97 | 98 | /* USER CODE BEGIN 3 */ 99 | } 100 | /* USER CODE END 3 */ 101 | } 102 | 103 | /** 104 | * @brief System Clock Configuration 105 | * @retval None 106 | */ 107 | void SystemClock_Config(void) 108 | { 109 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 110 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 111 | 112 | /** Configure the main internal regulator output voltage 113 | */ 114 | __HAL_RCC_PWR_CLK_ENABLE(); 115 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 116 | /** Initializes the RCC Oscillators according to the specified parameters 117 | * in the RCC_OscInitTypeDef structure. 118 | */ 119 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 120 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; 121 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 122 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 123 | RCC_OscInitStruct.PLL.PLLM = 4; 124 | RCC_OscInitStruct.PLL.PLLN = 168; 125 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 126 | RCC_OscInitStruct.PLL.PLLQ = 4; 127 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 128 | { 129 | Error_Handler(); 130 | } 131 | /** Initializes the CPU, AHB and APB buses clocks 132 | */ 133 | RCC_ClkInitStruct.ClockType = 134 | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 135 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 136 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 137 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 138 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; 139 | 140 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 141 | { 142 | Error_Handler(); 143 | } 144 | } 145 | 146 | /* USER CODE BEGIN 4 */ 147 | 148 | /* USER CODE END 4 */ 149 | 150 | /** 151 | * @brief This function is executed in case of error occurrence. 152 | * @retval None 153 | */ 154 | void Error_Handler(void) 155 | { 156 | /* USER CODE BEGIN Error_Handler_Debug */ 157 | /* User can add his own implementation to report the HAL error return state */ 158 | __disable_irq(); 159 | while (1) 160 | { 161 | } 162 | /* USER CODE END Error_Handler_Debug */ 163 | } 164 | 165 | #ifdef USE_FULL_ASSERT 166 | /** 167 | * @brief Reports the name of the source file and the source line number 168 | * where the assert_param error has occurred. 169 | * @param file: pointer to the source file name 170 | * @param line: assert_param error line source number 171 | * @retval None 172 | */ 173 | void assert_failed(uint8_t* file, uint32_t line) 174 | { 175 | /* USER CODE BEGIN 6 */ 176 | /* User can add his own implementation to report the file name and line number, 177 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 178 | /* USER CODE END 6 */ 179 | } 180 | #endif /* USE_FULL_ASSERT */ 181 | 182 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 183 | -------------------------------------------------------------------------------- /Core/Src/stm32f4xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f4xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 71 | __HAL_RCC_PWR_CLK_ENABLE(); 72 | 73 | /* System interrupt init*/ 74 | 75 | /* USER CODE BEGIN MspInit 1 */ 76 | 77 | /* USER CODE END MspInit 1 */ 78 | } 79 | 80 | /* USER CODE BEGIN 1 */ 81 | 82 | /* USER CODE END 1 */ 83 | 84 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 85 | -------------------------------------------------------------------------------- /Core/Src/stm32f4xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f4xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f4xx_it.h" 23 | #include "main.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* Private user code ---------------------------------------------------------*/ 54 | /* USER CODE BEGIN 0 */ 55 | 56 | /* USER CODE END 0 */ 57 | 58 | /* External variables --------------------------------------------------------*/ 59 | 60 | /* USER CODE BEGIN EV */ 61 | 62 | /* USER CODE END EV */ 63 | 64 | /******************************************************************************/ 65 | /* Cortex-M4 Processor Interruption and Exception Handlers */ 66 | /******************************************************************************/ 67 | /** 68 | * @brief This function handles Non maskable interrupt. 69 | */ 70 | void NMI_Handler(void) 71 | { 72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 73 | 74 | /* USER CODE END NonMaskableInt_IRQn 0 */ 75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 76 | while (1) 77 | { 78 | } 79 | /* USER CODE END NonMaskableInt_IRQn 1 */ 80 | } 81 | 82 | /** 83 | * @brief This function handles Hard fault interrupt. 84 | */ 85 | void HardFault_Handler(void) 86 | { 87 | /* USER CODE BEGIN HardFault_IRQn 0 */ 88 | 89 | /* USER CODE END HardFault_IRQn 0 */ 90 | while (1) 91 | { 92 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 93 | /* USER CODE END W1_HardFault_IRQn 0 */ 94 | } 95 | } 96 | 97 | /** 98 | * @brief This function handles Memory management fault. 99 | */ 100 | void MemManage_Handler(void) 101 | { 102 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 103 | 104 | /* USER CODE END MemoryManagement_IRQn 0 */ 105 | while (1) 106 | { 107 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 108 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 109 | } 110 | } 111 | 112 | /** 113 | * @brief This function handles Pre-fetch fault, memory access fault. 114 | */ 115 | void BusFault_Handler(void) 116 | { 117 | /* USER CODE BEGIN BusFault_IRQn 0 */ 118 | 119 | /* USER CODE END BusFault_IRQn 0 */ 120 | while (1) 121 | { 122 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 123 | /* USER CODE END W1_BusFault_IRQn 0 */ 124 | } 125 | } 126 | 127 | /** 128 | * @brief This function handles Undefined instruction or illegal state. 129 | */ 130 | void UsageFault_Handler(void) 131 | { 132 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 133 | 134 | /* USER CODE END UsageFault_IRQn 0 */ 135 | while (1) 136 | { 137 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 138 | /* USER CODE END W1_UsageFault_IRQn 0 */ 139 | } 140 | } 141 | 142 | /** 143 | * @brief This function handles System service call via SWI instruction. 144 | */ 145 | void SVC_Handler(void) 146 | { 147 | /* USER CODE BEGIN SVCall_IRQn 0 */ 148 | 149 | /* USER CODE END SVCall_IRQn 0 */ 150 | /* USER CODE BEGIN SVCall_IRQn 1 */ 151 | 152 | /* USER CODE END SVCall_IRQn 1 */ 153 | } 154 | 155 | /** 156 | * @brief This function handles Debug monitor. 157 | */ 158 | void DebugMon_Handler(void) 159 | { 160 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 161 | 162 | /* USER CODE END DebugMonitor_IRQn 0 */ 163 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 164 | 165 | /* USER CODE END DebugMonitor_IRQn 1 */ 166 | } 167 | 168 | /** 169 | * @brief This function handles Pendable request for system service. 170 | */ 171 | void PendSV_Handler(void) 172 | { 173 | /* USER CODE BEGIN PendSV_IRQn 0 */ 174 | 175 | /* USER CODE END PendSV_IRQn 0 */ 176 | /* USER CODE BEGIN PendSV_IRQn 1 */ 177 | 178 | /* USER CODE END PendSV_IRQn 1 */ 179 | } 180 | 181 | /** 182 | * @brief This function handles System tick timer. 183 | */ 184 | void SysTick_Handler(void) 185 | { 186 | /* USER CODE BEGIN SysTick_IRQn 0 */ 187 | 188 | /* USER CODE END SysTick_IRQn 0 */ 189 | HAL_IncTick(); 190 | /* USER CODE BEGIN SysTick_IRQn 1 */ 191 | 192 | /* USER CODE END SysTick_IRQn 1 */ 193 | } 194 | 195 | /******************************************************************************/ 196 | /* STM32F4xx Peripheral Interrupt Handlers */ 197 | /* Add here the Interrupt Handlers for the used peripherals. */ 198 | /* For the available peripheral interrupt handler names, */ 199 | /* please refer to the startup file (startup_stm32f4xx.s). */ 200 | /******************************************************************************/ 201 | 202 | /* USER CODE BEGIN 1 */ 203 | 204 | /* USER CODE END 1 */ 205 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 206 | -------------------------------------------------------------------------------- /CubeMX/Makefile: -------------------------------------------------------------------------------- 1 | ########################################################################################################################## 2 | # File automatically-generated by tool: [projectgenerator] version: [3.13.0-B3] date: [Fri Dec 31 18:51:48 CET 2021] 3 | ########################################################################################################################## 4 | 5 | # ------------------------------------------------ 6 | # Generic Makefile (based on gcc) 7 | # 8 | # ChangeLog : 9 | # 2017-02-10 - Several enhancements + project update mode 10 | # 2015-07-22 - first version 11 | # ------------------------------------------------ 12 | 13 | ###################################### 14 | # target 15 | ###################################### 16 | TARGET = STM32-project-template 17 | 18 | 19 | ###################################### 20 | # building variables 21 | ###################################### 22 | # debug build? 23 | DEBUG = 1 24 | # optimization 25 | OPT = -Og 26 | 27 | 28 | ####################################### 29 | # paths 30 | ####################################### 31 | # Build path 32 | BUILD_DIR = build 33 | 34 | ###################################### 35 | # source 36 | ###################################### 37 | # C sources 38 | C_SOURCES = \ 39 | ../Core/Src/main.c \ 40 | ../Core/Src/gpio.c \ 41 | ../Core/Src/stm32f4xx_it.c \ 42 | ../Core/Src/stm32f4xx_hal_msp.c \ 43 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ 44 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ 45 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ 46 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ 47 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ 48 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ 49 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ 50 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ 51 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ 52 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ 53 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ 54 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ 55 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ 56 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ 57 | ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ 58 | ../Core/Src/system_stm32f4xx.c 59 | 60 | # ASM sources 61 | ASM_SOURCES = \ 62 | startup_stm32f407xx.s 63 | 64 | 65 | ####################################### 66 | # binaries 67 | ####################################### 68 | PREFIX = arm-none-eabi- 69 | # The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) 70 | # either it can be added to the PATH environment variable. 71 | ifdef GCC_PATH 72 | CC = $(GCC_PATH)/$(PREFIX)gcc 73 | AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp 74 | CP = $(GCC_PATH)/$(PREFIX)objcopy 75 | SZ = $(GCC_PATH)/$(PREFIX)size 76 | else 77 | CC = $(PREFIX)gcc 78 | AS = $(PREFIX)gcc -x assembler-with-cpp 79 | CP = $(PREFIX)objcopy 80 | SZ = $(PREFIX)size 81 | endif 82 | HEX = $(CP) -O ihex 83 | BIN = $(CP) -O binary -S 84 | 85 | ####################################### 86 | # CFLAGS 87 | ####################################### 88 | # cpu 89 | CPU = -mcpu=cortex-m4 90 | 91 | # fpu 92 | FPU = -mfpu=fpv4-sp-d16 93 | 94 | # float-abi 95 | FLOAT-ABI = -mfloat-abi=hard 96 | 97 | # mcu 98 | MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) 99 | 100 | # macros for gcc 101 | # AS defines 102 | AS_DEFS = 103 | 104 | # C defines 105 | C_DEFS = \ 106 | -DUSE_HAL_DRIVER \ 107 | -DSTM32F407xx 108 | 109 | 110 | # AS includes 111 | AS_INCLUDES = 112 | 113 | # C includes 114 | C_INCLUDES = \ 115 | -I../Core/Inc \ 116 | -I../Drivers/STM32F4xx_HAL_Driver/Inc \ 117 | -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy \ 118 | -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include \ 119 | -I../Drivers/CMSIS/Include 120 | 121 | 122 | # compile gcc flags 123 | ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 124 | 125 | CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 126 | 127 | ifeq ($(DEBUG), 1) 128 | CFLAGS += -g -gdwarf-2 129 | endif 130 | 131 | 132 | # Generate dependency information 133 | CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" 134 | 135 | 136 | ####################################### 137 | # LDFLAGS 138 | ####################################### 139 | # link script 140 | LDSCRIPT = STM32F407VGTx_FLASH.ld 141 | 142 | # libraries 143 | LIBS = -lc -lm -lnosys 144 | LIBDIR = 145 | LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections 146 | 147 | # default action: build all 148 | all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin 149 | 150 | 151 | ####################################### 152 | # build the application 153 | ####################################### 154 | # list of objects 155 | OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) 156 | vpath %.c $(sort $(dir $(C_SOURCES))) 157 | # list of ASM program objects 158 | OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) 159 | vpath %.s $(sort $(dir $(ASM_SOURCES))) 160 | 161 | $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 162 | $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ 163 | 164 | $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) 165 | $(AS) -c $(CFLAGS) $< -o $@ 166 | 167 | $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile 168 | $(CC) $(OBJECTS) $(LDFLAGS) -o $@ 169 | $(SZ) $@ 170 | 171 | $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 172 | $(HEX) $< $@ 173 | 174 | $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 175 | $(BIN) $< $@ 176 | 177 | $(BUILD_DIR): 178 | mkdir $@ 179 | 180 | ####################################### 181 | # clean up 182 | ####################################### 183 | clean: 184 | -rm -fR $(BUILD_DIR) 185 | 186 | ####################################### 187 | # dependencies 188 | ####################################### 189 | -include $(wildcard $(BUILD_DIR)/*.d) 190 | 191 | # *** EOF *** -------------------------------------------------------------------------------- /CubeMX/STM32F407VGTx_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** Author : Auto-generated by System Workbench for STM32 8 | ** 9 | ** Abstract : Linker script for STM32F407VGTx series 10 | ** 1024Kbytes FLASH and 192Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used. 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed “as is,” without any warranty 20 | ** of any kind. 21 | ** 22 | ***************************************************************************** 23 | ** @attention 24 | ** 25 | **

© COPYRIGHT(c) 2019 STMicroelectronics

26 | ** 27 | ** Redistribution and use in source and binary forms, with or without modification, 28 | ** are permitted provided that the following conditions are met: 29 | ** 1. Redistributions of source code must retain the above copyright notice, 30 | ** this list of conditions and the following disclaimer. 31 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 32 | ** this list of conditions and the following disclaimer in the documentation 33 | ** and/or other materials provided with the distribution. 34 | ** 3. Neither the name of STMicroelectronics nor the names of its contributors 35 | ** may be used to endorse or promote products derived from this software 36 | ** without specific prior written permission. 37 | ** 38 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | ** 49 | ***************************************************************************** 50 | */ 51 | 52 | /* Entry Point */ 53 | ENTRY(Reset_Handler) 54 | 55 | /* Highest address of the user mode stack */ 56 | _estack = 0x20020000; /* end of RAM */ 57 | /* Generate a link error if heap and stack don't fit into RAM */ 58 | _Min_Heap_Size = 0x200; /* required amount of heap */ 59 | _Min_Stack_Size = 0x400; /* required amount of stack */ 60 | 61 | /* Specify the memory areas */ 62 | MEMORY 63 | { 64 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K 65 | CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K 66 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K 67 | } 68 | 69 | /* Define output sections */ 70 | SECTIONS 71 | { 72 | /* The startup code goes first into FLASH */ 73 | .isr_vector : 74 | { 75 | . = ALIGN(4); 76 | KEEP(*(.isr_vector)) /* Startup code */ 77 | . = ALIGN(4); 78 | } >FLASH 79 | 80 | /* The program code and other data goes into FLASH */ 81 | .text : 82 | { 83 | . = ALIGN(4); 84 | *(.text) /* .text sections (code) */ 85 | *(.text*) /* .text* sections (code) */ 86 | *(.glue_7) /* glue arm to thumb code */ 87 | *(.glue_7t) /* glue thumb to arm code */ 88 | *(.eh_frame) 89 | 90 | KEEP (*(.init)) 91 | KEEP (*(.fini)) 92 | 93 | . = ALIGN(4); 94 | _etext = .; /* define a global symbols at end of code */ 95 | } >FLASH 96 | 97 | /* Constant data goes into FLASH */ 98 | .rodata : 99 | { 100 | . = ALIGN(4); 101 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 102 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 103 | . = ALIGN(4); 104 | } >FLASH 105 | 106 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 107 | .ARM : { 108 | __exidx_start = .; 109 | *(.ARM.exidx*) 110 | __exidx_end = .; 111 | } >FLASH 112 | 113 | .preinit_array : 114 | { 115 | PROVIDE_HIDDEN (__preinit_array_start = .); 116 | KEEP (*(.preinit_array*)) 117 | PROVIDE_HIDDEN (__preinit_array_end = .); 118 | } >FLASH 119 | .init_array : 120 | { 121 | PROVIDE_HIDDEN (__init_array_start = .); 122 | KEEP (*(SORT(.init_array.*))) 123 | KEEP (*(.init_array*)) 124 | PROVIDE_HIDDEN (__init_array_end = .); 125 | } >FLASH 126 | .fini_array : 127 | { 128 | PROVIDE_HIDDEN (__fini_array_start = .); 129 | KEEP (*(SORT(.fini_array.*))) 130 | KEEP (*(.fini_array*)) 131 | PROVIDE_HIDDEN (__fini_array_end = .); 132 | } >FLASH 133 | 134 | /* used by the startup to initialize data */ 135 | _sidata = LOADADDR(.data); 136 | 137 | /* Initialized data sections goes into RAM, load LMA copy after code */ 138 | .data : 139 | { 140 | . = ALIGN(4); 141 | _sdata = .; /* create a global symbol at data start */ 142 | *(.data) /* .data sections */ 143 | *(.data*) /* .data* sections */ 144 | 145 | . = ALIGN(4); 146 | _edata = .; /* define a global symbol at data end */ 147 | } >RAM AT> FLASH 148 | 149 | _siccmram = LOADADDR(.ccmram); 150 | 151 | /* CCM-RAM section 152 | * 153 | * IMPORTANT NOTE! 154 | * If initialized variables will be placed in this section, 155 | * the startup code needs to be modified to copy the init-values. 156 | */ 157 | .ccmram : 158 | { 159 | . = ALIGN(4); 160 | _sccmram = .; /* create a global symbol at ccmram start */ 161 | *(.ccmram) 162 | *(.ccmram*) 163 | 164 | . = ALIGN(4); 165 | _eccmram = .; /* create a global symbol at ccmram end */ 166 | } >CCMRAM AT> FLASH 167 | 168 | 169 | /* Uninitialized data section */ 170 | . = ALIGN(4); 171 | .bss : 172 | { 173 | /* This is used by the startup in order to initialize the .bss secion */ 174 | _sbss = .; /* define a global symbol at bss start */ 175 | __bss_start__ = _sbss; 176 | *(.bss) 177 | *(.bss*) 178 | *(COMMON) 179 | 180 | . = ALIGN(4); 181 | _ebss = .; /* define a global symbol at bss end */ 182 | __bss_end__ = _ebss; 183 | } >RAM 184 | 185 | /* User_heap_stack section, used to check that there is enough RAM left */ 186 | ._user_heap_stack : 187 | { 188 | . = ALIGN(8); 189 | PROVIDE ( end = . ); 190 | PROVIDE ( _end = . ); 191 | . = . + _Min_Heap_Size; 192 | . = . + _Min_Stack_Size; 193 | . = ALIGN(8); 194 | } >RAM 195 | 196 | 197 | 198 | /* Remove information from the standard libraries */ 199 | /DISCARD/ : 200 | { 201 | libc.a ( * ) 202 | libm.a ( * ) 203 | libgcc.a ( * ) 204 | } 205 | 206 | .ARM.attributes 0 : { *(.ARM.attributes) } 207 | } 208 | 209 | 210 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/prtzl/stm32-cmake/b5eccbd7b75b69295aabea992b956076c63f2888/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© COPYRIGHT(c) 2017 STMicroelectronics

10 | * 11 | * Redistribution and use in source and binary forms, with or without modification, 12 | * are permitted provided that the following conditions are met: 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 | * may be used to endorse or promote products derived from this software 20 | * without specific prior written permission. 21 | * 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 | * 33 | ****************************************************************************** 34 | */ 35 | 36 | /** @addtogroup CMSIS 37 | * @{ 38 | */ 39 | 40 | /** @addtogroup stm32f4xx_system 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief Define to prevent recursive inclusion 46 | */ 47 | #ifndef __SYSTEM_STM32F4XX_H 48 | #define __SYSTEM_STM32F4XX_H 49 | 50 | #ifdef __cplusplus 51 | extern "C" 52 | { 53 | #endif 54 | 55 | /** @addtogroup STM32F4xx_System_Includes 56 | * @{ 57 | */ 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /** @addtogroup STM32F4xx_System_Exported_types 64 | * @{ 65 | */ 66 | /* This variable is updated in three ways: 67 | 1) by calling CMSIS function SystemCoreClockUpdate() 68 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 69 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 70 | Note: If you use this function to configure the system clock; then there 71 | is no need to call the 2 first functions listed above, since SystemCoreClock 72 | variable is updated automatically. 73 | */ 74 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 75 | 76 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 77 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @addtogroup STM32F4xx_System_Exported_Constants 84 | * @{ 85 | */ 86 | 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @addtogroup STM32F4xx_System_Exported_Macros 92 | * @{ 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @addtogroup STM32F4xx_System_Exported_Functions 100 | * @{ 101 | */ 102 | 103 | extern void SystemInit(void); 104 | extern void SystemCoreClockUpdate(void); 105 | /** 106 | * @} 107 | */ 108 | 109 | #ifdef __cplusplus 110 | } 111 | #endif 112 | 113 | #endif /*__SYSTEM_STM32F4XX_H */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /** 120 | * @} 121 | */ 122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 123 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************/ /** 2 | * @file 3 | *cmsis_compiler.h 4 | * @brief CMSIS 5 | *compiler generic 6 | *header file 7 | * @version V5.0.4 8 | * @date 10. 9 | *January 2018 10 | ******************************************************************************/ 11 | /* 12 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 13 | * 14 | * SPDX-License-Identifier: Apache-2.0 15 | * 16 | * Licensed under the Apache License, Version 2.0 (the License); you may 17 | * not use this file except in compliance with the License. 18 | * You may obtain a copy of the License at 19 | * 20 | * www.apache.org/licenses/LICENSE-2.0 21 | * 22 | * Unless required by applicable law or agreed to in writing, software 23 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | * See the License for the specific language governing permissions and 26 | * limitations under the License. 27 | */ 28 | 29 | #ifndef __CMSIS_COMPILER_H 30 | #define __CMSIS_COMPILER_H 31 | 32 | #include 33 | 34 | /* 35 | * Arm Compiler 4/5 36 | */ 37 | #if defined(__CC_ARM) 38 | #include "cmsis_armcc.h" 39 | 40 | /* 41 | * Arm Compiler 6 (armclang) 42 | */ 43 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 44 | #include "cmsis_armclang.h" 45 | 46 | /* 47 | * GNU Compiler 48 | */ 49 | #elif defined(__GNUC__) 50 | #include "cmsis_gcc.h" 51 | 52 | /* 53 | * IAR Compiler 54 | */ 55 | #elif defined(__ICCARM__) 56 | #include 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined(__TI_ARM__) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 96 | { 97 | uint32_t v; 98 | }; 99 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32*)(x))->v) 100 | #endif 101 | #ifndef __UNALIGNED_UINT16_WRITE 102 | __PACKED_STRUCT T_UINT16_WRITE 103 | { 104 | uint16_t v; 105 | }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) \ 107 | (void)((((struct T_UINT16_WRITE*)(void*)(addr))->v) = (val)) 108 | #endif 109 | #ifndef __UNALIGNED_UINT16_READ 110 | __PACKED_STRUCT T_UINT16_READ 111 | { 112 | uint16_t v; 113 | }; 114 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ*)(const void*)(addr))->v) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_WRITE 117 | __PACKED_STRUCT T_UINT32_WRITE 118 | { 119 | uint32_t v; 120 | }; 121 | #define __UNALIGNED_UINT32_WRITE(addr, val) \ 122 | (void)((((struct T_UINT32_WRITE*)(void*)(addr))->v) = (val)) 123 | #endif 124 | #ifndef __UNALIGNED_UINT32_READ 125 | __PACKED_STRUCT T_UINT32_READ 126 | { 127 | uint32_t v; 128 | }; 129 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ*)(const void*)(addr))->v) 130 | #endif 131 | #ifndef __ALIGNED 132 | #define __ALIGNED(x) __attribute__((aligned(x))) 133 | #endif 134 | #ifndef __RESTRICT 135 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 136 | #define __RESTRICT 137 | #endif 138 | 139 | /* 140 | * TASKING Compiler 141 | */ 142 | #elif defined(__TASKING__) 143 | /* 144 | * The CMSIS functions have been implemented as intrinsics in the compiler. 145 | * Please use "carm -?i" to get an up to date list of all intrinsics, 146 | * Including the CMSIS ones. 147 | */ 148 | 149 | #ifndef __ASM 150 | #define __ASM __asm 151 | #endif 152 | #ifndef __INLINE 153 | #define __INLINE inline 154 | #endif 155 | #ifndef __STATIC_INLINE 156 | #define __STATIC_INLINE static inline 157 | #endif 158 | #ifndef __STATIC_FORCEINLINE 159 | #define __STATIC_FORCEINLINE __STATIC_INLINE 160 | #endif 161 | #ifndef __NO_RETURN 162 | #define __NO_RETURN __attribute__((noreturn)) 163 | #endif 164 | #ifndef __USED 165 | #define __USED __attribute__((used)) 166 | #endif 167 | #ifndef __WEAK 168 | #define __WEAK __attribute__((weak)) 169 | #endif 170 | #ifndef __PACKED 171 | #define __PACKED __packed__ 172 | #endif 173 | #ifndef __PACKED_STRUCT 174 | #define __PACKED_STRUCT struct __packed__ 175 | #endif 176 | #ifndef __PACKED_UNION 177 | #define __PACKED_UNION union __packed__ 178 | #endif 179 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 180 | struct __packed__ T_UINT32 181 | { 182 | uint32_t v; 183 | }; 184 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32*)(x))->v) 185 | #endif 186 | #ifndef __UNALIGNED_UINT16_WRITE 187 | __PACKED_STRUCT T_UINT16_WRITE 188 | { 189 | uint16_t v; 190 | }; 191 | #define __UNALIGNED_UINT16_WRITE(addr, val) \ 192 | (void)((((struct T_UINT16_WRITE*)(void*)(addr))->v) = (val)) 193 | #endif 194 | #ifndef __UNALIGNED_UINT16_READ 195 | __PACKED_STRUCT T_UINT16_READ 196 | { 197 | uint16_t v; 198 | }; 199 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ*)(const void*)(addr))->v) 200 | #endif 201 | #ifndef __UNALIGNED_UINT32_WRITE 202 | __PACKED_STRUCT T_UINT32_WRITE 203 | { 204 | uint32_t v; 205 | }; 206 | #define __UNALIGNED_UINT32_WRITE(addr, val) \ 207 | (void)((((struct T_UINT32_WRITE*)(void*)(addr))->v) = (val)) 208 | #endif 209 | #ifndef __UNALIGNED_UINT32_READ 210 | __PACKED_STRUCT T_UINT32_READ 211 | { 212 | uint32_t v; 213 | }; 214 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ*)(const void*)(addr))->v) 215 | #endif 216 | #ifndef __ALIGNED 217 | #define __ALIGNED(x) __align(x) 218 | #endif 219 | #ifndef __RESTRICT 220 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 221 | #define __RESTRICT 222 | #endif 223 | 224 | /* 225 | * COSMIC Compiler 226 | */ 227 | #elif defined(__CSMC__) 228 | #include 229 | 230 | #ifndef __ASM 231 | #define __ASM _asm 232 | #endif 233 | #ifndef __INLINE 234 | #define __INLINE inline 235 | #endif 236 | #ifndef __STATIC_INLINE 237 | #define __STATIC_INLINE static inline 238 | #endif 239 | #ifndef __STATIC_FORCEINLINE 240 | #define __STATIC_FORCEINLINE __STATIC_INLINE 241 | #endif 242 | #ifndef __NO_RETURN 243 | // NO RETURN is automatically detected hence no warning here 244 | #define __NO_RETURN 245 | #endif 246 | #ifndef __USED 247 | #warning No compiler specific solution for __USED. __USED is ignored. 248 | #define __USED 249 | #endif 250 | #ifndef __WEAK 251 | #define __WEAK __weak 252 | #endif 253 | #ifndef __PACKED 254 | #define __PACKED @packed 255 | #endif 256 | #ifndef __PACKED_STRUCT 257 | #define __PACKED_STRUCT @packed struct 258 | #endif 259 | #ifndef __PACKED_UNION 260 | #define __PACKED_UNION @packed union 261 | #endif 262 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 263 | @packed struct T_UINT32 264 | { 265 | uint32_t v; 266 | }; 267 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32*)(x))->v) 268 | #endif 269 | #ifndef __UNALIGNED_UINT16_WRITE 270 | __PACKED_STRUCT T_UINT16_WRITE 271 | { 272 | uint16_t v; 273 | }; 274 | #define __UNALIGNED_UINT16_WRITE(addr, val) \ 275 | (void)((((struct T_UINT16_WRITE*)(void*)(addr))->v) = (val)) 276 | #endif 277 | #ifndef __UNALIGNED_UINT16_READ 278 | __PACKED_STRUCT T_UINT16_READ 279 | { 280 | uint16_t v; 281 | }; 282 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ*)(const void*)(addr))->v) 283 | #endif 284 | #ifndef __UNALIGNED_UINT32_WRITE 285 | __PACKED_STRUCT T_UINT32_WRITE 286 | { 287 | uint32_t v; 288 | }; 289 | #define __UNALIGNED_UINT32_WRITE(addr, val) \ 290 | (void)((((struct T_UINT32_WRITE*)(void*)(addr))->v) = (val)) 291 | #endif 292 | #ifndef __UNALIGNED_UINT32_READ 293 | __PACKED_STRUCT T_UINT32_READ 294 | { 295 | uint32_t v; 296 | }; 297 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ*)(const void*)(addr))->v) 298 | #endif 299 | #ifndef __ALIGNED 300 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 301 | #define __ALIGNED(x) 302 | #endif 303 | #ifndef __RESTRICT 304 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 305 | #define __RESTRICT 306 | #endif 307 | 308 | #else 309 | #error Unknown compiler. 310 | #endif 311 | 312 | #endif /* __CMSIS_COMPILER_H */ 313 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************/ /** 2 | * @file 3 | *cmsis_version.h 4 | * @brief CMSIS 5 | *Core(M) Version 6 | *definitions 7 | * @version V5.0.2 8 | * @date 19. 9 | *April 2017 10 | ******************************************************************************/ 11 | /* 12 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 13 | * 14 | * SPDX-License-Identifier: Apache-2.0 15 | * 16 | * Licensed under the Apache License, Version 2.0 (the License); you may 17 | * not use this file except in compliance with the License. 18 | * You may obtain a copy of the License at 19 | * 20 | * www.apache.org/licenses/LICENSE-2.0 21 | * 22 | * Unless required by applicable law or agreed to in writing, software 23 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | * See the License for the specific language governing permissions and 26 | * limitations under the License. 27 | */ 28 | 29 | #if defined(__ICCARM__) 30 | #pragma system_include /* treat file as system include file for MISRA check */ 31 | #elif defined(__clang__) 32 | #pragma clang system_header /* treat file as system include file */ 33 | #endif 34 | 35 | #ifndef __CMSIS_VERSION_H 36 | #define __CMSIS_VERSION_H 37 | 38 | /* CMSIS Version definitions */ 39 | #define __CM_CMSIS_VERSION_MAIN (5U) /*!< [31:16] CMSIS Core(M) main version */ 40 | #define __CM_CMSIS_VERSION_SUB (1U) /*!< [15:0] CMSIS Core(M) sub version */ 41 | #define __CM_CMSIS_VERSION \ 42 | ((__CM_CMSIS_VERSION_MAIN << 16U) \ 43 | | __CM_CMSIS_VERSION_SUB) /*!< CMSIS Core(M) version number */ 44 | #endif 45 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined(__ICCARM__) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined(__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress)&MPU_RBAR_ADDR_Msk) | ((Region)&MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk)) 77 | 78 | /** 79 | * MPU Memory Access Attributes 80 | * 81 | * \param TypeExtField Type extension field, allows you to configure memory access type, 82 | * for example strongly ordered, peripheral. \param IsShareable Region is shareable 83 | * between multiple bus masters. \param IsCacheable Region is cacheable, i.e. its value 84 | * may be kept in cache. \param IsBufferable Region is bufferable, i.e. using write-back 85 | * caching. Cacheable but non-bufferable regions use write-through policy. 86 | */ 87 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 88 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) \ 89 | | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) \ 90 | | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) \ 91 | | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 92 | 93 | /** 94 | * MPU Region Attribute and Size Register Value 95 | * 96 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 97 | * \param AccessPermission Data access permissions, allows you to configure read/write access 98 | * for User and Privileged mode. \param AccessAttributes Memory access attribution, see \ref 99 | * ARM_MPU_ACCESS_. \param SubRegionDisable Sub-region disable field. \param Size Region size 100 | * of the region to be configured, for example 4K, 8K. 101 | */ 102 | #define ARM_MPU_RASR_EX( \ 103 | DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) \ 105 | | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) \ 106 | | (((AccessAttributes)) \ 107 | & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 108 | 109 | /** 110 | * MPU Region Attribute and Size Register Value 111 | * 112 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 113 | * \param AccessPermission Data access permissions, allows you to configure read/write access 114 | * for User and Privileged mode. \param TypeExtField Type extension field, allows you to 115 | * configure memory access type, for example strongly ordered, peripheral. \param IsShareable 116 | * Region is shareable between multiple bus masters. \param IsCacheable Region is 117 | * cacheable, i.e. its value may be kept in cache. \param IsBufferable Region is 118 | * bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use 119 | * write-through policy. \param SubRegionDisable Sub-region disable field. \param Size Region 120 | * size of the region to be configured, for example 4K, 8K. 121 | */ 122 | #define ARM_MPU_RASR( \ 123 | DisableExec, \ 124 | AccessPermission, \ 125 | TypeExtField, \ 126 | IsShareable, \ 127 | IsCacheable, \ 128 | IsBufferable, \ 129 | SubRegionDisable, \ 130 | Size) \ 131 | ARM_MPU_RASR_EX( \ 132 | DisableExec, \ 133 | AccessPermission, \ 134 | ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), \ 135 | SubRegionDisable, \ 136 | Size) 137 | 138 | /** 139 | * MPU Memory Access Attribute for strongly ordered memory. 140 | * - TEX: 000b 141 | * - Shareable 142 | * - Non-cacheable 143 | * - Non-bufferable 144 | */ 145 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 146 | 147 | /** 148 | * MPU Memory Access Attribute for device memory. 149 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 150 | * - Shareable or non-shareable 151 | * - Non-cacheable 152 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 153 | * 154 | * \param IsShareable Configures the device memory as shareable or non-shareable. 155 | */ 156 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) \ 157 | ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute for normal memory. 161 | * - TEX: 1BBb (reflecting outer cacheability rules) 162 | * - Shareable or non-shareable 163 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 164 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 165 | * 166 | * \param OuterCp Configures the outer cache policy. 167 | * \param InnerCp Configures the inner cache policy. 168 | * \param IsShareable Configures the memory as shareable or non-shareable. 169 | */ 170 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) \ 171 | ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp)&2U), ((InnerCp)&1U)) 172 | 173 | /** 174 | * MPU Memory Access Attribute non-cacheable policy. 175 | */ 176 | #define ARM_MPU_CACHEP_NOCACHE 0U 177 | 178 | /** 179 | * MPU Memory Access Attribute write-back, write and read allocate policy. 180 | */ 181 | #define ARM_MPU_CACHEP_WB_WRA 1U 182 | 183 | /** 184 | * MPU Memory Access Attribute write-through, no write allocate policy. 185 | */ 186 | #define ARM_MPU_CACHEP_WT_NWA 2U 187 | 188 | /** 189 | * MPU Memory Access Attribute write-back, no write allocate policy. 190 | */ 191 | #define ARM_MPU_CACHEP_WB_NWA 3U 192 | 193 | /** 194 | * Struct for a single MPU Region 195 | */ 196 | typedef struct 197 | { 198 | uint32_t RBAR; //!< The region base address register value (RBAR) 199 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 200 | } ARM_MPU_Region_t; 201 | 202 | /** Enable the MPU. 203 | * \param MPU_Control Default access permissions for unconfigured regions. 204 | */ 205 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 206 | { 207 | __DSB(); 208 | __ISB(); 209 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 210 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 211 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 212 | #endif 213 | } 214 | 215 | /** Disable the MPU. 216 | */ 217 | __STATIC_INLINE void ARM_MPU_Disable(void) 218 | { 219 | __DSB(); 220 | __ISB(); 221 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 222 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 223 | #endif 224 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 225 | } 226 | 227 | /** Clear and disable the given MPU region. 228 | * \param rnr Region number to be cleared. 229 | */ 230 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 231 | { 232 | MPU->RNR = rnr; 233 | MPU->RASR = 0U; 234 | } 235 | 236 | /** Configure an MPU region. 237 | * \param rbar Value for RBAR register. 238 | * \param rsar Value for RSAR register. 239 | */ 240 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 241 | { 242 | MPU->RBAR = rbar; 243 | MPU->RASR = rasr; 244 | } 245 | 246 | /** Configure the given MPU region. 247 | * \param rnr Region number to be configured. 248 | * \param rbar Value for RBAR register. 249 | * \param rsar Value for RSAR register. 250 | */ 251 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 252 | { 253 | MPU->RNR = rnr; 254 | MPU->RBAR = rbar; 255 | MPU->RASR = rasr; 256 | } 257 | 258 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 259 | * \param dst Destination data is copied to. 260 | * \param src Source data is copied from. 261 | * \param len Amount of data words to be copied. 262 | */ 263 | __STATIC_INLINE void orderedCpy( 264 | volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 265 | { 266 | uint32_t i; 267 | for (i = 0U; i < len; ++i) 268 | { 269 | dst[i] = src[i]; 270 | } 271 | } 272 | 273 | /** Load the given number of MPU regions from a table. 274 | * \param table Pointer to the MPU configuration table. 275 | * \param cnt Amount of regions to be configured. 276 | */ 277 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 278 | { 279 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U; 280 | while (cnt > MPU_TYPE_RALIASES) 281 | { 282 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES * rowWordSize); 283 | table += MPU_TYPE_RALIASES; 284 | cnt -= MPU_TYPE_RALIASES; 285 | } 286 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt * rowWordSize); 287 | } 288 | 289 | #endif 290 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined(__ICCARM__) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined(__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE (0U) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE (4U) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement 50 | */ 51 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 52 | 53 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 54 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 55 | 56 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 57 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 58 | 59 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 60 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 61 | 62 | /** \brief Memory Attribute 63 | * \param O Outer memory attributes 64 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 65 | */ 66 | #define ARM_MPU_ATTR(O, I) \ 67 | (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 68 | 69 | /** \brief Normal memory non-shareable */ 70 | #define ARM_MPU_SH_NON (0U) 71 | 72 | /** \brief Normal memory outer shareable */ 73 | #define ARM_MPU_SH_OUTER (2U) 74 | 75 | /** \brief Normal memory inner shareable */ 76 | #define ARM_MPU_SH_INNER (3U) 77 | 78 | /** \brief Memory access permissions 79 | * \param RO Read-Only: Set to 1 for read-only memory. 80 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 81 | */ 82 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 83 | 84 | /** \brief Region Base Address Register value 85 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. 86 | * Effective address gets 32 byte aligned. \param SH Defines the Shareability domain for this 87 | * memory region. \param RO Read-Only: Set to 1 for a read-only memory region. \param NP 88 | * Non-Privileged: Set to 1 for a non-privileged memory region. \oaram XN eXecute Never: Set to 89 | * 1 for a non-executable memory region. 90 | */ 91 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 92 | ((BASE & MPU_RBAR_BASE_Msk) | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) \ 93 | | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) \ 94 | | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 95 | 96 | /** \brief Region Limit Address Register value 97 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one 98 | * extended. \param IDX The attribute index to be associated with this memory region. 99 | */ 100 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 101 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) \ 102 | | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct 108 | { 109 | uint32_t RBAR; /*!< Region Base Address Register value */ 110 | uint32_t RLAR; /*!< Region Limit Address Register value */ 111 | } ARM_MPU_Region_t; 112 | 113 | /** Enable the MPU. 114 | * \param MPU_Control Default access permissions for unconfigured regions. 115 | */ 116 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 117 | { 118 | __DSB(); 119 | __ISB(); 120 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 121 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 122 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 123 | #endif 124 | } 125 | 126 | /** Disable the MPU. 127 | */ 128 | __STATIC_INLINE void ARM_MPU_Disable(void) 129 | { 130 | __DSB(); 131 | __ISB(); 132 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 133 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 134 | #endif 135 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 136 | } 137 | 138 | #ifdef MPU_NS 139 | /** Enable the Non-secure MPU. 140 | * \param MPU_Control Default access permissions for unconfigured regions. 141 | */ 142 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 143 | { 144 | __DSB(); 145 | __ISB(); 146 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 147 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 148 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 149 | #endif 150 | } 151 | 152 | /** Disable the Non-secure MPU. 153 | */ 154 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 155 | { 156 | __DSB(); 157 | __ISB(); 158 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 160 | #endif 161 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 162 | } 163 | #endif 164 | 165 | /** Set the memory attribute encoding to the given MPU. 166 | * \param mpu Pointer to the MPU to be configured. 167 | * \param idx The attribute index to be set [0-7] 168 | * \param attr The attribute value to be set. 169 | */ 170 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 171 | { 172 | const uint8_t reg = idx / 4U; 173 | const uint32_t pos = ((idx % 4U) * 8U); 174 | const uint32_t mask = 0xFFU << pos; 175 | 176 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) 177 | { 178 | return; // invalid index 179 | } 180 | 181 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 182 | } 183 | 184 | /** Set the memory attribute encoding. 185 | * \param idx The attribute index to be set [0-7] 186 | * \param attr The attribute value to be set. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 189 | { 190 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 191 | } 192 | 193 | #ifdef MPU_NS 194 | /** Set the memory attribute encoding to the Non-secure MPU. 195 | * \param idx The attribute index to be set [0-7] 196 | * \param attr The attribute value to be set. 197 | */ 198 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 199 | { 200 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 201 | } 202 | #endif 203 | 204 | /** Clear and disable the given MPU region of the given MPU. 205 | * \param mpu Pointer to MPU to be used. 206 | * \param rnr Region number to be cleared. 207 | */ 208 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 209 | { 210 | mpu->RNR = rnr; 211 | mpu->RLAR = 0U; 212 | } 213 | 214 | /** Clear and disable the given MPU region. 215 | * \param rnr Region number to be cleared. 216 | */ 217 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 218 | { 219 | ARM_MPU_ClrRegionEx(MPU, rnr); 220 | } 221 | 222 | #ifdef MPU_NS 223 | /** Clear and disable the given Non-secure MPU region. 224 | * \param rnr Region number to be cleared. 225 | */ 226 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 227 | { 228 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 229 | } 230 | #endif 231 | 232 | /** Configure the given MPU region of the given MPU. 233 | * \param mpu Pointer to MPU to be used. 234 | * \param rnr Region number to be configured. 235 | * \param rbar Value for RBAR register. 236 | * \param rlar Value for RLAR register. 237 | */ 238 | __STATIC_INLINE void ARM_MPU_SetRegionEx( 239 | MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 240 | { 241 | mpu->RNR = rnr; 242 | mpu->RBAR = rbar; 243 | mpu->RLAR = rlar; 244 | } 245 | 246 | /** Configure the given MPU region. 247 | * \param rnr Region number to be configured. 248 | * \param rbar Value for RBAR register. 249 | * \param rlar Value for RLAR register. 250 | */ 251 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 252 | { 253 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 254 | } 255 | 256 | #ifdef MPU_NS 257 | /** Configure the given Non-secure MPU region. 258 | * \param rnr Region number to be configured. 259 | * \param rbar Value for RBAR register. 260 | * \param rlar Value for RLAR register. 261 | */ 262 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 263 | { 264 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 265 | } 266 | #endif 267 | 268 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 269 | * \param dst Destination data is copied to. 270 | * \param src Source data is copied from. 271 | * \param len Amount of data words to be copied. 272 | */ 273 | __STATIC_INLINE void orderedCpy( 274 | volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 275 | { 276 | uint32_t i; 277 | for (i = 0U; i < len; ++i) 278 | { 279 | dst[i] = src[i]; 280 | } 281 | } 282 | 283 | /** Load the given number of MPU regions from a table to the given MPU. 284 | * \param mpu Pointer to the MPU registers to be used. 285 | * \param rnr First region number to be configured. 286 | * \param table Pointer to the MPU configuration table. 287 | * \param cnt Amount of regions to be configured. 288 | */ 289 | __STATIC_INLINE void ARM_MPU_LoadEx( 290 | MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 291 | { 292 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U; 293 | if (cnt == 1U) 294 | { 295 | mpu->RNR = rnr; 296 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 297 | } 298 | else 299 | { 300 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES - 1U); 301 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 302 | 303 | mpu->RNR = rnrBase; 304 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) 305 | { 306 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 307 | orderedCpy(&(mpu->RBAR) + (rnrOffset * 2U), &(table->RBAR), c * rowWordSize); 308 | table += c; 309 | cnt -= c; 310 | rnrOffset = 0U; 311 | rnrBase += MPU_TYPE_RALIASES; 312 | mpu->RNR = rnrBase; 313 | } 314 | 315 | orderedCpy(&(mpu->RBAR) + (rnrOffset * 2U), &(table->RBAR), cnt * rowWordSize); 316 | } 317 | } 318 | 319 | /** Load the given number of MPU regions from a table. 320 | * \param rnr First region number to be configured. 321 | * \param table Pointer to the MPU configuration table. 322 | * \param cnt Amount of regions to be configured. 323 | */ 324 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 325 | { 326 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 327 | } 328 | 329 | #ifdef MPU_NS 330 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 331 | * \param rnr First region number to be configured. 332 | * \param table Pointer to the MPU configuration table. 333 | * \param cnt Amount of regions to be configured. 334 | */ 335 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 336 | { 337 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 338 | } 339 | #endif 340 | 341 | #endif 342 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined(__ICCARM__) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined(__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S(void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S(TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S(TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal.h 4 | * @author MCD Application Team 5 | * @brief This file contains all the functions prototypes for the HAL 6 | * module driver. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F4xx_HAL_H 23 | #define __STM32F4xx_HAL_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" 27 | { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f4xx_hal_conf.h" 32 | 33 | /** @addtogroup STM32F4xx_HAL_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup HAL 38 | * @{ 39 | */ 40 | 41 | /* Exported types ------------------------------------------------------------*/ 42 | /* Exported constants --------------------------------------------------------*/ 43 | 44 | /** @defgroup HAL_Exported_Constants HAL Exported Constants 45 | * @{ 46 | */ 47 | 48 | /** @defgroup HAL_TICK_FREQ Tick Frequency 49 | * @{ 50 | */ 51 | typedef enum 52 | { 53 | HAL_TICK_FREQ_10HZ = 100U, 54 | HAL_TICK_FREQ_100HZ = 10U, 55 | HAL_TICK_FREQ_1KHZ = 1U, 56 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 57 | } HAL_TickFreqTypeDef; 58 | /** 59 | * @} 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /* Exported macro ------------------------------------------------------------*/ 67 | /** @defgroup HAL_Exported_Macros HAL Exported Macros 68 | * @{ 69 | */ 70 | 71 | /** @brief Freeze/Unfreeze Peripherals in Debug mode 72 | */ 73 | #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) 74 | #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) 75 | #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) 76 | #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) 77 | #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) 78 | #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) 79 | #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) 80 | #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) 81 | #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) 82 | #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) 83 | #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) 84 | #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) 85 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() \ 86 | (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) 87 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() \ 88 | (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) 89 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() \ 90 | (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) 91 | #define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) 92 | #define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) 93 | #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) 94 | #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) 95 | #define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) 96 | #define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) 97 | #define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) 98 | 99 | #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) 100 | #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) 101 | #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) 102 | #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) 103 | #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) 104 | #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) 105 | #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) 106 | #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) 107 | #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) 108 | #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) 109 | #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) 110 | #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) 111 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() \ 112 | (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) 113 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() \ 114 | (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) 115 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() \ 116 | (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) 117 | #define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) 118 | #define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) 119 | #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) 120 | #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) 121 | #define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) 122 | #define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) 123 | #define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) 124 | 125 | /** @brief Main Flash memory mapped at 0x00000000 126 | */ 127 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) 128 | 129 | /** @brief System Flash memory mapped at 0x00000000 130 | */ 131 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() \ 132 | do \ 133 | { \ 134 | SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE); \ 135 | SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0; \ 136 | } while (0); 137 | 138 | /** @brief Embedded SRAM mapped at 0x00000000 139 | */ 140 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ 141 | do \ 142 | { \ 143 | SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE); \ 144 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1); \ 145 | } while (0); 146 | 147 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) \ 148 | || defined(STM32F417xx) 149 | /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 150 | */ 151 | #define __HAL_SYSCFG_REMAPMEMORY_FSMC() \ 152 | do \ 153 | { \ 154 | SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE); \ 155 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1); \ 156 | } while (0); 157 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 158 | 159 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) \ 160 | || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 161 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 162 | */ 163 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() \ 164 | do \ 165 | { \ 166 | SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE); \ 167 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1); \ 168 | } while (0); 169 | 170 | /** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000 171 | */ 172 | #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() \ 173 | do \ 174 | { \ 175 | SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE); \ 176 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2); \ 177 | } while (0); 178 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || \ 179 | STM32F479xx */ 180 | 181 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) \ 182 | || defined(STM32F413xx) || defined(STM32F423xx) 183 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable 184 | * @{ 185 | */ 186 | /** @brief SYSCFG Break Lockup lock 187 | * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 188 | * input 189 | * @note The selected configuration is locked and can be unlocked by system reset 190 | */ 191 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() \ 192 | do \ 193 | { \ 194 | SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ 195 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ 196 | } while (0) 197 | /** 198 | * @} 199 | */ 200 | 201 | /** @defgroup PVD_Lock_Enable PVD Lock 202 | * @{ 203 | */ 204 | /** @brief SYSCFG Break PVD lock 205 | * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the 206 | * PVDE and PLS[2:0] in the PWR_CR register 207 | * @note The selected configuration is locked and can be unlocked by system reset 208 | */ 209 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() \ 210 | do \ 211 | { \ 212 | SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ 213 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ 214 | } while (0) 215 | /** 216 | * @} 217 | */ 218 | #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */ 219 | /** 220 | * @} 221 | */ 222 | 223 | /** @defgroup HAL_Private_Macros HAL Private Macros 224 | * @{ 225 | */ 226 | #define IS_TICKFREQ(FREQ) \ 227 | (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) \ 228 | || ((FREQ) == HAL_TICK_FREQ_1KHZ)) 229 | /** 230 | * @} 231 | */ 232 | 233 | /* Exported variables --------------------------------------------------------*/ 234 | 235 | /** @addtogroup HAL_Exported_Variables 236 | * @{ 237 | */ 238 | extern __IO uint32_t uwTick; 239 | extern uint32_t uwTickPrio; 240 | extern HAL_TickFreqTypeDef uwTickFreq; 241 | /** 242 | * @} 243 | */ 244 | 245 | /* Exported functions --------------------------------------------------------*/ 246 | /** @addtogroup HAL_Exported_Functions 247 | * @{ 248 | */ 249 | /** @addtogroup HAL_Exported_Functions_Group1 250 | * @{ 251 | */ 252 | /* Initialization and Configuration functions ******************************/ 253 | HAL_StatusTypeDef HAL_Init(void); 254 | HAL_StatusTypeDef HAL_DeInit(void); 255 | void HAL_MspInit(void); 256 | void HAL_MspDeInit(void); 257 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 258 | /** 259 | * @} 260 | */ 261 | 262 | /** @addtogroup HAL_Exported_Functions_Group2 263 | * @{ 264 | */ 265 | /* Peripheral Control functions ************************************************/ 266 | void HAL_IncTick(void); 267 | void HAL_Delay(uint32_t Delay); 268 | uint32_t HAL_GetTick(void); 269 | uint32_t HAL_GetTickPrio(void); 270 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 271 | HAL_TickFreqTypeDef HAL_GetTickFreq(void); 272 | void HAL_SuspendTick(void); 273 | void HAL_ResumeTick(void); 274 | uint32_t HAL_GetHalVersion(void); 275 | uint32_t HAL_GetREVID(void); 276 | uint32_t HAL_GetDEVID(void); 277 | void HAL_DBGMCU_EnableDBGSleepMode(void); 278 | void HAL_DBGMCU_DisableDBGSleepMode(void); 279 | void HAL_DBGMCU_EnableDBGStopMode(void); 280 | void HAL_DBGMCU_DisableDBGStopMode(void); 281 | void HAL_DBGMCU_EnableDBGStandbyMode(void); 282 | void HAL_DBGMCU_DisableDBGStandbyMode(void); 283 | void HAL_EnableCompensationCell(void); 284 | void HAL_DisableCompensationCell(void); 285 | uint32_t HAL_GetUIDw0(void); 286 | uint32_t HAL_GetUIDw1(void); 287 | uint32_t HAL_GetUIDw2(void); 288 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) \ 289 | || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 290 | void HAL_EnableMemorySwappingBank(void); 291 | void HAL_DisableMemorySwappingBank(void); 292 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || \ 293 | STM32F479xx */ 294 | /** 295 | * @} 296 | */ 297 | 298 | /** 299 | * @} 300 | */ 301 | /* Private types -------------------------------------------------------------*/ 302 | /* Private variables ---------------------------------------------------------*/ 303 | /** @defgroup HAL_Private_Variables HAL Private Variables 304 | * @{ 305 | */ 306 | /** 307 | * @} 308 | */ 309 | /* Private constants ---------------------------------------------------------*/ 310 | /** @defgroup HAL_Private_Constants HAL Private Constants 311 | * @{ 312 | */ 313 | /** 314 | * @} 315 | */ 316 | /* Private macros ------------------------------------------------------------*/ 317 | /* Private functions ---------------------------------------------------------*/ 318 | /** 319 | * @} 320 | */ 321 | 322 | /** 323 | * @} 324 | */ 325 | 326 | #ifdef __cplusplus 327 | } 328 | #endif 329 | 330 | #endif /* __STM32F4xx_HAL_H */ 331 | 332 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 333 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F4xx_HAL_DEF 23 | #define __STM32F4xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" 27 | { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include "stm32f4xx.h" 33 | #include 34 | 35 | /* Exported types ------------------------------------------------------------*/ 36 | 37 | /** 38 | * @brief HAL Status structures definition 39 | */ 40 | typedef enum 41 | { 42 | HAL_OK = 0x00U, 43 | HAL_ERROR = 0x01U, 44 | HAL_BUSY = 0x02U, 45 | HAL_TIMEOUT = 0x03U 46 | } HAL_StatusTypeDef; 47 | 48 | /** 49 | * @brief HAL Lock structures definition 50 | */ 51 | typedef enum 52 | { 53 | HAL_UNLOCKED = 0x00U, 54 | HAL_LOCKED = 0x01U 55 | } HAL_LockTypeDef; 56 | 57 | /* Exported macro ------------------------------------------------------------*/ 58 | 59 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 60 | 61 | #define HAL_MAX_DELAY 0xFFFFFFFFU 62 | 63 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) 64 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 65 | 66 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 67 | do \ 68 | { \ 69 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 70 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 71 | } while (0U) 72 | 73 | /** @brief Reset the Handle's State field. 74 | * @param __HANDLE__ specifies the Peripheral Handle. 75 | * @note This macro can be used for the following purpose: 76 | * - When the Handle is declared as local variable; before passing it as parameter 77 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 78 | * to set to 0 the Handle's "State" field. 79 | * Otherwise, "State" field may have any random value and the first time the 80 | * function HAL_PPP_Init() is called, the low level hardware initialization will be missed 81 | * (i.e. HAL_PPP_MspInit() will not be executed). 82 | * - When there is a need to reconfigure the low level hardware: instead of calling 83 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then 84 | * HAL_PPP_Init(). In this later function, when the Handle's "State" field is set to 0, it will 85 | * execute the function HAL_PPP_MspInit() which will reconfigure the low level hardware. 86 | * @retval None 87 | */ 88 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 89 | 90 | #if (USE_RTOS == 1U) 91 | /* Reserved for future use */ 92 | #error "USE_RTOS should be 0 in the current HAL release" 93 | #else 94 | #define __HAL_LOCK(__HANDLE__) \ 95 | do \ 96 | { \ 97 | if ((__HANDLE__)->Lock == HAL_LOCKED) \ 98 | { \ 99 | return HAL_BUSY; \ 100 | } \ 101 | else \ 102 | { \ 103 | (__HANDLE__)->Lock = HAL_LOCKED; \ 104 | } \ 105 | } while (0U) 106 | 107 | #define __HAL_UNLOCK(__HANDLE__) \ 108 | do \ 109 | { \ 110 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 111 | } while (0U) 112 | #endif /* USE_RTOS */ 113 | 114 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 115 | #ifndef __weak 116 | #define __weak __attribute__((weak)) 117 | #endif 118 | #ifndef __packed 119 | #define __packed __attribute__((packed)) 120 | #endif 121 | #elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ 122 | #ifndef __weak 123 | #define __weak __attribute__((weak)) 124 | #endif /* __weak */ 125 | #ifndef __packed 126 | #define __packed __attribute__((__packed__)) 127 | #endif /* __packed */ 128 | #endif /* __GNUC__ */ 129 | 130 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma 131 | * data_alignment=4" must be used instead */ 132 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 133 | #ifndef __ALIGN_BEGIN 134 | #define __ALIGN_BEGIN 135 | #endif 136 | #ifndef __ALIGN_END 137 | #define __ALIGN_END __attribute__((aligned(4))) 138 | #endif 139 | #elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ 140 | #ifndef __ALIGN_END 141 | #define __ALIGN_END __attribute__((aligned(4))) 142 | #endif /* __ALIGN_END */ 143 | #ifndef __ALIGN_BEGIN 144 | #define __ALIGN_BEGIN 145 | #endif /* __ALIGN_BEGIN */ 146 | #else 147 | #ifndef __ALIGN_END 148 | #define __ALIGN_END 149 | #endif /* __ALIGN_END */ 150 | #ifndef __ALIGN_BEGIN 151 | #if defined(__CC_ARM) /* ARM Compiler V5*/ 152 | #define __ALIGN_BEGIN __align(4) 153 | #elif defined(__ICCARM__) /* IAR Compiler */ 154 | #define __ALIGN_BEGIN 155 | #endif /* __CC_ARM */ 156 | #endif /* __ALIGN_BEGIN */ 157 | #endif /* __GNUC__ */ 158 | 159 | /** 160 | * @brief __RAM_FUNC definition 161 | */ 162 | #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 163 | /* ARM Compiler V4/V5 and V6 164 | -------------------------- 165 | RAM functions are defined using the toolchain options. 166 | Functions that are executed in RAM should reside in a separate source module. 167 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 168 | area of a module to a memory space in physical RAM. 169 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 170 | dialog. 171 | */ 172 | #define __RAM_FUNC 173 | 174 | #elif defined(__ICCARM__) 175 | /* ICCARM Compiler 176 | --------------- 177 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 178 | */ 179 | #define __RAM_FUNC __ramfunc 180 | 181 | #elif defined(__GNUC__) 182 | /* GNU Compiler 183 | ------------ 184 | RAM functions are defined using a specific toolchain attribute 185 | "__attribute__((section(".RamFunc")))". 186 | */ 187 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 188 | 189 | #endif 190 | 191 | /** 192 | * @brief __NOINLINE definition 193 | */ 194 | #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) \ 195 | || defined(__GNUC__) 196 | /* ARM V4/V5 and V6 & GNU Compiler 197 | ------------------------------- 198 | */ 199 | #define __NOINLINE __attribute__((noinline)) 200 | 201 | #elif defined(__ICCARM__) 202 | /* ICCARM Compiler 203 | --------------- 204 | */ 205 | #define __NOINLINE _Pragma("optimize = no_inline") 206 | 207 | #endif 208 | 209 | #ifdef __cplusplus 210 | } 211 | #endif 212 | 213 | #endif /* ___STM32F4xx_HAL_DEF */ 214 | 215 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 216 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_dma_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of DMA HAL extension module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F4xx_HAL_DMA_EX_H 22 | #define __STM32F4xx_HAL_DMA_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" 26 | { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f4xx_hal_def.h" 31 | 32 | /** @addtogroup STM32F4xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @addtogroup DMAEx 37 | * @{ 38 | */ 39 | 40 | /* Exported types ------------------------------------------------------------*/ 41 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 42 | * @brief DMAEx Exported types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief HAL DMA Memory definition 48 | */ 49 | typedef enum 50 | { 51 | MEMORY0 = 0x00U, /*!< Memory 0 */ 52 | MEMORY1 = 0x01U /*!< Memory 1 */ 53 | } HAL_DMA_MemoryTypeDef; 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /* Exported functions --------------------------------------------------------*/ 60 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 61 | * @brief DMAEx Exported functions 62 | * @{ 63 | */ 64 | 65 | /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions 66 | * @brief Extended features functions 67 | * @{ 68 | */ 69 | 70 | /* IO operation functions *******************************************************/ 71 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart( 72 | DMA_HandleTypeDef* hdma, 73 | uint32_t SrcAddress, 74 | uint32_t DstAddress, 75 | uint32_t SecondMemAddress, 76 | uint32_t DataLength); 77 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT( 78 | DMA_HandleTypeDef* hdma, 79 | uint32_t SrcAddress, 80 | uint32_t DstAddress, 81 | uint32_t SecondMemAddress, 82 | uint32_t DataLength); 83 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory( 84 | DMA_HandleTypeDef* hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); 85 | 86 | /** 87 | * @} 88 | */ 89 | /** 90 | * @} 91 | */ 92 | 93 | /* Private functions ---------------------------------------------------------*/ 94 | /** @defgroup DMAEx_Private_Functions DMAEx Private Functions 95 | * @brief DMAEx Private functions 96 | * @{ 97 | */ 98 | /** 99 | * @} 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | #ifdef __cplusplus 111 | } 112 | #endif 113 | 114 | #endif /*__STM32F4xx_HAL_DMA_EX_H*/ 115 | 116 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 117 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_exti.h 4 | * @author MCD Application Team 5 | * @brief Header file of EXTI HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2018 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32f4xx_HAL_EXTI_H 22 | #define STM32f4xx_HAL_EXTI_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" 26 | { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f4xx_hal_def.h" 31 | 32 | /** @addtogroup STM32F4xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup EXTI EXTI 37 | * @brief EXTI HAL module driver 38 | * @{ 39 | */ 40 | 41 | /* Exported types ------------------------------------------------------------*/ 42 | 43 | /** @defgroup EXTI_Exported_Types EXTI Exported Types 44 | * @{ 45 | */ 46 | typedef enum 47 | { 48 | HAL_EXTI_COMMON_CB_ID = 0x00U 49 | } EXTI_CallbackIDTypeDef; 50 | 51 | /** 52 | * @brief EXTI Handle structure definition 53 | */ 54 | typedef struct 55 | { 56 | uint32_t Line; /*!< Exti line number */ 57 | void (*PendingCallback)(void); /*!< Exti pending callback */ 58 | } EXTI_HandleTypeDef; 59 | 60 | /** 61 | * @brief EXTI Configuration structure definition 62 | */ 63 | typedef struct 64 | { 65 | uint32_t Line; /*!< The Exti line to be configured. This parameter 66 | can be a value of @ref EXTI_Line */ 67 | uint32_t Mode; /*!< The Exit Mode to be configured for a core. 68 | This parameter can be a combination of @ref EXTI_Mode */ 69 | uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter 70 | can be a value of @ref EXTI_Trigger */ 71 | uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. 72 | This parameter is only possible for line 0 to 15. It 73 | can be a value of @ref EXTI_GPIOSel */ 74 | } EXTI_ConfigTypeDef; 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | /* Exported constants --------------------------------------------------------*/ 81 | /** @defgroup EXTI_Exported_Constants EXTI Exported Constants 82 | * @{ 83 | */ 84 | 85 | /** @defgroup EXTI_Line EXTI Line 86 | * @{ 87 | */ 88 | #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ 89 | #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ 90 | #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ 91 | #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ 92 | #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ 93 | #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ 94 | #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ 95 | #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ 96 | #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ 97 | #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ 98 | #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ 99 | #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ 100 | #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ 101 | #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ 102 | #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ 103 | #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ 104 | #define EXTI_LINE_16 \ 105 | (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ 106 | #define EXTI_LINE_17 \ 107 | (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 108 | #if defined(EXTI_IMR_IM18) 109 | #define EXTI_LINE_18 \ 110 | (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup \ 111 | from suspend event */ 112 | #else 113 | #define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ 114 | #endif /* EXTI_IMR_IM18 */ 115 | #if defined(EXTI_IMR_IM19) 116 | #define EXTI_LINE_19 \ 117 | (EXTI_CONFIG \ 118 | | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 119 | #else 120 | #define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ 121 | #endif /* EXTI_IMR_IM19 */ 122 | #if defined(EXTI_IMR_IM20) 123 | #define EXTI_LINE_20 \ 124 | (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS \ 125 | (configured in FS) Wakeup event */ 126 | #else 127 | #define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ 128 | #endif /* EXTI_IMR_IM20 */ 129 | #define EXTI_LINE_21 \ 130 | (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and \ 131 | Time Stamp events */ 132 | #define EXTI_LINE_22 \ 133 | (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event \ 134 | */ 135 | #if defined(EXTI_IMR_IM23) 136 | #define EXTI_LINE_23 \ 137 | (EXTI_CONFIG \ 138 | | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ 139 | #endif /* EXTI_IMR_IM23 */ 140 | 141 | /** 142 | * @} 143 | */ 144 | 145 | /** @defgroup EXTI_Mode EXTI Mode 146 | * @{ 147 | */ 148 | #define EXTI_MODE_NONE 0x00000000u 149 | #define EXTI_MODE_INTERRUPT 0x00000001u 150 | #define EXTI_MODE_EVENT 0x00000002u 151 | /** 152 | * @} 153 | */ 154 | 155 | /** @defgroup EXTI_Trigger EXTI Trigger 156 | * @{ 157 | */ 158 | 159 | #define EXTI_TRIGGER_NONE 0x00000000u 160 | #define EXTI_TRIGGER_RISING 0x00000001u 161 | #define EXTI_TRIGGER_FALLING 0x00000002u 162 | #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) 163 | /** 164 | * @} 165 | */ 166 | 167 | /** @defgroup EXTI_GPIOSel EXTI GPIOSel 168 | * @brief 169 | * @{ 170 | */ 171 | #define EXTI_GPIOA 0x00000000u 172 | #define EXTI_GPIOB 0x00000001u 173 | #define EXTI_GPIOC 0x00000002u 174 | #if defined(GPIOD) 175 | #define EXTI_GPIOD 0x00000003u 176 | #endif /* GPIOD */ 177 | #if defined(GPIOE) 178 | #define EXTI_GPIOE 0x00000004u 179 | #endif /* GPIOE */ 180 | #if defined(GPIOF) 181 | #define EXTI_GPIOF 0x00000005u 182 | #endif /* GPIOF */ 183 | #if defined(GPIOG) 184 | #define EXTI_GPIOG 0x00000006u 185 | #endif /* GPIOG */ 186 | #if defined(GPIOH) 187 | #define EXTI_GPIOH 0x00000007u 188 | #endif /* GPIOH */ 189 | #if defined(GPIOI) 190 | #define EXTI_GPIOI 0x00000008u 191 | #endif /* GPIOI */ 192 | #if defined(GPIOJ) 193 | #define EXTI_GPIOJ 0x00000009u 194 | #endif /* GPIOJ */ 195 | #if defined(GPIOK) 196 | #define EXTI_GPIOK 0x0000000Au 197 | #endif /* GPIOK */ 198 | 199 | /** 200 | * @} 201 | */ 202 | 203 | /** 204 | * @} 205 | */ 206 | 207 | /* Exported macro ------------------------------------------------------------*/ 208 | /** @defgroup EXTI_Exported_Macros EXTI Exported Macros 209 | * @{ 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /* Private constants --------------------------------------------------------*/ 217 | /** @defgroup EXTI_Private_Constants EXTI Private Constants 218 | * @{ 219 | */ 220 | /** 221 | * @brief EXTI Line property definition 222 | */ 223 | #define EXTI_PROPERTY_SHIFT 24u 224 | #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) 225 | #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) 226 | #define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) 227 | #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) 228 | 229 | /** 230 | * @brief EXTI bit usage 231 | */ 232 | #define EXTI_PIN_MASK 0x0000001Fu 233 | 234 | /** 235 | * @brief EXTI Mask for interrupt & event mode 236 | */ 237 | #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) 238 | 239 | /** 240 | * @brief EXTI Mask for trigger possibilities 241 | */ 242 | #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) 243 | 244 | /** 245 | * @brief EXTI Line number 246 | */ 247 | #if defined(EXTI_IMR_IM23) 248 | #define EXTI_LINE_NB 24UL 249 | #else 250 | #define EXTI_LINE_NB 23UL 251 | #endif /* EXTI_IMR_IM23 */ 252 | 253 | /** 254 | * @} 255 | */ 256 | 257 | /* Private macros ------------------------------------------------------------*/ 258 | /** @defgroup EXTI_Private_Macros EXTI Private Macros 259 | * @{ 260 | */ 261 | #define IS_EXTI_LINE(__EXTI_LINE__) \ 262 | ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) \ 263 | && ((((__EXTI_LINE__)&EXTI_PROPERTY_MASK) == EXTI_CONFIG) \ 264 | || (((__EXTI_LINE__)&EXTI_PROPERTY_MASK) == EXTI_GPIO)) \ 265 | && (((__EXTI_LINE__)&EXTI_PIN_MASK) < EXTI_LINE_NB)) 266 | 267 | #define IS_EXTI_MODE(__EXTI_LINE__) \ 268 | ((((__EXTI_LINE__)&EXTI_MODE_MASK) != 0x00u) \ 269 | && (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) 270 | 271 | #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) 272 | 273 | #define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) 274 | 275 | #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__)&EXTI_CONFIG) != 0x00u) 276 | 277 | #if !defined(GPIOD) 278 | #define IS_EXTI_GPIO_PORT(__PORT__) \ 279 | (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) \ 280 | || ((__PORT__) == EXTI_GPIOH)) 281 | #elif !defined(GPIOE) 282 | #define IS_EXTI_GPIO_PORT(__PORT__) \ 283 | (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) \ 284 | || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOH)) 285 | #elif !defined(GPIOF) 286 | #define IS_EXTI_GPIO_PORT(__PORT__) \ 287 | (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) \ 288 | || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) \ 289 | || ((__PORT__) == EXTI_GPIOH)) 290 | #elif !defined(GPIOI) 291 | #define IS_EXTI_GPIO_PORT(__PORT__) \ 292 | (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) \ 293 | || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) \ 294 | || ((__PORT__) == EXTI_GPIOF) || ((__PORT__) == EXTI_GPIOG) \ 295 | || ((__PORT__) == EXTI_GPIOH)) 296 | #elif !defined(GPIOJ) 297 | #define IS_EXTI_GPIO_PORT(__PORT__) \ 298 | (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) \ 299 | || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) \ 300 | || ((__PORT__) == EXTI_GPIOF) || ((__PORT__) == EXTI_GPIOG) \ 301 | || ((__PORT__) == EXTI_GPIOH) || ((__PORT__) == EXTI_GPIOI)) 302 | #else 303 | #define IS_EXTI_GPIO_PORT(__PORT__) \ 304 | (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) \ 305 | || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) \ 306 | || ((__PORT__) == EXTI_GPIOF) || ((__PORT__) == EXTI_GPIOG) \ 307 | || ((__PORT__) == EXTI_GPIOH) || ((__PORT__) == EXTI_GPIOI) \ 308 | || ((__PORT__) == EXTI_GPIOJ) || ((__PORT__) == EXTI_GPIOK)) 309 | #endif /* GPIOD */ 310 | 311 | #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) 312 | /** 313 | * @} 314 | */ 315 | 316 | /* Exported functions --------------------------------------------------------*/ 317 | /** @defgroup EXTI_Exported_Functions EXTI Exported Functions 318 | * @brief EXTI Exported Functions 319 | * @{ 320 | */ 321 | 322 | /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions 323 | * @brief Configuration functions 324 | * @{ 325 | */ 326 | /* Configuration functions ****************************************************/ 327 | HAL_StatusTypeDef HAL_EXTI_SetConfigLine( 328 | EXTI_HandleTypeDef* hexti, EXTI_ConfigTypeDef* pExtiConfig); 329 | HAL_StatusTypeDef HAL_EXTI_GetConfigLine( 330 | EXTI_HandleTypeDef* hexti, EXTI_ConfigTypeDef* pExtiConfig); 331 | HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef* hexti); 332 | HAL_StatusTypeDef HAL_EXTI_RegisterCallback( 333 | EXTI_HandleTypeDef* hexti, 334 | EXTI_CallbackIDTypeDef CallbackID, 335 | void (*pPendingCbfn)(void)); 336 | HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef* hexti, uint32_t ExtiLine); 337 | /** 338 | * @} 339 | */ 340 | 341 | /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions 342 | * @brief IO operation functions 343 | * @{ 344 | */ 345 | /* IO operation functions *****************************************************/ 346 | void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef* hexti); 347 | uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef* hexti, uint32_t Edge); 348 | void HAL_EXTI_ClearPending(EXTI_HandleTypeDef* hexti, uint32_t Edge); 349 | void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef* hexti); 350 | 351 | /** 352 | * @} 353 | */ 354 | 355 | /** 356 | * @} 357 | */ 358 | 359 | /** 360 | * @} 361 | */ 362 | 363 | /** 364 | * @} 365 | */ 366 | 367 | #ifdef __cplusplus 368 | } 369 | #endif 370 | 371 | #endif /* STM32f4xx_HAL_EXTI_H */ 372 | 373 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 374 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of FLASH HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F4xx_HAL_FLASH_H 22 | #define __STM32F4xx_HAL_FLASH_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" 26 | { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f4xx_hal_def.h" 31 | 32 | /** @addtogroup STM32F4xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @addtogroup FLASH 37 | * @{ 38 | */ 39 | 40 | /* Exported types ------------------------------------------------------------*/ 41 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief FLASH Procedure structure definition 47 | */ 48 | typedef enum 49 | { 50 | FLASH_PROC_NONE = 0U, 51 | FLASH_PROC_SECTERASE, 52 | FLASH_PROC_MASSERASE, 53 | FLASH_PROC_PROGRAM 54 | } FLASH_ProcedureTypeDef; 55 | 56 | /** 57 | * @brief FLASH handle Structure definition 58 | */ 59 | typedef struct 60 | { 61 | __IO FLASH_ProcedureTypeDef 62 | ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not 63 | in IT context*/ 64 | 65 | __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to 66 | erase in IT context*/ 67 | 68 | __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by 69 | user in IT context*/ 70 | 71 | __IO uint32_t 72 | Sector; /*Internal variable to define the current sector which is erasing*/ 73 | 74 | __IO uint32_t 75 | Bank; /*Internal variable to save current bank selected during mass erase*/ 76 | 77 | __IO uint32_t Address; /*Internal variable to save address selected for program*/ 78 | 79 | HAL_LockTypeDef Lock; /* FLASH locking object */ 80 | 81 | __IO uint32_t ErrorCode; /* FLASH error code */ 82 | 83 | } FLASH_ProcessTypeDef; 84 | 85 | /** 86 | * @} 87 | */ 88 | 89 | /* Exported constants --------------------------------------------------------*/ 90 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 91 | * @{ 92 | */ 93 | /** @defgroup FLASH_Error_Code FLASH Error Code 94 | * @brief FLASH Error Code 95 | * @{ 96 | */ 97 | #define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ 98 | #define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */ 99 | #define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */ 100 | #define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */ 101 | #define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */ 102 | #define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */ 103 | #define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */ 104 | /** 105 | * @} 106 | */ 107 | 108 | /** @defgroup FLASH_Type_Program FLASH Type Program 109 | * @{ 110 | */ 111 | #define FLASH_TYPEPROGRAM_BYTE \ 112 | 0x00000000U /*!< Program byte (8-bit) at a specified address */ 113 | #define FLASH_TYPEPROGRAM_HALFWORD \ 114 | 0x00000001U /*!< Program a half-word (16-bit) at a specified address */ 115 | #define FLASH_TYPEPROGRAM_WORD \ 116 | 0x00000002U /*!< Program a word (32-bit) at a specified address */ 117 | #define FLASH_TYPEPROGRAM_DOUBLEWORD \ 118 | 0x00000003U /*!< Program a double word (64-bit) at a specified address */ 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup FLASH_Flag_definition FLASH Flag definition 124 | * @brief Flag definition 125 | * @{ 126 | */ 127 | #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ 128 | #define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ 129 | #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ 130 | #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ 131 | #define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ 132 | #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ 133 | #if defined(FLASH_SR_RDERR) 134 | #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ 135 | #endif /* FLASH_SR_RDERR */ 136 | #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 137 | /** 138 | * @} 139 | */ 140 | 141 | /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition 142 | * @brief FLASH Interrupt definition 143 | * @{ 144 | */ 145 | #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 146 | #define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */ 147 | /** 148 | * @} 149 | */ 150 | 151 | /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism 152 | * @{ 153 | */ 154 | #define FLASH_PSIZE_BYTE 0x00000000U 155 | #define FLASH_PSIZE_HALF_WORD 0x00000100U 156 | #define FLASH_PSIZE_WORD 0x00000200U 157 | #define FLASH_PSIZE_DOUBLE_WORD 0x00000300U 158 | #define CR_PSIZE_MASK 0xFFFFFCFFU 159 | /** 160 | * @} 161 | */ 162 | 163 | /** @defgroup FLASH_Keys FLASH Keys 164 | * @{ 165 | */ 166 | #define RDP_KEY ((uint16_t)0x00A5) 167 | #define FLASH_KEY1 0x45670123U 168 | #define FLASH_KEY2 0xCDEF89ABU 169 | #define FLASH_OPT_KEY1 0x08192A3BU 170 | #define FLASH_OPT_KEY2 0x4C5D6E7FU 171 | /** 172 | * @} 173 | */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /* Exported macro ------------------------------------------------------------*/ 180 | /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 181 | * @{ 182 | */ 183 | /** 184 | * @brief Set the FLASH Latency. 185 | * @param __LATENCY__ FLASH Latency 186 | * The value of this parameter depend on device used within the same series 187 | * @retval none 188 | */ 189 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ 190 | (*(__IO uint8_t*)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__)) 191 | 192 | /** 193 | * @brief Get the FLASH Latency. 194 | * @retval FLASH Latency 195 | * The value of this parameter depend on device used within the same series 196 | */ 197 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 198 | 199 | /** 200 | * @brief Enable the FLASH prefetch buffer. 201 | * @retval none 202 | */ 203 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) 204 | 205 | /** 206 | * @brief Disable the FLASH prefetch buffer. 207 | * @retval none 208 | */ 209 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) 210 | 211 | /** 212 | * @brief Enable the FLASH instruction cache. 213 | * @retval none 214 | */ 215 | #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) 216 | 217 | /** 218 | * @brief Disable the FLASH instruction cache. 219 | * @retval none 220 | */ 221 | #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) 222 | 223 | /** 224 | * @brief Enable the FLASH data cache. 225 | * @retval none 226 | */ 227 | #define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) 228 | 229 | /** 230 | * @brief Disable the FLASH data cache. 231 | * @retval none 232 | */ 233 | #define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) 234 | 235 | /** 236 | * @brief Resets the FLASH instruction Cache. 237 | * @note This function must be used only when the Instruction Cache is disabled. 238 | * @retval None 239 | */ 240 | #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() \ 241 | do \ 242 | { \ 243 | FLASH->ACR |= FLASH_ACR_ICRST; \ 244 | FLASH->ACR &= ~FLASH_ACR_ICRST; \ 245 | } while (0U) 246 | 247 | /** 248 | * @brief Resets the FLASH data Cache. 249 | * @note This function must be used only when the data Cache is disabled. 250 | * @retval None 251 | */ 252 | #define __HAL_FLASH_DATA_CACHE_RESET() \ 253 | do \ 254 | { \ 255 | FLASH->ACR |= FLASH_ACR_DCRST; \ 256 | FLASH->ACR &= ~FLASH_ACR_DCRST; \ 257 | } while (0U) 258 | /** 259 | * @brief Enable the specified FLASH interrupt. 260 | * @param __INTERRUPT__ FLASH interrupt 261 | * This parameter can be any combination of the following values: 262 | * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 263 | * @arg FLASH_IT_ERR: Error Interrupt 264 | * @retval none 265 | */ 266 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) 267 | 268 | /** 269 | * @brief Disable the specified FLASH interrupt. 270 | * @param __INTERRUPT__ FLASH interrupt 271 | * This parameter can be any combination of the following values: 272 | * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 273 | * @arg FLASH_IT_ERR: Error Interrupt 274 | * @retval none 275 | */ 276 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) 277 | 278 | /** 279 | * @brief Get the specified FLASH flag status. 280 | * @param __FLAG__ specifies the FLASH flags to check. 281 | * This parameter can be any combination of the following values: 282 | * @arg FLASH_FLAG_EOP : FLASH End of Operation flag 283 | * @arg FLASH_FLAG_OPERR : FLASH operation Error flag 284 | * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 285 | * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 286 | * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag 287 | * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag 288 | * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) 289 | * @arg FLASH_FLAG_BSY : FLASH Busy flag 290 | * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices 291 | * @retval The new state of __FLAG__ (SET or RESET). 292 | */ 293 | #define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) 294 | 295 | /** 296 | * @brief Clear the specified FLASH flags. 297 | * @param __FLAG__ specifies the FLASH flags to clear. 298 | * This parameter can be any combination of the following values: 299 | * @arg FLASH_FLAG_EOP : FLASH End of Operation flag 300 | * @arg FLASH_FLAG_OPERR : FLASH operation Error flag 301 | * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 302 | * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 303 | * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag 304 | * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag 305 | * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) 306 | * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices 307 | * @retval none 308 | */ 309 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) 310 | /** 311 | * @} 312 | */ 313 | 314 | /* Include FLASH HAL Extension module */ 315 | #include "stm32f4xx_hal_flash_ex.h" 316 | #include "stm32f4xx_hal_flash_ramfunc.h" 317 | 318 | /* Exported functions --------------------------------------------------------*/ 319 | /** @addtogroup FLASH_Exported_Functions 320 | * @{ 321 | */ 322 | /** @addtogroup FLASH_Exported_Functions_Group1 323 | * @{ 324 | */ 325 | /* Program operation functions ***********************************************/ 326 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 327 | HAL_StatusTypeDef HAL_FLASH_Program_IT( 328 | uint32_t TypeProgram, uint32_t Address, uint64_t Data); 329 | /* FLASH IRQ handler method */ 330 | void HAL_FLASH_IRQHandler(void); 331 | /* Callbacks in non blocking modes */ 332 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 333 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 334 | /** 335 | * @} 336 | */ 337 | 338 | /** @addtogroup FLASH_Exported_Functions_Group2 339 | * @{ 340 | */ 341 | /* Peripheral Control functions **********************************************/ 342 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 343 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 344 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 345 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 346 | /* Option bytes control */ 347 | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 348 | /** 349 | * @} 350 | */ 351 | 352 | /** @addtogroup FLASH_Exported_Functions_Group3 353 | * @{ 354 | */ 355 | /* Peripheral State functions ************************************************/ 356 | uint32_t HAL_FLASH_GetError(void); 357 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 358 | /** 359 | * @} 360 | */ 361 | 362 | /** 363 | * @} 364 | */ 365 | /* Private types -------------------------------------------------------------*/ 366 | /* Private variables ---------------------------------------------------------*/ 367 | /** @defgroup FLASH_Private_Variables FLASH Private Variables 368 | * @{ 369 | */ 370 | 371 | /** 372 | * @} 373 | */ 374 | /* Private constants ---------------------------------------------------------*/ 375 | /** @defgroup FLASH_Private_Constants FLASH Private Constants 376 | * @{ 377 | */ 378 | 379 | /** 380 | * @brief ACR register byte 0 (Bits[7:0]) base address 381 | */ 382 | #define ACR_BYTE0_ADDRESS 0x40023C00U 383 | /** 384 | * @brief OPTCR register byte 0 (Bits[7:0]) base address 385 | */ 386 | #define OPTCR_BYTE0_ADDRESS 0x40023C14U 387 | /** 388 | * @brief OPTCR register byte 1 (Bits[15:8]) base address 389 | */ 390 | #define OPTCR_BYTE1_ADDRESS 0x40023C15U 391 | /** 392 | * @brief OPTCR register byte 2 (Bits[23:16]) base address 393 | */ 394 | #define OPTCR_BYTE2_ADDRESS 0x40023C16U 395 | /** 396 | * @brief OPTCR register byte 3 (Bits[31:24]) base address 397 | */ 398 | #define OPTCR_BYTE3_ADDRESS 0x40023C17U 399 | 400 | /** 401 | * @} 402 | */ 403 | 404 | /* Private macros ------------------------------------------------------------*/ 405 | /** @defgroup FLASH_Private_Macros FLASH Private Macros 406 | * @{ 407 | */ 408 | 409 | /** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters 410 | * @{ 411 | */ 412 | #define IS_FLASH_TYPEPROGRAM(VALUE) \ 413 | (((VALUE) == FLASH_TYPEPROGRAM_BYTE) || ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) \ 414 | || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 415 | /** 416 | * @} 417 | */ 418 | 419 | /** 420 | * @} 421 | */ 422 | 423 | /* Private functions ---------------------------------------------------------*/ 424 | /** @defgroup FLASH_Private_Functions FLASH Private Functions 425 | * @{ 426 | */ 427 | 428 | /** 429 | * @} 430 | */ 431 | 432 | /** 433 | * @} 434 | */ 435 | 436 | /** 437 | * @} 438 | */ 439 | 440 | #ifdef __cplusplus 441 | } 442 | #endif 443 | 444 | #endif /* __STM32F4xx_HAL_FLASH_H */ 445 | 446 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 447 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_flash_ramfunc.h 4 | * @author MCD Application Team 5 | * @brief Header file of FLASH RAMFUNC driver. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F4xx_FLASH_RAMFUNC_H 22 | #define __STM32F4xx_FLASH_RAMFUNC_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" 26 | { 27 | #endif 28 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) \ 29 | || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) \ 30 | || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | #include "stm32f4xx_hal_def.h" 34 | 35 | /** @addtogroup STM32F4xx_HAL_Driver 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup FLASH_RAMFUNC 40 | * @{ 41 | */ 42 | 43 | /* Exported types ------------------------------------------------------------*/ 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* Exported functions --------------------------------------------------------*/ 46 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions 47 | * @{ 48 | */ 49 | 50 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 51 | * @{ 52 | */ 53 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); 54 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); 55 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); 56 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); 57 | /** 58 | * @} 59 | */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** 66 | * @} 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || \ 74 | STM32F412Rx || STM32F412Cx */ 75 | #ifdef __cplusplus 76 | } 77 | #endif 78 | 79 | #endif /* __STM32F4xx_FLASH_RAMFUNC_H */ 80 | 81 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 82 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_gpio.h 4 | * @author MCD Application Team 5 | * @brief Header file of GPIO HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F4xx_HAL_GPIO_H 22 | #define __STM32F4xx_HAL_GPIO_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" 26 | { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f4xx_hal_def.h" 31 | 32 | /** @addtogroup STM32F4xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @addtogroup GPIO 37 | * @{ 38 | */ 39 | 40 | /* Exported types ------------------------------------------------------------*/ 41 | /** @defgroup GPIO_Exported_Types GPIO Exported Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief GPIO Init structure definition 47 | */ 48 | typedef struct 49 | { 50 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 51 | This parameter can be any value of @ref GPIO_pins_define */ 52 | 53 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 54 | This parameter can be a value of @ref GPIO_mode_define */ 55 | 56 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected 57 | pins. This parameter can be a value of @ref GPIO_pull_define */ 58 | 59 | uint32_t Speed; /*!< Specifies the speed for the selected pins. 60 | This parameter can be a value of @ref GPIO_speed_define */ 61 | 62 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. 63 | This parameter can be a value of @ref 64 | GPIO_Alternate_function_selection */ 65 | } GPIO_InitTypeDef; 66 | 67 | /** 68 | * @brief GPIO Bit SET and Bit RESET enumeration 69 | */ 70 | typedef enum 71 | { 72 | GPIO_PIN_RESET = 0, 73 | GPIO_PIN_SET 74 | } GPIO_PinState; 75 | /** 76 | * @} 77 | */ 78 | 79 | /* Exported constants --------------------------------------------------------*/ 80 | 81 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants 82 | * @{ 83 | */ 84 | 85 | /** @defgroup GPIO_pins_define GPIO pins define 86 | * @{ 87 | */ 88 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ 89 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ 90 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ 91 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ 92 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ 93 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ 94 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ 95 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ 96 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ 97 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ 98 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ 99 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ 100 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ 101 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ 102 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ 103 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ 104 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ 105 | 106 | #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup GPIO_mode_define GPIO mode define 112 | * @brief GPIO Configuration Mode 113 | * Elements values convention: 0x00WX00YZ 114 | * - W : EXTI trigger detection on 3 bits 115 | * - X : EXTI mode (IT or Event) on 2 bits 116 | * - Y : Output type (Push Pull or Open Drain) on 1 bit 117 | * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits 118 | * @{ 119 | */ 120 | #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ 121 | #define GPIO_MODE_OUTPUT_PP \ 122 | (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ 123 | #define GPIO_MODE_OUTPUT_OD \ 124 | (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ 125 | #define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ 126 | #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ 127 | 128 | #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ 129 | 130 | #define GPIO_MODE_IT_RISING \ 131 | (MODE_INPUT | EXTI_IT \ 132 | | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ 133 | #define GPIO_MODE_IT_FALLING \ 134 | (MODE_INPUT | EXTI_IT \ 135 | | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ 136 | #define GPIO_MODE_IT_RISING_FALLING \ 137 | (MODE_INPUT | EXTI_IT | TRIGGER_RISING \ 138 | | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger \ 139 | detection */ 140 | 141 | #define GPIO_MODE_EVT_RISING \ 142 | (MODE_INPUT | EXTI_EVT \ 143 | | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ 144 | #define GPIO_MODE_EVT_FALLING \ 145 | (MODE_INPUT | EXTI_EVT \ 146 | | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ 147 | #define GPIO_MODE_EVT_RISING_FALLING \ 148 | (MODE_INPUT | EXTI_EVT | TRIGGER_RISING \ 149 | | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection \ 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /** @defgroup GPIO_speed_define GPIO speed define 157 | * @brief GPIO Output Maximum frequency 158 | * @{ 159 | */ 160 | #define GPIO_SPEED_FREQ_LOW \ 161 | 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ 162 | #define GPIO_SPEED_FREQ_MEDIUM \ 163 | 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ 164 | #define GPIO_SPEED_FREQ_HIGH \ 165 | 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ 166 | #define GPIO_SPEED_FREQ_VERY_HIGH \ 167 | 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ 168 | /** 169 | * @} 170 | */ 171 | 172 | /** @defgroup GPIO_pull_define GPIO pull define 173 | * @brief GPIO Pull-Up or Pull-Down Activation 174 | * @{ 175 | */ 176 | #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ 177 | #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ 178 | #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ 179 | /** 180 | * @} 181 | */ 182 | 183 | /** 184 | * @} 185 | */ 186 | 187 | /* Exported macro ------------------------------------------------------------*/ 188 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros 189 | * @{ 190 | */ 191 | 192 | /** 193 | * @brief Checks whether the specified EXTI line flag is set or not. 194 | * @param __EXTI_LINE__ specifies the EXTI line flag to check. 195 | * This parameter can be GPIO_PIN_x where x can be(0..15) 196 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 197 | */ 198 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 199 | 200 | /** 201 | * @brief Clears the EXTI's line pending flags. 202 | * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. 203 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 204 | * @retval None 205 | */ 206 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 207 | 208 | /** 209 | * @brief Checks whether the specified EXTI line is asserted or not. 210 | * @param __EXTI_LINE__ specifies the EXTI line to check. 211 | * This parameter can be GPIO_PIN_x where x can be(0..15) 212 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 213 | */ 214 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) 215 | 216 | /** 217 | * @brief Clears the EXTI's line pending bits. 218 | * @param __EXTI_LINE__ specifies the EXTI lines to clear. 219 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 220 | * @retval None 221 | */ 222 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) 223 | 224 | /** 225 | * @brief Generates a Software interrupt on selected EXTI line. 226 | * @param __EXTI_LINE__ specifies the EXTI line to check. 227 | * This parameter can be GPIO_PIN_x where x can be(0..15) 228 | * @retval None 229 | */ 230 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) 231 | /** 232 | * @} 233 | */ 234 | 235 | /* Include GPIO HAL Extension module */ 236 | #include "stm32f4xx_hal_gpio_ex.h" 237 | 238 | /* Exported functions --------------------------------------------------------*/ 239 | /** @addtogroup GPIO_Exported_Functions 240 | * @{ 241 | */ 242 | 243 | /** @addtogroup GPIO_Exported_Functions_Group1 244 | * @{ 245 | */ 246 | /* Initialization and de-initialization functions *****************************/ 247 | void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_Init); 248 | void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); 249 | /** 250 | * @} 251 | */ 252 | 253 | /** @addtogroup GPIO_Exported_Functions_Group2 254 | * @{ 255 | */ 256 | /* IO operation functions *****************************************************/ 257 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 258 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); 259 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 260 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 261 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); 262 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); 263 | 264 | /** 265 | * @} 266 | */ 267 | 268 | /** 269 | * @} 270 | */ 271 | /* Private types -------------------------------------------------------------*/ 272 | /* Private variables ---------------------------------------------------------*/ 273 | /* Private constants ---------------------------------------------------------*/ 274 | /** @defgroup GPIO_Private_Constants GPIO Private Constants 275 | * @{ 276 | */ 277 | #define GPIO_MODE_Pos 0U 278 | #define GPIO_MODE (0x3UL << GPIO_MODE_Pos) 279 | #define MODE_INPUT (0x0UL << GPIO_MODE_Pos) 280 | #define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) 281 | #define MODE_AF (0x2UL << GPIO_MODE_Pos) 282 | #define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) 283 | #define OUTPUT_TYPE_Pos 4U 284 | #define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) 285 | #define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) 286 | #define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) 287 | #define EXTI_MODE_Pos 16U 288 | #define EXTI_MODE (0x3UL << EXTI_MODE_Pos) 289 | #define EXTI_IT (0x1UL << EXTI_MODE_Pos) 290 | #define EXTI_EVT (0x2UL << EXTI_MODE_Pos) 291 | #define TRIGGER_MODE_Pos 20U 292 | #define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) 293 | #define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) 294 | #define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /* Private macros ------------------------------------------------------------*/ 301 | /** @defgroup GPIO_Private_Macros GPIO Private Macros 302 | * @{ 303 | */ 304 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) 305 | #define IS_GPIO_PIN(PIN) \ 306 | (((((uint32_t)PIN) & GPIO_PIN_MASK) != 0x00U) \ 307 | && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) 308 | #define IS_GPIO_MODE(MODE) \ 309 | (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) \ 310 | || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) \ 311 | || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) \ 312 | || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) \ 313 | || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) \ 314 | || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || ((MODE) == GPIO_MODE_ANALOG)) 315 | #define IS_GPIO_SPEED(SPEED) \ 316 | (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) \ 317 | || ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) 318 | #define IS_GPIO_PULL(PULL) \ 319 | (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN)) 320 | /** 321 | * @} 322 | */ 323 | 324 | /* Private functions ---------------------------------------------------------*/ 325 | /** @defgroup GPIO_Private_Functions GPIO Private Functions 326 | * @{ 327 | */ 328 | 329 | /** 330 | * @} 331 | */ 332 | 333 | /** 334 | * @} 335 | */ 336 | 337 | /** 338 | * @} 339 | */ 340 | 341 | #ifdef __cplusplus 342 | } 343 | #endif 344 | 345 | #endif /* __STM32F4xx_HAL_GPIO_H */ 346 | 347 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 348 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_pwr.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F4xx_HAL_PWR_H 22 | #define __STM32F4xx_HAL_PWR_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" 26 | { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f4xx_hal_def.h" 31 | 32 | /** @addtogroup STM32F4xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @addtogroup PWR 37 | * @{ 38 | */ 39 | 40 | /* Exported types ------------------------------------------------------------*/ 41 | 42 | /** @defgroup PWR_Exported_Types PWR Exported Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief PWR PVD configuration structure definition 48 | */ 49 | typedef struct 50 | { 51 | uint32_t 52 | PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. 53 | This parameter can be a value of @ref PWR_PVD_detection_level */ 54 | 55 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 56 | This parameter can be a value of @ref PWR_PVD_Mode */ 57 | } PWR_PVDTypeDef; 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /* Exported constants --------------------------------------------------------*/ 64 | /** @defgroup PWR_Exported_Constants PWR Exported Constants 65 | * @{ 66 | */ 67 | 68 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins 69 | * @{ 70 | */ 71 | #define PWR_WAKEUP_PIN1 0x00000100U 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level 77 | * @{ 78 | */ 79 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 80 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 81 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 82 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 83 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 84 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 85 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 86 | #define PWR_PVDLEVEL_7 \ 87 | PWR_CR_PLS_LEV7 /* External input analog voltage \ 88 | (Compare internally to VREFINT) */ 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup PWR_PVD_Mode PWR PVD Mode 94 | * @{ 95 | */ 96 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ 97 | #define PWR_PVD_MODE_IT_RISING \ 98 | 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ 99 | #define PWR_PVD_MODE_IT_FALLING \ 100 | 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ 101 | #define PWR_PVD_MODE_IT_RISING_FALLING \ 102 | 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 103 | #define PWR_PVD_MODE_EVENT_RISING \ 104 | 0x00020001U /*!< Event Mode with Rising edge trigger detection */ 105 | #define PWR_PVD_MODE_EVENT_FALLING \ 106 | 0x00020002U /*!< Event Mode with Falling edge trigger detection */ 107 | #define PWR_PVD_MODE_EVENT_RISING_FALLING \ 108 | 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode 114 | * @{ 115 | */ 116 | #define PWR_MAINREGULATOR_ON 0x00000000U 117 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 123 | * @{ 124 | */ 125 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) 126 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) 127 | /** 128 | * @} 129 | */ 130 | 131 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 132 | * @{ 133 | */ 134 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) 135 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) 136 | /** 137 | * @} 138 | */ 139 | 140 | /** @defgroup PWR_Flag PWR Flag 141 | * @{ 142 | */ 143 | #define PWR_FLAG_WU PWR_CSR_WUF 144 | #define PWR_FLAG_SB PWR_CSR_SBF 145 | #define PWR_FLAG_PVDO PWR_CSR_PVDO 146 | #define PWR_FLAG_BRR PWR_CSR_BRR 147 | #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY 148 | /** 149 | * @} 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /* Exported macro ------------------------------------------------------------*/ 157 | /** @defgroup PWR_Exported_Macro PWR Exported Macro 158 | * @{ 159 | */ 160 | 161 | /** @brief Check PWR flag is set or not. 162 | * @param __FLAG__ specifies the flag to check. 163 | * This parameter can be one of the following values: 164 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 165 | * was received from the WKUP pin or from the RTC alarm (Alarm A 166 | * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. 167 | * An additional wakeup event is detected if the WKUP pin is enabled 168 | * (by setting the EWUP bit) when the WKUP pin level is already high. 169 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 170 | * resumed from StandBy mode. 171 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 172 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 173 | * For this reason, this bit is equal to 0 after Standby or reset 174 | * until the PVDE bit is set. 175 | * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 176 | * when the device wakes up from Standby mode or by a system reset 177 | * or power reset. 178 | * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 179 | * scaling output selection is ready. 180 | * @retval The new state of __FLAG__ (TRUE or FALSE). 181 | */ 182 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 183 | 184 | /** @brief Clear the PWR's pending flags. 185 | * @param __FLAG__ specifies the flag to clear. 186 | * This parameter can be one of the following values: 187 | * @arg PWR_FLAG_WU: Wake Up flag 188 | * @arg PWR_FLAG_SB: StandBy flag 189 | */ 190 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) 191 | 192 | /** 193 | * @brief Enable the PVD Exti Line 16. 194 | * @retval None. 195 | */ 196 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) 197 | 198 | /** 199 | * @brief Disable the PVD EXTI Line 16. 200 | * @retval None. 201 | */ 202 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) 203 | 204 | /** 205 | * @brief Enable event on PVD Exti Line 16. 206 | * @retval None. 207 | */ 208 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) 209 | 210 | /** 211 | * @brief Disable event on PVD Exti Line 16. 212 | * @retval None. 213 | */ 214 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) 215 | 216 | /** 217 | * @brief Enable the PVD Extended Interrupt Rising Trigger. 218 | * @retval None. 219 | */ 220 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 221 | 222 | /** 223 | * @brief Disable the PVD Extended Interrupt Rising Trigger. 224 | * @retval None. 225 | */ 226 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 227 | 228 | /** 229 | * @brief Enable the PVD Extended Interrupt Falling Trigger. 230 | * @retval None. 231 | */ 232 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 233 | 234 | /** 235 | * @brief Disable the PVD Extended Interrupt Falling Trigger. 236 | * @retval None. 237 | */ 238 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 239 | 240 | /** 241 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. 242 | * @retval None. 243 | */ 244 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 245 | do \ 246 | { \ 247 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 248 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 249 | } while (0U) 250 | 251 | /** 252 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 253 | * This parameter can be: 254 | * @retval None. 255 | */ 256 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 257 | do \ 258 | { \ 259 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 260 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 261 | } while (0U) 262 | 263 | /** 264 | * @brief checks whether the specified PVD Exti interrupt flag is set or not. 265 | * @retval EXTI PVD Line Status. 266 | */ 267 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 268 | 269 | /** 270 | * @brief Clear the PVD Exti flag. 271 | * @retval None. 272 | */ 273 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 274 | 275 | /** 276 | * @brief Generates a Software interrupt on PVD EXTI line. 277 | * @retval None 278 | */ 279 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) 280 | 281 | /** 282 | * @} 283 | */ 284 | 285 | /* Include PWR HAL Extension module */ 286 | #include "stm32f4xx_hal_pwr_ex.h" 287 | 288 | /* Exported functions --------------------------------------------------------*/ 289 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions 290 | * @{ 291 | */ 292 | 293 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization 294 | * functions 295 | * @{ 296 | */ 297 | /* Initialization and de-initialization functions *****************************/ 298 | void HAL_PWR_DeInit(void); 299 | void HAL_PWR_EnableBkUpAccess(void); 300 | void HAL_PWR_DisableBkUpAccess(void); 301 | /** 302 | * @} 303 | */ 304 | 305 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 306 | * @{ 307 | */ 308 | /* Peripheral Control functions **********************************************/ 309 | /* PVD configuration */ 310 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef* sConfigPVD); 311 | void HAL_PWR_EnablePVD(void); 312 | void HAL_PWR_DisablePVD(void); 313 | 314 | /* WakeUp pins configuration */ 315 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 316 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 317 | 318 | /* Low Power modes entry */ 319 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 320 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 321 | void HAL_PWR_EnterSTANDBYMode(void); 322 | 323 | /* Power PVD IRQ Handler */ 324 | void HAL_PWR_PVD_IRQHandler(void); 325 | void HAL_PWR_PVDCallback(void); 326 | 327 | /* Cortex System Control functions *******************************************/ 328 | void HAL_PWR_EnableSleepOnExit(void); 329 | void HAL_PWR_DisableSleepOnExit(void); 330 | void HAL_PWR_EnableSEVOnPend(void); 331 | void HAL_PWR_DisableSEVOnPend(void); 332 | /** 333 | * @} 334 | */ 335 | 336 | /** 337 | * @} 338 | */ 339 | 340 | /* Private types -------------------------------------------------------------*/ 341 | /* Private variables ---------------------------------------------------------*/ 342 | /* Private constants ---------------------------------------------------------*/ 343 | /** @defgroup PWR_Private_Constants PWR Private Constants 344 | * @{ 345 | */ 346 | 347 | /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line 348 | * @{ 349 | */ 350 | #define PWR_EXTI_LINE_PVD \ 351 | ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line \ 352 | */ 353 | /** 354 | * @} 355 | */ 356 | 357 | /** @defgroup PWR_register_alias_address PWR Register alias address 358 | * @{ 359 | */ 360 | /* ------------- PWR registers bit address in the alias region ---------------*/ 361 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 362 | #define PWR_CR_OFFSET 0x00U 363 | #define PWR_CSR_OFFSET 0x04U 364 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) 365 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) 366 | /** 367 | * @} 368 | */ 369 | 370 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address 371 | * @{ 372 | */ 373 | /* --- CR Register ---*/ 374 | /* Alias word address of DBP bit */ 375 | #define DBP_BIT_NUMBER PWR_CR_DBP_Pos 376 | #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) 377 | 378 | /* Alias word address of PVDE bit */ 379 | #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos 380 | #define CR_PVDE_BB \ 381 | (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) 382 | 383 | /* Alias word address of VOS bit */ 384 | #define VOS_BIT_NUMBER PWR_CR_VOS_Pos 385 | #define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) 386 | /** 387 | * @} 388 | */ 389 | 390 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address 391 | * @{ 392 | */ 393 | /* --- CSR Register ---*/ 394 | /* Alias word address of EWUP bit */ 395 | #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos 396 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) 397 | /** 398 | * @} 399 | */ 400 | 401 | /** 402 | * @} 403 | */ 404 | /* Private macros ------------------------------------------------------------*/ 405 | /** @defgroup PWR_Private_Macros PWR Private Macros 406 | * @{ 407 | */ 408 | 409 | /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters 410 | * @{ 411 | */ 412 | #define IS_PWR_PVD_LEVEL(LEVEL) \ 413 | (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) \ 414 | || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) \ 415 | || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \ 416 | || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 417 | #define IS_PWR_PVD_MODE(MODE) \ 418 | (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) \ 419 | || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \ 420 | || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) \ 421 | || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL)) 422 | #define IS_PWR_REGULATOR(REGULATOR) \ 423 | (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 424 | #define IS_PWR_SLEEP_ENTRY(ENTRY) \ 425 | (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 426 | #define IS_PWR_STOP_ENTRY(ENTRY) \ 427 | (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 428 | /** 429 | * @} 430 | */ 431 | 432 | /** 433 | * @} 434 | */ 435 | 436 | /** 437 | * @} 438 | */ 439 | 440 | /** 441 | * @} 442 | */ 443 | 444 | #ifdef __cplusplus 445 | } 446 | #endif 447 | 448 | #endif /* __STM32F4xx_HAL_PWR_H */ 449 | 450 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 451 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_dma_ex.c 4 | * @author MCD Application Team 5 | * @brief DMA Extension HAL module driver 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the DMA Extension peripheral: 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### How to use this driver ##### 13 | ============================================================================== 14 | [..] 15 | The DMA Extension HAL driver can be used as follows: 16 | (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function 17 | for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. 18 | 19 | -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. 20 | -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. 21 | -@- In Multi (Double) buffer mode, it is possible to update the base address for 22 | the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. 23 | 24 | @endverbatim 25 | ****************************************************************************** 26 | * @attention 27 | * 28 | *

© Copyright (c) 2017 STMicroelectronics. 29 | * All rights reserved.

30 | * 31 | * This software component is licensed by ST under BSD 3-Clause license, 32 | * the "License"; You may not use this file except in compliance with the 33 | * License. You may obtain a copy of the License at: 34 | * opensource.org/licenses/BSD-3-Clause 35 | * 36 | ****************************************************************************** 37 | */ 38 | 39 | /* Includes ------------------------------------------------------------------*/ 40 | #include "stm32f4xx_hal.h" 41 | 42 | /** @addtogroup STM32F4xx_HAL_Driver 43 | * @{ 44 | */ 45 | 46 | /** @defgroup DMAEx DMAEx 47 | * @brief DMA Extended HAL module driver 48 | * @{ 49 | */ 50 | 51 | #ifdef HAL_DMA_MODULE_ENABLED 52 | 53 | /* Private types -------------------------------------------------------------*/ 54 | /* Private variables ---------------------------------------------------------*/ 55 | /* Private Constants ---------------------------------------------------------*/ 56 | /* Private macros ------------------------------------------------------------*/ 57 | /* Private functions ---------------------------------------------------------*/ 58 | /** @addtogroup DMAEx_Private_Functions 59 | * @{ 60 | */ 61 | static void DMA_MultiBufferSetConfig( 62 | DMA_HandleTypeDef* hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 63 | /** 64 | * @} 65 | */ 66 | 67 | /* Exported functions ---------------------------------------------------------*/ 68 | 69 | /** @addtogroup DMAEx_Exported_Functions 70 | * @{ 71 | */ 72 | 73 | /** @addtogroup DMAEx_Exported_Functions_Group1 74 | * 75 | @verbatim 76 | =============================================================================== 77 | ##### Extended features functions ##### 78 | =============================================================================== 79 | [..] This section provides functions allowing to: 80 | (+) Configure the source, destination address and data length and 81 | Start MultiBuffer DMA transfer 82 | (+) Configure the source, destination address and data length and 83 | Start MultiBuffer DMA transfer with interrupt 84 | (+) Change on the fly the memory0 or memory1 address. 85 | 86 | @endverbatim 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @brief Starts the multi_buffer DMA Transfer. 92 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 93 | * the configuration information for the specified DMA Stream. 94 | * @param SrcAddress The source memory Buffer address 95 | * @param DstAddress The destination memory Buffer address 96 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer 97 | * @param DataLength The length of data to be transferred from source to destination 98 | * @retval HAL status 99 | */ 100 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart( 101 | DMA_HandleTypeDef* hdma, 102 | uint32_t SrcAddress, 103 | uint32_t DstAddress, 104 | uint32_t SecondMemAddress, 105 | uint32_t DataLength) 106 | { 107 | HAL_StatusTypeDef status = HAL_OK; 108 | 109 | /* Check the parameters */ 110 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); 111 | 112 | /* Memory-to-memory transfer not supported in double buffering mode */ 113 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 114 | { 115 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; 116 | status = HAL_ERROR; 117 | } 118 | else 119 | { 120 | /* Process Locked */ 121 | __HAL_LOCK(hdma); 122 | 123 | if (HAL_DMA_STATE_READY == hdma->State) 124 | { 125 | /* Change DMA peripheral state */ 126 | hdma->State = HAL_DMA_STATE_BUSY; 127 | 128 | /* Enable the double buffer mode */ 129 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; 130 | 131 | /* Configure DMA Stream destination address */ 132 | hdma->Instance->M1AR = SecondMemAddress; 133 | 134 | /* Configure the source, destination address and the data length */ 135 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 136 | 137 | /* Enable the peripheral */ 138 | __HAL_DMA_ENABLE(hdma); 139 | } 140 | else 141 | { 142 | /* Return error status */ 143 | status = HAL_BUSY; 144 | } 145 | } 146 | return status; 147 | } 148 | 149 | /** 150 | * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. 151 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 152 | * the configuration information for the specified DMA Stream. 153 | * @param SrcAddress The source memory Buffer address 154 | * @param DstAddress The destination memory Buffer address 155 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer 156 | * @param DataLength The length of data to be transferred from source to destination 157 | * @retval HAL status 158 | */ 159 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT( 160 | DMA_HandleTypeDef* hdma, 161 | uint32_t SrcAddress, 162 | uint32_t DstAddress, 163 | uint32_t SecondMemAddress, 164 | uint32_t DataLength) 165 | { 166 | HAL_StatusTypeDef status = HAL_OK; 167 | 168 | /* Check the parameters */ 169 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); 170 | 171 | /* Memory-to-memory transfer not supported in double buffering mode */ 172 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 173 | { 174 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; 175 | return HAL_ERROR; 176 | } 177 | 178 | /* Check callback functions */ 179 | if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) 180 | || (NULL == hdma->XferErrorCallback)) 181 | { 182 | hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 183 | return HAL_ERROR; 184 | } 185 | 186 | /* Process locked */ 187 | __HAL_LOCK(hdma); 188 | 189 | if (HAL_DMA_STATE_READY == hdma->State) 190 | { 191 | /* Change DMA peripheral state */ 192 | hdma->State = HAL_DMA_STATE_BUSY; 193 | 194 | /* Initialize the error code */ 195 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; 196 | 197 | /* Enable the Double buffer mode */ 198 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; 199 | 200 | /* Configure DMA Stream destination address */ 201 | hdma->Instance->M1AR = SecondMemAddress; 202 | 203 | /* Configure the source, destination address and the data length */ 204 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 205 | 206 | /* Clear all flags */ 207 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 208 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 209 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); 210 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); 211 | __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); 212 | 213 | /* Enable Common interrupts*/ 214 | hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; 215 | hdma->Instance->FCR |= DMA_IT_FE; 216 | 217 | if ((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 218 | { 219 | hdma->Instance->CR |= DMA_IT_HT; 220 | } 221 | 222 | /* Enable the peripheral */ 223 | __HAL_DMA_ENABLE(hdma); 224 | } 225 | else 226 | { 227 | /* Process unlocked */ 228 | __HAL_UNLOCK(hdma); 229 | 230 | /* Return error status */ 231 | status = HAL_BUSY; 232 | } 233 | return status; 234 | } 235 | 236 | /** 237 | * @brief Change the memory0 or memory1 address on the fly. 238 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 239 | * the configuration information for the specified DMA Stream. 240 | * @param Address The new address 241 | * @param memory the memory to be changed, This parameter can be one of 242 | * the following values: 243 | * MEMORY0 / 244 | * MEMORY1 245 | * @note The MEMORY0 address can be changed only when the current transfer use 246 | * MEMORY1 and the MEMORY1 address can be changed only when the current 247 | * transfer use MEMORY0. 248 | * @retval HAL status 249 | */ 250 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory( 251 | DMA_HandleTypeDef* hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) 252 | { 253 | if (memory == MEMORY0) 254 | { 255 | /* change the memory0 address */ 256 | hdma->Instance->M0AR = Address; 257 | } 258 | else 259 | { 260 | /* change the memory1 address */ 261 | hdma->Instance->M1AR = Address; 262 | } 263 | 264 | return HAL_OK; 265 | } 266 | 267 | /** 268 | * @} 269 | */ 270 | 271 | /** 272 | * @} 273 | */ 274 | 275 | /** @addtogroup DMAEx_Private_Functions 276 | * @{ 277 | */ 278 | 279 | /** 280 | * @brief Set the DMA Transfer parameter. 281 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 282 | * the configuration information for the specified DMA Stream. 283 | * @param SrcAddress The source memory Buffer address 284 | * @param DstAddress The destination memory Buffer address 285 | * @param DataLength The length of data to be transferred from source to destination 286 | * @retval HAL status 287 | */ 288 | static void DMA_MultiBufferSetConfig( 289 | DMA_HandleTypeDef* hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) 290 | { 291 | /* Configure DMA Stream data length */ 292 | hdma->Instance->NDTR = DataLength; 293 | 294 | /* Peripheral to Memory */ 295 | if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 296 | { 297 | /* Configure DMA Stream destination address */ 298 | hdma->Instance->PAR = DstAddress; 299 | 300 | /* Configure DMA Stream source address */ 301 | hdma->Instance->M0AR = SrcAddress; 302 | } 303 | /* Memory to Peripheral */ 304 | else 305 | { 306 | /* Configure DMA Stream source address */ 307 | hdma->Instance->PAR = SrcAddress; 308 | 309 | /* Configure DMA Stream destination address */ 310 | hdma->Instance->M0AR = DstAddress; 311 | } 312 | } 313 | 314 | /** 315 | * @} 316 | */ 317 | 318 | #endif /* HAL_DMA_MODULE_ENABLED */ 319 | /** 320 | * @} 321 | */ 322 | 323 | /** 324 | * @} 325 | */ 326 | 327 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 328 | -------------------------------------------------------------------------------- /Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_flash_ramfunc.c 4 | * @author MCD Application Team 5 | * @brief FLASH RAMFUNC module driver. 6 | * This file provides a FLASH firmware functions which should be 7 | * executed from internal SRAM 8 | * + Stop/Start the flash interface while System Run 9 | * + Enable/Disable the flash sleep while System Run 10 | @verbatim 11 | ============================================================================== 12 | ##### APIs executed from Internal RAM ##### 13 | ============================================================================== 14 | [..] 15 | *** ARM Compiler *** 16 | -------------------- 17 | [..] RAM functions are defined using the toolchain options. 18 | Functions that are be executed in RAM should reside in a separate 19 | source module. Using the 'Options for File' dialog you can simply change 20 | the 'Code / Const' area of a module to a memory space in physical RAM. 21 | Available memory areas are declared in the 'Target' tab of the 22 | Options for Target' dialog. 23 | 24 | *** ICCARM Compiler *** 25 | ----------------------- 26 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". 27 | 28 | *** GNU Compiler *** 29 | -------------------- 30 | [..] RAM functions are defined using a specific toolchain attribute 31 | "__attribute__((section(".RamFunc")))". 32 | 33 | @endverbatim 34 | ****************************************************************************** 35 | * @attention 36 | * 37 | *

© Copyright (c) 2017 STMicroelectronics. 38 | * All rights reserved.

39 | * 40 | * This software component is licensed by ST under BSD 3-Clause license, 41 | * the "License"; You may not use this file except in compliance with the 42 | * License. You may obtain a copy of the License at: 43 | * opensource.org/licenses/BSD-3-Clause 44 | * 45 | ****************************************************************************** 46 | */ 47 | 48 | /* Includes ------------------------------------------------------------------*/ 49 | #include "stm32f4xx_hal.h" 50 | 51 | /** @addtogroup STM32F4xx_HAL_Driver 52 | * @{ 53 | */ 54 | 55 | /** @defgroup FLASH_RAMFUNC FLASH RAMFUNC 56 | * @brief FLASH functions executed from RAM 57 | * @{ 58 | */ 59 | #ifdef HAL_FLASH_MODULE_ENABLED 60 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) \ 61 | || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) \ 62 | || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 63 | 64 | /* Private typedef -----------------------------------------------------------*/ 65 | /* Private define ------------------------------------------------------------*/ 66 | /* Private macro -------------------------------------------------------------*/ 67 | /* Private variables ---------------------------------------------------------*/ 68 | /* Private function prototypes -----------------------------------------------*/ 69 | /* Exported functions --------------------------------------------------------*/ 70 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions 71 | * @{ 72 | */ 73 | 74 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed 75 | from internal RAM 76 | * @brief Peripheral Extended features functions 77 | * 78 | @verbatim 79 | 80 | =============================================================================== 81 | ##### ramfunc functions ##### 82 | =============================================================================== 83 | [..] 84 | This subsection provides a set of functions that should be executed from RAM 85 | transfers. 86 | 87 | @endverbatim 88 | * @{ 89 | */ 90 | 91 | /** 92 | * @brief Stop the flash interface while System Run 93 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices. 94 | * @note This mode couldn't be set while executing with the flash itself. 95 | * It should be done with specific routine executed from RAM. 96 | * @retval HAL status 97 | */ 98 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) 99 | { 100 | /* Enable Power ctrl clock */ 101 | __HAL_RCC_PWR_CLK_ENABLE(); 102 | /* Stop the flash interface while System Run */ 103 | SET_BIT(PWR->CR, PWR_CR_FISSR); 104 | 105 | return HAL_OK; 106 | } 107 | 108 | /** 109 | * @brief Start the flash interface while System Run 110 | * @note This mode is only available for STM32F411xx/STM32F446xx devices. 111 | * @note This mode couldn't be set while executing with the flash itself. 112 | * It should be done with specific routine executed from RAM. 113 | * @retval HAL status 114 | */ 115 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) 116 | { 117 | /* Enable Power ctrl clock */ 118 | __HAL_RCC_PWR_CLK_ENABLE(); 119 | /* Start the flash interface while System Run */ 120 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR); 121 | 122 | return HAL_OK; 123 | } 124 | 125 | /** 126 | * @brief Enable the flash sleep while System Run 127 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices. 128 | * @note This mode could n't be set while executing with the flash itself. 129 | * It should be done with specific routine executed from RAM. 130 | * @retval HAL status 131 | */ 132 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) 133 | { 134 | /* Enable Power ctrl clock */ 135 | __HAL_RCC_PWR_CLK_ENABLE(); 136 | /* Enable the flash sleep while System Run */ 137 | SET_BIT(PWR->CR, PWR_CR_FMSSR); 138 | 139 | return HAL_OK; 140 | } 141 | 142 | /** 143 | * @brief Disable the flash sleep while System Run 144 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices. 145 | * @note This mode couldn't be set while executing with the flash itself. 146 | * It should be done with specific routine executed from RAM. 147 | * @retval HAL status 148 | */ 149 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) 150 | { 151 | /* Enable Power ctrl clock */ 152 | __HAL_RCC_PWR_CLK_ENABLE(); 153 | /* Disable the flash sleep while System Run */ 154 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); 155 | 156 | return HAL_OK; 157 | } 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || \ 168 | STM32F412Rx || STM32F412Cx */ 169 | #endif /* HAL_FLASH_MODULE_ENABLED */ 170 | /** 171 | * @} 172 | */ 173 | 174 | /** 175 | * @} 176 | */ 177 | 178 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 179 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: all build cmake clean format 2 | 3 | BUILD_DIR := build 4 | BUILD_TYPE ?= Debug 5 | 6 | all: build 7 | 8 | ${BUILD_DIR}/Makefile: 9 | cmake \ 10 | -B${BUILD_DIR} \ 11 | -DCMAKE_BUILD_TYPE=${BUILD_TYPE} \ 12 | -DCMAKE_TOOLCHAIN_FILE=gcc-arm-none-eabi.cmake \ 13 | -DCMAKE_EXPORT_COMPILE_COMMANDS=ON \ 14 | -DDUMP_ASM=OFF 15 | 16 | cmake: ${BUILD_DIR}/Makefile 17 | 18 | build: cmake 19 | $(MAKE) -C ${BUILD_DIR} --no-print-directory 20 | 21 | SRCS := $(shell find . -name '*.[ch]' -or -name '*.[ch]pp') 22 | %.format: % 23 | clang-format -i $< 24 | format: $(addsuffix .format, ${SRCS}) 25 | 26 | clean: 27 | rm -rf $(BUILD_DIR) 28 | -------------------------------------------------------------------------------- /Project/projectMain.cpp: -------------------------------------------------------------------------------- 1 | #include "main.h" 2 | #include 3 | 4 | struct Led 5 | { 6 | explicit Led(GPIO_TypeDef* t_gpio, uint16_t t_pin) 7 | : gpio(t_gpio) 8 | , pin(t_pin) 9 | { 10 | } 11 | void on() 12 | { 13 | HAL_GPIO_WritePin(gpio, pin, GPIO_PIN_SET); 14 | } 15 | void off() 16 | { 17 | HAL_GPIO_WritePin(gpio, pin, GPIO_PIN_RESET); 18 | } 19 | void toggle() 20 | { 21 | HAL_GPIO_TogglePin(gpio, pin); 22 | } 23 | auto state() -> bool 24 | { 25 | return HAL_GPIO_ReadPin(gpio, pin); 26 | } 27 | 28 | private: 29 | GPIO_TypeDef* gpio; 30 | uint16_t pin; 31 | }; 32 | 33 | void projectMain() 34 | { 35 | Led led(GPIOD, GPIO_PIN_15); 36 | 37 | while (true) 38 | { 39 | led.toggle(); 40 | HAL_Delay(500); 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /Project/projectMain.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #ifdef __cplusplus 4 | extern "C" 5 | { 6 | #endif 7 | 8 | void projectMain(); 9 | 10 | #ifdef __cplusplus 11 | } 12 | #endif 13 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32 CMake project template 2 | 3 | This repository is not maintained anymore and is here for youtube viewers. New version of this repository is available [here](https://github.com/prtzl/stm32). 4 | 5 | ## Dependencies 6 | 7 | ```shell 8 | git 9 | gnumake 10 | cmake 11 | gcc-arm-embedded 12 | clang-tools (optional) 13 | ``` 14 | 15 | I would recommend gcc-10.3.y for latest C++20 features. Versions 9.x.y will still do C++20 but with a limited feature set. If you have newer, then go for it. 16 | 17 | You can download arm-none-eabi toolchain from [website](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads). It is universal for most distros. If your distribution carries it, install it with that, but mind the version and compatability. 18 | 19 | Fedora 35 comes with latest gcc-11 with these packages: 20 | 21 | ```shell 22 | arm-none-eabi-gcc-cs 23 | arm-none-eabi-gcc-cs-c++ 24 | arm-none-eabi-newlib 25 | ``` 26 | 27 | Fedora does not have gdb in its packages, so you might want to download that separately. 28 | 29 | On ubuntu 20.04 LTS you can install all with just one package, but comes with older gcc-9, which does not support all the C++20 features: 30 | 31 | ```shell 32 | gcc-arm-none-eabi 33 | ``` 34 | 35 | Arch has gcc-11 and you can install it with following packages: 36 | 37 | ```shell 38 | arm-none-eabi-gcc 39 | arm-none-eabi-newlib 40 | 41 | optional: 42 | arm-none-eabi-gdb (debugger) 43 | arm-none-eabi-binutils (utilities) 44 | ``` 45 | 46 | **NOTE**. If your cmake fails to "compile a simple test program" while running the example, then you might not have `newlib` installed (one of the errors I have encountered). In the examples above, fedora and arch carry the package separately, but ubuntu has it all in one. 47 | 48 | ## Example 49 | You can utilize everything in root of the repository to build an example project. 50 | 51 | ## Workflow 52 | 53 | Output files will be located, by default, in `build`. You can change that with `BUILD_DIR` parameter in the [Makefile](Makefile). 54 | 55 | Just run cmake: 56 | 57 | ```shell 58 | make cmake 59 | ``` 60 | 61 | Run cmake and build: 62 | 63 | ```shell 64 | make -j 65 | ``` 66 | 67 | Clean: 68 | 69 | ```shell 70 | make clean 71 | ``` 72 | 73 | Format all source files: 74 | 75 | ```shell 76 | make format -j 77 | ``` 78 | -------------------------------------------------------------------------------- /STM32-project-template.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | Mcu.Family=STM32F4 3 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE 4 | ProjectManager.MainLocation=Core/Src 5 | ProjectManager.ProjectFileName=STM32-project-template.ioc 6 | PH0-OSC_IN.Signal=RCC_OSC_IN 7 | RCC.CortexFreq_Value=168000000 8 | ProjectManager.KeepUserCode=true 9 | Mcu.UserName=STM32F407VGTx 10 | Mcu.PinsNb=4 11 | ProjectManager.NoMain=false 12 | RCC.PLLCLKFreq_Value=168000000 13 | RCC.PLLQCLKFreq_Value=84000000 14 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false 15 | RCC.RTCFreq_Value=32000 16 | ProjectManager.DefaultFWLocation=true 17 | ProjectManager.DeletePrevious=true 18 | RCC.APB1CLKDivider=RCC_HCLK_DIV4 19 | PinOutPanel.RotationAngle=0 20 | RCC.FamilyName=M 21 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 22 | ProjectManager.StackSize=0x400 23 | RCC.FCLKCortexFreq_Value=168000000 24 | Mcu.IP2=SYS 25 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false 26 | Mcu.IP0=NVIC 27 | Mcu.IP1=RCC 28 | Mcu.UserConstants= 29 | ProjectManager.TargetToolchain=Makefile 30 | Mcu.ThirdPartyNb=0 31 | RCC.HCLKFreq_Value=168000000 32 | Mcu.IPNb=3 33 | RCC.I2SClocksFreq_Value=192000000 34 | ProjectManager.PreviousToolchain= 35 | RCC.APB2TimFreq_Value=84000000 36 | RCC.VcooutputI2S=192000000 37 | ProjectManager.RegisterCallBack= 38 | RCC.LSE_VALUE=32768 39 | RCC.AHBFreq_Value=168000000 40 | PH0-OSC_IN.Mode=HSE-External-Oscillator 41 | Mcu.Pin0=PH0-OSC_IN 42 | Mcu.Pin1=PH1-OSC_OUT 43 | GPIO.groupedBy= 44 | Mcu.Pin2=PD15 45 | Mcu.Pin3=VP_SYS_VS_Systick 46 | RCC.VCOI2SOutputFreq_Value=384000000 47 | ProjectManager.ProjectBuild=false 48 | RCC.HSE_VALUE=8000000 49 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 50 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false 51 | board=custom 52 | RCC.VCOOutputFreq_Value=336000000 53 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true 54 | ProjectManager.LastFirmware=true 55 | ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.26.2 56 | MxDb.Version=DB.6.0.21 57 | RCC.APB2Freq_Value=42000000 58 | ProjectManager.BackupPrevious=false 59 | MxCube.Version=6.2.1 60 | RCC.VCOInputFreq_Value=2000000 61 | File.Version=6 62 | VP_SYS_VS_Systick.Mode=SysTick 63 | RCC.EthernetFreq_Value=168000000 64 | PH1-OSC_OUT.Signal=RCC_OSC_OUT 65 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false 66 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false 67 | ProjectManager.FreePins=false 68 | RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S 69 | ProjectManager.AskForMigrate=true 70 | Mcu.Name=STM32F407V(E-G)Tx 71 | ProjectManager.HalAssertFull=false 72 | RCC.RTCHSEDivFreq_Value=4000000 73 | ProjectManager.ProjectName=STM32-project-template 74 | ProjectManager.UnderRoot=false 75 | ProjectManager.CoupleFile=true 76 | PH1-OSC_OUT.Mode=HSE-External-Oscillator 77 | RCC.48MHZClocksFreq_Value=84000000 78 | RCC.MCO2PinFreq_Value=168000000 79 | RCC.SYSCLKFreq_VALUE=168000000 80 | Mcu.Package=LQFP100 81 | NVIC.ForceEnableDMAVector=true 82 | KeepUserPlacement=false 83 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false 84 | ProjectManager.CompilerOptimize=6 85 | ProjectManager.ToolChainLocation=CubeMX 86 | RCC.LSI_VALUE=32000 87 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 88 | ProjectManager.HeapSize=0x200 89 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 90 | ProjectManager.ComputerToolchain=false 91 | RCC.HSI_VALUE=16000000 92 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 93 | RCC.APB2CLKDivider=RCC_HCLK_DIV4 94 | RCC.PLLM=4 95 | RCC.PLLN=168 96 | RCC.APB1TimFreq_Value=84000000 97 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 98 | RCC.APB1Freq_Value=42000000 99 | PD15.Signal=GPIO_Output 100 | ProjectManager.CustomerFirmwarePackage= 101 | ProjectManager.DeviceId=STM32F407VGTx 102 | ProjectManager.LibraryCopy=1 103 | -------------------------------------------------------------------------------- /default.nix: -------------------------------------------------------------------------------- 1 | with (import {}); 2 | 3 | stdenv.mkDerivation { 4 | name = "STM32"; 5 | 6 | nativeBuildInputs = with pkgs; [ 7 | clang-tools 8 | cmake 9 | gcc-arm-embedded 10 | git 11 | gnumake 12 | ]; 13 | } 14 | -------------------------------------------------------------------------------- /gcc-arm-none-eabi.cmake: -------------------------------------------------------------------------------- 1 | set(CMAKE_SYSTEM_NAME Generic) 2 | set(CMAKE_SYSTEM_PROCESSOR arm) 3 | 4 | set(TOOLCHAIN_PREFIX arm-none-eabi-) 5 | set(FLAGS 6 | "-fdata-sections -ffunction-sections --specs=nano.specs -Wl,--gc-sections") 7 | set(CPP_FLAGS 8 | "-fno-rtti -fno-exceptions -fno-threadsafe-statics") 9 | 10 | set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc ${FLAGS}) 11 | set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) 12 | set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++ ${FLAGS} ${CPP_FLAGS}) 13 | set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) 14 | set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) 15 | set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}objdump) 16 | 17 | set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") 18 | set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") 19 | set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") 20 | 21 | set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) 22 | --------------------------------------------------------------------------------