├── Bender.yml ├── CHANGELOG.md ├── LICENSE ├── README.md ├── src ├── apb_timer.sv └── timer.sv └── src_files.yml /Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: apb_timer 3 | authors: ["Florian Zaruba "] 4 | 5 | sources: 6 | # Level 0 7 | - src/timer.sv 8 | # Level 1 9 | - src/apb_timer.sv 10 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | All notable changes to this project will be documented in this file. 3 | 4 | The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) 5 | and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). 6 | 7 | ## Unreleased 8 | ### Added 9 | ### Fixed 10 | 11 | ## 0.1.0 - 2020-02-03 12 | ### Fixed 13 | - Move RTL to `src` 14 | 15 | ### Added 16 | - Add Bender.yml 17 | - Add CHANGELOG.md 18 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | SOLDERPAD HARDWARE LICENSE version 0.51 2 | 3 | This license is based closely on the Apache License Version 2.0, but is not 4 | approved or endorsed by the Apache Foundation. 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Each timer has three 5 | registers, the timer register, the timer compare register and the timer control 6 | register. 7 | -------------------------------------------------------------------------------- /src/apb_timer.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2015 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | `define REGS_MAX_ADR 2'd2 12 | 13 | module apb_timer 14 | #( 15 | parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default 16 | parameter TIMER_CNT = 2 // how many timers should be instantiated 17 | ) 18 | ( 19 | input logic HCLK, 20 | input logic HRESETn, 21 | input logic [APB_ADDR_WIDTH-1:0] PADDR, 22 | input logic [31:0] PWDATA, 23 | input logic PWRITE, 24 | input logic PSEL, 25 | input logic PENABLE, 26 | output logic [31:0] PRDATA, 27 | output logic PREADY, 28 | output logic PSLVERR, 29 | 30 | output logic [(TIMER_CNT * 2) - 1:0] irq_o // overflow and cmp interrupt 31 | ); 32 | 33 | logic [TIMER_CNT-1:0] psel_int, pready, pslverr; 34 | logic [$clog2(TIMER_CNT) - 1:0] slave_address_int; 35 | logic [TIMER_CNT-1:0] [31:0] prdata; 36 | 37 | assign slave_address_int = PADDR[$clog2(TIMER_CNT)+ `REGS_MAX_ADR + 1:`REGS_MAX_ADR + 2]; 38 | 39 | always_comb 40 | begin 41 | psel_int = '0; 42 | psel_int[slave_address_int] = PSEL; 43 | end 44 | 45 | // output mux 46 | always_comb 47 | begin 48 | 49 | if (psel_int != '0) 50 | begin 51 | PRDATA = prdata[slave_address_int]; 52 | PREADY = pready[slave_address_int]; 53 | PSLVERR = pslverr[slave_address_int]; 54 | end 55 | else 56 | begin 57 | PRDATA = '0; 58 | PREADY = 1'b1; 59 | PSLVERR = 1'b0; 60 | end 61 | end 62 | 63 | 64 | genvar k; 65 | 66 | generate 67 | for(k = 0; k < TIMER_CNT; k++) 68 | begin : TIMER_GEN 69 | timer #( 70 | .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ) 71 | ) timer_i ( 72 | .HCLK ( HCLK ), 73 | .HRESETn ( HRESETn ), 74 | 75 | .PADDR ( PADDR ), 76 | .PWDATA ( PWDATA ), 77 | .PWRITE ( PWRITE ), 78 | .PSEL ( psel_int[k] ), 79 | .PENABLE ( PENABLE ), 80 | .PRDATA ( prdata[k] ), 81 | .PREADY ( pready[k] ), 82 | .PSLVERR ( pslverr[k] ), 83 | 84 | .irq_o ( irq_o[2*k+1 : 2*k] ) 85 | ); 86 | end 87 | endgenerate 88 | endmodule 89 | -------------------------------------------------------------------------------- /src/timer.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2015 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // define three registers per timer - timer, cmp and prescaler registers 12 | `define REGS_MAX_IDX 'd2 13 | `define REG_TIMER 2'b00 14 | `define REG_TIMER_CTRL 2'b01 15 | `define REG_CMP 2'b10 16 | `define PRESCALER_STARTBIT 'd3 17 | `define PRESCALER_STOPBIT 'd5 18 | `define ENABLE_BIT 'd0 19 | 20 | module timer 21 | #( 22 | parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default 23 | ) 24 | ( 25 | input logic HCLK, 26 | input logic HRESETn, 27 | input logic [APB_ADDR_WIDTH-1:0] PADDR, 28 | input logic [31:0] PWDATA, 29 | input logic PWRITE, 30 | input logic PSEL, 31 | input logic PENABLE, 32 | output logic [31:0] PRDATA, 33 | output logic PREADY, 34 | output logic PSLVERR, 35 | 36 | output logic [1:0] irq_o // overflow and cmp interrupt 37 | ); 38 | 39 | // APB register interface 40 | logic [`REGS_MAX_IDX-1:0] register_adr; 41 | assign register_adr = PADDR[`REGS_MAX_IDX + 2:2]; 42 | // APB logic: we are always ready to capture the data into our regs 43 | // not supporting transfare failure 44 | assign PREADY = 1'b1; 45 | assign PSLVERR = 1'b0; 46 | // registers 47 | logic [0:`REGS_MAX_IDX] [31:0] regs_q, regs_n; 48 | logic [31:0] cycle_counter_n, cycle_counter_q; 49 | 50 | logic [2:0] prescaler_int; 51 | 52 | //irq logic 53 | always_comb 54 | begin 55 | irq_o = 2'b0; 56 | 57 | // overlow irq 58 | if (regs_q[`REG_TIMER] == 32'hffff_ffff) 59 | irq_o[0] = 1'b1; 60 | 61 | // compare match irq if compare reg ist set 62 | if (regs_q[`REG_CMP] != 'b0 && regs_q[`REG_TIMER] == regs_q[`REG_CMP]) 63 | irq_o[1] = 1'b1; 64 | 65 | end 66 | 67 | assign prescaler_int = regs_q[`REG_TIMER_CTRL][`PRESCALER_STOPBIT:`PRESCALER_STARTBIT]; 68 | // register write logic 69 | always_comb 70 | begin 71 | regs_n = regs_q; 72 | cycle_counter_n = cycle_counter_q + 1; 73 | 74 | // reset timer after cmp or overflow 75 | if (irq_o[0] == 1'b1 || irq_o[1] == 1'b1) 76 | regs_n[`REG_TIMER] = 1'b0; 77 | else if(regs_q[`REG_TIMER_CTRL][`ENABLE_BIT] && prescaler_int != 'b0 && prescaler_int == cycle_counter_q) // prescaler 78 | begin 79 | regs_n[`REG_TIMER] = regs_q[`REG_TIMER] + 1; //prescaler mode 80 | end 81 | else if (regs_q[`REG_TIMER_CTRL][`ENABLE_BIT] && regs_q[`REG_TIMER_CTRL][`PRESCALER_STOPBIT:`PRESCALER_STARTBIT] == 'b0) // normal count mode 82 | regs_n[`REG_TIMER] = regs_q[`REG_TIMER] + 1; 83 | 84 | // reset prescaler cycle counter 85 | if (cycle_counter_q >= regs_q[`REG_TIMER_CTRL]) 86 | cycle_counter_n = 32'b0; 87 | 88 | // written from APB bus - gets priority 89 | if (PSEL && PENABLE && PWRITE) 90 | begin 91 | 92 | case (register_adr) 93 | `REG_TIMER: 94 | regs_n[`REG_TIMER] = PWDATA; 95 | 96 | `REG_TIMER_CTRL: 97 | regs_n[`REG_TIMER_CTRL] = PWDATA; 98 | 99 | `REG_CMP: 100 | begin 101 | regs_n[`REG_CMP] = PWDATA; 102 | regs_n[`REG_TIMER] = 32'b0; // reset timer if compare register is written 103 | end 104 | endcase 105 | end 106 | end 107 | 108 | // APB register read logic 109 | always_comb 110 | begin 111 | PRDATA = 'b0; 112 | 113 | if (PSEL && PENABLE && !PWRITE) 114 | begin 115 | 116 | case (register_adr) 117 | `REG_TIMER: 118 | PRDATA = regs_q[`REG_TIMER]; 119 | 120 | `REG_TIMER_CTRL: 121 | PRDATA = regs_q[`REG_TIMER_CTRL]; 122 | 123 | `REG_CMP: 124 | PRDATA = regs_q[`REG_CMP]; 125 | endcase 126 | 127 | end 128 | end 129 | // synchronouse part 130 | always_ff @(posedge HCLK, negedge HRESETn) 131 | begin 132 | if(~HRESETn) 133 | begin 134 | regs_q <= '{default: 32'b0}; 135 | cycle_counter_q <= 32'b0; 136 | end 137 | else 138 | begin 139 | regs_q <= regs_n; 140 | cycle_counter_q <= cycle_counter_n; 141 | end 142 | end 143 | 144 | 145 | endmodule 146 | -------------------------------------------------------------------------------- /src_files.yml: -------------------------------------------------------------------------------- 1 | apb_timer: 2 | files: [ 3 | src/apb_timer.sv, 4 | src/timer.sv, 5 | ] 6 | --------------------------------------------------------------------------------