├── .gitignore ├── .gitmodules ├── Bender.yml ├── LICENSE ├── doc └── tcdm_interconnect │ ├── bfly_net.pdf │ ├── bfly_net.png │ ├── clos_net.pdf │ ├── clos_net.png │ ├── xbar.pdf │ └── xbar.png ├── rtl ├── core_demux │ └── CORE_DEMUX.v ├── low_latency_interco │ ├── AddressDecoder_Req.sv │ ├── AddressDecoder_Resp.sv │ ├── ArbitrationTree.sv │ ├── FanInPrimitive_Req.sv │ ├── FanInPrimitive_Resp.sv │ ├── MUX2_REQ.sv │ ├── RequestBlock1CH.sv │ ├── RequestBlock2CH.sv │ ├── ResponseBlock.sv │ ├── ResponseTree.sv │ ├── TCDM_PIPE_REQ.sv │ ├── TCDM_PIPE_RESP.sv │ ├── TestAndSet.sv │ ├── XBAR_TCDM.sv │ ├── XBAR_TCDM_WRAPPER.sv │ ├── grant_mask.sv │ ├── parameters.v │ ├── priority_Flag_Req.sv │ └── tcdm_xbar_wrap.sv ├── peripheral_interco │ ├── AddressDecoder_PE_Req.sv │ ├── AddressDecoder_Resp_PE.sv │ ├── ArbitrationTree_PE.sv │ ├── FanInPrimitive_PE_Resp.sv │ ├── FanInPrimitive_Req_PE.sv │ ├── MUX2_REQ_PE.sv │ ├── RR_Flag_Req_PE.sv │ ├── RequestBlock1CH_PE.sv │ ├── RequestBlock2CH_PE.sv │ ├── ResponseBlock_PE.sv │ ├── ResponseTree_PE.sv │ ├── XBAR_PE.sv │ └── parameters.v ├── tcdm_interconnect │ ├── README.md │ ├── addr_dec_resp_mux.sv │ ├── amo_shim.sv │ ├── bfly_net.sv │ ├── clos_net.sv │ ├── tcdm_interconnect.sv │ ├── tcdm_interconnect_pkg.sv │ └── xbar.sv └── variable_latency_interconnect │ ├── addr_decoder.sv │ ├── full_duplex_xbar.sv │ ├── simplex_xbar.sv │ ├── variable_latency_bfly_net.sv │ └── variable_latency_interconnect.sv ├── src_files.yml └── tb ├── common └── tb.svh ├── tb_tcdm_interconnect ├── .gitignore ├── Makefile ├── README.md ├── hdl │ ├── defaults.svh │ ├── tb.sv │ ├── tb_patterns.sv │ ├── tb_pkg.sv │ └── tcdm_interconnect_wrap.sv ├── matlab │ ├── clos_cost.m │ ├── evaluation.m │ ├── fairness_test.m │ ├── gen_clos_params.m │ ├── plot_scaling.m │ ├── plot_tests.m │ ├── read_stats.m │ ├── read_synth.m │ └── scatterplot_tests.m ├── plots │ ├── pareto_random_linear_128x.pdf │ ├── pareto_random_linear_128x.png │ ├── pareto_random_linear_16x.pdf │ ├── pareto_random_linear_16x.png │ ├── pareto_random_linear_256x.pdf │ ├── pareto_random_linear_256x.png │ ├── pareto_random_linear_32x.pdf │ ├── pareto_random_linear_32x.png │ ├── pareto_random_linear_64x.pdf │ ├── pareto_random_linear_64x.png │ ├── pareto_random_linear_8x.pdf │ ├── pareto_random_linear_8x.png │ ├── pareto_random_uniform_128x.pdf │ ├── pareto_random_uniform_128x.png │ ├── pareto_random_uniform_16x.pdf │ ├── pareto_random_uniform_16x.png │ ├── pareto_random_uniform_256x.pdf │ ├── pareto_random_uniform_256x.png │ ├── pareto_random_uniform_32x.pdf │ ├── pareto_random_uniform_32x.png │ ├── pareto_random_uniform_64x.pdf │ ├── pareto_random_uniform_64x.png │ ├── pareto_random_uniform_8x.pdf │ ├── pareto_random_uniform_8x.png │ ├── scaling_bf1.pdf │ ├── scaling_bf1.png │ ├── scaling_bf2.pdf │ ├── scaling_bf2.png │ ├── scaling_bf4.pdf │ ├── scaling_bf4.png │ ├── stats.mat │ ├── stats_bf2_64x.pdf │ ├── stats_bf2_64x.png │ ├── stats_clos_32x.pdf │ ├── stats_clos_32x.png │ ├── stats_selection_128x.pdf │ ├── stats_selection_128x.png │ ├── stats_selection_16x.pdf │ ├── stats_selection_16x.png │ ├── stats_selection_256x.pdf │ ├── stats_selection_256x.png │ ├── stats_selection_32x.pdf │ ├── stats_selection_32x.png │ ├── stats_selection_64x.pdf │ ├── stats_selection_64x.png │ ├── stats_selection_8x.pdf │ └── stats_selection_8x.png └── scripts │ ├── batch-clos.list │ ├── batch.list │ ├── src.list │ ├── synth.list │ ├── synth.tcl │ └── tb-src.list └── tb_variable_latency_interconnect ├── .gitignore ├── Makefile ├── hdl ├── defaults.svh ├── tb_patterns.sv ├── tb_pkg.sv ├── variable_latency_interconnect_tb.sv └── variable_latency_interconnect_wrap.sv ├── matlab ├── evaluation.m ├── export_fig ├── fairness_test.m ├── plot_scaling.m ├── plot_tests.m ├── read_stats.m ├── read_synth.m └── scatterplot_tests.m └── scripts ├── batch.list ├── src.list ├── synth.list └── tb-src.list /.gitignore: -------------------------------------------------------------------------------- 1 | .bender 2 | Bender.lock 3 | build/ 4 | deps 5 | *dvt* 6 | .project 7 | tech/* 8 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "tb/tb_tcdm_interconnect/matlab/export_fig"] 2 | path = tb/tb_tcdm_interconnect/matlab/export_fig 3 | url = https://github.com/altmany/export_fig.git 4 | -------------------------------------------------------------------------------- /Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: cluster_interconnect 3 | 4 | dependencies: 5 | common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } 6 | 7 | workspace: 8 | checkout_dir: "./deps" 9 | 10 | export_include_dirs: 11 | - rtl/low_latency_interco 12 | - rtl/peripheral_interco 13 | 14 | sources: 15 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this 16 | # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 17 | # levels 1 and 0, etc. Files within a level are ordered alphabetically. 18 | # Level 0 19 | - rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv 20 | - rtl/tcdm_interconnect/addr_dec_resp_mux.sv 21 | - rtl/tcdm_interconnect/amo_shim.sv 22 | - rtl/variable_latency_interconnect/addr_decoder.sv 23 | # Level 1 24 | - rtl/tcdm_interconnect/xbar.sv 25 | - rtl/variable_latency_interconnect/simplex_xbar.sv 26 | # Level 2 27 | - rtl/tcdm_interconnect/clos_net.sv 28 | - rtl/tcdm_interconnect/bfly_net.sv 29 | - rtl/variable_latency_interconnect/full_duplex_xbar.sv 30 | # Level 3 31 | - rtl/tcdm_interconnect/tcdm_interconnect.sv 32 | - rtl/variable_latency_interconnect/variable_latency_bfly_net.sv 33 | # Level 4 34 | - rtl/variable_latency_interconnect/variable_latency_interconnect.sv 35 | 36 | # Low-Latency Interco 37 | - rtl/low_latency_interco/FanInPrimitive_Req.sv 38 | - rtl/low_latency_interco/ArbitrationTree.sv 39 | - rtl/low_latency_interco/MUX2_REQ.sv 40 | - rtl/low_latency_interco/AddressDecoder_Resp.sv 41 | - rtl/low_latency_interco/TestAndSet.sv 42 | - rtl/low_latency_interco/RequestBlock2CH.sv 43 | - rtl/low_latency_interco/RequestBlock1CH.sv 44 | - rtl/low_latency_interco/FanInPrimitive_Resp.sv 45 | - rtl/low_latency_interco/ResponseTree.sv 46 | - rtl/low_latency_interco/ResponseBlock.sv 47 | - rtl/low_latency_interco/AddressDecoder_Req.sv 48 | - rtl/low_latency_interco/XBAR_TCDM.sv 49 | - rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv 50 | - rtl/low_latency_interco/TCDM_PIPE_REQ.sv 51 | - rtl/low_latency_interco/TCDM_PIPE_RESP.sv 52 | - rtl/low_latency_interco/grant_mask.sv 53 | - rtl/low_latency_interco/priority_Flag_Req.sv 54 | 55 | # Peripheral Interco 56 | - rtl/peripheral_interco/AddressDecoder_PE_Req.sv 57 | - rtl/peripheral_interco/AddressDecoder_Resp_PE.sv 58 | - rtl/peripheral_interco/ArbitrationTree_PE.sv 59 | - rtl/peripheral_interco/FanInPrimitive_Req_PE.sv 60 | - rtl/peripheral_interco/RR_Flag_Req_PE.sv 61 | - rtl/peripheral_interco/MUX2_REQ_PE.sv 62 | - rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv 63 | - rtl/peripheral_interco/RequestBlock1CH_PE.sv 64 | - rtl/peripheral_interco/RequestBlock2CH_PE.sv 65 | - rtl/peripheral_interco/ResponseBlock_PE.sv 66 | - rtl/peripheral_interco/ResponseTree_PE.sv 67 | - rtl/peripheral_interco/XBAR_PE.sv 68 | 69 | - target: tcdm_test 70 | include_dirs: 71 | - tb/common/ 72 | - tb/tb_tcdm_interconnect/hdl 73 | files: 74 | # Level 0 75 | - tb/tb_tcdm_interconnect/hdl/tb_pkg.sv 76 | # Level 2 77 | - tb/tb_tcdm_interconnect/hdl/tcdm_interconnect_wrap.sv 78 | # Level 2 79 | - tb/tb_tcdm_interconnect/hdl/tb.sv 80 | 81 | - target: variable_latency_test 82 | include_dirs: 83 | - tb/common/ 84 | - tb/tb_variable_latency_interconnect/hdl 85 | files: 86 | # Level 0 87 | - tb/tb_variable_latency_interconnect/hdl/tb_pkg.sv 88 | # Level 2 89 | - tb/tb_variable_latency_interconnect/hdl/variable_latency_interconnect_wrap.sv 90 | # Level 2 91 | - tb/tb_variable_latency_interconnect/hdl/variable_latency_interconnect_tb.sv 92 | -------------------------------------------------------------------------------- /doc/tcdm_interconnect/bfly_net.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/doc/tcdm_interconnect/bfly_net.pdf -------------------------------------------------------------------------------- /doc/tcdm_interconnect/bfly_net.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/doc/tcdm_interconnect/bfly_net.png -------------------------------------------------------------------------------- /doc/tcdm_interconnect/clos_net.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/doc/tcdm_interconnect/clos_net.pdf -------------------------------------------------------------------------------- /doc/tcdm_interconnect/clos_net.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/doc/tcdm_interconnect/clos_net.png -------------------------------------------------------------------------------- /doc/tcdm_interconnect/xbar.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/doc/tcdm_interconnect/xbar.pdf -------------------------------------------------------------------------------- /doc/tcdm_interconnect/xbar.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/doc/tcdm_interconnect/xbar.png -------------------------------------------------------------------------------- /rtl/low_latency_interco/AddressDecoder_Req.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 06/07/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: AddressDecoder_Req // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Address Decoder used to generate the individual requests // 30 | // for all the available memory cuts. It backroutes the // 31 | // stalls from the Arbitration tree to the processor // 32 | // // 33 | // // 34 | // Revision: // 35 | // Revision v0.1 - 06/07/2011 : File Created // 36 | // v0.2 - 14/08/2012 : Changed the Routing mechanism, added dual // 37 | // Flow COntrol support (Grant or stall) // 38 | // Revision v0.1 -19/02/2015 : Code Restyling // 39 | // Additional Comments: // 40 | // // 41 | // // 42 | // // 43 | // // 44 | //////////////////////////////////////////////////////////////////////////////// 45 | `include "parameters.v" 46 | 47 | module AddressDecoder_Req 48 | #( 49 | parameter ID_WIDTH = 16, // ID WIDTH (number of bits) --> see ID comment 50 | parameter ID = 1, // ID routed with REQUEST used to backroute response 51 | parameter N_SLAVE = 32, // Number of Memory cuts 52 | parameter ROUT_WIDTH = `log2_non_zero(N_SLAVE-1) // 53 | ) 54 | ( 55 | // MASTER SIDE 56 | input logic data_req_i, // Request from Master COre 57 | input logic [ROUT_WIDTH-1:0] routing_addr_i, // routing information from Master Core 58 | `ifdef GNT_BASED_FC 59 | output logic data_gnt_o, // Grant delivered to Master Core 60 | input logic [N_SLAVE-1:0] data_gnt_i, // Grant Array: one for each memory (ARB TREE SIDE) 61 | `else 62 | output logic data_stall_o, // Stall delivered to Master Core 63 | input logic [N_SLAVE-1:0] data_stall_i, // Stall Array: one for each memory (ARB TREE SIDE) 64 | `endif 65 | output logic [N_SLAVE-1:0] data_req_o, // Request Array: one for each memory 66 | output logic [ID_WIDTH-1:0] data_ID_o // data_ID_o is sent whit the request (like a PID) 67 | ); 68 | 69 | assign data_ID_o = ID; // ID is simply attached to the ID_OUT 70 | 71 | generate 72 | 73 | if(N_SLAVE == 1) 74 | begin : SINGLE_SLAVE 75 | 76 | assign data_req_o[0] = data_req_i; 77 | `ifdef GNT_BASED_FC 78 | assign data_gnt_o = data_gnt_i[0]; 79 | `else 80 | assign data_stall_o = data_stall_i[0]; 81 | `endif 82 | 83 | end 84 | else 85 | begin : MULTI_SLAVE 86 | 87 | always @(*) 88 | begin : Combinational_ADDR_DEC_REQ 89 | //DEFAULT VALUES 90 | data_req_o = '0; 91 | // Apply the rigth value 92 | data_req_o[routing_addr_i] = data_req_i; 93 | `ifdef GNT_BASED_FC 94 | data_gnt_o = data_gnt_i[routing_addr_i]; 95 | `else 96 | data_stall_o = data_stall_i[routing_addr_i]; 97 | `endif 98 | end 99 | 100 | end 101 | 102 | endgenerate 103 | endmodule 104 | -------------------------------------------------------------------------------- /rtl/low_latency_interco/AddressDecoder_Resp.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 06/07/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: AddressDecoder_Resp // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Address Decoder used to generate the individual requests // 30 | // for all the available masters . It routes the read data // 31 | // from the memory to the processor // 32 | // // 33 | // // 34 | // Revision: // 35 | // Revision v0.1 - File Created // 36 | // // 37 | // Additional Comments: // 38 | // // 39 | // // 40 | // // 41 | // // 42 | //////////////////////////////////////////////////////////////////////////////// 43 | 44 | `include "parameters.v" 45 | 46 | module AddressDecoder_Resp 47 | #( 48 | parameter ID_WIDTH = 20, // ID WIDTH (number of bits) --> see ID comment 49 | parameter N_MASTER = 20 // Number of Master 50 | ) 51 | ( 52 | // FROM Test And Set Interface 53 | input logic data_r_valid_i, 54 | input logic [ID_WIDTH-1:0] data_ID_i, 55 | 56 | // To Response Network 57 | output logic [N_MASTER-1:0] data_r_valid_o 58 | ); 59 | 60 | assign data_r_valid_o = {ID_WIDTH{data_r_valid_i}} & data_ID_i; 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /rtl/low_latency_interco/FanInPrimitive_Req.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: FanInPrimitive_Req // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Arbitration primitives used to build the arbitration trees.// 30 | // They are part of the request network with a distributed // 31 | // arbiter. The arbitration Algorithm is ROUND ROBIN // 32 | // // 33 | // // 34 | // Revision: // 35 | // Revision v0.1 - File Created // 36 | // Revision v0.2 - (19/02/2015) Restyling // 37 | // // 38 | // Additional Comments: // 39 | // // 40 | // // 41 | // // 42 | // // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | `include "parameters.v" 46 | 47 | 48 | module FanInPrimitive_Req 49 | #( 50 | parameter ADDR_WIDTH = 32, 51 | parameter ID_WIDTH = 16, 52 | parameter DATA_WIDTH = 32, 53 | parameter N_MASTER = 8, 54 | parameter BE_WIDTH = DATA_WIDTH/8 55 | ) 56 | ( 57 | input logic PRIO_FLAG, 58 | 59 | // LEFT SIDE 60 | input logic [DATA_WIDTH-1:0] data_wdata0_i, 61 | input logic [DATA_WIDTH-1:0] data_wdata1_i, 62 | input logic [ADDR_WIDTH-1:0] data_add0_i, 63 | input logic [ADDR_WIDTH-1:0] data_add1_i, 64 | input logic data_req0_i, 65 | input logic data_req1_i, 66 | input logic data_wen0_i, 67 | input logic data_wen1_i, 68 | input logic [BE_WIDTH-1:0] data_be0_i, 69 | input logic [BE_WIDTH-1:0] data_be1_i, 70 | input logic [ID_WIDTH-1:0] data_ID0_i, 71 | input logic [ID_WIDTH-1:0] data_ID1_i, 72 | input logic [$clog2(N_MASTER)-1:0] ID0_i, 73 | input logic [$clog2(N_MASTER)-1:0] ID1_i, 74 | `ifdef GNT_BASED_FC 75 | output logic data_gnt0_o, 76 | output logic data_gnt1_o, 77 | `else 78 | output logic data_stall0_o, 79 | output logic data_stall1_o, 80 | `endif 81 | // RIGTH SIDE 82 | output logic [DATA_WIDTH-1:0] data_wdata_o, 83 | output logic [ADDR_WIDTH-1:0] data_add_o, 84 | output logic data_req_o, 85 | output logic [ID_WIDTH-1:0] data_ID_o, 86 | output logic [$clog2(N_MASTER)-1:0] ID_o, 87 | output logic data_wen_o, 88 | output logic [BE_WIDTH-1:0] data_be_o, 89 | `ifdef GNT_BASED_FC 90 | input logic data_gnt_i 91 | `else 92 | input logic data_stall_i 93 | `endif 94 | ); 95 | 96 | logic SEL; 97 | 98 | assign data_req_o = data_req0_i | data_req1_i; 99 | assign SEL = ~data_req0_i | ( PRIO_FLAG & data_req1_i); // SEL FOR ROUND ROBIN MUX 100 | 101 | `ifdef GNT_BASED_FC 102 | // Grant gnt0 and gnt1 103 | assign data_gnt0_o = (( data_req0_i & ~data_req1_i) | ( data_req0_i & ~PRIO_FLAG)) & data_gnt_i; 104 | assign data_gnt1_o = ((~data_req0_i & data_req1_i) | ( data_req1_i & PRIO_FLAG)) & data_gnt_i; 105 | `else 106 | // Data stall0 and stall1 107 | assign data_stall0_o = (data_req0_i & data_req1_i & PRIO_FLAG) | ((( data_req0_i & ~data_req1_i) | ( data_req0_i & ~PRIO_FLAG)) & data_stall_i); 108 | assign data_stall1_o = (data_req0_i & data_req1_i & ~PRIO_FLAG) | (((~data_req0_i & data_req1_i) | ( data_req1_i & PRIO_FLAG)) & data_stall_i); 109 | `endif 110 | // SEL CONTROLLER 111 | //MUXES AND DEMUXES 112 | always_comb 113 | begin : FanIn_MUX2 114 | case(SEL) //synopsys full_case 115 | 1'b0: 116 | begin //PRIORITY ON CH_0 117 | data_wdata_o = data_wdata0_i; 118 | data_add_o = data_add0_i; 119 | data_wen_o = data_wen0_i; 120 | data_ID_o = data_ID0_i; 121 | data_be_o = data_be0_i; 122 | ID_o = ID0_i; 123 | end 124 | 125 | 1'b1: 126 | begin //PRIORITY ON CH_1 127 | data_wdata_o = data_wdata1_i; 128 | data_add_o = data_add1_i; 129 | data_wen_o = data_wen1_i; 130 | data_ID_o = data_ID1_i; 131 | data_be_o = data_be1_i; 132 | ID_o = ID1_i; 133 | end 134 | 135 | endcase 136 | end 137 | endmodule 138 | -------------------------------------------------------------------------------- /rtl/low_latency_interco/FanInPrimitive_Resp.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: FanInPrimitive_Resp // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Routing primitives used to build the Routing trees. // 30 | // They are part of the response network // 31 | // // 32 | // // 33 | // Revision: // 34 | // Revision v0.1 - File Created // 35 | // Revision v0.2 - (19/02/2015) Code Restyling // 36 | // // 37 | // Additional Comments: // 38 | // // 39 | // // 40 | // // 41 | // // 42 | //////////////////////////////////////////////////////////////////////////////// 43 | 44 | 45 | `include "parameters.v" 46 | 47 | module FanInPrimitive_Resp 48 | #( 49 | parameter DATA_WIDTH = 32 50 | ) 51 | ( 52 | // UPSTREAM SIDE 53 | input logic [DATA_WIDTH-1:0] data_r_rdata0_i, 54 | input logic [DATA_WIDTH-1:0] data_r_rdata1_i, 55 | input logic data_r_valid0_i, 56 | input logic data_r_valid1_i, 57 | // DOWNSTREAM SIDE 58 | output logic [DATA_WIDTH-1:0] data_r_rdata_o, 59 | output logic data_r_valid_o 60 | ); 61 | // Selector for the FanOut multiplexer 62 | logic SEL; 63 | 64 | // VAlid is simply the or of the two requests 65 | assign data_r_valid_o = data_r_valid1_i | data_r_valid0_i; 66 | // FIXME: (req0 & req1) must be always 0 67 | assign SEL = data_r_valid1_i; 68 | 69 | // SEL CONTROLLER 70 | always_comb 71 | begin : FanOut_MUX2 72 | case(SEL) //synopsys full_case 73 | 1'b0: begin data_r_rdata_o = data_r_rdata0_i; end 74 | 1'b1: begin data_r_rdata_o = data_r_rdata1_i; end 75 | endcase 76 | end 77 | endmodule 78 | -------------------------------------------------------------------------------- /rtl/low_latency_interco/parameters.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: MUX2_REQ // 26 | // Language: SystemVerilog // 27 | // // 28 | // Description: two input multiplxer whith custom ports used to multiplex // 29 | // the datapath request data. It includes an embeddedd // 30 | // Fixed Priory arbiter with max priority to Channel 0 (CH0) // 31 | // // 32 | // // 33 | // Revision: // 34 | // Revision v0.1 - File Created // 35 | // Revision v0.2 - File Cleaned , removed defines and moved in the rtl files // 36 | // as paramereters (19/02/2015) // 37 | // // 38 | // Additional Comments: // 39 | // // 40 | // // 41 | // // 42 | // // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | //---------------------------------------------------// 46 | // MACROS HERE // 47 | //---------------------------------------------------// 48 | `define ADDR_OFFSET(VALUE) ( `log2(VALUE-1) - 3 ) // Address Offset: OFFSET IS 32bit--> 2bit; 64bit--> 3bit; 128bit--> 4bit and so on 49 | 50 | // LOG2() 51 | `define log2(VALUE) ((VALUE) < ( 1 ) ? 0 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE)< (8) ? 3:(VALUE) < ( 16 ) ? 4 : (VALUE) < ( 32 ) ? 5 : (VALUE) < ( 64 ) ? 6 : (VALUE) < ( 128 ) ? 7 : (VALUE) < ( 256 ) ? 8 : (VALUE) < ( 512 ) ? 9 : 10) 52 | `define log2_non_zero(VALUE) ((VALUE) < ( 1 ) ? 1 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE)< (8) ? 3:(VALUE) < ( 16 ) ? 4 : (VALUE) < ( 32 ) ? 5 : (VALUE) < ( 64 ) ? 6 : (VALUE) < ( 128 ) ? 7 : (VALUE) < ( 256 ) ? 8 : (VALUE) < ( 512 ) ? 9 : 10) 53 | 54 | 55 | // Comment this to enable Stall based Flow COntrol 56 | `define GNT_BASED_FC 57 | 58 | 59 | -------------------------------------------------------------------------------- /rtl/low_latency_interco/priority_Flag_Req.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: RR_Flag_Req // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Round Robing FLAG generator for the arbitration trees. // 30 | // The values ( RR_FLAG_REQ ) is update only when request and // 31 | // grant are high. This allow to avoid high sw activity when // 32 | // there is no valid traffic. Allows for clock gating // 33 | // insertion // 34 | // // 35 | // Revision: // 36 | // Revision v0.1 - File Created // 37 | // Revision v0.2 - (19/02/2015) --> Code restyling // 38 | // // 39 | // Additional Comments: // 40 | // // 41 | // // 42 | // // 43 | // // 44 | //////////////////////////////////////////////////////////////////////////////// 45 | 46 | `include "parameters.v" 47 | 48 | 49 | module priority_Flag_Req 50 | #( 51 | parameter WIDTH = 3, 52 | parameter MAX_COUNT = 2**WIDTH-1 53 | ) 54 | ( 55 | input logic clk, 56 | input logic rst_n, 57 | input logic TCDM_arb_policy_i, 58 | 59 | output logic [WIDTH-1:0] PRIO_FLAG_o, 60 | input logic data_req_i, 61 | input logic [WIDTH-1:0] ID_i, 62 | `ifdef GNT_BASED_FC 63 | input logic data_gnt_i 64 | `else 65 | input logic data_stall_i 66 | `endif 67 | ); 68 | 69 | always_ff @(posedge clk, negedge rst_n) 70 | begin : Prio_Flag_Req_SEQ 71 | if(rst_n == 1'b0) 72 | PRIO_FLAG_o <= '0; 73 | else 74 | `ifdef GNT_BASED_FC 75 | if( data_req_i & data_gnt_i ) 76 | `else 77 | if( data_req_i & ~data_stall_i ) 78 | `endif 79 | begin 80 | if(TCDM_arb_policy_i == 1'b0) 81 | begin : RR_PRIORIY 82 | if(PRIO_FLAG_o < MAX_COUNT) 83 | PRIO_FLAG_o <= PRIO_FLAG_o + 1'b1; 84 | else 85 | PRIO_FLAG_o <= '0; 86 | end 87 | else 88 | begin : LAST_WIN_PRIO 89 | PRIO_FLAG_o <= ID_i; 90 | end 91 | end 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /rtl/low_latency_interco/tcdm_xbar_wrap.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Date: 06.03.2019 13 | // Description: wrapper for TCDM_XBAR for testbench and testsynthesis 14 | 15 | module tcdm_xbar_wrap #( 16 | parameter NumMaster = 8, // number of initiator ports 17 | parameter NumSlave = 16, // number of TCDM banks 18 | parameter AddrWidth = 32, // address width on initiator side 19 | parameter DataWidth = 32, // word width of data 20 | parameter BeWidth = DataWidth/8, // width of corresponding byte enables 21 | parameter AddrMemWidth = 12 // number of address bits per TCDM bank 22 | ) ( 23 | input logic clk_i, 24 | input logic rst_ni, 25 | // master side 26 | input logic [NumMaster-1:0] req_i, // Data request 27 | input logic [NumMaster-1:0][AddrWidth-1:0] add_i, // Data request Address 28 | input logic [NumMaster-1:0] wen_i, // Data request type : 0--> Store, 1 --> Load 29 | input logic [NumMaster-1:0][DataWidth-1:0] wdata_i, // Data request Write data 30 | input logic [NumMaster-1:0][BeWidth-1:0] be_i, // Data request Byte enable 31 | output logic [NumMaster-1:0] gnt_o, // Grant Incoming Request 32 | output logic [NumMaster-1:0] vld_o, // Data Response Valid (For LOAD/STORE commands) 33 | output logic [NumMaster-1:0][DataWidth-1:0] rdata_o, // Data Response DATA (For LOAD commands) 34 | // slave side 35 | output logic [NumSlave-1:0] req_o, // Reuest for bank 36 | input logic [NumSlave-1:0] gnt_i, // Grant input 37 | output logic [NumSlave-1:0][AddrMemWidth-1:0] add_o, // Data request Address 38 | output logic [NumSlave-1:0] wen_o, // Data request type : 0--> Store, 1 --> Load 39 | output logic [NumSlave-1:0][DataWidth-1:0] wdata_o, // Data request Wire data 40 | output logic [NumSlave-1:0][BeWidth-1:0] be_o, // Data request Byte enable 41 | input logic [NumSlave-1:0][DataWidth-1:0] rdata_i // Data Response DATA (For LOAD commands) 42 | ); 43 | 44 | logic [NumSlave-1:0][NumMaster-1:0] id_d, id_q; 45 | logic [NumSlave-1:0] vld_d, vld_q; 46 | logic [NumMaster-1:0][AddrWidth:0] add; 47 | 48 | 49 | assign vld_d = req_o & gnt_i; 50 | 51 | // disable test and set 52 | for (genvar k = 0; k < NumMaster; k++) begin : gen_ts 53 | assign add[k] = {1'b0, add_i[k]}; 54 | end 55 | 56 | XBAR_TCDM #( 57 | .N_CH0 ( NumMaster ), 58 | .N_CH1 ( 0 ),// use single channel mode 59 | .N_SLAVE ( NumSlave ), 60 | .ADDR_WIDTH ( AddrWidth+1 ), 61 | .DATA_WIDTH ( DataWidth ), 62 | .BE_WIDTH ( BeWidth ), 63 | .ADDR_MEM_WIDTH ( AddrMemWidth ), 64 | .TEST_SET_BIT ( 32 ) 65 | ) i_XBAR_TCDM ( 66 | .data_req_i ( req_i ), 67 | .data_add_i ( add ), 68 | .data_wen_i ( wen_i ), 69 | .data_wdata_i ( wdata_i ), 70 | .data_be_i ( be_i ), 71 | .data_gnt_o ( gnt_o ), 72 | .data_r_valid_o ( vld_o ), 73 | .data_r_rdata_o ( rdata_o ), 74 | .data_req_o ( req_o ), 75 | .data_ts_set_o ( ), 76 | .data_add_o ( add_o ), 77 | .data_wen_o ( wen_o ), 78 | .data_wdata_o ( wdata_o ), 79 | .data_be_o ( be_o ), 80 | .data_ID_o ( id_d ), 81 | .data_gnt_i ( gnt_i ), 82 | .data_r_rdata_i ( rdata_i ), 83 | .data_r_valid_i ( vld_q ), 84 | .data_r_ID_i ( id_q ), 85 | .TCDM_arb_policy_i ( '0 ), // round robin 86 | .clk ( clk_i ), 87 | .rst_n ( rst_ni ) 88 | ); 89 | 90 | always_ff @(posedge clk_i) begin : p_regs 91 | if (!rst_ni) begin 92 | id_q <= '0; 93 | vld_q <= '0; 94 | end else begin 95 | id_q <= id_d; 96 | vld_q <= vld_d; 97 | end 98 | end 99 | 100 | endmodule 101 | -------------------------------------------------------------------------------- /rtl/peripheral_interco/AddressDecoder_PE_Req.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: AddressDecoder_PE_Req // 26 | // Language: SystemVerilog // 27 | // // 28 | // Description: Address Decoder used to generate the individual requests // 29 | // for all the available memory cuts. It backroutes the // 30 | // grants from the Arbitration tree to the processor // 31 | // // 32 | // // 33 | // Revision: // 34 | // Revision v0.1 - File Created // 35 | // Revision v0.2 - Code Restyling (19/02/2015) // 36 | // v0.4 20/04/2018 - Supporting non power of 2 N_SLAVE // 37 | // // 38 | // Additional Comments: // 39 | // // 40 | // // 41 | // // 42 | // // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | `include "parameters.v" 46 | 47 | module AddressDecoder_PE_Req 48 | #( 49 | parameter ID_WIDTH = 17, // ID WIDTH (number of bits) --> see ID comment 50 | parameter ID = 1, // ID routed with REQUEST used to backroute response 51 | parameter N_SLAVE = 16, // Number of Memory cuts 52 | parameter LOG_CLUSTER = 5, 53 | parameter ADDR_WIDTH = 32, 54 | parameter PE_ROUTING_LSB = 16, 55 | parameter PE_ROUTING_MSB = 19, 56 | parameter CLUSTER_ALIAS = 1'b0, 57 | parameter CLUSTER_ALIAS_BASE = 12'h000 58 | ) 59 | ( 60 | input logic [LOG_CLUSTER-1:0] CLUSTER_ID, 61 | // MASTER SIDE 62 | input logic data_req_i, // Request from Master 63 | input logic [ADDR_WIDTH-1:0] data_add_i, // Address from Master 64 | `ifdef GNT_BASED_FC 65 | output logic data_gnt_o, // Grant delivered to Master 66 | input logic [N_SLAVE-1:0] data_gnt_i, // Grant Array: one for each memory on ARB TREE SIDE 67 | `else 68 | output logic data_stall_o, // Stall delivered to Master 69 | input logic [N_SLAVE-1:0] data_stall_i, // Stall Array: one for each memory on ARB TREE SIDE 70 | `endif 71 | // ARB TREE SIDE 72 | output logic [N_SLAVE-1:0] data_req_o, // Request Array: one for each memory 73 | output logic [ID_WIDTH-1:0] data_ID_o // data_ID_o is sent whit the request (like a PID) 74 | ); 75 | 76 | localparam LOG_SLAVE = `log2(N_SLAVE-1); 77 | 78 | logic [LOG_SLAVE-1:0] ROUTING_ADDR; // M = Number of memory cuts 79 | 80 | logic [11:0] PE_END; 81 | logic [11:0] PE_START; 82 | 83 | assign data_ID_o = ID; // ID is simply attached to the ID_OUT 84 | 85 | always_comb 86 | begin 87 | PE_START = 12'h100 + (CLUSTER_ID << 2) + 2; 88 | PE_END = 12'h100 + (CLUSTER_ID << 2) + 3; 89 | end 90 | 91 | 92 | always_comb 93 | begin 94 | if( ( data_add_i[31:20] >= PE_START ) && ( data_add_i[31:20] < PE_END ) || ( CLUSTER_ALIAS && ( ( data_add_i[31:20] >= (CLUSTER_ALIAS_BASE+2) ) && ( data_add_i[31:20] < (CLUSTER_ALIAS_BASE+3) ) ) ) ) 95 | ROUTING_ADDR = data_add_i[PE_ROUTING_MSB:PE_ROUTING_LSB]; 96 | else 97 | ROUTING_ADDR = '1; 98 | end 99 | 100 | always_comb 101 | begin : Combinational_ADDR_DEC_REQ 102 | //DEFAULT VALUES 103 | data_req_o = '0; 104 | 105 | // Apply the rigth value 106 | if(ROUTING_ADDR >= N_SLAVE-1) 107 | begin 108 | data_req_o[N_SLAVE-1] = data_req_i; 109 | 110 | `ifdef GNT_BASED_FC 111 | data_gnt_o = data_gnt_i[N_SLAVE-1]; 112 | `else 113 | data_stall_o = data_stall_i[N_SLAVE-1]; 114 | `endif 115 | 116 | end 117 | else 118 | begin 119 | data_req_o[ROUTING_ADDR] = data_req_i; 120 | `ifdef GNT_BASED_FC 121 | data_gnt_o = data_gnt_i[ROUTING_ADDR]; 122 | `else 123 | data_stall_o = data_stall_i[ROUTING_ADDR]; 124 | `endif 125 | end 126 | end 127 | 128 | endmodule 129 | -------------------------------------------------------------------------------- /rtl/peripheral_interco/AddressDecoder_Resp_PE.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 06/07/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: AddressDecoder_Resp // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Address Decoder used to generate the individual requests // 30 | // for all the available masters . It routes the read data // 31 | // from the memory to the processor // 32 | // // 33 | // // 34 | // Revision: // 35 | // Revision v0.1 - File Created // 36 | // Revision v0.2 - Code Restyling (19/02/2015) // 37 | // // 38 | // Additional Comments: // 39 | // // 40 | // // 41 | // // 42 | // // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | `include "parameters.v" 46 | 47 | module AddressDecoder_Resp_PE 48 | #( 49 | parameter ID_WIDTH = 20, // ID WIDTH (number of bits) --> see ID comment 50 | parameter N_MASTER = 20 // Number of Master 51 | ) 52 | ( 53 | // FROM Test And Set Interface 54 | input logic data_r_valid_i, 55 | input logic [ID_WIDTH-1:0] data_ID_i, 56 | 57 | // To Response Network 58 | output logic [N_MASTER-1:0] data_r_valid_o 59 | ); 60 | 61 | assign data_r_valid_o = {ID_WIDTH{data_r_valid_i}} & data_ID_i; 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: FanInPrimitive_Resp // 26 | // Language: SystemVerilog // 27 | // // 28 | // Description: Routing primitives used to build the Routing trees. // 29 | // They are part of the response network // 30 | // // 31 | // // 32 | // Revision: // 33 | // Revision v0.1 02/07/2011 - File Created // 34 | // v0.2 15/08/2012 - Improved the Interface Structure, // 35 | // Changed the routing mechanism // 36 | // Revision v0.3 19/02/2015 - Code Restyling // 37 | // // 38 | // // 39 | // // 40 | // Additional Comments: // 41 | // // 42 | // // 43 | // // 44 | // // 45 | //////////////////////////////////////////////////////////////////////////////// 46 | 47 | 48 | `include "parameters.v" 49 | 50 | module FanInPrimitive_PE_Resp 51 | #( 52 | parameter DATA_WIDTH = 32 53 | ) 54 | ( 55 | // UPSTREAM SIDE 56 | input logic [DATA_WIDTH-1:0] data_r_rdata0_i, 57 | input logic [DATA_WIDTH-1:0] data_r_rdata1_i, 58 | input logic data_r_valid0_i, 59 | input logic data_r_valid1_i, 60 | input logic data_r_opc0_i, 61 | input logic data_r_opc1_i, 62 | 63 | // DOWNSTREAM SIDE 64 | output logic [DATA_WIDTH-1:0] data_r_rdata_o, 65 | output logic data_r_valid_o, 66 | output logic data_r_opc_o 67 | ); 68 | 69 | // Selector for the FanOut multiplexer 70 | logic SEL; 71 | 72 | // VAlid is simply the or of the two requests 73 | assign data_r_valid_o = data_r_valid1_i | data_r_valid0_i; 74 | 75 | // FIXME: (req0 & req1) must be always 0 76 | assign SEL = data_r_valid1_i; 77 | 78 | 79 | // SEL CONTROLLER 80 | always_comb 81 | begin : FanOut_MUX2 82 | case(SEL) 83 | 1'b0: begin data_r_rdata_o = data_r_rdata0_i; data_r_opc_o = data_r_opc0_i; end 84 | 1'b1: begin data_r_rdata_o = data_r_rdata1_i; data_r_opc_o = data_r_opc1_i; end 85 | endcase 86 | end 87 | endmodule 88 | -------------------------------------------------------------------------------- /rtl/peripheral_interco/FanInPrimitive_Req_PE.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: FanInPrimitive_Req // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Arbitration primitives used to build the arbitration trees.// 30 | // They are part of the request network with a distributed // 31 | // arbiter. The arbitration Algorithm is ROUND ROBIN // 32 | // // 33 | // // 34 | // Revision: // 35 | // Revision v0.1 - File Created // 36 | // Revision v0.2 - Code Restyling (19/02/2015) // 37 | // // 38 | // Additional Comments: // 39 | // // 40 | // // 41 | // // 42 | // // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | `include "parameters.v" 46 | 47 | 48 | module FanInPrimitive_Req_PE 49 | #( 50 | parameter ADDR_WIDTH = 32, 51 | parameter ID_WIDTH = 16, 52 | parameter DATA_WIDTH = 32, 53 | parameter BE_WIDTH = DATA_WIDTH/8 54 | ) 55 | ( 56 | input logic RR_FLAG, 57 | 58 | // LEFT SIDE 59 | input logic [DATA_WIDTH-1:0] data_wdata0_i, 60 | input logic [DATA_WIDTH-1:0] data_wdata1_i, 61 | input logic [ADDR_WIDTH-1:0] data_add0_i, 62 | input logic [ADDR_WIDTH-1:0] data_add1_i, 63 | input logic data_req0_i, 64 | input logic data_req1_i, 65 | input logic data_wen0_i, 66 | input logic data_wen1_i, 67 | input logic [BE_WIDTH-1:0] data_be0_i, 68 | input logic [BE_WIDTH-1:0] data_be1_i, 69 | input logic [ID_WIDTH-1:0] data_ID0_i, 70 | input logic [ID_WIDTH-1:0] data_ID1_i, 71 | `ifdef GNT_BASED_FC 72 | output logic data_gnt0_o, 73 | output logic data_gnt1_o, 74 | `else 75 | output logic data_stall0_o, 76 | output logic data_stall1_o, 77 | `endif 78 | // RIGTH SIDE 79 | output logic [DATA_WIDTH-1:0] data_wdata_o, 80 | output logic [ADDR_WIDTH-1:0] data_add_o, 81 | output logic data_req_o, 82 | output logic [ID_WIDTH-1:0] data_ID_o, 83 | output logic data_wen_o, 84 | output logic [BE_WIDTH-1:0] data_be_o, 85 | `ifdef GNT_BASED_FC 86 | input logic data_gnt_i 87 | `else 88 | input logic data_stall_i 89 | `endif 90 | ); 91 | 92 | logic SEL; 93 | 94 | assign data_req_o = data_req0_i | data_req1_i; 95 | assign SEL = ~data_req0_i | ( RR_FLAG & data_req1_i); // SEL FOR ROUND ROBIN MUX 96 | 97 | `ifdef GNT_BASED_FC 98 | // Grant gnt0 and gnt1 99 | assign data_gnt0_o = (( data_req0_i & ~data_req1_i) | ( data_req0_i & ~RR_FLAG)) & data_gnt_i; 100 | assign data_gnt1_o = ((~data_req0_i & data_req1_i) | ( data_req1_i & RR_FLAG)) & data_gnt_i; 101 | `else 102 | // Data stall0 and stall1 103 | assign data_stall0_o = (data_req0_i & data_req1_i & RR_FLAG) | ((( data_req0_i & ~data_req1_i) | ( data_req0_i & ~RR_FLAG)) & data_stall_i); 104 | assign data_stall1_o = (data_req0_i & data_req1_i & ~RR_FLAG) | (((~data_req0_i & data_req1_i) | ( data_req1_i & RR_FLAG)) & data_stall_i); 105 | `endif 106 | 107 | //MUXES AND DEMUXES 108 | always_comb 109 | begin : FanIn_MUX2 110 | case(SEL) //synopsys full_case 111 | 1'b0: 112 | begin //PRIORITY ON CH_0 113 | data_wdata_o = data_wdata0_i; 114 | data_add_o = data_add0_i; 115 | data_wen_o = data_wen0_i; 116 | data_ID_o = data_ID0_i; 117 | data_be_o = data_be0_i; 118 | end 119 | 120 | 1'b1: 121 | begin //PRIORITY ON CH_1 122 | data_wdata_o = data_wdata1_i; 123 | data_add_o = data_add1_i; 124 | data_wen_o = data_wen1_i; 125 | data_ID_o = data_ID1_i; 126 | data_be_o = data_be1_i; 127 | end 128 | 129 | endcase 130 | end 131 | 132 | endmodule 133 | -------------------------------------------------------------------------------- /rtl/peripheral_interco/RR_Flag_Req_PE.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Copyright 2018 ETH Zurich and University of Bologna. // 4 | // Copyright and related rights are licensed under the Solderpad Hardware // 5 | // License, Version 0.51 (the "License"); you may not use this file except in // 6 | // compliance with the License. You may obtain a copy of the License at // 7 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // 8 | // or agreed to in writing, software, hardware and materials distributed under// 9 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // 10 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the // 11 | // specific language governing permissions and limitations under the License. // 12 | // // 13 | // Company: Micrel Lab @ DEIS - University of Bologna // 14 | // Viale Risorgimento 2 40136 // 15 | // Bologna - fax 0512093785 - // 16 | // // 17 | // Engineer: Igor Loi - igor.loi@unibo.it // 18 | // // 19 | // Additional contributions by: // 20 | // // 21 | // // 22 | // // 23 | // Create Date: 29/06/2011 // 24 | // Design Name: LOG_INTERCONNECT // 25 | // Module Name: RR_Flag_Req // 26 | // Project Name: MegaLEON // 27 | // Language: SystemVerilog // 28 | // // 29 | // Description: Round Robing FLAG generator for the arbitration trees. // 30 | // The values ( RR_FLAG_REQ ) is update only when request and // 31 | // grant are high. This allow to avoid high sw activity when // 32 | // there is no valid traffic. Allows for clock gating // 33 | // insertion // 34 | // // 35 | // Revision: // 36 | // Revision v0.1 - File Created // 37 | // // 38 | // Additional Comments: // 39 | // // 40 | // // 41 | // // 42 | // // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | `include "parameters.v" 46 | 47 | 48 | module RR_Flag_Req_PE 49 | #( 50 | parameter WIDTH = 3, 51 | parameter MAX_COUNT = 2**WIDTH-1 52 | ) 53 | ( 54 | input logic clk, 55 | input logic rst_n, 56 | output logic [WIDTH-1:0] RR_FLAG_o, 57 | input logic data_req_i, 58 | `ifdef GNT_BASED_FC 59 | input logic data_gnt_i 60 | `else 61 | input logic data_stall_i 62 | `endif 63 | ); 64 | 65 | 66 | 67 | 68 | always_ff @(posedge clk, negedge rst_n) 69 | begin : RR_Flag_Req_SEQ 70 | if(rst_n == 1'b0) 71 | RR_FLAG_o <= '0; 72 | else 73 | `ifdef GNT_BASED_FC 74 | if( data_req_i & data_gnt_i ) 75 | `else 76 | if( data_req_i & ~data_stall_i ) 77 | `endif 78 | begin 79 | if(RR_FLAG_o < MAX_COUNT) 80 | RR_FLAG_o <= RR_FLAG_o + 1'b1; 81 | else 82 | RR_FLAG_o <= '0; 83 | end 84 | end 85 | 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /rtl/peripheral_interco/parameters.v: -------------------------------------------------------------------------------- 1 | ../low_latency_interco/parameters.v -------------------------------------------------------------------------------- /rtl/tcdm_interconnect/addr_dec_resp_mux.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Date: 06.03.2019 13 | // Description: address decoder and response mux for full crossbar. 14 | 15 | module addr_dec_resp_mux #( 16 | parameter int unsigned NumOut = 32, 17 | parameter int unsigned ReqDataWidth = 32, 18 | parameter int unsigned RespDataWidth = 32, 19 | parameter int unsigned RespLat = 1, // response latency of slaves 20 | parameter bit WriteRespOn = 1'b1, // determines whether writes should return a response or not 21 | parameter bit BroadCastOn = 1'b0 // perform broadcast 22 | ) ( 23 | input logic clk_i, 24 | input logic rst_ni, 25 | // master side 26 | input logic req_i, // request from this master 27 | input logic [$clog2(NumOut)-1:0] add_i, // bank selection index to be decoded 28 | input logic wen_i, // write enable 29 | input logic [ReqDataWidth-1:0] data_i, // data to be transported to slaves 30 | output logic gnt_o, // grant to master 31 | output logic vld_o, // read/write response 32 | output logic [RespDataWidth-1:0] rdata_o, // read response 33 | // slave side 34 | /* verilator lint_off UNOPTFLAT */ 35 | output logic [NumOut-1:0] req_o, // request signals after decoding 36 | /* verilator lint_on UNOPTFLAT */ 37 | input logic [NumOut-1:0] gnt_i, // grants from slaves 38 | output logic [NumOut-1:0][ReqDataWidth-1:0] data_o, // data to be transported to slaves 39 | input logic [NumOut-1:0][RespDataWidth-1:0] rdata_i // read responses from slaves 40 | ); 41 | 42 | logic [RespLat-1:0] vld_d, vld_q; 43 | 44 | //////////////////////////////////////////////////////////////////////// 45 | // degenerate case 46 | //////////////////////////////////////////////////////////////////////// 47 | if (NumOut == unsigned'(1)) begin : gen_one_output 48 | 49 | assign data_o[0] = data_i; 50 | assign gnt_o = gnt_i[0]; 51 | assign req_o[0] = req_i; 52 | assign rdata_o = rdata_i[0]; 53 | assign vld_o = vld_q[$high(vld_q)]; 54 | 55 | if (RespLat > unsigned'(1)) begin : gen_lat_gt1 56 | assign vld_d = {vld_q[$high(vld_q)-1:0], gnt_o & (~wen_i | WriteRespOn)}; 57 | end else begin : gen_lat_le1 58 | assign vld_d = gnt_o & (~wen_i | WriteRespOn); 59 | end 60 | 61 | always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 62 | if (!rst_ni) begin 63 | vld_q <= '0; 64 | end else begin 65 | vld_q <= vld_d; 66 | end 67 | end 68 | 69 | //////////////////////////////////////////////////////////////////////// 70 | // normal case 71 | //////////////////////////////////////////////////////////////////////// 72 | end else begin : gen_several_outputs 73 | 74 | // address decoder 75 | always_comb begin : p_addr_dec 76 | req_o = '0; 77 | if (BroadCastOn) begin 78 | if (req_i) begin 79 | req_o = '1; 80 | end 81 | end else begin 82 | req_o[add_i] = req_i; 83 | end 84 | end 85 | 86 | // connect data outputs 87 | assign data_o = {NumOut{data_i}}; 88 | 89 | // aggregate grant signals 90 | assign gnt_o = |gnt_i; 91 | assign vld_o = vld_q[$high(vld_q)]; 92 | 93 | // response path in case of broadcasts 94 | if (BroadCastOn) begin : gen_bcast 95 | logic [NumOut-1:0] gnt_d, gnt_q; 96 | logic [$clog2(NumOut)-1:0] bank_sel; 97 | 98 | assign gnt_d = gnt_i; 99 | 100 | // determine index from 101 | // one-hot grant vector 102 | lzc #( 103 | .WIDTH(NumOut) 104 | ) lzc_i ( 105 | .in_i(gnt_q), 106 | .cnt_o(bank_sel), 107 | .empty_o() 108 | ); 109 | 110 | if (RespLat > unsigned'(1)) begin : gen_lat_gt1 111 | logic [RespLat-2:0][$clog2(NumOut)-1:0] bank_sel_d, bank_sel_q; 112 | 113 | assign rdata_o = rdata_i[bank_sel_q[$high(bank_sel_q)]]; 114 | assign vld_d = {vld_q[$high(vld_q)-1:0], gnt_o & (~wen_i | WriteRespOn)}; 115 | 116 | if (RespLat == unsigned'(2)) begin : gen_lat_eq2 117 | assign bank_sel_d = {bank_sel_q[$high(bank_sel_q)-2:0], bank_sel, bank_sel}; 118 | end else begin : gen_lat_le2 119 | assign bank_sel_d = bank_sel; 120 | end 121 | 122 | always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 123 | if (!rst_ni) begin 124 | bank_sel_q <= '0; 125 | end else begin 126 | bank_sel_q <= bank_sel_d; 127 | end 128 | end 129 | 130 | end else begin : gen_lat_eq1 131 | assign rdata_o = rdata_i[bank_sel]; 132 | assign vld_d = gnt_o & (~wen_i | WriteRespOn); 133 | end 134 | 135 | always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 136 | if (!rst_ni) begin 137 | gnt_q <= '0; 138 | vld_q <= '0; 139 | end else begin 140 | gnt_q <= gnt_d; 141 | vld_q <= vld_d; 142 | end 143 | end 144 | 145 | // non-broadcast case 146 | end else begin : gen_no_broadcast 147 | logic [RespLat-1:0][$clog2(NumOut)-1:0] bank_sel_d, bank_sel_q; 148 | 149 | assign rdata_o = rdata_i[bank_sel_q[$high(bank_sel_q)]]; 150 | 151 | if (RespLat > unsigned'(1)) begin : gen_lat_gt1 152 | assign bank_sel_d = {bank_sel_q[$high(bank_sel_q)-1:0], add_i}; 153 | assign vld_d = {vld_q[$high(vld_q)-1:0], gnt_o & (~wen_i | WriteRespOn)}; 154 | end else begin : gen_lat_le1 155 | assign bank_sel_d = add_i; 156 | assign vld_d = gnt_o & (~wen_i | WriteRespOn); 157 | end 158 | 159 | always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 160 | if (!rst_ni) begin 161 | bank_sel_q <= '0; 162 | vld_q <= '0; 163 | end else begin 164 | bank_sel_q <= bank_sel_d; 165 | vld_q <= vld_d; 166 | end 167 | end 168 | end 169 | end 170 | 171 | //////////////////////////////////////////////////////////////////////// 172 | // assertions 173 | //////////////////////////////////////////////////////////////////////// 174 | 175 | // pragma translate_off 176 | initial begin 177 | assert (RespLat > 0) else 178 | $fatal(1,"RespLat must be greater than 0"); 179 | assert (NumOut > 0) else 180 | $fatal(1,"NumOut must be greater than 0"); 181 | end 182 | // pragma translate_on 183 | 184 | endmodule // addr_dec_resp_mux 185 | -------------------------------------------------------------------------------- /rtl/tcdm_interconnect/amo_shim.sv: -------------------------------------------------------------------------------- 1 | /// Description: Governs atomic memory oeprations. This module needs to be instantiated 2 | /// in front of an SRAM. It needs to have exclusive access over it. 3 | 4 | /// Author: Florian Zaruba 5 | module amo_shim #( 6 | parameter int unsigned AddrMemWidth = 32 7 | ) ( 8 | input logic clk_i, 9 | input logic rst_ni, 10 | // master side 11 | input logic in_req_i, // Bank request 12 | output logic in_gnt_o, // Bank grant 13 | input logic [AddrMemWidth-1:0] in_add_i, // Address 14 | input logic [3:0] in_amo_i, // Atomic Memory Operation 15 | input logic in_wen_i, // 1: Store, 0: Load 16 | input logic [63:0] in_wdata_i, // Write data 17 | input logic [7:0] in_be_i, // Byte enable 18 | output logic [63:0] in_rdata_o, // Read data 19 | // slave side 20 | output logic out_req_o, // Bank request 21 | output logic [AddrMemWidth-1:0] out_add_o, // Address 22 | output logic out_wen_o, // 1: Store, 0: Load 23 | output logic [63:0] out_wdata_o, // Write data 24 | output logic [7:0] out_be_o, // Byte enable 25 | input logic [63:0] out_rdata_i // Read data 26 | ); 27 | 28 | typedef enum logic [3:0] { 29 | AMONone = 4'h0, 30 | AMOSwap = 4'h1, 31 | AMOAdd = 4'h2, 32 | AMOAnd = 4'h3, 33 | AMOOr = 4'h4, 34 | AMOXor = 4'h5, 35 | AMOMax = 4'h6, 36 | AMOMaxu = 4'h7, 37 | AMOMin = 4'h8, 38 | AMOMinu = 4'h9, 39 | AMOCAS = 4'hA 40 | } amo_op_t; 41 | 42 | enum logic { 43 | Idle, DoAMO 44 | } state_q; 45 | 46 | amo_op_t amo_op_q; 47 | 48 | logic load_amo; 49 | 50 | logic [AddrMemWidth-1:0] addr_q; 51 | 52 | logic [31:0] amo_operand_a; 53 | logic [31:0] amo_operand_b_q; 54 | // requested amo should be performed on upper 32 bit 55 | logic upper_word_q; 56 | logic [31:0] swap_value_q; 57 | logic [31:0] amo_result; // result of atomic memory operation 58 | 59 | assign amo_operand_a = upper_word_q ? out_rdata_i[63:32] : out_rdata_i[31:0]; 60 | 61 | always_comb begin 62 | // feed-through 63 | out_req_o = in_req_i; 64 | in_gnt_o = in_req_i; 65 | out_add_o = in_add_i; 66 | out_wen_o = in_wen_i; 67 | out_wdata_o = in_wdata_i; 68 | out_be_o = in_be_i; 69 | in_rdata_o = out_rdata_i; 70 | 71 | load_amo = 1'b0; 72 | 73 | unique case (state_q) 74 | Idle: begin 75 | if (in_req_i && amo_op_t'(in_amo_i) != AMONone) begin 76 | load_amo = 1'b1; 77 | end 78 | end 79 | 80 | // Claim the memory interface 81 | DoAMO: begin 82 | in_gnt_o = 1'b0; 83 | // Commit AMO 84 | out_req_o = 1'b1; 85 | out_add_o = addr_q; 86 | out_wen_o = 1'b1; 87 | // shift up if the address was pointing to the upper 32 bits 88 | out_be_o = upper_word_q ? 8'b1111_0000 : 8'b0000_1111; 89 | out_wdata_o = upper_word_q ? {amo_result, 32'b0} : {32'b0, amo_result}; 90 | in_rdata_o = upper_word_q ? {amo_operand_a, 32'b0} : {32'b0, amo_operand_a}; 91 | end 92 | default:; 93 | endcase 94 | end 95 | 96 | always_ff @(posedge clk_i or negedge rst_ni) begin 97 | if (!rst_ni) begin 98 | state_q <= Idle; 99 | amo_op_q <= amo_op_t'('0); 100 | addr_q <= '0; 101 | amo_operand_b_q <= '0; 102 | swap_value_q <= '0; 103 | upper_word_q <= '0; 104 | end else begin 105 | if (load_amo) begin 106 | amo_op_q <= amo_op_t'(in_amo_i); 107 | addr_q <= in_add_i; 108 | amo_operand_b_q <= in_be_i[0] ? in_wdata_i[31:0] : in_wdata_i[63:32]; 109 | // swap value is located in the upper word 110 | swap_value_q <= in_be_i[0] ? in_wdata_i[63:32] : in_wdata_i[63:32]; 111 | state_q <= DoAMO; 112 | upper_word_q <= in_be_i[4]; 113 | end else begin 114 | amo_op_q <= AMONone; 115 | state_q <= Idle; 116 | end 117 | end 118 | end 119 | 120 | // ---------------- 121 | // AMO ALU 122 | // ---------------- 123 | logic [33:0] adder_sum; 124 | logic [32:0] adder_operand_a, adder_operand_b; 125 | 126 | assign adder_sum = adder_operand_a + adder_operand_b; 127 | /* verilator lint_off WIDTH */ 128 | always_comb begin : amo_alu 129 | 130 | adder_operand_a = 33'($signed(amo_operand_a)); 131 | adder_operand_b = 33'($signed(amo_operand_b_q)); 132 | 133 | amo_result = amo_operand_b_q; 134 | 135 | unique case (amo_op_q) 136 | // the default is to output operand_b 137 | AMOSwap:; 138 | AMOAdd: amo_result = adder_sum[31:0]; 139 | AMOAnd: amo_result = amo_operand_a & amo_operand_b_q; 140 | AMOOr: amo_result = amo_operand_a | amo_operand_b_q; 141 | AMOXor: amo_result = amo_operand_a ^ amo_operand_b_q; 142 | AMOMax: begin 143 | adder_operand_b = -$signed(amo_operand_b_q); 144 | amo_result = adder_sum[32] ? amo_operand_b_q : amo_operand_a; 145 | end 146 | AMOMin: begin 147 | adder_operand_b = -$signed(amo_operand_b_q); 148 | amo_result = adder_sum[32] ? amo_operand_a : amo_operand_b_q; 149 | end 150 | AMOMaxu: begin 151 | adder_operand_a = 33'($unsigned(amo_operand_a)); 152 | adder_operand_b = -$unsigned(amo_operand_b_q); 153 | amo_result = adder_sum[32] ? amo_operand_b_q : amo_operand_a; 154 | end 155 | AMOMinu: begin 156 | adder_operand_a = 33'($unsigned(amo_operand_a)); 157 | adder_operand_b = -$unsigned(amo_operand_b_q); 158 | amo_result = adder_sum[32] ? amo_operand_a : amo_operand_b_q; 159 | end 160 | AMOCAS: begin 161 | adder_operand_b = -$signed(amo_operand_b_q); 162 | // values are equal -> update 163 | if (adder_sum == '0) begin 164 | amo_result = swap_value_q; 165 | // values are not euqal -> don't update 166 | end else begin 167 | amo_result = upper_word_q ? out_rdata_i[63:32] : out_rdata_i[31:0]; 168 | end 169 | end 170 | default: amo_result = '0; 171 | endcase 172 | end 173 | /* verilator lint_on WIDTH */ 174 | endmodule 175 | -------------------------------------------------------------------------------- /rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Date: 28.05.2019 13 | // Description: Package with important constants and lookup tables for TCDM 14 | // interconnect. 15 | 16 | package tcdm_interconnect_pkg; 17 | 18 | typedef enum logic [1:0] { LIC, BFLY2, BFLY4, CLOS } topo_e; 19 | 20 | //////////////////////////////////////////////////////////////////////// 21 | // LUT params for Clos net with configs: 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n, 22 | // to be indexed with [config_idx][$clog2(BankingFact)][$clog2(NumBanks)] 23 | // generated with MATLAB script gen_clos_params.m 24 | //////////////////////////////////////////////////////////////////////// 25 | localparam logic [3:1][4:0][12:2][15:0] ClosNLut = {16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 26 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 27 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 28 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 29 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 30 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 31 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 32 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 33 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 34 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 35 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 36 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 37 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 38 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 39 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2}; 40 | localparam logic [3:1][4:0][12:2][15:0] ClosMLut = {16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, 41 | 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, 42 | 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, 43 | 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, 44 | 16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4, 45 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 46 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 47 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 48 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 49 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 50 | 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, 51 | 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, 52 | 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, 53 | 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, 54 | 16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1,16'd1}; 55 | localparam logic [3:1][4:0][12:2][15:0] ClosRLut = {16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 56 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 57 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 58 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 59 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 60 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 61 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 62 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 63 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 64 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, 65 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 66 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 67 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 68 | 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, 69 | 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2}; 70 | 71 | 72 | 73 | endpackage : tcdm_interconnect_pkg 74 | -------------------------------------------------------------------------------- /rtl/tcdm_interconnect/xbar.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Date: 07.03.2019 13 | // Description: Full crossbar, implemented as logarithmic interconnect. 14 | 15 | module xbar #( 16 | parameter int unsigned NumIn = 4, // number of requestors 17 | parameter int unsigned NumOut = 4, // number of targets 18 | parameter int unsigned ReqDataWidth = 32, // word width of data 19 | parameter int unsigned RespDataWidth = 32, // word width of data 20 | parameter int unsigned RespLat = 1, // response latency of slaves 21 | parameter bit WriteRespOn = 1'b1, // defines whether the interconnect returns a write response 22 | parameter bit BroadCastOn = 1'b0, // perform broadcast 23 | parameter bit ExtPrio = 1'b0 // use external arbiter priority flags 24 | ) ( 25 | input logic clk_i, 26 | input logic rst_ni, 27 | // external prio flag input 28 | input logic [NumOut-1:0][$clog2(NumIn)-1:0] rr_i, // external prio input 29 | // master side 30 | input logic [NumIn-1:0] req_i, // request signal 31 | input logic [NumIn-1:0][$clog2(NumOut)-1:0] add_i, // bank Address 32 | input logic [NumIn-1:0] wen_i, // 1: store, 0: load 33 | input logic [NumIn-1:0][ReqDataWidth-1:0] wdata_i, // write data 34 | output logic [NumIn-1:0] gnt_o, // grant (combinationally dependent on req_i and add_i) 35 | output logic [NumIn-1:0] vld_o, // response valid, also asserted if write responses are enabled 36 | output logic [NumIn-1:0][RespDataWidth-1:0] rdata_o, // data response (for load commands) 37 | // slave side 38 | input logic [NumOut-1:0] gnt_i, // request out 39 | output logic [NumOut-1:0] req_o, // grant input 40 | /* verilator lint_off UNOPTFLAT */ 41 | output logic [NumOut-1:0][ReqDataWidth-1:0] wdata_o, // write data 42 | /* verilator lint_on UNOPTFLAT */ 43 | input logic [NumOut-1:0][RespDataWidth-1:0] rdata_i // data response (for load commands) 44 | ); 45 | 46 | //////////////////////////////////////////////////////////////////////// 47 | // inter-level wires 48 | //////////////////////////////////////////////////////////////////////// 49 | 50 | logic [NumOut-1:0][NumIn-1:0][ReqDataWidth-1:0] sl_data; 51 | logic [NumIn-1:0][NumOut-1:0][ReqDataWidth-1:0] ma_data; 52 | logic [NumOut-1:0][NumIn-1:0] sl_gnt, sl_req; 53 | logic [NumIn-1:0][NumOut-1:0] ma_gnt, ma_req; 54 | 55 | //////////////////////////////////////////////////////////////////////// 56 | // instantiate bank address decoder/resp mux for each master 57 | //////////////////////////////////////////////////////////////////////// 58 | for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs 59 | addr_dec_resp_mux #( 60 | .NumOut ( NumOut ), 61 | .ReqDataWidth ( ReqDataWidth ), 62 | .RespDataWidth ( RespDataWidth ), 63 | .RespLat ( RespLat ), 64 | .BroadCastOn ( BroadCastOn ), 65 | .WriteRespOn ( WriteRespOn ) 66 | ) i_addr_dec_resp_mux ( 67 | .clk_i ( clk_i ), 68 | .rst_ni ( rst_ni ), 69 | .req_i ( req_i[j] ), 70 | .add_i ( add_i[j] ), 71 | .wen_i ( wen_i[j] ), 72 | .data_i ( wdata_i[j] ), 73 | .gnt_o ( gnt_o[j] ), 74 | .vld_o ( vld_o[j] ), 75 | .rdata_o ( rdata_o[j] ), 76 | .req_o ( ma_req[j] ), 77 | .gnt_i ( ma_gnt[j] ), 78 | .data_o ( ma_data[j] ), 79 | .rdata_i ( rdata_i ) 80 | ); 81 | 82 | // reshape connections between M/S 83 | for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape 84 | assign sl_req[k][j] = ma_req[j][k]; 85 | assign ma_gnt[j][k] = sl_gnt[k][j]; 86 | assign sl_data[k][j] = ma_data[j][k]; 87 | end 88 | end 89 | 90 | //////////////////////////////////////////////////////////////////////// 91 | // instantiate an RR arbiter for each endpoint 92 | //////////////////////////////////////////////////////////////////////// 93 | for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs 94 | if (NumIn == unsigned'(1)) begin 95 | assign req_o[k] = sl_req[k][0]; 96 | assign sl_gnt[k][0] = gnt_i[k]; 97 | assign wdata_o[k] = sl_data[k][0]; 98 | end else begin : gen_rr_arb_tree 99 | rr_arb_tree #( 100 | .NumIn ( NumIn ), 101 | .DataWidth ( ReqDataWidth ), 102 | .ExtPrio ( ExtPrio ), 103 | .LockIn ( 1'b1 ) 104 | ) i_rr_arb_tree ( 105 | .clk_i ( clk_i ), 106 | .rst_ni ( rst_ni ), 107 | .flush_i ( 1'b0 ), 108 | .rr_i ( rr_i[k] ), 109 | .req_i ( sl_req[k] ), 110 | .gnt_o ( sl_gnt[k] ), 111 | .data_i ( sl_data[k] ), 112 | .gnt_i ( gnt_i[k] ), 113 | .req_o ( req_o[k] ), 114 | .data_o ( wdata_o[k] ), 115 | .idx_o ( )// disabled 116 | ); 117 | end 118 | end 119 | 120 | //////////////////////////////////////////////////////////////////////// 121 | // assertion 122 | //////////////////////////////////////////////////////////////////////// 123 | 124 | // pragma translate_off 125 | initial begin 126 | assert(NumIn > 0) else 127 | $fatal(1,"NumIn needs to be larger than 0."); 128 | assert(NumOut > 0) else 129 | $fatal(1,"NumOut needs to be larger than 0."); 130 | end 131 | // pragma translate_on 132 | 133 | endmodule // xbar 134 | -------------------------------------------------------------------------------- /rtl/variable_latency_interconnect/addr_decoder.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Matheus Cavalcante , ETH Zurich 13 | 14 | // Date: 12.02.2020 15 | 16 | // Description: Address decoder for the simplex crossbar. 17 | 18 | module addr_decoder #( 19 | parameter int unsigned NumOut = 32, 20 | parameter int unsigned DataWidth = 32, 21 | parameter bit AxiVldRdy = 1'b1, 22 | // Dependent parameters, DO NOT OVERRIDE! 23 | localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut) 24 | ) ( 25 | // Initiator side 26 | input logic valid_i, // Request valid from this initiator 27 | input logic [NumOutLog-1:0] addr_i, // Target selection index to be decoded 28 | input logic [DataWidth-1:0] data_i, // Data to be transported to the targets 29 | output logic ready_o, // Ready to the initiator 30 | // Target side 31 | output logic [NumOut-1:0] valid_o, // Request valid to this target 32 | input logic [NumOut-1:0] ready_i, // Targets ready to accept data 33 | output logic [NumOut-1:0][DataWidth-1:0] data_o 34 | ); 35 | 36 | /********************** 37 | * Degenerated case * 38 | **********************/ 39 | 40 | if (NumOut == 1) begin: gen_one_output 41 | assign valid_o[0] = valid_i ; 42 | assign ready_o = ready_i[0]; 43 | assign data_o[0] = data_i ; 44 | end 45 | 46 | /***************** 47 | * Normal case * 48 | *****************/ 49 | 50 | else begin: gen_several_outputs 51 | // Address decoder 52 | always_comb begin : p_addr_decoder 53 | valid_o = '0 ; 54 | valid_o[addr_i] = valid_i; 55 | end 56 | 57 | // Broadcast data outputs 58 | assign data_o = {NumOut{data_i}}; 59 | 60 | if (AxiVldRdy) 61 | // Demux ready signal 62 | assign ready_o = ready_i[addr_i]; 63 | else 64 | // Aggregate grant signals 65 | assign ready_o = |ready_i; 66 | end 67 | 68 | /**************** 69 | * Assertions * 70 | ****************/ 71 | 72 | if (NumOut <= 0) 73 | $fatal(1, "[addr_decoder] NumOut must be greater than 0."); 74 | 75 | endmodule : addr_decoder 76 | -------------------------------------------------------------------------------- /rtl/variable_latency_interconnect/full_duplex_xbar.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Matheus Cavalcante 12 | // Michael Schaffner , ETH Zurich 13 | 14 | // Date: 16.01.2020 15 | 16 | // Description: Full-duplex crossbar, capable of handling a variable 17 | // memory access latency. 18 | 19 | module full_duplex_xbar #( 20 | parameter int unsigned NumIn = 4, // Number of Initiators 21 | parameter int unsigned NumOut = 4, // Number of Targets 22 | parameter int unsigned ReqDataWidth = 32, // Request Data Width 23 | parameter int unsigned RespDataWidth = 32, // Response Data Width 24 | parameter bit ExtPrio = 1'b0, // Use external arbiter priority flags 25 | parameter bit SpillRegisterReq = 1'b0, // Insert a spill register on the request path (after arbitration) 26 | parameter bit SpillRegisterResp = 1'b0, // Insert a spill register on the response path (after arbitration) 27 | parameter bit AxiVldRdy = 1'b0, // Valid/ready signaling. 28 | parameter bit FallThroughRegister = 1'b0, // Insert a fall-through register, when not inserting a spill register 29 | // Dependent parameters, DO NOT OVERRIDE! 30 | localparam int unsigned NumInLog = NumIn == 1 ? 1 : $clog2(NumIn), 31 | localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut) 32 | ) ( 33 | input logic clk_i, 34 | input logic rst_ni, 35 | // External priority signals 36 | input logic [NumOut-1:0][NumInLog-1:0] req_rr_i, 37 | input logic [NumIn-1:0][NumOutLog-1:0] resp_rr_i, 38 | // Initiator side 39 | input logic [NumIn-1:0] req_valid_i, // Request valid 40 | output logic [NumIn-1:0] req_ready_o, // Request ready 41 | input logic [NumIn-1:0][NumOutLog-1:0] req_tgt_addr_i, // Target address 42 | input logic [NumIn-1:0][ReqDataWidth-1:0] req_wdata_i, // Write data 43 | output logic [NumIn-1:0] resp_valid_o, // Response valid 44 | input logic [NumIn-1:0] resp_ready_i, // Response ready 45 | output logic [NumIn-1:0][RespDataWidth-1:0] resp_rdata_o, // Data response (for load commands) 46 | // Target side 47 | output logic [NumOut-1:0] req_valid_o, // Request valid 48 | input logic [NumOut-1:0] req_ready_i, // Request ready 49 | output logic [NumOut-1:0][NumInLog-1:0] req_ini_addr_o, // Initiator address 50 | output logic [NumOut-1:0][ReqDataWidth-1:0] req_wdata_o, // Write data 51 | input logic [NumOut-1:0] resp_valid_i, // Response valid 52 | output logic [NumOut-1:0] resp_ready_o, // Response ready 53 | input logic [NumOut-1:0][NumInLog-1:0] resp_ini_addr_i, // Initiator address 54 | input logic [NumOut-1:0][RespDataWidth-1:0] resp_rdata_i // Data response (for load commands) 55 | ); 56 | 57 | /**************** 58 | * Crossbars * 59 | ****************/ 60 | 61 | // Instantiate two simplex crossbars, one for the requests and one for the responses. 62 | 63 | simplex_xbar #( 64 | .NumIn (NumIn ), 65 | .NumOut (NumOut ), 66 | .DataWidth (ReqDataWidth ), 67 | .ExtPrio (ExtPrio ), 68 | .AxiVldRdy (AxiVldRdy ), 69 | .SpillRegister (SpillRegisterReq ), 70 | .FallThroughRegister(FallThroughRegister) 71 | ) req_xbar ( 72 | .clk_i (clk_i ), 73 | .rst_ni (rst_ni ), 74 | .rr_i (req_rr_i ), 75 | .valid_i (req_valid_i ), 76 | .ready_o (req_ready_o ), 77 | .tgt_addr_i(req_tgt_addr_i), 78 | .data_i (req_wdata_i ), 79 | .valid_o (req_valid_o ), 80 | .ini_addr_o(req_ini_addr_o), 81 | .ready_i (req_ready_i ), 82 | .data_o (req_wdata_o ) 83 | ); 84 | 85 | simplex_xbar #( 86 | .NumIn (NumOut ), 87 | .NumOut (NumIn ), 88 | .DataWidth (RespDataWidth ), 89 | .ExtPrio (ExtPrio ), 90 | .AxiVldRdy (AxiVldRdy ), 91 | .SpillRegister (SpillRegisterResp ), 92 | .FallThroughRegister(FallThroughRegister) 93 | ) resp_xbar ( 94 | .clk_i (clk_i ), 95 | .rst_ni (rst_ni ), 96 | .rr_i (resp_rr_i ), 97 | .valid_i (resp_valid_i ), 98 | .ready_o (resp_ready_o ), 99 | .tgt_addr_i(resp_ini_addr_i), 100 | .data_i (resp_rdata_i ), 101 | .valid_o (resp_valid_o ), 102 | .ini_addr_o(/* Unused */ ), 103 | .ready_i (resp_ready_i ), 104 | .data_o (resp_rdata_o ) 105 | ); 106 | 107 | /****************** 108 | * Assertions * 109 | ******************/ 110 | 111 | if (NumIn <= 0) 112 | $fatal(1, "[full_duplex_xbar] NumIn needs to be larger than 0."); 113 | 114 | if (NumOut <= 0) 115 | $fatal(1, "[full_duplex_xbar] NumOut needs to be larger than 0."); 116 | 117 | endmodule : full_duplex_xbar 118 | -------------------------------------------------------------------------------- /rtl/variable_latency_interconnect/simplex_xbar.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Authors: Matheus Cavalcante , ETH Zurich 12 | // Michael Schaffner , ETH Zurich 13 | 14 | // Date: 16.01.2020 15 | // Description: Simplex (uni-directional) crossbar. 16 | 17 | module simplex_xbar #( 18 | parameter int unsigned NumIn = 4, // Number of Initiators 19 | parameter int unsigned NumOut = 4, // Number of Targets 20 | parameter int unsigned DataWidth = 32, // Data Width 21 | parameter bit ExtPrio = 1'b0, // Use external arbiter priority flags 22 | parameter bit AxiVldRdy = 1'b0, // Valid/ready signaling. 23 | parameter bit SpillRegister = 1'b0, 24 | parameter bit FallThroughRegister = 1'b0, 25 | // Dependent parameters, DO NOT OVERRIDE! 26 | localparam int unsigned NumInLog = NumIn == 1 ? 1 : $clog2(NumIn), 27 | localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut) 28 | ) ( 29 | input logic clk_i, 30 | input logic rst_ni, 31 | // External priority signal 32 | input logic [NumOut-1:0][NumInLog-1:0] rr_i, 33 | // Initiator side 34 | input logic [NumIn-1:0] valid_i, // Valid signal 35 | output logic [NumIn-1:0] ready_o, // Ready signal 36 | input logic [NumIn-1:0][NumOutLog-1:0] tgt_addr_i, // Target address 37 | input logic [NumIn-1:0][DataWidth-1:0] data_i, // Data 38 | // Target side 39 | output logic [NumOut-1:0] valid_o, // Valid signal 40 | input logic [NumOut-1:0] ready_i, // Ready signal 41 | output logic [NumOut-1:0][NumInLog-1:0] ini_addr_o, // Initiator address 42 | output logic [NumOut-1:0][DataWidth-1:0] data_o // Data 43 | ); 44 | 45 | /************* 46 | * Wires * 47 | *************/ 48 | 49 | logic [NumOut-1:0][ NumIn-1:0][DataWidth-1:0] tgt_data; 50 | logic [NumOut-1:0][ NumIn-1:0] tgt_ready, tgt_valid; 51 | 52 | logic [ NumIn-1:0][NumOut-1:0][DataWidth-1:0] ini_data; 53 | logic [ NumIn-1:0][NumOut-1:0] ini_ready, ini_valid; 54 | 55 | logic [NumOut-1:0] arb_valid, arb_ready; 56 | logic [NumOut-1:0][DataWidth-1:0] arb_data; 57 | logic [NumOut-1:0][NumInLog-1:0] arb_ini_addr; 58 | 59 | /****************** 60 | * Initiators * 61 | ******************/ 62 | 63 | for (genvar j = 0; unsigned'(j) < NumIn; j++) begin: gen_inputs 64 | 65 | /*********************** 66 | * Address decoder * 67 | ***********************/ 68 | 69 | // Instantiate a bank address decoder for each initiator 70 | addr_decoder #( 71 | .NumOut (NumOut ), 72 | .DataWidth(DataWidth), 73 | .AxiVldRdy(AxiVldRdy) 74 | ) i_addr_decoder ( 75 | // Initiator side 76 | .valid_i(valid_i[j] ), 77 | .addr_i (tgt_addr_i[j]), 78 | .data_i (data_i[j] ), 79 | .ready_o(ready_o[j] ), 80 | // Target side 81 | .valid_o(ini_valid[j] ), 82 | .ready_i(ini_ready[j] ), 83 | .data_o (ini_data[j] ) 84 | ); 85 | 86 | // Reshape connections between initiator and target 87 | for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_reshape 88 | assign tgt_valid[k][j] = ini_valid[j][k]; 89 | assign ini_ready[j][k] = tgt_ready[k][j]; 90 | assign tgt_data[k][j] = ini_data[j][k] ; 91 | end 92 | 93 | end : gen_inputs 94 | 95 | /*************** 96 | * Targets * 97 | ***************/ 98 | 99 | for (genvar k = 0; k < NumOut; k++) begin: gen_rr_outputs 100 | 101 | /**************** 102 | * Arbiters * 103 | ****************/ 104 | 105 | // Instantiate an RR arbiter for each target 106 | rr_arb_tree #( 107 | .NumIn (NumIn ), 108 | .DataWidth(DataWidth), 109 | .ExtPrio (ExtPrio ), 110 | .AxiVldRdy(AxiVldRdy) 111 | ) i_rr_arb_tree ( 112 | .clk_i (clk_i ), 113 | .rst_ni (rst_ni ), 114 | .flush_i(1'b0 ), 115 | .rr_i (rr_i[k] ), 116 | .req_i (tgt_valid[k] ), 117 | .gnt_o (tgt_ready[k] ), 118 | .data_i (tgt_data[k] ), 119 | .gnt_i (arb_ready[k] ), 120 | .req_o (arb_valid[k] ), 121 | .data_o (arb_data[k] ), 122 | .idx_o (arb_ini_addr[k]) 123 | ); 124 | 125 | // If not inserting spill-registers at all, or if inserting 126 | // a spill registers. 127 | if (!FallThroughRegister || SpillRegister) begin 128 | spill_register #( 129 | .Bypass(!SpillRegister ), 130 | .T (logic[DataWidth+NumInLog-1:0]) 131 | ) i_register ( 132 | .clk_i (clk_i ), 133 | .rst_ni (rst_ni ), 134 | .data_i ({arb_data[k], arb_ini_addr[k]}), 135 | .valid_i(arb_valid[k] ), 136 | .ready_o(arb_ready[k] ), 137 | .data_o ({data_o[k], ini_addr_o[k]} ), 138 | .valid_o(valid_o[k] ), 139 | .ready_i(ready_i[k] ) 140 | ); 141 | end else begin 142 | fall_through_register #( 143 | .T(logic[DataWidth+NumInLog-1:0]) 144 | ) i_register ( 145 | .clk_i (clk_i ), 146 | .rst_ni (rst_ni ), 147 | .clr_i (1'b0 ), 148 | .testmode_i(1'b0 ), 149 | .data_i ({arb_data[k], arb_ini_addr[k]}), 150 | .valid_i (arb_valid[k] ), 151 | .ready_o (arb_ready[k] ), 152 | .data_o ({data_o[k], ini_addr_o[k]} ), 153 | .valid_o (valid_o[k] ), 154 | .ready_i (ready_i[k] ) 155 | ); 156 | end 157 | 158 | end : gen_rr_outputs 159 | 160 | /****************** 161 | * Assertions * 162 | ******************/ 163 | 164 | if (NumIn <= 0) 165 | $fatal(1, "[simplex_xbar] NumIn needs to be larger than 0."); 166 | 167 | if (NumOut <= 0) 168 | $fatal(1, "[simplex_xbar] NumOut needs to be larger than 0."); 169 | 170 | endmodule : simplex_xbar 171 | -------------------------------------------------------------------------------- /src_files.yml: -------------------------------------------------------------------------------- 1 | low_latency_interco: 2 | incdirs: 3 | - rtl/low_latency_interco 4 | files: 5 | - rtl/low_latency_interco/FanInPrimitive_Req.sv 6 | - rtl/low_latency_interco/ArbitrationTree.sv 7 | - rtl/low_latency_interco/MUX2_REQ.sv 8 | - rtl/low_latency_interco/AddressDecoder_Resp.sv 9 | - rtl/low_latency_interco/TestAndSet.sv 10 | - rtl/low_latency_interco/RequestBlock2CH.sv 11 | - rtl/low_latency_interco/RequestBlock1CH.sv 12 | - rtl/low_latency_interco/FanInPrimitive_Resp.sv 13 | - rtl/low_latency_interco/ResponseTree.sv 14 | - rtl/low_latency_interco/ResponseBlock.sv 15 | - rtl/low_latency_interco/AddressDecoder_Req.sv 16 | - rtl/low_latency_interco/XBAR_TCDM.sv 17 | - rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv 18 | - rtl/low_latency_interco/TCDM_PIPE_REQ.sv 19 | - rtl/low_latency_interco/TCDM_PIPE_RESP.sv 20 | - rtl/low_latency_interco/grant_mask.sv 21 | - rtl/low_latency_interco/priority_Flag_Req.sv 22 | peripheral_interco: 23 | incdirs: [ 24 | rtl/peripheral_interco, 25 | ../../rtl/includes, 26 | ] 27 | files: [ 28 | rtl/peripheral_interco/AddressDecoder_PE_Req.sv, 29 | rtl/peripheral_interco/AddressDecoder_Resp_PE.sv, 30 | rtl/peripheral_interco/ArbitrationTree_PE.sv, 31 | rtl/peripheral_interco/FanInPrimitive_Req_PE.sv, 32 | rtl/peripheral_interco/RR_Flag_Req_PE.sv, 33 | rtl/peripheral_interco/MUX2_REQ_PE.sv, 34 | rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv, 35 | rtl/peripheral_interco/RequestBlock1CH_PE.sv, 36 | rtl/peripheral_interco/RequestBlock2CH_PE.sv, 37 | rtl/peripheral_interco/ResponseBlock_PE.sv, 38 | rtl/peripheral_interco/ResponseTree_PE.sv, 39 | rtl/peripheral_interco/XBAR_PE.sv, 40 | ] 41 | tcdm_interconnect: 42 | incdirs: [ 43 | rtl/low_latency_interco 44 | ] 45 | files: [ 46 | rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv, 47 | rtl/tcdm_interconnect/addr_dec_resp_mux.sv, 48 | rtl/tcdm_interconnect/amo_shim.sv, 49 | rtl/tcdm_interconnect/xbar.sv, 50 | rtl/tcdm_interconnect/clos_net.sv, 51 | rtl/tcdm_interconnect/bfly_net.sv, 52 | rtl/tcdm_interconnect/tcdm_interconnect.sv, 53 | ] 54 | -------------------------------------------------------------------------------- /tb/common/tb.svh: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2019 ETH Zurich, University of Bologna 2 | // All rights reserved. 3 | // 4 | // This code is under development and not yet released to the public. 5 | // Until it is released, the code is under the copyright of ETH Zurich and 6 | // the University of Bologna, and may contain confidential and/or unpublished 7 | // work. Any reuse/redistribution is strictly forbidden without written 8 | // permission from ETH Zurich. 9 | // 10 | // Bug fixes and contributions will eventually be released under the 11 | // SolderPad open hardware license in the context of the PULP platform 12 | // (http://www.pulp-platform.org), under the copyright of ETH Zurich and the 13 | // University of Bologna. 14 | // 15 | // Author: Michael Schaffner , ETH Zurich 16 | // Date: 15.08.2018 17 | // Description: 18 | // 19 | 20 | ////////////////////////////////////////////////////////////////////////////// 21 | // use to ensure proper ATI timing 22 | /////////////////////////////////////////////////////////////////////////////// 23 | 24 | `define APPL_ACQ_WAIT #(ACQ_DEL-APPL_DEL); 25 | 26 | `define WAIT_CYC(CLK, N) \ 27 | repeat(N) @(posedge(CLK)); 28 | 29 | `define WAIT(CLK, SIG) \ 30 | do begin \ 31 | @(posedge(CLK)); \ 32 | end while(SIG == 1'b0); 33 | 34 | `define WAIT_SIG(CLK,SIG) \ 35 | do begin \ 36 | @(posedge(CLK)); \ 37 | end while(SIG == 1'b0); 38 | 39 | `define APPL_WAIT_COMB_SIG(CLK,SIG) \ 40 | `APPL_ACQ_WAIT \ 41 | while(SIG == 1'b0) begin \ 42 | @(posedge(CLK)); \ 43 | #(ACQ_DEL); \ 44 | end 45 | 46 | `define APPL_WAIT_SIG(CLK,SIG) \ 47 | do begin \ 48 | @(posedge(CLK)); \ 49 | #(APPL_DEL); \ 50 | end while(SIG == 1'b0); 51 | 52 | `define ACQ_WAIT_SIG(CLK,SIG) \ 53 | do begin \ 54 | @(posedge(CLK)); \ 55 | #(ACQ_DEL); \ 56 | end while(SIG == 1'b0); 57 | 58 | 59 | `define APPL_WAIT_CYC(CLK, N) \ 60 | repeat(N) @(posedge(CLK)); \ 61 | #(tb_pkg::APPL_DEL); 62 | 63 | `define ACQ_WAIT_CYC(CLK, N) \ 64 | repeat(N) @(posedge(CLK)); \ 65 | #(tb_pkg::ACQ_DEL); 66 | 67 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | 8 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2019 ETH Zurich and University of Bologna. 2 | # Copyright and related rights are licensed under the Solderpad Hardware 3 | # License, Version 0.51 (the "License"); you may not use this file except in 4 | # compliance with the License. You may obtain a copy of the License at 5 | # http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | # or agreed to in writing, software, hardware and materials distributed under 7 | # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | # CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | # specific language governing permissions and limitations under the License. 10 | # 11 | # Author: Michael Schaffner , ETH Zurich 12 | # Date: 21.03.2019 13 | # Description: Makefile for the interconnect testbench. 14 | 15 | # 16 | eval-root := $(shell pwd) 17 | 18 | results-dir ?= sim-results 19 | library := work 20 | top-sim := tb 21 | top-synth := tcdm_interconnect_wrap 22 | 23 | batch-list ?= scripts/batch.list 24 | src-list := scripts/src.list 25 | tb-src-list := scripts/tb-src.list 26 | 27 | matlab-ver ?= matlab-2018b 28 | questa-ver ?= -10.5c 29 | vcs-ver ?= -2017.03 30 | 31 | compile_flag += -suppress 13262 -suppress 2583 32 | compile-flag-vcs += -full64 -sverilog +systemverilogext+.sv -timescale=1ps/1ps 33 | # +cover+i_dut -incr -64 -nologo -quiet 34 | sim_opts += -64 -voptargs="+acc" 35 | sim_opts_batch += -64 36 | #-voptargs="+acc" -64 37 | #-coverage -classdebug -voptargs="+acc" 38 | incdir +="$(shell pwd)/../common/"+"$(shell pwd)/../../rtl/low_latency_interco"+"$(shell pwd)/../../rtl/low_latency_interco"+"$(shell pwd)/hdl/" 39 | 40 | # points to DC folder 41 | dc-ver ?= synopsys-2018.06 dc_shell 42 | synth-dir := /usr/scratch2/toscana/michscha/projects/cluster_interconnect/tech/gf22/synopsys 43 | synth-script := scripts/synth.tcl 44 | 45 | 46 | # get sources 47 | src := $(addprefix $(eval-root)/,$(shell xargs printf '\n%s' < $(src-list) | cut -b 1-)) 48 | tb-src := $(addprefix $(eval-root)/,$(shell xargs printf '\n%s' < $(tb-src-list) | cut -b 1-)) 49 | 50 | # filter the batch-list first 51 | batch-name := $(shell cat $(batch-list) | grep -v '\#' | cut -d - -f 1) 52 | batch-config := $(shell cat $(batch-list) | grep -v '\#' | cut -d - -f 1-) 53 | 54 | build: clean 55 | vlib${questa-ver} $(library) 56 | vlog${questa-ver} -work $(library) -pedanticerrors $(src) $(tb-src) $(compile_flag) +incdir+$(incdir) 57 | 58 | # this starts modelsim with gui 59 | sim: build 60 | vsim${questa-ver} -lib $(library) $(top-sim) -do "do wave.do" $(sim_opts) 61 | 62 | # batch mode without gui 63 | simc: build 64 | vsim${questa-ver} -lib $(library) $(top-sim) -c -do "run -all; exit" $(sim_opts_batch) 65 | 66 | build-vcs: clean 67 | vcs${vcs-ver} vcs $(src) $(tb-src) $(compile-flag-vcs) +incdir+$(incdir) 68 | 69 | # TODO: implement VCS runs 70 | # this starts vcs with gui 71 | # sim-vcs: build-vcs 72 | # vsim${questa-ver} -lib $(library) $(top-sim) -do "do wave.do" $(sim_opts) 73 | 74 | # # batch mode without gui 75 | # simc-vcs: build-vcs 76 | # vsim${questa-ver} -lib $(library) $(top-sim) -c -do "run -all; exit" $(sim_opts_batch) 77 | 78 | clean: 79 | rm -rf $(library) 80 | rm -rf transcript statistics.log vsim.wlf modelsim.ini 81 | 82 | batch-clean-sim: 83 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _transcript.log, $(batch-name))) 84 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _statistics.log, $(batch-name))) 85 | 86 | batch-clean-synth: 87 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _synth.log, $(batch-name))) 88 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _timing.rpt, $(batch-name))) 89 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _power.rpt, $(batch-name))) 90 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _area.rpt, $(batch-name))) 91 | 92 | 93 | batch-clean: 94 | rm -rf $(batch-name) 95 | 96 | clean-all: clean batch-clean batch-clean-synth batch-clean-sim 97 | rm -rf $(results-dir) 98 | 99 | # runs the configurations defined in the batch-list file and gathers the statistics logs 100 | $(results-dir)/%_statistics.log: 101 | $(eval $@: name := $(subst _statistics.log,,$(subst $(results-dir)/,, $@))) 102 | mkdir -p $(name) 103 | vlib${questa-ver} $(name)/$(library) 104 | vlog${questa-ver} -work $(name)/$(library) -pedanticerrors $(src) $(tb-src) $(compile_flag) +incdir+$(incdir) $(addprefix +define+,$(subst $(name)-, , $(filter $(name)-%, $(batch-config)))) > $(name)/compile.log 105 | @echo $(name) started 106 | cd $(name) && vsim${questa-ver} -lib $(library) $(top-sim) -c -do "run -all; exit" $(sim_opts_batch) > /dev/null 107 | @echo $(name) finished 108 | cp $(name)/transcript $(results-dir)/$(name)_transcript.log 109 | cp $(name)/statistics.log $(results-dir)/$(name)_statistics.log 110 | 111 | batch-sim: 112 | mkdir -p $(results-dir) 113 | $(MAKE) $(addprefix $(results-dir)/, $(addsuffix _statistics.log, $(batch-name))) 114 | 115 | # mini prep script for DC that sets the required variables and calls a generic synthesis script 116 | dc-cmd = "set SRC {$(src)}; \ 117 | set TOP_ENTITY $(top-synth); \ 118 | set NAME $(name); \ 119 | set INCDIR $(incdir); \ 120 | set OUTDIR $(eval-root)/$(name)/ ; \ 121 | set LIB $(eval-root)/$(name)/$(library)-synth ; \ 122 | set DEFINE {$(subst +, ,$(subst $(name)-, , $(filter $(name)-%, $(batch-config)))) } ; \ 123 | source $(eval-root)/$(synth-script) \ 124 | " 125 | 126 | # synthesizes the configurations defined in the batch-list file and gathers the statistics logs 127 | $(results-dir)/%_area.rpt: 128 | $(eval $@: name := $(subst _area.rpt,,$(subst $(results-dir)/,, $@))) 129 | mkdir -p $(name) 130 | @echo $(name) started 131 | cd $(synth-dir) && $(dc-ver) -x $(dc-cmd) > $(eval-root)/$(name)/synth.log 132 | @echo $(name) finished 133 | cp $(name)/synth.log $(results-dir)/$(name)_synth.log 134 | cp $(name)/timing.rpt $(results-dir)/$(name)_timing.rpt 135 | cp $(name)/power.rpt $(results-dir)/$(name)_power.rpt 136 | cp $(name)/area.rpt $(results-dir)/$(name)_area.rpt 137 | 138 | batch-synth: 139 | mkdir -p $(results-dir) 140 | $(MAKE) $(addprefix $(results-dir)/, $(addsuffix _area.rpt, $(batch-name))) 141 | 142 | batch-plot: 143 | $(matlab-ver) -nosplash -nodesktop -r "addpath(genpath('./matlab')); run evaluation.m" 144 | 145 | batch-eval: batch-synth batch-sim 146 | $(MAKE) batch-plot 147 | 148 | .PHONY: build sim simc clean batch-clean clean-all batch-sim batch-synth batch-plot batch-eval 149 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/README.md: -------------------------------------------------------------------------------- 1 | # TCDM Interconnect - Testing and Exploration Framework 2 | 3 | This readme describes the testing and exploration framework that can be used to assess the `tcdm_interconnect` module. 4 | 5 | Make sure the toolversions configured in the Makefile exist on your machine. 6 | You can simulate the current default configuration as defined in `./hdl/defaults.svh` with the following command: 7 | 8 | ``` 9 | make sim 10 | ``` 11 | 12 | This invokes `make build` first and then runs simulation in questasim with gui. If you want to run this in console-only mode, do 13 | 14 | ``` 15 | make simc 16 | ``` 17 | 18 | In order to run the full evaluation in batch mode, you can call: 19 | 20 | ``` 21 | make batch-sim 22 | ``` 23 | 24 | This is a separate target that runs in several subfolders (one for each network configuration, as specified in `./scripts/batch.list`) and does not touch the standard, single simulation build described above. 25 | 26 | In order to run the batch synthesis, make sure that a valid IIS cockpit for FDX22 exists under the path `cluster_interconnect/tech/gf22`. Then you can synthesize the whole batch using 27 | 28 | ``` 29 | make batch-synth 30 | ``` 31 | 32 | The results of the batch synthesis and simulation are gathered in `sim-results`. You can selectively delete results in that folder and they will be regenerated upon invoking the batch targets above. In order to clean all temporary simulation / synthesis folders, invoke 33 | 34 | ``` 35 | make batch-clean 36 | ``` 37 | 38 | Note that the above command will not touch the `sim-results` folder. 39 | 40 | In order to parse and plot the results, either call 41 | 42 | ``` 43 | make batch-plot 44 | ``` 45 | 46 | or start Matlab in the same folder where this readme lives, open `./matlab/evaluation.m` in the Matlab editor and execute the script cells one by one or selectively. 47 | 48 | Note that if you run on a high core-count machine and have enough licenses available, you can parallelize the batch-synthesis and batch-simulation targets with `-jXX` where `XX` is the amount of jobs to start. 49 | 50 | For more details on the implementation and evaluation results, please see [this readme](../../rtl/tcdm_interconnect/README.md). 51 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/hdl/defaults.svh: -------------------------------------------------------------------------------- 1 | `ifndef MUT_IMPL 2 | `define MUT_IMPL 2 3 | `endif 4 | `ifndef NUM_MASTER 5 | `define NUM_MASTER 16 6 | `endif 7 | `ifndef BANK_FACT 8 | `define BANK_FACT 2 9 | `endif 10 | `ifndef DATA_WIDTH 11 | `define DATA_WIDTH 32 12 | `endif 13 | `ifndef TCDM_SIZE 14 | `define TCDM_SIZE 128*1024 15 | `endif 16 | `ifndef MEM_ADDR_BITS 17 | `define MEM_ADDR_BITS $clog2(`TCDM_SIZE/`NUM_MASTER/`BANK_FACT) 18 | `endif 19 | `ifndef PAR_STAGES 20 | `define PAR_STAGES 1 21 | `endif 22 | `ifndef TEST_CYCLES 23 | // scale this with the number of master ports (= bins) 24 | // for reliable statistics 25 | `define TEST_CYCLES (150*`NUM_MASTER) 26 | `endif 27 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/hdl/tb_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Date: 15.08.2018 13 | // Description: testbench package with some helper functions. 14 | 15 | 16 | package tb_pkg; 17 | 18 | // // for abs(double) function 19 | // import mti_cstdlib::*; 20 | 21 | // for timestamps 22 | import "DPI-C" \time = function int _time (inout int tloc[4]); 23 | import "DPI-C" function string ctime(inout int tloc[4]); 24 | 25 | /////////////////////////////////////////////////////////////////////////////// 26 | // parameters 27 | /////////////////////////////////////////////////////////////////////////////// 28 | 29 | // creates a 10ns ATI timing cycle 30 | time CLK_HI = 5ns; // set clock high time 31 | time CLK_LO = 5ns; // set clock low time 32 | time CLK_PERIOD = CLK_HI+CLK_LO; 33 | time APPL_DEL = 2ns; // set stimuli application delay 34 | time ACQ_DEL = 8ns; // set response aquisition delay 35 | 36 | parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... 37 | 38 | // tb_readport sequences 39 | typedef enum logic [2:0] { RANDOM_SEQ, LINEAR_SEQ, BURST_SEQ, IDLE_SEQ, WRAP_SEQ } seq_t; 40 | 41 | /////////////////////////////////////////////////////////////////////////////// 42 | // progress 43 | /////////////////////////////////////////////////////////////////////////////// 44 | 45 | class progress; 46 | real newState, oldState; 47 | longint numResp, acqCnt, errCnt, totAcqCnt, totErrCnt; 48 | string name; 49 | 50 | function new(string name); 51 | begin 52 | this.name = name; 53 | this.acqCnt = 0; 54 | this.errCnt = 0; 55 | this.newState = 0.0; 56 | this.oldState = 0.0; 57 | this.numResp = 1; 58 | this.totAcqCnt = 0; 59 | this.totErrCnt = 0; 60 | 61 | end 62 | endfunction : new 63 | 64 | function void reset(longint numResp_); 65 | begin 66 | this.acqCnt = 0; 67 | this.errCnt = 0; 68 | this.newState = 0.0; 69 | this.oldState = 0.0; 70 | this.numResp = numResp_; 71 | end 72 | endfunction : reset 73 | 74 | function void addRes(int isError); 75 | begin 76 | this.acqCnt++; 77 | this.totAcqCnt++; 78 | this.errCnt += isError; 79 | this.totErrCnt += isError; 80 | 81 | if(ERROR_CNT_STOP_LEVEL <= this.errCnt && ERROR_CNT_STOP_LEVEL > 0) begin 82 | $error("%s> simulation stopped (ERROR_CNT_STOP_LEVEL = %d reached).", this.name, ERROR_CNT_STOP_LEVEL); 83 | $stop(); 84 | end 85 | end 86 | endfunction : addRes 87 | 88 | function void print(); 89 | begin 90 | this.newState = $itor(this.acqCnt) / $itor(this.numResp); 91 | if(this.newState - this.oldState >= 0.01) begin 92 | $display("%s> validated %03d%% -- %01d failed (%03.3f%%) ", 93 | this.name, 94 | $rtoi(this.newState*100.0), 95 | this.errCnt, 96 | $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); 97 | // $fflush(); 98 | this.oldState = this.newState; 99 | end 100 | end 101 | endfunction : print 102 | 103 | function void printToFile(string file, bit summary = 0); 104 | begin 105 | int fptr; 106 | 107 | // sanitize string 108 | for(fptr=0; fptr, ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Calculates (abstract) clos cost in dependence of #banks, banking factor 14 | % and redundancy factor. The function also outputs the optimum network 15 | % configuration for a specific parameterisation (in terms of N, M, R). 16 | % 17 | % Usage: [cost, n, m, r] = clos_cost(k, b, c) 18 | % 19 | % Inputs: - k: number of banks 20 | % - b: banking factor 21 | % - c: redundancy factor 22 | % 23 | % Outputs: - cost: abstract area cost 24 | % - n, m, r: optimum clos configuration 25 | % 26 | % See also: gen_clos_params 27 | % 28 | 29 | function [cost, n, m, r] = clos_cost(k, b, c) 30 | % clos_cost Calculates (abstract) clos cost in dependence of #banks, banking factor 31 | % and redundancy factor. The function also outputs the optimum network 32 | % configuration for a specific parameterisation (in terms of N, M, R). 33 | 34 | n = 2.^ceil(log2(sqrt(k ./ (1+1./b)))); 35 | m = 2.^ceil(log2(c.*n)); 36 | r = 2.^ceil(log2(k./n)); 37 | cost = r.*n./b.*m + m.*r.^2 + r.*m.*n; 38 | 39 | if length(k) == 1 40 | fprintf('\nClos cost: \nk=%d, b=%d, c=%d\nm=%d, n=%d, r=%d\n-> cost = %.2f\n\n', k, b, c, m, n, r, cost); 41 | end 42 | end -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/matlab/evaluation.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Result parsing and plotting master script for network evaluation. 14 | 15 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 16 | %% Setup and Result Parsing 17 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 18 | 19 | addpath(genpath('./matlab')); 20 | mkdir plots 21 | 22 | % get simulation results 23 | [stats] = read_stats('sim-results'); 24 | % check for outliers (== implementation or arbitration bugs!) 25 | fairness_test(stats, 0.13); 26 | % annotate this with synthesis results 27 | stats = read_synth('sim-results', stats); 28 | 29 | % backup results 30 | save('plots/stats.mat','stats'); 31 | 32 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 33 | %% Statistical Evaluation 34 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 35 | 36 | %% clos networks 37 | plot_tests(stats, {'32x32','32x64','32x128'}, {'clos_2mn', 'clos_m1n', 'clos_m2n','lic'}); 38 | export_fig 'plots/stats_clos_32x' -png -pdf 39 | %% selection x8 40 | networkSel = {'bfly2_n1', 'bfly2_n2','bfly2_n4','bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 41 | plot_tests(stats, {'8x8','8x16','8x32'}, networkSel); 42 | export_fig 'plots/stats_selection_8x' -png -pdf 43 | %% selection x16 44 | networkSel = {'bfly2_n1', 'bfly2_n2','bfly2_n4','bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 45 | plot_tests(stats, {'16x16','16x32','16x64'}, networkSel); 46 | export_fig 'plots/stats_selection_16x' -png -pdf 47 | %% selection x32 48 | networkSel = {'bfly2_n1', 'bfly2_n2','bfly2_n4','bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 49 | plot_tests(stats, {'32x32','32x64','32x128'}, networkSel); 50 | export_fig 'plots/stats_selection_32x' -png -pdf 51 | %% selection x64 52 | networkSel = {'bfly2_n1', 'bfly2_n2','bfly2_n4','bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 53 | plot_tests(stats, {'64x64','64x128','64x256'}, networkSel); 54 | export_fig 'plots/stats_selection_64x' -png -pdf 55 | %% selection x128 56 | networkSel = {'bfly2_n1', 'bfly2_n2','bfly2_n4','bfly4_n1', 'bfly4_n2','bfly4_n4', 'bfly4_n8', 'lic'}; 57 | plot_tests(stats, {'128x128','128x256','128x512'}, networkSel); 58 | export_fig 'plots/stats_selection_128x' -png -pdf 59 | %% selection x256 60 | networkSel = {'bfly2_n4','bfly4_n1', 'bfly4_n2','bfly4_n4', 'bfly4_n8', 'lic'}; 61 | plot_tests(stats, {'256x256','256x512','256x1024'}, networkSel); 62 | export_fig 'plots/stats_selection_256x' -png -pdf 63 | %% plot only banking factor 2 64 | plot_tests(stats, {'64x64','64x128','64x256'}, {'bfly4_n1', 'clos_2mn', 'clos_m1n', 'clos_m2n','lic'}); 65 | export_fig 'plots/stats_bf2_64x' -png -pdf 66 | 67 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 68 | %% Pareto Plots 69 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 70 | 71 | %% 8 masters 72 | networkSel = {'clos_2mn', 'clos_m1n', 'clos_m2n', 'bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 73 | scatterplot_tests(stats, '8x', networkSel,'random uniform (p_{req}=1.00)'); 74 | export_fig 'plots/pareto_random_uniform_8x' -png -pdf 75 | %% 76 | scatterplot_tests(stats, '8x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 77 | export_fig 'plots/pareto_random_linear_8x' -png -pdf 78 | %% 16 masters 79 | networkSel = {'clos_2mn', 'clos_m1n', 'clos_m2n', 'bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 80 | scatterplot_tests(stats, '16x', networkSel,'random uniform (p_{req}=1.00)'); 81 | export_fig 'plots/pareto_random_uniform_16x' -png -pdf 82 | %% 83 | scatterplot_tests(stats, '16x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 84 | export_fig 'plots/pareto_random_linear_16x' -png -pdf 85 | %% 32 masters 86 | networkSel = {'clos_2mn', 'clos_m1n', 'clos_m2n', 'bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 87 | scatterplot_tests(stats, '32x', networkSel,'random uniform (p_{req}=1.00)'); 88 | export_fig 'plots/pareto_random_uniform_32x' -png -pdf 89 | %% 90 | scatterplot_tests(stats, '32x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 91 | export_fig 'plots/pareto_random_linear_32x' -png -pdf 92 | %% 64 masters 93 | networkSel = {'clos_2mn', 'clos_m1n', 'clos_m2n', 'bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 94 | scatterplot_tests(stats, '64x', networkSel,'random uniform (p_{req}=1.00)'); 95 | export_fig 'plots/pareto_random_uniform_64x' -png -pdf 96 | %% 97 | scatterplot_tests(stats, '64x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 98 | export_fig 'plots/pareto_random_linear_64x' -png -pdf 99 | %% 128 masters 100 | networkSel = {'clos_2mn', 'clos_m1n', 'clos_m2n', 'bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4','bfly4_n8', 'lic'}; 101 | scatterplot_tests(stats, '128x', networkSel,'random uniform (p_{req}=1.00)'); 102 | export_fig 'plots/pareto_random_uniform_128x' -png -pdf 103 | %% 104 | scatterplot_tests(stats, '128x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 105 | export_fig 'plots/pareto_random_linear_128x' -png -pdf 106 | %% 256 masters 107 | networkSel = {'bfly4_n1', 'bfly4_n2','bfly4_n4','bfly4_n8', 'lic'}; 108 | scatterplot_tests(stats, '256x', networkSel,'random uniform (p_{req}=1.00)'); 109 | export_fig 'plots/pareto_random_uniform_256x' -png -pdf 110 | %% 111 | scatterplot_tests(stats, '256x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 112 | export_fig 'plots/pareto_random_linear_256x' -png -pdf 113 | 114 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 115 | %% Pareto Plots 116 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 117 | %% scaling behavior with BF=1 118 | networkSel = {'bfly4_n1', 'bfly4_n2','bfly4_n4','bfly4_n8', 'lic'}; 119 | plot_scaling(stats, {'8x8','16x16','32x32','64x64','128x128','256x256'}, networkSel); 120 | export_fig 'plots/scaling_bf1' -png -pdf 121 | %% scaling behavior with BF=2 122 | plot_scaling(stats, {'8x16','16x32','32x64','64x128','128x256','256x512'}, networkSel); 123 | export_fig 'plots/scaling_bf2' -png -pdf 124 | %% scaling behavior with BF=4 125 | plot_scaling(stats, {'8x32','16x64','32x128','64x256','128x512','256x1024'}, networkSel); 126 | export_fig 'plots/scaling_bf4' -png -pdf 127 | %% for batch use 128 | exit(0); -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/matlab/fairness_test.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Checks whether grant probability std deviation is within 14 | % tolerance. This can be used as a quick sanity check since arbitration or 15 | % implementation errors often result in a non-uniform grant probability 16 | % when comparing across master ports. 17 | % 18 | % Usage: [idx] = fairness_test(stats, tol) 19 | % 20 | % Inputs: - stats: statistics struct, created with read_stats. 21 | % - tol: tolerance for std deviation 22 | % 23 | % Outputs: - idx: indices of failing tests. 24 | % 25 | % See also: read_stats, read_synth, plot_tests, 26 | % plot_tests, plot_scaling, scatterplot_tests 27 | 28 | function [idx] = fairness_test(stats, tol) 29 | %fairness_test checks whether grant probability std deviation is within tolerance 30 | 31 | fprintf('\nFairness check with tol=%.2f\n\n', tol); 32 | failingTests = ''; 33 | idx = []; 34 | for k = 1:length(stats.ports) 35 | tst_mean = mean(stats.ports{k}(:,2)); 36 | tst_std = std(stats.ports{k}(:,2)); 37 | str = 'OK'; 38 | str2 = ''; 39 | if tst_std ./ tst_mean > tol 40 | str = 'FAILED'; 41 | str2 = [stats.network{k} ' ' stats.configs{k} ' ' stats.testNameFull{k}]; 42 | failingTests = [failingTests str2 '\n']; 43 | end 44 | fprintf('> mean=%04.2f std=%04.2f -> %s %s\n', tst_mean, tst_std, str, str2); 45 | idx = [idx k]; 46 | end 47 | 48 | if ~isempty(failingTests) 49 | fprintf(['\n\nSome tests have failed:\n', failingTests]); 50 | else 51 | fprintf('\n\nAll tests passed with tol=%.2f!\n', tol); 52 | end 53 | end 54 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/matlab/gen_clos_params.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: This generates the clos parameters, to be dumped into the SV wrapper 14 | 15 | k = [2:12]; 16 | bankFacts = [0:4]; 17 | redFacts = [0.5,1,2]; 18 | width = 16; 19 | 20 | fprintf('\n\n'); 21 | fprintf('// LUT params for Clos net with configs: '); 22 | fprintf('%d: m=%.2f*n, ',[1:length(redFacts); redFacts]); 23 | fprintf('\n// to be indexed with [config_idx][$clog2(BankingFact)][$clog2(NumBanks)]\n'); 24 | fprintf('// generated with MATLAB script gen_clos_params.m\n'); 25 | chars = ['N','M','R']; 26 | for j = 1:3 27 | str = sprintf('localparam logic [%d:%d][%d:%d][%d:%d][%d:0] clos%s = {',length(redFacts),1,max(bankFacts),min(bankFacts),max(k),min(k),width-1,chars(j)); 28 | fprintf(str); 29 | for c = fliplr(redFacts) 30 | for b = fliplr(2.^bankFacts) 31 | [~,n,m,r] = clos_cost(fliplr(2.^k), b, c); 32 | switch j 33 | case 1 34 | tmp=n; 35 | case 2 36 | tmp=m; 37 | case 3 38 | tmp=r; 39 | end 40 | if b == 2^bankFacts(1) && c == redFacts(1) 41 | fprintf('%d''d%d,',[repmat(width,[1 length(k)-1]); tmp(1:end-1)]); 42 | fprintf('%d''d%d',width,tmp(end)); 43 | fprintf('};\n'); 44 | else 45 | fprintf('%d''d%d,',[repmat(width,[1 length(k)]); tmp]); 46 | fprintf('\n'); 47 | fprintf(repmat(' ',[1, length(str)])); 48 | end 49 | end 50 | end 51 | end 52 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/matlab/plot_scaling.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Plot scaling behavior of different networks, i.e. area in 14 | % dependency of the Master x Slave configuration. 15 | % 16 | % Usage: [] = plot_scaling(stats, configLabels, netLabels) 17 | % 18 | % Inputs: - stats: statistics struct, created with read_stats. 19 | % - configLabels: cell array with network port configs, e.g. {'64x128', '64x256'} 20 | % - netLabels: cell array with network labels, e.g. {'lic', 'bfly4_n1'} 21 | % 22 | % See also: read_stats, fairness_test, read_synth, plot_tests, 23 | % plot_tests, scatterplot_tests 24 | 25 | 26 | function [] = plot_scaling(stats, configLabels, netLabels) 27 | % plot_scaling Plot scaling behavior of different networks, i.e. area in 28 | % dependency of the Master x Slave configuration. 29 | 30 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 31 | %% global plot configs 32 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 33 | 34 | close; 35 | figure; 36 | 37 | cols = colormap('lines'); 38 | markers = ['o','d','s','<','>','v','h','^','+','-','x','.']; 39 | 40 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 41 | %% preprocess args 42 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 43 | 44 | fprintf('\n'); 45 | 46 | if ~isempty(netLabels) 47 | tmp = {}; 48 | for k = 1:length(netLabels) 49 | if any(strcmp(netLabels{k},stats.netTypes)) 50 | tmp = [tmp netLabels(k)]; 51 | else 52 | warning('netType %s not found in batch results, skipping config...', netLabels{k}); 53 | end 54 | end 55 | netLabels = tmp; 56 | else 57 | netLabels = stats.netTypes; 58 | end 59 | 60 | if isempty(configLabels) 61 | configLabels=stats.configLabels; 62 | end 63 | 64 | masterConfigs = []; 65 | bankFacts = []; 66 | for k=1:length(configLabels) 67 | tmp = sscanf(configLabels{k},'%dx%d'); 68 | masterConfigs(k)=tmp(1); 69 | bankFacts(k)=tmp(2)/tmp(1); 70 | % for j=1:length(configLabels{k}) 71 | % if configLabels{k}(j) == 'x' 72 | % masterConfigs{k} = configLabels{k}(1:j-1); 73 | % end 74 | % end 75 | end 76 | 77 | masterConfigs = unique(masterConfigs); 78 | bankFacts = unique(bankFacts); 79 | 80 | 81 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 82 | %% gather results 83 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 84 | 85 | res=nan(length(netLabels),length(bankFacts),length(masterConfigs)); 86 | for n=1:length(netLabels) 87 | for c=1:length(configLabels) 88 | tst2=strcmp(configLabels{c}, stats.configLabels); 89 | tst3=strcmp(netLabels{n}, stats.netTypes); 90 | 91 | idx2 = find(tst2,1); 92 | idx3 = find(tst3,1); 93 | 94 | tmp = sscanf(configLabels{c},'%dx%d'); 95 | 96 | tst = masterConfigs == tmp(1); 97 | idx = find(tst,1); 98 | tst4 = bankFacts == tmp(2)/tmp(1); 99 | idx4 = find(tst4,1); 100 | 101 | res(n,idx4,idx) = stats.synthArea(idx3,idx2,1); 102 | end 103 | end 104 | 105 | labels = {}; 106 | 107 | for n=1:length(netLabels) 108 | for c=1:length(bankFacts) 109 | labels = [labels {[netLabels{n} '_bf' num2str(bankFacts(c))]}]; 110 | end 111 | end 112 | 113 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 114 | %% plot #ports versus area 115 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 116 | 117 | hold on; 118 | for k=1:size(res,1) 119 | for j=1:size(res,2) 120 | plot(masterConfigs,squeeze(res(k,j,:)),'--','marker',markers(j),'color',cols(k,:),'markerEdgeColor','k','markerFaceColor',cols(k,:)); 121 | end 122 | end 123 | box on; 124 | grid on; 125 | 126 | legend(labels,'interpreter','none'); 127 | xticks(masterConfigs) 128 | set(gca,'yscale','log'); 129 | set(gca,'xscale','log'); 130 | 131 | title('scaling behavior'); 132 | xlabel('master ports'); 133 | ylabel('complexity [\mum^2]'); 134 | 135 | end -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/matlab/read_synth.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: This function reads synthesis results and annotates the stats struct 14 | % configurations with no synthesis result will be set to NaN. 15 | % 16 | % Usage: [stats] = read_synth(directory, stats) 17 | % 18 | % Inputs: - directory: directory to simulation output folder. 19 | % - stats: statistics struct, created with read_stats. 20 | % 21 | % Outputs: - stats: annotated statistics struct. 22 | % 23 | % See also: fairness_test, read_stats, plot_tests, 24 | % plot_tests, plot_scaling, scatterplot_tests 25 | 26 | function [stats] = read_synth(directory, stats) 27 | % read_synth this function reads synthesis results and annotates the stats struct 28 | % configurations with no synthesis result will be set to NaN. 29 | 30 | fprintf('\nreading synthesis results...\n'); 31 | 32 | stats.synthArea = nan(length(stats.netTypes), length(stats.configLabels), 3); 33 | stats.synthSlack = nan(length(stats.netTypes), length(stats.configLabels)); 34 | numFiles = 0; 35 | numSkipped = 0; 36 | for k = 1:length(stats.netTypes) 37 | for j = 1:length(stats.configLabels) 38 | fileName = [directory filesep stats.netTypes{k} '_' stats.configLabels{j} '_area.rpt']; 39 | 40 | if exist(fileName, 'file') 41 | [~,out] = system(['grep "Total cell area:" ' fileName ' | awk -e ''{print $4;}'' ']); 42 | stats.synthArea(k,j,1) = sscanf(out,'%f',1); 43 | [~,out] = system(['grep "Combinational area:" ' fileName ' | awk -e ''{print $3;}'' ']); 44 | stats.synthArea(k,j,2) = sscanf(out,'%f',1); 45 | [~,out] = system(['grep "Noncombinational area:" ' fileName ' | awk -e ''{print $3;}'' ']); 46 | stats.synthArea(k,j,3) = sscanf(out,'%f',1); 47 | numFiles = numFiles + 1; 48 | else 49 | warning('No Synthesis results found for %s', [stats.netTypes{k} '_' stats.configLabels{j}]); 50 | numSkipped = numSkipped + 1; 51 | end 52 | 53 | fileName = [directory filesep stats.netTypes{k} '_' stats.configLabels{j} '_timing.rpt']; 54 | 55 | if exist(fileName, 'file') 56 | [~,out] = system(['grep "slack" ' fileName ' | awk -e ''{print $3;}'' ']); 57 | stats.synthSlack(k,j) = sscanf(out,'%f',1); 58 | else 59 | warning('No Timing results found for %s', [stats.netTypes{k} '_' stats.configLabels{j}]); 60 | end 61 | end 62 | end 63 | 64 | fprintf('read %d synthesis results (%d skipped)\n\n', numFiles, numSkipped); 65 | end -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/plots/pareto_random_linear_128x.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cluster_interconnect/2967d8d17be0a6139229ca8d3d4956e182aec3de/tb/tb_tcdm_interconnect/plots/pareto_random_linear_128x.pdf -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/scripts/batch-clos.list: -------------------------------------------------------------------------------- 1 | ####################### 8 masters ####################### 2 | lic_8x8-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=8 3 | lic_8x16-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=8 4 | lic_8x32-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=8 5 | # 6 | clos_m2n_8x8-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=1+NUM_MASTER=8 7 | clos_m2n_8x16-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=2+NUM_MASTER=8 8 | clos_m2n_8x32-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=4+NUM_MASTER=8 9 | clos_m1n_8x8-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=1+NUM_MASTER=8 10 | clos_m1n_8x16-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=2+NUM_MASTER=8 11 | clos_m1n_8x32-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=4+NUM_MASTER=8 12 | clos_2mn_8x8-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=1+NUM_MASTER=8 13 | clos_2mn_8x16-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=2+NUM_MASTER=8 14 | clos_2mn_8x32-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=4+NUM_MASTER=8 15 | # 16 | ######################## 16 masters ####################### 17 | lic_16x16-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=16 18 | lic_16x32-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=16 19 | lic_16x64-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=16 20 | # 21 | clos_m2n_16x16-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=1+NUM_MASTER=16 22 | clos_m2n_16x32-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=2+NUM_MASTER=16 23 | clos_m2n_16x64-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=4+NUM_MASTER=16 24 | clos_m1n_16x16-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=1+NUM_MASTER=16 25 | clos_m1n_16x32-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=2+NUM_MASTER=16 26 | clos_m1n_16x64-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=4+NUM_MASTER=16 27 | clos_2mn_16x16-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=1+NUM_MASTER=16 28 | clos_2mn_16x32-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=2+NUM_MASTER=16 29 | clos_2mn_16x64-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=4+NUM_MASTER=16 30 | # 31 | ####################### 32 masters ####################### 32 | lic_32x32-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=32 33 | lic_32x64-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=32 34 | lic_32x128-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=32 35 | # 36 | clos_m2n_32x32-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=1+NUM_MASTER=32 37 | clos_m2n_32x64-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=2+NUM_MASTER=32 38 | clos_m2n_32x128-BATCH_SIM=1+MUT_IMPL=3+BANK_FACT=4+NUM_MASTER=32 39 | clos_m1n_32x32-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=1+NUM_MASTER=32 40 | clos_m1n_32x64-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=2+NUM_MASTER=32 41 | clos_m1n_32x128-BATCH_SIM=1+MUT_IMPL=4+BANK_FACT=4+NUM_MASTER=32 42 | clos_2mn_32x32-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=1+NUM_MASTER=32 43 | clos_2mn_32x64-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=2+NUM_MASTER=32 44 | clos_2mn_32x128-BATCH_SIM=1+MUT_IMPL=5+BANK_FACT=4+NUM_MASTER=32 45 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/scripts/src.list: -------------------------------------------------------------------------------- 1 | ../../rtl/low_latency_interco/AddressDecoder_Req.sv 2 | ../../rtl/low_latency_interco/AddressDecoder_Resp.sv 3 | ../../rtl/low_latency_interco/ArbitrationTree.sv 4 | ../../rtl/low_latency_interco/FanInPrimitive_Req.sv 5 | ../../rtl/low_latency_interco/FanInPrimitive_Resp.sv 6 | ../../rtl/low_latency_interco/grant_mask.sv 7 | ../../rtl/low_latency_interco/parameters.v 8 | ../../rtl/low_latency_interco/priority_Flag_Req.sv 9 | ../../rtl/low_latency_interco/RequestBlock1CH.sv 10 | ../../rtl/low_latency_interco/RequestBlock2CH.sv 11 | ../../rtl/low_latency_interco/ResponseBlock.sv 12 | ../../rtl/low_latency_interco/ResponseTree.sv 13 | ../../rtl/low_latency_interco/TCDM_PIPE_REQ.sv 14 | ../../rtl/low_latency_interco/TCDM_PIPE_RESP.sv 15 | ../../rtl/low_latency_interco/TestAndSet.sv 16 | ../../rtl/low_latency_interco/XBAR_TCDM.sv 17 | ../../rtl/low_latency_interco/tcdm_xbar_wrap.sv 18 | ../../../common_cells/src/lzc.sv 19 | ../../../common_cells/src/lfsr.sv 20 | ../../../common_cells/src/rr_arb_tree.sv 21 | ../../rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv 22 | ../../rtl/tcdm_interconnect/addr_dec_resp_mux.sv 23 | ../../rtl/tcdm_interconnect/xbar.sv 24 | ../../rtl/tcdm_interconnect/bfly_net.sv 25 | ../../rtl/tcdm_interconnect/clos_net.sv 26 | ../../rtl/tcdm_interconnect/tcdm_interconnect.sv 27 | hdl/tcdm_interconnect_wrap.sv 28 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/scripts/synth.list: -------------------------------------------------------------------------------- 1 | ../../rtl/low_latency_interco/AddressDecoder_Req.sv 2 | ../../rtl/low_latency_interco/AddressDecoder_Resp.sv 3 | ../../rtl/low_latency_interco/ArbitrationTree.sv 4 | ../../rtl/low_latency_interco/FanInPrimitive_Req.sv 5 | ../../rtl/low_latency_interco/FanInPrimitive_Resp.sv 6 | ../../rtl/low_latency_interco/grant_mask.sv 7 | ../../rtl/low_latency_interco/parameters.v 8 | ../../rtl/low_latency_interco/priority_Flag_Req.sv 9 | ../../rtl/low_latency_interco/RequestBlock1CH.sv 10 | ../../rtl/low_latency_interco/RequestBlock2CH.sv 11 | ../../rtl/low_latency_interco/ResponseBlock.sv 12 | ../../rtl/low_latency_interco/ResponseTree.sv 13 | ../../rtl/low_latency_interco/TCDM_PIPE_REQ.sv 14 | ../../rtl/low_latency_interco/TCDM_PIPE_RESP.sv 15 | ../../rtl/low_latency_interco/TestAndSet.sv 16 | ../../rtl/low_latency_interco/XBAR_TCDM.sv 17 | ../../rtl/low_latency_interco/tcdm_xbar_wrap.sv 18 | ../../../common_cells/src/lzc.sv 19 | ../../../common_cells/src/lfsr.sv 20 | ../../../common_cells/src/rr_arb_tree.sv 21 | ../../rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv 22 | ../../rtl/tcdm_interconnect/addr_dec_resp_mux.sv 23 | ../../rtl/tcdm_interconnect/xbar.sv 24 | ../../rtl/tcdm_interconnect/bfly_net.sv 25 | ../../rtl/tcdm_interconnect/clos_net.sv 26 | ../../rtl/tcdm_interconnect/tcdm_interconnect.sv 27 | hdl/tcdm_interconnect_wrap.sv 28 | -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/scripts/synth.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2019 ETH Zurich and University of Bologna. 2 | # Copyright and related rights are licensed under the Solderpad Hardware 3 | # License, Version 0.51 (the "License"); you may not use this file except in 4 | # compliance with the License. You may obtain a copy of the License at 5 | # http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | # or agreed to in writing, software, hardware and materials distributed under 7 | # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | # CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | # specific language governing permissions and limitations under the License. 10 | # 11 | # Author: Michael Schaffner , ETH Zurich 12 | # Date: 06.03.2019 13 | # Description: Synthesis script for TCDM interconnect 14 | 15 | ##################### 16 | ## SETUP ## 17 | ##################### 18 | 19 | echo "----------------------------------" 20 | echo "--- Synthesis Script Arguments ---" 21 | echo "----------------------------------" 22 | echo "SRC: $SRC " 23 | echo "TOP_ENTITY: $TOP_ENTITY " 24 | echo "NAME: $NAME " 25 | echo "INCDIR: $INCDIR " 26 | echo "OUTDIR: $OUTDIR " 27 | echo "DEFINE: $DEFINE " 28 | echo "LIB: $LIB " 29 | echo "----------------------------------" 30 | 31 | set CPUS 1 32 | set VARIANT "hp" 33 | set TCK 1000 34 | set CORNER_TRIM 0 35 | 36 | ##################### 37 | ## SET LIBRARY ## 38 | ##################### 39 | 40 | # TODO: set library and operating point here 41 | 42 | # TODO: define the following variables 43 | # set driving_cell 44 | # set driving_cell_clk 45 | # set load_cell 46 | # set load_lib 47 | 48 | ###################### 49 | ## CLOCK GATING ## 50 | ###################### 51 | 52 | set_clock_gating_style -num_stages 1 \ 53 | -positive_edge_logic integrated \ 54 | -control_point before \ 55 | -control_signal scan_enable 56 | 57 | ########################### 58 | ## ELABORATE DESIGN ## 59 | ########################### 60 | 61 | # make library 62 | sh mkdir -p $LIB 63 | define_design_lib WORK -path $LIB 64 | 65 | # delete previous designs. 66 | remove_design -designs 67 | sh rm -rf $LIB/* 68 | 69 | set CLK_PIN clk_i 70 | set RST_PIN rst_ni 71 | 72 | analyze -format sv $SRC -define $DEFINE 73 | 74 | elaborate ${TOP_ENTITY} 75 | 76 | ########################### 77 | ## APPLY CONSTRAINTS ## 78 | ########################### 79 | 80 | set IN_DEL 0.0 81 | set OUT_DEL 0.0 82 | set DELAY $TCK 83 | 84 | create_clock ${CLK_PIN} -period ${TCK} 85 | 86 | set_ideal_network ${CLK_PIN} 87 | set_ideal_network ${RST_PIN} 88 | 89 | set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs] 90 | set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${CLK_PIN}}] -clock ${CLK_PIN} 91 | set_output_delay ${OUT_DEL} [all_outputs] -clock ${CLK_PIN} 92 | 93 | set_driving_cell -no_design_rule -lib_cell ${driving_cell} -pin Z [all_inputs] 94 | set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs] 95 | 96 | ####################### 97 | ## COMPILE ULTRA ## 98 | ####################### 99 | 100 | compile_ultra -gate_clock -scan 101 | 102 | ################# 103 | ## NETLIST ## 104 | ################# 105 | 106 | change_names -rules verilog -hierarchy 107 | define_name_rules fixbackslashes -allowed "A-Za-z0-9_" -first_restricted "\\" -remove_chars 108 | change_names -rule fixbackslashes -h 109 | write_file -format ddc -hierarchy -output $OUTDIR/design.ddc 110 | write_file -format verilog -hierarchy -output $OUTDIR/design.v 111 | 112 | ################# 113 | ## REPORTS ## 114 | ################# 115 | 116 | report_power -hierarchy > $OUTDIR/power.rpt 117 | report_timing > $OUTDIR/timing.rpt 118 | report_area -hierarchy > $OUTDIR/area.rpt 119 | 120 | exit -------------------------------------------------------------------------------- /tb/tb_tcdm_interconnect/scripts/tb-src.list: -------------------------------------------------------------------------------- 1 | hdl/tb_pkg.sv 2 | hdl/tb.sv 3 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | plots 8 | sim-results 9 | scripts/synth.tcl 10 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2019 ETH Zurich and University of Bologna. 2 | # Copyright and related rights are licensed under the Solderpad Hardware 3 | # License, Version 0.51 (the "License"); you may not use this file except in 4 | # compliance with the License. You may obtain a copy of the License at 5 | # http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | # or agreed to in writing, software, hardware and materials distributed under 7 | # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | # CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | # specific language governing permissions and limitations under the License. 10 | 11 | # Author: Michael Schaffner , ETH Zurich 12 | # Date: 21.03.2019 13 | # Description: Makefile for the interconnect testbench. 14 | 15 | eval-root := $(shell pwd) 16 | 17 | results-dir ?= sim-results 18 | library := work 19 | top-sim := variable_latency_interconnect_tb 20 | top-synth := variable_latency_interconnect_wrap 21 | 22 | batch-list ?= scripts/batch.list 23 | src-list := scripts/src.list 24 | tb-src-list := scripts/tb-src.list 25 | 26 | matlab-ver ?= matlab-2018b 27 | questa-ver ?= questa-2019.3 28 | vcs-ver ?= -2017.03 29 | 30 | compile_flag += -suppress 13262 -suppress 2583 31 | compile-flag-vcs += -full64 -sverilog +systemverilogext+.sv -timescale=1ps/1ps 32 | sim_opts += -64 -voptargs="+acc" 33 | sim_opts_batch += -64 34 | incdir +="$(shell pwd)/../common/"+"$(shell pwd)/../../rtl/low_latency_interco"+"$(shell pwd)/../../rtl/low_latency_interco"+"$(shell pwd)/hdl/" 35 | 36 | # points to DC folder 37 | dc-ver ?= synopsys-2018.06 dc_shell 38 | synth-dir ?= gf22/synopsys 39 | synth-script := scripts/synth.tcl 40 | 41 | # get sources 42 | src := $(addprefix $(eval-root)/,$(shell xargs printf '\n%s' < $(src-list) | cut -b 1-)) 43 | tb-src := $(addprefix $(eval-root)/,$(shell xargs printf '\n%s' < $(tb-src-list) | cut -b 1-)) 44 | 45 | # filter the batch-list first 46 | batch-name := $(shell cat $(batch-list) | grep -v '\#' | cut -d - -f 1) 47 | batch-config := $(shell cat $(batch-list) | grep -v '\#' | cut -d - -f 1-) 48 | 49 | build: clean 50 | ${questa-ver} vlib $(library) 51 | bender script vsim -t rtl -t asic -t variable_latency_test --vlog-arg "\-timescale=1ps/1ps" > compile.tcl 52 | ${questa-ver} vsim -c -do "do compile.tcl; exit" 53 | 54 | # this starts modelsim with gui 55 | sim: build 56 | ${questa-ver} vsim -lib $(library) $(top-sim) -do "do wave.do" $(sim_opts) 57 | 58 | # batch mode without gui 59 | simc: build 60 | ${questa-ver} vsim -lib $(library) $(top-sim) -c -do "run -all; exit" $(sim_opts_batch) 61 | 62 | clean: 63 | rm -rf $(library) 64 | rm -rf transcript statistics.log vsim.wlf modelsim.ini 65 | 66 | batch-clean-sim: 67 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _transcript.log, $(batch-name))) 68 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _statistics.log, $(batch-name))) 69 | 70 | batch-clean-synth: 71 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _synth.log, $(batch-name))) 72 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _timing.rpt, $(batch-name))) 73 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _power.rpt, $(batch-name))) 74 | rm -rf $(addprefix $(results-dir)/, $(addsuffix _area.rpt, $(batch-name))) 75 | 76 | batch-clean: 77 | rm -rf $(batch-name) 78 | 79 | clean-all: clean batch-clean batch-clean-synth batch-clean-sim 80 | rm -rf $(results-dir) 81 | 82 | # runs the configurations defined in the batch-list file and gathers the statistics logs 83 | $(results-dir)/%_statistics.log: 84 | $(eval $@: name := $(subst _statistics.log,,$(subst $(results-dir)/,, $@))) 85 | mkdir -p $(name) 86 | ${questa-ver} vlib $(name)/$(library) 87 | ${questa-ver} vlog -work $(name)/$(library) -pedanticerrors $(src) $(tb-src) $(compile_flag) +incdir+$(incdir) $(addprefix +define+,$(subst $(name)-, , $(filter $(name)-%, $(batch-config)))) > $(name)/compile.log 88 | @echo $(name) started 89 | cd $(name) && ${questa-ver} vsim -lib $(library) $(top-sim) -c -do "run -all; exit" $(sim_opts_batch) > /dev/null 90 | @echo $(name) finished 91 | cp $(name)/transcript $(results-dir)/$(name)_transcript.log 92 | cp $(name)/statistics.log $(results-dir)/$(name)_statistics.log 93 | 94 | batch-sim: 95 | mkdir -p $(results-dir) 96 | $(MAKE) $(addprefix $(results-dir)/, $(addsuffix _statistics.log, $(batch-name))) 97 | 98 | # mini prep script for DC that sets the required variables and calls a generic synthesis script 99 | dc-cmd = "set SRC {$(src)}; \ 100 | set TOP_ENTITY $(top-synth); \ 101 | set NAME $(name); \ 102 | set INCDIR $(incdir); \ 103 | set OUTDIR $(eval-root)/$(name)/ ; \ 104 | set LIB $(eval-root)/$(name)/$(library)-synth ; \ 105 | set DEFINE {$(subst +, ,$(subst $(name)-, , $(filter $(name)-%, $(batch-config)))) } ; \ 106 | source $(eval-root)/$(synth-script) \ 107 | " 108 | 109 | # synthesizes the configurations defined in the batch-list file and gathers the statistics logs 110 | $(results-dir)/%_area.rpt: 111 | $(eval $@: name := $(subst _area.rpt,,$(subst $(results-dir)/,, $@))) 112 | mkdir -p $(name) 113 | @echo $(name) started 114 | cd $(synth-dir) && $(dc-ver) -x $(dc-cmd) > $(eval-root)/$(name)/synth.log 115 | @echo $(name) finished 116 | cp $(name)/synth.log $(results-dir)/$(name)_synth.log 117 | cp $(name)/timing.rpt $(results-dir)/$(name)_timing.rpt 118 | cp $(name)/power.rpt $(results-dir)/$(name)_power.rpt 119 | cp $(name)/area.rpt $(results-dir)/$(name)_area.rpt 120 | 121 | batch-synth: 122 | mkdir -p $(results-dir) 123 | $(MAKE) $(addprefix $(results-dir)/, $(addsuffix _area.rpt, $(batch-name))) 124 | 125 | batch-plot: 126 | $(matlab-ver) -nosplash -nodesktop -r "addpath(genpath('./matlab')); run evaluation.m" 127 | 128 | batch-eval: batch-synth batch-sim 129 | $(MAKE) batch-plot 130 | 131 | .PHONY: build sim simc clean batch-clean clean-all batch-sim batch-synth batch-plot batch-eval 132 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/hdl/defaults.svh: -------------------------------------------------------------------------------- 1 | ../../tb_tcdm_interconnect/hdl/defaults.svh -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/hdl/tb_patterns.sv: -------------------------------------------------------------------------------- 1 | ../../tb_tcdm_interconnect/hdl/tb_patterns.sv -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/hdl/tb_pkg.sv: -------------------------------------------------------------------------------- 1 | ../../tb_tcdm_interconnect/hdl/tb_pkg.sv -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/hdl/variable_latency_interconnect_wrap.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Michael Schaffner , ETH Zurich 12 | // Matheus Cavalcante , ETH Zurich 13 | // Date: 06.03.2019 14 | // Description: Synthesis wrapper for variable_latency_interconnect without parameters 15 | 16 | `include "defaults.svh" 17 | 18 | module variable_latency_interconnect_wrap ( 19 | input logic clk_i, 20 | input logic rst_ni, 21 | // Initiator side 22 | input logic [`NUM_MASTER-1:0] req_i, // Request signal 23 | input logic [`NUM_MASTER-1:0][`DATA_WIDTH-1:0] add_i, // Target Address 24 | input logic [`NUM_MASTER-1:0] wen_i, // Write enable 25 | input logic [`NUM_MASTER-1:0][`DATA_WIDTH-1:0] wdata_i, // Write data 26 | input logic [`NUM_MASTER-1:0][`DATA_WIDTH/8-1:0] be_i, // Byte enable 27 | output logic [`NUM_MASTER-1:0] gnt_o, // Grant signal 28 | output logic [`NUM_MASTER-1:0] vld_o, // Response valid 29 | input logic [`NUM_MASTER-1:0] rdy_i, // Response ready 30 | output logic [`NUM_MASTER-1:0][`DATA_WIDTH-1:0] rdata_o, // Data response (for load commands) 31 | // Target side 32 | output logic [`NUM_MASTER * `BANK_FACT-1:0] req_o, // Request signal 33 | output logic [`NUM_MASTER * `BANK_FACT-1:0][$clog2(`NUM_MASTER)-1:0] ini_add_o, // Initiator address 34 | input logic [`NUM_MASTER * `BANK_FACT-1:0] gnt_i, // Grant signal 35 | output logic [`NUM_MASTER * `BANK_FACT-1:0][`MEM_ADDR_BITS-1:0] add_o, // Target address 36 | output logic [`NUM_MASTER * `BANK_FACT-1:0] wen_o, // Write enable 37 | output logic [`NUM_MASTER * `BANK_FACT-1:0][`DATA_WIDTH-1:0] wdata_o, // Write data 38 | output logic [`NUM_MASTER * `BANK_FACT-1:0][`DATA_WIDTH/8-1:0] be_o, // Byte enable 39 | input logic [`NUM_MASTER * `BANK_FACT-1:0] vld_i, // Response valid 40 | output logic [`NUM_MASTER * `BANK_FACT-1:0] rdy_o, // Response ready 41 | input logic [`NUM_MASTER * `BANK_FACT-1:0][$clog2(`NUM_MASTER)-1:0] ini_add_i, // Initiator address (response) 42 | input logic [`NUM_MASTER * `BANK_FACT-1:0][`DATA_WIDTH-1:0] rdata_i // Data response (for load commands) 43 | ); 44 | 45 | if (`MUT_IMPL == 0) begin : gen_lic 46 | variable_latency_interconnect #( 47 | .NumIn (`NUM_MASTER ), 48 | .NumOut (`NUM_MASTER * `BANK_FACT ), 49 | .AddrWidth (`DATA_WIDTH ), 50 | .DataWidth (`DATA_WIDTH ), 51 | .AddrMemWidth (`MEM_ADDR_BITS ), 52 | .Topology (tcdm_interconnect_pkg::LIC) 53 | ) i_interco ( 54 | .clk_i (clk_i ), 55 | .rst_ni (rst_ni ), 56 | .req_i (req_i ), 57 | .add_i (add_i ), 58 | .wen_i (wen_i ), 59 | .wdata_i (wdata_i ), 60 | .be_i (be_i ) , 61 | .gnt_o (gnt_o ), 62 | .vld_o (vld_o ), 63 | .rdy_i (rdy_i ), 64 | .rdata_o (rdata_o ), 65 | .req_o (req_o ), 66 | .ini_add_o(ini_add_o), 67 | .gnt_i (gnt_i ), 68 | .add_o (add_o ), 69 | .wen_o (wen_o ) , 70 | .wdata_o (wdata_o ), 71 | .be_o (be_o ), 72 | .vld_i (vld_i ), 73 | .rdy_o (rdy_o ), 74 | .ini_add_i(ini_add_i), 75 | .rdata_i (rdata_i ) 76 | ); 77 | end else if (`MUT_IMPL == 1) begin : gen_bfly_r2 78 | variable_latency_interconnect #( 79 | .NumIn (`NUM_MASTER ), 80 | .NumOut (`NUM_MASTER * `BANK_FACT ), 81 | .AddrWidth (`DATA_WIDTH ), 82 | .DataWidth (`DATA_WIDTH ), 83 | .AddrMemWidth (`MEM_ADDR_BITS ), 84 | .Topology (tcdm_interconnect_pkg::BFLY2) 85 | ) i_interco ( 86 | .clk_i (clk_i ), 87 | .rst_ni (rst_ni ), 88 | .req_i (req_i ), 89 | .add_i (add_i ), 90 | .wen_i (wen_i ), 91 | .wdata_i (wdata_i ), 92 | .be_i (be_i ) , 93 | .gnt_o (gnt_o ), 94 | .vld_o (vld_o ), 95 | .rdy_i (rdy_i ), 96 | .rdata_o (rdata_o ), 97 | .req_o (req_o ), 98 | .ini_add_o(ini_add_o), 99 | .gnt_i (gnt_i ), 100 | .add_o (add_o ), 101 | .wen_o (wen_o ) , 102 | .wdata_o (wdata_o ), 103 | .be_o (be_o ), 104 | .vld_i (vld_i ), 105 | .rdy_o (rdy_o ), 106 | .ini_add_i(ini_add_i), 107 | .rdata_i (rdata_i ) 108 | ); 109 | end else if (`MUT_IMPL == 2) begin : gen_bfly_r4 110 | variable_latency_interconnect #( 111 | .NumIn (`NUM_MASTER ), 112 | .NumOut (`NUM_MASTER * `BANK_FACT ), 113 | .AddrWidth (`DATA_WIDTH ), 114 | .DataWidth (`DATA_WIDTH ), 115 | .AddrMemWidth (`MEM_ADDR_BITS ), 116 | .Topology (tcdm_interconnect_pkg::BFLY4) 117 | ) i_interco ( 118 | .clk_i (clk_i ), 119 | .rst_ni (rst_ni ), 120 | .req_i (req_i ), 121 | .add_i (add_i ), 122 | .wen_i (wen_i ), 123 | .wdata_i (wdata_i ), 124 | .be_i (be_i ) , 125 | .gnt_o (gnt_o ), 126 | .vld_o (vld_o ), 127 | .rdy_i (rdy_i ), 128 | .rdata_o (rdata_o ), 129 | .req_o (req_o ), 130 | .ini_add_o(ini_add_o), 131 | .gnt_i (gnt_i ), 132 | .add_o (add_o ), 133 | .wen_o (wen_o ) , 134 | .wdata_o (wdata_o ), 135 | .be_o (be_o ), 136 | .vld_i (vld_i ), 137 | .rdy_o (rdy_o ), 138 | .ini_add_i(ini_add_i), 139 | .rdata_i (rdata_i ) 140 | ); 141 | end else begin: gen_unknown 142 | $fatal(1, "[variable_latency_interconnect_wrap] Unknown TCDM network configuration."); 143 | end 144 | 145 | endmodule : variable_latency_interconnect_wrap 146 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/matlab/evaluation.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Result parsing and plotting master script for network evaluation. 14 | 15 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 16 | %% Setup and Result Parsing 17 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 18 | 19 | addpath(genpath('./matlab')); 20 | mkdir plots 21 | 22 | % get simulation results 23 | [stats] = read_stats('sim-results'); 24 | % check for outliers (== implementation or arbitration bugs!) 25 | fairness_test(stats, 0.13); 26 | % annotate this with synthesis results 27 | stats = read_synth('sim-results', stats); 28 | 29 | % backup results 30 | save('plots/stats.mat','stats'); 31 | 32 | % get simulation results 33 | [stats_tcdm] = read_stats('../tb_tcdm_interconnect/sim-results'); 34 | % check for outliers (== implementation or arbitration bugs!) 35 | fairness_test(stats_tcdm, 0.13); 36 | % annotate this with synthesis results 37 | stats_tcdm = read_synth('../tb_tcdm_interconnect/sim-results', stats_tcdm); 38 | 39 | % backup results 40 | save('plots/stats_tcdm.mat','stats_tcdm'); 41 | 42 | 43 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 44 | %% Statistical Evaluation 45 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 46 | 47 | %% selection x8 48 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic'}; 49 | plot_tests(stats, {'8x8','8x16','8x32'}, networkSel); 50 | export_fig 'plots/stats_selection_8x' -png -pdf 51 | %% selection x16 52 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic'}; 53 | plot_tests(stats, {'16x16','16x32','16x64'}, networkSel); 54 | export_fig 'plots/stats_selection_16x' -png -pdf 55 | %% selection x32 56 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic'}; 57 | plot_tests(stats, {'32x32','32x64','32x128'}, networkSel); 58 | export_fig 'plots/stats_selection_32x' -png -pdf 59 | %% selection x64 60 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic'}; 61 | plot_tests(stats, {'64x64','64x128','64x256'}, networkSel); 62 | export_fig 'plots/stats_selection_64x' -png -pdf 63 | %% selection x128 64 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic'}; 65 | plot_tests(stats, {'128x128','128x256','128x512'}, networkSel); 66 | export_fig 'plots/stats_selection_128x' -png -pdf 67 | %% selection x256 68 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic'}; 69 | %plot_tests(stats, {'256x256','256x512','256x1024'}, networkSel); 70 | %export_fig 'plots/stats_selection_256x' -png -pdf 71 | %% plot only banking factor 2 72 | plot_tests(stats, {'64x64','64x128','64x256'}, {'vl_bfly2', 'vl_bfly4', 'vl_lic'}); 73 | export_fig 'plots/stats_bf2_64x' -png -pdf 74 | 75 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 76 | %% Pareto Plots 77 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 78 | 79 | %% 8 masters 80 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic','bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 81 | scatterplot_tests([stats stats_tcdm], '8x', networkSel,'random uniform (p_{req}=1.00)'); 82 | export_fig 'plots/pareto_random_uniform_8x' -png -pdf 83 | %% 84 | scatterplot_tests([stats stats_tcdm], '8x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 85 | export_fig 'plots/pareto_random_linear_8x' -png -pdf 86 | %% 16 masters 87 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic','bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 88 | scatterplot_tests([stats stats_tcdm], '16x', networkSel,'random uniform (p_{req}=1.00)'); 89 | export_fig 'plots/pareto_random_uniform_16x' -png -pdf 90 | %% 91 | scatterplot_tests([stats stats_tcdm], '16x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 92 | export_fig 'plots/pareto_random_linear_16x' -png -pdf 93 | %% 32 masters 94 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic','bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 95 | scatterplot_tests([stats stats_tcdm], '32x', networkSel,'random uniform (p_{req}=1.00)'); 96 | export_fig 'plots/pareto_random_uniform_32x' -png -pdf 97 | %% 98 | scatterplot_tests([stats stats_tcdm], '32x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 99 | export_fig 'plots/pareto_random_linear_32x' -png -pdf 100 | %% 64 masters 101 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic','bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 102 | scatterplot_tests([stats stats_tcdm], '64x', networkSel,'random uniform (p_{req}=1.00)'); 103 | export_fig 'plots/pareto_random_uniform_64x' -png -pdf 104 | %% 105 | scatterplot_tests([stats stats_tcdm], '64x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 106 | export_fig 'plots/pareto_random_linear_64x' -png -pdf 107 | %% 128 masters 108 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic','bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 109 | scatterplot_tests([stats stats_tcdm], '128x', networkSel,'random uniform (p_{req}=1.00)'); 110 | export_fig 'plots/pareto_random_uniform_128x' -png -pdf 111 | %% 112 | scatterplot_tests([stats stats_tcdm], '128x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 113 | export_fig 'plots/pareto_random_linear_128x' -png -pdf 114 | %% 256 masters 115 | networkSel = {'vl_bfly2','vl_bfly4','vl_lic','bfly2_n1', 'bfly2_n2','bfly2_n4', 'bfly4_n1', 'bfly4_n2','bfly4_n4', 'lic'}; 116 | %scatterplot_tests([stats stats_tcdm], '256x', networkSel,'random uniform (p_{req}=1.00)'); 117 | %export_fig 'plots/pareto_random_uniform_256x' -png -pdf 118 | %% 119 | %scatterplot_tests([stats stats_tcdm], '256x', networkSel,'random linear bursts (p_{req}=1.00, len_{max}=100.00)'); 120 | %export_fig 'plots/pareto_random_linear_256x' -png -pdf 121 | 122 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 123 | %% Pareto Plots 124 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 125 | %% scaling behavior with BF=1 126 | networkSel = {'vl_bfly4','vl_lic'}; 127 | plot_scaling(stats, {'8x8','16x16','32x32','64x64','128x128','256x256'}, networkSel); 128 | export_fig 'plots/scaling_bf1' -png -pdf 129 | %% scaling behavior with BF=2 130 | plot_scaling(stats, {'8x16','16x32','32x64','64x128','128x256','256x512'}, networkSel); 131 | export_fig 'plots/scaling_bf2' -png -pdf 132 | %% scaling behavior with BF=4 133 | plot_scaling(stats, {'8x32','16x64','32x128','64x256','128x512','256x1024'}, networkSel); 134 | export_fig 'plots/scaling_bf4' -png -pdf 135 | %% for batch use 136 | exit(0); 137 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/matlab/export_fig: -------------------------------------------------------------------------------- 1 | ../../tb_tcdm_interconnect/matlab/export_fig -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/matlab/fairness_test.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Checks whether grant probability std deviation is within 14 | % tolerance. This can be used as a quick sanity check since arbitration or 15 | % implementation errors often result in a non-uniform grant probability 16 | % when comparing across master ports. 17 | % 18 | % Usage: [idx] = fairness_test(stats, tol) 19 | % 20 | % Inputs: - stats: statistics struct, created with read_stats. 21 | % - tol: tolerance for std deviation 22 | % 23 | % Outputs: - idx: indices of failing tests. 24 | % 25 | % See also: read_stats, read_synth, plot_tests, 26 | % plot_tests, plot_scaling, scatterplot_tests 27 | 28 | function [idx] = fairness_test(stats, tol) 29 | %fairness_test checks whether grant probability std deviation is within tolerance 30 | 31 | fprintf('\nFairness check with tol=%.2f\n\n', tol); 32 | failingTests = ''; 33 | idx = []; 34 | for k = 1:length(stats.ports) 35 | tst_mean = mean(stats.ports{k}(:,2)); 36 | tst_std = std(stats.ports{k}(:,2)); 37 | str = 'OK'; 38 | str2 = ''; 39 | if tst_std ./ tst_mean > tol 40 | str = 'FAILED'; 41 | str2 = [stats.network{k} ' ' stats.configs{k} ' ' stats.testNameFull{k}]; 42 | failingTests = [failingTests str2 '\n']; 43 | end 44 | fprintf('> mean=%04.2f std=%04.2f -> %s %s\n', tst_mean, tst_std, str, str2); 45 | idx = [idx k]; 46 | end 47 | 48 | if ~isempty(failingTests) 49 | fprintf(['\n\nSome tests have failed:\n', failingTests]); 50 | else 51 | fprintf('\n\nAll tests passed with tol=%.2f!\n', tol); 52 | end 53 | end 54 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/matlab/plot_scaling.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: Plot scaling behavior of different networks, i.e. area in 14 | % dependency of the Master x Slave configuration. 15 | % 16 | % Usage: [] = plot_scaling(stats, configLabels, netLabels) 17 | % 18 | % Inputs: - stats: statistics struct, created with read_stats. 19 | % - configLabels: cell array with network port configs, e.g. {'64x128', '64x256'} 20 | % - netLabels: cell array with network labels, e.g. {'lic', 'bfly4_n1'} 21 | % 22 | % See also: read_stats, fairness_test, read_synth, plot_tests, 23 | % plot_tests, scatterplot_tests 24 | 25 | 26 | function [] = plot_scaling(stats, configLabels, netLabels) 27 | % plot_scaling Plot scaling behavior of different networks, i.e. area in 28 | % dependency of the Master x Slave configuration. 29 | 30 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 31 | %% global plot configs 32 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 33 | 34 | close; 35 | figure; 36 | 37 | cols = colormap('lines'); 38 | markers = ['o','d','s','<','>','v','h','^','+','-','x','.']; 39 | 40 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 41 | %% preprocess args 42 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 43 | 44 | fprintf('\n'); 45 | 46 | if ~isempty(netLabels) 47 | tmp = {}; 48 | for k = 1:length(netLabels) 49 | if any(strcmp(netLabels{k},stats.netTypes)) 50 | tmp = [tmp netLabels(k)]; 51 | else 52 | warning('netType %s not found in batch results, skipping config...', netLabels{k}); 53 | end 54 | end 55 | netLabels = tmp; 56 | else 57 | netLabels = stats.netTypes; 58 | end 59 | 60 | if isempty(configLabels) 61 | configLabels=stats.configLabels; 62 | end 63 | 64 | masterConfigs = []; 65 | bankFacts = []; 66 | for k=1:length(configLabels) 67 | tmp = sscanf(configLabels{k},'%dx%d'); 68 | masterConfigs(k)=tmp(1); 69 | bankFacts(k)=tmp(2)/tmp(1); 70 | % for j=1:length(configLabels{k}) 71 | % if configLabels{k}(j) == 'x' 72 | % masterConfigs{k} = configLabels{k}(1:j-1); 73 | % end 74 | % end 75 | end 76 | 77 | masterConfigs = unique(masterConfigs); 78 | bankFacts = unique(bankFacts); 79 | 80 | 81 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 82 | %% gather results 83 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 84 | 85 | res=nan(length(netLabels),length(bankFacts),length(masterConfigs)); 86 | for n=1:length(netLabels) 87 | for c=1:length(configLabels) 88 | tst2=strcmp(configLabels{c}, stats.configLabels); 89 | tst3=strcmp(netLabels{n}, stats.netTypes); 90 | 91 | idx2 = find(tst2,1); 92 | idx3 = find(tst3,1); 93 | 94 | tmp = sscanf(configLabels{c},'%dx%d'); 95 | 96 | tst = masterConfigs == tmp(1); 97 | idx = find(tst,1); 98 | tst4 = bankFacts == tmp(2)/tmp(1); 99 | idx4 = find(tst4,1); 100 | 101 | res(n,idx4,idx) = stats.synthArea(idx3,idx2,1); 102 | end 103 | end 104 | 105 | labels = {}; 106 | 107 | for n=1:length(netLabels) 108 | for c=1:length(bankFacts) 109 | labels = [labels {[netLabels{n} '_bf' num2str(bankFacts(c))]}]; 110 | end 111 | end 112 | 113 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 114 | %% plot #ports versus area 115 | %%%%%%%%%%%%%%%%%%%%%%%%%%% 116 | 117 | hold on; 118 | for k=1:size(res,1) 119 | for j=1:size(res,2) 120 | plot(masterConfigs,squeeze(res(k,j,:)),'--','marker',markers(j),'color',cols(k,:),'markerEdgeColor','k','markerFaceColor',cols(k,:)); 121 | end 122 | end 123 | box on; 124 | grid on; 125 | 126 | legend(labels,'interpreter','none'); 127 | xticks(masterConfigs) 128 | set(gca,'yscale','log'); 129 | set(gca,'xscale','log'); 130 | 131 | title('scaling behavior'); 132 | xlabel('master ports'); 133 | ylabel('complexity [\mum^2]'); 134 | 135 | end 136 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/matlab/read_synth.m: -------------------------------------------------------------------------------- 1 | % Copyright 2019 ETH Zurich and University of Bologna. 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the "License"); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | % 11 | % Author: Michael Schaffner , ETH Zurich 12 | % Date: 07.03.2019 13 | % Description: This function reads synthesis results and annotates the stats struct 14 | % configurations with no synthesis result will be set to NaN. 15 | % 16 | % Usage: [stats] = read_synth(directory, stats) 17 | % 18 | % Inputs: - directory: directory to simulation output folder. 19 | % - stats: statistics struct, created with read_stats. 20 | % 21 | % Outputs: - stats: annotated statistics struct. 22 | % 23 | % See also: fairness_test, read_stats, plot_tests, 24 | % plot_tests, plot_scaling, scatterplot_tests 25 | 26 | function [stats] = read_synth(directory, stats) 27 | % read_synth this function reads synthesis results and annotates the stats struct 28 | % configurations with no synthesis result will be set to NaN. 29 | 30 | fprintf('\nreading synthesis results...\n'); 31 | 32 | stats.synthArea = nan(length(stats.netTypes), length(stats.configLabels), 3); 33 | stats.synthSlack = nan(length(stats.netTypes), length(stats.configLabels)); 34 | numFiles = 0; 35 | numSkipped = 0; 36 | for k = 1:length(stats.netTypes) 37 | for j = 1:length(stats.configLabels) 38 | fileName = [directory filesep stats.netTypes{k} '_' stats.configLabels{j} '_area.rpt']; 39 | 40 | if exist(fileName, 'file') 41 | [~,out] = system(['grep "Total cell area:" ' fileName ' | awk -e ''{print $4;}'' ']); 42 | stats.synthArea(k,j,1) = sscanf(out,'%f',1); 43 | [~,out] = system(['grep "Combinational area:" ' fileName ' | awk -e ''{print $3;}'' ']); 44 | stats.synthArea(k,j,2) = sscanf(out,'%f',1); 45 | [~,out] = system(['grep "Noncombinational area:" ' fileName ' | awk -e ''{print $3;}'' ']); 46 | stats.synthArea(k,j,3) = sscanf(out,'%f',1); 47 | numFiles = numFiles + 1; 48 | else 49 | warning('No Synthesis results found for %s', [stats.netTypes{k} '_' stats.configLabels{j}]); 50 | numSkipped = numSkipped + 1; 51 | end 52 | 53 | fileName = [directory filesep stats.netTypes{k} '_' stats.configLabels{j} '_timing.rpt']; 54 | 55 | if exist(fileName, 'file') 56 | [~,out] = system(['grep "slack" ' fileName ' | awk -e ''{print $3;}'' ']); 57 | stats.synthSlack(k,j) = sscanf(out,'%f',1); 58 | else 59 | warning('No Timing results found for %s', [stats.netTypes{k} '_' stats.configLabels{j}]); 60 | end 61 | end 62 | end 63 | 64 | fprintf('read %d synthesis results (%d skipped)\n\n', numFiles, numSkipped); 65 | 66 | end 67 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/scripts/batch.list: -------------------------------------------------------------------------------- 1 | ####################### 8 masters ####################### 2 | lic_8x8-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=8 3 | lic_8x16-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=8 4 | lic_8x32-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=8 5 | # 6 | bfly2_8x8-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=1+NUM_MASTER=8 7 | bfly2_8x16-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=2+NUM_MASTER=8 8 | bfly2_8x32-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=4+NUM_MASTER=8 9 | # 10 | bfly4_8x8-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=1+NUM_MASTER=8 11 | bfly4_8x16-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=2+NUM_MASTER=8 12 | bfly4_8x32-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=4+NUM_MASTER=8 13 | ######################## 16 masters ####################### 14 | lic_16x16-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=16 15 | lic_16x32-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=16 16 | lic_16x64-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=16 17 | # 18 | bfly2_16x16-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=1+NUM_MASTER=16 19 | bfly2_16x32-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=2+NUM_MASTER=16 20 | bfly2_16x64-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=4+NUM_MASTER=16 21 | # 22 | bfly4_16x16-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=1+NUM_MASTER=16 23 | bfly4_16x32-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=2+NUM_MASTER=16 24 | bfly4_16x64-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=4+NUM_MASTER=16 25 | ####################### 32 masters ####################### 26 | lic_32x32-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=32 27 | lic_32x64-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=32 28 | lic_32x128-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=32 29 | # 30 | bfly2_32x32-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=1+NUM_MASTER=32 31 | bfly2_32x64-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=2+NUM_MASTER=32 32 | bfly2_32x128-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=4+NUM_MASTER=32 33 | # 34 | bfly4_32x32-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=1+NUM_MASTER=32 35 | bfly4_32x64-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=2+NUM_MASTER=32 36 | bfly4_32x128-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=4+NUM_MASTER=32 37 | ####################### 64 masters ####################### 38 | lic_64x64-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=64 39 | lic_64x128-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=64 40 | lic_64x256-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=64 41 | # 42 | bfly2_64x64-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=1+NUM_MASTER=64 43 | bfly2_64x128-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=2+NUM_MASTER=64 44 | bfly2_64x256-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=4+NUM_MASTER=64 45 | # 46 | bfly4_64x64-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=1+NUM_MASTER=64 47 | bfly4_64x128-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=2+NUM_MASTER=64 48 | bfly4_64x256-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=4+NUM_MASTER=64 49 | ####################### 128 masters ####################### 50 | lic_128x128-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=128 51 | lic_128x256-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=128 52 | lic_128x512-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=128 53 | # 54 | bfly2_128x128-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=1+NUM_MASTER=128 55 | bfly2_128x256-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=2+NUM_MASTER=128 56 | bfly2_128x512-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=4+NUM_MASTER=128 57 | # 58 | bfly4_128x128-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=1+NUM_MASTER=128 59 | bfly4_128x256-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=2+NUM_MASTER=128 60 | bfly4_128x512-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=4+NUM_MASTER=128 61 | ####################### 256 masters ####################### 62 | lic_256x256-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=1+NUM_MASTER=256 63 | lic_256x512-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=2+NUM_MASTER=256 64 | lic_256x1024-BATCH_SIM=1+MUT_IMPL=0+BANK_FACT=4+NUM_MASTER=256 65 | # 66 | bfly2_256x256-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=1+NUM_MASTER=256 67 | bfly2_256x512-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=2+NUM_MASTER=256 68 | bfly2_256x1024-BATCH_SIM=1+MUT_IMPL=1+BANK_FACT=4+NUM_MASTER=256 69 | # 70 | bfly4_256x256-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=1+NUM_MASTER=256 71 | bfly4_256x512-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=2+NUM_MASTER=256 72 | bfly4_256x1024-BATCH_SIM=1+MUT_IMPL=2+BANK_FACT=4+NUM_MASTER=256 73 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/scripts/src.list: -------------------------------------------------------------------------------- 1 | ../../rtl/low_latency_interco/AddressDecoder_Req.sv 2 | ../../rtl/low_latency_interco/AddressDecoder_Resp.sv 3 | ../../rtl/low_latency_interco/ArbitrationTree.sv 4 | ../../rtl/low_latency_interco/FanInPrimitive_Req.sv 5 | ../../rtl/low_latency_interco/FanInPrimitive_Resp.sv 6 | ../../rtl/low_latency_interco/grant_mask.sv 7 | ../../rtl/low_latency_interco/parameters.v 8 | ../../rtl/low_latency_interco/priority_Flag_Req.sv 9 | ../../rtl/low_latency_interco/RequestBlock1CH.sv 10 | ../../rtl/low_latency_interco/RequestBlock2CH.sv 11 | ../../rtl/low_latency_interco/ResponseBlock.sv 12 | ../../rtl/low_latency_interco/ResponseTree.sv 13 | ../../rtl/low_latency_interco/TCDM_PIPE_REQ.sv 14 | ../../rtl/low_latency_interco/TCDM_PIPE_RESP.sv 15 | ../../rtl/low_latency_interco/TestAndSet.sv 16 | ../../rtl/low_latency_interco/XBAR_TCDM.sv 17 | ../../rtl/low_latency_interco/tcdm_xbar_wrap.sv 18 | ../../../common_cells/src/lzc.sv 19 | ../../../common_cells/src/lfsr.sv 20 | ../../../common_cells/src/fifo_v3.sv 21 | ../../../common_cells/src/rr_arb_tree.sv 22 | ../../rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv 23 | ../../rtl/tcdm_interconnect/addr_dec_resp_mux.sv 24 | ../../rtl/tcdm_interconnect/xbar.sv 25 | ../../rtl/tcdm_interconnect/bfly_net.sv 26 | ../../rtl/tcdm_interconnect/clos_net.sv 27 | ../../rtl/tcdm_interconnect/tcdm_interconnect.sv 28 | ../../rtl/variable_latency_interconnect/addr_decoder.sv 29 | ../../rtl/variable_latency_interconnect/simplex_xbar.sv 30 | ../../rtl/variable_latency_interconnect/full_duplex_xbar.sv 31 | ../../rtl/variable_latency_interconnect/variable_latency_bfly_net.sv 32 | ../../rtl/variable_latency_interconnect/variable_latency_interconnect.sv 33 | hdl/variable_latency_interconnect_wrap.sv 34 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/scripts/synth.list: -------------------------------------------------------------------------------- 1 | ../../rtl/low_latency_interco/AddressDecoder_Req.sv 2 | ../../rtl/low_latency_interco/AddressDecoder_Resp.sv 3 | ../../rtl/low_latency_interco/ArbitrationTree.sv 4 | ../../rtl/low_latency_interco/FanInPrimitive_Req.sv 5 | ../../rtl/low_latency_interco/FanInPrimitive_Resp.sv 6 | ../../rtl/low_latency_interco/grant_mask.sv 7 | ../../rtl/low_latency_interco/parameters.v 8 | ../../rtl/low_latency_interco/priority_Flag_Req.sv 9 | ../../rtl/low_latency_interco/RequestBlock1CH.sv 10 | ../../rtl/low_latency_interco/RequestBlock2CH.sv 11 | ../../rtl/low_latency_interco/ResponseBlock.sv 12 | ../../rtl/low_latency_interco/ResponseTree.sv 13 | ../../rtl/low_latency_interco/TCDM_PIPE_REQ.sv 14 | ../../rtl/low_latency_interco/TCDM_PIPE_RESP.sv 15 | ../../rtl/low_latency_interco/TestAndSet.sv 16 | ../../rtl/low_latency_interco/XBAR_TCDM.sv 17 | ../../rtl/low_latency_interco/tcdm_xbar_wrap.sv 18 | ../../../common_cells/src/lzc.sv 19 | ../../../common_cells/src/lfsr.sv 20 | ../../../common_cells/src/fifo_v3.sv 21 | ../../../common_cells/src/rr_arb_tree.sv 22 | ../../rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv 23 | ../../rtl/tcdm_interconnect/addr_dec_resp_mux.sv 24 | ../../rtl/tcdm_interconnect/xbar.sv 25 | ../../rtl/tcdm_interconnect/bfly_net.sv 26 | ../../rtl/tcdm_interconnect/clos_net.sv 27 | ../../rtl/tcdm_interconnect/tcdm_interconnect.sv 28 | ../../rtl/variable_latency_interconnect/addr_decoder.sv 29 | ../../rtl/variable_latency_interconnect/simplex_xbar.sv 30 | ../../rtl/variable_latency_interconnect/full_duplex_xbar.sv 31 | ../../rtl/variable_latency_interconnect/variable_latency_bfly_net.sv 32 | ../../rtl/variable_latency_interconnect/variable_latency_interconnect.sv 33 | hdl/variable_latency_interconnect_wrap.sv 34 | -------------------------------------------------------------------------------- /tb/tb_variable_latency_interconnect/scripts/tb-src.list: -------------------------------------------------------------------------------- 1 | hdl/tb_pkg.sv 2 | hdl/variable_latency_interconnect_tb.sv 3 | --------------------------------------------------------------------------------