├── .cockpitrc ├── .github ├── actions │ ├── oseda-caching │ │ └── action.yml │ └── oseda-cmd │ │ └── action.yml ├── config │ ├── croc_ci.json │ ├── croc_map_ci.json │ └── gh-pages-map.html ├── scripts │ └── check_sim.sh └── workflows │ ├── artistic.yml │ ├── full-flow.yml │ ├── license.yml │ └── short-flow.yml ├── .gitignore ├── .gitmodules ├── Bender.local ├── Bender.lock ├── Bender.yml ├── CHANGELOG.md ├── LICENSE.md ├── Makefile ├── README.md ├── croc.flist ├── doc ├── artwork │ ├── logo_chip.svg │ └── logo_template.svg ├── croc_arch.svg ├── croc_modules.jpg └── croc_routed.jpg ├── docker-compose.yml ├── ethz.env ├── ihp13 ├── bondpad │ ├── cdl │ │ └── bondpad_70x70.cdl │ ├── gds │ │ └── bondpad_70x70.gds │ ├── lef │ │ └── bondpad_70x70.lef │ └── verilog │ │ └── bondpad_70x70.v ├── tc_clk.sv └── tc_sram_impl.sv ├── klayout ├── .gitignore ├── def2gds.sh ├── def2stream.py └── sg13g2.map ├── openroad ├── .gitignore ├── openroad.mk ├── scripts │ ├── checkpoint.tcl │ ├── chip.tcl │ ├── floorplan.tcl │ ├── floorplan_util.tcl │ ├── init_tech.tcl │ ├── power_connect.tcl │ ├── power_grid.tcl │ ├── reports.tcl │ ├── reports_area.tcl │ └── startup.tcl └── src │ ├── constraints.sdc │ ├── instances.tcl │ └── padring.tcl ├── rtl ├── apb │ ├── Bender.yml │ ├── README.md │ ├── apb_pkg.sv │ └── include │ │ └── apb │ │ ├── assign.svh │ │ └── typedef.svh ├── apb_uart │ ├── Bender.yml │ ├── apb_uart.sv │ ├── apb_uart_wrap.sv │ ├── reg_uart_wrap.sv │ ├── slib_clock_div.sv │ ├── slib_counter.sv │ ├── slib_edge_detect.sv │ ├── slib_fifo.sv │ ├── slib_input_filter.sv │ ├── slib_input_sync.sv │ ├── slib_mv_filter.sv │ ├── uart_baudgen.sv │ ├── uart_interrupt.sv │ ├── uart_receiver.sv │ └── uart_transmitter.sv ├── common_cells │ ├── Bender.yml │ ├── README.md │ ├── addr_decode.sv │ ├── addr_decode_dync.sv │ ├── addr_decode_napot.sv │ ├── binary_to_gray.sv │ ├── cb_filter.sv │ ├── cb_filter_pkg.sv │ ├── cc_onehot.sv │ ├── cdc_2phase.sv │ ├── cdc_2phase_clearable.sv │ ├── cdc_4phase.sv │ ├── cdc_fifo_2phase.sv │ ├── cdc_fifo_gray.sv │ ├── cdc_fifo_gray_clearable.sv │ ├── cdc_reset_ctrlr.sv │ ├── cdc_reset_ctrlr_pkg.sv │ ├── cf_math_pkg.sv │ ├── clk_int_div.sv │ ├── clk_int_div_static.sv │ ├── clk_mux_glitch_free.sv │ ├── counter.sv │ ├── credit_counter.sv │ ├── delta_counter.sv │ ├── ecc_decode.sv │ ├── ecc_encode.sv │ ├── ecc_pkg.sv │ ├── edge_detect.sv │ ├── edge_propagator.sv │ ├── edge_propagator_ack.sv │ ├── edge_propagator_rx.sv │ ├── edge_propagator_tx.sv │ ├── exp_backoff.sv │ ├── fall_through_register.sv │ ├── fifo_v3.sv │ ├── gray_to_binary.sv │ ├── id_queue.sv │ ├── include │ │ └── common_cells │ │ │ ├── assertions.svh │ │ │ └── registers.svh │ ├── isochronous_4phase_handshake.sv │ ├── isochronous_spill_register.sv │ ├── lfsr.sv │ ├── lfsr_16bit.sv │ ├── lfsr_8bit.sv │ ├── lossy_valid_to_stream.sv │ ├── lzc.sv │ ├── max_counter.sv │ ├── mem_to_banks.sv │ ├── mem_to_banks_detailed.sv │ ├── multiaddr_decode.sv │ ├── mv_filter.sv │ ├── onehot_to_bin.sv │ ├── passthrough_stream_fifo.sv │ ├── plru_tree.sv │ ├── popcount.sv │ ├── read.sv │ ├── rr_arb_tree.sv │ ├── rstgen.sv │ ├── rstgen_bypass.sv │ ├── serial_deglitch.sv │ ├── shift_reg.sv │ ├── shift_reg_gated.sv │ ├── spill_register.sv │ ├── spill_register_flushable.sv │ ├── stream_arbiter.sv │ ├── stream_arbiter_flushable.sv │ ├── stream_delay.sv │ ├── stream_demux.sv │ ├── stream_fifo.sv │ ├── stream_fifo_optimal_wrap.sv │ ├── stream_filter.sv │ ├── stream_fork.sv │ ├── stream_fork_dynamic.sv │ ├── stream_intf.sv │ ├── stream_join.sv │ ├── stream_join_dynamic.sv │ ├── stream_mux.sv │ ├── stream_omega_net.sv │ ├── stream_register.sv │ ├── stream_throttle.sv │ ├── stream_to_mem.sv │ ├── stream_xbar.sv │ ├── sub_per_hash.sv │ ├── sync.sv │ ├── sync_wedge.sv │ └── unread.sv ├── common_verification │ ├── Bender.yml │ └── clk_rst_gen.sv ├── core_wrap.sv ├── croc_chip.sv ├── croc_domain.sv ├── croc_pkg.sv ├── croc_soc.sv ├── cve2 │ ├── Bender.yml │ ├── README.md │ ├── blockdiagram.svg │ ├── cve2_alu.sv │ ├── cve2_branch_predict.sv │ ├── cve2_compressed_decoder.sv │ ├── cve2_controller.sv │ ├── cve2_core.sv │ ├── cve2_core_tracing.sv │ ├── cve2_counter.sv │ ├── cve2_cs_registers.sv │ ├── cve2_csr.sv │ ├── cve2_decoder.sv │ ├── cve2_ex_block.sv │ ├── cve2_fetch_fifo.sv │ ├── cve2_id_stage.sv │ ├── cve2_if_stage.sv │ ├── cve2_load_store_unit.sv │ ├── cve2_multdiv_fast.sv │ ├── cve2_multdiv_slow.sv │ ├── cve2_pkg.sv │ ├── cve2_pmp.sv │ ├── cve2_prefetch_buffer.sv │ ├── cve2_register_file_ff.sv │ ├── cve2_tracer.sv │ ├── cve2_tracer_pkg.sv │ ├── cve2_wb.sv │ └── include │ │ ├── cve2 │ │ └── cve2_pmp_reset_default.svh │ │ └── lowrisc_prim │ │ ├── prim_assert.svh │ │ ├── prim_assert_dummy_macros.svh │ │ ├── prim_assert_sec_cm.svh │ │ ├── prim_assert_standard_macros.svh │ │ └── prim_assert_yosys_macros.svh ├── gpio │ ├── Bender.yml │ ├── README.md │ ├── gpio.sv │ ├── gpio_reg_pkg.sv │ └── gpio_reg_top.sv ├── obi │ ├── Bender.yml │ ├── Readme.md │ ├── include │ │ └── obi │ │ │ ├── assign.svh │ │ │ └── typedef.svh │ ├── obi_atop_resolver.sv │ ├── obi_cut.sv │ ├── obi_demux.sv │ ├── obi_err_sbr.sv │ ├── obi_intf.sv │ ├── obi_mux.sv │ ├── obi_pkg.sv │ ├── obi_rready_converter.sv │ ├── obi_sram_shim.sv │ └── obi_xbar.sv ├── patches │ ├── apb │ │ └── 0001-adjust-Bender-source-paths.patch │ ├── apb_uart │ │ ├── 0001-adjust-Bender-source-paths.patch │ │ └── src │ │ │ ├── 0001-Add-missing-parameter-keyword.patch │ │ │ └── 0002-Assign-missing-vector-bits.patch │ ├── common_cells │ │ └── 0001-adjust-Bender-source-paths.patch │ ├── common_verification │ │ └── 0001-adjust-Bender-source-paths.patch │ ├── cve2 │ │ ├── 0001-adjust-blockdiagram-path.patch │ │ ├── lowrisc_prim │ │ │ ├── 0001-remove-unused-files.patch │ │ │ └── 0002-adjust-include-paths.patch │ │ └── rtl │ │ │ ├── 0001-change-prim_assert-path.patch │ │ │ ├── 0002-remove-files-and-move-includes.patch │ │ │ ├── 0003-remove-dv_fcov_signal-macros.patch │ │ │ ├── 0004-remove-dv_fcov_macros-include.patch │ │ │ ├── 0005-remove-dv_fcov_macros-include.patch │ │ │ ├── 0006-add-multdiv-unused-signal-tieoff.patch │ │ │ └── 0007-add-bender-package-manifest.patch │ ├── obi │ │ └── 0001-adjust-Bender-source-paths.patch │ ├── register_interface │ │ └── 0001-adjust-Bender-source-paths-and-rm-axi.patch │ ├── riscv-dbg │ │ ├── 0001-adjust-Bender-source-paths.patch │ │ └── src │ │ │ └── 0001-Replace-deprecated-fifo_v2.patch │ ├── tech_cells_generic │ │ └── 0001-adjust-Bender-source-paths.patch │ └── timer_unit │ │ ├── 0001-adjust-Bender-source-paths.patch │ │ └── rtl │ │ └── 0001-add-README-with-register-description.patch ├── register_interface │ ├── Bender.yml │ ├── README.md │ ├── include │ │ └── register_interface │ │ │ ├── assign.svh │ │ │ └── typedef.svh │ ├── lowrisc_opentitan │ │ ├── prim_subreg.sv │ │ ├── prim_subreg_arb.sv │ │ ├── prim_subreg_ext.sv │ │ └── prim_subreg_shadow.sv │ ├── periph_to_reg.sv │ ├── reg_intf.sv │ └── reg_to_apb.sv ├── riscv-dbg │ ├── Bender.yml │ ├── README.md │ ├── debug_rom │ │ ├── debug_rom.sv │ │ └── debug_rom_one_scratch.sv │ ├── dm_csrs.sv │ ├── dm_mem.sv │ ├── dm_obi_top.sv │ ├── dm_pkg.sv │ ├── dm_sba.sv │ ├── dm_top.sv │ ├── dmi_bscane_tap.sv │ ├── dmi_cdc.sv │ ├── dmi_intf.sv │ ├── dmi_jtag.sv │ ├── dmi_jtag_tap.sv │ ├── dmi_test.sv │ └── tb │ │ └── jtag_test_simple.sv ├── soc_ctrl │ ├── boot_addr.patch │ ├── reg_html.css │ ├── soc_ctrl.h │ ├── soc_ctrl.html │ ├── soc_ctrl_reg_pkg.sv │ ├── soc_ctrl_reg_top.sv │ └── soc_ctrl_regs.hjson ├── tb_croc_soc.sv ├── tech_cells_generic │ ├── Bender.yml │ ├── README.md │ ├── fpga │ │ ├── pad_functional_xilinx.sv │ │ ├── tc_clk_xilinx.sv │ │ └── tc_sram_xilinx.sv │ ├── tc_clk.sv │ ├── tc_sram.sv │ └── tc_sram_impl.sv ├── timer_unit │ ├── Bender.yml │ ├── README.md │ ├── apb_timer_unit.sv │ ├── timer_unit.pdf │ ├── timer_unit.sv │ ├── timer_unit_counter.sv │ └── timer_unit_counter_presc.sv ├── user_domain.sv ├── user_domain │ └── .gitkeep └── user_pkg.sv ├── start_linux.sh ├── start_vnc.bat ├── start_vnc.sh ├── sw ├── .gitignore ├── Makefile ├── config.h ├── crt0.S ├── helloworld.c ├── lib │ ├── inc │ │ ├── gpio.h │ │ ├── print.h │ │ ├── soc_ctrl.h │ │ ├── timer.h │ │ ├── uart.h │ │ └── util.h │ └── src │ │ ├── gpio.c │ │ ├── print.c │ │ ├── timer.c │ │ └── uart.c └── link.ld ├── verilator ├── .gitignore └── tech.f ├── vsim ├── .gitignore ├── compile_tech.tcl ├── wave_rtl.do └── wave_yosys.do ├── xilinx ├── .gitignore ├── hw │ ├── croc_xilinx.sv │ └── fan_ctrl.sv ├── implement.sh ├── scripts │ ├── common.tcl │ ├── impl_ip.tcl │ ├── impl_sys.tcl │ └── openocd.genesys2.tcl └── src │ └── genesys2.xdc └── yosys ├── .gitignore ├── scripts ├── abc-opt.script ├── filter_output.awk ├── init_tech.tcl ├── yosys_common.tcl └── yosys_synthesis.tcl ├── src ├── abc.constr └── lazy_man_synth_library.aig └── yosys.mk /.github/actions/oseda-caching/action.yml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2025 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # Author: Philippe Sauter 6 | 7 | name: 'OSEDA Caching' 8 | description: 'Cache OSEDA Docker Images' 9 | 10 | runs: 11 | using: 'composite' 12 | steps: 13 | - name: Get image name from docker-compose 14 | id: get-image 15 | shell: bash 16 | run: | 17 | echo "UID=$(id -u)" >> $GITHUB_ENV 18 | echo "GID=$(id -g)" >> $GITHUB_ENV 19 | IMAGE=$(docker compose config | awk '/image:/{print $2}' | head -n1) 20 | echo "IMAGE_NAME=$IMAGE" >> $GITHUB_ENV 21 | 22 | - name: Restore Docker image cache 23 | id: restore-cache 24 | uses: actions/cache@v4 25 | with: 26 | path: /tmp/oseda.tar.gz 27 | key: oseda-${{ env.IMAGE_NAME }} 28 | 29 | - name: Check disk usage 30 | shell: bash 31 | run: df -h 32 | 33 | - name: Load cached Docker image 34 | shell: bash 35 | if: steps.restore-cache.outputs.cache-hit == 'true' 36 | run: docker import /tmp/oseda.tar.gz 37 | 38 | - name: Prepare Docker image for caching 39 | shell: bash 40 | if: steps.restore-cache.outputs.cache-hit != 'true' 41 | run: | 42 | docker system prune -af 43 | docker compose pull 44 | df -h 45 | docker save $IMAGE_NAME | pigz -9 -f > /tmp/oseda.tar.gz 46 | df -h 47 | 48 | - name: Check disk usage 49 | shell: bash 50 | run: df -h 51 | -------------------------------------------------------------------------------- /.github/config/croc_ci.json: -------------------------------------------------------------------------------- 1 | { 2 | "general" : { 3 | "chip" : "croc" 4 | }, 5 | "gds" : { 6 | "file" : "/fosic/designs/croc/artistic/meerkat_work/croc_chip.gds.gz", 7 | "x_offset_um" : -80, 8 | "y_offset_um" : -80, 9 | "width_um" : 1920, 10 | "height_um" : 1920 11 | }, 12 | "image": { 13 | "px_width" : 1920, 14 | "px_height" : 1920, 15 | "overrender_factor" : 4, 16 | "num_segs_width" : 1, 17 | "num_segs_height" : 1 18 | }, 19 | "paper": { 20 | "width_cm" : 84.1, 21 | "height_cm" : "-" 22 | }, 23 | "colors" : { 24 | "CONT" : {"layer" : "6/0", "color" : "#0000CD", "alpha" : "0.8" }, 25 | "M1" : {"layer" : "8/0", "color" : "#0000CD", "alpha" : "0.8" }, 26 | "V1" : {"layer" : "19/0", "color" : "#7CCD7C", "alpha" : "0.7" }, 27 | "M2" : {"layer" : "10/0", "color" : "#7CCD7C", "alpha" : "0.7" }, 28 | "V2" : {"layer" : "29/0", "color" : "#5c0c02", "alpha" : "0.6" }, 29 | "M3" : {"layer" : "30/0", "color" : "#5c0c02", "alpha" : "0.6" }, 30 | "V3" : {"layer" : "49/0", "color" : "#CD3700", "alpha" : "0.5" }, 31 | "M4" : {"layer" : "50/0", "color" : "#CD3700", "alpha" : "0.5" }, 32 | "V4" : {"layer" : "66/0", "color" : "#00CD00", "alpha" : "0.5" }, 33 | "M5" : {"layer" : "67/0", "color" : "#00CD00", "alpha" : "0.5" }, 34 | "TV1" : {"layer" : "125/0", "color" : "#7FFFD4", "alpha" : "0.5" }, 35 | "T1" : {"layer" : "126/0", "color" : "#7FFFD4", "alpha" : "0.5" }, 36 | "TV2" : {"layer" : "133/0", "color" : "#1E90FF", "alpha" : "0.5" }, 37 | "T2" : {"layer" : "134/0", "color" : "#FFFFFF", "alpha" : "0.8" } 38 | }, 39 | "work" : { 40 | "dir" : "/fosic/designs/croc/artistic/renderics" 41 | }, 42 | "tech" : { 43 | "manifest_version" : 1, 44 | "max_px_tile" : 2500000000, 45 | "pdk" : "ihp13", 46 | "layer_order" : [ 47 | "CONT", 48 | "M1", 49 | "V1", 50 | "M2", 51 | "V2", 52 | "M3", 53 | "V3", 54 | "M4", 55 | "V4", 56 | "M5", 57 | "TV1", 58 | "T1", 59 | "TV2", 60 | "T2" 61 | ], 62 | "db_unit_nm" : 0.1, 63 | "dry_run" : false 64 | } 65 | } 66 | 67 | -------------------------------------------------------------------------------- /.github/scripts/check_sim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Copyright (c) 2025 ETH Zurich and University of Bologna. 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 4 | # SPDX-License-Identifier: Apache-2.0 5 | 6 | # Author: Philippe Sauter 7 | 8 | LOG_FILE=$1 9 | 10 | expected_lines=( 11 | "\[CORE\] Start fetching instructions" 12 | "\[JTAG\] Halting hart 0" 13 | "\[JTAG\] Resumed hart 0" 14 | "\[UART\] Hello World!" 15 | "\[UART\] Result: 0x8940, Cycles: 0xBD" 16 | "\[UART\] Tick" 17 | "\[UART\] Tock" 18 | ) 19 | 20 | for line in "${expected_lines[@]}"; do 21 | if ! grep -q "$line" "$LOG_FILE"; then 22 | echo "Error: Expected line not found in the log: '$line'" 23 | exit 1 24 | fi 25 | done 26 | 27 | tick=$(awk '/\[UART\] Tick/ {print $2+0}' "$LOG_FILE") 28 | tock=$(awk '/\[UART\] Tock/ {print $2+0}' "$LOG_FILE") 29 | 30 | echo "Tick time: ${tick}" 31 | echo "Tock time: ${tock}" 32 | 33 | time_diff=$(echo "scale=2; ($tock - $tick) / 1000000" | bc) 34 | time_diff_ms=$(printf "%.0f" $time_diff) 35 | 36 | # 1.5ms tolerance 37 | if ((time_diff_ms >= 9 && time_diff_ms <= 11)); then 38 | echo "Timer correct: The gap between Tick and Tock is approximately 10ms: ${time_diff}ms." 39 | else 40 | echo "Timer Error: The gap between Tick and Tock is not approximately 10ms: ${time_diff}ms." 41 | exit 1 42 | fi 43 | 44 | echo "Hello world simulation passed." 45 | exit 0 46 | -------------------------------------------------------------------------------- /.github/workflows/full-flow.yml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2025 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # Author: Philippe Sauter 6 | # Author: Thomas Benz 7 | 8 | name: Full Flow 9 | 10 | on: 11 | workflow_dispatch: 12 | pull_request: 13 | push: 14 | branches: 15 | - main 16 | release: 17 | types: 18 | - created 19 | 20 | jobs: 21 | backend: 22 | runs-on: ubuntu-latest 23 | timeout-minutes: 180 24 | steps: 25 | - name: Checkout repository (with submodules) 26 | uses: actions/checkout@v4 27 | with: 28 | submodules: true 29 | 30 | - name: Run Yosys, OpenROAD and KLayout 31 | uses: ./.github/actions/oseda-cmd 32 | with: 33 | cmd: "make yosys && make openroad && make klayout" 34 | - name: Upload openroad output 35 | uses: actions/upload-artifact@v4 36 | with: 37 | name: croc-openroad-out 38 | path: openroad/out 39 | continue-on-error: true 40 | - name: Upload openroad reports 41 | uses: actions/upload-artifact@v4 42 | with: 43 | name: croc-openroad-reports 44 | path: openroad/reports 45 | continue-on-error: true 46 | - name: Upload gds 47 | uses: actions/upload-artifact@v4 48 | with: 49 | name: croc-gds 50 | path: klayout/croc_chip.gds 51 | continue-on-error: true 52 | -------------------------------------------------------------------------------- /.github/workflows/license.yml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2022 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # Author: Jannis Schönleber 6 | 7 | name: lint-license 8 | 9 | on: 10 | workflow_dispatch: 11 | 12 | jobs: 13 | lint-license: 14 | runs-on: ubuntu-latest 15 | steps: 16 | - name: lint license 17 | uses: pulp-platform/pulp-actions/lint-license@v2 18 | with: 19 | license: | 20 | Copyright \(c\) (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors). 21 | (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details. 22 | SPDX-License-Identifier: (SHL-0.51|Apache-2.0) 23 | exclude_paths: | 24 | deps 25 | include/version.h -------------------------------------------------------------------------------- /.github/workflows/short-flow.yml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2025 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # Author: Philippe Sauter 6 | 7 | name: Short Flow 8 | 9 | on: 10 | push: 11 | branches: 12 | - '**' 13 | 14 | jobs: 15 | simulation: 16 | runs-on: ubuntu-latest 17 | timeout-minutes: 30 18 | steps: 19 | - name: Checkout repository (with submodules) 20 | uses: actions/checkout@v4 21 | with: 22 | submodules: true 23 | 24 | - name: Run simulation commands in OSEDA 25 | uses: ./.github/actions/oseda-cmd 26 | with: 27 | cmd: "make sw && make verilator" 28 | - name: Upload built software 29 | uses: actions/upload-artifact@v4 30 | with: 31 | name: croc-sw 32 | path: sw/bin 33 | continue-on-error: true 34 | - name: Upload waveform 35 | uses: actions/upload-artifact@v4 36 | with: 37 | name: croc-waveform 38 | path: croc.vcd 39 | continue-on-error: true 40 | 41 | - name: Upload simulation output 42 | uses: actions/upload-artifact@v4 43 | with: 44 | name: simulation-output 45 | path: ${{ env.result_log }} 46 | - name: Check simulation output 47 | shell: bash 48 | run: ./.github/scripts/check_sim.sh ${{ env.result_log }} 49 | 50 | synthesis: 51 | runs-on: ubuntu-latest 52 | timeout-minutes: 30 53 | steps: 54 | - name: Checkout repository (with submodules) 55 | uses: actions/checkout@v4 56 | with: 57 | submodules: true 58 | 59 | - name: Setup OSEDA container 60 | uses: ./.github/actions/oseda-cmd 61 | with: 62 | cmd: "make yosys && tail -n 40 yosys/reports/*area.rpt" 63 | - name: Upload synthesis reports 64 | uses: actions/upload-artifact@v4 65 | with: 66 | name: croc-synth-reports 67 | path: yosys/reports 68 | continue-on-error: true 69 | - name: Upload netlist 70 | uses: actions/upload-artifact@v4 71 | with: 72 | name: croc-netlist 73 | path: yosys/out 74 | continue-on-error: true 75 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .bender 2 | tmp -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "ihp13/pdk"] 2 | path = ihp13/pdk 3 | url = https://github.com/IHP-GmbH/IHP-Open-PDK 4 | -------------------------------------------------------------------------------- /Bender.local: -------------------------------------------------------------------------------- 1 | overrides: 2 | common_verification: { path: "rtl/common_verification" } 3 | tech_cells_generic: { path: "rtl/tech_cells_generic" } 4 | common_cells: { path: "rtl/common_cells" } 5 | apb: { path: "rtl/apb" } 6 | register_interface: { path: "rtl/register_interface" } 7 | apb_uart: { path: "rtl/apb_uart" } 8 | ibex: { path: "rtl/ibex" } 9 | obi: { path: "rtl/obi" } 10 | riscv-dbg: { path: "rtl/riscv-dbg" } 11 | timer_unit: { path: "rtl/timer_unit" } 12 | -------------------------------------------------------------------------------- /Bender.lock: -------------------------------------------------------------------------------- 1 | packages: 2 | apb: 3 | revision: null 4 | version: null 5 | source: 6 | Path: rtl/apb 7 | dependencies: 8 | - common_cells 9 | apb_uart: 10 | revision: null 11 | version: null 12 | source: 13 | Path: rtl/apb_uart 14 | dependencies: 15 | - apb 16 | - register_interface 17 | common_cells: 18 | revision: null 19 | version: null 20 | source: 21 | Path: rtl/common_cells 22 | dependencies: 23 | - common_verification 24 | - tech_cells_generic 25 | common_verification: 26 | revision: null 27 | version: null 28 | source: 29 | Path: rtl/common_verification 30 | dependencies: [] 31 | cve2: 32 | revision: null 33 | version: null 34 | source: 35 | Path: rtl/cve2 36 | dependencies: [] 37 | obi: 38 | revision: null 39 | version: null 40 | source: 41 | Path: rtl/obi 42 | dependencies: 43 | - common_cells 44 | - common_verification 45 | register_interface: 46 | revision: null 47 | version: null 48 | source: 49 | Path: rtl/register_interface 50 | dependencies: 51 | - apb 52 | - common_cells 53 | - common_verification 54 | riscv-dbg: 55 | revision: null 56 | version: null 57 | source: 58 | Path: rtl/riscv-dbg 59 | dependencies: 60 | - common_cells 61 | - tech_cells_generic 62 | tech_cells_generic: 63 | revision: null 64 | version: null 65 | source: 66 | Path: rtl/tech_cells_generic 67 | dependencies: 68 | - common_verification 69 | timer_unit: 70 | revision: null 71 | version: null 72 | source: 73 | Path: rtl/timer_unit 74 | dependencies: [] 75 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | 3 | All notable changes to this project will be documented in this file. 4 | It is updated on each new release based on contributions since the last release. 5 | 6 | The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/), 7 | and this project loosely follows to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). 8 | 9 | 10 | ## 1.1.0 - 2025-05-07 11 | 12 | ### Added 13 | 14 | - sw: add various peripheral functions 15 | - sw: add expanded helloworld as peripheral test 16 | - pdk: add ETHZ cockpit integration 17 | - openroad: add startup script for ease-of-use 18 | - openroad: add parasitic extraction 19 | - ci: add short synthesis and simulation flows 20 | - ci: add long end-to-end flow 21 | - ci: add artistic rendering flow 22 | - openroad: add hierarchical area report 23 | 24 | ### Changed 25 | 26 | - hw: make SRAM pin `A_DLY` configurable (used to be tied to low when datasheet recommends tie to high) 27 | **IMPORTANT: This bug may create SRAM-internal timing violations; update strongly recommended** 28 | - hw: update OBI dependency 29 | - avoid explicit use of `r_optional` assignments 30 | - fix index width calculations for mux/demux etc 31 | - hw: update common_cells dependency 32 | - yosys: move configurations from makefrags to `yosys_synthesis.tcl` 33 | - yosys: add a default croc.flist 34 | 35 | ### Fixed 36 | 37 | - hw: fix OBI connections to timer peripheral 38 | - hw: various fixes to reduce warnings (Yosys, yosys-slang, Verilator) 39 | - openroad: fix LVS netlist 40 | - sw: fix linker script 41 | -test: fix uninitialized memory 42 | - verilator: speedup compile and synthesis 43 | - bender: fix cve2 vendor dependency 44 | 45 | ## 1.0.0 - 2024-12-05 46 | 47 | ### Added 48 | 49 | - Initial versioned release of the project 50 | -------------------------------------------------------------------------------- /doc/artwork/logo_chip.svg: -------------------------------------------------------------------------------- 1 | logo_template.svg -------------------------------------------------------------------------------- /doc/croc_modules.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/croc/b44242be749da0b533b7688c65376e15cc795d07/doc/croc_modules.jpg -------------------------------------------------------------------------------- /doc/croc_routed.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/croc/b44242be749da0b533b7688c65376e15cc795d07/doc/croc_routed.jpg -------------------------------------------------------------------------------- /docker-compose.yml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | services: 9 | pulp-docker: 10 | image: hpretl/iic-osic-tools:2025.03 11 | environment: 12 | - UID=${UID} 13 | - GID=${GID} 14 | user: "${UID}:${GID}" 15 | volumes: 16 | - ./:/fosic/designs/croc 17 | stdin_open: true 18 | tty: true 19 | working_dir: /fosic/designs/croc 20 | entrypoint: /dockerstartup/scripts/ui_startup.sh 21 | command: --skip bash 22 | -------------------------------------------------------------------------------- /ethz.env: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 4 | # SPDX-License-Identifier: Apache-2.0 5 | # 6 | # Authors: 7 | # - Philippe Sauter 8 | 9 | # used in Makefiles 10 | export BENDER="oseda bender" 11 | export OPENROAD="oseda openroad" 12 | export KLAYOUT="oseda klayout" 13 | export YOSYS="oseda yosys" 14 | export PYTHON3="oseda python3" 15 | export VERILATOR="oseda verilator" 16 | -------------------------------------------------------------------------------- /ihp13/bondpad/cdl/bondpad_70x70.cdl: -------------------------------------------------------------------------------- 1 | .SUBCKT bondpad_70x70 pad 2 | *.PININFO pad:B 3 | .ENDS 4 | -------------------------------------------------------------------------------- /ihp13/bondpad/gds/bondpad_70x70.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/croc/b44242be749da0b533b7688c65376e15cc795d07/ihp13/bondpad/gds/bondpad_70x70.gds -------------------------------------------------------------------------------- /ihp13/bondpad/lef/bondpad_70x70.lef: -------------------------------------------------------------------------------- 1 | VERSION 5.8 ; 2 | 3 | MACRO bondpad_70x70 4 | CLASS COVER ; 5 | ORIGIN 0 0 ; 6 | FOREIGN bondpad_70x70 0 0 ; 7 | SIZE 70.0 BY 70.0 ; 8 | SYMMETRY X Y R90 ; 9 | SITE sg13g2_ioSite ; 10 | PIN pad 11 | USE SIGNAL ; 12 | PORT 13 | LAYER Metal2 ; 14 | RECT 0 0 70.0 70.0 ; 15 | LAYER Metal3 ; 16 | RECT 0 0 70.0 70.0 ; 17 | LAYER Metal4 ; 18 | RECT 0 0 70.0 70.0 ; 19 | LAYER Metal5 ; 20 | RECT 0 0 70.0 70.0 ; 21 | LAYER TopMetal1 ; 22 | RECT 0 0 70.0 70.0 ; 23 | LAYER TopMetal2 ; 24 | RECT 0 0 70.0 70.0 ; 25 | END 26 | END pad 27 | 28 | OBS 29 | LAYER Metal1 ; 30 | RECT 0 0 70.0 70.0 ; 31 | LAYER Metal2 ; 32 | RECT 0 0 70.0 70.0 ; 33 | LAYER Metal3 ; 34 | RECT 0 0 70.0 70.0 ; 35 | LAYER Metal4 ; 36 | RECT 0 0 70.0 70.0 ; 37 | LAYER Metal5 ; 38 | RECT 0 0 70.0 70.0 ; 39 | LAYER TopMetal1 ; 40 | RECT 0 0 70.0 70.0 ; 41 | LAYER TopMetal2 ; 42 | RECT 0 0 70.0 70.0 ; 43 | END 44 | END bondpad_70x70 45 | -------------------------------------------------------------------------------- /ihp13/bondpad/verilog/bondpad_70x70.v: -------------------------------------------------------------------------------- 1 | module bondpad_70x70 (pad); 2 | inout pad; 3 | endmodule -------------------------------------------------------------------------------- /ihp13/tc_clk.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2023 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | // Authors: 5 | // 6 | // -Thomas Benz 7 | // -Tobias Senti 8 | 9 | module tc_clk_inverter ( 10 | input logic clk_i, 11 | output logic clk_o 12 | ); 13 | (* keep *)(* dont_touch = "true" *) 14 | sg13g2_inv_1 i_inv ( 15 | .A ( clk_i ), 16 | .Y ( clk_o ) 17 | ); 18 | 19 | endmodule 20 | 21 | module tc_clk_buffer ( 22 | input logic clk_i, 23 | output logic clk_o 24 | ); 25 | (* keep *)(* dont_touch = "true" *) 26 | sg13g2_buf_1 i_buf ( 27 | .A ( clk_i ), 28 | .X ( clk_o ) 29 | ); 30 | 31 | endmodule 32 | 33 | module tc_clk_mux2 ( 34 | input logic clk0_i, 35 | input logic clk1_i, 36 | input logic clk_sel_i, 37 | output logic clk_o 38 | ); 39 | (* keep *)(* dont_touch = "true" *) 40 | sg13g2_mux2_1 i_mux ( 41 | .A0 ( clk0_i ), 42 | .A1 ( clk1_i ), 43 | .S ( clk_sel_i ), 44 | .X ( clk_o ) 45 | ); 46 | endmodule 47 | 48 | module tc_clk_xor2 ( 49 | input logic clk0_i, 50 | input logic clk1_i, 51 | output logic clk_o 52 | ); 53 | 54 | (* keep *)(* dont_touch = "true" *) 55 | sg13g2_xor2_1 i_mux ( 56 | .A ( clk0_i ), 57 | .B ( clk1_i ), 58 | .X ( clk_o ) 59 | ); 60 | endmodule 61 | 62 | module tc_clk_gating #( 63 | parameter bit IS_FUNCTIONAL = 1'b1 64 | )( 65 | input logic clk_i, 66 | input logic en_i, 67 | input logic test_en_i, 68 | output logic clk_o 69 | ); 70 | 71 | if (IS_FUNCTIONAL || `ifdef USE_CLKGATE 1 `else 0 `endif) begin 72 | (* keep *)(* dont_touch = "true" *) 73 | sg13g2_slgcp_1 i_clkgate ( 74 | .GATE ( en_i ), 75 | .SCE ( test_en_i ), 76 | .CLK ( clk_i ), 77 | .GCLK ( clk_o ) 78 | ); 79 | end else begin 80 | assign clk_o = clk_i; 81 | end 82 | 83 | endmodule -------------------------------------------------------------------------------- /klayout/.gitignore: -------------------------------------------------------------------------------- 1 | .klayout 2 | *.gds -------------------------------------------------------------------------------- /openroad/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | save 3 | reports 4 | out 5 | IHP_rcx_patterns.rules 6 | -------------------------------------------------------------------------------- /openroad/openroad.mk: -------------------------------------------------------------------------------- 1 | # Copyright 2023 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | # Tools 9 | OPENROAD ?= openroad 10 | 11 | # Directories 12 | # directory of the path to the last called Makefile (this one) 13 | OR_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST))))) 14 | 15 | # Project variables 16 | # if you are running the entire flow these are set by the top level Makefile 17 | # in that case do not change them here 18 | TOP_DESIGN ?= croc_chip 19 | PROJ_NAME ?= croc 20 | NETLIST ?= $(realpath $(OR_DIR)/../yosys/out/$(PROJ_NAME)_yosys.v) 21 | 22 | SAVE ?= $(OR_DIR)/save 23 | REPORTS ?= $(OR_DIR)/reports 24 | OR_OUT ?= $(OR_DIR)/out 25 | OR_OUT_FILES = $(OR_OUT)/$(PROJ_NAME).def $(OR_OUT)/$(PROJ_NAME).v $(OR_OUT)/$(PROJ_NAME).sdc $(OR_OUT)/$(PROJ_NAME).odb 26 | 27 | backend: $(OR_OUT)/$(PROJ_NAME).def 28 | 29 | openroad: $(OR_OUT)/$(PROJ_NAME).def 30 | 31 | ## Place & Route flow using OpenROAD 32 | $(OR_OUT_FILES): $(NETLIST) $(OR_DIR)/scripts/*.tcl $(OR_DIR)/src/*.tcl $(OR_DIR)/src/*.sdc $(OR_DIR)/IHP_rcx_patterns.rules 33 | mkdir -p $(SAVE) 34 | mkdir -p $(REPORTS) 35 | mkdir -p $(OR_OUT) 36 | echo $(CROC_ROOT) 37 | cd $(OR_DIR) && \ 38 | NETLIST="$(NETLIST)" \ 39 | TOP_DESIGN="$(TOP_DESIGN)" \ 40 | PROJ_NAME="$(PROJ_NAME)" \ 41 | SAVE="$(SAVE)" \ 42 | REPORTS="$(REPORTS)" \ 43 | PDK="$(CROC_ROOT)/ihp13/pdk" \ 44 | QT_QPA_PLATFORM=$$(if [ -z "$$DISPLAY" ]; then echo "offscreen"; else echo "$$QT_QPA_PLATFORM"; fi) \ 45 | $(OPENROAD) scripts/chip.tcl \ 46 | $$(if [ "$(gui)" = "1" ]; then echo "-gui"; fi) \ 47 | -log $(PROJ_NAME).log \ 48 | 2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $$0 }'; 49 | 50 | or_clean: 51 | rm -rf $(SAVE) 52 | rm -rf $(REPORTS) 53 | rm -rf $(OR_OUT) 54 | rm -f $(PROJ_NAME).log 55 | 56 | start_openroad: 57 | cd $(OR_DIR) && \ 58 | PROJ_NAME="$(PROJ_NAME)" \ 59 | SAVE="$(SAVE)" \ 60 | REPORTS="$(REPORTS)" \ 61 | $(OPENROAD) scripts/startup.tcl 62 | 63 | start_openroad_gui: 64 | cd $(OR_DIR) && \ 65 | PROJ_NAME="$(PROJ_NAME)" \ 66 | SAVE="$(SAVE)" \ 67 | REPORTS="$(REPORTS)" \ 68 | $(OPENROAD) -gui scripts/startup.tcl 69 | 70 | .PHONY: backend openroad or_clean start_openroad start_openroad_gui 71 | -------------------------------------------------------------------------------- /openroad/scripts/checkpoint.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2023 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | # Authors: 6 | # - Jannis Schönleber 7 | # - Philippe Sauter 8 | 9 | # Helper macros to save and load checkpoints 10 | set time [elapsed_run_time] 11 | if { ![info exists save_dir] } {set save_dir "save"} 12 | 13 | proc save_checkpoint { checkpoint_name } { 14 | global save_dir time step_by_step_debug 15 | utl::report "Saving checkpoint $checkpoint_name" 16 | set checkpoint ${save_dir}/${checkpoint_name} 17 | 18 | write_def ${checkpoint}.def 19 | write_verilog ${checkpoint}.v 20 | write_db ${checkpoint}.odb 21 | write_sdc ${checkpoint}.sdc 22 | exec zip -j ${checkpoint}.zip ${checkpoint}.def ${checkpoint}.v ${checkpoint}.odb ${checkpoint}.sdc 23 | file delete ${checkpoint}.def ${checkpoint}.v ${checkpoint}.odb ${checkpoint}.sdc 24 | 25 | set deltaT [expr [elapsed_run_time] - $time] 26 | set time [elapsed_run_time] 27 | utl::report "Time: $time sec deltaT: $deltaT" 28 | if { $step_by_step_debug } { 29 | utl::report "Pause at checkpoint: $checkpoint_name" 30 | gui::pause 31 | } 32 | } 33 | 34 | proc load_checkpoint { checkpoint_name } { 35 | global save_dir 36 | utl::report "Loading checkpoint $checkpoint_name" 37 | set checkpoint ${save_dir}/${checkpoint_name} 38 | 39 | exec unzip -u ${checkpoint}.zip -d ${save_dir}/${checkpoint_name} 40 | #read_verilog ${checkpoint}/$checkpoint_name.v 41 | read_db ${checkpoint}/$checkpoint_name.odb 42 | if { [file exists ${checkpoint}/$checkpoint_name.sdc] } { 43 | read_sdc ${checkpoint}/$checkpoint_name.sdc 44 | } 45 | } 46 | 47 | proc load_checkpoint_def { checkpoint_name } { 48 | global save_dir 49 | utl::report "Loading checkpoint $checkpoint_name" 50 | set checkpoint ${save_dir}/${checkpoint_name} 51 | 52 | exec unzip ${checkpoint}.zip -d ${save_dir} 53 | read_verilog ${checkpoint}/$checkpoint_name.v 54 | read_def ${checkpoint}/$checkpoint_name.def 55 | } -------------------------------------------------------------------------------- /openroad/scripts/floorplan_util.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2023 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | # Authors: 6 | # - Tobias Senti 7 | # - Jannis Schönleber 8 | # - Philippe Sauter 9 | 10 | # Some useful functions for floorplaning 11 | 12 | # place_macro only allows R0, R180, MX, MY 13 | # Example: placeInstance $sram 25 50 R90 14 | proc placeInstance { name x y orient } { 15 | puts "placing $name at {$x $y} $orient" 16 | 17 | set block [ord::get_db_block] 18 | set inst [$block findInst $name] 19 | if {$inst == "NULL"} { 20 | error "Cannot find instance $name" 21 | } 22 | 23 | $inst setLocationOrient $orient 24 | $inst setLocation [ord::microns_to_dbu $x] [ord::microns_to_dbu $y] 25 | $inst setPlacementStatus FIRM 26 | } 27 | 28 | # Add placement blockage over two macros (ie block channels and so on) 29 | proc add_macro_blockage {negative_padding name1 name2} { 30 | set block [ord::get_db_block] 31 | set inst1 [odb::dbBlock_findInst $block $name1] 32 | set inst2 [odb::dbBlock_findInst $block $name2] 33 | set bb1 [odb::dbInst_getBBox $inst1] 34 | set bb2 [odb::dbInst_getBBox $inst2] 35 | # Find min max of X and Y 36 | set minx [expr min( [odb::dbBox_xMin $bb1], [odb::dbBox_xMin $bb2]) + [ord::microns_to_dbu $negative_padding]] 37 | set miny [expr min( [odb::dbBox_yMin $bb1], [odb::dbBox_yMin $bb2]) + [ord::microns_to_dbu $negative_padding]] 38 | set maxx [expr max( [odb::dbBox_xMax $bb1], [odb::dbBox_xMax $bb2]) - [ord::microns_to_dbu $negative_padding]] 39 | set maxy [expr max( [odb::dbBox_yMax $bb1], [odb::dbBox_yMax $bb2]) - [ord::microns_to_dbu $negative_padding]] 40 | 41 | set blockage [odb::dbBlockage_create [ord::get_db_block] $minx $miny $maxx $maxy] 42 | return $blockage 43 | } 44 | -------------------------------------------------------------------------------- /openroad/scripts/power_connect.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | 9 | ########################################################################## 10 | # Global Connections 11 | ########################################################################## 12 | 13 | # std cells 14 | add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD} -power 15 | add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS} -ground 16 | # pads 17 | add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {vdd} -power 18 | add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {vss} -ground 19 | # fix for bondpad/port naming 20 | add_global_connection -net {VDDIO} -inst_pattern {.*} -pin_pattern {.*vdd_RING} -power 21 | add_global_connection -net {VSSIO} -inst_pattern {.*} -pin_pattern {.*vss_RING} -ground 22 | # rams 23 | add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDDARRAY} -power 24 | add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDDARRAY!} -power 25 | add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power 26 | add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground 27 | 28 | # pads 29 | add_global_connection -net {VDDIO} -inst_pattern {.*} -pin_pattern {iovdd} -power 30 | add_global_connection -net {VSSIO} -inst_pattern {.*} -pin_pattern {iovss} -ground 31 | # fix for bondpad/port naming 32 | add_global_connection -net {VDDIO} -inst_pattern {.*} -pin_pattern {.*iovdd_RING} -power 33 | add_global_connection -net {VSSIO} -inst_pattern {.*} -pin_pattern {.*iovss_RING} -ground 34 | 35 | # connection 36 | global_connect 37 | 38 | # voltage domains 39 | set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} 40 | # standard cell grid and rings 41 | define_pdn_grid -name {core_grid} -voltage_domains {CORE} -------------------------------------------------------------------------------- /openroad/scripts/startup.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | # 5 | # Authors: 6 | # - Tim Fischer 7 | 8 | 9 | # Check whether PROJ_NAME is part of the environment variables 10 | 11 | 12 | 13 | if { [info exists ::env(PROJ_NAME)] } { 14 | set proj_name $::env(PROJ_NAME) 15 | } else { 16 | set proj_name "untitled" 17 | } 18 | 19 | if { [info exists ::env(REPORTS)] } { 20 | set report_dir $::env(REPORTS) 21 | } else { 22 | set report_dir "reports" 23 | } 24 | 25 | if { [info exists ::env(SAVE)] } { 26 | set save_dir $::env(SAVE) 27 | } else { 28 | set save_dir "save" 29 | } 30 | 31 | utl::report "Setting up project $proj_name" 32 | utl::report " - Report directory: $report_dir" 33 | utl::report " - Save directory: $save_dir" 34 | 35 | # helper scripts 36 | source scripts/reports.tcl 37 | source scripts/checkpoint.tcl 38 | 39 | # initialize technology data 40 | source scripts/init_tech.tcl 41 | -------------------------------------------------------------------------------- /openroad/src/instances.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | # Automatic collection of SRAMs and delay-line macros 9 | # Used for automatic macro placement 10 | # set macros [list] 11 | 12 | # set srams [get_cells *RM_IHP*] 13 | # foreach inst $srams { 14 | # lappend macros $inst 15 | # } 16 | 17 | 18 | # Macro names as produced by the yosys synthesis 19 | # Used for manual macro placement 20 | 21 | set CROC i_croc_soc/i_croc 22 | set USER i_croc_soc/i_user 23 | set IBEX $CROC/i_core_wrap.i_ibex 24 | set SRAM $CROC/gen_sram_bank 25 | set JTAG $CROC/i_dmi_jtag 26 | set SRAM_512x32 gen_512x32xBx1.i_cut 27 | 28 | # memory banks 29 | set sram {\[0\].i_sram/} 30 | set bank0_sram0 $SRAM$sram$SRAM_512x32 31 | set sram {\[1\].i_sram/} 32 | set bank1_sram0 $SRAM$sram$SRAM_512x32 33 | 34 | set JTAG_ASYNC_REQ [get_nets $JTAG/i_dmi_cdc.i_cdc_req/*async_*] 35 | set JTAG_ASYNC_RSP [get_nets $JTAG/i_dmi_cdc.i_cdc_resp/*async_*] -------------------------------------------------------------------------------- /rtl/apb/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: apb 3 | authors: 4 | - "Andreas Kurth " # current maintainer 5 | - "Fabian Schuiki " 6 | - "Wolfgang Roenninger " 7 | 8 | dependencies: 9 | common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.2 } 10 | 11 | export_include_dirs: 12 | - include 13 | 14 | sources: 15 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this 16 | # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 17 | # levels 1 and 0, etc. Files within a level are ordered alphabetically. 18 | # Level 0 19 | - apb_pkg.sv -------------------------------------------------------------------------------- /rtl/apb/README.md: -------------------------------------------------------------------------------- 1 | # APB 2 | 3 | This is the implementation of the AMBA APB4 protocol, version 2.0, developed as part of the PULP 4 | platform at ETH Zurich. 5 | 6 | Maintainer: Andreas Kurth 7 | 8 | ## Overview 9 | 10 | ### Package / Macros 11 | 12 | | Name | Description | 13 | |------------------------------------------|-------------------------------------------------------------------| 14 | | [`apb_pkg`](src/apb_pkg.sv) | Package with APB4 constants and type definitions | 15 | | [`apb/typedef`](include/apb/typedef.svh) | Macros which define the APB4 request/response structs | 16 | | [`apb/assign`](include/apb/typedef.svh) | Macros which assign/set/translates APB4 interfaces and structs | 17 | 18 | ### Interfaces 19 | 20 | | Name | Description | 21 | |------------------------------------------|-------------------------------------------------------------------| 22 | | [`APB`](src/apb_intf.sv) | APB4 interface with configurable address, data and sel widths | 23 | | [`APB_DV`](src/apb_intf.sv) | Clocked variant of `APB` for design verification | 24 | 25 | ### Leaf Modules 26 | 27 | | Name | Description | 28 | |----------------------------------+-----------------------------------------------------------| 29 | | [`apb_regs`](src/apb_regs.sv) | Read and write registers, with optional read only mapping | 30 | | [`apb_demux`](src/apb_demux.sv) | APB4 demultiplexer with using select signal | 31 | 32 | ### Verification and Simulation 33 | 34 | | Name | Description | 35 | |------------------------------------------|-------------------------------------------------------------------| 36 | | [`apb_driver`](src/apb_test.sv) | APB driver (can act as either slave or master) | 37 | -------------------------------------------------------------------------------- /rtl/apb/apb_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Wolfgang Roenninger 12 | 13 | // Description: Package with constant APB v2.0 constants 14 | 15 | package apb_pkg; 16 | 17 | typedef logic [2:0] prot_t; 18 | 19 | localparam RESP_OKAY = 1'b0; 20 | localparam RESP_SLVERR = 1'b1; 21 | 22 | endpackage 23 | -------------------------------------------------------------------------------- /rtl/apb_uart/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: apb_uart 3 | authors: [ 4 | "Sebastian Witt", 5 | "Jonathan Kimmitt" 6 | ] 7 | 8 | dependencies: 9 | apb: { git: "https://github.com/pulp-platform/apb", version: 0.2.1 } 10 | register_interface: { git: "https://github.com/pulp-platform/register_interface", version: 0.3.6 } 11 | 12 | sources: 13 | - slib_clock_div.sv 14 | - slib_counter.sv 15 | - slib_edge_detect.sv 16 | - slib_fifo.sv 17 | - slib_input_filter.sv 18 | - slib_input_sync.sv 19 | - slib_mv_filter.sv 20 | - uart_baudgen.sv 21 | - uart_interrupt.sv 22 | - uart_receiver.sv 23 | - uart_transmitter.sv 24 | - apb_uart.sv 25 | - apb_uart_wrap.sv 26 | - reg_uart_wrap.sv 27 | -------------------------------------------------------------------------------- /rtl/apb_uart/slib_clock_div.sv: -------------------------------------------------------------------------------- 1 | // 2 | // UART 16750 3 | // 4 | // Converted to System Verilog by Jonathan Kimmitt 5 | // This version has been partially checked with formality but some bugs remain 6 | // Original Author: Sebastian Witt 7 | // Date: 14.03.2019 8 | // Version: 1.6 9 | // 10 | // History: 1.0 - Initial version 11 | // 1.1 - THR empty interrupt register connected to RST 12 | // 1.2 - Registered outputs 13 | // 1.3 - Automatic flow control 14 | // 1.4 - De-assert IIR FIFO64 when FIFO is disabled 15 | // 1.5 - Inverted low active outputs when RST is active 16 | // 1.6 - Converted to System Verilog 17 | // 18 | // 19 | // This code is free software; you can redistribute it and/or 20 | // modify it under the terms of the GNU Lesser General Public 21 | // License as published by the Free Software Foundation; either 22 | // version 2.1 of the License, or (at your option) any later version. 23 | // 24 | // This code is distributed in the hope that it will be useful, 25 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 26 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 27 | // Lesser General Public License for more details. 28 | // 29 | // You should have received a copy of the GNU Lesser General Public 30 | // License along with this library; if not, write to the 31 | // Free Software Foundation, Inc., 59 Temple Place, Suite 330, 32 | // Boston, MA 02111-1307 USA 33 | // 34 | 35 | module slib_clock_div #(parameter RATIO = 4) ( 36 | input wire CLK, 37 | input wire RST, 38 | input wire CE, 39 | output logic Q); // 507 40 | /* design slib_clock_div */ 41 | /* architecture rtl */ 42 | typedef enum {FALSE,TRUE} bool_t; // 527 43 | reg iQ; // 612 44 | reg [$clog2(RATIO-1)-1:0] iCounter; 45 | 46 | always @(posedge CLK or posedge RST) 47 | begin 48 | if ((RST == 1'b1)) 49 | begin 50 | iCounter <= 0; // 413 51 | iQ <= 1'b0; // 413 52 | end 53 | else 54 | begin 55 | iQ <= 1'b0; // 413 56 | if ((CE == 1'b1)) 57 | begin 58 | if ((iCounter == (RATIO - 1))) 59 | begin 60 | iQ <= 1'b1; // 413 61 | iCounter <= 0; // 413 62 | end 63 | else 64 | begin 65 | iCounter <= iCounter + 1; // 413 66 | end 67 | end 68 | 69 | end 70 | 71 | end 72 | 73 | assign /*432*/ Q = iQ; // 434 74 | 75 | endmodule // slib_clock_div 76 | -------------------------------------------------------------------------------- /rtl/apb_uart/slib_edge_detect.sv: -------------------------------------------------------------------------------- 1 | // 2 | // UART 16750 3 | // 4 | // Converted to System Verilog by Jonathan Kimmitt 5 | // This version has been partially checked with formality but some bugs remain 6 | // Original Author: Sebastian Witt 7 | // Date: 14.03.2019 8 | // Version: 1.6 9 | // 10 | // History: 1.0 - Initial version 11 | // 1.1 - THR empty interrupt register connected to RST 12 | // 1.2 - Registered outputs 13 | // 1.3 - Automatic flow control 14 | // 1.4 - De-assert IIR FIFO64 when FIFO is disabled 15 | // 1.5 - Inverted low active outputs when RST is active 16 | // 1.6 - Converted to System Verilog 17 | // 18 | // 19 | // This code is free software; you can redistribute it and/or 20 | // modify it under the terms of the GNU Lesser General Public 21 | // License as published by the Free Software Foundation; either 22 | // version 2.1 of the License, or (at your option) any later version. 23 | // 24 | // This code is distributed in the hope that it will be useful, 25 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 26 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 27 | // Lesser General Public License for more details. 28 | // 29 | // You should have received a copy of the GNU Lesser General Public 30 | // License along with this library; if not, write to the 31 | // Free Software Foundation, Inc., 59 Temple Place, Suite 330, 32 | // Boston, MA 02111-1307 USA 33 | // 34 | 35 | module slib_edge_detect( 36 | input wire CLK, 37 | input wire RST, 38 | input wire D, 39 | output logic RE, 40 | output logic FE); // 507 41 | /* design slib_edge_detect */ 42 | /* architecture rtl */ 43 | typedef enum {FALSE,TRUE} bool_t; // 527 44 | reg iDd; // 612 45 | 46 | always @(posedge CLK or posedge RST) 47 | begin 48 | if ((RST == 1'b1)) 49 | begin 50 | iDd <= 1'b0; // 413 51 | end 52 | else 53 | begin 54 | iDd <= D; // 413 55 | end 56 | 57 | end 58 | 59 | assign /*903*/ RE = iDd == 1'b0 && D == 1'b1 ? 1'b1 : 1'b0; // 905 60 | assign /*903*/ FE = iDd == 1'b1 && D == 1'b0 ? 1'b1 : 1'b0; // 905 61 | 62 | endmodule // slib_edge_detect 63 | -------------------------------------------------------------------------------- /rtl/apb_uart/slib_input_sync.sv: -------------------------------------------------------------------------------- 1 | // 2 | // UART 16750 3 | // 4 | // Converted to System Verilog by Jonathan Kimmitt 5 | // This version has been partially checked with formality but some bugs remain 6 | // Original Author: Sebastian Witt 7 | // Date: 14.03.2019 8 | // Version: 1.6 9 | // 10 | // History: 1.0 - Initial version 11 | // 1.1 - THR empty interrupt register connected to RST 12 | // 1.2 - Registered outputs 13 | // 1.3 - Automatic flow control 14 | // 1.4 - De-assert IIR FIFO64 when FIFO is disabled 15 | // 1.5 - Inverted low active outputs when RST is active 16 | // 1.6 - Converted to System Verilog 17 | // 18 | // 19 | // This code is free software; you can redistribute it and/or 20 | // modify it under the terms of the GNU Lesser General Public 21 | // License as published by the Free Software Foundation; either 22 | // version 2.1 of the License, or (at your option) any later version. 23 | // 24 | // This code is distributed in the hope that it will be useful, 25 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 26 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 27 | // Lesser General Public License for more details. 28 | // 29 | // You should have received a copy of the GNU Lesser General Public 30 | // License along with this library; if not, write to the 31 | // Free Software Foundation, Inc., 59 Temple Place, Suite 330, 32 | // Boston, MA 02111-1307 USA 33 | // 34 | 35 | module slib_input_sync( 36 | input wire CLK, 37 | input wire RST, 38 | input wire D, 39 | output logic Q); // 507 40 | /* design slib_input_sync */ 41 | /* architecture rtl */ 42 | typedef enum {FALSE,TRUE} bool_t; // 527 43 | reg [1:0] iD; // 605 44 | 45 | always @(posedge CLK or posedge RST) 46 | begin 47 | if ((RST == 1'b1)) 48 | begin 49 | /* block const 263 */ 50 | iD <= (0<<1)|(0<<0); 51 | end 52 | else 53 | begin 54 | iD[0] <= D; 55 | iD[1] <= iD[0]; 56 | end 57 | end 58 | 59 | assign /*432*/ Q = iD[1]; // 434 60 | endmodule // slib_input_sync 61 | -------------------------------------------------------------------------------- /rtl/common_cells/binary_to_gray.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Fabian Schuiki 13 | 14 | /// A binary to gray code converter. 15 | module binary_to_gray #( 16 | parameter int N = -1 17 | )( 18 | input logic [N-1:0] A, 19 | output logic [N-1:0] Z 20 | ); 21 | assign Z = A ^ (A >> 1); 22 | endmodule 23 | -------------------------------------------------------------------------------- /rtl/common_cells/cb_filter_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2019 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Wolfgang Roenninger 12 | 13 | /// Package with the struct definition for the seeds and an example. 14 | package cb_filter_pkg; 15 | typedef struct packed { 16 | int unsigned PermuteSeed; 17 | int unsigned XorSeed; 18 | } cb_seed_t; 19 | 20 | // example seeding struct 21 | localparam cb_seed_t [2:0] EgSeeds = '{ 22 | '{PermuteSeed: 32'd299034753, XorSeed: 32'd4094834 }, 23 | '{PermuteSeed: 32'd19921030, XorSeed: 32'd995713 }, 24 | '{PermuteSeed: 32'd294388, XorSeed: 32'd65146511 } 25 | }; 26 | endpackage 27 | -------------------------------------------------------------------------------- /rtl/common_cells/cc_onehot.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2021 ETH Zurich. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | /// Hardware implementation of SystemVerilog's `$onehot()` function. 12 | /// It uses a tree of half adders and a separate 13 | /// or reduction tree for the carry. 14 | 15 | // Author: Florian Zaruba 16 | // Author: Fabian Schuiki 17 | // Author: Stefan Mach 18 | module cc_onehot #( 19 | parameter int unsigned Width = 4 20 | ) ( 21 | input logic [Width-1:0] d_i, 22 | output logic is_onehot_o 23 | ); 24 | // trivial base case 25 | if (Width == 1) begin : gen_degenerated_onehot 26 | assign is_onehot_o = d_i; 27 | end else begin : gen_onehot 28 | localparam int LVLS = $clog2(Width) + 1; 29 | 30 | logic [LVLS-1:0][2**(LVLS-1)-1:0] sum, carry; 31 | logic [LVLS-2:0] carry_array; 32 | 33 | // Extend to a power of two. 34 | assign sum[0] = $unsigned(d_i); 35 | 36 | // generate half adders for each lvl 37 | // lvl 0 is the input level 38 | for (genvar i = 1; i < LVLS; i++) begin : gen_lvl 39 | localparam int unsigned LVLWidth = 2**LVLS / 2**i; 40 | for (genvar j = 0; j < LVLWidth; j+=2) begin : gen_width 41 | assign sum[i][j/2] = sum[i-1][j] ^ sum[i-1][j+1]; 42 | assign carry[i][j/2] = sum[i-1][j] & sum[i-1][j+1]; 43 | end 44 | // generate carry tree 45 | assign carry_array[i-1] = |carry[i][LVLWidth/2-1:0]; 46 | end 47 | assign is_onehot_o = sum[LVLS-1][0] & ~|carry_array; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /rtl/common_cells/cdc_reset_ctrlr_pkg.sv: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // Copyright (C) 2022 ETH Zurich, University of Bologna 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // SPDX-License-Identifier: SHL-0.51 12 | //----------------------------------------------------------------------------- 13 | // 14 | // Author: Manuel Eggimann 15 | // 16 | // Contains common defintions for the CDC Clear Synchronization Circuitry 17 | 18 | package cdc_reset_ctrlr_pkg; 19 | 20 | typedef enum logic[1:0] { 21 | CLEAR_PHASE_IDLE, 22 | CLEAR_PHASE_ISOLATE, 23 | CLEAR_PHASE_CLEAR, 24 | CLEAR_PHASE_POST_CLEAR 25 | } clear_seq_phase_e; 26 | 27 | endpackage : cdc_reset_ctrlr_pkg 28 | -------------------------------------------------------------------------------- /rtl/common_cells/counter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Generic up/down counter 13 | 14 | module counter #( 15 | parameter int unsigned WIDTH = 4, 16 | parameter bit STICKY_OVERFLOW = 1'b0 17 | )( 18 | input logic clk_i, 19 | input logic rst_ni, 20 | input logic clear_i, // synchronous clear 21 | input logic en_i, // enable the counter 22 | input logic load_i, // load a new value 23 | input logic down_i, // downcount, default is up 24 | input logic [WIDTH-1:0] d_i, 25 | output logic [WIDTH-1:0] q_o, 26 | output logic overflow_o 27 | ); 28 | delta_counter #( 29 | .WIDTH (WIDTH), 30 | .STICKY_OVERFLOW (STICKY_OVERFLOW) 31 | ) i_counter ( 32 | .clk_i, 33 | .rst_ni, 34 | .clear_i, 35 | .en_i, 36 | .load_i, 37 | .down_i, 38 | .delta_i({{WIDTH-1{1'b0}}, 1'b1}), 39 | .d_i, 40 | .q_o, 41 | .overflow_o 42 | ); 43 | endmodule 44 | -------------------------------------------------------------------------------- /rtl/common_cells/credit_counter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | 5 | // Author: Fabian Schuiki 6 | // Author: Paul Scheffler 7 | 8 | `include "common_cells/registers.svh" 9 | `include "common_cells/assertions.svh" 10 | 11 | module credit_counter #( 12 | parameter int unsigned NumCredits = 0, 13 | /// Whether credit is full or empty on reset 14 | parameter bit InitCreditEmpty = 1'b0, 15 | /// Derived parameters *Do not override* 16 | parameter int unsigned InitNumCredits = InitCreditEmpty ? '0 : NumCredits, 17 | parameter type credit_cnt_t = logic [$clog2(NumCredits):0] 18 | ) ( 19 | input logic clk_i, 20 | input logic rst_ni, 21 | 22 | output credit_cnt_t credit_o, 23 | 24 | input logic credit_give_i, 25 | input logic credit_take_i, 26 | input logic credit_init_i, // Reinitialize (soft-reset) credit; takes priority 27 | 28 | output logic credit_left_o, 29 | output logic credit_crit_o, // Giving one more credit will fill the credits 30 | output logic credit_full_o 31 | ); 32 | 33 | credit_cnt_t credit_d, credit_q; 34 | logic increment, decrement; 35 | 36 | assign decrement = credit_take_i & ~credit_give_i; 37 | assign increment = ~credit_take_i & credit_give_i; 38 | 39 | always_comb begin 40 | credit_d = credit_q; 41 | if (decrement) credit_d = credit_q - 1; 42 | else if (increment) credit_d = credit_q + 1; 43 | end 44 | 45 | `FFARNC(credit_q, credit_d, credit_init_i, InitNumCredits, clk_i, rst_ni) 46 | 47 | assign credit_o = credit_q; 48 | assign credit_left_o = (credit_q != '0); 49 | assign credit_crit_o = (credit_q == NumCredits-1); 50 | assign credit_full_o = (credit_q == NumCredits); 51 | 52 | `ASSERT_NEVER(CreditUnderflow, credit_o == '0 && decrement) 53 | `ASSERT_NEVER(CreditOverflow, credit_o == NumCredits && increment) 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /rtl/common_cells/ecc_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Florian Zaruba 12 | // 13 | /// Contains common ECC definitions and helper functions. 14 | 15 | package ecc_pkg; 16 | 17 | // Calculate required ECC parity width: 18 | function automatic int unsigned get_parity_width (input int unsigned data_width); 19 | // data_width + cw_width + 1 <= 2**cw_width 20 | int unsigned cw_width = 2; 21 | while (unsigned'(2**cw_width) < cw_width + data_width + 1) cw_width++; 22 | return cw_width; 23 | endfunction 24 | 25 | // Calculate required ECC codeword width: 26 | function automatic int unsigned get_cw_width (input int unsigned data_width); 27 | // data width + parity width + one additional parity bit (for double error detection) 28 | return data_width + get_parity_width(data_width); 29 | endfunction 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /rtl/common_cells/edge_detect.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Edge detector, clock needs to oversample for proper edge detection 13 | 14 | module edge_detect ( 15 | input logic clk_i, // Clock 16 | input logic rst_ni, // Asynchronous reset active low 17 | input logic d_i, // data stream in 18 | output logic re_o, // rising edge detected 19 | output logic fe_o // falling edge detected 20 | ); 21 | 22 | sync_wedge i_sync_wedge ( 23 | .clk_i ( clk_i ), 24 | .rst_ni ( rst_ni ), 25 | .en_i ( 1'b1 ), 26 | .serial_i ( d_i ), 27 | .r_edge_o ( re_o ), 28 | .f_edge_o ( fe_o ), 29 | .serial_o ( ) 30 | ); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /rtl/common_cells/edge_propagator.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator ( 14 | input logic clk_tx_i, 15 | input logic rstn_tx_i, 16 | input logic edge_i, 17 | input logic clk_rx_i, 18 | input logic rstn_rx_i, 19 | output logic edge_o 20 | ); 21 | 22 | edge_propagator_ack i_edge_propagator_ack ( 23 | .clk_tx_i, 24 | .rstn_tx_i, 25 | .edge_i, 26 | .ack_tx_o (/* unused */), 27 | .clk_rx_i, 28 | .rstn_rx_i, 29 | .edge_o 30 | ); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /rtl/common_cells/edge_propagator_ack.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator_ack ( 14 | input logic clk_tx_i, 15 | input logic rstn_tx_i, 16 | input logic edge_i, 17 | output logic ack_tx_o, 18 | input logic clk_rx_i, 19 | input logic rstn_rx_i, 20 | output logic edge_o 21 | ); 22 | 23 | logic [1:0] sync_a; 24 | logic sync_b; 25 | 26 | logic r_input_reg; 27 | logic s_input_reg_next; 28 | 29 | assign ack_tx_o = sync_a[0]; 30 | 31 | assign s_input_reg_next = edge_i | (r_input_reg & ~sync_a[0]); 32 | 33 | always @(negedge rstn_tx_i or posedge clk_tx_i) begin 34 | if (~rstn_tx_i) begin 35 | r_input_reg <= 1'b0; 36 | sync_a <= 2'b00; 37 | end else begin 38 | r_input_reg <= s_input_reg_next; 39 | sync_a <= {sync_b,sync_a[1]}; 40 | end 41 | end 42 | 43 | pulp_sync_wedge u_sync_clkb ( 44 | .clk_i ( clk_rx_i ), 45 | .rstn_i ( rstn_rx_i ), 46 | .en_i ( 1'b1 ), 47 | .serial_i ( r_input_reg ), 48 | .r_edge_o ( edge_o ), 49 | .f_edge_o ( ), 50 | .serial_o ( sync_b ) 51 | ); 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /rtl/common_cells/edge_propagator_rx.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator_rx ( 14 | input logic clk_i, 15 | input logic rstn_i, 16 | input logic valid_i, 17 | output logic ack_o, 18 | output logic valid_o 19 | ); 20 | 21 | pulp_sync_wedge i_sync_clkb ( 22 | .clk_i ( clk_i ), 23 | .rstn_i ( rstn_i ), 24 | .en_i ( 1'b1 ), 25 | .serial_i ( valid_i ), 26 | .r_edge_o ( valid_o ), 27 | .f_edge_o ( ), 28 | .serial_o ( ack_o ) 29 | ); 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /rtl/common_cells/edge_propagator_tx.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module edge_propagator_tx ( 14 | input logic clk_i, 15 | input logic rstn_i, 16 | input logic valid_i, 17 | input logic ack_i, 18 | output logic valid_o 19 | ); 20 | 21 | logic [1:0] sync_a; 22 | 23 | logic r_input_reg; 24 | logic s_input_reg_next; 25 | 26 | assign s_input_reg_next = valid_i | (r_input_reg & ~sync_a[0]); 27 | 28 | always @(negedge rstn_i or posedge clk_i) begin 29 | if (~rstn_i) begin 30 | r_input_reg <= 1'b0; 31 | sync_a <= 2'b00; 32 | end else begin 33 | r_input_reg <= s_input_reg_next; 34 | sync_a <= {ack_i,sync_a[1]}; 35 | end 36 | end 37 | 38 | assign valid_o = r_input_reg; 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/common_cells/gray_to_binary.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Fabian Schuiki 13 | 14 | /// A gray code to binary converter. 15 | module gray_to_binary #( 16 | parameter int N = -1 17 | )( 18 | input logic [N-1:0] A, 19 | output logic [N-1:0] Z 20 | ); 21 | for (genvar i = 0; i < N; i++) 22 | assign Z[i] = ^A[N-1:i]; 23 | endmodule 24 | -------------------------------------------------------------------------------- /rtl/common_cells/lfsr_16bit.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba, ETH Zurich 12 | // Date: 5.11.2018 13 | // Description: 16-bit LFSR 14 | 15 | `include "common_cells/assertions.svh" 16 | 17 | // -------------- 18 | // 16-bit LFSR 19 | // -------------- 20 | // 21 | // Description: Shift register 22 | // 23 | module lfsr_16bit #( 24 | parameter logic [15:0] SEED = 8'b0, 25 | parameter int unsigned WIDTH = 16 26 | )( 27 | input logic clk_i, 28 | input logic rst_ni, 29 | input logic en_i, 30 | output logic [WIDTH-1:0] refill_way_oh, 31 | output logic [$clog2(WIDTH)-1:0] refill_way_bin 32 | ); 33 | 34 | localparam int unsigned LogWidth = $clog2(WIDTH); 35 | 36 | logic [15:0] shift_d, shift_q; 37 | 38 | 39 | always_comb begin 40 | 41 | automatic logic shift_in; 42 | shift_in = !(shift_q[15] ^ shift_q[12] ^ shift_q[5] ^ shift_q[1]); 43 | 44 | shift_d = shift_q; 45 | 46 | if (en_i) 47 | shift_d = {shift_q[14:0], shift_in}; 48 | 49 | // output assignment 50 | refill_way_oh = 'b0; 51 | refill_way_oh[shift_q[LogWidth-1:0]] = 1'b1; 52 | refill_way_bin = shift_q; 53 | end 54 | 55 | always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ 56 | if(~rst_ni) begin 57 | shift_q <= SEED; 58 | end else begin 59 | shift_q <= shift_d; 60 | end 61 | end 62 | 63 | `ifndef COMMON_CELLS_ASSERTS_OFF 64 | `ASSERT_INIT(width_gt_16, WIDTH <= 16, 65 | "WIDTH needs to be less than 16 because of the 16-bit LFSR") 66 | `endif 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /rtl/common_cells/lfsr_8bit.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Igor Loi - University of Bologna 12 | // Author: Florian Zaruba, ETH Zurich 13 | // Date: 12.11.2017 14 | // Description: 8-bit LFSR 15 | 16 | `include "common_cells/assertions.svh" 17 | 18 | /// 8 bit Linear Feedback Shift register 19 | module lfsr_8bit #( 20 | parameter logic [7:0] SEED = 8'b0, 21 | parameter int unsigned WIDTH = 8 22 | ) ( 23 | input logic clk_i, 24 | input logic rst_ni, 25 | input logic en_i, 26 | output logic [ WIDTH-1:0] refill_way_oh, 27 | output logic [$clog2(WIDTH)-1:0] refill_way_bin 28 | ); 29 | 30 | localparam int unsigned LogWidth = $clog2(WIDTH); 31 | 32 | logic [7:0] shift_d, shift_q; 33 | 34 | always_comb begin 35 | 36 | automatic logic shift_in; 37 | shift_in = !(shift_q[7] ^ shift_q[3] ^ shift_q[2] ^ shift_q[1]); 38 | 39 | shift_d = shift_q; 40 | 41 | if (en_i) shift_d = {shift_q[6:0], shift_in}; 42 | 43 | // output assignment 44 | refill_way_oh = 'b0; 45 | refill_way_oh[shift_q[LogWidth - 1:0]] = 1'b1; 46 | refill_way_bin = shift_q; 47 | end 48 | 49 | always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ 50 | if (~rst_ni) begin 51 | shift_q <= SEED; 52 | end else begin 53 | shift_q <= shift_d; 54 | end 55 | end 56 | 57 | `ifndef COMMON_CELLS_ASSERTS_OFF 58 | `ASSERT_INIT(width_gt_8, WIDTH <= 8, "WIDTH needs to be less than 8 because of the 8-bit LFSR") 59 | `endif 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /rtl/common_cells/mv_filter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | 13 | module mv_filter #( 14 | parameter int unsigned WIDTH = 4, 15 | parameter int unsigned THRESHOLD = 10 16 | )( 17 | input logic clk_i, 18 | input logic rst_ni, 19 | input logic sample_i, 20 | input logic clear_i, 21 | input logic d_i, 22 | output logic q_o 23 | ); 24 | logic [WIDTH-1:0] counter_q, counter_d; 25 | logic d, q; 26 | 27 | assign q_o = q; 28 | 29 | always_comb begin 30 | counter_d = counter_q; 31 | d = q; 32 | 33 | if (counter_q >= THRESHOLD[WIDTH-1:0]) begin 34 | d = 1'b1; 35 | end else if (sample_i && d_i) begin 36 | counter_d = counter_q + 1; 37 | end 38 | 39 | // sync reset 40 | if (clear_i) begin 41 | counter_d = '0; 42 | d = 1'b0; 43 | end 44 | end 45 | 46 | always_ff @(posedge clk_i or negedge rst_ni) begin 47 | if (~rst_ni) begin 48 | counter_q <= '0; 49 | q <= 1'b0; 50 | end else begin 51 | counter_q <= counter_d; 52 | q <= d; 53 | end 54 | end 55 | endmodule 56 | -------------------------------------------------------------------------------- /rtl/common_cells/onehot_to_bin.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Franceco Conti 12 | 13 | `include "common_cells/assertions.svh" 14 | 15 | module onehot_to_bin #( 16 | parameter int unsigned ONEHOT_WIDTH = 16, 17 | // Do Not Change 18 | parameter int unsigned BIN_WIDTH = ONEHOT_WIDTH == 1 ? 1 : $clog2(ONEHOT_WIDTH) 19 | ) ( 20 | input logic [ONEHOT_WIDTH-1:0] onehot, 21 | output logic [BIN_WIDTH-1:0] bin 22 | ); 23 | 24 | for (genvar j = 0; j < BIN_WIDTH; j++) begin : gen_jl 25 | logic [ONEHOT_WIDTH-1:0] tmp_mask; 26 | for (genvar i = 0; i < ONEHOT_WIDTH; i++) begin : gen_il 27 | logic [BIN_WIDTH-1:0] tmp_i; 28 | assign tmp_i = BIN_WIDTH'(i); 29 | assign tmp_mask[i] = tmp_i[j]; 30 | end 31 | assign bin[j] = |(tmp_mask & onehot); 32 | end 33 | 34 | `ifndef COMMON_CELLS_ASSERTS_OFF 35 | `ASSERT_FINAL(more_than_2_bits, $onehot0(onehot), "More than two bit set in the one-hot signal") 36 | `endif 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/common_cells/popcount.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2013-2018 ETH Zurich, University of Bologna 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Manuel Eggimann 12 | 13 | // Description: This module calculates the hamming weight (number of ones) in 14 | // its input vector. Any unsigned INPUT_WIDTH larger or equal 1 is legal. The output result 15 | // width is ceil(log2(INPUT_WIDTH))+1. 16 | // 17 | // This module used to be implemented using a binary added tree. However, 18 | // the heuristics of modern logic Synthesizers work much better with a flat high 19 | // level description using a for loop and yield exactly the same or even better results. 20 | 21 | 22 | module popcount #( 23 | parameter int unsigned INPUT_WIDTH = 256, 24 | localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH) + 1 25 | ) ( 26 | input logic [ INPUT_WIDTH-1:0] data_i, 27 | output logic [PopcountWidth-1:0] popcount_o 28 | ); 29 | 30 | if (INPUT_WIDTH < 1) 31 | $error("INPUT_WIDTH must be larger or equal to 1."); 32 | 33 | always_comb begin 34 | popcount_o = 0; 35 | for (int i = 0; i < INPUT_WIDTH; i++) begin 36 | popcount_o += data_i[i]; 37 | end 38 | end 39 | 40 | endmodule : popcount 41 | -------------------------------------------------------------------------------- /rtl/common_cells/read.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2022 EPFL 2 | // Solderpad Hardware License, Version 2.1, see LICENSE.md for details. 3 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | 5 | // Author: Davide Schiavone, EPFL, OpenHW Group 6 | // Date: 07.11.2022 7 | // Description: Dummy circuit to assign a signal, prevent signal being removed after non-ungroupped synthesis compilation 8 | 9 | (* no_ungroup *) 10 | module read #( 11 | parameter int unsigned Width = 1, 12 | parameter type T = logic [Width-1:0] 13 | ) ( 14 | input T d_i, 15 | output T d_o 16 | ); 17 | 18 | assign d_o = d_i; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /rtl/common_cells/rstgen.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Davide Rossi 12 | 13 | module rstgen ( 14 | input logic clk_i, 15 | input logic rst_ni, 16 | input logic test_mode_i, 17 | output logic rst_no, 18 | output logic init_no 19 | ); 20 | 21 | rstgen_bypass i_rstgen_bypass ( 22 | .clk_i ( clk_i ), 23 | .rst_ni ( rst_ni ), 24 | .rst_test_mode_ni ( rst_ni ), 25 | .test_mode_i ( test_mode_i ), 26 | .rst_no ( rst_no ), 27 | .init_no ( init_no ) 28 | ); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /rtl/common_cells/serial_deglitch.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Author: Florian Zaruba 12 | // Description: Deglitches a serial line by taking multiple samples until 13 | // asserting the output high/low. 14 | 15 | module serial_deglitch #( 16 | parameter int unsigned SIZE = 4 17 | )( 18 | input logic clk_i, // clock 19 | input logic rst_ni, // asynchronous reset active low 20 | input logic en_i, // enable 21 | input logic d_i, // serial data in 22 | output logic q_o // filtered data out 23 | ); 24 | logic [SIZE-1:0] count_q; 25 | logic q; 26 | 27 | always_ff @(posedge clk_i or negedge rst_ni) begin 28 | if (~rst_ni) begin 29 | count_q <= '0; 30 | q <= 1'b0; 31 | end else begin 32 | if (en_i) begin 33 | if (d_i == 1'b1 && count_q != SIZE[SIZE-1:0]) begin 34 | count_q <= count_q + 1; 35 | end else if (d_i == 1'b0 && count_q != SIZE[SIZE-1:0]) begin 36 | count_q <= count_q - 1; 37 | end 38 | end 39 | end 40 | end 41 | 42 | // output process 43 | always_comb begin 44 | if (count_q == SIZE[SIZE-1:0]) begin 45 | q_o = 1'b1; 46 | end else if (count_q == 0) begin 47 | q_o = 1'b0; 48 | end 49 | end 50 | endmodule 51 | -------------------------------------------------------------------------------- /rtl/common_cells/shift_reg.sv: -------------------------------------------------------------------------------- 1 | 2 | // Copyright 2018 ETH Zurich and University of Bologna. 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Author: 13 | // 14 | // Description: Simple shift register for arbitrary depth and types 15 | 16 | module shift_reg #( 17 | parameter type dtype = logic, 18 | parameter int unsigned Depth = 1 19 | )( 20 | input logic clk_i, // Clock 21 | input logic rst_ni, // Asynchronous reset active low 22 | input dtype d_i, 23 | output dtype d_o 24 | ); 25 | 26 | shift_reg_gated #( 27 | .Depth(Depth), 28 | .dtype(dtype) 29 | ) i_shift_reg_gated ( 30 | .clk_i (clk_i), 31 | .rst_ni (rst_ni), 32 | .valid_i(1'b1), 33 | .data_i (d_i), 34 | .valid_o(), 35 | .data_o (d_o) 36 | ); 37 | 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /rtl/common_cells/shift_reg_gated.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Description: A Simple shift register with ICG for arbitrary depth and types. 12 | 13 | `include "common_cells/registers.svh" 14 | 15 | module shift_reg_gated #( 16 | parameter int unsigned Depth = 32'd8, 17 | parameter type dtype = logic 18 | ) ( 19 | input logic clk_i, // Clock 20 | input logic rst_ni, // Asynchronous reset active low 21 | 22 | input logic valid_i, 23 | input dtype data_i, 24 | output logic valid_o, 25 | output dtype data_o 26 | ); 27 | 28 | // Register of depth 0 is a wire. 29 | if (Depth == 0) begin : gen_pass_through 30 | 31 | assign valid_o = valid_i; 32 | assign data_o = data_i; 33 | 34 | // It's a shift register if depth is greater than 0 35 | end else begin : gen_shift_reg 36 | 37 | logic [Depth-1 : 0] valid_d, valid_q; 38 | dtype [Depth-1 : 0] data_d, data_q; 39 | 40 | for (genvar i = 0; i < Depth; i++) begin : gen_regs 41 | 42 | // Prepare D port for each shift register. 43 | if (i == 0) begin : gen_shift_in 44 | assign valid_d[i] = valid_i; 45 | assign data_d[i] = data_i; 46 | end else begin : gen_shift 47 | assign valid_d[i] = valid_q[i-1]; 48 | assign data_d[i] = data_q[i-1]; 49 | end 50 | 51 | // shift valid flag without clock gate 52 | `FF(valid_q[i], valid_d[i], '0, clk_i, rst_ni) 53 | 54 | // Gate each shift register with a valid flag to enable the synthsis tools to insert ICG for 55 | // better power comsumption. 56 | `FFL(data_q[i], data_d[i], valid_d[i], dtype'('0), clk_i, rst_ni) 57 | end 58 | 59 | // Output the shifted result. 60 | assign valid_o = valid_q[Depth-1]; 61 | assign data_o = data_q[Depth-1]; 62 | 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /rtl/common_cells/spill_register.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Fabian Schuiki 13 | 14 | 15 | /// Wrapper around the flushable spill register to maintain back-ward 16 | /// compatibility. 17 | module spill_register #( 18 | parameter type T = logic, 19 | parameter bit Bypass = 1'b0 // make this spill register transparent 20 | ) ( 21 | input logic clk_i , 22 | input logic rst_ni , 23 | input logic valid_i , 24 | output logic ready_o , 25 | input T data_i , 26 | output logic valid_o , 27 | input logic ready_i , 28 | output T data_o 29 | ); 30 | 31 | spill_register_flushable #( 32 | .T(T), 33 | .Bypass(Bypass) 34 | ) spill_register_flushable_i ( 35 | .clk_i, 36 | .rst_ni, 37 | .valid_i, 38 | .flush_i(1'b0), 39 | .ready_o, 40 | .data_i, 41 | .valid_o, 42 | .ready_i, 43 | .data_o 44 | ); 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_arbiter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready 12 | // handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is 13 | // asserted, `oup_data_o` remains invariant until the output handshake has occurred. The 14 | // arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. 15 | 16 | module stream_arbiter #( 17 | parameter type DATA_T = logic, // Vivado requires a default value for type parameters. 18 | parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. 19 | parameter ARBITER = "rr" // "rr" or "prio" 20 | ) ( 21 | input logic clk_i, 22 | input logic rst_ni, 23 | 24 | input DATA_T [N_INP-1:0] inp_data_i, 25 | input logic [N_INP-1:0] inp_valid_i, 26 | output logic [N_INP-1:0] inp_ready_o, 27 | 28 | output DATA_T oup_data_o, 29 | output logic oup_valid_o, 30 | input logic oup_ready_i 31 | ); 32 | 33 | stream_arbiter_flushable #( 34 | .DATA_T (DATA_T), 35 | .N_INP (N_INP), 36 | .ARBITER (ARBITER) 37 | ) i_arb ( 38 | .clk_i (clk_i), 39 | .rst_ni (rst_ni), 40 | .flush_i (1'b0), 41 | .inp_data_i (inp_data_i), 42 | .inp_valid_i (inp_valid_i), 43 | .inp_ready_o (inp_ready_o), 44 | .oup_data_o (oup_data_o), 45 | .oup_valid_o (oup_valid_o), 46 | .oup_ready_i (oup_ready_i) 47 | ); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_demux.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | /// Connects the input stream (valid-ready) handshake to one of `N_OUP` output stream handshakes. 12 | /// 13 | /// This module has no data ports because stream data does not need to be demultiplexed: the data of 14 | /// the input stream can just be applied at all output streams. 15 | module stream_demux #( 16 | /// Number of connected outputs. 17 | parameter int unsigned N_OUP = 32'd1, 18 | /// Dependent parameters, DO NOT OVERRIDE! 19 | parameter int unsigned LOG_N_OUP = (N_OUP > 32'd1) ? unsigned'($clog2(N_OUP)) : 1'b1 20 | ) ( 21 | input logic inp_valid_i, 22 | output logic inp_ready_o, 23 | 24 | input logic [LOG_N_OUP-1:0] oup_sel_i, 25 | 26 | output logic [N_OUP-1:0] oup_valid_o, 27 | input logic [N_OUP-1:0] oup_ready_i 28 | ); 29 | 30 | always_comb begin 31 | oup_valid_o = '0; 32 | oup_valid_o[oup_sel_i] = inp_valid_i; 33 | end 34 | assign inp_ready_o = oup_ready_i[oup_sel_i]; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_filter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Stream filter: If `drop_i` is `1`, signal `ready` to the upstream regardless of the downstream, 12 | // and do not propagate `valid` downstream. Otherwise, connect upstream to downstream. 13 | module stream_filter ( 14 | input logic valid_i, 15 | output logic ready_o, 16 | 17 | input logic drop_i, 18 | 19 | output logic valid_o, 20 | input logic ready_i 21 | ); 22 | 23 | assign valid_o = drop_i ? 1'b0 : valid_i; 24 | assign ready_o = drop_i ? 1'b1 : ready_i; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_intf.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | 12 | // Author: Florian Zaruba 13 | 14 | `include "common_cells/assertions.svh" 15 | 16 | /// A stream interface with custom payload of type `payload_t`. 17 | /// Handshaking rules as defined in the AXI standard. 18 | interface STREAM_DV #( 19 | /// Custom payload type. 20 | parameter type payload_t = logic 21 | )( 22 | /// Interface clock. 23 | input logic clk_i 24 | ); 25 | payload_t data; 26 | logic valid; 27 | logic ready; 28 | 29 | modport In ( 30 | output ready, 31 | input valid, data 32 | ); 33 | 34 | modport Out ( 35 | output valid, data, 36 | input ready 37 | ); 38 | 39 | /// Passive modport for scoreboard and monitors. 40 | modport Passive ( 41 | input valid, ready, data 42 | ); 43 | 44 | // Make sure that the handshake and payload is stable 45 | `ifndef COMMON_CELLS_ASSERTS_OFF 46 | `ASSERT(data_unstable, (valid && !ready |=> $stable(data)), clk_i, 1'b0) 47 | `ASSERT(valid_unstable, (valid && !ready |=> valid), clk_i, 1'b0) 48 | `endif 49 | endinterface 50 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_join.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Authors: 12 | // - Andreas Kurth 13 | 14 | /// Stream join: Joins a parametrizable number of input streams (i.e., valid-ready handshaking with 15 | /// dependency rules as in AXI4) to a single output stream. The output handshake happens only once 16 | /// all inputs are valid. The data channel flows outside of this module. 17 | module stream_join #( 18 | /// Number of input streams 19 | parameter int unsigned N_INP = 32'd0 // Synopsys DC requires a default value for parameters. 20 | ) ( 21 | /// Input streams valid handshakes 22 | input logic [N_INP-1:0] inp_valid_i, 23 | /// Input streams ready handshakes 24 | output logic [N_INP-1:0] inp_ready_o, 25 | /// Output stream valid handshake 26 | output logic oup_valid_o, 27 | /// Output stream ready handshake 28 | input logic oup_ready_i 29 | ); 30 | 31 | stream_join_dynamic #( 32 | .N_INP(N_INP) 33 | ) i_stream_join_dynamic ( 34 | .inp_valid_i(inp_valid_i), 35 | .inp_ready_o(inp_ready_o), 36 | .sel_i ({N_INP{1'b1}}), 37 | .oup_valid_o(oup_valid_o), 38 | .oup_ready_i(oup_ready_i) 39 | ); 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_join_dynamic.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Authors: 12 | // - Luca Colagrande 13 | 14 | `include "common_cells/assertions.svh" 15 | 16 | // Stream join dynamic: Joins a parametrizable number of input streams (i.e. valid-ready 17 | // handshaking with dependency rules as in AXI4) to a single output stream. The subset of streams 18 | // to join can be configured dynamically via `sel_i`. The output handshake happens only after 19 | // there has been a handshake. The data channel flows outside of this module. 20 | module stream_join_dynamic #( 21 | /// Number of input streams 22 | parameter int unsigned N_INP = 32'd0 // Synopsys DC requires a default value for parameters. 23 | ) ( 24 | /// Input streams valid handshakes 25 | input logic [N_INP-1:0] inp_valid_i, 26 | /// Input streams ready handshakes 27 | output logic [N_INP-1:0] inp_ready_o, 28 | /// Selection mask for the output handshake 29 | input logic [N_INP-1:0] sel_i, 30 | /// Output stream valid handshake 31 | output logic oup_valid_o, 32 | /// Output stream ready handshake 33 | input logic oup_ready_i 34 | ); 35 | 36 | // Corner case when `sel_i` is all 0s should not generate valid 37 | assign oup_valid_o = &(inp_valid_i | ~sel_i) && |sel_i; 38 | for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready 39 | assign inp_ready_o[i] = oup_valid_o & oup_ready_i & sel_i[i]; 40 | end 41 | 42 | `ifndef COMMON_CELLS_ASSERTS_OFF 43 | `ASSERT_INIT(n_inp_0, N_INP >= 1, "N_INP must be at least 1!") 44 | `endif 45 | endmodule 46 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_mux.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | `include "common_cells/assertions.svh" 12 | 13 | /// Stream multiplexer: connects the output to one of `N_INP` data streams with valid-ready 14 | /// handshaking. 15 | 16 | module stream_mux #( 17 | parameter type DATA_T = logic, // Vivado requires a default value for type parameters. 18 | parameter integer N_INP = 0, // Synopsys DC requires a default value for value parameters. 19 | /// Dependent parameters, DO NOT OVERRIDE! 20 | parameter integer LOG_N_INP = $clog2(N_INP) 21 | ) ( 22 | input DATA_T [N_INP-1:0] inp_data_i, 23 | input logic [N_INP-1:0] inp_valid_i, 24 | output logic [N_INP-1:0] inp_ready_o, 25 | 26 | input logic [LOG_N_INP-1:0] inp_sel_i, 27 | 28 | output DATA_T oup_data_o, 29 | output logic oup_valid_o, 30 | input logic oup_ready_i 31 | ); 32 | 33 | always_comb begin 34 | inp_ready_o = '0; 35 | inp_ready_o[inp_sel_i] = oup_ready_i; 36 | end 37 | assign oup_data_o = inp_data_i[inp_sel_i]; 38 | assign oup_valid_o = inp_valid_i[inp_sel_i]; 39 | 40 | `ifndef COMMON_CELLS_ASSERTS_OFF 41 | `ASSERT_INIT(n_inp_0, N_INP >= 1, "The number of inputs must be at least 1!") 42 | `endif 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /rtl/common_cells/stream_register.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2022 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | `include "common_cells/registers.svh" 12 | 13 | /// Register with a simple stream-like ready/valid handshake. 14 | /// This register does not cut combinatorial paths on all control signals; if you need a complete 15 | /// cut, use the `spill_register`. 16 | module stream_register #( 17 | parameter type T = logic // Vivado requires a default value for type parameters. 18 | ) ( 19 | input logic clk_i, // Clock 20 | input logic rst_ni, // Asynchronous active-low reset 21 | input logic clr_i, // Synchronous clear 22 | input logic testmode_i, // Test mode to bypass clock gating 23 | // Input port 24 | input logic valid_i, 25 | output logic ready_o, 26 | input T data_i, 27 | // Output port 28 | output logic valid_o, 29 | input logic ready_i, 30 | output T data_o 31 | ); 32 | 33 | logic reg_ena; 34 | assign ready_o = ready_i | ~valid_o; 35 | assign reg_ena = valid_i & ready_o; 36 | // Load-enable FFs with synch clear 37 | `FFLARNC(valid_o, valid_i, ready_o, clr_i, 1'b0 , clk_i, rst_ni) 38 | `FFLARNC(data_o, data_i, reg_ena, clr_i, T'('0), clk_i, rst_ni) 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/common_cells/sync.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module sync #( 14 | parameter int unsigned STAGES = 2, 15 | parameter bit ResetValue = 1'b0 16 | ) ( 17 | input logic clk_i, 18 | input logic rst_ni, 19 | input logic serial_i, 20 | output logic serial_o 21 | ); 22 | 23 | (* dont_touch = "true" *) 24 | (* async_reg = "true" *) 25 | logic [STAGES-1:0] reg_q; 26 | 27 | always_ff @(posedge clk_i, negedge rst_ni) begin 28 | if (!rst_ni) begin 29 | reg_q <= {STAGES{ResetValue}}; 30 | end else begin 31 | reg_q <= {reg_q[STAGES-2:0], serial_i}; 32 | end 33 | end 34 | 35 | assign serial_o = reg_q[STAGES-1]; 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rtl/common_cells/sync_wedge.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Antonio Pullini 12 | 13 | module sync_wedge #( 14 | parameter int unsigned STAGES = 2 15 | ) ( 16 | input logic clk_i, 17 | input logic rst_ni, 18 | input logic en_i, 19 | input logic serial_i, 20 | output logic r_edge_o, 21 | output logic f_edge_o, 22 | output logic serial_o 23 | ); 24 | logic clk; 25 | logic serial, serial_q; 26 | 27 | assign serial_o = serial_q; 28 | assign f_edge_o = (~serial) & serial_q; 29 | assign r_edge_o = serial & (~serial_q); 30 | 31 | sync #( 32 | .STAGES (STAGES) 33 | ) i_sync ( 34 | .clk_i, 35 | .rst_ni, 36 | .serial_i, 37 | .serial_o ( serial ) 38 | ); 39 | 40 | pulp_clock_gating i_pulp_clock_gating ( 41 | .clk_i, 42 | .en_i, 43 | .test_en_i ( 1'b0 ), 44 | .clk_o ( clk ) 45 | ); 46 | 47 | always_ff @(posedge clk, negedge rst_ni) begin 48 | if (!rst_ni) begin 49 | serial_q <= 1'b0; 50 | end else begin 51 | if (en_i) begin 52 | serial_q <= serial; 53 | end 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /rtl/common_cells/unread.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Florian Zaruba, ETH Zurich 12 | // Date: 29.10.2018 13 | // Description: Dummy circuit to mitigate Open Pin warnings 14 | 15 | /* verilator lint_off UNUSED */ 16 | module unread ( 17 | input logic d_i 18 | ); 19 | // Vivado treats this module as black box otherwise 20 | `ifdef TARGET_VIVADO 21 | logic x; 22 | assign d_i = x; 23 | `endif 24 | endmodule 25 | /* verilator lint_on UNUSED */ 26 | -------------------------------------------------------------------------------- /rtl/common_verification/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: common_verification 3 | authors: 4 | - "Andreas Kurth " 5 | 6 | sources: 7 | # Files in this package are meant for simulation only. 8 | # Verilator does not support features commonly used in simulation (eg: rand conditioning) 9 | - target: any(simulation, verilator) 10 | files: 11 | - clk_rst_gen.sv 12 | -------------------------------------------------------------------------------- /rtl/common_verification/clk_rst_gen.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Clock and Reset Generator 12 | module clk_rst_gen #( 13 | parameter time ClkPeriod = 0ps, // minimum: 2ps 14 | parameter int unsigned RstClkCycles = 0 15 | ) ( 16 | output logic clk_o, 17 | output logic rst_no 18 | ); 19 | 20 | logic clk; 21 | 22 | // Clock Generation 23 | initial begin 24 | clk = 1'b0; 25 | end 26 | always begin 27 | // Emit rising clock edge. 28 | clk = 1'b1; 29 | // Wait for at most half the clock period before emitting falling clock edge. Due to integer 30 | // division, this is not always exactly half the clock period but as close as we can get. 31 | #(ClkPeriod / 2); 32 | // Emit falling clock edge. 33 | clk = 1'b0; 34 | // Wait for remainder of clock period before continuing with next cycle. 35 | #((ClkPeriod + 1) / 2); 36 | end 37 | assign clk_o = clk; 38 | 39 | // Reset Generation 40 | initial begin 41 | static int unsigned rst_cnt = 0; 42 | rst_no = 1'b0; 43 | #(ClkPeriod / 2); // Start counting clock cycles on first complete cycle. 44 | while (rst_cnt < RstClkCycles) begin 45 | @(posedge clk); 46 | rst_cnt++; 47 | end 48 | rst_no = 1'b1; 49 | end 50 | 51 | // Validate parameters. 52 | `ifndef VERILATOR 53 | initial begin: validate_params 54 | assert (ClkPeriod >= 2ps) 55 | else $fatal(1, "The clock period must be at least 2ps!"); 56 | // Reason: Gets divided by two, and some simulators do not support non-integer time steps, so 57 | // if the time unit is 1ps, this would fail. 58 | assert (RstClkCycles > 0) 59 | else $fatal(1, "The number of clock cycles in reset must be greater than 0!"); 60 | end 61 | `endif 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /rtl/cve2/Bender.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | package: 6 | name: cve2 7 | 8 | sources: 9 | - include_dirs: 10 | - include 11 | files: 12 | # Source files grouped in levels. Files in level 0 have no dependencies on files in this 13 | # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 14 | # levels 1 and 0, etc. Files within a level are ordered alphabetically. 15 | # Level 0 16 | - cve2_pkg.sv 17 | # Level 1 18 | - cve2_alu.sv 19 | - cve2_compressed_decoder.sv 20 | - cve2_controller.sv 21 | - cve2_counter.sv 22 | - cve2_csr.sv 23 | - cve2_decoder.sv 24 | - cve2_fetch_fifo.sv 25 | - cve2_load_store_unit.sv 26 | - cve2_multdiv_fast.sv 27 | - cve2_multdiv_slow.sv 28 | - cve2_pmp.sv 29 | - cve2_register_file_ff.sv 30 | - cve2_wb.sv 31 | # Level 2 32 | - cve2_cs_registers.sv 33 | - cve2_ex_block.sv 34 | - cve2_id_stage.sv 35 | - cve2_prefetch_buffer.sv 36 | # Level 3 37 | - cve2_if_stage.sv 38 | # Level 4 39 | - cve2_core.sv 40 | 41 | # In case we target RTL simulation, recompile the whole core with the RISC-V 42 | # formal interface so the tracer module works (`define RVFI). 43 | - target: all(any(test, cve2_include_tracer), not(cve2_exclude_tracer)) 44 | include_dirs: 45 | - include 46 | defines: 47 | RVFI: true 48 | files: 49 | - cve2_tracer_pkg.sv 50 | - cve2_tracer.sv 51 | - cve2_core_tracing.sv 52 | -------------------------------------------------------------------------------- /rtl/cve2/cve2_csr.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | /** 6 | * Control / status register primitive 7 | */ 8 | 9 | `include "lowrisc_prim/prim_assert.svh" 10 | 11 | module cve2_csr #( 12 | parameter int unsigned Width = 32, 13 | parameter bit ShadowCopy = 1'b0, 14 | parameter bit [Width-1:0] ResetValue = '0 15 | ) ( 16 | input logic clk_i, 17 | input logic rst_ni, 18 | 19 | input logic [Width-1:0] wr_data_i, 20 | input logic wr_en_i, 21 | output logic [Width-1:0] rd_data_o, 22 | 23 | output logic rd_error_o 24 | ); 25 | 26 | logic [Width-1:0] rdata_q; 27 | 28 | always_ff @(posedge clk_i or negedge rst_ni) begin 29 | if (!rst_ni) begin 30 | rdata_q <= ResetValue; 31 | end else if (wr_en_i) begin 32 | rdata_q <= wr_data_i; 33 | end 34 | end 35 | 36 | assign rd_data_o = rdata_q; 37 | 38 | if (ShadowCopy) begin : gen_shadow 39 | logic [Width-1:0] shadow_q; 40 | 41 | always_ff @(posedge clk_i or negedge rst_ni) begin 42 | if (!rst_ni) begin 43 | shadow_q <= ~ResetValue; 44 | end else if (wr_en_i) begin 45 | shadow_q <= ~wr_data_i; 46 | end 47 | end 48 | 49 | assign rd_error_o = rdata_q != ~shadow_q; 50 | 51 | end else begin : gen_no_shadow 52 | assign rd_error_o = 1'b0; 53 | end 54 | 55 | `ASSERT_KNOWN(IbexCSREnValid, wr_en_i) 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /rtl/cve2/include/lowrisc_prim/prim_assert_dummy_macros.svh: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Macro bodies included by prim_assert.sv for tools that don't support assertions. See 6 | // prim_assert.sv for documentation for each of the macros. 7 | 8 | `define ASSERT_I(__name, __prop) 9 | `define ASSERT_INIT(__name, __prop) 10 | `define ASSERT_INIT_NET(__name, __prop) 11 | `define ASSERT_FINAL(__name, __prop) 12 | `define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) 13 | `define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) 14 | `define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) 15 | `define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) 16 | `define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) 17 | `define ASSUME_I(__name, __prop) 18 | -------------------------------------------------------------------------------- /rtl/cve2/include/lowrisc_prim/prim_assert_sec_cm.svh: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // // Macros and helper code for security countermeasures. 6 | 7 | `ifndef PRIM_ASSERT_SEC_CM_SVH 8 | `define PRIM_ASSERT_SEC_CM_SVH 9 | 10 | // Helper macros 11 | `define ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_, ERR_NAME_) \ 12 | `ASSERT(FpvSecCm``NAME_``, $rose(PRIM_HIER_.ERR_NAME_) |-> ##[0:MAX_CYCLES_] (ALERT_.alert_p)) \ 13 | `ifdef INC_ASSERT \ 14 | assign PRIM_HIER_.unused_assert_connected = 1'b1; \ 15 | `endif \ 16 | `ASSUME_FPV(``NAME_``TriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> \ 17 | PRIM_HIER_.ERR_NAME_ == 0 [*10]) 18 | 19 | // macros for security countermeasures 20 | `define ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_ = 7) \ 21 | `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_, err_o) 22 | 23 | `define ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_ = 7) \ 24 | `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_, err_o) 25 | 26 | `define ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_ = 7) \ 27 | `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, MAX_CYCLES_, unused_err_o) 28 | 29 | `endif // PRIM_ASSERT_SEC_CM_SVH 30 | -------------------------------------------------------------------------------- /rtl/cve2/include/lowrisc_prim/prim_assert_yosys_macros.svh: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // Macro bodies included by prim_assert.sv for formal verification with Yosys. See prim_assert.sv 6 | // for documentation for each of the macros. 7 | 8 | `define ASSERT_I(__name, __prop) \ 9 | always_comb begin : __name \ 10 | assert (__prop); \ 11 | end 12 | 13 | `define ASSERT_INIT(__name, __prop) \ 14 | initial begin : __name \ 15 | assert (__prop); \ 16 | end 17 | 18 | `define ASSERT_INIT_NET(__name, __prop) \ 19 | initial begin : __name \ 20 | #1ps assert (__prop); \ 21 | end 22 | 23 | // This doesn't make much sense for a formal tool (we never get to the final block!) 24 | `define ASSERT_FINAL(__name, __prop) 25 | 26 | `define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ 27 | always_ff @(posedge __clk) begin \ 28 | if (! (__rst !== '0)) __name: assert (__prop); \ 29 | end 30 | 31 | `define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ 32 | always_ff @(posedge __clk) begin \ 33 | if (! (__rst !== '0)) __name: assert (! (__prop)); \ 34 | end 35 | 36 | // Yosys uses 2-state logic, so this doesn't make sense here 37 | `define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) 38 | 39 | `define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ 40 | always_ff @(posedge __clk) begin : __name \ 41 | cover ((! (__rst !== '0)) && (__prop)); \ 42 | end 43 | 44 | `define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ 45 | always_ff @(posedge __clk) begin \ 46 | if (! (__rst !== '0)) __name: assume (__prop); \ 47 | end 48 | 49 | `define ASSUME_I(__name, __prop) \ 50 | always_comb begin : __name \ 51 | assume (__prop); \ 52 | end 53 | -------------------------------------------------------------------------------- /rtl/gpio/Bender.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | package: 6 | name: gpio 7 | authors: 8 | - "Hannah Pochert " 9 | - "Luisa Wüthrich " 10 | - "Philippe Sauter " 11 | 12 | dependencies: 13 | common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 } 14 | common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } 15 | 16 | sources: 17 | # Level 0 18 | - gpio_reg_pkg.sv 19 | # Level 1 20 | - gpio_reg_top.sv 21 | # Level 2 22 | - gpio.sv 23 | -------------------------------------------------------------------------------- /rtl/gpio/README.md: -------------------------------------------------------------------------------- 1 | # GPIO Peripheral 2 | 3 | The GPIO can be configured to use anywhere between 1 and 32 GPIO lines. A common interrupt line is exposed, the interrupt cause can be seen in the interrupt status register which is cleared on read. 4 | 5 | For every GPIO there is one bit (starting at the LSB and filling towards MSB) in the following registers. 6 | 7 | ## Registers 8 | 9 | | Register Name | Offset | Access | Description | 10 | |----------------------|---------|--------|-----------------------------------------------------------| 11 | | `GPIO_DIR` | `0x000` | R/W | Direction register (0: input, 1: output) | 12 | | `GPIO_EN` | `0x080` | R/W | Enable register (0: disable updates, 1: enabled) | 13 | | `GPIO_IN` | `0x100` | R | Input value register | 14 | | `GPIO_OUT` | `0x180` | R/W | Output value register | 15 | | `GPIO_TOGGLE` | `0x200` | W | Toggle output value | 16 | | `GPIO_INTRPT_EN` | `0x280` | R/W | Enable interrupts register | 17 | | `GPIO_INTRPT_STATUS` | `0x300` | R | Interrupt status register (1: interrupt occured) | 18 | | `GPIO_INTRPT_EDGE` | `0x380` | R/W | Interrupt edge register (0: falling edge, 1: rising edge) | 19 | 20 | All registers are initialized to `0x00` after a reset. -------------------------------------------------------------------------------- /rtl/obi/Bender.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2023 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | package: 6 | name: obi 7 | authors: 8 | - "Michael Rogenmoser " 9 | 10 | dependencies: 11 | common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 } 12 | common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } 13 | 14 | export_include_dirs: 15 | - include 16 | 17 | sources: 18 | # Level 1 19 | - obi_pkg.sv 20 | # Level 2 21 | - obi_intf.sv 22 | - obi_rready_converter.sv 23 | # Level 3 24 | - obi_atop_resolver.sv 25 | - obi_cut.sv 26 | - obi_demux.sv 27 | - obi_err_sbr.sv 28 | - obi_mux.sv 29 | - obi_sram_shim.sv 30 | # Level 4 31 | - obi_xbar.sv 32 | -------------------------------------------------------------------------------- /rtl/obi/Readme.md: -------------------------------------------------------------------------------- 1 | # OBI 2 | 3 | The repository contains a collection of SystemVerilog IPs for the [OBI v1.6 standard](https://github.com/openhwgroup/obi/blob/072d9173c1f2d79471d6f2a10eae59ee387d4c6f/OBI-v1.6.0.pdf). 4 | 5 | They are designed by PULP-platform and are available under the Solderpad v0.51 license (See [`LICENSE`](LICENSE)). 6 | 7 | ## Using the IPs 8 | As the OBI protocol is very configurable, the IPs are designed to incorporate specific parameters for the design: 9 | 10 | - `ObiCfg`: This specifies the configuration used for the OBI protocol being input or output from the link. A default config can be found in the `obi_pkg.sv`. This config should be aligned with the `req` and `rsp` structs. 11 | - `obi_req_t`: The OBI request struct is designed to be generated with a macro available in the `include/obi/typedef.svh` include file and has fields for the handshake and a field for the *A* channel. 12 | - `obi_rsp_t`: The OBI response struct is designed to be generated with a macro available in the `include/obi/typedef.svh` include file and has fields for the handshake and a filed for the *R* channel. 13 | 14 | Most IPs will also support a SystemVerilog `interface` variant, also based on `ObiCfg`. 15 | 16 | ## Available IPs 17 | - `obi_mux.sv`: A multiplexer IP for the OBI protocol. 18 | - `obi_demux.sv`: A demultiplexer IP for the OBI protocol. 19 | - `obi_xbar.sv`: A crossbar interconnect IP for the OBI protocol. 20 | - `obi_err_sbr.sv`: A error subordinate, responding with the error bit set. 21 | - `obi_sram_shim.sv`: An adapter for a standard sram. 22 | - `obi_atop_resolver.sv`: An atomics filter, resolving atomic operations on an exclusive bus. 23 | 24 | ## License 25 | Solderpad Hardware License, Version 0.51 26 | -------------------------------------------------------------------------------- /rtl/obi/obi_cut.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2023 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | 5 | // Michael Rogenmoser 6 | 7 | module obi_cut #( 8 | /// The OBI configuration. 9 | parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig, 10 | /// The obi A channel struct. 11 | parameter type obi_a_chan_t = logic, 12 | /// The obi R channel struct. 13 | parameter type obi_r_chan_t = logic, 14 | /// The request struct. 15 | parameter type obi_req_t = logic, 16 | /// The response struct. 17 | parameter type obi_rsp_t = logic, 18 | /// Bypass enable, can be individually overridden! 19 | parameter bit Bypass = 1'b0, 20 | /// Bypass enable for Request side. 21 | parameter bit BypassReq = Bypass, 22 | /// Bypass enable for Response side. 23 | parameter bit BypassRsp = Bypass 24 | ) ( 25 | input logic clk_i, 26 | input logic rst_ni, 27 | 28 | input obi_req_t sbr_port_req_i, 29 | output obi_rsp_t sbr_port_rsp_o, 30 | 31 | output obi_req_t mgr_port_req_o, 32 | input obi_rsp_t mgr_port_rsp_i 33 | ); 34 | 35 | spill_register #( 36 | .T ( obi_a_chan_t ), 37 | .Bypass ( BypassReq ) 38 | ) i_reg_a ( 39 | .clk_i, 40 | .rst_ni, 41 | .valid_i ( sbr_port_req_i.req ), 42 | .ready_o ( sbr_port_rsp_o.gnt ), 43 | .data_i ( sbr_port_req_i.a ), 44 | .valid_o ( mgr_port_req_o.req ), 45 | .ready_i ( mgr_port_rsp_i.gnt ), 46 | .data_o ( mgr_port_req_o.a ) 47 | ); 48 | 49 | logic ready_o; 50 | logic ready_i; 51 | 52 | if (ObiCfg.UseRReady) begin : gen_use_rready 53 | assign mgr_port_req_o.rready = ready_o; 54 | assign ready_i = sbr_port_req_i.rready; 55 | end else begin : gen_no_use_rready 56 | assign ready_i = 1'b1; 57 | end 58 | 59 | spill_register #( 60 | .T ( obi_r_chan_t ), 61 | .Bypass ( BypassRsp ) 62 | ) i_req_r ( 63 | .clk_i, 64 | .rst_ni, 65 | .valid_i ( mgr_port_rsp_i.rvalid ), 66 | .ready_o ( ready_o ), 67 | .data_i ( mgr_port_rsp_i.r ), 68 | .valid_o ( sbr_port_rsp_o.rvalid ), 69 | .ready_i ( ready_i ), 70 | .data_o ( sbr_port_rsp_o.r ) 71 | ); 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /rtl/obi/obi_rready_converter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | 5 | // Author: Georg Rutishauser 6 | 7 | module obi_rready_converter #( 8 | parameter type obi_a_chan_t = logic, 9 | parameter type obi_r_chan_t = logic, 10 | parameter int unsigned Depth = 1, 11 | parameter bit CombRspReq = 1'b1 12 | ) ( 13 | input logic clk_i, 14 | input logic rst_ni, 15 | input logic test_mode_i, 16 | 17 | input obi_a_chan_t sbr_a_chan_i, 18 | input logic req_i, 19 | output logic gnt_o, 20 | output obi_r_chan_t sbr_r_chan_o, 21 | output logic rvalid_o, 22 | input logic rready_i, 23 | 24 | output obi_a_chan_t mgr_a_chan_o, 25 | output logic req_o, 26 | input logic gnt_i, 27 | input obi_r_chan_t mgr_r_chan_i, 28 | input logic rvalid_i 29 | ); 30 | 31 | logic fifo_ready, credit_left; 32 | stream_fifo #( 33 | .FALL_THROUGH ( 1'b1 ), 34 | .DEPTH ( Depth ), 35 | .T ( obi_r_chan_t ) 36 | ) response_fifo_i ( 37 | .clk_i, 38 | .rst_ni, 39 | .flush_i ( 1'b0 ), 40 | .testmode_i ( test_mode_i ), 41 | .usage_o (), 42 | .data_i ( mgr_r_chan_i ), 43 | .valid_i ( rvalid_i ), 44 | .ready_o ( fifo_ready ), 45 | .data_o ( sbr_r_chan_o ), 46 | .valid_o ( rvalid_o ), 47 | .ready_i ( rready_i ) 48 | ); 49 | 50 | credit_counter #( 51 | .NumCredits ( Depth ), 52 | .InitCreditEmpty ( 1'b0 ) 53 | ) credit_cntr_i ( 54 | .clk_i, 55 | .rst_ni, 56 | .credit_o (), 57 | .credit_give_i ( rvalid_o & rready_i ), 58 | .credit_take_i ( req_o & gnt_i ), 59 | .credit_init_i ( 1'b0 ), 60 | .credit_left_o ( credit_left ), 61 | .credit_crit_o (), 62 | .credit_full_o () 63 | ); 64 | 65 | // only transmit requests if we have credits left or free a space in the FIFO 66 | assign req_o = req_i & (credit_left | (CombRspReq & rready_i & rvalid_o)); 67 | // only grant requests if we have credits left or free a space in the FIFO 68 | assign gnt_o = gnt_i & (credit_left | (CombRspReq & rready_i & rvalid_o)); 69 | 70 | assign mgr_a_chan_o = sbr_a_chan_i; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /rtl/patches/apb/0001-adjust-Bender-source-paths.patch: -------------------------------------------------------------------------------- 1 | From ae01bcbabee08187a13963f9c760b0e009a60b3b Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 12:12:10 +0200 4 | Subject: [PATCH] adjust Bender source paths 5 | 6 | --- 7 | Bender.yml | 24 +----------------------- 8 | 1 file changed, 1 insertion(+), 23 deletions(-) 9 | 10 | diff --git a/Bender.yml b/Bender.yml 11 | index f73f9a6..1320858 100644 12 | --- a/Bender.yml 13 | +++ b/Bender.yml 14 | @@ -16,26 +16,4 @@ sources: 15 | # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 16 | # levels 1 and 0, etc. Files within a level are ordered alphabetically. 17 | # Level 0 18 | - - src/apb_pkg.sv 19 | - # Level 1 20 | - - src/apb_intf.sv 21 | - # Level 2 22 | - - src/apb_err_slv.sv 23 | - - src/apb_regs.sv 24 | - - src/apb_cdc.sv 25 | - - src/apb_demux.sv 26 | - 27 | - - target: simulation 28 | - files: 29 | - - src/apb_test.sv 30 | - 31 | - - target: test 32 | - files: 33 | - - test/tb_apb_regs.sv 34 | - - test/tb_apb_cdc.sv 35 | - - test/tb_apb_demux.sv 36 | - 37 | - - target: synth_test 38 | - files: 39 | - # Level 0 40 | - - test/synth_bench.sv 41 | + - apb_pkg.sv 42 | \ No newline at end of file 43 | -- 44 | 2.25.1 45 | 46 | -------------------------------------------------------------------------------- /rtl/patches/apb_uart/0001-adjust-Bender-source-paths.patch: -------------------------------------------------------------------------------- 1 | From f753ef201beb917408327d3cafc28b6228af3fb1 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 11:56:27 +0200 4 | Subject: [PATCH] adjust Bender source paths 5 | 6 | --- 7 | Bender.yml | 28 ++++++++++++++-------------- 8 | 1 file changed, 14 insertions(+), 14 deletions(-) 9 | 10 | diff --git a/Bender.yml b/Bender.yml 11 | index 40ec53d..60d59b6 100644 12 | --- a/Bender.yml 13 | +++ b/Bender.yml 14 | @@ -10,17 +10,17 @@ dependencies: 15 | register_interface: { git: "https://github.com/pulp-platform/register_interface", version: 0.3.6 } 16 | 17 | sources: 18 | - - src/slib_clock_div.sv 19 | - - src/slib_counter.sv 20 | - - src/slib_edge_detect.sv 21 | - - src/slib_fifo.sv 22 | - - src/slib_input_filter.sv 23 | - - src/slib_input_sync.sv 24 | - - src/slib_mv_filter.sv 25 | - - src/uart_baudgen.sv 26 | - - src/uart_interrupt.sv 27 | - - src/uart_receiver.sv 28 | - - src/uart_transmitter.sv 29 | - - src/apb_uart.sv 30 | - - src/apb_uart_wrap.sv 31 | - - src/reg_uart_wrap.sv 32 | + - slib_clock_div.sv 33 | + - slib_counter.sv 34 | + - slib_edge_detect.sv 35 | + - slib_fifo.sv 36 | + - slib_input_filter.sv 37 | + - slib_input_sync.sv 38 | + - slib_mv_filter.sv 39 | + - uart_baudgen.sv 40 | + - uart_interrupt.sv 41 | + - uart_receiver.sv 42 | + - uart_transmitter.sv 43 | + - apb_uart.sv 44 | + - apb_uart_wrap.sv 45 | + - reg_uart_wrap.sv 46 | -- 47 | 2.25.1 48 | 49 | -------------------------------------------------------------------------------- /rtl/patches/apb_uart/src/0001-Add-missing-parameter-keyword.patch: -------------------------------------------------------------------------------- 1 | From 342fbd22d648915c80fff8551aa72e470139572b Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 11:54:22 +0200 4 | Subject: [PATCH] Add missing parameter keyword 5 | 6 | --- 7 | slib_mv_filter.sv | 2 +- 8 | 1 file changed, 1 insertion(+), 1 deletion(-) 9 | 10 | diff --git a/slib_mv_filter.sv b/slib_mv_filter.sv 11 | index d5b50a9..363b89e 100644 12 | --- a/slib_mv_filter.sv 13 | +++ b/slib_mv_filter.sv 14 | @@ -32,7 +32,7 @@ 15 | // Boston, MA 02111-1307 USA 16 | // 17 | 18 | -module slib_mv_filter #(parameter WIDTH = 4, THRESHOLD = 10) ( 19 | +module slib_mv_filter #(parameter WIDTH = 4, parameter THRESHOLD = 10) ( 20 | input wire CLK, 21 | input wire RST, 22 | input wire SAMPLE, 23 | -- 24 | 2.25.1 25 | 26 | -------------------------------------------------------------------------------- /rtl/patches/common_verification/0001-adjust-Bender-source-paths.patch: -------------------------------------------------------------------------------- 1 | From 79d33cf53d9086c3324ebf8b2ca0a0995d1fd064 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 12:13:15 +0200 4 | Subject: [PATCH] adjust Bender source paths 5 | 6 | --- 7 | Bender.yml | 24 +----------------------- 8 | 1 file changed, 1 insertion(+), 23 deletions(-) 9 | 10 | diff --git a/Bender.yml b/Bender.yml 11 | index c209e9b..17cfeaa 100644 12 | --- a/Bender.yml 13 | +++ b/Bender.yml 14 | @@ -8,26 +8,4 @@ sources: 15 | # Verilator does not support features commonly used in simulation (eg: rand conditioning) 16 | - target: any(simulation, verilator) 17 | files: 18 | - - src/clk_rst_gen.sv 19 | - - src/sim_timeout.sv 20 | - - src/stream_watchdog.sv 21 | - - src/signal_highlighter.sv 22 | - 23 | - - target: simulation 24 | - files: 25 | - # Source files grouped in levels. Files in level 0 have no dependencies on files in this 26 | - # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 27 | - # levels 1 and 0, etc. Files within a level are ordered alphabetically. 28 | - # Level 0 29 | - - src/rand_id_queue.sv 30 | - - src/rand_stream_mst.sv 31 | - - src/rand_synch_holdable_driver.sv 32 | - - src/rand_verif_pkg.sv 33 | - # Level 1 34 | - - src/rand_synch_driver.sv 35 | - # Level 2 36 | - - src/rand_stream_slv.sv 37 | - 38 | - - target: test 39 | - files: 40 | - - test/tb_clk_rst_gen.sv 41 | + - clk_rst_gen.sv 42 | -- 43 | 2.25.1 44 | 45 | -------------------------------------------------------------------------------- /rtl/patches/cve2/0001-adjust-blockdiagram-path.patch: -------------------------------------------------------------------------------- 1 | From b29bab50d89f40c5523d99012396d8c0e7433896 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Tue, 19 Nov 2024 14:43:00 +0100 4 | Subject: [PATCH] adjust-blockdiagram-path 5 | 6 | --- 7 | README.md | 2 +- 8 | 1 file changed, 1 insertion(+), 1 deletion(-) 9 | 10 | diff --git a/README.md b/README.md 11 | index 23d220fa..d750c868 100644 12 | --- a/README.md 13 | +++ b/README.md 14 | @@ -16,7 +16,7 @@ Integer Multiplication and Division (M), and Compressed (C) extensions. 15 | The block diagram below shows the *small* parametrization with a 2-stage 16 | pipeline. 17 | 18 | -

19 | +

20 | 21 | CV32E20 was initially developed as part of the [PULP platform](https://www.pulp-platform.org) 22 | under the name ["Zero-riscy"](https://doi.org/10.1109/PATMOS.2017.8106976), and has been 23 | -- 24 | 2.34.1 25 | 26 | -------------------------------------------------------------------------------- /rtl/patches/cve2/lowrisc_prim/0002-adjust-include-paths.patch: -------------------------------------------------------------------------------- 1 | From 202695875dfe4b061bb9e327b943d3b8b7aff9f6 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Tue, 19 Nov 2024 16:17:33 +0100 4 | Subject: [PATCH] adjust include paths 5 | 6 | --- 7 | prim_assert.sv => prim_assert.svh | 10 +++++----- 8 | 1 file changed, 5 insertions(+), 5 deletions(-) 9 | rename vendor/lowrisc_ip/ip/prim/rtl/{prim_assert.sv => prim_assert.svh} (95%) 10 | 11 | diff --git a/prim_assert.sv b/prim_assert.svh 12 | similarity index 95% 13 | rename from prim_assert.sv 14 | rename to prim_assert.svh 15 | index a5b17a82..e8162497 100644 16 | --- a/prim_assert.sv 17 | +++ b/prim_assert.svh 18 | @@ -82,14 +82,14 @@ 19 | // ASSUME_I: Assume an immediate property 20 | 21 | `ifdef VERILATOR 22 | - `include "prim_assert_dummy_macros.svh" 23 | + `include "lowrisc_prim/prim_assert_dummy_macros.svh" 24 | `elsif SYNTHESIS 25 | - `include "prim_assert_dummy_macros.svh" 26 | + `include "lowrisc_prim/prim_assert_dummy_macros.svh" 27 | `elsif YOSYS 28 | - `include "prim_assert_yosys_macros.svh" 29 | + `include "lowrisc_prim/prim_assert_yosys_macros.svh" 30 | `define INC_ASSERT 31 | `else 32 | - `include "prim_assert_standard_macros.svh" 33 | + `include "lowrisc_prim/prim_assert_standard_macros.svh" 34 | `define INC_ASSERT 35 | `endif 36 | 37 | @@ -140,6 +140,6 @@ 38 | `COVER(__name, __prop, __clk, __rst) \ 39 | `endif 40 | 41 | -`include "prim_assert_sec_cm.svh" 42 | +`include "lowrisc_prim/prim_assert_sec_cm.svh" 43 | 44 | `endif // PRIM_ASSERT_SV 45 | -- 46 | 2.34.1 47 | 48 | -------------------------------------------------------------------------------- /rtl/patches/cve2/rtl/0004-remove-dv_fcov_macros-include.patch: -------------------------------------------------------------------------------- 1 | From eb65e8c2a363aca5ba25b0e429e95d9bae57e391 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Tue, 19 Nov 2024 15:42:09 +0100 4 | Subject: [PATCH] remove dv_fcov_macros include 5 | 6 | --- 7 | cve2_controller.sv | 1 - 8 | cve2_id_stage.sv | 1 - 9 | cve2_load_store_unit.sv | 1 - 10 | 3 files changed, 3 deletions(-) 11 | 12 | diff --git a/cve2_controller.sv b/cve2_controller.sv 13 | index 31245510..46b6ffdb 100644 14 | --- a/cve2_controller.sv 15 | +++ b/cve2_controller.sv 16 | @@ -8,7 +8,6 @@ 17 | */ 18 | 19 | `include "lowrisc_prim/prim_assert.svh" 20 | -`include "dv_fcov_macros.svh" 21 | 22 | module cve2_controller #( 23 | ) ( 24 | diff --git a/cve2_id_stage.sv b/cve2_id_stage.sv 25 | index b57188b2..a6c696c4 100644 26 | --- a/cve2_id_stage.sv 27 | +++ b/cve2_id_stage.sv 28 | @@ -15,7 +15,6 @@ 29 | */ 30 | 31 | `include "lowrisc_prim/prim_assert.svh" 32 | -`include "dv_fcov_macros.svh" 33 | 34 | module cve2_id_stage #( 35 | parameter bit RV32E = 0, 36 | diff --git a/cve2_load_store_unit.sv b/cve2_load_store_unit.sv 37 | index 08775649..6d0b4d91 100644 38 | --- a/cve2_load_store_unit.sv 39 | +++ b/cve2_load_store_unit.sv 40 | @@ -12,7 +12,6 @@ 41 | */ 42 | 43 | `include "lowrisc_prim/prim_assert.svh" 44 | -`include "dv_fcov_macros.svh" 45 | 46 | module cve2_load_store_unit 47 | ( 48 | -- 49 | 2.34.1 50 | 51 | -------------------------------------------------------------------------------- /rtl/patches/cve2/rtl/0005-remove-dv_fcov_macros-include.patch: -------------------------------------------------------------------------------- 1 | From 448095a86e776095dcdfeaad72e71a0b45e1caa4 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Tue, 19 Nov 2024 15:43:06 +0100 4 | Subject: [PATCH] remove dv_fcov_macros include 5 | 6 | --- 7 | cve2_wb.sv | 1 - 8 | 1 file changed, 1 deletion(-) 9 | 10 | diff --git a/cve2_wb.sv b/cve2_wb.sv 11 | index ab9970a6..987532b7 100644 12 | --- a/cve2_wb.sv 13 | +++ b/cve2_wb.sv 14 | @@ -10,7 +10,6 @@ 15 | */ 16 | 17 | `include "lowrisc_prim/prim_assert.svh" 18 | -`include "dv_fcov_macros.svh" 19 | 20 | module cve2_wb #( 21 | ) ( 22 | -- 23 | 2.34.1 24 | 25 | -------------------------------------------------------------------------------- /rtl/patches/cve2/rtl/0006-add-multdiv-unused-signal-tieoff.patch: -------------------------------------------------------------------------------- 1 | From c5eae6a070aa63946cc004856d9ca49daf98382f Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Mon, 25 Nov 2024 18:16:21 +0100 4 | Subject: [PATCH] add multdiv unused signal tieoff 5 | 6 | --- 7 | cve2_ex_block.sv | 5 +++++ 8 | 1 file changed, 5 insertions(+) 9 | 10 | diff --git a/cve2_ex_block.sv b/cve2_ex_block.sv 11 | index 98713a3d..e51c5ee4 100644 12 | --- a/cve2_ex_block.sv 13 | +++ b/cve2_ex_block.sv 14 | @@ -165,6 +165,11 @@ module cve2_ex_block #( 15 | .valid_o (multdiv_valid), 16 | .multdiv_result_o (multdiv_result) 17 | ); 18 | + end else begin 19 | + assign multdiv_alu_operand_a = '0; 20 | + assign multdiv_alu_operand_b = '0; 21 | + assign multdiv_result = '0; 22 | + assign multdiv_valid = '0; 23 | end 24 | 25 | // Multiplier/divider may require multiple cycles. The ALU output is valid in the same cycle 26 | -- 27 | 2.39.3 28 | 29 | -------------------------------------------------------------------------------- /rtl/patches/cve2/rtl/0007-add-bender-package-manifest.patch: -------------------------------------------------------------------------------- 1 | From 2242cdc93bfc8f004694ad07b36e611baf31d656 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Tue, 1 Apr 2025 18:38:28 +0200 4 | Subject: [PATCH] add bender package manifest 5 | 6 | --- 7 | Bender.yml | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 8 | 1 file changed, 51 insertions(+) 9 | create mode 100644 rtl/Bender.yml 10 | 11 | diff --git a/Bender.yml b/Bender.yml 12 | new file mode 100644 13 | index 00000000..73be92b7 14 | --- /dev/null 15 | +++ b/Bender.yml 16 | @@ -0,0 +1,51 @@ 17 | +# Copyright 2024 ETH Zurich and University of Bologna 18 | +# Solderpad Hardware License, Version 0.51, see LICENSE for details. 19 | +# SPDX-License-Identifier: SHL-0.51 20 | + 21 | +package: 22 | + name: cve2 23 | + 24 | +sources: 25 | + - include_dirs: 26 | + - include 27 | + files: 28 | + # Source files grouped in levels. Files in level 0 have no dependencies on files in this 29 | + # package. Files in level 1 only depend on files in level 0, files in level 2 on files in 30 | + # levels 1 and 0, etc. Files within a level are ordered alphabetically. 31 | + # Level 0 32 | + - cve2_pkg.sv 33 | + # Level 1 34 | + - cve2_alu.sv 35 | + - cve2_compressed_decoder.sv 36 | + - cve2_controller.sv 37 | + - cve2_counter.sv 38 | + - cve2_csr.sv 39 | + - cve2_decoder.sv 40 | + - cve2_fetch_fifo.sv 41 | + - cve2_load_store_unit.sv 42 | + - cve2_multdiv_fast.sv 43 | + - cve2_multdiv_slow.sv 44 | + - cve2_pmp.sv 45 | + - cve2_register_file_ff.sv 46 | + - cve2_wb.sv 47 | + # Level 2 48 | + - cve2_cs_registers.sv 49 | + - cve2_ex_block.sv 50 | + - cve2_id_stage.sv 51 | + - cve2_prefetch_buffer.sv 52 | + # Level 3 53 | + - cve2_if_stage.sv 54 | + # Level 4 55 | + - cve2_core.sv 56 | + 57 | + # In case we target RTL simulation, recompile the whole core with the RISC-V 58 | + # formal interface so the tracer module works (`define RVFI). 59 | + - target: all(any(test, cve2_include_tracer), not(cve2_exclude_tracer)) 60 | + include_dirs: 61 | + - include 62 | + defines: 63 | + RVFI: true 64 | + files: 65 | + - cve2_tracer_pkg.sv 66 | + - cve2_tracer.sv 67 | + - cve2_core_tracing.sv 68 | -- 69 | 2.34.1 70 | 71 | -------------------------------------------------------------------------------- /rtl/patches/obi/0001-adjust-Bender-source-paths.patch: -------------------------------------------------------------------------------- 1 | From 9c5d147e3656ff23fed8f9900b04db0596c00084 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Tue, 6 May 2025 17:08:53 +0200 4 | Subject: [PATCH] adjust Bender source paths 5 | 6 | --- 7 | Bender.yml | 28 ++++++++++------------------ 8 | 1 file changed, 10 insertions(+), 18 deletions(-) 9 | 10 | diff --git a/Bender.yml b/Bender.yml 11 | index a67bec7..33b2830 100644 12 | --- a/Bender.yml 13 | +++ b/Bender.yml 14 | @@ -16,24 +16,16 @@ export_include_dirs: 15 | 16 | sources: 17 | # Level 1 18 | - - src/obi_pkg.sv 19 | + - obi_pkg.sv 20 | # Level 2 21 | - - src/obi_intf.sv 22 | - - src/obi_rready_converter.sv 23 | + - obi_intf.sv 24 | + - obi_rready_converter.sv 25 | # Level 3 26 | - - src/obi_atop_resolver.sv 27 | - - src/obi_cut.sv 28 | - - src/obi_demux.sv 29 | - - src/obi_err_sbr.sv 30 | - - src/obi_mux.sv 31 | - - src/obi_sram_shim.sv 32 | + - obi_atop_resolver.sv 33 | + - obi_cut.sv 34 | + - obi_demux.sv 35 | + - obi_err_sbr.sv 36 | + - obi_mux.sv 37 | + - obi_sram_shim.sv 38 | # Level 4 39 | - - src/obi_xbar.sv 40 | - - target: test 41 | - files: 42 | - - src/test/obi_asserter.sv 43 | - - src/test/obi_test.sv 44 | - - src/test/obi_sim_mem.sv 45 | - - src/test/tb_obi_xbar.sv 46 | - - src/test/atop_golden_mem_pkg.sv 47 | - - src/test/tb_obi_atop_resolver.sv 48 | + - obi_xbar.sv 49 | -- 50 | 2.39.3 51 | 52 | -------------------------------------------------------------------------------- /rtl/patches/riscv-dbg/0001-adjust-Bender-source-paths.patch: -------------------------------------------------------------------------------- 1 | From cacd80b094ef7cfe00e53811e7ea73bdb415ec58 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 12:20:56 +0200 4 | Subject: [PATCH] adjust Bender source paths 5 | 6 | --- 7 | Bender.yml | 30 +++++++++++++----------------- 8 | 1 file changed, 13 insertions(+), 17 deletions(-) 9 | 10 | diff --git a/Bender.yml b/Bender.yml 11 | index 0e13a62..e6c362c 100644 12 | --- a/Bender.yml 13 | +++ b/Bender.yml 14 | @@ -15,39 +15,35 @@ dependencies: 15 | sources: 16 | files: 17 | # Level 1: 18 | - - src/dm_pkg.sv 19 | + - dm_pkg.sv 20 | - debug_rom/debug_rom.sv 21 | - debug_rom/debug_rom_one_scratch.sv 22 | # Level 2: 23 | - - src/dm_csrs.sv 24 | - - src/dm_mem.sv 25 | - - src/dmi_cdc.sv 26 | + - dm_csrs.sv 27 | + - dm_mem.sv 28 | + - dmi_cdc.sv 29 | - target: not(all(xilinx, bscane)) 30 | files: 31 | - - src/dmi_jtag_tap.sv 32 | + - dmi_jtag_tap.sv 33 | - target: all(xilinx, bscane) 34 | files: 35 | - - src/dmi_bscane_tap.sv 36 | + - dmi_bscane_tap.sv 37 | # Level 3: 38 | - - src/dm_sba.sv 39 | - - src/dm_top.sv 40 | - - src/dmi_jtag.sv 41 | + - dm_sba.sv 42 | + - dm_top.sv 43 | + - dmi_jtag.sv 44 | # Level 4: 45 | - - src/dm_obi_top.sv 46 | + - dm_obi_top.sv 47 | 48 | - target: simulation 49 | files: 50 | - - src/dmi_test.sv 51 | + - dmi_test.sv 52 | 53 | - target: test 54 | files: 55 | # Level 1 56 | - - src/dmi_intf.sv 57 | - - tb/jtag_dmi/jtag_intf.sv 58 | - - tb/jtag_dmi/jtag_test.sv 59 | - # Level 3 60 | - - tb/jtag_dmi/tb_jtag_dmi.sv 61 | + - dmi_intf.sv 62 | 63 | - target: verilator 64 | files: 65 | - - tb/jtag_dmi/jtag_test_simple.sv 66 | \ No newline at end of file 67 | + - tb/jtag_test_simple.sv 68 | \ No newline at end of file 69 | -- 70 | 2.25.1 71 | 72 | -------------------------------------------------------------------------------- /rtl/patches/riscv-dbg/src/0001-Replace-deprecated-fifo_v2.patch: -------------------------------------------------------------------------------- 1 | From 0ea6ebe0cb3ca697cbc0c45eb0237da8e6430058 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 12:00:43 +0200 4 | Subject: [PATCH] Replace deprecated fifo_v2 5 | 6 | --- 7 | dm_csrs.sv | 5 ++--- 8 | 1 file changed, 2 insertions(+), 3 deletions(-) 9 | 10 | diff --git a/dm_csrs.sv b/dm_csrs.sv 11 | index a945a70..fc5dec4 100644 12 | --- a/dm_csrs.sv 13 | +++ b/dm_csrs.sv 14 | @@ -590,7 +590,7 @@ module dm_csrs #( 15 | assign ndmreset_o = dmcontrol_q.ndmreset; 16 | 17 | // response FIFO 18 | - fifo_v2 #( 19 | + fifo_v3 #( 20 | .dtype ( logic [$bits(dmi_resp_o)-1:0] ), 21 | .DEPTH ( 2 ) 22 | ) i_fifo ( 23 | @@ -601,8 +601,7 @@ module dm_csrs #( 24 | .testmode_i ( testmode_i ), 25 | .full_o ( resp_queue_full ), 26 | .empty_o ( resp_queue_empty ), 27 | - .alm_full_o ( ), 28 | - .alm_empty_o ( ), 29 | + .usage_o ( ), 30 | .data_i ( resp_queue_inp ), 31 | .push_i ( resp_queue_push ), 32 | .data_o ( dmi_resp_o ), 33 | -- 34 | 2.25.1 35 | 36 | -------------------------------------------------------------------------------- /rtl/patches/timer_unit/0001-adjust-Bender-source-paths.patch: -------------------------------------------------------------------------------- 1 | From cb29a2d6b00b7b92981d95c5202dfe23d41d3974 Mon Sep 17 00:00:00 2001 2 | From: Philippe Sauter 3 | Date: Wed, 21 Aug 2024 12:26:12 +0200 4 | Subject: [PATCH] adjust Bender source paths 5 | 6 | --- 7 | Bender.yml | 8 ++++---- 8 | 1 file changed, 4 insertions(+), 4 deletions(-) 9 | 10 | diff --git a/Bender.yml b/Bender.yml 11 | index 1e1f780..9661475 100644 12 | --- a/Bender.yml 13 | +++ b/Bender.yml 14 | @@ -3,8 +3,8 @@ package: 15 | 16 | sources: 17 | # Level 0 18 | - - rtl/timer_unit_counter.sv 19 | - - rtl/timer_unit_counter_presc.sv 20 | + - timer_unit_counter.sv 21 | + - timer_unit_counter_presc.sv 22 | # Level 1 23 | - - rtl/apb_timer_unit.sv 24 | - - rtl/timer_unit.sv 25 | + - apb_timer_unit.sv 26 | + - timer_unit.sv 27 | -- 28 | 2.25.1 29 | 30 | -------------------------------------------------------------------------------- /rtl/register_interface/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: register_interface 3 | authors: ["Fabian Schuiki ", "Florian Zaruba "] 4 | 5 | dependencies: 6 | apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.2} 7 | common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } 8 | common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } 9 | 10 | export_include_dirs: 11 | - include 12 | 13 | sources: 14 | # Level 0 15 | - reg_intf.sv 16 | - lowrisc_opentitan/prim_subreg_arb.sv 17 | - lowrisc_opentitan/prim_subreg_ext.sv 18 | # Level 1 19 | - periph_to_reg.sv 20 | - reg_to_apb.sv 21 | - lowrisc_opentitan/prim_subreg_shadow.sv 22 | - lowrisc_opentitan/prim_subreg.sv 23 | -------------------------------------------------------------------------------- /rtl/register_interface/README.md: -------------------------------------------------------------------------------- 1 | # Generic Register Interface 2 | 3 | This repository contains a simple register interface definition as well as protocol adapters from APB, AXI-Lite, and AXI to said interface. Furthermore, it allows to generate a uniform register interface. 4 | 5 | ## Read Timing 6 | 7 | ![Read Timing](docs/timing_read.png) 8 | 9 | ## Write Timing 10 | 11 | ![Write Timing](docs/timing_write.png) 12 | 13 | ## Register File Generator 14 | 15 | We re-use lowrisc's register file generator to generate arbitrary configuration registers from an `hjson` description. See the the [tool's description](https://docs.opentitan.org/doc/rm/register_tool/) for further usage details. 16 | 17 | We use the [bender import tool](https://github.com/pulp-platform/bender#import-----copy-files-from-dependencies-that-do-not-support-bender) (`>v0.26.0`) to get the sources and apply our custom patches on top. 18 | 19 | curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- 0.26.0 20 | ./bender import --refetch 21 | 22 | to re-vendor. -------------------------------------------------------------------------------- /rtl/register_interface/include/register_interface/assign.svh: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 ETH Zurich, University of Bologna 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | 12 | // Florian Zaruba 13 | /// Macros to define register bus request/response structs. 14 | 15 | `ifndef REGISTER_INTERFACE_ASSIGN_SVH_ 16 | `define REGISTER_INTERFACE_ASSIGN_SVH_ 17 | 18 | `define REG_BUS_ASSIGN_TO_REQ(lhs, rhs) \ 19 | assign lhs = '{ \ 20 | addr: rhs.addr, \ 21 | write: rhs.write, \ 22 | wdata: rhs.wdata, \ 23 | wstrb: rhs.wstrb, \ 24 | valid: rhs.valid \ 25 | }; 26 | 27 | `define REG_BUS_ASSIGN_FROM_REQ(lhs, rhs) \ 28 | assign lhs.addr = rhs.addr; \ 29 | assign lhs.write = rhs.write; \ 30 | assign lhs.wdata = rhs.wdata; \ 31 | assign lhs.wstrb = rhs.wstrb; \ 32 | assign lhs.valid = rhs.valid; \ 33 | 34 | `define REG_BUS_ASSIGN_TO_RSP(lhs, rhs) \ 35 | assign lhs = '{ \ 36 | rdata: rhs.rdata, \ 37 | error: rhs.error, \ 38 | ready: rhs.ready \ 39 | }; 40 | 41 | `define REG_BUS_ASSIGN_FROM_RSP(lhs, rhs) \ 42 | assign lhs.rdata = rhs.rdata; \ 43 | assign lhs.error = rhs.error; \ 44 | assign lhs.ready = rhs.ready; 45 | 46 | `endif 47 | -------------------------------------------------------------------------------- /rtl/register_interface/include/register_interface/typedef.svh: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 ETH Zurich, University of Bologna 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | 12 | // Florian Zaruba 13 | /// Macros to define register bus request/response structs. 14 | 15 | `ifndef REGISTER_INTERFACE_TYPEDEF_SVH_ 16 | `define REGISTER_INTERFACE_TYPEDEF_SVH_ 17 | 18 | `define REG_BUS_TYPEDEF_REQ(req_t, addr_t, data_t, strb_t) \ 19 | typedef struct packed { \ 20 | addr_t addr; \ 21 | logic write; \ 22 | data_t wdata; \ 23 | strb_t wstrb; \ 24 | logic valid; \ 25 | } req_t; 26 | 27 | `define REG_BUS_TYPEDEF_RSP(rsp_t, data_t) \ 28 | typedef struct packed { \ 29 | data_t rdata; \ 30 | logic error; \ 31 | logic ready; \ 32 | } rsp_t; 33 | 34 | `define REG_BUS_TYPEDEF_ALL(name, addr_t, data_t, strb_t) \ 35 | `REG_BUS_TYPEDEF_REQ(name``_req_t, addr_t, data_t, strb_t) \ 36 | `REG_BUS_TYPEDEF_RSP(name``_rsp_t, data_t) 37 | 38 | `endif 39 | -------------------------------------------------------------------------------- /rtl/register_interface/lowrisc_opentitan/prim_subreg.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Register slice conforming to Comportibility guide. 6 | 7 | module prim_subreg #( 8 | parameter int DW = 32 , 9 | parameter SWACCESS = "RW", // {RW, RO, WO, W1C, W1S, W0C, RC} 10 | parameter logic [DW-1:0] RESVAL = '0 // Reset value 11 | ) ( 12 | input clk_i, 13 | input rst_ni, 14 | 15 | // From SW: valid for RW, WO, W1C, W1S, W0C, RC 16 | // In case of RC, Top connects Read Pulse to we 17 | input we, 18 | input [DW-1:0] wd, 19 | 20 | // From HW: valid for HRW, HWO 21 | input de, 22 | input [DW-1:0] d, 23 | 24 | // output to HW and Reg Read 25 | output logic qe, 26 | output logic [DW-1:0] q, 27 | output logic [DW-1:0] qs 28 | ); 29 | 30 | logic wr_en; 31 | logic [DW-1:0] wr_data; 32 | 33 | prim_subreg_arb #( 34 | .DW ( DW ), 35 | .SWACCESS ( SWACCESS ) 36 | ) wr_en_data_arb ( 37 | .we, 38 | .wd, 39 | .de, 40 | .d, 41 | .q, 42 | .wr_en, 43 | .wr_data 44 | ); 45 | 46 | always_ff @(posedge clk_i or negedge rst_ni) begin 47 | if (!rst_ni) begin 48 | qe <= 1'b0; 49 | end else begin 50 | qe <= we; 51 | end 52 | end 53 | 54 | always_ff @(posedge clk_i or negedge rst_ni) begin 55 | if (!rst_ni) begin 56 | q <= RESVAL; 57 | end else if (wr_en) begin 58 | q <= wr_data; 59 | end 60 | end 61 | 62 | assign qs = q; 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Register slice conforming to Comportibility guide. 6 | 7 | module prim_subreg_ext #( 8 | parameter int unsigned DW = 32 9 | ) ( 10 | input re, 11 | input we, 12 | input [DW-1:0] wd, 13 | 14 | input [DW-1:0] d, 15 | 16 | // output to HW and Reg Read 17 | output logic qe, 18 | output logic qre, 19 | output logic [DW-1:0] q, 20 | output logic [DW-1:0] qs 21 | ); 22 | 23 | assign qs = d; 24 | assign q = wd; 25 | assign qe = we; 26 | assign qre = re; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /rtl/register_interface/reg_intf.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Fabian Schuiki 12 | 13 | /// A simple register interface. 14 | /// 15 | /// This is pretty much as simple as it gets. Transactions consist of only one 16 | /// phase. The master sets the address, write, write data, and write strobe 17 | /// signals and pulls valid high. Once pulled high, valid must remain high and 18 | /// none of the signals may change. The transaction completes when both valid 19 | /// and ready are high. Valid must not depend on ready. The slave presents the 20 | /// read data and error signals. These signals must be constant while valid and 21 | /// ready are both high. 22 | interface REG_BUS #( 23 | /// The width of the address. 24 | parameter int ADDR_WIDTH = -1, 25 | /// The width of the data. 26 | parameter int DATA_WIDTH = -1 27 | )( 28 | input logic clk_i 29 | ); 30 | 31 | logic [ADDR_WIDTH-1:0] addr; 32 | logic write; // 0=read, 1=write 33 | logic [DATA_WIDTH-1:0] rdata; 34 | logic [DATA_WIDTH-1:0] wdata; 35 | logic [DATA_WIDTH/8-1:0] wstrb; // byte-wise strobe 36 | logic error; // 0=ok, 1=error 37 | logic valid; 38 | logic ready; 39 | 40 | modport in (input addr, write, wdata, wstrb, valid, output rdata, error, ready); 41 | modport out (output addr, write, wdata, wstrb, valid, input rdata, error, ready); 42 | 43 | endinterface 44 | -------------------------------------------------------------------------------- /rtl/register_interface/reg_to_apb.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | // 5 | // Nils Wistoff 6 | 7 | module reg_to_apb #( 8 | /// Regbus request struct type. 9 | parameter type reg_req_t = logic, 10 | /// Regbus response struct type. 11 | parameter type reg_rsp_t = logic, 12 | /// APB request struct type. 13 | parameter type apb_req_t = logic, 14 | /// APB response type. 15 | parameter type apb_rsp_t = logic 16 | ) 17 | ( 18 | input logic clk_i, 19 | input logic rst_ni, 20 | 21 | // Register interface 22 | input reg_req_t reg_req_i, 23 | output reg_rsp_t reg_rsp_o, 24 | 25 | // APB interface 26 | output apb_req_t apb_req_o, 27 | input apb_rsp_t apb_rsp_i 28 | ); 29 | 30 | // APB phase FSM 31 | typedef enum logic {SETUP, ACCESS} state_e; 32 | state_e state_d, state_q; 33 | 34 | // Feed these through. 35 | assign apb_req_o.paddr = reg_req_i.addr; 36 | assign apb_req_o.pwrite = reg_req_i.write; 37 | assign apb_req_o.pwdata = reg_req_i.wdata; 38 | assign apb_req_o.psel = reg_req_i.valid; 39 | assign apb_req_o.pstrb = reg_req_i.wstrb; 40 | 41 | assign reg_rsp_o.error = apb_rsp_i.pslverr; 42 | assign reg_rsp_o.rdata = apb_rsp_i.prdata; 43 | 44 | // Tie PPROT to {0: unprivileged, 1: non-secure, 0: data} 45 | assign apb_req_o.pprot = 3'b010; 46 | 47 | // APB phase FSM 48 | always_comb begin : apb_fsm 49 | apb_req_o.penable = 1'b0; 50 | reg_rsp_o.ready = 1'b0; 51 | state_d = state_q; 52 | unique case (state_q) 53 | // Setup phase (or idle). Deassert PENABLE, gate PREADY. 54 | SETUP: if (reg_req_i.valid) state_d = ACCESS; 55 | // Access phase. Assert PENABLE, feed PREADY through. 56 | ACCESS: begin 57 | apb_req_o.penable = 1'b1; 58 | reg_rsp_o.ready = apb_rsp_i.pready; 59 | if (apb_rsp_i.pready) state_d = SETUP; 60 | end 61 | // We should never reach this state. 62 | default: state_d = SETUP; 63 | endcase 64 | end 65 | 66 | always_ff @(posedge clk_i or negedge rst_ni) begin 67 | if (!rst_ni) begin 68 | state_q <= SETUP; 69 | end else begin 70 | state_q <= state_d; 71 | end 72 | end 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /rtl/riscv-dbg/Bender.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2020-2021 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | package: 6 | name: riscv-dbg 7 | authors: 8 | - Florian Zaruba 9 | - Robert Balas 10 | 11 | dependencies: 12 | tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } 13 | common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0} 14 | 15 | sources: 16 | files: 17 | # Level 1: 18 | - dm_pkg.sv 19 | - debug_rom/debug_rom.sv 20 | - debug_rom/debug_rom_one_scratch.sv 21 | # Level 2: 22 | - dm_csrs.sv 23 | - dm_mem.sv 24 | - dmi_cdc.sv 25 | - target: not(all(xilinx, bscane)) 26 | files: 27 | - dmi_jtag_tap.sv 28 | - target: all(xilinx, bscane) 29 | files: 30 | - dmi_bscane_tap.sv 31 | # Level 3: 32 | - dm_sba.sv 33 | - dm_top.sv 34 | - dmi_jtag.sv 35 | # Level 4: 36 | - dm_obi_top.sv 37 | 38 | - target: simulation 39 | files: 40 | - dmi_test.sv 41 | 42 | - target: test 43 | files: 44 | # Level 1 45 | - dmi_intf.sv 46 | 47 | - target: verilator 48 | files: 49 | - tb/jtag_test_simple.sv -------------------------------------------------------------------------------- /rtl/riscv-dbg/README.md: -------------------------------------------------------------------------------- 1 | [![Build Status](https://travis-ci.com/pulp-platform/riscv-dbg.svg?branch=master)](https://travis-ci.com/pulp-platform/riscv-dbg) 2 | 3 | # RISC-V Debug Support for PULP Cores 4 | 5 | This module is an implementation of a debug unit compliant with the [RISC-V 6 | debug specification](https://github.com/riscv/riscv-debug-spec) v0.13.1. It is 7 | used in the [Ariane](https://github.com/pulp-platform/ariane) and 8 | [RI5CY](https://github.com/pulp-platform/riscv) cores. 9 | 10 | ## Implementation 11 | We use an execution-based technique, also described in the specification, where 12 | the core is running in a "park loop". Depending on the request made to the debug 13 | unit via JTAG over the Debug Transport Module (DTM), the code that is being 14 | executed is changed dynamically. This approach simplifies the implementation 15 | side of the core, but means that the core is in fact always busy looping while 16 | debugging. 17 | 18 | ## Features 19 | The following features are currently supported 20 | 21 | * Parametrizable buswidth for `XLEN=32` `XLEN=64` cores 22 | * Accessing registers over abstract command 23 | * Program buffer 24 | * System bus access (only `XLEN`) 25 | * DTM with JTAG interface 26 | 27 | These are not implemented (yet) 28 | 29 | * Trigger module 30 | * Quick access using abstract commands 31 | * Accessing memory using abstract commands 32 | * Authentication 33 | 34 | ## Tests 35 | 36 | We use OpenOCD's [RISC-V compliance 37 | tests](https://github.com/riscv/riscv-openocd/blob/riscv/src/target/riscv/riscv-013.c), 38 | our custom testbench in `tb/` and 39 | [riscv-tests/debug](https://github.com/riscv/riscv-tests/tree/master/debug). 40 | -------------------------------------------------------------------------------- /rtl/riscv-dbg/debug_rom/debug_rom.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 ETH Zurich and University of Bologna. 2 | * Copyright and related rights are licensed under the Solderpad Hardware 3 | * License, Version 0.51 (the "License"); you may not use this file except in 4 | * compliance with the License. You may obtain a copy of the License at 5 | * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | * or agreed to in writing, software, hardware and materials distributed under 7 | * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | * specific language governing permissions and limitations under the License. 10 | * 11 | * File: $filename.v 12 | * 13 | * Description: Auto-generated bootrom 14 | */ 15 | 16 | // Auto-generated code 17 | module debug_rom ( 18 | input logic clk_i, 19 | input logic rst_ni, 20 | input logic req_i, 21 | input logic [63:0] addr_i, 22 | output logic [63:0] rdata_o 23 | ); 24 | 25 | localparam int unsigned RomSize = 20; 26 | 27 | logic [RomSize-1:0][63:0] mem; 28 | assign mem = { 29 | 64'h7b200073_7b202473, 30 | 64'h7b302573_10852823, 31 | 64'hf1402473_a79ff06f, 32 | 64'h7b202473_7b302573, 33 | 64'h10052423_00100073, 34 | 64'h7b202473_7b302573, 35 | 64'h10052c23_00c51513, 36 | 64'h00c55513_00000517, 37 | 64'hfd5ff06f_fa0418e3, 38 | 64'h00247413_40044403, 39 | 64'h00a40433_f1402473, 40 | 64'h02041c63_00147413, 41 | 64'h40044403_00a40433, 42 | 64'h10852023_f1402473, 43 | 64'h00c51513_00c55513, 44 | 64'h00000517_7b351073, 45 | 64'h7b241073_0ff0000f, 46 | 64'h00000013_0500006f, 47 | 64'h00000013_0840006f, 48 | 64'h00000013_0180006f 49 | }; 50 | 51 | logic [$clog2(RomSize)-1:0] addr_d, addr_q; 52 | 53 | assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q; 54 | 55 | always_ff @(posedge clk_i or negedge rst_ni) begin 56 | if (!rst_ni) begin 57 | addr_q <= '0; 58 | end else begin 59 | addr_q <= addr_d; 60 | end 61 | end 62 | 63 | // this prevents spurious Xes from propagating into 64 | // the speculative fetch stage of the core 65 | always_comb begin : p_outmux 66 | rdata_o = '0; 67 | if (addr_q < $clog2(RomSize)'(RomSize)) begin 68 | rdata_o = mem[addr_q]; 69 | end 70 | end 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv: -------------------------------------------------------------------------------- 1 | /* Copyright 2018 ETH Zurich and University of Bologna. 2 | * Copyright and related rights are licensed under the Solderpad Hardware 3 | * License, Version 0.51 (the "License"); you may not use this file except in 4 | * compliance with the License. You may obtain a copy of the License at 5 | * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | * or agreed to in writing, software, hardware and materials distributed under 7 | * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | * CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | * specific language governing permissions and limitations under the License. 10 | * 11 | * File: $filename.v 12 | * 13 | * Description: Auto-generated bootrom 14 | */ 15 | 16 | // Auto-generated code 17 | module debug_rom_one_scratch ( 18 | input logic clk_i, 19 | input logic rst_ni, 20 | input logic req_i, 21 | input logic [63:0] addr_i, 22 | output logic [63:0] rdata_o 23 | ); 24 | 25 | localparam int unsigned RomSize = 14; 26 | 27 | logic [RomSize-1:0][63:0] mem; 28 | assign mem = { 29 | 64'h7b200073_7b202473, 30 | 64'h10802823_f1402473, 31 | 64'haa5ff06f_7b202473, 32 | 64'h10002423_00100073, 33 | 64'h7b202473_10002c23, 34 | 64'hfddff06f_fc0414e3, 35 | 64'h00247413_40044403, 36 | 64'hf1402473_02041263, 37 | 64'h00147413_40044403, 38 | 64'h10802023_f1402473, 39 | 64'h7b241073_0ff0000f, 40 | 64'h00000013_0380006f, 41 | 64'h00000013_0580006f, 42 | 64'h00000013_0180006f 43 | }; 44 | 45 | logic [$clog2(RomSize)-1:0] addr_d, addr_q; 46 | 47 | assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q; 48 | 49 | always_ff @(posedge clk_i or negedge rst_ni) begin 50 | if (!rst_ni) begin 51 | addr_q <= '0; 52 | end else begin 53 | addr_q <= addr_d; 54 | end 55 | end 56 | 57 | // this prevents spurious Xes from propagating into 58 | // the speculative fetch stage of the core 59 | always_comb begin : p_outmux 60 | rdata_o = '0; 61 | if (addr_q < $clog2(RomSize)'(RomSize)) begin 62 | rdata_o = mem[addr_q]; 63 | end 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /rtl/riscv-dbg/dmi_intf.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2021 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | 5 | // Author: Florian Zaruba 6 | 7 | 8 | // The DV interface additionally carries a clock signal. 9 | interface DMI_BUS_DV #( 10 | /// The width of the address. 11 | parameter int ADDR_WIDTH = -1 12 | ) ( 13 | input logic clk_i 14 | ); 15 | 16 | import dm::*; 17 | 18 | typedef logic [ADDR_WIDTH-1:0] addr_t; 19 | typedef logic [31:0] data_t; 20 | /// The request channel (Q). 21 | addr_t q_addr; 22 | dtm_op_e q_op; 23 | data_t q_data; 24 | logic q_valid; 25 | logic q_ready; 26 | 27 | /// The response channel (P). 28 | data_t p_data; 29 | logic p_resp; 30 | logic p_valid; 31 | logic p_ready; 32 | 33 | modport in ( 34 | input q_addr, q_op, q_data, q_valid, p_ready, 35 | output q_ready, p_data, p_resp, p_valid 36 | ); 37 | modport out ( 38 | output q_addr, q_op, q_data, q_valid, p_ready, 39 | input q_ready, p_data, p_resp, p_valid 40 | ); 41 | modport monitor ( 42 | input q_addr, q_op, q_data, q_valid, p_ready, 43 | q_ready, p_data, p_resp, p_valid 44 | ); 45 | 46 | // pragma translate_off 47 | `ifndef VERILATOR 48 | assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_addr))); 49 | assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_op))); 50 | assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_data))); 51 | assert property (@(posedge clk_i) (q_valid && !q_ready |=> q_valid)); 52 | 53 | assert property (@(posedge clk_i) (p_valid && !p_ready |=> $stable(p_data))); 54 | assert property (@(posedge clk_i) (p_valid && !p_ready |=> $stable(p_resp))); 55 | assert property (@(posedge clk_i) (p_valid && !p_ready |=> p_valid)); 56 | `endif 57 | // pragma translate_on 58 | 59 | endinterface 60 | -------------------------------------------------------------------------------- /rtl/soc_ctrl/boot_addr.patch: -------------------------------------------------------------------------------- 1 | diff --git a/rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv b/rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv 2 | index 72ef442..ce0d906 100644 3 | --- a/rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv 4 | +++ b/rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv 5 | @@ -10,7 +10,8 @@ 6 | module safety_soc_ctrl_reg_top #( 7 | parameter type reg_req_t = logic, 8 | parameter type reg_rsp_t = logic, 9 | - parameter int AW = 4 10 | + parameter int AW = 4, 11 | + parameter int unsigned BootAddrDefault = 32'h0 12 | ) ( 13 | input logic clk_i, 14 | input logic rst_ni, 15 | @@ -83,7 +84,7 @@ module safety_soc_ctrl_reg_top #( 16 | prim_subreg #( 17 | .DW (32), 18 | .SWACCESS("RW"), 19 | - .RESVAL (32'h10000000) 20 | + .RESVAL (BootAddrDefault) 21 | ) u_bootaddr ( 22 | .clk_i (clk_i ), 23 | .rst_ni (rst_ni ), 24 | -------------------------------------------------------------------------------- /rtl/soc_ctrl/reg_html.css: -------------------------------------------------------------------------------- 1 | /* Stylesheet for reggen HTML register output */ 2 | /* Copyright lowRISC contributors. */ 3 | /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ 4 | /* SPDX-License-Identifier: Apache-2.0 */ 5 | 6 | table.regpic { 7 | width: 95%; 8 | border-collapse: collapse; 9 | margin-left:auto; 10 | margin-right:auto; 11 | table-layout:fixed; 12 | } 13 | 14 | table.regdef { 15 | border: 1px solid black; 16 | width: 80%; 17 | border-collapse: collapse; 18 | margin-left:auto; 19 | margin-right:auto; 20 | table-layout:auto; 21 | } 22 | 23 | table.regdef th { 24 | border: 1px solid black; 25 | font-family: sans-serif; 26 | 27 | } 28 | 29 | td.bitnum { 30 | font-size: 60%; 31 | text-align: center; 32 | } 33 | 34 | td.unused { 35 | border: 1px solid black; 36 | background-color: gray; 37 | } 38 | 39 | td.fname { 40 | border: 1px solid black; 41 | text-align: center; 42 | font-family: sans-serif; 43 | } 44 | 45 | 46 | td.regbits, td.regperm, td.regrv { 47 | border: 1px solid black; 48 | text-align: center; 49 | font-family: sans-serif; 50 | } 51 | 52 | td.regde, td.regfn { 53 | border: 1px solid black; 54 | } 55 | 56 | table.cfgtable { 57 | border: 1px solid black; 58 | width: 80%; 59 | border-collapse: collapse; 60 | margin-left:auto; 61 | margin-right:auto; 62 | table-layout:auto; 63 | } 64 | 65 | table.cfgtable th { 66 | border: 1px solid black; 67 | font-family: sans-serif; 68 | font-weight: bold; 69 | } 70 | 71 | table.cfgtable td { 72 | border: 1px solid black; 73 | font-family: sans-serif; 74 | } 75 | -------------------------------------------------------------------------------- /rtl/soc_ctrl/soc_ctrl.h: -------------------------------------------------------------------------------- 1 | // Generated register defines for safety_soc_ctrl 2 | 3 | // Copyright information found in source file: 4 | // Copyright 2024 ETH Zurich and University of Bologna 5 | 6 | // Licensing information found in source file: 7 | // 8 | // SPDX-License-Identifier: SHL-0.51 9 | 10 | #ifndef _SOC_CTRL_REG_DEFS_ 11 | #define _SOC_CTRL_REG_DEFS_ 12 | 13 | #ifdef __cplusplus 14 | extern "C" { 15 | #endif 16 | // Register width 17 | #define SOC_CTRL_PARAM_REG_WIDTH 32 18 | 19 | // Core Boot Address 20 | #define SOC_CTRL_BOOTADDR_REG_OFFSET 0x0 21 | 22 | // Core Fetch Enable 23 | #define SOC_CTRL_FETCHEN_REG_OFFSET 0x4 24 | #define SOC_CTRL_FETCHEN_FETCHEN_BIT 0 25 | 26 | // Core Return Status (return value, EOC) 27 | #define SOC_CTRL_CORESTATUS_REG_OFFSET 0x8 28 | 29 | // Core Boot Mode 30 | #define SOC_CTRL_BOOTMODE_REG_OFFSET 0xc 31 | #define SOC_CTRL_BOOTMODE_BOOTMODE_MASK 0x3 32 | #define SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET 0 33 | #define SOC_CTRL_BOOTMODE_BOOTMODE_FIELD \ 34 | ((bitfield_field32_t) { .mask = SOC_CTRL_BOOTMODE_BOOTMODE_MASK, .index = SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET }) 35 | 36 | #ifdef __cplusplus 37 | } // extern "C" 38 | #endif 39 | #endif // _SOC_CTRL_REG_DEFS_ 40 | // End generated register defines for safety_soc_ctrl -------------------------------------------------------------------------------- /rtl/soc_ctrl/soc_ctrl_regs.hjson: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | 5 | { 6 | name: "soc_ctrl", 7 | clock_primary: "clk_i", 8 | reset_primary: "rst_ni", 9 | bus_interfaces: [ 10 | { protocol: "reg_iface", 11 | direction: "device" 12 | } 13 | ], 14 | 15 | regwidth: "32", 16 | registers: [ 17 | { name: "bootaddr", 18 | desc: "Core Boot Address", 19 | swaccess: "rw", 20 | hwaccess: "hro", 21 | fields: [ 22 | { bits: "31:0", 23 | name: "bootaddr", 24 | desc: "Boot Address", 25 | resval: 0x1000_0000 26 | } 27 | ] 28 | 29 | }, 30 | { name: "fetchen", 31 | desc: "Core Fetch Enable", 32 | swaccess: "rw", 33 | hwaccess: "hrw", 34 | fields: [ 35 | { bits: "0", 36 | name: "fetchen", 37 | desc: "Fetch Enable", 38 | resval: 0 39 | } 40 | ] 41 | }, 42 | { name: "corestatus", 43 | desc: "Core Return Status (return value, EOC)", 44 | swaccess: "rw", 45 | hwaccess: "hro", 46 | fields: [ 47 | { bits: "31:0", 48 | name: "core_status", 49 | desc: "Core Return Status (EOC(bit[31]) and status(bit[30:0]))", 50 | resval: 0 51 | } 52 | ] 53 | }, 54 | { name: "bootmode", 55 | desc: "Core Boot Mode", 56 | swaccess: "rw", 57 | hwaccess: "hrw", 58 | fields: [ 59 | { bits: "0", 60 | name: "bootmode", 61 | desc: "Boot Mode", 62 | resval: 0x0 63 | } 64 | ] 65 | }, 66 | { name: "sram_dly", 67 | desc: "SRAM A_DLY value", 68 | swaccess: "rw", 69 | hwaccess: "hro", 70 | fields: [ 71 | { bits: "0", 72 | name: "sram_dly", 73 | desc: "Controls the A_DLY pin of the SRAMs (configured internal timings)", 74 | resval: 0x1 75 | } 76 | ] 77 | } 78 | 79 | ], 80 | } 81 | -------------------------------------------------------------------------------- /rtl/tech_cells_generic/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: tech_cells_generic 3 | description: "Technology-agnostic building blocks." 4 | 5 | dependencies: 6 | common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } 7 | 8 | sources: 9 | - target: all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_sram), not(tech_cells_generic_exclude_tc_sram)) 10 | files: 11 | # Level 0 12 | - tc_sram.sv 13 | - tc_sram_impl.sv 14 | 15 | - target: all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_clk), not(tech_cells_generic_exclude_tc_clk)) 16 | files: 17 | # Level 0 18 | - tc_clk.sv 19 | 20 | - target: all(any(fpga, tech_cells_generic_include_xilinx_xpm), not(tech_cells_generic_exclude_xilinx_xpm)) 21 | files: 22 | - fpga/pad_functional_xilinx.sv 23 | - fpga/tc_clk_xilinx.sv 24 | - fpga/tc_sram_xilinx.sv 25 | - tc_sram_impl.sv 26 | -------------------------------------------------------------------------------- /rtl/tech_cells_generic/fpga/pad_functional_xilinx.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | module pad_functional_pd 13 | ( 14 | input logic OEN, 15 | input logic I, 16 | output logic O, 17 | input logic PEN, 18 | inout logic PAD 19 | ); 20 | 21 | (* PULLDOWN = "YES" *) 22 | IOBUF iobuf_i ( 23 | .T ( OEN ), 24 | .I ( I ), 25 | .O ( O ), 26 | .IO( PAD ) 27 | ); 28 | 29 | endmodule 30 | 31 | module pad_functional_pu 32 | ( 33 | input logic OEN, 34 | input logic I, 35 | output logic O, 36 | input logic PEN, 37 | inout logic PAD 38 | ); 39 | 40 | (* PULLUP = "YES" *) 41 | IOBUF iobuf_i ( 42 | .T ( OEN ), 43 | .I ( I ), 44 | .O ( O ), 45 | .IO( PAD ) 46 | ); 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /rtl/timer_unit/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: timer_unit 3 | 4 | sources: 5 | # Level 0 6 | - timer_unit_counter.sv 7 | - timer_unit_counter_presc.sv 8 | # Level 1 9 | - apb_timer_unit.sv 10 | - timer_unit.sv 11 | -------------------------------------------------------------------------------- /rtl/timer_unit/timer_unit.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/croc/b44242be749da0b533b7688c65376e15cc795d07/rtl/timer_unit/timer_unit.pdf -------------------------------------------------------------------------------- /rtl/timer_unit/timer_unit_counter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2014-2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Davide Rossi 12 | 13 | module timer_unit_counter 14 | ( 15 | input logic clk_i, 16 | input logic rst_ni, 17 | 18 | input logic write_counter_i, 19 | input logic [31:0] counter_value_i, 20 | 21 | input logic reset_count_i, 22 | input logic enable_count_i, 23 | input logic [31:0] compare_value_i, 24 | 25 | output logic [31:0] counter_value_o, 26 | output logic target_reached_o 27 | ); 28 | 29 | logic [31:0] s_count, s_count_reg; 30 | 31 | // COUNTER 32 | always_comb 33 | begin 34 | s_count = s_count_reg; 35 | 36 | // start counting 37 | if ( reset_count_i == 1 ) 38 | s_count = 0; 39 | else 40 | begin 41 | if (write_counter_i == 1) // OVERWRITE COUNTER 42 | s_count = counter_value_i; 43 | else 44 | begin 45 | if ( enable_count_i == 1 ) // the counter is increased if counter is enabled and there is a tick 46 | s_count = s_count_reg + 1; 47 | end 48 | end 49 | end 50 | 51 | always_ff@(posedge clk_i, negedge rst_ni) 52 | begin 53 | if (rst_ni == 0) 54 | s_count_reg <= 0; 55 | else 56 | s_count_reg <= s_count; 57 | end 58 | 59 | // COMPARATOR 60 | always_ff@(posedge clk_i, negedge rst_ni) 61 | begin 62 | if (rst_ni == 0) 63 | target_reached_o <= 1'b0; 64 | else 65 | if ( s_count == compare_value_i ) 66 | target_reached_o <= 1'b1; 67 | else 68 | target_reached_o <= 1'b0; 69 | end 70 | 71 | assign counter_value_o = s_count_reg; 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /rtl/timer_unit/timer_unit_counter_presc.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2014-2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Davide Rossi 12 | 13 | module timer_unit_counter_presc 14 | ( 15 | input logic clk_i, 16 | input logic rst_ni, 17 | 18 | input logic write_counter_i, 19 | input logic [31:0] counter_value_i, 20 | 21 | input logic reset_count_i, 22 | input logic enable_count_i, 23 | input logic [31:0] compare_value_i, 24 | 25 | output logic [31:0] counter_value_o, 26 | output logic target_reached_o 27 | ); 28 | 29 | logic [31:0] s_count, s_count_reg; 30 | 31 | // COUNTER 32 | always_comb 33 | begin 34 | s_count = s_count_reg; 35 | 36 | // start counting 37 | if ( reset_count_i == 1 || target_reached_o==1) 38 | s_count = 0; 39 | else 40 | begin 41 | if (write_counter_i == 1) // OVERWRITE COUNTER 42 | s_count = counter_value_i; 43 | else 44 | begin 45 | if ( enable_count_i == 1 ) 46 | s_count = s_count_reg + 1; 47 | end 48 | end 49 | end 50 | 51 | always_ff@(posedge clk_i, negedge rst_ni) 52 | begin 53 | if (rst_ni == 0) 54 | s_count_reg <= 0; 55 | else 56 | s_count_reg <= s_count; 57 | end 58 | 59 | // COMPARATOR 60 | always_ff@(posedge clk_i, negedge rst_ni) 61 | begin 62 | if (rst_ni == 0) 63 | target_reached_o <= 1'b0; 64 | else 65 | if ( s_count == compare_value_i ) 66 | target_reached_o <= 1'b1; 67 | else 68 | target_reached_o <= 1'b0; 69 | end 70 | 71 | assign counter_value_o = s_count_reg; 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /rtl/user_domain/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/croc/b44242be749da0b533b7688c65376e15cc795d07/rtl/user_domain/.gitkeep -------------------------------------------------------------------------------- /rtl/user_pkg.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | // 5 | // Authors: 6 | // - Philippe Sauter 7 | 8 | `include "register_interface/typedef.svh" 9 | `include "obi/typedef.svh" 10 | 11 | package user_pkg; 12 | 13 | //////////////////////////////// 14 | // User Manager Address maps // 15 | /////////////////////////////// 16 | 17 | // None 18 | 19 | 20 | ///////////////////////////////////// 21 | // User Subordinate Address maps //// 22 | ///////////////////////////////////// 23 | 24 | localparam int unsigned NumUserDomainSubordinates = 0; 25 | 26 | localparam bit [31:0] UserRomAddrOffset = croc_pkg::UserBaseAddr; // 32'h2000_0000; 27 | localparam bit [31:0] UserRomAddrRange = 32'h0000_1000; // every subordinate has at least 4KB 28 | 29 | localparam int unsigned NumDemuxSbrRules = NumUserDomainSubordinates; // number of address rules in the decoder 30 | localparam int unsigned NumDemuxSbr = NumDemuxSbrRules + 1; // additional OBI error, used for signal arrays 31 | 32 | // Enum for bus indices 33 | typedef enum int { 34 | UserError = 0 35 | } user_demux_outputs_e; 36 | 37 | // Address rules given to address decoder 38 | localparam croc_pkg::addr_map_rule_t [NumDemuxSbrRules-1:0] user_addr_map = '0; 39 | 40 | endpackage 41 | -------------------------------------------------------------------------------- /start_linux.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 4 | # SPDX-License-Identifier: Apache-2.0 5 | # 6 | # Authors: 7 | # - Philippe Sauter 8 | 9 | env UID=$(id -u) GID=$(id -g) docker compose pull pulp-docker 10 | 11 | env UID=$(id -u) GID=$(id -g) docker compose run --rm \ 12 | -e PS1="\[\033[01;32m\]osic:\[\033[00m\]\[\033[01;34m\]\w\[\033[00m\] $" \ 13 | -e DISPLAY=$DISPLAY \ 14 | -v /tmp/.X11-unix:/tmp/.X11-unix \ 15 | pulp-docker 16 | -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | bin 2 | *.o 3 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Paul Scheffler 7 | # - Philippe Sauter 8 | 9 | SRCDIR ?= lib/src 10 | INCDIR ?= lib/inc 11 | 12 | # Toolchain 13 | 14 | RISCV_XLEN ?= 32 15 | RISCV_MARCH ?= rv$(RISCV_XLEN)i_zicsr 16 | RISCV_MABI ?= ilp32 17 | RISCV_PREFIX ?= riscv64-unknown-elf- 18 | RISCV_CC ?= $(RISCV_PREFIX)gcc 19 | RISCV_CXX ?= $(RISCV_PREFIX)g++ 20 | RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump 21 | RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy 22 | RISCV_AS ?= $(RISCV_PREFIX)as 23 | RISCV_AR ?= $(RISCV_PREFIX)ar 24 | RISCV_LD ?= $(RISCV_PREFIX)ld 25 | RISCV_STRIP ?= $(RISCV_PREFIX)strip 26 | 27 | RISCV_FLAGS ?= -march=$(RISCV_MARCH) -mabi=$(RISCV_MABI) -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding 28 | RISCV_CCFLAGS ?= $(RISCV_FLAGS) -Iinclude -I$(INCDIR) -I$(CURDIR) 29 | RISCV_LDFLAGS ?= -static -nostartfiles -lm -lgcc $(RISCV_FLAGS) 30 | 31 | # all 32 | 33 | all: compile 34 | 35 | # Building defaults 36 | 37 | BINDIR ?= bin 38 | CRT0 ?= crt0.S 39 | LINK ?= link.ld 40 | 41 | LIB_SOURCES := $(wildcard $(SRCDIR)/*.[cS]) 42 | LIB_OBJS := $(LIB_SOURCES:$(SRCDIR)/%=$(SRCDIR)/%.o) 43 | 44 | # Build all assembly and C files in the top level as seperate binaries 45 | TOP_SOURCES ?= $(filter-out $(CRT0), $(wildcard *.[cS])) 46 | TOP_BASENAMES := $(basename $(TOP_SOURCES)) 47 | TOP_OBJS := $(TOP_BASENAMES:=.o) 48 | ALL_TARGETS := $(TOP_BASENAMES:%=$(BINDIR)/%.elf) $(TOP_BASENAMES:%=$(BINDIR)/%.dump) $(TOP_BASENAMES:%=$(BINDIR)/%.hex) 49 | 50 | 51 | $(BINDIR): 52 | mkdir -p $(BINDIR) 53 | 54 | %.S.o: %.S 55 | $(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@ 56 | 57 | %.c.o: %.c 58 | $(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@ 59 | 60 | $(BINDIR)/%.elf: %.S.o $(CRT0).o $(LIB_OBJS) | $(BINDIR) 61 | $(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK) 62 | 63 | $(BINDIR)/%.elf: %.c.o $(CRT0).o $(LIB_OBJS) | $(BINDIR) 64 | $(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK) 65 | 66 | $(BINDIR)/%.dump: $(BINDIR)/%.elf 67 | $(RISCV_OBJDUMP) -D -s $< >$@ 68 | 69 | $(BINDIR)/%.hex: $(BINDIR)/%.elf 70 | $(RISCV_OBJCOPY) -O verilog $< $@ 71 | 72 | # Phonies 73 | .PHONY: all clean compile 74 | 75 | clean: 76 | rm -rf $(BINDIR) 77 | rm -f *.o 78 | 79 | compile: $(BINDIR) $(ALL_TARGETS) 80 | -------------------------------------------------------------------------------- /sw/config.h: -------------------------------------------------------------------------------- 1 | // Copyright 2022 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Nils Wistoff 6 | // Paul Scheffler 7 | 8 | #pragma once 9 | 10 | // Address map 11 | #define SOCCTRL_BASE_ADDR 0x03000000 12 | #define UART_BASE_ADDR 0x03002000 13 | #define GPIO_BASE_ADDR 0x03005000 14 | #define TIMER_BASE_ADDR 0x0300A000 15 | 16 | // Frequencies 17 | #define TB_FREQUENCY 20000000 18 | #define TB_BAUDRATE 115200 19 | 20 | // Peripheral configs 21 | // UART 22 | #define UART_BYTE_ALIGN 4 23 | #define UART_FREQ TB_FREQUENCY 24 | #define UART_BAUD TB_BAUDRATE -------------------------------------------------------------------------------- /sw/crt0.S: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Paul Scheffler 7 | # - Philippe Sauter 8 | 9 | .globl _start 10 | .section .text._start 11 | _start: 12 | # Global pointer 13 | .option push 14 | .option norelax 15 | la x3, __global_pointer$ 16 | .option pop 17 | # Stack pointer 18 | la x2, __stack_pointer$ 19 | # Reset vector 20 | li x1, 0 21 | li x4, 0 22 | li x5, 0 23 | li x6, 0 24 | li x7, 0 25 | li x8, 0 26 | li x9, 0 27 | li x10, 0 28 | li x11, 0 29 | li x12, 0 30 | li x13, 0 31 | li x14, 0 32 | li x15, 0 33 | call main 34 | _eoc: 35 | la t0, status 36 | sw a0, 0(t0) 37 | wfi 38 | -------------------------------------------------------------------------------- /sw/helloworld.c: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0/ 4 | // 5 | // Authors: 6 | // - Philippe Sauter 7 | 8 | #include "uart.h" 9 | #include "print.h" 10 | #include "timer.h" 11 | #include "gpio.h" 12 | #include "util.h" 13 | 14 | /// @brief Example integer square root 15 | /// @return integer square root of n 16 | uint32_t isqrt(uint32_t n) { 17 | uint32_t res = 0; 18 | uint32_t bit = (uint32_t)1 << 30; 19 | 20 | while (bit > n) bit >>= 2; 21 | 22 | while (bit) { 23 | if (n >= res + bit) { 24 | n -= res + bit; 25 | res = (res >> 1) + bit; 26 | } else { 27 | res >>= 1; 28 | } 29 | bit >>= 2; 30 | } 31 | return res; 32 | } 33 | 34 | int main() { 35 | uart_init(); // setup the uart peripheral 36 | 37 | // simple printf support (only prints text and hex numbers) 38 | printf("Hello World!\n"); 39 | // wait until uart has finished sending 40 | uart_write_flush(); 41 | 42 | // toggling some GPIOs 43 | gpio_set_direction(0xFFFF, 0x000F); // lowest four as outputs 44 | gpio_write(0x0A); // ready output pattern 45 | gpio_enable(0xFF); // enable lowest eight 46 | // wait a few cycles to give GPIO signal time to propagate 47 | asm volatile ("nop; nop; nop; nop; nop;"); 48 | printf("GPIO (expect 0xA0): 0x%x\n", gpio_read()); 49 | 50 | gpio_toggle(0x0F); // toggle lower 8 GPIOs 51 | asm volatile ("nop; nop; nop; nop; nop;"); 52 | printf("GPIO (expect 0x50): 0x%x\n", gpio_read()); 53 | uart_write_flush(); 54 | 55 | // doing some compute 56 | uint32_t start = get_mcycle(); 57 | uint32_t res = isqrt(1234567890UL); 58 | uint32_t end = get_mcycle(); 59 | printf("Result: 0x%x, Cycles: 0x%x\n", res, end - start); 60 | uart_write_flush(); 61 | 62 | // using the timer 63 | printf("Tick\n"); 64 | sleep_ms(10); 65 | printf("Tock\n"); 66 | uart_write_flush(); 67 | return 1; 68 | } 69 | -------------------------------------------------------------------------------- /sw/lib/inc/gpio.h: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Philippe Sauter 6 | 7 | #pragma once 8 | 9 | #include 10 | #include "config.h" 11 | 12 | 13 | #define GPIO_DIR_REG_OFFSET 0x000 14 | #define GPIO_EN_REG_OFFSET 0x080 15 | #define GPIO_IN_REG_OFFSET 0x100 16 | #define GPIO_OUT_REG_OFFSET 0x180 17 | #define GPIO_TOGGLE_REG_OFFSET 0x200 18 | #define GPIO_INTRPT_EN_REG_OFFSET 0x280 19 | #define GPIO_INTRPT_STATUS_REG_OFFSET 0x300 20 | #define GPIO_INTRPT_EDGE_REG_OFFSET 0x380 21 | 22 | // functions applying to all 32 GPIOs with mask 23 | // a 1 in the mask applies action to this GPIO pin 24 | // LSB is considered GPIO number 0 25 | void gpio_set_direction(uint32_t mask, uint32_t direction); // 1: output 26 | void gpio_enable(uint32_t mask); 27 | void gpio_disable(uint32_t mask); 28 | 29 | void gpio_write(uint32_t value); 30 | void gpio_toggle(uint32_t mask); 31 | uint32_t gpio_read(void); 32 | 33 | void gpio_enable_rising_interrupts(uint32_t mask); 34 | void gpio_enable_falling_interrupts(uint32_t mask); 35 | void gpio_disable_interrupts(uint32_t mask); 36 | uint32_t gpio_get_interrupt_status(void); 37 | 38 | // functions applying to only one GPIO pin 39 | // LSB is considered GPIO number 0 40 | void gpio_pin_set_output(uint8_t gpio_pin); 41 | void gpio_pin_enable(uint8_t gpio_pin); 42 | void gpio_pin_disable(uint8_t gpio_pin); 43 | 44 | void gpio_pin_set(uint8_t gpio_pin); 45 | void gpio_pin_clear(uint8_t gpio_pin); 46 | void gpio_pin_toggle(uint8_t gpio_pin); 47 | uint8_t gpio_pin_read(uint8_t gpio_pin); 48 | 49 | void gpio_pin_enable_rising_interrupt(uint8_t gpio_pin); 50 | void gpio_pin_enable_falling_interrupt(uint8_t gpio_pin); 51 | void gpio_pin_disable_interrupts(uint8_t gpio_pin); 52 | uint8_t gpio_pin_get_interrupt_status(uint8_t gpio_pin); 53 | -------------------------------------------------------------------------------- /sw/lib/inc/print.h: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Philippe Sauter 6 | 7 | #pragma once 8 | 9 | #include 10 | 11 | extern void putchar(char); 12 | 13 | // simple printf with support for %x formatter but no others 14 | void printf(const char *fmt, ...); 15 | -------------------------------------------------------------------------------- /sw/lib/inc/soc_ctrl.h: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Philippe Sauter 6 | 7 | #pragma once 8 | 9 | #define SOC_CTRL_BOOTADDR_REG_OFFSET 0x00 10 | #define SOC_CTRL_FETCHEN_REG_OFFSET 0x04 11 | #define SOC_CTRL_CORESTATUS_REG_OFFSET 0x08 12 | -------------------------------------------------------------------------------- /sw/lib/inc/timer.h: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Philippe Sauter 6 | 7 | #pragma once 8 | 9 | #include 10 | #include "config.h" 11 | 12 | // Register offsets 13 | #define CFG_LOW_REG_OFFSET 0x00 14 | #define CFG_HIGH_REG_OFFSET 0x04 15 | #define TIMER_VALUE_LOW_REG_OFFSET 0x08 16 | #define TIMER_VALUE_HIGH_REG_OFFSET 0x0C 17 | #define TIMER_CMP_LOW_REG_OFFSET 0x10 18 | #define TIMER_CMP_HIGH_REG_OFFSET 0x14 19 | #define TIMER_START_LOW_REG_OFFSET 0x18 20 | #define TIMER_START_HIGH_REG_OFFSET 0x1C 21 | #define TIMER_RESET_LOW_REG_OFFSET 0x20 22 | #define TIMER_RESET_HIGH_REG_OFFSET 0x24 23 | 24 | // Register fields 25 | #define CFG_LOW_REG_ENABLE_BIT 0 26 | #define CFG_LOW_REG_RESET_BIT 1 27 | #define CFG_LOW_REG_IRQ_ENABLE_BIT 2 28 | #define CFG_LOW_REG_CMP_CLR_BIT 4 29 | #define CFG_LOW_REG_ONE_SHOT_BIT 5 30 | #define CFG_LOW_REG_PRESC_ENABLE_BIT 6 31 | #define CFG_LOW_REG_CLOCK_SOURCE_BIT 7 32 | #define CFG_LOW_REG_PRESC_VALUE_BIT 8 // 15:8 33 | #define CFG_LOW_REG_64BIT_MODE_BIT 31 34 | 35 | #define CFG_HIGH_REG_ENABLE_BIT 0 36 | #define CFG_HIGH_REG_RESET_BIT 1 37 | #define CFG_HIGH_REG_IRQ_ENABLE_BIT 2 38 | #define CFG_HIGH_REG_CMP_CLR_BIT 4 39 | #define CFG_HIGH_REG_ONE_SHOT_BIT 5 40 | #define CFG_HIGH_REG_PRESC_ENABLE_BIT 6 41 | #define CFG_HIGH_REG_CLOCK_SOURCE_BIT 7 42 | 43 | void sleep_ms(uint32_t ms); 44 | -------------------------------------------------------------------------------- /sw/lib/inc/uart.h: -------------------------------------------------------------------------------- 1 | // Copyright 2022 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Nils Wistoff 6 | // Paul Scheffler 7 | 8 | #pragma once 9 | 10 | #include 11 | #include "config.h" 12 | 13 | // Registers below can be aligned to a byte, word, dword etc 14 | // UART_BYTE_ALIGN provides the number of bytes it is aligned to 15 | 16 | 17 | // Register offsets 18 | #define UART_RBR_REG_OFFSET (0*UART_BYTE_ALIGN) // Receive Buffer Register 19 | #define UART_THR_REG_OFFSET (0*UART_BYTE_ALIGN) // Transmitter Holding Register 20 | #define UART_INTR_ENABLE_REG_OFFSET (1*UART_BYTE_ALIGN) 21 | #define UART_INTR_IDENT_REG_OFFSET (2*UART_BYTE_ALIGN) 22 | #define UART_FIFO_CONTROL_REG_OFFSET (2*UART_BYTE_ALIGN) 23 | #define UART_LINE_CONTROL_REG_OFFSET (3*UART_BYTE_ALIGN) 24 | #define UART_MODEM_CONTROL_REG_OFFSET (4*UART_BYTE_ALIGN) 25 | #define UART_LINE_STATUS_REG_OFFSET (5*UART_BYTE_ALIGN) 26 | #define UART_MODEM_STATUS_REG_OFFSET (6*UART_BYTE_ALIGN) 27 | #define UART_SCRATCH_REG_OFFSET (7*UART_BYTE_ALIGN) 28 | #define UART_DLAB_LSB_REG_OFFSET (0*UART_BYTE_ALIGN) 29 | #define UART_DLAB_MSB_REG_OFFSET (1*UART_BYTE_ALIGN) 30 | 31 | // Register fields 32 | #define UART_LINE_STATUS_DATA_READY_BIT 0 33 | #define UART_LINE_STATUS_THR_EMPTY_BIT 5 34 | #define UART_LINE_STATUS_TMIT_EMPTY_BIT 6 35 | 36 | void uart_init(); 37 | 38 | int uart_read_ready(); 39 | 40 | void uart_write(uint8_t byte); 41 | 42 | void uart_write_str(void *src, uint32_t len); 43 | 44 | void uart_write_flush(); 45 | 46 | uint8_t uart_read(); 47 | 48 | void uart_read_str(void *dst, uint32_t len); 49 | 50 | void putchar(char byte); 51 | 52 | char getchar(); 53 | -------------------------------------------------------------------------------- /sw/lib/src/print.c: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Philippe Sauter 6 | 7 | #include "print.h" 8 | #include "util.h" 9 | #include "config.h" 10 | 11 | const char hex_symbols[16] = {'0', '1', '2', '3', '4', '5', '6', '7', 12 | '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; 13 | 14 | /// @brief format number as hexadecimal digits 15 | /// @return number of characters written to buffer 16 | uint8_t format_hex32(char *buffer, uint32_t num) { 17 | uint8_t idx = 0; 18 | if (num == 0) { 19 | buffer[0] = hex_symbols[0]; 20 | return 1; 21 | } 22 | 23 | while (num > 0) { 24 | buffer[idx++] = hex_symbols[num & 0xF]; 25 | num >>= 4; 26 | } 27 | return idx; 28 | } 29 | 30 | void printf(const char *fmt, ...) { 31 | va_list args; 32 | va_start(args, fmt); 33 | char buffer[12]; // holds string while assembling 34 | uint8_t idx; 35 | 36 | while (*fmt) { 37 | if (*fmt == '%') { 38 | fmt++; 39 | if (*fmt == 'x') { // hex 40 | idx = format_hex32(buffer, va_arg(args, unsigned int)); 41 | // print from buffer 42 | for (int j = idx - 1; j >= 0; j--) { 43 | putchar(buffer[j]); 44 | } 45 | } 46 | } else { 47 | putchar(*fmt); 48 | } 49 | fmt++; 50 | } 51 | 52 | va_end(args); 53 | } 54 | -------------------------------------------------------------------------------- /sw/lib/src/timer.c: -------------------------------------------------------------------------------- 1 | // Copyright 2024 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // Philippe Sauter 6 | 7 | #include "timer.h" 8 | #include "util.h" 9 | #include "config.h" 10 | 11 | void sleep_ms(uint32_t ms) { 12 | uint32_t config = \ 13 | (1 << CFG_LOW_REG_CLOCK_SOURCE_BIT) | // from 32.768 kHz ref clock 14 | (1 << CFG_LOW_REG_PRESC_ENABLE_BIT) | // enable prescaler 15 | (31 << CFG_LOW_REG_PRESC_VALUE_BIT) | // prescaler value 16 | (1 << CFG_LOW_REG_CMP_CLR_BIT) | // auto-clear 17 | (1 << CFG_LOW_REG_IRQ_ENABLE_BIT) | // enable IRQ 18 | (1 << CFG_LOW_REG_ENABLE_BIT); // enable timer 19 | 20 | // disable timer 21 | *reg32(TIMER_BASE_ADDR, CFG_LOW_REG_OFFSET) = 0; 22 | 23 | *reg32(TIMER_BASE_ADDR, TIMER_CMP_LOW_REG_OFFSET) = ms; 24 | 25 | set_mtie(1); // Machine Timer Interrupt Enable 26 | set_mie(1); // Global Interrupt Enable 27 | 28 | // start timer 29 | *reg32(TIMER_BASE_ADDR, CFG_LOW_REG_OFFSET) = config; 30 | 31 | asm volatile("wfi"); 32 | 33 | // turn off timer 34 | *reg32(TIMER_BASE_ADDR, CFG_LOW_REG_OFFSET) &= ~(1 << CFG_LOW_REG_ENABLE_BIT); 35 | 36 | // disable timer interrupt 37 | set_mtie(0); 38 | } 39 | -------------------------------------------------------------------------------- /sw/link.ld: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | * Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | * SPDX-License-Identifier: Apache-2.0 4 | * 5 | * Authors: 6 | * - Paul Scheffler 7 | * - Philippe Sauter 8 | */ 9 | 10 | OUTPUT_ARCH("riscv") 11 | ENTRY(_start) 12 | 13 | MEMORY 14 | { 15 | SRAM (rwxail) : ORIGIN = 0x10000000, LENGTH = 4K 16 | } 17 | 18 | SECTIONS 19 | { 20 | /DISCARD/ : { *(.riscv.attributes) *(.comment) } 21 | 22 | .text._start 0x10000000 : { *(.text._start) } >SRAM 23 | .text : { *(.text) *(.text.*) } >SRAM 24 | .misc : { *(.sdata) *(.*) } >SRAM 25 | 26 | __global_pointer$ = ADDR(.misc) + SIZEOF(.misc) / 2; 27 | __stack_pointer$ = ORIGIN(SRAM) + LENGTH(SRAM); 28 | 29 | status = 0x03000008; 30 | } 31 | -------------------------------------------------------------------------------- /verilator/.gitignore: -------------------------------------------------------------------------------- 1 | obj_dir 2 | croc*.f 3 | *.vcd 4 | -------------------------------------------------------------------------------- /verilator/tech.f: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | 9 | +define+TARGET_IHP13 10 | +define+TARGET_NETLIST_YOSYS 11 | +define+TARGET_SYNTHESIS 12 | +define+TARGET_VERILATOR 13 | +define+SYNTHESIS 14 | +define+VERILATOR 15 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v 16 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v 17 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v 18 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v 19 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v 20 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v 21 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v 22 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v 23 | ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v -------------------------------------------------------------------------------- /vsim/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | compile_rtl.tcl 3 | compile_netlist.tcl 4 | transcript 5 | vsim.wlf 6 | modelsim.ini 7 | *.vcd 8 | -------------------------------------------------------------------------------- /vsim/compile_tech.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | if {[catch { vlog -incr -sv \ 9 | +define+FUNCTIONAL \ 10 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v" \ 11 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v" \ 12 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v" \ 13 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v" \ 14 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v" \ 15 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \ 16 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \ 17 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ 18 | "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \ 19 | "$ROOT/ihp13/tc_sram.sv" \ 20 | "$ROOT/ihp13/tc_clk.sv" \ 21 | }]} {return 1} -------------------------------------------------------------------------------- /vsim/wave_yosys.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/rst_ni 4 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/clk_i 5 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/ref_clk_i 6 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/jtag_tck_i 7 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/jtag_tdi_i 8 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/jtag_tdo_o 9 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/jtag_tms_i 10 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/jtag_trst_ni 11 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_addr_o 12 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_be_o 13 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_gnt_i 14 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_rdata_i 15 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_req_o 16 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_rvalid_i 17 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_wdata_o 18 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/data_we_o 19 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/fetch_enable_i 20 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_addr_o 21 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_gnt_i 22 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_rdata_i 23 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_req_o 24 | add wave -noupdate /tb_croc_soc/i_croc_soc/i_croc/i_core_wrap/instr_rvalid_i 25 | update -------------------------------------------------------------------------------- /xilinx/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | out 3 | scripts/add_sources.genesys2.tcl 4 | 5 | -------------------------------------------------------------------------------- /xilinx/hw/fan_ctrl.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | // SPDX-License-Identifier: SHL-0.51 4 | // 5 | // Author: Florian Zaruba, zarubaf@iis.ee.ethz.ch 6 | // Description: PWM Fan Control for Genesys II board 7 | 8 | module fan_ctrl ( 9 | input logic clk_i, 10 | input logic rst_ni, 11 | input logic [3:0] pwm_setting_i, 12 | output logic fan_pwm_o 13 | ); 14 | logic [3:0] ms_clock_d, ms_clock_q; 15 | logic [11:0] cycle_counter_d, cycle_counter_q; 16 | 17 | // clock divider 18 | always_comb begin 19 | cycle_counter_d = cycle_counter_q + 1; 20 | ms_clock_d = ms_clock_q; 21 | 22 | // divide clock by 49 23 | // At 50 MHz input clock this results in a 62.5 kHz 24 | // PWM Signal 25 | if (cycle_counter_q == 49) begin 26 | cycle_counter_d = 0; 27 | ms_clock_d = ms_clock_q + 1; 28 | end 29 | 30 | if (ms_clock_q == 15) begin 31 | ms_clock_d = 0; 32 | end 33 | end 34 | 35 | // duty cycle 36 | always_comb begin 37 | if (ms_clock_q < pwm_setting_i) begin 38 | fan_pwm_o = 1'b1; 39 | end else begin 40 | fan_pwm_o = 1'b0; 41 | end 42 | end 43 | 44 | always_ff @(posedge clk_i or negedge rst_ni) begin 45 | if (~rst_ni) begin 46 | ms_clock_q <= '0; 47 | cycle_counter_q <= '0; 48 | end else begin 49 | ms_clock_q <= ms_clock_d; 50 | cycle_counter_q <= cycle_counter_d; 51 | end 52 | end 53 | endmodule -------------------------------------------------------------------------------- /xilinx/implement.sh: -------------------------------------------------------------------------------- 1 | bender script vivado -t fpga -t rtl -t genesys2 > scripts/add_sources.genesys2.tcl 2 | mkdir -p build/genesys2.clkwiz 3 | cd build/genesys2.clkwiz && \ 4 | vitis-2022.1 vivado -mode batch -log ../genesys2.clkwiz.log -jou ../genesys2.clkwiz.jou \ 5 | -source ../../scripts/impl_ip.tcl \ 6 | -tclargs genesys2 clkwiz \ 7 | && cd ../.. 8 | mkdir -p build/genesys2.vio 9 | cd build/genesys2.vio && 10 | vitis-2022.1 vivado -mode batch -log ../genesys2.vio.log -jou ../genesys2.vio.jou \ 11 | -source ../../scripts/impl_ip.tcl \ 12 | -tclargs genesys2 vio\ 13 | && cd ../.. 14 | mkdir -p build/genesys2.croc 15 | cd build/genesys2.croc && \ 16 | vitis-2022.1 vivado -mode batch -log ../croc.genesys2.log -jou ../croc.genesys2.jou \ 17 | -source ../../scripts/impl_sys.tcl \ 18 | -tclargs genesys2 croc \ 19 | ../genesys2.clkwiz/out.xci \ 20 | ../genesys2.vio/out.xci 21 | -------------------------------------------------------------------------------- /xilinx/scripts/impl_ip.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | # 5 | # Florian Zaruba 6 | # Cyril Koenig 7 | # Paul Scheffler 8 | 9 | # Initialize implementation 10 | set xilinx_root [file dirname [file dirname [file normalize [info script]]]] 11 | source ${xilinx_root}/scripts/common.tcl 12 | init_impl $xilinx_root $argc $argv 13 | 14 | # Create and configure selected IP 15 | switch $proj { 16 | 17 | clkwiz { 18 | create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $proj 19 | set_property -dict [list \ 20 | CONFIG.PRIM_SOURCE {No_buffer} \ 21 | CONFIG.PRIM_IN_FREQ {200.000} \ 22 | CONFIG.CLKOUT1_USED {true} \ 23 | CONFIG.CLK_OUT1_PORT {clk_20} \ 24 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \ 25 | CONFIG.CLKIN1_JITTER_PS {50.0} \ 26 | CONFIG.MMCM_CLKFBOUT_MULT_F {6.000} \ 27 | CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ 28 | CONFIG.MMCM_CLKOUT1_DIVIDE {60} \ 29 | CONFIG.NUM_OUT_CLKS {1} \ 30 | CONFIG.CLKOUT1_JITTER {155.330} \ 31 | CONFIG.CLKOUT1_PHASE_ERROR {89.971} \ 32 | ] [get_ips $proj] 33 | } 34 | 35 | vio { 36 | create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $proj 37 | set_property -dict [list \ 38 | CONFIG.C_NUM_PROBE_OUT {3} \ 39 | CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ 40 | CONFIG.C_PROBE_OUT1_INIT_VAL {0x0} \ 41 | CONFIG.C_PROBE_OUT2_INIT_VAL {0x0} \ 42 | CONFIG.C_PROBE_OUT1_WIDTH {2} \ 43 | CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ 44 | CONFIG.C_NUM_PROBE_IN {0} \ 45 | ] [get_ips $proj] 46 | } 47 | } 48 | 49 | # Generate targets 50 | set xci ${project_root}/${proj}.srcs/sources_1/ip/${proj}/${proj}.xci 51 | generate_target all [get_files $xci] 52 | 53 | # Synthesize proj 54 | create_ip_run [get_files -of_objects [get_fileset sources_1] $xci] 55 | launch_run -jobs $num_jobs ${proj}_synth_1 56 | wait_on_run ${proj}_synth_1 57 | 58 | # Symlink proj for easy access and build tracking, ensuring its update 59 | file delete -force ${project_root}/out.xci 60 | file link -symbolic ${project_root}/out.xci $xci 61 | -------------------------------------------------------------------------------- /xilinx/scripts/openocd.genesys2.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # OpenOCD script for Cheshire on Genesys2. 6 | 7 | adapter_khz 2000 8 | interface ftdi 9 | ftdi_vid_pid 0x0403 0x6010 10 | ftdi_layout_init 0x00e8 0x60eb 11 | ftdi_channel 0 12 | set irlen 5 13 | 14 | transport select jtag 15 | telnet_port disabled 16 | tcl_port disabled 17 | reset_config none 18 | 19 | set _CHIPNAME riscv 20 | jtag newtap $_CHIPNAME cpu -irlen ${irlen} -expected-id 0x0c0c5db3 21 | 22 | set _TARGETNAME $_CHIPNAME.cpu 23 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 24 | 25 | gdb_report_data_abort enable 26 | gdb_report_register_access_error enable 27 | 28 | riscv set_reset_timeout_sec 120 29 | riscv set_command_timeout_sec 120 30 | 31 | riscv set_prefer_sba off 32 | 33 | # Try enabling address translation (only works for newer versions) 34 | if { [catch { riscv set_enable_virtual on } ] } { 35 | echo "Warning: This version of OpenOCD does not support address translation.\ 36 | To debug on virtual addresses, please update to the latest version." 37 | } 38 | 39 | init 40 | halt 41 | echo "Ready for Remote Connections" 42 | -------------------------------------------------------------------------------- /yosys/.gitignore: -------------------------------------------------------------------------------- 1 | reports 2 | out 3 | WORK 4 | tmp 5 | *.log -------------------------------------------------------------------------------- /yosys/scripts/abc-opt.script: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2022 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | # 8 | # Optimization script utilizing 'Lazy Mans Synthesis' 9 | # Requires the library of 6-input records (src/rec6Lib...) 10 | # https://people.eecs.berkeley.edu/~alanmi/publications/2012/iccad12_lms.pdf 11 | 12 | print_stats 13 | 14 | # strash can fix some yosys-convertion edge-cases, good idea to run first 15 | strash 16 | 17 | rec_start3 src/lazy_man_synth_library.aig 18 | 19 | # main optimization iteration: 20 | alias &opt_iter "&st; &if -y -K 6; &syn2; &if -K 6; &st; &b" 21 | # &if -y -K 6; &syn2; &if -K 6, see LMS paper 22 | # &dc2 AIG rewriting (greedy minimization) 23 | # &b balance structure for depth 24 | # &st structural hashing 25 | # &dc compute structural choices 26 | # &nf select choice and map to tech 27 | # &ps print statistics 28 | # mapping iteration 29 | alias &map_iter "&st; &nf {D}; &ps" 30 | 31 | # initial mapping iteration 32 | &get -n 33 | echo "Initial network:" 34 | &ps 35 | echo "High effort delay optimization..." 36 | &opt_iter; &opt_iter; &ps; 37 | &opt_iter; &opt_iter; &ps; 38 | &opt_iter; &opt_iter; &ps; 39 | &opt_iter; &opt_iter; &ps; 40 | &put 41 | 42 | # according to https://people.eecs.berkeley.edu/~alanmi/abc/ 43 | # it can take up to 10-ish iterations for convergence 44 | # in my experience it seems to get 99% there after 5-6 with a lower runtime 45 | &get -n 46 | echo "Opt+mapping Iterations..." 47 | &opt_iter; &map_iter; 48 | &opt_iter; &map_iter; 49 | &opt_iter; &map_iter; 50 | &opt_iter; &map_iter; 51 | &opt_iter; &map_iter; 52 | &opt_iter; &map_iter; 53 | &opt_iter; &map_iter; 54 | &opt_iter; &map_iter; 55 | &put 56 | 57 | 58 | topo 59 | stime 60 | 61 | echo "buffering for delay and fanout..." 62 | buffer -p 63 | echo "resizing cells..." 64 | upsize {D} 65 | dnsize {D} 66 | upsize {D} 67 | dnsize {D} 68 | 69 | echo "Final timing:" 70 | stime 71 | -------------------------------------------------------------------------------- /yosys/scripts/filter_output.awk: -------------------------------------------------------------------------------- 1 | BEGIN { 2 | IGNORECASE=1 3 | capture = 0 4 | RED = "\033[31m" 5 | YELLOW = "\033[33m" 6 | RESET = "\033[0m" 7 | } 8 | 9 | /Executing SLANG frontend/ { 10 | # Start capturing when we find "Executing SLANG frontend" 11 | capture = 1 12 | gsub(/\/, YELLOW "Warning" RESET) 13 | gsub(/\/, RED "Error" RESET) 14 | print 15 | next 16 | } 17 | 18 | capture { 19 | gsub(/\/, YELLOW "Warning" RESET) 20 | gsub(/\/, RED "Error" RESET) 21 | print 22 | if ($0 ~ /Executing/ && $0 !~ /SLANG frontend/) { 23 | capture = 0 24 | } 25 | } 26 | 27 | /Executing/ { 28 | if ($0 ~ /[0-9\.]+ Executing/) { 29 | gsub(/\/, YELLOW "Warning" RESET) 30 | gsub(/\/, RED "Error" RESET) 31 | print 32 | } 33 | } 34 | 35 | /\|\/ { 36 | gsub(/\/, YELLOW "Warning" RESET) 37 | gsub(/\/, RED "Error" RESET) 38 | print 39 | } -------------------------------------------------------------------------------- /yosys/scripts/init_tech.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2022 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | # All paths relative to yosys/ 9 | 10 | if {[file exists "../technology"]} { 11 | puts "0. Executing init_tech: load technology from ETHZ DZ cockpit" 12 | set pdk_dir "../technology" 13 | set pdk_cells_lib ${pdk_dir}/lib 14 | set pdk_sram_lib ${pdk_dir}/lib 15 | set pdk_io_lib ${pdk_dir}/lib 16 | } else { 17 | puts "0. Executing init_tech: load technology from Github PDK" 18 | if {![info exists pdk_dir]} { 19 | set pdk_dir "../ihp13/pdk" 20 | } 21 | set pdk_cells_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib 22 | set pdk_sram_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_sram/lib 23 | set pdk_io_lib ${pdk_dir}/ihp-sg13g2/libs.ref/sg13g2_io/lib 24 | } 25 | 26 | set tech_cells [list "$pdk_cells_lib/sg13g2_stdcell_typ_1p20V_25C.lib"] 27 | set tech_macros [glob -directory $pdk_sram_lib *_typ_1p20V_25C.lib] 28 | lappend tech_macros "$pdk_io_lib/sg13g2_io_typ_1p2V_3p3V_25C.lib" 29 | 30 | # for hilomap 31 | set tech_cell_tiehi {sg13g2_tiehi L_HI} 32 | set tech_cell_tielo {sg13g2_tielo L_LO} 33 | 34 | # pre-formated for easier use in yosys commands 35 | # all liberty files 36 | set lib_list [concat [split $tech_cells] [split $tech_macros] ] 37 | set liberty_args_list [lmap lib $lib_list {concat "-liberty" $lib}] 38 | set liberty_args [concat {*}$liberty_args_list] 39 | # only the standard cells 40 | set tech_cells_args_list [lmap lib $tech_cells {concat "-liberty" $lib}] 41 | set tech_cells_args [concat {*}$tech_cells_args_list] 42 | 43 | # read library files 44 | foreach file $lib_list { 45 | yosys read_liberty -lib "$file" 46 | } -------------------------------------------------------------------------------- /yosys/scripts/yosys_common.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2022 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | # Preparation for the synthesis flow 9 | # A common setup to provide some functionality and define variables 10 | 11 | # list of global variables that may be used 12 | # define with scheme: { } 13 | set variables { 14 | sv_flist { SV_FLIST "../croc.flist" } 15 | top_design { TOP_DESIGN "croc_chip" } 16 | out_dir { OUT out } 17 | tmp_dir { TMP tmp } 18 | rep_dir { REPORTS reports } 19 | } 20 | 21 | 22 | # check if an env-var exists and is non-empty 23 | proc envVarValid {var_name} { 24 | if { [info exists ::env($var_name)]} { 25 | if {$::env($var_name) != "0" && $::env($var_name) ne ""} { 26 | return 1 27 | } 28 | } 29 | return 0 30 | } 31 | 32 | # If the ENVVAR is valid use it, otherwise use fallback 33 | foreach var [dict keys $variables] { 34 | set values [dict get $variables $var] 35 | set env_var [lindex $values 0] 36 | set fallback [lindex $values 1] 37 | 38 | if {[envVarValid $env_var]} { 39 | puts "using: $var= '$::env($env_var)'" 40 | set $var $::env($env_var) 41 | } 42 | } 43 | 44 | # process ABC script and write to temporary directory 45 | proc processAbcScript {abc_script} { 46 | global tmp_dir 47 | set src_dir [file join [file dirname [info script]] ../src] 48 | set abc_out_path $tmp_dir/[file tail $abc_script] 49 | 50 | # substitute {STRING} placeholders with their value 51 | set raw [read -nonewline [open $abc_script r]] 52 | set abc_script_recaig [string map -nocase [list "{REC_AIG}" [subst "$src_dir/lazy_man_synth_library.aig"]] $raw] 53 | set abc_out [open $abc_out_path w] 54 | puts -nonewline $abc_out $abc_script_recaig 55 | 56 | flush $abc_out 57 | close $abc_out 58 | return $abc_out_path 59 | } -------------------------------------------------------------------------------- /yosys/src/abc.constr: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | set_driving_cell sg13g2_buf_1 9 | set_load 0.015 10 | -------------------------------------------------------------------------------- /yosys/src/lazy_man_synth_library.aig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/croc/b44242be749da0b533b7688c65376e15cc795d07/yosys/src/lazy_man_synth_library.aig -------------------------------------------------------------------------------- /yosys/yosys.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2022 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | # 5 | # Authors: 6 | # - Philippe Sauter 7 | 8 | # Tools 9 | YOSYS ?= yosys 10 | 11 | # Directories 12 | # directory of the path to the last called Makefile (this one) 13 | YOSYS_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST))))) 14 | YOSYS_OUT := $(YOSYS_DIR)/out 15 | YOSYS_TMP := $(YOSYS_DIR)/tmp 16 | YOSYS_REPORTS := $(YOSYS_DIR)/reports 17 | 18 | # top level to be synthesized 19 | TOP_DESIGN ?= croc_chip 20 | 21 | # file containing include dirs, defines and paths to all source files 22 | SV_FLIST := $(realpath $(YOSYS_DIR)/..)/croc.flist 23 | 24 | # path to the resulting netlists (debug preserves multibit signals) 25 | NETLIST := $(YOSYS_OUT)/$(TOP_DESIGN)_yosys.v 26 | NETLIST_DEBUG := $(YOSYS_OUT)/$(TOP_DESIGN)_debug_yosys.v 27 | 28 | 29 | ## Synthesize netlist using Yosys 30 | yosys: $(NETLIST) 31 | 32 | $(NETLIST) $(NETLIST_DEBUG): $(SV_FLIST) 33 | @mkdir -p $(YOSYS_OUT) 34 | @mkdir -p $(YOSYS_TMP) 35 | @mkdir -p $(YOSYS_REPORTS) 36 | cd $(YOSYS_DIR) && \ 37 | SV_FLIST="$(SV_FLIST)" \ 38 | TOP_DESIGN="$(TOP_DESIGN)" \ 39 | TMP="$(YOSYS_TMP)" \ 40 | OUT="$(YOSYS_OUT)" \ 41 | REPORTS="$(YOSYS_REPORTS)" \ 42 | $(YOSYS) -c $(YOSYS_DIR)/scripts/yosys_synthesis.tcl \ 43 | 2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $$0 }' \ 44 | | tee "$(YOSYS_DIR)/$(TOP_DESIGN).log" \ 45 | | gawk -f $(YOSYS_DIR)/scripts/filter_output.awk; 46 | 47 | 48 | ys_clean: 49 | rm -rf $(YOSYS_OUT) 50 | rm -rf $(YOSYS_TMP) 51 | rm -rf $(YOSYS_REPORTS) 52 | rm -f $(YOSYS_DIR)/$(TOP_DESIGN).log 53 | 54 | .PHONY: ys_clean yosys 55 | --------------------------------------------------------------------------------