├── .editorconfig ├── .github ├── ISSUE_TEMPLATE │ ├── bug.yaml │ └── task.yaml ├── dependabot.yml └── workflows │ ├── bender-up-to-date.yml │ ├── ci.yml │ ├── dashboard-done.yml │ ├── integration.yml │ ├── stale.yml │ └── verible.yml ├── .gitignore ├── .gitlab-ci.yml ├── .gitlab-ci ├── README.md ├── expected_synth.yml ├── scripts │ ├── github_integration.py │ ├── merge_job_reports.py │ ├── report_benchmark.py │ ├── report_builder.py │ ├── report_coverage.py │ ├── report_envfail.py │ ├── report_fail.py │ ├── report_fpga.py │ ├── report_fpga_boot.py │ ├── report_pass.py │ ├── report_simu.py │ ├── report_spyglass_lint.py │ ├── report_synth.py │ └── report_tandem.py └── setup-ci-example │ └── core-v-verif-cva6.yml ├── .gitmodules ├── .readthedocs.yaml ├── ACKNOWLEDGEMENTS.md ├── Bender.yml ├── CHANGELOG-PULP.md ├── CHANGELOG.md ├── CITATION.cff ├── CODEOWNERS ├── CONTRIBUTING-PULP.md ├── CONTRIBUTING.md ├── Flist.ariane ├── LICENSE ├── LICENSE.Berkeley ├── LICENSE.SiFive ├── Makefile ├── README.md ├── RESOURCES.md ├── ariane.core ├── ci ├── build-hyp-riscv-tests.sh ├── build-riscv-gcc.sh ├── build-riscv-tests.sh ├── check-tests.sh ├── default.config ├── float.config ├── get-torture.sh ├── gitlab-ci-emul.sh ├── install-dtc.sh ├── install-fesvr.sh ├── install-prereq.sh ├── install-spike.sh ├── install-toolchain.sh ├── install-verilator.sh ├── make-tmp.sh ├── path-setup.sh ├── riscv-amo-tests.list ├── riscv-asm-tests.list ├── riscv-benchmarks.list ├── riscv-fp-tests.list ├── riscv-mul-tests.list ├── setup.sh ├── torture_make.patch └── travis-ci-emul.sh ├── common └── local │ └── util │ ├── ex_trace_item.svh │ ├── find_first_one.sv │ ├── hpdcache_sram_1rw.sv │ ├── hpdcache_sram_wbyteenable_1rw.sv │ ├── instr_trace_item.svh │ ├── instr_tracer.sv │ ├── sram.sv │ ├── sram_cache.sv │ ├── sram_pulp.sv │ ├── tc_sram_fpga_wrapper.sv │ ├── tc_sram_wrapper.sv │ └── tc_sram_wrapper_cache_techno.sv ├── config ├── gen_from_riscv_config │ ├── README.md │ ├── cv32a60x │ │ ├── linker │ │ │ └── link.ld │ │ └── spike │ │ │ └── spike.yaml │ ├── cv32a65x │ │ ├── csr │ │ │ ├── csr.adoc │ │ │ └── csr.rst │ │ ├── isa │ │ │ ├── isa.adoc │ │ │ └── isa.rst │ │ ├── linker │ │ │ └── link.ld │ │ └── spike │ │ │ └── spike.yaml │ ├── linker │ │ └── link.ld │ ├── requirements.txt │ ├── scripts │ │ ├── libs │ │ │ ├── csr_factorizer.py │ │ │ ├── csr_updater.py │ │ │ ├── isa_updater.py │ │ │ ├── spike_updater.py │ │ │ └── utils.py │ │ └── riscv_config_gen.py │ ├── templates │ │ ├── isa_template.yaml │ │ └── spike.mako │ └── updaters │ │ └── cv32a65x │ │ ├── csr_updater.yaml │ │ ├── isa_updater.yaml │ │ └── spike_updater.yaml └── riscv-config │ ├── Makefile │ ├── README.md │ └── cv32a65x │ ├── generated │ ├── custom_gen.yaml │ ├── isa_gen.yaml │ └── platform_gen.yaml │ └── spec │ ├── custom_spec.yaml │ ├── isa_spec.yaml │ └── platform_spec.yaml ├── core ├── Flist.cva6 ├── Flist.cva6_gate ├── acc_dispatcher.sv ├── alu.sv ├── amo_buffer.sv ├── ariane_regfile.sv ├── ariane_regfile_ff.sv ├── ariane_regfile_fpga.sv ├── axi_shim.sv ├── branch_unit.sv ├── cache_subsystem │ ├── amo_alu.sv │ ├── axi_adapter.sv │ ├── cache_ctrl.sv │ ├── cva6_hpdcache_if_adapter.sv │ ├── cva6_hpdcache_subsystem.sv │ ├── cva6_hpdcache_subsystem_axi_arbiter.sv │ ├── cva6_hpdcache_wrapper.sv │ ├── cva6_icache.sv │ ├── cva6_icache_axi_wrapper.sv │ ├── hpdcache_tc_sram.sv │ ├── miss_handler.sv │ ├── std_cache_subsystem.sv │ ├── std_nbdcache.sv │ ├── tag_cmp.sv │ ├── wt_axi_adapter.sv │ ├── wt_cache_subsystem.sv │ ├── wt_dcache.sv │ ├── wt_dcache_ctrl.sv │ ├── wt_dcache_mem.sv │ ├── wt_dcache_missunit.sv │ ├── wt_dcache_wbuffer.sv │ └── wt_l15_adapter.sv ├── commit_stage.sv ├── compressed_decoder.sv ├── controller.sv ├── csr_buffer.sv ├── csr_regfile.sv ├── cva6.sv ├── cva6_accel_first_pass_decoder_stub.sv ├── cva6_clic_controller.sv ├── cva6_fifo_v3.sv ├── cva6_mmu │ ├── cva6_mmu.sv │ ├── cva6_ptw.sv │ ├── cva6_shared_tlb.sv │ └── cva6_tlb.sv ├── cva6_rvfi.sv ├── cva6_rvfi_probes.sv ├── cvxif_compressed_if_driver.sv ├── cvxif_example │ ├── compressed_instr_decoder.sv │ ├── copro_alu.sv │ ├── cvxif_example_coprocessor.sv │ ├── include │ │ └── cvxif_instr_pkg.sv │ └── instr_decoder.sv ├── cvxif_fu.sv ├── cvxif_issue_register_commit_if_driver.sv ├── decoder.sv ├── ex_stage.sv ├── fpu_wrap.sv ├── frontend │ ├── bht.sv │ ├── btb.sv │ ├── frontend.sv │ ├── instr_queue.sv │ ├── instr_scan.sv │ └── ras.sv ├── id_stage.sv ├── include │ ├── ariane_pkg.sv │ ├── build_config_pkg.sv │ ├── config_pkg.sv │ ├── cv32a60x_config_pkg.sv │ ├── cv32a65x_config_pkg.sv │ ├── cv32a6_embedded_config_pkg_deprecated.sv │ ├── cv32a6_ima_sv32_fpga_config_pkg.sv │ ├── cv32a6_imac_sv0_config_pkg.sv │ ├── cv32a6_imac_sv32_config_pkg.sv │ ├── cv32a6_imafc_sv32_config_pkg.sv │ ├── cv64a6_imadfcv_sv39_polara_config_pkg.sv │ ├── cv64a6_imafdc_sv39_config_pkg.sv │ ├── cv64a6_imafdc_sv39_hpdcache_config_pkg.sv │ ├── cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv │ ├── cv64a6_imafdc_sv39_openpiton_config_pkg.sv │ ├── cv64a6_imafdc_sv39_wb_config_pkg.sv │ ├── cv64a6_imafdch_sv39_config_pkg.sv │ ├── cv64a6_imafdch_sv39_wb_config_pkg.sv │ ├── cv64a6_imafdchsclic_sv39_config_pkg.sv │ ├── cv64a6_imafdchsclic_sv39_hpdcache_config_pkg.sv │ ├── cv64a6_imafdchsclic_sv39_wb_config_pkg.sv │ ├── cv64a6_imafdcv_sv39_config_pkg.sv │ ├── cv64a6_mmu_config_pkg.sv │ ├── cvxif_types.svh │ ├── instr_tracer_pkg.sv │ ├── riscv_pkg.sv │ ├── rvfi_types.svh │ ├── std_cache_pkg.sv │ └── wt_cache_pkg.sv ├── instr_realign.sv ├── issue_read_operands.sv ├── issue_stage.sv ├── load_store_unit.sv ├── load_unit.sv ├── lsu_bypass.sv ├── macro_decoder.sv ├── mult.sv ├── multiplier.sv ├── perf_counters.sv ├── pmp │ ├── .gitignore │ ├── Bender.yml │ ├── Makefile │ ├── README.md │ ├── formal.sby │ ├── include │ │ └── riscv.sv │ ├── src │ │ ├── pmp.sv │ │ ├── pmp_data_if.sv │ │ └── pmp_entry.sv │ └── tb │ │ ├── pmp_tb.sv │ │ └── tb_pkg.sv ├── scoreboard.sv ├── serdiv.sv ├── store_buffer.sv ├── store_unit.sv └── zcmt_decoder.sv ├── corev_apu ├── altera │ ├── Makefile │ ├── altera.cfg │ ├── constraints │ │ └── SDC1.sdc │ ├── io_standard_constraints.csv │ ├── ip │ │ ├── cva6_intel_jtag_uart_0.tcl │ │ ├── ed_synth_emif_fm_0.tcl │ │ ├── emif_cal.tcl │ │ ├── iddr_intel.tcl │ │ ├── interconnect.tcl │ │ ├── io_pll.tcl │ │ ├── iobuf.tcl │ │ ├── oddr_intel.tcl │ │ ├── test_mm_ccb_0.tcl │ │ └── vJTAG.tcl │ ├── ip_files.csv │ ├── loc_constraints.csv │ ├── search_paths.csv │ ├── settings.csv │ └── src │ │ ├── cva6_altera.sv │ │ ├── cva6_altera_peripherals.sv │ │ ├── dmi_vjtag.sv │ │ └── dmi_vjtag_tap.sv ├── bootrom │ ├── .gitignore │ ├── Makefile │ ├── ariane.dts │ ├── bootrom.S │ ├── bootrom.h │ ├── bootrom.sv │ ├── encoding.h │ ├── gen_rom.py │ └── linker.ld ├── clint │ ├── README.md │ ├── axi_lite_interface.sv │ └── clint.sv ├── fpga │ ├── Makefile │ ├── ariane-multi-hart.cfg │ ├── ariane.cfg │ ├── ariane_pmod.cfg │ ├── ariane_pmod_tiny.cfg │ ├── constraints │ │ ├── ariane.xdc │ │ ├── genesys-2.xdc │ │ ├── kc705.xdc │ │ ├── nexys_video.xdc │ │ ├── vc707.xdc │ │ └── vcu118.xdc │ ├── scripts │ │ ├── check_fpga_boot.sh │ │ ├── linux_boot.py │ │ ├── program.tcl │ │ ├── program_genesys2.tcl │ │ ├── prologue.tcl │ │ ├── run.tcl │ │ └── write_cfgmem.tcl │ ├── sourceme.sh │ ├── src │ │ ├── agilex7.svh │ │ ├── ariane_peripherals_xilinx.sv │ │ ├── ariane_xilinx.sv │ │ ├── axi_dw_adapter │ │ │ ├── axi_dw_adapter.v │ │ │ ├── axi_dw_adapter_rd.v │ │ │ └── axi_dw_adapter_wr.v │ │ ├── bootrom │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── cv32a6.dts.in │ │ │ ├── cv64a6.dts.in │ │ │ ├── gen_rom.py │ │ │ ├── linker.lds │ │ │ ├── platform.h │ │ │ ├── src │ │ │ │ ├── LICENSE │ │ │ │ ├── gpt.c │ │ │ │ ├── gpt.h │ │ │ │ ├── main.c │ │ │ │ ├── sd.c │ │ │ │ ├── sd.h │ │ │ │ ├── smp.h │ │ │ │ ├── spi.c │ │ │ │ ├── spi.h │ │ │ │ ├── uart.c │ │ │ │ └── uart.h │ │ │ └── startup.S │ │ ├── fan_ctrl.sv │ │ ├── genesysii.svh │ │ ├── kc705.svh │ │ ├── nexys_video.svh │ │ ├── vc707.svh │ │ └── vcu118.svh │ └── xilinx │ │ ├── .gitignore │ │ ├── ariane_xlnx_ip.yml │ │ ├── common.mk │ │ ├── xlnx_axi_clock_converter │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_axi_dwidth_converter │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_axi_dwidth_converter_dm_master │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_axi_dwidth_converter_dm_slave │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_axi_gpio │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_axi_quad_spi │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_clk_gen │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_ila │ │ ├── Makefile │ │ └── tcl │ │ │ └── run.tcl │ │ ├── xlnx_mig_7_ddr3 │ │ ├── Makefile │ │ ├── mig_genesys2.prj │ │ ├── mig_kc705.prj │ │ ├── mig_nexys_video.prj │ │ ├── mig_vc707.prj │ │ └── tcl │ │ │ └── run.tcl │ │ └── xlnx_protocol_checker │ │ ├── Makefile │ │ └── tcl │ │ └── run.tcl ├── openpiton │ ├── ariane_verilog_wrap.sv │ ├── bootrom │ │ ├── .gitignore │ │ ├── baremetal │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── ariane.dts │ │ │ ├── bootrom.S │ │ │ ├── gen_rom.py │ │ │ └── linker.ld │ │ └── linux │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── ariane.dts │ │ │ ├── gen_rom.py │ │ │ ├── info.h │ │ │ ├── linker.lds │ │ │ ├── platform.h │ │ │ ├── src │ │ │ ├── gpt.c │ │ │ ├── gpt.h │ │ │ ├── main.c │ │ │ ├── sd.c │ │ │ ├── sd.h │ │ │ ├── smp.h │ │ │ ├── spi.c │ │ │ ├── spi.h │ │ │ ├── uart.c │ │ │ └── uart.h │ │ │ └── startup.S │ └── riscv_peripherals.sv ├── src │ └── ariane.sv └── tb │ ├── ariane_axi_pkg.sv │ ├── ariane_axi_soc_pkg.sv │ ├── ariane_gate_tb.sv │ ├── ariane_peripherals.sv │ ├── ariane_soc_pkg.sv │ ├── ariane_tb.cpp │ ├── ariane_tb.sv │ ├── ariane_testharness.sv │ ├── axi_intf.sv │ ├── common │ ├── SimDTM.sv │ ├── SimJTAG.sv │ ├── assign.svh │ ├── core_mem.sv │ ├── dp_ram.sv │ ├── mock_uart.sv │ ├── spike.sv │ ├── string_buffer.svh │ ├── tb.svh │ ├── tb_amoport.sv │ ├── tb_dcache_pkg.sv │ ├── tb_readport.sv │ ├── tb_writeport.sv │ └── uart.sv │ ├── dpi │ ├── SimDTM.cc │ ├── SimJTAG.cc │ ├── bootrom.h │ ├── elfloader.cc │ ├── msim_helper.cc │ ├── msim_helper.h │ ├── remote_bitbang.cc │ ├── remote_bitbang.h │ └── verilator.h │ ├── rvfi_tracer.sv │ ├── tb_cva6_icache │ ├── .gitignore │ ├── Makefile │ ├── hdl │ │ ├── mem_emul.sv │ │ ├── tb.sv │ │ ├── tb_pkg.sv │ │ └── tlb_emul.sv │ ├── tb.list │ └── wave.do │ ├── tb_serdiv │ ├── .gitignore │ ├── Makefile │ ├── hdl │ │ ├── tb.sv │ │ ├── tb_div.sv │ │ ├── tb_pkg.sv │ │ ├── tb_rem.sv │ │ ├── tb_udiv.sv │ │ └── tb_urem.sv │ └── tb.list │ ├── tb_wb_dcache │ ├── .gitignore │ ├── Makefile │ ├── hdl │ │ ├── cv32a6_config_pkg.sv │ │ ├── cv64a6_config_pkg.sv │ │ └── tb.sv │ ├── tb.list │ └── wave.do │ ├── tb_wt_axi_dcache │ ├── .gitignore │ ├── Makefile │ ├── hdl │ │ └── tb.sv │ ├── tb.list │ └── wave.do │ ├── tb_wt_dcache │ ├── .gitignore │ ├── Makefile │ ├── hdl │ │ ├── tb.sv │ │ └── tb_mem.sv │ ├── tb.list │ └── wave.do │ └── wave │ └── wave_core.do ├── docs ├── .gitignore ├── 01_cva6_user │ ├── AXI_Interface.rst │ ├── CSR_CV32A60AX.rst │ ├── CSR_CV32A60AX_list.rst │ ├── CSR_CV32A60X.rst │ ├── CSR_CV32A60X_list.rst │ ├── CSR_CV64A6_MMU.rst │ ├── CSR_CV64A6_MMU_list.rst │ ├── CSR_Cache_Control.rst │ ├── CSR_Performance_Counters.rst │ ├── CV32A6_Control_Status_Registers.rst │ ├── CV64A6_Control_Status_Registers.rst │ ├── CVA6_user_guide.rst │ ├── CVX_Interface_Coprocessor.rst │ ├── Compiler_Command_Lines.rst │ ├── Core_Integration.rst │ ├── Custom_Instructions.rst │ ├── Interfaces.rst │ ├── Introduction.rst │ ├── PMA.rst │ ├── PMP.rst │ ├── Parameters_Configuration.rst │ ├── Programmer_View.rst │ ├── RISCV_Instructions.rst │ ├── RISCV_Instructions_RV32A.rst │ ├── RISCV_Instructions_RV32C.rst │ ├── RISCV_Instructions_RV32I.rst │ ├── RISCV_Instructions_RV32M.rst │ ├── RISCV_Instructions_RV32ZCb.rst │ ├── RISCV_Instructions_RVZba.rst │ ├── RISCV_Instructions_RVZbb.rst │ ├── RISCV_Instructions_RVZbc.rst │ ├── RISCV_Instructions_RVZbkb.rst │ ├── RISCV_Instructions_RVZbs.rst │ ├── RISCV_Instructions_RVZcmp.rst │ ├── RISCV_Instructions_RVZicond.rst │ ├── RISCV_Instructions_RVZicsr.rst │ ├── RISCV_Instructions_RVZifencei.rst │ ├── Traps_Interrupts_Exceptions.rst │ ├── images │ │ └── jade_design_automation_logo.png │ ├── index.rst │ ├── rtype_format.png │ └── user_cfg_doc.rst ├── 02_cva6_requirements │ ├── cva6_requirements_specification.rst │ └── images │ │ └── cva6_scope.png ├── 03_cva6_design │ ├── MMU.rst │ ├── _static │ │ ├── LZC.png │ │ ├── RR.png │ │ ├── apb_uart.png │ │ ├── ariane.png │ │ ├── ariane_overview.drawio.png │ │ ├── ariane_overview.png │ │ ├── axi2mem.png │ │ ├── axi_adapter.png │ │ ├── bg.jpg │ │ ├── bootrom.png │ │ ├── branch_prediction.pdf │ │ ├── branch_prediction.png │ │ ├── clint.png │ │ ├── cva6_tlb_entry.png │ │ ├── cva6_tlb_hit.png │ │ ├── dm_top_slave.png │ │ ├── dram.png │ │ ├── fpga_bd.pdf │ │ ├── fpga_bd.png │ │ ├── in_out_tlb.png │ │ ├── instr_realign.pdf │ │ ├── instr_realign.png │ │ ├── jekyll-dark.png │ │ ├── jekyll.png │ │ ├── ld_pipeline_diagram.svg │ │ ├── logonav.png │ │ ├── lsu_blockdiagram.pdf │ │ ├── lsu_blockdiagram.png │ │ ├── mmu_blockdiagramm.pdf │ │ ├── mmu_blockdiagramm.png │ │ ├── mmu_control_flow.png │ │ ├── mmu_in_out.png │ │ ├── mmu_major_blocks.png │ │ ├── nested_translation.png │ │ ├── openhw-landscape.svg │ │ ├── plic.png │ │ ├── plic_top.png │ │ ├── plru_tree_indexing.png │ │ ├── ptw_dptw.png │ │ ├── ptw_dptw_s.png │ │ ├── ptw_idle.png │ │ ├── ptw_in_out.png │ │ ├── ptw_iptw.png │ │ ├── ptw_mis_sup.png │ │ ├── ptw_nlvl.png │ │ ├── ptw_pte_1.png │ │ ├── ptw_pte_flowchart.png │ │ ├── ptw_state_diagram.png │ │ ├── replacement_entry.png │ │ ├── scoreboard.pdf │ │ ├── scoreboard.png │ │ ├── sfence_vaddr_asid.png │ │ ├── sfence_vaddr_x0.png │ │ ├── sfence_x0_asid.png │ │ ├── sfence_x0_x0.png │ │ ├── shared_tlb.png │ │ ├── shared_tlb_in_out.png │ │ ├── shared_tlb_set.png │ │ ├── sram.png │ │ ├── test_harness.png │ │ ├── timer.png │ │ ├── update_tree.png │ │ ├── uvm_fu_tb.ai │ │ └── uvm_fu_tb.png │ ├── commit_stage.rst │ ├── ex_stage.md │ ├── id_stage.md │ ├── if_stage.md │ ├── index.rst │ ├── intro.rst │ ├── issue_stage.md │ └── pcgen_stage.md ├── 04_cv32a65x │ ├── design │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── design.rst │ │ └── source │ │ │ └── images │ │ │ └── CV32A65X_subsystems.png │ ├── index.rst │ ├── riscv │ │ ├── Makefile │ │ ├── priv.rst │ │ └── unpriv.rst │ └── tristan │ │ ├── README.md │ │ ├── tandem-verification │ │ ├── figures │ │ │ ├── Spike-simulation-scope.svg │ │ │ ├── overall-tandem-architecture.svg │ │ │ └── refmodel-step-stages.svg │ │ ├── reference.adoc │ │ └── tandem.adoc │ │ └── verif-spec │ │ ├── media │ │ ├── axiagentmerge.png │ │ ├── frontendsb.png │ │ ├── funccovresults.png │ │ ├── hvp.png │ │ ├── image1.png │ │ ├── image2.png │ │ ├── image3.png │ │ ├── image4.png │ │ ├── image5.png │ │ ├── image6.png │ │ ├── image7.png │ │ ├── interrupt_uvm_agent.png │ │ ├── rtlparam.png │ │ ├── rtlparamgates.png │ │ └── toggleresults.png │ │ └── verification_specifications.adoc ├── 05_cva6_apu │ ├── _static │ │ ├── apb_uart.png │ │ ├── ariane.png │ │ ├── axi2mem.png │ │ ├── axi_adapter.png │ │ ├── bootrom.png │ │ ├── clint.png │ │ ├── dm_top_slave.png │ │ ├── dram.png │ │ ├── plic.png │ │ ├── plic_top.png │ │ ├── sram.png │ │ ├── test_harness.png │ │ └── timer.png │ ├── cva6_apu.rst │ ├── cva6_testharness.md │ └── index.rst ├── 06_cv64a6_mmu │ ├── index.rst │ └── riscv │ │ ├── Makefile │ │ ├── priv.rst │ │ └── unpriv.rst ├── Makefile ├── README.md ├── _static │ ├── openhw-landscape.svg │ └── theme_overrides.css ├── common │ └── config_define.adoc ├── conf.py ├── csr-from-ip-xact │ ├── cv32a60ax │ │ ├── cva6_csr.md │ │ ├── cva6_csr.rst │ │ ├── cva6_csr.xml │ │ └── cva6_csr.yaml │ └── cv32a60x │ │ ├── csr.rst │ │ ├── csr_list.rst │ │ ├── cv32a60mx_csr.md │ │ ├── cv32a60mx_csr.xml │ │ └── cv32a60mx_csr.yaml ├── design │ ├── build.mk │ └── design-manual │ │ ├── Makefile │ │ └── source │ │ ├── AXI.adoc │ │ ├── AXI_Interface.adoc │ │ ├── CSRs.adoc │ │ ├── CVXIF.adoc │ │ ├── CVX_Interface_Coprocessor.adoc │ │ ├── Traps_Interrupts_Exceptions.adoc │ │ ├── architecture.adoc │ │ ├── cva6_caches.adoc │ │ ├── cva6_commit_stage.adoc │ │ ├── cva6_controller.adoc │ │ ├── cva6_csr_regfile.adoc │ │ ├── cva6_execute.adoc │ │ ├── cva6_frontend.adoc │ │ ├── cva6_id_stage.adoc │ │ ├── cva6_issue_stage.adoc │ │ ├── design.adoc │ │ ├── functionality.adoc │ │ ├── glossary.adoc │ │ ├── images │ │ ├── CVA6_subsystems.png │ │ ├── LZC.png │ │ ├── RR.png │ │ ├── ZoominFrontend.png │ │ ├── ariane_overview.drawio.png │ │ ├── ariane_overview.png │ │ ├── bht.png │ │ ├── caches.png │ │ ├── cva6_tlb_entry.png │ │ ├── cva6_tlb_hit.png │ │ ├── ex_stage_modules.png │ │ ├── frontend_modules.png │ │ ├── id_stage_modules.png │ │ ├── in_out_tlb.png │ │ ├── issue_stage_modules.png │ │ ├── load_store_unit_modules.png │ │ ├── mmu_control_flow.png │ │ ├── mmu_in_out.png │ │ ├── mmu_major_blocks.png │ │ ├── mult_modules.png │ │ ├── openhw-landscape.svg │ │ ├── plru_tree_indexing.png │ │ ├── ptw_dptw.png │ │ ├── ptw_dptw_s.png │ │ ├── ptw_idle.png │ │ ├── ptw_in_out.png │ │ ├── ptw_iptw.png │ │ ├── ptw_mis_sup.png │ │ ├── ptw_nlvl.png │ │ ├── ptw_pte_1.png │ │ ├── ptw_pte_flowchart.png │ │ ├── ptw_state_diagram.png │ │ ├── replacement_entry.png │ │ ├── schema_fsm_load_control.png │ │ ├── sfence_vaddr_asid.png │ │ ├── sfence_vaddr_x0.png │ │ ├── sfence_x0_asid.png │ │ ├── sfence_x0_x0.png │ │ ├── shared_tlb.png │ │ ├── shared_tlb_in_out.png │ │ ├── shared_tlb_set.png │ │ ├── subsystems.png │ │ └── update_tree.png │ │ ├── instructions.adoc │ │ ├── intro.adoc │ │ ├── mmu.adoc │ │ ├── subsystem.adoc │ │ └── traps.adoc ├── index.rst ├── requirements.txt ├── riscv-isa │ ├── build.mk │ └── src │ │ ├── a-st-ext.adoc │ │ ├── bfloat16.adoc │ │ ├── calling-convention.adoc │ │ ├── cmo.adoc │ │ ├── colophon.adoc │ │ ├── counters.adoc │ │ ├── d-st-ext.adoc │ │ ├── f-st-ext.adoc │ │ ├── hypervisor.adoc │ │ ├── images │ │ └── ohg_logo.png │ │ ├── indirect-csr.adoc │ │ ├── machine.adoc │ │ ├── mm-formal.adoc │ │ ├── priv-cfi.adoc │ │ ├── priv-csrs.adoc │ │ ├── priv-preface.adoc │ │ ├── q-st-ext.adoc │ │ ├── resources │ │ └── themes │ │ │ └── riscv-spec.yml │ │ ├── riscv-privileged.adoc │ │ ├── riscv-unprivileged.adoc │ │ ├── rnmi.adoc │ │ ├── rv-32-64g.adoc │ │ ├── rv128.adoc │ │ ├── rv32e.adoc │ │ ├── rv64.adoc │ │ ├── scalar-crypto.adoc │ │ ├── smcdeleg.adoc │ │ ├── smcntrpmf.adoc │ │ ├── smctr.adoc │ │ ├── smdbltrp.adoc │ │ ├── smepmp.adoc │ │ ├── smstateen.adoc │ │ ├── sscofpmf.adoc │ │ ├── ssdbltrp.adoc │ │ ├── sstc.adoc │ │ ├── supervisor.adoc │ │ ├── unpriv-cfi.adoc │ │ ├── v-st-ext.adoc │ │ ├── vector-crypto.adoc │ │ ├── vector-examples.adoc │ │ ├── zabha.adoc │ │ ├── zacas.adoc │ │ ├── zawrs.adoc │ │ ├── zfa.adoc │ │ ├── zfh.adoc │ │ ├── zfinx.adoc │ │ ├── zicond.adoc │ │ ├── zifencei.adoc │ │ ├── zihintntl.adoc │ │ ├── zihintpause.adoc │ │ ├── zimop.adoc │ │ ├── zpm.adoc │ │ └── ztso-st-ext.adoc ├── scripts │ ├── classes.py │ ├── define_blacklist.py │ ├── parameters_extractor.py │ └── spec_builder.py └── user_guide │ └── cva6_ug_csr.adoc ├── pd └── synth │ ├── .gitignore │ ├── Makefile │ ├── cva6_read.tcl │ ├── cva6_synth.tcl │ ├── hpdcache_sram_1rw_00000006_0000001c_00000040.sv │ ├── hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv │ ├── scripts │ ├── dc_setup.tcl │ ├── dc_setup_filenames.tcl │ └── gate_analysis.py │ └── tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv ├── spyglass ├── Makefile ├── reference_summary.rpt └── sg_setup │ └── cva6 │ ├── cva6.sgdc │ ├── cva6_goals_setup.tcl │ ├── cva6_options.tcl │ └── cva6_waiver.awl ├── src_files.yml ├── util ├── CODEOWNERS ├── README.md ├── flist_flattener.py ├── init_gate.do ├── init_testharness.do ├── parse_ila_trace.py ├── toolchain-builder │ ├── README.md │ ├── build-toolchain.sh │ ├── config │ │ ├── gcc-13.1.0-baremetal.sh │ │ ├── gcc-14.1.0-baremetal.sh │ │ ├── gcc-master-baremetal.sh │ │ ├── global.sh │ │ ├── llvm-18-baremetal.sh │ │ └── llvm-master-baremetal.sh │ └── get-toolchain.sh ├── user_config.py └── vendor.py ├── vendor ├── patches │ ├── pulp-platform │ │ └── common_cells │ │ │ └── 00001-spyglass-no-multiple-assignement-same-block-padded_input.patch │ └── riscv │ │ └── riscv-config │ │ ├── 0001-enable-implied-B-ext.patch │ │ ├── 0002-add-mstatus-UBE-bit.patch │ │ ├── 0003-add-mtval-roconst0-schema.patch │ │ ├── 0004-fix-mstatush-and-nonascii-chars.patch │ │ └── 0005-add-csr-schema-for-mconfigptr.patch ├── pulp-platform │ ├── axi │ │ ├── .gitignore │ │ ├── CHANGELOG.md │ │ ├── CONTRIBUTING.md │ │ ├── LICENSE │ │ ├── README.md │ │ ├── VERSION │ │ ├── include │ │ │ └── axi │ │ │ │ ├── assign.svh │ │ │ │ └── typedef.svh │ │ └── src │ │ │ ├── axi_atop_filter.sv │ │ │ ├── axi_burst_splitter.sv │ │ │ ├── axi_cdc.sv │ │ │ ├── axi_cdc_dst.sv │ │ │ ├── axi_cdc_src.sv │ │ │ ├── axi_cut.sv │ │ │ ├── axi_delayer.sv │ │ │ ├── axi_demux.sv │ │ │ ├── axi_dw_converter.sv │ │ │ ├── axi_dw_downsizer.sv │ │ │ ├── axi_dw_upsizer.sv │ │ │ ├── axi_err_slv.sv │ │ │ ├── axi_id_prepend.sv │ │ │ ├── axi_id_remap.sv │ │ │ ├── axi_id_serialize.sv │ │ │ ├── axi_intf.sv │ │ │ ├── axi_isolate.sv │ │ │ ├── axi_iw_converter.sv │ │ │ ├── axi_join.sv │ │ │ ├── axi_lite_demux.sv │ │ │ ├── axi_lite_join.sv │ │ │ ├── axi_lite_mailbox.sv │ │ │ ├── axi_lite_mux.sv │ │ │ ├── axi_lite_regs.sv │ │ │ ├── axi_lite_to_apb.sv │ │ │ ├── axi_lite_to_axi.sv │ │ │ ├── axi_lite_xbar.sv │ │ │ ├── axi_modify_address.sv │ │ │ ├── axi_multicut.sv │ │ │ ├── axi_mux.sv │ │ │ ├── axi_pkg.sv │ │ │ ├── axi_serializer.sv │ │ │ ├── axi_sim_mem.sv │ │ │ ├── axi_test.sv │ │ │ ├── axi_to_axi_lite.sv │ │ │ └── axi_xbar.sv │ ├── common_cells │ │ ├── .gitignore │ │ ├── CHANGELOG.md │ │ ├── LICENSE │ │ ├── README.md │ │ ├── include │ │ │ └── common_cells │ │ │ │ ├── assertions.svh │ │ │ │ └── registers.svh │ │ └── src │ │ │ ├── addr_decode.sv │ │ │ ├── binary_to_gray.sv │ │ │ ├── cb_filter.sv │ │ │ ├── cb_filter_pkg.sv │ │ │ ├── cc_onehot.sv │ │ │ ├── cdc_2phase.sv │ │ │ ├── cdc_fifo_2phase.sv │ │ │ ├── cdc_fifo_gray.sv │ │ │ ├── cf_math_pkg.sv │ │ │ ├── clk_div.sv │ │ │ ├── counter.sv │ │ │ ├── delta_counter.sv │ │ │ ├── deprecated │ │ │ ├── clock_divider.sv │ │ │ ├── clock_divider_counter.sv │ │ │ ├── fifo_v1.sv │ │ │ ├── fifo_v2.sv │ │ │ ├── find_first_one.sv │ │ │ ├── generic_LFSR_8bit.sv │ │ │ ├── generic_fifo.sv │ │ │ ├── generic_fifo_adv.sv │ │ │ ├── prioarbiter.sv │ │ │ ├── pulp_sync.sv │ │ │ ├── pulp_sync_wedge.sv │ │ │ ├── rrarbiter.sv │ │ │ └── sram.sv │ │ │ ├── ecc_decode.sv │ │ │ ├── ecc_encode.sv │ │ │ ├── ecc_pkg.sv │ │ │ ├── edge_detect.sv │ │ │ ├── edge_propagator.sv │ │ │ ├── edge_propagator_rx.sv │ │ │ ├── edge_propagator_tx.sv │ │ │ ├── exp_backoff.sv │ │ │ ├── fall_through_register.sv │ │ │ ├── fifo_v3.sv │ │ │ ├── gray_to_binary.sv │ │ │ ├── id_queue.sv │ │ │ ├── isochronous_4phase_handshake.sv │ │ │ ├── isochronous_spill_register.sv │ │ │ ├── lfsr.sv │ │ │ ├── lfsr_16bit.sv │ │ │ ├── lfsr_8bit.sv │ │ │ ├── lzc.sv │ │ │ ├── max_counter.sv │ │ │ ├── mv_filter.sv │ │ │ ├── onehot_to_bin.sv │ │ │ ├── plru_tree.sv │ │ │ ├── popcount.sv │ │ │ ├── rr_arb_tree.sv │ │ │ ├── rstgen.sv │ │ │ ├── rstgen_bypass.sv │ │ │ ├── serial_deglitch.sv │ │ │ ├── shift_reg.sv │ │ │ ├── spill_register.sv │ │ │ ├── spill_register_flushable.sv │ │ │ ├── stream_arbiter.sv │ │ │ ├── stream_arbiter_flushable.sv │ │ │ ├── stream_delay.sv │ │ │ ├── stream_demux.sv │ │ │ ├── stream_fifo.sv │ │ │ ├── stream_filter.sv │ │ │ ├── stream_fork.sv │ │ │ ├── stream_fork_dynamic.sv │ │ │ ├── stream_intf.sv │ │ │ ├── stream_join.sv │ │ │ ├── stream_mux.sv │ │ │ ├── stream_omega_net.sv │ │ │ ├── stream_register.sv │ │ │ ├── stream_to_mem.sv │ │ │ ├── stream_xbar.sv │ │ │ ├── sub_per_hash.sv │ │ │ ├── sync.sv │ │ │ ├── sync_wedge.sv │ │ │ └── unread.sv │ ├── fpga-support │ │ ├── CHANGELOG.md │ │ ├── CONTRIBUTING.md │ │ ├── LICENSE │ │ ├── README.md │ │ ├── behav │ │ │ ├── BramDwc │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── README.md │ │ │ │ ├── Testbench.sv │ │ │ │ ├── scripts │ │ │ │ │ ├── run.tcl │ │ │ │ │ ├── run_gui.tcl │ │ │ │ │ └── waves.tcl │ │ │ │ └── vectors │ │ │ │ │ ├── expresp.txt │ │ │ │ │ └── stim.txt │ │ │ ├── Makefile │ │ │ └── common │ │ │ │ ├── Makefile │ │ │ │ ├── gitignore │ │ │ │ ├── include │ │ │ │ └── assertions.sv │ │ │ │ └── modules │ │ │ │ └── ClkRstGen.sv │ │ ├── fpga-support-stubs.sv │ │ ├── rtl │ │ │ ├── AsyncDpRam.sv │ │ │ ├── AsyncThreePortRam.sv │ │ │ ├── AxiBramLogger.sv │ │ │ ├── AxiToAxiLitePc.sv │ │ │ ├── BramDwc.sv │ │ │ ├── BramLogger.sv │ │ │ ├── BramPort.sv │ │ │ ├── SyncDpRam.sv │ │ │ ├── SyncDpRam_ind_r_w.sv │ │ │ ├── SyncSpRam.sv │ │ │ ├── SyncSpRamBeNx32.sv │ │ │ ├── SyncSpRamBeNx64.sv │ │ │ ├── SyncThreePortRam.sv │ │ │ ├── SyncTpRam.sv │ │ │ └── TdpBramArray.sv │ │ └── synth │ │ │ ├── BramDwc │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── deps │ │ │ │ ├── .gitignore │ │ │ │ ├── BramDwc.sv │ │ │ │ └── BramPort.sv │ │ │ ├── scripts │ │ │ │ ├── setup.tcl │ │ │ │ └── synthesize.tcl │ │ │ └── src │ │ │ │ └── Top.sv │ │ │ └── common │ │ │ ├── Makefile │ │ │ ├── gitignore │ │ │ └── scripts │ │ │ ├── setup.tcl │ │ │ └── synthesize.tcl │ └── tech_cells_generic │ │ ├── .gitignore │ │ ├── CHANGELOG.md │ │ ├── CONTRIBUTING.md │ │ ├── LICENSE │ │ ├── README.md │ │ └── src │ │ ├── deprecated │ │ ├── cluster_clk_cells.sv │ │ ├── cluster_pwr_cells.sv │ │ ├── generic_memory.sv │ │ ├── generic_rom.sv │ │ ├── pad_functional.sv │ │ ├── pulp_buffer.sv │ │ ├── pulp_clk_cells.sv │ │ ├── pulp_clock_gating_async.sv │ │ └── pulp_pwr_cells.sv │ │ ├── fpga │ │ ├── pad_functional_xilinx.sv │ │ ├── tc_clk_xilinx.sv │ │ └── tc_sram_xilinx.sv │ │ ├── rtl │ │ ├── tc_clk.sv │ │ └── tc_sram.sv │ │ └── tc_pwr.sv ├── pulp-platform_axi.lock.hjson ├── pulp-platform_axi.vendor.hjson ├── pulp-platform_common_cells.lock.hjson ├── pulp-platform_common_cells.vendor.hjson ├── pulp-platform_fpga-support.lock.hjson ├── pulp-platform_fpga-support.vendor.hjson ├── pulp-platform_tech_cells_generic.lock.hjson ├── pulp-platform_tech_cells_generic.vendor.hjson ├── riscv │ └── riscv-config │ │ ├── .git_hooks │ │ ├── pre-commit │ │ └── setup.sh │ │ ├── .gitignore │ │ ├── CHANGELOG.md │ │ ├── CONTRIBUTING.rst │ │ ├── LICENSE │ │ ├── MANIFEST.in │ │ ├── README.rst │ │ ├── docs │ │ ├── Makefile │ │ ├── README.md │ │ ├── requirements.txt │ │ └── source │ │ │ ├── CONTRIBUTING.rst │ │ │ ├── _static │ │ │ ├── Tall_2.png │ │ │ ├── custom.css │ │ │ └── theme_overrides.css │ │ │ ├── _templates │ │ │ ├── breadcrumbs.html │ │ │ ├── layout.html │ │ │ └── versions.html │ │ │ ├── code-doc.rst │ │ │ ├── conf.py │ │ │ ├── index.rst │ │ │ ├── intro.rst │ │ │ ├── new-extensions.rst │ │ │ ├── overview.rst │ │ │ ├── quickstart.rst │ │ │ ├── revisions.rst │ │ │ ├── riscv_config-flow.png │ │ │ ├── schema_custom.rst │ │ │ └── yaml-specs.rst │ │ ├── examples │ │ ├── rv32i_custom.yaml │ │ ├── rv32i_debug.yaml │ │ ├── rv32i_isa.yaml │ │ ├── rv32i_isa_checked.yaml │ │ ├── rv32i_platform.yaml │ │ ├── rv32i_platform_checked.yaml │ │ ├── rv64i_custom.yaml │ │ ├── rv64i_debug.yaml │ │ ├── rv64i_isa.yaml │ │ ├── rv64i_isa_checked.yaml │ │ ├── rv64i_platform.yaml │ │ └── rv64i_platform_checked.yaml │ │ ├── requirements.txt │ │ ├── riscv_config │ │ ├── __init__.py │ │ ├── checker.py │ │ ├── constants.py │ │ ├── errors.py │ │ ├── isa_validator.py │ │ ├── main.py │ │ ├── schemaValidator.py │ │ ├── schemas │ │ │ ├── schema_custom.yaml │ │ │ ├── schema_debug.yaml │ │ │ ├── schema_isa.yaml │ │ │ └── schema_platform.yaml │ │ ├── utils.py │ │ └── warl.py │ │ ├── setup.cfg │ │ └── setup.py ├── riscv_riscv-config.lock.hjson └── riscv_riscv-config.vendor.hjson ├── verif ├── .gitignore ├── README.md ├── bsp │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── crt0.S │ ├── handlers.S │ ├── link.ld │ ├── syscalls.c │ ├── useful_sites.txt │ └── vectors.S ├── docs │ ├── Protocols │ │ ├── Makefile │ │ ├── figures │ │ │ └── interrupt-ack-uvm.svg │ │ ├── interrupt-verification.adoc │ │ └── wavedrom │ │ │ └── interrupt-ack-uvm.wave │ ├── UVM_verif_env.md │ ├── VerifPlans │ │ ├── AXI │ │ │ ├── VP_IP005.yml │ │ │ ├── VP_IP006.yml │ │ │ ├── VP_IP007.yml │ │ │ ├── VP_IP008.yml │ │ │ ├── VP_IP009.yml │ │ │ └── runme.sh │ │ ├── CVXIF │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP001.yml │ │ │ ├── VP_IP002.yml │ │ │ ├── VP_IP003.yml │ │ │ ├── custom_instruction.rst │ │ │ └── runme.sh │ │ ├── FENCEI │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP001.yml │ │ │ ├── VP_IP002.yml │ │ │ ├── VP_IP003.yml │ │ │ ├── VP_IP004.yml │ │ │ ├── VP_IP005.yml │ │ │ ├── VP_IP006.yml │ │ │ └── runme.sh │ │ ├── FRONTEND │ │ │ ├── VP_IP003.yml │ │ │ ├── VP_IP004.yml │ │ │ ├── VP_IP005.yml │ │ │ ├── VP_IP006.yml │ │ │ ├── VP_IP007.yml │ │ │ ├── VP_IP008.yml │ │ │ ├── VP_IP009.yml │ │ │ ├── VP_IP010.yml │ │ │ └── runme.sh │ │ ├── ISA_RV32 │ │ │ ├── RISCV_Instructions.rst │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP001.yml │ │ │ ├── VP_IP002.yml │ │ │ ├── VP_IP003.yml │ │ │ ├── VP_IP004.yml │ │ │ ├── VP_IP005.yml │ │ │ ├── VP_IP006.yml │ │ │ ├── VP_IP007.yml │ │ │ ├── VP_IP008.yml │ │ │ ├── VP_IP009.yml │ │ │ ├── VP_IP010.yml │ │ │ ├── VP_IP011.yml │ │ │ ├── VP_IP012.yml │ │ │ ├── VP_IP013.yml │ │ │ ├── VP_IP014.yml │ │ │ ├── VP_IP015.yml │ │ │ ├── VP_IP016.yml │ │ │ ├── VP_IP017.yml │ │ │ ├── VP_IP018.yml │ │ │ ├── VP_IP019.yml │ │ │ ├── VP_IP020.yml │ │ │ ├── VP_IP021.yml │ │ │ ├── VP_IP022.yml │ │ │ └── runme.sh │ │ ├── MMU_SV32 │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP001.yml │ │ │ ├── VP_IP002.yml │ │ │ └── runme.sh │ │ ├── Makefile │ │ ├── VPTOOL-VerifPlan-HOWTO.md │ │ ├── csr_access │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP001.yml │ │ │ ├── VP_IP002.yml │ │ │ ├── VP_IP003.yml │ │ │ ├── VP_IP004.yml │ │ │ ├── cva6_csr.rst │ │ │ └── runme.sh │ │ ├── csr_embedded_access │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP001.yml │ │ │ ├── VP_IP002.yml │ │ │ ├── cva6_embedded_csr.rst │ │ │ ├── dvplan_csr-embedded-access.md │ │ │ └── runme.sh │ │ ├── cvxif_VP.xlsx │ │ ├── images │ │ │ └── openhw-landscape.svg │ │ ├── install-prerequisites.sh │ │ ├── make.bat │ │ ├── requirements.txt │ │ ├── source │ │ │ ├── conf.py │ │ │ ├── dvplan_AXI.md │ │ │ ├── dvplan_CVXIF.md │ │ │ ├── dvplan_FENCEI.md │ │ │ ├── dvplan_FRONTEND.md │ │ │ ├── dvplan_ISA_RV32.md │ │ │ ├── dvplan_MMU_SV32.md │ │ │ ├── dvplan_csr-access.md │ │ │ ├── dvplan_csr-embedded-access.md │ │ │ ├── dvplan_intro.rst │ │ │ ├── dvplan_traps.md │ │ │ └── index.rst │ │ ├── traps │ │ │ ├── VP_IP000.yml │ │ │ ├── VP_IP002.yml │ │ │ ├── VP_IP003.yml │ │ │ ├── VP_IP005.yml │ │ │ ├── VP_IP006.yml │ │ │ ├── VP_IP007.yml │ │ │ ├── VP_IP008.yml │ │ │ ├── VP_IP009.yml │ │ │ ├── VP_IP010.yml │ │ │ ├── VP_IP011.yml │ │ │ └── runme.sh │ │ └── vp_config.py │ ├── coverage_status │ │ └── isacov_status.rst │ ├── images │ │ └── CVA6_env.drawio.drawio.png │ └── verif-approvals.md ├── env │ ├── corev-dv │ │ ├── README.md │ │ ├── custom │ │ │ ├── cvxif_custom_instr.sv │ │ │ ├── riscv_custom_instr_enum.sv │ │ │ ├── riscv_zcb_instr.sv │ │ │ ├── riscv_zcmp_instr.sv │ │ │ ├── riscv_zicond_instr.sv │ │ │ ├── rv32x_instr.sv │ │ │ ├── rv32zcb_instr.sv │ │ │ ├── rv32zcmp_instr.sv │ │ │ ├── rv32zicond_instr.sv │ │ │ └── rv64zcb_instr.sv │ │ ├── cva6-files.f │ │ ├── cva6_asm_program_gen.sv │ │ ├── cva6_defines.svh │ │ ├── cva6_ecall_instr_stream.sv │ │ ├── cva6_illegal_instr.sv │ │ ├── cva6_instr_base_test.sv │ │ ├── cva6_instr_gen_config.sv │ │ ├── cva6_instr_gen_tb_top.sv │ │ ├── cva6_instr_hazard_test.sv │ │ ├── cva6_instr_sequence.sv │ │ ├── cva6_instr_test_pkg.sv │ │ ├── cva6_load_store_instr_lib.sv │ │ ├── cva6_reg_hazard_stream.sv │ │ ├── cva6_signature_pkg.sv │ │ ├── cva6_unsupported_instr.sv │ │ ├── simulator.yaml │ │ ├── target │ │ │ ├── rv32imac │ │ │ │ └── riscv_core_setting.sv │ │ │ ├── rv32imcb │ │ │ │ └── riscv_core_setting.sv │ │ │ └── rv64gc │ │ │ │ └── riscv_core_setting.sv │ │ └── user_extension │ │ │ ├── user_define.h │ │ │ └── x_extn_user_define.h │ └── uvme │ │ ├── cov │ │ ├── uvme_axi_covg.sv │ │ ├── uvme_axi_ext_covg.sv │ │ ├── uvme_cva6_config_covg.sv │ │ ├── uvme_cva6_cov_model.sv │ │ ├── uvme_cvxif_covg.sv │ │ ├── uvme_exception_covg.sv │ │ ├── uvme_illegal_instr_covg.sv │ │ ├── uvme_interrupt_covg.sv │ │ └── uvme_isa_covg.sv │ │ ├── cvxif_vseq │ │ ├── custom_instruction.rst │ │ ├── custom_instructions_cvxif_1_0_0.rst │ │ ├── uvme_cvxif_base_vseq.sv │ │ └── uvme_cvxif_vseq.sv │ │ ├── reg │ │ ├── cva6_csr_reg_adapter.sv │ │ ├── cva6_csr_reg_block.sv │ │ ├── cva6_csr_reg_file.sv │ │ └── cva6_csr_reg_predictor.sv │ │ ├── uvma_cva6_core_cntrl_agent.sv │ │ ├── uvma_cva6_core_cntrl_cntxt.sv │ │ ├── uvma_cva6_core_cntrl_drv.sv │ │ ├── uvma_interrupt │ │ ├── README.md │ │ ├── cov │ │ │ └── uvma_interrupt_cov_model.sv │ │ ├── seq │ │ │ ├── uvma_interrupt_base_seq.sv │ │ │ ├── uvma_interrupt_seq.sv │ │ │ └── uvma_interrupt_seq_item.sv │ │ ├── uvma_interrupt_agent.sv │ │ ├── uvma_interrupt_cfg.sv │ │ ├── uvma_interrupt_cntxt.sv │ │ ├── uvma_interrupt_constants.sv │ │ ├── uvma_interrupt_drv.sv │ │ ├── uvma_interrupt_if.sv │ │ ├── uvma_interrupt_macros.sv │ │ ├── uvma_interrupt_mon.sv │ │ ├── uvma_interrupt_pkg.flist │ │ ├── uvma_interrupt_pkg.sv │ │ ├── uvma_interrupt_sqr.sv │ │ └── uvma_interrupt_tdefs.sv │ │ ├── uvme_cva6_cfg.sv │ │ ├── uvme_cva6_cntxt.sv │ │ ├── uvme_cva6_constants.sv │ │ ├── uvme_cva6_core_cntrl_if.sv │ │ ├── uvme_cva6_env.sv │ │ ├── uvme_cva6_macros.sv │ │ ├── uvme_cva6_pkg.flist │ │ ├── uvme_cva6_pkg.sv │ │ ├── uvme_cva6_prd.sv │ │ ├── uvme_cva6_sb.sv │ │ ├── uvme_cva6_tdefs.sv │ │ ├── uvme_cva6_vsqr.sv │ │ ├── uvml_mem_vp.sv │ │ └── vseq │ │ ├── uvme_axi_fw_preload_seq.sv │ │ ├── uvme_cva6_base_vseq.sv │ │ ├── uvme_cva6_reset_vseq.sv │ │ └── uvme_cva6_vseq_lib.sv ├── regress │ ├── benchmark.sh │ ├── coremark.sh │ ├── cv32a6_tests.sh │ ├── cv64a6_imafdc_tests.sh │ ├── cvxif_verif_regression.sh │ ├── debug_test.sh │ ├── dhrystone.sh │ ├── dhrystone_smoke.sh │ ├── dv-csr-embedded-tests.sh │ ├── dv-generated-tests.sh │ ├── dv-generated-xif-tests.sh │ ├── dv-interrupt-test.sh │ ├── dv-riscv-arch-test.sh │ ├── dv-riscv-compliance.sh │ ├── dv-riscv-csr-access-test.sh │ ├── dv-riscv-mmu-sv32-test.sh │ ├── dv-riscv-tests.sh │ ├── hwconfig_tests.sh │ ├── install-riscv-arch-test.sh │ ├── install-riscv-compliance.sh │ ├── install-riscv-tests.sh │ ├── install-spike.sh │ ├── install-verilator.sh │ ├── iss-tests.sh │ ├── issue-tests.sh │ ├── linux.sh │ ├── riscv-compliance.patch │ ├── riscv-dv.patch │ ├── riscv-tests-env.patch │ ├── riscv-tests.patch │ ├── smoke-gen_tests.sh │ ├── smoke-tests-cv32a65x.sh │ ├── smoke-tests-cv32a6_imac_sv32.sh │ ├── smoke-tests-cv64a6_imafdc_sv39.sh │ └── verilator-v5.patch ├── sim │ ├── Makefile │ ├── cov-exclude-mod.lst │ ├── cva6-simulator.yaml │ ├── cva6.hvp │ ├── cva6.py │ ├── cva6.yaml │ ├── cva6_base_testlist.yaml │ ├── cva6_spike_log_to_trace_csv.py │ ├── init_run_uvm_fsdb.do │ ├── init_run_uvm_vpd.do │ ├── init_uvm.do │ ├── setup-env.sh │ └── verilator_log_to_trace_csv.py ├── tb │ ├── core │ │ ├── Flist.cva6_tb │ │ ├── Makefile │ │ ├── README.md │ │ ├── bootrom │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── bootrom.S │ │ │ ├── bootrom.h │ │ │ ├── cva6.dts │ │ │ ├── encoding.h │ │ │ ├── gen_rom.py │ │ │ └── linker.ld │ │ ├── custom_uvm_macros.svh │ │ ├── cva6_tb_verilator.cpp │ │ ├── tb_components │ │ │ └── axi_master_connect.sv │ │ ├── uvma_core_cntrl_pkg.sv │ │ ├── uvma_cva6pkg_utils.sv │ │ ├── uvma_cva6pkg_utils_pkg.sv │ │ ├── uvma_rvfi_pkg.sv │ │ ├── uvmc_rvfi_reference_model_pkg.sv │ │ └── uvmc_rvfi_scoreboard_pkg.sv │ └── uvmt │ │ ├── cva6_tb_wrapper.sv │ │ ├── uvmt_axi_assert.sv │ │ ├── uvmt_axi_switch_intf.sv │ │ ├── uvmt_cva6.flist │ │ ├── uvmt_cva6_axi_assert.sv │ │ ├── uvmt_cva6_constants.sv │ │ ├── uvmt_cva6_dut_wrap.sv │ │ ├── uvmt_cva6_macros.sv │ │ ├── uvmt_cva6_pkg.sv │ │ ├── uvmt_cva6_tb.sv │ │ ├── uvmt_cva6_tb_ifs.sv │ │ ├── uvmt_cva6_tdefs.sv │ │ └── uvmt_default_inputs_intf.sv └── tests │ ├── custom │ ├── CSR │ │ ├── csr_access_failing_tests │ │ │ ├── README.md │ │ │ ├── riscv_marchid_csr_test_0.S │ │ │ ├── riscv_mstatus_csr_test_0.S │ │ │ ├── riscv_mvendorid_csr_test_0.S │ │ │ ├── riscv_pmpaddr0_csr_test_0.S │ │ │ ├── riscv_pmpaddr1_csr_test_0.S │ │ │ ├── riscv_pmpaddr2_csr_test_0.S │ │ │ ├── riscv_pmpaddr3_csr_test_0.S │ │ │ ├── riscv_pmpaddr4_csr_test_0.S │ │ │ ├── riscv_pmpaddr5_csr_test_0.S │ │ │ ├── riscv_pmpaddr6_csr_test_0.S │ │ │ ├── riscv_pmpaddr7_csr_test_0.S │ │ │ ├── riscv_pmpcfg0_csr_test_0.S │ │ │ ├── riscv_pmpcfg1_csr_test_0.S │ │ │ └── riscv_sstatus_csr_test_0.S │ │ ├── csr_access_tests │ │ │ ├── readme.md │ │ │ ├── riscv_cycle_csr_test_0.S │ │ │ ├── riscv_instret_csr_test_0.S │ │ │ ├── riscv_m_ro_csr_test_0.S │ │ │ ├── riscv_m_rw_csr_test_0.S │ │ │ ├── riscv_mcycle_csr_test_0.S │ │ │ ├── riscv_mcycleh_csr_test_0.S │ │ │ ├── riscv_minstret_csr_test_0.S │ │ │ ├── riscv_minstreth_csr_test_0.S │ │ │ └── riscv_s_rw_csr_test_0.S │ │ └── csr_access_yaml │ │ │ ├── README.md │ │ │ ├── cv32a6_m_ro_csr_test.yaml │ │ │ ├── cv32a6_m_rw_csr_test.yaml │ │ │ ├── cv32a6_s_rw_csr_test.yaml │ │ │ └── cva6_mscratch_csr_access.yaml │ ├── Zcmp │ │ ├── cm_mva01s_test.S │ │ ├── cm_mvsa01_test.S │ │ ├── cm_popret_test.S │ │ ├── cm_popretz_test.S │ │ ├── cm_push_pop_test.S │ │ ├── link.ld │ │ ├── readme.txt │ │ ├── riscv_test.h │ │ ├── syscalls.c │ │ └── util.h │ ├── common │ │ ├── crt.S │ │ ├── cva6_csr_access_test_32.S │ │ ├── cva6_csr_access_test_64.S │ │ ├── syscalls.c │ │ └── util.h │ ├── coremark │ │ ├── LICENSE.md │ │ ├── core_list_join.c │ │ ├── core_matrix.c │ │ ├── core_portme.c │ │ ├── core_portme.h │ │ ├── core_state.c │ │ ├── core_util.c │ │ ├── coremark.h │ │ ├── coremark_main.c │ │ ├── uart.c │ │ └── uart.h │ ├── csr_embedded │ │ ├── csr_counters_overflow.S │ │ ├── csr_test.S │ │ ├── csrcs_test.S │ │ ├── csrcsi_test.S │ │ ├── csrrst_test.S │ │ ├── csrrw_fields_test.S │ │ ├── csrrw_fullrandom_test.S │ │ ├── csrrw_ro_test.S │ │ ├── csrrw_test.S │ │ ├── csrrw_unmapped_test.S │ │ └── csrrwi_test.S │ ├── cv_xif │ │ ├── cvxif_add_nop.S │ │ ├── cvxif_exc.S │ │ ├── cvxif_full.S │ │ ├── cvxif_illegal.S │ │ ├── cvxif_issexc.S │ │ ├── cvxif_macros.h │ │ ├── cvxif_multi.S │ │ ├── cvxif_nopexc.S │ │ ├── cvxif_rs3.S │ │ ├── cvxif_s_mode.S │ │ └── cvxif_u_mode.S │ ├── debug_test │ │ ├── bsp │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── bsp.h │ │ │ ├── corev_uvmt.h │ │ │ ├── crt0.S │ │ │ ├── handlers.S │ │ │ ├── link.ld │ │ │ ├── link_corev-dv.ld │ │ │ ├── syscalls.c │ │ │ └── vectors.S │ │ ├── debug_test.c │ │ ├── debugger.S │ │ ├── debugger_exception.S │ │ ├── handlers.S │ │ ├── single_step.S │ │ ├── test.yaml │ │ └── trigger_code.S │ ├── dhrystone │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ └── dhrystone_main.c │ ├── env │ │ ├── LICENSE │ │ └── encoding.h │ ├── hello_world │ │ ├── custom_test_template.S │ │ └── hello_world.c │ ├── interrupt │ │ └── jump_to_zero.S │ ├── isacov │ │ ├── branch_to_zero.S │ │ ├── illegal_isa.S │ │ ├── isa_test.S │ │ ├── jump_test.S │ │ ├── load_reg_hazard.S │ │ ├── load_store_test.S │ │ └── seq_hazard.S │ ├── issues │ │ ├── compressed-fpreg-commits-rv32.S │ │ └── compressed-fpreg-commits-rv64.S │ ├── return0 │ │ └── return0.c │ ├── spike_params │ │ └── misa_csr_we.S │ ├── sv32 │ │ ├── macros.h │ │ ├── vm_access_bit_level_0.S │ │ ├── vm_access_bit_level_1.S │ │ ├── vm_bare_mode_level_0.S │ │ ├── vm_bare_mode_level_1.S │ │ ├── vm_dirty_bit_level_0.S │ │ ├── vm_dirty_bit_level_1.S │ │ ├── vm_invalid_pte_level_0.S │ │ ├── vm_invalid_pte_level_1.S │ │ ├── vm_misaligned_superpage.S │ │ ├── vm_mstatus_tvm_level_0.S │ │ ├── vm_mstatus_tvm_level_1.S │ │ ├── vm_mxr_clear_level_0.S │ │ ├── vm_mxr_clear_level_1.S │ │ ├── vm_mxr_set_level_0.S │ │ ├── vm_mxr_set_level_1.S │ │ ├── vm_nonleaf_pte.S │ │ ├── vm_pmp_check_level_0.S │ │ ├── vm_pmp_check_level_1.S │ │ ├── vm_pte_pmp_check_level_0.S │ │ ├── vm_pte_pmp_check_level_1.S │ │ ├── vm_pte_u_bit_set_01.S │ │ ├── vm_pte_u_bit_set_02.S │ │ ├── vm_pte_u_bit_set_03.S │ │ ├── vm_pte_u_bit_set_04.S │ │ ├── vm_pte_u_bit_unset_level_0.S │ │ ├── vm_pte_u_bit_unset_level_1.S │ │ ├── vm_rwx_access_smode_01.S │ │ ├── vm_rwx_access_smode_02.S │ │ ├── vm_rwx_access_smode_03.S │ │ ├── vm_rwx_access_smode_04.S │ │ ├── vm_rwx_reserved_level_0.S │ │ ├── vm_rwx_reserved_level_1.S │ │ ├── vm_satp_access.S │ │ ├── vm_satp_asid.S │ │ ├── vm_satp_mode_set.S │ │ ├── vm_sum_clear_level_0.S │ │ ├── vm_sum_clear_level_1.S │ │ ├── vm_sum_set_level_0.S │ │ └── vm_sum_set_level_1.S │ └── zcmt │ │ ├── cm_jalt.S │ │ ├── cm_jalt_long.S │ │ ├── cm_jalt_long_ret.S │ │ ├── cm_jalt_ret.S │ │ ├── cm_jt.S │ │ ├── cm_jt_long.S │ │ └── jvt_csr.S │ ├── testlist_csr_embedded.yaml │ ├── testlist_custom.yaml │ ├── testlist_cvxif.yaml │ ├── testlist_hwconfig.yaml │ ├── testlist_interrupt.yaml │ ├── testlist_isacov.yaml │ ├── testlist_issues.yaml │ ├── testlist_riscv-arch-test-cv32a60x.yaml │ ├── testlist_riscv-arch-test-cv32a65x.yaml │ ├── testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml │ ├── testlist_riscv-compliance-cv32a60x.yaml │ ├── testlist_riscv-compliance-cv32a65x.yaml │ ├── testlist_riscv-compliance-cv32a6_imac_sv0.yaml │ ├── testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml │ ├── testlist_riscv-compliance-rv32ima.yaml │ ├── testlist_riscv-csr-access-test-cv32a60x.yaml │ ├── testlist_riscv-csr-access-test-cv32a65x.yaml │ ├── testlist_riscv-mmu-sv32-arch-test-cv32a6_imac_sv32.yaml │ ├── testlist_riscv-tests-cv32a60x-p.yaml │ ├── testlist_riscv-tests-cv32a60x-v.yaml │ ├── testlist_riscv-tests-cv32a65x-p.yaml │ ├── testlist_riscv-tests-cv32a6_imac_sv0-p.yaml │ ├── testlist_riscv-tests-cv32a6_imac_sv0-v.yaml │ ├── testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml │ ├── testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml │ ├── testlist_riscv-tests-rv32ima-p.yaml │ ├── testlist_riscv-tests-rv32ima-v.yaml │ └── uvmt │ ├── base-tests │ ├── uvmt_cva6_base_test.sv │ └── uvmt_cva6_test_cfg.sv │ ├── compliance-tests │ └── uvmt_cva6_firmware_test.sv │ └── vseq │ └── uvmt_cva6_vseq_lib.sv └── verilator_config.vlt /.editorconfig: -------------------------------------------------------------------------------- 1 | # top-most EditorConfig file 2 | root = true 3 | 4 | # Unix-style newlines with a newline ending every file 5 | [*] 6 | end_of_line = lf 7 | insert_final_newline = true 8 | trim_trailing_whitespace = true 9 | max_line_length = 100 10 | # 4 space indentation 11 | [*.{sv, svh, v, vhd}] 12 | indent_style = space 13 | indent_size = 2 14 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug.yaml: -------------------------------------------------------------------------------- 1 | name: CVA6 bug 2 | description: Create a CVA6 bug 3 | title: "[BUG] " 4 | labels: ["Type:Bug"] 5 | body: 6 | - type: checkboxes 7 | attributes: 8 | label: Is there an existing CVA6 bug for this? 9 | description: Please search to see if an issue already exist for the bug you need to create 10 | options: 11 | - label: I have searched the existing bug issues 12 | required: true 13 | - type: textarea 14 | attributes: 15 | label: Bug Description 16 | description: A concise description of the bug 17 | validations: 18 | required: true 19 | -------------------------------------------------------------------------------- /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | - package-ecosystem: "gitsubmodule" 4 | directory: "/" 5 | schedule: 6 | interval: "weekly" 7 | time: "19:30" 8 | timezone: "Europe/Paris" 9 | allow: 10 | - dependency-name: "core/cache_subsystem/hpdcache" 11 | - dependency-name: "verif/core-v-verif" 12 | - dependency-name: "verif/sim/dv" 13 | labels: [] 14 | -------------------------------------------------------------------------------- /.github/workflows/bender-up-to-date.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2023 ETH Zurich and University of Bologna. 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # Author: Nils Wistoff <nwistoff@iis.ee.ethz.ch> 6 | 7 | name: bender-up-to-date 8 | 9 | on: [ push, pull_request, workflow_dispatch ] 10 | 11 | jobs: 12 | bender-up-to-date: 13 | runs-on: ubuntu-latest 14 | steps: 15 | - name: Check Bender up-to-date 16 | uses: pulp-platform/pulp-actions/bender-up-to-date@v2 17 | -------------------------------------------------------------------------------- /.github/workflows/integration.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2024 PULP Platform 2 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | # Author: Nils Wistoff <nwistoff@iis.ee.ethz.ch> 6 | 7 | name: integration 8 | on: [ push, pull_request, workflow_dispatch ] 9 | 10 | jobs: 11 | cheshire-integration: 12 | runs-on: ubuntu-latest 13 | timeout-minutes: 200 14 | # Skip on forks due to missing secrets. 15 | if: github.repository == 'pulp-platform/cva6' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository) 16 | steps: 17 | - name: Integrate into cheshire 18 | uses: pulp-platform/pulp-actions/integrate@v2.3.0 19 | with: 20 | ip-name: cva6 21 | org: pulp-platform 22 | repo: cheshire 23 | base-ref: cva6/pulp-v2.0.0-alpha.1 24 | token: ${{ secrets.CHESHIRE_TOKEN }} 25 | lifetime: 14 26 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | site/* 2 | *.ucdb 3 | covhtmlreport/* 4 | work/* 5 | transcript 6 | *.ini 7 | *.wlf 8 | .moore 9 | *.vstf 10 | wlft* 11 | *nfs* 12 | src/moore.sv 13 | *.sig 14 | *.dtb 15 | *.dasm 16 | build/* 17 | /tmp* 18 | *.dasm 19 | /Bender.local 20 | build/ 21 | *.vcd 22 | *.fsdb 23 | *.log 24 | *.out 25 | *.jou 26 | *.o 27 | uart 28 | work-ver/* 29 | corev_apu/fpga/work-fpga 30 | corev_apu/fpga/reports/ 31 | corev_apu/fpga/scripts/add_sources.tcl 32 | corev_apu/fpga/ariane.xpr 33 | corev_apu/fpga/ariane.cache/ 34 | corev_apu/fpga/ariane.hw/ 35 | corev_apu/fpga/.Xil/ 36 | corev_apu/fpga/mode* 37 | stdout/ 38 | work-dpi/ 39 | tb/riscv-isa-sim/ 40 | work-*/* 41 | install/ 42 | xrun_results/ 43 | /core/include/hwconfig_config_pkg.sv 44 | __pycache__ 45 | .bender/ 46 | Bender.lock 47 | /tools/ 48 | /util/toolchain-builder/src/ 49 | /util/toolchain-builder/build/ 50 | # Both following lines are needed to list contents of ISA manual build dir. 51 | !/vendor/riscv/riscv-isa-manual/build/ 52 | !/vendor/riscv/riscv-isa-manual/build/* 53 | -------------------------------------------------------------------------------- /.gitlab-ci/expected_synth.yml: -------------------------------------------------------------------------------- 1 | cv32a65x: 2 | gates: 184679 3 | -------------------------------------------------------------------------------- /.gitlab-ci/scripts/report_envfail.py: -------------------------------------------------------------------------------- 1 | # Copyright 2023 Thales Silicon Security 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Côme ALLART - Thales 9 | 10 | import report_builder as rb 11 | 12 | metric = rb.TableStatusMetric('') 13 | metric.add_fail('Environment failure detected. Some reports might be missing') 14 | 15 | report = rb.Report() 16 | report.add_metric(metric) 17 | report.dump() 18 | -------------------------------------------------------------------------------- /.gitlab-ci/scripts/report_fail.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales Silicon Security 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) 9 | 10 | import report_builder as rb 11 | 12 | metric = rb.TableStatusMetric('') 13 | metric.add_fail('Job has failed before end of script') 14 | 15 | report = rb.Report() 16 | report.add_metric(metric) 17 | report.dump() 18 | -------------------------------------------------------------------------------- /.gitlab-ci/scripts/report_fpga_boot.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales Silicon Security 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com) 9 | 10 | import sys 11 | import report_builder as rb 12 | 13 | with open(str(sys.argv[1]), "r") as f: 14 | lastline = f.readlines()[-1] 15 | 16 | with open(str(sys.argv[1]), "r") as f: 17 | log = f.read() 18 | 19 | metric = rb.TableStatusMetric('Linux boot log') 20 | if not ("Linux buildroot" in lastline and "riscv" in lastline): 21 | metric.add_fail(lastline) 22 | else: 23 | metric.add_pass(lastline) 24 | 25 | report = rb.Report() 26 | report.add_metric(metric) 27 | report.dump() 28 | -------------------------------------------------------------------------------- /.gitlab-ci/scripts/report_pass.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales Silicon Security 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) 9 | 10 | import report_builder as rb 11 | 12 | metric = rb.TableStatusMetric('') 13 | metric.add_pass('Job completed without error. No metric extraction is configured') 14 | 15 | report = rb.Report() 16 | report.add_metric(metric) 17 | report.dump() 18 | -------------------------------------------------------------------------------- /ACKNOWLEDGEMENTS.md: -------------------------------------------------------------------------------- 1 | # Acknowledgements 2 | 3 | Thanks to Gian Marti, Thomas Kramer and Thomas E. Benz for implementing the PLIC. 4 | 5 | Some contributions to CVA6 are supported by the FRACTAL, TRISTAN and ISOLDE projects, 6 | which have received funding from the Chips Joint Undertaking (Chips JU), 7 | Austria, Belgium, Czechia, Finland, France, Germany, Italy, the Netherlands, Poland, Romania, Sweden, Switzerland, Spain and Turkey 8 | under grant agreements 877056, 101095947 and 101112274. 9 | The JU receives support from the European Union’s Horizon Europe research and innovation program. 10 | 11 | ![EU Logo](https://github.com/openhwgroup/tristan-unified-access-page/blob/main/images/logo_EU.png)         12 | ![ChipsJU Logo](https://github.com/openhwgroup/tristan-unified-access-page/blob/main/images/logo_chipsJU.png) 13 | -------------------------------------------------------------------------------- /CITATION.cff: -------------------------------------------------------------------------------- 1 | cff-version: 1.2.0 2 | message: "If you use this software, please cite it as below." 3 | authors: 4 | - family-names: "Zaruba" 5 | given-names: "Florian" 6 | orcid: "https://orcid.org/0000-0002-8194-6521" 7 | - family-names: "Benini" 8 | given-names: "Luca" 9 | orcid: "https://orcid.org/0000-0001-8068-3806" 10 | title: "The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology" 11 | version: 2.0.4 12 | doi: 10.1109/TVLSI.2019.2926114 13 | date-released: 2019-07-26 14 | url: "https://github.com/openhwgroup/cva6" 15 | -------------------------------------------------------------------------------- /CODEOWNERS: -------------------------------------------------------------------------------- 1 | # Global Owners 2 | * @niwis 3 | 4 | -------------------------------------------------------------------------------- /ci/build-hyp-riscv-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 4 | VERSION="9ace7ffdb384ed84075dbe6219d9c0c9431f278b" 5 | 6 | cd $ROOT/tmp 7 | 8 | if [ -z ${NUM_JOBS} ]; then 9 | NUM_JOBS=1 10 | fi 11 | 12 | [ -d $ROOT/tmp/riscv-hyp-tests ] || git clone https://github.com/ninolomata/riscv-hyp-tests 13 | cd riscv-hyp-tests 14 | git checkout $VERSION 15 | git submodule update --init --recursive 16 | make PLAT=cva6 -------------------------------------------------------------------------------- /ci/build-riscv-gcc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # call with first argument = 0 to checkout only 3 | 4 | set -e 5 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 6 | VERSION="691e4e826251c7ec59f883cab18440c87baf45e7" 7 | 8 | mkdir -p $RISCV 9 | 10 | cd $RISCV 11 | 12 | if [ -z ${NUM_JOBS} ]; then 13 | NUM_JOBS=1 14 | fi 15 | 16 | 17 | if ! [ -e $RISCV/bin ]; then 18 | if ! [ -e $RISCV/riscv-gnu-toolchain ]; then 19 | git clone https://github.com/riscv/riscv-gnu-toolchain.git 20 | fi 21 | 22 | cd riscv-gnu-toolchain 23 | git checkout $VERSION 24 | git submodule update --init --recursive 25 | 26 | if [[ $1 -ne "0" || -z ${1} ]]; then 27 | echo "Compiling RISC-V Toolchain" 28 | ./configure --prefix=$RISCV > /dev/null 29 | make -j${NUM_JOBS} > /dev/null 30 | echo "Compilation Finished" 31 | fi 32 | fi 33 | -------------------------------------------------------------------------------- /ci/build-riscv-tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | set -x 4 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 5 | VERSION="eeacd5507db7a0f50ca8c4f27aff220fcbb60bdf" 6 | 7 | cd $ROOT/tmp 8 | 9 | if [ -z ${NUM_JOBS} ]; then 10 | NUM_JOBS=1 11 | fi 12 | 13 | [ -d $ROOT/tmp/riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git 14 | cd riscv-tests 15 | git checkout $VERSION 16 | git submodule update --init --recursive 17 | autoconf 18 | mkdir -p build 19 | cd build 20 | ../configure --prefix=$ROOT/tmp/riscv-tests/build 21 | make isa -j${NUM_JOBS} > /dev/null 22 | make benchmarks -j${NUM_JOBS} > /dev/null 23 | make install 24 | -------------------------------------------------------------------------------- /ci/get-torture.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 4 | VERSION="59b0f0f224ff4f1eb6ebb1b4dd7eaf1ab3fac2e5" 5 | 6 | cd $ROOT/tmp 7 | 8 | if [ -z ${NUM_JOBS} ]; then 9 | NUM_JOBS=1 10 | fi 11 | 12 | [ -d $ROOT/tmp/riscv-torture ] || git clone https://github.com/ucb-bar/riscv-torture.git 13 | cd riscv-torture 14 | git checkout $VERSION 15 | git submodule update --init --recursive 16 | 17 | # copy ariane specific config 18 | cp config/default.config config/default.config.bak 19 | cp $ROOT/ci/float.config config/default.config 20 | git checkout ./output/Makefile 21 | git apply $ROOT/ci/torture_make.patch 22 | 23 | -------------------------------------------------------------------------------- /ci/install-dtc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 4 | VERSION="b94c056b137e59deefc62fbfe0cd3a23edfcc07c" 5 | 6 | cd $ROOT/tmp 7 | 8 | if [ -z ${NUM_JOBS} ]; then 9 | NUM_JOBS=1 10 | fi 11 | 12 | if [ ! -e "$RISCV/bin/dtc" ]; then 13 | echo "Installing DTC" 14 | git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git 15 | cd dtc 16 | git checkout $VERSION 17 | make -j${NUM_JOBS} PREFIX=$RISCV/ NO_PYTHON=1 18 | make -j${NUM_JOBS} check NO_PYTHON=1 19 | make -j${NUM_JOBS} install PREFIX=$RISCV/ NO_PYTHON=1 20 | else 21 | echo "Using DTC from cached directory." 22 | fi 23 | -------------------------------------------------------------------------------- /ci/install-fesvr.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 4 | VERSION="35d50bc40e59ea1d5566fbd3d9226023821b1bb6" 5 | 6 | cd $ROOT/tmp 7 | 8 | if [ -z ${NUM_JOBS} ]; then 9 | NUM_JOBS=1 10 | fi 11 | 12 | if [ ! -e "${RISCV}/bin/spike" ]; then 13 | echo "Installing fesvr" 14 | git clone https://github.com/riscv/riscv-isa-sim.git 15 | cd riscv-isa-sim 16 | git checkout $VERSION 17 | mkdir -p build 18 | cd build 19 | ../configure --prefix="$RISCV/" 20 | make install-config-hdrs install-hdrs libfesvr.a 21 | mkdir -p $RISCV/lib 22 | cp libfesvr.a $RISCV/lib 23 | else 24 | echo "Using fesvr from cached directory." 25 | fi 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /ci/install-prereq.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | echo 'deb http://download.opensuse.org/repositories/home:/phiwag:/edatools/xUbuntu_20.04/ /' | sudo tee /etc/apt/sources.list.d/home:phiwag:edatools.list 4 | curl -fsSL https://download.opensuse.org/repositories/home:phiwag:edatools/Debian_Unstable/Release.key | gpg --dearmor | sudo tee /etc/apt/trusted.gpg.d/home_phiwag_edatools.gpg > /dev/null 5 | 6 | sudo apt update 7 | sudo apt install device-tree-compiler libfl-dev help2man 8 | 9 | -------------------------------------------------------------------------------- /ci/install-spike.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 4 | VERSION="5f76a0d1fa68bb80560cb890405c42041f744e89" 5 | 6 | cd $ROOT/tmp 7 | 8 | if [ -z ${NUM_JOBS} ]; then 9 | NUM_JOBS=1 10 | fi 11 | 12 | if [ ! -e "${RISCV}/bin/spike" ]; then 13 | echo "Installing Spike" 14 | git clone https://github.com/riscv/riscv-isa-sim.git 15 | cd riscv-isa-sim 16 | git checkout $VERSION 17 | mkdir -p build 18 | cd build 19 | ../configure --prefix="$RISCV/" 20 | make -j${NUM_JOBS} 21 | make install 22 | else 23 | echo "Using Spike from cached directory." 24 | fi 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /ci/install-toolchain.sh: -------------------------------------------------------------------------------- 1 | 2 | export PATH=$RISCV/bin:/bin:$PATH 3 | export LIBRARY_PATH=$RISCV/lib 4 | export LD_LIBRARY_PATH=$RISCV/lib 5 | export C_INCLUDE_PATH=$RISCV/include 6 | export CPLUS_INCLUDE_PATH=$RISCV/include 7 | 8 | EMBECOSM_BASE=https://buildbot.embecosm.com/job/riscv32-gcc-ubuntu2204-release/10/artifact 9 | 10 | mkdir -p $RISCV && chmod 777 $RISCV 11 | 12 | [ ! -d $RISCV ] && sudo mkdir -p $RISCV && sudo chmod 777 $RISCV 13 | 14 | if [ ! -d $RISCV/bin ]; then 15 | RISCV64_UNKNOWN_ELF_GCC=riscv32-embecosm-ubuntu2204-gcc13.2.0.tar.gz 16 | if [ ! -f "$RISCV64_UNKNOWN_ELF_GCC" ]; then 17 | wget $EMBECOSM_BASE/$RISCV64_UNKNOWN_ELF_GCC --no-check-certificate 18 | fi 19 | tar -x -f $RISCV64_UNKNOWN_ELF_GCC --strip-components=1 -C $RISCV 20 | fi 21 | -------------------------------------------------------------------------------- /ci/make-tmp.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | cd "$(dirname "${BASH_SOURCE[0]}")/.." 4 | [ -d tmp ] || rm -rf tmp 5 | mkdir -p tmp 6 | -------------------------------------------------------------------------------- /ci/path-setup.sh: -------------------------------------------------------------------------------- 1 | # Customise this to a fast local disk 2 | export TOP=/scratch/$USER/projects 3 | export CI_BUILD_DIR=$TOP/ariane-repo 4 | 5 | #customize this to your setup 6 | export QUESTASIM_HOME= 7 | export QUESTASIM_VERSION= 8 | export QUESTASIM_FLAGS= 9 | export CXX=g++-7 CC=gcc-7 10 | 11 | # where to install the tools 12 | export RISCV=$TOP/riscv_install 13 | export VERILATOR_ROOT=$TOP/verilator-4.014/ 14 | 15 | export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH 16 | export LIBRARY_PATH=$RISCV/lib 17 | export LD_LIBRARY_PATH=$RISCV/lib 18 | export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include 19 | export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include 20 | 21 | # number of parallel jobs to use for make commands and simulation 22 | export NUM_JOBS=8 -------------------------------------------------------------------------------- /ci/riscv-amo-tests.list: -------------------------------------------------------------------------------- 1 | rv64ua-p-amoadd_d 2 | rv64ua-p-amoadd_w 3 | rv64ua-p-amoor_d 4 | rv64ua-p-amoor_w 5 | rv64ua-p-amoand_d 6 | rv64ua-p-amoand_w 7 | rv64ua-p-amoswap_d 8 | rv64ua-p-amoswap_w 9 | rv64ua-p-amoxor_d 10 | rv64ua-p-amoxor_w 11 | rv64ua-p-amomax_d 12 | rv64ua-p-amomaxu_d 13 | rv64ua-p-amomaxu_w 14 | rv64ua-p-amomax_w 15 | rv64ua-p-amomin_d 16 | rv64ua-p-amomin_w 17 | rv64ua-p-amominu_d 18 | rv64ua-p-amominu_w 19 | rv64ua-p-lrsc 20 | rv64ua-v-amoadd_d 21 | rv64ua-v-amoadd_w 22 | rv64ua-v-amoor_d 23 | rv64ua-v-amoor_w 24 | rv64ua-v-amoand_d 25 | rv64ua-v-amoand_w 26 | rv64ua-v-amoswap_d 27 | rv64ua-v-amoswap_w 28 | rv64ua-v-amoxor_d 29 | rv64ua-v-amoxor_w 30 | rv64ua-v-amomax_d 31 | rv64ua-v-amomaxu_d 32 | rv64ua-v-amomaxu_w 33 | rv64ua-v-amomax_w 34 | rv64ua-v-amomin_d 35 | rv64ua-v-amomin_w 36 | rv64ua-v-amominu_d 37 | rv64ua-v-amominu_w 38 | rv64ua-v-lrsc 39 | -------------------------------------------------------------------------------- /ci/riscv-benchmarks.list: -------------------------------------------------------------------------------- 1 | dhrystone.riscv 2 | median.riscv 3 | multiply.riscv 4 | qsort.riscv 5 | rsort.riscv 6 | towers.riscv 7 | vvadd.riscv 8 | pmp.riscv 9 | -------------------------------------------------------------------------------- /ci/riscv-fp-tests.list: -------------------------------------------------------------------------------- 1 | rv64uf-p-fadd 2 | rv64uf-p-fclass 3 | rv64uf-p-fcmp 4 | rv64uf-p-fcvt 5 | rv64uf-p-fcvt_w 6 | rv64uf-p-fdiv 7 | rv64uf-p-fmadd 8 | rv64uf-p-fmin 9 | rv64uf-p-ldst 10 | rv64uf-p-move 11 | rv64uf-p-recoding 12 | rv64uf-v-fadd 13 | rv64uf-v-fclass 14 | rv64uf-v-fcmp 15 | rv64uf-v-fcvt 16 | rv64uf-v-fcvt_w 17 | rv64uf-v-fdiv 18 | rv64uf-v-fmadd 19 | rv64uf-v-fmin 20 | rv64uf-v-ldst 21 | rv64uf-v-move 22 | rv64uf-v-recoding 23 | rv64ud-p-fadd 24 | rv64ud-p-fclass 25 | rv64ud-p-fcmp 26 | rv64ud-p-fcvt 27 | rv64ud-p-fcvt_w 28 | rv64ud-p-fdiv 29 | rv64ud-p-fmadd 30 | rv64ud-p-fmin 31 | rv64ud-p-ldst 32 | rv64ud-p-move 33 | rv64ud-p-recoding 34 | rv64ud-p-structural 35 | rv64ud-v-fadd 36 | rv64ud-v-fclass 37 | rv64ud-v-fcmp 38 | rv64ud-v-fcvt 39 | rv64ud-v-fcvt_w 40 | rv64ud-v-fdiv 41 | rv64ud-v-fmadd 42 | rv64ud-v-fmin 43 | rv64ud-v-ldst 44 | rv64ud-v-move 45 | rv64ud-v-recoding 46 | rv64ud-v-structural 47 | -------------------------------------------------------------------------------- /ci/riscv-mul-tests.list: -------------------------------------------------------------------------------- 1 | rv64um-p-div 2 | rv64um-p-divu 3 | rv64um-p-divuw 4 | rv64um-p-divw 5 | rv64um-p-mul 6 | rv64um-p-mulh 7 | rv64um-p-mulhsu 8 | rv64um-p-mulhu 9 | rv64um-p-mulw 10 | rv64um-p-rem 11 | rv64um-p-remu 12 | rv64um-p-remuw 13 | rv64um-p-remw 14 | rv64um-v-div 15 | rv64um-v-divu 16 | rv64um-v-divuw 17 | rv64um-v-divw 18 | rv64um-v-mul 19 | rv64um-v-mulh 20 | rv64um-v-mulhsu 21 | rv64um-v-mulhu 22 | rv64um-v-mulw 23 | rv64um-v-rem 24 | rv64um-v-remu 25 | rv64um-v-remuw 26 | rv64um-v-remw 27 | -------------------------------------------------------------------------------- /ci/setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e 3 | set -x 4 | export ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) 5 | export ROOT_PROJECT=$ROOT 6 | export RISCV=$ROOT_PROJECT/tools/riscv-toolchain/ 7 | 8 | export VERILATOR_INSTALL_DIR="$ROOT_PROJECT"/tools/verilator/ 9 | 10 | ci/make-tmp.sh 11 | 12 | bash ci/install-prereq.sh 13 | 14 | bash ci/install-toolchain.sh 15 | 16 | source verif/sim/setup-env.sh 17 | 18 | source verif/regress/install-verilator.sh 19 | if [ -d ${VERILATOR_BUILD_DIR} ]; then 20 | make -C ${VERILATOR_BUILD_DIR} clean 21 | fi 22 | 23 | if [ -f ${SPIKE_PATH}/spike ]; then 24 | spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h )" 25 | spike_installed_version="$(${SPIKE_PATH}/spike -v |& cut -d ' ' -f 2)" 26 | if [ "$spike_installed_version" != "$spike_version" ]; then 27 | rm -rf ${SPIKE_INSTALL_DIR} 28 | fi 29 | fi 30 | source verif/regress/install-spike.sh 31 | if [ -d ${SPIKE_SRC_DIR}/build/ ]; then 32 | make -C ${SPIKE_SRC_DIR}/build clean 33 | fi 34 | -------------------------------------------------------------------------------- /config/gen_from_riscv_config/requirements.txt: -------------------------------------------------------------------------------- 1 | docutils 2 | pyyaml 3 | mdutils 4 | restructuredtext-lint 5 | rstcloth 6 | regex 7 | Mako -------------------------------------------------------------------------------- /config/gen_from_riscv_config/updaters/cv32a65x/isa_updater.yaml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 OpenHW Group 2 | # Copyright (c) 2024 Thales 3 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | # Author: Abdessamii Oukalrazqou 5 | 6 | 7 | # Enable and disable extension 8 | Zicond : False 9 | 10 | Zcb : True 11 | 12 | Zcmp : False 13 | 14 | Zbb : False 15 | 16 | 17 | -------------------------------------------------------------------------------- /config/gen_from_riscv_config/updaters/cv32a65x/spike_updater.yaml: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2024 OpenHW Group 2 | # Copyright (c) 2024 Thales 3 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 4 | # Author: Abdessamii Oukalrazqou 5 | 6 | 7 | 8 | 9 | 10 | cores: 11 | - isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei 12 | boot_addr: 0x80000000 13 | marchid: 0x3 14 | misa_we: false 15 | misa_we_enable: true 16 | pmpaddr0: 0x0 17 | pmpcfg0: 0x0 18 | pmpregions: 0x40 19 | usable_pmpregions : 0x8 20 | priv: M 21 | status_fs_field_we: false 22 | status_fs_field_we_enable: false 23 | status_vs_field_we: false 24 | status_vs_field_we_enable: false 25 | priv: M 26 | misa_we: false 27 | mstatus_write_mask: 0x00000088 28 | mstatus_override_mask: 0x00001800 29 | mtval_write_mask: 0x00000000 30 | unified_traps: true 31 | 32 | -------------------------------------------------------------------------------- /core/pmp/Bender.yml: -------------------------------------------------------------------------------- 1 | package: 2 | name: pmp 3 | authors: 4 | - "Moritz Schneider <moritz.schneider@inf.ethz.ch>" 5 | 6 | export_include_dirs: 7 | - include 8 | 9 | sources: 10 | # packages 11 | - include/riscv.sv 12 | # sources 13 | - src/pmp_entry.sv 14 | - src/pmp.sv 15 | 16 | - target: simulation 17 | files: 18 | - tb/pmp_tb.sv -------------------------------------------------------------------------------- /core/pmp/README.md: -------------------------------------------------------------------------------- 1 | # PMP 2 | 3 | This repository houses a purely combinatorial and parametrizable physical memory protection (PMP) unit. 4 | 5 | __Warning__: The PMP unit does only check the exact byte that is addressed. If the processor wants to load a 8 byte value, then every single byte should get checked. Due to the default granularity of PMPs of 4 bytes, this only comes into play for 8byte RISC-V memory accesses. An easy fix is to increase the granularity to 8 bytes. You can do this by setting the lowest bit of conf_addr_i to 1 if the pmp is in NAPOT mode, or to 0 if the PMP is in TOR mode. -------------------------------------------------------------------------------- /core/pmp/formal.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode prove 3 | depth 5 4 | 5 | [engines] 6 | smtbmc boolector 7 | smtbmc z3 8 | smtbmc yices 9 | 10 | [script] 11 | verific -vlog-incdir ./include 12 | verific -sv \ 13 | riscv.sv \ 14 | pmp_entry.sv \ 15 | pmp.sv 16 | 17 | verific -import -all pmp 18 | prep -nordff -ifx -top pmp 19 | 20 | [files] 21 | include/riscv.sv 22 | src/pmp_entry.sv 23 | src/pmp.sv 24 | -------------------------------------------------------------------------------- /corev_apu/altera/constraints/SDC1.sdc: -------------------------------------------------------------------------------- 1 | set_false_path -from [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}] -to [get_clocks {clocks|iopll_0_outclk0}] 2 | set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}] 3 | set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {clocks|iopll_0_refclk}] 4 | set_false_path -from [get_clocks {clocks|iopll_0_refclk}] -to [get_clocks {clocks|iopll_0_outclk0}] 5 | set_disable_timing [get_ports led[*]] 6 | set_false_path -hold -through [get_pins -hierarchical "*async*"] 7 | set_max_delay -through [get_pins -hierarchical "*async*"] 5.000 8 | -------------------------------------------------------------------------------- /corev_apu/altera/io_standard_constraints.csv: -------------------------------------------------------------------------------- 1 | IO_STANDARD "1.2 V" -to cpu_resetn -entity cva6_altera 2 | IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to pll_ref_clk_p -entity cva6_altera 3 | IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_ddr4_ch0_p -entity cva6_altera 4 | IO_STANDARD "1.2 V" -to led[3] -entity cva6_altera 5 | IO_STANDARD "1.2 V" -to led[2] -entity cva6_altera 6 | IO_STANDARD "1.2 V" -to led[1] -entity cva6_altera 7 | IO_STANDARD "1.2 V" -to led[0] -entity cva6_altera 8 | -------------------------------------------------------------------------------- /corev_apu/altera/ip_files.csv: -------------------------------------------------------------------------------- 1 | ./test_mm_ccb_0.ip 2 | ./io_pll.ip 3 | ./iobuf.ip 4 | ./oddr_intel.ip 5 | ./iddr_intel.ip 6 | ./ed_synth_emif_fm_0.ip 7 | ./emif_cal.ip 8 | ./vJTAG.ip 9 | ./cva6_intel_jtag_uart_0.ip 10 | -------------------------------------------------------------------------------- /corev_apu/altera/search_paths.csv: -------------------------------------------------------------------------------- 1 | "../fpga/src/apb/include" 2 | "../fpga/src" 3 | "../fpga/" 4 | "../../vendor/pulp-platform/common_cells/include" 5 | "../../vendor/pulp-platform/axi/include" 6 | "../../core/cache_subsystem/hpdcache/rtl/include" 7 | "../../core/include" 8 | "../register_interface/include" 9 | "../" -------------------------------------------------------------------------------- /corev_apu/bootrom/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.img 3 | *.dtb 4 | -------------------------------------------------------------------------------- /corev_apu/bootrom/Makefile: -------------------------------------------------------------------------------- 1 | bootrom_img = bootrom.img bootrom.sv 2 | 3 | RISCV_GCC?=riscv64-unknown-elf-gcc 4 | RISCV_OBJCOPY?=riscv64-unknown-elf-objcopy 5 | DTB=ariane.dtb 6 | PYTHON=python 7 | 8 | all: $(bootrom_img) 9 | 10 | %.img: %.bin 11 | dd if=$< of=$@ bs=128 12 | 13 | %.bin: %.elf 14 | $(RISCV_OBJCOPY) -O binary $< $@ 15 | 16 | %.elf: %.S linker.ld $(DTB) 17 | $(RISCV_GCC) -Tlinker.ld -march=rv32i -mabi=ilp32 $< -nostdlib -static -Wl,--no-gc-sections -o $@ 18 | 19 | %.dtb: %.dts 20 | dtc -I dts $< -O dtb -o $@ 21 | 22 | %.sv: %.img 23 | $(PYTHON) ./gen_rom.py $< 24 | 25 | clean: 26 | rm -f $(bootrom_img) $(DTB) 27 | -------------------------------------------------------------------------------- /corev_apu/bootrom/bootrom.S: -------------------------------------------------------------------------------- 1 | .section .text.start, "ax", @progbits 2 | .globl _start 3 | _start: 4 | # bootrom.sv need to be functional in 64 and 32 bits, 5 | # li s0, DRAM_BASE creates instructions not compatible with both 6 | # versions. That's why we have replaced it by li and slli instructions 7 | # to generates code compatible with both versions. 8 | li s0, 1 9 | slli s0, s0, 31 10 | csrr a0, mhartid 11 | la a1, _dtb 12 | jr s0 13 | 14 | .section .text.hang, "ax", @progbits 15 | .globl _hang 16 | _hang: 17 | csrr a0, mhartid 18 | la a1, _dtb 19 | 1: 20 | wfi 21 | j 1b 22 | 23 | .section .rodata.dtb, "a", @progbits 24 | .globl _dtb 25 | .align 5, 0 26 | _dtb: 27 | .incbin "ariane.dtb" 28 | -------------------------------------------------------------------------------- /corev_apu/bootrom/linker.ld: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | ROM_BASE = 0x10000; /* ... but actually position independent */ 4 | 5 | . = ROM_BASE; 6 | .text.start : { *(.text.start) } 7 | . = ROM_BASE + 0x40; 8 | .text.hang : { *(.text.hang) } 9 | . = ROM_BASE + 0x80; 10 | .rodata.dtb : { *(.rodata.dtb) } 11 | } 12 | -------------------------------------------------------------------------------- /corev_apu/clint/README.md: -------------------------------------------------------------------------------- 1 | # CLINT (Core-local Interrupt Controller) 2 | 3 | This repository contains a RISC-V privilege spec 1.11 (WIP) compatible CLINT for the Ariane Core. 4 | 5 | The CLINT plugs into an existing AXI Bus with an AXI 4 Lite interface. The IP mirrors transaction IDs and is fully pin-compatible with the full AXI 4 interface. It does not support burst transfers (as specified in the AMBA 4 Bus specifcation) 6 | 7 | | Address | Description | Note | 8 | |-------------------|-------------|------------------------------------------------| 9 | | `BASE` + `0x0` | msip | Machine mode software interrupt (IPI) | 10 | | `BASE` + `0x4000` | mtimecmp | Machine mode timer compare register for Hart 0 | 11 | | `BASE` + `0xBFF8` | mtime | Timer register | 12 | -------------------------------------------------------------------------------- /corev_apu/fpga/ariane_pmod.cfg: -------------------------------------------------------------------------------- 1 | adapter_khz 1000 2 | 3 | interface ftdi 4 | # ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232" 5 | ftdi_vid_pid 0x15ba 0x002b 6 | 7 | ftdi_layout_init 0x0808 0x0a1b 8 | ftdi_layout_signal nSRST -oe 0x0200 9 | ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 10 | ftdi_layout_signal LED -data 0x0800 11 | 12 | set _CHIPNAME riscv 13 | jtag newtap $_CHIPNAME cpu -irlen 5 14 | 15 | set _TARGETNAME $_CHIPNAME.cpu 16 | # select the HART to debug with the coreid switch 17 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 18 | 19 | gdb_report_data_abort enable 20 | gdb_report_register_access_error enable 21 | 22 | riscv set_reset_timeout_sec 120 23 | riscv set_command_timeout_sec 120 24 | 25 | # prefer to use sba for system bus access 26 | riscv set_prefer_sba off 27 | 28 | init 29 | halt 30 | echo "Ready for Remote Connections" 31 | -------------------------------------------------------------------------------- /corev_apu/fpga/ariane_pmod_tiny.cfg: -------------------------------------------------------------------------------- 1 | adapter_khz 1000 2 | 3 | interface ftdi 4 | ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" 5 | ftdi_vid_pid 0x15ba 0x002a 6 | 7 | ftdi_layout_init 0x0808 0x0a1b 8 | ftdi_layout_signal nSRST -oe 0x0200 9 | ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 10 | ftdi_layout_signal LED -data 0x0800 11 | 12 | set _CHIPNAME riscv 13 | jtag newtap $_CHIPNAME cpu -irlen 5 14 | 15 | set _TARGETNAME $_CHIPNAME.cpu 16 | # select the HART to debug with the coreid switch 17 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 18 | 19 | gdb_report_data_abort enable 20 | gdb_report_register_access_error enable 21 | 22 | riscv set_reset_timeout_sec 120 23 | riscv set_command_timeout_sec 120 24 | 25 | # prefer to use sba for system bus access 26 | riscv set_prefer_sba off 27 | 28 | init 29 | halt 30 | echo "Ready for Remote Connections" 31 | -------------------------------------------------------------------------------- /corev_apu/fpga/scripts/check_fpga_boot.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Copyright 2022 Thales DIS design services SAS 3 | # 4 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 7 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 8 | # 9 | # Original Author: Guillaume CHAUVON (guillaume.chauvon@thalesgroup.com) 10 | 11 | 12 | BITSTREAM=../work-fpga/ariane_xilinx.bit 13 | 14 | if ! [ -n "$VIVADO_CMD" ]; then 15 | echo "Error: VIVADO_CMD variable undefined. 16 | It most likely should be VIVADO_CMD=vivado_lab if you installed 2022's version of vivado." 17 | return 18 | fi 19 | 20 | if [ -f "$BITSTREAM" ]; then 21 | $VIVADO_CMD -mode batch -source program_genesys2.tcl &&\ 22 | python3 linux_boot.py 23 | fi 24 | -------------------------------------------------------------------------------- /corev_apu/fpga/scripts/program_genesys2.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales DIS design services SAS 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Guillaume CHAUVON (guillaume.chauvon@thalesgroup.com) 9 | 10 | # Program Genesys2 FPGA board connected to $HW_SERVER_URL with bitstream ../work-fpga/ariane_xilinx.bit 11 | 12 | open_hw_manager 13 | # Connect to an HW_SERVER connected to the FPGA. 14 | # It is recommended to launch the hw_server before using this script to specify its URL. 15 | connect_hw_server -url $env(HW_SERVER_URL) 16 | open_hw_target 17 | current_hw_device [get_hw_devices xc7k325t_0] 18 | set_property PROGRAM.FILE {../work-fpga/ariane_xilinx.bit} [get_hw_device xc7k325t_0] 19 | program_hw_devices [get_hw_devices xc7k325t_0] 20 | refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0] 21 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/agilex7.svh: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Description: Set global FPGA degines 12 | // Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch> 13 | 14 | `define AGILEX7 15 | // include KINTEX7 specific code (relevant for KC705, GENESYSII,...) 16 | `define KINTEX7 17 | 18 | `define ARIANE_DATA_WIDTH 64 19 | 20 | // Instantiate protocl checker 21 | // `define PROTOCOL_CHECKER 22 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/.gitignore: -------------------------------------------------------------------------------- 1 | venv 2 | *.elf 3 | *.o 4 | *.img 5 | *.bin 6 | *.dts 7 | *.dtb 8 | bootrom*.h 9 | bootrom*.sv 10 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/gen_rom.py: -------------------------------------------------------------------------------- 1 | ../../../bootrom/gen_rom.py -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/linker.lds: -------------------------------------------------------------------------------- 1 | ENTRY(main) 2 | 3 | SECTIONS 4 | { 5 | ROM_BASE = 0x10000; /* ... but actually position independent */ 6 | 7 | . = ROM_BASE; 8 | 9 | .text.init : { *(.text.init) } 10 | 11 | .text : ALIGN(0x100) { 12 | _TEXT_START_ = .; 13 | *(.text) 14 | _TEXT_END_ = .; 15 | } 16 | 17 | .data : ALIGN(0x100) { 18 | _DATA_START_ = .; 19 | *(.data) 20 | _DATA_END_ = .; 21 | } 22 | 23 | PROVIDE(_data = ADDR(.data)); 24 | PROVIDE(_data_lma = LOADADDR(.data)); 25 | PROVIDE(_edata = .); 26 | 27 | .bss : ALIGN(0x100) { 28 | _BSS_START_ = .; 29 | *(.bss) 30 | _BSS_END_ = .; 31 | } 32 | 33 | .rodata : ALIGN(0x100) { 34 | _RODATA_START_ = .; 35 | *(.rodata) 36 | *(.dtb*) 37 | *(.rodata*) 38 | _RODATA_END_ = .; 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/platform.h: -------------------------------------------------------------------------------- 1 | #define DRAM_BASE 0x80000000 2 | #define DRAM_SIZE 0x4000000 -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/src/sd.h: -------------------------------------------------------------------------------- 1 | // Copyright OpenHW Group contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | #pragma once 6 | 7 | #include <stdint.h> 8 | 9 | #define SD_CMD_STOP_TRANSMISSION 12 10 | #define SD_CMD_READ_BLOCK_MULTIPLE 18 11 | #define SD_DATA_TOKEN 0xfe 12 | #define SD_COPY_ERROR_CMD18 -1 13 | #define SD_COPY_ERROR_CMD18_CRC -2 14 | 15 | // errors 16 | #define SD_INIT_ERROR_CMD0 -1 17 | #define SD_INIT_ERROR_CMD8 -2 18 | #define SD_INIT_ERROR_ACMD41 -3 19 | 20 | int init_sd(); 21 | 22 | void put_sdcard_spi_mode(); 23 | 24 | int sd_copy(void *dst, uint32_t src_lba, uint32_t size); 25 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/src/spi.h: -------------------------------------------------------------------------------- 1 | // Copyright OpenHW Group contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | #pragma once 6 | 7 | #include <stdint.h> 8 | 9 | #define SPI_BASE 0x20000000 10 | 11 | #define SPI_RESET_REG SPI_BASE + 0x40 12 | #define SPI_CONTROL_REG SPI_BASE + 0x60 13 | #define SPI_STATUS_REG SPI_BASE + 0x64 14 | #define SPI_TRANSMIT_REG SPI_BASE + 0x68 15 | #define SPI_RECEIVE_REG SPI_BASE + 0x6C 16 | #define SPI_SLAVE_SELECT_REG SPI_BASE + 0x70 17 | #define SPI_TRANSMIT_OCCUPANCY SPI_BASE + 0x74 18 | #define SPI_RECEIVE_OCCUPANCY SPI_BASE + 0x78 19 | #define SPI_INTERRUPT_GLOBAL_ENABLE_REG SPI_BASE + 0x1c 20 | #define SPI_INTERRUPT_STATUS_REG SPI_BASE + 0x20 21 | #define SPI_INTERRUPT_ENABLE_REG SPI_BASE + 0x28 22 | 23 | 24 | void spi_init(); 25 | 26 | uint8_t spi_txrx(uint8_t byte); 27 | 28 | // return -1 if something went wrong 29 | int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret); 30 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/src/uart.h: -------------------------------------------------------------------------------- 1 | // Copyright OpenHW Group contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | #pragma once 6 | 7 | #include <stdint.h> 8 | 9 | #define UART_BASE 0x10000000 10 | 11 | #define UART_RBR UART_BASE + 0 12 | #define UART_THR UART_BASE + 0 13 | #define UART_INTERRUPT_ENABLE UART_BASE + 4 14 | #define UART_INTERRUPT_IDENT UART_BASE + 8 15 | #define UART_FIFO_CONTROL UART_BASE + 8 16 | #define UART_LINE_CONTROL UART_BASE + 12 17 | #define UART_MODEM_CONTROL UART_BASE + 16 18 | #define UART_LINE_STATUS UART_BASE + 20 19 | #define UART_MODEM_STATUS UART_BASE + 24 20 | #define UART_DLAB_LSB UART_BASE + 0 21 | #define UART_DLAB_MSB UART_BASE + 4 22 | 23 | void init_uart(); 24 | 25 | int read_serial(uint8_t *res); 26 | 27 | void print_uart(const char* str); 28 | 29 | void print_uart_int(uint32_t addr); 30 | 31 | void print_uart_addr(uint64_t addr); 32 | 33 | void print_uart_byte(uint8_t byte); 34 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/bootrom/startup.S: -------------------------------------------------------------------------------- 1 | # start sequence of the bootloader 2 | # 3 | # 4 | #include <smp.h> 5 | #define DRAM_BASE 0x80000000 6 | 7 | .section .text.init 8 | .option norvc 9 | .globl _prog_start 10 | _prog_start: 11 | smp_pause(s1, s2) 12 | li sp, 0x84000000 13 | call main 14 | smp_resume(s1, s2) 15 | csrr a0, mhartid 16 | la a1, _dtb 17 | li s1, DRAM_BASE 18 | jr s1 19 | 20 | .section .dtb 21 | .globl _dtb 22 | .align 4, 0 23 | _dtb: 24 | #if __riscv_xlen == 64 25 | .incbin "cv64a6.dtb" 26 | #else 27 | .incbin "cv32a6.dtb" 28 | #endif 29 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/kc705.svh: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Description: Set global FPGA degines 12 | // Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch> 13 | 14 | `define KC705 15 | // include KINTEX7 specific code (relevant for KC705, GENESYSII,...) 16 | `define KINTEX7 17 | 18 | `define ARIANE_DATA_WIDTH 64 19 | 20 | // Instantiate protocl checker 21 | // `define PROTOCOL_CHECKER 22 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/nexys_video.svh: -------------------------------------------------------------------------------- 1 | `define NEXYS_VIDEO 2 | 3 | `define ARIANE_DATA_WIDTH 64 4 | 5 | // Instantiate protocl checker 6 | // `define PROTOCOL_CHECKER 7 | 8 | // write-back cache 9 | // `define WB_DCACHE 10 | 11 | // write-through cache 12 | `define WT_DCACHE 13 | 14 | `define RAMB16 15 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/vc707.svh: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Description: Set global FPGA degines 12 | // Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch> 13 | 14 | `define VC707 15 | 16 | `define ARIANE_DATA_WIDTH 64 17 | 18 | // Instantiate protocl checker 19 | // `define PROTOCOL_CHECKER 20 | -------------------------------------------------------------------------------- /corev_apu/fpga/src/vcu118.svh: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | // Description: Set global FPGA degines 12 | // Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch> 13 | 14 | `define VCU118 15 | -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/.gitignore: -------------------------------------------------------------------------------- 1 | xlnx*/* 2 | !xlnx*/tcl 3 | !Makefile 4 | !common.mk 5 | !*.prj -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/common.mk: -------------------------------------------------------------------------------- 1 | all: 2 | vivado -mode batch -source tcl/run.tcl 3 | 4 | gui: 5 | vivado -mode gui -source tcl/run.tcl & 6 | 7 | clean: 8 | rm -rf ip/* 9 | mkdir -p ip 10 | rm -rf ${PROJECT}.* 11 | rm -rf component.xml 12 | rm -rf vivado*.jou 13 | rm -rf vivado*.log 14 | rm -rf vivado*.str 15 | rm -rf xgui 16 | rm -rf .Xil 17 | -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_axi_clock_converter 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | set partNumber $::env(XILINX_PART) 2 | set boardName $::env(XILINX_BOARD) 3 | 4 | set ipName xlnx_axi_clock_converter 5 | 6 | create_project $ipName . -force -part $partNumber 7 | set_property board_part $boardName [current_project] 8 | 9 | create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName 10 | 11 | set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {5}] [get_ips $ipName] 12 | 13 | generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 14 | generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 15 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 16 | launch_run -jobs 8 ${ipName}_synth_1 17 | wait_on_run ${ipName}_synth_1 -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_axi_dwidth_converter 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | set partNumber $::env(XILINX_PART) 2 | set boardName $::env(XILINX_BOARD) 3 | 4 | set ipName xlnx_axi_dwidth_converter 5 | 6 | create_project $ipName . -force -part $partNumber 7 | set_property board_part $boardName [current_project] 8 | 9 | create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName 10 | 11 | set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] 12 | 13 | generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 14 | generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 15 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 16 | launch_run -jobs 8 ${ipName}_synth_1 17 | wait_on_run ${ipName}_synth_1 -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_axi_dwidth_converter_dm_master 2 | include ../common.mk 3 | -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | set partNumber $::env(XILINX_PART) 2 | set boardName $::env(XILINX_BOARD) 3 | 4 | set ipName xlnx_axi_dwidth_converter_dm_master 5 | 6 | create_project $ipName . -force -part $partNumber 7 | set_property board_part $boardName [current_project] 8 | 9 | create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName 10 | 11 | set_property -dict [list CONFIG.SI_DATA_WIDTH {32} CONFIG.SI_ID_WIDTH {4} CONFIG.MI_DATA_WIDTH {64}] [get_ips $ipName] 12 | 13 | generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 14 | generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 15 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 16 | launch_run -jobs 8 ${ipName}_synth_1 17 | wait_on_run ${ipName}_synth_1 18 | -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_axi_dwidth_converter_dm_slave 2 | include ../common.mk 3 | -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | set partNumber $::env(XILINX_PART) 2 | set boardName $::env(XILINX_BOARD) 3 | 4 | set ipName xlnx_axi_dwidth_converter_dm_slave 5 | 6 | create_project $ipName . -force -part $partNumber 7 | set_property board_part $boardName [current_project] 8 | 9 | create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName 10 | 11 | set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] 12 | 13 | generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 14 | generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 15 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 16 | launch_run -jobs 8 ${ipName}_synth_1 17 | wait_on_run ${ipName}_synth_1 18 | -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_axi_gpio 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | set partNumber $::env(XILINX_PART) 2 | set boardName $::env(XILINX_BOARD) 3 | 4 | set ipName xlnx_axi_gpio 5 | 6 | create_project $ipName . -force -part $partNumber 7 | set_property board_part $boardName [current_project] 8 | 9 | create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName 10 | set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName] 11 | 12 | generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 13 | generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 14 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 15 | launch_run -jobs 8 ${ipName}_synth_1 16 | wait_on_run ${ipName}_synth_1 -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_axi_quad_spi 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | set partNumber $::env(XILINX_PART) 2 | set boardName $::env(XILINX_BOARD) 3 | 4 | set ipName xlnx_axi_quad_spi 5 | 6 | create_project $ipName . -part $partNumber 7 | set_property board_part $boardName [current_project] 8 | 9 | create_ip -name axi_quad_spi -vendor xilinx.com -library ip -module_name $ipName 10 | set_property -dict [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SCK_RATIO {4} CONFIG.C_FIFO_DEPTH {256} CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} CONFIG.C_S_AXI4_ID_WIDTH {0}] [get_ips $ipName] 11 | 12 | generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 13 | generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 14 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] 15 | launch_run -jobs 8 ${ipName}_synth_1 16 | wait_on_run ${ipName}_synth_1 -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_clk_gen 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_ila/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_ila 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_mig_7_ddr3 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xlnx_protocol_checker 2 | include ../common.mk -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.img 3 | *.dtb 4 | *.sv 5 | -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/baremetal/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.img 3 | *.dtb 4 | *.sv 5 | *.h 6 | -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/baremetal/Makefile: -------------------------------------------------------------------------------- 1 | ../../../bootrom/Makefile -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/baremetal/ariane.dts: -------------------------------------------------------------------------------- 1 | ../ariane.dts -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/baremetal/bootrom.S: -------------------------------------------------------------------------------- 1 | ../../../bootrom/bootrom.S -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/baremetal/gen_rom.py: -------------------------------------------------------------------------------- 1 | ../../../bootrom/gen_rom.py -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/baremetal/linker.ld: -------------------------------------------------------------------------------- 1 | ../../../bootrom/linker.ld -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.elf 3 | *.img 4 | *.dtb 5 | *.sv 6 | 7 | -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/ariane.dts: -------------------------------------------------------------------------------- 1 | ../ariane.dts -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/gen_rom.py: -------------------------------------------------------------------------------- 1 | ../../../bootrom/gen_rom.py -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/info.h: -------------------------------------------------------------------------------- 1 | ../info.h -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/linker.lds: -------------------------------------------------------------------------------- 1 | ENTRY(main) 2 | 3 | SECTIONS 4 | { 5 | ROM_BASE = 0x10000; /* ... but actually position independent */ 6 | 7 | . = ROM_BASE; 8 | 9 | .text.init : { *(.text.init) } 10 | 11 | .text : ALIGN(0x100) { 12 | _TEXT_START_ = .; 13 | *(.text) 14 | _TEXT_END_ = .; 15 | } 16 | 17 | .data : ALIGN(0x100) { 18 | _DATA_START_ = .; 19 | *(.data) 20 | _DATA_END_ = .; 21 | } 22 | 23 | PROVIDE(_data = ADDR(.data)); 24 | PROVIDE(_data_lma = LOADADDR(.data)); 25 | PROVIDE(_edata = .); 26 | 27 | .bss : ALIGN(0x100) { 28 | _BSS_START_ = .; 29 | *(.bss) 30 | _BSS_END_ = .; 31 | } 32 | 33 | .rodata : ALIGN(0x100) { 34 | _RODATA_START_ = .; 35 | *(.rodata) 36 | *(.dtb*) 37 | *(.rodata*) 38 | _RODATA_END_ = .; 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/platform.h: -------------------------------------------------------------------------------- 1 | #define DRAM_BASE 0x80000000 2 | #define DRAM_SIZE 0x4000000 -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/src/main.c: -------------------------------------------------------------------------------- 1 | #include "uart.h" 2 | #include "spi.h" 3 | #include "sd.h" 4 | #include "gpt.h" 5 | #include "info.h" 6 | 7 | int main() 8 | { 9 | init_uart(UART_FREQ, 115200); 10 | print_uart(info); 11 | 12 | print_uart("sd initialized!\r\n"); 13 | 14 | int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); 15 | 16 | return 0; 17 | } 18 | 19 | void handle_trap(void) 20 | { 21 | // print_uart("trap\r\n"); 22 | } -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/src/sd.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include <stdint.h> 4 | 5 | #define SD_CMD_STOP_TRANSMISSION 12 6 | #define SD_CMD_READ_BLOCK_MULTIPLE 18 7 | #define SD_DATA_TOKEN 0xfe 8 | #define SD_COPY_ERROR_CMD18 -1 9 | #define SD_COPY_ERROR_CMD18_CRC -2 10 | 11 | // errors 12 | #define SD_INIT_ERROR_CMD0 -1 13 | #define SD_INIT_ERROR_CMD8 -2 14 | #define SD_INIT_ERROR_ACMD41 -3 15 | 16 | int init_sd(); 17 | 18 | void put_sdcard_spi_mode(); 19 | 20 | int sd_copy(void *dst, uint32_t src_lba, uint32_t size); -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/src/spi.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include <stdint.h> 4 | 5 | #define SPI_BASE 0x20000000 6 | 7 | #define SPI_RESET_REG SPI_BASE + 0x40 8 | #define SPI_CONTROL_REG SPI_BASE + 0x60 9 | #define SPI_STATUS_REG SPI_BASE + 0x64 10 | #define SPI_TRANSMIT_REG SPI_BASE + 0x68 11 | #define SPI_RECEIVE_REG SPI_BASE + 0x6C 12 | #define SPI_SLAVE_SELECT_REG SPI_BASE + 0x70 13 | #define SPI_TRANSMIT_OCCUPANCY SPI_BASE + 0x74 14 | #define SPI_RECEIVE_OCCUPANCY SPI_BASE + 0x78 15 | #define SPI_INTERRUPT_GLOBAL_ENABLE_REG SPI_BASE + 0x1c 16 | #define SPI_INTERRUPT_STATUS_REG SPI_BASE + 0x20 17 | #define SPI_INTERRUPT_ENABLE_REG SPI_BASE + 0x28 18 | 19 | 20 | void spi_init(); 21 | 22 | uint8_t spi_txrx(uint8_t byte); 23 | 24 | // return -1 if something went wrong 25 | int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret); -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/src/uart.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include <stdint.h> 4 | 5 | #define UART_BASE 0xFFF0C2C000 6 | 7 | #define UART_RBR UART_BASE + 0 8 | #define UART_THR UART_BASE + 0 9 | #define UART_INTERRUPT_ENABLE UART_BASE + 1 10 | #define UART_INTERRUPT_IDENT UART_BASE + 2 11 | #define UART_FIFO_CONTROL UART_BASE + 2 12 | #define UART_LINE_CONTROL UART_BASE + 3 13 | #define UART_MODEM_CONTROL UART_BASE + 4 14 | #define UART_LINE_STATUS UART_BASE + 5 15 | #define UART_MODEM_STATUS UART_BASE + 6 16 | #define UART_DLAB_LSB UART_BASE + 0 17 | #define UART_DLAB_MSB UART_BASE + 1 18 | 19 | void init_uart(); 20 | 21 | int print_uart(const char* str); 22 | 23 | int print_uart_dec(uint32_t val, uint32_t digits); 24 | 25 | int print_uart_int(uint32_t addr); 26 | 27 | int print_uart_addr(uint64_t addr); 28 | 29 | int print_uart_byte(uint8_t byte); 30 | -------------------------------------------------------------------------------- /corev_apu/openpiton/bootrom/linux/startup.S: -------------------------------------------------------------------------------- 1 | # start sequence of the bootloader 2 | # 3 | # 4 | #include <smp.h> 5 | #define DRAM_BASE 0x80000000 6 | 7 | .section .text.init 8 | .option norvc 9 | .globl _prog_start 10 | _prog_start: 11 | smp_pause(s1, s2) 12 | li sp, 0x84000000 13 | call main 14 | smp_resume(s1, s2) 15 | csrr a0, mhartid 16 | la a1, _dtb 17 | li s1, DRAM_BASE 18 | jr s1 19 | 20 | .section .dtb 21 | .globl _dtb 22 | .align 4, 0 23 | _dtb: 24 | .incbin "ariane.dtb" -------------------------------------------------------------------------------- /corev_apu/tb/dpi/SimJTAG.cc: -------------------------------------------------------------------------------- 1 | // See LICENSE.SiFive for license details. 2 | 3 | #include <cstdlib> 4 | #include "remote_bitbang.h" 5 | 6 | remote_bitbang_t* jtag; 7 | extern "C" int jtag_tick 8 | ( 9 | unsigned char * jtag_TCK, 10 | unsigned char * jtag_TMS, 11 | unsigned char * jtag_TDI, 12 | unsigned char * jtag_TRSTn, 13 | unsigned char jtag_TDO 14 | ) 15 | { 16 | if (!jtag) { 17 | // TODO: Pass in real port number 18 | jtag = new remote_bitbang_t(0); 19 | } 20 | 21 | jtag->tick(jtag_TCK, jtag_TMS, jtag_TDI, jtag_TRSTn, jtag_TDO); 22 | 23 | return jtag->done() ? (jtag->exit_code() << 1 | 1) : 0; 24 | 25 | } 26 | -------------------------------------------------------------------------------- /corev_apu/tb/dpi/bootrom.h: -------------------------------------------------------------------------------- 1 | ../../bootrom/bootrom.h -------------------------------------------------------------------------------- /corev_apu/tb/dpi/msim_helper.h: -------------------------------------------------------------------------------- 1 | // Author: Florian Zaruba 2 | // Description: ModelSim Helper Functions 3 | #ifndef _MSIM_HELPER_H 4 | #define _MSIM_HELPER_H 5 | 6 | #include <vector> 7 | #include <string> 8 | 9 | // sanitize htif arguments 10 | std::vector<std::string> sanitize_args(); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /corev_apu/tb/dpi/verilator.h: -------------------------------------------------------------------------------- 1 | #ifndef _ROCKET_VERILATOR_H 2 | #define _ROCKET_VERILATOR_H 3 | 4 | #include "verilated_vcd_c.h" 5 | #include <stdlib.h> 6 | #include <stdio.h> 7 | 8 | extern bool verbose; 9 | extern bool done_reset; 10 | 11 | class VerilatedVcdFILE : public VerilatedVcdFile { 12 | public: 13 | VerilatedVcdFILE(FILE* file) : file(file) {} 14 | ~VerilatedVcdFILE() {} 15 | bool open(const std::string& name) override { 16 | // file should already be open 17 | return file != NULL; 18 | } 19 | void close() override { 20 | // file should be closed elsewhere 21 | } 22 | ssize_t write(const char* bufp, ssize_t len) override { 23 | return fwrite(bufp, 1, len, file); 24 | } 25 | private: 26 | FILE* file; 27 | }; 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_cva6_icache/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | 8 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_cva6_icache/tb.list: -------------------------------------------------------------------------------- 1 | ../../../core/include/cv64a6_imafdc_sv39_config_pkg.sv 2 | ../../../core/include/riscv_pkg.sv 3 | ../../riscv-dbg/src/dm_pkg.sv 4 | ../../../core/include/ariane_pkg.sv 5 | ../../../core/include/wt_cache_pkg.sv 6 | ../../../vendor/pulp-platform/common_cells/src/cf_math_pkg.sv 7 | ../../../common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv 8 | ../../../core/cache_subsystem/cva6_icache.sv 9 | ../../../vendor/pulp-platform/common_cells/src/lfsr.sv 10 | ../../../vendor/pulp-platform/common_cells/src/fifo_v3.sv 11 | ../../../vendor/pulp-platform/common_cells/src/lzc.sv 12 | ../../../common/local/util/sram.sv 13 | hdl/mem_emul.sv 14 | hdl/tlb_emul.sv 15 | hdl/tb_pkg.sv 16 | hdl/tb.sv 17 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_cva6_icache/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -group TB /tb/* 4 | add wave -noupdate -expand -group icache /tb/dut/* 5 | add wave -noupdate -group mem_emul /tb/i_mem_emul/* 6 | add wave -noupdate -group tlb_emul /tb/i_tlb_emul/* 7 | TreeUpdate [SetDefaultTree] 8 | WaveRestoreCursors {{Cursor 1} {3047 ps} 0} 9 | quietly wave cursor active 1 10 | configure wave -namecolwidth 208 11 | configure wave -valuecolwidth 420 12 | configure wave -justifyvalue left 13 | configure wave -signalnamewidth 1 14 | configure wave -snapdistance 10 15 | configure wave -datasetprefix 0 16 | configure wave -rowmargin 4 17 | configure wave -childrowmargin 2 18 | configure wave -gridoffset 0 19 | configure wave -gridperiod 1 20 | configure wave -griddelta 40 21 | configure wave -timeline 0 22 | configure wave -timelineunits ps 23 | update 24 | WaveRestoreZoom {3049926 ps} {3050004 ps} 25 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_serdiv/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | 8 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_serdiv/tb.list: -------------------------------------------------------------------------------- 1 | ../../include/riscv_pkg.sv 2 | ../../src/riscv-dbg/src/dm_pkg.sv 3 | ../../include/ariane_pkg.sv 4 | ../../src/common_cells/src/lzc.sv 5 | ../../src/serdiv.sv 6 | hdl/tb_pkg.sv 7 | hdl/tb.sv 8 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_wb_dcache/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | 8 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_wt_axi_dcache/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | 8 | -------------------------------------------------------------------------------- /corev_apu/tb/tb_wt_dcache/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | *.rep 3 | transcript 4 | *.ini 5 | *.wlf 6 | *.log 7 | 8 | -------------------------------------------------------------------------------- /docs/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | /_build 3 | *.swp 4 | *.html 5 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_CV32A60AX.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _CSR_CV32A60AX: 20 | 21 | 22 | CV32A60AX Control Status Registers 23 | ================================== 24 | 25 | *This chapter is not yet available.* 26 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_CV32A60AX_list.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _CSR_CV32A60AX_list: 20 | 21 | 22 | CV32A60AX Control Status Registers List 23 | ======================================= 24 | 25 | *This chapter is not yet available.* 26 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_CV32A60X.rst: -------------------------------------------------------------------------------- 1 | .. include:: ../csr-from-ip-xact/cv32a60x/csr.rst -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_CV32A60X_list.rst: -------------------------------------------------------------------------------- 1 | .. include:: ../csr-from-ip-xact/cv32a60x/csr_list.rst -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_CV64A6_MMU.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _CSR_CV64A6_MMU: 20 | 21 | 22 | CV64A6_MMU Control Status Registers 23 | ================================== 24 | 25 | *This chapter is not yet available.* 26 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_CV64A6_MMU_list.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _CSR_CV64A6_MMU_list: 20 | 21 | 22 | CV64A6_MMU Control Status Registers List 23 | ======================================= 24 | 25 | *This chapter is not yet available.* 26 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CSR_Cache_Control.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _cva6_csr_cache_control: 20 | 21 | The team is looking for contributors for this chapter. 22 | 23 | CSR cache control 24 | ================= 25 | Which cache controls are available to the user, what they do, how to use them. 26 | Typical usage can also be mentioned. 27 | 28 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CV64A6_Control_Status_Registers.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _cv64a6_control_status_registers: 20 | 21 | CV64A6 Control and Status Registers 22 | =================================== 23 | CSR table (CV64A6) 24 | The CSR table generated by JADE (standalone file. Does it already exist?). 25 | 26 | -------------------------------------------------------------------------------- /docs/01_cva6_user/CVA6_user_guide.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _cva6_user_guide: 20 | 21 | OpenHW Group CVA6 User Manual 22 | ============================= 23 | This is the user guide of the CVA6 family and its verified configurations. 24 | 25 | Changelog 26 | --------- 27 | We will start filling in the Changelog after the first “official” release of a CVA6 configuration. In the meantime, GitHub history will prevail. 28 | 29 | -------------------------------------------------------------------------------- /docs/01_cva6_user/Compiler_Command_Lines.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _cva6_compiler_command_lines: 20 | 21 | *The team is looking for contributors for this chapter.* 22 | 23 | Compiler command lines 24 | ====================== 25 | Add GCC and LLVM command lines, compiler versions, options that work well with CVA6. 26 | 27 | Going further to fine tune the compiler options for performance, benchmarking, code density is not the scope here and would call for a white paper. 28 | 29 | -------------------------------------------------------------------------------- /docs/01_cva6_user/Custom_Instructions.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | 7 | .. Level 1 8 | ======= 9 | 10 | Level 2 11 | ------- 12 | 13 | Level 3 14 | ~~~~~~~ 15 | 16 | Level 4 17 | ^^^^^^^ 18 | 19 | .. _cva6_custom_instructions: 20 | 21 | *This chapter is applicable to all configurations.* 22 | 23 | Custom RISC-V instructions 24 | ========================== 25 | As of now, CVA6 does not implement custom RISC-V instructions. 26 | 27 | The team is looking for contributors to implement the ``fence.t`` instruction that ensures that the execution time of subsequent instructions is unrelated with predecessor instructions. 28 | 29 | The user or integrator can also use the CV-X-IF coprocessor interface to implement their own extensions, without modifying the core. 30 | -------------------------------------------------------------------------------- /docs/01_cva6_user/images/jade_design_automation_logo.png: -------------------------------------------------------------------------------- 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It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. 5 | 6 | 7 | Scope and Purpose 8 | ----------------- 9 | 10 | The purpose of the core is to run a full OS at reasonable speed and IPC. To achieve the necessary speed the core features a 6-stage pipelined design. In order to increase the IPC the CPU features a scoreboard which should hide latency to the data RAM (cache) by issuing data-independent instructions. 11 | The instruction RAM has (or L1 instruction cache) an access latency of 1 cycle on a hit, while accesses to the data RAM (or L1 data cache) have a longer latency of 3 cycles on a hit. 12 | 13 | .. image:: _static/ariane_overview.drawio.png 14 | :alt: Ariane Block Diagram 15 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/design/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/design/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Thales DIS France SAS 2 | # Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); 3 | # you may not use this file except in compliance with the License. 4 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 5 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 6 | # 7 | # Original Author: Thales DIS 8 | 9 | CONFIG := cv32a65x 10 | include ../../design/build.mk 11 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/design/design.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2024 Thales 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | 10 | CV32A65X DESIGN DOCUMENT 11 | ======================== 12 | 13 | .. raw:: html 14 | 15 | <style> 16 | .wy-nav-content { 17 | max-width: none; 18 | } 19 | </style> 20 | 21 | .. raw:: html 22 | :file: design-cv32a65x.html 23 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/design/source/images/CV32A65X_subsystems.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/docs/04_cv32a65x/design/source/images/CV32A65X_subsystems.png -------------------------------------------------------------------------------- /docs/04_cv32a65x/index.rst: -------------------------------------------------------------------------------- 1 | CV32A65X documentation 2 | ====================== 3 | 4 | .. toctree:: 5 | :maxdepth: 1 6 | 7 | riscv/unpriv.rst 8 | riscv/priv.rst 9 | design/design.rst 10 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/riscv/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Thales DIS France SAS 2 | # Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); 3 | # you may not use this file except in compliance with the License. 4 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 5 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 6 | # 7 | # Original Author: Thales DIS 8 | 9 | CONFIG := cv32a65x 10 | include ../../riscv-isa/build.mk 11 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/riscv/priv.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2024 Thales 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | 10 | Privileged RISC-V ISA 11 | ===================== 12 | 13 | .. raw:: html 14 | :file: priv-isa-cv32a65x.html 15 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/riscv/unpriv.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2024 Thales 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | 10 | Unprivileged RISC-V ISA 11 | ======================= 12 | 13 | .. raw:: html 14 | :file: unpriv-isa-cv32a65x.html 15 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/tristan/README.md: -------------------------------------------------------------------------------- 1 | This directory contains documents written for Tristan project. 2 | 3 | - [Verification Specifications](./verif-spec/verification_specifications.adoc) 4 | This document describes the CVA6 verification strategy and implementation. 5 | - [Tandem-Based Verification](./tandem-verification/tandem.adoc) 6 | This document describes the CVA6 tandem (lockstep) verification infrastructure and contains associated User and Reference Manuals. 7 | -------------------------------------------------------------------------------- /docs/04_cv32a65x/tristan/verif-spec/media/axiagentmerge.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/docs/04_cv32a65x/tristan/verif-spec/media/axiagentmerge.png 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-------------------------------------------------------------------------------- /docs/05_cva6_apu/index.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2023 OpenHW Group 3 | Copyright (c) 2023 Thales DIS design services SAS 4 | 5 | Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | 9 | https://solderpad.org/licenses/ 10 | 11 | Unless required by applicable law or agreed to in writing, software 12 | distributed under the License is distributed on an "AS IS" BASIS, 13 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | See the License for the specific language governing permissions and 15 | limitations under the License. 16 | 17 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 18 | 19 | CVA6 APU 20 | ======== 21 | Editor: **Florian Zaruba** 22 | `florian@openhwgroup.org <mailto:florian@openhwgroup.org?subject=CVA6%20User%20Manual>`__ 23 | 24 | .. toctree:: 25 | :maxdepth: 2 26 | :caption: Contents: 27 | 28 | cva6_apu 29 | cva6_testharness 30 | -------------------------------------------------------------------------------- /docs/06_cv64a6_mmu/index.rst: -------------------------------------------------------------------------------- 1 | CV64A6_MMU documentation 2 | ====================== 3 | 4 | .. toctree:: 5 | :maxdepth: 1 6 | 7 | riscv/unpriv.rst 8 | riscv/priv.rst 9 | -------------------------------------------------------------------------------- /docs/06_cv64a6_mmu/riscv/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Thales DIS France SAS 2 | # Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); 3 | # you may not use this file except in compliance with the License. 4 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 5 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 6 | # 7 | # Original Author: Thales DIS 8 | 9 | CONFIG := cv64a6_mmu 10 | include ../../riscv-isa/build.mk 11 | -------------------------------------------------------------------------------- /docs/06_cv64a6_mmu/riscv/priv.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2024 Thales 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | 10 | Privileged RISC-V ISA 11 | ===================== 12 | 13 | .. raw:: html 14 | :file: priv-isa-cv64a6_mmu.html 15 | -------------------------------------------------------------------------------- /docs/06_cv64a6_mmu/riscv/unpriv.rst: -------------------------------------------------------------------------------- 1 | .. 2 | Copyright (c) 2024 Thales 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | 10 | Unprivileged RISC-V ISA 11 | ======================= 12 | 13 | .. raw:: html 14 | :file: unpriv-isa-cv64a6_mmu.html 15 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | all: prepare sphinx 2 | 3 | prepare: 4 | make -C 04_cv32a65x/riscv priv-html unpriv-html 5 | make -C 04_cv32a65x/design design-html 6 | 7 | make -C 06_cv64a6_mmu/riscv priv-html unpriv-html 8 | 9 | sphinx: 10 | sphinx-build . _build 11 | 12 | .PHONY: all prepare sphinx 13 | -------------------------------------------------------------------------------- /docs/_static/theme_overrides.css: -------------------------------------------------------------------------------- 1 | @media screen { 2 | /* content column 3 | * 4 | * RTD theme's default is 800px as max width for the content, but we have 5 | * tables with tons of columns, which need the full width of the view-port. 6 | * 7 | * Comment from yocto project theme_overrides.css 8 | */ 9 | 10 | .wy-nav-content{ max-width: none; } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/AXI.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2023 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | [[axi]] 11 | 12 | include::AXI_Interface.adoc[] 13 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/CSRs.adoc: -------------------------------------------------------------------------------- 1 | [[csrs]] 2 | 3 | include::csr/csr.adoc[] -------------------------------------------------------------------------------- /docs/design/design-manual/source/CVXIF.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2023 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[cvxif]] 12 | 13 | include::CVX_Interface_Coprocessor.adoc[] 14 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/cva6_caches.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2024 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[CVA6_CACHES]] 12 | CACHES Module 13 | ~~~~~~~~~~~~~ 14 | 15 | [[caches-description]] 16 | Description 17 | ^^^^^^^^^^^ 18 | 19 | The CACHES module implements an instruction cache, a data cache and an 20 | AXI adapter. 21 | 22 | The module is connected to: 23 | 24 | * TO_BE_COMPLETED 25 | 26 | include::port_cva6_hpdcache_subsystem.adoc[] 27 | 28 | [[caches-functionality]] 29 | Functionality 30 | ^^^^^^^^^^^^^ 31 | 32 | TO BE COMPLETED 33 | 34 | [[caches-submodules]] 35 | Submodules 36 | ^^^^^^^^^^ 37 | 38 | image:caches.png[CACHES submodules] 39 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/cva6_controller.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2024 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[CVA6_CONTROLLER]] 12 | CONTROLLER Module 13 | ~~~~~~~~~~~~~~~~~ 14 | 15 | [[controller-description]] 16 | Description 17 | ^^^^^^^^^^^ 18 | 19 | The CONTROLLER module implements ... TO BE COMPLETED 20 | 21 | The module is connected to: 22 | 23 | * TO BE COMPLETED 24 | 25 | include::port_controller.adoc[] 26 | 27 | [[controller-functionality]] 28 | Functionality 29 | ^^^^^^^^^^^^^ 30 | 31 | TO BE COMPLETED 32 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/cva6_csr_regfile.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2024 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[CVA6_CSR_REGFILE]] 12 | CSR_REGFILE Module 13 | ~~~~~~~~~~~~~~~~~~ 14 | 15 | [[csr_regfile-description]] 16 | Description 17 | ^^^^^^^^^^^ 18 | 19 | The CSR_REGFILE module implements ... TO BE COMPLETED 20 | 21 | The module is connected to: 22 | 23 | * TO BE COMPLETED 24 | 25 | include::port_csr_regfile.adoc[] 26 | 27 | [[csr_regfile-functionality]] 28 | Functionality 29 | ^^^^^^^^^^^^^ 30 | 31 | TO BE COMPLETED 32 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/functionality.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2023 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[functionality]] 12 | Functionality 13 | ------------- 14 | 15 | include::instructions.adoc[] 16 | include::traps.adoc[] 17 | include::CSRs.adoc[] 18 | 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/docs/design/design-manual/source/images/subsystems.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/docs/design/design-manual/source/images/subsystems.png -------------------------------------------------------------------------------- /docs/design/design-manual/source/images/update_tree.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/docs/design/design-manual/source/images/update_tree.png -------------------------------------------------------------------------------- /docs/design/design-manual/source/instructions.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2023 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[instructions]] 12 | Instructions 13 | ~~~~~~~~~~~~ 14 | 15 | The next subchapter lists the extensions implemented in {ohg-config}. By 16 | configuration, we can enable/disable the extensions. {ohg-config} supports 17 | the extensions described in the next subchapters. 18 | 19 | include::isa/isa.adoc[] 20 | -------------------------------------------------------------------------------- /docs/design/design-manual/source/traps.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | Copyright 2023 Thales DIS France SAS 3 | Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | 8 | Original Author: Jean-Roch COULON - Thales 9 | //// 10 | 11 | [[traps]] 12 | 13 | include::Traps_Interrupts_Exceptions.adoc[] 14 | 15 | 16 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | sphinx>=3.1.2 2 | sphinx-rtd-theme 3 | recommonmark 4 | sphinxcontrib-svg2pdfconverter 5 | sphinx_github_changelog 6 | 7 | # for gen_from_riscv_config 8 | mako 9 | mdutils 10 | pyyaml 11 | rstcloth 12 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/a-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[atomics]] 2 | == "A" Extension for Atomic Instructions, Version 2.1 3 | 4 | ifeval::[{RVA} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/bfloat16.adoc: -------------------------------------------------------------------------------- 1 | [[bf16]] 2 | == "BF16" Extensions for for BFloat16-precision Floating-Point, Version 1.0 3 | 4 | ifeval::[{RVZfbf-RZvfbf} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/calling-convention.adoc: -------------------------------------------------------------------------------- 1 | [appendix] 2 | == Calling Convention for Vector State (Not authoritative - Placeholder Only) 3 | 4 | ifeval::[{RVV} == false] 5 | {ohg-config}: This appendix is not applicable as vector extension is 6 | not supported. 7 | endif::[] 8 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/cmo.adoc: -------------------------------------------------------------------------------- 1 | [[cmo]] 2 | == "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0 3 | 4 | ifeval::[{RVZicbo} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/d-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[double-float]] 2 | == "D" Extension for Double-Precision Floating-Point, Version 2.2 3 | 4 | ifeval::[{RVD} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/f-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[single-float]] 2 | == "F" Extension for Single-Precision Floating-Point, Version 2.2 3 | 4 | ifeval::[{RVF} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/hypervisor.adoc: -------------------------------------------------------------------------------- 1 | [[hypervisor]] 2 | == "H" Extension for Hypervisor Support, Version 1.0 3 | 4 | ifeval::[{RVH} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/images/ohg_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/docs/riscv-isa/src/images/ohg_logo.png -------------------------------------------------------------------------------- /docs/riscv-isa/src/indirect-csr.adoc: -------------------------------------------------------------------------------- 1 | [[indirect-csr]] 2 | == "Smcsrind/Sscsrind" Indirect CSR Access, Version 1.0 3 | 4 | ifeval::[{RVZsmcsrind-RVZsscsrind} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/mm-formal.adoc: -------------------------------------------------------------------------------- 1 | [appendix] 2 | == Formal Memory Model Specifications, Version 0.1 3 | [[mm-formal]] 4 | 5 | ifeval::["{ohg-config}" == "CV32A65X"] 6 | {ohg-config}: No RVWMO memory model. 7 | endif::[] 8 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/priv-cfi.adoc: -------------------------------------------------------------------------------- 1 | [[priv-cfi]] 2 | == Control-flow Integrity (CFI) 3 | 4 | ifeval::[{RVZicfiss} == false] 5 | {ohg-config}: The Zicfiss extension is not supported. 6 | endif::[] 7 | 8 | ifeval::[{RVZicfilp} == false] 9 | {ohg-config}: The Zicfilp extension is not supported. 10 | endif::[] 11 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/q-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[quad-float]] 2 | == "Q" Extension for Quad-Precision Floating-Point, Version 2.2 3 | 4 | ifeval::[{RVQ} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/rnmi.adoc: -------------------------------------------------------------------------------- 1 | [[rnmi]] 2 | == "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0 3 | 4 | ifeval::[{RVZsmrnmi} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/rv128.adoc: -------------------------------------------------------------------------------- 1 | [[rv128]] 2 | == RV128I Base Integer Instruction Set, Version 1.7 3 | 4 | ifeval::[{XLEN} != 128] 5 | {ohg-config}: This instruction set is not supported. 6 | endif::[] 7 | 8 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/rv32e.adoc: -------------------------------------------------------------------------------- 1 | [[rv32e]] 2 | == RV32E and RV64E Base Integer Instruction Sets, Version 2.0 3 | 4 | ifeval::[{RVE} == false] 5 | {ohg-config}: These instruction sets are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/scalar-crypto.adoc: -------------------------------------------------------------------------------- 1 | [[crypto_scalar_instructions]] 2 | == Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 3 | 4 | ifeval::[{RVZk} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/smcdeleg.adoc: -------------------------------------------------------------------------------- 1 | [[smcdeleg]] 2 | == "Smcdeleg" Counter Delegation Extension, Version 1.0 3 | 4 | ifeval::[{RVZsmcdeleg} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/smcntrpmf.adoc: -------------------------------------------------------------------------------- 1 | [[smcntrpmf]] 2 | == "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0 3 | 4 | ifeval::[{RVZsmcntrpmf} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/smctr.adoc: -------------------------------------------------------------------------------- 1 | [[smctr]] 2 | 3 | == "Smctr" Control Transfer Records Extension, Version 1.0 4 | 5 | ifeval::[{RVZsmctr} == false] 6 | {ohg-config}: This extension is not supported. 7 | endif::[] 8 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/smdbltrp.adoc: -------------------------------------------------------------------------------- 1 | [[smdbltrp]] 2 | == "Smdbltrp" Double Trap Extension, Version 1.0 3 | 4 | ifeval::[{RVZsmdbltrp} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/smepmp.adoc: -------------------------------------------------------------------------------- 1 | [[smepmp]] 2 | == "Smepmp" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 3 | 4 | ifeval::[{RVZsmepmp} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/smstateen.adoc: -------------------------------------------------------------------------------- 1 | [[smstateen]] 2 | == "Smstateen/Ssstateen" Extensions, Version 1.0 3 | 4 | ifeval::[{RVZsmstateen} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/sscofpmf.adoc: -------------------------------------------------------------------------------- 1 | [[Sscofpmf]] 2 | == "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 3 | 4 | ifeval::[{RVZsscofpmf} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/ssdbltrp.adoc: -------------------------------------------------------------------------------- 1 | [[ssdbltrp]] 2 | == "Ssdbltrp" Double Trap Extension, Version 1.0 3 | 4 | ifeval::[{RVZssdbltrp} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/sstc.adoc: -------------------------------------------------------------------------------- 1 | [[Sstc]] 2 | == "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0 3 | 4 | ifeval::[{RVZsstc} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/unpriv-cfi.adoc: -------------------------------------------------------------------------------- 1 | [[unpriv-cfi]] 2 | == Control-flow Integrity (CFI) 3 | 4 | ifeval::[{RVZicfiss} == false] 5 | {ohg-config}: The Zicfiss extension is not supported. 6 | endif::[] 7 | 8 | ifeval::[{RVZicfilp} == false] 9 | {ohg-config}: The Zicfilp extension is not supported. 10 | endif::[] 11 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/v-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[vector]] 2 | == "V" Standard Extension for Vector Operations, Version 1.0 3 | 4 | ifeval::[{RVV} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/vector-crypto.adoc: -------------------------------------------------------------------------------- 1 | [[vector-crypto]] 2 | == Cryptography Extensions: Vector Instructions, Version 1.0 3 | 4 | ifeval::[{RVZvk} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/vector-examples.adoc: -------------------------------------------------------------------------------- 1 | [appendix] 2 | == Vector Assembly Code Examples 3 | 4 | ifeval::[{RVV} == false] 5 | {ohg-config}: This appendix is not applicable as vector extension is 6 | not supported. 7 | endif::[] 8 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zabha.adoc: -------------------------------------------------------------------------------- 1 | [[zabha]] 2 | == "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 3 | 4 | ifeval::[{RVZabha} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zacas.adoc: -------------------------------------------------------------------------------- 1 | [[chap:zacas]] 2 | == "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 3 | 4 | ifeval::[{RVZacas} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zawrs.adoc: -------------------------------------------------------------------------------- 1 | [[chap:zawrs]] 2 | == "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01 3 | 4 | ifeval::[{RVZawrs} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zfa.adoc: -------------------------------------------------------------------------------- 1 | [[zfa]] 2 | == "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0 3 | 4 | ifeval::[{RVZfa} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zfh.adoc: -------------------------------------------------------------------------------- 1 | [[zfh]] 2 | == "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0 3 | 4 | ifeval::[{RVZfh} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zfinx.adoc: -------------------------------------------------------------------------------- 1 | [[sec:zfinx]] 2 | == "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0 3 | 4 | ifeval::[{RVZfinx} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zicond.adoc: -------------------------------------------------------------------------------- 1 | [[Zicond]] 2 | == "Zicond" Extension for Integer Conditional Operations, Version 1.0.0 3 | 4 | ifeval::[{RVZicond} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zifencei.adoc: -------------------------------------------------------------------------------- 1 | [[zifencei]] 2 | == "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0 3 | 4 | ifeval::[{RVZifencei} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zihintntl.adoc: -------------------------------------------------------------------------------- 1 | [[chap:zihintntl]] 2 | == "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0 3 | 4 | ifeval::[{RVZihintntl} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zihintpause.adoc: -------------------------------------------------------------------------------- 1 | [[zihintpause]] 2 | == "Zihintpause" Extension for Pause Hint, Version 2.0 3 | 4 | ifeval::[{RVZihintpause} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zimop.adoc: -------------------------------------------------------------------------------- 1 | [[zimop]] 2 | == "Zimop" Extension for May-Be-Operations, Version 1.0 3 | 4 | ifeval::[{RVZimop} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | 8 | === "Zcmop" Compressed May-Be-Operations Extension, Version 1.0 9 | 10 | ifeval::[{RVZimop} == false] 11 | {ohg-config}: This extension is not supported. 12 | endif::[] 13 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/zpm.adoc: -------------------------------------------------------------------------------- 1 | [[Zpm]] 2 | == Pointer Masking Extensions, Version 1.0.0 3 | 4 | ifeval::[{RVZpm} == false] 5 | {ohg-config}: These extensions are not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /docs/riscv-isa/src/ztso-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[ztso]] 2 | == "Ztso" Extension for Total Store Ordering, Version 1.0 3 | 4 | ifeval::[{RVZtso} == false] 5 | {ohg-config}: This extension is not supported. 6 | endif::[] 7 | -------------------------------------------------------------------------------- /pd/synth/.gitignore: -------------------------------------------------------------------------------- 1 | work 2 | netlist 3 | reports 4 | alib-52 5 | command.tcl 6 | command_read.tcl 7 | default.svf 8 | cva6_* 9 | Flist.* 10 | pes.bat 11 | simv* 12 | -------------------------------------------------------------------------------- /pd/synth/cva6_read.tcl: -------------------------------------------------------------------------------- 1 | # Copyright 2021 Thales DIS design services SAS 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Jean-Roch COULON - Thales 9 | # 10 | 11 | source -echo -verbose scripts/dc_setup.tcl 12 | 13 | read_ddc ${DCRM_FINAL_DDC_OUTPUT_FILE} 14 | -------------------------------------------------------------------------------- /util/CODEOWNERS: -------------------------------------------------------------------------------- 1 | # Global Owners 2 | * @JeanRochCoulon @zarubaf 3 | 4 | # Core 5 | 6 | core/mmu_sv39 @sjthales 7 | core/cvxif_example @Gchauvon 8 | core/cvxif_fu.sv @Gchauvon 9 | 10 | # APU 11 | 12 | corev_apu/openpiton @Jbalkind 13 | 14 | ## Documentation 15 | 16 | docs/ @jquevremont 17 | -------------------------------------------------------------------------------- /util/README.md: -------------------------------------------------------------------------------- 1 | Content: 2 | 3 | * vendor.py 4 | - vendorization script 5 | - copied from https://github.com/openhwgroup/cv32e40p/blob/master/util/vendor.py, commit 69e839e 6 | -------------------------------------------------------------------------------- /util/init_gate.do: -------------------------------------------------------------------------------- 1 | fsdbDumpvars 0 "ariane_gate_tb" +all +trace_process 2 | -------------------------------------------------------------------------------- /util/init_testharness.do: -------------------------------------------------------------------------------- 1 | fsdbDumpvars 0 "ariane_tb" +all +trace_process 2 | -------------------------------------------------------------------------------- /util/parse_ila_trace.py: -------------------------------------------------------------------------------- 1 | import csv 2 | 3 | with open('iladata.csv', 'r') as csvfile: 4 | csvreader = csv.reader(csvfile, delimiter=',', quotechar='|') 5 | for row in csvreader: 6 | if (row[5] == '1'): 7 | print(row[3]) 8 | if (row[6] == '1'): 9 | print(row[4]) 10 | # print(', '.join(row[])); -------------------------------------------------------------------------------- /vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch: -------------------------------------------------------------------------------- 1 | diff --git a/vendor/pulp-platform/common_cells/src/popcount.sv b/vendor/pulp-platform/common_cells/src/popcount.sv 2 | index 72b9b71f0..6fde114f3 100644 3 | --- a/vendor/pulp-platform/common_cells/src/popcount.sv 4 | +++ b/vendor/pulp-platform/common_cells/src/popcount.sv 5 | @@ -30,10 +30,7 @@ module popcount #( 6 | logic [PopcountWidth-2:0] left_child_result, right_child_result; 7 | 8 | //Zero pad the input to next power of two 9 | - always_comb begin 10 | - padded_input = '0; 11 | - padded_input[INPUT_WIDTH-1:0] = data_i; 12 | - end 13 | + assign padded_input = {{{PaddedWidth-INPUT_WIDTH}{1'b0}}, data_i}; 14 | 15 | //Recursive instantiation to build binary adder tree 16 | if (INPUT_WIDTH == 1) begin : single_node 17 | -------------------------------------------------------------------------------- /vendor/patches/riscv/riscv-config/0003-add-mtval-roconst0-schema.patch: -------------------------------------------------------------------------------- 1 | diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml 2 | index a972efb14..a7536375f 100644 3 | --- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml 4 | +++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml 5 | @@ -3594,7 +3594,9 @@ hart_schema: 6 | lsb: {type: integer, default: 0, allowed: [0]} 7 | type: 8 | type: dict 9 | - schema: { warl: *ref_warl } 10 | + oneof: 11 | + - schema: { ro_constant: {type: integer, default: 0x0, allowed: [0x0]}} 12 | + - schema: { warl: *ref_warl } 13 | default: 14 | warl: 15 | dependency_fields: [] 16 | -------------------------------------------------------------------------------- /vendor/pulp-platform/axi/.gitignore: -------------------------------------------------------------------------------- 1 | .* 2 | !.git* 3 | !.ci/ 4 | /.git/ 5 | /build 6 | /Bender.lock 7 | /Bender.local 8 | -------------------------------------------------------------------------------- /vendor/pulp-platform/axi/VERSION: -------------------------------------------------------------------------------- 1 | 0.31.0 2 | -------------------------------------------------------------------------------- /vendor/pulp-platform/common_cells/.gitignore: -------------------------------------------------------------------------------- 1 | .* 2 | !.travis.yml 3 | !.git* 4 | *.out 5 | *~ 6 | /Bender.lock 7 | /Bender.local 8 | build 9 | formal/fifo_v3 10 | formal/counter 11 | formal/fall_through_register 12 | *.check 13 | *.vcd 14 | obj_dir/ 15 | -------------------------------------------------------------------------------- /vendor/pulp-platform/common_cells/src/binary_to_gray.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // Fabian Schuiki <fschuiki@iis.ee.ethz.ch> 13 | 14 | /// A binary to gray code converter. 15 | module binary_to_gray #( 16 | parameter int N = -1 17 | )( 18 | input logic [N-1:0] A, 19 | output logic [N-1:0] Z 20 | ); 21 | assign Z = A ^ (A >> 1); 22 | endmodule 23 | -------------------------------------------------------------------------------- /vendor/pulp-platform/common_cells/src/unread.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | // 11 | // Author: Florian Zaruba, ETH Zurich 12 | // Date: 29.10.2018 13 | // Description: Dummy circuit to mitigate Open Pin warnings 14 | 15 | /* verilator lint_off UNUSED */ 16 | module unread ( 17 | input logic d_i 18 | ); 19 | 20 | endmodule 21 | /* verilator lint_on UNUSED */ 22 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/BramDwc/.gitignore: -------------------------------------------------------------------------------- 1 | /work/* 2 | 3 | /*.log 4 | /*.out 5 | /*.wlf 6 | 7 | /modelsim.ini 8 | /transcript 9 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/BramDwc/README.md: -------------------------------------------------------------------------------- 1 | # BRAM Data Width Converter Behavioral Testbench 2 | 3 | ## Running Tests 4 | 5 | This module depends on the `CfMath` package. You have to specify the path to this package when 6 | running tests. If this module is not used as part of the `big.pulp` project, specify the correct 7 | path to the package in `CF_MATH_PKG_PATH`, e.g., 8 | 9 | CF_MATH_PKG_PATH=../../../../../fe/ips/pkg/cfmath make 10 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run.tcl: -------------------------------------------------------------------------------- 1 | run -all 2 | 3 | # vim: syntax=tcl 4 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run_gui.tcl: -------------------------------------------------------------------------------- 1 | source ./scripts/waves.tcl 2 | 3 | source ./scripts/run.tcl 4 | 5 | # vim: syntax=tcl 6 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/waves.tcl: -------------------------------------------------------------------------------- 1 | quietly WaveActivateNextPane {} 0 2 | 3 | configure wave -signalnamewidth 1 4 | 5 | delete wave * 6 | 7 | add wave -noupdate /Testbench/Clk_C 8 | add wave -noupdate /Testbench/Rst_RB 9 | add wave -noupdate /Testbench/EndOfSim_S 10 | 11 | add wave -noupdate -expand -group Bram_PM /Testbench/Bram_PM/* 12 | add wave -noupdate -expand -group Bram_PS /Testbench/Bram_PS/* 13 | add wave -noupdate -expand /Testbench/ExpResp 14 | 15 | update 16 | 17 | # vim: syntax=tcl 18 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/Makefile: -------------------------------------------------------------------------------- 1 | TARGETS = $(filter-out common/.,$(wildcard */.)) 2 | 3 | .PHONY: all ${TARGETS} 4 | all: ${TARGETS} 5 | 6 | ${TARGETS}: 7 | $(MAKE) -C $@ 8 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/behav/common/gitignore: -------------------------------------------------------------------------------- 1 | /work/* 2 | 3 | /*.log 4 | /*.out 5 | /*.wlf 6 | 7 | /modelsim.ini 8 | /transcript 9 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/BramDwc/.gitignore: -------------------------------------------------------------------------------- 1 | /*.jou 2 | /*.log 3 | /vivado.* 4 | /vivado_pid*.str 5 | /.Xil/* 6 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/BramDwc/Makefile: -------------------------------------------------------------------------------- 1 | VER = 2016.1 2 | VIVADO_SOURCE_CMDS = -source scripts/setup.tcl -source scripts/synthesize.tcl 3 | 4 | CF_MATH_PKG_PATH = ../../../../ips/pkg/cfmath 5 | 6 | nogui: pkgdeps synth_nogui 7 | 8 | gui: pkgdeps synth_gui 9 | 10 | pkgdeps: 11 | @if [ ! -e $(CF_MATH_PKG_PATH)/CfMath.sv ]; then \ 12 | echo "Error: Dependency 'CfMath.sv' not found, please specify 'CF_MATH_PKG_PATH'!"; \ 13 | exit 1; \ 14 | fi; \ 15 | ln -t deps/ -sf ../$(CF_MATH_PKG_PATH)/CfMath.sv 16 | 17 | synth_nogui: 18 | @vivado-${VER} vivado -mode batch $(VIVADO_SOURCE_CMDS) 19 | 20 | synth_gui: 21 | @vivado-${VER} vivado -mode gui $(VIVADO_SOURCE_CMDS) 22 | 23 | clean: 24 | @rm -f *.jou *.log vivado_*.str 25 | @rm -rf vivado.* 26 | 27 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/BramDwc/README.md: -------------------------------------------------------------------------------- 1 | # BRAM Data Width Converter Synthesis Testbench 2 | 3 | ## Running Tests 4 | 5 | This module depends on the `CfMath` package. You have to specify the path to this package when 6 | running tests. If this module is not used as part of the `big.pulp` project, specify the correct 7 | path to the package in `CF_MATH_PKG_PATH`, e.g., 8 | 9 | CF_MATH_PKG_PATH=../../../../../fe/ips/pkg/cfmath make 10 | 11 | ## TODO 12 | 13 | - Post-synthesis simulation 14 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/BramDwc/deps/.gitignore: -------------------------------------------------------------------------------- 1 | /CfMath.sv 2 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/setup.tcl: -------------------------------------------------------------------------------- 1 | # Create project. 2 | create_project vivado . -force -part xc7vx485tffg1157-1 3 | 4 | # Downgrade warning about "ignoring assertions" to information. 5 | set_msg_config -id {[Synth 8-2898]} -new_severity "info" 6 | 7 | # Add source files to project. 8 | add_files -norecurse -scan_for_includes [glob ./deps/*] 9 | add_files -norecurse -scan_for_includes [glob ./src/*] 10 | 11 | # Define top-level module. 12 | set_property top Top [current_fileset] 13 | 14 | # Update compile order (must do if in batch mode). 15 | update_compile_order -fileset [current_fileset] 16 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/synthesize.tcl: -------------------------------------------------------------------------------- 1 | synth_design -name synth_1 2 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/common/Makefile: -------------------------------------------------------------------------------- 1 | VER = 2016.1 2 | VIVADO_SOURCE_CMDS = -source scripts/setup.tcl -source scripts/synthesize.tcl 3 | 4 | CF_MATH_PKG_PATH = ../../../../ips/pkg/cfmath 5 | 6 | nogui: pkgdeps synth_nogui 7 | 8 | gui: pkgdeps synth_gui 9 | 10 | pkgdeps: 11 | @if [ ! -e $(CF_MATH_PKG_PATH)/CfMath.sv ]; then \ 12 | echo "Error: Dependency 'CfMath.sv' not found, please specify 'CF_MATH_PKG_PATH'!"; \ 13 | exit 1; \ 14 | fi; \ 15 | ln -t deps/ -sf ../$(CF_MATH_PKG_PATH)/CfMath.sv 16 | 17 | synth_nogui: 18 | @vivado-${VER} vivado -mode batch $(VIVADO_SOURCE_CMDS) 19 | 20 | synth_gui: 21 | @vivado-${VER} vivado -mode gui $(VIVADO_SOURCE_CMDS) 22 | 23 | clean: 24 | @rm -f *.jou *.log vivado_*.str 25 | @rm -rf vivado.* 26 | 27 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/common/gitignore: -------------------------------------------------------------------------------- 1 | /*.jou 2 | /*.log 3 | /vivado.* 4 | /vivado_pid*.str 5 | /.Xil/* 6 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/common/scripts/setup.tcl: -------------------------------------------------------------------------------- 1 | # Create project. 2 | create_project vivado . -force -part xc7vx485tffg1157-1 3 | 4 | # Downgrade warning about "ignoring assertions" to information. 5 | set_msg_config -id {[Synth 8-2898]} -new_severity "info" 6 | 7 | # Add source files to project. 8 | add_files -norecurse -scan_for_includes [glob ./deps/*] 9 | add_files -norecurse -scan_for_includes [glob ./src/*] 10 | 11 | # Define top-level module. 12 | set_property top Top [current_fileset] 13 | 14 | # Update compile order (must do if in batch mode). 15 | update_compile_order -fileset [current_fileset] 16 | -------------------------------------------------------------------------------- /vendor/pulp-platform/fpga-support/synth/common/scripts/synthesize.tcl: -------------------------------------------------------------------------------- 1 | synth_design -name synth_1 2 | -------------------------------------------------------------------------------- /vendor/pulp-platform/tech_cells_generic/.gitignore: -------------------------------------------------------------------------------- 1 | .* 2 | !.git* 3 | build 4 | scripts/vivado/add_sources.tcl 5 | /Bender.lock 6 | /Bender.local 7 | -------------------------------------------------------------------------------- /vendor/pulp-platform/tech_cells_generic/CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing 2 | 3 | See [our style and contribution guidelines](https://github.com/pulp-platform/style-guidelines). -------------------------------------------------------------------------------- /vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_buffer.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2018 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the "License"); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module pulp_buffer 12 | ( 13 | input logic in_i, 14 | output logic out_o 15 | ); 16 | 17 | assign out_o = in_i; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /vendor/pulp-platform_axi.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/pulp-platform/axi.git 12 | rev: 697f13ff67153a5243e347f2d1992a125018b6c2 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/pulp-platform_common_cells.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/pulp-platform/common_cells.git 12 | rev: dc555643226419b7a602f0aa39d449545ea4c1f2 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/pulp-platform_fpga-support.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/pulp-platform/fpga-support.git 12 | rev: a3ba269c0fc6cfcee6f81e5d9af018a08e479d2b 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/pulp-platform_fpga-support.vendor.hjson: -------------------------------------------------------------------------------- 1 | // -*- coding: utf-8 -*- 2 | // Copyright (C) 2023 Thales Silicon Security SAS 3 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. 4 | // Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) 5 | 6 | { 7 | // Name of the project 8 | name: "pulp_fpga-support", 9 | 10 | // Target directory: relative to the location of this script. 11 | target_dir: "pulp-platform/fpga-support", 12 | 13 | // Upstream repository 14 | upstream: { 15 | // URL 16 | url: "https://github.com/pulp-platform/fpga-support.git", 17 | // revision 18 | rev: "a3ba269c0fc6cfcee6f81e5d9af018a08e479d2b", 19 | } 20 | 21 | // Patch dir for local changes 22 | patch_dir: "patches/pulp-platform/fpga-support", 23 | 24 | // Exclusions from upstream content 25 | exclude_from_upstream: [ 26 | "ci", 27 | ".editorconfig", 28 | "src_files.yml", 29 | ] 30 | } 31 | -------------------------------------------------------------------------------- /vendor/pulp-platform_tech_cells_generic.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/pulp-platform/tech_cells_generic.git 12 | rev: 7968dd6e6180df2c644636bc6d2908a49f2190cf 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/pulp-platform_tech_cells_generic.vendor.hjson: -------------------------------------------------------------------------------- 1 | // -*- coding: utf-8 -*- 2 | // Copyright (C) 2022 Thales DIS France SAS 3 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. 4 | // Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) 5 | 6 | { 7 | // Name of the project 8 | name: "pulp_tech_cells_generic", 9 | 10 | // Target directory: relative to the location of this script. 11 | target_dir: "pulp-platform/tech_cells_generic", 12 | 13 | // Upstream repository 14 | upstream: { 15 | // URL 16 | url: "https://github.com/pulp-platform/tech_cells_generic.git", 17 | // revision 18 | rev: "v0.2.13", 19 | } 20 | 21 | // Patch dir for local changes 22 | patch_dir: "patches/pulp-platform/tech_cells_generic", 23 | 24 | // Exclusions from upstream content 25 | exclude_from_upstream: [ 26 | "Bender.yml", 27 | "scripts", 28 | "src_files.yml", 29 | "test", 30 | ] 31 | } 32 | 33 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/.git_hooks/pre-commit: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | ### Pre Commit Hook For The Shakti BLUESPEC codebase 4 | status=0; 5 | ### Check for Dependencies 6 | yapf --help 7 | status=$?; 8 | if [ $status -ne 0 ]; then 9 | echo "Please install yapf from :: https://github.com/google/yapf " 10 | exit $status; 11 | fi 12 | 13 | ### Hook Script Body 14 | echo "Running Pre-Commit YAPF Hook"; 15 | 16 | files=`git diff --cached --name-status | awk '$1 != "D" { print $2 }'` 17 | 18 | echo "$files" 19 | 20 | 21 | for f in $files 22 | do 23 | if [[ $f == *.py ]]; then 24 | echo "Formatting $f using YAPF." 25 | yapf -i --style google $f 26 | git add $f 27 | fi 28 | done 29 | 30 | status=$?; 31 | exit $status; 32 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/.git_hooks/setup.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Setup the git hooks 4 | echo "Setting up git-hooks" 5 | echo "====================" 6 | 7 | echo "Launched from" $(pwd) 8 | echo "" 9 | 10 | echo "Setting up pre-commit" 11 | ln -s -f ../../.git_hooks/pre-commit ./.git/hooks/pre-commit 12 | chmod a+x ./.git/hooks/pre-commit 13 | echo "Done" 14 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/.gitignore: -------------------------------------------------------------------------------- 1 | docs/build 2 | docs/source/schema_isa.rst 3 | docs/source/schema_platform.rst 4 | docs/source/schema_debug.rst 5 | 6 | run.log 7 | 8 | __pycache__/* 9 | 10 | *.pyc 11 | 12 | riscv_config_work/* 13 | .python-version 14 | 15 | riscv_config.egg-info/ 16 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/MANIFEST.in: -------------------------------------------------------------------------------- 1 | recursive-include schemas *.yaml 2 | exclude *.pyc -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/README.rst: -------------------------------------------------------------------------------- 1 | RISCV-Config 2 | ============== 3 | 4 | RISC-V Configuration Validator 5 | 6 | LICENSE: BSD-3 Clause. 7 | 8 | Latest Documentation of RISCV-Config: `HTML <https://riscv-config.readthedocs.io/>`_ 9 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/Makefile: -------------------------------------------------------------------------------- 1 | # See LICENSE for details 2 | 3 | # Minimal makefile for Sphinx documentation 4 | # 5 | 6 | # You can set these variables from the command line. 7 | SPHINXOPTS = 8 | SPHINXBUILD = sphinx-build 9 | SPHINXPROJ = riscv_config 10 | SOURCEDIR = source 11 | BUILDDIR = build 12 | 13 | # Put it first so that "make" without argument is like "make help". 14 | help: 15 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 16 | 17 | .PHONY: help Makefile 18 | 19 | # Catch-all target: route all unknown targets to Sphinx using the new 20 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 21 | %: Makefile 22 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 23 | 24 | clean: 25 | @$(SPHINXBUILD) -M clean "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 26 | 27 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/README.md: -------------------------------------------------------------------------------- 1 | # Build the docs 2 | 3 | ## For PDF 4 | ``` 5 | pip install -r requirements.txt 6 | make latexpdf 7 | evince build/latex/*.pdf 8 | ``` 9 | 10 | ## HTML 11 | ``` 12 | pip install -r requirements.txt 13 | make html 14 | firefox build/html/index.html 15 | ``` 16 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/requirements.txt: -------------------------------------------------------------------------------- 1 | alabaster==0.7.12 2 | Babel==2.7.0 3 | Cerberus==1.3.1 4 | certifi==2019.6.16 5 | chardet==3.0.4 6 | doc8==0.8.0 7 | docutils==0.14 8 | gitdb2==2.0.5 9 | idna==2.8 10 | imagesize==1.1.0 11 | Jinja2==2.10.1 12 | MarkupSafe==1.1.1 13 | oyaml==0.9 14 | packaging==19.0 15 | pbr==5.3.1 16 | Pygments==2.4.2 17 | pyparsing==2.4.0 18 | python-dateutil==2.8.0 19 | pytz==2019.1 20 | PyYAML==5.1.1 21 | requests==2.22.0 22 | restructuredtext-lint==1.3.0 23 | ruamel.yaml==0.15.97 24 | six==1.12.0 25 | smmap2==2.0.5 26 | snowballstemmer==1.2.1 27 | Sphinx==3.0.4 28 | sphinx-rtd-theme==0.4.3 29 | sphinxcontrib-autoyaml==0.5.0 30 | sphinxcontrib-mermaid 31 | sphinxcontrib-websupport==1.1.2 32 | sphinxcontrib-bibtex==1.0.0 33 | stevedore==1.30.1 34 | urllib3==1.25.3 35 | twine==1.13.0 36 | sphinx_tabs 37 | m2r2==0.2.7 38 | mistune==0.8.4 39 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/_static/Tall_2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/vendor/riscv/riscv-config/docs/source/_static/Tall_2.png -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/_static/theme_overrides.css: -------------------------------------------------------------------------------- 1 | /* override table width restrictions */ 2 | @media screen and (min-width: 767px) { 3 | 4 | .wy-table-responsive table td { 5 | /* !important prevents the common CSS stylesheets from overriding 6 | this as on RTD they are loaded after this stylesheet */ 7 | white-space: normal !important; 8 | } 9 | 10 | .wy-table-responsive { 11 | overflow: visible !important; 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/_templates/breadcrumbs.html: -------------------------------------------------------------------------------- 1 | {% extends "!breadcrumbs.html" %} 2 | {% block breadcrumbs %} 3 | <!-- {{ docs_title }} --> 4 | {# parameterize default name "Docs" in breadcrumb via docs_title in conf.py #} 5 | {% if not docs_title %} 6 | {% set docs_title = "Docs" %} 7 | {% endif %} 8 | 9 | <li><a href="{{ pathto(master_doc) }}">{{ docs_title }}</a> »</li> 10 | {% for doc in parents %} 11 | <li><a href="{{ doc.link|e }}">{{ doc.title }}</a> »</li> 12 | {% endfor %} 13 | <li>{{ title }}</li> 14 | {% endblock %} 15 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/_templates/layout.html: -------------------------------------------------------------------------------- 1 | {% extends "!layout.html" %} 2 | {% block document %} 3 | {% if is_release %} 4 | <div class="wy-alert wy-alert-danger"> 5 | The <a href="/latest/{{ pagename }}.html">latest development version</a> 6 | of this page may be more current than this released {{ version }} version. 7 | </div> 8 | {% endif %} 9 | {{ super() }} 10 | {% endblock %} 11 | {% block menu %} 12 | {% include "versions.html" %} 13 | {{ super() }} 14 | {% endblock %} 15 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/code-doc.rst: -------------------------------------------------------------------------------- 1 | ################## 2 | Code Documentation 3 | ################## 4 | .. _checker: 5 | 6 | riscv_config.checker 7 | --------------------- 8 | 9 | .. automodule:: riscv_config.checker 10 | :members: 11 | :special-members: 12 | :private-members: 13 | 14 | .. _schemaValidator: 15 | 16 | riscv_config.schemaValidator 17 | ---------------------------- 18 | .. automodule:: riscv_config.schemaValidator 19 | :members: 20 | :special-members: 21 | :private-members: 22 | 23 | 24 | Utils 25 | ----- 26 | 27 | .. automodule:: riscv_config.utils 28 | :members: 29 | :special-members: 30 | :private-members: 31 | 32 | WARL 33 | ---- 34 | 35 | .. automodule:: riscv_config.warl 36 | :members: 37 | :special-members: 38 | :private-members: 39 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/index.rst: -------------------------------------------------------------------------------- 1 | ####################### 2 | Welcome to RISCV-Config 3 | ####################### 4 | 5 | Welcome to RISC-V Configuration Validator documentation. 6 | 7 | For information about the changes and additions for releases, 8 | please refer to the :ref:`Revisions <revisions>` documentation. 9 | 10 | .. toctree:: 11 | :glob: 12 | :numbered: 13 | 14 | intro 15 | overview 16 | quickstart 17 | yaml-specs 18 | new-extensions 19 | CONTRIBUTING 20 | code-doc 21 | revisions 22 | 23 | Indices and tables 24 | ------------------ 25 | 26 | * :ref:`genindex` 27 | * :ref:`modindex` 28 | * :ref:`search` 29 | 30 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/intro.rst: -------------------------------------------------------------------------------- 1 | ############ 2 | Introduction 3 | ############ 4 | 5 | **RISCV-Config** (RISCV Configuration Leagalizer) is a YAML based framework which can be used to validate the specifications of a RISC-V implementation against the RISC-V privileged and unprivileged ISA spec and generate standard specification yaml file. 6 | 7 | **Caution**: This is still a work in progress and non-backward compatible changes are expected to happen. 8 | 9 | For more information on the official RISC-V spec please visit: `RISC-V Specs <https://riscv.org/specifications/>`_ 10 | 11 | RISCV-Config [`Repository <https://github.com/riscv/riscv-config>`_] 12 | 13 | 14 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/revisions.rst: -------------------------------------------------------------------------------- 1 | .. raw:: latex 2 | 3 | \pagebreak 4 | 5 | .. _revisions: 6 | 7 | .. mdinclude:: ../../CHANGELOG.md 8 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/riscv_config-flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/vendor/riscv/riscv-config/docs/source/riscv_config-flow.png -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/docs/source/schema_custom.rst: -------------------------------------------------------------------------------- 1 | Any Custom CSR 2 | -------------- 3 | 4 | All custom CSRs follow the same schema as an architecture-defined CSR. 5 | 6 | uArch signals 7 | ------------- 8 | 9 | - **^uarch_ signal/group name** 10 | 11 | All signal or group names must contain the ``uarch_`` prefix. 12 | 13 | - **msb** 14 | 15 | An integer value indicating the msb position of the signal. 16 | 17 | - **lsb** 18 | 19 | An integer indicating the lsb position of the group. 20 | 21 | - **reset-val** 22 | 23 | An integer indicating the reset value of a signal/group. 24 | In case of a group, this value resides outside the subfields dict. 25 | 26 | - **legal** 27 | 28 | A list of legal values for this signal. 29 | 30 | - **subfields** 31 | 32 | An optional way to structure signals. A subfield would contain msb, lsb, legal fields. 33 | 34 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/examples/rv32i_platform.yaml: -------------------------------------------------------------------------------- 1 | nmi: 2 | label: nmi_vector 3 | reset: 4 | label: reset_vector 5 | mtime: 6 | implemented: True 7 | address: 0x20000 8 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/examples/rv32i_platform_checked.yaml: -------------------------------------------------------------------------------- 1 | nmi: 2 | label: nmi_vector 3 | reset: 4 | label: reset_vector 5 | mtime: 6 | implemented: false 7 | mtimecmp: 8 | implemented: false 9 | mcause_non_standard: 10 | implemented: true 11 | mtval_condition_writes: 12 | implemented: false 13 | scause_non_standard: 14 | implemented: false 15 | stval_condition_writes: 16 | implemented: false 17 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/examples/rv64i_platform.yaml: -------------------------------------------------------------------------------- 1 | nmi: 2 | label: nmi_vector 3 | address: 12288 4 | reset: 5 | label: reset_vector 6 | address: 16384 7 | mtime: 8 | implemented: false 9 | mtimecmp: 10 | implemented: false 11 | mcause_non_standard: 12 | implemented: true 13 | mtval_condition_writes: 14 | implemented: false 15 | scause_non_standard: 16 | implemented: false 17 | stval_condition_writes: 18 | implemented: false 19 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/examples/rv64i_platform_checked.yaml: -------------------------------------------------------------------------------- 1 | nmi: 2 | label: nmi_vector 3 | reset: 4 | label: reset_vector 5 | mtime: 6 | implemented: false 7 | mtimecmp: 8 | implemented: false 9 | mcause_non_standard: 10 | implemented: true 11 | mtval_condition_writes: 12 | implemented: false 13 | scause_non_standard: 14 | implemented: false 15 | stval_condition_writes: 16 | implemented: false 17 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/requirements.txt: -------------------------------------------------------------------------------- 1 | Cerberus>=1.3.1 2 | ruamel.yaml==0.17.16 3 | pyyaml==5.2 4 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/riscv_config/__init__.py: -------------------------------------------------------------------------------- 1 | from pkgutil import extend_path 2 | __path__ = extend_path(__path__, __name__) 3 | __version__ = '3.18.1' 4 | 5 | -------------------------------------------------------------------------------- /vendor/riscv/riscv-config/setup.cfg: -------------------------------------------------------------------------------- 1 | [bumpversion] 2 | current_version = 3.18.1 3 | commit = True 4 | tag = True 5 | 6 | [bumpversion:file:riscv_config/__init__.py] 7 | search = __version__ = '{current_version}' 8 | replace = __version__ = '{new_version}' 9 | 10 | [bdist_wheel] 11 | universal = 1 12 | 13 | [flake8] 14 | exclude = docs 15 | 16 | [aliases] 17 | -------------------------------------------------------------------------------- /vendor/riscv_riscv-config.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/riscv/riscv-config.git 12 | rev: 3416efeb219b0b743013266c0341697b3580b625 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/riscv_riscv-config.vendor.hjson: -------------------------------------------------------------------------------- 1 | // -*- coding: utf-8 -*- 2 | // Copyright (C) 2024 Thales DIS France SAS 3 | // SPDX-License-Identifier: Apache-2.0. 4 | // Original Author: Zbigniew Chamski (Thales) 5 | 6 | { 7 | // Name of the project 8 | name: "riscv-config", 9 | 10 | // Target directory: relative to the location of this script. 11 | target_dir: "riscv/riscv-config", 12 | 13 | // Upstream repository 14 | upstream: { 15 | // URL 16 | url: "https://github.com/riscv/riscv-config.git", 17 | // revision 18 | rev: "3.18.1", 19 | } 20 | 21 | // Patch dir for local changes 22 | patch_dir: "patches/riscv/riscv-config", 23 | 24 | // Exclusions from upstream content 25 | exclude_from_upstream: [ 26 | ".github", 27 | ] 28 | } 29 | -------------------------------------------------------------------------------- /verif/bsp/.gitignore: -------------------------------------------------------------------------------- 1 | libcv-verif.a 2 | -------------------------------------------------------------------------------- /verif/bsp/Makefile: -------------------------------------------------------------------------------- 1 | CV_SW_TOOLCHAIN ?= /opt/riscv 2 | RISCV ?= $(CV_SW_TOOLCHAIN) 3 | RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf- 4 | RISCV_GCC = $(RISCV_EXE_PREFIX)gcc 5 | RISCV_AR = $(RISCV_EXE_PREFIX)ar 6 | SRC = crt0.S handlers.S syscalls.c vectors.S 7 | OBJ = crt0.o handlers.o syscalls.o vectors.o 8 | LIBCV-VERIF = libcv-verif.a 9 | CFLAGS ?= -Os -g -static -mabi=ilp32 -march=rv32imc -Wall -pedantic 10 | 11 | all: $(LIBCV-VERIF) 12 | 13 | $(LIBCV-VERIF): $(OBJ) 14 | $(RISCV_AR) rcs $@ $(OBJ) 15 | 16 | %.o : %.c 17 | $(RISCV_GCC) $(CFLAGS) -c $< -o $@ 18 | 19 | %.o : %.S 20 | $(RISCV_GCC) $(CFLAGS) -c $< -o $@ 21 | 22 | clean: 23 | rm -f $(OBJ) $(LIBCV-VERIF) 24 | 25 | 26 | vars: 27 | @echo "make bsp variables:" 28 | @echo " CV_SW_TOOLCHAIN = $(CV_SW_TOOLCHAIN)" 29 | @echo " RISCV = $(RISCV)" 30 | @echo " RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)" 31 | @echo " RISCV_GCC = $(RISCV_GCC)" 32 | 33 | -------------------------------------------------------------------------------- /verif/bsp/useful_sites.txt: -------------------------------------------------------------------------------- 1 | Google "RISC-V startup code" 2 | https://twilco.github.io/riscv-from-scratch/2019/04/27/riscv-from-scratch-2.html 3 | -------------------------------------------------------------------------------- /verif/docs/Protocols/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright 2024 Thales DIS France SAS 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Zbigniew CHAMSKI - Thales 9 | 10 | FIGDIR=figures 11 | WAVEDIR=wavedrom 12 | 13 | # Names of figure files, without directory prefix nor .svg suffix 14 | FIGURES=interrupt-ack-uvm 15 | 16 | SVG_FILES=$(patsubst %,$(FIGDIR)/%.svg,$(FIGURES)) 17 | WAVE_FILES=$(patsubst %,$(WAVEDIR)/%.wave,$(FIGURES)) 18 | 19 | all: $(SVG_FILES) 20 | 21 | # wavedrom-cli requires a local installation and needs nodejs version >= 14. 22 | # See https://github.com/wavedrom/cli. 23 | $(FIGDIR)/%.svg: $(WAVEDIR)/%.wave 24 | wavedrom-cli -i $^ -s $@ 25 | 26 | clean: 27 | $(RM) $(SVG_FILES) 28 | 29 | -------------------------------------------------------------------------------- /verif/docs/VerifPlans/FRONTEND/VP_IP009.yml: -------------------------------------------------------------------------------- 1 | !Feature 2 | next_elt_id: 0 3 | name: Instr_scan 4 | id: 9 5 | display_order: 9 6 | subfeatures: !!omap [] 7 | vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' 8 | io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' 9 | config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' 10 | ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' 11 | -------------------------------------------------------------------------------- /verif/docs/VerifPlans/cvxif_VP.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/verif/docs/VerifPlans/cvxif_VP.xlsx -------------------------------------------------------------------------------- /verif/docs/VerifPlans/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | if "%1" == "" goto help 14 | 15 | %SPHINXBUILD% >NUL 2>NUL 16 | if errorlevel 9009 ( 17 | echo. 18 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 19 | echo.installed, then set the SPHINXBUILD environment variable to point 20 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 21 | echo.may add the Sphinx directory to PATH. 22 | echo. 23 | echo.If you don't have Sphinx installed, grab it from 24 | echo.http://sphinx-doc.org/ 25 | exit /b 1 26 | ) 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /verif/docs/VerifPlans/requirements.txt: -------------------------------------------------------------------------------- 1 | sphinx 2 | sphinx-rtd-theme 3 | recommonmark 4 | sphinxcontrib-svg2pdfconverter 5 | sphinx_github_changelog 6 | -------------------------------------------------------------------------------- /verif/docs/images/CVA6_env.drawio.drawio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cva6/5576a2267f1a53ccc4e753ae61e7092c37f77786/verif/docs/images/CVA6_env.drawio.drawio.png -------------------------------------------------------------------------------- /verif/env/corev-dv/custom/rv32zcmp_instr.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2023 Thales DIS 2 | // Copyright 2022 OpenHW Group 3 | // 4 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 7 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 8 | // 9 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 10 | // ------------------------------------------------------------------------------ // 11 | 12 | `DEFINE_ZCMP_INSTR(CM_PUSH, R_FORMAT, ARITHMETIC, RV32X) 13 | `DEFINE_ZCMP_INSTR(CM_POP, R_FORMAT, ARITHMETIC, RV32X) 14 | `DEFINE_ZCMP_INSTR(CM_POPRET, R_FORMAT, ARITHMETIC, RV32X) 15 | `DEFINE_ZCMP_INSTR(CM_POPRETZ, R_FORMAT, ARITHMETIC, RV32X) 16 | `DEFINE_ZCMP_INSTR(CM_MVA01S, R_FORMAT, LOGICAL, RV32X) 17 | `DEFINE_ZCMP_INSTR(CM_MVSA01, R_FORMAT, LOGICAL, RV32X) 18 | -------------------------------------------------------------------------------- /verif/env/corev-dv/custom/rv32zicond_instr.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2023 Thales 2 | // Copyright 2023 OpenHW Group 3 | // 4 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 7 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 8 | // 9 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 10 | // ------------------------------------------------------------------------------ // 11 | 12 | `DEFINE_ZICOND_INSTR(CZERO_EQZ, R_FORMAT, ARITHMETIC, RV32X) 13 | `DEFINE_ZICOND_INSTR(CZERO_NEZ, R_FORMAT, ARITHMETIC, RV32X) 14 | -------------------------------------------------------------------------------- /verif/env/corev-dv/custom/rv64zcb_instr.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2023 Thales DIS 2 | // Copyright 2022 OpenHW Group 3 | // 4 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 7 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 8 | // 9 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 10 | // ------------------------------------------------------------------------------ // 11 | 12 | `DEFINE_ZCB_INSTR(C_ZEXT_W, R_FORMAT, ARITHMETIC, RV64X) 13 | 14 | -------------------------------------------------------------------------------- /verif/env/corev-dv/user_extension/user_define.h: -------------------------------------------------------------------------------- 1 | # Copyright 2023 Thales DIS design services SAS 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # ------------------------------------------------------------------------------ # 9 | 10 | # Add user macros, routines in this file 11 | 12 | # Mappings of zicond extension mnemonics to .insn pseudo-op of GAS 13 | 14 | 15 | # CZERO_EQZ rd, rs1, rs2 -> .insn r 0x33, 0x5, 0x7, rd, rs1, rs2 16 | .macro czero_eqz rd, rs1, rs2 17 | .insn r 0x33, 0x5, 0x7, \rd, \rs1, \rs2 18 | .endm 19 | 20 | # CZERO_NEZ rd, rs1, rs2 -> .insn r 0x33, 0x7, 0x7, rd, rs1, rs2 21 | .macro czero_nez rd, rs1, rs2 22 | .insn r 0x33, 0x7, 0x7, \rd, \rs1, \rs2 23 | .endm 24 | -------------------------------------------------------------------------------- /verif/env/uvme/uvma_interrupt/README.md: -------------------------------------------------------------------------------- 1 | *Interrupt Agent documentation:* 2 | 3 | You can see the UVM interrupt agent documentation in : https://gitlab-tss.gemalto.com/riscv/ohg-pr/cva6/-/blob/master/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc 4 | -------------------------------------------------------------------------------- /verif/env/uvme/uvma_interrupt/uvma_interrupt_constants.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Thales DIS SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 9 | 10 | `ifndef __UVMA_INTERRUPT_CONSTANTS_SV__ 11 | `define __UVMA_INTERRUPT_CONSTANTS_SV__ 12 | 13 | 14 | `endif // __UVMA_INTERRUPT_CONSTANTS_SV__ 15 | -------------------------------------------------------------------------------- /verif/env/uvme/uvma_interrupt/uvma_interrupt_if.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Thales DIS SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 9 | 10 | 11 | `ifndef __UVMA_INTERRUPT_IF_SV__ 12 | `define __UVMA_INTERRUPT_IF_SV__ 13 | 14 | 15 | /** 16 | * Encapsulates all signals and clocking of Interrupt interface. Used by 17 | * monitor and driver. 18 | */ 19 | interface uvma_interrupt_if 20 | ( 21 | input clk, 22 | input reset_n 23 | ); 24 | 25 | logic [15:0] irq; 26 | 27 | endinterface : uvma_interrupt_if 28 | 29 | 30 | `endif // __UVMA_INTERRUPT_IF_SV__ 31 | -------------------------------------------------------------------------------- /verif/env/uvme/uvma_interrupt/uvma_interrupt_macros.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 OpenHW Group 2 | // Copyright 2020 Datum Technology Corporation 3 | // Copyright 2020 Silicon Labs, Inc. 4 | // 5 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | 17 | 18 | `ifndef __UVMA_INTERRUPT_MACROS_SV__ 19 | `define __UVMA_INTERRUPT_MACROS_SV__ 20 | 21 | 22 | 23 | 24 | 25 | `endif // __UVMA_INTERRUPT_MACROS_SV__ 26 | -------------------------------------------------------------------------------- /verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.flist: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Thales DIS SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 9 | 10 | 11 | // Directories 12 | +incdir+${DV_UVMA_INTERRUPT_PATH} 13 | +incdir+${DV_UVMA_INTERRUPT_PATH}/cov 14 | +incdir+${DV_UVMA_INTERRUPT_PATH}/seq 15 | 16 | // Files 17 | ${DV_UVMA_INTERRUPT_PATH}/uvma_interrupt_pkg.sv 18 | -------------------------------------------------------------------------------- /verif/env/uvme/uvma_interrupt/uvma_interrupt_tdefs.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2024 Thales DIS SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) 9 | 10 | `ifndef __UVMA_INTERRUPT_TDEFS_SV__ 11 | `define __UVMA_INTERRUPT_TDEFS_SV__ 12 | 13 | 14 | typedef enum { 15 | UVMA_INTERRUPT_RESET_STATE_PRE_RESET, 16 | UVMA_INTERRUPT_RESET_STATE_IN_RESET, 17 | UVMA_INTERRUPT_RESET_STATE_POST_RESET 18 | } uvma_interrupt_reset_state_enum; 19 | 20 | `endif // __UVMA_INTERRUPT_TDEFS_SV__ 21 | -------------------------------------------------------------------------------- /verif/env/uvme/uvme_cva6_core_cntrl_if.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * Quasi-static core control signals. 3 | */ 4 | interface uvme_cva6_core_cntrl_if 5 | import uvm_pkg::*; 6 | import uvme_cva6_pkg::*; 7 | (); 8 | 9 | logic clk; 10 | 11 | logic [XLEN-1:0] boot_addr; 12 | 13 | endinterface : uvme_cva6_core_cntrl_if 14 | -------------------------------------------------------------------------------- /verif/regress/verilator-v5.patch: -------------------------------------------------------------------------------- 1 | diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS 2 | index 215fb6bd8..829752e6b 100644 3 | --- a/docs/CONTRIBUTORS 4 | +++ b/docs/CONTRIBUTORS 5 | @@ -154,5 +154,6 @@ Yuri Victorovich 6 | Yutetsu TAKATSUKASA 7 | Yu-Sheng Lin 8 | Yves Mathieu 9 | +Zbigniew Chamski 10 | Zhanglei Wang 11 | Zixi Li 12 | diff --git a/include/verilated_types.h b/include/verilated_types.h 13 | index cb7265e32..f1d482d8e 100644 14 | --- a/include/verilated_types.h 15 | +++ b/include/verilated_types.h 16 | @@ -1012,8 +1012,8 @@ struct VlUnpacked final { 17 | 18 | // METHODS 19 | // Raw access 20 | - WData* data() { return &m_storage[0]; } 21 | - const WData* data() const { return &m_storage[0]; } 22 | + WData* data() { return (WData*)&m_storage[0]; } 23 | + const WData* data() const { return (const WData*)&m_storage[0]; } 24 | 25 | T_Value& operator[](size_t index) { return m_storage[index]; } 26 | const T_Value& operator[](size_t index) const { return m_storage[index]; } 27 | -------------------------------------------------------------------------------- /verif/sim/cov-exclude-mod.lst: -------------------------------------------------------------------------------- 1 | // Copyright 2021 Thales DIS design services SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) 9 | 10 | 11 | -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.instr_tracer_i 12 | -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.tracer_if 13 | -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.genblk6.i_cva6_rvfi_combi 14 | -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.i_cva6_rvfi_probes 15 | -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.i_frontend.i_instr_queue.i_unread_* 16 | -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.gen_cache_hpd.i_cache_subsystem 17 | -------------------------------------------------------------------------------- /verif/sim/init_run_uvm_fsdb.do: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales DIS France 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 3 | # Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.com) 4 | 5 | fsdbDumpvars 0 "uvmt_cva6_tb" +all +trace_process 6 | run 7 | 8 | -------------------------------------------------------------------------------- /verif/sim/init_run_uvm_vpd.do: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales DIS France 2 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 3 | # Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.com) 4 | 5 | dump -file "novas.vpd" -type VPD 6 | dump -add "uvmt_cva6_tb" -depth 0 7 | run 8 | 9 | -------------------------------------------------------------------------------- /verif/sim/init_uvm.do: -------------------------------------------------------------------------------- 1 | fsdbDumpvars 0 "uvmt_cva6_tb" +all +trace_process 2 | -------------------------------------------------------------------------------- /verif/tb/core/README.md: -------------------------------------------------------------------------------- 1 | ## Experimental Stand-alone testbench for the CVA6 2 | This do-nothing TB supports experiments with the CVA6 to develop a standalone testbenech for the CVA6. 3 | It uses a "core-only" manifest file `Flist.cva6`. 4 | 5 | ### Current status: 6 | Compiles and runs without errors for a few thousand clock cycles under either Verilator, Metrics DSIM or Cadence Xcelium (xrun). 7 | 8 | ### Give it a try: 9 | ``` 10 | $ make help 11 | ``` 12 | -------------------------------------------------------------------------------- /verif/tb/core/bootrom/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.img 3 | *.dtb 4 | -------------------------------------------------------------------------------- /verif/tb/core/bootrom/bootrom.S: -------------------------------------------------------------------------------- 1 | .section .text.start, "ax", @progbits 2 | .globl _start 3 | _start: 4 | # bootrom.sv need to be functional in 64 and 32 bits, 5 | # li s0, DRAM_BASE creates instructions not compatible with both 6 | # versions. That's why we have replaced it by li and slli instructions 7 | # to generates code compatible with both versions. 8 | li s0, 1 9 | slli s0, s0, 31 10 | csrr a0, mhartid 11 | la a1, _dtb 12 | jr s0 13 | 14 | .section .text.hang, "ax", @progbits 15 | .globl _hang 16 | _hang: 17 | csrr a0, mhartid 18 | la a1, _dtb 19 | 1: 20 | wfi 21 | j 1b 22 | 23 | .section .rodata.dtb, "a", @progbits 24 | .globl _dtb 25 | .align 5, 0 26 | _dtb: 27 | .incbin "cva6.dtb" 28 | -------------------------------------------------------------------------------- /verif/tb/core/bootrom/linker.ld: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | ROM_BASE = 0x10000; /* ... but actually position independent */ 4 | 5 | . = ROM_BASE; 6 | .text.start : { *(.text.start) } 7 | . = ROM_BASE + 0x40; 8 | .text.hang : { *(.text.hang) } 9 | . = ROM_BASE + 0x80; 10 | .rodata.dtb : { *(.rodata.dtb) } 11 | } 12 | -------------------------------------------------------------------------------- /verif/tb/core/uvma_core_cntrl_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef __UVMA_CORE_CNTRL_PKG_SV__ 2 | `define __UVMA_CORE_CNTRL_PKG_SV__ 3 | 4 | package uvma_core_cntrl_pkg; 5 | 6 | // Constants / Structs / Enums 7 | `include "uvma_core_cntrl_constants.sv" 8 | `include "uvma_core_cntrl_tdefs.sv" 9 | `include "uvma_core_cntrl_utils.sv" 10 | 11 | endpackage : uvma_core_cntrl_pkg 12 | 13 | `endif 14 | -------------------------------------------------------------------------------- /verif/tb/core/uvma_cva6pkg_utils_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef __UVMA_CVA6PKG_UTILS_PKG_SV__ 2 | `define __UVMA_CVA6PKG_UTILS_PKG_SV__ 3 | 4 | package uvma_cva6pkg_utils_pkg; 5 | 6 | import ariane_pkg::*; 7 | import cva6_config_pkg::*; 8 | import uvma_core_cntrl_pkg::*; 9 | `include "uvma_cva6pkg_utils.sv" 10 | 11 | endpackage : uvma_cva6pkg_utils_pkg 12 | 13 | `endif 14 | -------------------------------------------------------------------------------- /verif/tb/core/uvma_rvfi_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef __UVMA_RVFI_PKG_SV__ 2 | `define __UVMA_RVFI_PKG_SV__ 3 | 4 | // Pre-processor macros 5 | `ifdef VERILATOR 6 | `include "custom_uvm_macros.svh" 7 | `else 8 | `include "uvm_macros.svh" 9 | `endif 10 | 11 | package uvma_rvfi_pkg; 12 | 13 | `ifndef VERILATOR 14 | import uvm_pkg ::*; 15 | `endif 16 | import uvma_core_cntrl_pkg::*; 17 | 18 | `include "uvma_rvfi_constants.sv" 19 | `include "uvma_rvfi_tdefs.sv" 20 | 21 | endpackage : uvma_rvfi_pkg 22 | 23 | `endif 24 | -------------------------------------------------------------------------------- /verif/tb/core/uvmc_rvfi_reference_model_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef __UVMC_RVFI_REFERENCE_MODEL_PKG_SV__ 2 | `define __UVMC_RVFI_REFERENCE_MODEL_PKG_SV__ 3 | 4 | // Pre-processor macros 5 | `ifdef VERILATOR 6 | `include "custom_uvm_macros.svh" 7 | `else 8 | `include "uvm_macros.svh" 9 | `endif 10 | 11 | package uvmc_rvfi_reference_model_pkg; 12 | 13 | `ifndef VERILATOR 14 | import uvm_pkg ::*; 15 | `endif 16 | import uvma_core_cntrl_pkg::*; 17 | import uvma_rvfi_pkg::*; 18 | 19 | `include "uvmc_rvfi_reference_model_utils.sv" 20 | `include "rvfi_spike.sv" 21 | 22 | endpackage : uvmc_rvfi_reference_model_pkg 23 | 24 | `endif 25 | -------------------------------------------------------------------------------- /verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv: -------------------------------------------------------------------------------- 1 | `ifndef __UVMC_RVFI_SCOREBOARD_PKG_SV__ 2 | `define __UVMC_RVFI_SCOREBOARD_PKG_SV__ 3 | 4 | // Pre-processor macros 5 | `ifdef VERILATOR 6 | `include "custom_uvm_macros.svh" 7 | `else 8 | `include "uvm_macros.svh" 9 | `endif 10 | 11 | package uvmc_rvfi_scoreboard_pkg; 12 | 13 | `ifndef VERILATOR 14 | import uvm_pkg ::*; 15 | `endif 16 | import uvma_core_cntrl_pkg::*; 17 | import uvmc_rvfi_reference_model_pkg::*; 18 | import uvma_rvfi_pkg::*; 19 | 20 | // DPI imports 21 | `include "dpi_dasm_imports.svh" 22 | 23 | `include "uvma_rvfi_constants.sv" 24 | `include "uvmc_rvfi_scoreboard_utils.sv" 25 | 26 | endpackage : uvmc_rvfi_scoreboard_pkg 27 | 28 | `endif 29 | -------------------------------------------------------------------------------- /verif/tb/uvmt/uvmt_axi_switch_intf.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2022 Thales DIS SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) 9 | 10 | /**** AXI interface to indicate the state of the agent ****/ 11 | 12 | 13 | interface uvmt_axi_switch_intf; 14 | 15 | logic active; 16 | 17 | 18 | endinterface : uvmt_axi_switch_intf 19 | -------------------------------------------------------------------------------- /verif/tb/uvmt/uvmt_cva6_constants.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2020 OpenHW Group 2 | // Copyright 2020 Datum Technologies 3 | // Copyright 2021 Thales DIS Design Services SAS 4 | // 5 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // https://solderpad.org/licenses/ 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | // 17 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 18 | 19 | `ifndef __UVMT_CVA6_CONSTANTS_SV__ 20 | `define __UVMT_CVA6_CONSTANTS_SV__ 21 | 22 | parameter XLEN = 32; 23 | 24 | `endif // __UVMT_CVA6_CONSTANTS_SV__ 25 | -------------------------------------------------------------------------------- /verif/tb/uvmt/uvmt_default_inputs_intf.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2023 Thales DIS SAS 2 | // 3 | // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | // You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | // 8 | // Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) – sub-contractor MU-Electronics for Thales group 9 | 10 | /**** AXI interface to indicate the state of the agent ****/ 11 | 12 | 13 | interface uvmt_default_inputs_intf; 14 | 15 | logic [63:0] hart_id; 16 | logic [1:0] irq; 17 | logic ipi; 18 | logic time_irq; 19 | logic debug_req; 20 | 21 | endinterface : uvmt_default_inputs_intf 22 | -------------------------------------------------------------------------------- /verif/tests/custom/CSR/csr_access_failing_tests/README.md: -------------------------------------------------------------------------------- 1 | This directory contain RISCV CVA6 CSR access mode failing tests. 2 | 3 | -------------------------------------------------------------------------------- /verif/tests/custom/CSR/csr_access_tests/readme.md: -------------------------------------------------------------------------------- 1 | Highlights: 2 | 3 | This directory includes test programs for the RISCV CVA6 CSR Access, which are divided into Machine read-write, Machine read-only, Supervisor read-write, and Machine Mode counter CSR tests. 4 | 5 | 1.Each CSR access has been verified in all priviliged modes(M,S and U). 6 | 7 | 2.The behavior of counter CSRs has been verified in all priviliged modes (M,S and U). 8 | 9 | 3.Checked the behavior of the RISC-V Machine mode counter CSRs when it reaches to maximum value. 10 | -------------------------------------------------------------------------------- /verif/tests/custom/CSR/csr_access_yaml/README.md: -------------------------------------------------------------------------------- 1 | This directory contains yaml files for RISCV CVA6 32-bit CSRs, which are divided into three categories: Supervisor mode read-write CSRs, Machine mode read-write CSRs, and read-only CSRs. 2 | -------------------------------------------------------------------------------- /verif/tests/custom/CSR/csr_access_yaml/cva6_mscratch_csr_access.yaml: -------------------------------------------------------------------------------- 1 | - csr: CSR_MSCRATCH 2 | description: > 3 | Scratch register for machine trap handlers 4 | address: 0x340 5 | privilege_mode: M 6 | rv32: 7 | - field_name: mscratch 8 | description: > 9 | hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler 10 | type: RW 11 | reset_val: 0 12 | msb: 31 13 | lsb: 0 14 | 15 | -------------------------------------------------------------------------------- /verif/tests/custom/Zcmp/cm_mva01s_test.S: -------------------------------------------------------------------------------- 1 | #include "riscv_test.h" 2 | 3 | RVTEST_RV32U 4 | RVTEST_CODE_BEGIN 5 | 6 | li s1, 5 7 | li s2, 7 8 | cm.mva01s s1, s2 9 | 10 | bne a0, s1, failure 11 | beq a1, s2, success 12 | failure: 13 | li x1, 1 14 | slli x1, x1, 1 15 | addi x1, x1, 1 16 | sw x1, tohost, t5 17 | self_loop_2: j self_loop_2 18 | 19 | success: 20 | li x1, 0 21 | slli x1, x1, 1 22 | addi x1, x1, 1 23 | sw x1, tohost, t5 24 | self_loop: j self_loop 25 | 26 | RVTEST_CODE_END 27 | 28 | .data 29 | 30 | RVTEST_DATA_BEGIN 31 | 32 | RVTEST_DATA_END 33 | -------------------------------------------------------------------------------- /verif/tests/custom/Zcmp/cm_mvsa01_test.S: -------------------------------------------------------------------------------- 1 | #include "riscv_test.h" 2 | 3 | RVTEST_RV32U 4 | RVTEST_CODE_BEGIN 5 | 6 | li a0, 5 7 | li a1, 7 8 | cm.mvsa01 s1, s2 9 | 10 | bne a0, s1, failure 11 | beq a1, s2, success 12 | failure: 13 | li x1, 1 14 | slli x1, x1, 1 15 | addi x1, x1, 1 16 | sw x1, tohost, t5 17 | self_loop_2: j self_loop_2 18 | 19 | success: 20 | li x1, 0 21 | slli x1, x1, 1 22 | addi x1, x1, 1 23 | sw x1, tohost, t5 24 | self_loop: j self_loop 25 | 26 | RVTEST_CODE_END 27 | 28 | .data 29 | 30 | RVTEST_DATA_BEGIN 31 | 32 | RVTEST_DATA_END 33 | -------------------------------------------------------------------------------- /verif/tests/custom/Zcmp/readme.txt: -------------------------------------------------------------------------------- 1 | Use the following command to build the test binaries (example for cm_push_pop_test.S): 2 | riscv32-corev-elf-gcc -static -mcmodel=medany -fvisibility=hidden -nostdlib -g syscalls.c -lgcc -Tlink.ld -march=rv32gc_zcmp -o cm_push_pop_test.elf cm_push_pop_test.S 3 | -------------------------------------------------------------------------------- /verif/tests/custom/coremark/uart.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include <stdint.h> 4 | 5 | #define UART_BASE 0x10000000 6 | 7 | #define UART_RBR UART_BASE + 0 8 | #define UART_THR UART_BASE + 0 9 | #define UART_INTERRUPT_ENABLE UART_BASE + 4 10 | #define UART_INTERRUPT_IDENT UART_BASE + 8 11 | #define UART_FIFO_CONTROL UART_BASE + 8 12 | #define UART_LINE_CONTROL UART_BASE + 12 13 | #define UART_MODEM_CONTROL UART_BASE + 16 14 | #define UART_LINE_STATUS UART_BASE + 20 15 | #define UART_MODEM_STATUS UART_BASE + 24 16 | #define UART_DLAB_LSB UART_BASE + 0 17 | #define UART_DLAB_MSB UART_BASE + 4 18 | 19 | void init_uart(); 20 | 21 | void print_uart(const char* str); 22 | 23 | void print_uart_int(uint32_t addr); 24 | 25 | void print_uart_addr(uint64_t addr); 26 | 27 | void print_uart_byte(uint8_t byte); -------------------------------------------------------------------------------- /verif/tests/custom/debug_test/bsp/.gitignore: -------------------------------------------------------------------------------- 1 | libcv-verif.a 2 | -------------------------------------------------------------------------------- /verif/tests/custom/debug_test/test.yaml: -------------------------------------------------------------------------------- 1 | # Test definition YAML for test 2 | 3 | # Debug directed test 4 | name: debug_test 5 | uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c 6 | program: debug_test 7 | description: > 8 | Debug directed test 9 | # FIXME:The minstret compare issues with this test should be filed as bug and fixed 10 | disable_csr_check: 11 | - minstret 12 | -------------------------------------------------------------------------------- /verif/tests/custom/hello_world/hello_world.c: -------------------------------------------------------------------------------- 1 | /* 2 | ** 3 | ** Copyright 2020 OpenHW Group 4 | ** 5 | ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 6 | ** you may not use this file except in compliance with the License. 7 | ** You may obtain a copy of the License at 8 | ** 9 | ** https://solderpad.org/licenses/ 10 | ** 11 | ** Unless required by applicable law or agreed to in writing, software 12 | ** distributed under the License is distributed on an "AS IS" BASIS, 13 | ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | ** See the License for the specific language governing permissions and 15 | ** limitations under the License. 16 | ** 17 | */ 18 | 19 | #include <stdint.h> 20 | #include <stdio.h> 21 | 22 | int main(int argc, char* arg[]) { 23 | 24 | printf("%d: Hello World !", 0); 25 | 26 | int a = 0; 27 | for (int i = 0; i < 5; i++) 28 | { 29 | a += i; 30 | } 31 | return 0; 32 | } 33 | -------------------------------------------------------------------------------- /verif/tests/custom/issues/compressed-fpreg-commits-rv64.S: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Thales DIS France 2 | # 3 | # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 6 | # You may obtain a copy of the License at https://solderpad.org/licenses/ 7 | # 8 | # Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr) 9 | 10 | #***************************************************************************** 11 | # compressed-fpreg-commits.S 12 | #----------------------------------------------------------------------------- 13 | # 14 | 15 | .globl main 16 | main: 17 | la s1, tohost; 18 | c.fld fs0, 0(s1); 19 | c.fldsp fs1, 0(sp); 20 | xor a2, a0, a0; # trivial PASS... 21 | beqz a2, pass; 22 | 23 | fail: 24 | # Failure post-processing; set retcode to 1. 25 | li a0, 0x1; 26 | jal exit; 27 | 28 | pass: 29 | # Success post-processing: set retcode to 0. 30 | li a0, 0x0; 31 | jal exit; 32 | 33 | -------------------------------------------------------------------------------- /verif/tests/custom/return0/return0.c: -------------------------------------------------------------------------------- 1 | /* 2 | ** 3 | ** Copyright 2020 OpenHW Group 4 | ** 5 | ** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); 6 | ** you may not use this file except in compliance with the License. 7 | ** You may obtain a copy of the License at 8 | ** 9 | ** https://solderpad.org/licenses/ 10 | ** 11 | ** Unless required by applicable law or agreed to in writing, software 12 | ** distributed under the License is distributed on an "AS IS" BASIS, 13 | ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | ** See the License for the specific language governing permissions and 15 | ** limitations under the License. 16 | ** 17 | */ 18 | 19 | int main() { 20 | 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /verif/tests/custom/spike_params/misa_csr_we.S: -------------------------------------------------------------------------------- 1 | .globl main 2 | main: 3 | # Disable extension C in MISA Extensions field 4 | li x1, 0x00141100 5 | csrw 0x301, x1 6 | # If misa_we=true, following code should provoke illegal instruction exceptions 7 | # And test should timeout 8 | c.li x2, 0 9 | c.addi x2, 2 10 | c.addi x2, -2 11 | li x1, 0 12 | slli x1, x1, 1 13 | addi x1, x1, 1 14 | sw x1, tohost, t5 15 | -------------------------------------------------------------------------------- /verilator_config.vlt: -------------------------------------------------------------------------------- 1 | // Copyright OpenHW contributors 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | // 5 | // common waiver rules for verilator 6 | 7 | `verilator_config 8 | 9 | // waving these warnings since they are in vendor or core_apu 10 | lint_off -rule STMTDLY -file "*/corev_apu/*" 11 | lint_off -rule WIDTHEXPAND -file "*/common/local/util/sram.sv" 12 | lint_off -rule WIDTHTRUNC -file "*/core/include/std_cache_pkg.sv" 13 | lint_off -file "*/corev_apu/*" 14 | lint_off -file "*/vendor/*" 15 | 16 | lint_off -rule WIDTHEXPAND -file "*/core/cache_subsystem/axi_adapter.sv" 17 | lint_off -rule WIDTHEXPAND -file "*/core/axi_shim.sv" 18 | 19 | // P2 20 | lint_off -rule WIDTHEXPAND -file "*/core/issue_read_operands.sv" 21 | lint_off -rule WIDTHEXPAND -file "*/core/ariane_regfile_ff.sv" 22 | lint_off -rule SELRANGE -file "*/core/commit_stage.sv" --------------------------------------------------------------------------------