├── .gitignore ├── .gitmodules ├── Bender.yml ├── CITATION.cff ├── LICENSE.apache ├── LICENSE.solderpad ├── README.license.md ├── README.md ├── docs ├── CHANGELOG-PULP.md ├── CHANGELOG.md ├── CODEOWNERS ├── CONTRIBUTING.md ├── README.md └── fig │ ├── multislice_block.png │ ├── opgrp_block.png │ ├── oprecomp_logo_inline1.png │ ├── slice_block.png │ └── top_block.png ├── ips_list.yml ├── src ├── fpnew_cast_multi.sv ├── fpnew_classifier.sv ├── fpnew_divsqrt_multi.sv ├── fpnew_divsqrt_th_32.sv ├── fpnew_divsqrt_th_64_multi.sv ├── fpnew_fma.sv ├── fpnew_fma_multi.sv ├── fpnew_noncomp.sv ├── fpnew_opgroup_block.sv ├── fpnew_opgroup_fmt_slice.sv ├── fpnew_opgroup_multifmt_slice.sv ├── fpnew_pkg.sv ├── fpnew_rounding.sv ├── fpnew_sdotp_multi.sv ├── fpnew_sdotp_multi_wrapper.sv ├── fpnew_top.sv └── lfsr_sr.sv ├── src_files.yml ├── util ├── README.md └── vendor.py └── vendor ├── openc910.lock.hjson ├── openc910.vendor.hjson ├── openc910 ├── C910_RTL_FACTORY │ └── gen_rtl │ │ ├── clk │ │ └── rtl │ │ │ └── gated_clk_cell.v │ │ └── vfdsu │ │ └── rtl │ │ ├── ct_vfdsu_ctrl.v │ │ ├── ct_vfdsu_double.v │ │ ├── ct_vfdsu_ff1.v │ │ ├── ct_vfdsu_pack.v │ │ ├── ct_vfdsu_prepare.v │ │ ├── ct_vfdsu_round.v │ │ ├── ct_vfdsu_scalar_dp.v │ │ ├── ct_vfdsu_srt.v │ │ ├── ct_vfdsu_srt_radix16_bound_table.v │ │ ├── ct_vfdsu_srt_radix16_with_sqrt.v │ │ └── ct_vfdsu_top.v ├── LICENSE └── README.md ├── opene906.lock.hjson ├── opene906.vendor.hjson ├── opene906 ├── E906_RTL_FACTORY │ └── gen_rtl │ │ ├── clk │ │ └── rtl │ │ │ └── gated_clk_cell.v │ │ ├── fdsu │ │ └── rtl │ │ │ ├── pa_fdsu_ctrl.v │ │ │ ├── pa_fdsu_ff1.v │ │ │ ├── pa_fdsu_pack_single.v │ │ │ ├── pa_fdsu_prepare.v │ │ │ ├── pa_fdsu_round_single.v │ │ │ ├── pa_fdsu_special.v │ │ │ ├── pa_fdsu_srt_single.v │ │ │ └── pa_fdsu_top.v │ │ └── fpu │ │ └── rtl │ │ ├── pa_fpu_dp.v │ │ ├── pa_fpu_frbus.v │ │ └── pa_fpu_src_type.v ├── LICENSE └── README.md └── patches ├── openc910 └── 0001-Add-FP16ALT-support-to-THMULTI-DivSqrt-unit.patch └── opene906 ├── 0001-Patch-pa_fdsu_prepare.patch ├── 0001-Patch-pa_fpu_fp.patch └── 0001-Patch-pa_fpu_frbus.patch /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | html 3 | Bender.lock 4 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "src-sv/common_cells"] 2 | path = src/common_cells 3 | url = https://github.com/pulp-platform/common_cells.git 4 | [submodule "src-sv/fpu_div_sqrt_mvp"] 5 | path = src/fpu_div_sqrt_mvp 6 | url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git 7 | [submodule "tb/flexfloat"] 8 | path = tb/flexfloat 9 | url = https://github.com/oprecomp/flexfloat.git 10 | -------------------------------------------------------------------------------- /Bender.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2019 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | package: 5 | name: FPnew 6 | authors: ["Stefan Mach "] 7 | 8 | dependencies: 9 | common_cells: {git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0} 10 | fpu_div_sqrt_mvp: {git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git", version: 1.0.4} 11 | 12 | sources: 13 | - src/fpnew_pkg.sv 14 | - src/fpnew_cast_multi.sv 15 | - src/fpnew_classifier.sv 16 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v 17 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v 18 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v 19 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v 20 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v 21 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v 22 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v 23 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v 24 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v 25 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v 26 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v 27 | - vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v 28 | # - vendor/openc910/C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v # same as the one from E906 29 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v 30 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v 31 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v 32 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_pack.v 33 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v 34 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_round.v 35 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v 36 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v 37 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_with_sqrt.v 38 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v 39 | - vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v 40 | - src/fpnew_divsqrt_th_32.sv 41 | - src/fpnew_divsqrt_th_64_multi.sv 42 | - src/fpnew_divsqrt_multi.sv 43 | - src/fpnew_fma.sv 44 | - src/fpnew_fma_multi.sv 45 | - src/fpnew_sdotp_multi.sv 46 | - src/fpnew_sdotp_multi_wrapper.sv 47 | - src/fpnew_noncomp.sv 48 | - src/fpnew_opgroup_block.sv 49 | - src/fpnew_opgroup_fmt_slice.sv 50 | - src/fpnew_opgroup_multifmt_slice.sv 51 | - src/fpnew_rounding.sv 52 | - src/lfsr_sr.sv 53 | - src/fpnew_top.sv 54 | -------------------------------------------------------------------------------- /CITATION.cff: -------------------------------------------------------------------------------- 1 | cff-version: 1.2.0 2 | message: "If you use FPnew, please cite it as below." 3 | authors: 4 | - family-names: "Mach" 5 | given-names: "Stefan" 6 | orcid: "https://orcid.org/0000-0002-3476-8857" 7 | title: "FPnew: - New Floating-Point Unit with Transprecision Capabilities" 8 | version: 0.6.6 9 | url: "https://github.com/pulp-platform/fpnew" 10 | preferred-citation: 11 | type: article 12 | authors: 13 | - family-names: "Mach" 14 | given-names: "Stefan" 15 | orcid: "https://orcid.org/0000-0002-3476-8857" 16 | - family-names: "Schuiki" 17 | given-names: "Fabian" 18 | orcid: "https://orcid.org/0000-0002-9923-5031" 19 | - family-names: "Zaruba" 20 | given-names: "Florian" 21 | orcid: "https://orcid.org/0000-0002-8194-6521" 22 | - family-names: "Benini" 23 | given-names: "Luca" 24 | orcid: "https://orcid.org/0000-0001-8068-3806" 25 | doi: "10.1109/TVLSI.2020.3044752" 26 | journal: "IEEE Transactions on Very Large Scale Integration (VLSI) Systems" 27 | month: 12 28 | start: 774 29 | end: 787 30 | title: "FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing" 31 | issue: 4 32 | volume: 29 33 | year: 2020 34 | -------------------------------------------------------------------------------- /LICENSE.apache: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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While redistributing the Work or 167 | Derivative Works thereof, You may choose to offer, and charge a fee for, 168 | acceptance of support, warranty, indemnity, or other liability obligations 169 | and/or rights consistent with this License. However, in accepting such 170 | obligations, You may act only on Your own behalf and on Your sole 171 | responsibility, not on behalf of any other Contributor, and only if You agree 172 | to indemnify, defend, and hold each Contributor harmless for any liability 173 | incurred by, or claims asserted against, such Contributor by reason of your 174 | accepting any such warranty or additional liability. 175 | 176 | END OF TERMS AND CONDITIONS -------------------------------------------------------------------------------- /README.license.md: -------------------------------------------------------------------------------- 1 | # Licensing 2 | 3 | FPnew is released under the *SolderPad Hardware License*, which is a permissive license based on Apache 2.0. Please refer to the [SolderPad license file](LICENSE.solderpad) for further information. 4 | 5 | The T-Head E906 and C910 DivSqrt units, integrated into FPnew in [`vendor/opene906`](vendor/opene906) and [`vendor/openc910`](vendor/openc910), are reseased under the *Apache License, Version 2.0*. Please refer to the [Apache 2.0 license file](LICENSE.apache) for further information. 6 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPnew - New Floating-Point Unit with Transprecision Capabilities 2 | 3 | Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats, written in SystemVerilog. 4 | 5 | Maintainer: Luca Bertaccini
6 | Principal Author: Stefan Mach 7 | 8 | ## Features 9 | 10 | The FPU is a parametric design that allows generating FP hardware units for various use cases. 11 | Even though mainly designed for use in RISC-V processors, the FPU or its sub-blocks can easily be utilized in other environments. 12 | Our design aims to be compliant with IEEE 754-2008 and provides the following features: 13 | 14 | ### Formats 15 | Any IEEE 754-2008 style binary floating-point format can be supported, including single-, double-, quad- and half-precision (`binary32`, `binary64`, `binary128`, `binary16`). 16 | Formats can be defined with arbitrary number of exponent and mantissa bits through parameters and are always symmetrically biased. 17 | Multiple FP formats can be supported concurrently, and the number of formats supported is not limited. 18 | 19 | Multiple integer formats with arbitrary number of bits (as source or destionation of conversions) can also be defined. 20 | 21 | ### Operations 22 | - Addition/Subtraction 23 | - Multiplication 24 | - Fused multiply-add in four flavours (`fmadd`, `fmsub`, `fnmadd`, `fnmsub`) 25 | - Division1,2 26 | - Square root1,2 27 | - Minimum/Maximum3 28 | - Comparisons 29 | - Sign-Injections (`copy`, `abs`, `negate`, `copySign` etc.) 30 | - Conversions among all supported FP formats 31 | - Conversions between FP formats and integers (signed & unsigned) and vice versa 32 | - Classification 33 | 34 | Multi-format FMA operations (i.e. multiplication in one format, accumulation in another) are optionally supported. 35 | 36 | Optionally, *packed-SIMD* versions of all the above operations can be generated for formats narrower than the FPU datapath width. 37 | E.g.: Support for double-precision (64bit) operations and two simultaneous single-precision (32bit) operations. 38 | 39 | It is also possible to generate only a subset of operations if e.g. divisions are not needed. 40 | 41 | 1Some compliance issues with IEEE 754-2008 are currently known to exist for the PULP DivSqrt unit (Rounding mismatches have been reported in GitHub issues. This can lead to results being off by 1ulp, and the inexact flag not being properly raised in these cases as well)
42 | 2Two DivSqrt units are supported: the multi-format PULP DivSqrt unit and a 32-bit unit integrated from the T-Head OpenE906. The `PulpDivsqrt` parameter can be set to 1 or 0 to select the former or the latter unit, respectively.
43 | 3Implementing IEEE 754-201x `minimumNumber` and `maximumNumber`, respectively 44 | 45 | ### Rounding modes 46 | All IEEE 754-2008 rounding modes are supported, namely 47 | - `roundTiesToEven` 48 | - `roundTiesToAway` 49 | - `roundTowardPositive` 50 | - `roundTowardNegative` 51 | - `roundTowardZero` 52 | 53 | ### Status Flags 54 | All IEEE 754-2008 status flags are supported, namely 55 | - Invalid operation (`NV`) 56 | - Division by zero (`DZ`) 57 | - Overflow (`OF`) 58 | - Underflow (`UF`) 59 | - Inexact (`NX`) 60 | 61 | ## Getting Started 62 | 63 | ### Dependencies 64 | 65 | FPnew currently depends on the following: 66 | - `lzc` and `rr_arb_tree` from the `common_cells` repository (https://github.com/pulp-platform/common_cells.git) 67 | - optional: Divider and square-root unit from the `fpu-div-sqrt-mvp` repository (https://github.com/pulp-platform/fpu_div_sqrt_mvp.git) 68 | 69 | These two repositories are included in the source code directory as git submodules, use 70 | ```bash 71 | git submodule update --init --recursive 72 | ``` 73 | if you want to load these dependencies there. 74 | 75 | Consider using [Bender](https://github.com/fabianschuiki/bender.git) for managing dependencies in your projects. FPnew comes with Bender support! 76 | 77 | ### Usage 78 | 79 | The top-level module of the FPU is called `fpnew_top` and can be directly instantiated in your design. 80 | Make sure you compile the package `fpnew_pkg` ahead of any files making references to types, parameters or functions defined there. 81 | 82 | It is discouraged to `import` all of `fpnew_pkg` into your source files. Instead, explicitly scope references into the package like so: `fpnew_pkg::foo`. 83 | 84 | #### Example Instantiation 85 | 86 | ```SystemVerilog 87 | // FPU instance 88 | fpnew_top #( 89 | .Features ( fpnew_pkg::RV64D ), 90 | .Implementation ( fpnew_pkg::DEFAULT_NOREGS ), 91 | .TagType ( logic ) 92 | ) i_fpnew_top ( 93 | .clk_i, 94 | .rst_ni, 95 | .operands_i, 96 | .rnd_mode_i, 97 | .op_i, 98 | .op_mod_i, 99 | .src_fmt_i, 100 | .dst_fmt_i, 101 | .int_fmt_i, 102 | .vectorial_op_i, 103 | .simd_mask_i, 104 | .tag_i, 105 | .in_valid_i, 106 | .in_ready_o, 107 | .flush_i, 108 | .result_o, 109 | .status_o, 110 | .tag_o, 111 | .out_valid_o, 112 | .out_ready_i, 113 | .busy_o 114 | ); 115 | ``` 116 | 117 | ### Documentation 118 | 119 | More in-depth documentation on the FPnew configuration, interfaces and architecture is provided in [`docs/README.md`](docs/README.md). 120 | 121 | ### Issues and Contributing 122 | 123 | In case you find any issues with FPnew that have not been reported yet, don't hesitate to open a new [issue](https://github.com/pulp-platform/fpnew/issues) here on Github. 124 | Please, don't use the issue tracker for support questions. 125 | Instead, consider contacting the maintainers or consulting the [PULP forums](https://pulp-platform.org/community/index.php). 126 | 127 | In case you would like to contribute to the project, please refer to the contributing guidelines in [`docs/CONTRIBUTING.md`](docs/CONTRIBUTING.md) before opening a pull request. 128 | 129 | 130 | ### Repository Structure 131 | 132 | HDL source code can be found in the `src` directory while documentation is located in `docs`. 133 | A changelog is kept at [`docs/CHANGELOG.md`](docs/CHANGELOG.md). 134 | 135 | This repository loosely follows the [GitFlow](https://nvie.com/posts/a-successful-git-branching-model/) branching model. 136 | This means that the `master` branch is considered stable and used to publish releases of the FPU while the `develop` branch contains features and bugfixes that have not yet been properly released. 137 | 138 | Furthermore, this repository tries to adhere to [SemVer](https://semver.org/), as outlined in the [changelog](docs/CHANGELOG.md). 139 | 140 | ## Licensing 141 | 142 | FPnew is released under the *SolderPad Hardware License*, which is a permissive license based on Apache 2.0. Please refer to the [SolderPad license file](LICENSE.solderpad) for further information. 143 | 144 | The T-Head E906 DivSqrt unit, integrated into FPnew in [`vendor/opene906`](vendor/opene906), is reseased under the *Apache License, Version 2.0*. Please refer to the [Apache 2.0 license file](LICENSE.apache) for further information. 145 | 146 | ## Publication 147 | 148 | If you use FPnew in your work, you can cite us: 149 | 150 |
151 | FPnew Publication 152 |

153 | 154 | ``` 155 | @article{mach2020fpnew, 156 | title={Fpnew: An open-source multiformat floating-point unit architecture for energy-proportional transprecision computing}, 157 | author={Mach, Stefan and Schuiki, Fabian and Zaruba, Florian and Benini, Luca}, 158 | journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 159 | volume={29}, 160 | number={4}, 161 | pages={774--787}, 162 | year={2020}, 163 | publisher={IEEE} 164 | } 165 | ``` 166 | 167 |

168 |

169 | 170 | If you use FPnew SDOTP in your work, you can cite us: 171 | 172 |
173 | SDOTP Publication 174 |

175 | 176 | ``` 177 | @inproceedings{bertaccini2022minifloat, 178 | title={MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores}, 179 | author={Bertaccini, Luca and Paulin, Gianna and Fischer, Tim and Mach, Stefan and Benini, Luca}, 180 | booktitle={2022 IEEE 29th Symposium on Computer Arithmetic (ARITH)}, 181 | pages={1--8}, 182 | year={2022}, 183 | organization={IEEE} 184 | } 185 | ``` 186 | 187 |

188 |
189 | 190 | 191 | ## Acknowledgement 192 | 193 | This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 732631. 194 | 195 | For further information, visit [oprecomp.eu](http://oprecomp.eu). 196 | 197 | ![OPRECOMP](docs/fig/oprecomp_logo_inline1.png) 198 | -------------------------------------------------------------------------------- /docs/CHANGELOG-PULP.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | 3 | All notable changes to this project will be documented in this file. 4 | 5 | The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). 6 | 7 | In this sense, we interpret the "Public API" of a hardware module as its port/parameter list. 8 | Versions of the IP in the same major relase are "pin-compatible" with each other. Minor relases are permitted to add new parameters as long as their default bindings ensure backwards compatibility. 9 | 10 | ## [pulp-v0.2.3] - 2024-09-27 11 | 12 | ### Fix 13 | - Fix illegal Verilog `'0` 14 | 15 | ## [pulp-v0.2.2] - 2024-06-24 16 | 17 | ### Added 18 | - Add FP16ALT support to THMULTI DivSqrt 19 | 20 | ## [pulp-v0.2.1] - 2024-06-07 21 | 22 | ### Fix 23 | - Fix synchronization of THMULTI DivSqrt lanes when FP16ALT, FP8, or FP8ALT are enabled. 24 | 25 | ## [pulp-v0.2.0] - 2024-05-29 26 | 27 | ### Added 28 | - Add support for alternative multi-format DivSqrt unit (from openC910), supporting FP64, FP32, FP16 and SIMD operations 29 | - Replace `PulpDivsqrt` top-level parameter with `DivSqrtSel` to choose among the legacy PULP DivSqrt unit (`PULP`), the openE906 DivSqrt (`TH32`), and the openC910 DivSqrt (`THMULTI`). The default choice is set to `THMULTI` 30 | 31 | ## [pulp-v0.1.3] - 2023-07-19 32 | 33 | ### Fixed 34 | - Fix `lane_valid` generation for SIMD CAST involving the largest precision available 35 | - Tie some potentially unused (depending on the FPU configuration) bits in `opgroup_multifmt_slice` to zero 36 | 37 | ## [pulp-v0.1.2] - 2023-06-12 38 | 39 | ### Fixed 40 | - Fix synchronization scheme for SIMD DivSqrt 41 | 42 | ## [pulp-v0.1.1] - 2023-05-05 43 | 44 | ### Fixed 45 | - Fix various tool compatibility issues 46 | 47 | ## [pulp-v0.1.0] - 2023-05-04 48 | 49 | ### Added 50 | - Add low and mixed-precision SDOTP with support for stochastic rounding 51 | - Add `FP8alt (1,4,3)` format 52 | - Add support for compressed vector compare results (one bit per comparison in the LSBs) 53 | -------------------------------------------------------------------------------- /docs/CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Changelog 2 | 3 | All notable changes to this project will be documented in this file. 4 | 5 | The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). 6 | 7 | In this sense, we interpret the "Public API" of a hardware module as its port/parameter list. 8 | Versions of the IP in the same major relase are "pin-compatible" with each other. Minor relases are permitted to add new parameters as long as their default bindings ensure backwards compatibility. 9 | 10 | 11 | ## [Unreleased] 12 | 13 | ### Added 14 | - Add support for alternative FP32-only DivSqrt unit 15 | 16 | ## [0.7.0] - 2023-03-20 17 | 18 | ### Added 19 | - Citation file `CITATION.cff` 20 | - Add support for RISC-V compliant classify in vectorial mode when the vector element width is at least 10 bits 21 | - Add `mask` input signal to mask exceptions from inactive SIMD elements 22 | - Add support for rounding toward odd (RISC-V V 1.0 compliant) 23 | 24 | ### Changed 25 | - Code ownership to @lucabertaccini 26 | 27 | ### Fixed 28 | - Fix de-synchronization among vectorial lanes during variable-latency operations (`fdiv`, `fsqrt`) 29 | 30 | 31 | ## [0.6.6] - 2021-04-19 32 | 33 | ### Changed 34 | - [common_cells] Bump common cells version [(#44)](https://github.com/pulp-platform/fpnew/issues/44) 35 | 36 | ## [0.6.5] - 2020-11-06 37 | 38 | ### Fixed 39 | - [common_cells] Bump to fix compilation order 40 | 41 | ## [0.6.4] - 2020-10-05 42 | 43 | ### Fixed 44 | - Updated dependencies for Bender and IPApproX [(#37)](https://github.com/pulp-platform/fpnew/issues/37) 45 | - [fpu_div_sqrt_mvp] Bump for formal version number 46 | 47 | 48 | ## [0.6.3] - 2020-10-02 49 | 50 | ### Fixed 51 | - Fix undriven signals for inactive case in `fpnew_fma_multi` 52 | - Fix potentially uncovered case item in `fpnew_pkg` 53 | - Undriven unused portions of signals in multi-format slices 54 | - Undriven portions of the result for non-divisible unit width & format width in multi-format slices 55 | - [fpu_div_sqrt_mvp] Bumped to fix signalling for underflows 56 | 57 | 58 | ## [0.6.2] - 2020-06-02 59 | 60 | ### Changed 61 | - Number of pipeline registers in multi-format units is the maximum of all contained formats instead of the first format marked `MERGED` 62 | 63 | ### Fixed 64 | - Typo in changelog 65 | - Missing type cast breaking simulation in VCS [(#24)](https://github.com/pulp-platform/fpnew/issues/24) 66 | 67 | 68 | ## [0.6.1] - 2019-07-10 69 | 70 | ### Fixed 71 | - A bug where the div/sqrt unit could lose operations in flight 72 | 73 | 74 | ## [0.6.0] - 2019-07-04 75 | 76 | ### Changed 77 | - Pipelines are generated in the datapath modules instead of separate instances 78 | 79 | ### Fixed 80 | - Don't care assignments to structs have been expanded for better tool support [(#14)](https://github.com/pulp-platform/fpnew/pull/14) 81 | - Undriven busy signal in output pipeline bypass 82 | - Typo in the documentation about the multiply operation 83 | - Generation of merged slices when the first package format is disabled 84 | - Potential simulation/synthesis mismatch of the UF flag 85 | - Various linter warnings 86 | - Documentation to reflect on updated pipeline distribution order 87 | - [fpu_div_sqrt_mvp] Bumped to fix linter warnings 88 | - [Bender] Fixed dependencies for Bender [(#15)](https://github.com/pulp-platform/fpnew/pull/15) 89 | 90 | ### Removed 91 | - Currently unused modules: `fpnew_pipe*`, `fpnew_{f2i,f2f,i2f}_cast` 92 | 93 | 94 | ## [0.5.6] - 2019-06-12 95 | 96 | ### Changed 97 | - Don't care logic value can be changed from the package now 98 | - Default pipeline config in the package is now `BEFORE` 99 | 100 | ### Fixed 101 | - Don't care values are assigned `'1` instead of `'X` by default 102 | 103 | 104 | ## [0.5.5] - 2019-06-02 105 | 106 | ### Fixed 107 | - UF flag handling according to IEEE754-2008 [(#11)](https://github.com/pulp-platform/fpnew/issues/11) 108 | 109 | 110 | ## [0.5.4] - 2019-06-02 111 | 112 | ### Added 113 | - Documentation about multi-format operations 114 | - Extended pipelining description slightly 115 | - Extended semantic versioning declaration in changelog 116 | 117 | ### Changed 118 | - Updated diagrams in architecture documentation 119 | 120 | ### Fixed 121 | - [common_cells] Bumped to fix src_files.yml bugs 122 | - [fpu_div_sqrt_mvp] Bumped to fix linter warnings 123 | 124 | 125 | ## [0.5.3] - 2019-05-31 126 | 127 | ### Fixed 128 | - ips_list.yml entry for updated common_cells 129 | 130 | 131 | ## [0.5.2] - 2019-05-31 132 | 133 | ### Fixed 134 | - Internal pipeline bypass in cast unit 135 | 136 | 137 | ## [0.5.1] - 2019-05-27 138 | 139 | ### Fixed 140 | - Include path for `common_cells` in `src_files.yml` 141 | 142 | 143 | ## [0.5.0] - 2019-05-27 144 | 145 | ### Added 146 | - The FPU :) 147 | - Initial Documentation 148 | 149 | ### Changed 150 | - "Restarted" the changelog as the old one was stale 151 | 152 | ### Fixed 153 | - Handling of exception flags for infinity operands 154 | -------------------------------------------------------------------------------- /docs/CODEOWNERS: -------------------------------------------------------------------------------- 1 | # Global owners 2 | * @lucabertaccini 3 | -------------------------------------------------------------------------------- /docs/CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing 2 | 3 | Thank you for considering contributing to FPnew! 4 | We very much appreciate contributions such as submitting bug reports and feature requests, writing code which can be included in the project or improvements to the documentation. 5 | 6 | When contributing to this repository, please first discuss the change you wish to make via issue, email, or any other method with the owners of this repository before making a change. 7 | 8 | Please, don't use the issue tracker for support questions. Instead, consider contacting the maintainers or consulting the [PULP forums](https://pulp-platform.org/community/index.php). 9 | 10 | 11 | ## Repository Structure 12 | 13 | This repository loosely follows the [GitFlow Branching Model](https://nvie.com/posts/a-successful-git-branching-model/). 14 | 15 | Some points about the workflow: 16 | - `master` branch will be used for versioned releases of the project 17 | - `develop` branch is the base for all development going on 18 | - New features / bugfixes shall create a *feature branch* off `develop` and merge back into it when the feature / fix is complete. 19 | - GitHub pull requests should be used to contribute your work by opening a PR against `develop`. 20 | - Commits should reflect some meaningful step of work and will likely be squashed and rebased before merging if it's for a single feature only. 21 | 22 | ## :wip: Under Construction 23 | 24 | This document is incomplete. We're working on it... 25 | -------------------------------------------------------------------------------- /docs/fig/multislice_block.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cvfpu/e5aa6a01b5bbe1675c3aa8872e1203413ded83d1/docs/fig/multislice_block.png -------------------------------------------------------------------------------- /docs/fig/opgrp_block.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cvfpu/e5aa6a01b5bbe1675c3aa8872e1203413ded83d1/docs/fig/opgrp_block.png -------------------------------------------------------------------------------- /docs/fig/oprecomp_logo_inline1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cvfpu/e5aa6a01b5bbe1675c3aa8872e1203413ded83d1/docs/fig/oprecomp_logo_inline1.png -------------------------------------------------------------------------------- /docs/fig/slice_block.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cvfpu/e5aa6a01b5bbe1675c3aa8872e1203413ded83d1/docs/fig/slice_block.png -------------------------------------------------------------------------------- /docs/fig/top_block.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pulp-platform/cvfpu/e5aa6a01b5bbe1675c3aa8872e1203413ded83d1/docs/fig/top_block.png -------------------------------------------------------------------------------- /ips_list.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2019 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | # 5 | # List of IPs and relative branch/commit-hash/tag. 6 | # Uses the YAML syntax. 7 | # 8 | # Examples: 9 | # 10 | # or10n: 11 | # commit: tags/PULP3_final 12 | # domain: [cluster] 13 | # udma: 14 | # commit: 62b10440 15 | # domain: [soc] 16 | # axi_slice: 17 | # commit: master 18 | # domain: [soc,cluster] 19 | # If a *tag* or *commit* is referenced, the IP will be in a 20 | # state of DETACHED HEAD. Before committing any additional 21 | # work, make sure to checkout a branch. 22 | # 23 | 24 | common_cells: 25 | commit: v1.21.0 26 | domain: [soc, cluster] 27 | 28 | fpu_div_sqrt_mvp: 29 | commit: v1.0.4 30 | domain: [cluster,soc] 31 | -------------------------------------------------------------------------------- /src/fpnew_classifier.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // SPDX-License-Identifier: SHL-0.51 13 | 14 | // Author: Stefan Mach 15 | 16 | module fpnew_classifier #( 17 | parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), 18 | parameter int unsigned NumOperands = 1, 19 | // Do not change 20 | localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) 21 | ) ( 22 | input logic [NumOperands-1:0][WIDTH-1:0] operands_i, 23 | input logic [NumOperands-1:0] is_boxed_i, 24 | output fpnew_pkg::fp_info_t [NumOperands-1:0] info_o 25 | ); 26 | 27 | localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); 28 | localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); 29 | 30 | // Type definition 31 | typedef struct packed { 32 | logic sign; 33 | logic [EXP_BITS-1:0] exponent; 34 | logic [MAN_BITS-1:0] mantissa; 35 | } fp_t; 36 | 37 | // Iterate through all operands 38 | for (genvar op = 0; op < int'(NumOperands); op++) begin : gen_num_values 39 | 40 | fp_t value; 41 | logic is_boxed; 42 | logic is_normal; 43 | logic is_inf; 44 | logic is_nan; 45 | logic is_signalling; 46 | logic is_quiet; 47 | logic is_zero; 48 | logic is_subnormal; 49 | 50 | // --------------- 51 | // Classify Input 52 | // --------------- 53 | always_comb begin : classify_input 54 | value = operands_i[op]; 55 | is_boxed = is_boxed_i[op]; 56 | is_normal = is_boxed && (value.exponent != '0) && (value.exponent != '1); 57 | is_zero = is_boxed && (value.exponent == '0) && (value.mantissa == '0); 58 | is_subnormal = is_boxed && (value.exponent == '0) && !is_zero; 59 | is_inf = is_boxed && ((value.exponent == '1) && (value.mantissa == '0)); 60 | is_nan = !is_boxed || ((value.exponent == '1) && (value.mantissa != '0)); 61 | is_signalling = is_boxed && is_nan && (value.mantissa[MAN_BITS-1] == 1'b0); 62 | is_quiet = is_nan && !is_signalling; 63 | // Assign output for current input 64 | info_o[op].is_normal = is_normal; 65 | info_o[op].is_subnormal = is_subnormal; 66 | info_o[op].is_zero = is_zero; 67 | info_o[op].is_inf = is_inf; 68 | info_o[op].is_nan = is_nan; 69 | info_o[op].is_signalling = is_signalling; 70 | info_o[op].is_quiet = is_quiet; 71 | info_o[op].is_boxed = is_boxed; 72 | end 73 | end 74 | endmodule 75 | -------------------------------------------------------------------------------- /src/fpnew_opgroup_block.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // SPDX-License-Identifier: SHL-0.51 13 | 14 | // Author: Stefan Mach 15 | 16 | module fpnew_opgroup_block #( 17 | parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::ADDMUL, 18 | // FPU configuration 19 | parameter int unsigned Width = 32, 20 | parameter logic EnableVectors = 1'b1, 21 | parameter fpnew_pkg::divsqrt_unit_t DivSqrtSel = fpnew_pkg::THMULTI, 22 | parameter fpnew_pkg::fmt_logic_t FpFmtMask = '1, 23 | parameter fpnew_pkg::ifmt_logic_t IntFmtMask = '1, 24 | parameter fpnew_pkg::fmt_unsigned_t FmtPipeRegs = '{default: 0}, 25 | parameter fpnew_pkg::fmt_unit_types_t FmtUnitTypes = '{default: fpnew_pkg::PARALLEL}, 26 | parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, 27 | parameter type TagType = logic, 28 | parameter logic TrueSIMDClass = 1'b0, 29 | parameter logic CompressedVecCmpResult = 1'b0, 30 | parameter fpnew_pkg::rsr_impl_t StochasticRndImplementation = fpnew_pkg::DEFAULT_NO_RSR, 31 | // Do not change 32 | localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, 33 | localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), 34 | localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtMask, EnableVectors), 35 | localparam type MaskType = logic [NUM_LANES-1:0] 36 | ) ( 37 | input logic clk_i, 38 | input logic rst_ni, 39 | input logic [31:0] hart_id_i, 40 | // Input signals 41 | input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, 42 | input logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed_i, 43 | input fpnew_pkg::roundmode_e rnd_mode_i, 44 | input fpnew_pkg::operation_e op_i, 45 | input logic op_mod_i, 46 | input fpnew_pkg::fp_format_e src_fmt_i, 47 | input fpnew_pkg::fp_format_e dst_fmt_i, 48 | input fpnew_pkg::int_format_e int_fmt_i, 49 | input logic vectorial_op_i, 50 | input TagType tag_i, 51 | input MaskType simd_mask_i, 52 | // Input Handshake 53 | input logic in_valid_i, 54 | output logic in_ready_o, 55 | input logic flush_i, 56 | // Output signals 57 | output logic [Width-1:0] result_o, 58 | output fpnew_pkg::status_t status_o, 59 | output logic extension_bit_o, 60 | output TagType tag_o, 61 | // Output handshake 62 | output logic out_valid_o, 63 | input logic out_ready_i, 64 | // Indication of valid data in flight 65 | output logic busy_o 66 | ); 67 | 68 | // ---------------- 69 | // Type Definition 70 | // ---------------- 71 | typedef struct packed { 72 | logic [Width-1:0] result; 73 | fpnew_pkg::status_t status; 74 | logic ext_bit; 75 | TagType tag; 76 | } output_t; 77 | 78 | // Handshake signals for the slices 79 | logic [NUM_FORMATS-1:0] fmt_in_ready, fmt_out_valid, fmt_out_ready, fmt_busy; 80 | output_t [NUM_FORMATS-1:0] fmt_outputs; 81 | 82 | // ----------- 83 | // Input Side 84 | // ----------- 85 | assign in_ready_o = in_valid_i & fmt_in_ready[dst_fmt_i]; // Ready is given by selected format 86 | 87 | // ------------------------- 88 | // Generate Parallel Slices 89 | // ------------------------- 90 | for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_parallel_slices 91 | // Some constants for this format 92 | localparam logic ANY_MERGED = fpnew_pkg::any_enabled_multi(FmtUnitTypes, FpFmtMask); 93 | localparam logic IS_FIRST_MERGED = 94 | fpnew_pkg::is_first_enabled_multi(fpnew_pkg::fp_format_e'(fmt), FmtUnitTypes, FpFmtMask); 95 | 96 | // Generate slice only if format enabled 97 | if (FpFmtMask[fmt] && (FmtUnitTypes[fmt] == fpnew_pkg::PARALLEL)) begin : active_format 98 | 99 | logic in_valid; 100 | 101 | assign in_valid = in_valid_i & (dst_fmt_i == fmt); // enable selected format 102 | 103 | // Forward masks related to the right SIMD lane 104 | localparam int unsigned INTERNAL_LANES = fpnew_pkg::num_lanes(Width, fpnew_pkg::fp_format_e'(fmt), EnableVectors); 105 | logic [INTERNAL_LANES-1:0] mask_slice; 106 | always_comb for (int b = 0; b < INTERNAL_LANES; b++) mask_slice[b] = simd_mask_i[(NUM_LANES/INTERNAL_LANES)*b]; 107 | 108 | fpnew_opgroup_fmt_slice #( 109 | .OpGroup ( OpGroup ), 110 | .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), 111 | .Width ( Width ), 112 | .EnableVectors ( EnableVectors ), 113 | .NumPipeRegs ( FmtPipeRegs[fmt] ), 114 | .PipeConfig ( PipeConfig ), 115 | .TagType ( TagType ), 116 | .TrueSIMDClass ( TrueSIMDClass ), 117 | .CompressedVecCmpResult ( CompressedVecCmpResult ) 118 | ) i_fmt_slice ( 119 | .clk_i, 120 | .rst_ni, 121 | .operands_i ( operands_i ), 122 | .is_boxed_i ( is_boxed_i[fmt] ), 123 | .rnd_mode_i, 124 | .op_i, 125 | .op_mod_i, 126 | .vectorial_op_i, 127 | .tag_i, 128 | .simd_mask_i ( mask_slice ), 129 | .in_valid_i ( in_valid ), 130 | .in_ready_o ( fmt_in_ready[fmt] ), 131 | .flush_i, 132 | .result_o ( fmt_outputs[fmt].result ), 133 | .status_o ( fmt_outputs[fmt].status ), 134 | .extension_bit_o( fmt_outputs[fmt].ext_bit ), 135 | .tag_o ( fmt_outputs[fmt].tag ), 136 | .out_valid_o ( fmt_out_valid[fmt] ), 137 | .out_ready_i ( fmt_out_ready[fmt] ), 138 | .busy_o ( fmt_busy[fmt] ) 139 | ); 140 | // If the format wants to use merged ops, tie off the dangling ones not used here 141 | end else if (FpFmtMask[fmt] && ANY_MERGED && !IS_FIRST_MERGED) begin : merged_unused 142 | 143 | localparam FMT = fpnew_pkg::get_first_enabled_multi(FmtUnitTypes, FpFmtMask); 144 | // Ready is split up into formats 145 | assign fmt_in_ready[fmt] = fmt_in_ready[int'(FMT)]; 146 | 147 | assign fmt_out_valid[fmt] = 1'b0; // don't emit values 148 | assign fmt_busy[fmt] = 1'b0; // never busy 149 | // Outputs are don't care 150 | assign fmt_outputs[fmt].result = '{default: fpnew_pkg::DONT_CARE}; 151 | assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; 152 | assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; 153 | assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); 154 | 155 | // Tie off disabled formats 156 | end else if (!FpFmtMask[fmt] || (FmtUnitTypes[fmt] == fpnew_pkg::DISABLED)) begin : disable_fmt 157 | assign fmt_in_ready[fmt] = 1'b0; // don't accept operations 158 | assign fmt_out_valid[fmt] = 1'b0; // don't emit values 159 | assign fmt_busy[fmt] = 1'b0; // never busy 160 | // Outputs are don't care 161 | assign fmt_outputs[fmt].result = '{default: fpnew_pkg::DONT_CARE}; 162 | assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; 163 | assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; 164 | assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); 165 | end 166 | end 167 | 168 | // ---------------------- 169 | // Generate Merged Slice 170 | // ---------------------- 171 | if (fpnew_pkg::any_enabled_multi(FmtUnitTypes, FpFmtMask)) begin : gen_merged_slice 172 | 173 | localparam FMT = fpnew_pkg::get_first_enabled_multi(FmtUnitTypes, FpFmtMask); 174 | localparam REG = fpnew_pkg::get_num_regs_multi(FmtPipeRegs, FmtUnitTypes, FpFmtMask); 175 | 176 | logic in_valid; 177 | 178 | assign in_valid = in_valid_i & (FmtUnitTypes[dst_fmt_i] == fpnew_pkg::MERGED); 179 | 180 | fpnew_opgroup_multifmt_slice #( 181 | .OpGroup ( OpGroup ), 182 | .Width ( Width ), 183 | .FpFmtConfig ( FpFmtMask ), 184 | .IntFmtConfig ( IntFmtMask ), 185 | .EnableVectors ( EnableVectors ), 186 | .DivSqrtSel ( DivSqrtSel ), 187 | .NumPipeRegs ( REG ), 188 | .PipeConfig ( PipeConfig ), 189 | .TagType ( TagType ), 190 | .StochasticRndImplementation ( StochasticRndImplementation ) 191 | ) i_multifmt_slice ( 192 | .clk_i, 193 | .rst_ni, 194 | .hart_id_i, 195 | .operands_i, 196 | .is_boxed_i, 197 | .rnd_mode_i, 198 | .op_i, 199 | .op_mod_i, 200 | .src_fmt_i, 201 | .dst_fmt_i, 202 | .int_fmt_i, 203 | .vectorial_op_i, 204 | .tag_i, 205 | .simd_mask_i ( simd_mask_i ), 206 | .in_valid_i ( in_valid ), 207 | .in_ready_o ( fmt_in_ready[FMT] ), 208 | .flush_i, 209 | .result_o ( fmt_outputs[FMT].result ), 210 | .status_o ( fmt_outputs[FMT].status ), 211 | .extension_bit_o ( fmt_outputs[FMT].ext_bit ), 212 | .tag_o ( fmt_outputs[FMT].tag ), 213 | .out_valid_o ( fmt_out_valid[FMT] ), 214 | .out_ready_i ( fmt_out_ready[FMT] ), 215 | .busy_o ( fmt_busy[FMT] ) 216 | ); 217 | 218 | end 219 | 220 | // ------------------ 221 | // Arbitrate Outputs 222 | // ------------------ 223 | output_t arbiter_output; 224 | 225 | // Round-Robin arbiter to decide which result to use 226 | rr_arb_tree #( 227 | .NumIn ( NUM_FORMATS ), 228 | .DataType ( output_t ), 229 | .AxiVldRdy ( 1'b1 ) 230 | ) i_arbiter ( 231 | .clk_i, 232 | .rst_ni, 233 | .flush_i, 234 | .rr_i ( '0 ), 235 | .req_i ( fmt_out_valid ), 236 | .gnt_o ( fmt_out_ready ), 237 | .data_i ( fmt_outputs ), 238 | .gnt_i ( out_ready_i ), 239 | .req_o ( out_valid_o ), 240 | .data_o ( arbiter_output ), 241 | .idx_o ( /* unused */ ) 242 | ); 243 | 244 | // Unpack output 245 | assign result_o = arbiter_output.result; 246 | assign status_o = arbiter_output.status; 247 | assign extension_bit_o = arbiter_output.ext_bit; 248 | assign tag_o = arbiter_output.tag; 249 | 250 | assign busy_o = (| fmt_busy); 251 | 252 | endmodule 253 | -------------------------------------------------------------------------------- /src/fpnew_rounding.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // SPDX-License-Identifier: SHL-0.51 13 | 14 | // Author: Stefan Mach 15 | 16 | module fpnew_rounding #( 17 | parameter int unsigned AbsWidth = 2, // Width of the abolute value, without sign bit 18 | parameter logic EnableRSR = 0, 19 | parameter int unsigned RsrPrecision = 12, 20 | //LFSR patameters 21 | parameter int unsigned LfsrWidth = 32, 22 | parameter logic [LfsrWidth-1:0] RstVal = '1 23 | ) ( 24 | // LFSR inputs 25 | input logic clk_i, 26 | input logic rst_ni, 27 | input logic [33:0] id_i, 28 | // Input value 29 | input logic [AbsWidth-1:0] abs_value_i, // absolute value without sign 30 | input logic sign_i, 31 | input logic en_rsr_i, 32 | // Rounding information 33 | input logic [1:0] round_sticky_bits_i, // round and sticky bits {RS} 34 | input logic [RsrPrecision-1:0] stochastic_rounding_bits_i, 35 | input fpnew_pkg::roundmode_e rnd_mode_i, 36 | input logic effective_subtraction_i, // sign of inputs affects rounding of zeroes 37 | // Output value 38 | output logic [AbsWidth-1:0] abs_rounded_o, // absolute value without sign 39 | output logic sign_o, 40 | // Output classification 41 | output logic exact_zero_o // output is an exact zero 42 | ); 43 | 44 | logic round_up; // Rounding decision 45 | 46 | // Take the rounding decision according to RISC-V spec, plus additional unbiased rounding modes 47 | // RoundMode | Mnemonic | Meaning 48 | // :--------:|:--------:|:------- 49 | // 000 | RNE | Round to Nearest, ties to Even 50 | // 001 | RTZ | Round towards Zero 51 | // 010 | RDN | Round Down (towards -\infty) 52 | // 011 | RUP | Round Up (towards \infty) 53 | // 100 | RMM | Round to Nearest, ties to Max Magnitude 54 | // 101 | ROD | Round towards odd (this mode is not define in RISC-V FP-SPEC) 55 | // 110 | RSR | Round by Stochastic Rounding 56 | // others | | *invalid* 57 | 58 | // LFSR generating random numbers for RSR mode 59 | logic [RsrPrecision-1:0] lfsr_out; 60 | 61 | if (EnableRSR) begin : gen_lfsr 62 | lfsr_sr #( 63 | .LfsrWidth ( LfsrWidth ), 64 | .OutWidth ( RsrPrecision ), 65 | .RstVal ( RstVal ), 66 | .CipherLayers ( 0 ), 67 | .CipherReg ( 0 ) 68 | ) i_lfsr ( 69 | .clk_i ( clk_i ), 70 | .rst_ni ( rst_ni ), 71 | .id_i ( id_i ), 72 | .en_i ( en_rsr_i ), 73 | .out_o ( lfsr_out ) 74 | ); 75 | end else begin 76 | assign lfsr_out = '0; 77 | end 78 | 79 | // Rounding results by stochastic rounding 80 | always_comb begin : rounding_decision 81 | unique case (rnd_mode_i) 82 | fpnew_pkg::RNE: // Decide according to round/sticky bits 83 | unique case (round_sticky_bits_i) 84 | 2'b00, 85 | 2'b01: round_up = 1'b0; // < ulp/2 away, round down 86 | 2'b10: round_up = abs_value_i[0]; // = ulp/2 away, round towards even result 87 | 2'b11: round_up = 1'b1; // > ulp/2 away, round up 88 | default: round_up = fpnew_pkg::DONT_CARE; 89 | endcase 90 | fpnew_pkg::RTZ: round_up = 1'b0; // always round down 91 | fpnew_pkg::RDN: round_up = (| round_sticky_bits_i) ? sign_i : 1'b0; // to 0 if +, away if - 92 | fpnew_pkg::RUP: round_up = (| round_sticky_bits_i) ? ~sign_i : 1'b0; // to 0 if -, away if + 93 | fpnew_pkg::RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up 94 | fpnew_pkg::ROD: round_up = ~abs_value_i[0] & (| round_sticky_bits_i); 95 | // Decide stochastically, comparing trailing bits and pseudo-random number 96 | fpnew_pkg::RSR: begin 97 | if (EnableRSR) begin 98 | round_up = (lfsr_out < stochastic_rounding_bits_i) ? 1'b1 : 1'b0; 99 | end else begin 100 | round_up = fpnew_pkg::DONT_CARE; 101 | end 102 | end 103 | default: round_up = fpnew_pkg::DONT_CARE; // propagate x 104 | endcase 105 | end 106 | 107 | // Perform the rounding, exponent change and overflow to inf happens automagically 108 | assign abs_rounded_o = abs_value_i + round_up; 109 | 110 | // True zero result is a zero result without dirty round/sticky bits 111 | assign exact_zero_o = (abs_value_i == '0) && (round_sticky_bits_i == '0); 112 | 113 | // In case of effective subtraction (thus signs of addition operands must have differed) and a 114 | // true zero result, the result sign is '-' in case of RDN and '+' for other modes. 115 | assign sign_o = (exact_zero_o && effective_subtraction_i) 116 | ? (rnd_mode_i == fpnew_pkg::RDN) 117 | : sign_i; 118 | 119 | endmodule 120 | -------------------------------------------------------------------------------- /src/fpnew_sdotp_multi_wrapper.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019-2021 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // SPDX-License-Identifier: SHL-0.51 13 | 14 | // Author: Gianna Paulin 15 | // Author: Luca Bertaccini 16 | // Author: Stefan Mach 17 | 18 | `include "common_cells/registers.svh" 19 | 20 | module fpnew_sdotp_multi_wrapper #( 21 | parameter int unsigned LaneWidth = 64, 22 | parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, 23 | parameter int unsigned NumPipeRegs = 0, 24 | parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, 25 | parameter type TagType = logic, 26 | parameter type AuxType = logic, 27 | parameter fpnew_pkg::rsr_impl_t StochasticRndImplementation = fpnew_pkg::DEFAULT_NO_RSR, 28 | // Do not change 29 | localparam fpnew_pkg::fmt_logic_t FpSrcFmtConfig = FpFmtConfig[0] ? (FpFmtConfig & 6'b001111) : (FpFmtConfig & 6'b000101), 30 | localparam fpnew_pkg::fmt_logic_t FpDstFmtConfig = fpnew_pkg::get_dotp_dst_fmts(FpFmtConfig, FpSrcFmtConfig), 31 | localparam int SRC_WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpSrcFmtConfig), 1), 32 | localparam int DST_WIDTH = fpnew_pkg::maximum(2*fpnew_pkg::max_fp_width(FpSrcFmtConfig), 1), // do not change, current assumption of sdotpex_multi 33 | localparam int OPERAND_WIDTH = LaneWidth, 34 | localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS 35 | ) ( 36 | input logic clk_i, 37 | input logic rst_ni, 38 | input logic [33:0] sdotp_hart_id_i, 39 | // Input signals 40 | input logic [2:0][OPERAND_WIDTH-1:0] operands_i, // 3 operands 41 | input logic [NUM_FORMATS-1:0][2:0] is_boxed_i, // 3 operands 42 | input fpnew_pkg::roundmode_e rnd_mode_i, 43 | input fpnew_pkg::operation_e op_i, 44 | input logic op_mod_i, 45 | input fpnew_pkg::fp_format_e src_fmt_i, 46 | input fpnew_pkg::fp_format_e dst_fmt_i, 47 | input TagType tag_i, 48 | input logic mask_i, 49 | input AuxType aux_i, 50 | // Input Handshake 51 | input logic in_valid_i, 52 | output logic in_ready_o, 53 | input logic flush_i, 54 | // Output signals 55 | output logic [OPERAND_WIDTH-1:0] result_o, 56 | output fpnew_pkg::status_t status_o, 57 | output logic extension_bit_o, 58 | output TagType tag_o, 59 | output logic mask_o, 60 | output AuxType aux_o, 61 | // Output handshake 62 | output logic out_valid_o, 63 | input logic out_ready_i, 64 | // Indication of valid data in flight 65 | output logic busy_o 66 | ); 67 | 68 | // ---------- 69 | // Constants 70 | // ---------- 71 | localparam int unsigned N_SRC_FMT_OPERANDS = 4; 72 | localparam int unsigned N_DST_FMT_OPERANDS = 1; 73 | 74 | // ----------------- 75 | // Input processing 76 | // ----------------- 77 | logic [NUM_FORMATS-1:0][DST_WIDTH-1:0] local_src_fmt_operand_a; // lane-local operands 78 | logic [NUM_FORMATS-1:0][SRC_WIDTH-1:0] local_src_fmt_operand_b; // lane-local operands 79 | logic [NUM_FORMATS-1:0][DST_WIDTH-1:0] local_src_fmt_operand_c; // lane-local operands 80 | logic [NUM_FORMATS-1:0][SRC_WIDTH-1:0] local_src_fmt_operand_d; // lane-local operands 81 | logic [DST_WIDTH-1:0] local_dst_fmt_operands; // lane-local operands 82 | logic [NUM_FORMATS-1:0][N_SRC_FMT_OPERANDS+N_DST_FMT_OPERANDS-1:0] local_is_boxed; // lane-local operands 83 | logic [OPERAND_WIDTH-1:0] local_result; // lane-local operands 84 | 85 | 86 | // ---------------------------------- 87 | // assign operands with dst format 88 | // ---------------------------------- 89 | assign local_dst_fmt_operands = operands_i[2][DST_WIDTH-1:0]; 90 | 91 | 92 | // ---------------------------------- 93 | // assign operands with src format 94 | // ---------------------------------- 95 | // NaN-boxing check 96 | for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_nanbox 97 | 98 | localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); 99 | localparam int unsigned FP_WIDTH_MIN = fpnew_pkg::minimum(SRC_WIDTH, FP_WIDTH); 100 | localparam int unsigned FP_WIDTH_DST_MIN = fpnew_pkg::minimum(DST_WIDTH, FP_WIDTH); 101 | 102 | logic [N_SRC_FMT_OPERANDS-1:0][FP_WIDTH_DST_MIN-1:0] tmp_operands; // lane-local operands 103 | 104 | always_comb begin : nanbox 105 | // shift operands to correct position 106 | tmp_operands[0] = operands_i[0] >> 0*FP_WIDTH; 107 | tmp_operands[1] = operands_i[1] >> 0*FP_WIDTH; 108 | tmp_operands[2] = operands_i[0] >> 1*FP_WIDTH; 109 | tmp_operands[3] = operands_i[1] >> 1*FP_WIDTH; 110 | // nan-box if needed 111 | local_src_fmt_operand_a[fmt] = '1; 112 | local_src_fmt_operand_b[fmt] = '1; 113 | local_src_fmt_operand_c[fmt] = '1; 114 | local_src_fmt_operand_d[fmt] = '1; 115 | if (op_i == fpnew_pkg::VSUM) begin 116 | local_src_fmt_operand_a[fmt][FP_WIDTH_DST_MIN-1:0] = tmp_operands[0][FP_WIDTH_DST_MIN-1:0]; 117 | local_src_fmt_operand_b[fmt][FP_WIDTH_MIN-1:0] = '1; 118 | if(FP_WIDTH == LaneWidth) begin 119 | local_src_fmt_operand_c[fmt][FP_WIDTH_DST_MIN-1:0] = tmp_operands[1][FP_WIDTH_DST_MIN-1:0]; 120 | end else begin 121 | local_src_fmt_operand_c[fmt][FP_WIDTH_DST_MIN-1:0] = tmp_operands[2][FP_WIDTH_DST_MIN-1:0]; 122 | end 123 | local_src_fmt_operand_d[fmt][FP_WIDTH_MIN-1:0] = '1; 124 | end else begin 125 | local_src_fmt_operand_a[fmt][FP_WIDTH_MIN-1:0] = tmp_operands[0][FP_WIDTH_MIN-1:0]; 126 | local_src_fmt_operand_b[fmt][FP_WIDTH_MIN-1:0] = tmp_operands[1][FP_WIDTH_MIN-1:0]; 127 | local_src_fmt_operand_c[fmt][FP_WIDTH_MIN-1:0] = tmp_operands[2][FP_WIDTH_MIN-1:0]; 128 | local_src_fmt_operand_d[fmt][FP_WIDTH_MIN-1:0] = tmp_operands[3][FP_WIDTH_MIN-1:0]; 129 | end 130 | // take is_boxed info from external or set to 1 if boxed for dotp operation 131 | local_is_boxed[fmt][0] = is_boxed_i[fmt][0]; 132 | local_is_boxed[fmt][1] = is_boxed_i[fmt][1]; 133 | local_is_boxed[fmt][2] = is_boxed_i[fmt][0]; 134 | local_is_boxed[fmt][3] = is_boxed_i[fmt][1]; 135 | if(FP_WIDTH <= SRC_WIDTH) begin 136 | local_is_boxed[fmt][0] = '1; 137 | local_is_boxed[fmt][1] = '1; 138 | local_is_boxed[fmt][2] = '1; 139 | local_is_boxed[fmt][3] = '1; 140 | end 141 | local_is_boxed[fmt][4] = is_boxed_i[dst_fmt_i][2]; 142 | end 143 | end 144 | 145 | fpnew_sdotp_multi #( 146 | .SrcDotpFpFmtConfig ( FpSrcFmtConfig ), // FP8, FP8ALT, FP16, FP16ALT 147 | .DstDotpFpFmtConfig ( FpDstFmtConfig ), // FP32, FP16, FP16ALT 148 | .NumPipeRegs ( NumPipeRegs ), 149 | .PipeConfig ( PipeConfig ), 150 | .TagType ( TagType ), 151 | .AuxType ( AuxType ), 152 | .StochasticRndImplementation ( StochasticRndImplementation ) 153 | ) i_fpnew_sdotp_multi ( 154 | .clk_i, 155 | .rst_ni, 156 | .sdotp_hart_id_i, 157 | .operand_a_i ( local_src_fmt_operand_a[src_fmt_i] ), 158 | .operand_b_i ( local_src_fmt_operand_b[src_fmt_i] ), 159 | .operand_c_i ( local_src_fmt_operand_c[src_fmt_i] ), 160 | .operand_d_i ( local_src_fmt_operand_d[src_fmt_i] ), 161 | .dst_operands_i ( local_dst_fmt_operands ), // 1 operand 162 | .is_boxed_i ( local_is_boxed ), 163 | .rnd_mode_i, 164 | .op_i, 165 | .op_mod_i, 166 | .src_fmt_i, // format of the multiplicands 167 | .dst_fmt_i, // format of the addend and result 168 | .tag_i, 169 | .mask_i, 170 | .aux_i, 171 | .in_valid_i, 172 | .in_ready_o , 173 | .flush_i, 174 | .result_o ( local_result[DST_WIDTH-1:0] ), 175 | .status_o, 176 | .extension_bit_o, 177 | .tag_o, 178 | .mask_o, 179 | .aux_o, 180 | .out_valid_o, 181 | .out_ready_i, 182 | .busy_o 183 | ); 184 | 185 | if(OPERAND_WIDTH > DST_WIDTH) begin 186 | assign local_result[OPERAND_WIDTH-1:DST_WIDTH] = '1; 187 | end 188 | assign result_o = local_result; 189 | 190 | endmodule 191 | -------------------------------------------------------------------------------- /src/fpnew_top.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2019 ETH Zurich and University of Bologna. 2 | // 3 | // Copyright and related rights are licensed under the Solderpad Hardware 4 | // License, Version 0.51 (the "License"); you may not use this file except in 5 | // compliance with the License. You may obtain a copy of the License at 6 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 7 | // or agreed to in writing, software, hardware and materials distributed under 8 | // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 9 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 10 | // specific language governing permissions and limitations under the License. 11 | // 12 | // SPDX-License-Identifier: SHL-0.51 13 | 14 | // Author: Stefan Mach 15 | 16 | module fpnew_top #( 17 | // FPU configuration 18 | parameter fpnew_pkg::fpu_features_t Features = fpnew_pkg::RV64D_Xsflt, 19 | parameter fpnew_pkg::fpu_implementation_t Implementation = fpnew_pkg::DEFAULT_NOREGS, 20 | // DivSqrtSel chooses among PULP, TH32, or THMULTI (see documentation and fpnew_pkg.sv for further details) 21 | parameter fpnew_pkg::divsqrt_unit_t DivSqrtSel = fpnew_pkg::THMULTI, 22 | parameter type TagType = logic, 23 | parameter logic TrueSIMDClass = 1'b0, 24 | parameter logic EnableSIMDMask = 1'b0, 25 | parameter logic CompressedVecCmpResult = 1'b0, // conceived for RV32FD cores 26 | parameter fpnew_pkg::rsr_impl_t StochasticRndImplementation = fpnew_pkg::DEFAULT_NO_RSR, 27 | // Do not change 28 | localparam int unsigned NumLanes = fpnew_pkg::max_num_lanes(Features.Width, Features.FpFmtMask, Features.EnableVectors), 29 | localparam type MaskType = logic [NumLanes-1:0], 30 | localparam int unsigned WIDTH = Features.Width, 31 | localparam int unsigned NUM_OPERANDS = 3 32 | ) ( 33 | input logic clk_i, 34 | input logic rst_ni, 35 | input logic [31:0] hart_id_i, 36 | // Input signals 37 | input logic [NUM_OPERANDS-1:0][WIDTH-1:0] operands_i, 38 | input fpnew_pkg::roundmode_e rnd_mode_i, 39 | input fpnew_pkg::operation_e op_i, 40 | input logic op_mod_i, 41 | input fpnew_pkg::fp_format_e src_fmt_i, 42 | input fpnew_pkg::fp_format_e dst_fmt_i, 43 | input fpnew_pkg::int_format_e int_fmt_i, 44 | input logic vectorial_op_i, 45 | input TagType tag_i, 46 | input MaskType simd_mask_i, 47 | // Input Handshake 48 | input logic in_valid_i, 49 | output logic in_ready_o, 50 | input logic flush_i, 51 | // Output signals 52 | output logic [WIDTH-1:0] result_o, 53 | output fpnew_pkg::status_t status_o, 54 | output TagType tag_o, 55 | // Output handshake 56 | output logic out_valid_o, 57 | input logic out_ready_i, 58 | // Indication of valid data in flight 59 | output logic busy_o 60 | ); 61 | 62 | localparam int unsigned NUM_OPGROUPS = fpnew_pkg::NUM_OPGROUPS; 63 | localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS; 64 | 65 | // ---------------- 66 | // Type Definition 67 | // ---------------- 68 | typedef struct packed { 69 | logic [WIDTH-1:0] result; 70 | fpnew_pkg::status_t status; 71 | TagType tag; 72 | } output_t; 73 | 74 | // Handshake signals for the blocks 75 | logic [NUM_OPGROUPS-1:0] opgrp_in_ready, opgrp_out_valid, opgrp_out_ready, opgrp_ext, opgrp_busy; 76 | output_t [NUM_OPGROUPS-1:0] opgrp_outputs; 77 | 78 | logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed; 79 | 80 | // ----------- 81 | // Input Side 82 | // ----------- 83 | assign in_ready_o = in_valid_i & opgrp_in_ready[fpnew_pkg::get_opgroup(op_i)]; 84 | 85 | // NaN-boxing check 86 | for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_nanbox_check 87 | localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); 88 | // NaN boxing is only generated if it's enabled and needed 89 | if (Features.EnableNanBox && (FP_WIDTH < WIDTH)) begin : check 90 | for (genvar op = 0; op < int'(NUM_OPERANDS); op++) begin : operands 91 | assign is_boxed[fmt][op] = (!vectorial_op_i) 92 | ? operands_i[op][WIDTH-1:FP_WIDTH] == '1 93 | : 1'b1; 94 | end 95 | end else begin : no_check 96 | assign is_boxed[fmt] = '1; 97 | end 98 | end 99 | 100 | // Filter out the mask if not used 101 | MaskType simd_mask; 102 | assign simd_mask = simd_mask_i | ~{NumLanes{EnableSIMDMask}}; 103 | 104 | // ------------------------- 105 | // Generate Operation Blocks 106 | // ------------------------- 107 | for (genvar opgrp = 0; opgrp < int'(NUM_OPGROUPS); opgrp++) begin : gen_operation_groups 108 | localparam int unsigned NUM_OPS = fpnew_pkg::num_operands(fpnew_pkg::opgroup_e'(opgrp)); 109 | 110 | logic in_valid; 111 | logic [NUM_FORMATS-1:0][NUM_OPS-1:0] input_boxed; 112 | 113 | assign in_valid = in_valid_i & (fpnew_pkg::get_opgroup(op_i) == fpnew_pkg::opgroup_e'(opgrp)); 114 | 115 | // slice out input boxing 116 | always_comb begin : slice_inputs 117 | for (int unsigned fmt = 0; fmt < NUM_FORMATS; fmt++) 118 | input_boxed[fmt] = is_boxed[fmt][NUM_OPS-1:0]; 119 | end 120 | 121 | fpnew_opgroup_block #( 122 | .OpGroup ( fpnew_pkg::opgroup_e'(opgrp) ), 123 | .Width ( WIDTH ), 124 | .EnableVectors ( Features.EnableVectors ), 125 | .DivSqrtSel ( DivSqrtSel ), 126 | .FpFmtMask ( Features.FpFmtMask ), 127 | .IntFmtMask ( Features.IntFmtMask ), 128 | .FmtPipeRegs ( Implementation.PipeRegs[opgrp] ), 129 | .FmtUnitTypes ( Implementation.UnitTypes[opgrp] ), 130 | .PipeConfig ( Implementation.PipeConfig ), 131 | .TagType ( TagType ), 132 | .TrueSIMDClass ( TrueSIMDClass ), 133 | .CompressedVecCmpResult ( CompressedVecCmpResult ), 134 | .StochasticRndImplementation ( StochasticRndImplementation ) 135 | ) i_opgroup_block ( 136 | .clk_i, 137 | .rst_ni, 138 | .hart_id_i, 139 | .operands_i ( operands_i[NUM_OPS-1:0] ), 140 | .is_boxed_i ( input_boxed ), 141 | .rnd_mode_i, 142 | .op_i, 143 | .op_mod_i, 144 | .src_fmt_i, 145 | .dst_fmt_i, 146 | .int_fmt_i, 147 | .vectorial_op_i, 148 | .tag_i, 149 | .simd_mask_i ( simd_mask ), 150 | .in_valid_i ( in_valid ), 151 | .in_ready_o ( opgrp_in_ready[opgrp] ), 152 | .flush_i, 153 | .result_o ( opgrp_outputs[opgrp].result ), 154 | .status_o ( opgrp_outputs[opgrp].status ), 155 | .extension_bit_o ( opgrp_ext[opgrp] ), 156 | .tag_o ( opgrp_outputs[opgrp].tag ), 157 | .out_valid_o ( opgrp_out_valid[opgrp] ), 158 | .out_ready_i ( opgrp_out_ready[opgrp] ), 159 | .busy_o ( opgrp_busy[opgrp] ) 160 | ); 161 | end 162 | 163 | // ------------------ 164 | // Arbitrate Outputs 165 | // ------------------ 166 | output_t arbiter_output; 167 | 168 | // Round-Robin arbiter to decide which result to use 169 | rr_arb_tree #( 170 | .NumIn ( NUM_OPGROUPS ), 171 | .DataType ( output_t ), 172 | .AxiVldRdy ( 1'b1 ) 173 | ) i_arbiter ( 174 | .clk_i, 175 | .rst_ni, 176 | .flush_i, 177 | .rr_i ( '0 ), 178 | .req_i ( opgrp_out_valid ), 179 | .gnt_o ( opgrp_out_ready ), 180 | .data_i ( opgrp_outputs ), 181 | .gnt_i ( out_ready_i ), 182 | .req_o ( out_valid_o ), 183 | .data_o ( arbiter_output ), 184 | .idx_o ( /* unused */ ) 185 | ); 186 | 187 | // Unpack output 188 | assign result_o = arbiter_output.result; 189 | assign status_o = arbiter_output.status; 190 | assign tag_o = arbiter_output.tag; 191 | 192 | assign busy_o = (| opgrp_busy); 193 | 194 | endmodule 195 | -------------------------------------------------------------------------------- /src_files.yml: -------------------------------------------------------------------------------- 1 | # Copyright 2019 ETH Zurich and University of Bologna. 2 | # Solderpad Hardware License, Version 0.51, see LICENSE for details. 3 | # SPDX-License-Identifier: SHL-0.51 4 | fpnew: 5 | incdirs: [ 6 | ../common_cells/include, 7 | ] 8 | files: [ 9 | src/fpnew_pkg.sv, 10 | src/fpnew_cast_multi.sv, 11 | src/fpnew_classifier.sv, 12 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v, 13 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v, 14 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v, 15 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v, 16 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v, 17 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v, 18 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v, 19 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v, 20 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v, 21 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v, 22 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v, 23 | vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v, 24 | # vendor/openc910/C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v, # same as the one from E906 25 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v, 26 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v, 27 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v, 28 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_pack.v, 29 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v, 30 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_round.v, 31 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v, 32 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v, 33 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_with_sqrt.v, 34 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v, 35 | vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v, 36 | src/fpnew_divsqrt_th_32.sv, 37 | src/fpnew_divsqrt_th_64_multi.sv, 38 | src/fpnew_divsqrt_multi.sv, 39 | src/fpnew_fma.sv, 40 | src/fpnew_fma_multi.sv, 41 | src/fpnew_sdotp_multi.sv, 42 | src/fpnew_sdotp_multi_wrapper.sv, 43 | src/fpnew_noncomp.sv, 44 | src/fpnew_opgroup_block.sv, 45 | src/fpnew_opgroup_fmt_slice.sv, 46 | src/fpnew_opgroup_multifmt_slice.sv, 47 | src/fpnew_rounding.sv, 48 | src/lfsr_sr.sv, 49 | src/fpnew_top.sv, 50 | ] 51 | -------------------------------------------------------------------------------- /util/README.md: -------------------------------------------------------------------------------- 1 | Content: 2 | 3 | * vendor.py 4 | - vendorization script 5 | - copied from https://github.com/openhwgroup/cv32e40p/blob/master/util/vendor.py, commit 69e839e 6 | -------------------------------------------------------------------------------- /vendor/openc910.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/T-head-Semi/openc910 12 | rev: e0c4ad8ec7f8c70f649d826ebd6c949086453272 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/openc910.vendor.hjson: -------------------------------------------------------------------------------- 1 | // Copyright 2023 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | { 5 | name: "openc910", 6 | target_dir: "openc910" 7 | 8 | upstream: { 9 | url: "https://github.com/T-head-Semi/openc910" 10 | rev: "e0c4ad8ec7f8c70f649d826ebd6c949086453272" 11 | } 12 | 13 | patch_dir: "patches/openc910" 14 | 15 | exclude_from_upstream: [ 16 | "doc", 17 | "smart_run", 18 | "C910_RTL_FACTORY/gen_rtl/biu", 19 | "C910_RTL_FACTORY/gen_rtl/biu/rtl", 20 | "C910_RTL_FACTORY/gen_rtl/ciu", 21 | "C910_RTL_FACTORY/gen_rtl/clint", 22 | "C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v", 23 | "C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_clk_top.v", 24 | "C910_RTL_FACTORY/gen_rtl/common", 25 | "C910_RTL_FACTORY/gen_rtl/cp0", 26 | "C910_RTL_FACTORY/gen_rtl/cpu", 27 | "C910_RTL_FACTORY/gen_rtl/filelists", 28 | "C910_RTL_FACTORY/gen_rtl/fpga", 29 | "C910_RTL_FACTORY/gen_rtl/had", 30 | "C910_RTL_FACTORY/gen_rtl/idu", 31 | "C910_RTL_FACTORY/gen_rtl/ifu", 32 | "C910_RTL_FACTORY/gen_rtl/iu", 33 | "C910_RTL_FACTORY/gen_rtl/l2c", 34 | "C910_RTL_FACTORY/gen_rtl/lsu", 35 | "C910_RTL_FACTORY/gen_rtl/mmu", 36 | "C910_RTL_FACTORY/gen_rtl/plic", 37 | "C910_RTL_FACTORY/gen_rtl/pmp", 38 | "C910_RTL_FACTORY/gen_rtl/pmu", 39 | "C910_RTL_FACTORY/gen_rtl/rst", 40 | "C910_RTL_FACTORY/gen_rtl/rtu", 41 | "C910_RTL_FACTORY/gen_rtl/vfalu", 42 | "C910_RTL_FACTORY/gen_rtl/vfmau", 43 | "C910_RTL_FACTORY/gen_rtl/vfpu", 44 | "C910_RTL_FACTORY/gen_rtl/vfpu/rtl", 45 | "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_only_div.v", 46 | "C910_RTL_FACTORY/setup" 47 | ] 48 | 49 | } 50 | -------------------------------------------------------------------------------- /vendor/openc910/C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module gated_clk_cell( 17 | clk_in, 18 | global_en, 19 | module_en, 20 | local_en, 21 | external_en, 22 | pad_yy_icg_scan_en, 23 | clk_out 24 | ); 25 | 26 | input clk_in; 27 | input global_en; 28 | input module_en; 29 | input local_en; 30 | input external_en; 31 | input pad_yy_icg_scan_en; 32 | output clk_out; 33 | 34 | wire clk_en_bf_latch; 35 | wire SE; 36 | 37 | assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ; 38 | 39 | // SE driven from primary input, held constant 40 | assign SE = pad_yy_icg_scan_en; 41 | 42 | // // &Connect( .clk_in (clk_in), @50 43 | // // .SE (SE), @51 44 | // // .external_en (clk_en_bf_latch), @52 45 | // // .clk_out (clk_out) @53 46 | // // ) ; @54 47 | assign clk_out = clk_in; 48 | 49 | endmodule -------------------------------------------------------------------------------- /vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module ct_vfdsu_ff1( 16 | fanc_shift_num, 17 | frac_bin_val, 18 | frac_num 19 | ); 20 | 21 | // &Ports; @22 22 | input [51:0] frac_num; 23 | output [51:0] fanc_shift_num; 24 | output [12:0] frac_bin_val; 25 | 26 | // &Regs; @23 27 | reg [51:0] fanc_shift_num; 28 | reg [12:0] frac_bin_val; 29 | 30 | // &Wires; @24 31 | wire [51:0] frac_num; 32 | 33 | 34 | // &CombBeg; @26 35 | always @( frac_num[51:0]) 36 | begin 37 | casez(frac_num[51:0]) 38 | 52'b1???????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h0; fanc_shift_num[51:0] = frac_num[51:0]; end 39 | 52'b01??????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fff; fanc_shift_num[51:0] = {frac_num[50:0],1'b0};end 40 | 52'b001?????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffe; fanc_shift_num[51:0] = {frac_num[49:0],2'b0};end 41 | 52'b0001????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffd; fanc_shift_num[51:0] = {frac_num[48:0],3'b0};end 42 | 52'b00001???????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffc; fanc_shift_num[51:0] = {frac_num[47:0],4'b0};end 43 | 52'b000001??????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffb; fanc_shift_num[51:0] = {frac_num[46:0],5'b0};end 44 | 52'b0000001?????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffa; fanc_shift_num[51:0] = {frac_num[45:0],6'b0};end 45 | 52'b00000001????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff9; fanc_shift_num[51:0] = {frac_num[44:0],7'b0};end 46 | 52'b000000001???????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff8; fanc_shift_num[51:0] = {frac_num[43:0],8'b0};end 47 | 52'b0000000001??????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff7; fanc_shift_num[51:0] = {frac_num[42:0],9'b0};end 48 | 52'b00000000001?????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff6; fanc_shift_num[51:0] = {frac_num[41:0],10'b0};end 49 | 52'b000000000001????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff5; fanc_shift_num[51:0] = {frac_num[40:0],11'b0};end 50 | 52'b0000000000001???????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff4; fanc_shift_num[51:0] = {frac_num[39:0],12'b0};end 51 | 52'b00000000000001??????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff3; fanc_shift_num[51:0] = {frac_num[38:0],13'b0};end 52 | 52'b000000000000001?????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff2; fanc_shift_num[51:0] = {frac_num[37:0],14'b0};end 53 | 52'b0000000000000001????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff1; fanc_shift_num[51:0] = {frac_num[36:0],15'b0};end 54 | 52'b00000000000000001???????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff0; fanc_shift_num[51:0] = {frac_num[35:0],16'b0};end 55 | 52'b000000000000000001??????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fef; fanc_shift_num[51:0] = {frac_num[34:0],17'b0};end 56 | 52'b0000000000000000001?????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fee; fanc_shift_num[51:0] = {frac_num[33:0],18'b0};end 57 | 52'b00000000000000000001????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fed; fanc_shift_num[51:0] = {frac_num[32:0],19'b0};end 58 | 52'b000000000000000000001???????????????????????????????: begin frac_bin_val[12:0] = 13'h1fec; fanc_shift_num[51:0] = {frac_num[31:0],20'b0};end 59 | 52'b0000000000000000000001??????????????????????????????: begin frac_bin_val[12:0] = 13'h1feb; fanc_shift_num[51:0] = {frac_num[30:0],21'b0};end 60 | 52'b00000000000000000000001?????????????????????????????: begin frac_bin_val[12:0] = 13'h1fea; fanc_shift_num[51:0] = {frac_num[29:0],22'b0};end 61 | 52'b000000000000000000000001????????????????????????????: begin frac_bin_val[12:0] = 13'h1fe9; fanc_shift_num[51:0] = {frac_num[28:0],23'b0};end 62 | 52'b0000000000000000000000001???????????????????????????: begin frac_bin_val[12:0] = 13'h1fe8; fanc_shift_num[51:0] = {frac_num[27:0],24'b0};end 63 | 52'b00000000000000000000000001??????????????????????????: begin frac_bin_val[12:0] = 13'h1fe7; fanc_shift_num[51:0] = {frac_num[26:0],25'b0};end 64 | 52'b000000000000000000000000001?????????????????????????: begin frac_bin_val[12:0] = 13'h1fe6; fanc_shift_num[51:0] = {frac_num[25:0],26'b0};end 65 | 52'b0000000000000000000000000001????????????????????????: begin frac_bin_val[12:0] = 13'h1fe5; fanc_shift_num[51:0] = {frac_num[24:0],27'b0};end 66 | 52'b00000000000000000000000000001???????????????????????: begin frac_bin_val[12:0] = 13'h1fe4; fanc_shift_num[51:0] = {frac_num[23:0],28'b0};end 67 | 52'b000000000000000000000000000001??????????????????????: begin frac_bin_val[12:0] = 13'h1fe3; fanc_shift_num[51:0] = {frac_num[22:0],29'b0};end 68 | 52'b0000000000000000000000000000001?????????????????????: begin frac_bin_val[12:0] = 13'h1fe2; fanc_shift_num[51:0] = {frac_num[21:0],30'b0};end 69 | 52'b00000000000000000000000000000001????????????????????: begin frac_bin_val[12:0] = 13'h1fe1; fanc_shift_num[51:0] = {frac_num[20:0],31'b0};end 70 | 52'b000000000000000000000000000000001???????????????????: begin frac_bin_val[12:0] = 13'h1fe0; fanc_shift_num[51:0] = {frac_num[19:0],32'b0};end 71 | 52'b0000000000000000000000000000000001??????????????????: begin frac_bin_val[12:0] = 13'h1fdf; fanc_shift_num[51:0] = {frac_num[18:0],33'b0};end 72 | 52'b00000000000000000000000000000000001?????????????????: begin frac_bin_val[12:0] = 13'h1fde; fanc_shift_num[51:0] = {frac_num[17:0],34'b0};end 73 | 52'b000000000000000000000000000000000001????????????????: begin frac_bin_val[12:0] = 13'h1fdd; fanc_shift_num[51:0] = {frac_num[16:0],35'b0};end 74 | 52'b0000000000000000000000000000000000001???????????????: begin frac_bin_val[12:0] = 13'h1fdc; fanc_shift_num[51:0] = {frac_num[15:0],36'b0};end 75 | 52'b00000000000000000000000000000000000001??????????????: begin frac_bin_val[12:0] = 13'h1fdb; fanc_shift_num[51:0] = {frac_num[14:0],37'b0};end 76 | 52'b000000000000000000000000000000000000001?????????????: begin frac_bin_val[12:0] = 13'h1fda; fanc_shift_num[51:0] = {frac_num[13:0],38'b0};end 77 | 52'b0000000000000000000000000000000000000001????????????: begin frac_bin_val[12:0] = 13'h1fd9; fanc_shift_num[51:0] = {frac_num[12:0],39'b0};end 78 | 52'b00000000000000000000000000000000000000001???????????: begin frac_bin_val[12:0] = 13'h1fd8; fanc_shift_num[51:0] = {frac_num[11:0],40'b0};end 79 | 52'b000000000000000000000000000000000000000001??????????: begin frac_bin_val[12:0] = 13'h1fd7; fanc_shift_num[51:0] = {frac_num[10:0],41'b0};end 80 | 52'b0000000000000000000000000000000000000000001?????????: begin frac_bin_val[12:0] = 13'h1fd6; fanc_shift_num[51:0] = {frac_num[9:0],42'b0};end 81 | 52'b00000000000000000000000000000000000000000001????????: begin frac_bin_val[12:0] = 13'h1fd5; fanc_shift_num[51:0] = {frac_num[8:0],43'b0};end 82 | 52'b000000000000000000000000000000000000000000001???????: begin frac_bin_val[12:0] = 13'h1fd4; fanc_shift_num[51:0] = {frac_num[7:0],44'b0};end 83 | 52'b0000000000000000000000000000000000000000000001??????: begin frac_bin_val[12:0] = 13'h1fd3; fanc_shift_num[51:0] = {frac_num[6:0],45'b0};end 84 | 52'b00000000000000000000000000000000000000000000001?????: begin frac_bin_val[12:0] = 13'h1fd2; fanc_shift_num[51:0] = {frac_num[5:0],46'b0};end 85 | 52'b000000000000000000000000000000000000000000000001????: begin frac_bin_val[12:0] = 13'h1fd1; fanc_shift_num[51:0] = {frac_num[4:0],47'b0};end 86 | 52'b0000000000000000000000000000000000000000000000001???: begin frac_bin_val[12:0] = 13'h1fd0; fanc_shift_num[51:0] = {frac_num[3:0],48'b0};end 87 | 52'b00000000000000000000000000000000000000000000000001??: begin frac_bin_val[12:0] = 13'h1fcf; fanc_shift_num[51:0] = {frac_num[2:0],49'b0};end 88 | 52'b000000000000000000000000000000000000000000000000001?: begin frac_bin_val[12:0] = 13'h1fce; fanc_shift_num[51:0] = {frac_num[1:0],50'b0};end 89 | 52'b0000000000000000000000000000000000000000000000000001: begin frac_bin_val[12:0] = 13'h1fcd; fanc_shift_num[51:0] = {frac_num[0:0],51'b0};end 90 | 52'b0000000000000000000000000000000000000000000000000000: begin frac_bin_val[12:0] = 13'h1fcc; fanc_shift_num[51:0] = {52'b0};end 91 | default:begin frac_bin_val[12:0] = 13'h000; fanc_shift_num[51:0] = {52'b0};end 92 | endcase 93 | // &CombEnd; @83 94 | end 95 | 96 | // &ModuleEnd; @85 97 | endmodule 98 | 99 | 100 | -------------------------------------------------------------------------------- /vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // &Depend("cpu_cfig.h"); @22 17 | // &ModuleBeg; @23 18 | module ct_vfdsu_scalar_dp( 19 | cp0_vfpu_icg_en, 20 | cp0_yy_clk_en, 21 | cpurst_b, 22 | dp_vfdsu_ex1_pipex_dst_ereg, 23 | dp_vfdsu_ex1_pipex_dst_vreg, 24 | dp_vfdsu_ex1_pipex_iid, 25 | dp_vfdsu_ex1_pipex_imm0, 26 | dp_vfdsu_ex1_pipex_srcf0, 27 | dp_vfdsu_ex1_pipex_srcf1, 28 | ex1_data_clk, 29 | ex1_div, 30 | ex1_double, 31 | ex1_pipedown, 32 | ex1_scalar, 33 | ex1_half, 34 | ex1_bfloat, 35 | ex1_single, 36 | ex1_sqrt, 37 | ex1_src0, 38 | ex1_src1, 39 | ex1_static_rm, 40 | ex2_data_clk, 41 | ex2_pipedown, 42 | ex3_data_clk, 43 | ex3_pipedown, 44 | ex4_out_expt, 45 | ex4_out_result, 46 | forever_cpuclk, 47 | idu_vfpu_rf_pipex_func, 48 | idu_vfpu_rf_pipex_gateclk_sel, 49 | pad_yy_icg_scan_en, 50 | pipex_dp_vfdsu_ereg, 51 | pipex_dp_vfdsu_ereg_data, 52 | pipex_dp_vfdsu_freg_data, 53 | pipex_dp_vfdsu_vreg, 54 | vfdsu_ex2_double, 55 | vfdsu_ex2_single, 56 | vfdsu_ex2_half, 57 | vfdsu_ex2_bfloat 58 | ); 59 | 60 | // &Ports; @24 61 | input cp0_vfpu_icg_en; 62 | input cp0_yy_clk_en; 63 | input cpurst_b; 64 | input [4 :0] dp_vfdsu_ex1_pipex_dst_ereg; 65 | input [6 :0] dp_vfdsu_ex1_pipex_dst_vreg; 66 | input [6 :0] dp_vfdsu_ex1_pipex_iid; 67 | input [2 :0] dp_vfdsu_ex1_pipex_imm0; 68 | input [63:0] dp_vfdsu_ex1_pipex_srcf0; 69 | input [63:0] dp_vfdsu_ex1_pipex_srcf1; 70 | input ex1_data_clk; 71 | input ex1_pipedown; 72 | input ex2_data_clk; 73 | input ex2_pipedown; 74 | input ex3_data_clk; 75 | input ex3_pipedown; 76 | input [4 :0] ex4_out_expt; 77 | input [63:0] ex4_out_result; 78 | input forever_cpuclk; 79 | input [19:0] idu_vfpu_rf_pipex_func; 80 | input idu_vfpu_rf_pipex_gateclk_sel; 81 | input pad_yy_icg_scan_en; 82 | output ex1_div; 83 | output ex1_double; 84 | output ex1_scalar; 85 | output ex1_single; 86 | output ex1_half; 87 | output ex1_bfloat; 88 | output ex1_sqrt; 89 | output [63:0] ex1_src0; 90 | output [63:0] ex1_src1; 91 | output [2 :0] ex1_static_rm; 92 | output [4 :0] pipex_dp_vfdsu_ereg; 93 | output [4 :0] pipex_dp_vfdsu_ereg_data; 94 | output [63:0] pipex_dp_vfdsu_freg_data; 95 | output [6 :0] pipex_dp_vfdsu_vreg; 96 | output vfdsu_ex2_double; 97 | output vfdsu_ex2_single; 98 | output vfdsu_ex2_half; 99 | output vfdsu_ex2_bfloat; 100 | 101 | // &Regs; @25 102 | reg ex1_div; 103 | reg ex1_double; 104 | reg ex1_single; 105 | reg ex1_half; 106 | reg ex1_bfloat; 107 | reg ex1_sqrt; 108 | reg vfdsu_ex2_div; 109 | reg vfdsu_ex2_double; 110 | reg [4 :0] vfdsu_ex2_dst_ereg; 111 | reg [6 :0] vfdsu_ex2_dst_vreg; 112 | reg [6 :0] vfdsu_ex2_iid; 113 | reg vfdsu_ex2_single; 114 | reg vfdsu_ex2_half; 115 | reg vfdsu_ex2_bfloat; 116 | reg vfdsu_ex2_sqrt; 117 | reg [4 :0] vfdsu_ex3_dst_ereg; 118 | reg [6 :0] vfdsu_ex3_dst_vreg; 119 | reg [6 :0] vfdsu_ex3_iid; 120 | reg [4 :0] vfdsu_ex4_dst_ereg; 121 | reg [6 :0] vfdsu_ex4_dst_vreg; 122 | reg [6 :0] vfdsu_ex4_iid; 123 | 124 | // &Wires; @26 125 | wire cp0_vfpu_icg_en; 126 | wire cp0_yy_clk_en; 127 | wire cpurst_b; 128 | wire [4 :0] dp_vfdsu_ex1_pipex_dst_ereg; 129 | wire [6 :0] dp_vfdsu_ex1_pipex_dst_vreg; 130 | wire [6 :0] dp_vfdsu_ex1_pipex_iid; 131 | wire [2 :0] dp_vfdsu_ex1_pipex_imm0; 132 | wire [63:0] dp_vfdsu_ex1_pipex_srcf0; 133 | wire [63:0] dp_vfdsu_ex1_pipex_srcf1; 134 | wire ex1_data_clk; 135 | wire ex1_pipedown; 136 | wire ex1_scalar; 137 | wire [63:0] ex1_src0; 138 | wire [63:0] ex1_src1; 139 | wire [2 :0] ex1_static_rm; 140 | wire ex2_data_clk; 141 | wire ex2_pipedown; 142 | wire ex3_data_clk; 143 | wire ex3_pipedown; 144 | wire [4 :0] ex4_out_expt; 145 | wire [63:0] ex4_out_result; 146 | wire forever_cpuclk; 147 | wire [19:0] idu_vfpu_rf_pipex_func; 148 | wire idu_vfpu_rf_pipex_gateclk_sel; 149 | wire pad_yy_icg_scan_en; 150 | wire [4 :0] pipex_dp_vfdsu_ereg; 151 | wire [4 :0] pipex_dp_vfdsu_ereg_data; 152 | wire [63:0] pipex_dp_vfdsu_freg_data; 153 | wire [6 :0] pipex_dp_vfdsu_vreg; 154 | wire vfdsu_sew_clk; 155 | wire vfdsu_sew_clk_en; 156 | 157 | 158 | //========================================================== 159 | // EX1 Stage Control Signal 160 | //========================================================== 161 | // &Force("bus","idu_vfpu_rf_pipex_func",19,0); @31 162 | //assign func[19:0] = dp_vfdsu_ex1_pipex_func[19:0]; 163 | // &Instance("gated_clk_cell","x_vfdsu_sew_clk"); @33 164 | gated_clk_cell x_vfdsu_sew_clk ( 165 | .clk_in (forever_cpuclk ), 166 | .clk_out (vfdsu_sew_clk ), 167 | .external_en (1'b0 ), 168 | .global_en (cp0_yy_clk_en ), 169 | .local_en (vfdsu_sew_clk_en ), 170 | .module_en (cp0_vfpu_icg_en ), 171 | .pad_yy_icg_scan_en (pad_yy_icg_scan_en) 172 | ); 173 | 174 | // &Connect( .clk_in (forever_cpuclk), @34 175 | // .clk_out (vfdsu_sew_clk),//Out Clock @35 176 | // .external_en (1'b0), @36 177 | // .global_en (cp0_yy_clk_en), @37 178 | // .local_en (vfdsu_sew_clk_en),//Local Condition @38 179 | // .module_en (cp0_vfpu_icg_en) @39 180 | // ); @40 181 | assign vfdsu_sew_clk_en = idu_vfpu_rf_pipex_gateclk_sel; 182 | always @(posedge vfdsu_sew_clk or negedge cpurst_b) 183 | begin 184 | if(!cpurst_b) 185 | begin 186 | ex1_div <= 1'b0; 187 | ex1_sqrt <= 1'b0; 188 | ex1_double <= 1'b0; 189 | ex1_single <= 1'b0; 190 | ex1_half <= 1'b0; 191 | ex1_bfloat <= 1'b0; 192 | end 193 | else if(idu_vfpu_rf_pipex_gateclk_sel) 194 | begin 195 | ex1_div <= idu_vfpu_rf_pipex_func[0]; 196 | ex1_sqrt <= idu_vfpu_rf_pipex_func[1]; 197 | ex1_double <= idu_vfpu_rf_pipex_func[16]; 198 | ex1_single <= idu_vfpu_rf_pipex_func[15]; 199 | ex1_half <= idu_vfpu_rf_pipex_func[14]; 200 | ex1_bfloat <= idu_vfpu_rf_pipex_func[13]; 201 | end 202 | end 203 | assign ex1_scalar = 1'b1; 204 | assign ex1_static_rm[2:0] = dp_vfdsu_ex1_pipex_imm0[2:0]; 205 | // &Force("output","ex1_div"); @61 206 | // &Force("output","ex1_sqrt"); @62 207 | // &Force("output","ex1_double"); @63 208 | // &Force("output","ex1_single"); @64 209 | 210 | assign ex1_src0[63:0] = dp_vfdsu_ex1_pipex_srcf0[63:0]; 211 | assign ex1_src1[63:0] = dp_vfdsu_ex1_pipex_srcf1[63:0]; 212 | 213 | 214 | always @(posedge ex1_data_clk or negedge cpurst_b) 215 | begin 216 | if(!cpurst_b) 217 | begin 218 | vfdsu_ex2_dst_ereg[4:0] <= 5'b0; 219 | vfdsu_ex2_dst_vreg[6:0] <= 7'b0; 220 | vfdsu_ex2_iid[6:0] <= 7'b0; 221 | vfdsu_ex2_double <= 1'b0; 222 | vfdsu_ex2_single <= 1'b0; 223 | vfdsu_ex2_half <= 1'b0; 224 | vfdsu_ex2_bfloat <= 1'b0; 225 | vfdsu_ex2_div <= 1'b0; 226 | vfdsu_ex2_sqrt <= 1'b0; 227 | end 228 | else if(ex1_pipedown) 229 | begin 230 | vfdsu_ex2_dst_ereg[4:0] <= dp_vfdsu_ex1_pipex_dst_ereg[4:0]; 231 | vfdsu_ex2_dst_vreg[6:0] <= dp_vfdsu_ex1_pipex_dst_vreg[6:0]; 232 | vfdsu_ex2_iid[6:0] <= dp_vfdsu_ex1_pipex_iid[6:0]; 233 | vfdsu_ex2_double <= ex1_double; 234 | vfdsu_ex2_single <= ex1_single; 235 | vfdsu_ex2_half <= ex1_half; 236 | vfdsu_ex2_bfloat <= ex1_bfloat; 237 | vfdsu_ex2_div <= ex1_div; 238 | vfdsu_ex2_sqrt <= ex1_sqrt; 239 | end 240 | else 241 | begin 242 | vfdsu_ex2_dst_ereg[4:0] <= vfdsu_ex2_dst_ereg[4:0]; 243 | vfdsu_ex2_dst_vreg[6:0] <= vfdsu_ex2_dst_vreg[6:0]; 244 | vfdsu_ex2_iid[6:0] <= vfdsu_ex2_iid[6:0]; 245 | vfdsu_ex2_double <= vfdsu_ex2_double; 246 | vfdsu_ex2_single <= vfdsu_ex2_single; 247 | vfdsu_ex2_half <= ex1_half; 248 | vfdsu_ex2_bfloat <= ex1_bfloat; 249 | vfdsu_ex2_div <= vfdsu_ex2_div; 250 | vfdsu_ex2_sqrt <= vfdsu_ex2_sqrt; 251 | end 252 | end 253 | // &Force("output","vfdsu_ex2_double"); @103 254 | // &Force("output","vfdsu_ex2_single"); @104 255 | // //&Force("output","vfdsu_ex2_div"); @105 256 | // //&Force("output","vfdsu_ex2_sqrt"); @106 257 | 258 | 259 | always @(posedge ex2_data_clk or negedge cpurst_b) 260 | begin 261 | if(!cpurst_b) 262 | begin 263 | vfdsu_ex3_dst_ereg[4:0] <= 5'b0; 264 | vfdsu_ex3_dst_vreg[6:0] <= 7'b0; 265 | vfdsu_ex3_iid[6:0] <= 7'b0; 266 | // vfdsu_ex3_double <= 1'b0; 267 | // vfdsu_ex3_single <= 1'b0; 268 | // vfdsu_ex3_div <= 1'b0; 269 | // vfdsu_ex3_sqrt <= 1'b0; 270 | end 271 | else if(ex2_pipedown) 272 | begin 273 | vfdsu_ex3_dst_ereg[4:0] <= vfdsu_ex2_dst_ereg[4:0]; 274 | vfdsu_ex3_dst_vreg[6:0] <= vfdsu_ex2_dst_vreg[6:0]; 275 | vfdsu_ex3_iid[6:0] <= vfdsu_ex2_iid[6:0]; 276 | // vfdsu_ex3_double <= vfdsu_ex2_double; 277 | // vfdsu_ex3_single <= vfdsu_ex2_single; 278 | // vfdsu_ex3_div <= vfdsu_ex2_div; 279 | // vfdsu_ex3_sqrt <= vfdsu_ex2_sqrt; 280 | end 281 | else 282 | begin 283 | vfdsu_ex3_dst_ereg[4:0] <= vfdsu_ex3_dst_ereg[4:0]; 284 | vfdsu_ex3_dst_vreg[6:0] <= vfdsu_ex3_dst_vreg[6:0]; 285 | vfdsu_ex3_iid[6:0] <= vfdsu_ex3_iid[6:0]; 286 | // vfdsu_ex3_double <= vfdsu_ex3_double; 287 | // vfdsu_ex3_single <= vfdsu_ex3_single; 288 | // vfdsu_ex3_div <= vfdsu_ex3_div; 289 | // vfdsu_ex3_sqrt <= vfdsu_ex3_sqrt; 290 | end 291 | end 292 | // //&Force("output","vfdsu_ex3_double"); @142 293 | // //&Force("output","vfdsu_ex3_single"); @143 294 | 295 | always @(posedge ex3_data_clk or negedge cpurst_b) 296 | begin 297 | if(!cpurst_b) 298 | begin 299 | vfdsu_ex4_dst_ereg[4:0] <= 5'b0; 300 | vfdsu_ex4_dst_vreg[6:0] <= 7'b0; 301 | vfdsu_ex4_iid[6:0] <= 7'b0; 302 | // vfdsu_ex4_double <= 1'b0; 303 | // vfdsu_ex4_single <= 1'b0; 304 | // vfdsu_ex4_div <= 1'b0; 305 | // vfdsu_ex4_sqrt <= 1'b0; 306 | end 307 | else if(ex3_pipedown) 308 | begin 309 | vfdsu_ex4_dst_ereg[4:0] <= vfdsu_ex3_dst_ereg[4:0]; 310 | vfdsu_ex4_dst_vreg[6:0] <= vfdsu_ex3_dst_vreg[6:0]; 311 | vfdsu_ex4_iid[6:0] <= vfdsu_ex3_iid[6:0]; 312 | // vfdsu_ex4_double <= vfdsu_ex3_double; 313 | // vfdsu_ex4_single <= vfdsu_ex3_single; 314 | // vfdsu_ex4_div <= vfdsu_ex3_div; 315 | // vfdsu_ex4_sqrt <= vfdsu_ex3_sqrt; 316 | end 317 | else 318 | begin 319 | vfdsu_ex4_dst_ereg[4:0] <= vfdsu_ex4_dst_ereg[4:0]; 320 | vfdsu_ex4_dst_vreg[6:0] <= vfdsu_ex4_dst_vreg[6:0]; 321 | vfdsu_ex4_iid[6:0] <= vfdsu_ex4_iid[6:0]; 322 | // vfdsu_ex4_double <= vfdsu_ex4_double; 323 | // vfdsu_ex4_single <= vfdsu_ex4_single; 324 | // vfdsu_ex4_div <= vfdsu_ex4_div; 325 | // vfdsu_ex4_sqrt <= vfdsu_ex4_sqrt; 326 | end 327 | end 328 | // //&Force("output","vfdsu_ex4_double"); @178 329 | // //&Force("output","vfdsu_ex4_single"); @179 330 | 331 | 332 | assign pipex_dp_vfdsu_ereg_data[4:0] = ex4_out_expt[4:0]; 333 | assign pipex_dp_vfdsu_freg_data[63:0] = ex4_out_result[63:0]; 334 | assign pipex_dp_vfdsu_ereg[4:0] = vfdsu_ex4_dst_ereg[4:0]; 335 | assign pipex_dp_vfdsu_vreg[6:0] = vfdsu_ex4_dst_vreg[6:0]; 336 | 337 | 338 | 339 | 340 | 341 | 342 | // &ModuleEnd; @192 343 | endmodule 344 | 345 | 346 | -------------------------------------------------------------------------------- /vendor/openc910/LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /vendor/openc910/README.md: -------------------------------------------------------------------------------- 1 | # IP Readme 2 | 3 | Welcome to C910! Some key directories are shown below. 4 | ``` 5 | |--C910_RTL_FACTORY/ 6 | |--gen_rtl/ ## Verilog source code of C910 7 | |--setup/ ## Script to set the environment variables 8 | |--smart_run/ ## RTL simulation environment 9 | |--impl/ ## SDC file, scripts and file lists for implementation 10 | |--logical/ ## SoC demo and test bench to run the simulation 11 | |--setup/ ## GNU tool chain setting 12 | |--tests/ ## Test driver and test cases 13 | |--work/ ## Working directory for builds 14 | |--Makefile ## Makefile for building and running sim targets 15 | |--doc/ ## The user and integration manual of C910 16 | ``` 17 | 18 | 19 | ## Usage 20 | 21 | Step1: Get Started 22 | 23 | ``` 24 | $ cd C910_RTL_FACTORY 25 | $ source setup/setup.csh 26 | $ cd ../smart_run 27 | $ make help 28 | To gain more information about how to use smart testbench. 29 | ``` 30 | 31 | Step2: Download and install C/C++ Compiler 32 | 33 | ``` 34 | You can download the GNU tool chain compiled by T-HEAD from the url below: 35 | https://occ.t-head.cn/community/download?id=3948120165480468480 36 | 37 | $ cd ./smart_run 38 | GNU tool chain (specific riscv version) must be installed and specified before 39 | compiling *.c/*.v tests of the smart environment. Please refer to the following 40 | setup file about how to specify it: 41 | ./smart_run/setup/example_setup.csh 42 | ``` 43 | 44 | 45 | ## Notes 46 | 47 | ``` 48 | The testbench supports Verilator(version is better newer than 4.215),iverilog, vcs and irun to run simulation and you can use Gtkwave or verdi 49 | to open the waveform under ./smart_run/work/ directory. 50 | 51 | You can get the debugger, IDE and SDK from the url:https://occ.t-head.cn/community/download?id=575997419775328256 52 | ``` 53 | 54 | 55 | ## Discussion 56 | If you are interested in participating in discussions or improving the "openXuantie" cores, you can scan the DingDing QR code below to join the discussion group. 57 | 58 | 59 | 60 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 61 | 62 | Licensed under the Apache License, Version 2.0 (the "License"); 63 | you may not use this file except in compliance with the License. 64 | You may obtain a copy of the License at 65 | 66 | http://www.apache.org/licenses/LICENSE-2.0 67 | 68 | Unless required by applicable law or agreed to in writing, software 69 | distributed under the License is distributed on an "AS IS" BASIS, 70 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 71 | See the License for the specific language governing permissions and 72 | limitations under the License. 73 | 74 | */ 75 | -------------------------------------------------------------------------------- /vendor/opene906.lock.hjson: -------------------------------------------------------------------------------- 1 | // Copyright lowRISC contributors. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | 5 | // This file is generated by the util/vendor script. Please do not modify it 6 | // manually. 7 | 8 | { 9 | upstream: 10 | { 11 | url: https://github.com/T-head-Semi/opene906 12 | rev: d45f0634d6a3638f39984899b0adb0b69726646e 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /vendor/opene906.vendor.hjson: -------------------------------------------------------------------------------- 1 | // Copyright 2023 ETH Zurich and University of Bologna. 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. 3 | // SPDX-License-Identifier: Apache-2.0 4 | { 5 | name: "opene906", 6 | target_dir: "opene906" 7 | 8 | upstream: { 9 | url: "https://github.com/T-head-Semi/opene906" 10 | rev: "d45f0634d6a3638f39984899b0adb0b69726646e" 11 | } 12 | 13 | patch_dir: "patches/opene906" 14 | 15 | exclude_from_upstream: [ 16 | "doc", 17 | "smart_run", 18 | "E906_RTL_FACTORY/gen_rtl/biu", 19 | "E906_RTL_FACTORY/gen_rtl/bmu", 20 | "E906_RTL_FACTORY/gen_rtl/biu", 21 | "E906_RTL_FACTORY/gen_rtl/bmu", 22 | "E906_RTL_FACTORY/gen_rtl/clic", 23 | "E906_RTL_FACTORY/gen_rtl/clk/rtl/pa_clkrst_top.v", 24 | "E906_RTL_FACTORY/gen_rtl/clk/rtl/pa_clk_top.v", 25 | "E906_RTL_FACTORY/gen_rtl/clint", 26 | "E906_RTL_FACTORY/gen_rtl/common", 27 | "E906_RTL_FACTORY/gen_rtl/cp0", 28 | "E906_RTL_FACTORY/gen_rtl/cpu", 29 | "E906_RTL_FACTORY/gen_rtl/dtu", 30 | "E906_RTL_FACTORY/gen_rtl/falu", 31 | "E906_RTL_FACTORY/gen_rtl/filelists", 32 | "E906_RTL_FACTORY/gen_rtl/fmau", 33 | "E906_RTL_FACTORY/gen_rtl/fpga", 34 | "E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_ctrl.v", 35 | "E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_top.v", 36 | "E906_RTL_FACTORY/gen_rtl/idu", 37 | "E906_RTL_FACTORY/gen_rtl/ifu", 38 | "E906_RTL_FACTORY/gen_rtl/iu", 39 | "E906_RTL_FACTORY/gen_rtl/lsu", 40 | "E906_RTL_FACTORY/gen_rtl/pmp", 41 | "E906_RTL_FACTORY/gen_rtl/pmu", 42 | "E906_RTL_FACTORY/gen_rtl/rst", 43 | "E906_RTL_FACTORY/gen_rtl/rtu", 44 | "E906_RTL_FACTORY/gen_rtl/sysmap", 45 | "E906_RTL_FACTORY/gen_rtl/tcipif", 46 | "E906_RTL_FACTORY/gen_rtl/tdt", 47 | "E906_RTL_FACTORY/setup" 48 | ] 49 | 50 | } 51 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module gated_clk_cell( 17 | clk_in, 18 | global_en, 19 | module_en, 20 | local_en, 21 | external_en, 22 | pad_yy_icg_scan_en, 23 | clk_out 24 | ); 25 | 26 | input clk_in; 27 | input global_en; 28 | input module_en; 29 | input local_en; 30 | input external_en; 31 | input pad_yy_icg_scan_en; 32 | output clk_out; 33 | 34 | wire clk_en_bf_latch; 35 | wire SE; 36 | 37 | assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ; 38 | 39 | // SE driven from primary input, held constant 40 | assign SE = pad_yy_icg_scan_en; 41 | 42 | // // &Connect( .clk_in (clk_in), @50 43 | // // .SE (SE), @51 44 | // // .external_en (clk_en_bf_latch), @52 45 | // // .clk_out (clk_out) @53 46 | // // ) ; @54 47 | 48 | assign clk_out = clk_in; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // &ModuleBeg; @23 17 | module pa_fdsu_ff1( 18 | fanc_shift_num, 19 | frac_bin_val, 20 | frac_num 21 | ); 22 | 23 | // &Ports; @24 24 | input [51:0] frac_num; 25 | output [51:0] fanc_shift_num; 26 | output [12:0] frac_bin_val; 27 | 28 | // &Regs; @25 29 | reg [51:0] fanc_shift_num; 30 | reg [12:0] frac_bin_val; 31 | 32 | // &Wires; @26 33 | wire [51:0] frac_num; 34 | 35 | 36 | // &CombBeg; @28 37 | always @( frac_num[51:0]) 38 | begin 39 | casez(frac_num[51:0]) 40 | 52'b1???????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h0; 41 | 52'b01??????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1fff; 42 | 52'b001?????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffe; 43 | 52'b0001????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffd; 44 | 52'b00001???????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffc; 45 | 52'b000001??????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffb; 46 | 52'b0000001?????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffa; 47 | 52'b00000001????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff9; 48 | 52'b000000001???????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff8; 49 | 52'b0000000001??????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff7; 50 | 52'b00000000001?????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff6; 51 | 52'b000000000001????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff5; 52 | 52'b0000000000001???????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff4; 53 | 52'b00000000000001??????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff3; 54 | 52'b000000000000001?????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff2; 55 | 52'b0000000000000001????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff1; 56 | 52'b00000000000000001???????????????????????????????????: frac_bin_val[12:0] = 13'h1ff0; 57 | 52'b000000000000000001??????????????????????????????????: frac_bin_val[12:0] = 13'h1fef; 58 | 52'b0000000000000000001?????????????????????????????????: frac_bin_val[12:0] = 13'h1fee; 59 | 52'b00000000000000000001????????????????????????????????: frac_bin_val[12:0] = 13'h1fed; 60 | 52'b000000000000000000001???????????????????????????????: frac_bin_val[12:0] = 13'h1fec; 61 | 52'b0000000000000000000001??????????????????????????????: frac_bin_val[12:0] = 13'h1feb; 62 | 52'b00000000000000000000001?????????????????????????????: frac_bin_val[12:0] = 13'h1fea; 63 | 52'b000000000000000000000001????????????????????????????: frac_bin_val[12:0] = 13'h1fe9; 64 | 52'b0000000000000000000000001???????????????????????????: frac_bin_val[12:0] = 13'h1fe8; 65 | 52'b00000000000000000000000001??????????????????????????: frac_bin_val[12:0] = 13'h1fe7; 66 | 52'b000000000000000000000000001?????????????????????????: frac_bin_val[12:0] = 13'h1fe6; 67 | 52'b0000000000000000000000000001????????????????????????: frac_bin_val[12:0] = 13'h1fe5; 68 | 52'b00000000000000000000000000001???????????????????????: frac_bin_val[12:0] = 13'h1fe4; 69 | 52'b000000000000000000000000000001??????????????????????: frac_bin_val[12:0] = 13'h1fe3; 70 | 52'b0000000000000000000000000000001?????????????????????: frac_bin_val[12:0] = 13'h1fe2; 71 | 52'b00000000000000000000000000000001????????????????????: frac_bin_val[12:0] = 13'h1fe1; 72 | 52'b000000000000000000000000000000001???????????????????: frac_bin_val[12:0] = 13'h1fe0; 73 | 52'b0000000000000000000000000000000001??????????????????: frac_bin_val[12:0] = 13'h1fdf; 74 | 52'b00000000000000000000000000000000001?????????????????: frac_bin_val[12:0] = 13'h1fde; 75 | 52'b000000000000000000000000000000000001????????????????: frac_bin_val[12:0] = 13'h1fdd; 76 | 52'b0000000000000000000000000000000000001???????????????: frac_bin_val[12:0] = 13'h1fdc; 77 | 52'b00000000000000000000000000000000000001??????????????: frac_bin_val[12:0] = 13'h1fdb; 78 | 52'b000000000000000000000000000000000000001?????????????: frac_bin_val[12:0] = 13'h1fda; 79 | 52'b0000000000000000000000000000000000000001????????????: frac_bin_val[12:0] = 13'h1fd9; 80 | 52'b00000000000000000000000000000000000000001???????????: frac_bin_val[12:0] = 13'h1fd8; 81 | 52'b000000000000000000000000000000000000000001??????????: frac_bin_val[12:0] = 13'h1fd7; 82 | 52'b0000000000000000000000000000000000000000001?????????: frac_bin_val[12:0] = 13'h1fd6; 83 | 52'b00000000000000000000000000000000000000000001????????: frac_bin_val[12:0] = 13'h1fd5; 84 | 52'b000000000000000000000000000000000000000000001???????: frac_bin_val[12:0] = 13'h1fd4; 85 | 52'b0000000000000000000000000000000000000000000001??????: frac_bin_val[12:0] = 13'h1fd3; 86 | 52'b00000000000000000000000000000000000000000000001?????: frac_bin_val[12:0] = 13'h1fd2; 87 | 52'b000000000000000000000000000000000000000000000001????: frac_bin_val[12:0] = 13'h1fd1; 88 | 52'b0000000000000000000000000000000000000000000000001???: frac_bin_val[12:0] = 13'h1fd0; 89 | 52'b00000000000000000000000000000000000000000000000001??: frac_bin_val[12:0] = 13'h1fcf; 90 | 52'b000000000000000000000000000000000000000000000000001?: frac_bin_val[12:0] = 13'h1fce; 91 | 52'b0000000000000000000000000000000000000000000000000001: frac_bin_val[12:0] = 13'h1fcd; 92 | 52'b0000000000000000000000000000000000000000000000000000: frac_bin_val[12:0] = 13'h1fcc; 93 | default : frac_bin_val[12:0] = 13'h000; 94 | endcase 95 | // &CombEnd; @85 96 | end 97 | 98 | // &CombBeg; @87 99 | always @( frac_num[51:0]) 100 | begin 101 | casez(frac_num[51:0]) 102 | 52'b1???????????????????????????????????????????????????: fanc_shift_num[51:0] = frac_num[51:0]; 103 | 52'b01??????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[50:0],1'b0}; 104 | 52'b001?????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[49:0],2'b0}; 105 | 52'b0001????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[48:0],3'b0}; 106 | 52'b00001???????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[47:0],4'b0}; 107 | 52'b000001??????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[46:0],5'b0}; 108 | 52'b0000001?????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[45:0],6'b0}; 109 | 52'b00000001????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[44:0],7'b0}; 110 | 52'b000000001???????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[43:0],8'b0}; 111 | 52'b0000000001??????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[42:0],9'b0}; 112 | 52'b00000000001?????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[41:0],10'b0}; 113 | 52'b000000000001????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[40:0],11'b0}; 114 | 52'b0000000000001???????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[39:0],12'b0}; 115 | 52'b00000000000001??????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[38:0],13'b0}; 116 | 52'b000000000000001?????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[37:0],14'b0}; 117 | 52'b0000000000000001????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[36:0],15'b0}; 118 | 52'b00000000000000001???????????????????????????????????: fanc_shift_num[51:0] = {frac_num[35:0],16'b0}; 119 | 52'b000000000000000001??????????????????????????????????: fanc_shift_num[51:0] = {frac_num[34:0],17'b0}; 120 | 52'b0000000000000000001?????????????????????????????????: fanc_shift_num[51:0] = {frac_num[33:0],18'b0}; 121 | 52'b00000000000000000001????????????????????????????????: fanc_shift_num[51:0] = {frac_num[32:0],19'b0}; 122 | 52'b000000000000000000001???????????????????????????????: fanc_shift_num[51:0] = {frac_num[31:0],20'b0}; 123 | 52'b0000000000000000000001??????????????????????????????: fanc_shift_num[51:0] = {frac_num[30:0],21'b0}; 124 | 52'b00000000000000000000001?????????????????????????????: fanc_shift_num[51:0] = {frac_num[29:0],22'b0}; 125 | 52'b000000000000000000000001????????????????????????????: fanc_shift_num[51:0] = {frac_num[28:0],23'b0}; 126 | 52'b0000000000000000000000001???????????????????????????: fanc_shift_num[51:0] = {frac_num[27:0],24'b0}; 127 | 52'b00000000000000000000000001??????????????????????????: fanc_shift_num[51:0] = {frac_num[26:0],25'b0}; 128 | 52'b000000000000000000000000001?????????????????????????: fanc_shift_num[51:0] = {frac_num[25:0],26'b0}; 129 | 52'b0000000000000000000000000001????????????????????????: fanc_shift_num[51:0] = {frac_num[24:0],27'b0}; 130 | 52'b00000000000000000000000000001???????????????????????: fanc_shift_num[51:0] = {frac_num[23:0],28'b0}; 131 | 52'b000000000000000000000000000001??????????????????????: fanc_shift_num[51:0] = {frac_num[22:0],29'b0}; 132 | 52'b0000000000000000000000000000001?????????????????????: fanc_shift_num[51:0] = {frac_num[21:0],30'b0}; 133 | 52'b00000000000000000000000000000001????????????????????: fanc_shift_num[51:0] = {frac_num[20:0],31'b0}; 134 | 52'b000000000000000000000000000000001???????????????????: fanc_shift_num[51:0] = {frac_num[19:0],32'b0}; 135 | 52'b0000000000000000000000000000000001??????????????????: fanc_shift_num[51:0] = {frac_num[18:0],33'b0}; 136 | 52'b00000000000000000000000000000000001?????????????????: fanc_shift_num[51:0] = {frac_num[17:0],34'b0}; 137 | 52'b000000000000000000000000000000000001????????????????: fanc_shift_num[51:0] = {frac_num[16:0],35'b0}; 138 | 52'b0000000000000000000000000000000000001???????????????: fanc_shift_num[51:0] = {frac_num[15:0],36'b0}; 139 | 52'b00000000000000000000000000000000000001??????????????: fanc_shift_num[51:0] = {frac_num[14:0],37'b0}; 140 | 52'b000000000000000000000000000000000000001?????????????: fanc_shift_num[51:0] = {frac_num[13:0],38'b0}; 141 | 52'b0000000000000000000000000000000000000001????????????: fanc_shift_num[51:0] = {frac_num[12:0],39'b0}; 142 | 52'b00000000000000000000000000000000000000001???????????: fanc_shift_num[51:0] = {frac_num[11:0],40'b0}; 143 | 52'b000000000000000000000000000000000000000001??????????: fanc_shift_num[51:0] = {frac_num[10:0],41'b0}; 144 | 52'b0000000000000000000000000000000000000000001?????????: fanc_shift_num[51:0] = {frac_num[9:0],42'b0}; 145 | 52'b00000000000000000000000000000000000000000001????????: fanc_shift_num[51:0] = {frac_num[8:0],43'b0}; 146 | 52'b000000000000000000000000000000000000000000001???????: fanc_shift_num[51:0] = {frac_num[7:0],44'b0}; 147 | 52'b0000000000000000000000000000000000000000000001??????: fanc_shift_num[51:0] = {frac_num[6:0],45'b0}; 148 | 52'b00000000000000000000000000000000000000000000001?????: fanc_shift_num[51:0] = {frac_num[5:0],46'b0}; 149 | 52'b000000000000000000000000000000000000000000000001????: fanc_shift_num[51:0] = {frac_num[4:0],47'b0}; 150 | 52'b0000000000000000000000000000000000000000000000001???: fanc_shift_num[51:0] = {frac_num[3:0],48'b0}; 151 | 52'b00000000000000000000000000000000000000000000000001??: fanc_shift_num[51:0] = {frac_num[2:0],49'b0}; 152 | 52'b000000000000000000000000000000000000000000000000001?: fanc_shift_num[51:0] = {frac_num[1:0],50'b0}; 153 | 52'b0000000000000000000000000000000000000000000000000001: fanc_shift_num[51:0] = {frac_num[0:0],51'b0}; 154 | 52'b0000000000000000000000000000000000000000000000000000: fanc_shift_num[51:0] = {52'b0}; 155 | default : fanc_shift_num[51:0] = {52'b0}; 156 | endcase 157 | // &CombEnd; @144 158 | end 159 | 160 | // &ModuleEnd; @146 161 | endmodule 162 | 163 | 164 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // &ModuleBeg; @23 17 | module pa_fdsu_pack_single( 18 | fdsu_ex4_denorm_to_tiny_frac, 19 | fdsu_ex4_frac, 20 | fdsu_ex4_nx, 21 | fdsu_ex4_potnt_norm, 22 | fdsu_ex4_result_nor, 23 | fdsu_frbus_data, 24 | fdsu_frbus_fflags, 25 | fdsu_frbus_freg, 26 | fdsu_yy_expnt_rst, 27 | fdsu_yy_of, 28 | fdsu_yy_of_rm_lfn, 29 | fdsu_yy_potnt_of, 30 | fdsu_yy_potnt_uf, 31 | fdsu_yy_result_inf, 32 | fdsu_yy_result_lfn, 33 | fdsu_yy_result_sign, 34 | fdsu_yy_rslt_denorm, 35 | fdsu_yy_uf, 36 | fdsu_yy_wb_freg 37 | ); 38 | 39 | // &Ports; @24 40 | input fdsu_ex4_denorm_to_tiny_frac; 41 | input [25:0] fdsu_ex4_frac; 42 | input fdsu_ex4_nx; 43 | input [1 :0] fdsu_ex4_potnt_norm; 44 | input fdsu_ex4_result_nor; 45 | input [9 :0] fdsu_yy_expnt_rst; 46 | input fdsu_yy_of; 47 | input fdsu_yy_of_rm_lfn; 48 | input fdsu_yy_potnt_of; 49 | input fdsu_yy_potnt_uf; 50 | input fdsu_yy_result_inf; 51 | input fdsu_yy_result_lfn; 52 | input fdsu_yy_result_sign; 53 | input fdsu_yy_rslt_denorm; 54 | input fdsu_yy_uf; 55 | input [4 :0] fdsu_yy_wb_freg; 56 | output [31:0] fdsu_frbus_data; 57 | output [4 :0] fdsu_frbus_fflags; 58 | output [4 :0] fdsu_frbus_freg; 59 | 60 | // &Regs; @25 61 | reg [22:0] ex4_frac_23; 62 | reg [31:0] ex4_result; 63 | reg [22:0] ex4_single_denorm_frac; 64 | reg [9 :0] expnt_add_op1; 65 | 66 | // &Wires; @26 67 | wire ex4_cor_nx; 68 | wire ex4_cor_uf; 69 | wire ex4_denorm_potnt_norm; 70 | wire [31:0] ex4_denorm_result; 71 | wire [9 :0] ex4_expnt_rst; 72 | wire [4 :0] ex4_expt; 73 | wire ex4_final_rst_norm; 74 | wire [25:0] ex4_frac; 75 | wire ex4_of_plus; 76 | wire ex4_result_inf; 77 | wire ex4_result_lfn; 78 | wire ex4_rslt_denorm; 79 | wire [31:0] ex4_rst_inf; 80 | wire [31:0] ex4_rst_lfn; 81 | wire ex4_rst_nor; 82 | wire [31:0] ex4_rst_norm; 83 | wire ex4_uf_plus; 84 | wire fdsu_ex4_denorm_to_tiny_frac; 85 | wire fdsu_ex4_dz; 86 | wire [9 :0] fdsu_ex4_expnt_rst; 87 | wire [25:0] fdsu_ex4_frac; 88 | wire fdsu_ex4_nv; 89 | wire fdsu_ex4_nx; 90 | wire fdsu_ex4_of; 91 | wire fdsu_ex4_of_rst_lfn; 92 | wire [1 :0] fdsu_ex4_potnt_norm; 93 | wire fdsu_ex4_potnt_of; 94 | wire fdsu_ex4_potnt_uf; 95 | wire fdsu_ex4_result_inf; 96 | wire fdsu_ex4_result_lfn; 97 | wire fdsu_ex4_result_nor; 98 | wire fdsu_ex4_result_sign; 99 | wire fdsu_ex4_rslt_denorm; 100 | wire fdsu_ex4_uf; 101 | wire [31:0] fdsu_frbus_data; 102 | wire [4 :0] fdsu_frbus_fflags; 103 | wire [4 :0] fdsu_frbus_freg; 104 | wire [9 :0] fdsu_yy_expnt_rst; 105 | wire fdsu_yy_of; 106 | wire fdsu_yy_of_rm_lfn; 107 | wire fdsu_yy_potnt_of; 108 | wire fdsu_yy_potnt_uf; 109 | wire fdsu_yy_result_inf; 110 | wire fdsu_yy_result_lfn; 111 | wire fdsu_yy_result_sign; 112 | wire fdsu_yy_rslt_denorm; 113 | wire fdsu_yy_uf; 114 | wire [4 :0] fdsu_yy_wb_freg; 115 | 116 | 117 | assign fdsu_ex4_result_sign = fdsu_yy_result_sign; 118 | assign fdsu_ex4_of_rst_lfn = fdsu_yy_of_rm_lfn; 119 | assign fdsu_ex4_result_inf = fdsu_yy_result_inf; 120 | assign fdsu_ex4_result_lfn = fdsu_yy_result_lfn; 121 | assign fdsu_ex4_of = fdsu_yy_of; 122 | assign fdsu_ex4_uf = fdsu_yy_uf; 123 | assign fdsu_ex4_potnt_of = fdsu_yy_potnt_of; 124 | assign fdsu_ex4_potnt_uf = fdsu_yy_potnt_uf; 125 | assign fdsu_ex4_nv = 1'b0; 126 | assign fdsu_ex4_dz = 1'b0; 127 | assign fdsu_ex4_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; 128 | assign fdsu_ex4_rslt_denorm = fdsu_yy_rslt_denorm; 129 | //============================EX4 STAGE===================== 130 | assign ex4_frac[25:0] = fdsu_ex4_frac[25:0]; 131 | //exponent adder 132 | // &CombBeg; @43 133 | always @( ex4_frac[25:24]) 134 | begin 135 | casez(ex4_frac[25:24]) 136 | 2'b00 : expnt_add_op1[9:0] = 10'h1ff; //the expnt sub 1 137 | 2'b01 : expnt_add_op1[9:0] = 10'h0; //the expnt stay the origi 138 | 2'b1? : expnt_add_op1[9:0] = 10'h1; // the exptn add 1 139 | default : expnt_add_op1[9:0] = 10'b0; 140 | endcase 141 | // &CombEnd; @50 142 | end 143 | assign ex4_expnt_rst[9:0] = fdsu_ex4_expnt_rst[9:0] + 144 | expnt_add_op1[9:0]; 145 | 146 | //==========================Result Pack===================== 147 | 148 | // result denormal pack 149 | // shift to the denormal number 150 | // &CombBeg; @58 151 | always @( fdsu_ex4_expnt_rst[9:0] 152 | or fdsu_ex4_denorm_to_tiny_frac 153 | or ex4_frac[25:1]) 154 | begin 155 | case(fdsu_ex4_expnt_rst[9:0]) 156 | 10'h1: ex4_single_denorm_frac[22:0] = { ex4_frac[23:1]}; //-1022 1 157 | 10'h0: ex4_single_denorm_frac[22:0] = { ex4_frac[24:2]}; //-1023 0 158 | 10'h3ff:ex4_single_denorm_frac[22:0] = { ex4_frac[25:3]}; //-1024 -1 159 | 10'h3fe:ex4_single_denorm_frac[22:0] = {1'b0, ex4_frac[25:4]}; //-1025 -2 160 | 10'h3fd:ex4_single_denorm_frac[22:0] = {2'b0, ex4_frac[25:5]}; //-1026 -3 161 | 10'h3fc:ex4_single_denorm_frac[22:0] = {3'b0, ex4_frac[25:6]}; //-1027 -4 162 | 10'h3fb:ex4_single_denorm_frac[22:0] = {4'b0, ex4_frac[25:7]}; //-1028 -5 163 | 10'h3fa:ex4_single_denorm_frac[22:0] = {5'b0, ex4_frac[25:8]}; //-1029 -6 164 | 10'h3f9:ex4_single_denorm_frac[22:0] = {6'b0, ex4_frac[25:9]}; //-1030 -7 165 | 10'h3f8:ex4_single_denorm_frac[22:0] = {7'b0, ex4_frac[25:10]}; //-1031 -8 166 | 10'h3f7:ex4_single_denorm_frac[22:0] = {8'b0, ex4_frac[25:11]}; //-1032 -9 167 | 10'h3f6:ex4_single_denorm_frac[22:0] = {9'b0, ex4_frac[25:12]}; //-1033 -10 168 | 10'h3f5:ex4_single_denorm_frac[22:0] = {10'b0,ex4_frac[25:13]}; //-1034 -11 169 | 10'h3f4:ex4_single_denorm_frac[22:0] = {11'b0,ex4_frac[25:14]}; //-1035 -12 170 | 10'h3f3:ex4_single_denorm_frac[22:0] = {12'b0,ex4_frac[25:15]}; //-1036 -13 171 | 10'h3f2:ex4_single_denorm_frac[22:0] = {13'b0,ex4_frac[25:16]}; // -1037 172 | 10'h3f1:ex4_single_denorm_frac[22:0] = {14'b0,ex4_frac[25:17]}; //-1038 173 | 10'h3f0:ex4_single_denorm_frac[22:0] = {15'b0,ex4_frac[25:18]}; //-1039 174 | 10'h3ef:ex4_single_denorm_frac[22:0] = {16'b0,ex4_frac[25:19]}; //-1040 175 | 10'h3ee:ex4_single_denorm_frac[22:0] = {17'b0,ex4_frac[25:20]}; //-1041 176 | 10'h3ed:ex4_single_denorm_frac[22:0] = {18'b0,ex4_frac[25:21]}; //-1042 177 | 10'h3ec:ex4_single_denorm_frac[22:0] = {19'b0,ex4_frac[25:22]}; //-1043 178 | 10'h3eb:ex4_single_denorm_frac[22:0] = {20'b0,ex4_frac[25:23]}; //-1044 179 | 10'h3ea:ex4_single_denorm_frac[22:0] = {21'b0,ex4_frac[25:24]}; //-1044 180 | default :ex4_single_denorm_frac[22:0] = fdsu_ex4_denorm_to_tiny_frac ? 23'b1 : 23'b0; //-1045 181 | endcase 182 | // &CombEnd; @86 183 | end 184 | //here when denormal number round to add1, it will become normal number 185 | assign ex4_denorm_potnt_norm = (fdsu_ex4_potnt_norm[1] && ex4_frac[24]) || 186 | (fdsu_ex4_potnt_norm[0] && ex4_frac[25]) ; 187 | assign ex4_rslt_denorm = fdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm; 188 | assign ex4_denorm_result[31:0] = {fdsu_ex4_result_sign, 189 | 8'h0,ex4_single_denorm_frac[22:0]}; 190 | 191 | 192 | //ex4 overflow/underflow plus 193 | assign ex4_rst_nor = fdsu_ex4_result_nor; 194 | assign ex4_of_plus = fdsu_ex4_potnt_of && 195 | (|ex4_frac[25:24]) && 196 | ex4_rst_nor; 197 | assign ex4_uf_plus = fdsu_ex4_potnt_uf && 198 | (~|ex4_frac[25:24]) && 199 | ex4_rst_nor; 200 | //ex4 overflow round result 201 | assign ex4_result_lfn = (ex4_of_plus && fdsu_ex4_of_rst_lfn) || 202 | fdsu_ex4_result_lfn; 203 | assign ex4_result_inf = (ex4_of_plus && !fdsu_ex4_of_rst_lfn) || 204 | fdsu_ex4_result_inf; 205 | //Special Result Form 206 | // result largest finity number 207 | assign ex4_rst_lfn[31:0] = {fdsu_ex4_result_sign,8'hfe,{23{1'b1}}}; 208 | //result infinity 209 | assign ex4_rst_inf[31:0] = {fdsu_ex4_result_sign,8'hff,23'b0}; 210 | //result normal 211 | // &CombBeg; @114 212 | always @( ex4_frac[25:0]) 213 | begin 214 | casez(ex4_frac[25:24]) 215 | 2'b00 : ex4_frac_23[22:0] = ex4_frac[22:0]; 216 | 2'b01 : ex4_frac_23[22:0] = ex4_frac[23:1]; 217 | 2'b1? : ex4_frac_23[22:0] = ex4_frac[24:2]; 218 | default : ex4_frac_23[22:0] = 23'b0; 219 | endcase 220 | // &CombEnd; @121 221 | end 222 | assign ex4_rst_norm[31:0] = {fdsu_ex4_result_sign, 223 | ex4_expnt_rst[7:0], 224 | ex4_frac_23[22:0]}; 225 | assign ex4_cor_uf = (fdsu_ex4_uf && !ex4_denorm_potnt_norm || ex4_uf_plus) 226 | && fdsu_ex4_nx; 227 | assign ex4_cor_nx = fdsu_ex4_nx 228 | || fdsu_ex4_of 229 | || ex4_of_plus; 230 | 231 | assign ex4_expt[4:0] = { 232 | fdsu_ex4_nv, 233 | fdsu_ex4_dz, 234 | fdsu_ex4_of | ex4_of_plus, 235 | ex4_cor_uf, 236 | ex4_cor_nx}; 237 | 238 | assign ex4_final_rst_norm = !ex4_result_inf && 239 | !ex4_result_lfn && 240 | !ex4_rslt_denorm; 241 | // &CombBeg; @141 242 | always @( ex4_denorm_result[31:0] 243 | or ex4_result_lfn 244 | or ex4_result_inf 245 | or ex4_final_rst_norm 246 | or ex4_rst_norm[31:0] 247 | or ex4_rst_lfn[31:0] 248 | or ex4_rst_inf[31:0] 249 | or ex4_rslt_denorm) 250 | begin 251 | case({ex4_rslt_denorm, 252 | ex4_result_inf, 253 | ex4_result_lfn, 254 | ex4_final_rst_norm}) 255 | 4'b1000 : ex4_result[31:0] = ex4_denorm_result[31:0]; 256 | 4'b0100 : ex4_result[31:0] = ex4_rst_inf[31:0]; 257 | 4'b0010 : ex4_result[31:0] = ex4_rst_lfn[31:0]; 258 | 4'b0001 : ex4_result[31:0] = ex4_rst_norm[31:0]; 259 | default : ex4_result[31:0] = 32'b0; 260 | endcase 261 | // &CombEnd; @152 262 | end 263 | 264 | //========================================================== 265 | // Result Generate 266 | //========================================================== 267 | assign fdsu_frbus_freg[4:0] = fdsu_yy_wb_freg[4:0]; 268 | assign fdsu_frbus_data[31:0] = ex4_result[31:0]; 269 | assign fdsu_frbus_fflags[4:0] = ex4_expt[4:0]; 270 | 271 | // &ModuleEnd; @161 272 | endmodule 273 | 274 | 275 | 276 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // &ModuleBeg; @23 17 | module pa_fdsu_prepare( 18 | dp_xx_ex1_rm, 19 | ex1_div, 20 | ex1_divisor, 21 | ex1_expnt_adder_op0, 22 | ex1_expnt_adder_op1, 23 | ex1_of_result_lfn, 24 | ex1_op0_id, 25 | ex1_op0_sign, 26 | ex1_op1_id, 27 | ex1_op1_id_vld, 28 | ex1_op1_sel, 29 | ex1_oper_id_expnt, 30 | ex1_oper_id_expnt_f, 31 | ex1_oper_id_frac, 32 | ex1_oper_id_frac_f, 33 | ex1_remainder, 34 | ex1_result_sign, 35 | ex1_rm, 36 | ex1_sqrt, 37 | fdsu_ex1_sel, 38 | idu_fpu_ex1_func, 39 | idu_fpu_ex1_srcf0, 40 | idu_fpu_ex1_srcf1 41 | ); 42 | 43 | // &Ports; @24 44 | input [2 :0] dp_xx_ex1_rm; 45 | input ex1_op0_id; 46 | input ex1_op1_id; 47 | input ex1_op1_sel; 48 | input [12:0] ex1_oper_id_expnt_f; 49 | input [51:0] ex1_oper_id_frac_f; 50 | input fdsu_ex1_sel; 51 | input [9 :0] idu_fpu_ex1_func; 52 | input [31:0] idu_fpu_ex1_srcf0; 53 | input [31:0] idu_fpu_ex1_srcf1; 54 | output ex1_div; 55 | output [23:0] ex1_divisor; 56 | output [12:0] ex1_expnt_adder_op0; 57 | output [12:0] ex1_expnt_adder_op1; 58 | output ex1_of_result_lfn; 59 | output ex1_op0_sign; 60 | output ex1_op1_id_vld; 61 | output [12:0] ex1_oper_id_expnt; 62 | output [51:0] ex1_oper_id_frac; 63 | output [31:0] ex1_remainder; 64 | output ex1_result_sign; 65 | output [2 :0] ex1_rm; 66 | output ex1_sqrt; 67 | 68 | // &Regs; @25 69 | reg [12:0] ex1_expnt_adder_op1; 70 | reg ex1_of_result_lfn; 71 | 72 | // &Wires; @26 73 | wire div_sign; 74 | wire [2 :0] dp_xx_ex1_rm; 75 | wire ex1_div; 76 | wire [52:0] ex1_div_noid_nor_srt_op0; 77 | wire [52:0] ex1_div_noid_nor_srt_op1; 78 | wire [52:0] ex1_div_nor_srt_op0; 79 | wire [52:0] ex1_div_nor_srt_op1; 80 | wire [12:0] ex1_div_op0_expnt; 81 | wire [12:0] ex1_div_op1_expnt; 82 | wire [52:0] ex1_div_srt_op0; 83 | wire [52:0] ex1_div_srt_op1; 84 | wire [23:0] ex1_divisor; 85 | wire ex1_double; 86 | wire [12:0] ex1_expnt_adder_op0; 87 | wire ex1_op0_id; 88 | wire ex1_op0_id_nor; 89 | wire ex1_op0_sign; 90 | wire ex1_op1_id; 91 | wire ex1_op1_id_nor; 92 | wire ex1_op1_id_vld; 93 | wire ex1_op1_sel; 94 | wire ex1_op1_sign; 95 | wire [63:0] ex1_oper0; 96 | wire [51:0] ex1_oper0_frac; 97 | wire [12:0] ex1_oper0_id_expnt; 98 | wire [51:0] ex1_oper0_id_frac; 99 | wire [63:0] ex1_oper1; 100 | wire [51:0] ex1_oper1_frac; 101 | wire [12:0] ex1_oper1_id_expnt; 102 | wire [51:0] ex1_oper1_id_frac; 103 | wire [51:0] ex1_oper_frac; 104 | wire [12:0] ex1_oper_id_expnt; 105 | wire [12:0] ex1_oper_id_expnt_f; 106 | wire [51:0] ex1_oper_id_frac; 107 | wire [51:0] ex1_oper_id_frac_f; 108 | wire [31:0] ex1_remainder; 109 | wire ex1_result_sign; 110 | wire [2 :0] ex1_rm; 111 | wire ex1_single; 112 | wire ex1_sqrt; 113 | wire ex1_sqrt_expnt_odd; 114 | wire ex1_sqrt_op0_expnt_0; 115 | wire [12:0] ex1_sqrt_op1_expnt; 116 | wire [52:0] ex1_sqrt_srt_op0; 117 | wire fdsu_ex1_sel; 118 | wire [9 :0] idu_fpu_ex1_func; 119 | wire [31:0] idu_fpu_ex1_srcf0; 120 | wire [31:0] idu_fpu_ex1_srcf1; 121 | wire [59:0] sqrt_remainder; 122 | wire sqrt_sign; 123 | 124 | 125 | assign ex1_sqrt = idu_fpu_ex1_func[0]; 126 | assign ex1_div = idu_fpu_ex1_func[1]; 127 | assign ex1_oper0[63:0] = {32'b0, idu_fpu_ex1_srcf0[31:0] & {32{fdsu_ex1_sel}}}; 128 | assign ex1_oper1[63:0] = {32'b0, idu_fpu_ex1_srcf1[31:0] & {32{fdsu_ex1_sel}}}; 129 | assign ex1_double = 1'b0; 130 | assign ex1_single = 1'b1; 131 | // &Force("bus", "idu_fpu_ex1_func", 9, 0); @43 132 | assign ex1_op0_id_nor = ex1_op0_id; 133 | assign ex1_op1_id_nor = ex1_op1_id; 134 | 135 | //Sign bit prepare 136 | assign ex1_op0_sign = ex1_double && ex1_oper0[63] 137 | || ex1_single && ex1_oper0[31]; 138 | assign ex1_op1_sign = ex1_double && ex1_oper1[63] 139 | || ex1_single && ex1_oper1[31]; 140 | assign div_sign = ex1_op0_sign ^ ex1_op1_sign; 141 | assign sqrt_sign = ex1_op0_sign; 142 | assign ex1_result_sign = (ex1_div) 143 | ? div_sign 144 | : sqrt_sign; 145 | 146 | //=====================find first one======================= 147 | // this is for the denormal number 148 | assign ex1_oper_frac[51:0] = ex1_op1_sel ? ex1_oper1_frac[51:0] 149 | : ex1_oper0_frac[51:0]; 150 | 151 | // &Instance("pa_fdsu_ff1", "x_frac_expnt"); @63 152 | pa_fdsu_ff1 x_frac_expnt ( 153 | .fanc_shift_num (ex1_oper_id_frac[51:0] ), 154 | .frac_bin_val (ex1_oper_id_expnt[12:0]), 155 | .frac_num (ex1_oper_frac[51:0] ) 156 | ); 157 | 158 | // &Connect(.frac_num(ex1_oper_frac[51:0])); @64 159 | // &Connect(.frac_bin_val(ex1_oper_id_expnt[12:0])); @65 160 | // &Connect(.fanc_shift_num(ex1_oper_id_frac[51:0])); @66 161 | // &Force("output", "ex1_oper_id_expnt"); &Force("bus", "ex1_oper_id_expnt", 12, 0); @67 162 | // &Force("output", "ex1_oper_id_frac"); &Force("bus", "ex1_oper_id_frac", 51, 0); @68 163 | 164 | assign ex1_oper0_id_expnt[12:0] = ex1_op1_sel ? ex1_oper_id_expnt_f[12:0] 165 | : ex1_oper_id_expnt[12:0]; 166 | assign ex1_oper0_id_frac[51:0] = ex1_op1_sel ? ex1_oper_id_frac_f[51:0] 167 | : ex1_oper_id_frac[51:0]; 168 | assign ex1_oper1_id_expnt[12:0] = ex1_oper_id_expnt[12:0]; 169 | assign ex1_oper1_id_frac[51:0] = ex1_oper_id_frac[51:0]; 170 | 171 | assign ex1_oper0_frac[51:0] = {52{ex1_double}} & ex1_oper0[51:0] 172 | | {52{ex1_single}} & {ex1_oper0[22:0],29'b0}; 173 | assign ex1_oper1_frac[51:0] = {52{ex1_double}} & ex1_oper1[51:0] 174 | | {52{ex1_single}} & {ex1_oper1[22:0],29'b0}; 175 | 176 | //=====================exponent add========================= 177 | //exponent number 0 178 | assign ex1_div_op0_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper0[62:52]} 179 | | {13{ex1_single}} & {5'b0,ex1_oper0[30:23]}; 180 | assign ex1_expnt_adder_op0[12:0] = ex1_op0_id_nor ? ex1_oper0_id_expnt[12:0] 181 | : ex1_div_op0_expnt[12:0]; 182 | //exponent number 1 183 | assign ex1_div_op1_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper1[62:52]} 184 | | {13{ex1_single}} & {5'b0,ex1_oper1[30:23]}; 185 | assign ex1_sqrt_op1_expnt[12:0] = {13{ex1_double}} & {3'b0,{10{1'b1}}} //'d1023 186 | | {13{ex1_single}} & {6'b0,{7{1'b1}}}; //'d127 187 | // &CombBeg; @93 188 | always @( ex1_oper1_id_expnt[12:0] 189 | or ex1_div 190 | or ex1_op1_id_nor 191 | or ex1_sqrt_op1_expnt[12:0] 192 | or ex1_sqrt 193 | or ex1_div_op1_expnt[12:0]) 194 | begin 195 | case({ex1_div,ex1_sqrt}) 196 | 2'b10: ex1_expnt_adder_op1[12:0] = ex1_op1_id_nor ? ex1_oper1_id_expnt[12:0] 197 | : ex1_div_op1_expnt[12:0]; 198 | 2'b01: ex1_expnt_adder_op1[12:0] = ex1_sqrt_op1_expnt[12:0]; 199 | default: ex1_expnt_adder_op1[12:0] = 13'b0; 200 | endcase 201 | // &CombEnd; @100 202 | end 203 | 204 | //ex1_sqrt_expnt_odd 205 | //fraction will shift left by 1 206 | // adder_op0/1 timing is bad. 207 | // assign ex1_sqrt_expnt_odd = ex1_expnt_adder_op0[0] ^ ex1_expnt_adder_op1[0]; 208 | 209 | // sqrt_odd is only used when is sqrt. 210 | assign ex1_sqrt_op0_expnt_0 = ex1_op0_id_nor ? ex1_oper_id_expnt[0] 211 | : ex1_div_op0_expnt[0]; 212 | // ex1_expnt_adder_op1 is always 1'b1, so adder_op0[0] should be 0. 213 | assign ex1_sqrt_expnt_odd = !ex1_sqrt_op0_expnt_0; 214 | 215 | assign ex1_rm[2:0] = dp_xx_ex1_rm[2:0]; 216 | //RNE : Always inc 1 because round to nearest of 1.111...11 217 | //RTZ : Always not inc 1 218 | //RUP : Always not inc 1 when posetive 219 | //RDN : Always not inc 1 when negative 220 | //RMM : Always inc 1 because round to max magnitude 221 | // &CombBeg; @119 222 | always @( ex1_rm[2:0] 223 | or ex1_result_sign) 224 | begin 225 | case(ex1_rm[2:0]) 226 | 3'b000 : ex1_of_result_lfn = 1'b0; 227 | 3'b001 : ex1_of_result_lfn = 1'b1; 228 | 3'b010 : ex1_of_result_lfn = !ex1_result_sign; 229 | 3'b011 : ex1_of_result_lfn = ex1_result_sign; 230 | 3'b100 : ex1_of_result_lfn = 1'b0; 231 | default: ex1_of_result_lfn = 1'b0; 232 | endcase 233 | // &CombEnd; @128 234 | end 235 | 236 | //EX1 Remainder 237 | //div : 1/8 <= x < 1/4 238 | //sqrt : 1/16 <= x < 1/4 239 | assign ex1_remainder[31:0] = {32{ex1_div }} & {5'b0,ex1_div_srt_op0[52:28],2'b0} | 240 | {32{ex1_sqrt}} & sqrt_remainder[59:28]; 241 | 242 | //EX1 Divisor 243 | //1/2 <= y < 1 244 | assign ex1_divisor[23:0] = ex1_div_srt_op1[52:29]; 245 | 246 | //ex1_div_srt_op0 247 | assign ex1_div_srt_op0[52:0] = ex1_div_nor_srt_op0[52:0]; 248 | //ex1_div_srt_op1 249 | assign ex1_div_srt_op1[52:0] = ex1_div_nor_srt_op1[52:0]; 250 | //ex1_div_nor_srt_op0 251 | assign ex1_div_noid_nor_srt_op0[52:0] = {53{ex1_double}} & {1'b1,ex1_oper0[51:0]} 252 | | {53{ex1_single}} & {1'b1,ex1_oper0[22:0],29'b0}; 253 | assign ex1_div_nor_srt_op0[52:0] = ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0],1'b0} 254 | : ex1_div_noid_nor_srt_op0[52:0]; 255 | //ex1_div_nor_srt_op1 256 | assign ex1_div_noid_nor_srt_op1[52:0] = {53{ex1_double}} & {1'b1,ex1_oper1[51:0]} 257 | | {53{ex1_single}} & {1'b1,ex1_oper1[22:0],29'b0}; 258 | assign ex1_div_nor_srt_op1[52:0] = ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0],1'b0} 259 | : ex1_div_noid_nor_srt_op1[52:0]; 260 | //sqrt_remainder 261 | assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd) 262 | ? {5'b0,ex1_sqrt_srt_op0[52:0],2'b0} 263 | : {6'b0,ex1_sqrt_srt_op0[52:0],1'b0}; 264 | //ex1_sqrt_srt_op0 265 | assign ex1_sqrt_srt_op0[52:0] = ex1_div_srt_op0[52:0]; 266 | 267 | //========================Pipe to EX2======================= 268 | //exponent register cal result 269 | // &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @173 270 | // &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @174 271 | // &Force("output", "ex1_double"); @175 272 | // &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @177 273 | // &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @178 274 | // &Force("output", "ex1_result_sign"); @180 275 | // &Force("output", "ex1_div"); @181 276 | // &Force("output", "ex1_sqrt"); @182 277 | // &Force("output", "ex1_rm"); &Force("bus", "ex1_rm", 2, 0); @183 278 | // &Force("output", "ex1_op0_sign"); @184 279 | 280 | assign ex1_op1_id_vld = ex1_op1_id_nor && ex1_div; 281 | 282 | // &ModuleEnd; @188 283 | endmodule 284 | 285 | 286 | 287 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // &ModuleBeg; @23 17 | module pa_fdsu_special( 18 | cp0_fpu_xx_dqnan, 19 | dp_xx_ex1_cnan, 20 | dp_xx_ex1_id, 21 | dp_xx_ex1_inf, 22 | dp_xx_ex1_qnan, 23 | dp_xx_ex1_snan, 24 | dp_xx_ex1_zero, 25 | ex1_div, 26 | ex1_op0_id, 27 | ex1_op0_norm, 28 | ex1_op0_sign, 29 | ex1_op1_id, 30 | ex1_op1_norm, 31 | ex1_result_sign, 32 | ex1_sqrt, 33 | ex1_srt_skip, 34 | fdsu_fpu_ex1_fflags, 35 | fdsu_fpu_ex1_special_sel, 36 | fdsu_fpu_ex1_special_sign 37 | ); 38 | 39 | // &Ports; @24 40 | input cp0_fpu_xx_dqnan; 41 | input [2:0] dp_xx_ex1_cnan; 42 | input [2:0] dp_xx_ex1_id; 43 | input [2:0] dp_xx_ex1_inf; 44 | input [2:0] dp_xx_ex1_qnan; 45 | input [2:0] dp_xx_ex1_snan; 46 | input [2:0] dp_xx_ex1_zero; 47 | input ex1_div; 48 | input ex1_op0_sign; 49 | input ex1_result_sign; 50 | input ex1_sqrt; 51 | output ex1_op0_id; 52 | output ex1_op0_norm; 53 | output ex1_op1_id; 54 | output ex1_op1_norm; 55 | output ex1_srt_skip; 56 | output [4:0] fdsu_fpu_ex1_fflags; 57 | output [7:0] fdsu_fpu_ex1_special_sel; 58 | output [3:0] fdsu_fpu_ex1_special_sign; 59 | 60 | // &Regs; @25 61 | reg ex1_result_cnan; 62 | reg ex1_result_qnan_op0; 63 | reg ex1_result_qnan_op1; 64 | 65 | // &Wires; @26 66 | wire cp0_fpu_xx_dqnan; 67 | wire [2:0] dp_xx_ex1_cnan; 68 | wire [2:0] dp_xx_ex1_id; 69 | wire [2:0] dp_xx_ex1_inf; 70 | wire [2:0] dp_xx_ex1_qnan; 71 | wire [2:0] dp_xx_ex1_snan; 72 | wire [2:0] dp_xx_ex1_zero; 73 | wire ex1_div; 74 | wire ex1_div_dz; 75 | wire ex1_div_nv; 76 | wire ex1_div_rst_inf; 77 | wire ex1_div_rst_qnan; 78 | wire ex1_div_rst_zero; 79 | wire ex1_dz; 80 | wire [4:0] ex1_fflags; 81 | wire ex1_nv; 82 | wire ex1_op0_cnan; 83 | wire ex1_op0_id; 84 | wire ex1_op0_inf; 85 | wire ex1_op0_is_qnan; 86 | wire ex1_op0_is_snan; 87 | wire ex1_op0_norm; 88 | wire ex1_op0_qnan; 89 | wire ex1_op0_sign; 90 | wire ex1_op0_snan; 91 | wire ex1_op0_tt_zero; 92 | wire ex1_op0_zero; 93 | wire ex1_op1_cnan; 94 | wire ex1_op1_id; 95 | wire ex1_op1_inf; 96 | wire ex1_op1_is_qnan; 97 | wire ex1_op1_is_snan; 98 | wire ex1_op1_norm; 99 | wire ex1_op1_qnan; 100 | wire ex1_op1_snan; 101 | wire ex1_op1_tt_zero; 102 | wire ex1_op1_zero; 103 | wire ex1_result_inf; 104 | wire ex1_result_lfn; 105 | wire ex1_result_qnan; 106 | wire ex1_result_sign; 107 | wire ex1_result_zero; 108 | wire ex1_rst_default_qnan; 109 | wire [7:0] ex1_special_sel; 110 | wire [3:0] ex1_special_sign; 111 | wire ex1_sqrt; 112 | wire ex1_sqrt_nv; 113 | wire ex1_sqrt_rst_inf; 114 | wire ex1_sqrt_rst_qnan; 115 | wire ex1_sqrt_rst_zero; 116 | wire ex1_srt_skip; 117 | wire [4:0] fdsu_fpu_ex1_fflags; 118 | wire [7:0] fdsu_fpu_ex1_special_sel; 119 | wire [3:0] fdsu_fpu_ex1_special_sign; 120 | 121 | 122 | //infinity number 123 | // &Force("bus", "dp_xx_ex1_inf", 2, 0); @29 124 | assign ex1_op0_inf = dp_xx_ex1_inf[0]; 125 | assign ex1_op1_inf = dp_xx_ex1_inf[1]; 126 | 127 | //zero 128 | // &Force("bus", "dp_xx_ex1_zero", 2, 0); @34 129 | assign ex1_op0_zero = dp_xx_ex1_zero[0]; 130 | assign ex1_op1_zero = dp_xx_ex1_zero[1]; 131 | 132 | //denormalize number 133 | // &Force("bus", "dp_xx_ex1_id", 2, 0); @39 134 | assign ex1_op0_id = dp_xx_ex1_id[0]; 135 | assign ex1_op1_id = dp_xx_ex1_id[1]; 136 | 137 | //cNaN 138 | // &Force("bus", "dp_xx_ex1_cnan", 2, 0); @44 139 | assign ex1_op0_cnan = dp_xx_ex1_cnan[0]; 140 | assign ex1_op1_cnan = dp_xx_ex1_cnan[1]; 141 | 142 | //sNaN 143 | // &Force("bus", "dp_xx_ex1_snan", 2, 0); @49 144 | assign ex1_op0_snan = dp_xx_ex1_snan[0]; 145 | assign ex1_op1_snan = dp_xx_ex1_snan[1]; 146 | 147 | //qNaN 148 | // &Force("bus", "dp_xx_ex1_qnan", 2, 0); @54 149 | assign ex1_op0_qnan = dp_xx_ex1_qnan[0]; 150 | assign ex1_op1_qnan = dp_xx_ex1_qnan[1]; 151 | 152 | 153 | //======================EX1 expt detect===================== 154 | //ex1_id_detect 155 | //any opration is zero 156 | // no input denormalize exception anymore 157 | // 158 | //ex1_nv_detect 159 | //div_nv 160 | // 1.any operation is sNaN 161 | // 2.0/0(include DN flush to zero) 162 | // 3.inf/inf 163 | //sqrt_nv 164 | // 1.any operation is sNaN 165 | // 2.operation sign is 1 && operation is not zero/qNaN 166 | assign ex1_nv = ex1_div && ex1_div_nv || 167 | ex1_sqrt && ex1_sqrt_nv; 168 | //ex1_div_nv 169 | assign ex1_div_nv = ex1_op0_snan || 170 | ex1_op1_snan || 171 | (ex1_op0_tt_zero && ex1_op1_tt_zero)|| 172 | (ex1_op0_inf && ex1_op1_inf); 173 | assign ex1_op0_tt_zero = ex1_op0_zero; 174 | assign ex1_op1_tt_zero = ex1_op1_zero; 175 | //ex1_sqrt_nv 176 | assign ex1_sqrt_nv = ex1_op0_snan || 177 | ex1_op0_sign && 178 | (ex1_op0_norm || 179 | ex1_op0_inf ); 180 | 181 | // This 'norm' also include denorm. 182 | assign ex1_op0_norm = !ex1_op0_inf && !ex1_op0_zero && !ex1_op0_snan && !ex1_op0_qnan && !ex1_op0_cnan; 183 | assign ex1_op1_norm = !ex1_op1_inf && !ex1_op1_zero && !ex1_op1_snan && !ex1_op1_qnan && !ex1_op1_cnan; 184 | 185 | //ex1_of_detect 186 | //div_of 187 | // 1.only detect id overflow case 188 | //assign ex1_of = ex1_div && ex1_div_of; 189 | //assign ex1_div_of = ex1_op1_id_fm1 && 190 | // ex1_op0_norm && 191 | // ex1_div_id_of; 192 | // 193 | ////ex1_uf_detect 194 | ////div_uf 195 | //// 1.only detect id underflow case 196 | //assign ex1_uf = ex1_div && ex1_div_uf; 197 | //assign ex1_div_uf = ex1_op0_id && 198 | // ex1_op1_norm && 199 | // ex1_div_id_uf; 200 | //ex1_dz_detect 201 | //div_dz 202 | // 1.op0 is normal && op1 zero 203 | assign ex1_dz = ex1_div && ex1_div_dz; 204 | assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm; 205 | 206 | //===================special cal result===================== 207 | //ex1 result is zero 208 | //div_zero 209 | // 1.op0 is zero && op1 is normal 210 | // 2.op0 is zero/normal && op1 is inf 211 | //sqrt_zero 212 | // 1.op0 is zero 213 | assign ex1_result_zero = ex1_div_rst_zero && ex1_div || 214 | ex1_sqrt_rst_zero && ex1_sqrt; 215 | assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm ) || 216 | // (!ex1_expnt0_max && !ex1_op0_cnan && ex1_op1_inf); 217 | (!ex1_op0_inf && !ex1_op0_qnan && !ex1_op0_snan && !ex1_op0_cnan && ex1_op1_inf); 218 | assign ex1_sqrt_rst_zero = ex1_op0_tt_zero; 219 | 220 | //ex1 result is qNaN 221 | //ex1_nv 222 | //div_qnan 223 | // 1.op0 is qnan || op1 is qnan 224 | //sqrt_qnan 225 | // 1.op0 is qnan 226 | assign ex1_result_qnan = ex1_div_rst_qnan && ex1_div || 227 | ex1_sqrt_rst_qnan && ex1_sqrt || 228 | ex1_nv; 229 | assign ex1_div_rst_qnan = ex1_op0_qnan || 230 | ex1_op1_qnan; 231 | assign ex1_sqrt_rst_qnan = ex1_op0_qnan; 232 | 233 | //ex1_rst_default_qnan 234 | //0/0, inf/inf, sqrt negative should get default qNaN 235 | assign ex1_rst_default_qnan = (ex1_div && ex1_op0_zero && ex1_op1_zero) || 236 | (ex1_div && ex1_op0_inf && ex1_op1_inf) || 237 | (ex1_sqrt&& ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf)); 238 | 239 | //ex1 result is inf 240 | //ex1_dz 241 | // 242 | //div_inf 243 | // 1.op0 is inf && op1 is normal/zero 244 | //sqrt_inf 245 | // 1.op0 is inf 246 | assign ex1_result_inf = ex1_div_rst_inf && ex1_div || 247 | ex1_sqrt_rst_inf && ex1_sqrt || 248 | ex1_dz ; 249 | // assign ex1_div_rst_inf = ex1_op0_inf && !ex1_expnt1_max && !ex1_op1_cnan; 250 | assign ex1_div_rst_inf = ex1_op0_inf && !ex1_op1_inf && !ex1_op1_qnan && !ex1_op1_snan && !ex1_op1_cnan; 251 | assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign; 252 | 253 | //ex1 result is lfn 254 | //ex1_of && round result toward not inc 1 255 | assign ex1_result_lfn = 1'b0; 256 | 257 | //Default_qnan/Standard_qnan Select 258 | assign ex1_op0_is_snan = ex1_op0_snan; 259 | assign ex1_op1_is_snan = ex1_op1_snan && ex1_div; 260 | assign ex1_op0_is_qnan = ex1_op0_qnan; 261 | assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div; 262 | 263 | // &CombBeg; @169 264 | always @( ex1_op0_is_snan 265 | or ex1_op0_cnan 266 | or ex1_result_qnan 267 | or ex1_op0_is_qnan 268 | or ex1_rst_default_qnan 269 | or cp0_fpu_xx_dqnan 270 | or ex1_op1_cnan 271 | or ex1_op1_is_qnan 272 | or ex1_op1_is_snan) 273 | begin 274 | if(ex1_rst_default_qnan) 275 | begin 276 | ex1_result_qnan_op0 = 1'b0; 277 | ex1_result_qnan_op1 = 1'b0; 278 | ex1_result_cnan = ex1_result_qnan; 279 | end 280 | else if(ex1_op0_is_snan && cp0_fpu_xx_dqnan) 281 | begin 282 | ex1_result_qnan_op0 = ex1_result_qnan; 283 | ex1_result_qnan_op1 = 1'b0; 284 | ex1_result_cnan = 1'b0; 285 | end 286 | else if(ex1_op1_is_snan && cp0_fpu_xx_dqnan) 287 | begin 288 | ex1_result_qnan_op0 = 1'b0; 289 | ex1_result_qnan_op1 = ex1_result_qnan; 290 | ex1_result_cnan = 1'b0; 291 | end 292 | else if(ex1_op0_is_qnan && cp0_fpu_xx_dqnan) 293 | begin 294 | ex1_result_qnan_op0 = ex1_result_qnan && !ex1_op0_cnan; 295 | ex1_result_qnan_op1 = 1'b0; 296 | ex1_result_cnan = ex1_result_qnan && ex1_op0_cnan; 297 | end 298 | else if(ex1_op1_is_qnan && cp0_fpu_xx_dqnan) 299 | begin 300 | ex1_result_qnan_op0 = 1'b0; 301 | ex1_result_qnan_op1 = ex1_result_qnan && !ex1_op1_cnan; 302 | ex1_result_cnan = ex1_result_qnan && ex1_op1_cnan; 303 | end 304 | else 305 | begin 306 | ex1_result_qnan_op0 = 1'b0; 307 | ex1_result_qnan_op1 = 1'b0; 308 | ex1_result_cnan = ex1_result_qnan; 309 | end 310 | // &CombEnd; @206 311 | end 312 | 313 | 314 | //Special result should skip SRT logic 315 | assign ex1_srt_skip = ex1_result_zero || 316 | ex1_result_qnan || 317 | ex1_result_lfn || 318 | ex1_result_inf; 319 | // fflags: 320 | // NV, DZ, OF, UF, NX 321 | assign ex1_fflags[4:0] = {ex1_nv, ex1_dz, 3'b0}; 322 | // Special Sel[7:0]: 323 | // qnan_src2, qnan_src1, qnan_src0, cnan, lfn, inf, zero, src2 324 | assign ex1_special_sel[7:0] = {1'b0, ex1_result_qnan_op1, ex1_result_qnan_op0, 325 | ex1_result_cnan, ex1_result_lfn, ex1_result_inf, 326 | ex1_result_zero, 1'b0}; 327 | // Special Sign[3:0] 328 | // lfn, inf, zero, src2 329 | assign ex1_special_sign[3:0] = {ex1_result_sign, ex1_result_sign, ex1_result_sign, 1'b0}; 330 | 331 | //========================================================== 332 | // Output Signal 333 | //========================================================== 334 | assign fdsu_fpu_ex1_fflags[4:0] = ex1_fflags[4:0]; 335 | assign fdsu_fpu_ex1_special_sel[7:0] = ex1_special_sel[7:0]; 336 | assign fdsu_fpu_ex1_special_sign[3:0] = ex1_special_sign[3:0]; 337 | 338 | // &Force("output", "ex1_op0_norm"); @233 339 | // &Force("output", "ex1_op1_norm"); @234 340 | 341 | // &ModuleEnd; @236 342 | endmodule 343 | 344 | 345 | 346 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module pa_fpu_dp( 17 | cp0_fpu_icg_en, 18 | cp0_fpu_xx_rm, 19 | cp0_yy_clk_en, 20 | ctrl_xx_ex1_inst_vld, 21 | ctrl_xx_ex1_stall, 22 | ctrl_xx_ex1_warm_up, 23 | dp_frbus_ex2_data, 24 | dp_frbus_ex2_fflags, 25 | dp_xx_ex1_cnan, 26 | dp_xx_ex1_id, 27 | dp_xx_ex1_inf, 28 | dp_xx_ex1_norm, 29 | dp_xx_ex1_qnan, 30 | dp_xx_ex1_snan, 31 | dp_xx_ex1_zero, 32 | ex2_inst_wb, 33 | fdsu_fpu_ex1_fflags, 34 | fdsu_fpu_ex1_special_sel, 35 | fdsu_fpu_ex1_special_sign, 36 | forever_cpuclk, 37 | idu_fpu_ex1_eu_sel, 38 | idu_fpu_ex1_func, 39 | idu_fpu_ex1_gateclk_vld, 40 | idu_fpu_ex1_rm, 41 | idu_fpu_ex1_srcf0, 42 | idu_fpu_ex1_srcf1, 43 | idu_fpu_ex1_srcf2, 44 | pad_yy_icg_scan_en 45 | ); 46 | 47 | input cp0_fpu_icg_en; 48 | input [2 :0] cp0_fpu_xx_rm; 49 | input cp0_yy_clk_en; 50 | input ctrl_xx_ex1_inst_vld; 51 | input ctrl_xx_ex1_stall; 52 | input ctrl_xx_ex1_warm_up; 53 | input [4 :0] fdsu_fpu_ex1_fflags; 54 | input [7 :0] fdsu_fpu_ex1_special_sel; 55 | input [3 :0] fdsu_fpu_ex1_special_sign; 56 | input forever_cpuclk; 57 | input [2 :0] idu_fpu_ex1_eu_sel; 58 | input [9 :0] idu_fpu_ex1_func; 59 | input idu_fpu_ex1_gateclk_vld; 60 | input [2 :0] idu_fpu_ex1_rm; 61 | input [31:0] idu_fpu_ex1_srcf0; 62 | input [31:0] idu_fpu_ex1_srcf1; 63 | input [31:0] idu_fpu_ex1_srcf2; 64 | input pad_yy_icg_scan_en; 65 | output [31:0] dp_frbus_ex2_data; 66 | output [4 :0] dp_frbus_ex2_fflags; 67 | output [2 :0] dp_xx_ex1_cnan; 68 | output [2 :0] dp_xx_ex1_id; 69 | output [2 :0] dp_xx_ex1_inf; 70 | output [2 :0] dp_xx_ex1_norm; 71 | output [2 :0] dp_xx_ex1_qnan; 72 | output [2 :0] dp_xx_ex1_snan; 73 | output [2 :0] dp_xx_ex1_zero; 74 | output ex2_inst_wb; 75 | 76 | reg [4 :0] ex1_fflags; 77 | reg [31:0] ex1_special_data; 78 | reg [8 :0] ex1_special_sel; 79 | reg [3 :0] ex1_special_sign; 80 | reg [4 :0] ex2_fflags; 81 | reg [31:0] ex2_result; 82 | reg [31:0] ex2_special_data; 83 | reg [6 :0] ex2_special_sel; 84 | reg [3 :0] ex2_special_sign; 85 | 86 | wire cp0_fpu_icg_en; 87 | wire [2 :0] cp0_fpu_xx_rm; 88 | wire cp0_yy_clk_en; 89 | wire ctrl_xx_ex1_inst_vld; 90 | wire ctrl_xx_ex1_stall; 91 | wire ctrl_xx_ex1_warm_up; 92 | wire [31:0] dp_frbus_ex2_data; 93 | wire [4 :0] dp_frbus_ex2_fflags; 94 | wire [2 :0] dp_xx_ex1_cnan; 95 | wire [2 :0] dp_xx_ex1_id; 96 | wire [2 :0] dp_xx_ex1_inf; 97 | wire [2 :0] dp_xx_ex1_norm; 98 | wire [2 :0] dp_xx_ex1_qnan; 99 | wire [2 :0] dp_xx_ex1_snan; 100 | wire [2 :0] dp_xx_ex1_zero; 101 | wire [2 :0] ex1_decode_rm; 102 | wire ex1_double; 103 | wire [2 :0] ex1_eu_sel; 104 | wire [9 :0] ex1_func; 105 | wire [2 :0] ex1_global_rm; 106 | wire [2 :0] ex1_rm; 107 | wire ex1_single; 108 | wire [31:0] ex1_special_data_final; 109 | wire [63:0] ex1_src0; 110 | wire [63:0] ex1_src1; 111 | wire [63:0] ex1_src2; 112 | wire ex1_src2_vld; 113 | wire [2 :0] ex1_src_cnan; 114 | wire [2 :0] ex1_src_id; 115 | wire [2 :0] ex1_src_inf; 116 | wire [2 :0] ex1_src_norm; 117 | wire [2 :0] ex1_src_qnan; 118 | wire [2 :0] ex1_src_snan; 119 | wire [2 :0] ex1_src_zero; 120 | wire ex2_data_clk; 121 | wire ex2_data_clk_en; 122 | wire ex2_inst_wb; 123 | wire [4 :0] fdsu_fpu_ex1_fflags; 124 | wire [7 :0] fdsu_fpu_ex1_special_sel; 125 | wire [3 :0] fdsu_fpu_ex1_special_sign; 126 | wire forever_cpuclk; 127 | wire [2 :0] idu_fpu_ex1_eu_sel; 128 | wire [9 :0] idu_fpu_ex1_func; 129 | wire idu_fpu_ex1_gateclk_vld; 130 | wire [2 :0] idu_fpu_ex1_rm; 131 | wire [31:0] idu_fpu_ex1_srcf0; 132 | wire [31:0] idu_fpu_ex1_srcf1; 133 | wire [31:0] idu_fpu_ex1_srcf2; 134 | wire pad_yy_icg_scan_en; 135 | 136 | 137 | parameter DOUBLE_WIDTH =64; 138 | parameter SINGLE_WIDTH =32; 139 | parameter FUNC_WIDTH =10; 140 | //========================================================== 141 | // EX1 special data path 142 | //========================================================== 143 | assign ex1_eu_sel[2:0] = idu_fpu_ex1_eu_sel[2:0]; //3'h4 144 | assign ex1_func[FUNC_WIDTH-1:0] = idu_fpu_ex1_func[FUNC_WIDTH-1:0]; 145 | assign ex1_global_rm[2:0] = cp0_fpu_xx_rm[2:0]; 146 | assign ex1_decode_rm[2:0] = idu_fpu_ex1_rm[2:0]; 147 | 148 | assign ex1_rm[2:0] = (ex1_decode_rm[2:0]==3'b111) 149 | ? ex1_global_rm[2:0] : ex1_decode_rm[2:0]; 150 | 151 | assign ex1_src2_vld = idu_fpu_ex1_eu_sel[1] && ex1_func[0]; 152 | 153 | assign ex1_src0[DOUBLE_WIDTH-1:0] = { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf0[SINGLE_WIDTH-1:0]}; 154 | assign ex1_src1[DOUBLE_WIDTH-1:0] = { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf1[SINGLE_WIDTH-1:0]}; 155 | assign ex1_src2[DOUBLE_WIDTH-1:0] = ex1_src2_vld ? { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf2[SINGLE_WIDTH-1:0]} 156 | : { {SINGLE_WIDTH{1'b1}},{SINGLE_WIDTH{1'b0}} }; 157 | 158 | assign ex1_double = 1'b0; 159 | assign ex1_single = 1'b1; 160 | 161 | //========================================================== 162 | // EX1 special src data judge 163 | //========================================================== 164 | pa_fpu_src_type x_pa_fpu_ex1_srcf0_type ( 165 | .inst_double (ex1_double ), 166 | .inst_single (ex1_single ), 167 | .src_cnan (ex1_src_cnan[0]), 168 | .src_id (ex1_src_id[0] ), 169 | .src_in (ex1_src0 ), 170 | .src_inf (ex1_src_inf[0] ), 171 | .src_norm (ex1_src_norm[0]), 172 | .src_qnan (ex1_src_qnan[0]), 173 | .src_snan (ex1_src_snan[0]), 174 | .src_zero (ex1_src_zero[0]) 175 | ); 176 | 177 | pa_fpu_src_type x_pa_fpu_ex1_srcf1_type ( 178 | .inst_double (ex1_double ), 179 | .inst_single (ex1_single ), 180 | .src_cnan (ex1_src_cnan[1]), 181 | .src_id (ex1_src_id[1] ), 182 | .src_in (ex1_src1 ), 183 | .src_inf (ex1_src_inf[1] ), 184 | .src_norm (ex1_src_norm[1]), 185 | .src_qnan (ex1_src_qnan[1]), 186 | .src_snan (ex1_src_snan[1]), 187 | .src_zero (ex1_src_zero[1]) 188 | ); 189 | 190 | pa_fpu_src_type x_pa_fpu_ex1_srcf2_type ( 191 | .inst_double (ex1_double ), 192 | .inst_single (ex1_single ), 193 | .src_cnan (ex1_src_cnan[2]), 194 | .src_id (ex1_src_id[2] ), 195 | .src_in (ex1_src2 ), 196 | .src_inf (ex1_src_inf[2] ), 197 | .src_norm (ex1_src_norm[2]), 198 | .src_qnan (ex1_src_qnan[2]), 199 | .src_snan (ex1_src_snan[2]), 200 | .src_zero (ex1_src_zero[2]) 201 | ); 202 | 203 | assign dp_xx_ex1_cnan[2:0] = ex1_src_cnan[2:0]; 204 | assign dp_xx_ex1_snan[2:0] = ex1_src_snan[2:0]; 205 | assign dp_xx_ex1_qnan[2:0] = ex1_src_qnan[2:0]; 206 | assign dp_xx_ex1_norm[2:0] = ex1_src_norm[2:0]; 207 | assign dp_xx_ex1_zero[2:0] = ex1_src_zero[2:0]; 208 | assign dp_xx_ex1_inf[2:0] = ex1_src_inf[2:0]; 209 | assign dp_xx_ex1_id[2:0] = ex1_src_id[2:0]; 210 | 211 | //========================================================== 212 | // EX1 special result judge 213 | //========================================================== 214 | 215 | always @( fdsu_fpu_ex1_special_sign[3:0] 216 | or fdsu_fpu_ex1_fflags[4:0] 217 | or ex1_eu_sel[2:0] 218 | or fdsu_fpu_ex1_special_sel[7:0]) 219 | begin 220 | case(ex1_eu_sel[2:0]) //3'h4 221 | 3'b100: begin//FDSU 222 | ex1_fflags[4:0] = fdsu_fpu_ex1_fflags[4:0]; 223 | ex1_special_sel[8:0] ={1'b0,fdsu_fpu_ex1_special_sel[7:0]}; 224 | ex1_special_sign[3:0] = fdsu_fpu_ex1_special_sign[3:0]; 225 | end 226 | default: begin//FDSU 227 | ex1_fflags[4:0] = {5{1'b0}}; 228 | ex1_special_sel[8:0] = {9{1'b0}}; 229 | ex1_special_sign[3:0] = {4{1'b0}}; 230 | end 231 | endcase 232 | end 233 | 234 | always @( ex1_special_sel[8:5] 235 | or ex1_src0[31:0] 236 | or ex1_src1[31:0] 237 | or ex1_src2[31:0]) 238 | begin 239 | case(ex1_special_sel[8:5]) 240 | 4'b0001: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src0[SINGLE_WIDTH-1:0]; 241 | 4'b0010: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src1[SINGLE_WIDTH-1:0]; 242 | 4'b0100: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src2[SINGLE_WIDTH-1:0]; 243 | default : ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src2[SINGLE_WIDTH-1:0]; 244 | endcase 245 | end 246 | 247 | assign ex1_special_data_final[SINGLE_WIDTH-1:0] = ex1_special_data[SINGLE_WIDTH-1:0]; 248 | 249 | //========================================================== 250 | // EX1-EX2 data pipedown 251 | //========================================================== 252 | assign ex2_data_clk_en = idu_fpu_ex1_gateclk_vld || ctrl_xx_ex1_warm_up; 253 | 254 | gated_clk_cell x_fpu_data_ex2_gated_clk ( 255 | .clk_in (forever_cpuclk ), 256 | .clk_out (ex2_data_clk ), 257 | .external_en (1'b0 ), 258 | .global_en (cp0_yy_clk_en ), 259 | .local_en (ex2_data_clk_en ), 260 | .module_en (cp0_fpu_icg_en ), 261 | .pad_yy_icg_scan_en (pad_yy_icg_scan_en) 262 | ); 263 | 264 | always @(posedge ex2_data_clk) 265 | begin 266 | if(ctrl_xx_ex1_inst_vld && !ctrl_xx_ex1_stall || ctrl_xx_ex1_warm_up) 267 | begin 268 | ex2_fflags[4:0] <= ex1_fflags[4:0]; 269 | ex2_special_sign[3:0] <= ex1_special_sign[3:0]; 270 | ex2_special_sel[6:0] <={ex1_special_sel[8],|ex1_special_sel[7:5],ex1_special_sel[4:0]}; 271 | ex2_special_data[SINGLE_WIDTH-1:0] <= ex1_special_data_final[SINGLE_WIDTH-1:0]; 272 | end 273 | end 274 | 275 | assign ex2_inst_wb = (|ex2_special_sel[6:0]); 276 | 277 | always @( ex2_special_sel[6:0] 278 | or ex2_special_data[31:0] 279 | or ex2_special_sign[3:0]) 280 | begin 281 | case(ex2_special_sel[6:0]) 282 | 7'b0000_001: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[0],ex2_special_data[SINGLE_WIDTH-2:0]};//src2 283 | 7'b0000_010: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[1], {31{1'b0}} };//zero 284 | 7'b0000_100: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[2], {8{1'b1}},{23{1'b0}} };//inf 285 | 7'b0001_000: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[3], {7{1'b1}},1'b0,{23{1'b1}} };//lfn 286 | 7'b0010_000: ex2_result[SINGLE_WIDTH-1:0] = { 1'b0, {8{1'b1}},1'b1, {22{1'b0}} };//cnan 287 | 7'b0100_000: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_data[31],{8{1'b1}}, 1'b1, ex2_special_data[21:0]};//propagate qnan 288 | 7'b1000_000: ex2_result[SINGLE_WIDTH-1:0] = ex2_special_data[SINGLE_WIDTH-1:0]; //ex1 falu special result 289 | default: ex2_result[SINGLE_WIDTH-1:0] = {SINGLE_WIDTH{1'b0}}; 290 | endcase 291 | end 292 | 293 | assign dp_frbus_ex2_data[SINGLE_WIDTH-1:0] = ex2_result[SINGLE_WIDTH-1:0]; 294 | assign dp_frbus_ex2_fflags[4:0] = ex2_fflags[4:0]; 295 | 296 | endmodule 297 | 298 | 299 | 300 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module pa_fpu_frbus( 17 | ctrl_frbus_ex2_wb_req, 18 | dp_frbus_ex2_data, 19 | dp_frbus_ex2_fflags, 20 | fdsu_frbus_data, 21 | fdsu_frbus_fflags, 22 | fdsu_frbus_wb_vld, 23 | fpu_idu_fwd_data, 24 | fpu_idu_fwd_fflags, 25 | fpu_idu_fwd_vld 26 | ); 27 | 28 | input ctrl_frbus_ex2_wb_req; 29 | input [31:0] dp_frbus_ex2_data; 30 | input [4 :0] dp_frbus_ex2_fflags; 31 | input [31:0] fdsu_frbus_data; 32 | input [4 :0] fdsu_frbus_fflags; 33 | input fdsu_frbus_wb_vld; 34 | output [31:0] fpu_idu_fwd_data; 35 | output [4 :0] fpu_idu_fwd_fflags; 36 | output fpu_idu_fwd_vld; 37 | 38 | reg [31:0] frbus_wb_data; 39 | reg [4 :0] frbus_wb_fflags; 40 | 41 | wire ctrl_frbus_ex2_wb_req; 42 | wire [31:0] fdsu_frbus_data; 43 | wire [4 :0] fdsu_frbus_fflags; 44 | wire fdsu_frbus_wb_vld; 45 | wire [31:0] fpu_idu_fwd_data; 46 | wire [4 :0] fpu_idu_fwd_fflags; 47 | wire fpu_idu_fwd_vld; 48 | wire frbus_ex2_wb_vld; 49 | wire frbus_fdsu_wb_vld; 50 | wire frbus_wb_vld; 51 | wire [3 :0] frbus_source_vld; 52 | 53 | 54 | //========================================================== 55 | // Input Signal Rename 56 | //========================================================== 57 | assign frbus_fdsu_wb_vld = fdsu_frbus_wb_vld; 58 | assign frbus_ex2_wb_vld = ctrl_frbus_ex2_wb_req; 59 | assign frbus_source_vld[3:0] = {1'b0, 1'b0, frbus_ex2_wb_vld, frbus_fdsu_wb_vld}; 60 | assign frbus_wb_vld = frbus_ex2_wb_vld | frbus_fdsu_wb_vld; 61 | 62 | always @( frbus_source_vld[3:0] 63 | or fdsu_frbus_data[31:0] 64 | or dp_frbus_ex2_data[31:0] 65 | or fdsu_frbus_fflags[4:0] 66 | or dp_frbus_ex2_fflags[4:0]) 67 | begin 68 | case(frbus_source_vld[3:0]) 69 | 4'b0001: begin // DIV 70 | frbus_wb_data[31:0] = fdsu_frbus_data[31:0]; 71 | frbus_wb_fflags[4:0] = fdsu_frbus_fflags[4:0]; 72 | end 73 | 4'b0010: begin // EX2 74 | frbus_wb_data[31:0] = dp_frbus_ex2_data[31:0]; 75 | frbus_wb_fflags[4:0] = dp_frbus_ex2_fflags[4:0]; 76 | end 77 | default: begin 78 | frbus_wb_data[31:0] = {31{1'b0}}; 79 | frbus_wb_fflags[4:0] = 5'b0; 80 | end 81 | endcase 82 | end 83 | 84 | assign fpu_idu_fwd_vld = frbus_wb_vld; 85 | assign fpu_idu_fwd_fflags[4:0] = frbus_wb_fflags[4:0]; 86 | assign fpu_idu_fwd_data[31:0] = frbus_wb_data[31:0]; 87 | 88 | endmodule 89 | 90 | 91 | -------------------------------------------------------------------------------- /vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v: -------------------------------------------------------------------------------- 1 | /*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // &ModuleBeg; @24 17 | module pa_fpu_src_type( 18 | inst_double, 19 | inst_single, 20 | src_cnan, 21 | src_id, 22 | src_in, 23 | src_inf, 24 | src_norm, 25 | src_qnan, 26 | src_snan, 27 | src_zero 28 | ); 29 | 30 | // &Ports; @25 31 | input inst_double; 32 | input inst_single; 33 | input [63:0] src_in; 34 | output src_cnan; 35 | output src_id; 36 | output src_inf; 37 | output src_norm; 38 | output src_qnan; 39 | output src_snan; 40 | output src_zero; 41 | 42 | // &Regs; @26 43 | 44 | // &Wires; @27 45 | wire inst_double; 46 | wire inst_single; 47 | wire [63:0] src; 48 | wire src_cnan; 49 | wire src_expn_max; 50 | wire src_expn_zero; 51 | wire src_frac_msb; 52 | wire src_frac_zero; 53 | wire src_id; 54 | wire [63:0] src_in; 55 | wire src_inf; 56 | wire src_norm; 57 | wire src_qnan; 58 | wire src_snan; 59 | wire src_zero; 60 | 61 | 62 | // &Depend("cpu_cfig.h"); @29 63 | assign src[63:0] = src_in[63:0]; 64 | 65 | assign src_cnan = !(&src[63:32]) && inst_single; 66 | 67 | assign src_expn_zero = !(|src[62:52]) && inst_double || 68 | !(|src[30:23]) && inst_single; 69 | 70 | assign src_expn_max = (&src[62:52]) && inst_double || 71 | (&src[30:23]) && inst_single; 72 | 73 | assign src_frac_zero = !(|src[51:0]) && inst_double || 74 | !(|src[22:0]) && inst_single; 75 | 76 | assign src_frac_msb = src[51] && inst_double || src[22] && inst_single; 77 | 78 | assign src_snan = src_expn_max && !src_frac_msb && !src_frac_zero && !src_cnan; 79 | assign src_qnan = src_expn_max && src_frac_msb || src_cnan; 80 | assign src_zero = src_expn_zero && src_frac_zero && !src_cnan; 81 | assign src_id = src_expn_zero && !src_frac_zero && !src_cnan; 82 | assign src_inf = src_expn_max && src_frac_zero && !src_cnan; 83 | assign src_norm =!(src_expn_zero && src_frac_zero) && 84 | ! src_expn_max && !src_cnan; 85 | 86 | // &Force("output","src_cnan"); @53 87 | 88 | // &ModuleEnd; @55 89 | endmodule 90 | 91 | 92 | 93 | -------------------------------------------------------------------------------- /vendor/opene906/LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /vendor/opene906/README.md: -------------------------------------------------------------------------------- 1 | # IP Readme 2 | 3 | Welcome to E906! Some key directories are shown below. 4 | ``` 5 | |--E906_RTL_FACRORY/ 6 | |--gen_rtl/ ##the source verilog code of E906 7 | |--setup/ ##set the environment variables 8 | |--smart_run/ ##the RTL simulation environment 9 | |--impl/ ##sdc file 10 | |--logical/ ##the SoC demo and test bench to run the simulation 11 | |--setup/ ##GNU tool chain setting 12 | |--tests/ ##include the test suit, linker file, boot code and so on 13 | |--work/ ##the working directory 14 | |--Makefile ##the simulation script 15 | |--doc/ ##the user and integration manual of E906 16 | ``` 17 | 18 | 19 | ## Usage 20 | 21 | Step1: Get Started 22 | 23 | ``` 24 | $ cd E906_RTL_FACTORY 25 | $ source setup/setup.csh 26 | $ cd ../smart_run 27 | $ make help 28 | To gain more information about how to use smart testbench. 29 | ``` 30 | 31 | 32 | Step2: Download and install C/C++ Compiler 33 | 34 | ``` 35 | You can download the GNU tool chain compiled by T-HEAD from the url below: 36 | https://occ.t-head.cn/community/download?id=3948120165480468480 37 | 38 | $ cd ./smart_run 39 | GNU tool chain (specific riscv version) must be installed and specified before 40 | compiling *.c/*.v tests of the smart environment. Please refer to the following 41 | setup file about how to specify it: 42 | ./smart_run/setup/example_setup.csh 43 | ``` 44 | 45 | 46 | ## Notes 47 | 48 | ``` 49 | The testbench supports iverilog, vcs and irun to run simulation and you can use Gtkwave or verdi 50 | to open the waveform under ./smart_run/work/ directory. 51 | 52 | You can get the debugger, IDE and SDK from the url:https://occ.t-head.cn/community/download?id=575997419775328256 53 | ``` 54 | 55 | 56 | ## Discussion 57 | If you are interested in participating in discussions or improving the "openXuantie" cores, you can scan the DingDing QR code below to join the discussion group. 58 | 59 | 60 | 61 | #/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. 62 | # 63 | #Licensed under the Apache License, Version 2.0 (the "License"); 64 | #you may not use this file except in compliance with the License. 65 | #You may obtain a copy of the License at 66 | # 67 | ### http://www.apache.org/licenses/LICENSE-2.0 68 | # 69 | #Unless required by applicable law or agreed to in writing, software 70 | #distributed under the License is distributed on an "AS IS" BASIS, 71 | #WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 72 | #See the License for the specific language governing permissions and 73 | #limitations under the License. 74 | #*/ 75 | 76 | -------------------------------------------------------------------------------- /vendor/patches/opene906/0001-Patch-pa_fdsu_prepare.patch: -------------------------------------------------------------------------------- 1 | From 37d26413e3bb82a79073bd036677fa653f0bb540 Mon Sep 17 00:00:00 2001 2 | From: Luca Bertaccini 3 | Date: Thu, 9 Mar 2023 12:17:22 +0100 4 | Subject: [PATCH] Patch pa_fdsu_prepare 5 | 6 | --- 7 | E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v | 6 ++---- 8 | 1 file changed, 2 insertions(+), 4 deletions(-) 9 | 10 | diff --git a/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v b/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v 11 | index 56d179b..f7bc5d2 100644 12 | --- a/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v 13 | +++ b/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v 14 | @@ -122,12 +122,10 @@ wire [59:0] sqrt_remainder; 15 | wire sqrt_sign; 16 | 17 | 18 | -parameter FLEN = `FLEN; 19 | - 20 | assign ex1_sqrt = idu_fpu_ex1_func[0]; 21 | assign ex1_div = idu_fpu_ex1_func[1]; 22 | -assign ex1_oper0[63:0] = {32'b0, idu_fpu_ex1_srcf0[FLEN-1:0] & {32{fdsu_ex1_sel}}}; 23 | -assign ex1_oper1[63:0] = {32'b0, idu_fpu_ex1_srcf1[FLEN-1:0] & {32{fdsu_ex1_sel}}}; 24 | +assign ex1_oper0[63:0] = {32'b0, idu_fpu_ex1_srcf0[31:0] & {32{fdsu_ex1_sel}}}; 25 | +assign ex1_oper1[63:0] = {32'b0, idu_fpu_ex1_srcf1[31:0] & {32{fdsu_ex1_sel}}}; 26 | assign ex1_double = 1'b0; 27 | assign ex1_single = 1'b1; 28 | // &Force("bus", "idu_fpu_ex1_func", 9, 0); @43 29 | -- 30 | 2.16.5 31 | 32 | --------------------------------------------------------------------------------