├── LICENSE ├── README.md ├── adv2eth.hex ├── adv2eth.py ├── adv2eth ├── .cproject ├── .mrs │ ├── adv2eth.mrs-workspace │ └── launch.json ├── .project ├── .settings │ └── language.settings.xml ├── .template ├── APP │ ├── app_drv_fifo.c │ ├── ch32v20x_it.c │ ├── eth.c │ ├── include │ │ ├── app_drv_fifo.h │ │ ├── ch32v20x_conf.h │ │ ├── ch32v20x_it.h │ │ ├── eth.h │ │ ├── net_config.h │ │ ├── observer.h │ │ ├── peripheral.h │ │ └── system_ch32v20x.h │ ├── main.c │ ├── observer.c │ └── system_ch32v20x.c ├── HAL │ ├── KEY.c │ ├── LED.c │ ├── Link.ld │ ├── MCU.c │ ├── RTC.c │ ├── SLEEP.c │ └── include │ │ ├── HAL.h │ │ ├── KEY.h │ │ ├── LED.h │ │ ├── RTC.h │ │ ├── SLEEP.h │ │ └── config.h ├── LIB │ ├── ble_task_scheduler.S │ ├── libwchble.a │ ├── wchble.h │ ├── wchble_rom.h │ └── wchble_rom.hex ├── NetLib │ ├── eth_driver.c │ ├── eth_driver.h │ ├── libwchnet.a │ └── wchnet.h ├── SRC │ ├── Core │ │ ├── core_riscv.c │ │ └── core_riscv.h │ ├── Debug │ │ ├── debug.c │ │ └── debug.h │ ├── Ld │ │ └── Link.ld │ ├── Peripheral │ │ ├── inc │ │ │ ├── ch32v20x.h │ │ │ ├── ch32v20x_adc.h │ │ │ ├── ch32v20x_bkp.h │ │ │ ├── ch32v20x_can.h │ │ │ ├── ch32v20x_crc.h │ │ │ ├── ch32v20x_dbgmcu.h │ │ │ ├── ch32v20x_dma.h │ │ │ ├── ch32v20x_exti.h │ │ │ ├── ch32v20x_flash.h │ │ │ ├── ch32v20x_gpio.h │ │ │ ├── ch32v20x_i2c.h │ │ │ ├── ch32v20x_iwdg.h │ │ │ ├── ch32v20x_misc.h │ │ │ ├── ch32v20x_opa.h │ │ │ ├── ch32v20x_pwr.h │ │ │ ├── ch32v20x_rcc.h │ │ │ ├── ch32v20x_rtc.h │ │ │ ├── ch32v20x_spi.h │ │ │ ├── ch32v20x_tim.h │ │ │ ├── ch32v20x_usart.h │ │ │ ├── ch32v20x_usb.h │ │ │ └── ch32v20x_wwdg.h │ │ └── src │ │ │ ├── ch32v20x_adc.c │ │ │ ├── ch32v20x_bkp.c │ │ │ ├── ch32v20x_can.c │ │ │ ├── ch32v20x_crc.c │ │ │ ├── ch32v20x_dbgmcu.c │ │ │ ├── ch32v20x_dma.c │ │ │ ├── ch32v20x_exti.c │ │ │ ├── ch32v20x_flash.c │ │ │ ├── ch32v20x_gpio.c │ │ │ ├── ch32v20x_i2c.c │ │ │ ├── ch32v20x_iwdg.c │ │ │ ├── ch32v20x_misc.c │ │ │ ├── ch32v20x_opa.c │ │ │ ├── ch32v20x_pwr.c │ │ │ ├── ch32v20x_rcc.c │ │ │ ├── ch32v20x_rtc.c │ │ │ ├── ch32v20x_spi.c │ │ │ ├── ch32v20x_tim.c │ │ │ ├── ch32v20x_usart.c │ │ │ └── ch32v20x_wwdg.c │ └── Startup │ │ └── startup_ch32v20x_D8W.S ├── adv2eth.launch └── adv2eth.wvproj └── img └── CH32V208WBU6-EVT-R0.jpg /LICENSE: -------------------------------------------------------------------------------- 1 | SOURCE LICENSE: 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining 4 | a copy of this software and associated documentation files (the "Software"), 5 | to deal in the Software without restriction, including without limitation the 6 | rights to use, copy, modify, merge, publish, distribute, sublicense, 7 | and/or sell copies of the Software. 8 | 9 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 10 | INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 11 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 13 | WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 14 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 15 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # WCHBLE2ETH 2 | BLE Advertisements Repeater into Ethernet TCP/IP 3 | 4 | Проект в начальной разработке... 5 | 6 | Чип CH32V208W. 7 | 8 | Demo-board от WCH - CH32V208WBU6-EVT-R0: 9 | 10 | ![img](https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/master/img/CH32V208WBU6-EVT-R0.jpg) 11 | 12 | CH32V208W принимает BLE-рекламу и отправляет в TCP/IP сокет. 13 | 14 | * Принимаются все типы BLE-реклам, включая "LE Long Range" (CODED PHY). 15 | * Обеспечивает прием более 60 реклам в секунду. 16 | * Используется DHCP. 17 | * Порт сервера TCP/IP сокета устройства - 1000. 18 | 19 | ## Формат TCP потока 20 | 21 | Передача принятых фреймов BLE-реклам стартует при соединении с сокетом устройства (порт с номером 1000). 22 | Фреймы передаются друг за дургом. 23 | 24 | |N байта | Информация| 25 | |---|---| 26 | | 0 | размер структуры данных BLE рекламы | 27 | | 1 | [0:3] GAP Advertising Report Event Types, [4:7] GAP Address type | 28 | | 2 | [0:3] primary PHY, [4:7] secondary PHY | 29 | | 3 | RSSI | 30 | | 4..9 | MAC | 31 | | 10.. | структура данных BLE рекламы | 32 | 33 | Первый байт, с номером 0, равен размеру всего фрейма минус 10. 34 | 35 | | ID | GAP Advertising Report Event Types | 36 | |--- |--- | 37 | | 0x00 | Connectable undirected advertisement | 38 | | 0x01 | Connectable directed advertisement | 39 | | 0x02 | Scannable undirected advertisement | 40 | | 0x03 | Non-Connectable undirected advertisement | 41 | | 0x04 | Scan Response | 42 | | 0x05 | Extend Connectable directed report type | 43 | | 0x06 | Extend Scannable undirected report type | 44 | | 0x07 | Extend Non-Connectable and Non-Scannable undirected report type | 45 | | 0x08 | Extend Connectable undirected report type | 46 | | 0x09 | Extend Scannable directed report type | 47 | | 0x0A | Extend Non-Connectable and Non-Scannable directed report type | 48 | | 0x0B | Eextend Scan Response report type | 49 | 50 | | ID | GAP Address type | 51 | |--- |--- | 52 | | 0x00 | Public address | 53 | | 0x01 | Static address | 54 | | 0x02 | Generate Non-Resolvable Private Address | 55 | | 0x03 | Generate Resolvable Private Address | 56 | 57 | | ID | Primary/Secondary PHY | 58 | |--- |--- | 59 | | 0x01 | 1M | 60 | | 0x02 | 2M | 61 | | 0x03 | Coded | 62 | 63 | ## Демонстрационный adv2eth.py 64 | 65 | Производит соединение с устройством WCHBLE2ETH и распечатывает приемный поток. 66 | 67 | Параметром задается IP адрес или URL устройства WCHBLE2ETH в сети. 68 | 69 | Пример: 70 | 71 | ``` 72 | python3 adv2eth.py 192.168.2.134 73 | ``` 74 | 75 | Лог: 76 | ``` 77 | Press 'ESC' to exit 78 | Connecting to 192.168.2.134 ... 79 | 00 11 bb a4c138565870 02010612161a1870585638c1a42d0663125c091cab0e 80 | 00 11 b6 a4c138565870 02010612161a1870585638c1a42d0663125c091cab0e 81 | 00 11 ac 1c90ffdc0cc6 020106030201a2141601a201d3496059d9146eded9e4d956127b7b6f 82 | 23 11 cc 1b18fbd1b5d6 1eff0600010920068c32d352e9e632c900aef72af1f0e7d8ebb185b080ed38 83 | 00 11 b7 381f8dd93b3a 020106030201a2141601a201ca55525ec10fca3811cab285e0b6b66c 84 | 32 11 cb 60419a85a1b6 0303f3fe 85 | 08 33 af a4c138ae3ebf 0201060e16d2fc40002c01470202f70393140b095448535f414533454246 86 | 00 11 d0 381f8dd93cb6 020106030201a2141601a2016db2d52cd37c86fa958e84fb795ead4e 87 | ... 88 | ``` 89 | 90 | 91 | ## Сборка проекта 92 | 93 | Для сборки проекта используйте импорт в [MounRiver Studio](http://mounriver.com). 94 | -------------------------------------------------------------------------------- /adv2eth.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # adv2ethernet.py 17.02.2024 pvvx # 4 | 5 | import sys 6 | import socket 7 | from pynput import keyboard 8 | 9 | def on_press(key): 10 | if key == keyboard.Key.esc: 11 | return False 12 | 13 | def main(): 14 | if(len(sys.argv) < 2): 15 | print("Usage: adv2eth ") 16 | sys.exit(1) 17 | if(sys.argv[1] == "-h"): 18 | print("Usage: adv2eth ") 19 | sys.exit(0) 20 | print("Press 'ESC' to exit") 21 | print ('Connecting to '+sys.argv[1]+' ...') 22 | sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM) # Create a TCP/IP socket 23 | sock.connect((sys.argv[1],1000)) # connect to the server 24 | data = bytes(0) 25 | with keyboard.Listener(on_press=on_press) as listener: 26 | while listener.running: 27 | data += sock.recv(1460*2) # TCP MSS * 2 receive response 28 | #print('Received from server: %d' % len(data)) 29 | while(data[0] + 10 < len(data)): 30 | l = data[0] 31 | evt = data[1:2].hex() 32 | adt = data[2:3].hex() 33 | rssi = data[3:4].hex() 34 | xmac = bytes([data[9], data[8], data[7], data[6], data[5], data[4]]) 35 | mac = xmac.hex() 36 | dump = data[10:l+10].hex() 37 | print(evt, adt, rssi, mac, dump) 38 | data = data[l + 10:] 39 | sock.close() # close the connection 40 | sys.exit(0) 41 | 42 | if __name__ == '__main__': 43 | main() 44 | -------------------------------------------------------------------------------- /adv2eth/.mrs/adv2eth.mrs-workspace: -------------------------------------------------------------------------------- 1 | { 2 | "folders": [ 3 | { 4 | "path": "." 5 | }, 6 | { 7 | "name": "adv2eth", 8 | "path": "../" 9 | } 10 | ], 11 | "settings": { 12 | "mrs.workspace.type": "project", 13 | "files.associations": { 14 | "*.c": "c", 15 | "*.h": "cpp", 16 | "*.hxx": "cpp", 17 | "*.hpp": "cpp", 18 | "*.c++": "cpp", 19 | "*.cpp": "cpp", 20 | "*.cxx": "cpp", 21 | "*.cc": "cpp", 22 | "*.hh": "cpp", 23 | "*.h++": "cpp" 24 | } 25 | } 26 | } -------------------------------------------------------------------------------- /adv2eth/.mrs/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "0.2.0", 3 | "configurations": [ 4 | { 5 | "type": "mrs-debugger", 6 | "request": "launch", 7 | "name": "adv2eth", 8 | "cwd": "e:\\WCH\\wk2\\adv2eth", 9 | "openOCDCfg": { 10 | "useLocalOpenOCD": true, 11 | "executable": "d:/MCU/MounRiver_Studio2/resources/app/resources/win32/components/WCH/OpenOCD/OpenOCD/bin/openocd.exe", 12 | "configOptions": [ 13 | "-f \"d:/MCU/MounRiver_Studio2/resources/app/resources/win32/components/WCH/OpenOCD/OpenOCD/bin/wch-riscv.cfg\" -c \"chip_id CH32V20x\"" 14 | ], 15 | "gdbport": 3333, 16 | "telnetport": 4444, 17 | "tclport": 6666, 18 | "host": "localhost", 19 | "port": 3333, 20 | "skipDownloadBeforeDebug": false, 21 | "enablePageEraser": false, 22 | "enableNoZeroWaitingAreaFlash": false 23 | }, 24 | "gdbCfg": { 25 | "executable": "d:/MCU/MounRiver_Studio2/resources/app/resources/win32/components/WCH/Toolchain/RISC-V Embedded GCC/bin/riscv-none-embed-gdb.exe", 26 | "commands": [ 27 | "set mem inaccessible-by-default off", 28 | "set architecture riscv:rv32", 29 | "set remotetimeout unlimited", 30 | "set disassembler-options xw" 31 | ], 32 | "options": [] 33 | }, 34 | "startup": { 35 | "initCommands": { 36 | "initReset": true, 37 | "initResetType": "init", 38 | "armSemihosting": false, 39 | "additionalCommands": [] 40 | }, 41 | "loadedFiles": { 42 | "executableFile": "e:\\WCH\\wk2\\adv2eth\\obj\\adv2eth.elf", 43 | "symbolFile": "e:\\WCH\\wk2\\adv2eth\\obj\\adv2eth.elf", 44 | "executableFileOffset": 0, 45 | "symbolFileOffset": 0 46 | }, 47 | "runCommands": { 48 | "runReset": true, 49 | "runResetType": "halt", 50 | "additionalCommands": [], 51 | "setBreakAt": "handle_reset", 52 | "continue": true, 53 | "setProgramCounterAt": 0 54 | }, 55 | "debugInRAM": false 56 | }, 57 | "svdpath": "d:\\MCU\\MounRiver_Studio2\\resources\\app\\resources\\win32\\components\\WCH\\SDK\\default/RISC-V/CH32V208/NoneOS/CH32V208xx.svd", 58 | "output": { 59 | "showDebugGDBTrace": true, 60 | "saveDebugOutputToFile": false, 61 | "showDebugOutputTimestamps": true 62 | } 63 | } 64 | ] 65 | } -------------------------------------------------------------------------------- /adv2eth/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | adv2eth 4 | 5 | 6 | 7 | 8 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 9 | clean,full,incremental, 10 | 11 | 12 | 13 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 14 | full,incremental, 15 | 16 | 17 | 18 | 19 | org.eclipse.cdt.core.cnature 20 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 21 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 22 | 23 | 24 | 25 | 26 | 27 | 6 28 | 29 | org.eclipse.ui.ide.multiFilter 30 | 1.0-name-matches-false-false-*.wvproj 31 | 32 | 33 | 34 | SRC/Startup 35 | 6 36 | 37 | org.eclipse.ui.ide.multiFilter 38 | 1.0-name-matches-false-false-startup_ch32v20x_D6.S 39 | 40 | 41 | 42 | SRC/Startup 43 | 6 44 | 45 | org.eclipse.ui.ide.multiFilter 46 | 1.0-name-matches-false-false-startup_ch32v20x_D8.S 47 | 48 | 49 | 50 | -------------------------------------------------------------------------------- /adv2eth/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /adv2eth/.template: -------------------------------------------------------------------------------- 1 | Vendor=WCH 2 | Toolchain=RISC-V 3 | Series=CH32V208 4 | RTOS=NoneOS 5 | MCU=CH32V208WBU6 6 | Link=WCH-Link 7 | PeripheralVersion=2.2 8 | Description=Website: http://www.wch.cn/products/CH32V208.html?\nROM(byte): 160K, SRAM(byte): 32K, CHIP PINS: 68, GPIO PORTS: 54.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. 9 | Mcu Type=CH32V20x 10 | Address=0x08000000 11 | Target Path=obj/adv2eth.hex 12 | Exe Path= 13 | Exe Arguments= 14 | CLKSpeed=1 15 | DebugInterfaceMode=0 16 | Erase All=true 17 | Program=true 18 | Verify=true 19 | Reset=true 20 | SDIPrintf=false 21 | Disable Power Output=false 22 | Clear CodeFlash=false 23 | Disable Code-Protect=false -------------------------------------------------------------------------------- /adv2eth/APP/app_drv_fifo.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : app_drv_fifo.c 3 | * Author : WCH 4 | * Version : V1.1 5 | * Date : 2022/01/19 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #include "app_drv_fifo.h" 14 | 15 | static __inline uint16_t fifo_length(app_drv_fifo_t *fifo) 16 | { 17 | uint16_t tmp = fifo->begin; 18 | return fifo->end - tmp; 19 | } 20 | 21 | uint16_t app_drv_fifo_length(app_drv_fifo_t *fifo) 22 | { 23 | return fifo_length(fifo); 24 | } 25 | 26 | app_drv_fifo_result_t 27 | app_drv_fifo_init(app_drv_fifo_t *fifo, uint8_t *buffer, uint16_t buffer_size) 28 | { 29 | if(buffer_size == 0) 30 | { 31 | return APP_DRV_FIFO_RESULT_LENGTH_ERROR; 32 | } 33 | if(0 != ((buffer_size) & (buffer_size - 1))) 34 | { 35 | return APP_DRV_FIFO_RESULT_LENGTH_ERROR; 36 | } 37 | fifo->begin = 0; 38 | fifo->end = 0; 39 | fifo->data = buffer; 40 | fifo->size = buffer_size; 41 | fifo->size_mask = buffer_size - 1; 42 | return APP_DRV_FIFO_RESULT_SUCCESS; 43 | } 44 | 45 | void app_drv_fifo_push(app_drv_fifo_t *fifo, uint8_t data) 46 | { 47 | fifo->data[fifo->end & fifo->size_mask] = data; 48 | fifo->end++; 49 | } 50 | 51 | uint8_t app_drv_fifo_pop(app_drv_fifo_t *fifo) 52 | { 53 | uint8_t data = fifo->data[fifo->begin & fifo->size_mask]; 54 | fifo->begin++; 55 | return data; 56 | } 57 | 58 | void app_drv_fifo_flush(app_drv_fifo_t *fifo) 59 | { 60 | fifo->begin = 0; 61 | fifo->end = 0; 62 | } 63 | 64 | bool app_drv_fifo_is_empty(app_drv_fifo_t *fifo) 65 | { 66 | return (fifo->begin == fifo->end); 67 | } 68 | 69 | bool app_drv_fifo_is_full(app_drv_fifo_t *fifo) 70 | { 71 | return (fifo_length(fifo) == fifo->size); 72 | } 73 | 74 | app_drv_fifo_result_t 75 | app_drv_fifo_write(app_drv_fifo_t *fifo, uint8_t *data, uint16_t *p_write_length) 76 | { 77 | if(fifo == NULL) 78 | { 79 | return APP_DRV_FIFO_RESULT_NULL; 80 | } 81 | if(p_write_length == NULL) 82 | { 83 | return APP_DRV_FIFO_RESULT_NULL; 84 | } 85 | //PRINT("fifo_length = %d\r\n",fifo_length(fifo)); 86 | const uint16_t available_count = fifo->size - fifo_length(fifo); 87 | const uint16_t requested_len = (*p_write_length); 88 | uint16_t index = 0; 89 | uint16_t write_size = MIN(requested_len, available_count); 90 | //PRINT("available_count %d\r\n",available_count); 91 | // Check if the FIFO is FULL. 92 | if(available_count == 0) 93 | { 94 | return APP_DRV_FIFO_RESULT_NOT_MEM; 95 | } 96 | 97 | // Check if application has requested only the size. 98 | if(data == NULL) 99 | { 100 | return APP_DRV_FIFO_RESULT_SUCCESS; 101 | } 102 | 103 | for(index = 0; index < write_size; index++) 104 | { 105 | //push 106 | fifo->data[fifo->end & fifo->size_mask] = data[index]; 107 | fifo->end++; 108 | } 109 | (*p_write_length) = write_size; 110 | return APP_DRV_FIFO_RESULT_SUCCESS; 111 | } 112 | 113 | app_drv_fifo_result_t 114 | app_drv_fifo_write_from_same_addr(app_drv_fifo_t *fifo, uint8_t *data, uint16_t write_length) 115 | { 116 | if(fifo == NULL) 117 | { 118 | return APP_DRV_FIFO_RESULT_NULL; 119 | } 120 | const uint16_t available_count = fifo->size_mask - fifo_length(fifo) + 1; 121 | const uint16_t requested_len = (write_length); 122 | uint16_t index = 0; 123 | uint16_t write_size = MIN(requested_len, available_count); 124 | 125 | // Check if the FIFO is FULL. 126 | if(available_count == 0) 127 | { 128 | return APP_DRV_FIFO_RESULT_NOT_MEM; 129 | } 130 | 131 | for(index = 0; index < write_size; index++) 132 | { 133 | //push 134 | fifo->data[fifo->end & fifo->size_mask] = data[0]; 135 | fifo->end++; 136 | } 137 | return APP_DRV_FIFO_RESULT_SUCCESS; 138 | } 139 | 140 | app_drv_fifo_result_t 141 | app_drv_fifo_read(app_drv_fifo_t *fifo, uint8_t *data, uint16_t *p_read_length) 142 | { 143 | if(fifo == NULL) 144 | { 145 | return APP_DRV_FIFO_RESULT_NULL; 146 | } 147 | if(p_read_length == NULL) 148 | { 149 | return APP_DRV_FIFO_RESULT_NULL; 150 | } 151 | const uint16_t byte_count = fifo_length(fifo); 152 | const uint16_t requested_len = (*p_read_length); 153 | uint32_t index = 0; 154 | uint32_t read_size = MIN(requested_len, byte_count); 155 | 156 | if(byte_count == 0) 157 | { 158 | return APP_DRV_FIFO_RESULT_NOT_FOUND; 159 | } 160 | //PRINT("read size = %d,byte_count = %d\r\n",read_size,byte_count); 161 | for(index = 0; index < read_size; index++) 162 | { 163 | //pop 164 | data[index] = fifo->data[fifo->begin & fifo->size_mask]; 165 | fifo->begin++; 166 | } 167 | 168 | (*p_read_length) = read_size; 169 | return APP_DRV_FIFO_RESULT_SUCCESS; 170 | } 171 | 172 | app_drv_fifo_result_t 173 | app_drv_fifo_read_to_same_addr(app_drv_fifo_t *fifo, uint8_t *data, uint16_t read_length) 174 | { 175 | if(fifo == NULL) 176 | { 177 | return APP_DRV_FIFO_RESULT_NULL; 178 | } 179 | const uint16_t byte_count = fifo_length(fifo); 180 | const uint16_t requested_len = (read_length); 181 | uint32_t index = 0; 182 | uint32_t read_size = MIN(requested_len, byte_count); 183 | 184 | for(index = 0; index < read_size; index++) 185 | { 186 | //pop 187 | data[0] = fifo->data[fifo->begin & fifo->size_mask]; 188 | fifo->begin++; 189 | } 190 | return APP_DRV_FIFO_RESULT_SUCCESS; 191 | } 192 | -------------------------------------------------------------------------------- /adv2eth/APP/ch32v20x_it.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_it.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/06/16 6 | * Description : Main Interrupt Service Routines. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /********************************************************************* 14 | * INCLUDES 15 | */ 16 | #include "ch32v20x_it.h" 17 | #include "CONFIG.h" 18 | #include "wchnet.h" 19 | #include "eth_driver.h" 20 | 21 | /********************************************************************* 22 | * LOCAL FUNCTIONS 23 | */ 24 | void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 25 | void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 26 | void BB_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 27 | void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 28 | void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 29 | 30 | /********************************************************************* 31 | * @fn NMI_Handler 32 | * 33 | * @brief This function handles NMI exception. 34 | * 35 | * @return None 36 | */ 37 | void NMI_Handler(void) 38 | { 39 | } 40 | 41 | /********************************************************************* 42 | * @fn HardFault_Handler 43 | * 44 | * @brief This function handles Hard Fault exception. 45 | * 46 | * @return None 47 | */ 48 | void HardFault_Handler(void) 49 | { 50 | while(1) 51 | { 52 | } 53 | } 54 | 55 | /********************************************************************* 56 | * @fn ETH_IRQHandler 57 | * 58 | * @brief This function handles ETH exception. 59 | * 60 | * @return none 61 | */ 62 | void ETH_IRQHandler(void) 63 | { 64 | WCHNET_ETHIsr(); 65 | } 66 | 67 | /********************************************************************* 68 | * @fn TIM2_IRQHandler 69 | * 70 | * @brief This function handles TIM2 exception. 71 | * 72 | * @return none 73 | */ 74 | void TIM2_IRQHandler(void) 75 | { 76 | WCHNET_TimeIsr(WCHNETTIMERPERIOD); 77 | TIM_ClearITPendingBit(TIM2, TIM_IT_Update); 78 | } 79 | 80 | /********************************************************************* 81 | * @fn BB_IRQHandler 82 | * 83 | * @brief BB Interrupt for BLE. 84 | * 85 | * @return None 86 | */ 87 | void BB_IRQHandler(void) 88 | { 89 | BB_IRQLibHandler(); 90 | } 91 | -------------------------------------------------------------------------------- /adv2eth/APP/include/app_drv_fifo.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : app_drv_fifo.h 3 | * Author : WCH 4 | * Version : V1.1 5 | * Date : 2022/01/19 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef __APP_DRV_FIFO_H__ 14 | #define __APP_DRV_FIFO_H__ 15 | 16 | #include 17 | #include 18 | 19 | #ifndef BV 20 | #define BV(n) (1 << (n)) 21 | #endif 22 | 23 | #ifndef BF 24 | #define BF(x, b, s) (((x) & (b)) >> (s)) 25 | #endif 26 | 27 | #ifndef MIN 28 | #define MIN(n, m) (((n) < (m)) ? (n) : (m)) 29 | #endif 30 | 31 | #ifndef MAX 32 | #define MAX(n, m) (((n) < (m)) ? (m) : (n)) 33 | #endif 34 | 35 | #ifndef ABS 36 | #define ABS(n) (((n) < 0) ? -(n) : (n)) 37 | #endif 38 | 39 | typedef enum 40 | { 41 | APP_DRV_FIFO_RESULT_SUCCESS = 0, 42 | APP_DRV_FIFO_RESULT_LENGTH_ERROR, 43 | APP_DRV_FIFO_RESULT_NOT_FOUND, 44 | APP_DRV_FIFO_RESULT_NOT_MEM, 45 | APP_DRV_FIFO_RESULT_NULL, 46 | 47 | } app_drv_fifo_result_t; 48 | 49 | #ifndef NULL 50 | #define NULL 0 51 | #endif 52 | 53 | /*! 54 | * FIFO structure 55 | */ 56 | typedef struct Fifo_s 57 | { 58 | uint16_t begin; 59 | uint16_t end; 60 | uint8_t *data; 61 | uint16_t size; 62 | uint16_t size_mask; 63 | } app_drv_fifo_t; 64 | 65 | //__inline uint16_t app_drv_fifo_length(app_drv_fifo_t *fifo); 66 | 67 | uint16_t app_drv_fifo_length(app_drv_fifo_t *fifo); 68 | 69 | /*! 70 | * Initializes the FIFO structure 71 | * 72 | * \param [IN] fifo Pointer to the FIFO object 73 | * \param [IN] buffer Buffer to be used as FIFO 74 | * \param [IN] size size of the buffer 75 | */ 76 | app_drv_fifo_result_t 77 | app_drv_fifo_init(app_drv_fifo_t *fifo, uint8_t *buffer, uint16_t buffer_size); 78 | 79 | /*! 80 | * Pushes data to the FIFO 81 | * 82 | * \param [IN] fifo Pointer to the FIFO object 83 | * \param [IN] data data to be pushed into the FIFO 84 | */ 85 | void app_drv_fifo_push(app_drv_fifo_t *fifo, uint8_t data); 86 | 87 | /*! 88 | * Pops data from the FIFO 89 | * 90 | * \param [IN] fifo Pointer to the FIFO object 91 | * \retval data data popped from the FIFO 92 | */ 93 | uint8_t app_drv_fifo_pop(app_drv_fifo_t *fifo); 94 | 95 | /*! 96 | * Flushes the FIFO 97 | * 98 | * \param [IN] fifo Pointer to the FIFO object 99 | */ 100 | void app_drv_fifo_flush(app_drv_fifo_t *fifo); 101 | 102 | /*! 103 | * Checks if the FIFO is empty 104 | * 105 | * \param [IN] fifo Pointer to the FIFO object 106 | * \retval isEmpty true: FIFO is empty, false FIFO is not empty 107 | */ 108 | bool app_drv_fifo_is_empty(app_drv_fifo_t *fifo); 109 | 110 | /*! 111 | * Checks if the FIFO is full 112 | * 113 | * \param [IN] fifo Pointer to the FIFO object 114 | * \retval isFull true: FIFO is full, false FIFO is not full 115 | */ 116 | bool app_drv_fifo_is_full(app_drv_fifo_t *fifo); 117 | 118 | app_drv_fifo_result_t 119 | app_drv_fifo_write(app_drv_fifo_t *fifo, uint8_t *data, 120 | uint16_t *p_write_length); 121 | 122 | app_drv_fifo_result_t 123 | app_drv_fifo_write_from_same_addr(app_drv_fifo_t *fifo, uint8_t *data, 124 | uint16_t write_length); 125 | 126 | app_drv_fifo_result_t 127 | app_drv_fifo_read(app_drv_fifo_t *fifo, uint8_t *data, uint16_t *p_read_length); 128 | 129 | app_drv_fifo_result_t 130 | app_drv_fifo_read_to_same_addr(app_drv_fifo_t *fifo, uint8_t *data, 131 | uint16_t read_length); 132 | 133 | #endif // __APP_DRV_FIFO_H__ 134 | -------------------------------------------------------------------------------- /adv2eth/APP/include/ch32v20x_conf.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_conf.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/06/16 6 | * Description : Library configuration file. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef __CH32V20x_CONF_H 14 | #define __CH32V20x_CONF_H 15 | 16 | #include "ch32v20x_adc.h" 17 | #include "ch32v20x_bkp.h" 18 | #include "ch32v20x_can.h" 19 | #include "ch32v20x_crc.h" 20 | #include "ch32v20x_dbgmcu.h" 21 | #include "ch32v20x_dma.h" 22 | #include "ch32v20x_exti.h" 23 | #include "ch32v20x_flash.h" 24 | #include "ch32v20x_gpio.h" 25 | #include "ch32v20x_i2c.h" 26 | #include "ch32v20x_iwdg.h" 27 | #include "ch32v20x_pwr.h" 28 | #include "ch32v20x_rcc.h" 29 | #include "ch32v20x_rtc.h" 30 | #include "ch32v20x_spi.h" 31 | #include "ch32v20x_tim.h" 32 | #include "ch32v20x_usart.h" 33 | #include "ch32v20x_wwdg.h" 34 | #include "ch32v20x_it.h" 35 | #include "ch32v20x_misc.h" 36 | 37 | #endif /* __CH32V20x_CONF_H */ 38 | -------------------------------------------------------------------------------- /adv2eth/APP/include/ch32v20x_it.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_it.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/06/16 6 | * Description : This file contains the headers of the interrupt handlers. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef __CH32V20x_IT_H 14 | #define __CH32V20x_IT_H 15 | 16 | #include "debug.h" 17 | 18 | #endif /* __CH32V20x_IT_H */ 19 | -------------------------------------------------------------------------------- /adv2eth/APP/include/eth.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : eth.h 3 | * Author : WCH 4 | * Version : V1.1 5 | * Date : 2021/11/18 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef eth_H 14 | #define eth_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | /********************************************************************* 21 | * INCLUDES 22 | */ 23 | 24 | /********************************************************************* 25 | * CONSTANTS 26 | */ 27 | 28 | // ETH Task Events 29 | #define ETH_SENG_DATA_EVENT 1<<1 30 | 31 | /********************************************************************* 32 | * MACROS 33 | */ 34 | 35 | /********************************************************************* 36 | * FUNCTIONS 37 | */ 38 | 39 | /* 40 | * eth_init 41 | */ 42 | extern void eth_init(void); 43 | 44 | /* 45 | * eth_process 46 | */ 47 | extern void eth_process(void); 48 | 49 | extern uint8_t eth_TaskID; 50 | extern uint8_t socket_connected; 51 | 52 | /********************************************************************* 53 | *********************************************************************/ 54 | 55 | #ifdef __cplusplus 56 | } 57 | #endif 58 | 59 | #endif 60 | -------------------------------------------------------------------------------- /adv2eth/APP/include/net_config.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : net_config.h 3 | * Author : WCH 4 | * Version : V1.30 5 | * Date : 2022/06/02 6 | * Description : This file contains the configurations of 7 | * Ethernet protocol stack library 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __NET_CONFIG_H__ 14 | #define __NET_CONFIG_H__ 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | /********************************************************************* 21 | * socket configuration, IPRAW + UDP + TCP + TCP_LISTEN = number of sockets 22 | */ 23 | #define WCHNET_NUM_IPRAW 0 /* Number of IPRAW connections */ 24 | 25 | #define WCHNET_NUM_UDP 1 /* The number of UDP connections */ 26 | 27 | #define WCHNET_NUM_TCP 1 /* Number of TCP connections (server + client) */ 28 | 29 | #define WCHNET_NUM_TCP_LISTEN 1 /* Number of TCP listening */ 30 | 31 | /* The number of sockets, the maximum is 31 */ 32 | #define WCHNET_MAX_SOCKET_NUM (WCHNET_NUM_IPRAW+WCHNET_NUM_UDP+WCHNET_NUM_TCP+WCHNET_NUM_TCP_LISTEN) 33 | 34 | #define WCHNET_TCP_MSS 1460 /* Size of TCP MSS*/ 35 | 36 | /********************************************************************* 37 | * MAC queue configuration 38 | */ 39 | #define ETH_TXBUFNB 1 /* The number of descriptors sent by the MAC */ 40 | 41 | #define ETH_RXBUFNB 4 /* Number of MAC received descriptors */ 42 | 43 | #ifndef ETH_MAX_PACKET_SIZE 44 | #define ETH_RX_BUF_SZE 1520 /* MAC receive buffer length, an integer multiple of 4 */ 45 | #define ETH_TX_BUF_SZE 1520 /* MAC send buffer length, an integer multiple of 4 */ 46 | #else 47 | #define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE 48 | #define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE 49 | #endif 50 | 51 | /********************************************************************* 52 | * Functional configuration 53 | */ 54 | #define WCHNET_PING_ENABLE 1 /* PING is enabled, PING is enabled by default */ 55 | 56 | #define TCP_RETRY_COUNT 20 /* The number of TCP retransmissions, the default value is 20 */ 57 | 58 | #define TCP_RETRY_PERIOD 10 /* TCP retransmission period, the default value is 10, the unit is 50ms */ 59 | 60 | #define SOCKET_SEND_RETRY 1 /* Send failed retry configuration, 1: enable, 0: disable */ 61 | 62 | #define CFG0_TCP_SEND_COPY 1 /* TCP send buffer copy, 1: copy, 0: not copy */ 63 | 64 | #define CFG0_TCP_RECV_COPY 1 /* TCP receive replication optimization, internal debugging use */ 65 | 66 | #define CFG0_TCP_OLD_DELETE 0 /* Delete oldest TCP connection, 1: enable, 0: disable */ 67 | 68 | /********************************************************************* 69 | * Memory related configuration 70 | */ 71 | /*If a single socket cannot reach full speed, 72 | * try to increase RECE_BUF_LEN to (WCHNET_TCP_MSS*4) 73 | * and increase WCHNET_NUM_TCP_SEG to (WCHNET_NUM_TCP*4)*/ 74 | #define RECE_BUF_LEN (WCHNET_TCP_MSS*2) /* socket receive buffer size */ 75 | 76 | #define WCHNET_NUM_PBUF (WCHNET_MAX_SOCKET_NUM+WCHNET_NUM_TCP) /* Number of PBUF structures */ 77 | 78 | #define WCHNET_NUM_TCP_SEG (WCHNET_NUM_TCP*2) /* The number of TCP segments used to send */ 79 | 80 | #define WCHNET_MEM_HEAP_SIZE (((WCHNET_TCP_MSS+0x10+54)*WCHNET_NUM_TCP_SEG)+ETH_TX_BUF_SZE+64) /* memory heap size */ 81 | 82 | #define WCHNET_NUM_ARP_TABLE 50 /* Number of ARP lists */ 83 | 84 | #define WCHNET_NUM_IP_REASSDATA 4 /* Number of IP segments */ 85 | 86 | #define CFG0_IP_REASS_PBUFS 4 /* Number of reassembled IP PBUFs */ 87 | 88 | #define WCHNET_MEM_ALIGNMENT 4 /* 4 byte alignment */ 89 | 90 | #define WCHNET_NUM_POOL_BUF (WCHNET_NUM_TCP*2+2) /* The number of POOL BUFs, the number of receive queues */ 91 | 92 | #define WCHNET_SIZE_POOL_BUF (((WCHNET_TCP_MSS + 40 + 14 + 4) + 3) & ~3) /* Buffer size for receiving a single packet */ 93 | 94 | /* Check the configuration of the SOCKET quantity */ 95 | #if( WCHNET_NUM_TCP_LISTEN && !WCHNET_NUM_TCP ) 96 | #error "WCHNET_NUM_TCP Error)" 97 | #endif 98 | /* Check byte alignment must be a multiple of 4 */ 99 | #if((WCHNET_MEM_ALIGNMENT % 4) || (WCHNET_MEM_ALIGNMENT == 0)) 100 | #error "WCHNET_MEM_ALIGNMENT Error,Please Config WCHNET_MEM_ALIGNMENT = 4 * N, N >=1" 101 | #endif 102 | /* TCP maximum segment length */ 103 | #if((WCHNET_TCP_MSS > 1460) || (WCHNET_TCP_MSS < 60)) 104 | #error "WCHNET_TCP_MSS Error,Please Config WCHNET_TCP_MSS >= 60 && WCHNET_TCP_MSS <= 1460" 105 | #endif 106 | /* Number of ARP cache tables */ 107 | #if((WCHNET_NUM_ARP_TABLE > 0X7F) || (WCHNET_NUM_ARP_TABLE < 1)) 108 | #error "WCHNET_NUM_ARP_TABLE Error,Please Config WCHNET_NUM_ARP_TABLE >= 1 && WCHNET_NUM_ARP_TABLE <= 0X7F" 109 | #endif 110 | /* Check POOL BUF configuration */ 111 | #if(WCHNET_NUM_POOL_BUF < 1) 112 | #error "WCHNET_NUM_POOL_BUF Error,Please Config WCHNET_NUM_POOL_BUF >= 1" 113 | #endif 114 | /* Check PBUF structure configuration */ 115 | #if(WCHNET_NUM_PBUF < 1) 116 | #error "WCHNET_NUM_PBUF Error,Please Config WCHNET_NUM_PBUF >= 1" 117 | #endif 118 | /* Check IP Assignment Configuration */ 119 | #if((WCHNET_NUM_IP_REASSDATA > 10) || (WCHNET_NUM_IP_REASSDATA < 1)) 120 | #error "WCHNET_NUM_IP_REASSDATA Error,Please Config WCHNET_NUM_IP_REASSDATA < 10 && WCHNET_NUM_IP_REASSDATA >= 1 " 121 | #endif 122 | /* Check the number of reassembled IP PBUFs */ 123 | #if(WCHNET_IP_REASS_PBUFS > WCHNET_NUM_POOL_BUF) 124 | #error "WCHNET_IP_REASS_PBUFS Error,Please Config WCHNET_IP_REASS_PBUFS < WCHNET_NUM_POOL_BUF" 125 | #endif 126 | 127 | #if(WCHNETTIMERPERIOD > 50) 128 | #error "WCHNETTIMERPERIOD Error,Please Config WCHNETTIMERPERIOD < 50" 129 | #endif 130 | 131 | /* Configuration value 0 */ 132 | #define WCHNET_MISC_CONFIG0 (((CFG0_TCP_SEND_COPY) << 0) |\ 133 | ((CFG0_TCP_RECV_COPY) << 1) |\ 134 | ((CFG0_TCP_OLD_DELETE) << 2) |\ 135 | ((CFG0_IP_REASS_PBUFS) << 3) ) 136 | /* Configuration value 1 */ 137 | #define WCHNET_MISC_CONFIG1 (((WCHNET_MAX_SOCKET_NUM)<<0)|\ 138 | ((WCHNET_PING_ENABLE) << 13) |\ 139 | ((TCP_RETRY_COUNT) << 14) |\ 140 | ((TCP_RETRY_PERIOD) << 19) |\ 141 | ((SOCKET_SEND_RETRY) << 25) ) 142 | 143 | #ifdef __cplusplus 144 | } 145 | #endif 146 | #endif 147 | -------------------------------------------------------------------------------- /adv2eth/APP/include/observer.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : observer.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2018/11/12 6 | * Description : The main function and task system of the observer application initialization 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef OBSERVER_H 14 | #define OBSERVER_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | /********************************************************************* 21 | * INCLUDES 22 | */ 23 | #include "app_drv_fifo.h" 24 | /********************************************************************* 25 | * CONSTANTS 26 | */ 27 | 28 | // Simple BLE Observer Task Events 29 | #define START_DEVICE_EVT 0x0001 30 | #define START_DISCOVERY_EVT 0x0002 31 | #define START_SCAN_EVT 0x0004 32 | 33 | /********************************************************************* 34 | * MACROS 35 | */ 36 | 37 | /********************************************************************* 38 | * FUNCTIONS 39 | */ 40 | 41 | /* 42 | * Task Initialization for the BLE Application 43 | */ 44 | extern void Observer_Init(void); 45 | 46 | /* 47 | * Task Event Processor for the BLE Application 48 | */ 49 | extern uint16_t Observer_ProcessEvent(uint8_t task_id, uint16_t events); 50 | 51 | extern app_drv_fifo_t app_tx_fifo; 52 | 53 | /********************************************************************* 54 | *********************************************************************/ 55 | 56 | #ifdef __cplusplus 57 | } 58 | #endif 59 | 60 | #endif /* OBSERVER_H */ 61 | -------------------------------------------------------------------------------- /adv2eth/APP/include/peripheral.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : peripheral.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2018/12/11 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef PERIPHERAL_H 14 | #define PERIPHERAL_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | /********************************************************************* 21 | * INCLUDES 22 | */ 23 | 24 | /********************************************************************* 25 | * CONSTANTS 26 | */ 27 | 28 | // Peripheral Task Events 29 | #define SBP_START_DEVICE_EVT 0x0001 30 | #define SBP_PERIODIC_EVT 0x0002 31 | #define SBP_READ_RSSI_EVT 0x0004 32 | #define SBP_PARAM_UPDATE_EVT 0x0008 33 | #define SBP_PHY_UPDATE_EVT 0x0010 34 | 35 | /********************************************************************* 36 | * MACROS 37 | */ 38 | typedef struct 39 | { 40 | uint16_t connHandle; // Connection handle of current connection 41 | uint16_t connInterval; 42 | uint16_t connSlaveLatency; 43 | uint16_t connTimeout; 44 | } peripheralConnItem_t; 45 | 46 | /********************************************************************* 47 | * FUNCTIONS 48 | */ 49 | 50 | /* 51 | * Task Initialization for the BLE Application 52 | */ 53 | extern void Peripheral_Init(void); 54 | 55 | /* 56 | * Task Event Processor for the BLE Application 57 | */ 58 | extern uint16_t Peripheral_ProcessEvent(uint8_t task_id, uint16_t events); 59 | 60 | /********************************************************************* 61 | *********************************************************************/ 62 | 63 | #ifdef __cplusplus 64 | } 65 | #endif 66 | 67 | #endif 68 | -------------------------------------------------------------------------------- /adv2eth/APP/include/system_ch32v20x.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : system_ch32v20x.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/06/16 6 | * Description : CH32V20x Device Peripheral Access Layer System Header File. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | #ifndef __SYSTEM_ch32v20x_H 14 | #define __SYSTEM_ch32v20x_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ 21 | 22 | /* System_Exported_Functions */ 23 | extern void SystemInit(void); 24 | extern void SystemCoreClockUpdate(void); 25 | 26 | 27 | #ifdef __cplusplus 28 | } 29 | #endif 30 | 31 | #endif /*__CH32V20x_SYSTEM_H */ 32 | -------------------------------------------------------------------------------- /adv2eth/APP/main.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : main.c 3 | * Author : WCH 4 | * Version : V1.1 5 | * Date : 2020/08/06 6 | * Description : Peripheral slave application main function and task system initialization 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | /* Header file contains */ 15 | #include "CONFIG.h" 16 | #include "HAL.h" 17 | #include "observer.h" 18 | #include "eth.h" 19 | 20 | /********************************************************************* 21 | * GLOBAL TYPEDEFS 22 | */ 23 | __attribute__((aligned(4))) uint32_t MEM_BUF[BLE_MEMHEAP_SIZE / 4]; 24 | 25 | #if(defined(BLE_MAC)) && (BLE_MAC == TRUE) 26 | const uint8_t MacAddr[6] = {0x84, 0xC2, 0xE4, 0x03, 0x02, 0x02}; 27 | #endif 28 | 29 | /********************************************************************* 30 | * @fn Main_Circulation 31 | * 32 | * @brief Main loop 33 | * 34 | * @return none 35 | */ 36 | __attribute__((section(".highcode"))) 37 | __attribute__((noinline)) 38 | void Main_Circulation(void) 39 | { 40 | while(1) 41 | { 42 | TMOS_SystemProcess(); 43 | eth_process(); 44 | } 45 | } 46 | 47 | /********************************************************************* 48 | * @fn main 49 | * 50 | * @brief Main function 51 | * 52 | * @return none 53 | */ 54 | int main(void) 55 | { 56 | SystemCoreClockUpdate(); 57 | Delay_Init(); 58 | #ifdef DEBUG 59 | USART_Printf_Init( 115200 ); 60 | #endif 61 | PRINT("%s\r\n", VER_LIB); 62 | WCHBLE_Init(); 63 | HAL_Init(); 64 | 65 | GAPRole_ObserverInit(); 66 | Observer_Init(); 67 | eth_init(); 68 | Main_Circulation(); 69 | } 70 | 71 | /******************************** endfile @ main ******************************/ 72 | -------------------------------------------------------------------------------- /adv2eth/HAL/KEY.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : KEY.c 3 | * Author : WCH 4 | * Version : V1.2 5 | * Date : 2022/01/18 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | /* Header file contains */ 15 | #include "HAL.h" 16 | 17 | /************************************************************************************************** 18 | * GLOBAL VARIABLES 19 | **************************************************************************************************/ 20 | 21 | static uint8_t halKeySavedKeys; /* Keep the last state of the button to query whether there is a key value change */ 22 | 23 | /************************************************************************************************** 24 | * FUNCTIONS - Local 25 | **************************************************************************************************/ 26 | static halKeyCBack_t pHalKeyProcessFunction; /* callback function */ 27 | 28 | /************************************************************************************************** 29 | * @fn HAL_KeyInit 30 | * 31 | * @brief Initilize Key Service 32 | * 33 | * @param none 34 | * 35 | * @return None 36 | **************************************************************************************************/ 37 | void HAL_KeyInit(void) 38 | { 39 | /* Initialize previous key to 0 */ 40 | halKeySavedKeys = 0; 41 | /* Initialize callback function */ 42 | pHalKeyProcessFunction = NULL; 43 | 44 | RCC_APB2PeriphClockCmd(KEY1_PCENR, ENABLE); 45 | GPIO_InitTypeDef GPIO_InitStructure; 46 | GPIO_InitStructure.GPIO_Pin = KEY1_BV; 47 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 48 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; 49 | GPIO_Init(KEY1_GPIO, &GPIO_InitStructure); 50 | } 51 | 52 | /************************************************************************************************** 53 | * @fn HalKeyConfig 54 | * 55 | * @brief Configure the Key serivce 56 | * 57 | * @param cback - pointer to the CallBack function 58 | * 59 | * @return None 60 | **************************************************************************************************/ 61 | void HalKeyConfig(halKeyCBack_t cback) 62 | { 63 | /* Register the callback fucntion */ 64 | pHalKeyProcessFunction = cback; 65 | tmos_start_task(halTaskID, HAL_KEY_EVENT, HAL_KEY_POLLING_VALUE); /* Kick off polling */ 66 | } 67 | 68 | /************************************************************************************************** 69 | * @fn HalKeyRead 70 | * 71 | * @brief Read the current value of a key 72 | * 73 | * @param None 74 | * 75 | * @return keys - current keys status 76 | **************************************************************************************************/ 77 | uint8_t HalKeyRead(void) 78 | { 79 | uint8_t keys = 0; 80 | 81 | if(HAL_PUSH_BUTTON1()) 82 | { //Read button 1 83 | keys |= HAL_KEY_SW_1; 84 | } 85 | if(HAL_PUSH_BUTTON2()) 86 | { //Read button 1 87 | keys |= HAL_KEY_SW_2; 88 | } 89 | if(HAL_PUSH_BUTTON3()) 90 | { //Read button 1 91 | keys |= HAL_KEY_SW_3; 92 | } 93 | if(HAL_PUSH_BUTTON4()) 94 | { //Read button 1 95 | keys |= HAL_KEY_SW_4; 96 | } 97 | return keys; 98 | } 99 | 100 | /************************************************************************************************** 101 | * @fn HAL_KeyPoll 102 | * 103 | * @brief Called by hal_driver to poll the keys 104 | * 105 | * @param None 106 | * 107 | * @return None 108 | **************************************************************************************************/ 109 | void HAL_KeyPoll(void) 110 | { 111 | uint8_t keys = 0; 112 | if(HAL_PUSH_BUTTON1()) 113 | { 114 | keys |= HAL_KEY_SW_1; 115 | } 116 | if(HAL_PUSH_BUTTON2()) 117 | { 118 | keys |= HAL_KEY_SW_2; 119 | } 120 | if(HAL_PUSH_BUTTON3()) 121 | { 122 | keys |= HAL_KEY_SW_3; 123 | } 124 | if(HAL_PUSH_BUTTON4()) 125 | { 126 | keys |= HAL_KEY_SW_4; 127 | } 128 | if(keys == halKeySavedKeys) 129 | { /* Exit - since no keys have changed */ 130 | return; 131 | } 132 | halKeySavedKeys = keys; /* Store the current keys for comparation next time */ 133 | /* Invoke Callback if new keys were depressed */ 134 | if(keys && (pHalKeyProcessFunction)) 135 | { 136 | (pHalKeyProcessFunction)(keys); 137 | } 138 | } 139 | 140 | /******************************** endfile @ key ******************************/ 141 | -------------------------------------------------------------------------------- /adv2eth/HAL/Link.ld: -------------------------------------------------------------------------------- 1 | ENTRY( _start ) 2 | 3 | __stack_size = 2048; 4 | 5 | PROVIDE( _stack_size = __stack_size ); 6 | 7 | 8 | MEMORY 9 | { 10 | /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ 11 | /* 12 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K 13 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K 14 | */ 15 | 16 | /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ 17 | /* 18 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K 19 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 20 | */ 21 | 22 | /* CH32V20x_D8 - CH32V203RB 23 | CH32V20x_D8W - CH32V208x 24 | FLASH + RAM supports the following configuration 25 | FLASH-128K + RAM-64K 26 | FLASH-144K + RAM-48K 27 | FLASH-160K + RAM-32K 28 | */ 29 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 448K 30 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K 31 | 32 | } 33 | 34 | 35 | SECTIONS 36 | { 37 | 38 | .init : 39 | { 40 | _sinit = .; 41 | . = ALIGN(4); 42 | KEEP(*(SORT_NONE(.init))) 43 | . = ALIGN(4); 44 | _einit = .; 45 | } >FLASH AT>FLASH 46 | 47 | .vector : 48 | { 49 | *(.vector); 50 | . = ALIGN(64); 51 | KEEP(*(SORT_NONE(.handle_reset))) 52 | } >FLASH AT>FLASH 53 | 54 | .highcode : 55 | { 56 | . = ALIGN(4); 57 | *(.highcode); 58 | *(.highcode.*); 59 | . = ALIGN(4); 60 | } >FLASH AT>FLASH 61 | 62 | .text : 63 | { 64 | . = ALIGN(4); 65 | 66 | EXCLUDE_FILE (*wchble.a) *(.text .text*) 67 | 68 | *(.text) 69 | *(.text.*) 70 | *(.rodata) 71 | *(.rodata*) 72 | *(.sdata2.*) 73 | *(.glue_7) 74 | *(.glue_7t) 75 | *(.gnu.linkonce.t.*) 76 | . = ALIGN(4); 77 | } >FLASH AT>FLASH 78 | 79 | .fini : 80 | { 81 | KEEP(*(SORT_NONE(.fini))) 82 | . = ALIGN(4); 83 | } >FLASH AT>FLASH 84 | 85 | PROVIDE( _etext = . ); 86 | PROVIDE( _eitcm = . ); 87 | 88 | .preinit_array : 89 | { 90 | PROVIDE_HIDDEN (__preinit_array_start = .); 91 | KEEP (*(.preinit_array)) 92 | PROVIDE_HIDDEN (__preinit_array_end = .); 93 | } >FLASH AT>FLASH 94 | 95 | .init_array : 96 | { 97 | PROVIDE_HIDDEN (__init_array_start = .); 98 | KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) 99 | KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) 100 | PROVIDE_HIDDEN (__init_array_end = .); 101 | } >FLASH AT>FLASH 102 | 103 | .fini_array : 104 | { 105 | PROVIDE_HIDDEN (__fini_array_start = .); 106 | KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) 107 | KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) 108 | PROVIDE_HIDDEN (__fini_array_end = .); 109 | } >FLASH AT>FLASH 110 | 111 | .ctors : 112 | { 113 | /* gcc uses crtbegin.o to find the start of 114 | the constructors, so we make sure it is 115 | first. Because this is a wildcard, it 116 | doesn't matter if the user does not 117 | actually link against crtbegin.o; the 118 | linker won't look for a file to match a 119 | wildcard. The wildcard also means that it 120 | doesn't matter which directory crtbegin.o 121 | is in. */ 122 | KEEP (*crtbegin.o(.ctors)) 123 | KEEP (*crtbegin?.o(.ctors)) 124 | /* We don't want to include the .ctor section from 125 | the crtend.o file until after the sorted ctors. 126 | The .ctor section from the crtend file contains the 127 | end of ctors marker and it must be last */ 128 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) 129 | KEEP (*(SORT(.ctors.*))) 130 | KEEP (*(.ctors)) 131 | } >FLASH AT>FLASH 132 | 133 | .dtors : 134 | { 135 | KEEP (*crtbegin.o(.dtors)) 136 | KEEP (*crtbegin?.o(.dtors)) 137 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) 138 | KEEP (*(SORT(.dtors.*))) 139 | KEEP (*(.dtors)) 140 | } >FLASH AT>FLASH 141 | 142 | .dalign : 143 | { 144 | . = ALIGN(4); 145 | PROVIDE(_data_vma = .); 146 | } >RAM AT>FLASH 147 | 148 | .dlalign : 149 | { 150 | . = ALIGN(4); 151 | PROVIDE(_data_lma = .); 152 | } >FLASH AT>FLASH 153 | 154 | .data : 155 | { 156 | *(.gnu.linkonce.r.*) 157 | *(.data .data.*) 158 | *(.gnu.linkonce.d.*) 159 | . = ALIGN(8); 160 | PROVIDE( __global_pointer$ = . + 0x800 ); 161 | *(.sdata .sdata.*) 162 | *(.gnu.linkonce.s.*) 163 | . = ALIGN(8); 164 | *(.srodata.cst16) 165 | *(.srodata.cst8) 166 | *(.srodata.cst4) 167 | *(.srodata.cst2) 168 | *(.srodata .srodata.*) 169 | . = ALIGN(4); 170 | PROVIDE( _edata = .); 171 | } >RAM AT>FLASH 172 | 173 | .bss : 174 | { 175 | . = ALIGN(4); 176 | PROVIDE( _sbss = .); 177 | *(.sbss*) 178 | *(.gnu.linkonce.sb.*) 179 | *(.bss*) 180 | *(.gnu.linkonce.b.*) 181 | *(COMMON*) 182 | . = ALIGN(4); 183 | PROVIDE( _ebss = .); 184 | } >RAM AT>FLASH 185 | 186 | PROVIDE( _end = _ebss); 187 | PROVIDE( end = . ); 188 | 189 | /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : 190 | { 191 | PROVIDE( _heap_end = . ); 192 | . = ALIGN(4); 193 | PROVIDE(_susrstack = . ); 194 | . = . + __stack_size; 195 | PROVIDE( _eusrstack = .); 196 | } >RAM */ 197 | 198 | .stack ORIGIN(RAM)+LENGTH(RAM) : 199 | { 200 | PROVIDE( _heap_end = . ); 201 | . = ALIGN(4); 202 | PROVIDE(_eusrstack = . ); 203 | } >RAM 204 | } 205 | -------------------------------------------------------------------------------- /adv2eth/HAL/MCU.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/485fca6fccfb4511921e4eea160f9d147d4ad4c4/adv2eth/HAL/MCU.c -------------------------------------------------------------------------------- /adv2eth/HAL/RTC.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : RTC.c 3 | * Author : WCH 4 | * Version : V1.2 5 | * Date : 2022/01/18 6 | * Description : RTC configuration and its initialization 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | /* Header file contains */ 15 | #include "HAL.h" 16 | 17 | /********************************************************************* 18 | * CONSTANTS 19 | */ 20 | #define RTC_INIT_TIME_HOUR 0 21 | #define RTC_INIT_TIME_MINUTE 0 22 | #define RTC_INIT_TIME_SECEND 0 23 | 24 | /*************************************************** 25 | * Global variables 26 | */ 27 | volatile uint32_t RTCTigFlag; 28 | 29 | /******************************************************************************* 30 | * @fn RTC_SetTignTime 31 | * 32 | * @brief Configure RTC trigger time 33 | * 34 | * @param time - Trigger time. 35 | * 36 | * @return None. 37 | */ 38 | void RTC_SetTignTime(uint32_t time) 39 | { 40 | RTC_WaitForLastTask(); 41 | RTC_SetAlarm(time); 42 | RTC_WaitForLastTask(); 43 | RTCTigFlag = 0; 44 | } 45 | 46 | /******************************************************************************* 47 | * @fn HAL_Time0Init 48 | * 49 | * @brief System timer initialization 50 | * 51 | * @param None. 52 | * 53 | * @return None. 54 | */ 55 | void HAL_TimeInit(void) 56 | { 57 | uint16_t temp=0; 58 | uint8_t state=0; 59 | bleClockConfig_t conf={0}; 60 | 61 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR|RCC_APB1Periph_BKP, ENABLE); 62 | PWR_BackupAccessCmd(ENABLE); 63 | #if( CLK_OSC32K ) 64 | RCC_LSICmd(ENABLE); 65 | RCC_LSEConfig(RCC_LSE_OFF); 66 | RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); 67 | #else 68 | RCC_LSEConfig(RCC_LSE_ON); 69 | /* Check the specified RCC logo position settings or not, 70 | * wait for the low-speed crystal oscillator to be ready */ 71 | while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) 72 | { 73 | temp++; 74 | Delay_Ms(10); 75 | } 76 | if(temp>=250) 77 | { 78 | printf("time error..\n"); 79 | } 80 | RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); 81 | #endif 82 | RCC_RTCCLKCmd(ENABLE); 83 | RTC_WaitForLastTask(); 84 | RTC_WaitForLastTask(); 85 | RTC_SetPrescaler(1); 86 | RTC_WaitForLastTask(); 87 | RTC_SetCounter(0); 88 | RTC_WaitForLastTask(); 89 | #if( CLK_OSC32K ) 90 | Lib_Calibration_LSI(); 91 | #endif 92 | conf.ClockAccuracy = CLK_OSC32K?1000:100; 93 | conf.ClockFrequency = CAB_LSIFQ/2; 94 | conf.ClockMaxCount = 0xFFFFFFFF; 95 | conf.getClockValue = RTC_GetCounter; 96 | state = TMOS_TimerInit( &conf ); 97 | if(state) 98 | { 99 | PRINT("TMOS_TimerInit err %x\n",state); 100 | } 101 | } 102 | 103 | 104 | __attribute__((interrupt("WCH-Interrupt-fast"))) 105 | void RTCAlarm_IRQHandler(void) 106 | { 107 | RTCTigFlag = 1; 108 | EXTI_ClearITPendingBit(EXTI_Line17); 109 | RTC_ClearITPendingBit(RTC_IT_ALR); 110 | RTC_WaitForLastTask(); 111 | } 112 | 113 | /******************************** endfile @ time ******************************/ 114 | -------------------------------------------------------------------------------- /adv2eth/HAL/SLEEP.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/485fca6fccfb4511921e4eea160f9d147d4ad4c4/adv2eth/HAL/SLEEP.c -------------------------------------------------------------------------------- /adv2eth/HAL/include/HAL.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : HAL.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2016/05/05 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | #ifndef __HAL_H 15 | #define __HAL_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | #include "config.h" 22 | #include "RTC.h" 23 | #include "SLEEP.h" 24 | #include "KEY.h" 25 | #include "LED.h" 26 | 27 | /* hal task Event */ 28 | #define LED_BLINK_EVENT 0x0001 29 | #define HAL_KEY_EVENT 0x0002 30 | #define HAL_REG_INIT_EVENT 0x2000 31 | #define HAL_TEST_EVENT 0x4000 32 | 33 | /********************************************************************* 34 | * GLOBAL VARIABLES 35 | */ 36 | extern tmosTaskID halTaskID; 37 | 38 | /********************************************************************* 39 | * GLOBAL FUNCTIONS 40 | */ 41 | 42 | /** 43 | * @brief Hardware initialization 44 | */ 45 | extern void HAL_Init(void); 46 | 47 | /** 48 | * @brief HAL processing 49 | * 50 | * @param task_id - The TMOS assigned task ID. 51 | * @param events - events to process. This is a bit map and can 52 | * contain more than one event. 53 | */ 54 | extern tmosEvents HAL_ProcessEvent(tmosTaskID task_id, tmosEvents events); 55 | 56 | /** 57 | * @brief Initialization of the BLE library 58 | */ 59 | extern void WCHBLE_Init(void); 60 | 61 | /** 62 | * @brief Get the internal temperature sampling value. 63 | * If the ADC interrupt sampling is used, 64 | * the interrupt is temporarily shielded in this function. 65 | * 66 | * @return Internal temperature sampling value. 67 | */ 68 | extern uint16_t HAL_GetInterTempValue(void); 69 | 70 | /** 71 | * @brief Internal 32K calibration 72 | */ 73 | extern void Lib_Calibration_LSI(void); 74 | 75 | /********************************************************************* 76 | *********************************************************************/ 77 | 78 | #ifdef __cplusplus 79 | } 80 | #endif 81 | 82 | #endif 83 | -------------------------------------------------------------------------------- /adv2eth/HAL/include/KEY.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : KEY.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2016/04/12 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | #ifndef __KEY_H 15 | #define __KEY_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /************************************************************************************************** 22 | * MACROS 23 | **************************************************************************************************/ 24 | #define HAL_KEY_POLLING_VALUE 100 25 | 26 | /* Switches (keys) */ 27 | #define HAL_KEY_SW_1 0x01 // key1 28 | #define HAL_KEY_SW_2 0x02 // key2 29 | #define HAL_KEY_SW_3 0x04 // key3 30 | #define HAL_KEY_SW_4 0x08 // key4 31 | 32 | /* Key definition */ 33 | 34 | /* 1 - KEY */ 35 | #define KEY1_PCENR (RCC_APB2Periph_GPIOB) 36 | #define KEY2_PCENR () 37 | #define KEY3_PCENR () 38 | #define KEY4_PCENR () 39 | 40 | #define KEY1_GPIO (GPIOB) 41 | #define KEY2_GPIO () 42 | #define KEY3_GPIO () 43 | #define KEY4_GPIO () 44 | 45 | #define KEY1_BV BV(13) 46 | #define KEY2_BV () 47 | #define KEY3_BV () 48 | #define KEY4_BV () 49 | 50 | #define KEY1_IN (GPIO_ReadInputDataBit(KEY1_GPIO, KEY1_BV)==0) 51 | #define KEY2_IN () 52 | #define KEY3_IN () 53 | #define KEY4_IN () 54 | 55 | #define HAL_PUSH_BUTTON1() (KEY1_IN) //Add custom button 56 | #define HAL_PUSH_BUTTON2() (0) 57 | #define HAL_PUSH_BUTTON3() (0) 58 | #define HAL_PUSH_BUTTON4() (0) 59 | 60 | /************************************************************************************************** 61 | * TYPEDEFS 62 | **************************************************************************************************/ 63 | typedef void (*halKeyCBack_t)(uint8_t keys); 64 | 65 | typedef struct 66 | { 67 | uint8_t keys; // keys 68 | } keyChange_t; 69 | 70 | /************************************************************************************************** 71 | * GLOBAL VARIABLES 72 | **************************************************************************************************/ 73 | 74 | /********************************************************************* 75 | * FUNCTIONS 76 | */ 77 | 78 | /** 79 | * @brief Initialize the Key Service 80 | */ 81 | void HAL_KeyInit(void); 82 | 83 | /** 84 | * @brief This is for internal used by hal_driver 85 | */ 86 | void HAL_KeyPoll(void); 87 | 88 | /** 89 | * @brief Configure the Key serivce 90 | * 91 | * @param cback - pointer to the CallBack function 92 | */ 93 | void HalKeyConfig(const halKeyCBack_t cback); 94 | 95 | /** 96 | * @brief Read the Key callback 97 | */ 98 | void HalKeyCallback(uint8_t keys); 99 | 100 | /** 101 | * @brief Read the Key status 102 | */ 103 | uint8_t HalKeyRead(void); 104 | 105 | /************************************************************************************************** 106 | **************************************************************************************************/ 107 | 108 | #ifdef __cplusplus 109 | } 110 | #endif 111 | 112 | #endif 113 | -------------------------------------------------------------------------------- /adv2eth/HAL/include/LED.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : LED.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2016/04/12 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | #ifndef __LED_H 15 | #define __LED_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /********************************************************************* 22 | * CONSTANTS 23 | */ 24 | 25 | /* LEDS - The LED number is the same as the bit position */ 26 | #define HAL_LED_1 0x01 27 | #define HAL_LED_2 0x02 28 | #define HAL_LED_3 0x04 29 | #define HAL_LED_4 0x08 30 | #define HAL_LED_ALL (HAL_LED_1 | HAL_LED_2 | HAL_LED_3 | HAL_LED_4) 31 | 32 | /* Modes */ 33 | #define HAL_LED_MODE_OFF 0x00 34 | #define HAL_LED_MODE_ON 0x01 35 | #define HAL_LED_MODE_BLINK 0x02 36 | #define HAL_LED_MODE_FLASH 0x04 37 | #define HAL_LED_MODE_TOGGLE 0x08 38 | 39 | /* Defaults */ 40 | #define HAL_LED_DEFAULT_MAX_LEDS 4 41 | #define HAL_LED_DEFAULT_DUTY_CYCLE 5 42 | #define HAL_LED_DEFAULT_FLASH_COUNT 50 43 | #define HAL_LED_DEFAULT_FLASH_TIME 1000 44 | 45 | /********************************************************************* 46 | * TYPEDEFS 47 | */ 48 | 49 | /* Connect an LED to monitor the progress of the demo program, the low-level LED is on */ 50 | 51 | /* 1 - LED */ 52 | #define LED1_PCENR (RCC_APB2Periph_GPIOB) 53 | #define LED2_PCENR 54 | #define LED3_PCENR 55 | 56 | #define LED1_GPIO (GPIOB) 57 | #define LED2_GPIO 58 | #define LED3_GPIO 59 | 60 | #define LED1_BV BV(15) 61 | #define LED2_BV 62 | #define LED3_BV 63 | 64 | #define HAL_TURN_OFF_LED1() (GPIO_WriteBit(LED1_GPIO, LED1_BV, Bit_SET)) 65 | #define HAL_TURN_OFF_LED2() 66 | #define HAL_TURN_OFF_LED3() 67 | #define HAL_TURN_OFF_LED4() 68 | 69 | #define HAL_TURN_ON_LED1() (GPIO_WriteBit(LED1_GPIO, LED1_BV, Bit_RESET)) 70 | #define HAL_TURN_ON_LED2() 71 | #define HAL_TURN_ON_LED3() 72 | #define HAL_TURN_ON_LED4() 73 | 74 | #define HAL_STATE_LED1() 0 75 | #define HAL_STATE_LED2() 0 76 | #define HAL_STATE_LED3() 0 77 | #define HAL_STATE_LED4() 0 78 | 79 | /********************************************************************* 80 | * GLOBAL VARIABLES 81 | */ 82 | 83 | /** 84 | * @brief Initialize LED Service. 85 | */ 86 | void HAL_LedInit(void); 87 | 88 | /** 89 | * @brief update time LED Service. 90 | */ 91 | void HalLedUpdate(void); 92 | 93 | /** 94 | * @brief Turn ON/OFF/TOGGLE given LEDs 95 | * 96 | * @param led - bit mask value of leds to be turned ON/OFF/TOGGLE 97 | * @param mode - BLINK, FLASH, TOGGLE, ON, OFF 98 | */ 99 | extern uint8_t HalLedSet(uint8_t led, uint8_t mode); 100 | 101 | /** 102 | * @brief Blink the leds 103 | * 104 | * @param led - bit mask value of leds to be turned ON/OFF/TOGGLE 105 | * @param numBlinks - number of blinks 106 | * @param percent - the percentage in each period where the led will be on 107 | * @param period - length of each cycle in milliseconds 108 | */ 109 | extern void HalLedBlink(uint8_t leds, uint8_t cnt, uint8_t duty, uint16_t time); 110 | 111 | /** 112 | * @brief Put LEDs in sleep state - store current values 113 | */ 114 | extern void HalLedEnterSleep(void); 115 | 116 | /** 117 | * @brief Retore LEDs from sleep state 118 | */ 119 | extern void HalLedExitSleep(void); 120 | 121 | /** 122 | * @brief Return LED state 123 | */ 124 | extern uint8_t HalLedGetState(void); 125 | 126 | /********************************************************************* 127 | *********************************************************************/ 128 | 129 | #ifdef __cplusplus 130 | } 131 | #endif 132 | 133 | #endif 134 | -------------------------------------------------------------------------------- /adv2eth/HAL/include/RTC.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : RTC.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2016/04/12 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | #ifndef __RTC_H 15 | #define __RTC_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | 22 | extern volatile uint32_t RTCTigFlag; 23 | 24 | /** 25 | * @brief Initialize time Service. 26 | */ 27 | void HAL_TimeInit(void); 28 | 29 | /** 30 | * @brief Configure RTC trigger time 31 | * 32 | * @param time - Trigger time. 33 | */ 34 | extern void RTC_SetTignTime(uint32_t time); 35 | 36 | #ifdef __cplusplus 37 | } 38 | #endif 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /adv2eth/HAL/include/SLEEP.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : SLEEP.h 3 | * Author : WCH 4 | * Version : V1.0 5 | * Date : 2018/11/12 6 | * Description : 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | 13 | /******************************************************************************/ 14 | #ifndef __SLEEP_H 15 | #define __SLEEP_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | /********************************************************************* 22 | * GLOBAL VARIABLES 23 | */ 24 | 25 | /********************************************************************* 26 | * FUNCTIONS 27 | */ 28 | 29 | /** 30 | * @brief Configure sleep Wake-up source - RTC wake up, trigger mode 31 | */ 32 | extern void HAL_SleepInit(void); 33 | 34 | /** 35 | * @brief Start sleep 36 | * 37 | * @param time - Wake-up time (RTC absolute value) 38 | * 39 | * @return state. 40 | */ 41 | extern uint32_t BLE_LowPower(uint32_t time); 42 | 43 | /********************************************************************* 44 | *********************************************************************/ 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /adv2eth/HAL/include/config.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/485fca6fccfb4511921e4eea160f9d147d4ad4c4/adv2eth/HAL/include/config.h -------------------------------------------------------------------------------- /adv2eth/LIB/ble_task_scheduler.S: -------------------------------------------------------------------------------- 1 | .global Ecall_M_Mode_Handler 2 | .global Ecall_U_Mode_Handler 3 | .global LLE_IRQHandler 4 | 5 | .extern g_LLE_IRQLibHandlerLocation 6 | 7 | .section .highcode,"ax",@progbits 8 | .align 2 9 | .func 10 | Ecall_M_Mode_Handler: 11 | Ecall_U_Mode_Handler: 12 | 13 | addi a1, x0, 0x20 14 | csrs 0x804, a1 15 | 16 | lw a1, 0 * 4( sp ) 17 | csrw mepc, a1 18 | 19 | lw x1, 1 * 4( sp ) 20 | lw x4, 2 * 4( sp ) 21 | lw x5, 3 * 4( sp ) 22 | lw x6, 4 * 4( sp ) 23 | lw x7, 5 * 4( sp ) 24 | lw x8, 6 * 4( sp ) 25 | lw x9, 7 * 4( sp ) 26 | lw x10, 8 * 4( sp ) 27 | lw x11, 9 * 4( sp ) 28 | lw x12, 10 * 4( sp ) 29 | lw x13, 11 * 4( sp ) 30 | lw x14, 12 * 4( sp ) 31 | lw x15, 13 * 4( sp ) 32 | lw x16, 14 * 4( sp ) 33 | lw x17, 15 * 4( sp ) 34 | lw x18, 16 * 4( sp ) 35 | lw x19, 17 * 4( sp ) 36 | lw x20, 18 * 4( sp ) 37 | lw x21, 19 * 4( sp ) 38 | lw x22, 20 * 4( sp ) 39 | lw x23, 21 * 4( sp ) 40 | lw x24, 22 * 4( sp ) 41 | lw x25, 23 * 4( sp ) 42 | lw x26, 24 * 4( sp ) 43 | lw x27, 25 * 4( sp ) 44 | lw x28, 26 * 4( sp ) 45 | lw x29, 27 * 4( sp ) 46 | lw x30, 28 * 4( sp ) 47 | lw x31, 29 * 4( sp ) 48 | 49 | addi sp, sp, 32*4 50 | 51 | mret 52 | .endfunc 53 | 54 | .section .highcode.LLE_IRQHandler,"ax",@progbits 55 | .align 2 56 | .func 57 | LLE_IRQHandler: 58 | addi sp, sp, -32*4 59 | 60 | sw x1, 1 * 4( sp ) 61 | sw x4, 2 * 4( sp ) 62 | sw x5, 3 * 4( sp ) 63 | sw x6, 4 * 4( sp ) 64 | sw x7, 5 * 4( sp ) 65 | sw x8, 6 * 4( sp ) 66 | sw x9, 7 * 4( sp ) 67 | sw x10, 8 * 4( sp ) 68 | sw x11, 9 * 4( sp ) 69 | sw x12, 10 * 4( sp ) 70 | sw x13, 11 * 4( sp ) 71 | sw x14, 12 * 4( sp ) 72 | sw x15, 13 * 4( sp ) 73 | sw x16, 14 * 4( sp ) 74 | sw x17, 15 * 4( sp ) 75 | sw x18, 16 * 4( sp ) 76 | sw x19, 17 * 4( sp ) 77 | sw x20, 18 * 4( sp ) 78 | sw x21, 19 * 4( sp ) 79 | sw x22, 20 * 4( sp ) 80 | sw x23, 21 * 4( sp ) 81 | sw x24, 22 * 4( sp ) 82 | sw x25, 23 * 4( sp ) 83 | sw x26, 24 * 4( sp ) 84 | sw x27, 25 * 4( sp ) 85 | sw x28, 26 * 4( sp ) 86 | sw x29, 27 * 4( sp ) 87 | sw x30, 28 * 4( sp ) 88 | sw x31, 29 * 4( sp ) 89 | 90 | la a1, g_LLE_IRQLibHandlerLocation 91 | lw a0, 0(a1) 92 | jalr x1, 0(a0) 93 | 94 | lw x1, 1 * 4( sp ) 95 | lw x4, 2 * 4( sp ) 96 | lw x5, 3 * 4( sp ) 97 | lw x6, 4 * 4( sp ) 98 | lw x7, 5 * 4( sp ) 99 | lw x8, 6 * 4( sp ) 100 | lw x9, 7 * 4( sp ) 101 | lw x10, 8 * 4( sp ) 102 | lw x11, 9 * 4( sp ) 103 | lw x12, 10 * 4( sp ) 104 | lw x13, 11 * 4( sp ) 105 | lw x14, 12 * 4( sp ) 106 | lw x15, 13 * 4( sp ) 107 | lw x16, 14 * 4( sp ) 108 | lw x17, 15 * 4( sp ) 109 | lw x18, 16 * 4( sp ) 110 | lw x19, 17 * 4( sp ) 111 | lw x20, 18 * 4( sp ) 112 | lw x21, 19 * 4( sp ) 113 | lw x22, 20 * 4( sp ) 114 | lw x23, 21 * 4( sp ) 115 | lw x24, 22 * 4( sp ) 116 | lw x25, 23 * 4( sp ) 117 | lw x26, 24 * 4( sp ) 118 | lw x27, 25 * 4( sp ) 119 | lw x28, 26 * 4( sp ) 120 | lw x29, 27 * 4( sp ) 121 | lw x30, 28 * 4( sp ) 122 | lw x31, 29 * 4( sp ) 123 | 124 | addi sp, sp, 32*4 125 | 126 | mret 127 | .endfunc 128 | -------------------------------------------------------------------------------- /adv2eth/LIB/libwchble.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/485fca6fccfb4511921e4eea160f9d147d4ad4c4/adv2eth/LIB/libwchble.a -------------------------------------------------------------------------------- /adv2eth/LIB/wchble_rom.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/485fca6fccfb4511921e4eea160f9d147d4ad4c4/adv2eth/LIB/wchble_rom.h -------------------------------------------------------------------------------- /adv2eth/NetLib/eth_driver.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : eth_driver.h 3 | * Author : WCH 4 | * Version : V1.3.0 5 | * Date : 2022/05/27 6 | * Description : This file contains the headers of the ETH Driver. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __ETH_DRIVER__ 13 | #define __ETH_DRIVER__ 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | #include "debug.h" 20 | 21 | #define ROM_CFG_USERADR_ID 0x1FFFF7E8 22 | 23 | #define PHY_LINK_TASK_PERIOD 50 24 | 25 | #define PHY_ANLPAR_SELECTOR_FIELD 0x1F 26 | #define PHY_ANLPAR_SELECTOR_VALUE 0x01 /* 5B'00001 */ 27 | 28 | #define PHY_LINK_INIT 0x00 29 | #define PHY_LINK_SUC_P (1<<0) 30 | #define PHY_LINK_SUC_N (1<<1) 31 | #define PHY_LINK_WAIT_SUC (1<<7) 32 | 33 | #define PHY_PN_SWITCH_P (0<<2) 34 | #define PHY_PN_SWITCH_N (1<<2) 35 | #define PHY_PN_SWITCH_AUTO (2<<2) 36 | 37 | #ifndef WCHNETTIMERPERIOD 38 | #define WCHNETTIMERPERIOD 10 /* Timer period, in Ms. */ 39 | #endif 40 | 41 | #define PHY_NEGOTIATION_PARAM_INIT() do{\ 42 | phySucCnt = 0;\ 43 | phyStatus = 0;\ 44 | phyLinkCnt = 0;\ 45 | phyRetryCnt = 0;\ 46 | phyPNChangeCnt = 0;\ 47 | phyLinkStatus = PHY_LINK_INIT;\ 48 | }while(0) 49 | 50 | /* definition for Ethernet frame */ 51 | #define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 52 | #define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 53 | #define ETH_CRC 4 /* Ethernet CRC */ 54 | #define ETH_EXTRA 2 /* Extra bytes in some cases */ 55 | #define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ 56 | #define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ 57 | #define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ 58 | 59 | /* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ 60 | #define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ 61 | 62 | /* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ 63 | #define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ 64 | #define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ 65 | #define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: */ 66 | #define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ 67 | #define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ 68 | 69 | #define ETH_DMARxDesc_FrameLengthShift 16 70 | 71 | /* ETHERNET errors */ 72 | #define ETH_ERROR ((uint32_t)0) 73 | #define ETH_SUCCESS ((uint32_t)1) 74 | 75 | /* ETH structure definition */ 76 | typedef struct 77 | { 78 | uint32_t volatile Status; /* Status */ 79 | uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ 80 | uint32_t Buffer1Addr; /* Buffer1 address pointer */ 81 | uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ 82 | } ETH_DMADESCTypeDef; 83 | 84 | #include "wchnet.h" 85 | 86 | extern SOCK_INF SocketInf[ ]; 87 | 88 | void ETH_PHYLink( void ); 89 | void WCHNET_ETHIsr( void ); 90 | void WCHNET_MainTask( void ); 91 | void ETH_LedConfiguration(void); 92 | void ETH_Init( uint8_t *macAddr ); 93 | void ETH_LedLinkSet( uint8_t mode ); 94 | void ETH_LedDataSet( uint8_t mode ); 95 | void WCHNET_TimeIsr( uint16_t timperiod ); 96 | void ETH_Configuration( uint8_t *macAddr ); 97 | uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr); 98 | 99 | #ifdef __cplusplus 100 | } 101 | #endif 102 | 103 | #endif 104 | -------------------------------------------------------------------------------- /adv2eth/NetLib/libwchnet.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/pvvx/WCHBLE2ETH/485fca6fccfb4511921e4eea160f9d147d4ad4c4/adv2eth/NetLib/libwchnet.a -------------------------------------------------------------------------------- /adv2eth/SRC/Core/core_riscv.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.c 3 | * Author : WCH 4 | * Version : V1.0.1 5 | * Date : 2023/11/11 6 | * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V20x 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | /* define compiler specific symbols */ 15 | #if defined ( __CC_ARM ) 16 | #define __ASM __asm /* asm keyword for ARM Compiler */ 17 | #define __INLINE __inline /* inline keyword for ARM Compiler */ 18 | 19 | #elif defined ( __ICCARM__ ) 20 | #define __ASM __asm /* asm keyword for IAR Compiler */ 21 | #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */ 22 | 23 | #elif defined ( __GNUC__ ) 24 | #define __ASM __asm /* asm keyword for GNU Compiler */ 25 | #define __INLINE inline /* inline keyword for GNU Compiler */ 26 | 27 | #elif defined ( __TASKING__ ) 28 | #define __ASM __asm /* asm keyword for TASKING Compiler */ 29 | #define __INLINE inline /* inline keyword for TASKING Compiler */ 30 | 31 | #endif 32 | 33 | 34 | 35 | /********************************************************************* 36 | * @fn __get_MSTATUS 37 | * 38 | * @brief Return the Machine Status Register 39 | * 40 | * @return mstatus value 41 | */ 42 | uint32_t __get_MSTATUS(void) 43 | { 44 | uint32_t result; 45 | 46 | __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); 47 | return (result); 48 | } 49 | 50 | /********************************************************************* 51 | * @fn __set_MSTATUS 52 | * 53 | * @brief Set the Machine Status Register 54 | * 55 | * @param value - set mstatus value 56 | * 57 | * @return none 58 | */ 59 | void __set_MSTATUS(uint32_t value) 60 | { 61 | __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); 62 | } 63 | 64 | /********************************************************************* 65 | * @fn __get_MISA 66 | * 67 | * @brief Return the Machine ISA Register 68 | * 69 | * @return misa value 70 | */ 71 | uint32_t __get_MISA(void) 72 | { 73 | uint32_t result; 74 | 75 | __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); 76 | return (result); 77 | } 78 | 79 | /********************************************************************* 80 | * @fn __set_MISA 81 | * 82 | * @brief Set the Machine ISA Register 83 | * 84 | * @param value - set misa value 85 | * 86 | * @return none 87 | */ 88 | void __set_MISA(uint32_t value) 89 | { 90 | __ASM volatile ("csrw misa, %0" : : "r" (value) ); 91 | } 92 | 93 | /********************************************************************* 94 | * @fn __get_MTVEC 95 | * 96 | * @brief Return the Machine Trap-Vector Base-Address Register 97 | * 98 | * @return mtvec value 99 | */ 100 | uint32_t __get_MTVEC(void) 101 | { 102 | uint32_t result; 103 | 104 | __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); 105 | return (result); 106 | } 107 | 108 | /********************************************************************* 109 | * @fn __set_MTVEC 110 | * 111 | * @brief Set the Machine Trap-Vector Base-Address Register 112 | * 113 | * @param value - set mtvec value 114 | * 115 | * @return none 116 | */ 117 | void __set_MTVEC(uint32_t value) 118 | { 119 | __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); 120 | } 121 | 122 | /********************************************************************* 123 | * @fn __get_MSCRATCH 124 | * 125 | * @brief Return the Machine Seratch Register 126 | * 127 | * @return mscratch value 128 | */ 129 | uint32_t __get_MSCRATCH(void) 130 | { 131 | uint32_t result; 132 | 133 | __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); 134 | return (result); 135 | } 136 | 137 | /********************************************************************* 138 | * @fn __set_MSCRATCH 139 | * 140 | * @brief Set the Machine Seratch Register 141 | * 142 | * @param value - set mscratch value 143 | * 144 | * @return none 145 | */ 146 | void __set_MSCRATCH(uint32_t value) 147 | { 148 | __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); 149 | } 150 | 151 | /********************************************************************* 152 | * @fn __get_MEPC 153 | * 154 | * @brief Return the Machine Exception Program Register 155 | * 156 | * @return mepc value 157 | */ 158 | uint32_t __get_MEPC(void) 159 | { 160 | uint32_t result; 161 | 162 | __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); 163 | return (result); 164 | } 165 | 166 | /********************************************************************* 167 | * @fn __set_MEPC 168 | * 169 | * @brief Set the Machine Exception Program Register 170 | * 171 | * @return mepc value 172 | */ 173 | void __set_MEPC(uint32_t value) 174 | { 175 | __ASM volatile ("csrw mepc, %0" : : "r" (value) ); 176 | } 177 | 178 | /********************************************************************* 179 | * @fn __get_MCAUSE 180 | * 181 | * @brief Return the Machine Cause Register 182 | * 183 | * @return mcause value 184 | */ 185 | uint32_t __get_MCAUSE(void) 186 | { 187 | uint32_t result; 188 | 189 | __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); 190 | return (result); 191 | } 192 | 193 | /********************************************************************* 194 | * @fn __set_MEPC 195 | * 196 | * @brief Set the Machine Cause Register 197 | * 198 | * @return mcause value 199 | */ 200 | void __set_MCAUSE(uint32_t value) 201 | { 202 | __ASM volatile ("csrw mcause, %0" : : "r" (value) ); 203 | } 204 | 205 | /********************************************************************* 206 | * @fn __get_MTVAL 207 | * 208 | * @brief Return the Machine Trap Value Register 209 | * 210 | * @return mtval value 211 | */ 212 | uint32_t __get_MTVAL(void) 213 | { 214 | uint32_t result; 215 | 216 | __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); 217 | return (result); 218 | } 219 | 220 | /********************************************************************* 221 | * @fn __set_MTVAL 222 | * 223 | * @brief Set the Machine Trap Value Register 224 | * 225 | * @return mtval value 226 | */ 227 | void __set_MTVAL(uint32_t value) 228 | { 229 | __ASM volatile ("csrw mtval, %0" : : "r" (value) ); 230 | } 231 | 232 | /********************************************************************* 233 | * @fn __get_MVENDORID 234 | * 235 | * @brief Return Vendor ID Register 236 | * 237 | * @return mvendorid value 238 | */ 239 | uint32_t __get_MVENDORID(void) 240 | { 241 | uint32_t result; 242 | 243 | __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); 244 | return (result); 245 | } 246 | 247 | /********************************************************************* 248 | * @fn __get_MARCHID 249 | * 250 | * @brief Return Machine Architecture ID Register 251 | * 252 | * @return marchid value 253 | */ 254 | uint32_t __get_MARCHID(void) 255 | { 256 | uint32_t result; 257 | 258 | __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); 259 | return (result); 260 | } 261 | 262 | /********************************************************************* 263 | * @fn __get_MIMPID 264 | * 265 | * @brief Return Machine Implementation ID Register 266 | * 267 | * @return mimpid value 268 | */ 269 | uint32_t __get_MIMPID(void) 270 | { 271 | uint32_t result; 272 | 273 | __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); 274 | return (result); 275 | } 276 | 277 | /********************************************************************* 278 | * @fn __get_MHARTID 279 | * 280 | * @brief Return Hart ID Register 281 | * 282 | * @return mhartid value 283 | */ 284 | uint32_t __get_MHARTID(void) 285 | { 286 | uint32_t result; 287 | 288 | __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); 289 | return (result); 290 | } 291 | 292 | /********************************************************************* 293 | * @fn __get_SP 294 | * 295 | * @brief Return SP Register 296 | * 297 | * @return SP value 298 | */ 299 | uint32_t __get_SP(void) 300 | { 301 | uint32_t result; 302 | 303 | __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); 304 | return (result); 305 | } 306 | 307 | -------------------------------------------------------------------------------- /adv2eth/SRC/Debug/debug.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : debug.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for UART 7 | * Printf , Delay functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #include "debug.h" 14 | 15 | static uint8_t p_us = 0; 16 | static uint16_t p_ms = 0; 17 | 18 | #define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) 19 | #define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) 20 | 21 | /********************************************************************* 22 | * @fn Delay_Init 23 | * 24 | * @brief Initializes Delay Funcation. 25 | * 26 | * @return none 27 | */ 28 | void Delay_Init(void) 29 | { 30 | p_us = SystemCoreClock / 8000000; 31 | p_ms = (uint16_t)p_us * 1000; 32 | } 33 | 34 | /********************************************************************* 35 | * @fn Delay_Us 36 | * 37 | * @brief Microsecond Delay Time. 38 | * 39 | * @param n - Microsecond number. 40 | * 41 | * @return None 42 | */ 43 | void Delay_Us(uint32_t n) 44 | { 45 | uint32_t i; 46 | 47 | SysTick->SR &= ~(1 << 0); 48 | i = (uint32_t)n * p_us; 49 | 50 | SysTick->CMP = i; 51 | SysTick->CTLR |= (1 << 4); 52 | SysTick->CTLR |= (1 << 5) | (1 << 0); 53 | 54 | while((SysTick->SR & (1 << 0)) != (1 << 0)); 55 | SysTick->CTLR &= ~(1 << 0); 56 | } 57 | 58 | /********************************************************************* 59 | * @fn Delay_Ms 60 | * 61 | * @brief Millisecond Delay Time. 62 | * 63 | * @param n - Millisecond number. 64 | * 65 | * @return None 66 | */ 67 | void Delay_Ms(uint32_t n) 68 | { 69 | uint32_t i; 70 | 71 | SysTick->SR &= ~(1 << 0); 72 | i = (uint32_t)n * p_ms; 73 | 74 | SysTick->CMP = i; 75 | SysTick->CTLR |= (1 << 4); 76 | SysTick->CTLR |= (1 << 5) | (1 << 0); 77 | 78 | while((SysTick->SR & (1 << 0)) != (1 << 0)); 79 | SysTick->CTLR &= ~(1 << 0); 80 | } 81 | 82 | /********************************************************************* 83 | * @fn USART_Printf_Init 84 | * 85 | * @brief Initializes the USARTx peripheral. 86 | * 87 | * @param baudrate - USART communication baud rate. 88 | * 89 | * @return None 90 | */ 91 | void USART_Printf_Init(uint32_t baudrate) 92 | { 93 | GPIO_InitTypeDef GPIO_InitStructure; 94 | USART_InitTypeDef USART_InitStructure; 95 | 96 | #if(DEBUG == DEBUG_UART1) 97 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); 98 | 99 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; 100 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 101 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 102 | GPIO_Init(GPIOA, &GPIO_InitStructure); 103 | 104 | #elif(DEBUG == DEBUG_UART2) 105 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); 106 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 107 | 108 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 109 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 110 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 111 | GPIO_Init(GPIOA, &GPIO_InitStructure); 112 | 113 | #elif(DEBUG == DEBUG_UART3) 114 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); 115 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 116 | 117 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 118 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 119 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 120 | GPIO_Init(GPIOB, &GPIO_InitStructure); 121 | 122 | #endif 123 | 124 | USART_InitStructure.USART_BaudRate = baudrate; 125 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 126 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 127 | USART_InitStructure.USART_Parity = USART_Parity_No; 128 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 129 | USART_InitStructure.USART_Mode = USART_Mode_Tx; 130 | 131 | #if(DEBUG == DEBUG_UART1) 132 | USART_Init(USART1, &USART_InitStructure); 133 | USART_Cmd(USART1, ENABLE); 134 | 135 | #elif(DEBUG == DEBUG_UART2) 136 | USART_Init(USART2, &USART_InitStructure); 137 | USART_Cmd(USART2, ENABLE); 138 | 139 | #elif(DEBUG == DEBUG_UART3) 140 | USART_Init(USART3, &USART_InitStructure); 141 | USART_Cmd(USART3, ENABLE); 142 | 143 | #endif 144 | } 145 | 146 | /********************************************************************* 147 | * @fn SDI_Printf_Enable 148 | * 149 | * @brief Initializes the SDI printf Function. 150 | * 151 | * @param None 152 | * 153 | * @return None 154 | */ 155 | void SDI_Printf_Enable(void) 156 | { 157 | *(DEBUG_DATA0_ADDRESS) = 0; 158 | Delay_Init(); 159 | Delay_Ms(1); 160 | } 161 | 162 | /********************************************************************* 163 | * @fn _write 164 | * 165 | * @brief Support Printf Function 166 | * 167 | * @param *buf - UART send Data. 168 | * size - Data length 169 | * 170 | * @return size: Data length 171 | */ 172 | __attribute__((used)) 173 | int _write(int fd, char *buf, int size) 174 | { 175 | int i = 0; 176 | 177 | #if (SDI_PRINT == SDI_PR_OPEN) 178 | int writeSize = size; 179 | 180 | do 181 | { 182 | 183 | /** 184 | * data0 data1 8 byte 185 | * data0 The storage length of the lowest byte, with a maximum of 7 bytes. 186 | */ 187 | 188 | while( (*(DEBUG_DATA0_ADDRESS) != 0u)) 189 | { 190 | 191 | } 192 | 193 | if(writeSize>7) 194 | { 195 | *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); 196 | *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); 197 | 198 | i += 7; 199 | writeSize -= 7; 200 | } 201 | else 202 | { 203 | *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); 204 | *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); 205 | 206 | writeSize = 0; 207 | } 208 | 209 | } while (writeSize); 210 | 211 | 212 | #else 213 | for(i = 0; i < size; i++){ 214 | #if(DEBUG == DEBUG_UART1) 215 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); 216 | USART_SendData(USART1, *buf++); 217 | #elif(DEBUG == DEBUG_UART2) 218 | while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); 219 | USART_SendData(USART2, *buf++); 220 | #elif(DEBUG == DEBUG_UART3) 221 | while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); 222 | USART_SendData(USART3, *buf++); 223 | #endif 224 | } 225 | #endif 226 | return size; 227 | } 228 | 229 | /********************************************************************* 230 | * @fn _sbrk 231 | * 232 | * @brief Change the spatial position of data segment. 233 | * 234 | * @return size: Data length 235 | */ 236 | __attribute__((used)) 237 | void *_sbrk(ptrdiff_t incr) 238 | { 239 | extern char _end[]; 240 | extern char _heap_end[]; 241 | static char *curbrk = _end; 242 | 243 | if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) 244 | return NULL - 1; 245 | 246 | curbrk += incr; 247 | return curbrk - incr; 248 | } 249 | -------------------------------------------------------------------------------- /adv2eth/SRC/Debug/debug.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : debug.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2023/10/24 6 | * Description : This file contains all the functions prototypes for UART 7 | * Printf , Delay functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __DEBUG_H 14 | #define __DEBUG_H 15 | 16 | #include "stdio.h" 17 | #include "ch32v20x.h" 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | /* UART Printf Definition */ 24 | #define DEBUG_UART1 1 25 | #define DEBUG_UART2 2 26 | #define DEBUG_UART3 3 27 | 28 | /* DEBUG UATR Definition */ 29 | #ifndef DEBUG 30 | #define DEBUG DEBUG_UART1 31 | #endif 32 | 33 | /* SDI Printf Definition */ 34 | #define SDI_PR_CLOSE 0 35 | #define SDI_PR_OPEN 1 36 | 37 | #ifndef SDI_PRINT 38 | #define SDI_PRINT SDI_PR_CLOSE 39 | #endif 40 | 41 | 42 | void Delay_Init(void); 43 | void Delay_Us(uint32_t n); 44 | void Delay_Ms(uint32_t n); 45 | void USART_Printf_Init(uint32_t baudrate); 46 | void SDI_Printf_Enable(void); 47 | 48 | #if(DEBUG) 49 | #define PRINT(format, ...) printf(format, ##__VA_ARGS__) 50 | #else 51 | #define PRINT(X...) 52 | #endif 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif 59 | -------------------------------------------------------------------------------- /adv2eth/SRC/Ld/Link.ld: -------------------------------------------------------------------------------- 1 | ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /**/ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_bkp.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_bkp.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * BKP firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_BKP_H 14 | #define __CH32V20x_BKP_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* Tamper_Pin_active_level */ 23 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 24 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 25 | 26 | /* RTC_output_source_to_output_on_the_Tamper_pin */ 27 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 28 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 29 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 30 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 31 | 32 | /* Data_Backup_Register */ 33 | #define BKP_DR1 ((uint16_t)0x0004) 34 | #define BKP_DR2 ((uint16_t)0x0008) 35 | #define BKP_DR3 ((uint16_t)0x000C) 36 | #define BKP_DR4 ((uint16_t)0x0010) 37 | #define BKP_DR5 ((uint16_t)0x0014) 38 | #define BKP_DR6 ((uint16_t)0x0018) 39 | #define BKP_DR7 ((uint16_t)0x001C) 40 | #define BKP_DR8 ((uint16_t)0x0020) 41 | #define BKP_DR9 ((uint16_t)0x0024) 42 | #define BKP_DR10 ((uint16_t)0x0028) 43 | #define BKP_DR11 ((uint16_t)0x0040) 44 | #define BKP_DR12 ((uint16_t)0x0044) 45 | #define BKP_DR13 ((uint16_t)0x0048) 46 | #define BKP_DR14 ((uint16_t)0x004C) 47 | #define BKP_DR15 ((uint16_t)0x0050) 48 | #define BKP_DR16 ((uint16_t)0x0054) 49 | #define BKP_DR17 ((uint16_t)0x0058) 50 | #define BKP_DR18 ((uint16_t)0x005C) 51 | #define BKP_DR19 ((uint16_t)0x0060) 52 | #define BKP_DR20 ((uint16_t)0x0064) 53 | #define BKP_DR21 ((uint16_t)0x0068) 54 | #define BKP_DR22 ((uint16_t)0x006C) 55 | #define BKP_DR23 ((uint16_t)0x0070) 56 | #define BKP_DR24 ((uint16_t)0x0074) 57 | #define BKP_DR25 ((uint16_t)0x0078) 58 | #define BKP_DR26 ((uint16_t)0x007C) 59 | #define BKP_DR27 ((uint16_t)0x0080) 60 | #define BKP_DR28 ((uint16_t)0x0084) 61 | #define BKP_DR29 ((uint16_t)0x0088) 62 | #define BKP_DR30 ((uint16_t)0x008C) 63 | #define BKP_DR31 ((uint16_t)0x0090) 64 | #define BKP_DR32 ((uint16_t)0x0094) 65 | #define BKP_DR33 ((uint16_t)0x0098) 66 | #define BKP_DR34 ((uint16_t)0x009C) 67 | #define BKP_DR35 ((uint16_t)0x00A0) 68 | #define BKP_DR36 ((uint16_t)0x00A4) 69 | #define BKP_DR37 ((uint16_t)0x00A8) 70 | #define BKP_DR38 ((uint16_t)0x00AC) 71 | #define BKP_DR39 ((uint16_t)0x00B0) 72 | #define BKP_DR40 ((uint16_t)0x00B4) 73 | #define BKP_DR41 ((uint16_t)0x00B8) 74 | #define BKP_DR42 ((uint16_t)0x00BC) 75 | 76 | void BKP_DeInit(void); 77 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 78 | void BKP_TamperPinCmd(FunctionalState NewState); 79 | void BKP_ITConfig(FunctionalState NewState); 80 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 81 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 82 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 83 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 84 | FlagStatus BKP_GetFlagStatus(void); 85 | void BKP_ClearFlag(void); 86 | ITStatus BKP_GetITStatus(void); 87 | void BKP_ClearITPendingBit(void); 88 | 89 | #ifdef __cplusplus 90 | } 91 | #endif 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_crc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_crc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * CRC firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_CRC_H 14 | #define __CH32V20x_CRC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | void CRC_ResetDR(void); 23 | uint32_t CRC_CalcCRC(uint32_t Data); 24 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 25 | uint32_t CRC_GetCRC(void); 26 | void CRC_SetIDRegister(uint8_t IDValue); 27 | uint8_t CRC_GetIDRegister(void); 28 | 29 | #ifdef __cplusplus 30 | } 31 | #endif 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_dbgmcu.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DBGMCU firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_DBGMCU_H 14 | #define __CH32V20x_DBGMCU_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 23 | #define DBGMCU_STOP ((uint32_t)0x00000002) 24 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 25 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 26 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 27 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) 28 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) 29 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) 30 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) 31 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) 32 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) 33 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) 34 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) 35 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) 36 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) 37 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) 38 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 39 | #define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) 40 | #define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) 41 | 42 | uint32_t DBGMCU_GetREVID(void); 43 | uint32_t DBGMCU_GetDEVID(void); 44 | uint32_t __get_DEBUG_CR(void); 45 | void __set_DEBUG_CR(uint32_t value); 46 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 47 | uint32_t DBGMCU_GetCHIPID( void ); 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_dma.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_dma.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DMA firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_DMA_H 14 | #define __CH32V20x_DMA_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* DMA Init structure definition */ 23 | typedef struct 24 | { 25 | uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ 26 | 27 | uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ 28 | 29 | uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. 30 | This parameter can be a value of @ref DMA_data_transfer_direction */ 31 | 32 | uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. 33 | The data unit is equal to the configuration set in DMA_PeripheralDataSize 34 | or DMA_MemoryDataSize members depending in the transfer direction. */ 35 | 36 | uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. 37 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 38 | 39 | uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. 40 | This parameter can be a value of @ref DMA_memory_incremented_mode */ 41 | 42 | uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. 43 | This parameter can be a value of @ref DMA_peripheral_data_size */ 44 | 45 | uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. 46 | This parameter can be a value of @ref DMA_memory_data_size */ 47 | 48 | uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. 49 | This parameter can be a value of @ref DMA_circular_normal_mode. 50 | @note: The circular buffer mode cannot be used if the memory-to-memory 51 | data transfer is configured on the selected Channel */ 52 | 53 | uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. 54 | This parameter can be a value of @ref DMA_priority_level */ 55 | 56 | uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 57 | This parameter can be a value of @ref DMA_memory_to_memory */ 58 | } DMA_InitTypeDef; 59 | 60 | /* DMA_data_transfer_direction */ 61 | #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) 62 | #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 63 | 64 | /* DMA_peripheral_incremented_mode */ 65 | #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) 66 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 67 | 68 | /* DMA_memory_incremented_mode */ 69 | #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) 70 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 71 | 72 | /* DMA_peripheral_data_size */ 73 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 74 | #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) 75 | #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) 76 | 77 | /* DMA_memory_data_size */ 78 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 79 | #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 80 | #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 81 | 82 | /* DMA_circular_normal_mode */ 83 | #define DMA_Mode_Circular ((uint32_t)0x00000020) 84 | #define DMA_Mode_Normal ((uint32_t)0x00000000) 85 | 86 | /* DMA_priority_level */ 87 | #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) 88 | #define DMA_Priority_High ((uint32_t)0x00002000) 89 | #define DMA_Priority_Medium ((uint32_t)0x00001000) 90 | #define DMA_Priority_Low ((uint32_t)0x00000000) 91 | 92 | /* DMA_memory_to_memory */ 93 | #define DMA_M2M_Enable ((uint32_t)0x00004000) 94 | #define DMA_M2M_Disable ((uint32_t)0x00000000) 95 | 96 | /* DMA_interrupts_definition */ 97 | #define DMA_IT_TC ((uint32_t)0x00000002) 98 | #define DMA_IT_HT ((uint32_t)0x00000004) 99 | #define DMA_IT_TE ((uint32_t)0x00000008) 100 | 101 | #define DMA1_IT_GL1 ((uint32_t)0x00000001) 102 | #define DMA1_IT_TC1 ((uint32_t)0x00000002) 103 | #define DMA1_IT_HT1 ((uint32_t)0x00000004) 104 | #define DMA1_IT_TE1 ((uint32_t)0x00000008) 105 | #define DMA1_IT_GL2 ((uint32_t)0x00000010) 106 | #define DMA1_IT_TC2 ((uint32_t)0x00000020) 107 | #define DMA1_IT_HT2 ((uint32_t)0x00000040) 108 | #define DMA1_IT_TE2 ((uint32_t)0x00000080) 109 | #define DMA1_IT_GL3 ((uint32_t)0x00000100) 110 | #define DMA1_IT_TC3 ((uint32_t)0x00000200) 111 | #define DMA1_IT_HT3 ((uint32_t)0x00000400) 112 | #define DMA1_IT_TE3 ((uint32_t)0x00000800) 113 | #define DMA1_IT_GL4 ((uint32_t)0x00001000) 114 | #define DMA1_IT_TC4 ((uint32_t)0x00002000) 115 | #define DMA1_IT_HT4 ((uint32_t)0x00004000) 116 | #define DMA1_IT_TE4 ((uint32_t)0x00008000) 117 | #define DMA1_IT_GL5 ((uint32_t)0x00010000) 118 | #define DMA1_IT_TC5 ((uint32_t)0x00020000) 119 | #define DMA1_IT_HT5 ((uint32_t)0x00040000) 120 | #define DMA1_IT_TE5 ((uint32_t)0x00080000) 121 | #define DMA1_IT_GL6 ((uint32_t)0x00100000) 122 | #define DMA1_IT_TC6 ((uint32_t)0x00200000) 123 | #define DMA1_IT_HT6 ((uint32_t)0x00400000) 124 | #define DMA1_IT_TE6 ((uint32_t)0x00800000) 125 | #define DMA1_IT_GL7 ((uint32_t)0x01000000) 126 | #define DMA1_IT_TC7 ((uint32_t)0x02000000) 127 | #define DMA1_IT_HT7 ((uint32_t)0x04000000) 128 | #define DMA1_IT_TE7 ((uint32_t)0x08000000) 129 | #define DMA1_IT_GL8 ((uint32_t)0x10000000) 130 | #define DMA1_IT_TC8 ((uint32_t)0x20000000) 131 | #define DMA1_IT_HT8 ((uint32_t)0x40000000) 132 | #define DMA1_IT_TE8 ((uint32_t)0x80000000) 133 | 134 | /* DMA_flags_definition */ 135 | #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) 136 | #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) 137 | #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) 138 | #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) 139 | #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) 140 | #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) 141 | #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) 142 | #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) 143 | #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) 144 | #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) 145 | #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) 146 | #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) 147 | #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) 148 | #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) 149 | #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) 150 | #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) 151 | #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) 152 | #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) 153 | #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) 154 | #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) 155 | #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) 156 | #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) 157 | #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) 158 | #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) 159 | #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) 160 | #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) 161 | #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) 162 | #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) 163 | #define DMA1_FLAG_GL8 ((uint32_t)0x10000000) 164 | #define DMA1_FLAG_TC8 ((uint32_t)0x20000000) 165 | #define DMA1_FLAG_HT8 ((uint32_t)0x40000000) 166 | #define DMA1_FLAG_TE8 ((uint32_t)0x80000000) 167 | 168 | void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); 169 | void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); 170 | void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); 171 | void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); 172 | void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 173 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); 174 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); 175 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); 176 | void DMA_ClearFlag(uint32_t DMAy_FLAG); 177 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT); 178 | void DMA_ClearITPendingBit(uint32_t DMAy_IT); 179 | 180 | #ifdef __cplusplus 181 | } 182 | #endif 183 | 184 | #endif 185 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_exti.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_exti.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * EXTI firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_EXTI_H 14 | #define __CH32V20x_EXTI_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* EXTI mode enumeration */ 23 | typedef enum 24 | { 25 | EXTI_Mode_Interrupt = 0x00, 26 | EXTI_Mode_Event = 0x04 27 | } EXTIMode_TypeDef; 28 | 29 | /* EXTI Trigger enumeration */ 30 | typedef enum 31 | { 32 | EXTI_Trigger_Rising = 0x08, 33 | EXTI_Trigger_Falling = 0x0C, 34 | EXTI_Trigger_Rising_Falling = 0x10 35 | } EXTITrigger_TypeDef; 36 | 37 | /* EXTI Init Structure definition */ 38 | typedef struct 39 | { 40 | uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. 41 | This parameter can be any combination of @ref EXTI_Lines */ 42 | 43 | EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. 44 | This parameter can be a value of @ref EXTIMode_TypeDef */ 45 | 46 | EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. 47 | This parameter can be a value of @ref EXTIMode_TypeDef */ 48 | 49 | FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. 50 | This parameter can be set either to ENABLE or DISABLE */ 51 | } EXTI_InitTypeDef; 52 | 53 | /* EXTI_Lines */ 54 | #define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ 55 | #define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ 56 | #define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ 57 | #define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ 58 | #define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ 59 | #define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ 60 | #define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ 61 | #define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ 62 | #define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ 63 | #define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ 64 | #define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ 65 | #define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ 66 | #define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ 67 | #define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ 68 | #define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ 69 | #define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ 70 | #define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ 71 | #define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ 72 | #define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \ 73 | Wakeup from suspend event */ 74 | #define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ 75 | #define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */ 76 | 77 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 78 | #define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */ 79 | 80 | #endif 81 | 82 | void EXTI_DeInit(void); 83 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); 84 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); 85 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 86 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 87 | void EXTI_ClearFlag(uint32_t EXTI_Line); 88 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 89 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif 96 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_flash.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_flash.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the FLASH 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_FLASH_H 14 | #define __CH32V20x_FLASH_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* FLASH Status */ 23 | typedef enum 24 | { 25 | FLASH_BUSY = 1, 26 | FLASH_ERROR_PG, 27 | FLASH_ERROR_WRP, 28 | FLASH_COMPLETE, 29 | FLASH_TIMEOUT, 30 | FLASH_OP_RANGE_ERROR = 0xFD, 31 | FLASH_ALIGN_ERROR = 0xFE, 32 | FLASH_ADR_RANGE_ERROR = 0xFF, 33 | } FLASH_Status; 34 | 35 | /* Write Protect */ 36 | #define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ 37 | #define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ 38 | #define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ 39 | #define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ 40 | #define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ 41 | #define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ 42 | #define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ 43 | #define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ 44 | #define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ 45 | #define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ 46 | #define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ 47 | #define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ 48 | #define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ 49 | #define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ 50 | #define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ 51 | #define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ 52 | #define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ 53 | #define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ 54 | #define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ 55 | #define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ 56 | #define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ 57 | #define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ 58 | #define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ 59 | #define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ 60 | #define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ 61 | #define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ 62 | #define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ 63 | #define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ 64 | #define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ 65 | #define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ 66 | #define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ 67 | #define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ 68 | 69 | #define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ 70 | 71 | /* Option_Bytes_IWatchdog */ 72 | #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ 73 | #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ 74 | 75 | /* Option_Bytes_nRST_STOP */ 76 | #define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ 77 | #define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ 78 | 79 | /* Option_Bytes_nRST_STDBY */ 80 | #define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ 81 | #define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ 82 | 83 | /* FLASH_Interrupts */ 84 | #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ 85 | #define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ 86 | #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ 87 | #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ 88 | 89 | /* FLASH_Flags */ 90 | #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ 91 | #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ 92 | #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ 93 | #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ 94 | 95 | #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ 96 | #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ 97 | #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ 98 | 99 | /* FLASH_Access_CLK */ 100 | #define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */ 101 | #define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */ 102 | 103 | /*Functions used for all devices*/ 104 | void FLASH_Unlock(void); 105 | void FLASH_Lock(void); 106 | FLASH_Status FLASH_ErasePage(uint32_t Page_Address); 107 | FLASH_Status FLASH_EraseAllPages(void); 108 | FLASH_Status FLASH_EraseOptionBytes(void); 109 | FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); 110 | FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); 111 | FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); 112 | FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); 113 | FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); 114 | FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); 115 | uint32_t FLASH_GetUserOptionByte(void); 116 | uint32_t FLASH_GetWriteProtectionOptionByte(void); 117 | FlagStatus FLASH_GetReadOutProtectionStatus(void); 118 | void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); 119 | FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); 120 | void FLASH_ClearFlag(uint32_t FLASH_FLAG); 121 | FLASH_Status FLASH_GetStatus(void); 122 | FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); 123 | void FLASH_Unlock_Fast(void); 124 | void FLASH_Lock_Fast(void); 125 | void FLASH_ErasePage_Fast(uint32_t Page_Address); 126 | void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); 127 | void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); 128 | void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf); 129 | void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); 130 | void FLASH_Enhance_Mode(FunctionalState NewState); 131 | 132 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 133 | void FLASH_GetMACAddress(uint8_t *Buffer); 134 | #endif 135 | 136 | /* New function used for all devices */ 137 | void FLASH_UnlockBank1(void); 138 | void FLASH_LockBank1(void); 139 | FLASH_Status FLASH_EraseAllBank1Pages(void); 140 | FLASH_Status FLASH_GetBank1Status(void); 141 | FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); 142 | FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); 143 | FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif 148 | 149 | #endif 150 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_iwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_iwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * IWDG firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_IWDG_H 14 | #define __CH32V20x_IWDG_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* IWDG_WriteAccess */ 23 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 24 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 25 | 26 | /* IWDG_prescaler */ 27 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 28 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 29 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 30 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 31 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 32 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 33 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 34 | 35 | /* IWDG_Flag */ 36 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 37 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 38 | 39 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 40 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 41 | void IWDG_SetReload(uint16_t Reload); 42 | void IWDG_ReloadCounter(void); 43 | void IWDG_Enable(void); 44 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_misc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_misc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * miscellaneous firmware library functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_MISC_H 14 | #define __CH32V20x_MISC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* NVIC Init Structure definition */ 23 | typedef struct 24 | { 25 | uint8_t NVIC_IRQChannel; 26 | uint8_t NVIC_IRQChannelPreemptionPriority; 27 | uint8_t NVIC_IRQChannelSubPriority; 28 | FunctionalState NVIC_IRQChannelCmd; 29 | } NVIC_InitTypeDef; 30 | 31 | /* Preemption_Priority_Group */ 32 | #define NVIC_PriorityGroup_0 ((uint32_t)0x00) 33 | #define NVIC_PriorityGroup_1 ((uint32_t)0x01) 34 | #define NVIC_PriorityGroup_2 ((uint32_t)0x02) 35 | #define NVIC_PriorityGroup_3 ((uint32_t)0x03) 36 | #define NVIC_PriorityGroup_4 ((uint32_t)0x04) 37 | 38 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 39 | void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_opa.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_opa.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * OPA firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_OPA_H 14 | #define __CH32V20x_OPA_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | #define OPA_PSEL_OFFSET 3 23 | #define OPA_NSEL_OFFSET 2 24 | #define OPA_MODE_OFFSET 1 25 | 26 | /* OPA member enumeration */ 27 | typedef enum 28 | { 29 | OPA1 = 0, 30 | OPA2, 31 | OPA3, 32 | OPA4 33 | } OPA_Num_TypeDef; 34 | 35 | /* OPA PSEL enumeration */ 36 | typedef enum 37 | { 38 | CHP0 = 0, 39 | CHP1 40 | } OPA_PSEL_TypeDef; 41 | 42 | /* OPA NSEL enumeration */ 43 | typedef enum 44 | { 45 | CHN0 = 0, 46 | CHN1 47 | } OPA_NSEL_TypeDef; 48 | 49 | /* OPA out channel enumeration */ 50 | typedef enum 51 | { 52 | OUT_IO_OUT0 = 0, 53 | OUT_IO_OUT1 54 | } OPA_Mode_TypeDef; 55 | 56 | /* OPA Init Structure definition */ 57 | typedef struct 58 | { 59 | OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ 60 | OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ 61 | OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ 62 | OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ 63 | } OPA_InitTypeDef; 64 | 65 | void OPA_DeInit(void); 66 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); 67 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); 68 | void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif 73 | 74 | #endif 75 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_pwr.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_pwr.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the PWR 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_PWR_H 14 | #define __CH32V20x_PWR_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* PVD_detection_level */ 23 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 24 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 25 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 26 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 27 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 28 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 29 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 30 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 31 | 32 | /* Regulator_state_is_STOP_mode */ 33 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 34 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 35 | 36 | /* STOP_mode_entry */ 37 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 38 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 39 | 40 | /* PWR_Flag */ 41 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 42 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 43 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 44 | 45 | void PWR_DeInit(void); 46 | void PWR_BackupAccessCmd(FunctionalState NewState); 47 | void PWR_PVDCmd(FunctionalState NewState); 48 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 49 | void PWR_WakeUpPinCmd(FunctionalState NewState); 50 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 51 | void PWR_EnterSTANDBYMode(void); 52 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 53 | void PWR_ClearFlag(uint32_t PWR_FLAG); 54 | void PWR_EnterSTANDBYMode_RAM(void); 55 | void PWR_EnterSTANDBYMode_RAM_LV(void); 56 | void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); 57 | void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); 58 | void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_rtc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_rtc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the RTC 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_RTC_H 14 | #define __CH32V20x_RTC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | typedef enum 23 | { 24 | Level_32 = 2, 25 | Level_64, 26 | Level_128, 27 | 28 | } Cali_LevelTypeDef; 29 | 30 | /* RTC_interrupts_define */ 31 | #define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ 32 | #define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ 33 | #define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ 34 | 35 | /* RTC_interrupts_flags */ 36 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ 37 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ 38 | #define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ 39 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ 40 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ 41 | 42 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 43 | #define RB_OSC32K_HTUNE (0x1FE0) 44 | #define RB_OSC32K_LTUNE (0x1F) 45 | 46 | #define RB_OSC_CAL_HALT (0x80) 47 | #define RB_OSC_CAL_EN (0x02) 48 | #define RB_OSC_CAL_INT_EN (0x01) 49 | 50 | #define RB_OSC_CAL_OV_CNT (0xFF) 51 | 52 | #define RB_OSC_CAL_IF_END (1 << 15) 53 | #define RB_OSC_CAL_CNT_OV (1 << 14) 54 | #define RB_OSC_CAL_CNT (0x3FFF) 55 | 56 | #define RB_CAL_LP_EN (1 << 6) 57 | #define RB_CAL_WKUP_EN (1 << 5) 58 | #define RB_OSC_HALT_MD (1 << 4) 59 | #define RB_OSC_CNT_VLU (0x0F) 60 | 61 | 62 | #ifdef CLK_OSC32K 63 | #if ( CLK_OSC32K == 1 ) 64 | #define CAB_LSIFQ 32000 65 | #else 66 | #define CAB_LSIFQ 32768 67 | #endif 68 | #else 69 | #define CAB_LSIFQ 32000 70 | #endif 71 | #endif 72 | 73 | 74 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 75 | void RTC_EnterConfigMode(void); 76 | void RTC_ExitConfigMode(void); 77 | uint32_t RTC_GetCounter(void); 78 | void RTC_SetCounter(uint32_t CounterValue); 79 | void RTC_SetPrescaler(uint32_t PrescalerValue); 80 | void RTC_SetAlarm(uint32_t AlarmValue); 81 | uint32_t RTC_GetDivider(void); 82 | void RTC_WaitForLastTask(void); 83 | void RTC_WaitForSynchro(void); 84 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 85 | void RTC_ClearFlag(uint16_t RTC_FLAG); 86 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 87 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 88 | 89 | #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) 90 | void Calibration_LSI(Cali_LevelTypeDef cali_Lv); 91 | 92 | #endif 93 | 94 | #ifdef __cplusplus 95 | } 96 | #endif 97 | 98 | #endif 99 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_spi.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_spi.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * SPI firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_SPI_H 14 | #define __CH32V20x_SPI_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* SPI Init structure definition */ 23 | typedef struct 24 | { 25 | uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. 26 | This parameter can be a value of @ref SPI_data_direction */ 27 | 28 | uint16_t SPI_Mode; /* Specifies the SPI operating mode. 29 | This parameter can be a value of @ref SPI_mode */ 30 | 31 | uint16_t SPI_DataSize; /* Specifies the SPI data size. 32 | This parameter can be a value of @ref SPI_data_size */ 33 | 34 | uint16_t SPI_CPOL; /* Specifies the serial clock steady state. 35 | This parameter can be a value of @ref SPI_Clock_Polarity */ 36 | 37 | uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. 38 | This parameter can be a value of @ref SPI_Clock_Phase */ 39 | 40 | uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by 41 | hardware (NSS pin) or by software using the SSI bit. 42 | This parameter can be a value of @ref SPI_Slave_Select_management */ 43 | 44 | uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be 45 | used to configure the transmit and receive SCK clock. 46 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. 47 | @note The communication clock is derived from the master 48 | clock. The slave clock does not need to be set. */ 49 | 50 | uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. 51 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 52 | 53 | uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ 54 | } SPI_InitTypeDef; 55 | 56 | /* I2S Init structure definition */ 57 | typedef struct 58 | { 59 | uint16_t I2S_Mode; /* Specifies the I2S operating mode. 60 | This parameter can be a value of @ref I2S_Mode */ 61 | 62 | uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. 63 | This parameter can be a value of @ref I2S_Standard */ 64 | 65 | uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. 66 | This parameter can be a value of @ref I2S_Data_Format */ 67 | 68 | uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. 69 | This parameter can be a value of @ref I2S_MCLK_Output */ 70 | 71 | uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. 72 | This parameter can be a value of @ref I2S_Audio_Frequency */ 73 | 74 | uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. 75 | This parameter can be a value of @ref I2S_Clock_Polarity */ 76 | } I2S_InitTypeDef; 77 | 78 | /* SPI_data_direction */ 79 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 80 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 81 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 82 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 83 | 84 | /* SPI_mode */ 85 | #define SPI_Mode_Master ((uint16_t)0x0104) 86 | #define SPI_Mode_Slave ((uint16_t)0x0000) 87 | 88 | /* SPI_data_size */ 89 | #define SPI_DataSize_16b ((uint16_t)0x0800) 90 | #define SPI_DataSize_8b ((uint16_t)0x0000) 91 | 92 | /* SPI_Clock_Polarity */ 93 | #define SPI_CPOL_Low ((uint16_t)0x0000) 94 | #define SPI_CPOL_High ((uint16_t)0x0002) 95 | 96 | /* SPI_Clock_Phase */ 97 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) 98 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) 99 | 100 | /* SPI_Slave_Select_management */ 101 | #define SPI_NSS_Soft ((uint16_t)0x0200) 102 | #define SPI_NSS_Hard ((uint16_t)0x0000) 103 | 104 | /* SPI_BaudRate_Prescaler */ 105 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 106 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 107 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 108 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 109 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 110 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 111 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 112 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 113 | 114 | /* SPI_MSB_LSB_transmission */ 115 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) 116 | #define SPI_FirstBit_LSB ((uint16_t)0x0080) 117 | 118 | /* I2S_Mode */ 119 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 120 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 121 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) 122 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) 123 | 124 | /* I2S_Standard */ 125 | #define I2S_Standard_Phillips ((uint16_t)0x0000) 126 | #define I2S_Standard_MSB ((uint16_t)0x0010) 127 | #define I2S_Standard_LSB ((uint16_t)0x0020) 128 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) 129 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 130 | 131 | /* I2S_Data_Format */ 132 | #define I2S_DataFormat_16b ((uint16_t)0x0000) 133 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 134 | #define I2S_DataFormat_24b ((uint16_t)0x0003) 135 | #define I2S_DataFormat_32b ((uint16_t)0x0005) 136 | 137 | /* I2S_MCLK_Output */ 138 | #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 139 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 140 | 141 | /* I2S_Audio_Frequency */ 142 | #define I2S_AudioFreq_192k ((uint32_t)192000) 143 | #define I2S_AudioFreq_96k ((uint32_t)96000) 144 | #define I2S_AudioFreq_48k ((uint32_t)48000) 145 | #define I2S_AudioFreq_44k ((uint32_t)44100) 146 | #define I2S_AudioFreq_32k ((uint32_t)32000) 147 | #define I2S_AudioFreq_22k ((uint32_t)22050) 148 | #define I2S_AudioFreq_16k ((uint32_t)16000) 149 | #define I2S_AudioFreq_11k ((uint32_t)11025) 150 | #define I2S_AudioFreq_8k ((uint32_t)8000) 151 | #define I2S_AudioFreq_Default ((uint32_t)2) 152 | 153 | /* I2S_Clock_Polarity */ 154 | #define I2S_CPOL_Low ((uint16_t)0x0000) 155 | #define I2S_CPOL_High ((uint16_t)0x0008) 156 | 157 | /* SPI_I2S_DMA_transfer_requests */ 158 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 159 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 160 | 161 | /* SPI_NSS_internal_software_management */ 162 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 163 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 164 | 165 | /* SPI_CRC_Transmit_Receive */ 166 | #define SPI_CRC_Tx ((uint8_t)0x00) 167 | #define SPI_CRC_Rx ((uint8_t)0x01) 168 | 169 | /* SPI_direction_transmit_receive */ 170 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) 171 | #define SPI_Direction_Tx ((uint16_t)0x4000) 172 | 173 | /* SPI_I2S_interrupts_definition */ 174 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) 175 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 176 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) 177 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) 178 | #define SPI_IT_MODF ((uint8_t)0x55) 179 | #define SPI_IT_CRCERR ((uint8_t)0x54) 180 | #define I2S_IT_UDR ((uint8_t)0x53) 181 | 182 | /* SPI_I2S_flags_definition */ 183 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 184 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 185 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 186 | #define I2S_FLAG_UDR ((uint16_t)0x0008) 187 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 188 | #define SPI_FLAG_MODF ((uint16_t)0x0020) 189 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 190 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 191 | 192 | void SPI_I2S_DeInit(SPI_TypeDef *SPIx); 193 | void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); 194 | void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct); 195 | void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); 196 | void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct); 197 | void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); 198 | void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); 199 | void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 200 | void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 201 | void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); 202 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); 203 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); 204 | void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); 205 | void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); 206 | void SPI_TransmitCRC(SPI_TypeDef *SPIx); 207 | void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); 208 | uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); 209 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); 210 | void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); 211 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); 212 | void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); 213 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); 214 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); 215 | 216 | #ifdef __cplusplus 217 | } 218 | #endif 219 | 220 | #endif 221 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_usart.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_usart.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * USART firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_USART_H 14 | #define __CH32V20x_USART_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* USART Init Structure definition */ 23 | typedef struct 24 | { 25 | uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. 26 | The baud rate is computed using the following formula: 27 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) 28 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ 29 | 30 | uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. 31 | This parameter can be a value of @ref USART_Word_Length */ 32 | 33 | uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. 34 | This parameter can be a value of @ref USART_Stop_Bits */ 35 | 36 | uint16_t USART_Parity; /* Specifies the parity mode. 37 | This parameter can be a value of @ref USART_Parity 38 | @note When parity is enabled, the computed parity is inserted 39 | at the MSB position of the transmitted data (9th bit when 40 | the word length is set to 9 data bits; 8th bit when the 41 | word length is set to 8 data bits). */ 42 | 43 | uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. 44 | This parameter can be a value of @ref USART_Mode */ 45 | 46 | uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled 47 | or disabled. 48 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ 49 | } USART_InitTypeDef; 50 | 51 | /* USART Clock Init Structure definition */ 52 | typedef struct 53 | { 54 | uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. 55 | This parameter can be a value of @ref USART_Clock */ 56 | 57 | uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. 58 | This parameter can be a value of @ref USART_Clock_Polarity */ 59 | 60 | uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. 61 | This parameter can be a value of @ref USART_Clock_Phase */ 62 | 63 | uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted 64 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. 65 | This parameter can be a value of @ref USART_Last_Bit */ 66 | } USART_ClockInitTypeDef; 67 | 68 | /* USART_Word_Length */ 69 | #define USART_WordLength_8b ((uint16_t)0x0000) 70 | #define USART_WordLength_9b ((uint16_t)0x1000) 71 | 72 | /* USART_Stop_Bits */ 73 | #define USART_StopBits_1 ((uint16_t)0x0000) 74 | #define USART_StopBits_0_5 ((uint16_t)0x1000) 75 | #define USART_StopBits_2 ((uint16_t)0x2000) 76 | #define USART_StopBits_1_5 ((uint16_t)0x3000) 77 | 78 | /* USART_Parity */ 79 | #define USART_Parity_No ((uint16_t)0x0000) 80 | #define USART_Parity_Even ((uint16_t)0x0400) 81 | #define USART_Parity_Odd ((uint16_t)0x0600) 82 | 83 | /* USART_Mode */ 84 | #define USART_Mode_Rx ((uint16_t)0x0004) 85 | #define USART_Mode_Tx ((uint16_t)0x0008) 86 | 87 | /* USART_Hardware_Flow_Control */ 88 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) 89 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) 90 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) 91 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) 92 | 93 | /* USART_Clock */ 94 | #define USART_Clock_Disable ((uint16_t)0x0000) 95 | #define USART_Clock_Enable ((uint16_t)0x0800) 96 | 97 | /* USART_Clock_Polarity */ 98 | #define USART_CPOL_Low ((uint16_t)0x0000) 99 | #define USART_CPOL_High ((uint16_t)0x0400) 100 | 101 | /* USART_Clock_Phase */ 102 | #define USART_CPHA_1Edge ((uint16_t)0x0000) 103 | #define USART_CPHA_2Edge ((uint16_t)0x0200) 104 | 105 | /* USART_Last_Bit */ 106 | #define USART_LastBit_Disable ((uint16_t)0x0000) 107 | #define USART_LastBit_Enable ((uint16_t)0x0100) 108 | 109 | /* USART_Interrupt_definition */ 110 | #define USART_IT_PE ((uint16_t)0x0028) 111 | #define USART_IT_TXE ((uint16_t)0x0727) 112 | #define USART_IT_TC ((uint16_t)0x0626) 113 | #define USART_IT_RXNE ((uint16_t)0x0525) 114 | #define USART_IT_ORE_RX ((uint16_t)0x0325) 115 | #define USART_IT_IDLE ((uint16_t)0x0424) 116 | #define USART_IT_LBD ((uint16_t)0x0846) 117 | #define USART_IT_CTS ((uint16_t)0x096A) 118 | #define USART_IT_ERR ((uint16_t)0x0060) 119 | #define USART_IT_ORE_ER ((uint16_t)0x0360) 120 | #define USART_IT_NE ((uint16_t)0x0260) 121 | #define USART_IT_FE ((uint16_t)0x0160) 122 | 123 | #define USART_IT_ORE USART_IT_ORE_ER 124 | 125 | /* USART_DMA_Requests */ 126 | #define USART_DMAReq_Tx ((uint16_t)0x0080) 127 | #define USART_DMAReq_Rx ((uint16_t)0x0040) 128 | 129 | /* USART_WakeUp_methods */ 130 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) 131 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) 132 | 133 | /* USART_LIN_Break_Detection_Length */ 134 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) 135 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) 136 | 137 | /* USART_IrDA_Low_Power */ 138 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) 139 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) 140 | 141 | /* USART_Flags */ 142 | #define USART_FLAG_CTS ((uint16_t)0x0200) 143 | #define USART_FLAG_LBD ((uint16_t)0x0100) 144 | #define USART_FLAG_TXE ((uint16_t)0x0080) 145 | #define USART_FLAG_TC ((uint16_t)0x0040) 146 | #define USART_FLAG_RXNE ((uint16_t)0x0020) 147 | #define USART_FLAG_IDLE ((uint16_t)0x0010) 148 | #define USART_FLAG_ORE ((uint16_t)0x0008) 149 | #define USART_FLAG_NE ((uint16_t)0x0004) 150 | #define USART_FLAG_FE ((uint16_t)0x0002) 151 | #define USART_FLAG_PE ((uint16_t)0x0001) 152 | 153 | void USART_DeInit(USART_TypeDef *USARTx); 154 | void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); 155 | void USART_StructInit(USART_InitTypeDef *USART_InitStruct); 156 | void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); 157 | void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); 158 | void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); 159 | void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); 160 | void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); 161 | void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); 162 | void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); 163 | void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); 164 | void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); 165 | void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); 166 | void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); 167 | uint16_t USART_ReceiveData(USART_TypeDef *USARTx); 168 | void USART_SendBreak(USART_TypeDef *USARTx); 169 | void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); 170 | void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); 171 | void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); 172 | void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); 173 | void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); 174 | void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); 175 | void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); 176 | void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); 177 | void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); 178 | FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); 179 | void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); 180 | ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); 181 | void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); 182 | 183 | #ifdef __cplusplus 184 | } 185 | #endif 186 | 187 | #endif 188 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/inc/ch32v20x_wwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_wwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the WWDG 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V20x_WWDG_H 14 | #define __CH32V20x_WWDG_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v20x.h" 21 | 22 | /* WWDG_Prescaler */ 23 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 24 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 25 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 26 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 27 | 28 | void WWDG_DeInit(void); 29 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 30 | void WWDG_SetWindowValue(uint8_t WindowValue); 31 | void WWDG_EnableIT(void); 32 | void WWDG_SetCounter(uint8_t Counter); 33 | void WWDG_Enable(uint8_t Counter); 34 | FlagStatus WWDG_GetFlagStatus(void); 35 | void WWDG_ClearFlag(void); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_bkp.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_bkp.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the BKP firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_bkp.h" 13 | #include "ch32v20x_rcc.h" 14 | 15 | /* BKP registers bit mask */ 16 | 17 | /* OCTLR register bit mask */ 18 | #define OCTLR_CAL_MASK ((uint16_t)0xFF80) 19 | #define OCTLR_MASK ((uint16_t)0xFC7F) 20 | 21 | /********************************************************************* 22 | * @fn BKP_DeInit 23 | * 24 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 25 | * 26 | * @return none 27 | */ 28 | void BKP_DeInit(void) 29 | { 30 | RCC_BackupResetCmd(ENABLE); 31 | RCC_BackupResetCmd(DISABLE); 32 | } 33 | 34 | /********************************************************************* 35 | * @fn BKP_TamperPinLevelConfig 36 | * 37 | * @brief Configures the Tamper Pin active level. 38 | * 39 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 40 | * BKP_TamperPinLevel_High - Tamper pin active on high level. 41 | * BKP_TamperPinLevel_Low - Tamper pin active on low level. 42 | * 43 | * @return none 44 | */ 45 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 46 | { 47 | if(BKP_TamperPinLevel) 48 | { 49 | BKP->TPCTLR |= (1 << 1); 50 | } 51 | else 52 | { 53 | BKP->TPCTLR &= ~(1 << 1); 54 | } 55 | } 56 | 57 | /********************************************************************* 58 | * @fn BKP_TamperPinCmd 59 | * 60 | * @brief Enables or disables the Tamper Pin activation. 61 | * 62 | * @param NewState - ENABLE or DISABLE. 63 | * 64 | * @return none 65 | */ 66 | void BKP_TamperPinCmd(FunctionalState NewState) 67 | { 68 | if(NewState) 69 | { 70 | BKP->TPCTLR |= (1 << 0); 71 | } 72 | else 73 | { 74 | BKP->TPCTLR &= ~(1 << 0); 75 | } 76 | } 77 | 78 | /********************************************************************* 79 | * @fn BKP_ITConfig 80 | * 81 | * @brief Enables or disables the Tamper Pin Interrupt. 82 | * 83 | * @param NewState - ENABLE or DISABLE. 84 | * 85 | * @return none 86 | */ 87 | void BKP_ITConfig(FunctionalState NewState) 88 | { 89 | if(NewState) 90 | { 91 | BKP->TPCSR |= (1 << 2); 92 | } 93 | else 94 | { 95 | BKP->TPCSR &= ~(1 << 2); 96 | } 97 | } 98 | 99 | /********************************************************************* 100 | * @fn BKP_RTCOutputConfig 101 | * 102 | * @brief Select the RTC output source to output on the Tamper pin. 103 | * 104 | * @param BKP_RTCOutputSource - specifies the RTC output source. 105 | * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. 106 | * BKP_RTCOutputSource_CalibClock - output the RTC clock with 107 | * frequency divided by 64 on the Tamper pin. 108 | * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal 109 | * on the Tamper pin. 110 | * BKP_RTCOutputSource_Second - output the RTC Second pulse 111 | * signal on the Tamper pin. 112 | * 113 | * @return none 114 | */ 115 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 116 | { 117 | uint16_t tmpreg = 0; 118 | 119 | tmpreg = BKP->OCTLR; 120 | tmpreg &= OCTLR_MASK; 121 | tmpreg |= BKP_RTCOutputSource; 122 | BKP->OCTLR = tmpreg; 123 | } 124 | 125 | /********************************************************************* 126 | * @fn BKP_SetRTCCalibrationValue 127 | * 128 | * @brief Sets RTC Clock Calibration value. 129 | * 130 | * @param CalibrationValue - specifies the RTC Clock Calibration value. 131 | * This parameter must be a number between 0 and 0x1F. 132 | * 133 | * @return none 134 | */ 135 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 136 | { 137 | uint16_t tmpreg = 0; 138 | 139 | tmpreg = BKP->OCTLR; 140 | tmpreg &= OCTLR_CAL_MASK; 141 | tmpreg |= CalibrationValue; 142 | BKP->OCTLR = tmpreg; 143 | } 144 | 145 | /********************************************************************* 146 | * @fn BKP_WriteBackupRegister 147 | * 148 | * @brief Writes user data to the specified Data Backup Register. 149 | * 150 | * @param BKP_DR - specifies the Data Backup Register. 151 | * Data - data to write. 152 | * 153 | * @return none 154 | */ 155 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 156 | { 157 | __IO uint32_t tmp = 0; 158 | 159 | tmp = (uint32_t)BKP_BASE; 160 | tmp += BKP_DR; 161 | *(__IO uint32_t *)tmp = Data; 162 | } 163 | 164 | /********************************************************************* 165 | * @fn BKP_ReadBackupRegister 166 | * 167 | * @brief Reads data from the specified Data Backup Register. 168 | * 169 | * @param BKP_DR - specifies the Data Backup Register. 170 | * This parameter can be BKP_DRx where x=[1, 42]. 171 | * 172 | * @return none 173 | */ 174 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 175 | { 176 | __IO uint32_t tmp = 0; 177 | 178 | tmp = (uint32_t)BKP_BASE; 179 | tmp += BKP_DR; 180 | 181 | return (*(__IO uint16_t *)tmp); 182 | } 183 | 184 | /********************************************************************* 185 | * @fn BKP_GetFlagStatus 186 | * 187 | * @brief Checks whether the Tamper Pin Event flag is set or not. 188 | * 189 | * @return FlagStatus - SET or RESET. 190 | */ 191 | FlagStatus BKP_GetFlagStatus(void) 192 | { 193 | if(BKP->TPCSR & (1 << 8)) 194 | { 195 | return SET; 196 | } 197 | else 198 | { 199 | return RESET; 200 | } 201 | } 202 | 203 | /********************************************************************* 204 | * @fn BKP_ClearFlag 205 | * 206 | * @brief Clears Tamper Pin Event pending flag. 207 | * 208 | * @return none 209 | */ 210 | void BKP_ClearFlag(void) 211 | { 212 | BKP->TPCSR |= BKP_CTE; 213 | } 214 | 215 | /********************************************************************* 216 | * @fn BKP_GetITStatus 217 | * 218 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 219 | * 220 | * @return ITStatus - SET or RESET. 221 | */ 222 | ITStatus BKP_GetITStatus(void) 223 | { 224 | if(BKP->TPCSR & (1 << 9)) 225 | { 226 | return SET; 227 | } 228 | else 229 | { 230 | return RESET; 231 | } 232 | } 233 | 234 | /********************************************************************* 235 | * @fn BKP_ClearITPendingBit 236 | * 237 | * @brief Clears Tamper Pin Interrupt pending bit. 238 | * 239 | * @return none 240 | */ 241 | void BKP_ClearITPendingBit(void) 242 | { 243 | BKP->TPCSR |= BKP_CTI; 244 | } 245 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_crc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_crc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the CRC firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_crc.h" 13 | 14 | /********************************************************************* 15 | * @fn CRC_ResetDR 16 | * 17 | * @brief Resets the CRC Data register (DR). 18 | * 19 | * @return none 20 | */ 21 | void CRC_ResetDR(void) 22 | { 23 | CRC->CTLR = CRC_CTLR_RESET; 24 | } 25 | 26 | /********************************************************************* 27 | * @fn CRC_CalcCRC 28 | * 29 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 30 | * 31 | * @param Data - data word(32-bit) to compute its CRC. 32 | * 33 | * @return 32-bit CRC. 34 | */ 35 | uint32_t CRC_CalcCRC(uint32_t Data) 36 | { 37 | CRC->DATAR = Data; 38 | 39 | return (CRC->DATAR); 40 | } 41 | 42 | /********************************************************************* 43 | * @fn CRC_CalcBlockCRC 44 | * 45 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 46 | * 47 | * @param pBuffer - pointer to the buffer containing the data to be computed. 48 | * BufferLength - length of the buffer to be computed. 49 | * 50 | * @return 32-bit CRC. 51 | */ 52 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 53 | { 54 | uint32_t index = 0; 55 | 56 | for(index = 0; index < BufferLength; index++){ 57 | CRC->DATAR = pBuffer[index]; 58 | } 59 | 60 | return (CRC->DATAR); 61 | } 62 | 63 | /********************************************************************* 64 | * @fn CRC_GetCRC 65 | * 66 | * @brief Returns the current CRC value. 67 | * 68 | * @return 32-bit CRC. 69 | */ 70 | uint32_t CRC_GetCRC(void) 71 | { 72 | return (CRC->DATAR); 73 | } 74 | 75 | /********************************************************************* 76 | * @fn CRC_SetIDRegister 77 | * 78 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 79 | * 80 | * @param IDValue - 8-bit value to be stored in the ID register. 81 | * 82 | * @return none 83 | */ 84 | void CRC_SetIDRegister(uint8_t IDValue) 85 | { 86 | CRC->IDATAR = IDValue; 87 | } 88 | 89 | /********************************************************************* 90 | * @fn CRC_GetIDRegister 91 | * 92 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register. 93 | * 94 | * @return 8-bit value of the ID register. 95 | */ 96 | uint8_t CRC_GetIDRegister(void) 97 | { 98 | return (CRC->IDATAR); 99 | } 100 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_dbgmcu.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the DBGMCU firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_dbgmcu.h" 13 | 14 | #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) 15 | 16 | /********************************************************************* 17 | * @fn DBGMCU_GetREVID 18 | * 19 | * @brief Returns the device revision identifier. 20 | * 21 | * @return Revision identifier. 22 | */ 23 | uint32_t DBGMCU_GetREVID(void) 24 | { 25 | return ((*(uint32_t *)0x1FFFF704) >> 16); 26 | } 27 | 28 | /********************************************************************* 29 | * @fn DBGMCU_GetDEVID 30 | * 31 | * @brief Returns the device identifier. 32 | * 33 | * @return Device identifier. 34 | */ 35 | uint32_t DBGMCU_GetDEVID(void) 36 | { 37 | return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); 38 | } 39 | 40 | /********************************************************************* 41 | * @fn __get_DEBUG_CR 42 | * 43 | * @brief Return the DEBUGE Control Register 44 | * 45 | * @return DEBUGE Control value 46 | */ 47 | uint32_t __get_DEBUG_CR(void) 48 | { 49 | uint32_t result; 50 | 51 | __asm volatile("csrr %0,""0x7C0" : "=r"(result)); 52 | return (result); 53 | } 54 | 55 | /********************************************************************* 56 | * @fn __set_DEBUG_CR 57 | * 58 | * @brief Set the DEBUGE Control Register 59 | * 60 | * @param value - set DEBUGE Control value 61 | * 62 | * @return none 63 | */ 64 | void __set_DEBUG_CR(uint32_t value) 65 | { 66 | __asm volatile("csrw 0x7C0, %0" : : "r"(value)); 67 | } 68 | 69 | 70 | /********************************************************************* 71 | * @fn DBGMCU_Config 72 | * 73 | * @brief Configures the specified peripheral and low power mode behavior 74 | * when the MCU under Debug mode. 75 | * 76 | * @param DBGMCU_Periph - specifies the peripheral and low power mode. 77 | * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted 78 | * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted 79 | * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted 80 | * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted 81 | * NewState - ENABLE or DISABLE. 82 | * 83 | * @return none 84 | */ 85 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 86 | { 87 | uint32_t val; 88 | 89 | if(NewState != DISABLE) 90 | { 91 | __set_DEBUG_CR(DBGMCU_Periph); 92 | } 93 | else 94 | { 95 | val = __get_DEBUG_CR(); 96 | val &= ~(uint32_t)DBGMCU_Periph; 97 | __set_DEBUG_CR(val); 98 | } 99 | 100 | } 101 | /********************************************************************* 102 | * @fn DBGMCU_GetCHIPID 103 | * 104 | * @brief Returns the CHIP identifier. 105 | * 106 | * @return Device identifier. 107 | * ChipID List- 108 | * CH32V203C8U6-0x203005x0 109 | * CH32V203C8T6-0x203105x0 110 | * CH32V203K8T6-0x203205x0 111 | * CH32V203C6T6-0x203305x0 112 | * CH32V203K6T6-0x203505x0 113 | * CH32V203G6U6-0x203605x0 114 | * CH32V203G8R6-0x203B05x0 115 | * CH32V203F8U6-0x203E05x0 116 | * CH32V203F6P6-0x203705x0-0x203905x0 117 | * CH32V203F8P6-0x203A05x0 118 | * CH32V203RBT6-0x203405xC 119 | * CH32V208WBU6-0x208005xC 120 | * CH32V208RBT6-0x208105xC 121 | * CH32V208CBU6-0x208205xC 122 | * CH32V208GBU6-0x208305xC 123 | */ 124 | uint32_t DBGMCU_GetCHIPID( void ) 125 | { 126 | return( *( uint32_t * )0x1FFFF704 ); 127 | } 128 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_exti.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_exti.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the EXTI firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_exti.h" 13 | 14 | /* No interrupt selected */ 15 | #define EXTI_LINENONE ((uint32_t)0x00000) 16 | 17 | /********************************************************************* 18 | * @fn EXTI_DeInit 19 | * 20 | * @brief Deinitializes the EXTI peripheral registers to their default 21 | * reset values. 22 | * 23 | * @return none. 24 | */ 25 | void EXTI_DeInit(void) 26 | { 27 | EXTI->INTENR = 0x00000000; 28 | EXTI->EVENR = 0x00000000; 29 | EXTI->RTENR = 0x00000000; 30 | EXTI->FTENR = 0x00000000; 31 | EXTI->INTFR = 0x000FFFFF; 32 | } 33 | 34 | /********************************************************************* 35 | * @fn EXTI_Init 36 | * 37 | * @brief Initializes the EXTI peripheral according to the specified 38 | * parameters in the EXTI_InitStruct. 39 | * 40 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure 41 | * 42 | * @return none. 43 | */ 44 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) 45 | { 46 | uint32_t tmp = 0; 47 | 48 | tmp = (uint32_t)EXTI_BASE; 49 | if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) 50 | { 51 | EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; 52 | EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; 53 | tmp += EXTI_InitStruct->EXTI_Mode; 54 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 55 | EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; 56 | EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; 57 | if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 58 | { 59 | EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; 60 | EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; 61 | } 62 | else 63 | { 64 | tmp = (uint32_t)EXTI_BASE; 65 | tmp += EXTI_InitStruct->EXTI_Trigger; 66 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 67 | } 68 | } 69 | else 70 | { 71 | tmp += EXTI_InitStruct->EXTI_Mode; 72 | *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; 73 | } 74 | } 75 | 76 | /********************************************************************* 77 | * @fn EXTI_StructInit 78 | * 79 | * @brief Fills each EXTI_InitStruct member with its reset value. 80 | * 81 | * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure 82 | * 83 | * @return none. 84 | */ 85 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) 86 | { 87 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 88 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 89 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 90 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 91 | } 92 | 93 | /********************************************************************* 94 | * @fn EXTI_GenerateSWInterrupt 95 | * 96 | * @brief Generates a Software interrupt. 97 | * 98 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 99 | * 100 | * @return none. 101 | */ 102 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 103 | { 104 | EXTI->SWIEVR |= EXTI_Line; 105 | } 106 | 107 | /********************************************************************* 108 | * @fn EXTI_GetFlagStatus 109 | * 110 | * @brief Checks whether the specified EXTI line flag is set or not. 111 | * 112 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 113 | * 114 | * @return The new state of EXTI_Line (SET or RESET). 115 | */ 116 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 117 | { 118 | FlagStatus bitstatus = RESET; 119 | if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) 120 | { 121 | bitstatus = SET; 122 | } 123 | else 124 | { 125 | bitstatus = RESET; 126 | } 127 | return bitstatus; 128 | } 129 | 130 | /********************************************************************* 131 | * @fn EXTI_ClearFlag 132 | * 133 | * @brief Clears the EXTI's line pending flags. 134 | * 135 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 136 | * 137 | * @return None 138 | */ 139 | void EXTI_ClearFlag(uint32_t EXTI_Line) 140 | { 141 | EXTI->INTFR = EXTI_Line; 142 | } 143 | 144 | /********************************************************************* 145 | * @fn EXTI_GetITStatus 146 | * 147 | * @brief Checks whether the specified EXTI line is asserted or not. 148 | * 149 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 150 | * 151 | * @return The new state of EXTI_Line (SET or RESET). 152 | */ 153 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 154 | { 155 | ITStatus bitstatus = RESET; 156 | uint32_t enablestatus = 0; 157 | 158 | enablestatus = EXTI->INTENR & EXTI_Line; 159 | if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 160 | { 161 | bitstatus = SET; 162 | } 163 | else 164 | { 165 | bitstatus = RESET; 166 | } 167 | return bitstatus; 168 | } 169 | 170 | /********************************************************************* 171 | * @fn EXTI_ClearITPendingBit 172 | * 173 | * @brief Clears the EXTI's line pending bits. 174 | * 175 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 176 | * 177 | * @return none 178 | */ 179 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 180 | { 181 | EXTI->INTFR = EXTI_Line; 182 | } 183 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_iwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_iwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the IWDG firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_iwdg.h" 13 | 14 | /* CTLR register bit mask */ 15 | #define CTLR_KEY_Reload ((uint16_t)0xAAAA) 16 | #define CTLR_KEY_Enable ((uint16_t)0xCCCC) 17 | 18 | /********************************************************************* 19 | * @fn IWDG_WriteAccessCmd 20 | * 21 | * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. 22 | * 23 | * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and 24 | * IWDG_RLDR registers. 25 | * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and 26 | * IWDG_RLDR registers. 27 | * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR 28 | * and IWDG_RLDR registers. 29 | * 30 | * @return none 31 | */ 32 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 33 | { 34 | IWDG->CTLR = IWDG_WriteAccess; 35 | } 36 | 37 | /********************************************************************* 38 | * @fn IWDG_SetPrescaler 39 | * 40 | * @brief Sets IWDG Prescaler value. 41 | * 42 | * @param IWDG_Prescaler - specifies the IWDG Prescaler value. 43 | * IWDG_Prescaler_4 - IWDG prescaler set to 4. 44 | * IWDG_Prescaler_8 - IWDG prescaler set to 8. 45 | * IWDG_Prescaler_16 - IWDG prescaler set to 16. 46 | * IWDG_Prescaler_32 - IWDG prescaler set to 32. 47 | * IWDG_Prescaler_64 - IWDG prescaler set to 64. 48 | * IWDG_Prescaler_128 - IWDG prescaler set to 128. 49 | * IWDG_Prescaler_256 - IWDG prescaler set to 256. 50 | * 51 | * @return none 52 | */ 53 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 54 | { 55 | IWDG->PSCR = IWDG_Prescaler; 56 | } 57 | 58 | /********************************************************************* 59 | * @fn IWDG_SetReload 60 | * 61 | * @brief Sets IWDG Reload value. 62 | * 63 | * @param Reload - specifies the IWDG Reload value. 64 | * This parameter must be a number between 0 and 0x0FFF. 65 | * 66 | * @return none 67 | */ 68 | void IWDG_SetReload(uint16_t Reload) 69 | { 70 | IWDG->RLDR = Reload; 71 | } 72 | 73 | /********************************************************************* 74 | * @fn IWDG_ReloadCounter 75 | * 76 | * @brief Reloads IWDG counter with value defined in the reload register. 77 | * 78 | * @return none 79 | */ 80 | void IWDG_ReloadCounter(void) 81 | { 82 | IWDG->CTLR = CTLR_KEY_Reload; 83 | } 84 | 85 | /********************************************************************* 86 | * @fn IWDG_Enable 87 | * 88 | * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). 89 | * 90 | * @return none 91 | */ 92 | void IWDG_Enable(void) 93 | { 94 | IWDG->CTLR = CTLR_KEY_Enable; 95 | } 96 | 97 | /********************************************************************* 98 | * @fn IWDG_GetFlagStatus 99 | * 100 | * @brief Checks whether the specified IWDG flag is set or not. 101 | * 102 | * @param IWDG_FLAG - specifies the flag to check. 103 | * IWDG_FLAG_PVU - Prescaler Value Update on going. 104 | * IWDG_FLAG_RVU - Reload Value Update on going. 105 | * 106 | * @return none 107 | */ 108 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 109 | { 110 | FlagStatus bitstatus = RESET; 111 | 112 | if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) 113 | { 114 | bitstatus = SET; 115 | } 116 | else 117 | { 118 | bitstatus = RESET; 119 | } 120 | 121 | return bitstatus; 122 | } 123 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_misc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_misc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the miscellaneous firmware functions . 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_misc.h" 13 | 14 | __IO uint32_t NVIC_Priority_Group = 0; 15 | 16 | /********************************************************************* 17 | * @fn NVIC_PriorityGroupConfig 18 | * 19 | * @brief Configures the priority grouping - pre-emption priority and subpriority. 20 | * 21 | * @param NVIC_PriorityGroup - specifies the priority grouping bits length. 22 | * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority 23 | * 4 bits for subpriority 24 | * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority 25 | * 3 bits for subpriority 26 | * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority 27 | * 2 bits for subpriority 28 | * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority 29 | * 1 bits for subpriority 30 | * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority 31 | * 0 bits for subpriority 32 | * 33 | * @return none 34 | */ 35 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 36 | { 37 | NVIC_Priority_Group = NVIC_PriorityGroup; 38 | } 39 | 40 | /********************************************************************* 41 | * @fn NVIC_Init 42 | * 43 | * @brief Initializes the NVIC peripheral according to the specified parameters in 44 | * the NVIC_InitStruct. 45 | * 46 | * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the 47 | * configuration information for the specified NVIC peripheral. 48 | * 49 | * @return none 50 | */ 51 | void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) 52 | { 53 | uint8_t tmppre = 0; 54 | 55 | if(NVIC_Priority_Group == NVIC_PriorityGroup_0) 56 | { 57 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); 58 | } 59 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) 60 | { 61 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) 62 | { 63 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 64 | } 65 | else 66 | { 67 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 68 | } 69 | } 70 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) 71 | { 72 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) 73 | { 74 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 75 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 76 | } 77 | else 78 | { 79 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); 80 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 81 | } 82 | } 83 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) 84 | { 85 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) 86 | { 87 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 88 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 89 | } 90 | else 91 | { 92 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); 93 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 94 | } 95 | } 96 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) 97 | { 98 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); 99 | } 100 | 101 | if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 102 | { 103 | NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 104 | } 105 | else 106 | { 107 | NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 108 | } 109 | } 110 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_opa.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_opa.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the OPA firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_opa.h" 13 | 14 | #define OPA_MASK ((uint32_t)0x000F) 15 | #define OPA_Total_NUM 4 16 | 17 | /********************************************************************* 18 | * @fn OPA_DeInit 19 | * 20 | * @brief Deinitializes the OPA peripheral registers to their default 21 | * reset values. 22 | * 23 | * @return none 24 | */ 25 | void OPA_DeInit(void) 26 | { 27 | OPA->CR = 0; 28 | } 29 | 30 | /********************************************************************* 31 | * @fn OPA_Init 32 | * 33 | * @brief Initializes the OPA peripheral according to the specified 34 | * parameters in the OPA_InitStruct. 35 | * 36 | * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure 37 | * 38 | * @return none 39 | */ 40 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) 41 | { 42 | uint32_t tmp = 0; 43 | tmp = OPA->CR; 44 | tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); 45 | tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); 46 | OPA->CR = tmp; 47 | } 48 | 49 | /********************************************************************* 50 | * @fn OPA_StructInit 51 | * 52 | * @brief Fills each OPA_StructInit member with its reset value. 53 | * 54 | * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure 55 | * 56 | * @return none 57 | */ 58 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) 59 | { 60 | OPA_InitStruct->Mode = OUT_IO_OUT1; 61 | OPA_InitStruct->PSEL = CHP0; 62 | OPA_InitStruct->NSEL = CHN0; 63 | OPA_InitStruct->OPA_NUM = OPA1; 64 | } 65 | 66 | /********************************************************************* 67 | * @fn OPA_Cmd 68 | * 69 | * @brief Enables or disables the specified OPA peripheral. 70 | * 71 | * @param OPA_NUM - Select OPA 72 | * NewState - ENABLE or DISABLE. 73 | * 74 | * @return none 75 | */ 76 | void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) 77 | { 78 | if(NewState == ENABLE) 79 | { 80 | OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); 81 | } 82 | else 83 | { 84 | OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); 85 | } 86 | } 87 | -------------------------------------------------------------------------------- /adv2eth/SRC/Peripheral/src/ch32v20x_wwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v20x_wwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the WWDG firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include "ch32v20x_wwdg.h" 13 | #include "ch32v20x_rcc.h" 14 | 15 | /* CTLR register bit mask */ 16 | #define CTLR_WDGA_Set ((uint32_t)0x00000080) 17 | 18 | /* CFGR register bit mask */ 19 | #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 20 | #define CFGR_W_Mask ((uint32_t)0xFFFFFF80) 21 | #define BIT_Mask ((uint8_t)0x7F) 22 | 23 | /********************************************************************* 24 | * @fn WWDG_DeInit 25 | * 26 | * @brief Deinitializes the WWDG peripheral registers to their default reset values 27 | * 28 | * @return none 29 | */ 30 | void WWDG_DeInit(void) 31 | { 32 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 33 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 34 | } 35 | 36 | /********************************************************************* 37 | * @fn WWDG_SetPrescaler 38 | * 39 | * @brief Sets the WWDG Prescaler 40 | * 41 | * @param WWDG_Prescaler - specifies the WWDG Prescaler 42 | * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 43 | * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 44 | * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 45 | * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 46 | * 47 | * @return none 48 | */ 49 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 50 | { 51 | uint32_t tmpreg = 0; 52 | tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; 53 | tmpreg |= WWDG_Prescaler; 54 | WWDG->CFGR = tmpreg; 55 | } 56 | 57 | /********************************************************************* 58 | * @fn WWDG_SetWindowValue 59 | * 60 | * @brief Sets the WWDG window value 61 | * 62 | * @param WindowValue - specifies the window value to be compared to the 63 | * downcounter,which must be lower than 0x80 64 | * 65 | * @return none 66 | */ 67 | void WWDG_SetWindowValue(uint8_t WindowValue) 68 | { 69 | __IO uint32_t tmpreg = 0; 70 | 71 | tmpreg = WWDG->CFGR & CFGR_W_Mask; 72 | 73 | tmpreg |= WindowValue & (uint32_t)BIT_Mask; 74 | 75 | WWDG->CFGR = tmpreg; 76 | } 77 | 78 | /********************************************************************* 79 | * @fn WWDG_EnableIT 80 | * 81 | * @brief Enables the WWDG Early Wakeup interrupt(EWI) 82 | * 83 | * @return none 84 | */ 85 | void WWDG_EnableIT(void) 86 | { 87 | WWDG->CFGR |= (1 << 9); 88 | } 89 | 90 | /********************************************************************* 91 | * @fn WWDG_SetCounter 92 | * 93 | * @brief Sets the WWDG counter value 94 | * 95 | * @param Counter - specifies the watchdog counter value,which must be a 96 | * number between 0x40 and 0x7F 97 | * 98 | * @return none 99 | */ 100 | void WWDG_SetCounter(uint8_t Counter) 101 | { 102 | WWDG->CTLR = Counter & BIT_Mask; 103 | } 104 | 105 | /********************************************************************* 106 | * @fn WWDG_Enable 107 | * 108 | * @brief Enables WWDG and load the counter value 109 | * 110 | * @param Counter - specifies the watchdog counter value,which must be a 111 | * number between 0x40 and 0x7F 112 | * @return none 113 | */ 114 | void WWDG_Enable(uint8_t Counter) 115 | { 116 | WWDG->CTLR = CTLR_WDGA_Set | Counter; 117 | } 118 | 119 | /********************************************************************* 120 | * @fn WWDG_GetFlagStatus 121 | * 122 | * @brief Checks whether the Early Wakeup interrupt flag is set or not 123 | * 124 | * @return The new state of the Early Wakeup interrupt flag (SET or RESET) 125 | */ 126 | FlagStatus WWDG_GetFlagStatus(void) 127 | { 128 | return (FlagStatus)(WWDG->STATR); 129 | } 130 | 131 | /********************************************************************* 132 | * @fn WWDG_ClearFlag 133 | * 134 | * @brief Clears Early Wakeup interrupt flag 135 | * 136 | * @return none 137 | */ 138 | void WWDG_ClearFlag(void) 139 | { 140 | WWDG->STATR = (uint32_t)RESET; 141 | } 142 | -------------------------------------------------------------------------------- /adv2eth/SRC/Startup/startup_ch32v20x_D8W.S: -------------------------------------------------------------------------------- 1 | ;/********************************** (C) COPYRIGHT ******************************* 2 | ;* File Name : startup_ch32v20x_D8W.s 3 | ;* Author : WCH 4 | ;* Version : V1.0.1 5 | ;* Date : 2023/11/11 6 | ;* Description : CH32V208x 7 | ;* vector table for eclipse toolchain. 8 | ;********************************************************************************* 9 | ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | ;* Attention: This software (modified or not) and binary are used for 11 | ;* microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | 14 | .section .init,"ax",@progbits 15 | .global _start 16 | .align 1 17 | _start: 18 | j handle_reset 19 | 20 | .section .vector,"ax",@progbits 21 | .align 1 22 | _vector_base: 23 | .option norvc; 24 | .word _start 25 | .word 0 26 | .word NMI_Handler /* NMI */ 27 | .word HardFault_Handler /* Hard Fault */ 28 | .word 0 29 | .word Ecall_M_Mode_Handler /* Ecall M Mode */ 30 | .word 0 31 | .word 0 32 | .word Ecall_U_Mode_Handler /* Ecall U Mode */ 33 | .word Break_Point_Handler /* Break Point */ 34 | .word 0 35 | .word 0 36 | .word SysTick_Handler /* SysTick */ 37 | .word 0 38 | .word SW_Handler /* SW */ 39 | .word 0 40 | /* External Interrupts */ 41 | .word WWDG_IRQHandler /* Window Watchdog */ 42 | .word PVD_IRQHandler /* PVD through EXTI Line detect */ 43 | .word TAMPER_IRQHandler /* TAMPER */ 44 | .word RTC_IRQHandler /* RTC */ 45 | .word FLASH_IRQHandler /* Flash */ 46 | .word RCC_IRQHandler /* RCC */ 47 | .word EXTI0_IRQHandler /* EXTI Line 0 */ 48 | .word EXTI1_IRQHandler /* EXTI Line 1 */ 49 | .word EXTI2_IRQHandler /* EXTI Line 2 */ 50 | .word EXTI3_IRQHandler /* EXTI Line 3 */ 51 | .word EXTI4_IRQHandler /* EXTI Line 4 */ 52 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 53 | .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 54 | .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 55 | .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 56 | .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 57 | .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 58 | .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 59 | .word ADC1_2_IRQHandler /* ADC1_2 */ 60 | .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 61 | .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 62 | .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 63 | .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 64 | .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 65 | .word TIM1_BRK_IRQHandler /* TIM1 Break */ 66 | .word TIM1_UP_IRQHandler /* TIM1 Update */ 67 | .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 68 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 69 | .word TIM2_IRQHandler /* TIM2 */ 70 | .word TIM3_IRQHandler /* TIM3 */ 71 | .word TIM4_IRQHandler /* TIM4 */ 72 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 73 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 74 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 75 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 76 | .word SPI1_IRQHandler /* SPI1 */ 77 | .word SPI2_IRQHandler /* SPI2 */ 78 | .word USART1_IRQHandler /* USART1 */ 79 | .word USART2_IRQHandler /* USART2 */ 80 | .word USART3_IRQHandler /* USART3 */ 81 | .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 82 | .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 83 | .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ 84 | .word USBHD_IRQHandler /* USBHD Break */ 85 | .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ 86 | .word ETH_IRQHandler /* ETH global */ 87 | .word ETHWakeUp_IRQHandler /* ETH Wake up */ 88 | .word BB_IRQHandler /* BLE BB */ 89 | .word LLE_IRQHandler /* BLE LLE */ 90 | .word TIM5_IRQHandler /* TIM5 */ 91 | .word UART4_IRQHandler /* UART4 */ 92 | .word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 93 | .word OSC32KCal_IRQHandler /* OSC32KCal */ 94 | .word OSCWakeUp_IRQHandler /* OSC Wake Up */ 95 | 96 | .option rvc; 97 | .section .text.vector_handler, "ax", @progbits 98 | .weak NMI_Handler /* NMI */ 99 | .weak HardFault_Handler /* Hard Fault */ 100 | .weak Ecall_M_Mode_Handler /* Ecall M Mode */ 101 | .weak Ecall_U_Mode_Handler /* Ecall U Mode */ 102 | .weak Break_Point_Handler /* Break Point */ 103 | .weak SysTick_Handler /* SysTick */ 104 | .weak SW_Handler /* SW */ 105 | .weak WWDG_IRQHandler /* Window Watchdog */ 106 | .weak PVD_IRQHandler /* PVD through EXTI Line detect */ 107 | .weak TAMPER_IRQHandler /* TAMPER */ 108 | .weak RTC_IRQHandler /* RTC */ 109 | .weak FLASH_IRQHandler /* Flash */ 110 | .weak RCC_IRQHandler /* RCC */ 111 | .weak EXTI0_IRQHandler /* EXTI Line 0 */ 112 | .weak EXTI1_IRQHandler /* EXTI Line 1 */ 113 | .weak EXTI2_IRQHandler /* EXTI Line 2 */ 114 | .weak EXTI3_IRQHandler /* EXTI Line 3 */ 115 | .weak EXTI4_IRQHandler /* EXTI Line 4 */ 116 | .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 117 | .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 118 | .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 119 | .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 120 | .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 121 | .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 122 | .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 123 | .weak ADC1_2_IRQHandler /* ADC1_2 */ 124 | .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ 125 | .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ 126 | .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ 127 | .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ 128 | .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ 129 | .weak TIM1_BRK_IRQHandler /* TIM1 Break */ 130 | .weak TIM1_UP_IRQHandler /* TIM1 Update */ 131 | .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 132 | .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 133 | .weak TIM2_IRQHandler /* TIM2 */ 134 | .weak TIM3_IRQHandler /* TIM3 */ 135 | .weak TIM4_IRQHandler /* TIM4 */ 136 | .weak I2C1_EV_IRQHandler /* I2C1 Event */ 137 | .weak I2C1_ER_IRQHandler /* I2C1 Error */ 138 | .weak I2C2_EV_IRQHandler /* I2C2 Event */ 139 | .weak I2C2_ER_IRQHandler /* I2C2 Error */ 140 | .weak SPI1_IRQHandler /* SPI1 */ 141 | .weak SPI2_IRQHandler /* SPI2 */ 142 | .weak USART1_IRQHandler /* USART1 */ 143 | .weak USART2_IRQHandler /* USART2 */ 144 | .weak USART3_IRQHandler /* USART3 */ 145 | .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ 146 | .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ 147 | .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ 148 | .weak USBHD_IRQHandler /* USBHD */ 149 | .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ 150 | .weak ETH_IRQHandler /* ETH global */ 151 | .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ 152 | .weak BB_IRQHandler /* BLE BB */ 153 | .weak LLE_IRQHandler /* BLE LLE */ 154 | .weak TIM5_IRQHandler /* TIM5 */ 155 | .weak UART4_IRQHandler /* UART4 */ 156 | .weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */ 157 | .weak OSC32KCal_IRQHandler /* OSC32 KCal */ 158 | .weak OSCWakeUp_IRQHandler /* OSC Wake Up */ 159 | 160 | NMI_Handler: 161 | HardFault_Handler: 162 | Ecall_M_Mode_Handler: 163 | Ecall_U_Mode_Handler: 164 | Break_Point_Handler: 165 | SysTick_Handler: 166 | SW_Handler: 167 | WWDG_IRQHandler: 168 | PVD_IRQHandler: 169 | TAMPER_IRQHandler: 170 | RTC_IRQHandler: 171 | FLASH_IRQHandler: 172 | RCC_IRQHandler: 173 | EXTI0_IRQHandler: 174 | EXTI1_IRQHandler: 175 | EXTI2_IRQHandler: 176 | EXTI3_IRQHandler: 177 | EXTI4_IRQHandler: 178 | DMA1_Channel1_IRQHandler: 179 | DMA1_Channel2_IRQHandler: 180 | DMA1_Channel3_IRQHandler: 181 | DMA1_Channel4_IRQHandler: 182 | DMA1_Channel5_IRQHandler: 183 | DMA1_Channel6_IRQHandler: 184 | DMA1_Channel7_IRQHandler: 185 | ADC1_2_IRQHandler: 186 | USB_HP_CAN1_TX_IRQHandler: 187 | USB_LP_CAN1_RX0_IRQHandler: 188 | CAN1_RX1_IRQHandler: 189 | CAN1_SCE_IRQHandler: 190 | EXTI9_5_IRQHandler: 191 | TIM1_BRK_IRQHandler: 192 | TIM1_UP_IRQHandler: 193 | TIM1_TRG_COM_IRQHandler: 194 | TIM1_CC_IRQHandler: 195 | TIM2_IRQHandler: 196 | TIM3_IRQHandler: 197 | TIM4_IRQHandler: 198 | I2C1_EV_IRQHandler: 199 | I2C1_ER_IRQHandler: 200 | I2C2_EV_IRQHandler: 201 | I2C2_ER_IRQHandler: 202 | SPI1_IRQHandler: 203 | SPI2_IRQHandler: 204 | USART1_IRQHandler: 205 | USART2_IRQHandler: 206 | USART3_IRQHandler: 207 | EXTI15_10_IRQHandler: 208 | RTCAlarm_IRQHandler: 209 | USBWakeUp_IRQHandler: 210 | USBHD_IRQHandler: 211 | USBHDWakeUp_IRQHandler: 212 | ETH_IRQHandler: 213 | ETHWakeUp_IRQHandler: 214 | BB_IRQHandler: 215 | LLE_IRQHandler: 216 | TIM5_IRQHandler: 217 | UART4_IRQHandler: 218 | DMA1_Channel8_IRQHandler: 219 | OSC32KCal_IRQHandler: 220 | OSCWakeUp_IRQHandler: 221 | 1: 222 | j 1b 223 | 224 | .section .text.handle_reset,"ax",@progbits 225 | .weak handle_reset 226 | .align 1 227 | handle_reset: 228 | .option push 229 | .option norelax 230 | la gp, __global_pointer$ 231 | .option pop 232 | 1: 233 | la sp, _eusrstack 234 | 2: 235 | /* Load data section from flash to RAM */ 236 | la a0, _data_lma 237 | la a1, _data_vma 238 | la a2, _edata 239 | bgeu a1, a2, 2f 240 | 1: 241 | lw t0, (a0) 242 | sw t0, (a1) 243 | addi a0, a0, 4 244 | addi a1, a1, 4 245 | bltu a1, a2, 1b 246 | 2: 247 | /* Clear bss section */ 248 | la a0, _sbss 249 | la a1, _ebss 250 | bgeu a0, a1, 2f 251 | 1: 252 | sw zero, (a0) 253 | addi a0, a0, 4 254 | bltu a0, a1, 1b 255 | 2: 256 | /* Configure pipelining and instruction prediction */ 257 | li t0, 0x1f 258 | csrw 0xbc0, t0 259 | /* Enable interrupt nesting and hardware stack */ 260 | li t0, 0x3 261 | csrw 0x804, t0 262 | /* Enable global interrupt and configure privileged mode */ 263 | li t0, 0x88 264 | csrw mstatus, t0 265 | /* Configure the interrupt vector table recognition mode and entry address mode */ 266 | la t0, _vector_base 267 | ori t0, t0, 3 268 | csrw mtvec, t0 269 | 270 | jal SystemInit 271 | la t0, main 272 | csrw mepc, t0 273 | mret 274 | 275 | 276 | -------------------------------------------------------------------------------- /adv2eth/adv2eth.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /img/CH32V208WBU6-EVT-R0.jpg: -------------------------------------------------------------------------------- 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