├── cortex_m ├── .gitignore ├── peripherals │ ├── bak │ │ ├── syst.yaml │ │ ├── tpiu.yaml │ │ ├── dcb.yaml │ │ ├── fpu.yaml │ │ ├── nvic_v6.yaml │ │ ├── cpuid_v6.yaml │ │ ├── scb.yaml │ │ ├── mpu.yaml │ │ ├── cpb.yaml │ │ ├── fpb.yaml │ │ └── cpuid_v7.yaml │ ├── syst.yaml │ ├── dcb.yaml │ ├── scb_v7.yaml │ ├── fpu.yaml │ ├── nvic_v6.yaml │ ├── tpiu.yaml │ ├── cpuid_v6.yaml │ ├── scb.yaml │ ├── mpu.yaml │ ├── cpb.yaml │ ├── fpb.yaml │ └── cpuid_v7.yaml ├── armv8m.yaml ├── Makefile ├── armv6m.yaml ├── README.md ├── armv7m.yaml ├── armv7em.yaml ├── armv6m.svd ├── armv7em.svd ├── armv7m.svd └── armv8m.svd ├── devices ├── common_patches │ ├── timer_ccr_reg_array.yaml │ ├── adc_rw.yaml │ ├── flash_f040_rename.yaml │ ├── f002b_dbg.yaml │ ├── spi_f002b.yaml │ ├── usart_f040_rename.yaml │ ├── syscfg_f002b.yaml │ ├── dma_cluster.yaml │ ├── usart_dr8.yaml │ ├── spi_dr8.yaml │ ├── rtc_040_renames.yaml │ ├── syscfg_f002a.yaml │ ├── isr_array.yaml │ └── pwr_f002a.yaml ├── py32f002a.yaml ├── py32f002b.yaml ├── py32f003.yaml ├── py32f030.yaml └── py32f040.yaml ├── peripherals ├── crc │ └── crc_f0.yaml ├── dbg │ ├── dbg_f002b.yaml │ ├── dbg_f002a.yaml │ └── dbg_f0.yaml ├── iwdg │ ├── iwdg_f002b.yaml │ └── iwdg_f0.yaml ├── wwdg │ └── wwdg_f0.yaml ├── syscfg │ ├── syscfg_f002a.yaml │ ├── syscfg_f002b.yaml │ ├── syscfg_f0.yaml │ └── syscfg_f040.yaml ├── pwr │ ├── pwr_f002b.yaml │ ├── pwr_f002a.yaml │ ├── pwr_f040.yaml │ └── pwr_f0.yaml ├── lptim │ └── lptim_f0.yaml ├── exti │ └── exti_f0.yaml ├── comp │ ├── comp_f002b.yaml │ ├── comp_f040.yaml │ └── comp_f0.yaml ├── led │ └── led_f0.yaml ├── gpio │ └── gpio_f0.yaml ├── rtc │ └── rtc_f0.yaml ├── dma │ └── dma_f0.yaml ├── lcd │ └── lcd_f0.yaml ├── flash │ ├── flash_f040.yaml │ ├── flash_f002a.yaml │ ├── flash_f002b.yaml │ └── flash_f0.yaml ├── spi │ ├── spi_f002b.yaml │ ├── spi_f002a.yaml │ ├── spi_f040.yaml │ └── spi_f0.yaml ├── i2c │ ├── i2c_f002a.yaml │ ├── i2c_f002b.yaml │ └── i2c_f0.yaml ├── usart │ ├── usart_f002b.yaml │ ├── usart_f002a.yaml │ └── usart_f0.yaml └── rcc │ ├── rcc_f002a.yaml │ └── rcc_f002b.yaml ├── .gitignore ├── svd └── extract.sh ├── Makefile.toml ├── .github └── workflows │ ├── changelog.yaml │ ├── gh-pages.yaml │ ├── ci.yaml │ └── cargo-make.yaml ├── scripts ├── comparesvd.py ├── htmlcomparesvdall.sh ├── interrupts.py ├── tool_install.sh ├── makehtml.index.template.html ├── timer_hierarchy.py ├── viewgroups.html ├── README.md ├── periphtemplate.py ├── matchperipherals.py └── makejson.py ├── LICENSE-MIT ├── CHANGELOG.md ├── py32_part_table.yaml └── Makefile /cortex_m/.gitignore: -------------------------------------------------------------------------------- 1 | *.patched 2 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/syst.yaml: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/tpiu.yaml: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /cortex_m/armv8m.yaml: -------------------------------------------------------------------------------- 1 | _svd: armv8m.svd 2 | 3 | # No files included yet. 4 | -------------------------------------------------------------------------------- /devices/common_patches/timer_ccr_reg_array.yaml: -------------------------------------------------------------------------------- 1 | _array: 2 | CCR*: {} 3 | -------------------------------------------------------------------------------- /devices/common_patches/adc_rw.yaml: -------------------------------------------------------------------------------- 1 | SR: 2 | _modify: 3 | OVER: 4 | access: read-write 5 | -------------------------------------------------------------------------------- /devices/common_patches/flash_f040_rename.yaml: -------------------------------------------------------------------------------- 1 | OPTR: 2 | _modify: 3 | NBOOT1: 4 | name: nBOOT1 5 | -------------------------------------------------------------------------------- /devices/common_patches/f002b_dbg.yaml: -------------------------------------------------------------------------------- 1 | APB_FZ2: 2 | _modify: 3 | DBG_TIM14_STOP: 4 | name: DBG_TIMER14_STOP 5 | -------------------------------------------------------------------------------- /devices/common_patches/spi_f002b.yaml: -------------------------------------------------------------------------------- 1 | # Rename DDF field in CR1 to DFF to match datasheet 2 | CR1: 3 | _modify: 4 | DDF: 5 | name: DFF 6 | description: desc DFF 7 | -------------------------------------------------------------------------------- /devices/common_patches/usart_f040_rename.yaml: -------------------------------------------------------------------------------- 1 | BRR: 2 | _modify: 3 | DIV_FRACTION: 4 | name: DIV_Fraction 5 | DIV_MANTISSA: 6 | name: DIV_Mantissa 7 | CR3: 8 | _modify: 9 | ABRMODE: 10 | name: ABRMOD 11 | -------------------------------------------------------------------------------- /peripherals/crc/crc_f0.yaml: -------------------------------------------------------------------------------- 1 | CRC: 2 | DR: 3 | DR: [0, 4294967295] 4 | IDR: 5 | IDR: [0, 255] 6 | CR: 7 | RESET: 8 | _write: 9 | Reset: [1, "Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF"] 10 | -------------------------------------------------------------------------------- /cortex_m/Makefile: -------------------------------------------------------------------------------- 1 | all: patch 2 | 3 | YAMLS := $(wildcard *.yaml) 4 | PATCHED_SVDS := $(patsubst %.yaml, %.svd.patched, $(YAMLS)) 5 | 6 | %.svd.patched: %.yaml %.svd 7 | svd patch $< 8 | 9 | patch: $(PATCHED_SVDS) 10 | 11 | clean: 12 | rm -f $(PATCHED_SVDS) 13 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | **/__pycache__/ 2 | **/target/ 3 | **/*.rs.bk 4 | **/Cargo.lock 5 | .deps/ 6 | */src/py32*/ 7 | */src/generic.rs 8 | html/ 9 | mmaps/ 10 | /venv 11 | .devcontainer 12 | svd/*.svd* 13 | svd/.extracted 14 | 15 | # automatically generated crates 16 | /py32*/ 17 | -------------------------------------------------------------------------------- /svd/extract.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | # Copy svd files and rename to remove trailing 'x' 4 | cp vendor/PY32F002Axx.svd py32f002a.svd 5 | cp vendor/PY32F002Bxx.svd py32f002b.svd 6 | cp vendor/PY32F003xx.svd py32f003.svd 7 | cp vendor/PY32F030xx.svd py32f030.svd 8 | cp vendor/py32f040xx.svd py32f040.svd 9 | -------------------------------------------------------------------------------- /devices/common_patches/syscfg_f002b.yaml: -------------------------------------------------------------------------------- 1 | SYSCFG: 2 | CFGR2: 3 | _add: 4 | COMP1_BRK_TIM1: 5 | description: "COMP1 output connect to TIM1 Break input" 6 | bitOffset: 3 7 | bitWidth: 1 8 | COMP2_BRK_TIM1: 9 | description: "COMP2 output connect to TIM1 Break input" 10 | bitOffset: 4 11 | bitWidth: 1 -------------------------------------------------------------------------------- /devices/common_patches/dma_cluster.yaml: -------------------------------------------------------------------------------- 1 | _cluster: 2 | "CH%s": 3 | description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" 4 | "CCR?": 5 | name: CR 6 | "CNDTR?": 7 | name: NDTR 8 | "CPAR?": 9 | name: PAR 10 | "CMAR?": 11 | name: MAR 12 | 13 | _include: 14 | - isr_array.yaml 15 | -------------------------------------------------------------------------------- /devices/common_patches/usart_dr8.yaml: -------------------------------------------------------------------------------- 1 | _add: 2 | DR8: 3 | description: Direct 8-bit access to data register 4 | access: read-write 5 | addressOffset: 0x4 6 | alternateRegister: DR 7 | size: 0x8 8 | fields: 9 | DR: 10 | bitOffset: 0 11 | bitWidth: 8 12 | description: Data register 13 | 14 | DR8: 15 | DR: [0, 0xFF] 16 | -------------------------------------------------------------------------------- /devices/common_patches/spi_dr8.yaml: -------------------------------------------------------------------------------- 1 | _add: 2 | DR8: 3 | description: Direct 8-bit access to data register 4 | access: read-write 5 | addressOffset: 0xC 6 | alternateRegister: DR 7 | size: 0x8 8 | fields: 9 | DR: 10 | bitOffset: 0 11 | bitWidth: 8 12 | description: Data register 13 | 14 | DR8: 15 | DR: [0, 0xFF] 16 | 17 | -------------------------------------------------------------------------------- /Makefile.toml: -------------------------------------------------------------------------------- 1 | [tasks.crates] 2 | command = "make" 3 | args = ["crates"] 4 | 5 | [tasks.install] 6 | command = "make" 7 | args = ["install"] 8 | 9 | [tasks.patch] 10 | command = "make" 11 | args = ["patch"] 12 | 13 | [tasks.svd2rust] 14 | command = "make" 15 | args = ["svd2rust"] 16 | 17 | [tasks.form] 18 | command = "make" 19 | args = ["form"] 20 | 21 | [tasks.check] 22 | command = "make" 23 | args = ["check"] 24 | 25 | [tasks.clean] 26 | command = "make" 27 | args = ["clean"] 28 | -------------------------------------------------------------------------------- /cortex_m/armv6m.yaml: -------------------------------------------------------------------------------- 1 | _svd: armv6m.svd 2 | 3 | _include: 4 | - peripherals/cpuid_v6.yaml 5 | - peripherals/dcb.yaml 6 | - peripherals/dwt.yaml 7 | # These three peripherals are included in the ST SVD files, so don't 8 | # include them in the generic ARMv6-M SVD as well. 9 | # Uncomment them here if you want to include them for some other reason. 10 | #- peripherals/mpu.yaml 11 | #- peripherals/nvic.yaml 12 | #- peripherals/nvic_v6.yaml 13 | #- peripherals/scb.yaml 14 | - peripherals/syst.yaml 15 | -------------------------------------------------------------------------------- /cortex_m/README.md: -------------------------------------------------------------------------------- 1 | # Cortex-M SVD files 2 | 3 | We can use the existing SVD patching framework to build SVD files which define 4 | the peripherals common to all Cortex-M devices. 5 | 6 | The base SVD files are `armv6m.svd`, `armv7m.svd`, and `armv7em.svd`, which do 7 | not contain any peripherals. They are patched to create `armv6m.svd.patched` 8 | and `armv7m.patched` using `svd patch` and the `armv6m.yaml` and 9 | `armv7m.yaml` device files. The peripheral definitions all come from 10 | the `peripherals/` directory. 11 | -------------------------------------------------------------------------------- /devices/common_patches/rtc_040_renames.yaml: -------------------------------------------------------------------------------- 1 | PRLH: 2 | _modify: 3 | PRL: 4 | name: PRLH 5 | PRLL: 6 | _modify: 7 | PRL: 8 | name: PRLL 9 | DIVH: 10 | _modify: 11 | DIV: 12 | name: DIVH 13 | DIVL: 14 | _modify: 15 | DIV: 16 | name: DIVL 17 | CNTH: 18 | _modify: 19 | RTC_CNT: 20 | name: CNTH 21 | CNTL: 22 | _modify: 23 | RTC_CNT: 24 | name: CNTL 25 | ALRH: 26 | _modify: 27 | RTC_ALR: 28 | name: ALRH 29 | ALRL: 30 | _modify: 31 | RTC_ALR: 32 | name: ALRL 33 | _modify: 34 | BKP_RTCCR: 35 | name: RTCCR 36 | -------------------------------------------------------------------------------- /devices/common_patches/syscfg_f002a.yaml: -------------------------------------------------------------------------------- 1 | SYSCFG: 2 | CFGR2: 3 | _add: 4 | COMP1_BRK_TIM1: 5 | description: "COMP1 output connect to TIM1 Break input" 6 | bitOffset: 3 7 | bitWidth: 1 8 | COMP2_BRK_TIM1: 9 | description: "COMP2 output connect to TIM1 Break input" 10 | bitOffset: 4 11 | bitWidth: 1 12 | COMP1_BRK_TIM16: 13 | description: "COMP1 output connect to TIM16 Break input" 14 | bitOffset: 5 15 | bitWidth: 1 16 | COMP2_BRK_TIM16: 17 | description: "COMP2 output connect to TIM16 Break input" 18 | bitOffset: 6 19 | bitWidth: 1 -------------------------------------------------------------------------------- /cortex_m/armv7m.yaml: -------------------------------------------------------------------------------- 1 | _svd: armv7m.svd 2 | 3 | _include: 4 | - peripherals/cpb.yaml 5 | - peripherals/cpuid_v7.yaml 6 | - peripherals/dcb.yaml 7 | - peripherals/dwt.yaml 8 | - peripherals/fpb.yaml 9 | - peripherals/itm.yaml 10 | # These three peripherals are included in the ST SVD files, so don't 11 | # include them in the generic ARMv7-M SVD as well. 12 | # Uncomment them here if you want to include them for some other reason. 13 | #- peripherals/mpu.yaml 14 | #- peripherals/nvic.yaml 15 | #- peripherals/nvic_v7.yaml 16 | #- peripherals/scb.yaml 17 | #- peripherals/scb_v7.yaml 18 | - peripherals/syst.yaml 19 | - peripherals/tpiu.yaml 20 | -------------------------------------------------------------------------------- /devices/common_patches/isr_array.yaml: -------------------------------------------------------------------------------- 1 | ISR: 2 | _array: 3 | "TEIF*": 4 | description: Channel %s Transfer Error flag 5 | "HTIF*": 6 | description: Channel %s Half Transfer Complete flag 7 | "TCIF*": 8 | description: Channel %s Transfer Complete flag 9 | "GIF*": 10 | description: Channel %s Global interrupt flag 11 | 12 | IFCR: 13 | _array: 14 | "CTEIF*": 15 | description: Channel %s Transfer Error clear 16 | "CHTIF*": 17 | description: Channel %s Half Transfer clear 18 | "CTCIF*": 19 | description: Channel %s Transfer Complete clear 20 | "CGIF*": 21 | description: Channel %s Global interrupt clear 22 | -------------------------------------------------------------------------------- /cortex_m/armv7em.yaml: -------------------------------------------------------------------------------- 1 | _svd: armv7em.svd 2 | 3 | _include: 4 | - peripherals/cpb.yaml 5 | - peripherals/cpuid_v7.yaml 6 | - peripherals/dcb.yaml 7 | - peripherals/dwt.yaml 8 | - peripherals/fpb.yaml 9 | # These five peripherals are included in the ST SVD files, so don't 10 | # include them in the generic ARMv7E-M SVD as well. 11 | # Uncomment them here if you want to include them for some other reason. 12 | #- peripherals/fpu.yaml 13 | #- peripherals/mpu.yaml 14 | #- peripherals/nvic.yaml 15 | #- peripherals/nvic_v7.yaml 16 | #- peripherals/scb.yaml 17 | #- peripherals/scb_v7.yaml 18 | - peripherals/itm.yaml 19 | - peripherals/syst.yaml 20 | - peripherals/tpiu.yaml 21 | -------------------------------------------------------------------------------- /.github/workflows/changelog.yaml: -------------------------------------------------------------------------------- 1 | on: 2 | pull_request: 3 | # Run on labeled/unlabeled in addition to defaults to detect 4 | # adding/removing skip-changelog labels. 5 | types: [ opened, reopened, labeled, unlabeled, synchronize ] 6 | merge_group: 7 | 8 | name: Changelog 9 | 10 | jobs: 11 | changelog: 12 | name: Require Changelog 13 | runs-on: ubuntu-latest 14 | steps: 15 | - name: Checkout sources 16 | uses: actions/checkout@v3 17 | 18 | - name: Check changelog update 19 | uses: dangoslen/changelog-enforcer@v3 20 | with: 21 | skipLabels: skip-changelog 22 | missingUpdateErrorMessage: 'Please add a changelog entry to the appropriate section of the CHANGELOG.md file.' 23 | -------------------------------------------------------------------------------- /peripherals/dbg/dbg_f002b.yaml: -------------------------------------------------------------------------------- 1 | _modify: 2 | DBGMCU: 3 | name: DBG 4 | 5 | DBG: 6 | IDCODE: 7 | _add: 8 | CODE: 9 | description: DBG ID code register 10 | bitOffset: 0 11 | bitWidth: 32 12 | CR: 13 | DBG_STOP: 14 | Disabled: [0, "Debug Stop Mode Disabled"] 15 | Enabled: [1, "Debug Stop Mode Enabled"] 16 | APB_FZ1: 17 | DBG_LPTIM_STOP: 18 | Continue: [ 0, "LPTIMx counter clock is fed even if the core is halted" ] 19 | Stop: [ 1, "LPTIMx counter clock is stopped when the core is halted" ] 20 | APB_FZ2: 21 | "DBG_TIM*_STOP": 22 | Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] 23 | Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] 24 | 25 | -------------------------------------------------------------------------------- /cortex_m/peripherals/syst.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | SYST: 5 | description: System Timer 6 | baseAddress: 0xE000E010 7 | addressBlock: 8 | offset: 0x0 9 | size: 0xF0 10 | registers: 11 | CSR: 12 | description: SysTick Control and Status Register 13 | addressOffset: 0x0 14 | access: read-write 15 | RVR: 16 | description: SysTick Reload Value Register 17 | addressOffset: 0x4 18 | access: read-write 19 | CVR: 20 | description: SysTick Current Value Register 21 | addressOffset: 0x8 22 | access: read-write 23 | CALIB: 24 | description: SysTick Calibration Value Register 25 | addressOffset: 0x1C 26 | access: read-only 27 | -------------------------------------------------------------------------------- /cortex_m/peripherals/dcb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | DCB: 5 | description: Debug Control Block 6 | baseAddress: 0xE000EDF0 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x110 10 | registers: 11 | DHCSR: 12 | description: Debug Halting Control and Status Register 13 | addressOffset: 0x0 14 | access: read-write 15 | DCRSR: 16 | description: Debug Core Register Selector Register 17 | addressOffset: 0x4 18 | access: write-only 19 | DCRDR: 20 | description: Debug Core Register Data Register 21 | addressOffset: 0x8 22 | access: read-write 23 | DEMCR: 24 | description: Debug Exception and Monitor Control Register 25 | addressOffset: 0xC 26 | access: read-write 27 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/dcb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | DCB: 5 | description: Debug Control Block 6 | baseAddress: 0xE000EDF0 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x110 10 | registers: 11 | DHCSR: 12 | description: Debug Halting Control and Status Register 13 | addressOffset: 0x0 14 | access: read-write 15 | DCRSR: 16 | description: Debug Core Register Selector Register 17 | addressOffset: 0x4 18 | access: write-only 19 | DCRDR: 20 | description: Debug Core Register Data Register 21 | addressOffset: 0x8 22 | access: read-write 23 | DEMCR: 24 | description: Debug Exception and Monitor Control Register 25 | addressOffset: 0xC 26 | access: read-write 27 | -------------------------------------------------------------------------------- /peripherals/iwdg/iwdg_f002b.yaml: -------------------------------------------------------------------------------- 1 | "IWDG,IWDG?": 2 | KR: 3 | KEY: 4 | Enable: [21845, "Enable access to PR, RLR and WINR registers (0x5555)"] 5 | Reset: [43690, "Reset the watchdog value (0xAAAA)"] 6 | Start: [52428, "Start the watchdog (0xCCCC)"] 7 | PR: 8 | PR: 9 | DivideBy4: [0, "Divider /4"] 10 | DivideBy8: [1, "Divider /8"] 11 | DivideBy16: [2, "Divider /16"] 12 | DivideBy32: [3, "Divider /32"] 13 | DivideBy64: [4, "Divider /64"] 14 | DivideBy128: [5, "Divider /128"] 15 | DivideBy256: [6, "Divider /256"] 16 | DivideBy256bis: [7, "Divider /256"] 17 | RLR: 18 | RL: [0, 4095] 19 | SR: 20 | RVU: 21 | Idle: [0, "No update on-going"] 22 | Busy: [1, "Update on-going"] 23 | PVU: 24 | Idle: [0, "No update on-going"] 25 | Busy: [1, "Update on-going"] 26 | -------------------------------------------------------------------------------- /cortex_m/armv6m.svd: -------------------------------------------------------------------------------- 1 | 2 | 5 | ARMv6-M 6 | 1.0 7 | ARMv6-M Common Peripherals 8 | 9 | CM3 10 | r1p0 11 | little 12 | false 13 | false 14 | 3 15 | false 16 | 17 | 8 18 | 32 19 | 0x20 20 | 0x0 21 | 0xFFFFFFFF 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /cortex_m/armv7em.svd: -------------------------------------------------------------------------------- 1 | 2 | 5 | ARMv7E-M 6 | 1.0 7 | ARMv7E-M Common Peripherals 8 | 9 | CM4 10 | r1p0 11 | little 12 | true 13 | true 14 | 3 15 | false 16 | 17 | 8 18 | 32 19 | 0x20 20 | 0x0 21 | 0xFFFFFFFF 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /cortex_m/armv7m.svd: -------------------------------------------------------------------------------- 1 | 2 | 5 | ARMv7-M 6 | 1.0 7 | ARMv7-M Common Peripherals 8 | 9 | CM4 10 | r1p0 11 | little 12 | true 13 | false 14 | 3 15 | false 16 | 17 | 8 18 | 32 19 | 0x20 20 | 0x0 21 | 0xFFFFFFFF 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /cortex_m/armv8m.svd: -------------------------------------------------------------------------------- 1 | 2 | 5 | ARMv8-M 6 | 1.0 7 | ARMv8-M Common Peripherals 8 | 9 | CM33 10 | r1p0 11 | little 12 | true 13 | false 14 | 3 15 | false 16 | 17 | 8 18 | 32 19 | 0x20 20 | 0x0 21 | 0xFFFFFFFF 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /peripherals/wwdg/wwdg_f0.yaml: -------------------------------------------------------------------------------- 1 | "WWDG,WWDG?": 2 | CR: 3 | WDGA: 4 | Disabled: [0, "Watchdog disabled"] 5 | Enabled: [1, "Watchdog enabled"] 6 | T: [0, 127] 7 | CFR: 8 | _merge: 9 | - "WDGTB*" 10 | WDGTB: 11 | Div1: [0, "Counter clock (PCLK1 div 4096) div 1"] 12 | Div2: [1, "Counter clock (PCLK1 div 4096) div 2"] 13 | Div4: [2, "Counter clock (PCLK1 div 4096) div 4"] 14 | Div8: [3, "Counter clock (PCLK1 div 4096) div 8"] 15 | W: [0, 127] 16 | EWI: 17 | _write: 18 | Enable: [1, "interrupt occurs whenever the counter reaches the value 0x40"] 19 | SR: 20 | EWIF: 21 | _read: 22 | Pending: [1, "The EWI Interrupt Service Routine has been triggered"] 23 | Finished: [0, "The EWI Interrupt Service Routine has been serviced"] 24 | _W0C: 25 | Finished: [0, "The EWI Interrupt Service Routine has been serviced"] 26 | -------------------------------------------------------------------------------- /scripts/comparesvd.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import xml.etree.ElementTree as ET 3 | 4 | s1 = ET.parse(sys.argv[1]) 5 | s2 = ET.parse(sys.argv[2]) 6 | 7 | 8 | def getregs(s): 9 | regs = {} 10 | for peripheral in s.iter('peripheral'): 11 | pname = peripheral.find('name').text 12 | base = int(peripheral.find('baseAddress').text, 0) 13 | for register in peripheral.iter('register'): 14 | rname = register.find('name').text 15 | name = pname + "_" + rname 16 | offset = int(register.find('addressOffset').text, 0) 17 | regs[name] = hex(base+offset) 18 | return regs 19 | 20 | r1 = getregs(s1) 21 | r2 = getregs(s2) 22 | 23 | for reg in r1: 24 | if reg not in r2: 25 | print("+A", reg, r1[reg]) 26 | else: 27 | if r1[reg] != r2[reg]: 28 | print("X ", reg, r1[reg], r2[reg]) 29 | for reg in r2: 30 | if reg not in r1: 31 | print("+B", reg, r2[reg]) 32 | -------------------------------------------------------------------------------- /peripherals/iwdg/iwdg_f0.yaml: -------------------------------------------------------------------------------- 1 | "IWDG,IWDG?": 2 | KR: 3 | KEY: 4 | Enable: [21845, "Enable access to PR, RLR and WINR registers (0x5555)"] 5 | Reset: [43690, "Reset the watchdog value (0xAAAA)"] 6 | Start: [52428, "Start the watchdog (0xCCCC)"] 7 | PR: 8 | PR: 9 | DivideBy4: [0, "Divider /4"] 10 | DivideBy8: [1, "Divider /8"] 11 | DivideBy16: [2, "Divider /16"] 12 | DivideBy32: [3, "Divider /32"] 13 | DivideBy64: [4, "Divider /64"] 14 | DivideBy128: [5, "Divider /128"] 15 | DivideBy256: [6, "Divider /256"] 16 | DivideBy256bis: [7, "Divider /256"] 17 | RLR: 18 | RL: [0, 4095] 19 | SR: 20 | ?~WVU: 21 | Idle: [0, "No update on-going"] 22 | Busy: [1, "Update on-going"] 23 | RVU: 24 | Idle: [0, "No update on-going"] 25 | Busy: [1, "Update on-going"] 26 | PVU: 27 | Idle: [0, "No update on-going"] 28 | Busy: [1, "Update on-going"] 29 | ?~WINR: 30 | WIN: [0, 4095] 31 | -------------------------------------------------------------------------------- /peripherals/dbg/dbg_f002a.yaml: -------------------------------------------------------------------------------- 1 | _modify: 2 | DBGMCU: 3 | name: DBG 4 | 5 | DBG: 6 | IDCODE: 7 | _add: 8 | CODE: 9 | description: DBG ID code register 10 | bitOffset: 0 11 | bitWidth: 32 12 | CR: 13 | DBG_STOP: 14 | Disabled: [0, "Debug Stop Mode Disabled"] 15 | Enabled: [1, "Debug Stop Mode Enabled"] 16 | APB_FZ1: 17 | DBG_IWDG_STOP: 18 | Continue: [0, "The independent watchdog counter clock continues even if the core is halted"] 19 | Stop: [1, "The independent watchdog counter clock is stopped when the core is halted"] 20 | DBG_LPTIM_STOP: 21 | Continue: [ 0, "LPTIMx counter clock is fed even if the core is halted" ] 22 | Stop: [ 1, "LPTIMx counter clock is stopped when the core is halted" ] 23 | APB_FZ2: 24 | "DBG_TIM*_STOP": 25 | Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] 26 | Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] 27 | 28 | -------------------------------------------------------------------------------- /devices/py32f002a.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/py32f002a.svd 2 | 3 | "SPI*": 4 | _include: 5 | - common_patches/spi_dr8.yaml 6 | 7 | "USART*": 8 | _include: 9 | - common_patches/usart_dr8.yaml 10 | 11 | TIM1: 12 | _include: 13 | - common_patches/timer_ccr_reg_array.yaml 14 | 15 | _include: 16 | - ./common_patches/pwr_f002a.yaml 17 | - ./common_patches/syscfg_f002a.yaml 18 | - ../peripherals/flash/flash_f002a.yaml 19 | - ../peripherals/pwr/pwr_f002a.yaml 20 | - ../peripherals/rcc/rcc_f002a.yaml 21 | - ../peripherals/gpio/gpio_f0.yaml 22 | - ../peripherals/syscfg/syscfg_f002a.yaml 23 | - ../peripherals/exti/exti_f0.yaml 24 | - ../peripherals/crc/crc_f0.yaml 25 | - ../peripherals/adc/adc_f002a.yaml 26 | - ../peripherals/comp/comp_f0.yaml 27 | - ../peripherals/tim/tim_f002a.yaml 28 | - ../peripherals/lptim/lptim_f0.yaml 29 | - ../peripherals/iwdg/iwdg_f0.yaml 30 | - ../peripherals/i2c/i2c_f002a.yaml 31 | - ../peripherals/usart/usart_f002a.yaml 32 | - ../peripherals/spi/spi_f002a.yaml 33 | - ../peripherals/dbg/dbg_f002a.yaml 34 | -------------------------------------------------------------------------------- /cortex_m/peripherals/scb_v7.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | SCB: 4 | _add: 5 | _registers: 6 | SHPR1: 7 | description: System Handler Priority Register 1 8 | addressOffset: 0x18 9 | access: read-write 10 | CFSR: 11 | description: Configurable Fault Status Register 12 | addressOffset: 0x28 13 | access: read-write 14 | HFSR: 15 | description: HardFault Status Register 16 | addressOffset: 0x2C 17 | access: read-write 18 | MMFAR: 19 | description: MemManage Fault Address Register 20 | addressOffset: 0x34 21 | access: read-write 22 | BFAR: 23 | description: BusFault Address Register 24 | addressOffset: 0x38 25 | access: read-write 26 | AFSR: 27 | description: Auxiliary Fault Status Register 28 | addressOffset: 0x3C 29 | access: read-write 30 | CPACR: 31 | description: Coprocessor Access Control Register 32 | addressOffset: 0x88 33 | access: read-write 34 | -------------------------------------------------------------------------------- /peripherals/syscfg/syscfg_f002a.yaml: -------------------------------------------------------------------------------- 1 | SYSCFG: 2 | CFGR1: 3 | MEM_MODE: 4 | MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] 5 | SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] 6 | MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] 7 | SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] 8 | "I2C_P?*_ANF": 9 | Standard: [0, "Pin operate in standard mode"] 10 | AnalogFilter: [1, "I2C Analog filter enabled on pin"] 11 | CFGR2: 12 | ETR_SRC_TIM1: 13 | GPIO: [0, "TIM1_ETR is connected to GPIO"] 14 | COMP1: [1, "TIM1_ETR is connected to COMP1"] 15 | COMP2: [2, "TIM1_ETR is connected to COMP2"] 16 | ADC: [3, "TIM1_ETR is connected to ADC"] 17 | "COMP?_BRK_TIM*": 18 | Disconnected: [0, "COMP? output not connect to TIM? Break input"] 19 | Connected: [1, "COMP? output connected to TIM? Break input"] 20 | LOCKUP_LOCK: 21 | Disconnected: [0, "Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input"] 22 | Connected: [1, "Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input"] -------------------------------------------------------------------------------- /peripherals/pwr/pwr_f002b.yaml: -------------------------------------------------------------------------------- 1 | PWR: 2 | CR1: 3 | HSION_CTRL: 4 | WaiteMR: [0, "Enable HSI after MR is stable"] 5 | WakeOnVR: [1, "Enable HSI when VR is on (enable HSI immediately when wakeup)"] 6 | SRAM_RETV: 7 | V0_9: [3, "Supply voltage 0.9 V for SRAM"] 8 | V1_x: [4, "Supply voltage 1.0 or 1.2 V (depends on VOS) for SRAM"] 9 | _modify: 10 | LPR: 11 | name: LPRUN 12 | LPRUN: 13 | MainMode: [0, "Voltage regulator in Main mode in Low-power run mode"] 14 | LowPowerMode: [1, "Voltage regulator in low-power mode in Low-power run mode"] 15 | FLS_SLPTIME: 16 | FiveMicroSec: [0, "Flash wait 5 us after wakeup from stop mode"] 17 | TwoMicroSec: [1, "Flash wait 2 us after wakeup from stop mode"] 18 | ThreeMicroSec: [2, "Flash wait 3 us after wakeup from stop mode"] 19 | ExcuteFromSRAM: [3, "Excute program from SRAM after wakeup from stop mode"] 20 | BIAS_CR_SEL: 21 | FactoryConfig: [0, "Bias config from factory config bytes"] 22 | BiasCR: [1, "Bias config from BIAS_CR register"] 23 | BIAS_CR: 24 | [0, 15] -------------------------------------------------------------------------------- /cortex_m/peripherals/fpu.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | FPU: 5 | description: Floating Point Unit 6 | baseAddress: 0xE000EF30 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x1C 10 | registers: 11 | FPCCR: 12 | description: Floating Point Context Control Register 13 | addressOffset: 0x4 14 | access: read-write 15 | FPCAR: 16 | description: Floating Point Context Address Register 17 | addressOffset: 0x8 18 | access: read-write 19 | FPDSCR: 20 | description: Floating Point Default Status Control Register 21 | addressOffset: 0xC 22 | access: read-write 23 | MVFR0: 24 | description: Media and FP Feature Register 0 25 | addressOffset: 0x10 26 | access: read-only 27 | MVFR1: 28 | description: Media and FP Feature Register 1 29 | addressOffset: 0x14 30 | access: read-only 31 | MVFR2: 32 | description: Media and FP Feature Register 2 33 | addressOffset: 0x18 34 | access: read-only 35 | -------------------------------------------------------------------------------- /devices/py32f002b.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/py32f002b.svd 2 | 3 | "SPI*": 4 | _include: 5 | - common_patches/spi_dr8.yaml 6 | - common_patches/spi_f002b.yaml 7 | 8 | "USART*": 9 | _include: 10 | - common_patches/usart_dr8.yaml 11 | 12 | "DBG": 13 | _include: 14 | - common_patches/f002b_dbg.yaml 15 | 16 | "TIM*": 17 | _include: 18 | - common_patches/timer_ccr_reg_array.yaml 19 | 20 | _include: 21 | - ./common_patches/syscfg_f002b.yaml 22 | - ../peripherals/flash/flash_f002b.yaml 23 | - ../peripherals/pwr/pwr_f002b.yaml 24 | - ../peripherals/rcc/rcc_f002b.yaml 25 | - ../peripherals/gpio/gpio_f0.yaml 26 | - ../peripherals/syscfg/syscfg_f002b.yaml 27 | - ../peripherals/exti/exti_f0.yaml 28 | - ../peripherals/crc/crc_f0.yaml 29 | - ../peripherals/adc/adc_f002b.yaml 30 | - ../peripherals/comp/comp_f002b.yaml 31 | - ../peripherals/tim/tim_f002b.yaml 32 | - ../peripherals/lptim/lptim_f0.yaml 33 | - ../peripherals/iwdg/iwdg_f002b.yaml 34 | - ../peripherals/i2c/i2c_f002b.yaml 35 | - ../peripherals/usart/usart_f002b.yaml 36 | - ../peripherals/spi/spi_f002b.yaml 37 | - ../peripherals/dbg/dbg_f002b.yaml 38 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/fpu.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | FPU: 5 | description: Floating Point Unit 6 | baseAddress: 0xE000EF30 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x1C 10 | registers: 11 | FPCCR: 12 | description: Floating Point Context Control register 13 | addressOffset: 0x4 14 | access: read-write 15 | FPCAR: 16 | description: Floating Point Context Address register 17 | addressOffset: 0x8 18 | access: read-write 19 | FPDSCR: 20 | description: Floating Point Default Status Control register 21 | addressOffset: 0xC 22 | access: read-write 23 | MVFR0: 24 | description: Media and FP Feature Register 0 25 | addressOffset: 0x10 26 | access: read-only 27 | MVFR1: 28 | description: Media and FP Feature Register 1 29 | addressOffset: 0x14 30 | access: read-only 31 | MVFR2: 32 | description: Media and FP Feature Register 2 33 | addressOffset: 0x18 34 | access: read-only 35 | -------------------------------------------------------------------------------- /devices/py32f003.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/py32f003.svd 2 | 3 | "SPI*": 4 | _include: 5 | - common_patches/spi_dr8.yaml 6 | 7 | "USART*": 8 | _include: 9 | - common_patches/usart_dr8.yaml 10 | 11 | "DMA, DMA[12]": 12 | _include: 13 | - common_patches/dma_cluster.yaml 14 | 15 | "TIM*": 16 | _include: 17 | - common_patches/timer_ccr_reg_array.yaml 18 | 19 | _include: 20 | - ../peripherals/flash/flash_f0.yaml 21 | - ../peripherals/pwr/pwr_f0.yaml 22 | - ../peripherals/rcc/rcc_f003.yaml 23 | - ../peripherals/gpio/gpio_f0.yaml 24 | - ../peripherals/syscfg/syscfg_f0.yaml 25 | - ../peripherals/dma/dma_f0.yaml 26 | - ../peripherals/exti/exti_f0.yaml 27 | - ../peripherals/crc/crc_f0.yaml 28 | - ../peripherals/adc/adc_f0.yaml 29 | - ../peripherals/comp/comp_f0.yaml 30 | - ../peripherals/tim/tim_f0.yaml 31 | - ../peripherals/lptim/lptim_f0.yaml 32 | - ../peripherals/iwdg/iwdg_f0.yaml 33 | - ../peripherals/wwdg/wwdg_f0.yaml 34 | - ../peripherals/rtc/rtc_f0.yaml 35 | - ../peripherals/i2c/i2c_f0.yaml 36 | - ../peripherals/usart/usart_f0.yaml 37 | - ../peripherals/spi/spi_f0.yaml 38 | - ../peripherals/dbg/dbg_f0.yaml 39 | -------------------------------------------------------------------------------- /.github/workflows/gh-pages.yaml: -------------------------------------------------------------------------------- 1 | name: build gh-pages 2 | on: 3 | push: 4 | branches: 5 | - master 6 | 7 | jobs: 8 | build_html: 9 | name: Build HTML 10 | runs-on: ubuntu-latest 11 | env: 12 | SVDTOOLS: svdtools 13 | steps: 14 | - name: Checkout master 15 | uses: actions/checkout@v3 16 | with: 17 | persist-credentials: false 18 | - name: Install tools 19 | run: | 20 | ./scripts/tool_install.sh svdtools 21 | ./scripts/tool_install.sh svd2html 22 | - name: Build HTML 23 | run: make -j2 html 24 | - name: Upload artifact 25 | uses: actions/upload-pages-artifact@v1 26 | with: 27 | path: html 28 | 29 | deploy_pages: 30 | name: Deploy GH Pages 31 | runs-on: ubuntu-latest 32 | needs: build_html 33 | permissions: 34 | pages: write 35 | id-token: write 36 | environment: 37 | name: github-pages 38 | url: ${{ steps.deployment.outputs.page_url }} 39 | steps: 40 | - name: Deploy to Github Pages 41 | id: deployment 42 | uses: actions/deploy-pages@v1 43 | -------------------------------------------------------------------------------- /cortex_m/peripherals/nvic_v6.yaml: -------------------------------------------------------------------------------- 1 | NVIC: 2 | _add: 3 | _registers: 4 | IPR0: 5 | description: Interrupt Priority Register 0 6 | addressOffset: 0x300 7 | access: read-write 8 | IPR1: 9 | description: Interrupt Priority Register 1 10 | addressOffset: 0x304 11 | access: read-write 12 | IPR2: 13 | description: Interrupt Priority Register 2 14 | addressOffset: 0x308 15 | access: read-write 16 | IPR3: 17 | description: Interrupt Priority Register 3 18 | addressOffset: 0x30c 19 | access: read-write 20 | IPR4: 21 | description: Interrupt Priority Register 4 22 | addressOffset: 0x310 23 | access: read-write 24 | IPR5: 25 | description: Interrupt Priority Register 5 26 | addressOffset: 0x314 27 | access: read-write 28 | IPR6: 29 | description: Interrupt Priority Register 6 30 | addressOffset: 0x318 31 | access: read-write 32 | IPR7: 33 | description: Interrupt Priority Register 7 34 | addressOffset: 0x31c 35 | access: read-write 36 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/nvic_v6.yaml: -------------------------------------------------------------------------------- 1 | NVIC: 2 | _add: 3 | _registers: 4 | IPR0: 5 | description: Interrupt Priority register 0 6 | addressOffset: 0x300 7 | access: read-write 8 | IPR1: 9 | description: Interrupt Priority register 1 10 | addressOffset: 0x304 11 | access: read-write 12 | IPR2: 13 | description: Interrupt Priority register 2 14 | addressOffset: 0x308 15 | access: read-write 16 | IPR3: 17 | description: Interrupt Priority register 3 18 | addressOffset: 0x30c 19 | access: read-write 20 | IPR4: 21 | description: Interrupt Priority register 4 22 | addressOffset: 0x310 23 | access: read-write 24 | IPR5: 25 | description: Interrupt Priority register 5 26 | addressOffset: 0x314 27 | access: read-write 28 | IPR6: 29 | description: Interrupt Priority register 6 30 | addressOffset: 0x318 31 | access: read-write 32 | IPR7: 33 | description: Interrupt Priority register 7 34 | addressOffset: 0x31c 35 | access: read-write 36 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | Copyright (c) 2017 The py32-rs authors. 2 | 3 | Permission is hereby granted, free of charge, to any 4 | person obtaining a copy of this software and associated 5 | documentation files (the "Software"), to deal in the 6 | Software without restriction, including without 7 | limitation the rights to use, copy, modify, merge, 8 | publish, distribute, sublicense, and/or sell copies of 9 | the Software, and to permit persons to whom the Software 10 | is furnished to do so, subject to the following 11 | conditions: 12 | 13 | The above copyright notice and this permission notice 14 | shall be included in all copies or substantial portions 15 | of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF 18 | ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 19 | TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 20 | PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT 21 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 22 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 24 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 | DEALINGS IN THE SOFTWARE. 26 | -------------------------------------------------------------------------------- /devices/py32f030.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/py32f030.svd 2 | 3 | "SPI*": 4 | _include: 5 | - common_patches/spi_dr8.yaml 6 | 7 | "USART*": 8 | _include: 9 | - common_patches/usart_dr8.yaml 10 | 11 | "DMA, DMA[12]": 12 | _include: 13 | - common_patches/dma_cluster.yaml 14 | 15 | "TIM*": 16 | _include: 17 | - common_patches/timer_ccr_reg_array.yaml 18 | 19 | _include: 20 | - ../peripherals/flash/flash_f0.yaml 21 | - ../peripherals/pwr/pwr_f0.yaml 22 | - ../peripherals/rcc/rcc_f0.yaml 23 | - ../peripherals/gpio/gpio_f0.yaml 24 | - ../peripherals/syscfg/syscfg_f0.yaml 25 | - ../peripherals/dma/dma_f0.yaml 26 | - ../peripherals/exti/exti_f0.yaml 27 | - ../peripherals/crc/crc_f0.yaml 28 | - ../peripherals/adc/adc_f0.yaml 29 | - ../peripherals/comp/comp_f0.yaml 30 | - ../peripherals/led/led_f0.yaml 31 | - ../peripherals/tim/tim_f0.yaml 32 | - ../peripherals/lptim/lptim_f0.yaml 33 | - ../peripherals/iwdg/iwdg_f0.yaml 34 | - ../peripherals/wwdg/wwdg_f0.yaml 35 | - ../peripherals/rtc/rtc_f0.yaml 36 | - ../peripherals/i2c/i2c_f0.yaml 37 | - ../peripherals/usart/usart_f0.yaml 38 | - ../peripherals/spi/spi_f0.yaml 39 | - ../peripherals/dbg/dbg_f0.yaml 40 | -------------------------------------------------------------------------------- /peripherals/syscfg/syscfg_f002b.yaml: -------------------------------------------------------------------------------- 1 | SYSCFG: 2 | CFGR1: 3 | MEM_MODE: 4 | MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] 5 | SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] 6 | MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] 7 | SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] 8 | "I2C_P?*_FMP": 9 | Standard: [0, "Pin operate in standard mode"] 10 | AnalogFilter: [1, "I2C FM+ mode enabled on pin"] 11 | CFGR2: 12 | ETR_SRC_TIM1: 13 | GPIO: [0, "TIM1_ETR is connected to GPIO"] 14 | COMP1: [1, "TIM1_ETR is connected to COMP1"] 15 | COMP2: [2, "TIM1_ETR is connected to COMP2"] 16 | ADC: [3, "TIM1_ETR is connected to ADC"] 17 | "COMP?_BRK_TIM*": 18 | Disconnected: [0, "COMP? output not connect to TIM? Break input"] 19 | Connected: [1, "COMP? output connected to TIM? Break input"] 20 | LOCKUP_LOCK: 21 | Disconnected: [0, "Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input"] 22 | Connected: [1, "Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input"] 23 | GPIO_ENS: 24 | PA_ENS: [0, 63] 25 | PB_ENS: [0, 63] 26 | PC_ENS: [0, 3] 27 | -------------------------------------------------------------------------------- /cortex_m/peripherals/tpiu.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | TPIU: 5 | description: Trace Port Interface Unit 6 | baseAddress: 0xE0040000 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x1000 10 | registers: 11 | SSPSR: 12 | description: Supported Parallel Port Sizes Register 13 | addressOffset: 0x0 14 | access: read-only 15 | CSPSR: 16 | description: Current Parallel Port Size Register 17 | addressOffset: 0x4 18 | access: read-write 19 | ACPR: 20 | description: Asynchronous Clock Prescaler Register 21 | addressOffset: 0x10 22 | access: read-write 23 | SPPR: 24 | description: Selected Pin Protocol Register 25 | addressOffset: 0xF0 26 | access: read-write 27 | TYPE: 28 | description: TPIU Type Register 29 | addressOffset: 0xFC8 30 | access: read-only 31 | LSR: 32 | description: Lock Status Register 33 | addressOffset: 0xFB4 34 | access: read-only 35 | LAR: 36 | description: Lock Access Register 37 | addressOffset: 0xFB0 38 | access: write-only 39 | -------------------------------------------------------------------------------- /peripherals/lptim/lptim_f0.yaml: -------------------------------------------------------------------------------- 1 | LPTIM,LPTIM?: 2 | ISR: 3 | ARRM: 4 | _read: 5 | Set: [1, "Autoreload match"] 6 | ICR: 7 | ARRMCF: 8 | _write: 9 | Clear: [1, "Autoreload match Clear Flag"] 10 | IER: 11 | ARRMIE: 12 | Disabled: [0, "ARRM interrupt disabled"] 13 | Enabled: [1, "ARRM interrupt enabled"] 14 | CFGR: 15 | PRELOAD: 16 | Immediate: [0, "Registers are updated after each APB bus write access"] 17 | EndOfPeriod: [1, "Registers are updated at the end of the current LPTIM period"] 18 | PRESC: 19 | Div1: [0, "/1"] 20 | Div2: [1, "/2"] 21 | Div4: [2, "/4"] 22 | Div8: [3, "/8"] 23 | Div16: [4, "/16"] 24 | Div32: [5, "/32"] 25 | Div64: [6, "/64"] 26 | Div128: [7, "/128"] 27 | CR: 28 | RSTARE: 29 | Disabled: [0, "CNT Register reads do not trigger reset"] 30 | Enabled: [1, "CNT Register reads trigger reset of LPTIM"] 31 | SNGSTRT: 32 | _write: 33 | Start: [1, "LPTIM start in Single mode"] 34 | ENABLE: 35 | Disabled: [0, "LPTIM is disabled"] 36 | Enabled: [1, "LPTIM is enabled"] 37 | ARR: 38 | ARR: [0, 0xFFFF] 39 | CNT: 40 | CNT: [0, 0xFFFF] 41 | -------------------------------------------------------------------------------- /peripherals/exti/exti_f0.yaml: -------------------------------------------------------------------------------- 1 | EXTI: 2 | RTSR: 3 | "RT*": 4 | Disabled: [0, "Rising edge trigger is disabled"] 5 | Enabled: [1, "Rising edge trigger is enabled"] 6 | FTSR: 7 | "FT*": 8 | Disabled: [0, "Falling edge trigger is disabled"] 9 | Enabled: [1, "Falling edge trigger is enabled"] 10 | SWIER,SWIER?: 11 | "SWI*": 12 | _write: 13 | Pend: [1, "Generates an interrupt request"] 14 | PR: 15 | "PR*": 16 | _W1C: 17 | Clear: [1, "Clears pending bit"] 18 | _read: 19 | NotPending: [0, "No trigger request occurred"] 20 | Pending: [1, "Selected trigger request occurred"] 21 | "EXTICR[12]": 22 | "EXTI[0-4]": 23 | PA: [0, "GPIO port A selected"] 24 | PB: [1, "GPIO port B selected"] 25 | PF: [2, "GPIO port F selected"] 26 | "EXTICR[23]": 27 | "EXTI[5-8]": 28 | PA: [0, "GPIO port A selected"] 29 | PB: [1, "GPIO port B selected"] 30 | IMR: 31 | "IM*": 32 | Masked: [0, "Interrupt request line is masked"] 33 | Unmasked: [1, "Interrupt request line is unmasked"] 34 | EMR: 35 | "EM*": 36 | Masked: [0, "Interrupt request line is masked"] 37 | Unmasked: [1, "Interrupt request line is unmasked"] 38 | -------------------------------------------------------------------------------- /.github/workflows/ci.yaml: -------------------------------------------------------------------------------- 1 | name: CI 2 | 3 | on: 4 | push: 5 | branches: 6 | - master 7 | pull_request: 8 | merge_group: 9 | 10 | jobs: 11 | check: 12 | name: Check 13 | runs-on: ubuntu-latest 14 | strategy: 15 | matrix: 16 | crate: 17 | - py32f0 18 | 19 | env: 20 | CRATES: ${{ matrix.crate }} 21 | CARGO_INCREMENTAL: 0 22 | SVDTOOLS: svdtools 23 | 24 | steps: 25 | - name: Checkout code 26 | uses: actions/checkout@v3 27 | 28 | - name: Install Rust 29 | uses: dtolnay/rust-toolchain@stable 30 | with: 31 | components: rustfmt 32 | 33 | - name: Install xmllint 34 | run: | 35 | sudo apt-get update 36 | sudo apt-get install libxml2-utils 37 | 38 | - name: Create working crate 39 | run: make crates 40 | 41 | - name: Install tools 42 | run: | 43 | ./scripts/tool_install.sh svdtools 44 | ./scripts/tool_install.sh svd2rust 45 | 46 | - name: Patch SVDs 47 | run: make -j2 patch 48 | 49 | - name: Check SVDs 50 | run: make lint 51 | 52 | - name: Build PACs 53 | run: make -j2 svd2rust 54 | 55 | - name: Check PACs 56 | run: make -j2 check 57 | -------------------------------------------------------------------------------- /cortex_m/peripherals/cpuid_v6.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv6-M Architecture Reference Manual issue C 2 | 3 | _add: 4 | CPUID: 5 | description: CPUID 6 | baseAddress: 0xE000ED00 7 | addressBlock: 8 | offset: 0x0 9 | size: 4 10 | registers: 11 | Base: 12 | description: Provides identification information for the processor 13 | addressOffset: 0x0 14 | access: read-only 15 | fields: 16 | IMPLEMENTER: 17 | description: This field defines the implementer 18 | bitOffset: 24 19 | bitWidth: 7 20 | VARIANT: 21 | description: Implementation defined 22 | bitOffset: 20 23 | bitWidth: 4 24 | ARCHITECTURE: 25 | description: This field defines the architecture 26 | bitOffset: 16 27 | bitWidth: 4 28 | PARTNO: 29 | description: Implementation defined. 30 | bitOffset: 4 31 | bitWidth: 12 32 | REVISION: 33 | description: Implementation defined. 34 | bitOffset: 0 35 | bitWidth: 4 36 | 37 | CPUID: 38 | Base: 39 | IMPLEMENTER: 40 | ARM: [0x41, "ARM Limited"] 41 | ARCHITECTURE: 42 | ARMv6M: [0xC, "ARMv6-M"] 43 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/cpuid_v6.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv6-M Architecture Reference Manual issue C 2 | 3 | _add: 4 | CPUID: 5 | description: CPUID 6 | baseAddress: 0xE000ED00 7 | addressBlock: 8 | offset: 0x0 9 | size: 4 10 | registers: 11 | Base: 12 | description: Provides identification information for the processor 13 | addressOffset: 0x0 14 | access: read-only 15 | fields: 16 | IMPLEMENTER: 17 | description: This field defines the implementer 18 | bitOffset: 24 19 | bitWidth: 7 20 | VARIANT: 21 | description: Implementation defined 22 | bitOffset: 20 23 | bitWidth: 4 24 | ARCHITECTURE: 25 | description: This field defines the architecture 26 | bitOffset: 16 27 | bitWidth: 4 28 | PARTNO: 29 | description: Implementation defined. 30 | bitOffset: 4 31 | bitWidth: 12 32 | REVISION: 33 | description: Implementation defined. 34 | bitOffset: 0 35 | bitWidth: 4 36 | 37 | CPUID: 38 | Base: 39 | IMPLEMENTER: 40 | ARM: [0x41, "ARM Limited"] 41 | ARCHITECTURE: 42 | ARMv6M: [0xC, "ARMv6-M"] 43 | -------------------------------------------------------------------------------- /.github/workflows/cargo-make.yaml: -------------------------------------------------------------------------------- 1 | name: Cargo Make 2 | 3 | on: 4 | push: 5 | branches: 6 | - master 7 | pull_request: 8 | merge_group: 9 | 10 | jobs: 11 | cargo_make: 12 | name: Cargo Make 13 | runs-on: ubuntu-latest 14 | 15 | env: 16 | CRATES: py32f0 17 | CARGO_INCREMENTAL: 0 18 | SVDTOOLS: svdtools 19 | 20 | steps: 21 | - name: Checkout code 22 | uses: actions/checkout@v3 23 | 24 | - name: Install Rust 25 | uses: dtolnay/rust-toolchain@stable 26 | with: 27 | components: rustfmt 28 | 29 | - name: Install cargo-make 30 | run: | 31 | wget https://github.com/sagiegurari/cargo-make/releases/download/0.36.8/cargo-make-v0.36.8-x86_64-unknown-linux-gnu.zip 32 | unzip cargo-make-*.zip 33 | mv cargo-make*/cargo-make $HOME/.cargo/bin 34 | 35 | - name: Create working crate 36 | run: cargo make crates 37 | 38 | - name: Install tools 39 | run: cargo make install 40 | 41 | - name: Patch SVDs 42 | run: cargo make patch 43 | 44 | - name: Build PACs 45 | run: cargo make svd2rust 46 | 47 | - name: Format PACs 48 | run: cargo make form 49 | 50 | - name: Check PACs 51 | run: cargo make check 52 | 53 | - name: Clean up 54 | run: cargo make clean 55 | -------------------------------------------------------------------------------- /peripherals/comp/comp_f002b.yaml: -------------------------------------------------------------------------------- 1 | COMP?: 2 | CSR: 3 | _modify: 4 | COMP_EN: 5 | name: EN 6 | COMP_OUT: 7 | name: VALUE 8 | EN: 9 | Disabled: [0, "Comparator 1 disabled"] 10 | Enabled: [1, "Comparator 1 enabled"] 11 | POLARITY: 12 | NotInverted: [0, "Output is not inverted"] 13 | Inverted: [1, "Output is inverted"] 14 | VALUE: 15 | _read: 16 | Low: [0, "Comparator output is low"] 17 | High: [1, "Comparator output is high"] 18 | FR: 19 | _modify: 20 | FLTEN: 21 | name: FLTEN* 22 | Disabled: [0, "Comparator digital filter disabled"] 23 | Enabled: [1, "Comparator digital filter enabled"] 24 | FLTCNT: 25 | name: FLTCNT* 26 | value: [0, 0xFFFF] 27 | 28 | COMP1: 29 | CSR: 30 | INNSEL: 31 | PB0: [0, "PB0 connected to inverting input"] 32 | PB1: [1, "PB1 connected to inverting input"] 33 | WINMODE: 34 | Disabled: [0, "COMP1 non-inverting input is connected to COMP1_INP"] 35 | Enabled: [1, "COMP1 non-inverting input is connected to COMP2_INP"] 36 | 37 | COMP2: 38 | CSR: 39 | INMSEL: 40 | PA4: [0, "PA4 connected to inverting input"] 41 | PA3: [1, "PA3 connected to inverting input"] 42 | INPSEL: 43 | PA3: [0, "PA3 connected to non-inverting input"] 44 | VRefCmp: [1, "VRef comp"] 45 | -------------------------------------------------------------------------------- /CHANGELOG.md: -------------------------------------------------------------------------------- 1 | # Change Log 2 | 3 | All notable changes to this project will be documented in this file. 4 | 5 | ## v0.2.1 2025-01-28 6 | 7 | ### Added 8 | 9 | - Added array access to timer CCR registers 10 | - Added py32f040 device 11 | - `scripts/README.md` to show usage of scripts 12 | - modified scripts to handle `bitRange` vs `bitOffset` and `bitWidth` usage in svd files 13 | 14 | ### Changed 15 | 16 | - Renamed field `DBG_TIM14_STOP` to `DBG_TIMER14_STOP` in `DBG` peripheral for py32f002b to make it consistent with other devices 17 | 18 | ### Removed 19 | 20 | - Removed renaming of timer CCR registers 21 | 22 | ## v0.2.0 2024-12-28 23 | 24 | ### Added 25 | 26 | - Clustered DMA registers into channels 27 | - Added arrays to DMA registers 28 | - Add direct 8-bit access to USART data register 29 | 30 | ### Changed 31 | 32 | - Updated Repository url in `README.md` and `scripts/makecrates.py` 33 | - Renamed `DDF` field in spi CR1 register to `DFF` to match datasheet for device py32f002b 34 | - Updated form version from 0.10.0 to 0.12.1 35 | - Updated svdtools version from 0.3.0 to 0.3.14 36 | 37 | ## v0.1.1 2024-10-10 38 | 39 | ## V0.1.0 2024-09-27 40 | 41 | ## v0.0.1 2023-06-10 42 | 43 | - Original Release 44 | 45 | The format is based on [Keep a Changelog](http://keepachangelog.com/) 46 | and this project adheres to [Semantic Versioning](http://semver.org/). 47 | -------------------------------------------------------------------------------- /devices/py32f040.yaml: -------------------------------------------------------------------------------- 1 | _svd: ../svd/py32f040.svd 2 | 3 | "SPI*": 4 | _include: 5 | - common_patches/spi_dr8.yaml 6 | 7 | "USART*": 8 | _include: 9 | - common_patches/usart_dr8.yaml 10 | - common_patches/usart_f040_rename.yaml 11 | 12 | "DMA, DMA[12]": 13 | _include: 14 | - common_patches/dma_cluster.yaml 15 | 16 | "FLASH": 17 | _include: 18 | - common_patches/flash_f040_rename.yaml 19 | 20 | "ADC": 21 | _include: 22 | - common_patches/adc_rw.yaml 23 | 24 | "RTC": 25 | _include: 26 | - common_patches/rtc_040_renames.yaml 27 | 28 | _include: 29 | - ../peripherals/flash/flash_f040.yaml 30 | - ../peripherals/pwr/pwr_f040.yaml 31 | - ../peripherals/rcc/rcc_f040.yaml 32 | - ../peripherals/gpio/gpio_f0.yaml 33 | - ../peripherals/syscfg/syscfg_f040.yaml 34 | - ../peripherals/dma/dma_f0.yaml 35 | - ../peripherals/exti/exti_f0.yaml 36 | - ../peripherals/crc/crc_f0.yaml 37 | - ../peripherals/adc/adc_f040.yaml 38 | - ../peripherals/comp/comp_f040.yaml 39 | - ../peripherals/lcd/lcd_f0.yaml 40 | - ../peripherals/tim/tim_f040.yaml 41 | - ../peripherals/lptim/lptim_f0.yaml 42 | - ../peripherals/iwdg/iwdg_f0.yaml 43 | - ../peripherals/wwdg/wwdg_f0.yaml 44 | - ../peripherals/rtc/rtc_f0.yaml 45 | - ../peripherals/i2c/i2c_f040.yaml 46 | - ../peripherals/usart/usart_f0.yaml 47 | - ../peripherals/spi/spi_f040.yaml 48 | - ../peripherals/dbg/dbg_f0.yaml 49 | -------------------------------------------------------------------------------- /scripts/htmlcomparesvdall.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | set -euxo pipefail 3 | 4 | mkdir -p html/py32f/py32f0 5 | python3 scripts/htmlcomparesvd.py html/py32f/py32f0 svd/py32f0*.svd.patched 6 | 7 | 8 | cat > html/comparisons.html < 10 | 11 | 12 | 13 | py32-rs Peripheral Comparisons 14 | 15 | 16 | 17 | 18 | 19 | 31 | 32 |

Device families

33 | 36 | 37 | 38 | EOF 39 | -------------------------------------------------------------------------------- /peripherals/pwr/pwr_f002a.yaml: -------------------------------------------------------------------------------- 1 | PWR: 2 | CR1: 3 | _modify: 4 | LPR: 5 | name: LPRUN 6 | LPRUN: 7 | MainMode: [0, "Voltage regulator in Main mode in Low-power run mode"] 8 | LowPowerMode: [1, "Voltage regulator in low-power mode in Low-power run mode"] 9 | HSION_CTRL: 10 | WaiteMR: [0, "Enable HSI after MR is stable"] 11 | WakeOnVR: [1, "Enable HSI when VR is on (enable HSI immediately when wakeup)"] 12 | SRAM_RETV: 13 | V0_9: [3, "Supply voltage 0.9 V for SRAM"] 14 | V1_x: [4, "Supply voltage 1.0 or 1.2 V (depends on VOS) for SRAM"] 15 | FLS_SLPTIME: 16 | FiveMicroSec: [0, "Flash wait 5 us after wakeup from stop mode"] 17 | TwoMicroSec: [1, "Flash wait 2 us after wakeup from stop mode"] 18 | ThreeMicroSec: [2, "Flash wait 3 us after wakeup from stop mode"] 19 | ExcuteFromSRAM: [3, "Excute program from SRAM after wakeup from stop mode"] 20 | MRRDY_TIME: 21 | TwoMicroSec: [0, "MR ready after 2 us"] 22 | ThreeMicroSec: [1, "MR ready after 3 us"] 23 | FourMicroSec: [2, "MR ready after 4 us"] 24 | FiveMicroSec: [3, "MR ready after 5 us"] 25 | VOS: 26 | V1_2: [0, "1.2 V (range 1)"] 27 | V1_0: [1, "1.0 V (range 2)"] 28 | DBP: 29 | Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"] 30 | Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"] 31 | BIAS_CR_SEL: 32 | FactoryConfig: [0, "Bias config from factory config bytes"] 33 | BiasCR: [1, "Bias config from BIAS_CR register"] 34 | BIAS_CR: 35 | [0, 15] -------------------------------------------------------------------------------- /peripherals/dbg/dbg_f0.yaml: -------------------------------------------------------------------------------- 1 | _modify: 2 | DBGMCU: 3 | name: DBG 4 | 5 | DBG: 6 | IDCODE: 7 | _add: 8 | CODE: 9 | description: DBG ID code register 10 | bitOffset: 0 11 | bitWidth: 32 12 | CR: 13 | DBG_STOP: 14 | Disabled: [0, "Debug Stop Mode Disabled"] 15 | Enabled: [1, "Debug Stop Mode Enabled"] 16 | APB_FZ1: 17 | DBG_IWDG_STOP: 18 | Continue: [0, "The independent watchdog counter clock continues even if the core is halted"] 19 | Stop: [1, "The independent watchdog counter clock is stopped when the core is halted"] 20 | DBG_WWDG_STOP: 21 | Continue: [0, "The window watchdog counter clock continues even if the core is halted"] 22 | Stop: [1, "The window watchdog counter clock is stopped when the core is halted"] 23 | DBG_RTC_STOP: 24 | Continue: [0, "The clock of the RTC counter is fed even if the core is halted"] 25 | Stop: [1, "The clock of the RTC counter is stopped when the core is halted"] 26 | "DBG_TIM*_STOP": 27 | Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] 28 | Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] 29 | "DBG_LPTIM*_STOP": 30 | Continue: [ 0, "LPTIMx counter clock is fed even if the core is halted" ] 31 | Stop: [ 1, "LPTIMx counter clock is stopped when the core is halted" ] 32 | APB_FZ2: 33 | "DBG_TIM*_STOP": 34 | Continue: [ 0, "The counter clock of TIMx is fed even if the core is halted" ] 35 | Stop: [ 1, "The counter clock of TIMx is stopped when the core is halted" ] 36 | 37 | -------------------------------------------------------------------------------- /cortex_m/peripherals/scb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv6-M Architecture Reference Manual Issue C 2 | 3 | _add: 4 | SCB: 5 | description: System Control Block 6 | baseAddress: 0xE000ED00 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x90 10 | registers: 11 | CPUID: 12 | description: CPUID Base Register 13 | addressOffset: 0x0 14 | access: read-only 15 | ICSR: 16 | description: Interrupt Control and State Register 17 | addressOffset: 0x4 18 | access: read-write 19 | VTOR: 20 | description: Vector Table Offset Register 21 | addressOffset: 0x8 22 | access: read-write 23 | AIRCR: 24 | description: Application Interrupt and Reset Control regsiter 25 | addressOffset: 0xC 26 | access: read-write 27 | SCR: 28 | description: System Control Register 29 | addressOffset: 0x10 30 | access: read-write 31 | CCR: 32 | description: Configuration and Control Register 33 | addressOffset: 0x14 34 | access: read-only 35 | SHPR2: 36 | description: System Handler Priority Register 2 37 | addressOffset: 0x1C 38 | access: read-write 39 | SHPR3: 40 | description: System Handler Priority Register 3 41 | addressOffset: 0x20 42 | access: read-write 43 | SHCSR: 44 | description: System Handler Control and State Register 45 | addressOffset: 0x24 46 | access: read-write 47 | DFSR: 48 | description: Debug Fault Status Register 49 | addressOffset: 0x30 50 | access: read-write 51 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/scb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | SCB: 5 | description: System Control Block 6 | baseAddress: 0xE000ED00 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x90 10 | registers: 11 | CPUID: 12 | description: CPUID Base register 13 | addressOffset: 0x0 14 | access: read-only 15 | ICSR: 16 | description: Interrupt Control and State register 17 | addressOffset: 0x4 18 | access: read-write 19 | VTOR: 20 | description: Vector Table Offset register 21 | addressOffset: 0x8 22 | access: read-write 23 | AIRCR: 24 | description: Application Interrupt and Reset Control regsiter 25 | addressOffset: 0xC 26 | access: read-write 27 | SCR: 28 | description: System Control register 29 | addressOffset: 0x10 30 | access: read-write 31 | CCR: 32 | description: Configuration and Control register 33 | addressOffset: 0x14 34 | access: read-only 35 | SHPR2: 36 | description: System Handler Priority Register 2 37 | addressOffset: 0x1C 38 | access: read-write 39 | SHPR3: 40 | description: System Handler Priority Register 3 41 | addressOffset: 0x20 42 | access: read-write 43 | SHCSR: 44 | description: System Handler Control and State Register 45 | addressOffset: 0x24 46 | access: read-write 47 | DFSR: 48 | description: Debug Fault Status Register 49 | addressOffset: 0x30 50 | access: read-write 51 | -------------------------------------------------------------------------------- /cortex_m/peripherals/mpu.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | MPU: 5 | description: Memory Protection Unit 6 | baseAddress: 0xE000ED90 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x60 10 | registers: 11 | TYPE: 12 | description: MPU Type Register 13 | addressOffset: 0x0 14 | access: read-only 15 | CTRL: 16 | description: MPU Control Register 17 | addressOffset: 0x4 18 | access: read-write 19 | RNR: 20 | description: MPU Region Number Register 21 | addressOffset: 0x8 22 | access: read-write 23 | RBAR: 24 | description: MPU Region Base Address Register 25 | addressOffset: 0xC 26 | access: read-write 27 | RASR: 28 | description: MPU Region Attribute and Size Register 29 | addressOffset: 0x10 30 | access: read-write 31 | RBAR_A1: 32 | description: Alias 1 of RBAR 33 | addressOffset: 0x14 34 | access: read-write 35 | RASR_A1: 36 | description: Alias 1 of RSAR 37 | addressOffset: 0x18 38 | acces: read-write 39 | RBAR_A2: 40 | description: Alias 2 of RBAR 41 | addressOffset: 0x1C 42 | access: read-write 43 | RASR_A2: 44 | description: Alias 2 of RSAR 45 | addressOffset: 0x20 46 | acces: read-write 47 | RBAR_A3: 48 | description: Alias 3 of RBAR 49 | addressOffset: 0x24 50 | access: read-write 51 | RASR_A3: 52 | description: Alias 3 of RSAR 53 | addressOffset: 0x28 54 | acces: read-write 55 | -------------------------------------------------------------------------------- /peripherals/led/led_f0.yaml: -------------------------------------------------------------------------------- 1 | LED: 2 | CR: 3 | LEDON: 4 | Disabled: [0, "Disable LED controller"] 5 | Enabled: [1, "Enable LED controller"] 6 | LED_COM_SEL: 7 | OneDigit: [0, "One digit"] 8 | TwoDigits: [1, "Two digits sequentially"] 9 | ThreeDigits: [2, "Three digits sequentially"] 10 | FourDigits: [3, "Four digits sequentially"] 11 | IE: 12 | Disabled: [0, "Disable interrupt"] 13 | Enabled: [1, "Enable interrupt"] 14 | EHS: 15 | NoComOutput: [0, "No COM output"] 16 | HighSink: [1, "LED COM output high sink, driven level configured by GPIO_OSPEEDR"] 17 | PR: 18 | PR: [0, 255] 19 | TR: 20 | T1: [0, 255] 21 | T2: [0, 255] 22 | DR?: 23 | DATA?_A: 24 | Off: [0, "DATAx seg A off"] 25 | On: [1, "DATAx seg A on"] 26 | DATA?_B: 27 | Off: [0, "DATAx seg B off"] 28 | On: [1, "DATAx seg B on"] 29 | DATA?_C: 30 | Off: [0, "DATAx seg C off"] 31 | On: [1, "DATAx seg C on"] 32 | DATA?_D: 33 | Off: [0, "DATAx seg D off"] 34 | On: [1, "DATAx seg D on"] 35 | DATA?_E: 36 | Off: [0, "DATAx seg E off"] 37 | On: [1, "DATAx seg E on"] 38 | DATA?_F: 39 | Off: [0, "DATAx seg F off"] 40 | On: [1, "DATAx seg F on"] 41 | DATA?_G: 42 | Off: [0, "DATAx seg G off"] 43 | On: [1, "DATAx seg G on"] 44 | DATA?_DP: 45 | Off: [0, "DATAx seg DP off"] 46 | On: [1, "DATAx seg DP on"] 47 | IR: 48 | FLAG: 49 | _read: 50 | NotComplete: [0, "Not complete one digit lit"] 51 | Completed: [1, "Complete one digit lit"] 52 | _write: 53 | Clear: [1, "Clear interrupt flag"] -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/mpu.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | MPU: 5 | description: Memory Protection Unit 6 | baseAddress: 0xE000ED90 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x60 10 | registers: 11 | TYPE: 12 | description: MPU Type register 13 | addressOffset: 0x0 14 | access: read-only 15 | CTRL: 16 | description: MPU Control register 17 | addressOffset: 0x4 18 | access: read-write 19 | RNR: 20 | description: MPU Region Number register 21 | addressOffset: 0x8 22 | access: read-write 23 | RBAR: 24 | description: MPU Region Base Address register 25 | addressOffset: 0xC 26 | access: read-write 27 | RASR: 28 | description: MPU Region Attribute and Size register 29 | addressOffset: 0x10 30 | access: read-write 31 | RBAR_A1: 32 | description: Alias 1 of RBAR 33 | addressOffset: 0x14 34 | access: read-write 35 | RASR_A1: 36 | description: Alias 1 of RSAR 37 | addressOffset: 0x18 38 | acces: read-write 39 | RBAR_A2: 40 | description: Alias 2 of RBAR 41 | addressOffset: 0x1C 42 | access: read-write 43 | RASR_A2: 44 | description: Alias 2 of RSAR 45 | addressOffset: 0x20 46 | acces: read-write 47 | RBAR_A3: 48 | description: Alias 3 of RBAR 49 | addressOffset: 0x24 50 | access: read-write 51 | RASR_A3: 52 | description: Alias 3 of RSAR 53 | addressOffset: 0x28 54 | acces: read-write 55 | -------------------------------------------------------------------------------- /scripts/interrupts.py: -------------------------------------------------------------------------------- 1 | import os 2 | import argparse 3 | import xml.etree.ElementTree as ET 4 | 5 | 6 | def parse_device(svdfile): 7 | interrupts = {} 8 | tree = ET.parse(svdfile) 9 | dname = tree.find("name").text 10 | for ptag in tree.iter('peripheral'): 11 | pname = ptag.find('name').text 12 | for itag in ptag.iter('interrupt'): 13 | name = itag.find('name').text 14 | value = itag.find('value').text 15 | desc = itag.find('description').text.replace("\n", " ") 16 | interrupts[int(value)] = {"name": name, 17 | "desc": desc, 18 | "pname": pname} 19 | return dname, interrupts 20 | 21 | 22 | def main(): 23 | parser = argparse.ArgumentParser() 24 | parser.add_argument("outdir", help="directory to write files to") 25 | parser.add_argument("svdfiles", nargs="*", help="List of SVD files") 26 | args = parser.parse_args() 27 | devices = {} 28 | for f in args.svdfiles: 29 | name, interrupts = parse_device(f) 30 | devices[name] = interrupts 31 | missing = set() 32 | with open(os.path.join(args.outdir, name), "w") as f: 33 | lastint = -1 34 | for val in sorted(interrupts.keys()): 35 | for v in range(lastint+1, val): 36 | missing.add(v) 37 | lastint = val 38 | i = interrupts[val] 39 | f.write("{} {}: {} (in {})\n".format( 40 | val, i["name"], i["desc"], i["pname"])) 41 | f.write("\nGaps: {}\n" 42 | .format(", ".join(str(x) for x in sorted(missing)))) 43 | 44 | 45 | if __name__ == "__main__": 46 | main() 47 | -------------------------------------------------------------------------------- /scripts/tool_install.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | set -euo pipefail 4 | 5 | FORM_VERSION="${FORM_VERSION:-v0.12.1}" 6 | SVDTOOLS_VERSION="${SVDTOOLS_VERSION:-v0.3.14}" 7 | SVD2RUST_VERSION="${SVD2RUST_VERSION:-v0.28.0}" 8 | SVD2HTML_VERSION="${SVD2HTML_VERSION:-v0.1.3}" 9 | 10 | case "${1:-}" in 11 | form) 12 | form="${2:-$FORM_VERSION}" 13 | ;; 14 | svdtools) 15 | svdtools="${2:-$SVDTOOLS_VERSION}" 16 | ;; 17 | svd2rust) 18 | svd2rust="${2:-$SVD2RUST_VERSION}" 19 | ;; 20 | svd2html) 21 | svd2html="${2:-$SVD2HTML_VERSION}" 22 | ;; 23 | *) 24 | form=$FORM_VERSION 25 | svdtools=$SVDTOOLS_VERSION 26 | svd2rust=$SVD2RUST_VERSION 27 | svd2html=$SVD2HTML_VERSION 28 | echo "Install default versions" 29 | ;; 30 | esac 31 | 32 | if [ "${form:-}" ]; then 33 | echo "form = ${form}" 34 | curl -sSfL https://github.com/djmcgill/form/releases/download/$form/form-x86_64-unknown-linux-gnu.gz | gzip -d - > ~/.cargo/bin/form 35 | chmod +x ~/.cargo/bin/form 36 | fi 37 | 38 | if [ "${svdtools:-}" ]; then 39 | echo "svdtools = ${svdtools}" 40 | curl -sSfL https://github.com/rust-embedded/svdtools/releases/download/$svdtools/svdtools-x86_64-unknown-linux-gnu.gz | gzip -d - > ~/.cargo/bin/svdtools 41 | chmod +x ~/.cargo/bin/svdtools 42 | fi 43 | 44 | if [ "${svd2rust:-}" ]; then 45 | echo "svd2rust = ${svd2rust}" 46 | curl -sSfL https://github.com/rust-embedded/svd2rust/releases/download/$svd2rust/svd2rust-x86_64-unknown-linux-gnu.gz | gzip -d - > ~/.cargo/bin/svd2rust 47 | chmod +x ~/.cargo/bin/svd2rust 48 | fi 49 | 50 | if [ "${svd2html:-}" ]; then 51 | echo "svd2html = ${svd2html}" 52 | curl -sSfL https://github.com/burrbull/svd2html/releases/download/$svd2html/svd2html-x86_64-unknown-linux-gnu.gz | gzip -d - > ~/.cargo/bin/svd2html 53 | chmod +x ~/.cargo/bin/svd2html 54 | fi 55 | -------------------------------------------------------------------------------- /devices/common_patches/pwr_f002a.yaml: -------------------------------------------------------------------------------- 1 | _add: 2 | PWR: 3 | description: "Power control" 4 | baseAddress: 0x40007000 5 | addressBlock: 6 | offset: 0x0 7 | size: 0x400 8 | usage: registers 9 | registers: 10 | CR1: 11 | description: "Power control register 1" 12 | addressOffset: 0x0 13 | size: 0x20 14 | access: read-write 15 | resetValue: 0x00030000 16 | CR2: 17 | description: "Power control register 2" 18 | addressOffset: 0x4 19 | size: 0x20 20 | access: read-write 21 | resetValue: 0x00000500 22 | SR: 23 | description: "Power status register" 24 | addressOffset: 0x14 25 | size: 0x20 26 | access: read-only 27 | resetValue: 0x00000000 28 | 29 | PWR: 30 | CR1: 31 | _add: 32 | BIAS_CR: 33 | description: "MR Bias current" 34 | bitOffset: 0 35 | bitWidth: 4 36 | BIAS_CR_SEL: 37 | description: "MR Bias current selection" 38 | bitOffset: 4 39 | bitWidth: 1 40 | DBP: 41 | description: "Disable backup domain write protection" 42 | bitOffset: 8 43 | bitWidth: 1 44 | VOS: 45 | description: "Voltage scaling range selection" 46 | bitOffset: 9 47 | bitWidth: 1 48 | MRRDY_TIME: 49 | description: "Time selection wakeup from LP to VR" 50 | bitOffset: 10 51 | bitWidth: 2 52 | FLS_SLPTIME: 53 | description: "Flash wait time after wakeup from the stop mode" 54 | bitOffset: 12 55 | bitWidth: 2 56 | LPRUN: 57 | description: "Low-power run" 58 | bitOffset: 14 59 | bitWidth: 1 60 | SRAM_RETV: 61 | description: "SRAM retention voltage control" 62 | bitOffset: 16 63 | bitWidth: 3 64 | HSION_CTRL: 65 | description: "HSI open time control" 66 | bitOffset: 19 67 | bitWidth: 1 -------------------------------------------------------------------------------- /scripts/makehtml.index.template.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | py32-rs Device Coverage 7 | 8 | 9 | 10 | 11 | 12 | 13 | 25 | 26 |
27 |
28 |
29 |
30 |

Available Devices

31 |
32 |
33 |
34 | {% for name, device in devices|dictsort %} 35 |
36 |
37 |
38 | {{ device.name }} 39 | (svd): 40 | {{ device.fields_documented }}/{{ device.fields_total }} fields 41 | documented 42 |
43 |
44 |
45 |
46 | {% set width = (100 * device.fields_documented) / device.fields_total %} 47 |
48 |
49 |
50 |
51 | {% endfor %} 52 |
53 | -------------------------------------------------------------------------------- /peripherals/gpio/gpio_f0.yaml: -------------------------------------------------------------------------------- 1 | "GPIO*": 2 | MODER: 3 | "MODE*": 4 | Input: [0, "Input mode"] 5 | Output: [1, "General purpose output mode"] 6 | Alternate: [2, "Alternate function mode"] 7 | Analog: [3, "Analog mode"] 8 | OTYPER: 9 | "OT*": 10 | PushPull: [0, "Output push-pull (reset state)"] 11 | OpenDrain: [1, "Output open-drain"] 12 | OSPEEDR: 13 | "OSPEED*": 14 | LowSpeed: [0, "Low speed"] 15 | MediumSpeed: [1, "Medium speed"] 16 | HighSpeed: [2, "High speed"] 17 | VeryHighSpeed: [3, "Very high speed"] 18 | PUPDR: 19 | "PUPD*": 20 | Floating: [0, "No pull-up, pull-down"] 21 | PullUp: [1, "Pull-up"] 22 | PullDown: [2, "Pull-down"] 23 | IDR: 24 | "ID*": 25 | High: [1, "Input is logic high"] 26 | Low: [0, "Input is logic low"] 27 | ODR: 28 | "OD*": 29 | High: [1, "Set output to logic high"] 30 | Low: [0, "Set output to logic low"] 31 | BSRR: 32 | "BR*": 33 | _write: 34 | Reset: [1, "Resets the corresponding ODx bit"] 35 | "BS*": 36 | _write: 37 | Set: [1, "Sets the corresponding ODx bit"] 38 | BRR: 39 | "BR[0-9],BR1[0-5]": 40 | _write: 41 | NoAction: [0, "No action on the corresponding ODx bit"] 42 | Reset: [1, "Reset the ODx bit"] 43 | LCKR: 44 | "LCK[0-9],LCK1[0-5]": 45 | Unlocked: [0, "Port configuration not locked"] 46 | Locked: [1, "Port configuration locked"] 47 | "LCKK": 48 | NotActive: [0, "Port configuration lock key not active"] 49 | Active: [1, "Port configuration lock key active"] 50 | "AFR[LH]": 51 | "AFSEL*": 52 | AF0: [0, "AF0"] 53 | AF1: [1, "AF1"] 54 | AF2: [2, "AF2"] 55 | AF3: [3, "AF3"] 56 | AF4: [4, "AF4"] 57 | AF5: [5, "AF5"] 58 | AF6: [6, "AF6"] 59 | AF7: [7, "AF7"] 60 | AF8: [8, "AF8"] 61 | AF9: [9, "AF9"] 62 | AF10: [10, "AF10"] 63 | AF11: [11, "AF11"] 64 | AF12: [12, "AF12"] 65 | AF13: [13, "AF13"] 66 | AF14: [14, "AF14"] 67 | AF15: [15, "AF15"] 68 | -------------------------------------------------------------------------------- /peripherals/pwr/pwr_f040.yaml: -------------------------------------------------------------------------------- 1 | PWR: 2 | CR1: 3 | _modify: 4 | LPR: 5 | name: LPRUN 6 | LPRUN: 7 | MainMode: [0, "Voltage regulator in Main mode in Low-power run mode"] 8 | LowPowerMode: [1, "Voltage regulator in low-power mode in Low-power run mode"] 9 | HSION_CTRL: 10 | WaiteMR: [0, "Enable HSI after MR is stable"] 11 | WakeOnVR: [1, "Enable HSI when VR is on (enable HSI immediately when wakeup)"] 12 | VOS: 13 | V1_2: [0, "1.2 V (range 1)"] 14 | V1_0: [1, "1.0 V (range 2)"] 15 | DBP: 16 | Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"] 17 | Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"] 18 | BIAS_CR_SEL: 19 | FactoryConfig: [0, "Bias config from factory config bytes"] 20 | BiasCR: [1, "Bias config from BIAS_CR register"] 21 | BIAS_CR: 22 | [0, 15] 23 | CR2: 24 | FLT_TIME: 25 | T30us: [0, "Filter time is about 30 us"] 26 | T60us: [1, "Filter time is about 60 us"] 27 | T120us: [2, "Filter time is about 120 us"] 28 | T480us: [3, "Filter time is about 480 us"] 29 | T1_92ms: [4, "Filter time is about 1.92 ms"] 30 | T3_8ms: [5, "Filter time is about 3.8 ms"] 31 | T30_7ms: [6, "Filter time is about 30.7 ms"] 32 | FLTEN: 33 | Disabled: [0, "Digital filter disabled"] 34 | Enabled: [1, "Digital filter enabled"] 35 | PVDT: 36 | V1_8: [0, "1.8 V"] 37 | V2_0: [1, "2.0 V"] 38 | V2_2: [2, "2.2 V"] 39 | V2_4: [3, "2.4 V"] 40 | V2_6: [4, "2.6 V"] 41 | V2_8: [5, "2.8 V"] 42 | V3_0: [6, "3.0 V"] 43 | V3_2: [7, "3.2 V"] 44 | _modify: 45 | SRCSEL: 46 | name: PVD_SRCSEL 47 | PVD_SRCSEL: 48 | Vcc: [0, "VCC as detector source"] 49 | PB7: [1, "PB7 pin as detector source"] 50 | PVDE: 51 | Disabled: [0, "PVD Disabled"] 52 | Enabled: [1, "PVD Enabled"] 53 | SR: 54 | PVDO: 55 | _read: 56 | AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"] 57 | BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"] 58 | -------------------------------------------------------------------------------- /scripts/timer_hierarchy.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import xml.etree.ElementTree as ET 3 | import pprint 4 | import re 5 | 6 | from collections import defaultdict 7 | 8 | from svdtools import patch 9 | 10 | 11 | def iter_peripherals(tree, pspec): 12 | for ptag in tree.iter('peripheral'): 13 | if re.match(pspec, ptag.find('name').text): 14 | yield ptag 15 | 16 | 17 | def iter_registers(ptag): 18 | for rtag in ptag.iter('register'): 19 | yield rtag 20 | 21 | 22 | def iter_fields(rtag): 23 | for ftag in rtag.iter('field'): 24 | yield ftag 25 | 26 | 27 | def main(svdfile): 28 | tree = ET.parse(svdfile) 29 | field_tims = defaultdict(set) 30 | for ptag in iter_peripherals(tree, "TIM*"): 31 | pname = ptag.find('name').text 32 | for rtag in iter_registers(ptag): 33 | rname = rtag.find('name').text 34 | for ftag in iter_fields(rtag): 35 | fname = ftag.find('name').text 36 | rfname = "{}.{}".format(rname, fname) 37 | field_tims[rfname].add(pname) 38 | for ptag in tree.iter('peripheral'): 39 | pname = ptag.find('name').text 40 | if patch.matchname(pname, "TIM*"): 41 | if "derivedFrom" in ptag.attrib: 42 | derives = ptag.attrib["derivedFrom"] 43 | for _, tims in field_tims.items(): 44 | if derives in tims: 45 | tims.add(pname) 46 | tims_field = defaultdict(lambda: defaultdict(list)) 47 | for field, timers in field_tims.items(): 48 | rname, fname = field.split(".") 49 | tims = list(timers) 50 | tims.sort(key=lambda x: int(x[3:])) 51 | tims_field[tuple(tims)][rname].append(fname) 52 | tf = list(tims_field.items()) 53 | tf.sort(key=lambda x: len(x[0])) 54 | for tims, regs in tf: 55 | print("\n" + ", ".join(tims) + ":") 56 | for reg in sorted(list(regs.keys())): 57 | print(" ", reg + ":", " ".join(sorted(regs[reg]))) 58 | 59 | 60 | if __name__ == "__main__": 61 | parser = argparse.ArgumentParser() 62 | parser.add_argument("svdfile") 63 | args = parser.parse_args() 64 | main(args.svdfile) 65 | -------------------------------------------------------------------------------- /peripherals/rtc/rtc_f0.yaml: -------------------------------------------------------------------------------- 1 | RTC: 2 | CRH: 3 | OWIE: 4 | Disabled: [0, "Overflow interrupt is masked"] 5 | Enabled: [1, "Overflow interrupt is enabled"] 6 | ALRIE: 7 | Disabled: [0, "Alarm interrupt is masked"] 8 | Enabled: [1, "Alarm interrupt is enabled"] 9 | SECIE: 10 | Disabled: [0, "Second interrupt is masked"] 11 | Enabled: [1, "Second interrupt is enabled"] 12 | CRL: 13 | RTOFF: 14 | Enabled: [0, "Last write operation on RTC registers is still ongoing"] 15 | Disabled: [1, "Last write operation on RTC registers terminated"] 16 | CNF: 17 | Exit: [0, "Exit configuration mode (start update of RTC registers)"] 18 | Enter: [1, "Enter configuration mode"] 19 | RSF: 20 | _read: 21 | NotSynchronized: [0, "Registers not yet synchronized"] 22 | Synchronized: [1, "Registers synchronized"] 23 | _W0C: 24 | Clear: [0, "Clear flag"] 25 | OWF: 26 | _read: 27 | NoOverflow: [0, "Overflow not detected"] 28 | Overflow: [1, "32-bit programmable counter overflow occurred"] 29 | _W0C: 30 | Clear: [0, "Clear flag"] 31 | ALRF: 32 | _read: 33 | NoAlarm: [0, "Alarm not detected"] 34 | Alarm: [1, "Alarm detected"] 35 | _W0C: 36 | Clear: [0, "Clear flag"] 37 | SECF: 38 | _read: 39 | NoPrescalerOverflow: [0, "Second flag condition not met"] 40 | PrescalerOverflow: [1, "Second flag condition met"] 41 | _W0C: 42 | Clear: [0, "Clear flag"] 43 | PRLH: 44 | PRLH: [0, 0xF] 45 | PRLL: 46 | PRLL: [0, 0xFFFF] 47 | DIVH: 48 | DIVH: [0, 0xF] 49 | DIVL: 50 | DIVL: [0, 0xFFFF] 51 | CNTH: 52 | CNTH: [0, 0xFFFF] 53 | CNTL: 54 | CNTL: [0, 0xFFFF] 55 | ALRH: 56 | ALRH: [0, 0xFFFF] 57 | ALRL: 58 | ALRL: [0, 0xFFFF] 59 | RTCCR: 60 | ASOS: 61 | Alarm: [0, "RTC Alarm pulse output selected"] 62 | Second: [1, "RTC Second pulse output selected"] 63 | ASOE: 64 | Disabled: [0, "Disabled"] 65 | Enabled: [1, "Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit"] 66 | CCO: 67 | Disabled: [0, "Calibration clock output disabled"] 68 | Enabled: [1, "Setting this bit output calibration clock (RTC clock / 64) on the pin"] 69 | CAL: [0, 121] 70 | -------------------------------------------------------------------------------- /cortex_m/peripherals/cpb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | CPB: 5 | description: Cache and branch predictor maintenance operations 6 | baseAddress: 0xE000EF50 7 | addressBlock: 8 | offset: 0x0 9 | size: 52 10 | registers: 11 | ICIALLU: 12 | description: I-cache invalidate all to PoU 13 | addressOffset: 0x0 14 | access: write-only 15 | ICIMVAU: 16 | description: I-cache invalidate by MVA to PoU 17 | addressOffset: 0x8 18 | access: write-only 19 | fields: 20 | MVA: 21 | description: Memory address 22 | bitOffset: 0 23 | bitWidth: 32 24 | DCIMVAC: 25 | description: D-cache invalidate by MVA to PoC 26 | addressOffset: 0xC 27 | access: write-only 28 | fields: 29 | MVA: 30 | description: Memory address 31 | bitOffset: 0 32 | bitWidth: 32 33 | DCISW: 34 | description: D-cache invaldiate by set-way 35 | addressOffset: 0x10 36 | access: write-only 37 | DCCMVAU: 38 | description: D-cache clean by MVA to PoU 39 | addressOffset: 0x14 40 | access: write-only 41 | fields: 42 | MVA: 43 | description: Memory address 44 | bitOffset: 0 45 | bitWidth: 32 46 | DCCMVAC: 47 | description: D-cache clean by MVA to PoC 48 | addressOffset: 0x18 49 | access: write-only 50 | fields: 51 | MVA: 52 | description: Memory address 53 | bitOffset: 0 54 | bitWidth: 32 55 | DCCSW: 56 | description: D-cache clean by set-way 57 | addressOffset: 0x1C 58 | access: write-only 59 | DCCIMVAC: 60 | description: D-cache clean and invalidate by MVA to PoC 61 | addressOffset: 0x20 62 | access: write-only 63 | fields: 64 | MVA: 65 | description: Memory address 66 | bitOffset: 0 67 | bitWidth: 32 68 | DCCISW: 69 | description: D-cache clean and invalidate by set-way 70 | addressOffset: 0x24 71 | access: write-only 72 | BPIALL: 73 | description: Branch predictor invalidate all 74 | addressOffset: 0x28 75 | access: write-only 76 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/cpb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | CPB: 5 | description: Cache and branch predictor maintenance operations 6 | baseAddress: 0xE000EF50 7 | addressBlock: 8 | offset: 0x0 9 | size: 52 10 | registers: 11 | ICIALLU: 12 | description: I-cache invalidate all to PoU 13 | addressOffset: 0x0 14 | access: write-only 15 | ICIMVAU: 16 | description: I-cache invalidate by MVA to PoU 17 | addressOffset: 0x8 18 | access: write-only 19 | fields: 20 | MVA: 21 | description: Memory address 22 | bitOffset: 0 23 | bitWidth: 32 24 | DCIMVAC: 25 | description: D-cache invalidate by MVA to PoC 26 | addressOffset: 0xC 27 | access: write-only 28 | fields: 29 | MVA: 30 | description: Memory address 31 | bitOffset: 0 32 | bitWidth: 32 33 | DCISW: 34 | description: D-cache invaldiate by set-way 35 | addressOffset: 0x10 36 | access: write-only 37 | DCCMVAU: 38 | description: D-cache clean by MVA to PoU 39 | addressOffset: 0x14 40 | access: write-only 41 | fields: 42 | MVA: 43 | description: Memory address 44 | bitOffset: 0 45 | bitWidth: 32 46 | DCCMVAC: 47 | description: D-cache clean by MVA to PoC 48 | addressOffset: 0x18 49 | access: write-only 50 | fields: 51 | MVA: 52 | description: Memory address 53 | bitOffset: 0 54 | bitWidth: 32 55 | DCCSW: 56 | description: D-cache clean by set-way 57 | addressOffset: 0x1C 58 | access: write-only 59 | DCCIMVAC: 60 | description: D-cache clean and invalidate by MVA to PoC 61 | addressOffset: 0x20 62 | access: write-only 63 | fields: 64 | MVA: 65 | description: Memory address 66 | bitOffset: 0 67 | bitWidth: 32 68 | DCCISW: 69 | description: D-cache clean and invalidate by set-way 70 | addressOffset: 0x24 71 | access: write-only 72 | BPIALL: 73 | description: Branch predictor invalidate all 74 | addressOffset: 0x28 75 | access: write-only 76 | -------------------------------------------------------------------------------- /peripherals/dma/dma_f0.yaml: -------------------------------------------------------------------------------- 1 | "DMA, DMA[12]": 2 | ISR: 3 | "TEIF*": 4 | NoError: [0, "No transfer error"] 5 | Error: [1, "A transfer error has occured"] 6 | "HTIF*": 7 | NotHalf: [0, "No half transfer event"] 8 | Half: [1, "A half transfer event has occured"] 9 | "TCIF*": 10 | NotComplete: [0, "No transfer complete event"] 11 | Complete: [1, "A transfer complete event has occured"] 12 | "GIF*": 13 | NoEvent: [0, "No transfer error, half event, complete event"] 14 | Event: [1, "A transfer error, half event or complete event has occured"] 15 | IFCR: 16 | "CTEIF*": 17 | Clear: [1, "Clears the TEIF flag in the ISR register"] 18 | "CHTIF*": 19 | Clear: [1, "Clears the HTIF flag in the ISR register"] 20 | "CTCIF*": 21 | Clear: [1, "Clears the TCIF flag in the ISR register"] 22 | "CGIF*": 23 | Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"] 24 | "CCR*": 25 | MEM2MEM: 26 | Disabled: [0, "Memory to memory mode disabled"] 27 | Enabled: [1, "Memory to memory mode enabled"] 28 | PL: 29 | Low: [0, "Low priority"] 30 | Medium: [1, "Medium priority"] 31 | High: [2, "High priority"] 32 | VeryHigh: [3, "Very high priority"] 33 | "[MP]SIZE": 34 | Bits8: [0, "8-bit size"] # or Byte 35 | Bits16: [1, "16-bit size"] # or HalfWord 36 | Bits32: [2, "32-bit size"] # or Word 37 | "[MP]INC": 38 | Disabled: [0, "Increment mode disabled"] 39 | Enabled: [1, "Increment mode enabled"] 40 | CIRC: 41 | Disabled: [0, "Circular buffer disabled"] 42 | Enabled: [1, "Circular buffer enabled"] 43 | DIR: 44 | FromPeripheral: [0, "Read from peripheral"] 45 | FromMemory: [1, "Read from memory"] 46 | TEIE: 47 | Disabled: [0, "Transfer Error interrupt disabled"] 48 | Enabled: [1, "Transfer Error interrupt enabled"] 49 | HTIE: 50 | Disabled: [0, "Half Transfer interrupt disabled"] 51 | Enabled: [1, "Half Transfer interrupt enabled"] 52 | TCIE: 53 | Disabled: [0, "Transfer Complete interrupt disabled"] 54 | Enabled: [1, "Transfer Complete interrupt enabled"] 55 | EN: 56 | Disabled: [0, "Channel disabled"] 57 | Enabled: [1, "Channel enabled"] 58 | "CNDTR*": 59 | NDT: [0, 0xFFFF] 60 | "CPAR?": 61 | PA: [0, 0xFFFFFFFF] 62 | "CMAR?": 63 | MA: [0, 0xFFFFFFFF] -------------------------------------------------------------------------------- /py32_part_table.yaml: -------------------------------------------------------------------------------- 1 | # This file contains a table of all supported PY32 microcontrollers. 2 | # 3 | # It lists them by family (which corresponds to a crate), 4 | # then by the "device" in that family (corresponds to an SVD file, 5 | # and to a module within each crate). 6 | # 7 | # For each device, there is a link to the product page and reference manual, 8 | # the reference manual ID, the title from the reference manual, 9 | # and a list of actual members of this family (without size/package codes). 10 | # 11 | # This data is used to generate more informative crate READMEs. 12 | 13 | py32f0: 14 | py32f002a: 15 | url: https://www.puyasemi.com/py32f002axilie629.html?tag=16#common 16 | rm: PY32F002A Reference manual 17 | rm_title: PY32F002A Reference manual 18 | rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU%20%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8/PY32F002A%20Reference%20manual%20v1.0_EN.pdf 19 | members: 20 | - PY32F002A 21 | py32f002b: 22 | url: https://www.puyasemi.com/py32f002bxilie429.html?tag=16#common 23 | rm: PY32F002B Reference manual 24 | rm_title: PY32F002B Reference manual 25 | rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU%20%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8/PY32F002B%20Reference%20manual%20v1.0_EN.pdf 26 | members: 27 | - PY32F002B 28 | py32f003: 29 | url: https://www.puyasemi.com/py32f003xilie.html?tag=16#common 30 | rm: PY32F003 Reference manual 31 | rm_title: PY32F003 Reference manual 32 | rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU%20%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8/PY32F003%20Reference%20manual%20v1.1_EN.pdf 33 | members: 34 | - PY32F003 35 | py32f030: 36 | url: https://www.puyasemi.com/py32f030xilie.html?tag=15#common 37 | rm: PY32F030 Reference manual 38 | rm_title: PY32F030 Reference manual 39 | rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU%20%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8/PY32F030%20Reference%20manual%20v1.3_EN.pdf 40 | members: 41 | - PY32F030 42 | py32f040: 43 | url: https://www.puyasemi.com/en/py32f040.html?tag=48#common 44 | rm: PY32F040 Reference manual 45 | rm_title: PY32F040 Reference manual 46 | rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU/PY32F040_Reference_Manual_V0.2.pdf 47 | members: 48 | - PY32F040 49 | -------------------------------------------------------------------------------- /peripherals/comp/comp_f040.yaml: -------------------------------------------------------------------------------- 1 | "COMP?": 2 | CSR: 3 | _modify: 4 | COMP_OUT: 5 | name: VALUE 6 | VALUE: 7 | _read: 8 | Low: [0, "Comparator output is low"] 9 | High: [1, "Comparator output is high"] 10 | PWRMODE: 11 | HighSpeed: [0, "High speed 250 ua"] 12 | MediumSpeed: [1, "Medium speed 5 ua"] 13 | HYST: 14 | No: [0, "no Comp1 hysteresis"] 15 | Yes: [1, "Comp1 hysteresis voltage approx 20mV"] 16 | POLARITY: 17 | NotInverted: [0, "Output is not inverted"] 18 | Inverted: [1, "Output is inverted"] 19 | WINMODE: 20 | Disabled: [0, ""] 21 | Enabled: [1, ""] 22 | INPSEL: 23 | Inp0: [0, "COMP1_INP0 from PC0"] 24 | Inp1: [1, "COMP1_INP1 from PC1"] 25 | Inp2: [2, "COMP1_INP2 from PC2"] 26 | Inp3: [3, "COMP1_INP3 from PC3"] 27 | Inp4: [4, "COMP1_INP4 from PA0"] 28 | Inp5: [5, "COMP1_INP5 from PA1"] 29 | Inp6: [6, "COMP1_INP6 from PA2"] 30 | Inp7: [7, "COMP1_INP7 from PA3"] 31 | Inp8: [8, "COMP1_INP8 from PA4"] 32 | Inp9: [9, "COMP1_INP9 from PA5"] 33 | Inp10: [10, "COMP1_INP10 from PA6"] 34 | Inp11: [11, "COMP1_INP11 from PA7"] 35 | Inp12: [12, "COMP1_INP12 from PB4"] 36 | Inp13: [13, "COMP1_INP13 from PB5"] 37 | Inp14: [14, "COMP1_INP14 from PB6"] 38 | INMSEL: 39 | Inm0: [0, "COMP1_INM0 from PA0"] 40 | Inm1: [1, "COMP1_INM1 from PA1"] 41 | Inm2: [2, "COMP1_INM2 from PA2"] 42 | Inm3: [3, "COMP1_INM3 from PA3"] 43 | Inm4: [4, "COMP1_INM4 from PA4"] 44 | Inm5: [5, "COMP1_INM5 from PA5"] 45 | Inm6: [6, "COMP1_INM6 from PA6"] 46 | Inm7: [7, "COMP1_INM7 from PA7"] 47 | Inm8: [8, "COMP1_INM8 from PC4"] 48 | Inm9: [9, "COMP1_INM9 from PC5"] 49 | Inm11: [10, "COMP1_INM11 from resistor voltage divider"] 50 | Inm12: [11, "COMP1_INM12 from TS_VIN"] 51 | Inm13: [12, "COMP1_INM13 from VREF1P2"] 52 | Inm14: [13, "COMP1_INM14 from VREFBUF"] 53 | Inm15: [14, "COMP1_INM15 from OPA1_VIN"] 54 | EN: 55 | Disabled: [0, "Comparator 1 disabled"] 56 | Enabled: [1, "Comparator 1 enabled"] 57 | 58 | FR: 59 | "FLTCNT?": [0, 0xffff] 60 | "FLTEN?": 61 | Disabled: [0, "Comparator digital filter disabled"] 62 | Enabled: [1, "Comparator digital filter enabled"] 63 | 64 | COMP1: 65 | CSR: 66 | VCSEL: 67 | Vcc: [0, "VCC"] 68 | AdcRef: [1, "ADC reference voltage"] 69 | VCDIV_EN: 70 | Disabled: [0, "Voltage division not enabled"] 71 | Enabled: [1, "Voltage division enabled"] 72 | VCDIV: [0, 0x3f] 73 | -------------------------------------------------------------------------------- /scripts/viewgroups.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | PY32 Family Tree 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 |
15 | 16 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /peripherals/pwr/pwr_f0.yaml: -------------------------------------------------------------------------------- 1 | PWR: 2 | CR1: 3 | _modify: 4 | LPR: 5 | name: LPRUN 6 | LPRUN: 7 | MainMode: [0, "Voltage regulator in Main mode in Low-power run mode"] 8 | LowPowerMode: [1, "Voltage regulator in low-power mode in Low-power run mode"] 9 | HSION_CTRL: 10 | WaiteMR: [0, "Enable HSI after MR is stable"] 11 | WakeOnVR: [1, "Enable HSI when VR is on (enable HSI immediately when wakeup)"] 12 | SRAM_RETV: 13 | V0_9: [3, "Supply voltage 0.9 V for SRAM"] 14 | V1_x: [4, "Supply voltage 1.0 or 1.2 V (depends on VOS) for SRAM"] 15 | FLS_SLPTIME: 16 | FiveMicroSec: [0, "Flash wait 5 us after wakeup from stop mode"] 17 | TwoMicroSec: [1, "Flash wait 2 us after wakeup from stop mode"] 18 | ThreeMicroSec: [2, "Flash wait 3 us after wakeup from stop mode"] 19 | ExcuteFromSRAM: [3, "Excute program from SRAM after wakeup from stop mode"] 20 | MRRDY_TIME: 21 | TwoMicroSec: [0, "MR ready after 2 us"] 22 | ThreeMicroSec: [1, "MR ready after 3 us"] 23 | FourMicroSec: [2, "MR ready after 4 us"] 24 | FiveMicroSec: [3, "MR ready after 5 us"] 25 | VOS: 26 | V1_2: [0, "1.2 V (range 1)"] 27 | V1_0: [1, "1.0 V (range 2)"] 28 | DBP: 29 | Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"] 30 | Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"] 31 | BIAS_CR_SEL: 32 | FactoryConfig: [0, "Bias config from factory config bytes"] 33 | BiasCR: [1, "Bias config from BIAS_CR register"] 34 | BIAS_CR: 35 | [0, 15] 36 | CR2: 37 | FLT_TIME: 38 | T30us: [0, "Filter time is about 30 us"] 39 | T60us: [1, "Filter time is about 60 us"] 40 | T120us: [2, "Filter time is about 120 us"] 41 | T480us: [3, "Filter time is about 480 us"] 42 | T1_92ms: [4, "Filter time is about 1.92 ms"] 43 | T3_8ms: [5, "Filter time is about 3.8 ms"] 44 | T30_7ms: [6, "Filter time is about 30.7 ms"] 45 | FLTEN: 46 | Disabled: [0, "Digital filter disabled"] 47 | Enabled: [1, "Digital filter enabled"] 48 | PVDT: 49 | V1_8: [0, "1.8 V"] 50 | V2_0: [1, "2.0 V"] 51 | V2_2: [2, "2.2 V"] 52 | V2_4: [3, "2.4 V"] 53 | V2_6: [4, "2.6 V"] 54 | V2_8: [5, "2.8 V"] 55 | V3_0: [6, "3.0 V"] 56 | V3_2: [7, "3.2 V"] 57 | _modify: 58 | SRCSEL: 59 | name: PVD_SRCSEL 60 | PVD_SRCSEL: 61 | Vcc: [0, "VCC as detector source"] 62 | PB7: [1, "PB7 pin as detector source"] 63 | PVDE: 64 | Disabled: [0, "PVD Disabled"] 65 | Enabled: [1, "PVD Enabled"] 66 | SR: 67 | PVDO: 68 | _read: 69 | AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"] 70 | BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"] 71 | -------------------------------------------------------------------------------- /peripherals/lcd/lcd_f0.yaml: -------------------------------------------------------------------------------- 1 | LCD: 2 | CR0: 3 | CONTRAST: [0, 0xf] 4 | BSEL: 5 | Ext: [0, "External resistor mode, external circuitry required"] 6 | IntMed: [2, " Internal resistive divider, medium power consumption mode"] 7 | IntSm: [4, "Internal resistive voltage divider, small power consumption mode"] 8 | IntHi: [6, "Internal resistive voltage divider, high power mode"] 9 | DUTY: 10 | Static: [0, "Static"] 11 | Duty2: [1, "1/2 duty"] 12 | Duty3: [2, "1/3 duty"] 13 | Duty4: [3, "1/4 duty"] 14 | Duty6: [5, "1/6 duty"] 15 | Duty8: [7, "1/8 duty"] 16 | BIAS: 17 | Bias3: [0, "1/3 bias"] 18 | Bias2: [1, "1/2 bias"] 19 | LCDCLK: 20 | Hz64: [0, "64 Hz"] 21 | Hz128: [1, "128 Hz"] 22 | Hz256: [2, "256 Hz"] 23 | Hz512: [3, "512 Hz"] 24 | EN: 25 | Disabled: [0, "LCD disabled"] 26 | Enabled: [1, "LCD enabled"] 27 | 28 | CR1: 29 | INTF: 30 | NoInterrupt: [0, "No Interrupt"] 31 | Interrupt: [1, "Interrupt"] 32 | DMAEN: 33 | Disabled: [0, "Disable LCD interrupt triggered DMA"] 34 | Enabled: [1, "Enables LCD interrupt triggering DMA"] 35 | IE: 36 | Disabled: [0, "Interrupt disabled"] 37 | Enabled: [1, "Interrupt enabled"] 38 | MODE: 39 | Mode0: [0, "Mode 0"] 40 | Mode1: [1, "Mode 1"] 41 | BLINKEN: 42 | Disabled: [0, "LCD splash screen disabled"] 43 | Enabled: [1, "LCD splash screen enabled"] 44 | BLINKCNT: [0, 0x3f] 45 | 46 | INTCLR: 47 | INTF_CLR: 48 | _W0C: 49 | Clear: [0, "Clear flag"] 50 | 51 | POEN0: 52 | S31: 53 | S30: 54 | S29: 55 | S28: 56 | S27: 57 | S26: 58 | S25: 59 | S24: 60 | S23: 61 | S22: 62 | S21: 63 | S20: 64 | S19: 65 | S18: 66 | S17: 67 | S16: 68 | S15: 69 | S14: 70 | S13: 71 | S12: 72 | S11: 73 | S10: 74 | S9: 75 | S8: 76 | S7: 77 | S6: 78 | S5: 79 | S4: 80 | S3: 81 | S2: 82 | S1: 83 | S0: 84 | 85 | POEN1: 86 | MUX: 87 | C3: 88 | C2: 89 | C1: 90 | C0: 91 | S36C7: 92 | S37C6: 93 | S38C5: 94 | S39C4: 95 | S35: 96 | S34: 97 | S33: 98 | S32: 99 | 100 | RAM0: 101 | D: 102 | 103 | RAM1: 104 | D: 105 | 106 | RAM2: 107 | D: 108 | 109 | RAM3: 110 | D: 111 | 112 | RAM4: 113 | D: 114 | 115 | RAM5: 116 | D: 117 | 118 | RAM6: 119 | D: 120 | 121 | RAM7: 122 | D: 123 | 124 | RAM8: 125 | D: 126 | 127 | RAM9: 128 | D: 129 | 130 | RAM10: 131 | D: 132 | 133 | RAM11: 134 | D: 135 | 136 | RAM12: 137 | D: 138 | 139 | RAM13: 140 | D: 141 | 142 | RAM14: 143 | D: 144 | 145 | RAM15: 146 | D: 147 | -------------------------------------------------------------------------------- /peripherals/syscfg/syscfg_f0.yaml: -------------------------------------------------------------------------------- 1 | SYSCFG: 2 | CFGR1: 3 | MEM_MODE: 4 | MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] 5 | SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] 6 | MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] 7 | SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] 8 | "I2C_P?*_ANF": 9 | Standard: [0, "Pin operate in standard mode"] 10 | AnalogFilter: [1, "I2C Analog filter enabled on pin"] 11 | CFGR2: 12 | ETR_SRC_TIM1: 13 | GPIO: [0, "TIM1_ETR is connected to GPIO"] 14 | COMP1: [1, "TIM1_ETR is connected to COMP1"] 15 | COMP2: [2, "TIM1_ETR is connected to COMP2"] 16 | ADC: [3, "TIM1_ETR is connected to ADC"] 17 | "COMP?_BRK_TIM*": 18 | Disconnected: [0, "COMP? output not connect to TIM? Break input"] 19 | Connected: [1, "COMP? output connected to TIM? Break input"] 20 | PVD_LOCK: 21 | Disconnected: [0, "PVD LOCKUP output disconnected from TIM1/16/17 Break input"] 22 | Connected: [1, "PVD LOCKUP output connected to TIM1/16/17 Break input"] 23 | LOCKUP_LOCK: 24 | Disconnected: [0, "Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input"] 25 | Connected: [1, "Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input"] 26 | CFGR3: 27 | "DMA?_MAP": 28 | ADC: [0, "ADC DMA requests mapped on DMA?"] 29 | SPI1_TX: [1, "SPI1_TX DMA requests mapped on DMA?"] 30 | SPI1_RX: [2, "SPI1_RX DMA requests mapped on DMA?"] 31 | USART1_TX: [5, "USART1_TX DMA requests mapped on DMA?"] 32 | USART1_RX: [6, "USART1_RX DMA requests mapped on DMA?"] 33 | USART2_TX: [7, "USART2_TX DMA requests mapped on DMA?"] 34 | USART2_RX: [8, "USART2_RX DMA requests mapped on DMA?"] 35 | I2C_TX: [9, "I2C_TX DMA requests mapped on DMA?"] 36 | I2C_RX: [10, "I2C_RX DMA requests mapped on DMA?"] 37 | TIM1_CH1: [11, "TIM1_CH1 DMA requests mapped on DMA?"] 38 | TIM1_CH2: [12, "TIM1_CH2 DMA requests mapped on DMA?"] 39 | TIM1_CH3: [13, "TIM1_CH3 DMA requests mapped on DMA?"] 40 | TIM1_CH4: [14, "TIM1_CH4 DMA requests mapped on DMA?"] 41 | TIM1_COM: [15, "TIM1_COM DMA requests mapped on DMA?"] 42 | TIM1_UP: [16, "TIM1_UP DMA requests mapped on DMA?"] 43 | TIM1_TRIG: [17, "TIM1_TRIG DMA requests mapped on DMA?"] 44 | TIM3_CH1: [18, "TIM3_CH1 DMA requests mapped on DMA?"] 45 | TIM3_CH3: [19, "TIM3_CH3 DMA requests mapped on DMA?"] 46 | TIM3_CH4: [20, "TIM3_CH4 DMA requests mapped on DMA?"] 47 | TIM3_TRG: [21, "TIM3_TRG DMA requests mapped on DMA?"] 48 | TIM3_UP: [22, "TIM3_UP DMA requests mapped on DMA?"] 49 | TIM16_CH1: [24, "TIM16_CH1 DMA requests mapped on DMA?"] 50 | TIM16_UP: [25, "TIM16_UP DMA requests mapped on DMA?"] 51 | TIM17_CH1: [26, "TIM17_CH1 DMA requests mapped on DMA?"] 52 | TIM17_UP: [27, "TIM17_UP DMA requests mapped on DMA?"] -------------------------------------------------------------------------------- /peripherals/comp/comp_f0.yaml: -------------------------------------------------------------------------------- 1 | COMP?: 2 | CSR: 3 | _modify: 4 | COMP_EN: 5 | name: EN 6 | COMP_OUT: 7 | name: VALUE 8 | EN: 9 | Disabled: [0, "Comparator 1 disabled"] 10 | Enabled: [1, "Comparator 1 enabled"] 11 | POLARITY: 12 | NotInverted: [0, "Output is not inverted"] 13 | Inverted: [1, "Output is inverted"] 14 | PWRMODE: 15 | HighSpeed: [0, "High speed / full power"] 16 | MediumSpeed: [1, "Medium speed / medium power"] 17 | LowSpeed: [2, "Low speed / low power"] 18 | VeryLowSpeed: [3, "Very-low speed / ultra-low power"] 19 | VALUE: 20 | _read: 21 | Low: [0, "Comparator output is low"] 22 | High: [1, "Comparator output is high"] 23 | LOCK: 24 | Unlocked: [0, "Comparator CSR bits are read-write"] 25 | Locked: [1, "Comparator CSR bits are read-only"] 26 | FR: 27 | FLTEN: 28 | Disabled: [0, "Comparator digital filter disabled"] 29 | Enabled: [1, "Comparator digital filter enabled"] 30 | FLTCNT: 31 | [0, 0xFFFF] 32 | 33 | COMP1: 34 | CSR: 35 | _modify: 36 | SCALER_EN: 37 | name: SCALER 38 | SCALER: 39 | Disabled: [0, "Voltage scaler disabled"] 40 | Enabled: [1, "Voltage scaler enabled"] 41 | INMSEL: 42 | OneQuarterVRef: [0, "1/4 of VRefint"] 43 | OneHalfVRef: [1, "1/2 of VRefint"] 44 | ThreeQuarterVRef: [2, "3/4 of VRefint"] 45 | VRef: [3, "VRefint"] 46 | Vcc: [4, "VCC"] 47 | TS: [5, "TS"] 48 | PB1: [6, "PB1 connected to inverting input"] 49 | PA0: [8, "PA0 connected to inverting input"] 50 | INPSEL: 51 | PB8: [0, "PB8 connected to non-inverting input"] 52 | PB2: [1, "PB2 connected to non-inverting input"] 53 | PA1: [2, "PA1 connected to non-inverting input"] 54 | WINMODE: 55 | Disabled: [0, "COMP1 non-inverting input is not connected to COMP2_INP"] 56 | Enabled: [1, "COMP1 non-inverting input is connected to COMP2_INP"] 57 | HYST: 58 | Disabled: [0, "COMP1 and COMP2 hysteresis disabled"] 59 | Enabled: [1, "COMP1 and COMP2 hysteresis enabled"] 60 | 61 | COMP2: 62 | CSR: 63 | INMSEL: 64 | OneQuarterVRef: [0, "1/4 of VRefint"] 65 | ThreeQuarterVRef: [1, "3/4 of VRefint"] 66 | OneHalfVRef: [2, "1/2 of VRefint"] 67 | VRef: [3, "VRefint"] 68 | Vcc: [4, "VCC"] 69 | TS: [5, "TS"] 70 | PB3: [6, "PB3 connected to inverting input"] 71 | PB7: [7, "PB6 connected to inverting input"] 72 | PA2: [8, "PA2 connected to inverting input"] 73 | INPSEL: 74 | PB4: [0, "PB4 connected to non-inverting input"] 75 | PB6: [1, "PB6 connected to non-inverting input"] 76 | PA3: [2, "PA3 connected to non-inverting input"] 77 | PF3: [3, "PF3 connected to non-inverting input"] 78 | WINMODE: 79 | Disabled: [0, "COMP2 non-inverting input is not connected to COMP1_INP"] 80 | Enabled: [1, "COMP2 non-inverting input is connected to COMP1_INP"] 81 | -------------------------------------------------------------------------------- /cortex_m/peripherals/fpb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | FPB: 5 | description: Flash Patch and Breakpoint Unit 6 | baseAddress: 0xE0002000 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x1000 10 | registers: 11 | CTRL: 12 | description: FlashPatch Control Register 13 | addressOffset: 0x0 14 | access: read-write 15 | REMAP: 16 | description: FlashPatch Remap Register 17 | addressOffset: 0x4 18 | access: read-write 19 | COMP0: 20 | description: FlashPatch Comparator Register 0 21 | addressOffset: 0x8 22 | access: read-write 23 | COMP1: 24 | description: FlashPatch Comparator Register 1 25 | addressOffset: 0xc 26 | access: read-write 27 | COMP2: 28 | description: FlashPatch Comparator Register 2 29 | addressOffset: 0x10 30 | access: read-write 31 | COMP3: 32 | description: FlashPatch Comparator Register 3 33 | addressOffset: 0x14 34 | access: read-write 35 | COMP4: 36 | description: FlashPatch Comparator Register 4 37 | addressOffset: 0x18 38 | access: read-write 39 | COMP5: 40 | description: FlashPatch Comparator Register 5 41 | addressOffset: 0x1c 42 | access: read-write 43 | COMP6: 44 | description: FlashPatch Comparator Register 6 45 | addressOffset: 0x20 46 | access: read-write 47 | COMP7: 48 | description: FlashPatch Comparator Register 7 49 | addressOffset: 0x24 50 | access: read-write 51 | COMP8: 52 | description: FlashPatch Comparator Register 8 53 | addressOffset: 0x28 54 | access: read-write 55 | COMP9: 56 | description: FlashPatch Comparator Register 9 57 | addressOffset: 0x2c 58 | access: read-write 59 | COMP10: 60 | description: FlashPatch Comparator Register 10 61 | addressOffset: 0x30 62 | access: read-write 63 | COMP11: 64 | description: FlashPatch Comparator Register 11 65 | addressOffset: 0x34 66 | access: read-write 67 | COMP12: 68 | description: FlashPatch Comparator Register 12 69 | addressOffset: 0x38 70 | access: read-write 71 | COMP13: 72 | description: FlashPatch Comparator Register 13 73 | addressOffset: 0x3c 74 | access: read-write 75 | COMP14: 76 | description: FlashPatch Comparator Register 14 77 | addressOffset: 0x40 78 | access: read-write 79 | COMP15: 80 | description: FlashPatch Comparator Register 15 81 | addressOffset: 0x44 82 | access: read-write 83 | LSR: 84 | description: Lock Status Register 85 | addressOffset: 0xFB4 86 | access: read-only 87 | LAR: 88 | description: Lock Access Register 89 | addressOffset: 0xFB0 90 | access: write-only 91 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/fpb.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | FPB: 5 | description: Flash Patch and Breakpoint Unit 6 | baseAddress: 0xE0002000 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x1000 10 | registers: 11 | CTRL: 12 | description: FlashPatch Control register 13 | addressOffset: 0x0 14 | access: read-write 15 | REMAP: 16 | description: FlashPatch Remap register 17 | addressOffset: 0x4 18 | access: read-write 19 | COMP0: 20 | description: FlashPatch Comparator register 0 21 | addressOffset: 0x8 22 | access: read-write 23 | COMP1: 24 | description: FlashPatch Comparator register 1 25 | addressOffset: 0xc 26 | access: read-write 27 | COMP2: 28 | description: FlashPatch Comparator register 2 29 | addressOffset: 0x10 30 | access: read-write 31 | COMP3: 32 | description: FlashPatch Comparator register 3 33 | addressOffset: 0x14 34 | access: read-write 35 | COMP4: 36 | description: FlashPatch Comparator register 4 37 | addressOffset: 0x18 38 | access: read-write 39 | COMP5: 40 | description: FlashPatch Comparator register 5 41 | addressOffset: 0x1c 42 | access: read-write 43 | COMP6: 44 | description: FlashPatch Comparator register 6 45 | addressOffset: 0x20 46 | access: read-write 47 | COMP7: 48 | description: FlashPatch Comparator register 7 49 | addressOffset: 0x24 50 | access: read-write 51 | COMP8: 52 | description: FlashPatch Comparator register 8 53 | addressOffset: 0x28 54 | access: read-write 55 | COMP9: 56 | description: FlashPatch Comparator register 9 57 | addressOffset: 0x2c 58 | access: read-write 59 | COMP10: 60 | description: FlashPatch Comparator register 10 61 | addressOffset: 0x30 62 | access: read-write 63 | COMP11: 64 | description: FlashPatch Comparator register 11 65 | addressOffset: 0x34 66 | access: read-write 67 | COMP12: 68 | description: FlashPatch Comparator register 12 69 | addressOffset: 0x38 70 | access: read-write 71 | COMP13: 72 | description: FlashPatch Comparator register 13 73 | addressOffset: 0x3c 74 | access: read-write 75 | COMP14: 76 | description: FlashPatch Comparator register 14 77 | addressOffset: 0x40 78 | access: read-write 79 | COMP15: 80 | description: FlashPatch Comparator register 15 81 | addressOffset: 0x44 82 | access: read-write 83 | LSR: 84 | description: Lock Status register 85 | addressOffset: 0xFB4 86 | access: read-only 87 | LAR: 88 | description: Lock Access register 89 | addressOffset: 0xFB0 90 | access: write-only 91 | -------------------------------------------------------------------------------- /peripherals/flash/flash_f040.yaml: -------------------------------------------------------------------------------- 1 | FLASH: 2 | ACR: 3 | LATENCY: 4 | WS0: [0, "0 wait states"] 5 | WS1: [1, "1 wait state"] 6 | 7 | KEYR: 8 | KEY: [0, 0xFFFFFFFF] 9 | 10 | OPTKEYR: 11 | OPTKEY: [0, 0xFFFFFFFF] 12 | 13 | SR: 14 | EOP: 15 | NoEvent: [0, "No EOP operation occurred"] 16 | Event: [1, "An EOP event occurred"] 17 | WRPERR: 18 | NoError: [0, "No write protection error occurred"] 19 | Error: [1, "A write protection error occurred"] 20 | OPTVERR: 21 | NoError: [0, "No option and Engineering bits loading validity error occurred"] 22 | Error: [1, " An option and Engineering bits loading validity error occurred"] 23 | BSY: 24 | _read: 25 | Inactive: [0, "No write/erase operation is in progress"] 26 | Active: [1, "A write/erase operation is in progress"] 27 | 28 | CR: 29 | OBL_LAUNCH: 30 | Inactive: [0, "Force option byte loading inactive"] 31 | Active: [1, "Force option byte loading active"] 32 | EOPIE: 33 | Disabled: [0, "End of operation interrupt disabled"] 34 | Enabled: [1, "End of operation interrupt enabled"] 35 | ERRIE: 36 | Disabled: [0, "Error interrupt generation disabled"] 37 | Enabled: [1, "Error interrupt generation enabled"] 38 | OPTLOCK: 39 | Unlocked: [0, "Options is unlocked"] 40 | Locked: [1, "Options is locked"] 41 | LOCK: 42 | Unlocked: [0, "FLASH_CR register is unlocked"] 43 | Locked: [1, "FLASH_CR register is locked"] 44 | _modify: 45 | PGTSTRT: 46 | name: PGSTRT 47 | Start: [1, "Flash main memory program start"] 48 | OPTSTRT: 49 | OptionByteProgram: [1, "Option byte program start"] 50 | SER: 51 | SectorErase: [1, "Erase activated for user sectors"] 52 | MER: 53 | MassErase: [1, "Erase activated for all user sectors"] 54 | PER: 55 | PageErase: [1, "Erase activated for selected page"] 56 | PG: 57 | Program: [1, "Flash programming activated"] 58 | OPTR: 59 | nBOOT1: 60 | Clear: [0, "Select boot mode together with BOOT Pin"] 61 | Set: [1, "Select boot mode together with BOOT Pin"] 62 | NRST_MODE: 63 | NRST: [0, "Configure as NRST pin"] 64 | GPIO: [1, "Configure as GPIO pin"] 65 | WWDG_SW: 66 | Hardware: [0, "Hardware window watchdog"] 67 | Software: [1, "Software window watchdog"] 68 | _modify: 69 | IDWG_SW: 70 | name: IWDG_SW 71 | Hardware: [0, "Hardware independent watchdog"] 72 | Software: [1, "Software independent watchdog"] 73 | RDP: 74 | Level0: [0xAA, "Level 0, readout protection not active"] 75 | Level2: [0xCC, "Level 2, chip readout protection active"] 76 | # The manual specifies "Others" for Level 1, 0x88 is arbitrary 77 | # Since the reset value is AA, the value for Level 1 needs to be written 78 | # so there is no conflict reading other values (unless unsafe is used) 79 | Level1: [0x88, "Level 1, memories readout protection active (writes 0x88)"] 80 | WRPR: 81 | WRP: [0, 0xFFFF] 82 | -------------------------------------------------------------------------------- /scripts/README.md: -------------------------------------------------------------------------------- 1 | # Scripts for py32-rs 2 | These scripts are used during development of the py32f0 crates 3 | 4 | ## comparesvd.py 5 | Compares 2 svd's by peripheral memory address. 6 | ``` 7 | usage: comparesvd.py svdfile1 svdfile2 8 | ``` 9 | 10 | ## group.py [NOT WORKING] 11 | Generate sets of devices with peripherals in common 12 | ``` 13 | usage: group.py [-h] devices output 14 | ``` 15 | 16 | ## htmlcomparesvdall.sh 17 | Runs `htmlcomparesvd.py` on all patched svd files in svd directory. Generates a `html/comparisons.html` file. 18 | ``` 19 | usage: htmlcomparesvdall.sh 20 | ``` 21 | 22 | ## htmlcomparesvd.py 23 | Creates html pages that compare peripherals, registers, and fields given a set of svd's. 24 | ``` 25 | usage: htmlcomparesvd.py [-h] htmldir [svdfiles ...] 26 | ``` 27 | 28 | ## interrupts.py 29 | Outputs peripheral vector number, interrupt name, and description from a svd 30 | ``` 31 | usage: interrupts.py [-h] outdir [svdfiles ...] 32 | ``` 33 | 34 | ## makecrates.py 35 | Script that builds the rust crates. 36 | ``` 37 | usage: makecrates.py [-h] [-y] [--families FAMILY [FAMILY ...]] devices 38 | ``` 39 | 40 | ## makehtml.py 41 | Generates a webpage for a given SVD file containing details on every 42 | peripheral and register and their level of coverage. 43 | ``` 44 | usage: makehtml.py [-h] htmldir [svdfiles ...] 45 | ``` 46 | 47 | ## makejson.py [NOT WORKING] 48 | Transforms the given SVD files into a JSON format more suited for 49 | web pages. 50 | ``` 51 | usage: makejson.py [-h] htmldir [svdfiles ...] 52 | ``` 53 | 54 | ## matchperipherals.py [NOT WORKING] 55 | 56 | ## periphtemplate.py 57 | Prints out a basic yaml template of a peripheral in svdfile. 58 | ``` 59 | usage: periphtemplate.py [-h] svdfile peripheral yamlfile 60 | ``` 61 | 62 | ## svdmmap.py 63 | Outputs a peripheral memory map of the device in a svd file 64 | usage: 65 | ``` 66 | python3 svdmmap.py 67 | ``` 68 | Example output (partial) 69 | ``` 70 | 0x40000000 A PERIPHERAL TIM2 71 | 0x40000000 B REGISTER CR1: desc CR1 72 | 0x40000000 C FIELD 00w01 CEN: desc CEN 73 | 0x40000000 C FIELD 01w01 UDIS: desc UDIS 74 | 0x40000000 C FIELD 02w01 URS: desc URS 75 | 0x40000000 C FIELD 03w01 OPM: desc OPM 76 | 0x40000000 C FIELD 04w01 DIR: desc DIR 77 | 0x40000000 C FIELD 05w02 CMS: desc CMS 78 | 0x40000000 C FIELD 07w01 ARPE: desc ARPE 79 | 0x40000000 C FIELD 08w02 CKD: desc CKD 80 | 0x40000004 B REGISTER CR2: desc CR2 81 | 0x40000004 C FIELD 03w01 CCDS: desc CCDS 82 | 0x40000004 C FIELD 04w03 MMS: desc MMS 83 | 0x40000004 C FIELD 07w01 TI1S: desc TI1S 84 | ... 85 | ``` 86 | 87 | ## timer_hierarchy.py 88 | Prints the timer peripherals common registers and fields for the device in a svd file 89 | ``` 90 | usage: timer_hierarchy.py [-h] svdfile 91 | ``` 92 | 93 | ## tool_install.sh 94 | Installs the tools required to generate the rust crates for this device family. The script will download and install 95 | the specific version of the tools needed. 96 | 97 | ## HTML Templates 98 | Used in `makehtml.py` and `makejson.py` 99 | 100 | - makehtml.index.template.html 101 | - makehtml.template.html 102 | - viewgroups.html 103 | -------------------------------------------------------------------------------- /peripherals/spi/spi_f002b.yaml: -------------------------------------------------------------------------------- 1 | "SPI*": 2 | CR1: 3 | BIDIMODE: 4 | Unidirectional: [0, "2-line unidirectional data mode selected"] 5 | Bidirectional: [1, "1-line bidirectional data mode selected"] 6 | BIDIOE: 7 | OutputDisabled: [0, "Output disabled (receive-only mode)"] 8 | OutputEnabled: [1, "Output enabled (transmit-only mode)"] 9 | RXONLY: 10 | FullDuplex: [0, "Full duplex (Transmit and receive)"] 11 | OutputDisabled: [1, "Output disabled (Receive-only mode)"] 12 | SSM: 13 | Disabled: [0, "Software slave management disabled"] 14 | Enabled: [1, "Software slave management enabled"] 15 | SSI: 16 | SlaveSelected: [0, "0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 17 | SlaveNotSelected: [1, "1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 18 | LSBFIRST: 19 | MSBFirst: [0, "Data is transmitted/received with the MSB first"] 20 | LSBFirst: [1, "Data is transmitted/received with the LSB first"] 21 | SPE: 22 | Disabled: [0, "Peripheral disabled"] 23 | Enabled: [1, "Peripheral enabled"] 24 | BR: 25 | Div2: [0, "f_PCLK / 2"] 26 | Div4: [1, "f_PCLK / 4"] 27 | Div8: [2, "f_PCLK / 8"] 28 | Div16: [3, "f_PCLK / 16"] 29 | Div32: [4, "f_PCLK / 32"] 30 | Div64: [5, "f_PCLK / 64"] 31 | Div128: [6, "f_PCLK / 128"] 32 | Div256: [7, "f_PCLK / 256"] 33 | MSTR: 34 | Slave: [0, "Slave configuration"] 35 | Master: [1, "Master configuration"] 36 | CPOL: 37 | IdleLow: [0, "CK to 0 when idle"] 38 | IdleHigh: [1, "CK to 1 when idle"] 39 | CPHA: 40 | FirstEdge: [0, "The first clock transition is the first data capture edge"] 41 | SecondEdge: [1, "The second clock transition is the first data capture edge"] 42 | CR2: 43 | SLVFM: 44 | Normal: [0, "Slave normal mode, spi clock speed less than PCLK / 4"] 45 | Fast: [1, "Slave fast mode, spi clock speed equal to PCLK / 4"] 46 | DS: 47 | EightBit: [0, "8-bit"] 48 | SixteenBit: [1, "16-bit"] 49 | TXEIE: 50 | Masked: [0, "TXE interrupt masked"] 51 | NotMasked: [1, "TXE interrupt not masked"] 52 | RXNEIE: 53 | Masked: [0, "RXE interrupt masked"] 54 | NotMasked: [1, "RXE interrupt not masked"] 55 | ERRIE: 56 | Masked: [0, "Error interrupt masked"] 57 | NotMasked: [1, "Error interrupt not masked"] 58 | SSOE: 59 | Disabled: [0, "SS output is disabled in master mode"] 60 | Enabled: [1, "SS output is enabled in master mode"] 61 | SR: 62 | FTLVL: 63 | _read: 64 | Empty: [0, "Tx FIFO Empty"] 65 | Quarter: [1, "Tx 1/4 FIFO"] 66 | Half: [2, "Tx 1/2 FIFO"] 67 | Full: [3, "Tx FIFO full"] 68 | FRLVL: 69 | _read: 70 | Empty: [0, "Rx FIFO Empty"] 71 | Quarter: [1, "Rx 1/4 FIFO"] 72 | Half: [2, "Rx 1/2 FIFO"] 73 | Full: [3, "Rx FIFO full"] 74 | BSY: 75 | _read: 76 | NotBusy: [0, "SPI not busy"] 77 | Busy: [1, "SPI busy"] 78 | OVR: 79 | _read: 80 | NoOverrun: [0, "No overrun occurred"] 81 | Overrun: [1, "Overrun occurred"] 82 | MODF: 83 | _read: 84 | NoFault: [0, "No mode fault occurred"] 85 | Fault: [1, "Mode fault occurred"] 86 | TXE: 87 | NotEmpty: [0, "Tx buffer not empty"] 88 | Empty: [1, "Tx buffer empty"] 89 | RXNE: 90 | Empty: [0, "Rx buffer empty"] 91 | NotEmpty: [1, "Rx buffer not empty"] 92 | DR: 93 | DR: [0, 0xFFFF] 94 | -------------------------------------------------------------------------------- /peripherals/flash/flash_f002a.yaml: -------------------------------------------------------------------------------- 1 | FLASH: 2 | ACR: 3 | LATENCY: 4 | WS0: [0, "0 wait states"] 5 | WS1: [1, "1 wait state"] 6 | 7 | KEYR: 8 | KEY: [0, 0xFFFFFFFF] 9 | 10 | OPTKEYR: 11 | OPTKEY: [0, 0xFFFFFFFF] 12 | 13 | SR: 14 | EOP: 15 | NoEvent: [0, "No EOP operation occurred"] 16 | Event: [1, "An EOP event occurred"] 17 | WRPERR: 18 | NoError: [0, "No write protection error occurred"] 19 | Error: [1, "A write protection error occurred"] 20 | OPTVERR: 21 | NoError: [0, "No option and Engineering bits loading validity error occurred"] 22 | Error: [1, " An option and Engineering bits loading validity error occurred"] 23 | BSY: 24 | _read: 25 | Inactive: [0, "No write/erase operation is in progress"] 26 | Active: [1, "A write/erase operation is in progress"] 27 | 28 | CR: 29 | OBL_LAUNCH: 30 | Inactive: [0, "Force option byte loading inactive"] 31 | Active: [1, "Force option byte loading active"] 32 | EOPIE: 33 | Disabled: [0, "End of operation interrupt disabled"] 34 | Enabled: [1, "End of operation interrupt enabled"] 35 | ERRIE: 36 | Disabled: [0, "Error interrupt generation disabled"] 37 | Enabled: [1, "Error interrupt generation enabled"] 38 | OPTLOCK: 39 | Unlocked: [0, "Options is unlocked"] 40 | Locked: [1, "Options is locked"] 41 | LOCK: 42 | Unlocked: [0, "FLASH_CR register is unlocked"] 43 | Locked: [1, "FLASH_CR register is locked"] 44 | _modify: 45 | PGTSTRT: 46 | name: PGSTRT 47 | Start: [1, "Flash main memory program start"] 48 | OPTSTRT: 49 | OptionByteProgram: [1, "Option byte program start"] 50 | SER: 51 | SectorErase: [1, "Erase activated for user sectors"] 52 | MER: 53 | MassErase: [1, "Erase activated for all user sectors"] 54 | PER: 55 | PageErase: [1, "Erase activated for selected page"] 56 | PG: 57 | Program: [1, "Flash programming activated"] 58 | OPTR: 59 | nBOOT1: 60 | Clear: [0, "Select boot mode together with BOOT Pin"] 61 | Set: [1, "Select boot mode together with BOOT Pin"] 62 | NRST_MODE: 63 | NRST: [0, "Configure as NRST pin"] 64 | GPIO: [1, "Configure as GPIO pin"] 65 | _modify: 66 | IDWG_SW: 67 | name: IWDG_SW 68 | Hardware: [0, "Hardware independent watchdog"] 69 | Software: [1, "Software independent watchdog"] 70 | BORF_LEV: 71 | Level0: [0, "BOR level 0. Reset level threshold is around 1.8 V"] 72 | Level1: [1, "BOR level 1. Reset level threshold is around 2.0 V"] 73 | Level2: [2, "BOR level 2. Reset level threshold is around 2.2 V"] 74 | Level3: [3, "BOR level 3. Reset level threshold is around 2.4 V"] 75 | Level4: [4, "BOR level 4. Reset level threshold is around 2.6 V"] 76 | Level5: [5, "BOR level 5. Reset level threshold is around 2.8 V"] 77 | Level6: [6, "BOR level 6. Reset level threshold is around 3.0 V"] 78 | Level7: [7, "BOR level 7. Reset level threshold is around 3.2 V"] 79 | BOREN: 80 | Disabled: [0, "BOR disabled"] 81 | Enabled: [1, "BOR enabled"] 82 | RDP: 83 | Level0: [0xAA, "Level 0, readout protection not active"] 84 | Level2: [0xCC, "Level 2, chip readout protection active"] 85 | # The manual specifies "Others" for Level 1, 0x88 is arbitrary 86 | # Since the reset value is AA, the value for Level 1 needs to be written 87 | # so there is no conflict reading other values (unless unsafe is used) 88 | Level1: [0x88, "Level 1, memories readout protection active (writes 0x88)"] 89 | WRPR: 90 | WRP: [0, 0xFFFF] 91 | -------------------------------------------------------------------------------- /cortex_m/peripherals/cpuid_v7.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | CPUID: 5 | description: CPUID 6 | baseAddress: 0xE000ED00 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x88 10 | registers: 11 | Base: 12 | description: Provides identification information for the processor 13 | addressOffset: 0x0 14 | access: read-only 15 | fields: 16 | IMPLEMENTER: 17 | description: This field defines the implementer 18 | bitOffset: 24 19 | bitWidth: 7 20 | VARIANT: 21 | description: Implementation defined 22 | bitOffset: 20 23 | bitWidth: 4 24 | ARCHITECTURE: 25 | description: This field defines the architecture 26 | bitOffset: 16 27 | bitWidth: 4 28 | PARTNO: 29 | description: Implementation defined. 30 | bitOffset: 4 31 | bitWidth: 12 32 | REVISION: 33 | description: Implementation defined. 34 | bitOffset: 0 35 | bitWidth: 4 36 | PFR0: 37 | description: Processor Feature Register 0 38 | addressOffset: 0x40 39 | access: read-only 40 | PFR1: 41 | description: Processor Feature Register 1 42 | addressOffset: 0x44 43 | access: read-only 44 | DFR0: 45 | description: Debug Feature Register 0 46 | addressOffset: 0x48 47 | access: read-only 48 | AFR0: 49 | description: Auxiliary Feature Register 0 50 | addressOffset: 0x4C 51 | access: read-only 52 | MMFR0: 53 | description: Memory Model Feature Register 0 54 | addressOffset: 0x50 55 | access: read-only 56 | MMFR1: 57 | description: Memory Model Feature Register 1 58 | addressOffset: 0x54 59 | access: read-only 60 | MMFR2: 61 | description: Memory Model Feature Register 2 62 | addressOffset: 0x58 63 | access: read-only 64 | MMFR3: 65 | description: Memory Model Feature Register 3 66 | addressOffset: 0x5C 67 | access: read-only 68 | ISAR0: 69 | description: Instruction Set Attribute Register 0 70 | addressOffset: 0x60 71 | access: read-only 72 | ISAR1: 73 | description: Instruction Set Attribute Register 1 74 | addressOffset: 0x64 75 | access: read-only 76 | ISAR2: 77 | description: Instruction Set Attribute Register 2 78 | addressOffset: 0x68 79 | access: read-only 80 | ISAR3: 81 | description: Instruction Set Attribute Register 3 82 | addressOffset: 0x6C 83 | access: read-only 84 | ISAR4: 85 | description: Instruction Set Attribute Register 4 86 | addressOffset: 0x70 87 | access: read-only 88 | CLIDR: 89 | description: Cache Level ID Register 90 | addressOffset: 0x78 91 | access: read-only 92 | CTR: 93 | description: Cache Type Register 94 | addressOffset: 0x7C 95 | access: read-only 96 | CCSIDR: 97 | description: Cache Size ID Register 98 | addressOffset: 0x80 99 | access: read-only 100 | CSSELR: 101 | description: Cache Size Selection Register 102 | addressOffset: 0x84 103 | access: read-write 104 | 105 | CPUID: 106 | Base: 107 | IMPLEMENTER: 108 | ARM: [0x41, "ARM Limited"] 109 | ARCHITECTURE: 110 | ARMv6M: [0xC, "ARMv6-M"] 111 | -------------------------------------------------------------------------------- /cortex_m/peripherals/bak/cpuid_v7.yaml: -------------------------------------------------------------------------------- 1 | # Reference: ARMv7-M Architecture Reference Manual issue E.b 2 | 3 | _add: 4 | CPUID: 5 | description: CPUID 6 | baseAddress: 0xE000ED00 7 | addressBlock: 8 | offset: 0x0 9 | size: 0x88 10 | registers: 11 | Base: 12 | description: Provides identification information for the processor 13 | addressOffset: 0x0 14 | access: read-only 15 | fields: 16 | IMPLEMENTER: 17 | description: This field defines the implementer 18 | bitOffset: 24 19 | bitWidth: 7 20 | VARIANT: 21 | description: Implementation defined 22 | bitOffset: 20 23 | bitWidth: 4 24 | ARCHITECTURE: 25 | description: This field defines the architecture 26 | bitOffset: 16 27 | bitWidth: 4 28 | PARTNO: 29 | description: Implementation defined. 30 | bitOffset: 4 31 | bitWidth: 12 32 | REVISION: 33 | description: Implementation defined. 34 | bitOffset: 0 35 | bitWidth: 4 36 | PFR0: 37 | description: Processor Feature Register 0 38 | addressOffset: 0x40 39 | access: read-only 40 | PFR1: 41 | description: Processor Feature Register 1 42 | addressOffset: 0x44 43 | access: read-only 44 | DFR0: 45 | description: Debug Feature Register 0 46 | addressOffset: 0x48 47 | access: read-only 48 | AFR0: 49 | description: Auxiliary Feature Register 0 50 | addressOffset: 0x4C 51 | access: read-only 52 | MMFR0: 53 | description: Memory Model Feature Register 0 54 | addressOffset: 0x50 55 | access: read-only 56 | MMFR1: 57 | description: Memory Model Feature Register 1 58 | addressOffset: 0x54 59 | access: read-only 60 | MMFR2: 61 | description: Memory Model Feature Register 2 62 | addressOffset: 0x58 63 | access: read-only 64 | MMFR3: 65 | description: Memory Model Feature Register 3 66 | addressOffset: 0x5C 67 | access: read-only 68 | ISAR0: 69 | description: Instruction Set Attribute Register 0 70 | addressOffset: 0x60 71 | access: read-only 72 | ISAR1: 73 | description: Instruction Set Attribute Register 1 74 | addressOffset: 0x64 75 | access: read-only 76 | ISAR2: 77 | description: Instruction Set Attribute Register 2 78 | addressOffset: 0x68 79 | access: read-only 80 | ISAR3: 81 | description: Instruction Set Attribute Register 3 82 | addressOffset: 0x6C 83 | access: read-only 84 | ISAR4: 85 | description: Instruction Set Attribute Register 4 86 | addressOffset: 0x70 87 | access: read-only 88 | CLIDR: 89 | description: Cache Level ID Register 90 | addressOffset: 0x78 91 | access: read-only 92 | CTR: 93 | description: Cache Type Register 94 | addressOffset: 0x7C 95 | access: read-only 96 | CCSIDR: 97 | description: Cache Size ID Register 98 | addressOffset: 0x80 99 | access: read-only 100 | CSSELR: 101 | description: Cache Size Selection Register 102 | addressOffset: 0x84 103 | access: read-write 104 | 105 | CPUID: 106 | Base: 107 | IMPLEMENTER: 108 | ARM: [0x41, "ARM Limited"] 109 | ARCHITECTURE: 110 | ARMv6M: [0xC, "ARMv6-M"] 111 | -------------------------------------------------------------------------------- /peripherals/flash/flash_f002b.yaml: -------------------------------------------------------------------------------- 1 | FLASH: 2 | ACR: 3 | LATENCY: 4 | WS0: [0, "0 wait states"] 5 | WS1: [1, "1 wait state"] 6 | 7 | KEYR: 8 | KEY: [0, 0xFFFFFFFF] 9 | 10 | OPTKEYR: 11 | OPTKEY: [0, 0xFFFFFFFF] 12 | 13 | SR: 14 | EOP: 15 | NoEvent: [0, "No EOP operation occurred"] 16 | Event: [1, "An EOP event occurred"] 17 | WRPERR: 18 | NoError: [0, "No write protection error occurred"] 19 | Error: [1, "A write protection error occurred"] 20 | OPTVERR: 21 | NoError: [0, "No option and Engineering bits loading validity error occurred"] 22 | Error: [1, " An option and Engineering bits loading validity error occurred"] 23 | BSY: 24 | _read: 25 | Inactive: [0, "No write/erase operation is in progress"] 26 | Active: [1, "A write/erase operation is in progress"] 27 | 28 | CR: 29 | OBL_LAUNCH: 30 | Inactive: [0, "Force option byte loading inactive"] 31 | Active: [1, "Force option byte loading active"] 32 | EOPIE: 33 | Disabled: [0, "End of operation interrupt disabled"] 34 | Enabled: [1, "End of operation interrupt enabled"] 35 | ERRIE: 36 | Disabled: [0, "Error interrupt generation disabled"] 37 | Enabled: [1, "Error interrupt generation enabled"] 38 | OPTLOCK: 39 | Unlocked: [0, "Options is unlocked"] 40 | Locked: [1, "Options is locked"] 41 | LOCK: 42 | Unlocked: [0, "FLASH_CR register is unlocked"] 43 | Locked: [1, "FLASH_CR register is locked"] 44 | PGSTRT: 45 | Start: [1, "Flash main memory program start"] 46 | OPTSTRT: 47 | OptionByteProgram: [1, "Option byte program start"] 48 | SER: 49 | SectorErase: [1, "Erase activated for user sectors"] 50 | MER: 51 | MassErase: [1, "Erase activated for all user sectors"] 52 | PER: 53 | PageErase: [1, "Erase activated for selected page"] 54 | PG: 55 | Program: [1, "Flash programming activated"] 56 | OPTR: 57 | NRST_MODE: 58 | NRST: [0, "Configure pin mode together with SWD_MODE"] 59 | GPIO: [1, "Configure pin mode together with SWD_MODE"] 60 | SWD_MODE: 61 | SWD: [0, "Configure pin mode together with NRST_MODE"] 62 | GPIO: [1, "Configure pin mode together with NRST_MODE"] 63 | IWDG_SW: 64 | Hardware: [0, "Hardware independent watchdog"] 65 | Software: [1, "Software independent watchdog"] 66 | BORF_LEV: 67 | Level0: [0, "BOR level 0. Reset level threshold is around 1.8 V"] 68 | Level1: [1, "BOR level 1. Reset level threshold is around 2.0 V"] 69 | Level2: [2, "BOR level 2. Reset level threshold is around 2.2 V"] 70 | Level3: [3, "BOR level 3. Reset level threshold is around 2.4 V"] 71 | Level4: [4, "BOR level 4. Reset level threshold is around 2.6 V"] 72 | Level5: [5, "BOR level 5. Reset level threshold is around 2.8 V"] 73 | Level6: [6, "BOR level 6. Reset level threshold is around 3.0 V"] 74 | Level7: [7, "BOR level 7. Reset level threshold is around 3.2 V"] 75 | BOREN: 76 | Disabled: [0, "BOR disabled"] 77 | Enabled: [1, "BOR enabled"] 78 | BTCR: 79 | NBOOT1: 80 | SRAM: [0, "Select boot mode together with BOOT0"] 81 | LoadFlash: [1, "Select boot mode together with BOOT0"] 82 | BOOT0: 83 | MainFlash: [0, "Boot from main flash"] 84 | BOOT1: [1, "Select boot mode together with nBOOT1"] 85 | BOOT_SIZE: 86 | NoLoad: [0, "No load flash area"] 87 | Boot_1K: [1, "Boot size = 1K 0x08005C00~0x08005FFF"] 88 | Boot_2K: [2, "Boot size = 2K 0x08005800~0x08005FFF"] 89 | Boot_3K: [3, "Boot size = 3K 0x08005400~0x08005FFF"] 90 | Boot_4K: [4, "Boot size = 4K 0x08005000~0x08005FFF"] 91 | WRPR: 92 | WRP: [0, 0x1F] 93 | -------------------------------------------------------------------------------- /peripherals/spi/spi_f002a.yaml: -------------------------------------------------------------------------------- 1 | "SPI*": 2 | CR1: 3 | BIDIMODE: 4 | Unidirectional: [0, "2-line unidirectional data mode selected"] 5 | Bidirectional: [1, "1-line bidirectional data mode selected"] 6 | BIDIOE: 7 | OutputDisabled: [0, "Output disabled (receive-only mode)"] 8 | OutputEnabled: [1, "Output enabled (transmit-only mode)"] 9 | RXONLY: 10 | FullDuplex: [0, "Full duplex (Transmit and receive)"] 11 | OutputDisabled: [1, "Output disabled (Receive-only mode)"] 12 | SSM: 13 | Disabled: [0, "Software slave management disabled"] 14 | Enabled: [1, "Software slave management enabled"] 15 | SSI: 16 | SlaveSelected: [0, "0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 17 | SlaveNotSelected: [1, "1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 18 | LSBFIRST: 19 | MSBFirst: [0, "Data is transmitted/received with the MSB first"] 20 | LSBFirst: [1, "Data is transmitted/received with the LSB first"] 21 | SPE: 22 | Disabled: [0, "Peripheral disabled"] 23 | Enabled: [1, "Peripheral enabled"] 24 | BR: 25 | Div2: [0, "f_PCLK / 2"] 26 | Div4: [1, "f_PCLK / 4"] 27 | Div8: [2, "f_PCLK / 8"] 28 | Div16: [3, "f_PCLK / 16"] 29 | Div32: [4, "f_PCLK / 32"] 30 | Div64: [5, "f_PCLK / 64"] 31 | Div128: [6, "f_PCLK / 128"] 32 | Div256: [7, "f_PCLK / 256"] 33 | MSTR: 34 | Slave: [0, "Slave configuration"] 35 | Master: [1, "Master configuration"] 36 | CPOL: 37 | IdleLow: [0, "CK to 0 when idle"] 38 | IdleHigh: [1, "CK to 1 when idle"] 39 | CPHA: 40 | FirstEdge: [0, "The first clock transition is the first data capture edge"] 41 | SecondEdge: [1, "The second clock transition is the first data capture edge"] 42 | CR2: 43 | SLVFM: 44 | Normal: [0, "Slave normal mode, spi clock speed less than PCLK / 4"] 45 | Fast: [1, "Slave fast mode, spi clock speed equal to PCLK / 4"] 46 | FRXTH: 47 | Half: [0, "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] 48 | Quarter: [1, "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] 49 | DS: 50 | EightBit: [0, "8-bit"] 51 | SixteenBit: [1, "16-bit"] 52 | TXEIE: 53 | Masked: [0, "TXE interrupt masked"] 54 | NotMasked: [1, "TXE interrupt not masked"] 55 | RXNEIE: 56 | Masked: [0, "RXE interrupt masked"] 57 | NotMasked: [1, "RXE interrupt not masked"] 58 | ERRIE: 59 | Masked: [0, "Error interrupt masked"] 60 | NotMasked: [1, "Error interrupt not masked"] 61 | SSOE: 62 | Disabled: [0, "SS output is disabled in master mode"] 63 | Enabled: [1, "SS output is enabled in master mode"] 64 | SR: 65 | FTLVL: 66 | _read: 67 | Empty: [0, "Tx FIFO Empty"] 68 | Quarter: [1, "Tx 1/4 FIFO"] 69 | Half: [2, "Tx 1/2 FIFO"] 70 | Full: [3, "Tx FIFO full"] 71 | FRLVL: 72 | _read: 73 | Empty: [0, "Rx FIFO Empty"] 74 | Quarter: [1, "Rx 1/4 FIFO"] 75 | Half: [2, "Rx 1/2 FIFO"] 76 | Full: [3, "Rx FIFO full"] 77 | BSY: 78 | _read: 79 | NotBusy: [0, "SPI not busy"] 80 | Busy: [1, "SPI busy"] 81 | OVR: 82 | _read: 83 | NoOverrun: [0, "No overrun occurred"] 84 | Overrun: [1, "Overrun occurred"] 85 | MODF: 86 | _read: 87 | NoFault: [0, "No mode fault occurred"] 88 | Fault: [1, "Mode fault occurred"] 89 | TXE: 90 | NotEmpty: [0, "Tx buffer not empty"] 91 | Empty: [1, "Tx buffer empty"] 92 | RXNE: 93 | Empty: [0, "Rx buffer empty"] 94 | NotEmpty: [1, "Rx buffer not empty"] 95 | DR: 96 | DR: [0, 0xFFFF] 97 | -------------------------------------------------------------------------------- /peripherals/flash/flash_f0.yaml: -------------------------------------------------------------------------------- 1 | FLASH: 2 | ACR: 3 | LATENCY: 4 | WS0: [0, "0 wait states"] 5 | WS1: [1, "1 wait state"] 6 | 7 | KEYR: 8 | KEY: [0, 0xFFFFFFFF] 9 | 10 | OPTKEYR: 11 | OPTKEY: [0, 0xFFFFFFFF] 12 | 13 | SR: 14 | EOP: 15 | NoEvent: [0, "No EOP operation occurred"] 16 | Event: [1, "An EOP event occurred"] 17 | WRPERR: 18 | NoError: [0, "No write protection error occurred"] 19 | Error: [1, "A write protection error occurred"] 20 | OPTVERR: 21 | NoError: [0, "No option and Engineering bits loading validity error occurred"] 22 | Error: [1, " An option and Engineering bits loading validity error occurred"] 23 | BSY: 24 | _read: 25 | Inactive: [0, "No write/erase operation is in progress"] 26 | Active: [1, "A write/erase operation is in progress"] 27 | 28 | CR: 29 | OBL_LAUNCH: 30 | Inactive: [0, "Force option byte loading inactive"] 31 | Active: [1, "Force option byte loading active"] 32 | EOPIE: 33 | Disabled: [0, "End of operation interrupt disabled"] 34 | Enabled: [1, "End of operation interrupt enabled"] 35 | ERRIE: 36 | Disabled: [0, "Error interrupt generation disabled"] 37 | Enabled: [1, "Error interrupt generation enabled"] 38 | OPTLOCK: 39 | Unlocked: [0, "Options is unlocked"] 40 | Locked: [1, "Options is locked"] 41 | LOCK: 42 | Unlocked: [0, "FLASH_CR register is unlocked"] 43 | Locked: [1, "FLASH_CR register is locked"] 44 | _modify: 45 | PGTSTRT: 46 | name: PGSTRT 47 | Start: [1, "Flash main memory program start"] 48 | OPTSTRT: 49 | OptionByteProgram: [1, "Option byte program start"] 50 | SER: 51 | SectorErase: [1, "Erase activated for user sectors"] 52 | MER: 53 | MassErase: [1, "Erase activated for all user sectors"] 54 | PER: 55 | PageErase: [1, "Erase activated for selected page"] 56 | PG: 57 | Program: [1, "Flash programming activated"] 58 | OPTR: 59 | nBOOT1: 60 | Clear: [0, "Select boot mode together with BOOT Pin"] 61 | Set: [1, "Select boot mode together with BOOT Pin"] 62 | NRST_MODE: 63 | NRST: [0, "Configure as NRST pin"] 64 | GPIO: [1, "Configure as GPIO pin"] 65 | WWDG_SW: 66 | Hardware: [0, "Hardware window watchdog"] 67 | Software: [1, "Software window watchdog"] 68 | _modify: 69 | IDWG_SW: 70 | name: IWDG_SW 71 | Hardware: [0, "Hardware independent watchdog"] 72 | Software: [1, "Software independent watchdog"] 73 | BORF_LEV: 74 | Level0: [0, "BOR level 0. Reset level threshold is around 1.8 V"] 75 | Level1: [1, "BOR level 1. Reset level threshold is around 2.0 V"] 76 | Level2: [2, "BOR level 2. Reset level threshold is around 2.2 V"] 77 | Level3: [3, "BOR level 3. Reset level threshold is around 2.4 V"] 78 | Level4: [4, "BOR level 4. Reset level threshold is around 2.6 V"] 79 | Level5: [5, "BOR level 5. Reset level threshold is around 2.8 V"] 80 | Level6: [6, "BOR level 6. Reset level threshold is around 3.0 V"] 81 | Level7: [7, "BOR level 7. Reset level threshold is around 3.2 V"] 82 | BOREN: 83 | Disabled: [0, "BOR disabled"] 84 | Enabled: [1, "BOR enabled"] 85 | RDP: 86 | Level0: [0xAA, "Level 0, readout protection not active"] 87 | Level2: [0xCC, "Level 2, chip readout protection active"] 88 | # The manual specifies "Others" for Level 1, 0x88 is arbitrary 89 | # Since the reset value is AA, the value for Level 1 needs to be written 90 | # so there is no conflict reading other values (unless unsafe is used) 91 | Level1: [0x88, "Level 1, memories readout protection active (writes 0x88)"] 92 | WRPR: 93 | WRP: [0, 0xFFFF] 94 | -------------------------------------------------------------------------------- /scripts/periphtemplate.py: -------------------------------------------------------------------------------- 1 | """ 2 | periphtemplate.py 3 | Copyright 2018 Adam Greig 4 | Licensed under the MIT and Apache 2.0 licenses. 5 | 6 | Generates a YAML template for describing fields in a peripheral's registers 7 | from a provided SVD file. 8 | """ 9 | 10 | import argparse 11 | import xml.etree.ElementTree as ET 12 | import re 13 | 14 | def get_field_offset_width(ftag): 15 | # Some svd files will specify a bitRange rather than 16 | # bitOffset and bitWidth 17 | if ftag.find('bitRange') != None: 18 | frange = ftag.find('bitRange').text 19 | parts = frange[1:-1].split(':') 20 | end = int(parts[0], 0) 21 | start = int(parts[1], 0) 22 | foffset = start 23 | fwidth = end - start + 1 24 | else: 25 | # some svd files will specify msb,lsb rather 26 | # then bitOffset and bitWidth 27 | if ftag.find('msb') != None: 28 | foffset = int(ftag.find('lsb').text, 0) 29 | fwidth = int(ftag.find('msb').text, 0) - foffset + 1 30 | else: 31 | foffset = int(ftag.find('bitOffset').text, 0) 32 | fwidth = int(ftag.find('bitWidth').text, 0) 33 | return (foffset, fwidth) 34 | 35 | def parse_periph(svdfile, pname): 36 | tree = ET.parse(svdfile) 37 | ptag = tree.find(".//peripheral/[name='" + pname + "']") 38 | if not ptag: 39 | print("Can't find peripheral {} in device".format(pname)) 40 | return 41 | if 'derivedFrom' in ptag.attrib: 42 | dfname = ptag.attrib['derivedFrom'] 43 | dffrom = tree.find(".//peripheral/[name='" + dfname + "']") 44 | if dffrom: 45 | ptag = dffrom 46 | else: 47 | print("Can't find derivedFrom={} for {}".format(dfname, pname)) 48 | return 49 | registers = {} 50 | for rtag in ptag.iter('register'): 51 | fields = {} 52 | rname = rtag.find('name').text 53 | roffset = int(rtag.find('addressOffset').text, 0) 54 | for ftag in rtag.iter('field'): 55 | fname = ftag.find('name').text 56 | foffset, fwidth = get_field_offset_width(ftag) 57 | fields[foffset] = {"name": fname, "offset": foffset, "width": fwidth} 58 | registers[roffset] = {"name": rname, "fields": fields} 59 | return registers 60 | 61 | 62 | def make_template(pname, registers): 63 | out = ["", '"{}":'.format(pname)] 64 | for roffset in sorted(registers.keys()): 65 | register = registers[roffset] 66 | rname = register['name'] 67 | out.append(" {}:".format(rname)) 68 | for foffset in reversed(sorted(register['fields'].keys())): 69 | field = register['fields'][foffset] 70 | fname = field['name'] 71 | fwidth = field['width'] 72 | out.append(" {}:".format(fname)) 73 | if fwidth == 1 and fname.endswith("E"): 74 | out.append(' Disabled: [0, ""]') 75 | out.append(' Enabled: [1, ""]') 76 | elif fwidth == 1 and fname.endswith("D"): 77 | out.append(' Enabled: [0, ""]') 78 | out.append(' Disabled: [1, ""]') 79 | out.append("") 80 | return "\n".join(out) 81 | 82 | 83 | def main(): 84 | parser = argparse.ArgumentParser() 85 | parser.add_argument("svdfile", help="Path to read SVD file from") 86 | parser.add_argument("peripheral", help="Name of peripheral to template") 87 | parser.add_argument("yamlfile", help="YAML file to write out") 88 | args = parser.parse_args() 89 | registers = parse_periph(args.svdfile, args.peripheral) 90 | if not registers: 91 | print("Parsing device failed") 92 | return 93 | tpl = make_template(args.peripheral, registers) 94 | with open(args.yamlfile, "w") as f: 95 | f.write(tpl) 96 | 97 | 98 | if __name__ == "__main__": 99 | main() 100 | -------------------------------------------------------------------------------- /peripherals/spi/spi_f040.yaml: -------------------------------------------------------------------------------- 1 | "SPI*": 2 | CR1: 3 | BIDIMODE: 4 | Unidirectional: [0, "2-line unidirectional data mode selected"] 5 | Bidirectional: [1, "1-line bidirectional data mode selected"] 6 | BIDIOE: 7 | OutputDisabled: [0, "Output disabled (receive-only mode)"] 8 | OutputEnabled: [1, "Output enabled (transmit-only mode)"] 9 | RXONLY: 10 | FullDuplex: [0, "Full duplex (Transmit and receive)"] 11 | OutputDisabled: [1, "Output disabled (Receive-only mode)"] 12 | SSM: 13 | Disabled: [0, "Software slave management disabled"] 14 | Enabled: [1, "Software slave management enabled"] 15 | SSI: 16 | SlaveSelected: [0, "0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 17 | SlaveNotSelected: [1, "1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 18 | LSBFIRST: 19 | MSBFirst: [0, "Data is transmitted/received with the MSB first"] 20 | LSBFirst: [1, "Data is transmitted/received with the LSB first"] 21 | SPE: 22 | Disabled: [0, "Peripheral disabled"] 23 | Enabled: [1, "Peripheral enabled"] 24 | BR: 25 | Div2: [0, "f_PCLK / 2"] 26 | Div4: [1, "f_PCLK / 4"] 27 | Div8: [2, "f_PCLK / 8"] 28 | Div16: [3, "f_PCLK / 16"] 29 | Div32: [4, "f_PCLK / 32"] 30 | Div64: [5, "f_PCLK / 64"] 31 | Div128: [6, "f_PCLK / 128"] 32 | Div256: [7, "f_PCLK / 256"] 33 | MSTR: 34 | Slave: [0, "Slave configuration"] 35 | Master: [1, "Master configuration"] 36 | CPOL: 37 | IdleLow: [0, "CK to 0 when idle"] 38 | IdleHigh: [1, "CK to 1 when idle"] 39 | CPHA: 40 | FirstEdge: [0, "The first clock transition is the first data capture edge"] 41 | SecondEdge: [1, "The second clock transition is the first data capture edge"] 42 | CR2: 43 | LDMA_TX: 44 | Even: [0, "Number of data to transfer for transmit is even"] 45 | Odd: [1, "Number of data to transfer for transmit is odd"] 46 | LDMA_RX: 47 | Even: [0, "Number of data to transfer for receive is even"] 48 | Odd: [1, "Number of data to transfer for receive is odd"] 49 | FRXTH: 50 | Half: [0, "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] 51 | Quarter: [1, "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] 52 | TXEIE: 53 | Masked: [0, "TXE interrupt masked"] 54 | NotMasked: [1, "TXE interrupt not masked"] 55 | RXNEIE: 56 | Masked: [0, "RXE interrupt masked"] 57 | NotMasked: [1, "RXE interrupt not masked"] 58 | ERRIE: 59 | Masked: [0, "Error interrupt masked"] 60 | NotMasked: [1, "Error interrupt not masked"] 61 | CLRTXFIFO: 62 | NoEffect: [0, "No Effect"] 63 | ClearTxFifo: [1, "Clear Tx Fifo"] 64 | SSOE: 65 | Disabled: [0, "SS output is disabled in master mode"] 66 | Enabled: [1, "SS output is enabled in master mode"] 67 | TXDMAEN: 68 | Disabled: [0, "Tx buffer DMA disabled"] 69 | Enabled: [1, "Tx buffer DMA enabled"] 70 | RXDMAEN: 71 | Disabled: [0, "Rx buffer DMA disabled"] 72 | Enabled: [1, "Rx buffer DMA enabled"] 73 | SR: 74 | FTLVL: 75 | _read: 76 | Empty: [0, "Tx FIFO Empty"] 77 | Quarter: [1, "Tx 1/4 FIFO"] 78 | Half: [2, "Tx 1/2 FIFO"] 79 | Full: [3, "Tx FIFO full"] 80 | FRLVL: 81 | _read: 82 | Empty: [0, "Rx FIFO Empty"] 83 | Quarter: [1, "Rx 1/4 FIFO"] 84 | Half: [2, "Rx 1/2 FIFO"] 85 | Full: [3, "Rx FIFO full"] 86 | BSY: 87 | _read: 88 | NotBusy: [0, "SPI not busy"] 89 | Busy: [1, "SPI busy"] 90 | OVR: 91 | _read: 92 | NoOverrun: [0, "No overrun occurred"] 93 | Overrun: [1, "Overrun occurred"] 94 | MODF: 95 | _read: 96 | NoFault: [0, "No mode fault occurred"] 97 | Fault: [1, "Mode fault occurred"] 98 | TXE: 99 | NotEmpty: [0, "Tx buffer not empty"] 100 | Empty: [1, "Tx buffer empty"] 101 | RXNE: 102 | Empty: [0, "Rx buffer empty"] 103 | NotEmpty: [1, "Rx buffer not empty"] 104 | DR: 105 | DR: [0, 0xFFFF] 106 | -------------------------------------------------------------------------------- /scripts/matchperipherals.py: -------------------------------------------------------------------------------- 1 | """ 2 | matchperipherals.py 3 | Copyright 2017 Adam Greig 4 | Licensed under the MIT and Apache 2.0 licenses. 5 | 6 | Finds all peripherals that match the specified device. 7 | 8 | Usage: python3 scripts/matchperipherals.py peripherals/ devices/py32f030.yaml 9 | """ 10 | 11 | import sys 12 | import yaml 13 | import fnmatch 14 | import os.path 15 | import argparse 16 | import xml.etree.ElementTree as ET 17 | 18 | from svdtools import patch 19 | 20 | 21 | def process_yamlfile(svd, yamlpath, quiet): 22 | with open(yamlpath, encoding='utf-8') as f: 23 | peripheral = yaml.safe_load(f) 24 | peripheral["_path"] = yamlpath 25 | patch.yaml_includes(peripheral) 26 | matched = True 27 | for pspec in peripheral: 28 | if not pspec.startswith("_"): 29 | peripheral[pspec]["_path"] = peripheral["_path"] 30 | try: 31 | device = patch.Device(svd) 32 | device.process_peripheral(pspec, peripheral[pspec], True) 33 | except patch.SvdPatchError as e: 34 | if not quiet: 35 | print("Couldn't match {}: {}".format(yamlpath, e)) 36 | matched = False 37 | continue 38 | return matched 39 | 40 | 41 | def process_device(device, ppath, quiet): 42 | # Load the SVD and process all modifications from the yaml 43 | # (but don't bother actually applying the enums/ranges). 44 | svdpath = patch.abspath(device["_path"], device["_svd"]) 45 | if not quiet: 46 | print("Loading SVD {} for {}".format(svdpath, device["_path"])) 47 | tree = ET.parse(svdpath) 48 | if not quiet: 49 | print("Processing existing device peripherals") 50 | already_included = patch.yaml_includes(device) 51 | patch.process_device(tree, device, False) 52 | 53 | # Now go through every YAML file we can find and see if they could be 54 | # matched against the device 55 | if not quiet: 56 | print("Matching against remaining peripherals") 57 | matches = [] 58 | if os.path.isfile(ppath): 59 | yamlpath = os.path.realpath(ppath) 60 | if yamlpath not in already_included: 61 | if process_yamlfile(tree, ppath, quiet): 62 | matches.append(ppath) 63 | else: 64 | for root, dirnames, filenames in os.walk(ppath): 65 | for filename in fnmatch.filter(filenames, "*.yaml"): 66 | yamlpath = os.path.realpath(os.path.join(root, filename)) 67 | if yamlpath in already_included: 68 | continue 69 | if process_yamlfile(tree, yamlpath, quiet): 70 | matches.append(yamlpath) 71 | return matches 72 | 73 | 74 | def main(dpath, ppath, update, quiet): 75 | with open(dpath, encoding='utf-8') as f: 76 | device = yaml.safe_load(f) 77 | if "_svd" not in device: 78 | print("Could not find _svd in device YAML, cannot proceed.") 79 | return 80 | device["_path"] = dpath 81 | matches = process_device(device, ppath, quiet) 82 | if matches: 83 | absdpath = patch.abspath(sys.argv[0], dpath) 84 | common = os.path.commonprefix([absdpath] + matches) 85 | matches = [" - ../" + match[len(common) :] for match in matches] 86 | if not quiet: 87 | print("\nMatched these new peripherals:") 88 | print("\n".join(matches)) 89 | else: 90 | print(dpath) 91 | print("\n".join(matches)) 92 | if update: 93 | print("Updating device YAML") 94 | with open(dpath, "a") as f: 95 | f.write("\n".join(matches)) 96 | f.write("\n") 97 | print() 98 | else: 99 | if not quiet: 100 | print("No new peripherals matched.\n") 101 | 102 | 103 | if __name__ == "__main__": 104 | parser = argparse.ArgumentParser() 105 | parser.add_argument('--update', action='store_true') 106 | parser.add_argument('--quiet', '-q', action='store_true') 107 | parser.add_argument("peripherals") 108 | parser.add_argument("devices", nargs="*") 109 | args = parser.parse_args() 110 | for device in args.devices: 111 | main(device, args.peripherals, args.update, args.quiet) 112 | -------------------------------------------------------------------------------- /peripherals/spi/spi_f0.yaml: -------------------------------------------------------------------------------- 1 | "SPI*": 2 | CR1: 3 | BIDIMODE: 4 | Unidirectional: [0, "2-line unidirectional data mode selected"] 5 | Bidirectional: [1, "1-line bidirectional data mode selected"] 6 | BIDIOE: 7 | OutputDisabled: [0, "Output disabled (receive-only mode)"] 8 | OutputEnabled: [1, "Output enabled (transmit-only mode)"] 9 | RXONLY: 10 | FullDuplex: [0, "Full duplex (Transmit and receive)"] 11 | OutputDisabled: [1, "Output disabled (Receive-only mode)"] 12 | SSM: 13 | Disabled: [0, "Software slave management disabled"] 14 | Enabled: [1, "Software slave management enabled"] 15 | SSI: 16 | SlaveSelected: [0, "0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 17 | SlaveNotSelected: [1, "1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] 18 | LSBFIRST: 19 | MSBFirst: [0, "Data is transmitted/received with the MSB first"] 20 | LSBFirst: [1, "Data is transmitted/received with the LSB first"] 21 | SPE: 22 | Disabled: [0, "Peripheral disabled"] 23 | Enabled: [1, "Peripheral enabled"] 24 | BR: 25 | Div2: [0, "f_PCLK / 2"] 26 | Div4: [1, "f_PCLK / 4"] 27 | Div8: [2, "f_PCLK / 8"] 28 | Div16: [3, "f_PCLK / 16"] 29 | Div32: [4, "f_PCLK / 32"] 30 | Div64: [5, "f_PCLK / 64"] 31 | Div128: [6, "f_PCLK / 128"] 32 | Div256: [7, "f_PCLK / 256"] 33 | MSTR: 34 | Slave: [0, "Slave configuration"] 35 | Master: [1, "Master configuration"] 36 | CPOL: 37 | IdleLow: [0, "CK to 0 when idle"] 38 | IdleHigh: [1, "CK to 1 when idle"] 39 | CPHA: 40 | FirstEdge: [0, "The first clock transition is the first data capture edge"] 41 | SecondEdge: [1, "The second clock transition is the first data capture edge"] 42 | CR2: 43 | SLVFM: 44 | Normal: [0, "Slave normal mode, spi clock speed less than PCLK / 4"] 45 | Fast: [1, "Slave fast mode, spi clock speed equal to PCLK / 4"] 46 | LDMA_TX: 47 | Even: [0, "Number of data to transfer for transmit is even"] 48 | Odd: [1, "Number of data to transfer for transmit is odd"] 49 | LDMA_RX: 50 | Even: [0, "Number of data to transfer for receive is even"] 51 | Odd: [1, "Number of data to transfer for receive is odd"] 52 | FRXTH: 53 | Half: [0, "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] 54 | Quarter: [1, "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] 55 | DS: 56 | EightBit: [0, "8-bit"] 57 | SixteenBit: [1, "16-bit"] 58 | TXEIE: 59 | Masked: [0, "TXE interrupt masked"] 60 | NotMasked: [1, "TXE interrupt not masked"] 61 | RXNEIE: 62 | Masked: [0, "RXE interrupt masked"] 63 | NotMasked: [1, "RXE interrupt not masked"] 64 | ERRIE: 65 | Masked: [0, "Error interrupt masked"] 66 | NotMasked: [1, "Error interrupt not masked"] 67 | SSOE: 68 | Disabled: [0, "SS output is disabled in master mode"] 69 | Enabled: [1, "SS output is enabled in master mode"] 70 | TXDMAEN: 71 | Disabled: [0, "Tx buffer DMA disabled"] 72 | Enabled: [1, "Tx buffer DMA enabled"] 73 | RXDMAEN: 74 | Disabled: [0, "Rx buffer DMA disabled"] 75 | Enabled: [1, "Rx buffer DMA enabled"] 76 | SR: 77 | FTLVL: 78 | _read: 79 | Empty: [0, "Tx FIFO Empty"] 80 | Quarter: [1, "Tx 1/4 FIFO"] 81 | Half: [2, "Tx 1/2 FIFO"] 82 | Full: [3, "Tx FIFO full"] 83 | FRLVL: 84 | _read: 85 | Empty: [0, "Rx FIFO Empty"] 86 | Quarter: [1, "Rx 1/4 FIFO"] 87 | Half: [2, "Rx 1/2 FIFO"] 88 | Full: [3, "Rx FIFO full"] 89 | BSY: 90 | _read: 91 | NotBusy: [0, "SPI not busy"] 92 | Busy: [1, "SPI busy"] 93 | OVR: 94 | _read: 95 | NoOverrun: [0, "No overrun occurred"] 96 | Overrun: [1, "Overrun occurred"] 97 | MODF: 98 | _read: 99 | NoFault: [0, "No mode fault occurred"] 100 | Fault: [1, "Mode fault occurred"] 101 | TXE: 102 | NotEmpty: [0, "Tx buffer not empty"] 103 | Empty: [1, "Tx buffer empty"] 104 | RXNE: 105 | Empty: [0, "Rx buffer empty"] 106 | NotEmpty: [1, "Rx buffer not empty"] 107 | DR: 108 | DR: [0, 0xFFFF] 109 | -------------------------------------------------------------------------------- /peripherals/i2c/i2c_f002a.yaml: -------------------------------------------------------------------------------- 1 | "I2C*": 2 | CR1: 3 | SWRST: 4 | NotReset: [0, "I2C peripheral not under reset"] 5 | Reset: [1, "I2C peripheral under reset"] 6 | POS: 7 | Current: [0, "ACK bit controls the (N)ACK of the current byte being received"] 8 | Next: [1, "ACK bit controls the (N)ACK of the next byte to be received"] 9 | ACK: 10 | NAK: [0, "No acknowledge returned"] 11 | ACK: [1, "Acknowledge returned after a byte is received"] 12 | STOP: 13 | NoStop: [0, "No Stop generation"] 14 | Stop: [1, "In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte"] 15 | START: 16 | NoStart: [0, "No Start generation"] 17 | Start: [1, "In master mode: repeated start generation, in slave mode: start generation when bus is free"] 18 | NOSTRETCH: 19 | Enabled: [0, "Clock stretching enabled"] 20 | Disabled: [1, "Clock stretching disabled"] 21 | ENGC: 22 | Disabled: [0, "General call disabled"] 23 | Enabled: [1, "General call enabled"] 24 | PE: 25 | Disabled: [0, "Peripheral disabled"] 26 | Enabled: [1, "Peripheral enabled"] 27 | 28 | CR2: 29 | ITBUFEN: 30 | Disabled: [0, "TxE=1 or RxNE=1 does not generate any interrupt"] 31 | Enabled: [1, "TxE=1 or RxNE=1 generates Event interrupt"] 32 | ITEVTEN: 33 | Disabled: [0, "Event interrupt disabled"] 34 | Enabled: [1, "Event interrupt enabled"] 35 | ITERREN: 36 | Disabled: [0, "Error interrupt disabled"] 37 | Enabled: [1, "Error interrupt enabled"] 38 | FREQ: [2, 50] 39 | 40 | OAR1: 41 | ADD: [0, 0x7F] 42 | 43 | DR: 44 | DR: [0, 0xFF] 45 | 46 | SR1: 47 | PECERR: 48 | _read: 49 | NoError: [0, "no PEC error: receiver returns ACK after PEC reception (if ACK=1)"] 50 | Error: [1, "PEC error: receiver returns NACK after PEC reception (whatever ACK)"] 51 | _W0C: 52 | Clear: [0, "Clear flag"] 53 | OVR: 54 | _read: 55 | NoOverrun: [0, "No overrun/underrun occured"] 56 | Overrun: [1, "Overrun/underrun occured"] 57 | _W0C: 58 | Clear: [0, "Clear flag"] 59 | AF: 60 | _read: 61 | NoFailure: [0, "No acknowledge failure"] 62 | Failure: [1, "Acknowledge failure"] 63 | _W0C: 64 | Clear: [0, "Clear flag"] 65 | ARLO: 66 | _read: 67 | NoLost: [0, "No Arbitration Lost detected"] 68 | Lost: [1, "Arbitration Lost detected"] 69 | _W0C: 70 | Clear: [0, "Clear flag"] 71 | BERR: 72 | _read: 73 | NoError: [0, "No misplaced Start or Stop condition"] 74 | Error: [1, "Misplaced Start or Stop condition"] 75 | _W0C: 76 | Clear: [0, "Clear flag"] 77 | _modify: 78 | TxE: 79 | name: TXE 80 | RxNE: 81 | name: RXNE 82 | TXE: 83 | NotEmpty: [0, "Data register not empty"] 84 | Empty: [1, "Data register empty"] 85 | RXNE: 86 | Empty: [0, "Data register empty"] 87 | NotEmpty: [1, "Data register not empty"] 88 | STOPF: 89 | NoStop: [0, "No Stop condition detected"] 90 | Stop: [1, "Stop condition detected"] 91 | BTF: 92 | NotFinished: [0, "Data byte transfer not done"] 93 | Finished: [1, "Data byte transfer successful"] 94 | ADDR: 95 | NotMatch: [0, "Adress mismatched or not received"] 96 | Match: [1, "Received slave address matched with one of the enabled slave addresses"] 97 | SB: 98 | NoStart: [0, "No Start condition"] 99 | Start: [1, "Start condition generated"] 100 | SR2: 101 | GENCALL: 102 | _read: 103 | NoGeneralCallRecv: [0, "Not receive general call address"] 104 | GeneralCallRecv: [1, "When ENGC=1, received a general call address"] 105 | TRA: 106 | _read: 107 | Received: [0, "Data received flag"] 108 | Transferred: [1, "Data transferred flag"] 109 | BUSY: 110 | _read: 111 | NotBusy: [0, "No communication on bus"] 112 | Busy: [1, "Bus busy"] 113 | MSL: 114 | _read: 115 | Slave: [0, "Slave mode"] 116 | Master: [1, "Master mode"] 117 | CCR: 118 | F_S: 119 | Standard: [0, "Standard mode I2C"] 120 | Fast: [1, "Fast mode I2C"] 121 | DUTY: 122 | Duty2_1: [0, "Duty cycle t_low/t_high = 2/1"] 123 | Duty16_9: [1, "Duty cycle t_low/t_high = 16/9"] 124 | CCR: [1, 0xFFF] 125 | 126 | TRISE: 127 | TRISE: [0, 0x3F] 128 | -------------------------------------------------------------------------------- /peripherals/i2c/i2c_f002b.yaml: -------------------------------------------------------------------------------- 1 | "I2C*": 2 | CR1: 3 | SWRST: 4 | NotReset: [0, "I2C peripheral not under reset"] 5 | Reset: [1, "I2C peripheral under reset"] 6 | POS: 7 | Current: [0, "ACK bit controls the (N)ACK of the current byte being received"] 8 | Next: [1, "ACK bit controls the (N)ACK of the next byte to be received"] 9 | ACK: 10 | NAK: [0, "No acknowledge returned"] 11 | ACK: [1, "Acknowledge returned after a byte is received"] 12 | STOP: 13 | NoStop: [0, "No Stop generation"] 14 | Stop: [1, "In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte"] 15 | START: 16 | NoStart: [0, "No Start generation"] 17 | Start: [1, "In master mode: repeated start generation, in slave mode: start generation when bus is free"] 18 | NOSTRETCH: 19 | Enabled: [0, "Clock stretching enabled"] 20 | Disabled: [1, "Clock stretching disabled"] 21 | ENGC: 22 | Disabled: [0, "General call disabled"] 23 | Enabled: [1, "General call enabled"] 24 | PE: 25 | Disabled: [0, "Peripheral disabled"] 26 | Enabled: [1, "Peripheral enabled"] 27 | 28 | CR2: 29 | ITBUFEN: 30 | Disabled: [0, "TxE=1 or RxNE=1 does not generate any interrupt"] 31 | Enabled: [1, "TxE=1 or RxNE=1 generates Event interrupt"] 32 | ITEVTEN: 33 | Disabled: [0, "Event interrupt disabled"] 34 | Enabled: [1, "Event interrupt enabled"] 35 | ITERREN: 36 | Disabled: [0, "Error interrupt disabled"] 37 | Enabled: [1, "Error interrupt enabled"] 38 | FREQ: [2, 50] 39 | 40 | OAR1: 41 | ADD: [0, 0x7F] 42 | 43 | DR: 44 | DR: [0, 0xFF] 45 | 46 | SR1: 47 | _add: 48 | PECERR: 49 | description: "PEC Error in reception" 50 | bitOffset: 12 51 | bitWidth: 1 52 | _read: 53 | NoError: [0, "no PEC error: receiver returns ACK after PEC reception (if ACK=1)"] 54 | Error: [1, "PEC error: receiver returns NACK after PEC reception (whatever ACK)"] 55 | _W0C: 56 | Clear: [0, "Clear flag"] 57 | OVR: 58 | _read: 59 | NoOverrun: [0, "No overrun/underrun occured"] 60 | Overrun: [1, "Overrun/underrun occured"] 61 | _W0C: 62 | Clear: [0, "Clear flag"] 63 | AF: 64 | _read: 65 | NoFailure: [0, "No acknowledge failure"] 66 | Failure: [1, "Acknowledge failure"] 67 | _W0C: 68 | Clear: [0, "Clear flag"] 69 | ARLO: 70 | _read: 71 | NoLost: [0, "No Arbitration Lost detected"] 72 | Lost: [1, "Arbitration Lost detected"] 73 | _W0C: 74 | Clear: [0, "Clear flag"] 75 | BERR: 76 | _read: 77 | NoError: [0, "No misplaced Start or Stop condition"] 78 | Error: [1, "Misplaced Start or Stop condition"] 79 | _W0C: 80 | Clear: [0, "Clear flag"] 81 | _modify: 82 | TxE: 83 | name: TXE 84 | RxNE: 85 | name: RXNE 86 | TXE: 87 | NotEmpty: [0, "Data register not empty"] 88 | Empty: [1, "Data register empty"] 89 | RXNE: 90 | Empty: [0, "Data register empty"] 91 | NotEmpty: [1, "Data register not empty"] 92 | STOPF: 93 | NoStop: [0, "No Stop condition detected"] 94 | Stop: [1, "Stop condition detected"] 95 | BTF: 96 | NotFinished: [0, "Data byte transfer not done"] 97 | Finished: [1, "Data byte transfer successful"] 98 | ADDR: 99 | NotMatch: [0, "Adress mismatched or not received"] 100 | Match: [1, "Received slave address matched with one of the enabled slave addresses"] 101 | SB: 102 | NoStart: [0, "No Start condition"] 103 | Start: [1, "Start condition generated"] 104 | SR2: 105 | GENCALL: 106 | _read: 107 | NoGeneralCallRecv: [0, "Not receive general call address"] 108 | GeneralCallRecv: [1, "When ENGC=1, received a general call address"] 109 | TRA: 110 | _read: 111 | Received: [0, "Data received flag"] 112 | Transferred: [1, "Data transferred flag"] 113 | BUSY: 114 | _read: 115 | NotBusy: [0, "No communication on bus"] 116 | Busy: [1, "Bus busy"] 117 | MSL: 118 | _read: 119 | Slave: [0, "Slave mode"] 120 | Master: [1, "Master mode"] 121 | CCR: 122 | F_S: 123 | Standard: [0, "Standard mode I2C"] 124 | Fast: [1, "Fast mode I2C"] 125 | DUTY: 126 | Duty2_1: [0, "Duty cycle t_low/t_high = 2/1"] 127 | Duty16_9: [1, "Duty cycle t_low/t_high = 16/9"] 128 | CCR: [1, 0xFFF] 129 | 130 | TRISE: 131 | TRISE: [0, 0x3F] 132 | -------------------------------------------------------------------------------- /peripherals/syscfg/syscfg_f040.yaml: -------------------------------------------------------------------------------- 1 | SYSCFG: 2 | CFGR1: 3 | MEM_MODE: 4 | MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] 5 | SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] 6 | MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] 7 | SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] 8 | "TIM?_IC*": 9 | Standard: [0, "From TIM?_CH* IO"] 10 | Comp1: [1, "From Comp 1"] 11 | Comp2: [2, "From Comp 2"] 12 | Comp3: [3, "From Comp 3"] 13 | "ETR_SRC_TIM?": 14 | GPIO: [0, "TIM*_ETR is connected to GPIO"] 15 | COMP1: [1, "TIM*_ETR is connected to COMP1"] 16 | COMP2: [2, "TIM*_ETR is connected to COMP2"] 17 | ADC: [3, "TIM*_ETR is connected to ADC"] 18 | GPIO_AHB_SEL: 19 | FastIO: [0, "Fast IO bus access to GPIO register control"] 20 | AHB: [1, "AHB bus access to GPIO register control"] 21 | CFGR2: 22 | "COMP?_OCREF_CLR_TIM*": 23 | NotUsed: [0, "COMP? output not used as TIM? ocref_clr input"] 24 | Used: [1, "COMP? output used as TIM? ocref_clr input"] 25 | "COMP?_BRK_TIM*": 26 | Disconnected: [0, "COMP? output not connect to TIM? Break input"] 27 | Connected: [1, "COMP? output connected to TIM? Break input"] 28 | PVD_LOCK: 29 | Disconnected: [0, "PVD LOCKUP output disconnected from TIM1/16/17 Break input"] 30 | Connected: [1, "PVD LOCKUP output connected to TIM1/16/17 Break input"] 31 | LOCKUP_LOCK: 32 | Disconnected: [0, "Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input"] 33 | Connected: [1, "Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input"] 34 | "CFGR[34]": 35 | "DMA?_MAP": 36 | ADC: [0, "ADC DMA requests mapped on DMA?"] 37 | SPI1_TX: [3, "SPI1_TX DMA requests mapped on DMA?"] 38 | SPI1_RX: [4, "SPI1_RX DMA requests mapped on DMA?"] 39 | SPI2_TX: [5, "SPI2_TX DMA requests mapped on DMA?"] 40 | SPI2_RX: [6, "SPI2_RX DMA requests mapped on DMA?"] 41 | USART1_TX: [7, "USART1_TX DMA requests mapped on DMA?"] 42 | USART1_RX: [8, "USART1_RX DMA requests mapped on DMA?"] 43 | USART2_TX: [9, "USART2_TX DMA requests mapped on DMA?"] 44 | USART2_RX: [10, "USART2_RX DMA requests mapped on DMA?"] 45 | USART3_TX: [11, "USART3_TX DMA requests mapped on DMA?"] 46 | USART3_RX: [12, "USART3_RX DMA requests mapped on DMA?"] 47 | USART4_TX: [13, "USART4_TX DMA requests mapped on DMA?"] 48 | USART4_RX: [14, "USART4_RX DMA requests mapped on DMA?"] 49 | I2C1_TX: [15, "I2C1_TX DMA requests mapped on DMA?"] 50 | I2C1_RX: [16, "I2C1_RX DMA requests mapped on DMA?"] 51 | I2C2_TX: [17, "I2C2_TX DMA requests mapped on DMA?"] 52 | I2C2_RX: [18, "I2C2_RX DMA requests mapped on DMA?"] 53 | TIM1_CH1: [19, "TIM1_CH1 DMA requests mapped on DMA?"] 54 | TIM1_CH2: [20, "TIM1_CH2 DMA requests mapped on DMA?"] 55 | TIM1_CH3: [21, "TIM1_CH3 DMA requests mapped on DMA?"] 56 | TIM1_CH4: [22, "TIM1_CH4 DMA requests mapped on DMA?"] 57 | TIM1_COM: [23, "TIM1_COM DMA requests mapped on DMA?"] 58 | TIM1_TRIG: [24, "TIM1_TRIG DMA requests mapped on DMA?"] 59 | TIM1_UP: [25, "TIM1_UP DMA requests mapped on DMA?"] 60 | TIM2_CH1: [26, "TIM2_CH1 DMA requests mapped on DMA?"] 61 | TIM2_CH2: [27, "TIM2_CH2 DMA requests mapped on DMA?"] 62 | TIM2_CH3: [28, "TIM2_CH3 DMA requests mapped on DMA?"] 63 | TIM2_CH4: [29, "TIM2_CH4 DMA requests mapped on DMA?"] 64 | TIM2_UP: [30, "TIM2_UP DMA requests mapped on DMA?"] 65 | TIM2_TRIG: [31, "TIM2_TRIG DMA requests mapped on DMA?"] 66 | TIM3_CH1: [32, "TIM3_CH1 DMA requests mapped on DMA?"] 67 | TIM3_CH2: [33, "TIM3_CH2 DMA requests mapped on DMA?"] 68 | TIM3_CH3: [34, "TIM3_CH3 DMA requests mapped on DMA?"] 69 | TIM3_CH4: [35, "TIM3_CH4 DMA requests mapped on DMA?"] 70 | TIM3_UP: [36, "TIM3_UP DMA requests mapped on DMA?"] 71 | TIM3_TRIG: [37, "TIM3_TRIG DMA requests mapped on DMA?"] 72 | TIM6_UP: [38, "TIM6_UP DMA requests mapped on DMA?"] 73 | TIM7_UP: [39, "TIM7_UP DMA requests mapped on DMA?"] 74 | TIM15_CH1: [40, "TIM15_CH1 DMA requests mapped on DMA?"] 75 | TIM15_CH2: [41, "TIM15_CH2 DMA requests mapped on DMA?"] 76 | TIM15_UP: [42, "TIM15_UP DMA requests mapped on DMA?"] 77 | TIM15_TRIG: [43, "TIM15_TRIG DMA requests mapped on DMA?"] 78 | TIM15_COM: [44, "TIM15_COM DMA requests mapped on DMA?"] 79 | TIM16_CH1: [45, "TIM16_CH1 DMA requests mapped on DMA?"] 80 | TIM16_UP: [46, "TIM16_UP DMA requests mapped on DMA?"] 81 | TIM17_CH1: [47, "TIM17_CH1 DMA requests mapped on DMA?"] 82 | TIM17_UP: [48, "TIM17_UP DMA requests mapped on DMA?"] 83 | LCD: [49, "LCD DMA requests mapped on DMA?"] 84 | -------------------------------------------------------------------------------- /peripherals/usart/usart_f002b.yaml: -------------------------------------------------------------------------------- 1 | "USART*": 2 | DR: 3 | DR: [0, 0x1FF] 4 | 5 | BRR: 6 | DIV_Mantissa: [0, 0xFFF] 7 | DIV_Fraction: [0, 0xF] 8 | 9 | CR1: 10 | UE: 11 | Disabled: [0, "USART prescaler and outputs disabled"] 12 | Enabled: [1, "USART enabled"] 13 | M: 14 | M8: [0, "8 data bits"] 15 | M9: [1, "9 data bits"] 16 | WAKE: 17 | IdleLine: [0, "USART wakeup on idle line"] 18 | AddressMark: [1, "USART wakeup on address mark"] 19 | PCE: 20 | Disabled: [0, "Parity control disabled"] 21 | Enabled: [1, "Parity control enabled"] 22 | PS: 23 | Even: [0, "Even parity"] 24 | Odd: [1, "Odd parity"] 25 | PEIE: 26 | Disabled: [0, "PE interrupt disabled"] 27 | Enabled: [1, "PE interrupt enabled"] 28 | TXEIE: 29 | Disabled: [0, "TXE interrupt disabled"] 30 | Enabled: [1, "TXE interrupt enabled"] 31 | TCIE: 32 | Disabled: [0, "TC interrupt disabled"] 33 | Enabled: [1, "TC interrupt enabled"] 34 | RXNEIE: 35 | Disabled: [0, "RXNE interrupt disabled"] 36 | Enabled: [1, "RXNE interrupt enabled"] 37 | IDLEIE: 38 | Disabled: [0, "IDLE interrupt disabled"] 39 | Enabled: [1, "IDLE interrupt enabled"] 40 | TE: 41 | Disabled: [0, "Transmitter disabled"] 42 | Enabled: [1, "Transmitter enabled"] 43 | RE: 44 | Disabled: [0, "Receiver disabled"] 45 | Enabled: [1, "Receiver enabled"] 46 | RWU: 47 | Active: [0, "Receiver in active mode"] 48 | Mute: [1, "Receiver in mute mode"] 49 | 50 | CR2: 51 | STOP: 52 | Stop1: [0, "1 stop bit"] 53 | Stop2: [1, "2 stop bits"] 54 | CLKEN: 55 | Disabled: [0, "CK pin disabled"] 56 | Enabled: [1, "CK pin enabled"] 57 | CPOL: 58 | Low: [0, "Steady low value on CK pin outside transmission window"] 59 | High: [1, "Steady high value on CK pin outside transmission window"] 60 | CPHA: 61 | First: [0, "The first clock transition is the first data capture edge"] 62 | Second: [1, "The second clock transition is the first data capture edge"] 63 | LBCL: 64 | NotOutput: [0, "The clock pulse of the last data bit is not output to the CK pin"] 65 | Output: [1, "The clock pulse of the last data bit is output to the CK pin"] 66 | ADD: [0, 0xF] 67 | 68 | CR3: 69 | ABRMOD: 70 | Start: [0, "Measurement of the start bit is used to detect the baud rate"] 71 | Edge: [1, "Falling edge to falling edge measurement"] 72 | Reserved1: [2, "Reserved"] 73 | Reserved2: [3, "Reserved"] 74 | ABREN: 75 | Disabled: [0, "Auto baud rate detection is disabled"] 76 | Enabled: [1, "Auto baud rate detection is enabled"] 77 | OVER8: 78 | Oversampling16: [0, "Oversampling by 16"] 79 | Oversampling8: [1, "Oversampling by 8"] 80 | CTSIE: 81 | Disabled: [0, "CTS interrupt disabled"] 82 | Enabled: [1, "CTS interrupt enabled"] 83 | CTSE: 84 | Disabled: [0, "CTS hardware flow control disabled"] 85 | Enabled: [1, "CTS hardware flow control enabled"] 86 | RTSE: 87 | Disabled: [0, "RTS hardware flow control disabled"] 88 | Enabled: [1, "RTS hardware flow control enabled"] 89 | HDSEL: 90 | FullDuplex: [0, "Half duplex mode is not selected"] 91 | HalfDuplex: [1, "Half duplex mode is selected"] 92 | EIE: 93 | Disabled: [0, "Error interrupt disabled"] 94 | Enabled: [1, "Error interrupt enabled"] 95 | SR: 96 | ABRRQ: 97 | _write: 98 | Request: [1, "Reset ABRE flag and request auto baud rate detect for next data frame"] 99 | ABRE: 100 | _read: 101 | Error: [1, "Auto baud rate error flag"] 102 | ABRF: 103 | _read: 104 | Detected: [1, "Auto baud rate flag"] 105 | CTS: 106 | _read: 107 | NotChange: [0, "CTS line not change"] 108 | Toggle: [1, "CTS line toggle"] 109 | _write: 110 | Clear: [0, "Clear CTS flag"] 111 | TXE: 112 | _read: 113 | NotEmpty: [0, "Data not transfer to shift register"] 114 | Empty: [1, "Data transferred to shift register"] 115 | TC: 116 | _read: 117 | NotComplete: [0, "Data transmit not complete"] 118 | Complete: [1, "Data transmit complete"] 119 | _write: 120 | Clear: [0, "Clear TC flag"] 121 | RXNE: 122 | _read: 123 | Empty: [0, "No data recived"] 124 | NotEmpty: [1, "Received data"] 125 | _write: 126 | Clear: [0, "Clear RXNE flag"] 127 | IDLE: 128 | _read: 129 | Busy: [0, "Idle line not detected"] 130 | Idle: [1, "Idle line detected"] 131 | ORE: 132 | NF: 133 | FE: 134 | PE: 135 | -------------------------------------------------------------------------------- /peripherals/i2c/i2c_f0.yaml: -------------------------------------------------------------------------------- 1 | "I2C*": 2 | CR1: 3 | SWRST: 4 | NotReset: [0, "I2C peripheral not under reset"] 5 | Reset: [1, "I2C peripheral under reset"] 6 | POS: 7 | Current: [0, "ACK bit controls the (N)ACK of the current byte being received"] 8 | Next: [1, "ACK bit controls the (N)ACK of the next byte to be received"] 9 | ACK: 10 | NAK: [0, "No acknowledge returned"] 11 | ACK: [1, "Acknowledge returned after a byte is received"] 12 | STOP: 13 | NoStop: [0, "No Stop generation"] 14 | Stop: [1, "In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte"] 15 | START: 16 | NoStart: [0, "No Start generation"] 17 | Start: [1, "In master mode: repeated start generation, in slave mode: start generation when bus is free"] 18 | NOSTRETCH: 19 | Enabled: [0, "Clock stretching enabled"] 20 | Disabled: [1, "Clock stretching disabled"] 21 | ENGC: 22 | Disabled: [0, "General call disabled"] 23 | Enabled: [1, "General call enabled"] 24 | PE: 25 | Disabled: [0, "Peripheral disabled"] 26 | Enabled: [1, "Peripheral enabled"] 27 | 28 | CR2: 29 | LAST: 30 | NotLast: [0, "Next DMA EOT is not the last transfer"] 31 | Last: [1, "Next DMA EOT is the last transfer"] 32 | DMAEN: 33 | Disabled: [0, "DMA requests disabled"] 34 | Enabled: [1, "DMA request enabled when TxE=1 or RxNE=1"] 35 | ITBUFEN: 36 | Disabled: [0, "TxE=1 or RxNE=1 does not generate any interrupt"] 37 | Enabled: [1, "TxE=1 or RxNE=1 generates Event interrupt"] 38 | ITEVTEN: 39 | Disabled: [0, "Event interrupt disabled"] 40 | Enabled: [1, "Event interrupt enabled"] 41 | ITERREN: 42 | Disabled: [0, "Error interrupt disabled"] 43 | Enabled: [1, "Error interrupt enabled"] 44 | FREQ: [2, 50] 45 | 46 | OAR1: 47 | ADD: [0, 0x7F] 48 | 49 | DR: 50 | DR: [0, 0xFF] 51 | 52 | SR1: 53 | PECERR: 54 | _read: 55 | NoError: [0, "no PEC error: receiver returns ACK after PEC reception (if ACK=1)"] 56 | Error: [1, "PEC error: receiver returns NACK after PEC reception (whatever ACK)"] 57 | _W0C: 58 | Clear: [0, "Clear flag"] 59 | OVR: 60 | _read: 61 | NoOverrun: [0, "No overrun/underrun occured"] 62 | Overrun: [1, "Overrun/underrun occured"] 63 | _W0C: 64 | Clear: [0, "Clear flag"] 65 | AF: 66 | _read: 67 | NoFailure: [0, "No acknowledge failure"] 68 | Failure: [1, "Acknowledge failure"] 69 | _W0C: 70 | Clear: [0, "Clear flag"] 71 | ARLO: 72 | _read: 73 | NoLost: [0, "No Arbitration Lost detected"] 74 | Lost: [1, "Arbitration Lost detected"] 75 | _W0C: 76 | Clear: [0, "Clear flag"] 77 | BERR: 78 | _read: 79 | NoError: [0, "No misplaced Start or Stop condition"] 80 | Error: [1, "Misplaced Start or Stop condition"] 81 | _W0C: 82 | Clear: [0, "Clear flag"] 83 | _modify: 84 | TxE: 85 | name: TXE 86 | RxNE: 87 | name: RXNE 88 | TXE: 89 | NotEmpty: [0, "Data register not empty"] 90 | Empty: [1, "Data register empty"] 91 | RXNE: 92 | Empty: [0, "Data register empty"] 93 | NotEmpty: [1, "Data register not empty"] 94 | STOPF: 95 | NoStop: [0, "No Stop condition detected"] 96 | Stop: [1, "Stop condition detected"] 97 | BTF: 98 | NotFinished: [0, "Data byte transfer not done"] 99 | Finished: [1, "Data byte transfer successful"] 100 | ADDR: 101 | NotMatch: [0, "Adress mismatched or not received"] 102 | Match: [1, "Received slave address matched with one of the enabled slave addresses"] 103 | SB: 104 | NoStart: [0, "No Start condition"] 105 | Start: [1, "Start condition generated"] 106 | SR2: 107 | GENCALL: 108 | _read: 109 | NoGeneralCallRecv: [0, "Not receive general call address"] 110 | GeneralCallRecv: [1, "When ENGC=1, received a general call address"] 111 | TRA: 112 | _read: 113 | Received: [0, "Data received flag"] 114 | Transferred: [1, "Data transferred flag"] 115 | BUSY: 116 | _read: 117 | NotBusy: [0, "No communication on bus"] 118 | Busy: [1, "Bus busy"] 119 | MSL: 120 | _read: 121 | Slave: [0, "Slave mode"] 122 | Master: [1, "Master mode"] 123 | CCR: 124 | F_S: 125 | Standard: [0, "Standard mode I2C"] 126 | Fast: [1, "Fast mode I2C"] 127 | DUTY: 128 | Duty2_1: [0, "Duty cycle t_low/t_high = 2/1"] 129 | Duty16_9: [1, "Duty cycle t_low/t_high = 16/9"] 130 | CCR: [1, 0xFFF] 131 | 132 | TRISE: 133 | TRISE: [0, 0x3F] 134 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | all: patch svd2rust 2 | 3 | .PHONY: extract patch crates svd2rust form check clean-rs clean-patch clean-html clean-svd clean lint mmaps 4 | .PRECIOUS: svd/%.svd .deps/%.d 5 | 6 | SHELL := /usr/bin/env bash 7 | 8 | # Path to `svd`/`svdtools` 9 | SVDTOOLS ?= svdtools 10 | 11 | CRATES ?= py32f0 12 | 13 | # All yaml files in devices/ will be used to patch an SVD 14 | YAMLS := $(foreach crate, $(CRATES), \ 15 | $(wildcard devices/$(crate)*.yaml)) 16 | 17 | # Each yaml file in devices/ exactly name-matches an SVD file in svd/ 18 | EXTRACTED_SVDS := $(patsubst devices/%.yaml, svd/%.svd, $(YAMLS)) 19 | PATCHED_SVDS := $(patsubst devices/%.yaml, svd/%.svd.patched, $(YAMLS)) 20 | FORMATTED_SVDS := $(patsubst devices/%.yaml, svd/%.svd.formatted, $(YAMLS)) 21 | 22 | # Each yaml file also corresponds to a mmap in mmaps/ 23 | MMAPS := $(patsubst devices/%.yaml, mmaps/%.mmap, $(YAMLS)) 24 | 25 | # Each device will lead to a crate/src/device/mod.rs file 26 | RUST_SRCS := $(foreach crate, $(CRATES), \ 27 | $(patsubst devices/$(crate)%.yaml, \ 28 | $(crate)/src/$(crate)%/mod.rs, \ 29 | $(wildcard devices/$(crate)*.yaml))) 30 | RUST_DIRS := $(foreach crate, $(CRATES), \ 31 | $(patsubst devices/$(crate)%.yaml, \ 32 | $(crate)/src/$(crate)%/, \ 33 | $(wildcard devices/$(crate)*.yaml))) 34 | FORM_SRCS := $(foreach crate, $(CRATES), \ 35 | $(patsubst devices/$(crate)%.yaml, \ 36 | $(crate)/src/$(crate)%/.form, \ 37 | $(wildcard devices/$(crate)*.yaml))) 38 | CHECK_SRCS := $(foreach crate, $(CRATES), \ 39 | $(patsubst devices/$(crate)%.yaml, \ 40 | $(crate)/src/$(crate)%/.check, \ 41 | $(wildcard devices/$(crate)*.yaml))) 42 | 43 | # Turn a devices/device.yaml and svd/device.svd into svd/device.svd.patched 44 | svd/%.svd.patched: devices/%.yaml svd/%.svd .deps/%.d 45 | $(SVDTOOLS) patch $< 46 | 47 | svd/%.svd.formatted: svd/%.svd.patched 48 | xmllint $< --format -o $@ 49 | 50 | # Generate mmap from patched SVD 51 | mmaps/%.mmap: svd/%.svd.patched 52 | @mkdir -p mmaps 53 | $(SVDTOOLS) mmap $< > $@ 54 | 55 | # Generates the common crate files: Cargo.toml, build.rs, src/lib.rs, README.md 56 | crates: 57 | python3 scripts/makecrates.py devices/ -y --families $(CRATES) 58 | 59 | define crate_template 60 | $(1)/src/%/mod.rs: svd/%.svd.patched $(1)/Cargo.toml 61 | mkdir -p $$(@D) 62 | cd $$(@D); svd2rust -m -g --strict --pascal_enum_values --max_cluster_size -i ../../../$$< 63 | rustfmt $$@ 64 | rm $$(@D)/build.rs 65 | mv -f $$(@D)/generic.rs $$(@D)/../ 66 | 67 | $(1)/src/%/.form: $(1)/src/%/mod.rs 68 | form -f -i $$< -o $$(@D) 69 | rm $$< 70 | mv $$(@D)/lib.rs $$< 71 | rustfmt $$< 72 | touch $$@ 73 | 74 | $(1)/src/%/.check: $(1)/src/%/mod.rs 75 | cd $(1) && cargo check --target-dir ../target/check/ --features rt,$$* 76 | touch $$@ 77 | 78 | $(1)/Cargo.toml: crates 79 | 80 | endef 81 | 82 | $(foreach crate,$(CRATES),$(eval $(call crate_template, $(crate)))) 83 | 84 | svd/%.svd: svd/.extracted ; 85 | 86 | svd/.extracted: 87 | cd svd && ./extract.sh && touch .extracted 88 | 89 | extract: $(EXTRACTED_SVDS) 90 | 91 | patch: $(PATCHED_SVDS) 92 | 93 | svd2rust: $(RUST_SRCS) crates 94 | 95 | form: $(FORM_SRCS) crates 96 | 97 | svdformat: $(FORMATTED_SVDS) 98 | 99 | check: $(CHECK_SRCS) 100 | 101 | html/index.html: $(PATCHED_SVDS) 102 | @mkdir -p html 103 | svd2html html/ $(PATCHED_SVDS) 104 | 105 | html/comparisons.html: $(PATCHED_SVDS) scripts/htmlcomparesvdall.sh scripts/htmlcomparesvd.py 106 | scripts/htmlcomparesvdall.sh 107 | 108 | html: html/index.html html/comparisons.html 109 | 110 | lint: $(PATCHED_SVDS) 111 | xmllint --schema svd/cmsis-svd.xsd --noout $(PATCHED_SVDS) 112 | 113 | mmaps: $(MMAPS) 114 | 115 | clean-rs: 116 | rm -rf $(RUST_DIRS) 117 | rm -f */src/generic.rs 118 | 119 | clean-patch: 120 | rm -f $(PATCHED_SVDS) 121 | rm -f $(FORMATTED_SVDS) 122 | 123 | clean-html: 124 | rm -rf html 125 | 126 | clean-crates: 127 | rm -rf $(CRATES) 128 | 129 | clean-svd: 130 | rm -f svd/*.svd 131 | rm -f svd/.extracted 132 | 133 | clean: clean-rs clean-patch clean-html clean-svd 134 | rm -rf .deps 135 | 136 | # As alternative to `pip install --user svdtools`: 137 | # run `make venv update-venv` and `source venv/bin/activate' 138 | venv: 139 | python3 -m venv venv 140 | 141 | update-venv: 142 | venv/bin/pip install -U pip 143 | venv/bin/pip install -U -r requirements.txt 144 | 145 | install: 146 | scripts/tool_install.sh 147 | 148 | # Generate dependencies for each device YAML 149 | .deps/%.d: devices/%.yaml 150 | @mkdir -p .deps 151 | $(SVDTOOLS) makedeps $< $@ 152 | 153 | -include .deps/* 154 | -------------------------------------------------------------------------------- /peripherals/usart/usart_f002a.yaml: -------------------------------------------------------------------------------- 1 | "USART*": 2 | DR: 3 | DR: [0, 0x1FF] 4 | 5 | BRR: 6 | DIV_Mantissa: [0, 0xFFF] 7 | DIV_Fraction: [0, 0xF] 8 | 9 | CR1: 10 | UE: 11 | Disabled: [0, "USART prescaler and outputs disabled"] 12 | Enabled: [1, "USART enabled"] 13 | M: 14 | M8: [0, "8 data bits"] 15 | M9: [1, "9 data bits"] 16 | WAKE: 17 | IdleLine: [0, "USART wakeup on idle line"] 18 | AddressMark: [1, "USART wakeup on address mark"] 19 | PCE: 20 | Disabled: [0, "Parity control disabled"] 21 | Enabled: [1, "Parity control enabled"] 22 | PS: 23 | Even: [0, "Even parity"] 24 | Odd: [1, "Odd parity"] 25 | PEIE: 26 | Disabled: [0, "PE interrupt disabled"] 27 | Enabled: [1, "PE interrupt enabled"] 28 | TXEIE: 29 | Disabled: [0, "TXE interrupt disabled"] 30 | Enabled: [1, "TXE interrupt enabled"] 31 | TCIE: 32 | Disabled: [0, "TC interrupt disabled"] 33 | Enabled: [1, "TC interrupt enabled"] 34 | RXNEIE: 35 | Disabled: [0, "RXNE interrupt disabled"] 36 | Enabled: [1, "RXNE interrupt enabled"] 37 | IDLEIE: 38 | Disabled: [0, "IDLE interrupt disabled"] 39 | Enabled: [1, "IDLE interrupt enabled"] 40 | TE: 41 | Disabled: [0, "Transmitter disabled"] 42 | Enabled: [1, "Transmitter enabled"] 43 | RE: 44 | Disabled: [0, "Receiver disabled"] 45 | Enabled: [1, "Receiver enabled"] 46 | RWU: 47 | Active: [0, "Receiver in active mode"] 48 | Mute: [1, "Receiver in mute mode"] 49 | SBK: 50 | NoBreak: [0, "No break character is transmitted"] 51 | Break: [1, "Break character transmitted"] 52 | 53 | CR2: 54 | STOP: 55 | Stop1: [0, "1 stop bit"] 56 | Stop2: [1, "2 stop bits"] 57 | CLKEN: 58 | Disabled: [0, "CK pin disabled"] 59 | Enabled: [1, "CK pin enabled"] 60 | CPOL: 61 | Low: [0, "Steady low value on CK pin outside transmission window"] 62 | High: [1, "Steady high value on CK pin outside transmission window"] 63 | CPHA: 64 | First: [0, "The first clock transition is the first data capture edge"] 65 | Second: [1, "The second clock transition is the first data capture edge"] 66 | LBCL: 67 | NotOutput: [0, "The clock pulse of the last data bit is not output to the CK pin"] 68 | Output: [1, "The clock pulse of the last data bit is output to the CK pin"] 69 | ADD: [0, 0xF] 70 | 71 | CR3: 72 | ABRMOD: 73 | Start: [0, "Measurement of the start bit is used to detect the baud rate"] 74 | Edge: [1, "Falling edge to falling edge measurement"] 75 | Reserved1: [2, "Reserved"] 76 | Reserved2: [3, "Reserved"] 77 | ABREN: 78 | Disabled: [0, "Auto baud rate detection is disabled"] 79 | Enabled: [1, "Auto baud rate detection is enabled"] 80 | OVER8: 81 | Oversampling16: [0, "Oversampling by 16"] 82 | Oversampling8: [1, "Oversampling by 8"] 83 | CTSIE: 84 | Disabled: [0, "CTS interrupt disabled"] 85 | Enabled: [1, "CTS interrupt enabled"] 86 | CTSE: 87 | Disabled: [0, "CTS hardware flow control disabled"] 88 | Enabled: [1, "CTS hardware flow control enabled"] 89 | RTSE: 90 | Disabled: [0, "RTS hardware flow control disabled"] 91 | Enabled: [1, "RTS hardware flow control enabled"] 92 | HDSEL: 93 | FullDuplex: [0, "Half duplex mode is not selected"] 94 | HalfDuplex: [1, "Half duplex mode is selected"] 95 | IRLP: 96 | Normal: [0, "Normal mode"] 97 | LowPower: [1, "Low-power mode"] 98 | IREN: 99 | Disabled: [0, "IrDA disabled"] 100 | Enabled: [1, "IrDA enabled"] 101 | EIE: 102 | Disabled: [0, "Error interrupt disabled"] 103 | Enabled: [1, "Error interrupt enabled"] 104 | SR: 105 | ABRRQ: 106 | _write: 107 | Request: [1, "Reset ABRE flag and request auto baud rate detect for next data frame"] 108 | ABRE: 109 | _read: 110 | Error: [1, "Auto baud rate error flag"] 111 | ABRF: 112 | _read: 113 | Detected: [1, "Auto baud rate flag"] 114 | CTS: 115 | _read: 116 | NotChange: [0, "CTS line not change"] 117 | Toggle: [1, "CTS line toggle"] 118 | _write: 119 | Clear: [0, "Clear CTS flag"] 120 | TXE: 121 | _read: 122 | NotEmpty: [0, "Data not transfer to shift register"] 123 | Empty: [1, "Data transferred to shift register"] 124 | TC: 125 | _read: 126 | NotComplete: [0, "Data transmit not complete"] 127 | Complete: [1, "Data transmit complete"] 128 | _write: 129 | Clear: [0, "Clear TC flag"] 130 | RXNE: 131 | _read: 132 | Empty: [0, "No data recived"] 133 | NotEmpty: [1, "Received data"] 134 | _write: 135 | Clear: [0, "Clear RXNE flag"] 136 | IDLE: 137 | _read: 138 | Busy: [0, "Idle line not detected"] 139 | Idle: [1, "Idle line detected"] 140 | ORE: 141 | NF: 142 | FE: 143 | PE: 144 | -------------------------------------------------------------------------------- /scripts/makejson.py: -------------------------------------------------------------------------------- 1 | """ 2 | makejson.py 3 | Copyright 2017 Adam Greig 4 | Licensed under the MIT and Apache 2.0 licenses. 5 | 6 | Transforms the given SVD files into a JSON format more suited for 7 | web pages. 8 | """ 9 | 10 | import os.path 11 | import argparse 12 | import xml.etree.ElementTree as ET 13 | from jinja2 import Environment, PackageLoader, select_autoescape 14 | 15 | env = Environment(loader=PackageLoader('makehtml', ''), 16 | autoescape=select_autoescape(['html'])) 17 | 18 | 19 | def generate_device_page(device): 20 | template = env.get_template('makehtml.template.html') 21 | return template.render(device=device) 22 | 23 | def get_field_offset_width(ftag): 24 | # Some svd files will specify a bitRange rather than 25 | # bitOffset and bitWidth 26 | if ftag.find('bitRange') != None: 27 | frange = ftag.find('bitRange').text 28 | parts = frange[1:-1].split(':') 29 | end = int(parts[0], 0) 30 | start = int(parts[1], 0) 31 | foffset = start 32 | fwidth = end - start + 1 33 | else: 34 | # some svd files will specify msb,lsb rather 35 | # then bitOffset and bitWidth 36 | if ftag.find('msb') != None: 37 | foffset = int(ftag.find('lsb').text, 0) 38 | fwidth = int(ftag.find('msb').text, 0) - foffset + 1 39 | else: 40 | foffset = int(ftag.find('bitOffset').text, 0) 41 | fwidth = int(ftag.find('bitWidth').text, 0) 42 | return (foffset, fwidth) 43 | 44 | def parse_device(svdfile): 45 | tree = ET.parse(svdfile) 46 | dname = tree.find('name').text 47 | peripherals = {} 48 | device_fields_total = 0 49 | device_fields_documented = 0 50 | for ptag in tree.iter('peripheral'): 51 | registers = {} 52 | peripheral_fields_total = 0 53 | peripheral_fields_documented = 0 54 | pname = ptag.find('name').text 55 | pbase = ptag.find('baseAddress').text 56 | if 'derivedFrom' in ptag.attrib: 57 | # peripherals[pname] = {"name": pname, "base": pbase} 58 | # peripherals[pname]["derivedFrom"] = ptag.attrib["derivedFrom"] 59 | continue 60 | pdesc = ptag.find('description').text 61 | for rtag in ptag.iter('register'): 62 | fields = {} 63 | register_fields_total = 0 64 | register_fields_documented = 0 65 | rname = rtag.find('name').text 66 | rdesc = rtag.find('description').text 67 | rrstv = rtag.find('resetValue').text 68 | raccs = rtag.find('access') 69 | if raccs is not None: 70 | raccs = raccs.text 71 | else: 72 | raccs = "Unspecified" 73 | roffset = int(rtag.find('addressOffset').text, 0) 74 | for ftag in rtag.iter('field'): 75 | register_fields_total += 1 76 | fname = ftag.find('name').text 77 | fdesc = ftag.find('description').text 78 | foffset, fwidth = get_field_offset_width(ftag) 79 | enum = ftag.find('enumeratedValues') 80 | if enum is not None: 81 | register_fields_documented += 1 82 | fields[fname] = {"name": fname, "offset": foffset, 83 | "width": fwidth, "description": fdesc} 84 | registers[rname] = {"name": rname, "offset": roffset, 85 | "description": rdesc, "resetValue": rrstv, 86 | "access": raccs, "fields": fields, 87 | "fields_total": register_fields_total, 88 | "fields_documented": 89 | register_fields_documented} 90 | peripheral_fields_total += register_fields_total 91 | peripheral_fields_documented += register_fields_documented 92 | peripherals[pname] = {"name": pname, "base": pbase, 93 | "description": pdesc, "registers": registers, 94 | "fields_total": peripheral_fields_total, 95 | "fields_documented": 96 | peripheral_fields_documented} 97 | device_fields_total += peripheral_fields_total 98 | device_fields_documented += peripheral_fields_documented 99 | return {"name": dname, "peripherals": peripherals, 100 | "fields_total": device_fields_total, 101 | "fields_documented": device_fields_documented} 102 | 103 | 104 | if __name__ == "__main__": 105 | parser = argparse.ArgumentParser() 106 | parser.add_argument("htmldir", help="Path to write HTML files to") 107 | parser.add_argument("svdfiles", help="Path to patched SVD files", 108 | nargs="*") 109 | args = parser.parse_args() 110 | for svdfile in args.svdfiles: 111 | print("Processing", svdfile) 112 | device = parse_device(svdfile) 113 | page = generate_device_page(device) 114 | pagename = "{}.html".format(device["name"]) 115 | with open(os.path.join(args.htmldir, pagename), "w") as f: 116 | f.write(page) 117 | -------------------------------------------------------------------------------- /peripherals/usart/usart_f0.yaml: -------------------------------------------------------------------------------- 1 | "USART*": 2 | DR: 3 | DR: [0, 0x1FF] 4 | 5 | BRR: 6 | DIV_Mantissa: [0, 0xFFF] 7 | DIV_Fraction: [0, 0xF] 8 | 9 | CR1: 10 | UE: 11 | Disabled: [0, "USART prescaler and outputs disabled"] 12 | Enabled: [1, "USART enabled"] 13 | M: 14 | M8: [0, "8 data bits"] 15 | M9: [1, "9 data bits"] 16 | WAKE: 17 | IdleLine: [0, "USART wakeup on idle line"] 18 | AddressMark: [1, "USART wakeup on address mark"] 19 | PCE: 20 | Disabled: [0, "Parity control disabled"] 21 | Enabled: [1, "Parity control enabled"] 22 | PS: 23 | Even: [0, "Even parity"] 24 | Odd: [1, "Odd parity"] 25 | PEIE: 26 | Disabled: [0, "PE interrupt disabled"] 27 | Enabled: [1, "PE interrupt enabled"] 28 | TXEIE: 29 | Disabled: [0, "TXE interrupt disabled"] 30 | Enabled: [1, "TXE interrupt enabled"] 31 | TCIE: 32 | Disabled: [0, "TC interrupt disabled"] 33 | Enabled: [1, "TC interrupt enabled"] 34 | RXNEIE: 35 | Disabled: [0, "RXNE interrupt disabled"] 36 | Enabled: [1, "RXNE interrupt enabled"] 37 | IDLEIE: 38 | Disabled: [0, "IDLE interrupt disabled"] 39 | Enabled: [1, "IDLE interrupt enabled"] 40 | TE: 41 | Disabled: [0, "Transmitter disabled"] 42 | Enabled: [1, "Transmitter enabled"] 43 | RE: 44 | Disabled: [0, "Receiver disabled"] 45 | Enabled: [1, "Receiver enabled"] 46 | RWU: 47 | Active: [0, "Receiver in active mode"] 48 | Mute: [1, "Receiver in mute mode"] 49 | SBK: 50 | NoBreak: [0, "No break character is transmitted"] 51 | Break: [1, "Break character transmitted"] 52 | 53 | CR2: 54 | STOP: 55 | Stop1: [0, "1 stop bit"] 56 | Stop2: [1, "2 stop bits"] 57 | CLKEN: 58 | Disabled: [0, "CK pin disabled"] 59 | Enabled: [1, "CK pin enabled"] 60 | CPOL: 61 | Low: [0, "Steady low value on CK pin outside transmission window"] 62 | High: [1, "Steady high value on CK pin outside transmission window"] 63 | CPHA: 64 | First: [0, "The first clock transition is the first data capture edge"] 65 | Second: [1, "The second clock transition is the first data capture edge"] 66 | LBCL: 67 | NotOutput: [0, "The clock pulse of the last data bit is not output to the CK pin"] 68 | Output: [1, "The clock pulse of the last data bit is output to the CK pin"] 69 | ADD: [0, 0xF] 70 | 71 | CR3: 72 | ABRMOD: 73 | Start: [0, "Measurement of the start bit is used to detect the baud rate"] 74 | Edge: [1, "Falling edge to falling edge measurement"] 75 | Reserved1: [2, "Reserved"] 76 | Reserved2: [3, "Reserved"] 77 | ABREN: 78 | Disabled: [0, "Auto baud rate detection is disabled"] 79 | Enabled: [1, "Auto baud rate detection is enabled"] 80 | OVER8: 81 | Oversampling16: [0, "Oversampling by 16"] 82 | Oversampling8: [1, "Oversampling by 8"] 83 | CTSIE: 84 | Disabled: [0, "CTS interrupt disabled"] 85 | Enabled: [1, "CTS interrupt enabled"] 86 | CTSE: 87 | Disabled: [0, "CTS hardware flow control disabled"] 88 | Enabled: [1, "CTS hardware flow control enabled"] 89 | RTSE: 90 | Disabled: [0, "RTS hardware flow control disabled"] 91 | Enabled: [1, "RTS hardware flow control enabled"] 92 | DMAT: 93 | Disabled: [0, "DMA mode is disabled for transmission"] 94 | Enabled: [1, "DMA mode is enabled for transmission"] 95 | DMAR: 96 | Disabled: [0, "DMA mode is disabled for reception"] 97 | Enabled: [1, "DMA mode is enabled for reception"] 98 | HDSEL: 99 | FullDuplex: [0, "Half duplex mode is not selected"] 100 | HalfDuplex: [1, "Half duplex mode is selected"] 101 | IRLP: 102 | Normal: [0, "Normal mode"] 103 | LowPower: [1, "Low-power mode"] 104 | IREN: 105 | Disabled: [0, "IrDA disabled"] 106 | Enabled: [1, "IrDA enabled"] 107 | EIE: 108 | Disabled: [0, "Error interrupt disabled"] 109 | Enabled: [1, "Error interrupt enabled"] 110 | SR: 111 | ABRRQ: 112 | _write: 113 | Request: [1, "Reset ABRE flag and request auto baud rate detect for next data frame"] 114 | ABRE: 115 | _read: 116 | Error: [1, "Auto baud rate error flag"] 117 | ABRF: 118 | _read: 119 | Detected: [1, "Auto baud rate flag"] 120 | CTS: 121 | _read: 122 | NotChange: [0, "CTS line not change"] 123 | Toggle: [1, "CTS line toggle"] 124 | _write: 125 | Clear: [0, "Clear CTS flag"] 126 | TXE: 127 | _read: 128 | NotEmpty: [0, "Data not transfer to shift register"] 129 | Empty: [1, "Data transferred to shift register"] 130 | TC: 131 | _read: 132 | NotComplete: [0, "Data transmit not complete"] 133 | Complete: [1, "Data transmit complete"] 134 | _write: 135 | Clear: [0, "Clear TC flag"] 136 | RXNE: 137 | _read: 138 | Empty: [0, "No data recived"] 139 | NotEmpty: [1, "Received data"] 140 | _write: 141 | Clear: [0, "Clear RXNE flag"] 142 | IDLE: 143 | _read: 144 | Busy: [0, "Idle line not detected"] 145 | Idle: [1, "Idle line detected"] 146 | ORE: 147 | NF: 148 | FE: 149 | PE: 150 | -------------------------------------------------------------------------------- /peripherals/rcc/rcc_f002a.yaml: -------------------------------------------------------------------------------- 1 | RCC: 2 | CR: 3 | "*ON": 4 | Off: [0, "Clock disabled"] 5 | On: [1, "Clock enabled"] 6 | HSEBYP: 7 | NotBypassed: [0, "HSE oscillator not bypassed"] 8 | Bypassed: [1, "HSE oscillator bypassed"] 9 | "*RDY": 10 | _read: 11 | NotReady: [0, "Oscillator is not stable"] 12 | Ready: [1, "Oscillator is stable"] 13 | HSIDIV: 14 | NotDivided: [0, "no HSI division requested"] 15 | Div2: [1, "HSI division by 2 requested"] 16 | Div4: [2, "HSI division by 4 requested"] 17 | Div8: [3, "HSI division by 8 requested"] 18 | Div16: [4, "HSI division by 16 requested"] 19 | Div32: [5, "HSI division by 32 requested"] 20 | Div64: [6, "HSI division by 64 requested"] 21 | Div128: [7, "HSI division by 128 requested"] 22 | ICSCR: 23 | LSI_STARTUP: 24 | Cycles4: [0, "4 LSI cycles for startup"] 25 | Cycles16: [1, "16 LSI cycles for startup"] 26 | Cycles64: [2, "64 LSI cycles for startup"] 27 | Cycles256: [3, "256 LSI cycles for startup"] 28 | LSI_TRIM: [0, 255] 29 | HSI_FS: 30 | Freq4MHz: [0, "Select internal 4 MHz oscilator"] 31 | Freq8MHz: [1, "Select internal 8 MHz oscilator"] 32 | Freq16MHz: [2, "Select internal 16 MHz oscilator"] 33 | Freq22_12MHz: [3, "Select internal 22.12 MHz oscilator"] 34 | Freq24MHz: [4, "Select internal 24 MHz oscilator"] 35 | HSI_TRIM: [0, 31] 36 | CFGR: 37 | MCOPRE: 38 | NotDivided: [0, "No division"] 39 | Div2: [1, "Division by 2"] 40 | Div4: [2, "Division by 4"] 41 | Div8: [3, "Division by 8"] 42 | Div16: [4, "Division by 16"] 43 | Div32: [5, "Division by 32"] 44 | Div64: [6, "Division by 64"] 45 | Div128: [7, "Division by 128"] 46 | MCOSEL: 47 | NoClock: [0, "No clock"] 48 | SYSCLK: [1, "SYSCLK clock selected"] 49 | Reserved: [2, "Reserved"] 50 | HSI: [3, "MSI oscillator clock selected"] 51 | HSE: [4, "HSE oscillator clock selected"] 52 | PLL: [5, "PLL clock selected"] 53 | LSI: [6, "LSI oscillator clock selected"] 54 | PPRE: 55 | NotDivided: [3, "HCLK not divided"] 56 | Div2: [4, "HCLK divided by 2"] 57 | Div4: [5, "HCLK divided by 4"] 58 | Div8: [6, "HCLK divided by 8"] 59 | Div16: [7, "HCLK divided by 16"] 60 | HPRE: 61 | NotDivided: [7, "system clock not divided"] 62 | Div2: [8, "system clock divided by 2"] 63 | Div4: [9, "system clock divided by 4"] 64 | Div8: [10, "system clock divided by 8"] 65 | Div16: [11, "system clock divided by 16"] 66 | Div64: [12, "system clock divided by 64"] 67 | Div128: [13, "system clock divided by 128"] 68 | Div256: [14, "system clock divided by 256"] 69 | Div512: [15, "system clock divided by 512"] 70 | SWS: 71 | HSISYS: [0, "HSI oscillator used as system clock"] 72 | HSE: [1, "HSE oscillator used as system clock"] 73 | PLL: [2, "PLL used as system clock"] 74 | LSI: [3, "LSI oscillator used as system clock"] 75 | SW: 76 | HSISYS: [0, "HSI oscillator used as system clock"] 77 | HSE: [1, "HSE oscillator used as system clock"] 78 | PLL: [2, "PLL used as system clock"] 79 | LSI: [3, "LSI oscillator used as system clock"] 80 | ECSCR: 81 | HSE_FREQ: 82 | Disabled: [0, "Disable HSE drive"] 83 | Freq4_8MHz: [1, "4MHz ~ 8MHz"] 84 | Freq8_16MHz: [2, "8MHz ~ 16MHz"] 85 | Freq16_32MHz: [3, "16MHz ~ 32MHz"] 86 | CIER: 87 | "*RDYIE": 88 | Disabled: [0, "Ready interrupt disabled"] 89 | Enabled: [1, "Ready interrupt enabled"] 90 | CIFR: 91 | CSSF: 92 | NoClock: [0, "No clock security interrupt caused by HSE clock failure"] 93 | Clock: [1, "Clock security interrupt caused by HSE clock failure"] 94 | "*RDYF": 95 | _read: 96 | NotInterrupted: [0, "No clock ready interrupt"] 97 | Interrupted: [1, "Clock ready interrupt"] 98 | CICR: 99 | "*SEC,*RDYC": 100 | _write: 101 | Clear: [1, "Clear interrupt flag"] 102 | IOPRSTR: 103 | "*RST": 104 | Reset: [1, "Reset I/O port"] 105 | IOPENR: 106 | "*EN": 107 | Disabled: [0, "Port clock disabled"] 108 | Enabled: [1, "Port clock enabled"] 109 | AHBRSTR: 110 | "*RST": 111 | _write: 112 | Reset: [1, "Reset the module"] 113 | "APBRSTR?": 114 | "*RST": 115 | _write: 116 | Reset: [1, "Reset the module"] 117 | AHBENR: 118 | "*EN": 119 | Disabled: [0, "Clock disabled"] 120 | Enabled: [1, "Clock enabled"] 121 | "APBENR?": 122 | "*EN": 123 | Disabled: [0, "Clock disabled"] 124 | Enabled: [1, "Clock enabled"] 125 | CCIPR: 126 | LPTIM1SEL: 127 | PCLK: [0, "APB clock selected as Timer clock"] 128 | LSI: [1, "LSI clock selected as Timer clock"] 129 | Reserved: [2, "No clock selected (Reserved)"] 130 | "COMP?SEL, PVDSEL": 131 | PCLK: [0, "APB clock selected as Timer clock"] 132 | LSC: [1, "LSC clock selected as Timer clock"] 133 | BDCR: 134 | LSCOEN: 135 | Disabled: [0, "LSCO disabled"] 136 | Enabled: [1, "LSCO enabled"] 137 | CSR: 138 | "*ON": 139 | "Off": [0, "Oscillator OFF"] 140 | "On": [1, "Oscillator ON"] 141 | "*RDY": 142 | NotReady: [0, "Oscillator not ready"] 143 | Ready: [1, "Oscillator ready"] 144 | "*RSTF": 145 | _read: 146 | NoReset: [0, "No reset has occured"] 147 | Reset: [1, "A reset has occured"] 148 | RMVF: 149 | _write: 150 | Clear: [1, "Clears the reset flag"] 151 | -------------------------------------------------------------------------------- /peripherals/rcc/rcc_f002b.yaml: -------------------------------------------------------------------------------- 1 | RCC: 2 | CR: 3 | _modify: 4 | HSEEN: 5 | name: "HSEBYP" 6 | HSEBYP: 7 | NotBypassed: [0, "HSE oscillator not bypassed"] 8 | Bypassed: [1, "HSE oscillator bypassed"] 9 | HSIRDY: 10 | _read: 11 | NotReady: [0, "Oscillator is not stable"] 12 | Ready: [1, "Oscillator is stable"] 13 | HSIDIV: 14 | NotDivided: [0, "no HSI division requested"] 15 | Div2: [1, "HSI division by 2 requested"] 16 | Div4: [2, "HSI division by 4 requested"] 17 | Div8: [3, "HSI division by 8 requested"] 18 | Div16: [4, "HSI division by 16 requested"] 19 | Div32: [5, "HSI division by 32 requested"] 20 | Div64: [6, "HSI division by 64 requested"] 21 | Div128: [7, "HSI division by 128 requested"] 22 | ICSCR: 23 | LSI_STARTUP: 24 | Cycles4: [0, "4 LSI cycles for startup"] 25 | Cycles16: [1, "16 LSI cycles for startup"] 26 | Cycles64: [2, "64 LSI cycles for startup"] 27 | Cycles256: [3, "256 LSI cycles for startup"] 28 | LSI_TRIM: [0, 255] 29 | HSI_FS: 30 | Freq4MHz: [0, "Select internal 4 MHz oscilator"] 31 | Freq8MHz: [1, "Select internal 8 MHz oscilator"] 32 | Freq16MHz: [2, "Select internal 16 MHz oscilator"] 33 | Freq22_12MHz: [3, "Select internal 22.12 MHz oscilator"] 34 | Freq24MHz: [4, "Select internal 24 MHz oscilator"] 35 | HSI_TRIM: [0, 31] 36 | CFGR: 37 | MCOPRE: 38 | NotDivided: [0, "No division"] 39 | Div2: [1, "Division by 2"] 40 | Div4: [2, "Division by 4"] 41 | Div8: [3, "Division by 8"] 42 | Div16: [4, "Division by 16"] 43 | Div32: [5, "Division by 32"] 44 | Div64: [6, "Division by 64"] 45 | Div128: [7, "Division by 128"] 46 | MCOSEL: 47 | NoClock: [0, "No clock"] 48 | SYSCLK: [1, "SYSCLK clock selected"] 49 | Reserved: [2, "Reserved"] 50 | HSI: [3, "MSI oscillator clock selected"] 51 | HSE: [4, "HSE oscillator clock selected"] 52 | PLL: [5, "PLL clock selected"] 53 | LSI: [6, "LSI oscillator clock selected"] 54 | PPRE: 55 | NotDivided: [3, "HCLK not divided"] 56 | Div2: [4, "HCLK divided by 2"] 57 | Div4: [5, "HCLK divided by 4"] 58 | Div8: [6, "HCLK divided by 8"] 59 | Div16: [7, "HCLK divided by 16"] 60 | HPRE: 61 | NotDivided: [7, "system clock not divided"] 62 | Div2: [8, "system clock divided by 2"] 63 | Div4: [9, "system clock divided by 4"] 64 | Div8: [10, "system clock divided by 8"] 65 | Div16: [11, "system clock divided by 16"] 66 | Div64: [12, "system clock divided by 64"] 67 | Div128: [13, "system clock divided by 128"] 68 | Div256: [14, "system clock divided by 256"] 69 | Div512: [15, "system clock divided by 512"] 70 | SWS: 71 | HSISYS: [0, "HSI oscillator used as system clock"] 72 | HSE: [1, "HSE oscillator used as system clock"] 73 | PLL: [2, "PLL used as system clock"] 74 | LSI: [3, "LSI oscillator used as system clock"] 75 | SW: 76 | HSISYS: [0, "HSI oscillator used as system clock"] 77 | HSE: [1, "HSE oscillator used as system clock"] 78 | PLL: [2, "PLL used as system clock"] 79 | LSI: [3, "LSI oscillator used as system clock"] 80 | ECSCR: 81 | LSE_STARTUP: 82 | Cycles4096: [0, "4096 LSE cycles for startup"] 83 | Cycles2048: [1, "2048 LSE cycles for startup"] 84 | Cycles8192: [2, "8192 LSE cycles for startup"] 85 | Immediate: [3, "No LSE startup"] 86 | LSE_DRIVER: 87 | Lowest: [0, "Lowest driver power"] 88 | Low: [1, "Low driver power"] 89 | Default: [2, "Default driver power"] 90 | Highest: [3, "Highest driver power"] 91 | CIER: 92 | "*RDYIE": 93 | Disabled: [0, "Ready interrupt disabled"] 94 | Enabled: [1, "Ready interrupt enabled"] 95 | CIFR: 96 | LSECSSF: 97 | NoClock: [0, "No clock security interrupt caused by LSE clock failure"] 98 | Clock: [1, "Clock security interrupt caused by LSE clock failure"] 99 | "*RDYF": 100 | _read: 101 | NotInterrupted: [0, "No clock ready interrupt"] 102 | Interrupted: [1, "Clock ready interrupt"] 103 | CICR: 104 | "*SEC,*RDYC": 105 | _write: 106 | Clear: [1, "Clear interrupt flag"] 107 | IOPRSTR: 108 | "*RST": 109 | Reset: [1, "Reset I/O port"] 110 | IOPENR: 111 | "*EN": 112 | Disabled: [0, "Port clock disabled"] 113 | Enabled: [1, "Port clock enabled"] 114 | AHBRSTR: 115 | "*RST": 116 | _write: 117 | Reset: [1, "Reset the module"] 118 | "APBRSTR?": 119 | "*RST": 120 | _write: 121 | Reset: [1, "Reset the module"] 122 | AHBENR: 123 | "*EN": 124 | Disabled: [0, "Clock disabled"] 125 | Enabled: [1, "Clock enabled"] 126 | "APBENR?": 127 | "*EN": 128 | Disabled: [0, "Clock disabled"] 129 | Enabled: [1, "Clock enabled"] 130 | CCIPR: 131 | LPTIM1SEL: 132 | PCLK: [0, "APB clock selected as Timer clock"] 133 | LSI: [1, "LSI clock selected as Timer clock"] 134 | Reserved: [2, "No clock selected (Reserved)"] 135 | "COMP?SEL, PVDSEL": 136 | PCLK: [0, "APB clock selected as Timer clock"] 137 | LSC: [1, "LSC clock selected as Timer clock"] 138 | BDCR: 139 | LSCOEN: 140 | Disabled: [0, "LSCO disabled"] 141 | Enabled: [1, "LSCO enabled"] 142 | CSR: 143 | "*ON": 144 | "Off": [0, "Oscillator OFF"] 145 | "On": [1, "Oscillator ON"] 146 | "*RDY": 147 | NotReady: [0, "Oscillator not ready"] 148 | Ready: [1, "Oscillator ready"] 149 | "*RSTF": 150 | _read: 151 | NoReset: [0, "No reset has occured"] 152 | Reset: [1, "A reset has occured"] 153 | RMVF: 154 | _write: 155 | Clear: [1, "Clears the reset flag"] 156 | --------------------------------------------------------------------------------