├── README.md ├── boards ├── board_files │ ├── myd-xc7z010 │ │ └── 1.0 │ │ │ ├── board.xml │ │ │ ├── myd-c7z010-s.jpg │ │ │ ├── part0_pins.xml │ │ │ └── preset.xml │ ├── zturn-7z010 │ │ └── 2.1 │ │ │ ├── board.xml │ │ │ ├── part0_pins.xml │ │ │ ├── preset.xml │ │ │ └── zturn_board.jpg │ └── zturn-7z020 │ │ └── 2.1 │ │ ├── board.xml │ │ ├── part0_pins.xml │ │ ├── preset.xml │ │ └── zturn_board.jpg └── board_parts │ └── zynq │ └── zturn-7z010 │ └── 1.0 │ ├── board_part.xml │ └── ps7.tcl ├── constraints └── system.xdc ├── pmod-cape ├── cn1_sorted ├── cn2_sorted ├── eagle │ └── pmod-cape.sch ├── zturn-pmod-cache.lib ├── zturn-pmod.bak ├── zturn-pmod.kicad_pcb ├── zturn-pmod.pro ├── zturn-pmod.sch ├── zturn.bak ├── zturn.bck ├── zturn.dcm └── zturn.lib └── sdsoc └── zturn-7z020 ├── arm-xilinx-eabi ├── lib │ └── libxil.a └── lscript.ld ├── boot ├── fsbl.elf ├── generic.readme └── standalone.bif ├── hardware └── prebuilt │ ├── bitstream.bit │ ├── export │ └── z_turn20.hdf │ ├── hwcf │ ├── apsys_0.xml │ └── partitions.xml │ └── swcf │ ├── devreg.c │ ├── devreg.h │ ├── portinfo.c │ └── portinfo.h ├── vivado ├── z_turn20.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── system.xdc │ └── sources_1 │ │ ├── bd │ │ └── z_turn │ │ │ ├── hdl │ │ │ ├── z_turn.hwdef │ │ │ ├── z_turn.v │ │ │ └── z_turn_wrapper.v │ │ │ ├── hw_handoff │ │ │ ├── z_turn.hwh │ │ │ └── z_turn_bd.tcl │ │ │ ├── ip │ │ │ ├── z_turn_proc_sys_reset1_0 │ │ │ │ ├── doc │ │ │ │ │ └── proc_sys_reset_v5_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_proc_sys_reset1_0.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_proc_sys_reset1_0.vhd │ │ │ │ ├── z_turn_proc_sys_reset1_0.upgrade_log │ │ │ │ ├── z_turn_proc_sys_reset1_0.veo │ │ │ │ ├── z_turn_proc_sys_reset1_0.xci │ │ │ │ ├── z_turn_proc_sys_reset1_0.xdc │ │ │ │ ├── z_turn_proc_sys_reset1_0.xml │ │ │ │ ├── z_turn_proc_sys_reset1_0_board.xdc │ │ │ │ └── z_turn_proc_sys_reset1_0_ooc.xdc │ │ │ ├── z_turn_proc_sys_reset_1_0 │ │ │ │ ├── doc │ │ │ │ │ └── proc_sys_reset_v5_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_proc_sys_reset_1_0.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_proc_sys_reset_1_0.vhd │ │ │ │ ├── z_turn_proc_sys_reset_1_0.upgrade_log │ │ │ │ ├── z_turn_proc_sys_reset_1_0.veo │ │ │ │ ├── z_turn_proc_sys_reset_1_0.xci │ │ │ │ ├── z_turn_proc_sys_reset_1_0.xdc │ │ │ │ ├── z_turn_proc_sys_reset_1_0.xml │ │ │ │ ├── z_turn_proc_sys_reset_1_0_board.xdc │ │ │ │ └── z_turn_proc_sys_reset_1_0_ooc.xdc │ │ │ ├── z_turn_proc_sys_reset_3_0 │ │ │ │ ├── doc │ │ │ │ │ └── proc_sys_reset_v5_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_proc_sys_reset_3_0.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_proc_sys_reset_3_0.vhd │ │ │ │ ├── z_turn_proc_sys_reset_3_0.upgrade_log │ │ │ │ ├── z_turn_proc_sys_reset_3_0.veo │ │ │ │ ├── z_turn_proc_sys_reset_3_0.xci │ │ │ │ ├── z_turn_proc_sys_reset_3_0.xdc │ │ │ │ ├── z_turn_proc_sys_reset_3_0.xml │ │ │ │ ├── z_turn_proc_sys_reset_3_0_board.xdc │ │ │ │ └── z_turn_proc_sys_reset_3_0_ooc.xdc │ │ │ ├── z_turn_processing_system7_0_0 │ │ │ │ ├── doc │ │ │ │ │ └── processing_system7_v5_5_changelog.txt │ │ │ │ ├── hdl │ │ │ │ │ └── verilog │ │ │ │ │ │ └── processing_system7_v5_5_processing_system7.v │ │ │ │ ├── processing_system7.txt │ │ │ │ ├── ps7_init.c │ │ │ │ ├── ps7_init.h │ │ │ │ ├── ps7_init.html │ │ │ │ ├── ps7_init.tcl │ │ │ │ ├── ps7_init_gpl.c │ │ │ │ ├── ps7_init_gpl.h │ │ │ │ ├── ps7_parameters.xml │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_processing_system7_0_0.v │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_processing_system7_0_0.v │ │ │ │ ├── z_turn_processing_system7_0_0.upgrade_log │ │ │ │ ├── z_turn_processing_system7_0_0.veo │ │ │ │ ├── z_turn_processing_system7_0_0.xci │ │ │ │ ├── z_turn_processing_system7_0_0.xdc │ │ │ │ └── z_turn_processing_system7_0_0.xml │ │ │ ├── z_turn_ps_7_axi_periph_0 │ │ │ │ ├── z_turn_ps_7_axi_periph_0.upgrade_log │ │ │ │ ├── z_turn_ps_7_axi_periph_0.xci │ │ │ │ └── z_turn_ps_7_axi_periph_0.xml │ │ │ ├── z_turn_ps_7_axi_periph_1 │ │ │ │ ├── z_turn_ps_7_axi_periph_1.upgrade_log │ │ │ │ ├── z_turn_ps_7_axi_periph_1.xci │ │ │ │ └── z_turn_ps_7_axi_periph_1.xml │ │ │ ├── z_turn_rst_ps_7_166M_0 │ │ │ │ ├── doc │ │ │ │ │ └── proc_sys_reset_v5_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_rst_ps_7_166M_0.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_rst_ps_7_166M_0.vhd │ │ │ │ ├── z_turn_rst_ps_7_166M_0.upgrade_log │ │ │ │ ├── z_turn_rst_ps_7_166M_0.veo │ │ │ │ ├── z_turn_rst_ps_7_166M_0.xci │ │ │ │ ├── z_turn_rst_ps_7_166M_0.xdc │ │ │ │ ├── z_turn_rst_ps_7_166M_0.xml │ │ │ │ ├── z_turn_rst_ps_7_166M_0_board.xdc │ │ │ │ └── z_turn_rst_ps_7_166M_0_ooc.xdc │ │ │ ├── z_turn_util_vector_logic_0_0 │ │ │ │ ├── doc │ │ │ │ │ └── util_vector_logic_v2_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_util_vector_logic_0_0.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_util_vector_logic_0_0.vhd │ │ │ │ ├── z_turn_util_vector_logic_0_0.upgrade_log │ │ │ │ ├── z_turn_util_vector_logic_0_0.veo │ │ │ │ ├── z_turn_util_vector_logic_0_0.xci │ │ │ │ └── z_turn_util_vector_logic_0_0.xml │ │ │ ├── z_turn_util_vector_logic_0_1 │ │ │ │ ├── doc │ │ │ │ │ └── util_vector_logic_v2_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_util_vector_logic_0_1.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_util_vector_logic_0_1.vhd │ │ │ │ ├── z_turn_util_vector_logic_0_1.upgrade_log │ │ │ │ ├── z_turn_util_vector_logic_0_1.veo │ │ │ │ ├── z_turn_util_vector_logic_0_1.xci │ │ │ │ └── z_turn_util_vector_logic_0_1.xml │ │ │ ├── z_turn_util_vector_logic_1_0 │ │ │ │ ├── doc │ │ │ │ │ └── util_vector_logic_v2_0_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_util_vector_logic_1_0.vhd │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_util_vector_logic_1_0.vhd │ │ │ │ ├── z_turn_util_vector_logic_1_0.upgrade_log │ │ │ │ ├── z_turn_util_vector_logic_1_0.veo │ │ │ │ ├── z_turn_util_vector_logic_1_0.xci │ │ │ │ └── z_turn_util_vector_logic_1_0.xml │ │ │ ├── z_turn_xlconcat_0_0 │ │ │ │ ├── doc │ │ │ │ │ └── xlconcat_v2_1_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_xlconcat_0_0.v │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_xlconcat_0_0.v │ │ │ │ ├── z_turn_xlconcat_0_0.upgrade_log │ │ │ │ ├── z_turn_xlconcat_0_0.veo │ │ │ │ ├── z_turn_xlconcat_0_0.xci │ │ │ │ └── z_turn_xlconcat_0_0.xml │ │ │ ├── z_turn_xlconcat_0_1 │ │ │ │ ├── doc │ │ │ │ │ └── xlconcat_v2_1_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_xlconcat_0_1.v │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_xlconcat_0_1.v │ │ │ │ ├── z_turn_xlconcat_0_1.upgrade_log │ │ │ │ ├── z_turn_xlconcat_0_1.veo │ │ │ │ ├── z_turn_xlconcat_0_1.xci │ │ │ │ └── z_turn_xlconcat_0_1.xml │ │ │ ├── z_turn_xlconcat_0_2 │ │ │ │ ├── doc │ │ │ │ │ └── xlconcat_v2_1_changelog.txt │ │ │ │ ├── sim │ │ │ │ │ └── z_turn_xlconcat_0_2.v │ │ │ │ ├── synth │ │ │ │ │ └── z_turn_xlconcat_0_2.v │ │ │ │ ├── z_turn_xlconcat_0_2.upgrade_log │ │ │ │ ├── z_turn_xlconcat_0_2.veo │ │ │ │ ├── z_turn_xlconcat_0_2.xci │ │ │ │ └── z_turn_xlconcat_0_2.xml │ │ │ └── z_turn_xlconcat_1_0 │ │ │ │ ├── doc │ │ │ │ └── xlconcat_v2_1_changelog.txt │ │ │ │ ├── sim │ │ │ │ └── z_turn_xlconcat_1_0.v │ │ │ │ ├── synth │ │ │ │ └── z_turn_xlconcat_1_0.v │ │ │ │ ├── z_turn_xlconcat_1_0.upgrade_log │ │ │ │ ├── z_turn_xlconcat_1_0.veo │ │ │ │ ├── z_turn_xlconcat_1_0.xci │ │ │ │ └── z_turn_xlconcat_1_0.xml │ │ │ ├── ui │ │ │ ├── bd_24d8caf0.ui │ │ │ └── bd_35e35d22.ui │ │ │ ├── z_turn.bd │ │ │ ├── z_turn.bxml │ │ │ └── z_turn_ooc.xdc │ │ └── ipshared │ │ └── xilinx.com │ │ ├── lib_cdc_v1_0 │ │ └── ea79928f │ │ │ └── hdl │ │ │ └── src │ │ │ └── vhdl │ │ │ └── cdc_sync.vhd │ │ ├── proc_sys_reset_v5_0 │ │ └── 066de7cd │ │ │ └── hdl │ │ │ └── src │ │ │ └── vhdl │ │ │ ├── lpf.vhd │ │ │ ├── proc_sys_reset.vhd │ │ │ ├── sequence.vhd │ │ │ └── upcnt_n.vhd │ │ ├── processing_system7_bfm_v2_0 │ │ └── adcdcea3 │ │ │ └── hdl │ │ │ ├── processing_system7_bfm_v2_0_afi_slave.v │ │ │ ├── processing_system7_bfm_v2_0_apis.v │ │ │ ├── processing_system7_bfm_v2_0_arb_hp0_1.v │ │ │ ├── processing_system7_bfm_v2_0_arb_hp2_3.v │ │ │ ├── processing_system7_bfm_v2_0_arb_rd.v │ │ │ ├── processing_system7_bfm_v2_0_arb_rd_4.v │ │ │ ├── processing_system7_bfm_v2_0_arb_wr.v │ │ │ ├── processing_system7_bfm_v2_0_arb_wr_4.v │ │ │ ├── processing_system7_bfm_v2_0_axi_acp.v │ │ │ ├── processing_system7_bfm_v2_0_axi_gp.v │ │ │ ├── processing_system7_bfm_v2_0_axi_hp.v │ │ │ ├── processing_system7_bfm_v2_0_axi_master.v │ │ │ ├── processing_system7_bfm_v2_0_axi_slave.v │ │ │ ├── processing_system7_bfm_v2_0_ddrc.v │ │ │ ├── processing_system7_bfm_v2_0_fmsw_gp.v │ │ │ ├── processing_system7_bfm_v2_0_gen_clock.v │ │ │ ├── processing_system7_bfm_v2_0_gen_reset.v │ │ │ ├── processing_system7_bfm_v2_0_interconnect_model.v │ │ │ ├── processing_system7_bfm_v2_0_intr_rd_mem.v │ │ │ ├── processing_system7_bfm_v2_0_intr_wr_mem.v │ │ │ ├── processing_system7_bfm_v2_0_local_params.v │ │ │ ├── processing_system7_bfm_v2_0_ocm_mem.v │ │ │ ├── processing_system7_bfm_v2_0_ocmc.v │ │ │ ├── processing_system7_bfm_v2_0_processing_system7_bfm.v │ │ │ ├── processing_system7_bfm_v2_0_reg_init.v │ │ │ ├── processing_system7_bfm_v2_0_reg_map.v │ │ │ ├── processing_system7_bfm_v2_0_reg_params.v │ │ │ ├── processing_system7_bfm_v2_0_regc.v │ │ │ ├── processing_system7_bfm_v2_0_sparse_mem.v │ │ │ ├── processing_system7_bfm_v2_0_ssw_hp.v │ │ │ └── processing_system7_bfm_v2_0_unused_ports.v │ │ ├── processing_system7_v5_5 │ │ └── ad955ff5 │ │ │ ├── fixedio.xml │ │ │ ├── fixedio_rtl.xml │ │ │ ├── hdl │ │ │ └── verilog │ │ │ │ ├── processing_system7_v5_5_atc.v │ │ │ │ ├── processing_system7_v5_5_aw_atc.v │ │ │ │ ├── processing_system7_v5_5_b_atc.v │ │ │ │ ├── processing_system7_v5_5_trace_buffer.v │ │ │ │ └── processing_system7_v5_5_w_atc.v │ │ │ ├── hpstatusctrl.xml │ │ │ ├── hpstatusctrl_rtl.xml │ │ │ ├── jtag.xml │ │ │ ├── jtag_rtl.xml │ │ │ ├── usbctrl.xml │ │ │ └── usbctrl_rtl.xml │ │ ├── util_vector_logic_v2_0 │ │ └── 5ac42227 │ │ │ └── hdl │ │ │ └── util_vector_logic.vhd │ │ └── xlconcat_v2_1 │ │ └── 21a398c4 │ │ └── xlconcat.v └── z_turn20.xpr ├── z_turn20_hw.pfm └── z_turn20_sw.pfm /README.md: -------------------------------------------------------------------------------- 1 | # Various Files & Examples for MYiR Z-turn Board 2 | 3 | ![top-view](http://www.myirtech.com/attached/image/20150129/zturntop.jpg) 4 | 5 | ## Contents 6 | 7 | This repository contains: 8 | 9 | 1. I/O constraints file (`constraints/`) 10 | 2. Board interface definition and automation (`boards/`) 11 | 3. KiCAD Pmod Adapter Board (`pmod-cape/`) 12 | 4. SDSoC Platform definition (`sdsoc/`) 13 | 5. Some simple Vivado examples (`examples/`) 14 | 15 | ## Installing 16 | 17 | For instructions on how to install the board definition files, the following wiki page can be used. 18 | 19 | https://reference.digilentinc.com/vivado:boardfiles2015 20 | 21 | Alternatively, you can add the following line to your Vivado init script (`~/.Xilinx/Vivado/init.tcl`): 22 | 23 | ```tcl 24 | set_param board.repoPaths [list “/boards/board_files”] 25 | ``` 26 | 27 | For a full description of the board definition XML schemas, please consult UG895, Appendix A *Board Interface File*. 28 | 29 | ## References & Links 30 | 31 | * [Z-turn Product Page](http://www.myirtech.com/list.asp?id=502) 32 | * [Z-turn Manuals, Schematics & Example designs](https://rwth-aachen.sciebo.de/index.php/s/f030d08ff42ee4faefcd63dc32e104bc), [new version](https://rwth-aachen.sciebo.de/index.php/s/MCzrMyyzyvRlRce) 33 | * [Z-turn Wiki](https://wiki.hackerspace.pl/projects:zturn-hackers) (unofficial, Warsaw Hackerspace) 34 | * [Zynq Channel](irc://##zynq@irc.freenode.net): ##zynq on freenode.net (inofficial, [statistics](https://dev.0l.dn42/irc/zynq/), [webchat](http://webchat.freenode.net?channels=%23%23zynq)) 35 | * [Adam Taylors Microzed Chronicles](http://git.io/vtRGd) 36 | 37 | ## License 38 | 39 | - Copyright (c) 2015, Sergiusz 'q3k' Bazański 40 | - Copyright (c) 2015-2016, Steffen 'stv0g' Vogel 41 | - Copyright (c) 2016, Saad 'SaadTiwana' Tiwana 42 | 43 | ``` 44 | All rights reserved. 45 | 46 | Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 47 | 48 | 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 49 | 50 | 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 51 | 52 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 | ``` 54 | -------------------------------------------------------------------------------- /boards/board_files/myd-xc7z010/1.0/board.xml: -------------------------------------------------------------------------------- 1 | 8 | 9 | 10 | 11 | 12 | myd-xc7z010 Board top image 13 | 14 | 15 | The myd-xc7z010 board is a cheap Zynq evaluation board from the Chinese company MYiR Technologies. 16 | 1.0 17 | 18 | 1 19 | 20 | 21 | 22 | FPGA part on the board 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /boards/board_files/myd-xc7z010/1.0/myd-c7z010-s.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/boards/board_files/myd-xc7z010/1.0/myd-c7z010-s.jpg -------------------------------------------------------------------------------- /boards/board_files/myd-xc7z010/1.0/part0_pins.xml: -------------------------------------------------------------------------------- 1 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /boards/board_files/zturn-7z010/2.1/part0_pins.xml: -------------------------------------------------------------------------------- 1 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /boards/board_files/zturn-7z010/2.1/zturn_board.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/boards/board_files/zturn-7z010/2.1/zturn_board.jpg -------------------------------------------------------------------------------- /boards/board_files/zturn-7z020/2.1/part0_pins.xml: -------------------------------------------------------------------------------- 1 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /boards/board_files/zturn-7z020/2.1/zturn_board.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/boards/board_files/zturn-7z020/2.1/zturn_board.jpg -------------------------------------------------------------------------------- /boards/board_parts/zynq/zturn-7z010/1.0/board_part.xml: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /pmod-cape/cn1_sorted: -------------------------------------------------------------------------------- 1 | 1 VDD_5V 2 | 2 GND 3 | 3 VDD_3.3V 4 | 4 GND 5 | 5 VDD18_KEY_BACKUP 6 | 6 JTAG_TCK 7 | 7 IO_L11P_T1_13 8 | 8 JTAG_TMS 9 | 9 IO_L11N_T1_13 10 | 10 JTAG_TDI 11 | 11 IO_L12P_T1_13 12 | 12 JTAG_TDO 13 | 13 IO_L12N_T1_13 14 | 14 JTAG_NTRST 15 | 15 VDDIO_13_PL 16 | 16 IO_L14P_T2_13 17 | 17 IO_L13P_T2_13 18 | 18 IO_L14N_T2_13 19 | 19 IO_L13N_T2_13 20 | 20 IO_L21P_T3_13 21 | 21 IO_L15P_T2_13 22 | 22 IO_L21N_T3_13 23 | 23 IO_L15N_T2_13 24 | 24 GND 25 | 25 GND 26 | 26 IO_L1P_T0_34 27 | 27 IO_L2P_T0_34 28 | 28 IO_L1N_T0_34 29 | 29 IO_L2N_T0_34 30 | 30 IO_L3P_T0_34 31 | 31 IO_L4P_T0_34 32 | 32 IO_L3N_T0_34 33 | 33 IO_L4N_T0_34 34 | 34 GND 35 | 35 GND 36 | 36 IO_L5P_T0_34 37 | 37 IO_L6P_T0_34 38 | 38 IO_L5N_T0_34 39 | 39 IO_L6N_T0_34 40 | 40 IO_L7P_T1_34 41 | 41 IO_L8P_T1_34 42 | 42 IO_L7N_T1_34 43 | 43 IO_L8N_T1_34 44 | 44 GND 45 | 45 IO_L11P_T1_34 46 | 46 IO_L10P_T1_34 47 | 47 IO_L11N_T1_34 48 | 48 IO_L10N_T1_34 49 | 49 VDDIO_34_PL 50 | 50 IO_L13P_T2_34 51 | 51 IO_L9P_T1_34 52 | 52 IO_L13N_T2_34 53 | 53 IO_L15P_T2_34 54 | 54 GND 55 | 55 IO_L12P_T1_34 56 | 56 IO_L15P_T2_34 57 | 57 IO_L12N_T1_34 58 | 58 IO_L15N_T2_34 59 | 59 IO_L14P_T2_34 60 | 60 IO_L17P_T2_34 61 | 61 IO_L14N_T2_34 62 | 62 IO_L17N_T2_34 63 | 63 IO_L16P_T2_34 64 | 64 IO_L19P_T3_34 65 | 65 IO_L16N_T2_34 66 | 66 IO_L19N_T3_34 67 | 67 GND 68 | 68 GND 69 | 69 IO_L18N_T2_34 70 | 70 IO_L18P_T2_34 71 | 71 IO_L20P_T3_34 72 | 72 IO_L20N_T3_34 73 | 73 IO_L21N_T3_34 74 | 74 IO_L21P_T3_34 75 | 75 IO_L22P_T3_34 76 | 76 IO_L24P_T3_34 77 | 77 IO_L22N_T3_34 78 | 78 IO_L24N_T3_34 79 | 79 IO_L23P_T3_34 80 | 80 IO_L23N_T3_34 81 | -------------------------------------------------------------------------------- /pmod-cape/cn2_sorted: -------------------------------------------------------------------------------- 1 | 1 VDD_5V 2 | 2 GND 3 | 3 VDD_3.3V 4 | 4 GND 5 | 5 XADC_INP0 6 | 6 DXP_0 7 | 7 XADC_INN0 8 | 8 DXN_0 9 | 9 XADC_VCC 10 | 10 GND 11 | 11 PS_MIO0_500 12 | 12 PS_MIO10_500 13 | 13 PS_MIO8_500 14 | 14 PS_MIO11_500 15 | 15 PS_MIO9_500 16 | 16 PS_MIO14_500 17 | 17 PS_MIO12_500 18 | 18 PS_MIO15_500 19 | 19 PS_MIO13_500 20 | 20 GND 21 | 21 GND 22 | 22 IO_L2P_T0_35 23 | 23 IO_L1P_T0_35 24 | 24 IO_L2N_T0_35 25 | 25 IO_L18N_T2_35 26 | 26 IO_L4P_T0_35 27 | 27 IO_L3P_T0_35 28 | 28 IO_L4N_T0_35 29 | 29 IO_L3N_T0_35 30 | 30 GND 31 | 31 GND 32 | 32 IO_L6P_T0_35 33 | 33 IO_L5P_T0_35 34 | 34 IO_L6N_T0_35 35 | 35 IO_L5N_T0_35 36 | 36 IO_L8P_T1_35 37 | 37 IO_L7P_T1_35 38 | 38 IO_L8N_T1_35 39 | 39 IO_L7N_T1_35 40 | 40 GND 41 | 41 GND 42 | 42 IO_L10P_T1_35 43 | 43 IO_L9P_T1_35 44 | 44 IO_L10N_T1_35 45 | 45 IO_L9N_T1_35 46 | 46 IO_L12P_T1_35 47 | 47 IO_L11P_T1_35 48 | 48 IO_L12N_T1_35 49 | 49 IO_L11N_T1_35 50 | 50 GND 51 | 51 VDDIO_35_PL 52 | 52 IO_L14P_T2_35 53 | 53 IO_L13P_35 54 | 54 IO_L14N_T2_35 55 | 55 IO_L13N_35 56 | 56 IO_L16P_T2_35 57 | 57 IO_L15P_T2_35 58 | 58 IO_L16N_T2_35 59 | 59 IO_L15N_T2_35 60 | 60 GND 61 | 61 GND 62 | 62 IO_L18P_T2_35 63 | 63 IO_L17P_T2_35 64 | 64 IO_L18N_T2_35 65 | 65 IO_L17N_T2_35 66 | 66 IO_L20P_T3_35 67 | 67 IO_L19P_T3_35 68 | 68 IO_L20N_T3_35 69 | 69 IO_L19N_T3_35 70 | 70 GND 71 | 71 GND 72 | 72 IO_L22P_T3_35 73 | 73 IO_L21P_T3_35 74 | 74 IO_L22N_T3_35 75 | 75 IO_L21N_T3_35 76 | 76 IO_L24P_T3_35 77 | 77 IO_L23P_T3_35 78 | 78 IO_L24N_T3_35 79 | 79 IO_L23N_T3_35 80 | 80 GND 81 | -------------------------------------------------------------------------------- /pmod-cape/zturn-pmod-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # C 5 | # 6 | DEF C C 0 10 N Y 1 F N 7 | F0 "C" 25 100 50 H V L CNN 8 | F1 "C" 25 -100 50 H V L CNN 9 | F2 "" 38 -150 50 H V C CNN 10 | F3 "" 0 0 50 H V C CNN 11 | $FPLIST 12 | C? 13 | C_????_* 14 | C_???? 15 | SMD*_c 16 | Capacitor* 17 | $ENDFPLIST 18 | DRAW 19 | P 2 0 1 20 -80 -30 80 -30 N 20 | P 2 0 1 20 -80 30 80 30 N 21 | X ~ 1 0 150 110 D 40 40 1 1 P 22 | X ~ 2 0 -150 110 U 40 40 1 1 P 23 | ENDDRAW 24 | ENDDEF 25 | # 26 | # ZENER 27 | # 28 | DEF ZENER D 0 40 N N 1 F N 29 | F0 "D" 0 100 50 H V C CNN 30 | F1 "ZENER" 0 -100 50 H V C CNN 31 | F2 "" 0 0 50 H V C CNN 32 | F3 "" 0 0 50 H V C CNN 33 | $FPLIST 34 | D? 35 | SO* 36 | SM* 37 | $ENDFPLIST 38 | DRAW 39 | P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N 40 | P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F 41 | X K 1 -200 0 150 R 50 50 1 1 P 42 | X A 2 200 0 150 L 50 50 1 1 P 43 | ENDDRAW 44 | ENDDEF 45 | # 46 | #End Library 47 | -------------------------------------------------------------------------------- /pmod-cape/zturn-pmod.bak: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 2 2 | -------------------------------------------------------------------------------- /pmod-cape/zturn-pmod.kicad_pcb: -------------------------------------------------------------------------------- 1 | (kicad_pcb (version 4) (host kicad "dummy file") ) 2 | -------------------------------------------------------------------------------- /pmod-cape/zturn-pmod.pro: -------------------------------------------------------------------------------- 1 | update=Dienstag, 15. März 2016 'u23' 00:23:28 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [general] 27 | version=1 28 | [eeschema] 29 | version=1 30 | LibDir= 31 | [eeschema/libraries] 32 | LibName1=power 33 | LibName2=device 34 | LibName3=transistors 35 | LibName4=conn 36 | LibName5=linear 37 | LibName6=regul 38 | LibName7=74xx 39 | LibName8=cmos4000 40 | LibName9=adc-dac 41 | LibName10=memory 42 | LibName11=xilinx 43 | LibName12=microcontrollers 44 | LibName13=dsp 45 | LibName14=microchip 46 | LibName15=analog_switches 47 | LibName16=motorola 48 | LibName17=texas 49 | LibName18=intel 50 | LibName19=audio 51 | LibName20=interface 52 | LibName21=digital-audio 53 | LibName22=philips 54 | LibName23=display 55 | LibName24=cypress 56 | LibName25=siliconi 57 | LibName26=opto 58 | LibName27=atmel 59 | LibName28=contrib 60 | LibName29=valves 61 | LibName30=zturn 62 | -------------------------------------------------------------------------------- /pmod-cape/zturn-pmod.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 2 2 | LIBS:power 3 | LIBS:device 4 | LIBS:transistors 5 | LIBS:conn 6 | LIBS:linear 7 | LIBS:regul 8 | LIBS:74xx 9 | LIBS:cmos4000 10 | LIBS:adc-dac 11 | LIBS:memory 12 | LIBS:xilinx 13 | LIBS:microcontrollers 14 | LIBS:dsp 15 | LIBS:microchip 16 | LIBS:analog_switches 17 | LIBS:motorola 18 | LIBS:texas 19 | LIBS:intel 20 | LIBS:audio 21 | LIBS:interface 22 | LIBS:digital-audio 23 | LIBS:philips 24 | LIBS:display 25 | LIBS:cypress 26 | LIBS:siliconi 27 | LIBS:opto 28 | LIBS:atmel 29 | LIBS:contrib 30 | LIBS:valves 31 | EELAYER 25 0 32 | EELAYER END 33 | $Descr A4 11693 8268 34 | encoding utf-8 35 | Sheet 1 1 36 | Title "" 37 | Date "" 38 | Rev "" 39 | Comp "" 40 | Comment1 "" 41 | Comment2 "" 42 | Comment3 "" 43 | Comment4 "" 44 | $EndDescr 45 | $Comp 46 | L C C? 47 | U 1 1 56E71EDB 48 | P 3600 2600 49 | F 0 "C?" H 3625 2700 50 0000 L CNN 50 | F 1 "C" H 3625 2500 50 0000 L CNN 51 | F 2 "" H 3638 2450 50 0000 C CNN 52 | F 3 "" H 3600 2600 50 0000 C CNN 53 | 1 3600 2600 54 | 1 0 0 -1 55 | $EndComp 56 | $Comp 57 | L ZENER D? 58 | U 1 1 56E71F0C 59 | P 4300 2600 60 | F 0 "D?" H 4300 2700 50 0000 C CNN 61 | F 1 "ZENER" H 4300 2450 50 0000 C CNN 62 | F 2 "" H 4300 2600 50 0000 C CNN 63 | F 3 "" H 4300 2600 50 0000 C CNN 64 | 1 4300 2600 65 | 1 0 0 -1 66 | $EndComp 67 | $EndSCHEMATC 68 | -------------------------------------------------------------------------------- /pmod-cape/zturn.bck: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /pmod-cape/zturn.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/arm-xilinx-eabi/lib/libxil.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/sdsoc/zturn-7z020/arm-xilinx-eabi/lib/libxil.a -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/boot/fsbl.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/sdsoc/zturn-7z020/boot/fsbl.elf -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/boot/generic.readme: -------------------------------------------------------------------------------- 1 | -= SD card boot image =- 2 | 3 | Platform: 4 | Application: 5 | 6 | 1. Copy the contents of this directory to an SD card 7 | 2. Set boot mode to SD 8 | Jumper J1 NC 9 | Jumper J2 1-2 10 | 3. Insert SD card and turn board on 11 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/boot/standalone.bif: -------------------------------------------------------------------------------- 1 | /* standalone */ 2 | the_ROM_image: 3 | { 4 | [bootloader] 5 | 6 | 7 | } 8 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/bitstream.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/sdsoc/zturn-7z020/hardware/prebuilt/bitstream.bit -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/export/z_turn20.hdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/sdsoc/zturn-7z020/hardware/prebuilt/export/z_turn20.hdf -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/hwcf/apsys_0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/hwcf/partitions.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/swcf/devreg.c: -------------------------------------------------------------------------------- 1 | /* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/devreg.c */ 2 | #include "cf_lib.h" 3 | #include "cf_request.h" 4 | #include "devreg.h" 5 | 6 | #include "stdio.h" // for getting printf 7 | #include "xlnk_core_cf.h" 8 | #include "accel_info.h" 9 | #include "axi_dma_simple_dm.h" 10 | #include "axi_lite_dm.h" 11 | 12 | axi_dma_simple_info_t _p0_datamover_0 = { 13 | .device_id = 0, 14 | .phys_base_addr = 0x80400000, 15 | .addr_range = 0x10000, 16 | .dir = XLNK_DMA_TO_DEV, 17 | }; 18 | 19 | axi_dma_simple_info_t _p0_datamover_1 = { 20 | .device_id = 1, 21 | .phys_base_addr = 0x80410000, 22 | .addr_range = 0x10000, 23 | .dir = XLNK_DMA_TO_DEV, 24 | }; 25 | 26 | axi_dma_simple_info_t _p0_datamover_2 = { 27 | .device_id = 2, 28 | .phys_base_addr = 0x80420000, 29 | .addr_range = 0x10000, 30 | .dir = XLNK_DMA_FROM_DEV, 31 | }; 32 | 33 | accel_info_t _sds__p0_mmult_0 = { 34 | .device_id = 3, 35 | .phys_base_addr = 0x83c00000, 36 | .addr_range = 0x10000, 37 | .ip_type = "axis_acc_adapter" 38 | }; 39 | 40 | void _p0_cf_register(int first) 41 | { 42 | int xlnk_init_done = cf_xlnk_open(first); 43 | if (xlnk_init_done == 0) { 44 | axi_dma_simple_register(&_p0_datamover_0); 45 | axi_dma_simple_register(&_p0_datamover_1); 46 | axi_dma_simple_register(&_p0_datamover_2); 47 | accel_register(&_sds__p0_mmult_0); 48 | cf_xlnk_init(first); 49 | } 50 | else if (xlnk_init_done <0) { 51 | fprintf(stderr, "ERROR: unable to open xlnk %d\n", xlnk_init_done); 52 | } 53 | else { 54 | } 55 | } 56 | 57 | void _p0_cf_unregister(int last) 58 | { 59 | axi_dma_simple_unregister(&_p0_datamover_0); 60 | axi_dma_simple_unregister(&_p0_datamover_1); 61 | axi_dma_simple_unregister(&_p0_datamover_2); 62 | accel_unregister(&_sds__p0_mmult_0); 63 | xlnkClose(last,NULL); 64 | } 65 | 66 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/swcf/devreg.h: -------------------------------------------------------------------------------- 1 | #ifndef _SDI_DEVREG_H 2 | #define _SDI_DEVREG_H 3 | /* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/devreg.h */ 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | void _p0_cf_register(int); 9 | void _p0_cf_unregister(int); 10 | #ifdef __cplusplus 11 | }; 12 | #endif 13 | #endif /* _SDI_DEVREG_H_ */ 14 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/swcf/portinfo.c: -------------------------------------------------------------------------------- 1 | /* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/portinfo.c */ 2 | #include "cf_lib.h" 3 | #include "cf_request.h" 4 | #include "devreg.h" 5 | 6 | #include "portinfo.h" 7 | 8 | #include "stdio.h" // for printf 9 | 10 | #include "xlnk_core_cf.h" 11 | #include "accel_info.h" 12 | #include "axi_dma_simple_dm.h" 13 | #include "axi_lite_dm.h" 14 | 15 | extern axi_dma_simple_info_t _p0_datamover_0; 16 | extern axi_dma_simple_info_t _p0_datamover_1; 17 | extern axi_dma_simple_info_t _p0_datamover_2; 18 | extern accel_info_t _sds__p0_mmult_0; 19 | 20 | axi_lite_info_t _p0_swinst_mmult_0_cmd_mmult_info = { 21 | .accel_info = &_sds__p0_mmult_0, 22 | .reg_name = "0x28" 23 | }; 24 | 25 | axi_dma_simple_channel_info_t _p0_swinst_mmult_0_A_info = { 26 | .dma_info = &_p0_datamover_1, 27 | .in_use = 0, 28 | .needs_cache_flush_invalidate = 0 29 | }; 30 | 31 | axi_dma_simple_channel_info_t _p0_swinst_mmult_0_B_info = { 32 | .dma_info = &_p0_datamover_0, 33 | .in_use = 0, 34 | .needs_cache_flush_invalidate = 0 35 | }; 36 | 37 | axi_dma_simple_channel_info_t _p0_swinst_mmult_0_C_info = { 38 | .dma_info = &_p0_datamover_2, 39 | .in_use = 0, 40 | .needs_cache_flush_invalidate = 0 41 | }; 42 | 43 | struct _p0_swblk_mmult _p0_swinst_mmult_0 = { 44 | .cmd_mmult = { .base = { 45 | .channel_info = &_p0_swinst_mmult_0_cmd_mmult_info, 46 | .open_i = &axi_lite_open, 47 | .close_i = &axi_lite_close }, 48 | .send_i = &axi_lite_send }, 49 | .A = { .base = { 50 | .channel_info = &_p0_swinst_mmult_0_A_info, 51 | .open_i = &axi_dma_simple_open, 52 | .close_i = &axi_dma_simple_close }, 53 | .send_i = &axi_dma_simple_send_i }, 54 | .B = { .base = { 55 | .channel_info = &_p0_swinst_mmult_0_B_info, 56 | .open_i = &axi_dma_simple_open, 57 | .close_i = &axi_dma_simple_close }, 58 | .send_i = &axi_dma_simple_send_i }, 59 | .C = { .base = { 60 | .channel_info = &_p0_swinst_mmult_0_C_info, 61 | .open_i = &axi_dma_simple_open, 62 | .close_i = &axi_dma_simple_close }, 63 | .receive_ref_i = 0, 64 | .receive_i = &axi_dma_simple_recv_i }, 65 | }; 66 | 67 | void _p0_cf_open_port (cf_port_base_t *port) 68 | { 69 | port->open_i(port, NULL); 70 | } 71 | 72 | void _p0_cf_framework_open(int first) 73 | { 74 | cf_context_init(); 75 | xlnkCounterMap(); 76 | _p0_cf_register(first); 77 | cf_get_current_context(); 78 | accel_open(&_sds__p0_mmult_0); 79 | _p0_cf_open_port( &_p0_swinst_mmult_0.cmd_mmult.base ); 80 | _p0_cf_open_port( &_p0_swinst_mmult_0.A.base ); 81 | _p0_cf_open_port( &_p0_swinst_mmult_0.B.base ); 82 | _p0_cf_open_port( &_p0_swinst_mmult_0.C.base ); 83 | } 84 | 85 | void _p0_cf_framework_close(int last) 86 | { 87 | cf_close_i( &_p0_swinst_mmult_0.cmd_mmult, NULL); 88 | cf_close_i( &_p0_swinst_mmult_0.A, NULL); 89 | cf_close_i( &_p0_swinst_mmult_0.B, NULL); 90 | cf_close_i( &_p0_swinst_mmult_0.C, NULL); 91 | accel_close(&_sds__p0_mmult_0); 92 | _p0_cf_unregister(last); 93 | } 94 | 95 | #define TOTAL_PARTITIONS 1 96 | int current_partition_num = 0; 97 | struct { 98 | void (*open)(int); 99 | void (*close)(int); 100 | } 101 | 102 | _ptable[TOTAL_PARTITIONS] = { 103 | {.open = &_p0_cf_framework_open, .close= &_p0_cf_framework_close}, 104 | }; 105 | 106 | void switch_to_next_partition(int partition_num) 107 | { 108 | #ifdef __linux__ 109 | if (current_partition_num != partition_num) { 110 | _ptable[current_partition_num].close(0); 111 | char buf[128]; 112 | sprintf(buf, "cat /mnt/_sds/_p%d_.bin > /dev/xdevcfg", partition_num); 113 | system(buf); 114 | _ptable[partition_num].open(0); 115 | current_partition_num = partition_num; 116 | } 117 | #endif 118 | } 119 | 120 | void init_first_partition() __attribute__ ((constructor)); 121 | void close_last_partition() __attribute__ ((destructor)); 122 | void init_first_partition() 123 | { 124 | current_partition_num = 0; 125 | _ptable[current_partition_num].open(1); 126 | } 127 | 128 | 129 | void close_last_partition() 130 | { 131 | #ifdef PERF_EST 132 | apf_perf_estimation_exit(); 133 | #endif 134 | _ptable[current_partition_num].close(1); 135 | current_partition_num = 0; 136 | } 137 | 138 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/hardware/prebuilt/swcf/portinfo.h: -------------------------------------------------------------------------------- 1 | #ifndef _SDI_PORTINFO_H 2 | #define _SDI_PORTINFO_H 3 | /* File: E:/temp/SDSoc_2015.2/z_turn20/SDDebug/_sds/p0/.cf_work/portinfo.h */ 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | struct _p0_swblk_mmult { 9 | cf_port_send_t cmd_mmult; 10 | cf_port_send_t A; 11 | cf_port_send_t B; 12 | cf_port_receive_t C; 13 | }; 14 | 15 | extern struct _p0_swblk_mmult _p0_swinst_mmult_0; 16 | void _p0_cf_framework_open(int); 17 | void _p0_cf_framework_close(int); 18 | 19 | #ifdef __cplusplus 20 | }; 21 | #endif 22 | #ifdef __cplusplus 23 | extern "C" { 24 | #endif 25 | void switch_to_next_partition(int); 26 | void init_first_partition(); 27 | void close_last_partition(); 28 | #ifdef __cplusplus 29 | }; 30 | #endif /* extern "C" */ 31 | #endif /* _SDI_PORTINFO_H_ */ 32 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.hwdef: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/q3k/zturn-stuff/26920369734302e74246972d3e155b5197891631/sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/hdl/z_turn.hwdef -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/doc/proc_sys_reset_v5_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.2: 2 | * Version 5.0 (Rev. 7) 3 | * No changes 4 | 5 | 2015.1: 6 | * Version 5.0 (Rev. 7) 7 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk 8 | * Supported devices and production status are now determined automatically, to simplify support for future devices 9 | 10 | 2014.4.1: 11 | * Version 5.0 (Rev. 6) 12 | * No changes 13 | 14 | 2014.4: 15 | * Version 5.0 (Rev. 6) 16 | * No changes 17 | 18 | 2014.3: 19 | * Version 5.0 (Rev. 6) 20 | * Modified to use new sub-cores in place of proc_common,no functional changes 21 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 22 | * Updated core to use utils.tcl, needed for board flow from common location 23 | 24 | 2014.2: 25 | * Version 5.0 (Rev. 5) 26 | * Enhanced support for IP Integrator 27 | * Board flow related updates, no functional changes 28 | 29 | 2014.1: 30 | * Version 5.0 (Rev. 4) 31 | * Internal device family name change, no functional changes 32 | 33 | 2013.4: 34 | * Version 5.0 (Rev. 3) 35 | * Added exdes.xdc file 36 | * Changed the associated resets for slowest_sync_clk 37 | * Kintex UltraScale Pre-Production support 38 | 39 | 2013.3: 40 | * Version 5.0 (Rev. 2) 41 | * Changed board flow specific parameter name as per new requirements 42 | * Added example design and demonstration testbench 43 | * Reduced warnings in synthesis and simulation 44 | * Enhanced support for IP Integrator 45 | * Added support for Cadence IES and Synopsys VCS simulators 46 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 47 | * Support for 7-series devices at Production status 48 | 49 | 2013.2: 50 | * Version 5.0 (Rev. 1) 51 | * Added BETA support for future devices. 52 | * No other RTL updates 53 | 54 | 2013.1: 55 | * Version 5.0 56 | * Updated version for 2013.1 57 | * Updated bd.tcl for board flow 58 | * No other RTL updates 59 | 60 | (c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved. 61 | 62 | This file contains confidential and proprietary information 63 | of Xilinx, Inc. and is protected under U.S. and 64 | international copyright and other intellectual property 65 | laws. 66 | 67 | DISCLAIMER 68 | This disclaimer is not a license and does not grant any 69 | rights to the materials distributed herewith. Except as 70 | otherwise provided in a valid license issued to you by 71 | Xilinx, and to the maximum extent permitted by applicable 72 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 73 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 74 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 75 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 76 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 77 | (2) Xilinx shall not be liable (whether in contract or tort, 78 | including negligence, or under any other theory of 79 | liability) for any loss or damage of any kind or nature 80 | related to, arising under or in connection with these 81 | materials, including for any direct, or any indirect, 82 | special, incidental, or consequential loss or damage 83 | (including loss of data, profits, goodwill, or any type of 84 | loss or damage suffered as a result of any action brought 85 | by a third party) even if such damage or loss was 86 | reasonably foreseeable or Xilinx had been advised of the 87 | possibility of the same. 88 | 89 | CRITICAL APPLICATIONS 90 | Xilinx products are not designed or intended to be fail- 91 | safe, or for use in any application requiring fail-safe 92 | performance, such as life-support or safety devices or 93 | systems, Class III medical devices, nuclear facilities, 94 | applications related to the deployment of airbags, or any 95 | other applications that could lead to death, personal 96 | injury, or severe property or environmental damage 97 | (individually and collectively, "Critical 98 | Applications"). Customer assumes the sole risk and 99 | liability of any use of Xilinx products in Critical 100 | Applications, subject only to applicable laws and 101 | regulations governing limitations on product liability. 102 | 103 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 104 | PART OF THIS FILE AT ALL TIMES. 105 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:43:45 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_proc_sys_reset1_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_proc_sys_reset1_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 50 | // IP Revision: 7 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_proc_sys_reset1_0 your_instance_name ( 58 | .slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk 59 | .ext_reset_in(ext_reset_in), // input wire ext_reset_in 60 | .aux_reset_in(aux_reset_in), // input wire aux_reset_in 61 | .mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst 62 | .dcm_locked(dcm_locked), // input wire dcm_locked 63 | .mb_reset(mb_reset), // output wire mb_reset 64 | .bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset 65 | .peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset 66 | .interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn 67 | .peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn 68 | ); 69 | // INST_TAG_END ------ End INSTANTIATION Template --------- 70 | 71 | // You must compile the wrapper file z_turn_proc_sys_reset1_0.v when simulating 72 | // the core, z_turn_proc_sys_reset1_0. When compiling the wrapper file, be sure to 73 | // reference the Verilog simulation library. 74 | 75 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: z_turn_proc_sys_reset1_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset1_0/z_turn_proc_sys_reset1_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk] 57 | 58 | 59 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/doc/proc_sys_reset_v5_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.2: 2 | * Version 5.0 (Rev. 7) 3 | * No changes 4 | 5 | 2015.1: 6 | * Version 5.0 (Rev. 7) 7 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk 8 | * Supported devices and production status are now determined automatically, to simplify support for future devices 9 | 10 | 2014.4.1: 11 | * Version 5.0 (Rev. 6) 12 | * No changes 13 | 14 | 2014.4: 15 | * Version 5.0 (Rev. 6) 16 | * No changes 17 | 18 | 2014.3: 19 | * Version 5.0 (Rev. 6) 20 | * Modified to use new sub-cores in place of proc_common,no functional changes 21 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 22 | * Updated core to use utils.tcl, needed for board flow from common location 23 | 24 | 2014.2: 25 | * Version 5.0 (Rev. 5) 26 | * Enhanced support for IP Integrator 27 | * Board flow related updates, no functional changes 28 | 29 | 2014.1: 30 | * Version 5.0 (Rev. 4) 31 | * Internal device family name change, no functional changes 32 | 33 | 2013.4: 34 | * Version 5.0 (Rev. 3) 35 | * Added exdes.xdc file 36 | * Changed the associated resets for slowest_sync_clk 37 | * Kintex UltraScale Pre-Production support 38 | 39 | 2013.3: 40 | * Version 5.0 (Rev. 2) 41 | * Changed board flow specific parameter name as per new requirements 42 | * Added example design and demonstration testbench 43 | * Reduced warnings in synthesis and simulation 44 | * Enhanced support for IP Integrator 45 | * Added support for Cadence IES and Synopsys VCS simulators 46 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 47 | * Support for 7-series devices at Production status 48 | 49 | 2013.2: 50 | * Version 5.0 (Rev. 1) 51 | * Added BETA support for future devices. 52 | * No other RTL updates 53 | 54 | 2013.1: 55 | * Version 5.0 56 | * Updated version for 2013.1 57 | * Updated bd.tcl for board flow 58 | * No other RTL updates 59 | 60 | (c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved. 61 | 62 | This file contains confidential and proprietary information 63 | of Xilinx, Inc. and is protected under U.S. and 64 | international copyright and other intellectual property 65 | laws. 66 | 67 | DISCLAIMER 68 | This disclaimer is not a license and does not grant any 69 | rights to the materials distributed herewith. Except as 70 | otherwise provided in a valid license issued to you by 71 | Xilinx, and to the maximum extent permitted by applicable 72 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 73 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 74 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 75 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 76 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 77 | (2) Xilinx shall not be liable (whether in contract or tort, 78 | including negligence, or under any other theory of 79 | liability) for any loss or damage of any kind or nature 80 | related to, arising under or in connection with these 81 | materials, including for any direct, or any indirect, 82 | special, incidental, or consequential loss or damage 83 | (including loss of data, profits, goodwill, or any type of 84 | loss or damage suffered as a result of any action brought 85 | by a third party) even if such damage or loss was 86 | reasonably foreseeable or Xilinx had been advised of the 87 | possibility of the same. 88 | 89 | CRITICAL APPLICATIONS 90 | Xilinx products are not designed or intended to be fail- 91 | safe, or for use in any application requiring fail-safe 92 | performance, such as life-support or safety devices or 93 | systems, Class III medical devices, nuclear facilities, 94 | applications related to the deployment of airbags, or any 95 | other applications that could lead to death, personal 96 | injury, or severe property or environmental damage 97 | (individually and collectively, "Critical 98 | Applications"). Customer assumes the sole risk and 99 | liability of any use of Xilinx products in Critical 100 | Applications, subject only to applicable laws and 101 | regulations governing limitations on product liability. 102 | 103 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 104 | PART OF THIS FILE AT ALL TIMES. 105 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:43:46 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_proc_sys_reset_1_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_proc_sys_reset_1_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 50 | // IP Revision: 7 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_proc_sys_reset_1_0 your_instance_name ( 58 | .slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk 59 | .ext_reset_in(ext_reset_in), // input wire ext_reset_in 60 | .aux_reset_in(aux_reset_in), // input wire aux_reset_in 61 | .mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst 62 | .dcm_locked(dcm_locked), // input wire dcm_locked 63 | .mb_reset(mb_reset), // output wire mb_reset 64 | .bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset 65 | .peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset 66 | .interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn 67 | .peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn 68 | ); 69 | // INST_TAG_END ------ End INSTANTIATION Template --------- 70 | 71 | // You must compile the wrapper file z_turn_proc_sys_reset_1_0.v when simulating 72 | // the core, z_turn_proc_sys_reset_1_0. When compiling the wrapper file, be sure to 73 | // reference the Verilog simulation library. 74 | 75 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: z_turn_proc_sys_reset_1_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_1_0/z_turn_proc_sys_reset_1_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 5 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk] 57 | 58 | 59 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/doc/proc_sys_reset_v5_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.2: 2 | * Version 5.0 (Rev. 7) 3 | * No changes 4 | 5 | 2015.1: 6 | * Version 5.0 (Rev. 7) 7 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk 8 | * Supported devices and production status are now determined automatically, to simplify support for future devices 9 | 10 | 2014.4.1: 11 | * Version 5.0 (Rev. 6) 12 | * No changes 13 | 14 | 2014.4: 15 | * Version 5.0 (Rev. 6) 16 | * No changes 17 | 18 | 2014.3: 19 | * Version 5.0 (Rev. 6) 20 | * Modified to use new sub-cores in place of proc_common,no functional changes 21 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 22 | * Updated core to use utils.tcl, needed for board flow from common location 23 | 24 | 2014.2: 25 | * Version 5.0 (Rev. 5) 26 | * Enhanced support for IP Integrator 27 | * Board flow related updates, no functional changes 28 | 29 | 2014.1: 30 | * Version 5.0 (Rev. 4) 31 | * Internal device family name change, no functional changes 32 | 33 | 2013.4: 34 | * Version 5.0 (Rev. 3) 35 | * Added exdes.xdc file 36 | * Changed the associated resets for slowest_sync_clk 37 | * Kintex UltraScale Pre-Production support 38 | 39 | 2013.3: 40 | * Version 5.0 (Rev. 2) 41 | * Changed board flow specific parameter name as per new requirements 42 | * Added example design and demonstration testbench 43 | * Reduced warnings in synthesis and simulation 44 | * Enhanced support for IP Integrator 45 | * Added support for Cadence IES and Synopsys VCS simulators 46 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 47 | * Support for 7-series devices at Production status 48 | 49 | 2013.2: 50 | * Version 5.0 (Rev. 1) 51 | * Added BETA support for future devices. 52 | * No other RTL updates 53 | 54 | 2013.1: 55 | * Version 5.0 56 | * Updated version for 2013.1 57 | * Updated bd.tcl for board flow 58 | * No other RTL updates 59 | 60 | (c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved. 61 | 62 | This file contains confidential and proprietary information 63 | of Xilinx, Inc. and is protected under U.S. and 64 | international copyright and other intellectual property 65 | laws. 66 | 67 | DISCLAIMER 68 | This disclaimer is not a license and does not grant any 69 | rights to the materials distributed herewith. Except as 70 | otherwise provided in a valid license issued to you by 71 | Xilinx, and to the maximum extent permitted by applicable 72 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 73 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 74 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 75 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 76 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 77 | (2) Xilinx shall not be liable (whether in contract or tort, 78 | including negligence, or under any other theory of 79 | liability) for any loss or damage of any kind or nature 80 | related to, arising under or in connection with these 81 | materials, including for any direct, or any indirect, 82 | special, incidental, or consequential loss or damage 83 | (including loss of data, profits, goodwill, or any type of 84 | loss or damage suffered as a result of any action brought 85 | by a third party) even if such damage or loss was 86 | reasonably foreseeable or Xilinx had been advised of the 87 | possibility of the same. 88 | 89 | CRITICAL APPLICATIONS 90 | Xilinx products are not designed or intended to be fail- 91 | safe, or for use in any application requiring fail-safe 92 | performance, such as life-support or safety devices or 93 | systems, Class III medical devices, nuclear facilities, 94 | applications related to the deployment of airbags, or any 95 | other applications that could lead to death, personal 96 | injury, or severe property or environmental damage 97 | (individually and collectively, "Critical 98 | Applications"). Customer assumes the sole risk and 99 | liability of any use of Xilinx products in Critical 100 | Applications, subject only to applicable laws and 101 | regulations governing limitations on product liability. 102 | 103 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 104 | PART OF THIS FILE AT ALL TIMES. 105 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:43:47 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_proc_sys_reset_3_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_proc_sys_reset_3_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 50 | // IP Revision: 7 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_proc_sys_reset_3_0 your_instance_name ( 58 | .slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk 59 | .ext_reset_in(ext_reset_in), // input wire ext_reset_in 60 | .aux_reset_in(aux_reset_in), // input wire aux_reset_in 61 | .mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst 62 | .dcm_locked(dcm_locked), // input wire dcm_locked 63 | .mb_reset(mb_reset), // output wire mb_reset 64 | .bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset 65 | .peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset 66 | .interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn 67 | .peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn 68 | ); 69 | // INST_TAG_END ------ End INSTANTIATION Template --------- 70 | 71 | // You must compile the wrapper file z_turn_proc_sys_reset_3_0.v when simulating 72 | // the core, z_turn_proc_sys_reset_3_0. When compiling the wrapper file, be sure to 73 | // reference the Verilog simulation library. 74 | 75 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: z_turn_proc_sys_reset_3_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_proc_sys_reset_3_0/z_turn_proc_sys_reset_3_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 6 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk] 57 | 58 | 59 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/processing_system7.txt: -------------------------------------------------------------------------------- 1 | // 2 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_processing_system7_0_0/z_turn_processing_system7_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:12 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_processing_system7_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 1)) to current project options. 16 | 17 | 2. Upgrade messages 18 | ------------------- 19 | 20 | WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5 21 | WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5 22 | 23 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_0/z_turn_ps_7_axi_periph_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:15 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_ps_7_axi_periph_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_ps_7_axi_periph_0 (xilinx.com:ip:axi_interconnect:2.1 (Rev. 6)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_ps_7_axi_periph_1/z_turn_ps_7_axi_periph_1.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:16 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_ps_7_axi_periph_1' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_ps_7_axi_periph_1 (xilinx.com:ip:axi_interconnect:2.1 (Rev. 6)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/doc/proc_sys_reset_v5_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.2: 2 | * Version 5.0 (Rev. 7) 3 | * No changes 4 | 5 | 2015.1: 6 | * Version 5.0 (Rev. 7) 7 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk 8 | * Supported devices and production status are now determined automatically, to simplify support for future devices 9 | 10 | 2014.4.1: 11 | * Version 5.0 (Rev. 6) 12 | * No changes 13 | 14 | 2014.4: 15 | * Version 5.0 (Rev. 6) 16 | * No changes 17 | 18 | 2014.3: 19 | * Version 5.0 (Rev. 6) 20 | * Modified to use new sub-cores in place of proc_common,no functional changes 21 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 22 | * Updated core to use utils.tcl, needed for board flow from common location 23 | 24 | 2014.2: 25 | * Version 5.0 (Rev. 5) 26 | * Enhanced support for IP Integrator 27 | * Board flow related updates, no functional changes 28 | 29 | 2014.1: 30 | * Version 5.0 (Rev. 4) 31 | * Internal device family name change, no functional changes 32 | 33 | 2013.4: 34 | * Version 5.0 (Rev. 3) 35 | * Added exdes.xdc file 36 | * Changed the associated resets for slowest_sync_clk 37 | * Kintex UltraScale Pre-Production support 38 | 39 | 2013.3: 40 | * Version 5.0 (Rev. 2) 41 | * Changed board flow specific parameter name as per new requirements 42 | * Added example design and demonstration testbench 43 | * Reduced warnings in synthesis and simulation 44 | * Enhanced support for IP Integrator 45 | * Added support for Cadence IES and Synopsys VCS simulators 46 | * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability 47 | * Support for 7-series devices at Production status 48 | 49 | 2013.2: 50 | * Version 5.0 (Rev. 1) 51 | * Added BETA support for future devices. 52 | * No other RTL updates 53 | 54 | 2013.1: 55 | * Version 5.0 56 | * Updated version for 2013.1 57 | * Updated bd.tcl for board flow 58 | * No other RTL updates 59 | 60 | (c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved. 61 | 62 | This file contains confidential and proprietary information 63 | of Xilinx, Inc. and is protected under U.S. and 64 | international copyright and other intellectual property 65 | laws. 66 | 67 | DISCLAIMER 68 | This disclaimer is not a license and does not grant any 69 | rights to the materials distributed herewith. Except as 70 | otherwise provided in a valid license issued to you by 71 | Xilinx, and to the maximum extent permitted by applicable 72 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 73 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 74 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 75 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 76 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 77 | (2) Xilinx shall not be liable (whether in contract or tort, 78 | including negligence, or under any other theory of 79 | liability) for any loss or damage of any kind or nature 80 | related to, arising under or in connection with these 81 | materials, including for any direct, or any indirect, 82 | special, incidental, or consequential loss or damage 83 | (including loss of data, profits, goodwill, or any type of 84 | loss or damage suffered as a result of any action brought 85 | by a third party) even if such damage or loss was 86 | reasonably foreseeable or Xilinx had been advised of the 87 | possibility of the same. 88 | 89 | CRITICAL APPLICATIONS 90 | Xilinx products are not designed or intended to be fail- 91 | safe, or for use in any application requiring fail-safe 92 | performance, such as life-support or safety devices or 93 | systems, Class III medical devices, nuclear facilities, 94 | applications related to the deployment of airbags, or any 95 | other applications that could lead to death, personal 96 | injury, or severe property or environmental damage 97 | (individually and collectively, "Critical 98 | Applications"). Customer assumes the sole risk and 99 | liability of any use of Xilinx products in Critical 100 | Applications, subject only to applicable laws and 101 | regulations governing limitations on product liability. 102 | 103 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 104 | PART OF THIS FILE AT ALL TIMES. 105 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:17 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_rst_ps_7_166M_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_rst_ps_7_166M_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 7)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 50 | // IP Revision: 7 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_rst_ps_7_166M_0 your_instance_name ( 58 | .slowest_sync_clk(slowest_sync_clk), // input wire slowest_sync_clk 59 | .ext_reset_in(ext_reset_in), // input wire ext_reset_in 60 | .aux_reset_in(aux_reset_in), // input wire aux_reset_in 61 | .mb_debug_sys_rst(mb_debug_sys_rst), // input wire mb_debug_sys_rst 62 | .dcm_locked(dcm_locked), // input wire dcm_locked 63 | .mb_reset(mb_reset), // output wire mb_reset 64 | .bus_struct_reset(bus_struct_reset), // output wire [0 : 0] bus_struct_reset 65 | .peripheral_reset(peripheral_reset), // output wire [0 : 0] peripheral_reset 66 | .interconnect_aresetn(interconnect_aresetn), // output wire [0 : 0] interconnect_aresetn 67 | .peripheral_aresetn(peripheral_aresetn) // output wire [0 : 0] peripheral_aresetn 68 | ); 69 | // INST_TAG_END ------ End INSTANTIATION Template --------- 70 | 71 | // You must compile the wrapper file z_turn_rst_ps_7_166M_0.v when simulating 72 | // the core, z_turn_rst_ps_7_166M_0. When compiling the wrapper file, be sure to 73 | // reference the Verilog simulation library. 74 | 75 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: z_turn_rst_ps_7_166M_0.xdc 3 | # (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | 49 | set_false_path -to [get_pins -hier *cdc_to*/D] 50 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_rst_ps_7_166M_0/z_turn_rst_ps_7_166M_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2015 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 20 -name slowest_sync_clk [get_ports slowest_sync_clk] 56 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports slowest_sync_clk] 57 | 58 | 59 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/doc/util_vector_logic_v2_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4: 2 | * Version 2.0 3 | * Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0) 4 | * Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0 5 | 6 | 2014.1: 7 | * Version 1.0 (Rev. 2) 8 | * Updated the vhdl library name from work to util_vector_logic_v1_0 9 | 10 | 11 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 12 | 13 | This file contains confidential and proprietary information 14 | of Xilinx, Inc. and is protected under U.S. and 15 | international copyright and other intellectual property 16 | laws. 17 | 18 | DISCLAIMER 19 | This disclaimer is not a license and does not grant any 20 | rights to the materials distributed herewith. Except as 21 | otherwise provided in a valid license issued to you by 22 | Xilinx, and to the maximum extent permitted by applicable 23 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 24 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 25 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 26 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 27 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 28 | (2) Xilinx shall not be liable (whether in contract or tort, 29 | including negligence, or under any other theory of 30 | liability) for any loss or damage of any kind or nature 31 | related to, arising under or in connection with these 32 | materials, including for any direct, or any indirect, 33 | special, incidental, or consequential loss or damage 34 | (including loss of data, profits, goodwill, or any type of 35 | loss or damage suffered as a result of any action brought 36 | by a third party) even if such damage or loss was 37 | reasonably foreseeable or Xilinx had been advised of the 38 | possibility of the same. 39 | 40 | CRITICAL APPLICATIONS 41 | Xilinx products are not designed or intended to be fail- 42 | safe, or for use in any application requiring fail-safe 43 | performance, such as life-support or safety devices or 44 | systems, Class III medical devices, nuclear facilities, 45 | applications related to the deployment of airbags, or any 46 | other applications that could lead to death, personal 47 | injury, or severe property or environmental damage 48 | (individually and collectively, "Critical 49 | Applications"). Customer assumes the sole risk and 50 | liability of any use of Xilinx products in Critical 51 | Applications, subject only to applicable laws and 52 | regulations governing limitations on product liability. 53 | 54 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 55 | PART OF THIS FILE AT ALL TIMES. 56 | 57 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/sim/z_turn_util_vector_logic_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | -- IP Revision: 0 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY util_vector_logic_v2_0; 57 | USE util_vector_logic_v2_0.util_vector_logic; 58 | 59 | ENTITY z_turn_util_vector_logic_0_0 IS 60 | PORT ( 61 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 62 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 63 | ); 64 | END z_turn_util_vector_logic_0_0; 65 | 66 | ARCHITECTURE z_turn_util_vector_logic_0_0_arch OF z_turn_util_vector_logic_0_0 IS 67 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes"; 69 | 70 | COMPONENT util_vector_logic IS 71 | GENERIC ( 72 | C_OPERATION : STRING; 73 | C_SIZE : INTEGER 74 | ); 75 | PORT ( 76 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 77 | Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 78 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 79 | ); 80 | END COMPONENT util_vector_logic; 81 | BEGIN 82 | U0 : util_vector_logic 83 | GENERIC MAP ( 84 | C_OPERATION => "not", 85 | C_SIZE => 1 86 | ) 87 | PORT MAP ( 88 | Op1 => Op1, 89 | Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 90 | Res => Res 91 | ); 92 | END z_turn_util_vector_logic_0_0_arch; 93 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/synth/z_turn_util_vector_logic_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | -- IP Revision: 0 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY util_vector_logic_v2_0; 57 | USE util_vector_logic_v2_0.util_vector_logic; 58 | 59 | ENTITY z_turn_util_vector_logic_0_0 IS 60 | PORT ( 61 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 62 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 63 | ); 64 | END z_turn_util_vector_logic_0_0; 65 | 66 | ARCHITECTURE z_turn_util_vector_logic_0_0_arch OF z_turn_util_vector_logic_0_0 IS 67 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes"; 69 | 70 | COMPONENT util_vector_logic IS 71 | GENERIC ( 72 | C_OPERATION : STRING; 73 | C_SIZE : INTEGER 74 | ); 75 | PORT ( 76 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 77 | Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 78 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 79 | ); 80 | END COMPONENT util_vector_logic; 81 | ATTRIBUTE X_CORE_INFO : STRING; 82 | ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2"; 83 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 84 | ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_0_0_arch : ARCHITECTURE IS "z_turn_util_vector_logic_0_0,util_vector_logic,{}"; 85 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 86 | ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_0_0_arch: ARCHITECTURE IS "z_turn_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}"; 87 | BEGIN 88 | U0 : util_vector_logic 89 | GENERIC MAP ( 90 | C_OPERATION => "not", 91 | C_SIZE => 1 92 | ) 93 | PORT MAP ( 94 | Op1 => Op1, 95 | Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 96 | Res => Res 97 | ); 98 | END z_turn_util_vector_logic_0_0_arch; 99 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:18 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_util_vector_logic_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_util_vector_logic_0_0 (xilinx.com:ip:util_vector_logic:2.0) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | // IP Revision: 0 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_util_vector_logic_0_0 your_instance_name ( 58 | .Op1(Op1), // input wire [0 : 0] Op1 59 | .Res(Res) // output wire [0 : 0] Res 60 | ); 61 | // INST_TAG_END ------ End INSTANTIATION Template --------- 62 | 63 | // You must compile the wrapper file z_turn_util_vector_logic_0_0.v when simulating 64 | // the core, z_turn_util_vector_logic_0_0. When compiling the wrapper file, be sure to 65 | // reference the Verilog simulation library. 66 | 67 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_0/z_turn_util_vector_logic_0_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | z_turn_util_vector_logic_0_0 10 | 11 | 12 | 1 13 | not 14 | z_turn_util_vector_logic_0_0 15 | not 16 | 1 17 | zynq 18 | xc7z020 19 | clg400 20 | -1 21 | C 22 | 23 | VERILOG 24 | MIXED 25 | TRUE 26 | TRUE 27 | 28 | TRUE 29 | 2015.2 30 | 0 31 | OUT_OF_CONTEXT 32 | 33 | . 34 | ../../../../ipshared 35 | IP_Integrator 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/doc/util_vector_logic_v2_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4: 2 | * Version 2.0 3 | * Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0) 4 | * Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0 5 | 6 | 2014.1: 7 | * Version 1.0 (Rev. 2) 8 | * Updated the vhdl library name from work to util_vector_logic_v1_0 9 | 10 | 11 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 12 | 13 | This file contains confidential and proprietary information 14 | of Xilinx, Inc. and is protected under U.S. and 15 | international copyright and other intellectual property 16 | laws. 17 | 18 | DISCLAIMER 19 | This disclaimer is not a license and does not grant any 20 | rights to the materials distributed herewith. Except as 21 | otherwise provided in a valid license issued to you by 22 | Xilinx, and to the maximum extent permitted by applicable 23 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 24 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 25 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 26 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 27 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 28 | (2) Xilinx shall not be liable (whether in contract or tort, 29 | including negligence, or under any other theory of 30 | liability) for any loss or damage of any kind or nature 31 | related to, arising under or in connection with these 32 | materials, including for any direct, or any indirect, 33 | special, incidental, or consequential loss or damage 34 | (including loss of data, profits, goodwill, or any type of 35 | loss or damage suffered as a result of any action brought 36 | by a third party) even if such damage or loss was 37 | reasonably foreseeable or Xilinx had been advised of the 38 | possibility of the same. 39 | 40 | CRITICAL APPLICATIONS 41 | Xilinx products are not designed or intended to be fail- 42 | safe, or for use in any application requiring fail-safe 43 | performance, such as life-support or safety devices or 44 | systems, Class III medical devices, nuclear facilities, 45 | applications related to the deployment of airbags, or any 46 | other applications that could lead to death, personal 47 | injury, or severe property or environmental damage 48 | (individually and collectively, "Critical 49 | Applications"). Customer assumes the sole risk and 50 | liability of any use of Xilinx products in Critical 51 | Applications, subject only to applicable laws and 52 | regulations governing limitations on product liability. 53 | 54 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 55 | PART OF THIS FILE AT ALL TIMES. 56 | 57 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/sim/z_turn_util_vector_logic_0_1.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | -- IP Revision: 0 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY util_vector_logic_v2_0; 57 | USE util_vector_logic_v2_0.util_vector_logic; 58 | 59 | ENTITY z_turn_util_vector_logic_0_1 IS 60 | PORT ( 61 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 62 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 63 | ); 64 | END z_turn_util_vector_logic_0_1; 65 | 66 | ARCHITECTURE z_turn_util_vector_logic_0_1_arch OF z_turn_util_vector_logic_0_1 IS 67 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "yes"; 69 | 70 | COMPONENT util_vector_logic IS 71 | GENERIC ( 72 | C_OPERATION : STRING; 73 | C_SIZE : INTEGER 74 | ); 75 | PORT ( 76 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 77 | Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 78 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 79 | ); 80 | END COMPONENT util_vector_logic; 81 | BEGIN 82 | U0 : util_vector_logic 83 | GENERIC MAP ( 84 | C_OPERATION => "not", 85 | C_SIZE => 1 86 | ) 87 | PORT MAP ( 88 | Op1 => Op1, 89 | Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 90 | Res => Res 91 | ); 92 | END z_turn_util_vector_logic_0_1_arch; 93 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/synth/z_turn_util_vector_logic_0_1.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | -- IP Revision: 0 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY util_vector_logic_v2_0; 57 | USE util_vector_logic_v2_0.util_vector_logic; 58 | 59 | ENTITY z_turn_util_vector_logic_0_1 IS 60 | PORT ( 61 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 62 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 63 | ); 64 | END z_turn_util_vector_logic_0_1; 65 | 66 | ARCHITECTURE z_turn_util_vector_logic_0_1_arch OF z_turn_util_vector_logic_0_1 IS 67 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "yes"; 69 | 70 | COMPONENT util_vector_logic IS 71 | GENERIC ( 72 | C_OPERATION : STRING; 73 | C_SIZE : INTEGER 74 | ); 75 | PORT ( 76 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 77 | Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 78 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 79 | ); 80 | END COMPONENT util_vector_logic; 81 | ATTRIBUTE X_CORE_INFO : STRING; 82 | ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2"; 83 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 84 | ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_0_1_arch : ARCHITECTURE IS "z_turn_util_vector_logic_0_1,util_vector_logic,{}"; 85 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 86 | ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_0_1_arch: ARCHITECTURE IS "z_turn_util_vector_logic_0_1,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}"; 87 | BEGIN 88 | U0 : util_vector_logic 89 | GENERIC MAP ( 90 | C_OPERATION => "not", 91 | C_SIZE => 1 92 | ) 93 | PORT MAP ( 94 | Op1 => Op1, 95 | Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 96 | Res => Res 97 | ); 98 | END z_turn_util_vector_logic_0_1_arch; 99 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:21 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_util_vector_logic_0_1' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_util_vector_logic_0_1 (xilinx.com:ip:util_vector_logic:2.0) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | // IP Revision: 0 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_util_vector_logic_0_1 your_instance_name ( 58 | .Op1(Op1), // input wire [0 : 0] Op1 59 | .Res(Res) // output wire [0 : 0] Res 60 | ); 61 | // INST_TAG_END ------ End INSTANTIATION Template --------- 62 | 63 | // You must compile the wrapper file z_turn_util_vector_logic_0_1.v when simulating 64 | // the core, z_turn_util_vector_logic_0_1. When compiling the wrapper file, be sure to 65 | // reference the Verilog simulation library. 66 | 67 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_0_1/z_turn_util_vector_logic_0_1.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | z_turn_util_vector_logic_0_1 10 | 11 | 12 | 1 13 | not 14 | z_turn_util_vector_logic_0_1 15 | not 16 | 1 17 | zynq 18 | xc7z020 19 | clg400 20 | -1 21 | C 22 | 23 | VERILOG 24 | MIXED 25 | TRUE 26 | TRUE 27 | 28 | TRUE 29 | 2015.2 30 | 0 31 | OUT_OF_CONTEXT 32 | 33 | . 34 | ../../../../ipshared 35 | IP_Integrator 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/doc/util_vector_logic_v2_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4: 2 | * Version 2.0 3 | * Changed the port ordering from (0 to C_SIZE-1) to (C_SIZE-1 downto 0) 4 | * Updated the vhdl library name from util_vector_logic_v1_0 to util_vector_logic_v2_0 5 | 6 | 2014.1: 7 | * Version 1.0 (Rev. 2) 8 | * Updated the vhdl library name from work to util_vector_logic_v1_0 9 | 10 | 11 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 12 | 13 | This file contains confidential and proprietary information 14 | of Xilinx, Inc. and is protected under U.S. and 15 | international copyright and other intellectual property 16 | laws. 17 | 18 | DISCLAIMER 19 | This disclaimer is not a license and does not grant any 20 | rights to the materials distributed herewith. Except as 21 | otherwise provided in a valid license issued to you by 22 | Xilinx, and to the maximum extent permitted by applicable 23 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 24 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 25 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 26 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 27 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 28 | (2) Xilinx shall not be liable (whether in contract or tort, 29 | including negligence, or under any other theory of 30 | liability) for any loss or damage of any kind or nature 31 | related to, arising under or in connection with these 32 | materials, including for any direct, or any indirect, 33 | special, incidental, or consequential loss or damage 34 | (including loss of data, profits, goodwill, or any type of 35 | loss or damage suffered as a result of any action brought 36 | by a third party) even if such damage or loss was 37 | reasonably foreseeable or Xilinx had been advised of the 38 | possibility of the same. 39 | 40 | CRITICAL APPLICATIONS 41 | Xilinx products are not designed or intended to be fail- 42 | safe, or for use in any application requiring fail-safe 43 | performance, such as life-support or safety devices or 44 | systems, Class III medical devices, nuclear facilities, 45 | applications related to the deployment of airbags, or any 46 | other applications that could lead to death, personal 47 | injury, or severe property or environmental damage 48 | (individually and collectively, "Critical 49 | Applications"). Customer assumes the sole risk and 50 | liability of any use of Xilinx products in Critical 51 | Applications, subject only to applicable laws and 52 | regulations governing limitations on product liability. 53 | 54 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 55 | PART OF THIS FILE AT ALL TIMES. 56 | 57 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/sim/z_turn_util_vector_logic_1_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | -- IP Revision: 0 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY util_vector_logic_v2_0; 57 | USE util_vector_logic_v2_0.util_vector_logic; 58 | 59 | ENTITY z_turn_util_vector_logic_1_0 IS 60 | PORT ( 61 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 62 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 63 | ); 64 | END z_turn_util_vector_logic_1_0; 65 | 66 | ARCHITECTURE z_turn_util_vector_logic_1_0_arch OF z_turn_util_vector_logic_1_0 IS 67 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes"; 69 | 70 | COMPONENT util_vector_logic IS 71 | GENERIC ( 72 | C_OPERATION : STRING; 73 | C_SIZE : INTEGER 74 | ); 75 | PORT ( 76 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 77 | Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 78 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 79 | ); 80 | END COMPONENT util_vector_logic; 81 | BEGIN 82 | U0 : util_vector_logic 83 | GENERIC MAP ( 84 | C_OPERATION => "not", 85 | C_SIZE => 1 86 | ) 87 | PORT MAP ( 88 | Op1 => Op1, 89 | Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 90 | Res => Res 91 | ); 92 | END z_turn_util_vector_logic_1_0_arch; 93 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/synth/z_turn_util_vector_logic_1_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | -- IP Revision: 0 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY util_vector_logic_v2_0; 57 | USE util_vector_logic_v2_0.util_vector_logic; 58 | 59 | ENTITY z_turn_util_vector_logic_1_0 IS 60 | PORT ( 61 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 62 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 63 | ); 64 | END z_turn_util_vector_logic_1_0; 65 | 66 | ARCHITECTURE z_turn_util_vector_logic_1_0_arch OF z_turn_util_vector_logic_1_0 IS 67 | ATTRIBUTE DowngradeIPIdentifiedWarnings : string; 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes"; 69 | 70 | COMPONENT util_vector_logic IS 71 | GENERIC ( 72 | C_OPERATION : STRING; 73 | C_SIZE : INTEGER 74 | ); 75 | PORT ( 76 | Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 77 | Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 78 | Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) 79 | ); 80 | END COMPONENT util_vector_logic; 81 | ATTRIBUTE X_CORE_INFO : STRING; 82 | ATTRIBUTE X_CORE_INFO OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2015.2"; 83 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 84 | ATTRIBUTE CHECK_LICENSE_TYPE OF z_turn_util_vector_logic_1_0_arch : ARCHITECTURE IS "z_turn_util_vector_logic_1_0,util_vector_logic,{}"; 85 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 86 | ATTRIBUTE CORE_GENERATION_INFO OF z_turn_util_vector_logic_1_0_arch: ARCHITECTURE IS "z_turn_util_vector_logic_1_0,util_vector_logic,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}"; 87 | BEGIN 88 | U0 : util_vector_logic 89 | GENERIC MAP ( 90 | C_OPERATION => "not", 91 | C_SIZE => 1 92 | ) 93 | PORT MAP ( 94 | Op1 => Op1, 95 | Op2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 96 | Res => Res 97 | ); 98 | END z_turn_util_vector_logic_1_0_arch; 99 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:22 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_util_vector_logic_1_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_util_vector_logic_1_0 (xilinx.com:ip:util_vector_logic:2.0) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:util_vector_logic:2.0 50 | // IP Revision: 0 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_util_vector_logic_1_0 your_instance_name ( 58 | .Op1(Op1), // input wire [0 : 0] Op1 59 | .Res(Res) // output wire [0 : 0] Res 60 | ); 61 | // INST_TAG_END ------ End INSTANTIATION Template --------- 62 | 63 | // You must compile the wrapper file z_turn_util_vector_logic_1_0.v when simulating 64 | // the core, z_turn_util_vector_logic_1_0. When compiling the wrapper file, be sure to 65 | // reference the Verilog simulation library. 66 | 67 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_util_vector_logic_1_0/z_turn_util_vector_logic_1_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | z_turn_util_vector_logic_1_0 10 | 11 | 12 | 1 13 | not 14 | z_turn_util_vector_logic_1_0 15 | not 16 | 1 17 | zynq 18 | xc7z020 19 | clg400 20 | -1 21 | C 22 | 23 | VERILOG 24 | MIXED 25 | TRUE 26 | TRUE 27 | 28 | TRUE 29 | 2015.2 30 | 0 31 | OUT_OF_CONTEXT 32 | 33 | . 34 | ../../../../ipshared 35 | IP_Integrator 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/doc/xlconcat_v2_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4 2 | * Version 2.1 (Rev.1) 3 | * Add Auto/Manual button for Inxx Width in GUI dialog. 4 | 5 | 2014.2 6 | * Version 2.1 7 | * upgrade input sources from 16 to 32. 8 | 9 | 2014.1: 10 | * Version 2.0 11 | * Version 1.0 of the xlconcat block reverses the order in 12 | * which input signals are concatenated. Version 2.0 13 | * preserves the order of input signals on the output. 14 | * The upgrade from 1.0 to 2.0 will change input connections 15 | * in order to preserve the overall the signal order on output. 16 | 17 | 18 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 19 | 20 | This file contains confidential and proprietary information 21 | of Xilinx, Inc. and is protected under U.S. and 22 | international copyright and other intellectual property 23 | laws. 24 | 25 | DISCLAIMER 26 | This disclaimer is not a license and does not grant any 27 | rights to the materials distributed herewith. Except as 28 | otherwise provided in a valid license issued to you by 29 | Xilinx, and to the maximum extent permitted by applicable 30 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 31 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 32 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 33 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 34 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 35 | (2) Xilinx shall not be liable (whether in contract or tort, 36 | including negligence, or under any other theory of 37 | liability) for any loss or damage of any kind or nature 38 | related to, arising under or in connection with these 39 | materials, including for any direct, or any indirect, 40 | special, incidental, or consequential loss or damage 41 | (including loss of data, profits, goodwill, or any type of 42 | loss or damage suffered as a result of any action brought 43 | by a third party) even if such damage or loss was 44 | reasonably foreseeable or Xilinx had been advised of the 45 | possibility of the same. 46 | 47 | CRITICAL APPLICATIONS 48 | Xilinx products are not designed or intended to be fail- 49 | safe, or for use in any application requiring fail-safe 50 | performance, such as life-support or safety devices or 51 | systems, Class III medical devices, nuclear facilities, 52 | applications related to the deployment of airbags, or any 53 | other applications that could lead to death, personal 54 | injury, or severe property or environmental damage 55 | (individually and collectively, "Critical 56 | Applications"). Customer assumes the sole risk and 57 | liability of any use of Xilinx products in Critical 58 | Applications, subject only to applicable laws and 59 | regulations governing limitations on product liability. 60 | 61 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 62 | PART OF THIS FILE AT ALL TIMES. 63 | 64 | 65 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:23 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_xlconcat_0_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_xlconcat_0_0 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_0/z_turn_xlconcat_0_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:xlconcat:2.1 50 | // IP Revision: 1 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_xlconcat_0_0 your_instance_name ( 58 | .In0(In0), // input wire [0 : 0] In0 59 | .In1(In1), // input wire [0 : 0] In1 60 | .In2(In2), // input wire [0 : 0] In2 61 | .In3(In3), // input wire [0 : 0] In3 62 | .In4(In4), // input wire [0 : 0] In4 63 | .In5(In5), // input wire [0 : 0] In5 64 | .In6(In6), // input wire [0 : 0] In6 65 | .In7(In7), // input wire [0 : 0] In7 66 | .In8(In8), // input wire [0 : 0] In8 67 | .In9(In9), // input wire [0 : 0] In9 68 | .In10(In10), // input wire [0 : 0] In10 69 | .In11(In11), // input wire [0 : 0] In11 70 | .In12(In12), // input wire [0 : 0] In12 71 | .In13(In13), // input wire [0 : 0] In13 72 | .In14(In14), // input wire [0 : 0] In14 73 | .In15(In15), // input wire [0 : 0] In15 74 | .dout(dout) // output wire [15 : 0] dout 75 | ); 76 | // INST_TAG_END ------ End INSTANTIATION Template --------- 77 | 78 | // You must compile the wrapper file z_turn_xlconcat_0_0.v when simulating 79 | // the core, z_turn_xlconcat_0_0. When compiling the wrapper file, be sure to 80 | // reference the Verilog simulation library. 81 | 82 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/doc/xlconcat_v2_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4 2 | * Version 2.1 (Rev.1) 3 | * Add Auto/Manual button for Inxx Width in GUI dialog. 4 | 5 | 2014.2 6 | * Version 2.1 7 | * upgrade input sources from 16 to 32. 8 | 9 | 2014.1: 10 | * Version 2.0 11 | * Version 1.0 of the xlconcat block reverses the order in 12 | * which input signals are concatenated. Version 2.0 13 | * preserves the order of input signals on the output. 14 | * The upgrade from 1.0 to 2.0 will change input connections 15 | * in order to preserve the overall the signal order on output. 16 | 17 | 18 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 19 | 20 | This file contains confidential and proprietary information 21 | of Xilinx, Inc. and is protected under U.S. and 22 | international copyright and other intellectual property 23 | laws. 24 | 25 | DISCLAIMER 26 | This disclaimer is not a license and does not grant any 27 | rights to the materials distributed herewith. Except as 28 | otherwise provided in a valid license issued to you by 29 | Xilinx, and to the maximum extent permitted by applicable 30 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 31 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 32 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 33 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 34 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 35 | (2) Xilinx shall not be liable (whether in contract or tort, 36 | including negligence, or under any other theory of 37 | liability) for any loss or damage of any kind or nature 38 | related to, arising under or in connection with these 39 | materials, including for any direct, or any indirect, 40 | special, incidental, or consequential loss or damage 41 | (including loss of data, profits, goodwill, or any type of 42 | loss or damage suffered as a result of any action brought 43 | by a third party) even if such damage or loss was 44 | reasonably foreseeable or Xilinx had been advised of the 45 | possibility of the same. 46 | 47 | CRITICAL APPLICATIONS 48 | Xilinx products are not designed or intended to be fail- 49 | safe, or for use in any application requiring fail-safe 50 | performance, such as life-support or safety devices or 51 | systems, Class III medical devices, nuclear facilities, 52 | applications related to the deployment of airbags, or any 53 | other applications that could lead to death, personal 54 | injury, or severe property or environmental damage 55 | (individually and collectively, "Critical 56 | Applications"). Customer assumes the sole risk and 57 | liability of any use of Xilinx products in Critical 58 | Applications, subject only to applicable laws and 59 | regulations governing limitations on product liability. 60 | 61 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 62 | PART OF THIS FILE AT ALL TIMES. 63 | 64 | 65 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/sim/z_turn_xlconcat_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: xilinx.com:ip:xlconcat:2.1 51 | // IP Revision: 1 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module z_turn_xlconcat_0_1 ( 57 | In0, 58 | In1, 59 | dout 60 | ); 61 | 62 | input wire [31 : 0] In0; 63 | input wire [31 : 0] In1; 64 | output wire [63 : 0] dout; 65 | 66 | xlconcat #( 67 | .IN0_WIDTH(32), 68 | .IN1_WIDTH(32), 69 | .IN2_WIDTH(1), 70 | .IN3_WIDTH(1), 71 | .IN4_WIDTH(1), 72 | .IN5_WIDTH(1), 73 | .IN6_WIDTH(1), 74 | .IN7_WIDTH(1), 75 | .IN8_WIDTH(1), 76 | .IN9_WIDTH(1), 77 | .IN10_WIDTH(1), 78 | .IN11_WIDTH(1), 79 | .IN12_WIDTH(1), 80 | .IN13_WIDTH(1), 81 | .IN14_WIDTH(1), 82 | .IN15_WIDTH(1), 83 | .IN16_WIDTH(1), 84 | .IN17_WIDTH(1), 85 | .IN18_WIDTH(1), 86 | .IN19_WIDTH(1), 87 | .IN20_WIDTH(1), 88 | .IN21_WIDTH(1), 89 | .IN22_WIDTH(1), 90 | .IN23_WIDTH(1), 91 | .IN24_WIDTH(1), 92 | .IN25_WIDTH(1), 93 | .IN26_WIDTH(1), 94 | .IN27_WIDTH(1), 95 | .IN28_WIDTH(1), 96 | .IN29_WIDTH(1), 97 | .IN30_WIDTH(1), 98 | .IN31_WIDTH(1), 99 | .dout_width(64), 100 | .NUM_PORTS(2) 101 | ) inst ( 102 | .In0(In0), 103 | .In1(In1), 104 | .In2(1'B0), 105 | .In3(1'B0), 106 | .In4(1'B0), 107 | .In5(1'B0), 108 | .In6(1'B0), 109 | .In7(1'B0), 110 | .In8(1'B0), 111 | .In9(1'B0), 112 | .In10(1'B0), 113 | .In11(1'B0), 114 | .In12(1'B0), 115 | .In13(1'B0), 116 | .In14(1'B0), 117 | .In15(1'B0), 118 | .In16(1'B0), 119 | .In17(1'B0), 120 | .In18(1'B0), 121 | .In19(1'B0), 122 | .In20(1'B0), 123 | .In21(1'B0), 124 | .In22(1'B0), 125 | .In23(1'B0), 126 | .In24(1'B0), 127 | .In25(1'B0), 128 | .In26(1'B0), 129 | .In27(1'B0), 130 | .In28(1'B0), 131 | .In29(1'B0), 132 | .In30(1'B0), 133 | .In31(1'B0), 134 | .dout(dout) 135 | ); 136 | endmodule 137 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:23 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_xlconcat_0_1' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_xlconcat_0_1 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_1/z_turn_xlconcat_0_1.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:xlconcat:2.1 50 | // IP Revision: 1 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_xlconcat_0_1 your_instance_name ( 58 | .In0(In0), // input wire [31 : 0] In0 59 | .In1(In1), // input wire [31 : 0] In1 60 | .dout(dout) // output wire [63 : 0] dout 61 | ); 62 | // INST_TAG_END ------ End INSTANTIATION Template --------- 63 | 64 | // You must compile the wrapper file z_turn_xlconcat_0_1.v when simulating 65 | // the core, z_turn_xlconcat_0_1. When compiling the wrapper file, be sure to 66 | // reference the Verilog simulation library. 67 | 68 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/doc/xlconcat_v2_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4 2 | * Version 2.1 (Rev.1) 3 | * Add Auto/Manual button for Inxx Width in GUI dialog. 4 | 5 | 2014.2 6 | * Version 2.1 7 | * upgrade input sources from 16 to 32. 8 | 9 | 2014.1: 10 | * Version 2.0 11 | * Version 1.0 of the xlconcat block reverses the order in 12 | * which input signals are concatenated. Version 2.0 13 | * preserves the order of input signals on the output. 14 | * The upgrade from 1.0 to 2.0 will change input connections 15 | * in order to preserve the overall the signal order on output. 16 | 17 | 18 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 19 | 20 | This file contains confidential and proprietary information 21 | of Xilinx, Inc. and is protected under U.S. and 22 | international copyright and other intellectual property 23 | laws. 24 | 25 | DISCLAIMER 26 | This disclaimer is not a license and does not grant any 27 | rights to the materials distributed herewith. Except as 28 | otherwise provided in a valid license issued to you by 29 | Xilinx, and to the maximum extent permitted by applicable 30 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 31 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 32 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 33 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 34 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 35 | (2) Xilinx shall not be liable (whether in contract or tort, 36 | including negligence, or under any other theory of 37 | liability) for any loss or damage of any kind or nature 38 | related to, arising under or in connection with these 39 | materials, including for any direct, or any indirect, 40 | special, incidental, or consequential loss or damage 41 | (including loss of data, profits, goodwill, or any type of 42 | loss or damage suffered as a result of any action brought 43 | by a third party) even if such damage or loss was 44 | reasonably foreseeable or Xilinx had been advised of the 45 | possibility of the same. 46 | 47 | CRITICAL APPLICATIONS 48 | Xilinx products are not designed or intended to be fail- 49 | safe, or for use in any application requiring fail-safe 50 | performance, such as life-support or safety devices or 51 | systems, Class III medical devices, nuclear facilities, 52 | applications related to the deployment of airbags, or any 53 | other applications that could lead to death, personal 54 | injury, or severe property or environmental damage 55 | (individually and collectively, "Critical 56 | Applications"). Customer assumes the sole risk and 57 | liability of any use of Xilinx products in Critical 58 | Applications, subject only to applicable laws and 59 | regulations governing limitations on product liability. 60 | 61 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 62 | PART OF THIS FILE AT ALL TIMES. 63 | 64 | 65 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_0_2/z_turn_xlconcat_0_2.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:24 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_xlconcat_0_2' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_xlconcat_0_2 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/doc/xlconcat_v2_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.4 2 | * Version 2.1 (Rev.1) 3 | * Add Auto/Manual button for Inxx Width in GUI dialog. 4 | 5 | 2014.2 6 | * Version 2.1 7 | * upgrade input sources from 16 to 32. 8 | 9 | 2014.1: 10 | * Version 2.0 11 | * Version 1.0 of the xlconcat block reverses the order in 12 | * which input signals are concatenated. Version 2.0 13 | * preserves the order of input signals on the output. 14 | * The upgrade from 1.0 to 2.0 will change input connections 15 | * in order to preserve the overall the signal order on output. 16 | 17 | 18 | (c) Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. 19 | 20 | This file contains confidential and proprietary information 21 | of Xilinx, Inc. and is protected under U.S. and 22 | international copyright and other intellectual property 23 | laws. 24 | 25 | DISCLAIMER 26 | This disclaimer is not a license and does not grant any 27 | rights to the materials distributed herewith. Except as 28 | otherwise provided in a valid license issued to you by 29 | Xilinx, and to the maximum extent permitted by applicable 30 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 31 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 32 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 33 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 34 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 35 | (2) Xilinx shall not be liable (whether in contract or tort, 36 | including negligence, or under any other theory of 37 | liability) for any loss or damage of any kind or nature 38 | related to, arising under or in connection with these 39 | materials, including for any direct, or any indirect, 40 | special, incidental, or consequential loss or damage 41 | (including loss of data, profits, goodwill, or any type of 42 | loss or damage suffered as a result of any action brought 43 | by a third party) even if such damage or loss was 44 | reasonably foreseeable or Xilinx had been advised of the 45 | possibility of the same. 46 | 47 | CRITICAL APPLICATIONS 48 | Xilinx products are not designed or intended to be fail- 49 | safe, or for use in any application requiring fail-safe 50 | performance, such as life-support or safety devices or 51 | systems, Class III medical devices, nuclear facilities, 52 | applications related to the deployment of airbags, or any 53 | other applications that could lead to death, personal 54 | injury, or severe property or environmental damage 55 | (individually and collectively, "Critical 56 | Applications"). Customer assumes the sole risk and 57 | liability of any use of Xilinx products in Critical 58 | Applications, subject only to applicable laws and 59 | regulations governing limitations on product liability. 60 | 61 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 62 | PART OF THIS FILE AT ALL TIMES. 63 | 64 | 65 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.upgrade_log: -------------------------------------------------------------------------------- 1 | Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2015.2 (win64) Build 1263262 Tue Jun 23 17:59:39 MDT 2015 4 | | Date : Fri Jul 10 13:44:25 2015 5 | | Host : Mitch-PC running 64-bit Service Pack 1 (build 7601) 6 | | Command : upgrade_ip 7 | | Device : xc7z020clg400-1 8 | ------------------------------------------------------------------------------------ 9 | 10 | Upgrade Log for IP 'z_turn_xlconcat_1_0' 11 | 12 | 1. Summary 13 | ---------- 14 | 15 | SUCCESS in the update of z_turn_xlconcat_1_0 (xilinx.com:ip:xlconcat:2.1 (Rev. 1)) to current project options. 16 | 17 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ip/z_turn_xlconcat_1_0/z_turn_xlconcat_1_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:xlconcat:2.1 50 | // IP Revision: 1 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | z_turn_xlconcat_1_0 your_instance_name ( 58 | .In0(In0), // input wire [0 : 0] In0 59 | .In1(In1), // input wire [0 : 0] In1 60 | .In2(In2), // input wire [0 : 0] In2 61 | .In3(In3), // input wire [0 : 0] In3 62 | .In4(In4), // input wire [0 : 0] In4 63 | .In5(In5), // input wire [0 : 0] In5 64 | .In6(In6), // input wire [0 : 0] In6 65 | .In7(In7), // input wire [0 : 0] In7 66 | .In8(In8), // input wire [0 : 0] In8 67 | .In9(In9), // input wire [0 : 0] In9 68 | .In10(In10), // input wire [0 : 0] In10 69 | .In11(In11), // input wire [0 : 0] In11 70 | .In12(In12), // input wire [0 : 0] In12 71 | .In13(In13), // input wire [0 : 0] In13 72 | .In14(In14), // input wire [0 : 0] In14 73 | .In15(In15), // input wire [0 : 0] In15 74 | .In16(In16), // input wire [0 : 0] In16 75 | .In17(In17), // input wire [0 : 0] In17 76 | .In18(In18), // input wire [0 : 0] In18 77 | .In19(In19), // input wire [0 : 0] In19 78 | .In20(In20), // input wire [0 : 0] In20 79 | .In21(In21), // input wire [0 : 0] In21 80 | .In22(In22), // input wire [0 : 0] In22 81 | .In23(In23), // input wire [0 : 0] In23 82 | .In24(In24), // input wire [3 : 0] In24 83 | .In25(In25), // input wire [0 : 0] In25 84 | .In26(In26), // input wire [0 : 0] In26 85 | .In27(In27), // input wire [0 : 0] In27 86 | .In28(In28), // input wire [0 : 0] In28 87 | .dout(dout) // output wire [31 : 0] dout 88 | ); 89 | // INST_TAG_END ------ End INSTANTIATION Template --------- 90 | 91 | // You must compile the wrapper file z_turn_xlconcat_1_0.v when simulating 92 | // the core, z_turn_xlconcat_1_0. When compiling the wrapper file, be sure to 93 | // reference the Verilog simulation library. 94 | 95 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_24d8caf0.ui: -------------------------------------------------------------------------------- 1 | { 2 | guistr: "# # String gsaved with Nlview 6.4.12 2014-12-16 bk=1.3272 VDI=35 GEI=35 GUI=JA:1.6 3 | # -string -flagsOSRD 4 | preplace port M_ACLK -pg 1 -y 60 -defaultsOSRD 5 | preplace port S_ACLK -pg 1 -y 20 -defaultsOSRD 6 | preplace port S_AXI -pg 1 -y 40 -defaultsOSRD 7 | preplace port M_AXI -pg 1 -y 60 -defaultsOSRD 8 | preplace portBus M_ARESETN -pg 1 -y 80 -defaultsOSRD 9 | preplace portBus S_ARESETN -pg 1 -y 100 -defaultsOSRD 10 | preplace inst s00_data_fifo -pg 1 -lvl 1 -y 60 -defaultsOSRD 11 | preplace netloc s00_data_fifo_to_s00_couplers 1 1 1 N 12 | preplace netloc M_ACLK_1 1 0 1 NJ 13 | preplace netloc M_ARESETN_1 1 0 1 NJ 14 | preplace netloc s00_couplers_to_s00_data_fifo 1 0 1 NJ 15 | levelinfo -pg 1 130 240 350 16 | ", 17 | } 18 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/ui/bd_35e35d22.ui: -------------------------------------------------------------------------------- 1 | { 2 | commentid: "", 3 | guistr: "# # String gsaved with Nlview 6.4.12 2014-12-16 bk=1.3272 VDI=35 GEI=35 GUI=JA:1.6 4 | # -string -flagsOSRD 5 | preplace port I2S_FSYNC_IN -pg 1 -y 80 -defaultsOSRD 6 | preplace port I2S_DIN -pg 1 -y 180 -defaultsOSRD 7 | preplace port DDR -pg 1 -y 470 -defaultsOSRD 8 | preplace port MEMS_INTn -pg 1 -y 260 -defaultsOSRD 9 | preplace port HDMI_INTn -pg 1 -y 340 -defaultsOSRD 10 | preplace port IO_B34_LP11 -pg 1 -y 160 -defaultsOSRD 11 | preplace port LCD_VSYNC -pg 1 -y 380 -defaultsOSRD 12 | preplace port IO_B34_LN8 -pg 1 -y 140 -defaultsOSRD 13 | preplace port I2S_SCLK -pg 1 -y 70 -defaultsOSRD 14 | preplace port LCD_HSYNC -pg 1 -y 400 -defaultsOSRD 15 | preplace port BP -pg 1 -y 210 -defaultsOSRD 16 | preplace port IO_B34_LN11 -pg 1 -y 100 -defaultsOSRD 17 | preplace port LCD_PCLK -pg 1 -y 340 -defaultsOSRD 18 | preplace port LCD_DE -pg 1 -y 360 -defaultsOSRD 19 | preplace port IIC_0 -pg 1 -y 710 -defaultsOSRD 20 | preplace port FIXED_IO -pg 1 -y 490 -defaultsOSRD 21 | preplace port IO_B34_LP6 -pg 1 -y 60 -defaultsOSRD 22 | preplace port I2S_DOUT -pg 1 -y 110 -defaultsOSRD 23 | preplace port IO_B34_LP8 -pg 1 -y 120 -defaultsOSRD 24 | preplace port I2S_FSYNC_OUT -pg 1 -y 90 -defaultsOSRD 25 | preplace portBus IO_B35_LP -pg 1 -y 360 -defaultsOSRD 26 | preplace portBus IO_B34_LN -pg 1 -y 40 -defaultsOSRD 27 | preplace portBus IO_B34_LP -pg 1 -y 20 -defaultsOSRD 28 | preplace portBus LCD_DATA -pg 1 -y 420 -defaultsOSRD 29 | preplace portBus SW -pg 1 -y 210 -defaultsOSRD 30 | preplace portBus LEDS -pg 1 -y 230 -defaultsOSRD 31 | preplace portBus IO_B35_LN -pg 1 -y 390 -defaultsOSRD 32 | preplace inst z_turn_ps_7_axi_periph_0 -pg 1 -lvl 7 -y 500 -defaultsOSRD 33 | preplace inst ps7 -pg 1 -lvl 5 -y 820 -defaultsOSRD 34 | preplace inst z_turn_ps_7_axi_periph_1 -pg 1 -lvl 7 -y 800 -defaultsOSRD -resize 200 196 35 | preplace inst xlconcat_0 -pg 1 -lvl 2 -y 430 -defaultsOSRD 36 | preplace inst util_vector_logic_0 -pg 1 -lvl 3 -y 430 -defaultsOSRD 37 | preplace inst proc_sys_reset_0 -pg 1 -lvl 6 -y 230 -defaultsOSRD -resize 280 140 38 | preplace inst xlconcat_1 -pg 1 -lvl 1 -y 510 -defaultsOSRD -resize 160 205 39 | preplace inst util_vector_logic_1 -pg 1 -lvl 3 -y 510 -defaultsOSRD -resize 140 60 40 | preplace inst proc_sys_reset_1 -pg 1 -lvl 6 -y 440 -defaultsOSRD 41 | preplace inst xlconcat_2 -pg 1 -lvl 1 -y 980 -defaultsOSRD -resize 160 205 42 | preplace inst xlconcat -pg 1 -lvl 4 -y 580 -defaultsOSRD 43 | preplace inst util_vector_logic_2 -pg 1 -lvl 3 -y 610 -defaultsOSRD -resize 140 60 44 | preplace inst proc_sys_reset_2 -pg 1 -lvl 6 -y 760 -defaultsOSRD -resize 280 140 45 | preplace inst proc_sys_reset_3 -pg 1 -lvl 6 -y 990 -defaultsOSRD -resize 280 140 46 | preplace netloc ps_7_FIXED_IO 1 5 3 2140 870 NJ 930 NJ 47 | preplace netloc MEMS_INTn_1 1 0 3 NJ 260 NJ 260 610 48 | preplace netloc ps_7_FCLK_CLK0 1 4 3 1460 370 2110 350 2600 49 | preplace netloc ps_7_FCLK_CLK1 1 5 1 2090 50 | preplace netloc proc_sys_reset2_peripheral_aresetn 1 6 1 2540 51 | preplace netloc proc_sys_reset2_interconnect_aresetn 1 6 1 N 52 | preplace netloc ps_7_FCLK_RESET1_N 1 5 1 2150 53 | preplace netloc xlconcat_1_dout 1 1 1 360 54 | preplace netloc util_vector_logic_0_Res 1 3 1 N 55 | preplace netloc ps_7_FCLK_RESET0_N 1 5 1 2100 56 | preplace netloc ps_7_FCLK_CLK2 1 4 3 1470 1080 2180 550 2570 57 | preplace netloc ps_7_FCLK_CLK3 1 5 1 N 58 | preplace netloc HDMI_INTn_1 1 0 3 NJ 340 NJ 490 620 59 | preplace netloc ps_7_M_AXI_GP0 1 5 2 2130 850 NJ 60 | preplace netloc ps_7_FCLK_RESET3_N 1 5 1 2190 61 | preplace netloc ps_7_FCLK_RESET2_N 1 5 1 2170 62 | preplace netloc rst_ps_7_166M_peripheral_aresetn 1 6 1 2580 63 | preplace netloc xlconcat_0_dout 1 4 1 1450 64 | preplace netloc ps_7_DDR 1 5 3 2160 860 NJ 920 NJ 65 | preplace netloc ps7_IIC_0 1 5 3 2120 880 NJ 940 NJ 66 | preplace netloc util_vector_logic_2_Res 1 3 1 1110 67 | preplace netloc util_vector_logic_1_Res 1 3 1 1100 68 | preplace netloc io2axis_M00_AXI 1 4 4 1470 560 NJ 560 NJ 680 2940 69 | preplace netloc xlconcat_2_dout 1 1 1 380 70 | preplace netloc SW_1 1 0 1 160 71 | preplace netloc xlconcat_0_dout1 1 2 4 NJ 560 NJ 380 NJ 380 2080 72 | preplace netloc rst_ps_7_166M_interconnect_aresetn 1 6 1 2590 73 | levelinfo -pg 1 140 260 500 990 1350 1880 2350 2800 2990 74 | ", 75 | } 76 | { 77 | da_axi4_cnt: "1", 78 | } -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/bd/z_turn/z_turn_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name IO_B34_LP11 -period 20 [get_ports IO_B34_LP11] 10 | create_clock -name ps7_FCLK_CLK0 -period 5.9999998080000063 [get_pins ps7/FCLK_CLK0] 11 | create_clock -name ps7_FCLK_CLK1 -period 20 [get_pins ps7/FCLK_CLK1] 12 | create_clock -name ps7_FCLK_CLK2 -period 10 [get_pins ps7/FCLK_CLK2] 13 | create_clock -name ps7_FCLK_CLK3 -period 5 [get_pins ps7/FCLK_CLK3] 14 | 15 | ################################################################################ -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_arb_hp0_1.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Module that arbitrates between RD/WR requests from 2 ports. 7 | * Used for modelling the Top_Interconnect switch. 8 | *****************************************************************************/ 9 | `timescale 1ns/1ps 10 | 11 | module processing_system7_bfm_v2_0_arb_hp0_1( 12 | sw_clk, 13 | rstn, 14 | w_qos_hp0, 15 | r_qos_hp0, 16 | w_qos_hp1, 17 | r_qos_hp1, 18 | 19 | wr_ack_ddr_hp0, 20 | wr_data_hp0, 21 | wr_addr_hp0, 22 | wr_bytes_hp0, 23 | wr_dv_ddr_hp0, 24 | rd_req_ddr_hp0, 25 | rd_addr_hp0, 26 | rd_bytes_hp0, 27 | rd_data_ddr_hp0, 28 | rd_dv_ddr_hp0, 29 | 30 | wr_ack_ddr_hp1, 31 | wr_data_hp1, 32 | wr_addr_hp1, 33 | wr_bytes_hp1, 34 | wr_dv_ddr_hp1, 35 | rd_req_ddr_hp1, 36 | rd_addr_hp1, 37 | rd_bytes_hp1, 38 | rd_data_ddr_hp1, 39 | rd_dv_ddr_hp1, 40 | 41 | ddr_wr_ack, 42 | ddr_wr_dv, 43 | ddr_rd_req, 44 | ddr_rd_dv, 45 | ddr_rd_qos, 46 | ddr_wr_qos, 47 | 48 | ddr_wr_addr, 49 | ddr_wr_data, 50 | ddr_wr_bytes, 51 | ddr_rd_addr, 52 | ddr_rd_data, 53 | ddr_rd_bytes 54 | 55 | ); 56 | `include "processing_system7_bfm_v2_0_local_params.v" 57 | input sw_clk; 58 | input rstn; 59 | input [axi_qos_width-1:0] w_qos_hp0; 60 | input [axi_qos_width-1:0] r_qos_hp0; 61 | input [axi_qos_width-1:0] w_qos_hp1; 62 | input [axi_qos_width-1:0] r_qos_hp1; 63 | input [axi_qos_width-1:0] ddr_rd_qos; 64 | input [axi_qos_width-1:0] ddr_wr_qos; 65 | 66 | output wr_ack_ddr_hp0; 67 | input [max_burst_bits-1:0] wr_data_hp0; 68 | input [addr_width-1:0] wr_addr_hp0; 69 | input [max_burst_bytes_width:0] wr_bytes_hp0; 70 | output wr_dv_ddr_hp0; 71 | 72 | input rd_req_ddr_hp0; 73 | input [addr_width-1:0] rd_addr_hp0; 74 | input [max_burst_bytes_width:0] rd_bytes_hp0; 75 | output [max_burst_bits-1:0] rd_data_ddr_hp0; 76 | output rd_dv_ddr_hp0; 77 | 78 | output wr_ack_ddr_hp1; 79 | input [max_burst_bits-1:0] wr_data_hp1; 80 | input [addr_width-1:0] wr_addr_hp1; 81 | input [max_burst_bytes_width:0] wr_bytes_hp1; 82 | output wr_dv_ddr_hp1; 83 | 84 | input rd_req_ddr_hp1; 85 | input [addr_width-1:0] rd_addr_hp1; 86 | input [max_burst_bytes_width:0] rd_bytes_hp1; 87 | output [max_burst_bits-1:0] rd_data_ddr_hp1; 88 | output rd_dv_ddr_hp1; 89 | 90 | input ddr_wr_ack; 91 | output ddr_wr_dv; 92 | output [addr_width-1:0]ddr_wr_addr; 93 | output [max_burst_bits-1:0]ddr_wr_data; 94 | output [max_burst_bytes_width:0]ddr_wr_bytes; 95 | 96 | input ddr_rd_dv; 97 | input [max_burst_bits-1:0] ddr_rd_data; 98 | output ddr_rd_req; 99 | output [addr_width-1:0] ddr_rd_addr; 100 | output [max_burst_bytes_width:0] ddr_rd_bytes; 101 | 102 | 103 | 104 | 105 | processing_system7_bfm_v2_0_arb_wr ddr_hp_wr( 106 | .rstn(rstn), 107 | .sw_clk(sw_clk), 108 | .qos1(w_qos_hp0), 109 | .qos2(w_qos_hp1), 110 | .prt_dv1(wr_dv_ddr_hp0), 111 | .prt_dv2(wr_dv_ddr_hp1), 112 | .prt_data1(wr_data_hp0), 113 | .prt_data2(wr_data_hp1), 114 | .prt_addr1(wr_addr_hp0), 115 | .prt_addr2(wr_addr_hp1), 116 | .prt_bytes1(wr_bytes_hp0), 117 | .prt_bytes2(wr_bytes_hp1), 118 | .prt_ack1(wr_ack_ddr_hp0), 119 | .prt_ack2(wr_ack_ddr_hp1), 120 | .prt_req(ddr_wr_dv), 121 | .prt_qos(ddr_wr_qos), 122 | .prt_data(ddr_wr_data), 123 | .prt_addr(ddr_wr_addr), 124 | .prt_bytes(ddr_wr_bytes), 125 | .prt_ack(ddr_wr_ack) 126 | ); 127 | 128 | processing_system7_bfm_v2_0_arb_rd ddr_hp_rd( 129 | .rstn(rstn), 130 | .sw_clk(sw_clk), 131 | .qos1(r_qos_hp0), 132 | .qos2(r_qos_hp1), 133 | .prt_req1(rd_req_ddr_hp0), 134 | .prt_req2(rd_req_ddr_hp1), 135 | .prt_data1(rd_data_ddr_hp0), 136 | .prt_data2(rd_data_ddr_hp1), 137 | .prt_addr1(rd_addr_hp0), 138 | .prt_addr2(rd_addr_hp1), 139 | .prt_bytes1(rd_bytes_hp0), 140 | .prt_bytes2(rd_bytes_hp1), 141 | .prt_dv1(rd_dv_ddr_hp0), 142 | .prt_dv2(rd_dv_ddr_hp1), 143 | .prt_qos(ddr_rd_qos), 144 | .prt_req(ddr_rd_req), 145 | .prt_data(ddr_rd_data), 146 | .prt_addr(ddr_rd_addr), 147 | .prt_bytes(ddr_rd_bytes), 148 | .prt_dv(ddr_rd_dv) 149 | ); 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_arb_hp2_3.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Module that arbitrates between RD/WR requests from 2 ports. 7 | * Used for modelling the Top_Interconnect switch. 8 | *****************************************************************************/ 9 | `timescale 1ns/1ps 10 | 11 | module processing_system7_bfm_v2_0_arb_hp2_3( 12 | sw_clk, 13 | rstn, 14 | w_qos_hp2, 15 | r_qos_hp2, 16 | w_qos_hp3, 17 | r_qos_hp3, 18 | 19 | wr_ack_ddr_hp2, 20 | wr_data_hp2, 21 | wr_addr_hp2, 22 | wr_bytes_hp2, 23 | wr_dv_ddr_hp2, 24 | rd_req_ddr_hp2, 25 | rd_addr_hp2, 26 | rd_bytes_hp2, 27 | rd_data_ddr_hp2, 28 | rd_dv_ddr_hp2, 29 | 30 | wr_ack_ddr_hp3, 31 | wr_data_hp3, 32 | wr_addr_hp3, 33 | wr_bytes_hp3, 34 | wr_dv_ddr_hp3, 35 | rd_req_ddr_hp3, 36 | rd_addr_hp3, 37 | rd_bytes_hp3, 38 | rd_data_ddr_hp3, 39 | rd_dv_ddr_hp3, 40 | 41 | ddr_wr_ack, 42 | ddr_wr_dv, 43 | ddr_rd_req, 44 | ddr_rd_dv, 45 | ddr_rd_qos, 46 | ddr_wr_qos, 47 | 48 | ddr_wr_addr, 49 | ddr_wr_data, 50 | ddr_wr_bytes, 51 | ddr_rd_addr, 52 | ddr_rd_data, 53 | ddr_rd_bytes 54 | 55 | ); 56 | `include "processing_system7_bfm_v2_0_local_params.v" 57 | input sw_clk; 58 | input rstn; 59 | input [axi_qos_width-1:0] w_qos_hp2; 60 | input [axi_qos_width-1:0] r_qos_hp2; 61 | input [axi_qos_width-1:0] w_qos_hp3; 62 | input [axi_qos_width-1:0] r_qos_hp3; 63 | input [axi_qos_width-1:0] ddr_rd_qos; 64 | input [axi_qos_width-1:0] ddr_wr_qos; 65 | 66 | output wr_ack_ddr_hp2; 67 | input [max_burst_bits-1:0] wr_data_hp2; 68 | input [addr_width-1:0] wr_addr_hp2; 69 | input [max_burst_bytes_width:0] wr_bytes_hp2; 70 | output wr_dv_ddr_hp2; 71 | 72 | input rd_req_ddr_hp2; 73 | input [addr_width-1:0] rd_addr_hp2; 74 | input [max_burst_bytes_width:0] rd_bytes_hp2; 75 | output [max_burst_bits-1:0] rd_data_ddr_hp2; 76 | output rd_dv_ddr_hp2; 77 | 78 | output wr_ack_ddr_hp3; 79 | input [max_burst_bits-1:0] wr_data_hp3; 80 | input [addr_width-1:0] wr_addr_hp3; 81 | input [max_burst_bytes_width:0] wr_bytes_hp3; 82 | output wr_dv_ddr_hp3; 83 | 84 | input rd_req_ddr_hp3; 85 | input [addr_width-1:0] rd_addr_hp3; 86 | input [max_burst_bytes_width:0] rd_bytes_hp3; 87 | output [max_burst_bits-1:0] rd_data_ddr_hp3; 88 | output rd_dv_ddr_hp3; 89 | 90 | input ddr_wr_ack; 91 | output ddr_wr_dv; 92 | output [addr_width-1:0]ddr_wr_addr; 93 | output [max_burst_bits-1:0]ddr_wr_data; 94 | output [max_burst_bytes_width:0]ddr_wr_bytes; 95 | 96 | input ddr_rd_dv; 97 | input [max_burst_bits-1:0] ddr_rd_data; 98 | output ddr_rd_req; 99 | output [addr_width-1:0] ddr_rd_addr; 100 | output [max_burst_bytes_width:0] ddr_rd_bytes; 101 | 102 | 103 | 104 | 105 | processing_system7_bfm_v2_0_arb_wr ddr_hp_wr( 106 | .rstn(rstn), 107 | .sw_clk(sw_clk), 108 | .qos1(w_qos_hp2), 109 | .qos2(w_qos_hp3), 110 | .prt_dv1(wr_dv_ddr_hp2), 111 | .prt_dv2(wr_dv_ddr_hp3), 112 | .prt_data1(wr_data_hp2), 113 | .prt_data2(wr_data_hp3), 114 | .prt_addr1(wr_addr_hp2), 115 | .prt_addr2(wr_addr_hp3), 116 | .prt_bytes1(wr_bytes_hp2), 117 | .prt_bytes2(wr_bytes_hp3), 118 | .prt_ack1(wr_ack_ddr_hp2), 119 | .prt_ack2(wr_ack_ddr_hp3), 120 | .prt_req(ddr_wr_dv), 121 | .prt_qos(ddr_wr_qos), 122 | .prt_data(ddr_wr_data), 123 | .prt_addr(ddr_wr_addr), 124 | .prt_bytes(ddr_wr_bytes), 125 | .prt_ack(ddr_wr_ack) 126 | ); 127 | 128 | processing_system7_bfm_v2_0_arb_rd ddr_hp_rd( 129 | .rstn(rstn), 130 | .sw_clk(sw_clk), 131 | .qos1(r_qos_hp2), 132 | .qos2(r_qos_hp3), 133 | .prt_req1(rd_req_ddr_hp2), 134 | .prt_req2(rd_req_ddr_hp3), 135 | .prt_data1(rd_data_ddr_hp2), 136 | .prt_data2(rd_data_ddr_hp3), 137 | .prt_addr1(rd_addr_hp2), 138 | .prt_addr2(rd_addr_hp3), 139 | .prt_bytes1(rd_bytes_hp2), 140 | .prt_bytes2(rd_bytes_hp3), 141 | .prt_dv1(rd_dv_ddr_hp2), 142 | .prt_dv2(rd_dv_ddr_hp3), 143 | .prt_req(ddr_rd_req), 144 | .prt_qos(ddr_rd_qos), 145 | .prt_data(ddr_rd_data), 146 | .prt_addr(ddr_rd_addr), 147 | .prt_bytes(ddr_rd_bytes), 148 | .prt_dv(ddr_rd_dv) 149 | ); 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_axi_acp.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_axi_acp.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Connections for ACP port 7 | * 8 | *****************************************************************************/ 9 | 10 | /* AXI Slave ACP */ 11 | processing_system7_bfm_v2_0_axi_slave #( C_USE_S_AXI_ACP, // enable 12 | axi_acp_name, // name 13 | axi_acp_data_width, // data width 14 | addr_width, /// address width 15 | axi_acp_id_width, // ID width 16 | C_S_AXI_ACP_BASEADDR, // slave base address 17 | C_S_AXI_ACP_HIGHADDR,// slave size 18 | axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes 19 | axi_slv_excl_support, // Exclusive access support 20 | axi_acp_wr_outstanding, 21 | axi_acp_rd_outstanding) 22 | S_AXI_ACP(.S_RESETN (net_axi_acp_rstn), 23 | .S_ACLK (S_AXI_ACP_ACLK), 24 | // Write Address Channel 25 | .S_AWID (S_AXI_ACP_AWID), 26 | .S_AWADDR (S_AXI_ACP_AWADDR), 27 | .S_AWLEN (S_AXI_ACP_AWLEN), 28 | .S_AWSIZE (S_AXI_ACP_AWSIZE), 29 | .S_AWBURST (S_AXI_ACP_AWBURST), 30 | .S_AWLOCK (S_AXI_ACP_AWLOCK), 31 | .S_AWCACHE (S_AXI_ACP_AWCACHE), 32 | .S_AWPROT (S_AXI_ACP_AWPROT), 33 | .S_AWVALID (S_AXI_ACP_AWVALID), 34 | .S_AWREADY (S_AXI_ACP_AWREADY), 35 | // Write Data Channel Signals. 36 | .S_WID (S_AXI_ACP_WID), 37 | .S_WDATA (S_AXI_ACP_WDATA), 38 | .S_WSTRB (S_AXI_ACP_WSTRB), 39 | .S_WLAST (S_AXI_ACP_WLAST), 40 | .S_WVALID (S_AXI_ACP_WVALID), 41 | .S_WREADY (S_AXI_ACP_WREADY), 42 | // Write Response Channel Signals. 43 | .S_BID (S_AXI_ACP_BID), 44 | .S_BRESP (S_AXI_ACP_BRESP), 45 | .S_BVALID (S_AXI_ACP_BVALID), 46 | .S_BREADY (S_AXI_ACP_BREADY), 47 | // Read Address Channel Signals. 48 | .S_ARID (S_AXI_ACP_ARID), 49 | .S_ARADDR (S_AXI_ACP_ARADDR), 50 | .S_ARLEN (S_AXI_ACP_ARLEN), 51 | .S_ARSIZE (S_AXI_ACP_ARSIZE), 52 | .S_ARBURST (S_AXI_ACP_ARBURST), 53 | .S_ARLOCK (S_AXI_ACP_ARLOCK), 54 | .S_ARCACHE (S_AXI_ACP_ARCACHE), 55 | .S_ARPROT (S_AXI_ACP_ARPROT), 56 | .S_ARVALID (S_AXI_ACP_ARVALID), 57 | .S_ARREADY (S_AXI_ACP_ARREADY), 58 | // Read Data Channel Signals. 59 | .S_RID (S_AXI_ACP_RID), 60 | .S_RDATA (S_AXI_ACP_RDATA), 61 | .S_RRESP (S_AXI_ACP_RRESP), 62 | .S_RLAST (S_AXI_ACP_RLAST), 63 | .S_RVALID (S_AXI_ACP_RVALID), 64 | .S_RREADY (S_AXI_ACP_RREADY), 65 | // Side band signals 66 | .S_AWQOS (S_AXI_ACP_AWQOS), 67 | .S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals 68 | 69 | .SW_CLK (net_sw_clk), 70 | /* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/ 71 | .WR_DATA_ACK_DDR (ddr_wr_ack_port0), 72 | .WR_DATA_ACK_OCM (ocm_wr_ack_port0), 73 | .WR_DATA (net_wr_data_acp), 74 | .WR_ADDR (net_wr_addr_acp), 75 | .WR_BYTES (net_wr_bytes_acp), 76 | .WR_DATA_VALID_DDR (ddr_wr_dv_port0), 77 | .WR_DATA_VALID_OCM (ocm_wr_dv_port0), 78 | .WR_QOS (net_wr_qos_acp), 79 | 80 | .RD_REQ_DDR (ddr_rd_req_port0), 81 | .RD_REQ_OCM (ocm_rd_req_port0), 82 | .RD_REQ_REG (reg_rd_req_port0), 83 | .RD_ADDR (net_rd_addr_acp), 84 | .RD_DATA_DDR (ddr_rd_data_port0), 85 | .RD_DATA_OCM (ocm_rd_data_port0), 86 | .RD_DATA_REG (reg_rd_data_port0), 87 | .RD_BYTES (net_rd_bytes_acp), 88 | .RD_DATA_VALID_DDR (ddr_rd_dv_port0), 89 | .RD_DATA_VALID_OCM (ocm_rd_dv_port0), 90 | .RD_DATA_VALID_REG (reg_rd_dv_port0), 91 | .RD_QOS (net_rd_qos_acp) 92 | 93 | ); 94 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_gen_clock.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_gen_clock.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Module that generates FCLK clocks and internal clock for Zynq BFM. 7 | * 8 | *****************************************************************************/ 9 | `timescale 1ns/1ps 10 | 11 | module processing_system7_bfm_v2_0_gen_clock( 12 | ps_clk, 13 | sw_clk, 14 | 15 | fclk_clk3, 16 | fclk_clk2, 17 | fclk_clk1, 18 | fclk_clk0 19 | ); 20 | 21 | input ps_clk; 22 | output sw_clk; 23 | 24 | output fclk_clk3; 25 | output fclk_clk2; 26 | output fclk_clk1; 27 | output fclk_clk0; 28 | 29 | parameter freq_clk3 = 50; 30 | parameter freq_clk2 = 50; 31 | parameter freq_clk1 = 50; 32 | parameter freq_clk0 = 50; 33 | 34 | reg clk0 = 1'b0; 35 | reg clk1 = 1'b0; 36 | reg clk2 = 1'b0; 37 | reg clk3 = 1'b0; 38 | reg sw_clk = 1'b0; 39 | 40 | assign fclk_clk0 = clk0; 41 | assign fclk_clk1 = clk1; 42 | assign fclk_clk2 = clk2; 43 | assign fclk_clk3 = clk3; 44 | 45 | real clk3_p = (1000.00/freq_clk3)/2; 46 | real clk2_p = (1000.00/freq_clk2)/2; 47 | real clk1_p = (1000.00/freq_clk1)/2; 48 | real clk0_p = (1000.00/freq_clk0)/2; 49 | 50 | always #(clk3_p) clk3 = !clk3; 51 | always #(clk2_p) clk2 = !clk2; 52 | always #(clk1_p) clk1 = !clk1; 53 | always #(clk0_p) clk0 = !clk0; 54 | 55 | always #(0.5) sw_clk = !sw_clk; 56 | 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_intr_rd_mem.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Mimics interconnect for Reads between AFI and DDRC/OCM 7 | * 8 | *****************************************************************************/ 9 | `timescale 1ns/1ps 10 | 11 | module processing_system7_bfm_v2_0_intr_rd_mem( 12 | sw_clk, 13 | rstn, 14 | 15 | full, 16 | empty, 17 | 18 | req, 19 | invalid_rd_req, 20 | rd_info, 21 | 22 | RD_DATA_OCM, 23 | RD_DATA_DDR, 24 | RD_DATA_VALID_OCM, 25 | RD_DATA_VALID_DDR 26 | 27 | ); 28 | `include "processing_system7_bfm_v2_0_local_params.v" 29 | 30 | input sw_clk, rstn; 31 | output full, empty; 32 | 33 | input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM; 34 | input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM; 35 | input req, invalid_rd_req; 36 | input [rd_info_bits-1:0] rd_info; 37 | 38 | reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; 39 | reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes 40 | wire full, empty; 41 | 42 | 43 | assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; 44 | assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; 45 | 46 | /* read from the fifo */ 47 | task read_mem; 48 | output [rd_afi_fifo_bits-1:0] data; 49 | begin 50 | data = rd_fifo[rd_ptr[intr_cnt_width-1:0]]; 51 | if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 52 | rd_ptr[intr_cnt_width-2:0] = 0; 53 | else 54 | rd_ptr = rd_ptr + 1; 55 | end 56 | endtask 57 | 58 | reg state; 59 | reg invalid_rd; 60 | /* write in the fifo */ 61 | always@(negedge rstn or posedge sw_clk) 62 | begin 63 | if(!rstn) begin 64 | wr_ptr = 0; 65 | rd_ptr = 0; 66 | state = 0; 67 | invalid_rd = 0; 68 | end else begin 69 | case (state) 70 | 0 : begin 71 | state = 0; 72 | invalid_rd = 0; 73 | if(req)begin 74 | state = 1; 75 | invalid_rd = invalid_rd_req; 76 | end 77 | end 78 | 1 : begin 79 | state = 1; 80 | if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin 81 | if(RD_DATA_VALID_DDR) 82 | rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info}; 83 | else if(RD_DATA_VALID_OCM) 84 | rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info}; 85 | else 86 | rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info; 87 | if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 88 | wr_ptr[intr_cnt_width-2:0] = 0; 89 | else 90 | wr_ptr = wr_ptr + 1; 91 | state = 0; 92 | invalid_rd = 0; 93 | end 94 | end 95 | endcase 96 | end 97 | end 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_intr_wr_mem.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Mimics interconnect for Writes between AFI and DDRC/OCM 7 | * 8 | *****************************************************************************/ 9 | `timescale 1ns/1ps 10 | 11 | module processing_system7_bfm_v2_0_intr_wr_mem( 12 | sw_clk, 13 | rstn, 14 | 15 | full, 16 | 17 | WR_DATA_ACK_OCM, 18 | WR_DATA_ACK_DDR, 19 | WR_ADDR, 20 | WR_DATA, 21 | WR_BYTES, 22 | WR_QOS, 23 | WR_DATA_VALID_OCM, 24 | WR_DATA_VALID_DDR 25 | ); 26 | 27 | `include "processing_system7_bfm_v2_0_local_params.v" 28 | /* local parameters for interconnect wr fifo model */ 29 | 30 | input sw_clk, rstn; 31 | output full; 32 | 33 | input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM; 34 | output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM; 35 | output reg [max_burst_bits-1:0] WR_DATA; 36 | output reg [addr_width-1:0] WR_ADDR; 37 | output reg [max_burst_bytes_width:0] WR_BYTES; 38 | output reg [axi_qos_width-1:0] WR_QOS; 39 | reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0; 40 | reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1]; 41 | wire empty; 42 | 43 | assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0; 44 | assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0; 45 | 46 | parameter SEND_DATA = 0, WAIT_ACK = 1; 47 | reg state; 48 | 49 | task automatic write_mem; 50 | input [wr_fifo_data_bits-1:0] data; 51 | begin 52 | wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data; 53 | if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) 54 | wr_ptr[intr_cnt_width-2:0] = 0; 55 | else 56 | wr_ptr = wr_ptr + 1; 57 | end 58 | endtask 59 | 60 | always@(negedge rstn or posedge sw_clk) 61 | begin 62 | if(!rstn) begin 63 | wr_ptr = 0; 64 | rd_ptr = 0; 65 | WR_DATA_VALID_DDR = 1'b0; 66 | WR_DATA_VALID_OCM = 1'b0; 67 | WR_QOS = 0; 68 | state = SEND_DATA; 69 | end else begin 70 | case(state) 71 | SEND_DATA :begin 72 | state = SEND_DATA; 73 | WR_DATA_VALID_OCM = 1'b0; 74 | WR_DATA_VALID_DDR = 1'b0; 75 | if(!empty) begin 76 | WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb]; 77 | WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]; 78 | WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb]; 79 | WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb]; 80 | state = WAIT_ACK; 81 | case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb])) 82 | OCM_MEM : WR_DATA_VALID_OCM = 1; 83 | DDR_MEM : WR_DATA_VALID_DDR = 1; 84 | default : state = SEND_DATA; 85 | endcase 86 | if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin 87 | rd_ptr[intr_cnt_width-2:0] = 0; 88 | end else begin 89 | rd_ptr = rd_ptr+1; 90 | end 91 | end 92 | end 93 | WAIT_ACK :begin 94 | state = WAIT_ACK; 95 | if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin 96 | WR_DATA_VALID_OCM = 1'b0; 97 | WR_DATA_VALID_DDR = 1'b0; 98 | state = SEND_DATA; 99 | end 100 | end 101 | endcase 102 | end 103 | end 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/adcdcea3/hdl/processing_system7_bfm_v2_0_regc.v: -------------------------------------------------------------------------------- 1 | /***************************************************************************** 2 | * File : processing_system7_bfm_v2_0_regc.v 3 | * 4 | * Date : 2012-11 5 | * 6 | * Description : Controller for Register Map Memory 7 | * 8 | *****************************************************************************/ 9 | `timescale 1ns/1ps 10 | 11 | module processing_system7_bfm_v2_0_regc( 12 | rstn, 13 | sw_clk, 14 | 15 | /* Goes to port 0 of REG */ 16 | reg_rd_req_port0, 17 | reg_rd_dv_port0, 18 | reg_rd_addr_port0, 19 | reg_rd_data_port0, 20 | reg_rd_bytes_port0, 21 | reg_rd_qos_port0, 22 | 23 | 24 | /* Goes to port 1 of REG */ 25 | reg_rd_req_port1, 26 | reg_rd_dv_port1, 27 | reg_rd_addr_port1, 28 | reg_rd_data_port1, 29 | reg_rd_bytes_port1, 30 | reg_rd_qos_port1 31 | 32 | ); 33 | 34 | input rstn; 35 | input sw_clk; 36 | 37 | input reg_rd_req_port0; 38 | output reg_rd_dv_port0; 39 | input[31:0] reg_rd_addr_port0; 40 | output[1023:0] reg_rd_data_port0; 41 | input[7:0] reg_rd_bytes_port0; 42 | input [3:0] reg_rd_qos_port0; 43 | 44 | input reg_rd_req_port1; 45 | output reg_rd_dv_port1; 46 | input[31:0] reg_rd_addr_port1; 47 | output[1023:0] reg_rd_data_port1; 48 | input[7:0] reg_rd_bytes_port1; 49 | input[3:0] reg_rd_qos_port1; 50 | 51 | wire [3:0] rd_qos; 52 | reg [1023:0] rd_data; 53 | wire [31:0] rd_addr; 54 | wire [7:0] rd_bytes; 55 | reg rd_dv; 56 | wire rd_req; 57 | 58 | processing_system7_bfm_v2_0_arb_rd reg_read_ports ( 59 | .rstn(rstn), 60 | .sw_clk(sw_clk), 61 | 62 | .qos1(reg_rd_qos_port0), 63 | .qos2(reg_rd_qos_port1), 64 | 65 | .prt_req1(reg_rd_req_port0), 66 | .prt_req2(reg_rd_req_port1), 67 | 68 | .prt_data1(reg_rd_data_port0), 69 | .prt_data2(reg_rd_data_port1), 70 | 71 | .prt_addr1(reg_rd_addr_port0), 72 | .prt_addr2(reg_rd_addr_port1), 73 | 74 | .prt_bytes1(reg_rd_bytes_port0), 75 | .prt_bytes2(reg_rd_bytes_port1), 76 | 77 | .prt_dv1(reg_rd_dv_port0), 78 | .prt_dv2(reg_rd_dv_port1), 79 | 80 | .prt_qos(rd_qos), 81 | .prt_req(rd_req), 82 | .prt_data(rd_data), 83 | .prt_addr(rd_addr), 84 | .prt_bytes(rd_bytes), 85 | .prt_dv(rd_dv) 86 | 87 | ); 88 | 89 | processing_system7_bfm_v2_0_reg_map regm(); 90 | 91 | reg state; 92 | always@(posedge sw_clk or negedge rstn) 93 | begin 94 | if(!rstn) begin 95 | rd_dv <= 0; 96 | state <= 0; 97 | end else begin 98 | case(state) 99 | 0:begin 100 | state <= 0; 101 | rd_dv <= 0; 102 | if(rd_req) begin 103 | regm.read_reg_mem(rd_data,rd_addr, rd_bytes); 104 | rd_dv <= 1; 105 | state <= 1; 106 | end 107 | 108 | end 109 | 1:begin 110 | rd_dv <= 0; 111 | state <= 0; 112 | end 113 | 114 | endcase 115 | end /// if 116 | end// always 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/fixedio.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | display_processing_system7 5 | fixedio 6 | 1.0 7 | false 8 | false 9 | Zynq fixed IO interface consisting of ports with fixed locations 10 | 11 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/hpstatusctrl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | display_processing_system7 5 | hpstatusctrl 6 | 1.0 7 | false 8 | false 9 | Zynq HP status ctrl interface consists of FIFO occupancy and Interconnect Issuance Throttling signals for High performance axi interface 10 | 11 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | interface 5 | jtag 6 | 2.0 7 | true 8 | false 9 | 1 10 | 1 11 | Provides debug access via a standard JTAG debug interface 12 | 13 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/jtag_rtl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | interface 5 | jtag_rtl 6 | 2.0 7 | 8 | 9 | 10 | TCK 11 | 12 | 13 | true 14 | 15 | 16 | required 17 | 1 18 | out 19 | 20 | 21 | required 22 | 1 23 | in 24 | 25 | 26 | 27 | 28 | TMS 29 | 30 | 31 | required 32 | 1 33 | out 34 | 35 | 36 | required 37 | 1 38 | in 39 | 40 | 41 | 42 | 43 | TDI 44 | 45 | 46 | true 47 | 48 | 49 | required 50 | 1 51 | out 52 | 53 | 54 | required 55 | 1 56 | in 57 | 58 | 59 | 60 | 61 | TDO 62 | 63 | 64 | true 65 | 66 | 67 | required 68 | 1 69 | in 70 | 71 | 72 | required 73 | 1 74 | out 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | display_processing_system7 5 | usbctrl 6 | 1.0 7 | false 8 | false 9 | The usbctrl interface consists of Port indicator and power signals 10 | 11 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/vivado/z_turn20.srcs/sources_1/ipshared/xilinx.com/processing_system7_v5_5/ad955ff5/usbctrl_rtl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | display_processing_system7 5 | usbctrl_rtl 6 | 1.0 7 | 8 | 9 | 10 | PORT_INDCTL 11 | Port Indicator 12 | 13 | 14 | optional 15 | 2 16 | out 17 | 18 | 19 | optional 20 | 2 21 | in 22 | 23 | 24 | 25 | 26 | VBUS_PWRSELECT 27 | Power Select 28 | 29 | 30 | optional 31 | 1 32 | out 33 | 34 | 35 | optional 36 | 1 37 | in 38 | 39 | 40 | 41 | 42 | VBUS_PWRFAULT 43 | Power Fault 44 | 45 | 46 | optional 47 | 1 48 | in 49 | 50 | 51 | optional 52 | 1 53 | out 54 | 55 | 56 | 57 | 58 | 59 | -------------------------------------------------------------------------------- /sdsoc/zturn-7z020/z_turn20_sw.pfm: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Basic platform targeting the Z-turn Board, which includes 1 GB of DDR3, 128 Mb QSPI Flash and a MicroSD card interface. More information at http://www.myir-tech.com/product/z-turn_board.htm 5 | 6 | 11 | 12 | 17 | 18 | 25 | 26 | 27 | 28 | --------------------------------------------------------------------------------