├── RELEASE_NOTES ├── bindings ├── vb6 │ ├── Form1.frx │ ├── screenshot.png │ ├── CX86Operand.cls │ ├── Project1.vbw │ ├── vbCapstone.sln │ ├── CX86OpMem.cls │ ├── README.txt │ └── Project1.vbp ├── java │ ├── capstone │ │ └── .gitignore │ ├── .gitignore │ ├── README │ └── run.sh ├── python │ ├── prebuilt │ │ └── .gitkeep │ ├── setup.cfg │ ├── pyx │ │ └── README │ ├── MANIFEST.in │ ├── .gitignore │ ├── build_wheel.sh │ ├── capstone │ │ ├── evm.py │ │ ├── mos65xx.py │ │ ├── mips.py │ │ ├── xcore.py │ │ └── systemz.py │ ├── test_all.py │ ├── test_evm.py │ └── test_customized_mnem.py ├── powershell │ ├── Capstone │ │ └── Lib │ │ │ └── Capstone │ │ │ └── .gitignore │ └── README.md └── ocaml │ ├── mips.ml │ ├── xcore.ml │ ├── sparc.ml │ ├── systemz.ml │ ├── ppc.ml │ ├── README │ ├── x86.ml │ ├── arm64.ml │ ├── m680x.ml │ └── arm.ml ├── .gitattributes ├── suite ├── fuzz │ ├── fuzz_disasm.options │ ├── README │ ├── onefile.c │ └── fuzz_llvm.cpp ├── x86 │ ├── README │ └── verify │ │ └── README ├── MC │ ├── Mips │ │ ├── mips-jump-instructions.s.cs │ │ ├── mips64-instructions.s.cs │ │ ├── hilo-addressing.s.cs │ │ ├── test_elm_insert.s.cs │ │ ├── set-at-directive.s.cs │ │ ├── test_i10.s.cs │ │ ├── micromips-jump-instructions-EB.s.cs │ │ ├── micromips-multiply-instructions.s.cs │ │ ├── micromips-jump-instructions.s.cs │ │ ├── micromips-loadstore-unaligned.s.cs │ │ ├── test_lsa.s.cs │ │ ├── micromips-movcond-instructions.s.cs │ │ ├── micromips-multiply-instructions-EB.s.cs │ │ ├── test_elm_insve.s.cs │ │ ├── micromips-loadstore-unaligned-EB.s.cs │ │ ├── micromips-movcond-instructions-EB.s.cs │ │ ├── test_vec.s.cs │ │ ├── micromips-loadstore-instructions.s.cs │ │ ├── micromips-shift-instructions.s.cs │ │ ├── micromips-loadstore-instructions-EB.s.cs │ │ ├── micromips-shift-instructions-EB.s.cs │ │ ├── mips_directives.s.cs │ │ ├── micromips-branch-instructions.s.cs │ │ ├── test_cbranch.s.cs │ │ ├── micromips-branch-instructions-EB.s.cs │ │ ├── test_i8.s.cs │ │ ├── nabi-regs.s.cs │ │ ├── micromips-trap-instructions.s.cs │ │ ├── micromips-trap-instructions-EB.s.cs │ │ ├── test_2r.s.cs │ │ ├── mips-memory-instructions.s.cs │ │ ├── test_elm.s.cs │ │ ├── mips-coprocessor-encodings.s.cs │ │ ├── mips-expansions.s.cs │ │ ├── micromips-expansions.s.cs │ │ ├── test_mi10.s.cs │ │ └── mips-control-instructions.s.cs │ ├── X86 │ │ ├── x86_64-sse4a.s.cs │ │ ├── x86_64-rtm-encoding.s.cs │ │ ├── address-size.s.cs │ │ ├── x86_64-rand-encoding.s.cs │ │ ├── x86_64-avx-clmul-encoding.s.cs │ │ ├── avx512-encodings.s.cs │ │ ├── intel-syntax-encoding.s.cs │ │ ├── x86-32-ms-inline-asm.s.cs │ │ └── 3DNow.s.cs │ ├── Sparc │ │ ├── sparcv9-instructions.s.cs │ │ ├── sparc-vis.s.cs │ │ ├── sparcv8-instructions.s.cs │ │ ├── sparc-atomic-instructions.s.cs │ │ ├── sparc-ctrl-instructions.s.cs │ │ ├── sparc64-alu-instructions.s.cs │ │ └── sparc-mem-instructions.s.cs │ ├── ARM │ │ ├── basic-thumb2-instructions-v8.s.cs │ │ ├── arm-it-block.s.cs │ │ ├── thumb2-pldw.s.cs │ │ ├── thumb2-b.w-encodingT4.s.cs │ │ ├── arm-thumb-trustzone.s.cs │ │ ├── arm-trustzone.s.cs │ │ ├── dot-req.s.cs │ │ ├── idiv.s.cs │ │ ├── neon-vswp.s.cs │ │ ├── idiv-thumb.s.cs │ │ ├── mode-switch.s.cs │ │ ├── arm-aliases.s.cs │ │ ├── crc32.s.cs │ │ ├── crc32-thumb.s.cs │ │ ├── thumb-hints.s.cs │ │ ├── basic-arm-instructions-v8.s.cs │ │ ├── arm_addrmode3.s.cs │ │ ├── vpush-vpop.s.cs │ │ ├── vpush-vpop-thumb.s.cs │ │ ├── neon-table-encoding.s.cs │ │ ├── neont2-table-encoding.s.cs │ │ ├── thumb.s.cs │ │ ├── neon-dup-encoding.s.cs │ │ ├── neon-reverse-encoding.s.cs │ │ ├── neont2-reverse-encoding.s.cs │ │ ├── vfp4.s.cs │ │ ├── neon-reciprocal-encoding.s.cs │ │ ├── vfp4-thumb.s.cs │ │ ├── neont2-reciprocal-encoding.s.cs │ │ ├── neon-bitcount-encoding.s.cs │ │ ├── neon-abs-encoding.s.cs │ │ ├── neon-neg-encoding.s.cs │ │ ├── neont2-bitcount-encoding.s.cs │ │ ├── neont2-abs-encoding.s.cs │ │ ├── neont2-bitwise-encoding.s.cs │ │ ├── neont2-neg-encoding.s.cs │ │ ├── load-store-acquire-release-v8.s.cs │ │ ├── load-store-acquire-release-v8-thumb.s.cs │ │ ├── arm_addrmode2.s.cs │ │ ├── neon-crypto.s.cs │ │ ├── thumb-neon-crypto.s.cs │ │ ├── neont2-cmp-encoding.s.cs │ │ ├── neont2-dup-encoding.s.cs │ │ ├── neont2-convert-encoding.s.cs │ │ ├── thumb-shift-encoding.s.cs │ │ ├── neont2-sub-encoding.s.cs │ │ ├── neont2-shuffle-encoding.s.cs │ │ ├── arm_instructions.s.cs │ │ └── neon-convert-encoding.s.cs │ ├── AArch64 │ │ ├── neon-scalar-add-sub.s.cs │ │ ├── neon-scalar-shift.s.cs │ │ ├── neon-scalar-reduce-pairwise.s.cs │ │ ├── neon-scalar-rounding-shift.s.cs │ │ ├── neon-extract.s.cs │ │ ├── neon-scalar-neg.s.cs │ │ ├── neon-scalar-abs.s.cs │ │ ├── neon-frsqrt-frecp.s.cs │ │ ├── neon-scalar-saturating-shift.s.cs │ │ ├── neon-scalar-extract-narrow.s.cs │ │ ├── neon-scalar-saturating-rounding-shift.s.cs │ │ ├── neon-scalar-recip.s.cs │ │ ├── neon-scalar-compare.s.cs │ │ ├── neon-add-pairwise.s.cs │ │ ├── neon-scalar-mul.s.cs │ │ ├── neon-scalar-by-elem-mla.s.cs │ │ ├── neon-scalar-by-elem-mul.s.cs │ │ ├── neon-shift-left-long.s.cs │ │ ├── neon-facge-facgt.s.cs │ │ ├── neon-rounding-halving-add.s.cs │ │ ├── neon-crypto.s.cs │ │ ├── neon-rounding-shift.s.cs │ │ ├── neon-saturating-shift.s.cs │ │ ├── neon-scalar-by-elem-saturating-mla.s.cs │ │ ├── neon-saturating-rounding-shift.s.cs │ │ ├── neon-bitwise-instructions.s.cs │ │ ├── neon-scalar-by-elem-saturating-mul.s.cs │ │ ├── neon-mla-mls-instructions.s.cs │ │ ├── neon-scalar-fp-compare.s.cs │ │ ├── neon-scalar-dup.s.cs │ │ ├── neon-add-sub-instructions.s.cs │ │ ├── neon-shift.s.cs │ │ ├── neon-scalar-saturating-add-sub.s.cs │ │ ├── neon-mul-div-instructions.s.cs │ │ └── neon-halving-add-sub.s.cs │ ├── README │ └── PowerPC │ │ ├── ppc64-encoding-bookII.s.cs │ │ └── ppc64-operands.s.cs ├── python_capstone_setup.py ├── test_all.sh ├── regress │ ├── Makefile │ ├── invalid_read_in_print_operand.c │ └── regress.py ├── arm │ └── Makefile ├── cstest │ ├── Makefile │ ├── build_cstest.sh │ ├── src │ │ └── evm_detail.c │ └── include │ │ ├── helper.h │ │ └── factory.h ├── benchmark │ └── Makefile ├── disasm_mc.sh ├── test_python.sh ├── test_c.sh ├── test_mc.sh ├── compile_all.sh ├── patch_major_os_version.py └── README ├── windows ├── README └── winkernel_mm.h ├── docs ├── capstone-logo.png ├── BHUSA2014-capstone.pdf └── Capstone-Engine-Documentation │ └── API_Doc_Pic │ ├── 1.jpg │ ├── 2.jpg │ ├── 3.jpg │ ├── 4.jpg │ ├── 5.jpg │ ├── 6.jpg │ ├── 7.jpg │ ├── 8.jpg │ ├── 9.jpg │ ├── 10.jpg │ ├── 11.jpg │ ├── 12.jpg │ ├── 13.jpg │ ├── 14.jpg │ ├── 15.jpg │ ├── 16.jpg │ ├── 17.jpg │ ├── 18.jpg │ ├── 19.jpg │ ├── 20.jpg │ ├── 21.jpg │ ├── 22.jpg │ ├── 23.jpg │ ├── 24.jpg │ ├── 25.jpg │ └── 26.jpg ├── xcode ├── CapstoneFramework │ ├── module.modulemap │ └── Info.plist └── Capstone.xcodeproj │ └── project.xcworkspace │ └── contents.xcworkspacedata ├── windowsce └── .gitignore ├── contrib ├── README ├── cs_driver │ ├── README │ └── cs_driver │ │ └── cs_driver.vcxproj.filters └── windows_kernel │ ├── README │ └── libc.h ├── functions.mk ├── arch ├── EVM │ ├── EVMMapping.h │ ├── EVMModule.h │ ├── EVMDisassembler.h │ ├── EVMInstPrinter.h │ ├── EVMInstPrinter.c │ └── EVMModule.c ├── ARM │ ├── ARMModule.h │ ├── ARMDisassembler.h │ └── ARMMapping.h ├── X86 │ ├── X86Module.h │ └── X86InstPrinter.h ├── M68K │ ├── M68KModule.h │ ├── M68KInstPrinter.h │ ├── M68KModule.c │ └── M68KDisassembler.h ├── Mips │ ├── MipsModule.h │ ├── MipsDisassembler.h │ ├── MipsMapping.h │ ├── MipsInstPrinter.h │ └── MipsModule.c ├── M680X │ ├── M680XModule.h │ ├── hd6301.inc │ ├── M680XDisassembler.h │ └── M680XInstPrinter.h ├── PowerPC │ ├── PPCModule.h │ ├── PPCInstPrinter.h │ ├── PPCDisassembler.h │ ├── PPCMapping.h │ └── PPCModule.c ├── Sparc │ ├── SparcModule.h │ ├── SparcInstPrinter.h │ ├── SparcDisassembler.h │ ├── SparcMapping.h │ ├── SparcModule.c │ └── SparcGenSubtargetInfo.inc ├── XCore │ ├── XCoreModule.h │ ├── XCoreDisassembler.h │ ├── XCoreInstPrinter.h │ ├── XCoreMapping.h │ └── XCoreModule.c ├── AArch64 │ ├── AArch64Module.h │ ├── AArch64Disassembler.h │ ├── AArch64InstPrinter.h │ ├── AArch64Module.c │ └── AArch64GenSubtargetInfo.inc ├── MOS65XX │ ├── MOS65XXModule.h │ ├── MOS65XXDisassembler.h │ └── MOS65XXModule.c ├── SystemZ │ ├── SystemZModule.h │ ├── SystemZInstPrinter.h │ ├── SystemZDisassembler.h │ ├── SystemZMapping.h │ └── SystemZModule.c └── TMS320C64x │ ├── TMS320C64xModule.h │ ├── TMS320C64xInstPrinter.h │ ├── TMS320C64xDisassembler.h │ ├── TMS320C64xMapping.h │ └── TMS320C64xModule.c ├── pkgconfig.mk ├── .appveyor.yml ├── MCDisassembler.h ├── include └── windowsce │ └── intrin.h ├── capstone.pc.in ├── packages ├── freebsd │ └── ports │ │ └── devel │ │ └── capstone │ │ ├── pkg-plist │ │ ├── Makefile │ │ └── pkg-descr └── macports │ └── devel │ └── capstone │ └── files │ └── patch-Makefile.diff ├── TODO ├── MCInstrDesc.c ├── cstool ├── cstool_evm.c └── Makefile ├── .github └── workflows │ └── fuzz.yml ├── SPONSORS.TXT ├── SStream.h ├── nmake.bat ├── msvc └── README ├── LEB128.h ├── cmake.sh └── tests └── README /RELEASE_NOTES: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bindings/vb6/Form1.frx: -------------------------------------------------------------------------------- 1 | Text1 -------------------------------------------------------------------------------- /bindings/java/capstone/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bindings/python/prebuilt/.gitkeep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bindings/java/.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | tags 3 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | /arch/**/*.inc linguist-language=C 2 | -------------------------------------------------------------------------------- /bindings/powershell/Capstone/Lib/Capstone/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bindings/python/setup.cfg: -------------------------------------------------------------------------------- 1 | [bdist_wheel] 2 | universal = 1 3 | -------------------------------------------------------------------------------- /bindings/python/pyx/README: -------------------------------------------------------------------------------- 1 | This directory contains Cython files. 2 | -------------------------------------------------------------------------------- /suite/fuzz/fuzz_disasm.options: -------------------------------------------------------------------------------- 1 | [libfuzzer] 2 | max_len = 4096 3 | -------------------------------------------------------------------------------- /suite/x86/README: -------------------------------------------------------------------------------- 1 | This directory contains some tools to test X86 engine. 2 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips-jump-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | -------------------------------------------------------------------------------- /suite/MC/X86/x86_64-sse4a.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | -------------------------------------------------------------------------------- /windows/README: -------------------------------------------------------------------------------- 1 | This directory contains code specific to Windows platforms. 2 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparcv9-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | -------------------------------------------------------------------------------- /docs/capstone-logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/qemu/capstone/HEAD/docs/capstone-logo.png -------------------------------------------------------------------------------- /suite/MC/ARM/basic-thumb2-instructions-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | -------------------------------------------------------------------------------- /bindings/vb6/screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/qemu/capstone/HEAD/bindings/vb6/screenshot.png -------------------------------------------------------------------------------- /docs/BHUSA2014-capstone.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/qemu/capstone/HEAD/docs/BHUSA2014-capstone.pdf -------------------------------------------------------------------------------- /bindings/vb6/CX86Operand.cls: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/qemu/capstone/HEAD/bindings/vb6/CX86Operand.cls -------------------------------------------------------------------------------- /suite/MC/ARM/arm-it-block.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x03,0x20,0xa0,0x01 = moveq r2, r3 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-pldw.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xb0,0xf8,0x01,0xf1 = pldw [r0, #257] 3 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-vis.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xbf,0xb0,0x0c,0x20 = fzeros %f31 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb2-b.w-encodingT4.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x36,0xf0,0x06,0xbc = b.w #223248 3 | -------------------------------------------------------------------------------- /suite/fuzz/README: -------------------------------------------------------------------------------- 1 | This directory contains a fuzz testing harness for Capstone. 2 | Run "make" to compile this code. 3 | -------------------------------------------------------------------------------- /xcode/CapstoneFramework/module.modulemap: -------------------------------------------------------------------------------- 1 | module capstone { 2 | header "Headers/capstone.h" 3 | export * 4 | } 5 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-thumb-trustzone.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xff,0xf7,0x00,0x80 = smc #15 3 | 0x0c,0xbf = ite eq 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-trustzone.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x7f,0x00,0x60,0xe1 = smc #15 3 | 0x70,0x00,0x60,0x01 = smceq #0 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/dot-req.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x05,0xb0,0xa0,0xe1 = mov r11, r5 3 | 0x06,0x10,0xa0,0xe1 = mov r1, r6 4 | -------------------------------------------------------------------------------- /suite/x86/verify/README: -------------------------------------------------------------------------------- 1 | This directory contains some tools to verify Capstone output, 2 | as well as semantics of X86 machine code. 3 | -------------------------------------------------------------------------------- /suite/MC/ARM/idiv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3 3 | 0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5 4 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-vswp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x02,0x10,0xb2,0xf3 = vswp d1, d2 3 | 0x44,0x20,0xb2,0xf3 = vswp q1, q2 4 | -------------------------------------------------------------------------------- /bindings/python/MANIFEST.in: -------------------------------------------------------------------------------- 1 | recursive-include src * 2 | include LICENSE.TXT 3 | include README.txt 4 | include BUILDING.txt 5 | include Makefile 6 | -------------------------------------------------------------------------------- /docs/Capstone-Engine-Documentation/API_Doc_Pic/1.jpg: -------------------------------------------------------------------------------- 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0x1f,0x84,0xf0,0x5e = add d31, d0, d16 3 | 0xe1,0x84,0xe8,0x7e = sub d1, d7, d8 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xf1,0x47,0xe8,0x5e = sshl d17, d31, d8 3 | 0xf1,0x47,0xe8,0x7e = ushl d17, d31, d8 4 | -------------------------------------------------------------------------------- /bindings/python/.gitignore: -------------------------------------------------------------------------------- 1 | MANIFEST 2 | dist/ 3 | src/ 4 | capstone/lib 5 | capstone/include 6 | pyx/lib 7 | pyx/include 8 | pyx/*.c 9 | pyx/*.pyx 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0xb8,0xf1,0x5e = addp d0, v1.2d 3 | 0x34,0xd8,0x70,0x7e = faddp d20, v1.2d 4 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xf1,0x57,0xe8,0x5e = srshl d17, d31, d8 3 | 0xf1,0x57,0xe8,0x7e = urshl d17, d31, d8 4 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips64-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64, None 2 | 0x81,0x00,0x42,0x4d = ldxc1 $f2, $v0($t2) 3 | 0x09,0x40,0x24,0x4f = sdxc1 $f8, $a0($t9) 4 | -------------------------------------------------------------------------------- /suite/MC/X86/x86_64-rtm-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x0f,0x01,0xd5 = xend 3 | 0x0f,0x01,0xd6 = xtest 4 | 0xc6,0xf8,0x0d = xabort $13 5 | -------------------------------------------------------------------------------- /suite/python_capstone_setup.py: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # this prints out Capstone setup & core+Python-binding versions 3 | 4 | python -c "import capstone; print capstone.debug()" 5 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-extract.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x18,0x02,0x2e = ext v0.8b, v1.8b, v2.8b, #0x3 3 | 0x20,0x18,0x02,0x6e = ext v0.16b, v1.16b, v2.16b, #0x3 4 | -------------------------------------------------------------------------------- /windowsce/.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.obj 3 | 4 | # Libraries 5 | *.lib 6 | 7 | # Shared objects (inc. Windows DLLs) 8 | *.dll 9 | 10 | # VisualStudio 11 | *.exp 12 | *.map 13 | *.pdb 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/mode-switch.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1 3 | 0x40,0x18 = adds r0, r0, r1 4 | 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1 5 | 0x40,0x18 = adds r0, r0, r1 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/hilo-addressing.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | // 0x3c,0x04,0xde,0xae = lui $a0, %hi(addr) 3 | 0x03,0xe0,0x00,0x08 = jr $ra 4 | // 0x80,0x82,0xbe,0xef = lb $v0, %lo(addr)($a0) 5 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_elm_insert.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp 3 | 0x79,0x22,0x2d,0x19 = insert.h $w20[2], $a1 4 | 0x79,0x32,0x7a,0x19 = insert.w $w8[2], $t7 5 | -------------------------------------------------------------------------------- /suite/MC/Mips/set-at-directive.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x08,0x00,0x60,0x00 = jr $v1 3 | 0x08,0x00,0x80,0x03 = jr $gp 4 | 0x08,0x00,0xc0,0x03 = jr $fp 5 | 0x08,0x00,0xa0,0x03 = jr $sp 6 | 0x08,0x00,0xe0,0x03 = jr $ra 7 | -------------------------------------------------------------------------------- /xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata: -------------------------------------------------------------------------------- 1 | 2 | 4 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_i10.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x7b,0x06,0x32,0x07 = ldi.b $w8, 198 3 | 0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313 4 | 0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492 5 | // 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180 6 | -------------------------------------------------------------------------------- /contrib/README: -------------------------------------------------------------------------------- 1 | This directory contains contributions that do not belong to the core engine. 2 | Code here might be helpful for those who want to integrate Capstone into 3 | their own projects. 4 | 5 | The license of these code was defined by their authors. 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-jump-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0xd4,0x00,0x02,0x98 = j 1328 3 | 0xf4,0x00,0x02,0x98 = jal 1328 4 | // 0x03,0xe6,0x0f,0x3c = jalr $a2 5 | 0x00,0x07,0x0f,0x3c = jr $a3 6 | -------------------------------------------------------------------------------- /suite/MC/X86/address-size.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | // 0x67,// 0xc6,0x06,0x00 = movb $0x0, (%esi) 3 | // 0xc6,0x06,0x00 = movb $0x0, (%rsi) 4 | // 0x67,// 0xc6,0x06,0x00 = movb $0x0, (%si) 5 | // 0xc6,0x06,0x00 = movb $0x0, (%esi) 6 | -------------------------------------------------------------------------------- /functions.mk: -------------------------------------------------------------------------------- 1 | # Capstone Disassembly Engine 2 | # Common functions used by Makefile & tests/Makefile 3 | 4 | define compile 5 | ${CC} ${CFLAGS} -c $< -o $@ 6 | endef 7 | 8 | 9 | define log 10 | @printf " %-7s %s\n" "$(1)" "$(2)" 11 | endef 12 | 13 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-multiply-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa4,0x00,0x3c,0xcb = madd $a0, $a1 3 | 0xa4,0x00,0x3c,0xdb = maddu $a0, $a1 4 | 0xa4,0x00,0x3c,0xeb = msub $a0, $a1 5 | 0xa4,0x00,0x3c,0xfb = msubu $a0, $a1 6 | -------------------------------------------------------------------------------- /suite/test_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # dump test output to /tmp/ for diffing 4 | # this is useful to detect if a change modifies any disasm output 5 | 6 | # syntax: test_all.sh 7 | 8 | ./test_archs.py > /tmp/$1_arch 9 | ./test_c.sh $1_c 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-neg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x1d,0xbb,0xe0,0x7e = neg d29, d24 3 | 0xd3,0x79,0x20,0x7e = sqneg b19, b14 4 | 0xf5,0x79,0x60,0x7e = sqneg h21, h15 5 | 0x94,0x79,0xa0,0x7e = sqneg s20, s12 6 | 0x92,0x79,0xe0,0x7e = sqneg d18, d12 7 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-jump-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x00,0xd4,0x98,0x02 = j 1328 3 | 0x00,0xf4,0x98,0x02 = jal 1328 4 | // 0xe6,0x03,0x3c,0x0f = jalr $a2 5 | 0x07,0x00,0x3c,0x0f = jr $a3 6 | 0x07,0x00,0x3c,0x0f = jr $a3 7 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-unaligned.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x85,0x60,0x10,0x00 = lwl $a0, 16($a1) 3 | 0x85,0x60,0x10,0x10 = lwr $a0, 16($a1) 4 | 0x85,0x60,0x10,0x80 = swl $a0, 16($a1) 5 | 0x85,0x60,0x10,0x90 = swr $a0, 16($a1) 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_lsa.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x01,0x2a,0x40,0x05 = lsa $t0, $t1, $t2, 1 3 | 0x01,0x2a,0x40,0x45 = lsa $t0, $t1, $t2, 2 4 | 0x01,0x2a,0x40,0x85 = lsa $t0, $t1, $t2, 3 5 | 0x01,0x2a,0x40,0xc5 = lsa $t0, $t1, $t2, 4 6 | -------------------------------------------------------------------------------- /contrib/cs_driver/README: -------------------------------------------------------------------------------- 1 | This directory contains a sample project for using Capstone from a Windows 2 | driver. Open cs_driver.sln with Visual Studio 2013 or newer and see cs_driver.c 3 | for details. 4 | 5 | For prerequisites to compile Capstone for drivers, see COMPILE_MSVC.TXT. 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-movcond-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xe6,0x00,0x58,0x48 = movz $t1, $a2, $a3 3 | 0xe6,0x00,0x18,0x48 = movn $t1, $a2, $a3 4 | 0x26,0x55,0x7b,0x09 = movt $t1, $a2, $fcc0 5 | 0x26,0x55,0x7b,0x01 = movf $t1, $a2, $fcc0 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-multiply-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0xa4,0xcb,0x3c = madd $a0, $a1 3 | 0x00,0xa4,0xdb,0x3c = maddu $a0, $a1 4 | 0x00,0xa4,0xeb,0x3c = msub $a0, $a1 5 | 0x00,0xa4,0xfb,0x3c = msubu $a0, $a1 6 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_elm_insve.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0] 3 | 0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0] 4 | 0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0] 5 | 0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0] 6 | -------------------------------------------------------------------------------- /suite/regress/Makefile: -------------------------------------------------------------------------------- 1 | LIBNAME = capstone 2 | 3 | invalid_read_in_print_operand: invalid_read_in_print_operand.o 4 | ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ 5 | 6 | %.o: %.c 7 | ${CC} -c -I../../include $< -o $@ 8 | 9 | clean: 10 | rm -rf *.o invalid_read_in_print_operand 11 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x60,0x85,0x00,0x10 = lwl $a0, 16($a1) 3 | 0x60,0x85,0x10,0x10 = lwr $a0, 16($a1) 4 | 0x60,0x85,0x80,0x10 = swl $a0, 16($a1) 5 | 0x60,0x85,0x90,0x10 = swr $a0, 16($a1) 6 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm-aliases.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x03,0x10,0x82,0xe0 = add r1, r2, r3 3 | 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 4 | 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 5 | 0x03,0x10,0x82,0xe1 = orr r1, r2, r3 6 | 0x03,0x10,0x02,0xe0 = and r1, r2, r3 7 | 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 8 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-movcond-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0xe6,0x48,0x58 = movz $t1, $a2, $a3 3 | 0x00,0xe6,0x48,0x18 = movn $t1, $a2, $a3 4 | 0x55,0x26,0x09,0x7b = movt $t1, $a2, $fcc0 5 | 0x55,0x26,0x01,0x7b = movf $t1, $a2, $fcc0 6 | -------------------------------------------------------------------------------- /suite/MC/README: -------------------------------------------------------------------------------- 1 | Input files for testing Capstone engine. 2 | 3 | Format of input files: 4 | 5 | # ARCH, MODE, OPTION 6 | hexcode = assembly 7 | 8 | Format of issue file: 9 | # ARCH, MODE, OPTION 10 | hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count -------------------------------------------------------------------------------- /suite/arm/Makefile: -------------------------------------------------------------------------------- 1 | # Sample Makefile for Capstone Disassembly Engine 2 | 3 | LIBNAME = capstone 4 | 5 | test_arm_regression: test_arm_regression.o 6 | ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ 7 | 8 | %.o: %.c 9 | ${CC} -c -I../../include $< -o $@ 10 | 11 | clean: 12 | rm -rf *.o test_arm_regression 13 | -------------------------------------------------------------------------------- /suite/cstest/Makefile: -------------------------------------------------------------------------------- 1 | SOURCE=src 2 | INCLUDE=include 3 | BUILD=build 4 | LIBRARY= -lcmocka -lcapstone 5 | 6 | all: 7 | rm -rf $(BUILD) 8 | mkdir $(BUILD) 9 | $(CC) $(SOURCE)/*.c -I$(INCLUDE) -o $(BUILD)/cstest $(LIBRARY) 10 | cstest: 11 | $(BUILD)/cstest -d ../MC 12 | clean: 13 | rm -rf $(BUILD) 14 | -------------------------------------------------------------------------------- /suite/benchmark/Makefile: -------------------------------------------------------------------------------- 1 | # Sample Makefile for Capstone Disassembly Engine 2 | 3 | LIBNAME = capstone 4 | 5 | test_iter_benchmark: test_iter_benchmark.o 6 | ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ 7 | 8 | %.o: %.c 9 | ${CC} -c -I../../include $< -o $@ 10 | 11 | clean: 12 | rm -rf *.o test_iter_benchmark 13 | -------------------------------------------------------------------------------- /arch/EVM/EVMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #include 5 | 6 | void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 7 | const char *EVM_insn_name(csh handle, unsigned int id); 8 | const char *EVM_group_name(csh handle, unsigned int id); 9 | -------------------------------------------------------------------------------- /pkgconfig.mk: -------------------------------------------------------------------------------- 1 | # Package version of Capstone for Makefile. 2 | # To be used to generate capstone.pc for pkg-config 3 | 4 | # version major & minor 5 | PKG_MAJOR = 5 6 | PKG_MINOR = 0 7 | 8 | # version bugfix level. Example: PKG_EXTRA = 1 9 | PKG_EXTRA = 0 10 | 11 | # version tag. Examples: rc1, b2, post1 12 | PKG_TAG = 13 | -------------------------------------------------------------------------------- /suite/MC/ARM/crc32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x42,0x00,0x01,0xe1 = crc32b r0, r1, r2 3 | 0x42,0x00,0x21,0xe1 = crc32h r0, r1, r2 4 | 0x42,0x00,0x41,0xe1 = crc32w r0, r1, r2 5 | 0x42,0x02,0x01,0xe1 = crc32cb r0, r1, r2 6 | 0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2 7 | 0x42,0x02,0x41,0xe1 = crc32cw r0, r1, r2 8 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparcv8-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x81,0xa8,0x0a,0x24 = fcmps %f0, %f4 3 | 0x81,0xa8,0x0a,0x44 = fcmpd %f0, %f4 4 | 0x81,0xa8,0x0a,0x64 = fcmpq %f0, %f4 5 | 0x81,0xa8,0x0a,0xa4 = fcmpes %f0, %f4 6 | 0x81,0xa8,0x0a,0xc4 = fcmped %f0, %f4 7 | 0x81,0xa8,0x0a,0xe4 = fcmpeq %f0, %f4 8 | -------------------------------------------------------------------------------- /suite/cstest/build_cstest.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd cmocka && mkdir build && cd build 4 | if [ "$(uname)" = Darwin ]; then 5 | cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install 6 | else # Linux 7 | cmake -DCMAKE_INSTALL_PREFIX=/usr .. && make -j2 && sudo make install 8 | fi 9 | cd ../.. && make 10 | -------------------------------------------------------------------------------- /suite/MC/ARM/crc32-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xc1,0xfa,0x82,0xf0 = crc32b r0, r1, r2 3 | 0xc1,0xfa,0x92,0xf0 = crc32h r0, r1, r2 4 | 0xc1,0xfa,0xa2,0xf0 = crc32w r0, r1, r2 5 | 0xd1,0xfa,0x82,0xf0 = crc32cb r0, r1, r2 6 | 0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2 7 | 0xd1,0xfa,0xa2,0xf0 = crc32cw r0, r1, r2 8 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-atomic-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x81,0x43,0xe0,0x0f = membar 15 3 | 0x81,0x43,0xc0,0x00 = stbar 4 | 0xd4,0x7e,0x00,0x16 = swap [%i0+%l6], %o2 5 | 0xd4,0x7e,0x20,0x20 = swap [%i0+32], %o2 6 | 0xd5,0xe6,0x10,0x16 = cas [%i0], %l6, %o2 7 | 0xd5,0xf6,0x10,0x16 = casx [%i0], %l6, %o2 8 | -------------------------------------------------------------------------------- /.appveyor.yml: -------------------------------------------------------------------------------- 1 | version: 4.0-{build} 2 | 3 | os: 4 | - Visual Studio 2015 5 | 6 | before_build: 7 | - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 8 | 9 | build_script: 10 | - mkdir build 11 | - cd build 12 | - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. 13 | - nmake 14 | 15 | -------------------------------------------------------------------------------- /arch/ARM/ARMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_ARM_MODULE_H 5 | #define CS_ARM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err ARM_global_init(cs_struct *ud); 10 | cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/EVM/EVMModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_EVM_MODULE_H 5 | #define CS_EVM_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err EVM_global_init(cs_struct *ud); 10 | cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/X86/X86Module.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_X86_MODULE_H 5 | #define CS_X86_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err X86_global_init(cs_struct *ud); 10 | cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-abs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x1d,0xbb,0xe0,0x5e = abs d29, d24 3 | 0x1d,0xd7,0xb4,0x7e = fabd s29, s24, s20 4 | 0x1d,0xd7,0xf4,0x7e = fabd d29, d24, d20 5 | 0xd3,0x79,0x20,0x5e = sqabs b19, b14 6 | 0xf5,0x79,0x60,0x5e = sqabs h21, h15 7 | 0x94,0x79,0xa0,0x5e = sqabs s20, s12 8 | 0x92,0x79,0xe0,0x5e = sqabs d18, d12 9 | -------------------------------------------------------------------------------- /arch/M68K/M68KModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_M68K_MODULE_H 5 | #define CS_M68K_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err M68K_global_init(cs_struct *ud); 10 | cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/Mips/MipsModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_MIPS_MODULE_H 5 | #define CS_MIPS_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err Mips_global_init(cs_struct *ud); 10 | cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /MCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_MCDISASSEMBLER_H 5 | #define CS_MCDISASSEMBLER_H 6 | 7 | typedef enum DecodeStatus { 8 | MCDisassembler_Fail = 0, 9 | MCDisassembler_SoftFail = 1, 10 | MCDisassembler_Success = 3, 11 | } DecodeStatus; 12 | 13 | #endif 14 | 15 | -------------------------------------------------------------------------------- /arch/M680X/M680XModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_M680X_MODULE_H 5 | #define CS_M680X_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err M680X_global_init(cs_struct *ud); 10 | cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/PowerPC/PPCModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_POWERPC_MODULE_H 5 | #define CS_POWERPC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err PPC_global_init(cs_struct *ud); 10 | cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/Sparc/SparcModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_SPARC_MODULE_H 5 | #define CS_SPARC_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err Sparc_global_init(cs_struct *ud); 10 | cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/XCore/XCoreModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_XCORE_MODULE_H 5 | #define CS_XCORE_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err XCore_global_init(cs_struct *ud); 10 | cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/EVM/EVMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_EVMDISASSEMBLER_H 5 | #define CS_EVMDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/AArch64/AArch64Module.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_AARCH64_MODULE_H 5 | #define CS_AARCH64_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err AArch64_global_init(cs_struct *ud); 10 | cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/MOS65XX/MOS65XXModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Sebastian Macke , 2018 */ 3 | 4 | #ifndef CS_MOS65XX_MODULE_H 5 | #define CS_MOS65XX_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err MOS65XX_global_init(cs_struct *ud); 10 | cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /arch/SystemZ/SystemZModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_SYSTEMZ_MODULE_H 5 | #define CS_SYSTEMZ_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err SystemZ_global_init(cs_struct *ud); 10 | cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb-hints.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x00,0xbf = nop 3 | 0x10,0xbf = yield 4 | 0x20,0xbf = wfe 5 | 0x30,0xbf = wfi 6 | 0x40,0xbf = sev 7 | 0xbf,0xf3,0x5f,0x8f = dmb sy 8 | 0xbf,0xf3,0x5f,0x8f = dmb sy 9 | 0xbf,0xf3,0x4f,0x8f = dsb sy 10 | 0xbf,0xf3,0x4f,0x8f = dsb sy 11 | 0xbf,0xf3,0x6f,0x8f = isb sy 12 | 0xbf,0xf3,0x6f,0x8f = isb sy 13 | -------------------------------------------------------------------------------- /suite/disasm_mc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # This script test all architectures by default. 4 | 5 | find MC/ -name *.cs | ./disasm_mc.py 6 | 7 | # To test just one architecture, specify the corresponsing dir: 8 | # $ find MC/X86 -name *.cs | ./disasm_mc.py 9 | 10 | # To test just one input file, run disasm_mc.py with that file: 11 | # $ ./disasm_mc.py MC/X86/x86-32-fma3.s.cs 12 | -------------------------------------------------------------------------------- /include/windowsce/intrin.h: -------------------------------------------------------------------------------- 1 | 2 | #if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN) 3 | #define _STDINT 4 | 5 | #ifdef _M_ARM 6 | #include 7 | #if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) 8 | #include 9 | #endif 10 | #endif // _M_ARM 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-frsqrt-frecp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xe0,0xff,0xb0,0x0e = frsqrts v0.2s, v31.2s, v16.2s 3 | 0xe4,0xfc,0xaf,0x4e = frsqrts v4.4s, v7.4s, v15.4s 4 | 0x5d,0xfc,0xe5,0x4e = frsqrts v29.2d, v2.2d, v5.2d 5 | 0xbf,0xff,0x3c,0x4e = frecps v31.4s, v29.4s, v28.4s 6 | 0x03,0xfd,0x2c,0x0e = frecps v3.2s, v8.2s, v12.2s 7 | 0xf1,0xfd,0x6d,0x4e = frecps v17.2d, v15.2d, v13.2d 8 | -------------------------------------------------------------------------------- /arch/TMS320C64x/TMS320C64xModule.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Travis Finkenauer , 2018 */ 3 | 4 | #ifndef CS_TMS320C64X_MODULE_H 5 | #define CS_TMS320C64X_MODULE_H 6 | 7 | #include "../../utils.h" 8 | 9 | cs_err TMS320C64x_global_init(cs_struct *ud); 10 | cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value); 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /suite/MC/ARM/basic-arm-instructions-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x59,0xf0,0x7f,0xf5 = dmb ishld 3 | 0x51,0xf0,0x7f,0xf5 = dmb oshld 4 | 0x55,0xf0,0x7f,0xf5 = dmb nshld 5 | 0x5d,0xf0,0x7f,0xf5 = dmb ld 6 | 0x49,0xf0,0x7f,0xf5 = dsb ishld 7 | 0x41,0xf0,0x7f,0xf5 = dsb oshld 8 | 0x45,0xf0,0x7f,0xf5 = dsb nshld 9 | 0x4d,0xf0,0x7f,0xf5 = dsb ld 10 | 0x05,0xf0,0x20,0xe3 = sevl 11 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_vec.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27 3 | 0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7 4 | 0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9 5 | 0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14 6 | 0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0 7 | 0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30 8 | 0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15 9 | -------------------------------------------------------------------------------- /arch/EVM/EVMInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifndef CS_EVMINSTPRINTER_H 5 | #define CS_EVMINSTPRINTER_H 6 | 7 | 8 | #include "capstone/capstone.h" 9 | #include "../../MCInst.h" 10 | #include "../../SStream.h" 11 | #include "../../cs_priv.h" 12 | 13 | struct SStream; 14 | 15 | void EVM_printInst(MCInst *MI, struct SStream *O, void *Info); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /bindings/vb6/Project1.vbw: -------------------------------------------------------------------------------- 1 | Form1 = 110, 110, 1233, 906, , 88, 88, 1116, 749, C 2 | mCapStone = 22, 22, 1050, 683, 3 | mx86 = 88, 88, 1040, 757, 4 | mMisc = 66, 66, 1094, 727, 5 | CInstruction = 0, 0, 0, 0, C 6 | CInstDetails = 132, 132, 1084, 801, C 7 | CDisassembler = 44, 44, 1229, 809, 8 | CX86Inst = 154, 154, 1106, 823, C 9 | CX86Operand = 176, 176, 1128, 845, C 10 | CX86OpMem = 198, 198, 1150, 867, C 11 | -------------------------------------------------------------------------------- /capstone.pc.in: -------------------------------------------------------------------------------- 1 | prefix=@CMAKE_INSTALL_PREFIX@ 2 | exec_prefix=${prefix} 3 | libdir=${prefix}/@CMAKE_INSTALL_LIBDIR@ 4 | includedir=${prefix}/include/capstone 5 | 6 | Name: capstone 7 | Description: Capstone disassembly engine 8 | Version: @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@ 9 | URL: https://www.capstone-engine.org 10 | archive=${libdir}/libcapstone.a 11 | Libs: -L${libdir} -lcapstone 12 | Cflags: -I${includedir} 13 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm_addrmode3.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 3 | 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 4 | 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 5 | 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 6 | 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 7 | 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 8 | 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 9 | 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4 10 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-saturating-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x4c,0x22,0x5e = sqshl b0, b1, b2 3 | 0x6a,0x4d,0x6c,0x5e = sqshl h10, h11, h12 4 | 0xb4,0x4e,0xa2,0x5e = sqshl s20, s21, s2 5 | 0xf1,0x4f,0xe8,0x5e = sqshl d17, d31, d8 6 | 0x20,0x4c,0x22,0x7e = uqshl b0, b1, b2 7 | 0x6a,0x4d,0x6c,0x7e = uqshl h10, h11, h12 8 | 0xb4,0x4e,0xa2,0x7e = uqshl s20, s21, s2 9 | 0xf1,0x4f,0xe8,0x7e = uqshl d17, d31, d8 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa4,0x1c,0x08,0x00 = lb $a1, 8($a0) 3 | 0xc4,0x14,0x08,0x00 = lbu $a2, 8($a0) 4 | 0x44,0x3c,0x08,0x00 = lh $v0, 8($a0) 5 | 0x82,0x34,0x08,0x00 = lhu $a0, 8($v0) 6 | 0xc5,0xfc,0x04,0x00 = lw $a2, 4($a1) 7 | 0xa4,0x18,0x08,0x00 = sb $a1, 8($a0) 8 | 0x44,0x38,0x08,0x00 = sh $v0, 8($a0) 9 | 0xa6,0xf8,0x04,0x00 = sw $a1, 4($a2) 10 | -------------------------------------------------------------------------------- /packages/freebsd/ports/devel/capstone/pkg-plist: -------------------------------------------------------------------------------- 1 | include/capstone/arm.h 2 | include/capstone/arm64.h 3 | include/capstone/capstone.h 4 | include/capstone/mips.h 5 | include/capstone/ppc.h 6 | include/capstone/sparc.h 7 | include/capstone/systemz.h 8 | include/capstone/x86.h 9 | include/capstone/xcore.h 10 | include/capstone/platform.h 11 | lib/libcapstone.a 12 | lib/libcapstone.so 13 | libdata/pkgconfig/capstone.pc 14 | @dirrmtry include/capstone 15 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-extract-narrow.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xd3,0x29,0x21,0x7e = sqxtun b19, h14 3 | 0xf5,0x29,0x61,0x7e = sqxtun h21, s15 4 | 0x94,0x29,0xa1,0x7e = sqxtun s20, d12 5 | 0x52,0x4a,0x21,0x5e = sqxtn b18, h18 6 | 0x34,0x4a,0x61,0x5e = sqxtn h20, s17 7 | 0xd3,0x49,0xa1,0x5e = sqxtn s19, d14 8 | 0x52,0x4a,0x21,0x7e = uqxtn b18, h18 9 | 0x34,0x4a,0x61,0x7e = uqxtn h20, s17 10 | 0xd3,0x49,0xa1,0x7e = uqxtn s19, d14 11 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-shift-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x83,0x00,0x00,0x38 = sll $a0, $v1, 7 3 | 0x65,0x00,0x10,0x10 = sllv $v0, $v1, $a1 4 | 0x83,0x00,0x80,0x38 = sra $a0, $v1, 7 5 | 0x65,0x00,0x90,0x10 = srav $v0, $v1, $a1 6 | 0x83,0x00,0x40,0x38 = srl $a0, $v1, 7 7 | 0x65,0x00,0x50,0x10 = srlv $v0, $v1, $a1 8 | 0x26,0x01,0xc0,0x38 = rotr $t1, $a2, 7 9 | 0xc7,0x00,0xd0,0x48 = rotrv $t1, $a2, $a3 10 | -------------------------------------------------------------------------------- /bindings/python/build_wheel.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -e -x 3 | 4 | cd bindings/python 5 | sudo rm /usr/bin/python && sudo ln -s /opt/python/cp27-cp27m/bin/python /usr/bin/python; python -V 6 | 7 | # Compile wheels 8 | if [ -f /opt/python/cp36-cp36m/bin/python ];then 9 | /opt/python/cp36-cp36m/bin/python setup.py bdist_wheel 10 | else 11 | python3 setup.py bdist_wheel 12 | fi 13 | cd dist 14 | auditwheel repair *.whl 15 | mv -f wheelhouse/*.whl . 16 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x5c,0x22,0x5e = sqrshl b0, b1, b2 3 | 0x6a,0x5d,0x6c,0x5e = sqrshl h10, h11, h12 4 | 0xb4,0x5e,0xa2,0x5e = sqrshl s20, s21, s2 5 | 0xf1,0x5f,0xe8,0x5e = sqrshl d17, d31, d8 6 | 0x20,0x5c,0x22,0x7e = uqrshl b0, b1, b2 7 | 0x6a,0x5d,0x6c,0x7e = uqrshl h10, h11, h12 8 | 0xb4,0x5e,0xa2,0x7e = uqrshl s20, s21, s2 9 | 0xf1,0x5f,0xe8,0x7e = uqrshl d17, d31, d8 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x1c,0xa4,0x00,0x08 = lb $a1, 8($a0) 3 | 0x14,0xc4,0x00,0x08 = lbu $a2, 8($a0) 4 | 0x3c,0x44,0x00,0x08 = lh $v0, 8($a0) 5 | 0x34,0x82,0x00,0x08 = lhu $a0, 8($v0) 6 | 0xfc,0xc5,0x00,0x04 = lw $a2, 4($a1) 7 | 0x18,0xa4,0x00,0x08 = sb $a1, 8($a0) 8 | 0x38,0x44,0x00,0x08 = sh $v0, 8($a0) 9 | 0xf8,0xa6,0x00,0x04 = sw $a1, 4($a2) 10 | -------------------------------------------------------------------------------- /suite/regress/invalid_read_in_print_operand.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #define BINARY "\x3b\x30\x62\x93\x5d\x61\x03\xe8" 4 | 5 | int main(int argc, char **argv, char **envp) { 6 | csh handle; 7 | if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle)) { 8 | printf("cs_open(…) failed\n"); 9 | return 1; 10 | } 11 | cs_insn *insn; 12 | cs_disasm(handle, (uint8_t *)BINARY, sizeof(BINARY) - 1, 0x1000, 0, &insn); 13 | return 0; 14 | } 15 | -------------------------------------------------------------------------------- /arch/PowerPC/PPCInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_PPCINSTPRINTER_H 5 | #define CS_PPCINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void PPC_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /bindings/python/capstone/evm.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .evm_const import * 6 | 7 | # define the API 8 | class CsEvm(ctypes.Structure): 9 | _fields_ = ( 10 | ('pop', ctypes.c_byte), 11 | ('push', ctypes.c_byte), 12 | ('fee', ctypes.c_uint), 13 | ) 14 | 15 | def get_arch_info(a): 16 | return (a.pop, a.push, a.fee) 17 | 18 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-ctrl-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x9f,0xc0,0x40,0x1a = call %g1+%i2 3 | 0x9f,0xc2,0x60,0x08 = call %o1+8 4 | 0x9f,0xc0,0x60,0x00 = call %g1 5 | 0x81,0xc0,0x40,0x1a = jmp %g1+%i2 6 | 0x81,0xc2,0x60,0x08 = jmp %o1+8 7 | 0x81,0xc0,0x60,0x00 = jmp %g1 8 | 0x85,0xc0,0x40,0x1a = jmpl %g1+%i2, %g2 9 | 0x85,0xc2,0x60,0x08 = jmpl %o1+8, %g2 10 | 0x85,0xc0,0x60,0x00 = jmpl %g1, %g2 11 | 0x81,0xcf,0xe0,0x08 = rett %i7+8 12 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-shift-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0x83,0x38,0x00 = sll $a0, $v1, 7 3 | 0x00,0x65,0x10,0x10 = sllv $v0, $v1, $a1 4 | 0x00,0x83,0x38,0x80 = sra $a0, $v1, 7 5 | 0x00,0x65,0x10,0x90 = srav $v0, $v1, $a1 6 | 0x00,0x83,0x38,0x40 = srl $a0, $v1, 7 7 | 0x00,0x65,0x10,0x50 = srlv $v0, $v1, $a1 8 | 0x01,0x26,0x38,0xc0 = rotr $t1, $a2, 7 9 | 0x00,0xc7,0x48,0xd0 = rotrv $t1, $a2, $a3 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips_directives.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x10,0x00,0x01,0x4d = b 1336 3 | 0x08,0x00,0x01,0x4c = j 1328 4 | 0x0c,0x00,0x01,0x4c = jal 1328 5 | 0x10,0x00,0x01,0x4d = b 1336 6 | 0x00,0x00,0x00,0x00 = nop 7 | 0x08,0x00,0x01,0x4c = j 1328 8 | 0x00,0x00,0x00,0x00 = nop 9 | 0x0c,0x00,0x01,0x4c = jal 1328 10 | 0x00,0x00,0x00,0x00 = nop 11 | 0x46,0x00,0x39,0x85 = abs.s $f6, $f7 12 | 0x01,0xef,0x18,0x24 = and $v1, $t7, $t7 13 | -------------------------------------------------------------------------------- /arch/SystemZ/SystemZInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SYSZINSTPRINTER_H 5 | #define CS_SYSZINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void SystemZ_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /TODO: -------------------------------------------------------------------------------- 1 | Issues to be solved in next versions 2 | 3 | 4 | [Core] 5 | 6 | - X86 can already handle all the malware tricks we are aware of. If you find 7 | any such instruction sequence that Capstone disassembles wrongly or fails 8 | completely, please report. Fixing this issue is always the top priority of 9 | our project. 10 | 11 | - More optimization for better performance. 12 | 13 | 14 | [Bindings] 15 | 16 | - OCaml binding is working, but still needs to support the core API better. 17 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-recip.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x15,0xfe,0x2d,0x5e = frecps s21, s16, s13 3 | 0xd6,0xff,0x75,0x5e = frecps d22, d30, d21 4 | 0xb5,0xfc,0xac,0x5e = frsqrts s21, s5, s12 5 | 0xc8,0xfe,0xf2,0x5e = frsqrts d8, d22, d18 6 | 0xd3,0xd9,0xa1,0x5e = frecpe s19, s14 7 | 0xad,0xd9,0xe1,0x5e = frecpe d13, d13 8 | 0x52,0xf9,0xa1,0x5e = frecpx s18, s10 9 | 0x70,0xfa,0xe1,0x5e = frecpx d16, d19 10 | 0xb6,0xd9,0xa1,0x7e = frsqrte s22, s13 11 | 0x95,0xd9,0xe1,0x7e = frsqrte d21, d12 12 | -------------------------------------------------------------------------------- /suite/MC/ARM/vpush-vpop.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} 3 | 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} 4 | 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} 5 | 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} 6 | 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} 7 | 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} 8 | 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} 9 | 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} 10 | -------------------------------------------------------------------------------- /arch/TMS320C64x/TMS320C64xInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifndef CS_TMS320C64XINSTPRINTER_H 5 | #define CS_TMS320C64XINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/vpush-vpop-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} 3 | 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} 4 | 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} 5 | 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} 6 | 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} 7 | 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} 8 | 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} 9 | 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-branch-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x00,0x94,0x9a,0x02 = b 1332 3 | 0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 1332 4 | 0x46,0x40,0x9a,0x02 = bgez $a2, 1332 5 | 0x66,0x40,0x9a,0x02 = bgezal $a2, 1332 6 | 0x26,0x40,0x9a,0x02 = bltzal $a2, 1332 7 | 0xc6,0x40,0x9a,0x02 = bgtz $a2, 1332 8 | 0x86,0x40,0x9a,0x02 = blez $a2, 1332 9 | 0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 1332 10 | // 0x60,0x40,0x9a,0x02 = bal 1332 11 | 0x06,0x40,0x9a,0x02 = bltz $a2, 1332 12 | -------------------------------------------------------------------------------- /arch/Mips/MipsDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_MIPSDISASSEMBLER_H 5 | #define CS_MIPSDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCInst.h" 9 | #include "../../MCRegisterInfo.h" 10 | 11 | void Mips_init(MCRegisterInfo *MRI); 12 | 13 | bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /arch/PowerPC/PPCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_PPCDISASSEMBLER_H 5 | #define CS_PPCDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void PPC_init(MCRegisterInfo *MRI); 12 | 13 | bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-table-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16 3 | 0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18 4 | 0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20 5 | 0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20 6 | 0xe1,0x28,0xf0,0xf3 = vtbx.8 d18, {d16}, d17 7 | 0xe2,0x39,0xf0,0xf3 = vtbx.8 d19, {d16, d17}, d18 8 | 0xe5,0x4a,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18}, d21 9 | 0xe5,0x4b,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18, d19}, d21 10 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_cbranch.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | // 0x47,0x80,0x00,0x01 = bnz.b $w0, 4 3 | // 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16 4 | // 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128 5 | // 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128 6 | // 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4 7 | // 0x47,0x00,0x00,0x20 = bz.b $w0, 128 8 | // 0x47,0x21,0x00,0x40 = bz.h $w1, 256 9 | // 0x47,0x42,0x00,0x80 = bz.w $w2, 512 10 | // 0x47,0x63,0xff,0x00 = bz.d $w3, -1024 11 | // 0x45,0x60,0x00,0x01 = bz.v $w0, 4 12 | -------------------------------------------------------------------------------- /arch/Sparc/SparcInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SPARCINSTPRINTER_H 5 | #define CS_SPARCINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void Sparc_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | void Sparc_addReg(MCInst *MI, int reg); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-table-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xff,0xa0,0x08 = vtbl.8 d16, {d17}, d16 3 | 0xf0,0xff,0xa2,0x09 = vtbl.8 d16, {d16, d17}, d18 4 | 0xf0,0xff,0xa4,0x0a = vtbl.8 d16, {d16, d17, d18}, d20 5 | 0xf0,0xff,0xa4,0x0b = vtbl.8 d16, {d16, d17, d18, d19}, d20 6 | 0xf0,0xff,0xe1,0x28 = vtbx.8 d18, {d16}, d17 7 | 0xf0,0xff,0xe2,0x39 = vtbx.8 d19, {d16, d17}, d18 8 | 0xf0,0xff,0xe5,0x4a = vtbx.8 d20, {d16, d17, d18}, d21 9 | 0xf0,0xff,0xe5,0x4b = vtbx.8 d20, {d16, d17, d18, d19}, d21 10 | -------------------------------------------------------------------------------- /arch/Sparc/SparcDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SPARCDISASSEMBLER_H 5 | #define CS_SPARCDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void Sparc_init(MCRegisterInfo *MRI); 12 | 13 | bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /arch/XCore/XCoreDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_XCOREDISASSEMBLER_H 5 | #define CS_XCOREDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void XCore_init(MCRegisterInfo *MRI); 12 | 13 | bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-branch-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x94,0x00,0x02,0x9a = b 1332 3 | 0x94,0xc9,0x02,0x9a = beq $t1, $a2, 1332 4 | 0x40,0x46,0x02,0x9a = bgez $a2, 1332 5 | 0x40,0x66,0x02,0x9a = bgezal $a2, 1332 6 | 0x40,0x26,0x02,0x9a = bltzal $a2, 1332 7 | 0x40,0xc6,0x02,0x9a = bgtz $a2, 1332 8 | 0x40,0x86,0x02,0x9a = blez $a2, 1332 9 | 0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 1332 10 | // 0x40,0x60,0x02,0x9a = bal 1332 11 | 0x40,0x06,0x02,0x9a = bltz $a2, 1332 12 | -------------------------------------------------------------------------------- /arch/SystemZ/SystemZDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SYSZDISASSEMBLER_H 5 | #define CS_SYSZDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void SystemZ_init(MCRegisterInfo *MRI); 12 | 13 | bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /bindings/ocaml/mips.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open Mips_const 5 | 6 | (* architecture specific info of instruction *) 7 | type mips_op_mem = { 8 | base: int; 9 | disp: int 10 | } 11 | 12 | type mips_op_value = 13 | | MIPS_OP_INVALID of int 14 | | MIPS_OP_REG of int 15 | | MIPS_OP_IMM of int 16 | | MIPS_OP_MEM of mips_op_mem 17 | 18 | type mips_op = { 19 | value: mips_op_value; 20 | } 21 | 22 | type cs_mips = { 23 | operands: mips_op array; 24 | } 25 | -------------------------------------------------------------------------------- /arch/AArch64/AArch64Disassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_AARCH64_DISASSEMBLER_H 5 | #define CS_AARCH64_DISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | void AArch64_init(MCRegisterInfo *MRI); 12 | 13 | bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, 14 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /bindings/ocaml/xcore.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Xcore_const 5 | 6 | type xcore_op_mem = { 7 | base: int; 8 | index: int; 9 | disp: int; 10 | direct: int; 11 | } 12 | 13 | type xcore_op_value = 14 | | XCORE_OP_INVALID of int 15 | | XCORE_OP_REG of int 16 | | XCORE_OP_IMM of int 17 | | XCORE_OP_MEM of xcore_op_mem 18 | 19 | type xcore_op = { 20 | value: xcore_op_value; 21 | } 22 | 23 | type cs_xcore = { 24 | operands: xcore_op array; 25 | } 26 | 27 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x91,0x42 = cmp r1, r2 3 | 0x16,0xbc = pop {r1, r2, r4} 4 | 0xfe,0xde = trap 5 | 0xc8,0x47 = blx r9 6 | 0xd0,0x47 = blx r10 7 | 0x1a,0xba = rev r2, r3 8 | 0x63,0xba = rev16 r3, r4 9 | 0xf5,0xba = revsh r5, r6 10 | 0x5a,0xb2 = sxtb r2, r3 11 | 0x1a,0xb2 = sxth r2, r3 12 | 0x2c,0x42 = tst r4, r5 13 | 0xf3,0xb2 = uxtb r3, r6 14 | 0xb3,0xb2 = uxth r3, r6 15 | 0x8b,0x58 = ldr r3, [r1, r2] 16 | 0x02,0xbe = bkpt #2 17 | 0xc0,0x46 = mov r8, r8 18 | 0x67,0xb6 = cpsie aif 19 | 0x78,0x46 = mov r0, pc 20 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_i8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48 3 | 0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126 4 | 0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88 5 | 0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189 6 | 0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56 7 | 0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135 8 | 0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105 9 | 0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76 10 | 0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93 11 | 0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20 12 | -------------------------------------------------------------------------------- /suite/MC/X86/x86_64-rand-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x66,0x0f,0xc7,0xf0 = rdrandw %ax 3 | 0x0f,0xc7,0xf0 = rdrandl %eax 4 | 0x48,0x0f,0xc7,0xf0 = rdrandq %rax 5 | 0x66,0x41,0x0f,0xc7,0xf3 = rdrandw %r11w 6 | 0x41,0x0f,0xc7,0xf3 = rdrandl %r11d 7 | 0x49,0x0f,0xc7,0xf3 = rdrandq %r11 8 | 0x66,0x0f,0xc7,0xf8 = rdseedw %ax 9 | 0x0f,0xc7,0xf8 = rdseedl %eax 10 | 0x48,0x0f,0xc7,0xf8 = rdseedq %rax 11 | 0x66,0x41,0x0f,0xc7,0xfb = rdseedw %r11w 12 | 0x41,0x0f,0xc7,0xfb = rdseedl %r11d 13 | 0x49,0x0f,0xc7,0xfb = rdseedq %r11 14 | -------------------------------------------------------------------------------- /bindings/ocaml/sparc.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Sparc_const 5 | 6 | type sparc_op_mem = { 7 | base: int; 8 | index: int; 9 | disp: int; 10 | } 11 | 12 | type sparc_op_value = 13 | | SPARC_OP_INVALID of int 14 | | SPARC_OP_REG of int 15 | | SPARC_OP_IMM of int 16 | | SPARC_OP_MEM of sparc_op_mem 17 | 18 | type sparc_op = { 19 | value: sparc_op_value; 20 | } 21 | 22 | type cs_sparc = { 23 | cc: int; 24 | hint: int; 25 | operands: sparc_op array; 26 | } 27 | 28 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-compare.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xb4,0x8e,0xf6,0x7e = cmeq d20, d21, d22 3 | 0xb4,0x9a,0xe0,0x5e = cmeq d20, d21, #0x0 4 | 0xb4,0x3e,0xf6,0x7e = cmhs d20, d21, d22 5 | 0xb4,0x3e,0xf6,0x5e = cmge d20, d21, d22 6 | 0xb4,0x8a,0xe0,0x7e = cmge d20, d21, #0x0 7 | 0xb4,0x36,0xf6,0x7e = cmhi d20, d21, d22 8 | 0xb4,0x36,0xf6,0x5e = cmgt d20, d21, d22 9 | 0xb4,0x8a,0xe0,0x5e = cmgt d20, d21, #0x0 10 | 0xb4,0x9a,0xe0,0x7e = cmle d20, d21, #0x0 11 | 0xb4,0xaa,0xe0,0x5e = cmlt d20, d21, #0x0 12 | 0xb4,0x8e,0xf6,0x5e = cmtst d20, d21, d22 13 | -------------------------------------------------------------------------------- /suite/MC/Mips/nabi-regs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 2 | 0x02,0x04,0x80,0x20 = add $s0, $s0, $a0 3 | 0x02,0x06,0x80,0x20 = add $s0, $s0, $a2 4 | 0x02,0x07,0x80,0x20 = add $s0, $s0, $a3 5 | 0x02,0x08,0x80,0x20 = add $s0, $s0, $t0 6 | 0x02,0x09,0x80,0x20 = add $s0, $s0, $t1 7 | 0x02,0x0a,0x80,0x20 = add $s0, $s0, $t2 8 | 0x02,0x0b,0x80,0x20 = add $s0, $s0, $t3 9 | 0x02,0x0c,0x80,0x20 = add $s0, $s0, $t4 10 | 0x02,0x0d,0x80,0x20 = add $s0, $s0, $t5 11 | 0x02,0x0e,0x80,0x20 = add $s0, $s0, $t6 12 | 0x02,0x0f,0x80,0x20 = add $s0, $s0, $t7 13 | -------------------------------------------------------------------------------- /bindings/ocaml/systemz.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Sysz_const 5 | 6 | type sysz_op_mem = { 7 | base: int; 8 | index: int; 9 | length: int64; 10 | disp: int64; 11 | } 12 | 13 | type sysz_op_value = 14 | | SYSZ_OP_INVALID of int 15 | | SYSZ_OP_REG of int 16 | | SYSZ_OP_ACREG of int 17 | | SYSZ_OP_IMM of int 18 | | SYSZ_OP_MEM of sysz_op_mem 19 | 20 | type sysz_op = { 21 | value: sysz_op_value; 22 | } 23 | 24 | type cs_sysz = { 25 | cc: int; 26 | operands: sysz_op array; 27 | } 28 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-add-pairwise.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0xbc,0x22,0x0e = addp v0.8b, v1.8b, v2.8b 3 | 0x20,0xbc,0x22,0x4e = addp v0.16b, v1.16b, v2.16b 4 | 0x20,0xbc,0x62,0x0e = addp v0.4h, v1.4h, v2.4h 5 | 0x20,0xbc,0x62,0x4e = addp v0.8h, v1.8h, v2.8h 6 | 0x20,0xbc,0xa2,0x0e = addp v0.2s, v1.2s, v2.2s 7 | 0x20,0xbc,0xa2,0x4e = addp v0.4s, v1.4s, v2.4s 8 | 0x20,0xbc,0xe2,0x4e = addp v0.2d, v1.2d, v2.2d 9 | 0x20,0xd4,0x22,0x2e = faddp v0.2s, v1.2s, v2.2s 10 | 0x20,0xd4,0x22,0x6e = faddp v0.4s, v1.4s, v2.4s 11 | 0x20,0xd4,0x62,0x6e = faddp v0.2d, v1.2d, v2.2d 12 | -------------------------------------------------------------------------------- /arch/EVM/EVMInstPrinter.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #include "EVMInstPrinter.h" 5 | #include "EVMMapping.h" 6 | 7 | 8 | void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) 9 | { 10 | SStream_concat(O, EVM_insn_name((csh)MI->csh, MI->Opcode)); 11 | 12 | if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) { 13 | unsigned int i; 14 | 15 | SStream_concat0(O, "\t"); 16 | for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) { 17 | SStream_concat(O, "%02x", MI->evm_data[i]); 18 | } 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /arch/XCore/XCoreInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_XCOREINSTPRINTER_H 5 | #define CS_XCOREINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void XCore_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | // extract details from assembly code @code 16 | void XCore_insn_extract(MCInst *MI, const char *code); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-dup-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x90,0x0b,0xc0,0xee = vdup.8 d16, r0 3 | 0xb0,0x0b,0x80,0xee = vdup.16 d16, r0 4 | 0x90,0x0b,0x80,0xee = vdup.32 d16, r0 5 | 0x90,0x0b,0xe0,0xee = vdup.8 q8, r0 6 | 0xb0,0x0b,0xa0,0xee = vdup.16 q8, r0 7 | 0x90,0x0b,0xa0,0xee = vdup.32 q8, r0 8 | 0x20,0x0c,0xf3,0xf3 = vdup.8 d16, d16[1] 9 | 0x20,0x0c,0xf6,0xf3 = vdup.16 d16, d16[1] 10 | 0x20,0x0c,0xfc,0xf3 = vdup.32 d16, d16[1] 11 | 0x60,0x0c,0xf3,0xf3 = vdup.8 q8, d16[1] 12 | 0x60,0x0c,0xf6,0xf3 = vdup.16 q8, d16[1] 13 | 0x60,0x0c,0xfc,0xf3 = vdup.32 q8, d16[1] 14 | -------------------------------------------------------------------------------- /arch/TMS320C64x/TMS320C64xDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifndef CS_TMS320C64XDISASSEMBLER_H 5 | #define CS_TMS320C64XDISASSEMBLER_H 6 | 7 | #include 8 | 9 | #include "capstone/capstone.h" 10 | #include "../../MCRegisterInfo.h" 11 | #include "../../MCInst.h" 12 | 13 | void TMS320C64x_init(MCRegisterInfo *MRI); 14 | 15 | bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, 16 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 17 | 18 | #endif 19 | 20 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-reverse-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x00,0xf0,0xf3 = vrev64.8 d16, d16 3 | 0x20,0x00,0xf4,0xf3 = vrev64.16 d16, d16 4 | 0x20,0x00,0xf8,0xf3 = vrev64.32 d16, d16 5 | 0x60,0x00,0xf0,0xf3 = vrev64.8 q8, q8 6 | 0x60,0x00,0xf4,0xf3 = vrev64.16 q8, q8 7 | 0x60,0x00,0xf8,0xf3 = vrev64.32 q8, q8 8 | 0xa0,0x00,0xf0,0xf3 = vrev32.8 d16, d16 9 | 0xa0,0x00,0xf4,0xf3 = vrev32.16 d16, d16 10 | 0xe0,0x00,0xf0,0xf3 = vrev32.8 q8, q8 11 | 0xe0,0x00,0xf4,0xf3 = vrev32.16 q8, q8 12 | 0x20,0x01,0xf0,0xf3 = vrev16.8 d16, d16 13 | 0x60,0x01,0xf0,0xf3 = vrev16.8 q8, q8 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-reverse-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf0,0xff,0x20,0x00 = vrev64.8 d16, d16 3 | 0xf4,0xff,0x20,0x00 = vrev64.16 d16, d16 4 | 0xf8,0xff,0x20,0x00 = vrev64.32 d16, d16 5 | 0xf0,0xff,0x60,0x00 = vrev64.8 q8, q8 6 | 0xf4,0xff,0x60,0x00 = vrev64.16 q8, q8 7 | 0xf8,0xff,0x60,0x00 = vrev64.32 q8, q8 8 | 0xf0,0xff,0xa0,0x00 = vrev32.8 d16, d16 9 | 0xf4,0xff,0xa0,0x00 = vrev32.16 d16, d16 10 | 0xf0,0xff,0xe0,0x00 = vrev32.8 q8, q8 11 | 0xf4,0xff,0xe0,0x00 = vrev32.16 q8, q8 12 | 0xf0,0xff,0x20,0x01 = vrev16.8 d16, d16 13 | 0xf0,0xff,0x60,0x01 = vrev16.8 q8, q8 14 | -------------------------------------------------------------------------------- /suite/test_python.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run all the Python tests, and send the output that to a file to be compared later 4 | # This is useful when we want to verify if a commit (wrongly) changes the disassemble result. 5 | 6 | ../bindings/python/test.py > /tmp/$1 7 | ../bindings/python/test_detail.py >> /tmp/$1 8 | ../bindings/python/test_arm.py >> /tmp/$1 9 | ../bindings/python/test_arm64.py >> /tmp/$1 10 | ../bindings/python/test_mips.py >> /tmp/$1 11 | ../bindings/python/test_ppc.py >> /tmp/$1 12 | ../bindings/python/test_sparc.py >> /tmp/$1 13 | ../bindings/python/test_x86.py >> /tmp/$1 14 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-trap-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | // 0x28,0x01,0x3c,0x00 = teq $t0, $t1 3 | // 0x28,0x01,0x3c,0x02 = tge $t0, $t1 4 | // 0x28,0x01,0x3c,0x04 = tgeu $t0, $t1 5 | // 0x28,0x01,0x3c,0x08 = tlt $t0, $t1 6 | // 0x28,0x01,0x3c,0x0a = tltu $t0, $t1 7 | // 0x28,0x01,0x3c,0x0c = tne $t0, $t1 8 | 0xc9,0x41,0x67,0x45 = teqi $t1, 17767 9 | 0x29,0x41,0x67,0x45 = tgei $t1, 17767 10 | 0x69,0x41,0x67,0x45 = tgeiu $t1, 17767 11 | 0x09,0x41,0x67,0x45 = tlti $t1, 17767 12 | 0x49,0x41,0x67,0x45 = tltiu $t1, 17767 13 | 0x89,0x41,0x67,0x45 = tnei $t1, 17767 14 | -------------------------------------------------------------------------------- /MCInstrDesc.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #include "MCInstrDesc.h" 5 | 6 | /// isPredicate - Set if this is one of the operands that made up of 7 | /// the predicate operand that controls an isPredicable() instruction. 8 | bool MCOperandInfo_isPredicate(const MCOperandInfo *m) 9 | { 10 | return m->Flags & (1 << MCOI_Predicate); 11 | } 12 | 13 | /// isOptionalDef - Set if this operand is a optional def. 14 | /// 15 | bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m) 16 | { 17 | return m->Flags & (1 << MCOI_OptionalDef); 18 | } 19 | -------------------------------------------------------------------------------- /contrib/windows_kernel/README: -------------------------------------------------------------------------------- 1 | For Windows kernel programming, the SDK does not offer some functions 2 | needed by Capstone. The missing functions are: 3 | 4 | - Memory allocations: malloc(), calloc(), realloc() & free(). 5 | - Format input variables & write out result to char buffer: vsnprintf() 6 | 7 | This directory contains some code providing above-mentioned functions, so you can 8 | integrate Capstone with your Windows-kernel drivers using C++. 9 | 10 | All the code here is contributed by Peter Hlavaty 11 | See the full example with Capstone integration at https://github.com/zer0mem/libc.git 12 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc64-alu-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xb1,0x28,0x50,0x1a = sllx %g1, %i2, %i0 3 | 0xb1,0x28,0x70,0x3f = sllx %g1, 63, %i0 4 | 0xb1,0x30,0x50,0x1a = srlx %g1, %i2, %i0 5 | 0xb1,0x30,0x70,0x3f = srlx %g1, 63, %i0 6 | 0xb1,0x38,0x50,0x1a = srax %g1, %i2, %i0 7 | 0xb1,0x38,0x70,0x3f = srax %g1, 63, %i0 8 | 0xb0,0x48,0x40,0x1a = mulx %g1, %i2, %i0 9 | 0xb0,0x48,0x60,0x3f = mulx %g1, 63, %i0 10 | 0xb1,0x68,0x40,0x1a = sdivx %g1, %i2, %i0 11 | 0xb1,0x68,0x60,0x3f = sdivx %g1, 63, %i0 12 | 0xb0,0x68,0x40,0x1a = udivx %g1, %i2, %i0 13 | 0xb0,0x68,0x60,0x3f = udivx %g1, 63, %i0 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/vfp4.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17 3 | 0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0 4 | 0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17 5 | 0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0 6 | 0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17 7 | 0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0 8 | 0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17 9 | 0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0 10 | 0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17 11 | 0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0 12 | 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17 13 | 0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0 14 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-trap-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | // 0x01,0x28,0x00,0x3c = teq $t0, $t1 3 | // 0x01,0x28,0x02,0x3c = tge $t0, $t1 4 | // 0x01,0x28,0x04,0x3c = tgeu $t0, $t1 5 | // 0x01,0x28,0x08,0x3c = tlt $t0, $t1 6 | // 0x01,0x28,0x0a,0x3c = tltu $t0, $t1 7 | // 0x01,0x28,0x0c,0x3c = tne $t0, $t1 8 | 0x41,0xc9,0x45,0x67 = teqi $t1, 17767 9 | 0x41,0x29,0x45,0x67 = tgei $t1, 17767 10 | 0x41,0x69,0x45,0x67 = tgeiu $t1, 17767 11 | 0x41,0x09,0x45,0x67 = tlti $t1, 17767 12 | 0x41,0x49,0x45,0x67 = tltiu $t1, 17767 13 | 0x41,0x89,0x45,0x67 = tnei $t1, 17767 14 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x6a,0xb5,0x6c,0x5e = sqdmulh h10, h11, h12 3 | 0xb4,0xb6,0xa2,0x5e = sqdmulh s20, s21, s2 4 | 0x6a,0xb5,0x6c,0x7e = sqrdmulh h10, h11, h12 5 | 0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2 6 | 0xd4,0xde,0x2f,0x5e = fmulx s20, s22, s15 7 | 0x77,0xdd,0x61,0x5e = fmulx d23, d11, d1 8 | 0x71,0x93,0x6c,0x5e = sqdmlal s17, h27, h12 9 | 0x13,0x93,0xac,0x5e = sqdmlal d19, s24, s12 10 | 0x8e,0xb1,0x79,0x5e = sqdmlsl s14, h12, h25 11 | 0xec,0xb2,0xad,0x5e = sqdmlsl d12, s23, s13 12 | 0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12 13 | 0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-reciprocal-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x04,0xfb,0xf3 = vrecpe.u32 d16, d16 3 | 0x60,0x04,0xfb,0xf3 = vrecpe.u32 q8, q8 4 | 0x20,0x05,0xfb,0xf3 = vrecpe.f32 d16, d16 5 | 0x60,0x05,0xfb,0xf3 = vrecpe.f32 q8, q8 6 | 0xb1,0x0f,0x40,0xf2 = vrecps.f32 d16, d16, d17 7 | 0xf2,0x0f,0x40,0xf2 = vrecps.f32 q8, q8, q9 8 | 0xa0,0x04,0xfb,0xf3 = vrsqrte.u32 d16, d16 9 | 0xe0,0x04,0xfb,0xf3 = vrsqrte.u32 q8, q8 10 | 0xa0,0x05,0xfb,0xf3 = vrsqrte.f32 d16, d16 11 | 0xe0,0x05,0xfb,0xf3 = vrsqrte.f32 q8, q8 12 | 0xb1,0x0f,0x60,0xf2 = vrsqrts.f32 d16, d16, d17 13 | 0xf2,0x0f,0x60,0xf2 = vrsqrts.f32 q8, q8, q9 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/vfp4-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17 3 | 0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0 4 | 0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17 5 | 0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0 6 | 0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17 7 | 0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0 8 | 0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17 9 | 0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0 10 | 0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17 11 | 0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0 12 | 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17 13 | 0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0 14 | -------------------------------------------------------------------------------- /suite/test_c.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run all the Python tests, and send the output that to a file to be compared later 4 | # This is useful when we want to verify if a commit (wrongly) changes the disassemble result. 5 | 6 | ../tests/test > /tmp/$1 7 | ../tests/test_detail >> /tmp/$1 8 | ../tests/test_skipdata >> /tmp/$1 9 | ../tests/test_iter >> /tmp/$1 10 | ../tests/test_arm >> /tmp/$1 11 | ../tests/test_arm64 >> /tmp/$1 12 | ../tests/test_mips >> /tmp/$1 13 | ../tests/test_ppc >> /tmp/$1 14 | ../tests/test_sparc >> /tmp/$1 15 | ../tests/test_x86 >> /tmp/$1 16 | ../tests/test_systemz >> /tmp/$1 17 | ../tests/test_xcore >> /tmp/$1 18 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-reciprocal-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xfb,0xff,0x20,0x04 = vrecpe.u32 d16, d16 3 | 0xfb,0xff,0x60,0x04 = vrecpe.u32 q8, q8 4 | 0xfb,0xff,0x20,0x05 = vrecpe.f32 d16, d16 5 | 0xfb,0xff,0x60,0x05 = vrecpe.f32 q8, q8 6 | 0x40,0xef,0xb1,0x0f = vrecps.f32 d16, d16, d17 7 | 0x40,0xef,0xf2,0x0f = vrecps.f32 q8, q8, q9 8 | 0xfb,0xff,0xa0,0x04 = vrsqrte.u32 d16, d16 9 | 0xfb,0xff,0xe0,0x04 = vrsqrte.u32 q8, q8 10 | 0xfb,0xff,0xa0,0x05 = vrsqrte.f32 d16, d16 11 | 0xfb,0xff,0xe0,0x05 = vrsqrte.f32 q8, q8 12 | 0x60,0xef,0xb1,0x0f = vrsqrts.f32 d16, d16, d17 13 | 0x60,0xef,0xf2,0x0f = vrsqrts.f32 q8, q8, q9 14 | -------------------------------------------------------------------------------- /arch/M680X/hd6301.inc: -------------------------------------------------------------------------------- 1 | 2 | // Additional instructions only supported on HD6301/3 3 | static const inst_pageX g_hd6301_inst_overlay_table[] = { 4 | { 0x18, M680X_INS_XGDX, inh_hid, inh_hid }, 5 | { 0x1a, M680X_INS_SLP, inh_hid, inh_hid }, 6 | { 0x61, M680X_INS_AIM, imm8_hid, idxX_hid }, 7 | { 0x62, M680X_INS_OIM, imm8_hid, idxX_hid }, 8 | { 0x65, M680X_INS_EIM, imm8_hid, idxX_hid }, 9 | { 0x6B, M680X_INS_TIM, imm8_hid, idxX_hid }, 10 | { 0x71, M680X_INS_AIM, imm8_hid, dir_hid }, 11 | { 0x72, M680X_INS_OIM, imm8_hid, dir_hid }, 12 | { 0x75, M680X_INS_EIM, imm8_hid, dir_hid }, 13 | { 0x7B, M680X_INS_TIM, imm8_hid, dir_hid }, 14 | }; 15 | 16 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x10,0x81,0x5f = fmla s0, s1, v1.s[0] 3 | 0x7e,0x11,0xa1,0x5f = fmla s30, s11, v1.s[1] 4 | 0xa4,0x18,0x87,0x5f = fmla s4, s5, v7.s[2] 5 | 0xd0,0x1a,0xb0,0x5f = fmla s16, s22, v16.s[3] 6 | 0x20,0x10,0xc1,0x5f = fmla d0, d1, v1.d[0] 7 | 0x7e,0x19,0xc1,0x5f = fmla d30, d11, v1.d[1] 8 | 0x62,0x50,0x84,0x5f = fmls s2, s3, v4.s[0] 9 | 0x5d,0x51,0xbc,0x5f = fmls s29, s10, v28.s[1] 10 | 0x85,0x59,0x97,0x5f = fmls s5, s12, v23.s[2] 11 | 0x27,0x5a,0xba,0x5f = fmls s7, s17, v26.s[3] 12 | 0x20,0x50,0xc1,0x5f = fmls d0, d1, v1.d[0] 13 | 0x7e,0x59,0xc1,0x5f = fmls d30, d11, v1.d[1] 14 | -------------------------------------------------------------------------------- /arch/M680X/M680XDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M680X Backend by Wolfgang Schwotzer 2017 */ 3 | 4 | #ifndef CS_M680XDISASSEMBLER_H 5 | #define CS_M680XDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len, 10 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 11 | void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 12 | void M680X_reg_access(const cs_insn *insn, 13 | cs_regs regs_read, uint8_t *regs_read_count, 14 | cs_regs regs_write, uint8_t *regs_write_count); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x90,0x81,0x5f = fmul s0, s1, v1.s[0] 3 | 0x7e,0x91,0xa1,0x5f = fmul s30, s11, v1.s[1] 4 | 0xa4,0x98,0x87,0x5f = fmul s4, s5, v7.s[2] 5 | 0xd0,0x9a,0xb0,0x5f = fmul s16, s22, v16.s[3] 6 | 0x20,0x90,0xc1,0x5f = fmul d0, d1, v1.d[0] 7 | 0x7e,0x99,0xc1,0x5f = fmul d30, d11, v1.d[1] 8 | 0x46,0x90,0x88,0x7f = fmulx s6, s2, v8.s[0] 9 | 0x67,0x90,0xad,0x7f = fmulx s7, s3, v13.s[1] 10 | 0xe9,0x98,0x89,0x7f = fmulx s9, s7, v9.s[2] 11 | 0xad,0x9a,0xaa,0x7f = fmulx s13, s21, v10.s[3] 12 | 0x2f,0x91,0xc7,0x7f = fmulx d15, d9, v7.d[0] 13 | 0x8d,0x99,0xcb,0x7f = fmulx d13, d12, v11.d[1] 14 | -------------------------------------------------------------------------------- /cstool/cstool_evm.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include 5 | 6 | void print_string_hex(char *comment, unsigned char *str, size_t len); 7 | 8 | void print_insn_detail_evm(csh handle, cs_insn *ins) 9 | { 10 | cs_evm *evm; 11 | 12 | // detail can be NULL on "data" instruction if SKIPDATA option is turned ON 13 | if (ins->detail == NULL) 14 | return; 15 | 16 | evm = &(ins->detail->evm); 17 | 18 | if (evm->pop) 19 | printf("\tPop: %u\n", evm->pop); 20 | 21 | if (evm->push) 22 | printf("\tPush: %u\n", evm->push); 23 | 24 | if (evm->fee) 25 | printf("\tGas fee: %u\n", evm->fee); 26 | } 27 | -------------------------------------------------------------------------------- /bindings/ocaml/ppc.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Ppc_const 5 | 6 | type ppc_op_mem = { 7 | base: int; 8 | disp: int; 9 | } 10 | 11 | type ppc_op_crx = { 12 | scale: int; 13 | reg: int; 14 | cond: int; 15 | } 16 | 17 | type ppc_op_value = 18 | | PPC_OP_INVALID of int 19 | | PPC_OP_REG of int 20 | | PPC_OP_IMM of int 21 | | PPC_OP_MEM of ppc_op_mem 22 | | PPC_OP_CRX of ppc_op_crx 23 | 24 | type ppc_op = { 25 | value: ppc_op_value; 26 | } 27 | 28 | type cs_ppc = { 29 | bc: int; 30 | bh: int; 31 | update_cr0: bool; 32 | operands: ppc_op array; 33 | } 34 | 35 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-shift-left-long.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0xa4,0x0b,0x0f = sshll v0.8h, v1.8b, #3 3 | 0x20,0xa4,0x13,0x0f = sshll v0.4s, v1.4h, #3 4 | 0x20,0xa4,0x23,0x0f = sshll v0.2d, v1.2s, #3 5 | 0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3 6 | 0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3 7 | 0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3 8 | 0x20,0xa4,0x0b,0x2f = ushll v0.8h, v1.8b, #3 9 | 0x20,0xa4,0x13,0x2f = ushll v0.4s, v1.4h, #3 10 | 0x20,0xa4,0x23,0x2f = ushll v0.2d, v1.2s, #3 11 | 0x20,0xa4,0x0b,0x6f = ushll2 v0.8h, v1.16b, #3 12 | 0x20,0xa4,0x13,0x6f = ushll2 v0.4s, v1.8h, #3 13 | 0x20,0xa4,0x23,0x6f = ushll2 v0.2d, v1.4s, #3 14 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-bitcount-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x05,0xf0,0xf3 = vcnt.8 d16, d16 3 | 0x60,0x05,0xf0,0xf3 = vcnt.8 q8, q8 4 | 0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16 5 | 0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16 6 | 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16 7 | 0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8 8 | 0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8 9 | 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8 10 | 0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16 11 | 0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16 12 | 0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16 13 | 0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8 14 | 0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8 15 | 0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-abs-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x03,0xf1,0xf3 = vabs.s8 d16, d16 3 | 0x20,0x03,0xf5,0xf3 = vabs.s16 d16, d16 4 | 0x20,0x03,0xf9,0xf3 = vabs.s32 d16, d16 5 | 0x20,0x07,0xf9,0xf3 = vabs.f32 d16, d16 6 | 0x60,0x03,0xf1,0xf3 = vabs.s8 q8, q8 7 | 0x60,0x03,0xf5,0xf3 = vabs.s16 q8, q8 8 | 0x60,0x03,0xf9,0xf3 = vabs.s32 q8, q8 9 | 0x60,0x07,0xf9,0xf3 = vabs.f32 q8, q8 10 | 0x20,0x07,0xf0,0xf3 = vqabs.s8 d16, d16 11 | 0x20,0x07,0xf4,0xf3 = vqabs.s16 d16, d16 12 | 0x20,0x07,0xf8,0xf3 = vqabs.s32 d16, d16 13 | 0x60,0x07,0xf0,0xf3 = vqabs.s8 q8, q8 14 | 0x60,0x07,0xf4,0xf3 = vqabs.s16 q8, q8 15 | 0x60,0x07,0xf8,0xf3 = vqabs.s32 q8, q8 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-neg-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xa0,0x03,0xf1,0xf3 = vneg.s8 d16, d16 3 | 0xa0,0x03,0xf5,0xf3 = vneg.s16 d16, d16 4 | 0xa0,0x03,0xf9,0xf3 = vneg.s32 d16, d16 5 | 0xa0,0x07,0xf9,0xf3 = vneg.f32 d16, d16 6 | 0xe0,0x03,0xf1,0xf3 = vneg.s8 q8, q8 7 | 0xe0,0x03,0xf5,0xf3 = vneg.s16 q8, q8 8 | 0xe0,0x03,0xf9,0xf3 = vneg.s32 q8, q8 9 | 0xe0,0x07,0xf9,0xf3 = vneg.f32 q8, q8 10 | 0xa0,0x07,0xf0,0xf3 = vqneg.s8 d16, d16 11 | 0xa0,0x07,0xf4,0xf3 = vqneg.s16 d16, d16 12 | 0xa0,0x07,0xf8,0xf3 = vqneg.s32 d16, d16 13 | 0xe0,0x07,0xf0,0xf3 = vqneg.s8 q8, q8 14 | 0xe0,0x07,0xf4,0xf3 = vqneg.s16 q8, q8 15 | 0xe0,0x07,0xf8,0xf3 = vqneg.s32 q8, q8 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-bitcount-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf0,0xff,0x20,0x05 = vcnt.8 d16, d16 3 | 0xf0,0xff,0x60,0x05 = vcnt.8 q8, q8 4 | 0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16 5 | 0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16 6 | 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16 7 | 0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8 8 | 0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8 9 | 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8 10 | 0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16 11 | 0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16 12 | 0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16 13 | 0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8 14 | 0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8 15 | 0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8 16 | -------------------------------------------------------------------------------- /suite/test_mc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # This script test all architectures by default. 4 | # At the output are all the mismatches between Capstone (CS) & LLVM (MC). 5 | # While most differences coming from the fact that Capstone uses more friendly 6 | # number format, some mismatches might be because Capstone is based on older 7 | # version of LLVM (which should be fixed in the next release) 8 | 9 | find MC/ -name *.cs | ./test_mc.py 10 | 11 | # To test just one architecture, specify the corresponsing dir: 12 | # $ find MC/X86 -name *.cs | ./test_mc.py 13 | 14 | # To test just one input file, run test_mc.py with that file: 15 | # $ ./test_mc.py MC/X86/x86-32-fma3.s.cs 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-abs-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xff,0x20,0x03 = vabs.s8 d16, d16 3 | 0xf5,0xff,0x20,0x03 = vabs.s16 d16, d16 4 | 0xf9,0xff,0x20,0x03 = vabs.s32 d16, d16 5 | 0xf9,0xff,0x20,0x07 = vabs.f32 d16, d16 6 | 0xf1,0xff,0x60,0x03 = vabs.s8 q8, q8 7 | 0xf5,0xff,0x60,0x03 = vabs.s16 q8, q8 8 | 0xf9,0xff,0x60,0x03 = vabs.s32 q8, q8 9 | 0xf9,0xff,0x60,0x07 = vabs.f32 q8, q8 10 | 0xf0,0xff,0x20,0x07 = vqabs.s8 d16, d16 11 | 0xf4,0xff,0x20,0x07 = vqabs.s16 d16, d16 12 | 0xf8,0xff,0x20,0x07 = vqabs.s32 d16, d16 13 | 0xf0,0xff,0x60,0x07 = vqabs.s8 q8, q8 14 | 0xf4,0xff,0x60,0x07 = vqabs.s16 q8, q8 15 | 0xf8,0xff,0x60,0x07 = vqabs.s32 q8, q8 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-bitwise-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x41,0xef,0xb0,0x01 = vand d16, d17, d16 3 | 0x40,0xef,0xf2,0x01 = vand q8, q8, q9 4 | 0x41,0xff,0xb0,0x01 = veor d16, d17, d16 5 | 0x40,0xff,0xf2,0x01 = veor q8, q8, q9 6 | 0x61,0xef,0xb0,0x01 = vorr d16, d17, d16 7 | 0x60,0xef,0xf2,0x01 = vorr q8, q8, q9 8 | 0x51,0xef,0xb0,0x01 = vbic d16, d17, d16 9 | 0x50,0xef,0xf2,0x01 = vbic q8, q8, q9 10 | 0x71,0xef,0xb0,0x01 = vorn d16, d17, d16 11 | 0x70,0xef,0xf2,0x01 = vorn q8, q8, q9 12 | 0xf0,0xff,0xa0,0x05 = vmvn d16, d16 13 | 0xf0,0xff,0xe0,0x05 = vmvn q8, q8 14 | 0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16 15 | 0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-neg-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xff,0xa0,0x03 = vneg.s8 d16, d16 3 | 0xf5,0xff,0xa0,0x03 = vneg.s16 d16, d16 4 | 0xf9,0xff,0xa0,0x03 = vneg.s32 d16, d16 5 | 0xf9,0xff,0xa0,0x07 = vneg.f32 d16, d16 6 | 0xf1,0xff,0xe0,0x03 = vneg.s8 q8, q8 7 | 0xf5,0xff,0xe0,0x03 = vneg.s16 q8, q8 8 | 0xf9,0xff,0xe0,0x03 = vneg.s32 q8, q8 9 | 0xf9,0xff,0xe0,0x07 = vneg.f32 q8, q8 10 | 0xf0,0xff,0xa0,0x07 = vqneg.s8 d16, d16 11 | 0xf4,0xff,0xa0,0x07 = vqneg.s16 d16, d16 12 | 0xf8,0xff,0xa0,0x07 = vqneg.s32 d16, d16 13 | 0xf0,0xff,0xe0,0x07 = vqneg.s8 q8, q8 14 | 0xf4,0xff,0xe0,0x07 = vqneg.s16 q8, q8 15 | 0xf8,0xff,0xe0,0x07 = vqneg.s32 q8, q8 16 | -------------------------------------------------------------------------------- /arch/ARM/ARMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_ARMDISASSEMBLER_H 5 | #define CS_ARMDISASSEMBLER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | 10 | void ARM_init(MCRegisterInfo *MRI); 11 | 12 | bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 13 | 14 | bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | uint64_t ARM_getFeatureBits(unsigned int mode); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /suite/MC/ARM/load-store-acquire-release-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x9f,0x3e,0xd4,0xe1 = ldaexb r3, [r4] 3 | 0x9f,0x2e,0xf5,0xe1 = ldaexh r2, [r5] 4 | 0x9f,0x1e,0x97,0xe1 = ldaex r1, [r7] 5 | 0x9f,0x6e,0xb8,0xe1 = ldaexd r6, r7, [r8] 6 | 0x93,0x1e,0xc4,0xe1 = stlexb r1, r3, [r4] 7 | 0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5] 8 | 0x91,0x2e,0x87,0xe1 = stlex r2, r1, [r7] 9 | 0x92,0x6e,0xa8,0xe1 = stlexd r6, r2, r3, [r8] 10 | 0x9f,0x5c,0x96,0xe1 = lda r5, [r6] 11 | 0x9f,0x5c,0xd6,0xe1 = ldab r5, [r6] 12 | 0x9f,0xcc,0xf9,0xe1 = ldah r12, [r9] 13 | 0x93,0xfc,0x80,0xe1 = stl r3, [r0] 14 | 0x92,0xfc,0xc1,0xe1 = stlb r2, [r1] 15 | 0x92,0xfc,0xe3,0xe1 = stlh r2, [r3] 16 | -------------------------------------------------------------------------------- /suite/MC/ARM/load-store-acquire-release-v8-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xd4,0xe8,0xcf,0x3f = ldaexb r3, [r4] 3 | 0xd5,0xe8,0xdf,0x2f = ldaexh r2, [r5] 4 | 0xd7,0xe8,0xef,0x1f = ldaex r1, [r7] 5 | 0xd8,0xe8,0xff,0x67 = ldaexd r6, r7, [r8] 6 | 0xc4,0xe8,0xc1,0x3f = stlexb r1, r3, [r4] 7 | 0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5] 8 | 0xc7,0xe8,0xe2,0x1f = stlex r2, r1, [r7] 9 | 0xc8,0xe8,0xf6,0x23 = stlexd r6, r2, r3, [r8] 10 | 0xd6,0xe8,0xaf,0x5f = lda r5, [r6] 11 | 0xd6,0xe8,0x8f,0x5f = ldab r5, [r6] 12 | 0xd9,0xe8,0x9f,0xcf = ldah r12, [r9] 13 | 0xc0,0xe8,0xaf,0x3f = stl r3, [r0] 14 | 0xc1,0xe8,0x8f,0x2f = stlb r2, [r1] 15 | 0xc3,0xe8,0x9f,0x2f = stlh r2, [r3] 16 | -------------------------------------------------------------------------------- /suite/compile_all.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | # By Daniel Godas-Lopez. 3 | 4 | export LD_LIBRARY_PATH=. 5 | 6 | for x in default nix32 cross-win32 cross-win64 cygwin-mingw32 cygwin-mingw64 bsd clang gcc; do 7 | echo -n "Compiling: $x ... " 8 | ./compile.sh $x &> /dev/null 9 | 10 | if [ $? == 0 ]; then 11 | echo "-> PASS" 12 | else 13 | echo -e "-> FAILED\n" 14 | continue 15 | fi 16 | 17 | for t in test test_arm test_arm64 test_detail test_mips test_x86 test_ppc; do 18 | ./tests/$t &> /dev/null 19 | 20 | if [ $? -eq 0 ]; then 21 | echo " Run $t -> PASS" 22 | else 23 | echo " Run $t -> FAIL" 24 | fi 25 | done 26 | 27 | echo 28 | done 29 | 30 | make clean &> /dev/null 31 | -------------------------------------------------------------------------------- /suite/cstest/src/evm_detail.c: -------------------------------------------------------------------------------- 1 | /* Capstone testing regression */ 2 | /* By Do Minh Tuan , 02-2019 */ 3 | 4 | 5 | #include "factory.h" 6 | 7 | char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins) 8 | { 9 | cs_evm *evm; 10 | char *result; 11 | 12 | result = (char *)malloc(sizeof(char)); 13 | result[0] = '\0'; 14 | 15 | if (ins->detail == NULL) 16 | return result; 17 | 18 | evm = &(ins->detail->evm); 19 | 20 | if (evm->pop) 21 | add_str(&result, " ; Pop: %u", evm->pop); 22 | 23 | if (evm->push) 24 | add_str(&result, " ; Push: %u", evm->push); 25 | 26 | if (evm->fee) 27 | add_str(&result, " ; Gas fee: %u", evm->fee); 28 | 29 | return result; 30 | } 31 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-facge-facgt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s 3 | 0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s 4 | 0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d 5 | 0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s 6 | 0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s 7 | 0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d 8 | 0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s 9 | 0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s 10 | 0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d 11 | 0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s 12 | 0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s 13 | 0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d 14 | -------------------------------------------------------------------------------- /packages/freebsd/ports/devel/capstone/Makefile: -------------------------------------------------------------------------------- 1 | # $FreeBSD$ 2 | 3 | PORTNAME= capstone 4 | PORTVERSION= 4.0.0 5 | CATEGORIES= devel 6 | MASTER_SITES= https://capstone-engine.org/download/${PORTVERSION}/ 7 | 8 | MAINTAINER= oliver.pntr@gmail.com 9 | COMMENT= Multi-platform, multi-architecture disassembly framework 10 | 11 | LICENSE= BSD3CLAUSE 12 | 13 | USES= gmake 14 | USE_LDCONFIG= yes 15 | 16 | MAKE_ENV+= INSTALL_LIB="${INSTALL_LIB}" \ 17 | INSTALL_DATA="${INSTALL_DATA}" 18 | 19 | post-build: 20 | # The pkgconfig file is generated and points to stagedir 21 | ${REINPLACE_CMD} -e '/libdir/s|\(libdir=\)\(.*\)\(devel/capstone/work/stage\)|\1|g' ${WRKSRC}/capstone.pc 22 | 23 | .include 24 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-rounding-halving-add.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x14,0x22,0x0e = srhadd v0.8b, v1.8b, v2.8b 3 | 0x20,0x14,0x22,0x4e = srhadd v0.16b, v1.16b, v2.16b 4 | 0x20,0x14,0x62,0x0e = srhadd v0.4h, v1.4h, v2.4h 5 | 0x20,0x14,0x62,0x4e = srhadd v0.8h, v1.8h, v2.8h 6 | 0x20,0x14,0xa2,0x0e = srhadd v0.2s, v1.2s, v2.2s 7 | 0x20,0x14,0xa2,0x4e = srhadd v0.4s, v1.4s, v2.4s 8 | 0x20,0x14,0x22,0x2e = urhadd v0.8b, v1.8b, v2.8b 9 | 0x20,0x14,0x22,0x6e = urhadd v0.16b, v1.16b, v2.16b 10 | 0x20,0x14,0x62,0x2e = urhadd v0.4h, v1.4h, v2.4h 11 | 0x20,0x14,0x62,0x6e = urhadd v0.8h, v1.8h, v2.8h 12 | 0x20,0x14,0xa2,0x2e = urhadd v0.2s, v1.2s, v2.2s 13 | 0x20,0x14,0xa2,0x6e = urhadd v0.4s, v1.4s, v2.4s 14 | -------------------------------------------------------------------------------- /.github/workflows/fuzz.yml: -------------------------------------------------------------------------------- 1 | name: CIFuzz 2 | on: [pull_request] 3 | jobs: 4 | Fuzzing: 5 | runs-on: ubuntu-latest 6 | steps: 7 | - name: Build Fuzzers 8 | uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master 9 | with: 10 | oss-fuzz-project-name: 'capstone' 11 | dry-run: false 12 | - name: Run Fuzzers 13 | uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master 14 | with: 15 | oss-fuzz-project-name: 'capstone' 16 | fuzz-seconds: 600 17 | dry-run: false 18 | - name: Upload Crash 19 | uses: actions/upload-artifact@v1 20 | if: failure() 21 | with: 22 | name: artifacts 23 | path: ./out/artifacts 24 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-crypto.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x48,0x28,0x4e = aese v0.16b, v1.16b 3 | 0x20,0x58,0x28,0x4e = aesd v0.16b, v1.16b 4 | 0x20,0x68,0x28,0x4e = aesmc v0.16b, v1.16b 5 | 0x20,0x78,0x28,0x4e = aesimc v0.16b, v1.16b 6 | 0x20,0x08,0x28,0x5e = sha1h s0, s1 7 | 0x20,0x18,0x28,0x5e = sha1su1 v0.4s, v1.4s 8 | 0x20,0x28,0x28,0x5e = sha256su0 v0.4s, v1.4s 9 | 0x20,0x00,0x02,0x5e = sha1c q0, s1, v2.4s 10 | 0x20,0x10,0x02,0x5e = sha1p q0, s1, v2.4s 11 | 0x20,0x20,0x02,0x5e = sha1m q0, s1, v2.4s 12 | 0x20,0x30,0x02,0x5e = sha1su0 v0.4s, v1.4s, v2.4s 13 | 0x20,0x40,0x02,0x5e = sha256h q0, q1, v2.4s 14 | 0x20,0x50,0x02,0x5e = sha256h2 q0, q1, v2.4s 15 | 0x20,0x60,0x02,0x5e = sha256su1 v0.4s, v1.4s, v2.4s 16 | -------------------------------------------------------------------------------- /SPONSORS.TXT: -------------------------------------------------------------------------------- 1 | * Version 4.0.1 - January 10th, 2019 2 | 3 | Release 4.0.1 was sponsored by the following companies (in no particular order). 4 | 5 | - NowSecure: https://www.nowsecure.com 6 | - Verichains: https://verichains.io 7 | - Vsec: https://vsec.com.vn 8 | 9 | ----------------------------------- 10 | * Version 4.0 - December 18th, 2018 11 | 12 | Capstone 4.0 version marks 5 years of the project! 13 | This release was sponsored by the following companies (in no particular order). 14 | 15 | - Thinkst Canary: https://canary.tools 16 | - NowSecure: https://www.nowsecure.com 17 | - ECQ: https://e-cq.net 18 | - Senrio: https://senr.io 19 | - GracefulBits: https://gracefulbits.com 20 | - Catena Cyber: https://catenacyber.fr 21 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_2r.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x7b,0x00,0x4f,0x9e = fill.b $w30, $t1 3 | 0x7b,0x01,0xbf,0xde = fill.h $w31, $s7 4 | 0x7b,0x02,0xc4,0x1e = fill.w $w16, $t8 5 | 0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0 6 | 0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31 7 | 0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23 8 | 0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10 9 | 0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2 10 | 0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22 11 | 0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29 12 | 0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9 13 | 0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18 14 | 0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8 15 | 0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9 16 | 0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24 17 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm_addrmode2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2 3 | 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3 4 | 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4 5 | 0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2 6 | 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3 7 | 0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4 8 | 0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2 9 | 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3 10 | 0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4 11 | 0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2 12 | 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3 13 | 0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4 14 | 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]! 15 | 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]! 16 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips-memory-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x10,0x00,0xa4,0xa0 = sb $a0, 16($a1) 3 | 0x10,0x00,0xa4,0xe0 = sc $a0, 16($a1) 4 | 0x10,0x00,0xa4,0xa4 = sh $a0, 16($a1) 5 | 0x10,0x00,0xa4,0xac = sw $a0, 16($a1) 6 | 0x00,0x00,0xa7,0xac = sw $a3, ($a1) 7 | 0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($a1) 8 | 0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1) 9 | 0x04,0x00,0xa4,0x80 = lb $a0, 4($a1) 10 | 0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) 11 | 0x04,0x00,0xa4,0x90 = lbu $a0, 4($a1) 12 | 0x04,0x00,0xa4,0x84 = lh $a0, 4($a1) 13 | 0x04,0x00,0xa4,0x94 = lhu $a0, 4($a1) 14 | 0x04,0x00,0xa4,0xc0 = ll $a0, 4($a1) 15 | 0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) 16 | 0x00,0x00,0xe7,0x8c = lw $a3, ($a3) 17 | 0x10,0x00,0xa2,0x8f = lw $v0, 16($sp) 18 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-crypto.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x42,0x03,0xb0,0xf3 = aesd.8 q0, q1 3 | 0x02,0x03,0xb0,0xf3 = aese.8 q0, q1 4 | 0xc2,0x03,0xb0,0xf3 = aesimc.8 q0, q1 5 | 0x82,0x03,0xb0,0xf3 = aesmc.8 q0, q1 6 | 0xc2,0x02,0xb9,0xf3 = sha1h.32 q0, q1 7 | 0x82,0x03,0xba,0xf3 = sha1su1.32 q0, q1 8 | 0xc2,0x03,0xba,0xf3 = sha256su0.32 q0, q1 9 | 0x44,0x0c,0x02,0xf2 = sha1c.32 q0, q1, q2 10 | 0x44,0x0c,0x22,0xf2 = sha1m.32 q0, q1, q2 11 | 0x44,0x0c,0x12,0xf2 = sha1p.32 q0, q1, q2 12 | 0x44,0x0c,0x32,0xf2 = sha1su0.32 q0, q1, q2 13 | 0x44,0x0c,0x02,0xf3 = sha256h.32 q0, q1, q2 14 | 0x44,0x0c,0x12,0xf3 = sha256h2.32 q0, q1, q2 15 | 0x44,0x0c,0x22,0xf3 = sha256su1.32 q0, q1, q2 16 | 0xa1,0x0e,0xe0,0xf2 = vmull.p64 q8, d16, d17 17 | -------------------------------------------------------------------------------- /windows/winkernel_mm.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Satoshi Tanda , 2016 */ 3 | 4 | #ifndef CS_WINDOWS_WINKERNEL_MM_H 5 | #define CS_WINDOWS_WINKERNEL_MM_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | 13 | void CAPSTONE_API cs_winkernel_free(void *ptr); 14 | void * CAPSTONE_API cs_winkernel_malloc(size_t size); 15 | void * CAPSTONE_API cs_winkernel_calloc(size_t n, size_t size); 16 | void * CAPSTONE_API cs_winkernel_realloc(void *ptr, size_t size); 17 | int CAPSTONE_API cs_winkernel_vsnprintf(char *buffer, size_t count, const char *format, va_list argptr); 18 | 19 | #ifdef __cplusplus 20 | } 21 | #endif 22 | 23 | #endif // CS_WINDOWS_WINKERNEL_MM_H 24 | -------------------------------------------------------------------------------- /bindings/python/test_all.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import test_basic, test_arm, test_arm64, test_detail, test_lite, test_m68k, test_mips, \ 4 | test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \ 5 | test_m680x, test_mos65xx 6 | 7 | test_basic.test_class() 8 | test_arm.test_class() 9 | test_arm64.test_class() 10 | test_detail.test_class() 11 | test_lite.test_class() 12 | test_m68k.test_class() 13 | test_mips.test_class() 14 | test_mos65xx.test_class() 15 | test_ppc.test_class() 16 | test_sparc.test_class() 17 | test_systemz.test_class() 18 | test_x86.test_class() 19 | test_tms320c64x.test_class() 20 | test_m680x.test_class() 21 | test_skipdata.test_class() 22 | test_customized_mnem.test() 23 | -------------------------------------------------------------------------------- /arch/SystemZ/SystemZMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SYSZ_MAP_H 5 | #define CS_SYSZ_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *SystemZ_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *SystemZ_insn_name(csh handle, unsigned int id); 16 | 17 | const char *SystemZ_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | sysz_reg SystemZ_map_register(unsigned int r); 21 | 22 | #endif 23 | 24 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb-neon-crypto.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xb0,0xff,0x42,0x03 = aesd.8 q0, q1 3 | 0xb0,0xff,0x02,0x03 = aese.8 q0, q1 4 | 0xb0,0xff,0xc2,0x03 = aesimc.8 q0, q1 5 | 0xb0,0xff,0x82,0x03 = aesmc.8 q0, q1 6 | 0xb9,0xff,0xc2,0x02 = sha1h.32 q0, q1 7 | 0xba,0xff,0x82,0x03 = sha1su1.32 q0, q1 8 | 0xba,0xff,0xc2,0x03 = sha256su0.32 q0, q1 9 | 0x02,0xef,0x44,0x0c = sha1c.32 q0, q1, q2 10 | 0x22,0xef,0x44,0x0c = sha1m.32 q0, q1, q2 11 | 0x12,0xef,0x44,0x0c = sha1p.32 q0, q1, q2 12 | 0x32,0xef,0x44,0x0c = sha1su0.32 q0, q1, q2 13 | 0x02,0xff,0x44,0x0c = sha256h.32 q0, q1, q2 14 | 0x12,0xff,0x44,0x0c = sha256h2.32 q0, q1, q2 15 | 0x22,0xff,0x44,0x0c = sha256su1.32 q0, q1, q2 16 | 0xe0,0xef,0xa1,0x0e = vmull.p64 q8, d16, d17 17 | -------------------------------------------------------------------------------- /bindings/python/test_evm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # Capstone Python bindings, by Nguyen Anh Quynnh 4 | 5 | from __future__ import print_function 6 | from capstone import * 7 | 8 | cs = Cs(CS_ARCH_EVM, 0) 9 | cs.detail = True 10 | 11 | for i in cs.disasm("\x60\x61\x55", 0x100): 12 | print("0x%x:\t%s\t%s" %(i.address, i.mnemonic, i.op_str)) 13 | if i.pop > 0: 14 | print("\tPop: %u" %i.pop) 15 | if i.push > 0: 16 | print("\tPush: %u" %i.push) 17 | if i.fee > 0: 18 | print("\tGas fee: %u" %i.fee) 19 | if len(i.groups) > 0: 20 | print("\tThis instruction belongs to groups: ", end=''), 21 | for m in i.groups: 22 | print("%s " % i.group_name(m), end=''), 23 | print() 24 | -------------------------------------------------------------------------------- /arch/M680X/M680XInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M680X Backend by Wolfgang Schwotzer 2017 */ 3 | 4 | #ifndef CS_M680XINSTPRINTER_H 5 | #define CS_M680XINSTPRINTER_H 6 | 7 | 8 | #include "capstone/capstone.h" 9 | #include "../../MCRegisterInfo.h" 10 | #include "../../MCInst.h" 11 | 12 | struct SStream; 13 | 14 | void M680X_init(MCRegisterInfo *MRI); 15 | 16 | void M680X_printInst(MCInst *MI, struct SStream *O, void *Info); 17 | const char *M680X_reg_name(csh handle, unsigned int reg); 18 | const char *M680X_insn_name(csh handle, unsigned int id); 19 | const char *M680X_group_name(csh handle, unsigned int id); 20 | void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, 21 | MCInst *mci); 22 | 23 | #endif 24 | 25 | 26 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_elm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x82,0x43,0x59 = copy_s.b $t5, $w8[2] 3 | 0x78,0xa0,0xc8,0x59 = copy_s.h $at, $w25[0] 4 | 0x78,0xb1,0x2d,0x99 = copy_s.w $s6, $w5[1] 5 | 0x78,0xc4,0xa5,0x99 = copy_u.b $s6, $w20[4] 6 | 0x78,0xe0,0x25,0x19 = copy_u.h $s4, $w4[0] 7 | 0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2] 8 | 0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4] 9 | 0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0] 10 | 0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2] 11 | 0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0] 12 | 0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2] 13 | 0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1] 14 | 0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0] 15 | 0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0] 16 | 0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24 17 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x54,0x22,0x0e = srshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x54,0x22,0x4e = srshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x54,0x62,0x0e = srshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x54,0x62,0x4e = srshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x54,0xa2,0x0e = srshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x54,0xa2,0x4e = srshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x54,0xe2,0x4e = srshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x54,0x22,0x2e = urshl v0.8b, v1.8b, v2.8b 10 | 0x20,0x54,0x22,0x6e = urshl v0.16b, v1.16b, v2.16b 11 | 0x20,0x54,0x62,0x2e = urshl v0.4h, v1.4h, v2.4h 12 | 0x20,0x54,0x62,0x6e = urshl v0.8h, v1.8h, v2.8h 13 | 0x20,0x54,0xa2,0x2e = urshl v0.2s, v1.2s, v2.2s 14 | 0x20,0x54,0xa2,0x6e = urshl v0.4s, v1.4s, v2.4s 15 | 0x20,0x54,0xe2,0x6e = urshl v0.2d, v1.2d, v2.2d 16 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-saturating-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x4c,0x22,0x0e = sqshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x4c,0x22,0x4e = sqshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x4c,0x62,0x0e = sqshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x4c,0x62,0x4e = sqshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x4c,0xa2,0x0e = sqshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x4c,0xa2,0x4e = sqshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x4c,0xe2,0x4e = sqshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x4c,0x22,0x2e = uqshl v0.8b, v1.8b, v2.8b 10 | 0x20,0x4c,0x22,0x6e = uqshl v0.16b, v1.16b, v2.16b 11 | 0x20,0x4c,0x62,0x2e = uqshl v0.4h, v1.4h, v2.4h 12 | 0x20,0x4c,0x62,0x6e = uqshl v0.8h, v1.8h, v2.8h 13 | 0x20,0x4c,0xa2,0x2e = uqshl v0.2s, v1.2s, v2.2s 14 | 0x20,0x4c,0xa2,0x6e = uqshl v0.4s, v1.4s, v2.4s 15 | 0x20,0x4c,0xe2,0x6e = uqshl v0.2d, v1.2d, v2.2d 16 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x00,0x30,0x40,0x5f = sqdmlal s0, h0, v0.h[0] 3 | 0x27,0x30,0x74,0x5f = sqdmlal s7, h1, v4.h[3] 4 | 0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4] 5 | 0xde,0x3b,0x7f,0x5f = sqdmlal s30, h30, v15.h[7] 6 | 0x00,0x30,0x83,0x5f = sqdmlal d0, s0, v3.s[0] 7 | 0xde,0x3b,0xbe,0x5f = sqdmlal d30, s30, v30.s[3] 8 | 0x28,0x31,0xae,0x5f = sqdmlal d8, s9, v14.s[1] 9 | 0x21,0x70,0x41,0x5f = sqdmlsl s1, h1, v1.h[0] 10 | 0x48,0x70,0x55,0x5f = sqdmlsl s8, h2, v5.h[1] 11 | 0xac,0x71,0x6e,0x5f = sqdmlsl s12, h13, v14.h[2] 12 | 0x9d,0x7b,0x7b,0x5f = sqdmlsl s29, h28, v11.h[7] 13 | 0x21,0x70,0x8d,0x5f = sqdmlsl d1, s1, v13.s[0] 14 | 0xff,0x7b,0x9f,0x5f = sqdmlsl d31, s31, v31.s[2] 15 | 0x50,0x7a,0xbc,0x5f = sqdmlsl d16, s18, v28.s[3] 16 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips-coprocessor-encodings.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 2 | 0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2 3 | 0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0 4 | 0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2 5 | 0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0 6 | 0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2 7 | 0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0 8 | 0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2 9 | 0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0 10 | 0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2 11 | 0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0 12 | 0x48,0x8c,0x80,0x02 = mtc2 $t4, $s0, 2 13 | 0x48,0x8c,0x80,0x00 = mtc2 $t4, $s0, 0 14 | 0x48,0x2c,0x80,0x02 = dmfc2 $t4, $s0, 2 15 | 0x48,0x2c,0x80,0x00 = dmfc2 $t4, $s0, 0 16 | 0x48,0x0c,0x80,0x02 = mfc2 $t4, $s0, 2 17 | 0x48,0x0c,0x80,0x00 = mfc2 $t4, $s0, 0 18 | -------------------------------------------------------------------------------- /arch/M68K/M68KInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M68K Backend by Daniel Collin 2015 */ 3 | 4 | #ifndef CS_M68KINSTPRINTER_H 5 | #define CS_M68KINSTPRINTER_H 6 | 7 | #include "capstone/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../MCInst.h" 10 | 11 | struct SStream; 12 | 13 | void M68K_init(MCRegisterInfo *MRI); 14 | void M68K_printInst(MCInst* MI, struct SStream* O, void* Info); 15 | const char* M68K_reg_name(csh handle, unsigned int reg); 16 | void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id); 17 | const char *M68K_insn_name(csh handle, unsigned int id); 18 | const char* M68K_group_name(csh handle, unsigned int id); 19 | void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci); 20 | 21 | #endif 22 | -------------------------------------------------------------------------------- /arch/EVM/EVMModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh, 2018 */ 3 | 4 | #ifdef CAPSTONE_HAS_EVM 5 | 6 | #include "../../cs_priv.h" 7 | #include "EVMDisassembler.h" 8 | #include "EVMInstPrinter.h" 9 | #include "EVMMapping.h" 10 | #include "EVMModule.h" 11 | 12 | cs_err EVM_global_init(cs_struct *ud) 13 | { 14 | // verify if requested mode is valid 15 | if (ud->mode) 16 | return CS_ERR_MODE; 17 | 18 | ud->printer = EVM_printInst; 19 | ud->printer_info = NULL; 20 | ud->insn_id = EVM_get_insn_id; 21 | ud->insn_name = EVM_insn_name; 22 | ud->group_name = EVM_group_name; 23 | ud->disasm = EVM_getInstruction; 24 | 25 | return CS_ERR_OK; 26 | } 27 | 28 | cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value) 29 | { 30 | return CS_ERR_OK; 31 | } 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /packages/macports/devel/capstone/files/patch-Makefile.diff: -------------------------------------------------------------------------------- 1 | --- Makefile 2 | +++ Makefile 3 | @@ -246,14 +246,6 @@ EXT = dylib 4 | VERSION_EXT = $(API_MAJOR).$(EXT) 5 | $(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) 6 | AR_EXT = a 7 | -# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE 8 | -# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default 9 | -ifneq ($(HOMEBREW_CAPSTONE),1) 10 | -ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) 11 | -# remove string check because OSX kernel complains about missing symbols 12 | -CFLAGS += -D_FORTIFY_SOURCE=0 13 | -endif 14 | -endif 15 | else 16 | $(LIBNAME)_LDFLAGS += -shared 17 | # Cygwin? 18 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-saturating-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x5c,0x22,0x0e = sqrshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x5c,0x22,0x4e = sqrshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x5c,0x62,0x0e = sqrshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x5c,0x62,0x4e = sqrshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x5c,0xa2,0x0e = sqrshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x5c,0xa2,0x4e = sqrshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x5c,0xe2,0x4e = sqrshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x5c,0x22,0x2e = uqrshl v0.8b, v1.8b, v2.8b 10 | 0x20,0x5c,0x22,0x6e = uqrshl v0.16b, v1.16b, v2.16b 11 | 0x20,0x5c,0x62,0x2e = uqrshl v0.4h, v1.4h, v2.4h 12 | 0x20,0x5c,0x62,0x6e = uqrshl v0.8h, v1.8h, v2.8h 13 | 0x20,0x5c,0xa2,0x2e = uqrshl v0.2s, v1.2s, v2.2s 14 | 0x20,0x5c,0xa2,0x6e = uqrshl v0.4s, v1.4s, v2.4s 15 | 0x20,0x5c,0xe2,0x6e = uqrshl v0.2d, v1.2d, v2.2d 16 | -------------------------------------------------------------------------------- /arch/Mips/MipsMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_MIPS_MAP_H 5 | #define CS_MIPS_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *Mips_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *Mips_insn_name(csh handle, unsigned int id); 16 | 17 | const char *Mips_group_name(csh handle, unsigned int id); 18 | 19 | // map instruction name to instruction ID 20 | mips_reg Mips_map_insn(const char *name); 21 | 22 | // map internal raw register to 'public' register 23 | mips_reg Mips_map_register(unsigned int r); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /arch/XCore/XCoreMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_XCORE_MAP_H 5 | #define CS_XCORE_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *XCore_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *XCore_insn_name(csh handle, unsigned int id); 16 | 17 | const char *XCore_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | xcore_reg XCore_map_register(unsigned int r); 21 | 22 | // map register name to register ID 23 | xcore_reg XCore_reg_id(char *name); 24 | 25 | #endif 26 | 27 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips-expansions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x7b,0x00,0x05,0x34 = ori $a1, $zero, 123 3 | 0xd7,0xf6,0x06,0x24 = addiu $a2, $zero, -2345 4 | 0x01,0x00,0x07,0x3c = lui $a3, 1 5 | 0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 6 | 0x14,0x00,0x04,0x24 = addiu $a0, $zero, 20 7 | 0x01,0x00,0x07,0x3c = lui $a3, 1 8 | 0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 9 | 0x14,0x00,0xa4,0x24 = addiu $a0, $a1, 20 10 | 0x01,0x00,0x07,0x3c = lui $a3, 1 11 | 0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 12 | 0x21,0x38,0xe8,0x00 = addu $a3, $a3, $t0 13 | 0x21,0x50,0x44,0x01 = addu $t2, $t2, $a0 14 | 0x21,0x08,0x29,0x00 = addu $at, $at, $t1 15 | 0x0a,0x00,0x0a,0x3c = lui $t2, 10 16 | 0x7b,0x00,0x4a,0x8d = lw $t2, 123($t2) 17 | 0x02,0x00,0x01,0x3c = lui $at, 2 18 | 0x21,0x08,0x29,0x00 = addu $at, $at, $t1 19 | // 0x40,0xe2,0x2a,0xac = sw $t2, 57920($at) 20 | -------------------------------------------------------------------------------- /suite/MC/X86/x86_64-avx-clmul-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | // 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulhqhqdq %xmm12, %xmm10, %xmm11 3 | // 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulhqhqdq (%rax), %xmm10, %xmm13 4 | // 0xc4,0x43,0x29,0x44,0xdc,0x01 = vpclmulhqlqdq %xmm12, %xmm10, %xmm11 5 | // 0xc4,0x63,0x29,0x44,0x28,0x01 = vpclmulhqlqdq (%rax), %xmm10, %xmm13 6 | // 0xc4,0x43,0x29,0x44,0xdc,0x10 = vpclmullqhqdq %xmm12, %xmm10, %xmm11 7 | // 0xc4,0x63,0x29,0x44,0x28,0x10 = vpclmullqhqdq (%rax), %xmm10, %xmm13 8 | // 0xc4,0x43,0x29,0x44,0xdc,0x00 = vpclmullqlqdq %xmm12, %xmm10, %xmm11 9 | // 0xc4,0x63,0x29,0x44,0x28,0x00 = vpclmullqlqdq (%rax), %xmm10, %xmm13 10 | // 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulqdq $17, %xmm12, %xmm10, %xmm11 11 | // 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulqdq $17, (%rax), %xmm10, %xmm13 12 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-cmp-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 3 | 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 4 | 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 5 | 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 6 | 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 7 | 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 8 | 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 9 | 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 10 | 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 11 | 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 12 | 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 13 | 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 14 | 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 15 | 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 16 | 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 17 | 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 18 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-dup-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xc0,0xee,0x90,0x1b = vdup.8 d16, r1 3 | 0x8f,0xee,0x30,0x2b = vdup.16 d15, r2 4 | 0x8e,0xee,0x10,0x3b = vdup.32 d14, r3 5 | 0xe2,0xee,0x90,0x4b = vdup.8 q9, r4 6 | 0xa0,0xee,0xb0,0x5b = vdup.16 q8, r5 7 | 0xae,0xee,0x10,0x6b = vdup.32 q7, r6 8 | 0xf1,0xff,0x0b,0x0c = vdup.8 d16, d11[0] 9 | 0xf2,0xff,0x0c,0x1c = vdup.16 d17, d12[0] 10 | 0xf4,0xff,0x0d,0x2c = vdup.32 d18, d13[0] 11 | 0xb1,0xff,0x4a,0x6c = vdup.8 q3, d10[0] 12 | 0xf2,0xff,0x49,0x2c = vdup.16 q9, d9[0] 13 | 0xf4,0xff,0x48,0x0c = vdup.32 q8, d8[0] 14 | 0xf3,0xff,0x0b,0x0c = vdup.8 d16, d11[1] 15 | 0xf6,0xff,0x0c,0x1c = vdup.16 d17, d12[1] 16 | 0xfc,0xff,0x0d,0x2c = vdup.32 d18, d13[1] 17 | 0xb3,0xff,0x4a,0x6c = vdup.8 q3, d10[1] 18 | 0xf6,0xff,0x49,0x2c = vdup.16 q9, d9[1] 19 | 0xfc,0xff,0x48,0x0c = vdup.32 q8, d8[1] 20 | -------------------------------------------------------------------------------- /packages/freebsd/ports/devel/capstone/pkg-descr: -------------------------------------------------------------------------------- 1 | Capstone is a lightweight multi-platform, multi-architecture disassembly 2 | framework. 3 | 4 | Features: 5 | * Supported architectures: ARM, ARM64 (aka ARMv8), Mips, PowerPC, Sparc, 6 | SystemZ, X86, X86_64 & XCore. 7 | * Clean/simple/lightweight/intuitive architecture-neutral API 8 | * Provide details on disassembled instruction (called "decomposer") 9 | * Provide some semantics of the disassembled instruction, such as list of 10 | implicit registers read & written. 11 | * Implemented in pure C language, with bindings for Python, Ruby, C#, Java, 12 | Javascript, GO, OCaml & Vala available. 13 | * Native support for Windows & *nix (including MacOSX, Linux, *BSD & Solaris) 14 | * Thread-safe by design 15 | * Distributed under the open source BSD license 16 | 17 | WWW: https://capstone-engine.org/ 18 | -------------------------------------------------------------------------------- /arch/MOS65XX/MOS65XXDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* MOS65XX Backend by Sebastian Macke 2018 */ 3 | 4 | #ifndef CAPSTONE_MOS65XXDISASSEMBLER_H 5 | #define CAPSTONE_MOS65XXDISASSEMBLER_H 6 | 7 | #include "../../utils.h" 8 | 9 | void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo); 10 | 11 | void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 12 | 13 | const char *MOS65XX_insn_name(csh handle, unsigned int id); 14 | 15 | const char *MOS65XX_group_name(csh handle, unsigned int id); 16 | 17 | const char* MOS65XX_reg_name(csh handle, unsigned int reg); 18 | 19 | bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len, 20 | MCInst *MI, uint16_t *size, uint64_t address, void *inst_info); 21 | 22 | #endif //CAPSTONE_MOS65XXDISASSEMBLER_H 23 | -------------------------------------------------------------------------------- /arch/Mips/MipsInstPrinter.h: -------------------------------------------------------------------------------- 1 | //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints a Mips MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2015 */ 16 | 17 | #ifndef CS_MIPSINSTPRINTER_H 18 | #define CS_MIPSINSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../SStream.h" 22 | 23 | void Mips_printInst(MCInst *MI, SStream *O, void *info); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-bitwise-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x1c,0x22,0x0e = and v0.8b, v1.8b, v2.8b 3 | 0x20,0x1c,0x22,0x4e = and v0.16b, v1.16b, v2.16b 4 | 0x20,0x1c,0xa2,0x0e = orr v0.8b, v1.8b, v2.8b 5 | 0x20,0x1c,0xa2,0x4e = orr v0.16b, v1.16b, v2.16b 6 | 0x20,0x1c,0x22,0x2e = eor v0.8b, v1.8b, v2.8b 7 | 0x20,0x1c,0x22,0x6e = eor v0.16b, v1.16b, v2.16b 8 | 0x20,0x1c,0xa2,0x2e = bit v0.8b, v1.8b, v2.8b 9 | 0x20,0x1c,0xa2,0x6e = bit v0.16b, v1.16b, v2.16b 10 | 0x20,0x1c,0xe2,0x2e = bif v0.8b, v1.8b, v2.8b 11 | 0x20,0x1c,0xe2,0x6e = bif v0.16b, v1.16b, v2.16b 12 | 0x20,0x1c,0x62,0x2e = bsl v0.8b, v1.8b, v2.8b 13 | 0x20,0x1c,0x62,0x6e = bsl v0.16b, v1.16b, v2.16b 14 | 0x20,0x1c,0xe2,0x0e = orn v0.8b, v1.8b, v2.8b 15 | 0x20,0x1c,0xe2,0x4e = orn v0.16b, v1.16b, v2.16b 16 | 0x20,0x1c,0x62,0x0e = bic v0.8b, v1.8b, v2.8b 17 | 0x20,0x1c,0x62,0x4e = bic v0.16b, v1.16b, v2.16b 18 | -------------------------------------------------------------------------------- /arch/TMS320C64x/TMS320C64xMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifndef CS_TMS320C64X_MAP_H 5 | #define CS_TMS320C64X_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *TMS320C64x_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *TMS320C64x_insn_name(csh handle, unsigned int id); 16 | 17 | const char *TMS320C64x_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | tms320c64x_reg TMS320C64x_map_register(unsigned int r); 21 | 22 | // map register name to register ID 23 | tms320c64x_reg TMS320C64x_reg_id(char *name); 24 | 25 | #endif 26 | 27 | -------------------------------------------------------------------------------- /suite/MC/Mips/micromips-expansions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa0,0x50,0x7b,0x00 = ori $a1, $zero, 123 3 | 0xc0,0x30,0xd7,0xf6 = addiu $a2, $zero, -2345 4 | 0xa7,0x41,0x01,0x00 = lui $a3, 1 5 | 0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 6 | 0x80,0x30,0x14,0x00 = addiu $a0, $zero, 20 7 | 0xa7,0x41,0x01,0x00 = lui $a3, 1 8 | 0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 9 | 0x85,0x30,0x14,0x00 = addiu $a0, $a1, 20 10 | 0xa7,0x41,0x01,0x00 = lui $a3, 1 11 | 0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 12 | 0x07,0x01,0x50,0x39 = addu $a3, $a3, $t0 13 | 0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 14 | 0x21,0x01,0x50,0x09 = addu $at, $at, $t1 15 | 0xaa,0x41,0x0a,0x00 = lui $t2, 10 16 | 0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 17 | 0x4a,0xfd,0x7b,0x00 = lw $t2, 123($t2) 18 | 0xa1,0x41,0x02,0x00 = lui $at, 2 19 | 0x21,0x01,0x50,0x09 = addu $at, $at, $t1 20 | // 0x41,0xf9,0x40,0xe2 = sw $t2, 57920($at) 21 | -------------------------------------------------------------------------------- /arch/MOS65XX/MOS65XXModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* MOS65XX Backend by Sebastian Macke 2018 */ 3 | 4 | #ifdef CAPSTONE_HAS_MOS65XX 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "MOS65XXDisassembler.h" 9 | #include "MOS65XXModule.h" 10 | 11 | cs_err MOS65XX_global_init(cs_struct *ud) 12 | { 13 | // verify if requested mode is valid 14 | if (ud->mode) 15 | return CS_ERR_MODE; 16 | 17 | ud->printer = MOS65XX_printInst; 18 | ud->printer_info = NULL; 19 | ud->insn_id = MOS65XX_get_insn_id; 20 | ud->insn_name = MOS65XX_insn_name; 21 | ud->group_name = MOS65XX_group_name; 22 | ud->disasm = MOS65XX_getInstruction; 23 | ud->reg_name = MOS65XX_reg_name; 24 | 25 | return CS_ERR_OK; 26 | } 27 | 28 | cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value) 29 | { 30 | return CS_ERR_OK; 31 | } 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /bindings/ocaml/README: -------------------------------------------------------------------------------- 1 | To compile Ocaml binding, Ocaml toolchain is needed. On Ubuntu Linux, 2 | you can install Ocaml with: 3 | 4 | $ sudo apt-get install ocaml-nox 5 | 6 | To compile Ocaml binding, simply run "make" on the command line. 7 | 8 | 9 | This directory also contains some test code to show how to use Capstone API. 10 | 11 | - test_basic.ml 12 | This code shows the most simple form of API where we only want to get basic 13 | information out of disassembled instruction, such as address, mnemonic and 14 | operand string. 15 | 16 | - test_detail.ml: 17 | This code shows how to access to architecture-neutral information in disassembled 18 | instructions, such as implicit registers read/written, or groups of instructions 19 | that this instruction belong to. 20 | 21 | - test_.ml 22 | These code show how to access architecture-specific information for each 23 | architecture. 24 | -------------------------------------------------------------------------------- /suite/MC/X86/avx512-encodings.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x62,0xa3,0x55,0x48,0x38,0xcd,0x01 = vinserti32x4 $1, %xmm21, %zmm5, %zmm17 3 | 0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01 = vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17 4 | 0x62,0x33,0x7d,0x48,0x39,0xc9,0x01 = vextracti32x4 $1, %zmm9, %xmm17 5 | 0x62,0x33,0xfd,0x48,0x3b,0xc9,0x01 = vextracti64x4 $1, %zmm9, %ymm17 6 | 0x62,0x73,0xfd,0x48,0x3b,0x4f,0x10,0x01 = vextracti64x4 $1, %zmm9, 512(%rdi) 7 | 0x62,0xb1,0x35,0x40,0x72,0xe1,0x02 = vpsrad $2, %zmm17, %zmm25 8 | // 0x62,0xf1,0x35,0x40,0x72,0x64,0xb7,0x08,0x02 = vpsrad $2, 512(%rdi, %rsi, 4), %zmm25 9 | 0x62,0x21,0x1d,0x48,0xe2,0xc9 = vpsrad %xmm17, %zmm12, %zmm25 10 | 0x62,0x61,0x1d,0x48,0xe2,0x4c,0xb7,0x20 = vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25 11 | 0x62,0xf2,0x7d,0xc9,0x58,0xc8 = vpbroadcastd %xmm0, %zmm1 {%k1} {z} 12 | 0x62,0xf1,0xfe,0x4b,0x6f,0xc8 = vmovdqu64 %zmm0, %zmm1 {%k3} 13 | -------------------------------------------------------------------------------- /suite/patch_major_os_version.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # By Daniel Pistelli & Nguyen Tan Cong 3 | 4 | # This script is to patch DLL/EXE MajorVersion to 5, 5 | # so they can be loaded by Windows XP. 6 | # This is the problem introduced by compiling on Windows 7, using VS2013. 7 | 8 | import sys, struct 9 | 10 | if len(sys.argv) < 2: 11 | print("Usage: %s " % sys.argv[0]) 12 | sys.exit(0) 13 | 14 | pe_file_path = sys.argv[1] 15 | 16 | with open(pe_file_path, "rb") as f: 17 | b = f.read() 18 | 19 | if not b.startswith("MZ"): 20 | print("Not a PE file") 21 | sys.exit(0) 22 | 23 | e_lfanew = struct.unpack_from(" 2 | 3 | 4 | 5 | CFBundleDevelopmentRegion 6 | en 7 | CFBundleExecutable 8 | $(EXECUTABLE_NAME) 9 | CFBundleIdentifier 10 | $(PRODUCT_BUNDLE_IDENTIFIER) 11 | CFBundleInfoDictionaryVersion 12 | 6.0 13 | CFBundleName 14 | $(PRODUCT_NAME) 15 | CFBundlePackageType 16 | FMWK 17 | CFBundleShortVersionString 18 | 1.0 19 | CFBundleSignature 20 | ???? 21 | CFBundleVersion 22 | $(CURRENT_PROJECT_VERSION) 23 | NSPrincipalClass 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-convert-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 3 | 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 4 | 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 5 | 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 6 | 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 7 | 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 8 | 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 9 | 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 10 | 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 11 | 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 12 | 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 13 | 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 14 | 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 15 | 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 16 | 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 17 | 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 18 | 0xf6,0xff,0x20,0x07 = vcvt.f32.f16 q8, d16 19 | 0xf6,0xff,0x20,0x06 = vcvt.f16.f32 d16, q8 20 | -------------------------------------------------------------------------------- /suite/cstest/include/helper.h: -------------------------------------------------------------------------------- 1 | /* Capstone testing regression */ 2 | /* By Do Minh Tuan , 02-2019 */ 3 | 4 | 5 | #ifndef HELPER_H 6 | #define HELPER_H 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include "capstone_test.h" 15 | 16 | #define X86_16 0 17 | #define X86_32 1 18 | #define X86_64 2 19 | 20 | char **split(char *str, char *delim, int *size); 21 | void print_strs(char **list_str, int size); 22 | void free_strs(char **list_str, int size); 23 | void add_str(char **src, const char *format, ...); 24 | void trim_str(char *src); 25 | void replace_hex(char *src); 26 | void replace_negative(char *src, int mode); 27 | const char *get_filename_ext(const char *filename); 28 | 29 | char *readfile(const char *filename); 30 | void listdir(const char *name, char ***files, int *num_files); 31 | 32 | #endif /* HELPER_H */ 33 | -------------------------------------------------------------------------------- /arch/X86/X86InstPrinter.h: -------------------------------------------------------------------------------- 1 | //= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an X86 MCInst to Intel style .s file syntax. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2015 */ 16 | 17 | #ifndef CS_X86_INSTPRINTER_H 18 | #define CS_X86_INSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../SStream.h" 22 | 23 | void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info); 24 | void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info); 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1] 3 | 0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2] 4 | 0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3] 5 | 0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7] 6 | 0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0] 7 | 0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3] 8 | 0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0] 9 | 0x20,0xc0,0x40,0x5f = sqdmulh h0, h1, v0.h[0] 10 | 0x6a,0xc9,0x4a,0x5f = sqdmulh h10, h11, v10.h[4] 11 | 0xb4,0xca,0x7f,0x5f = sqdmulh h20, h21, v15.h[7] 12 | 0x59,0xcb,0xbb,0x5f = sqdmulh s25, s26, v27.s[3] 13 | 0xc2,0xc0,0x87,0x5f = sqdmulh s2, s6, v7.s[0] 14 | 0xdf,0xd3,0x6e,0x5f = sqrdmulh h31, h30, v14.h[2] 15 | 0x21,0xd8,0x41,0x5f = sqrdmulh h1, h1, v1.h[4] 16 | 0xd5,0xda,0x7f,0x5f = sqrdmulh h21, h22, v15.h[7] 17 | 0xc5,0xd8,0x87,0x5f = sqrdmulh s5, s6, v7.s[2] 18 | 0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1] 19 | -------------------------------------------------------------------------------- /SStream.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SSTREAM_H_ 5 | #define CS_SSTREAM_H_ 6 | 7 | #include "include/capstone/platform.h" 8 | 9 | typedef struct SStream { 10 | char buffer[512]; 11 | int index; 12 | } SStream; 13 | 14 | void SStream_Init(SStream *ss); 15 | 16 | void SStream_concat(SStream *ss, const char *fmt, ...); 17 | 18 | void SStream_concat0(SStream *ss, const char *s); 19 | 20 | void printInt64Bang(SStream *O, int64_t val); 21 | 22 | void printUInt64Bang(SStream *O, uint64_t val); 23 | 24 | void printInt64(SStream *O, int64_t val); 25 | 26 | void printInt32Bang(SStream *O, int32_t val); 27 | 28 | void printInt32(SStream *O, int32_t val); 29 | 30 | void printUInt32Bang(SStream *O, uint32_t val); 31 | 32 | void printUInt32(SStream *O, uint32_t val); 33 | 34 | // print number in decimal mode 35 | void printInt32BangDec(SStream *O, int32_t val); 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /bindings/java/README: -------------------------------------------------------------------------------- 1 | This has been tested with OpenJDK version 6 & 7 on Ubuntu-12.04 and 2 | Arch Linux-3.11, 64-bit. 3 | 4 | - OpenJDK is required to compile and run this test code. 5 | For example, install OpenJDK 6 with: 6 | 7 | $ sudo apt-get install openjdk-6-jre-headless openjdk-6-jdk 8 | 9 | - Java Native Access is required to run the code, you can install it with: 10 | 11 | $ sudo apt-get install libjna-java 12 | 13 | - To compile and run this Java test code: 14 | 15 | $ make 16 | $ ./run.sh 17 | 18 | 19 | This directory contains some test code to show how to use Capstone API. 20 | 21 | - TestBasic.java 22 | This code shows the most simple form of API where we only want to get basic 23 | information out of disassembled instruction, such as address, mnemonic and 24 | operand string. 25 | 26 | - Test.java 27 | These code show how to retrieve architecture-specific information for each 28 | architecture. 29 | -------------------------------------------------------------------------------- /suite/MC/ARM/thumb-shift-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x6e,0xeb,0x00,0x0c = sbc.w r12, lr, r0 3 | 0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #32 4 | 0x67,0xeb,0x1f,0x42 = sbc.w r2, r7, pc, lsr #16 5 | 0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10 6 | 0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #16 7 | 0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #32 8 | 0x63,0xeb,0x2d,0x46 = sbc.w r6, r3, sp, asr #16 9 | 0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx 10 | 0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #16 11 | 0x0e,0xea,0x00,0x0c = and.w r12, lr, r0 12 | 0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #32 13 | 0x07,0xea,0x1f,0x42 = and.w r2, r7, pc, lsr #16 14 | 0x06,0xea,0x0a,0x03 = and.w r3, r6, r10 15 | 0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #16 16 | 0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #32 17 | 0x03,0xea,0x2d,0x46 = and.w r6, r3, sp, asr #16 18 | 0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx 19 | 0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #16 20 | -------------------------------------------------------------------------------- /bindings/java/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | JNA=/usr/share/java/jna.jar 3 | 4 | if [ ! -f ${JNA} ]; then 5 | if [ ! -f /usr/share/java/jna/jna.jar ]; then 6 | echo "*** Unable to find jna.jar *** "; 7 | exit; 8 | else 9 | JNA=/usr/share/java/jna/jna.jar; 10 | fi 11 | fi 12 | 13 | case "$1" in 14 | "") java -classpath ${JNA}:. TestBasic ;; 15 | "testbasic") java -classpath ${JNA}:. TestBasic ;; 16 | "arm") java -classpath ${JNA}:. TestArm ;; 17 | "arm64") java -classpath ${JNA}:. TestArm64 ;; 18 | "mips") java -classpath ${JNA}:. TestMips ;; 19 | "x86") java -classpath ${JNA}:. TestX86 ;; 20 | "xcore") java -classpath ${JNA}:. TestXcore; ;; 21 | "ppc") java -classpath ${JNA}:. TestPpc ;; 22 | "sparc") java -classpath ${JNA}:. TestSparc ;; 23 | "systemz") java -classpath ${JNA}:. TestSystemz ;; 24 | "m680x") java -classpath ${JNA}:. TestM680x ;; 25 | * ) echo "Usage: ./run.sh [arm|arm64|m680x|mips|ppc|sparc|systemz|x86]"; exit 1;; 26 | esac 27 | -------------------------------------------------------------------------------- /bindings/ocaml/x86.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open X86_const 5 | 6 | (* architecture specific info of instruction *) 7 | type x86_op_mem = { 8 | segment: int; 9 | base: int; 10 | index: int; 11 | scale: int; 12 | disp: int; 13 | } 14 | 15 | type x86_op_value = 16 | | X86_OP_INVALID of int 17 | | X86_OP_REG of int 18 | | X86_OP_IMM of int 19 | | X86_OP_MEM of x86_op_mem 20 | 21 | type x86_op = { 22 | value: x86_op_value; 23 | size: int; 24 | access: int; 25 | avx_bcast: int; 26 | avx_zero_opmask: int; 27 | } 28 | 29 | type cs_x86 = { 30 | prefix: int array; 31 | opcode: int array; 32 | rex: int; 33 | addr_size: int; 34 | modrm: int; 35 | sib: int; 36 | disp: int; 37 | sib_index: int; 38 | sib_scale: int; 39 | sib_base: int; 40 | xop_cc: int; 41 | sse_cc: int; 42 | avx_cc: int; 43 | avx_sae: int; 44 | avx_rm: int; 45 | eflags: int; 46 | operands: x86_op array; 47 | } 48 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-mla-mls-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x94,0x22,0x0e = mla v0.8b, v1.8b, v2.8b 3 | 0x20,0x94,0x22,0x4e = mla v0.16b, v1.16b, v2.16b 4 | 0x20,0x94,0x62,0x0e = mla v0.4h, v1.4h, v2.4h 5 | 0x20,0x94,0x62,0x4e = mla v0.8h, v1.8h, v2.8h 6 | 0x20,0x94,0xa2,0x0e = mla v0.2s, v1.2s, v2.2s 7 | 0x20,0x94,0xa2,0x4e = mla v0.4s, v1.4s, v2.4s 8 | 0x20,0x94,0x22,0x2e = mls v0.8b, v1.8b, v2.8b 9 | 0x20,0x94,0x22,0x6e = mls v0.16b, v1.16b, v2.16b 10 | 0x20,0x94,0x62,0x2e = mls v0.4h, v1.4h, v2.4h 11 | 0x20,0x94,0x62,0x6e = mls v0.8h, v1.8h, v2.8h 12 | 0x20,0x94,0xa2,0x2e = mls v0.2s, v1.2s, v2.2s 13 | 0x20,0x94,0xa2,0x6e = mls v0.4s, v1.4s, v2.4s 14 | 0x20,0xcc,0x22,0x0e = fmla v0.2s, v1.2s, v2.2s 15 | 0x20,0xcc,0x22,0x4e = fmla v0.4s, v1.4s, v2.4s 16 | 0x20,0xcc,0x62,0x4e = fmla v0.2d, v1.2d, v2.2d 17 | 0x20,0xcc,0xa2,0x0e = fmls v0.2s, v1.2s, v2.2s 18 | 0x20,0xcc,0xa2,0x4e = fmls v0.4s, v1.4s, v2.4s 19 | 0x20,0xcc,0xe2,0x4e = fmls v0.2d, v1.2d, v2.2d 20 | -------------------------------------------------------------------------------- /bindings/vb6/vbCapstone.sln: -------------------------------------------------------------------------------- 1 | 2 | Microsoft Visual Studio Solution File, Format Version 10.00 3 | # Visual Studio 2008 4 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "vbCapstone", "vbCapstone.vcproj", "{B693CA7B-8B91-4413-AAED-14F1947F012A}" 5 | EndProject 6 | Global 7 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 8 | Debug|Win32 = Debug|Win32 9 | Release|Win32 = Release|Win32 10 | EndGlobalSection 11 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 12 | {B693CA7B-8B91-4413-AAED-14F1947F012A}.Debug|Win32.ActiveCfg = Debug|Win32 13 | {B693CA7B-8B91-4413-AAED-14F1947F012A}.Debug|Win32.Build.0 = Debug|Win32 14 | {B693CA7B-8B91-4413-AAED-14F1947F012A}.Release|Win32.ActiveCfg = Release|Win32 15 | {B693CA7B-8B91-4413-AAED-14F1947F012A}.Release|Win32.Build.0 = Release|Win32 16 | EndGlobalSection 17 | GlobalSection(SolutionProperties) = preSolution 18 | HideSolutionNode = FALSE 19 | EndGlobalSection 20 | EndGlobal 21 | -------------------------------------------------------------------------------- /suite/MC/PowerPC/ppc64-encoding-bookII.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 2 | 0x7c,0x02,0x1f,0xac = icbi 2, 3 3 | 0x7c,0x02,0x1a,0x2c = dcbt 2, 3 4 | 0x7c,0x02,0x19,0xec = dcbtst 2, 3 5 | 0x7c,0x02,0x1f,0xec = dcbz 2, 3 6 | 0x7c,0x02,0x18,0x6c = dcbst 2, 3 7 | 0x4c,0x00,0x01,0x2c = isync 8 | 0x7c,0x43,0x21,0x2d = stwcx. 2, 3, 4 9 | 0x7c,0x43,0x21,0xad = stdcx. 2, 3, 4 10 | // 0x7c,0x40,0x04,0xac = sync 2 11 | 0x7c,0x00,0x06,0xac = eieio 12 | // 0x7c,0x40,0x00,0x7c = wait 2 13 | 0x7c,0x02,0x18,0xac = dcbf 2, 3 14 | 0x7c,0x43,0x20,0x28 = lwarx 2, 3, 4 15 | 0x7c,0x43,0x20,0xa8 = ldarx 2, 3, 4 16 | 0x7c,0x00,0x04,0xac = sync 0 17 | 0x7c,0x00,0x04,0xac = sync 0 18 | // 0x7c,0x20,0x04,0xac = sync 1 19 | // 0x7c,0x40,0x04,0xac = sync 2 20 | // 0x7c,0x00,0x00,0x7c = wait 0 21 | // 0x7c,0x20,0x00,0x7c = wait 1 22 | // 0x7c,0x40,0x00,0x7c = wait 2 23 | 0x7c,0x5b,0x1a,0xe6 = mftb 2, 123 24 | 0x7c,0x4c,0x42,0xe6 = mftb 2, 268 25 | // 0x7c,0x4d,0x42,0xe6 = mftb 2, 269 26 | -------------------------------------------------------------------------------- /suite/regress/regress.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import unittest 4 | 5 | from os.path import dirname, basename, isfile 6 | import glob 7 | 8 | # Find all unittest type in this directory and run it. 9 | 10 | class RegressTest(unittest.TestCase): 11 | pass 12 | 13 | def main(): 14 | unittest.main() 15 | 16 | if __name__ == '__main__': 17 | directory = dirname(__file__) 18 | if directory == '': 19 | directory = '.' 20 | modules = glob.glob(directory+"/*.py") 21 | __all__ = [ basename(f)[:-3] for f in modules if isfile(f)] 22 | suite = unittest.TestSuite() 23 | 24 | for module in __all__: 25 | m = __import__(module) 26 | for cl in dir(m): 27 | try: 28 | realcl = getattr(m,cl) 29 | if issubclass(realcl, unittest.TestCase): 30 | suite.addTest(realcl()) 31 | except Exception as e: 32 | pass 33 | 34 | unittest.TextTestRunner().run(suite) 35 | -------------------------------------------------------------------------------- /nmake.bat: -------------------------------------------------------------------------------- 1 | :: Capstone disassembler engine (www.capstone-engine.org) 2 | :: Build Capstone libs (capstone.dll & capstone.lib) on Windows with CMake & Nmake 3 | :: By Nguyen Anh Quynh, Jorn Vernee, 2017, 2019 4 | 5 | @echo off 6 | 7 | set flags="-DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_STATIC_RUNTIME=ON" 8 | 9 | if "%1"=="ARM" set %arch%=ARM 10 | if "%1"=="ARM64" set %arch%=ARM64 11 | if "%1"=="M68K" set %arch%=M68K 12 | if "%1"=="MIPS" set %arch%=MIPS 13 | if "%1"=="PowerPC" set %arch%=PPC 14 | if "%1"=="Sparc" set %arch%=SPARC 15 | if "%1"=="SystemZ" set %arch%=SYSZ 16 | if "%1"=="XCore" set %arch%=XCORE 17 | if "%1"=="x86" set %arch%=X86 18 | if "%1"=="TMS320C64x" set %arch%=TMS320C64X 19 | if "%1"=="M680x" set %arch%=M680X 20 | if "%1"=="EVM" set %arch%=EVM 21 | if "%1"=="MOS65XX" set %arch%=MOS65XX 22 | 23 | if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON" 24 | 25 | cmake %flags% -G "NMake Makefiles" .. 26 | nmake 27 | 28 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-fp-compare.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x6a,0xe5,0x2c,0x5e = fcmeq s10, s11, s12 3 | 0xb4,0xe6,0x76,0x5e = fcmeq d20, d21, d22 4 | 0x6a,0xd9,0xa0,0x5e = fcmeq s10, s11, #0.0 5 | 0xb4,0xda,0xe0,0x5e = fcmeq d20, d21, #0.0 6 | 0x6a,0xe5,0x2c,0x7e = fcmge s10, s11, s12 7 | 0xb4,0xe6,0x76,0x7e = fcmge d20, d21, d22 8 | 0x6a,0xc9,0xa0,0x7e = fcmge s10, s11, #0.0 9 | 0xb4,0xca,0xe0,0x7e = fcmge d20, d21, #0.0 10 | 0x6a,0xe5,0xac,0x7e = fcmgt s10, s11, s12 11 | 0xb4,0xe6,0xf6,0x7e = fcmgt d20, d21, d22 12 | 0x6a,0xc9,0xa0,0x5e = fcmgt s10, s11, #0.0 13 | 0xb4,0xca,0xe0,0x5e = fcmgt d20, d21, #0.0 14 | 0x6a,0xd9,0xa0,0x7e = fcmle s10, s11, #0.0 15 | 0xb4,0xda,0xe0,0x7e = fcmle d20, d21, #0.0 16 | 0x6a,0xe9,0xa0,0x5e = fcmlt s10, s11, #0.0 17 | 0xb4,0xea,0xe0,0x5e = fcmlt d20, d21, #0.0 18 | 0x6a,0xed,0x2c,0x7e = facge s10, s11, s12 19 | 0xb4,0xee,0x76,0x7e = facge d20, d21, d22 20 | 0x6a,0xed,0xac,0x7e = facgt s10, s11, s12 21 | 0xb4,0xee,0xf6,0x7e = facgt d20, d21, d22 22 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-dup.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x00,0x04,0x1f,0x5e = mov b0, v0.b[15] 3 | 0x01,0x04,0x0f,0x5e = mov b1, v0.b[7] 4 | 0x11,0x04,0x01,0x5e = mov b17, v0.b[0] 5 | 0xe5,0x07,0x1e,0x5e = mov h5, v31.h[7] 6 | 0x29,0x04,0x12,0x5e = mov h9, v1.h[4] 7 | 0x2b,0x06,0x02,0x5e = mov h11, v17.h[0] 8 | 0x42,0x04,0x1c,0x5e = mov s2, v2.s[3] 9 | 0xa4,0x06,0x04,0x5e = mov s4, v21.s[0] 10 | 0xbf,0x06,0x14,0x5e = mov s31, v21.s[2] 11 | 0xa3,0x04,0x08,0x5e = mov d3, v5.d[0] 12 | 0xa6,0x04,0x18,0x5e = mov d6, v5.d[1] 13 | 0x00,0x04,0x1f,0x5e = mov b0, v0.b[15] 14 | 0x01,0x04,0x0f,0x5e = mov b1, v0.b[7] 15 | 0x11,0x04,0x01,0x5e = mov b17, v0.b[0] 16 | 0xe5,0x07,0x1e,0x5e = mov h5, v31.h[7] 17 | 0x29,0x04,0x12,0x5e = mov h9, v1.h[4] 18 | 0x2b,0x06,0x02,0x5e = mov h11, v17.h[0] 19 | 0x42,0x04,0x1c,0x5e = mov s2, v2.s[3] 20 | 0xa4,0x06,0x04,0x5e = mov s4, v21.s[0] 21 | 0xbf,0x06,0x14,0x5e = mov s31, v21.s[2] 22 | 0xa3,0x04,0x08,0x5e = mov d3, v5.d[0] 23 | 0xa6,0x04,0x18,0x5e = mov d6, v5.d[1] 24 | -------------------------------------------------------------------------------- /contrib/windows_kernel/libc.h: -------------------------------------------------------------------------------- 1 | /** 2 | * @file libc.h 3 | * @author created by: Peter Hlavaty 4 | */ 5 | 6 | #pragma once 7 | 8 | #include 9 | 10 | EXTERN_C 11 | __drv_when(return!=0, __drv_allocatesMem(pBlock)) 12 | __checkReturn 13 | __drv_maxIRQL(DISPATCH_LEVEL) 14 | __bcount_opt(size) 15 | void* __cdecl malloc(__in size_t size); 16 | 17 | 18 | EXTERN_C 19 | __drv_when(return != 0, __drv_allocatesMem(p)) 20 | __checkReturn 21 | __drv_maxIRQL(DISPATCH_LEVEL) 22 | __bcount_opt(size * n) 23 | void* __cdecl calloc(size_t n, size_t size); 24 | 25 | 26 | EXTERN_C 27 | __drv_when(return!=0, __drv_allocatesMem(inblock)) 28 | __checkReturn 29 | __drv_maxIRQL(DISPATCH_LEVEL) 30 | __bcount_opt(size) 31 | void* __cdecl realloc(__in_opt void* ptr, __in size_t size); 32 | 33 | 34 | EXTERN_C 35 | __drv_maxIRQL(DISPATCH_LEVEL) 36 | void __cdecl free(__inout_opt __drv_freesMem(Mem) void* ptr); 37 | 38 | 39 | int __cdecl vsnprintf(char *buffer, size_t count, 40 | const char *format, va_list argptr); 41 | -------------------------------------------------------------------------------- /bindings/powershell/README.md: -------------------------------------------------------------------------------- 1 | This documentation explains how to install & use the PowerShell binding for Capstone. 2 | 3 | 4 | Install 5 | ------ 6 | 7 | Compile the relevant version (x86/x64) of `capstone.dll` and place it in 8 | `./Capstone/Lib/Capstone/`. 9 | 10 | Alternatively, pre-compiled DLL’s can be obtained from the Capstone homepage 11 | at https://capstone-engine.org/download 12 | 13 | 14 | Usage 15 | ----- 16 | 17 | To use the PowerShell binding, the entire Capstone folder should be added to 18 | one of the PowerShell module directories: 19 | 20 | # Global PSModulePath path 21 | %Windir%\System32\WindowsPowerShell\v1.0\Modules 22 | 23 | # User PSModulePath path 24 | %UserProfile%\Documents\WindowsPowerShell\Modules 25 | 26 | Once this is done the module can be initialized by typing “Import-Module Capstone” 27 | in a new PowerShell terminal. Further information on the usage of the binding 28 | can be obtained with the following command: 29 | 30 | Get-Help Get-CapstoneDisassembly -Full -------------------------------------------------------------------------------- /arch/AArch64/AArch64InstPrinter.h: -------------------------------------------------------------------------------- 1 | //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an AArch64 MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2015 */ 16 | 17 | #ifndef CS_LLVM_AARCH64INSTPRINTER_H 18 | #define CS_LLVM_AARCH64INSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../MCRegisterInfo.h" 22 | #include "../../SStream.h" 23 | 24 | void AArch64_printInst(MCInst *MI, SStream *O, void *); 25 | 26 | void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-sub-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 3 | 0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 4 | 0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 5 | 0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 6 | 0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 7 | 0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 8 | 0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 9 | 0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 10 | 0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 11 | 0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 12 | 0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 13 | 0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 14 | 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 15 | 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 16 | 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 17 | 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 18 | 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 19 | 0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 20 | 0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 21 | 0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 22 | 0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 23 | 0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 24 | -------------------------------------------------------------------------------- /arch/M68K/M68KModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M68K Backend by Daniel Collin 2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_M68K 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "M68KDisassembler.h" 9 | #include "M68KInstPrinter.h" 10 | #include "M68KModule.h" 11 | 12 | cs_err M68K_global_init(cs_struct *ud) 13 | { 14 | m68k_info *info; 15 | 16 | info = cs_mem_malloc(sizeof(m68k_info)); 17 | if (!info) { 18 | return CS_ERR_MEM; 19 | } 20 | 21 | ud->printer = M68K_printInst; 22 | ud->printer_info = info; 23 | ud->getinsn_info = NULL; 24 | ud->disasm = M68K_getInstruction; 25 | ud->skipdata_size = 2; 26 | ud->post_printer = NULL; 27 | 28 | ud->reg_name = M68K_reg_name; 29 | ud->insn_id = M68K_get_insn_id; 30 | ud->insn_name = M68K_insn_name; 31 | ud->group_name = M68K_group_name; 32 | 33 | return CS_ERR_OK; 34 | } 35 | 36 | cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value) 37 | { 38 | return CS_ERR_OK; 39 | } 40 | 41 | #endif 42 | 43 | -------------------------------------------------------------------------------- /suite/MC/ARM/neont2-shuffle-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 3 | 0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 4 | 0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 5 | 0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 6 | 0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 7 | 0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 8 | 0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 9 | 0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 10 | 0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 11 | 0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 12 | 0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 13 | 0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 14 | 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 15 | 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 16 | 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 17 | 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 18 | 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 19 | 0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 20 | 0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 21 | 0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 22 | 0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 23 | 0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 24 | -------------------------------------------------------------------------------- /bindings/ocaml/arm64.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open Arm64_const 5 | 6 | (* architecture specific info of instruction *) 7 | type arm64_op_shift = { 8 | shift_type: int; 9 | shift_value: int; 10 | } 11 | 12 | type arm64_op_mem = { 13 | base: int; 14 | index: int; 15 | disp: int 16 | } 17 | 18 | type arm64_op_value = 19 | | ARM64_OP_INVALID of int 20 | | ARM64_OP_REG of int 21 | | ARM64_OP_CIMM of int 22 | | ARM64_OP_IMM of int 23 | | ARM64_OP_FP of float 24 | | ARM64_OP_MEM of arm64_op_mem 25 | | ARM64_OP_REG_MRS of int 26 | | ARM64_OP_REG_MSR of int 27 | | ARM64_OP_PSTATE of int 28 | | ARM64_OP_SYS of int 29 | | ARM64_OP_PREFETCH of int 30 | | ARM64_OP_BARRIER of int 31 | 32 | type arm64_op = { 33 | vector_index: int; 34 | vas: int; 35 | vess: int; 36 | shift: arm64_op_shift; 37 | ext: int; 38 | value: arm64_op_value; 39 | } 40 | 41 | type cs_arm64 = { 42 | cc: int; 43 | update_flags: bool; 44 | writeback: bool; 45 | operands: arm64_op array; 46 | } 47 | -------------------------------------------------------------------------------- /bindings/ocaml/m680x.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * M680X Backend by Wolfgang Schwotzer 2017 *) 3 | 4 | open M680x_const 5 | 6 | 7 | (* architecture specific info of instruction *) 8 | type m680x_op_idx = { 9 | base_reg: int; 10 | offset_reg: int; 11 | offset: int; 12 | offset_addr: int; 13 | offset_bits: int; 14 | inc_dec: int; 15 | flags: int; 16 | } 17 | 18 | type m680x_op_rel = { 19 | addr_rel: int; 20 | offset: int; 21 | } 22 | 23 | type m680x_op_ext = { 24 | addr_ext: int; 25 | indirect: bool; 26 | } 27 | 28 | type m680x_op_value = 29 | | M680X_OP_INVALID of int 30 | | M680X_OP_IMMEDIATE of int 31 | | M680X_OP_REGISTER of int 32 | | M680X_OP_INDEXED of m680x_op_idx 33 | | M680X_OP_RELATIVE of m680x_op_rel 34 | | M680X_OP_EXTENDED of m680x_op_ext 35 | | M680X_OP_DIRECT of int 36 | | M680X_OP_CONSTANT of int 37 | 38 | type m680x_op = { 39 | value: m680x_op_value; 40 | size: int; 41 | access: int; 42 | } 43 | 44 | type cs_m680x = { 45 | flags: int; 46 | operands: m680x_op array; 47 | } 48 | 49 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-add-sub-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x84,0x22,0x0e = add v0.8b, v1.8b, v2.8b 3 | 0x20,0x84,0x22,0x4e = add v0.16b, v1.16b, v2.16b 4 | 0x20,0x84,0x62,0x0e = add v0.4h, v1.4h, v2.4h 5 | 0x20,0x84,0x62,0x4e = add v0.8h, v1.8h, v2.8h 6 | 0x20,0x84,0xa2,0x0e = add v0.2s, v1.2s, v2.2s 7 | 0x20,0x84,0xa2,0x4e = add v0.4s, v1.4s, v2.4s 8 | 0x20,0x84,0xe2,0x4e = add v0.2d, v1.2d, v2.2d 9 | 0x20,0x84,0x22,0x2e = sub v0.8b, v1.8b, v2.8b 10 | 0x20,0x84,0x22,0x6e = sub v0.16b, v1.16b, v2.16b 11 | 0x20,0x84,0x62,0x2e = sub v0.4h, v1.4h, v2.4h 12 | 0x20,0x84,0x62,0x6e = sub v0.8h, v1.8h, v2.8h 13 | 0x20,0x84,0xa2,0x2e = sub v0.2s, v1.2s, v2.2s 14 | 0x20,0x84,0xa2,0x6e = sub v0.4s, v1.4s, v2.4s 15 | 0x20,0x84,0xe2,0x6e = sub v0.2d, v1.2d, v2.2d 16 | 0x20,0xd4,0x22,0x0e = fadd v0.2s, v1.2s, v2.2s 17 | 0x20,0xd4,0x22,0x4e = fadd v0.4s, v1.4s, v2.4s 18 | 0x20,0xd4,0x62,0x4e = fadd v0.2d, v1.2d, v2.2d 19 | 0x20,0xd4,0xa2,0x0e = fsub v0.2s, v1.2s, v2.2s 20 | 0x20,0xd4,0xa2,0x4e = fsub v0.4s, v1.4s, v2.4s 21 | 0x20,0xd4,0xe2,0x4e = fsub v0.2d, v1.2d, v2.2d 22 | -------------------------------------------------------------------------------- /arch/Sparc/SparcMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_SPARC_MAP_H 5 | #define CS_SPARC_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *Sparc_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *Sparc_insn_name(csh handle, unsigned int id); 16 | 17 | const char *Sparc_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | sparc_reg Sparc_map_register(unsigned int r); 21 | 22 | // map instruction name to instruction ID (public) 23 | // this is for alias instructions only 24 | sparc_reg Sparc_map_insn(const char *name); 25 | 26 | // map CC string to CC id 27 | sparc_cc Sparc_map_ICC(const char *name); 28 | 29 | sparc_cc Sparc_map_FCC(const char *name); 30 | 31 | sparc_hint Sparc_map_hint(const char *name); 32 | 33 | #endif 34 | 35 | -------------------------------------------------------------------------------- /suite/MC/ARM/arm_instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x1e,0xff,0x2f,0xe1 = bx lr 3 | 0xa0,0x0d,0xe1,0xf2 = vqdmull.s32 q8, d17, d16 4 | 0x03,0x10,0x02,0xe0 = and r1, r2, r3 5 | 0x03,0x10,0x12,0xe0 = ands r1, r2, r3 6 | 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 7 | 0x03,0x10,0x32,0xe0 = eors r1, r2, r3 8 | 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 9 | 0x03,0x10,0x52,0xe0 = subs r1, r2, r3 10 | 0x03,0x10,0x82,0xe0 = add r1, r2, r3 11 | 0x03,0x10,0x92,0xe0 = adds r1, r2, r3 12 | 0x03,0x10,0xa2,0xe0 = adc r1, r2, r3 13 | 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 14 | 0x03,0x10,0xd2,0xe1 = bics r1, r2, r3 15 | 0x02,0x10,0xa0,0xe1 = mov r1, r2 16 | 0x02,0x10,0xe0,0xe1 = mvn r1, r2 17 | 0x02,0x10,0xf0,0xe1 = mvns r1, r2 18 | 0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7 19 | 0x7a,0x00,0x20,0xe1 = bkpt #10 20 | 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4 21 | 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4 22 | 0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4 23 | 0x30,0x0f,0xa6,0xe6 = ssat16 r0, #7, r0 24 | 0x00,0x00,0x0a,0xf1 = cpsie none, #0 25 | 0xb0,0x30,0x42,0xe1 = strh r3, [r2, #-0] 26 | -------------------------------------------------------------------------------- /arch/PowerPC/PPCMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_PPC_MAP_H 5 | #define CS_PPC_MAP_H 6 | 7 | #include "capstone/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *PPC_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *PPC_insn_name(csh handle, unsigned int id); 16 | const char *PPC_group_name(csh handle, unsigned int id); 17 | 18 | // map internal raw register to 'public' register 19 | ppc_reg PPC_map_register(unsigned int r); 20 | 21 | struct ppc_alias { 22 | unsigned int id; // instruction id 23 | int cc; // code condition 24 | const char *mnem; 25 | }; 26 | 27 | // given alias mnemonic, return instruction ID & CC 28 | bool PPC_alias_insn(const char *name, struct ppc_alias *alias); 29 | 30 | // check if this insn is relative branch 31 | bool PPC_abs_branch(cs_struct *h, unsigned int id); 32 | 33 | #endif 34 | 35 | -------------------------------------------------------------------------------- /bindings/vb6/CX86OpMem.cls: -------------------------------------------------------------------------------- 1 | VERSION 1.0 CLASS 2 | BEGIN 3 | MultiUse = -1 'True 4 | Persistable = 0 'NotPersistable 5 | DataBindingBehavior = 0 'vbNone 6 | DataSourceBehavior = 0 'vbNone 7 | MTSTransactionMode = 0 'NotAnMTSObject 8 | END 9 | Attribute VB_Name = "CX86OpMem" 10 | Attribute VB_GlobalNameSpace = False 11 | Attribute VB_Creatable = True 12 | Attribute VB_PredeclaredId = False 13 | Attribute VB_Exposed = False 14 | Option Explicit 15 | 16 | 'Capstone Disassembly Engine bindings for VB6 17 | 'Contributed by FireEye FLARE Team 18 | 'Author: David Zimmer , 19 | 'License: Apache 20 | 'Copyright: FireEye 2017 21 | 22 | 23 | Public segment As Long ' segment register (or X86_REG_INVALID if irrelevant) UNSIGNED 24 | Public base As Long ' base register (or X86_REG_INVALID if irrelevant) UNSIGNED 25 | Public index As Long ' index register (or X86_REG_INVALID if irrelevant) UNSIGNED 26 | Public scale_ As Long ' scale for index register 27 | Public disp As Currency ' displacement value 28 | 29 | -------------------------------------------------------------------------------- /cstool/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for Cstool of Capstone Disassembly Engine 2 | 3 | include ../functions.mk 4 | 5 | .PHONY: clean all 6 | 7 | LIBNAME = capstone 8 | 9 | CFLAGS += -I../include -I. 10 | LDFLAGS += -O3 -Wall -L.. -l$(LIBNAME) 11 | 12 | TARGET = cstool 13 | SOURCES := $(wildcard *.c) 14 | OBJECTS := $(SOURCES:.c=.o) 15 | 16 | LIBCAPSTONE = libcapstone.a 17 | 18 | IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l) 19 | ifeq ($(IS_CYGWIN),1) 20 | LIBCAPSTONE = capstone.lib 21 | else 22 | IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) 23 | ifeq ($(IS_MINGW),1) 24 | LIBCAPSTONE = capstone.lib 25 | endif 26 | endif 27 | 28 | all: $(TARGET) 29 | 30 | $(TARGET): ../$(LIBCAPSTONE) $(OBJECTS) 31 | ifeq ($(V),0) 32 | $(call log,LINK,$@) 33 | @${CC} $(OBJECTS) $(LDFLAGS) -o $@ 34 | else 35 | ${CC} $(OBJECTS) $(LDFLAGS) -o $@ 36 | endif 37 | 38 | clean: 39 | ${RM} -rf *.o $(TARGET) 40 | 41 | %.o: %.c 42 | ifeq ($(V),0) 43 | $(call log,CC,$@) 44 | @${CC} $(CFLAGS) -c $< -o $@ 45 | else 46 | ${CC} $(CFLAGS) -c $< -o $@ 47 | endif 48 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x44,0x22,0x0e = sshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x44,0x22,0x4e = sshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x44,0x62,0x0e = sshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x44,0x62,0x4e = sshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x44,0xa2,0x0e = sshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x44,0xa2,0x4e = sshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x44,0xe2,0x4e = sshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x44,0x22,0x2e = ushl v0.8b, v1.8b, v2.8b 10 | 0x20,0x44,0x22,0x6e = ushl v0.16b, v1.16b, v2.16b 11 | 0x20,0x44,0x62,0x2e = ushl v0.4h, v1.4h, v2.4h 12 | 0x20,0x44,0x62,0x6e = ushl v0.8h, v1.8h, v2.8h 13 | 0x20,0x44,0xa2,0x2e = ushl v0.2s, v1.2s, v2.2s 14 | 0x20,0x44,0xa2,0x6e = ushl v0.4s, v1.4s, v2.4s 15 | 0x20,0x44,0xe2,0x6e = ushl v0.2d, v1.2d, v2.2d 16 | 0x20,0x54,0x0b,0x0f = shl v0.8b, v1.8b, #3 17 | 0x20,0x54,0x13,0x0f = shl v0.4h, v1.4h, #3 18 | 0x20,0x54,0x23,0x0f = shl v0.2s, v1.2s, #3 19 | 0x20,0x54,0x0b,0x4f = shl v0.16b, v1.16b, #3 20 | 0x20,0x54,0x13,0x4f = shl v0.8h, v1.8h, #3 21 | 0x20,0x54,0x23,0x4f = shl v0.4s, v1.4s, #3 22 | 0x20,0x54,0x43,0x4f = shl v0.2d, v1.2d, #3 23 | -------------------------------------------------------------------------------- /arch/TMS320C64x/TMS320C64xModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* TMS320C64x Backend by Fotis Loukos 2016 */ 3 | 4 | #ifdef CAPSTONE_HAS_TMS320C64X 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "TMS320C64xDisassembler.h" 9 | #include "TMS320C64xInstPrinter.h" 10 | #include "TMS320C64xMapping.h" 11 | #include "TMS320C64xModule.h" 12 | 13 | cs_err TMS320C64x_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | 17 | mri = cs_mem_malloc(sizeof(*mri)); 18 | 19 | TMS320C64x_init(mri); 20 | ud->printer = TMS320C64x_printInst; 21 | ud->printer_info = mri; 22 | ud->getinsn_info = mri; 23 | ud->disasm = TMS320C64x_getInstruction; 24 | ud->post_printer = TMS320C64x_post_printer; 25 | 26 | ud->reg_name = TMS320C64x_reg_name; 27 | ud->insn_id = TMS320C64x_get_insn_id; 28 | ud->insn_name = TMS320C64x_insn_name; 29 | ud->group_name = TMS320C64x_group_name; 30 | 31 | return CS_ERR_OK; 32 | } 33 | 34 | cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value) 35 | { 36 | return CS_ERR_OK; 37 | } 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /arch/ARM/ARMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifndef CS_ARM_MAP_H 5 | #define CS_ARM_MAP_H 6 | 7 | #include "../../include/capstone/capstone.h" 8 | #include "../../utils.h" 9 | 10 | // return name of regiser in friendly string 11 | const char *ARM_reg_name(csh handle, unsigned int reg); 12 | const char *ARM_reg_name2(csh handle, unsigned int reg); 13 | 14 | // given internal insn id, return public instruction ID 15 | void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 16 | 17 | const char *ARM_insn_name(csh handle, unsigned int id); 18 | 19 | const char *ARM_group_name(csh handle, unsigned int id); 20 | 21 | // check if this insn is relative branch 22 | bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); 23 | 24 | bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); 25 | 26 | uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); 27 | 28 | void ARM_reg_access(const cs_insn *insn, 29 | cs_regs regs_read, uint8_t *regs_read_count, 30 | cs_regs regs_write, uint8_t *regs_write_count); 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x0c,0x22,0x5e = sqadd b0, b1, b2 3 | 0x6a,0x0d,0x6c,0x5e = sqadd h10, h11, h12 4 | 0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2 5 | 0xf1,0x0f,0xe8,0x5e = sqadd d17, d31, d8 6 | 0x20,0x0c,0x22,0x7e = uqadd b0, b1, b2 7 | 0x6a,0x0d,0x6c,0x7e = uqadd h10, h11, h12 8 | 0xb4,0x0e,0xa2,0x7e = uqadd s20, s21, s2 9 | 0xf1,0x0f,0xe8,0x7e = uqadd d17, d31, d8 10 | 0x20,0x2c,0x22,0x5e = sqsub b0, b1, b2 11 | 0x6a,0x2d,0x6c,0x5e = sqsub h10, h11, h12 12 | 0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2 13 | 0xf1,0x2f,0xe8,0x5e = sqsub d17, d31, d8 14 | 0x20,0x2c,0x22,0x7e = uqsub b0, b1, b2 15 | 0x6a,0x2d,0x6c,0x7e = uqsub h10, h11, h12 16 | 0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2 17 | 0xf1,0x2f,0xe8,0x7e = uqsub d17, d31, d8 18 | 0xd3,0x39,0x20,0x5e = suqadd b19, b14 19 | 0xf4,0x39,0x60,0x5e = suqadd h20, h15 20 | 0x95,0x39,0xa0,0x5e = suqadd s21, s12 21 | 0xd2,0x3a,0xe0,0x5e = suqadd d18, d22 22 | 0xd3,0x39,0x20,0x7e = usqadd b19, b14 23 | 0xf4,0x39,0x60,0x7e = usqadd h20, h15 24 | 0x95,0x39,0xa0,0x7e = usqadd s21, s12 25 | 0xd2,0x3a,0xe0,0x7e = usqadd d18, d22 26 | -------------------------------------------------------------------------------- /suite/MC/Sparc/sparc-mem-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xd4,0x4e,0x00,0x16 = ldsb [%i0+%l6], %o2 3 | 0xd4,0x4e,0x20,0x20 = ldsb [%i0+32], %o2 4 | 0xd8,0x48,0x60,0x00 = ldsb [%g1], %o4 5 | 0xd4,0x56,0x00,0x16 = ldsh [%i0+%l6], %o2 6 | 0xd4,0x56,0x20,0x20 = ldsh [%i0+32], %o2 7 | 0xd8,0x50,0x60,0x00 = ldsh [%g1], %o4 8 | 0xd4,0x0e,0x00,0x16 = ldub [%i0+%l6], %o2 9 | 0xd4,0x0e,0x20,0x20 = ldub [%i0+32], %o2 10 | 0xd4,0x08,0x60,0x00 = ldub [%g1], %o2 11 | 0xd4,0x16,0x00,0x16 = lduh [%i0+%l6], %o2 12 | 0xd4,0x16,0x20,0x20 = lduh [%i0+32], %o2 13 | 0xd4,0x10,0x60,0x00 = lduh [%g1], %o2 14 | 0xd4,0x06,0x00,0x16 = ld [%i0+%l6], %o2 15 | 0xd4,0x06,0x20,0x20 = ld [%i0+32], %o2 16 | 0xd4,0x00,0x60,0x00 = ld [%g1], %o2 17 | 0xd4,0x2e,0x00,0x16 = stb %o2, [%i0+%l6] 18 | 0xd4,0x2e,0x20,0x20 = stb %o2, [%i0+32] 19 | 0xd4,0x28,0x60,0x00 = stb %o2, [%g1] 20 | 0xd4,0x36,0x00,0x16 = sth %o2, [%i0+%l6] 21 | 0xd4,0x36,0x20,0x20 = sth %o2, [%i0+32] 22 | 0xd4,0x30,0x60,0x00 = sth %o2, [%g1] 23 | 0xd4,0x26,0x00,0x16 = st %o2, [%i0+%l6] 24 | 0xd4,0x26,0x20,0x20 = st %o2, [%i0+32] 25 | 0xd4,0x20,0x60,0x00 = st %o2, [%g1] 26 | -------------------------------------------------------------------------------- /suite/MC/X86/intel-syntax-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, None 2 | 0x66,0x83,0xf0,0x0c = xor ax, 12 3 | 0x83,0xf0,0x0c = xor eax, 12 4 | 0x48,0x83,0xf0,0x0c = xor rax, 12 5 | 0x66,0x83,0xc8,0x0c = or ax, 12 6 | 0x83,0xc8,0x0c = or eax, 12 7 | 0x48,0x83,0xc8,0x0c = or rax, 12 8 | 0x66,0x83,0xf8,0x0c = cmp ax, 12 9 | 0x83,0xf8,0x0c = cmp eax, 12 10 | 0x48,0x83,0xf8,0x0c = cmp rax, 12 11 | 0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX 12 | 0x66,0x83,0xc0,0xf4 = add ax, -12 13 | 0x83,0xc0,0xf4 = add eax, -12 14 | 0x48,0x83,0xc0,0xf4 = add rax, -12 15 | 0x66,0x83,0xd0,0xf4 = adc ax, -12 16 | 0x83,0xd0,0xf4 = adc eax, -12 17 | 0x48,0x83,0xd0,0xf4 = adc rax, -12 18 | 0x66,0x83,0xd8,0xf4 = sbb ax, -12 19 | 0x83,0xd8,0xf4 = sbb eax, -12 20 | 0x48,0x83,0xd8,0xf4 = sbb rax, -12 21 | 0x66,0x83,0xf8,0xf4 = cmp ax, -12 22 | 0x83,0xf8,0xf4 = cmp eax, -12 23 | 0x48,0x83,0xf8,0xf4 = cmp rax, -12 24 | 0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff = movsd XMM5, QWORD PTR [-8] 25 | 0xd1,0xe7 = shl EDI, 1 26 | 0x0f,0xc2,0xd1,0x01 = cmpltps XMM2, XMM1 27 | 0xc3 = ret 28 | 0xcb = retf 29 | 0xc2,0x08,0x00 = ret 8 30 | 0xca,0x08,0x00 = retf 8 31 | -------------------------------------------------------------------------------- /suite/MC/Mips/test_mi10.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x7a,0x00,0x08,0x20 = ld.b $w0, -512($at) 3 | 0x78,0x00,0x10,0x60 = ld.b $w1, ($v0) 4 | 0x79,0xff,0x18,0xa0 = ld.b $w2, 511($v1) 5 | 0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($a0) 6 | 0x7b,0x00,0x29,0x21 = ld.h $w4, -512($a1) 7 | 0x78,0x00,0x31,0x61 = ld.h $w5, ($a2) 8 | 0x79,0x00,0x39,0xa1 = ld.h $w6, 512($a3) 9 | 0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($t0) 10 | 0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($t1) 11 | 0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($t2) 12 | 0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($t3) 13 | 0x78,0x80,0x62,0xe2 = ld.w $w11, 512($t4) 14 | 0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($t5) 15 | 0x79,0xff,0x73,0x62 = ld.w $w13, 2044($t6) 16 | 0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($t7) 17 | 0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($s0) 18 | 0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($s1) 19 | 0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($s2) 20 | 0x78,0x00,0x9c,0xa3 = ld.d $w18, ($s3) 21 | 0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($s4) 22 | 0x78,0x80,0xad,0x23 = ld.d $w20, 1024($s5) 23 | 0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($s6) 24 | 0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($s7) 25 | -------------------------------------------------------------------------------- /arch/XCore/XCoreModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_XCORE 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "XCoreDisassembler.h" 9 | #include "XCoreInstPrinter.h" 10 | #include "XCoreMapping.h" 11 | #include "XCoreModule.h" 12 | 13 | cs_err XCore_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | XCore_init(mri); 19 | ud->printer = XCore_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = XCore_getInstruction; 23 | ud->post_printer = XCore_post_printer; 24 | 25 | ud->reg_name = XCore_reg_name; 26 | ud->insn_id = XCore_get_insn_id; 27 | ud->insn_name = XCore_insn_name; 28 | ud->group_name = XCore_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot 36 | // test for CS_MODE_LITTLE_ENDIAN because it is 0 37 | 38 | return CS_ERR_OK; 39 | } 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /arch/PowerPC/PPCModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_POWERPC 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "PPCDisassembler.h" 9 | #include "PPCInstPrinter.h" 10 | #include "PPCMapping.h" 11 | #include "PPCModule.h" 12 | 13 | cs_err PPC_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri)); 17 | 18 | PPC_init(mri); 19 | ud->printer = PPC_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = PPC_getInstruction; 23 | ud->post_printer = PPC_post_printer; 24 | 25 | ud->reg_name = PPC_reg_name; 26 | ud->insn_id = PPC_get_insn_id; 27 | ud->insn_name = PPC_insn_name; 28 | ud->group_name = PPC_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | if (type == CS_OPT_MODE) { 39 | handle->mode = (cs_mode)value; 40 | } 41 | 42 | return CS_ERR_OK; 43 | } 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /suite/cstest/include/factory.h: -------------------------------------------------------------------------------- 1 | /* Capstone testing regression */ 2 | /* By Do Minh Tuan , 02-2019 */ 3 | 4 | 5 | #ifndef FACTORY_H 6 | #define FACTORY_H 7 | 8 | #include 9 | #include "helper.h" 10 | 11 | char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins); 12 | char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins); 13 | char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins); 14 | char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *ins); 15 | char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins); 16 | char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins); 17 | char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins); 18 | char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins); 19 | char *get_detail_x86(csh *handle, cs_mode mode, cs_insn *ins); 20 | char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins); 21 | char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins); 22 | char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins); 23 | char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); 24 | 25 | #endif /* FACTORY_H */ 26 | -------------------------------------------------------------------------------- /arch/Sparc/SparcModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_SPARC 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "SparcDisassembler.h" 9 | #include "SparcInstPrinter.h" 10 | #include "SparcMapping.h" 11 | #include "SparcModule.h" 12 | 13 | cs_err Sparc_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | Sparc_init(mri); 19 | ud->printer = Sparc_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = Sparc_getInstruction; 23 | ud->post_printer = Sparc_post_printer; 24 | 25 | ud->reg_name = Sparc_reg_name; 26 | ud->insn_id = Sparc_get_insn_id; 27 | ud->insn_name = Sparc_insn_name; 28 | ud->group_name = Sparc_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | if (type == CS_OPT_MODE) { 39 | handle->mode = (cs_mode)value; 40 | } 41 | 42 | return CS_ERR_OK; 43 | } 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /arch/Sparc/SparcGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, https://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2015 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | Sparc_FeatureHardQuad = 1ULL << 0, 18 | Sparc_FeatureV8Deprecated = 1ULL << 1, 19 | Sparc_FeatureV9 = 1ULL << 2, 20 | Sparc_FeatureVIS = 1ULL << 3, 21 | Sparc_FeatureVIS2 = 1ULL << 4, 22 | Sparc_FeatureVIS3 = 1ULL << 5, 23 | Sparc_UsePopc = 1ULL << 6 24 | }; 25 | 26 | #endif // GET_SUBTARGETINFO_ENUM 27 | 28 | -------------------------------------------------------------------------------- /bindings/python/capstone/mos65xx.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .mos65xx_const import * 6 | 7 | # define the API 8 | class MOS65xxOpValue(ctypes.Union): 9 | _fields_ = ( 10 | ('reg', ctypes.c_uint), 11 | ('imm', ctypes.c_uint8), 12 | ('mem', ctypes.c_uint16), 13 | ) 14 | 15 | class MOS65xxOp(ctypes.Structure): 16 | _fields_ = ( 17 | ('type', ctypes.c_uint), 18 | ('value', MOS65xxOpValue), 19 | ) 20 | 21 | @property 22 | def imm(self): 23 | return self.value.imm 24 | 25 | @property 26 | def reg(self): 27 | return self.value.reg 28 | 29 | @property 30 | def mem(self): 31 | return self.value.mem 32 | 33 | 34 | class CsMOS65xx(ctypes.Structure): 35 | _fields_ = ( 36 | ('am', ctypes.c_uint), 37 | ('modifies_flags', ctypes.c_uint8), 38 | ('op_count', ctypes.c_uint8), 39 | ('operands', MOS65xxOp * 3), 40 | ) 41 | 42 | def get_arch_info(a): 43 | return (a.am, a.modifies_flags, copy_ctypes_list(a.operands[:a.op_count])) 44 | 45 | 46 | -------------------------------------------------------------------------------- /suite/README: -------------------------------------------------------------------------------- 1 | This directory contains some tools used by developers of Capstone project. 2 | Average users should ignore all the contents here. 3 | 4 | 5 | - arm/ 6 | Test some ARM's special input. 7 | 8 | - MC/ 9 | Input used to test various architectures & modes. 10 | 11 | - benchmark.py 12 | This script benchmarks Python binding by disassembling some random code. 13 | 14 | - test_*.sh 15 | Run all the tests and send the output to external file to be compared later. 16 | This is useful when we want to verify if a commit (wrongly) changes 17 | the disassemble result. 18 | 19 | - compile_all.sh 20 | Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) & 21 | report the result as pass or fail. 22 | 23 | - fuzz.py 24 | This simple script disassembles random code for all archs (or selected arch) 25 | in order to find segfaults. 26 | 27 | - test_mc.sh 28 | This script compares the output of Capstone with LLVM's llvm-mc with the 29 | input coming from MC/. This relies on test_mc.py to do all the hard works. 30 | 31 | - x86odd.py 32 | Test some tricky X86 instructions. 33 | 34 | - ppcbranch.py 35 | Test some tricky branch PPC instructions. 36 | -------------------------------------------------------------------------------- /bindings/python/test_customized_mnem.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # Capstone Python bindings, by Nguyen Anh Quynnh 4 | 5 | from __future__ import print_function 6 | from capstone import * 7 | from capstone.x86 import * 8 | from xprint import to_hex 9 | 10 | 11 | X86_CODE32 = b"\x75\x01" 12 | 13 | 14 | def print_insn(md, code): 15 | print("%s\t" % to_hex(code, False), end="") 16 | 17 | for insn in md.disasm(code, 0x1000): 18 | print("\t%s\t%s\n" % (insn.mnemonic, insn.op_str)) 19 | 20 | 21 | def test(): 22 | try: 23 | md = Cs(CS_ARCH_X86, CS_MODE_32) 24 | 25 | print("Disassemble X86 code with default instruction mnemonic") 26 | print_insn(md, X86_CODE32) 27 | 28 | print("Now customize engine to change mnemonic from 'JNE' to 'JNZ'") 29 | md.mnemonic_setup(X86_INS_JNE, "jnz") 30 | print_insn(md, X86_CODE32) 31 | 32 | print("Reset engine to use the default mnemonic") 33 | md.mnemonic_setup(X86_INS_JNE, None) 34 | print_insn(md, X86_CODE32) 35 | except CsError as e: 36 | print("ERROR: %s" % e) 37 | 38 | 39 | if __name__ == '__main__': 40 | test() 41 | -------------------------------------------------------------------------------- /arch/M68K/M68KDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* M68K Backend by Daniel Collin 2015-2016 */ 3 | 4 | #ifndef CS_M68KDISASSEMBLER_H 5 | #define CS_M68KDISASSEMBLER_H 6 | 7 | #include "../../MCInst.h" 8 | 9 | /* Private, For internal use only */ 10 | typedef struct m68k_info { 11 | const uint8_t *code; 12 | size_t code_len; 13 | uint64_t baseAddress; 14 | MCInst *inst; 15 | unsigned int pc; /* program counter */ 16 | unsigned int ir; /* instruction register */ 17 | unsigned int type; 18 | unsigned int address_mask; /* Address mask to simulate address lines */ 19 | cs_m68k extension; 20 | uint16_t regs_read[20]; // list of implicit registers read by this insn 21 | uint8_t regs_read_count; // number of implicit registers read by this insn 22 | uint16_t regs_write[20]; // list of implicit registers modified by this insn 23 | uint8_t regs_write_count; // number of implicit registers modified by this insn 24 | uint8_t groups[8]; 25 | uint8_t groups_count; 26 | } m68k_info; 27 | 28 | bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info); 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /bindings/python/capstone/mips.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .mips_const import * 6 | 7 | # define the API 8 | class MipsOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint), 11 | ('disp', ctypes.c_int64), 12 | ) 13 | 14 | class MipsOpValue(ctypes.Union): 15 | _fields_ = ( 16 | ('reg', ctypes.c_uint), 17 | ('imm', ctypes.c_int64), 18 | ('mem', MipsOpMem), 19 | ) 20 | 21 | class MipsOp(ctypes.Structure): 22 | _fields_ = ( 23 | ('type', ctypes.c_uint), 24 | ('value', MipsOpValue), 25 | ) 26 | 27 | @property 28 | def imm(self): 29 | return self.value.imm 30 | 31 | @property 32 | def reg(self): 33 | return self.value.reg 34 | 35 | @property 36 | def mem(self): 37 | return self.value.mem 38 | 39 | 40 | class CsMips(ctypes.Structure): 41 | _fields_ = ( 42 | ('op_count', ctypes.c_uint8), 43 | ('operands', MipsOp * 10), 44 | ) 45 | 46 | def get_arch_info(a): 47 | return copy_ctypes_list(a.operands[:a.op_count]) 48 | 49 | -------------------------------------------------------------------------------- /arch/AArch64/AArch64Module.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_ARM64 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "AArch64Disassembler.h" 9 | #include "AArch64InstPrinter.h" 10 | #include "AArch64Mapping.h" 11 | #include "AArch64Module.h" 12 | 13 | cs_err AArch64_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | AArch64_init(mri); 19 | ud->printer = AArch64_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = AArch64_getInstruction; 23 | ud->reg_name = AArch64_reg_name; 24 | ud->insn_id = AArch64_get_insn_id; 25 | ud->insn_name = AArch64_insn_name; 26 | ud->group_name = AArch64_group_name; 27 | ud->post_printer = AArch64_post_printer; 28 | #ifndef CAPSTONE_DIET 29 | ud->reg_access = AArch64_reg_access; 30 | #endif 31 | 32 | return CS_ERR_OK; 33 | } 34 | 35 | cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value) 36 | { 37 | if (type == CS_OPT_MODE) { 38 | handle->mode = (cs_mode)value; 39 | } 40 | 41 | return CS_ERR_OK; 42 | } 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /bindings/vb6/README.txt: -------------------------------------------------------------------------------- 1 | 2 | Capstone Disassembly Engine bindings for VB6 3 | Contributed by FireEye FLARE Team 4 | Author: David Zimmer , 5 | License: Apache 6 | Copyright: FireEye 2017 7 | 8 | This is a sample for using the capstone disassembly engine with VB6. 9 | 10 | All of the capstone API are implemented, so this lib supports basic 11 | disassembly of all of the processor architectures that capstone implements. 12 | 13 | In the vb code, full instruction details are currently only supported for 14 | the x86 processor family. 15 | 16 | This sample was built against Capstone 3.0 rc4. Note that if the capstone 17 | structures change in the future this code will have to be adjusted to match. 18 | 19 | The vbCapstone.dll is written in C. Project files are provided for VS2008. 20 | It is a small shim to give VB6 access to a stdcall API to access capstone. 21 | You could also modify capstone itself so its exports were stdcall. 22 | 23 | The C project has an additional include directory set to ./../../include/ 24 | for . This is for the /capstone/bindings/vb6/ directory structure 25 | 26 | 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /suite/fuzz/onefile.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); 6 | 7 | int main(int argc, char** argv) 8 | { 9 | FILE * fp; 10 | uint8_t *Data; 11 | size_t Size; 12 | 13 | if (argc != 2) { 14 | return 1; 15 | } 16 | //opens the file, get its size, and reads it into a buffer 17 | fp = fopen(argv[1], "rb"); 18 | if (fp == NULL) { 19 | return 2; 20 | } 21 | if (fseek(fp, 0L, SEEK_END) != 0) { 22 | fclose(fp); 23 | return 2; 24 | } 25 | Size = ftell(fp); 26 | if (Size == (size_t) -1) { 27 | fclose(fp); 28 | return 2; 29 | } 30 | if (fseek(fp, 0L, SEEK_SET) != 0) { 31 | fclose(fp); 32 | return 2; 33 | } 34 | Data = malloc(Size); 35 | if (Data == NULL) { 36 | fclose(fp); 37 | return 2; 38 | } 39 | if (fread(Data, Size, 1, fp) != 1) { 40 | fclose(fp); 41 | free(Data); 42 | return 2; 43 | } 44 | 45 | //lauch fuzzer 46 | LLVMFuzzerTestOneInput(Data, Size); 47 | free(Data); 48 | fclose(fp); 49 | return 0; 50 | } 51 | 52 | -------------------------------------------------------------------------------- /msvc/README: -------------------------------------------------------------------------------- 1 | This directory includes all the necessary files to compile Capstone on Windows 2 | using Microsoft Visual Studio (VS). 3 | 4 | 5 | NOTE: 6 | 7 | (1) Visual Studio 2010 or newer versions is required. Open "capstone.sln" to 8 | build the libraries & test code with Visual Studio. The resulted binaries 9 | are put under either msvc/Debug, msvc/Release, msvc/x64/Debug, or 10 | msvc/x64/Release, depending on how you choose to compile them. 11 | 12 | (2) The solution (capstone.sln) & all project files (*.vcxproj) are made in 13 | Visual Studio 2010, so if you open them using newer version, an extra step 14 | is needed to convert them to current version. Just accept this when 15 | asked at the initial dialog, and proceed to build the solution normally 16 | afterwards. 17 | 18 | (3) The capstone_static_winkernel and test_winkernel projects are for Windows 19 | kernel drivers and excluded from build by default. In order to build them, 20 | you need to install Visual Studio 2013 or newer versions, and Windows Driver 21 | Kit 8.1 Update 1 or newer versions, then check "Build" check boxes for those 22 | projects on the Configuration Manager through the [Build] menu. 23 | -------------------------------------------------------------------------------- /arch/Mips/MipsModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_MIPS 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "MipsDisassembler.h" 9 | #include "MipsInstPrinter.h" 10 | #include "MipsMapping.h" 11 | #include "MipsModule.h" 12 | 13 | // Returns mode value with implied bits set 14 | static cs_mode updated_mode(cs_mode mode) 15 | { 16 | if (mode & CS_MODE_MIPS32R6) { 17 | mode |= CS_MODE_32; 18 | } 19 | 20 | return mode; 21 | } 22 | 23 | cs_err Mips_global_init(cs_struct *ud) 24 | { 25 | MCRegisterInfo *mri; 26 | mri = cs_mem_malloc(sizeof(*mri)); 27 | 28 | Mips_init(mri); 29 | ud->printer = Mips_printInst; 30 | ud->printer_info = mri; 31 | ud->getinsn_info = mri; 32 | ud->reg_name = Mips_reg_name; 33 | ud->insn_id = Mips_get_insn_id; 34 | ud->insn_name = Mips_insn_name; 35 | ud->group_name = Mips_group_name; 36 | 37 | ud->disasm = Mips_getInstruction; 38 | 39 | return CS_ERR_OK; 40 | } 41 | 42 | cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) 43 | { 44 | if (type == CS_OPT_MODE) { 45 | handle->mode = updated_mode(value); 46 | } 47 | 48 | return CS_ERR_OK; 49 | } 50 | 51 | #endif 52 | -------------------------------------------------------------------------------- /LEB128.h: -------------------------------------------------------------------------------- 1 | //===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file declares some utility functions for encoding SLEB128 and 11 | // ULEB128 values. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | /* Capstone Disassembly Engine */ 16 | /* By Nguyen Anh Quynh , 2013-2015 */ 17 | 18 | #ifndef CS_LLVM_SUPPORT_LEB128_H 19 | #define CS_LLVM_SUPPORT_LEB128_H 20 | 21 | #include "include/capstone/capstone.h" 22 | 23 | /// Utility function to decode a ULEB128 value. 24 | static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) 25 | { 26 | const uint8_t *orig_p = p; 27 | uint64_t Value = 0; 28 | unsigned Shift = 0; 29 | do { 30 | Value += (uint64_t)(*p & 0x7f) << Shift; 31 | Shift += 7; 32 | } while (*p++ >= 128); 33 | if (n) 34 | *n = (unsigned)(p - orig_p); 35 | return Value; 36 | } 37 | 38 | #endif // LLVM_SYSTEM_LEB128_H 39 | -------------------------------------------------------------------------------- /arch/SystemZ/SystemZModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2015 */ 3 | 4 | #ifdef CAPSTONE_HAS_SYSZ 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "SystemZDisassembler.h" 9 | #include "SystemZInstPrinter.h" 10 | #include "SystemZMapping.h" 11 | #include "SystemZModule.h" 12 | 13 | cs_err SystemZ_global_init(cs_struct *ud) 14 | { 15 | MCRegisterInfo *mri; 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | SystemZ_init(mri); 19 | ud->printer = SystemZ_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = SystemZ_getInstruction; 23 | ud->post_printer = SystemZ_post_printer; 24 | 25 | ud->reg_name = SystemZ_reg_name; 26 | ud->insn_id = SystemZ_get_insn_id; 27 | ud->insn_name = SystemZ_insn_name; 28 | ud->group_name = SystemZ_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot 39 | // test for CS_MODE_LITTLE_ENDIAN because it is 0 40 | 41 | return CS_ERR_OK; 42 | } 43 | 44 | #endif 45 | -------------------------------------------------------------------------------- /contrib/cs_driver/cs_driver/cs_driver.vcxproj.filters: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | {4FC737F1-C7A5-4376-A066-2A32D752A2FF} 6 | cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx 7 | 8 | 9 | {93995380-89BD-4b04-88EB-625FBE52EBFB} 10 | h;hpp;hxx;hm;inl;inc;xsd 11 | 12 | 13 | {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} 14 | rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms 15 | 16 | 17 | {8E41214B-6785-4CFE-B992-037D68949A14} 18 | inf;inv;inx;mof;mc; 19 | 20 | 21 | 22 | 23 | Source Files 24 | 25 | 26 | -------------------------------------------------------------------------------- /suite/MC/PowerPC/ppc64-operands.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 2 | 0x7c,0x22,0x1a,0x14 = add 1, 2, 3 3 | 0x7c,0x22,0x1a,0x14 = add 1, 2, 3 4 | 0x7c,0x00,0x02,0x14 = add 0, 0, 0 5 | 0x7f,0xff,0xfa,0x14 = add 31, 31, 31 6 | 0x38,0x20,0x00,0x00 = li 1, 0 7 | 0x38,0x22,0x00,0x00 = addi 1, 2, 0 8 | 0x38,0x20,0x80,0x00 = li 1, 0x8000 9 | 0x38,0x20,0x7f,0xff = li 1, 0x7fff 10 | 0x60,0x41,0x00,0x00 = ori 1, 2, 0 11 | 0x60,0x41,0xff,0xff = ori 1, 2, 65535 12 | 0x3c,0x20,0x00,0x00 = lis 1, 0 13 | 0x3c,0x20,0xff,0xff = lis 1, 0xffff 14 | 0x80,0x20,0x00,0x00 = lwz 1, 0(0) 15 | 0x80,0x20,0x00,0x00 = lwz 1, 0(0) 16 | 0x80,0x3f,0x00,0x00 = lwz 1, 0(31) 17 | 0x80,0x3f,0x00,0x00 = lwz 1, 0(31) 18 | 0x80,0x22,0x80,0x00 = lwz 1, -32768(2) 19 | 0x80,0x22,0x7f,0xff = lwz 1, 32767(2) 20 | 0xe8,0x20,0x00,0x00 = ld 1, 0(0) 21 | 0xe8,0x20,0x00,0x00 = ld 1, 0(0) 22 | 0xe8,0x3f,0x00,0x00 = ld 1, 0(31) 23 | 0xe8,0x3f,0x00,0x00 = ld 1, 0(31) 24 | 0xe8,0x22,0x80,0x00 = ld 1, -32768(2) 25 | 0xe8,0x22,0x7f,0xfc = ld 1, 32764(2) 26 | 0xe8,0x22,0x00,0x04 = ld 1, 4(2) 27 | 0xe8,0x22,0xff,0xfc = ld 1, -4(2) 28 | // 0x48,0x00,0x04,0x00 = b .+1024 29 | 0x48,0x00,0x04,0x02 = ba 1024 30 | // 0x41,0x82,0x04,0x00 = beq 0, .+1024 31 | // 0x41,0x82,0x04,0x02 = beqa 0, 1024 32 | -------------------------------------------------------------------------------- /bindings/vb6/Project1.vbp: -------------------------------------------------------------------------------- 1 | Type=Exe 2 | Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#C:\WINDOWS\system32\stdole2.tlb#OLE Automation 3 | Form=Form1.frm 4 | Module=mCapStone; Module1.bas 5 | Module=mx86; mx86.bas 6 | Module=mMisc; mMisc.bas 7 | Class=CInstruction; CInstruction.cls 8 | Class=CInstDetails; CInstDetails.cls 9 | Class=CDisassembler; CDisassembler.cls 10 | Object={831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0; mscomctl.ocx 11 | Class=CX86Inst; CX86Inst.cls 12 | Class=CX86Operand; CX86Operand.cls 13 | Class=CX86OpMem; CX86OpMem.cls 14 | Startup="Form1" 15 | ExeName32="Project1.exe" 16 | Command32="" 17 | Name="Project1" 18 | HelpContextID="0" 19 | CompatibleMode="0" 20 | MajorVer=1 21 | MinorVer=0 22 | RevisionVer=0 23 | AutoIncrementVer=0 24 | ServerSupportFiles=0 25 | VersionCompanyName="sandsprite" 26 | CompilationType=0 27 | OptimizationType=0 28 | FavorPentiumPro(tm)=0 29 | CodeViewDebugInfo=0 30 | NoAliasing=0 31 | BoundsCheck=0 32 | OverflowCheck=0 33 | FlPointCheck=0 34 | FDIVCheck=0 35 | UnroundedFP=0 36 | StartMode=0 37 | Unattended=0 38 | Retained=0 39 | ThreadPerObject=0 40 | MaxNumberOfThreads=1 41 | 42 | [MS Transaction Server] 43 | AutoRefresh=1 44 | 45 | [fastBuild] 46 | fullPath=%ap%\bin\demo.exe 47 | -------------------------------------------------------------------------------- /cmake.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Capstone disassembler engine (www.capstone-engine.org) 4 | # Build Capstone libs for specified architecture, or all if none is specified (libcapstone.so & libcapstone.a) on *nix with CMake & make 5 | # By Nguyen Anh Quynh, Jorn Vernee, 2019 6 | 7 | FLAGS="-DCMAKE_BUILD_TYPE=Release" 8 | # Uncomment below line to compile in Diet mode 9 | # FLAGS+=" -DCAPSTONE_BUILD_DIET=ON" 10 | 11 | case $1 in 12 | ARM) 13 | ARCH=ARM 14 | ;; 15 | ARM64) 16 | ARCH=ARM64 17 | ;; 18 | M68K) 19 | ARCH=M68K 20 | ;; 21 | MIPS) 22 | ARCH=MIPS 23 | ;; 24 | PowerPC) 25 | ARCH=PPC 26 | ;; 27 | Sparc) 28 | ARCH=SPARC 29 | ;; 30 | SystemZ) 31 | ARCH=SYSZ 32 | ;; 33 | XCore) 34 | ARCH=XCORE 35 | ;; 36 | x86) 37 | ARCH=X86 38 | ;; 39 | TMS320C64x) 40 | ARCH=TMS320C64X 41 | ;; 42 | M680x) 43 | ARCH=M680X 44 | ;; 45 | EVM) 46 | ARCH=EVM 47 | ;; 48 | MOS65XX) 49 | ARCH=MOS65XX 50 | ;; 51 | *) 52 | ;; 53 | esac 54 | 55 | if [ "x${ARCH}" = "x" ]; then 56 | FLAGS+=" -DCAPSTONE_ARCHITECTURE_DEFAULT=ON" 57 | else 58 | FLAGS+=" -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_${ARCH}_SUPPORT=ON" 59 | fi 60 | 61 | cmake $FLAGS .. 62 | 63 | make -j8 64 | -------------------------------------------------------------------------------- /arch/AArch64/AArch64GenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, https://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2015 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | AArch64_FeatureCRC = 1ULL << 0, 18 | AArch64_FeatureCrypto = 1ULL << 1, 19 | AArch64_FeatureFPARMv8 = 1ULL << 2, 20 | AArch64_FeatureNEON = 1ULL << 3, 21 | AArch64_FeatureZCRegMove = 1ULL << 4, 22 | AArch64_FeatureZCZeroing = 1ULL << 5, 23 | AArch64_ProcA53 = 1ULL << 6, 24 | AArch64_ProcA57 = 1ULL << 7, 25 | AArch64_ProcCyclone = 1ULL << 8 26 | }; 27 | 28 | #endif // GET_SUBTARGETINFO_ENUM 29 | 30 | -------------------------------------------------------------------------------- /bindings/python/capstone/xcore.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .xcore_const import * 6 | 7 | # define the API 8 | class XcoreOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint8), 11 | ('index', ctypes.c_uint8), 12 | ('disp', ctypes.c_int32), 13 | ('direct', ctypes.c_int), 14 | ) 15 | 16 | class XcoreOpValue(ctypes.Union): 17 | _fields_ = ( 18 | ('reg', ctypes.c_uint), 19 | ('imm', ctypes.c_int32), 20 | ('mem', XcoreOpMem), 21 | ) 22 | 23 | class XcoreOp(ctypes.Structure): 24 | _fields_ = ( 25 | ('type', ctypes.c_uint), 26 | ('value', XcoreOpValue), 27 | ) 28 | 29 | @property 30 | def imm(self): 31 | return self.value.imm 32 | 33 | @property 34 | def reg(self): 35 | return self.value.reg 36 | 37 | @property 38 | def mem(self): 39 | return self.value.mem 40 | 41 | 42 | class CsXcore(ctypes.Structure): 43 | _fields_ = ( 44 | ('op_count', ctypes.c_uint8), 45 | ('operands', XcoreOp * 8), 46 | ) 47 | 48 | def get_arch_info(a): 49 | return (copy_ctypes_list(a.operands[:a.op_count])) 50 | 51 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-mul-div-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x9c,0x22,0x0e = mul v0.8b, v1.8b, v2.8b 3 | 0x20,0x9c,0x22,0x4e = mul v0.16b, v1.16b, v2.16b 4 | 0x20,0x9c,0x62,0x0e = mul v0.4h, v1.4h, v2.4h 5 | 0x20,0x9c,0x62,0x4e = mul v0.8h, v1.8h, v2.8h 6 | 0x20,0x9c,0xa2,0x0e = mul v0.2s, v1.2s, v2.2s 7 | 0x20,0x9c,0xa2,0x4e = mul v0.4s, v1.4s, v2.4s 8 | 0x20,0xdc,0x22,0x2e = fmul v0.2s, v1.2s, v2.2s 9 | 0x20,0xdc,0x22,0x6e = fmul v0.4s, v1.4s, v2.4s 10 | 0x20,0xdc,0x62,0x6e = fmul v0.2d, v1.2d, v2.2d 11 | 0x20,0xfc,0x22,0x2e = fdiv v0.2s, v1.2s, v2.2s 12 | 0x20,0xfc,0x22,0x6e = fdiv v0.4s, v1.4s, v2.4s 13 | 0x20,0xfc,0x62,0x6e = fdiv v0.2d, v1.2d, v2.2d 14 | 0xf1,0x9f,0x30,0x2e = pmul v17.8b, v31.8b, v16.8b 15 | 0x20,0x9c,0x22,0x6e = pmul v0.16b, v1.16b, v2.16b 16 | 0x22,0xb7,0x63,0x0e = sqdmulh v2.4h, v25.4h, v3.4h 17 | 0xac,0xb4,0x6d,0x4e = sqdmulh v12.8h, v5.8h, v13.8h 18 | 0x23,0xb4,0xbe,0x0e = sqdmulh v3.2s, v1.2s, v30.2s 19 | 0x22,0xb7,0x63,0x2e = sqrdmulh v2.4h, v25.4h, v3.4h 20 | 0xac,0xb4,0x6d,0x6e = sqrdmulh v12.8h, v5.8h, v13.8h 21 | 0x23,0xb4,0xbe,0x2e = sqrdmulh v3.2s, v1.2s, v30.2s 22 | 0xb5,0xdc,0x2d,0x0e = fmulx v21.2s, v5.2s, v13.2s 23 | 0x21,0xdf,0x23,0x4e = fmulx v1.4s, v25.4s, v3.4s 24 | 0xdf,0xde,0x62,0x4e = fmulx v31.2d, v22.2d, v2.2d 25 | -------------------------------------------------------------------------------- /suite/MC/X86/x86-32-ms-inline-asm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 2 | 0x8b,0x03 = movl (%ebx), %eax 3 | 0x89,0x4b,0x04 = movl %ecx, 4(%ebx) 4 | 0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax 5 | 0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax 6 | 0x8b,0x04,0x06 = movl (%esi, %eax), %eax 7 | 0x8b,0x04,0x06 = movl (%esi, %eax), %eax 8 | 0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax 9 | 0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax 10 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 11 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 12 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 13 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 14 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 15 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 16 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 17 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 18 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 19 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 20 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 21 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 22 | 0x8b,0x44,0x46,0x10 = movl 16(%esi, %eax, 2), %eax 23 | 0x0f,0x18,0x40,0x40 = prefetchnta 64(%eax) 24 | 0x60 = pushal 25 | 0x61 = popal 26 | 0x60 = pushal 27 | 0x61 = popal 28 | -------------------------------------------------------------------------------- /bindings/ocaml/arm.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open Arm_const 5 | 6 | let _CS_OP_ARCH = 5;; 7 | let _CS_OP_CIMM = _CS_OP_ARCH (* C-Immediate *) 8 | let _CS_OP_PIMM = _CS_OP_ARCH + 1 (* P-Immediate *) 9 | 10 | 11 | (* architecture specific info of instruction *) 12 | type arm_op_shift = { 13 | shift_type: int; (* TODO: covert this to pattern like arm_op_value? *) 14 | shift_value: int; 15 | } 16 | 17 | type arm_op_mem = { 18 | base: int; 19 | index: int; 20 | scale: int; 21 | disp: int; 22 | lshift: int; 23 | } 24 | 25 | type arm_op_value = 26 | | ARM_OP_INVALID of int 27 | | ARM_OP_REG of int 28 | | ARM_OP_CIMM of int 29 | | ARM_OP_PIMM of int 30 | | ARM_OP_IMM of int 31 | | ARM_OP_FP of float 32 | | ARM_OP_MEM of arm_op_mem 33 | | ARM_OP_SETEND of int 34 | 35 | type arm_op = { 36 | vector_index: int; 37 | shift: arm_op_shift; 38 | value: arm_op_value; 39 | subtracted: bool; 40 | access: int; 41 | neon_lane: int; 42 | } 43 | 44 | type cs_arm = { 45 | usermode: bool; 46 | vector_size: int; 47 | vector_data: int; 48 | cps_mode: int; 49 | cps_flag: int; 50 | cc: int; 51 | update_flags: bool; 52 | writeback: bool; 53 | mem_barrier: int; 54 | operands: arm_op array; 55 | } 56 | -------------------------------------------------------------------------------- /suite/fuzz/fuzz_llvm.cpp: -------------------------------------------------------------------------------- 1 | #include "llvm-c/Disassembler.h" 2 | #include "llvm-c/Target.h" 3 | #include "llvm/MC/SubtargetFeature.h" 4 | #include "llvm/Support/CommandLine.h" 5 | #include "llvm/Support/raw_ostream.h" 6 | 7 | using namespace llvm; 8 | 9 | extern "C" void LLVMFuzzerInit() { 10 | LLVMInitializeAllTargetInfos(); 11 | LLVMInitializeAllTargetMCs(); 12 | LLVMInitializeAllDisassemblers(); 13 | } 14 | 15 | 16 | extern "C" int LLVMFuzzerReturnOneInput(const uint8_t *Data, size_t Size, char * AssemblyText) { 17 | LLVMDisasmContextRef Ctx; 18 | std::vector DataCopy(Data, Data + Size); 19 | uint8_t *p = DataCopy.data(); 20 | int r = 1; 21 | 22 | switch(Data[0]) { 23 | case 0: 24 | Ctx = LLVMCreateDisasmCPUFeatures("i386", "", "", nullptr, 0, nullptr, nullptr); 25 | if (LLVMSetDisasmOptions(Ctx, LLVMDisassembler_Option_AsmPrinterVariant) == 0) { 26 | abort(); 27 | } 28 | break; 29 | //TODO other cases 30 | default: 31 | return 1; 32 | } 33 | assert(Ctx); 34 | 35 | if (LLVMDisasmInstruction(Ctx, p+1, Size-1, 0, AssemblyText, 80) > 0) { 36 | r = 0; 37 | } 38 | LLVMDisasmDispose(Ctx); 39 | 40 | return r; 41 | } 42 | -------------------------------------------------------------------------------- /tests/README: -------------------------------------------------------------------------------- 1 | This directory contains some test code to show how to use Capstone API. 2 | 3 | - test_basic.c 4 | This code shows the most simple form of API where we only want to get basic 5 | information out of disassembled instruction, such as address, mnemonic and 6 | operand string. 7 | 8 | - test_detail.c: 9 | This code shows how to access to architecture-neutral information in disassembled 10 | instructions, such as implicit registers read/written, or groups of instructions 11 | that this instruction belong to. 12 | 13 | - test_skipdata.c: 14 | This code shows how to use SKIPDATA option to skip broken instructions (most likely 15 | some data mixed with instructions) and continue to decode at the next legitimate 16 | instructions. 17 | 18 | - test_iter.c: 19 | This code shows how to use the API cs_disasm_iter() to decode one instruction at 20 | a time inside a loop. 21 | 22 | - test_customized_mnem.c: 23 | This code shows how to use MNEMONIC option to customize instruction mnemonic 24 | at run-time, and then how to reset the engine to use the default mnemonic. 25 | 26 | - test_.c 27 | These code show how to access architecture-specific information for each 28 | architecture. 29 | 30 | - test_winkernel.cpp 31 | This code shows how to use Capstone from a Windows driver. 32 | -------------------------------------------------------------------------------- /bindings/python/capstone/systemz.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .sysz_const import * 6 | 7 | # define the API 8 | class SyszOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint8), 11 | ('index', ctypes.c_uint8), 12 | ('length', ctypes.c_uint64), 13 | ('disp', ctypes.c_int64), 14 | ) 15 | 16 | class SyszOpValue(ctypes.Union): 17 | _fields_ = ( 18 | ('reg', ctypes.c_uint), 19 | ('imm', ctypes.c_int64), 20 | ('mem', SyszOpMem), 21 | ) 22 | 23 | class SyszOp(ctypes.Structure): 24 | _fields_ = ( 25 | ('type', ctypes.c_uint), 26 | ('value', SyszOpValue), 27 | ) 28 | 29 | @property 30 | def imm(self): 31 | return self.value.imm 32 | 33 | @property 34 | def reg(self): 35 | return self.value.reg 36 | 37 | @property 38 | def mem(self): 39 | return self.value.mem 40 | 41 | 42 | class CsSysz(ctypes.Structure): 43 | _fields_ = ( 44 | ('cc', ctypes.c_uint), 45 | ('op_count', ctypes.c_uint8), 46 | ('operands', SyszOp * 6), 47 | ) 48 | 49 | def get_arch_info(a): 50 | return (a.cc, copy_ctypes_list(a.operands[:a.op_count])) 51 | 52 | -------------------------------------------------------------------------------- /suite/MC/AArch64/neon-halving-add-sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x04,0x22,0x0e = shadd v0.8b, v1.8b, v2.8b 3 | 0x20,0x04,0x22,0x4e = shadd v0.16b, v1.16b, v2.16b 4 | 0x20,0x04,0x62,0x0e = shadd v0.4h, v1.4h, v2.4h 5 | 0x20,0x04,0x62,0x4e = shadd v0.8h, v1.8h, v2.8h 6 | 0x20,0x04,0xa2,0x0e = shadd v0.2s, v1.2s, v2.2s 7 | 0x20,0x04,0xa2,0x4e = shadd v0.4s, v1.4s, v2.4s 8 | 0x20,0x04,0x22,0x2e = uhadd v0.8b, v1.8b, v2.8b 9 | 0x20,0x04,0x22,0x6e = uhadd v0.16b, v1.16b, v2.16b 10 | 0x20,0x04,0x62,0x2e = uhadd v0.4h, v1.4h, v2.4h 11 | 0x20,0x04,0x62,0x6e = uhadd v0.8h, v1.8h, v2.8h 12 | 0x20,0x04,0xa2,0x2e = uhadd v0.2s, v1.2s, v2.2s 13 | 0x20,0x04,0xa2,0x6e = uhadd v0.4s, v1.4s, v2.4s 14 | 0x20,0x24,0x22,0x0e = shsub v0.8b, v1.8b, v2.8b 15 | 0x20,0x24,0x22,0x4e = shsub v0.16b, v1.16b, v2.16b 16 | 0x20,0x24,0x62,0x0e = shsub v0.4h, v1.4h, v2.4h 17 | 0x20,0x24,0x62,0x4e = shsub v0.8h, v1.8h, v2.8h 18 | 0x20,0x24,0xa2,0x0e = shsub v0.2s, v1.2s, v2.2s 19 | 0x20,0x24,0xa2,0x4e = shsub v0.4s, v1.4s, v2.4s 20 | 0x20,0x24,0x22,0x2e = uhsub v0.8b, v1.8b, v2.8b 21 | 0x20,0x24,0x22,0x6e = uhsub v0.16b, v1.16b, v2.16b 22 | 0x20,0x24,0x62,0x2e = uhsub v0.4h, v1.4h, v2.4h 23 | 0x20,0x24,0x62,0x6e = uhsub v0.8h, v1.8h, v2.8h 24 | 0x20,0x24,0xa2,0x2e = uhsub v0.2s, v1.2s, v2.2s 25 | 0x20,0x24,0xa2,0x6e = uhsub v0.4s, v1.4s, v2.4s 26 | -------------------------------------------------------------------------------- /suite/MC/ARM/neon-convert-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 3 | 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 4 | 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 5 | 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 6 | 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 7 | 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 8 | 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 9 | 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 10 | 0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1 11 | 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 12 | 0x30,0x0f,0xff,0xf3 = vcvt.u32.f32 d16, d16, #1 13 | 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 14 | 0x30,0x0e,0xff,0xf2 = vcvt.f32.s32 d16, d16, #1 15 | 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 16 | 0x30,0x0e,0xff,0xf3 = vcvt.f32.u32 d16, d16, #1 17 | 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 18 | 0x70,0x0f,0xff,0xf2 = vcvt.s32.f32 q8, q8, #1 19 | 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 20 | 0x70,0x0f,0xff,0xf3 = vcvt.u32.f32 q8, q8, #1 21 | 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 22 | 0x70,0x0e,0xff,0xf2 = vcvt.f32.s32 q8, q8, #1 23 | 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 24 | 0x70,0x0e,0xff,0xf3 = vcvt.f32.u32 q8, q8, #1 25 | 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 26 | 0x20,0x07,0xf6,0xf3 = vcvt.f32.f16 q8, d16 27 | 0x20,0x06,0xf6,0xf3 = vcvt.f16.f32 d16, q8 28 | -------------------------------------------------------------------------------- /suite/MC/Mips/mips-control-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0x00,0x00,0x0d = break 3 | // 0x00,0x07,0x00,0x0d = break 7, 0 4 | 0x00,0x07,0x01,0x4d = break 7, 5 5 | 0x00,0x00,0x00,0x0c = syscall 6 | 0x00,0x0d,0x15,0x0c = syscall 13396 7 | 0x42,0x00,0x00,0x18 = eret 8 | 0x42,0x00,0x00,0x1f = deret 9 | 0x41,0x60,0x60,0x00 = di 10 | 0x41,0x60,0x60,0x00 = di 11 | 0x41,0x6a,0x60,0x00 = di $t2 12 | 0x41,0x60,0x60,0x20 = ei 13 | 0x41,0x60,0x60,0x20 = ei 14 | 0x41,0x6a,0x60,0x20 = ei $t2 15 | 0x42,0x00,0x00,0x20 = wait 16 | 0x00,0x03,0x00,0x34 = teq $zero, $v1 17 | 0x00,0x03,0x00,0x74 = teq $zero, $v1, 1 18 | 0x04,0x6c,0x00,0x01 = teqi $v1, 1 19 | 0x00,0x03,0x00,0x30 = tge $zero, $v1 20 | 0x00,0x03,0x00,0xf0 = tge $zero, $v1, 3 21 | 0x04,0x68,0x00,0x03 = tgei $v1, 3 22 | 0x00,0x03,0x00,0x31 = tgeu $zero, $v1 23 | 0x00,0x03,0x01,0xf1 = tgeu $zero, $v1, 7 24 | 0x04,0x69,0x00,0x07 = tgeiu $v1, 7 25 | 0x00,0x03,0x00,0x32 = tlt $zero, $v1 26 | 0x00,0x03,0x07,0xf2 = tlt $zero, $v1, 31 27 | 0x04,0x6a,0x00,0x1f = tlti $v1, 31 28 | 0x00,0x03,0x00,0x33 = tltu $zero, $v1 29 | 0x00,0x03,0x3f,0xf3 = tltu $zero, $v1, 255 30 | 0x04,0x6b,0x00,0xff = tltiu $v1, 255 31 | 0x00,0x03,0x00,0x36 = tne $zero, $v1 32 | 0x00,0x03,0xff,0xf6 = tne $zero, $v1, 1023 33 | 0x04,0x6e,0x03,0xff = tnei $v1, 1023 34 | -------------------------------------------------------------------------------- /suite/MC/X86/3DNow.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 2 | 0x0f,0x0f,0xca,0xbf = pavgusb %mm2, %mm1 3 | // 0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf = pavgusb 9(%esi,%edx), %mm3 4 | 0x0f,0x0f,0xca,0x1d = pf2id %mm2, %mm1 5 | // 0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d = pf2id 9(%esi,%edx), %mm3 6 | 0x0f,0x0f,0xca,0xae = pfacc %mm2, %mm1 7 | 0x0f,0x0f,0xca,0x9e = pfadd %mm2, %mm1 8 | 0x0f,0x0f,0xca,0xb0 = pfcmpeq %mm2, %mm1 9 | 0x0f,0x0f,0xca,0x90 = pfcmpge %mm2, %mm1 10 | 0x0f,0x0f,0xca,0xa0 = pfcmpgt %mm2, %mm1 11 | 0x0f,0x0f,0xca,0xa4 = pfmax %mm2, %mm1 12 | 0x0f,0x0f,0xca,0x94 = pfmin %mm2, %mm1 13 | 0x0f,0x0f,0xca,0xb4 = pfmul %mm2, %mm1 14 | 0x0f,0x0f,0xca,0x96 = pfrcp %mm2, %mm1 15 | 0x0f,0x0f,0xca,0xa6 = pfrcpit1 %mm2, %mm1 16 | 0x0f,0x0f,0xca,0xb6 = pfrcpit2 %mm2, %mm1 17 | 0x0f,0x0f,0xca,0xa7 = pfrsqit1 %mm2, %mm1 18 | 0x0f,0x0f,0xca,0x97 = pfrsqrt %mm2, %mm1 19 | 0x0f,0x0f,0xca,0x9a = pfsub %mm2, %mm1 20 | 0x0f,0x0f,0xca,0xaa = pfsubr %mm2, %mm1 21 | 0x0f,0x0f,0xca,0x0d = pi2fd %mm2, %mm1 22 | 0x0f,0x0f,0xca,0xb7 = pmulhrw %mm2, %mm1 23 | 0x0f,0x0e = femms 24 | // 0x0f,0x0d,0x00 = prefetch (%eax) 25 | 0x0f,0x0f,0xca,0x1c = pf2iw %mm2, %mm1 26 | 0x0f,0x0f,0xca,0x0c = pi2fw %mm2, %mm1 27 | 0x0f,0x0f,0xca,0x8a = pfnacc %mm2, %mm1 28 | 0x0f,0x0f,0xca,0x8e = pfpnacc %mm2, %mm1 29 | 0x0f,0x0f,0xca,0xbb = pswapd %mm2, %mm1 30 | --------------------------------------------------------------------------------