├── clean.bat ├── .gitattributes ├── demod_fir_sim ├── cadence │ ├── hdl.var │ ├── cds.lib │ └── ncsim_setup.sh ├── demod_fir_coef_int.txt ├── demod_fir_param.txt ├── demod_fir_input.txt ├── synopsys │ └── vcsmx │ │ ├── synopsys_sim.setup │ │ └── vcsmx_setup.sh ├── dspba_library_package.vhd ├── demod_fir.vhd ├── demod_fir_nativelink.tcl ├── auk_dspip_avalon_streaming_controller_hpfir.vhd ├── demod_fir_model.m ├── demod_fir_mlab.m ├── demod_fir_msim.tcl ├── auk_dspip_roundsat_hpfir.vhd └── demod_fir_ast.vhd ├── other ├── fir.fda ├── generator.m └── README.md ├── .qsys_edit ├── filters.xml └── preferences.xml ├── .gitignore ├── README.md ├── ipcores ├── cos_generator.qip ├── sin_generator.qip ├── cos_generator_bb.v ├── sin_generator_bb.v ├── cos_generator.v └── sin_generator.v ├── src ├── mod_mul.v ├── data_create.v ├── mod_s2p.v ├── top.v ├── demod_mul.v ├── freq_div.v ├── carrier_generator.v ├── demod_dec.v ├── mod_16QAM.v └── demod_16QAM.v ├── demod_fir.cmp ├── demod_p2s.v ├── demod_fir_sim.f ├── 16QAM.qpf ├── demod_fir.spd ├── demod_fir ├── dspba_library_package.vhd ├── demod_fir_0002.vhd ├── auk_dspip_avalon_streaming_controller_hpfir.vhd ├── auk_dspip_roundsat_hpfir.vhd └── demod_fir_0002_ast.vhd ├── demod_fir.sip ├── simulation └── modelsim │ ├── data_create.vt │ ├── carrier_generator.vt │ ├── top.vt │ ├── mod_16QAM.vt │ ├── mod_s2p.vt │ ├── demod_16QAM.vt │ └── data │ ├── cos.ver │ ├── sin.ver │ ├── cos.hex │ └── sin.hex ├── data ├── cos.mif ├── sin.mif ├── cos.hex └── sin.hex ├── demod_fir.bsf └── demod_fir.v /clean.bat: -------------------------------------------------------------------------------- 1 | del *.bak /s -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.vhd linguist-language=Verilog 2 | -------------------------------------------------------------------------------- /demod_fir_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /other/fir.fda: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/qxdn/16QAM/HEAD/other/fir.fda -------------------------------------------------------------------------------- /other/generator.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/qxdn/16QAM/HEAD/other/generator.m -------------------------------------------------------------------------------- /.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /other/README.md: -------------------------------------------------------------------------------- 1 | [generator.m](generator.m):正余弦生成 2 | 3 | [fir.fda](fir.fda):滤波器设计。在matlab命令行中使用filter designer -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_coef_int.txt: -------------------------------------------------------------------------------- 1 | 2 2 | 12 3 | 31 4 | 59 5 | 91 6 | 117 7 | 127 8 | 117 9 | 91 10 | 59 11 | 31 12 | 12 13 | 2 14 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | db 2 | output_files 3 | greybox_tmp 4 | incremental_db 5 | 6 | #仿真文件 7 | /simulation/modelsim/* 8 | /simulation/qsim/* 9 | !/simulation/modelsim/*.vt 10 | !/simulation/modelsim/data 11 | 12 | 13 | *.qsf 14 | *.bak 15 | *.rpt 16 | *.qws -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## 16QAM 2 | 使用FPGA完成16QAM的调制解调 3 | 4 | 5 | 设置FIR的IP核的时候不小心存错地方了，懒得改了 6 | 7 | [other](./other)里面是matlab进行正余弦采样和滤波器设计的代码 8 | 9 | [报告](https://github.com/qxdn/16QAM/releases/download/1.0.0/default.pdf) 10 | 11 | ## TODO 12 | - [x] 上传报告 13 | -------------------------------------------------------------------------------- /ipcores/cos_generator.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cos_generator.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cos_generator_bb.v"] 6 | -------------------------------------------------------------------------------- /ipcores/sin_generator.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sin_generator.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sin_generator_bb.v"] 6 | -------------------------------------------------------------------------------- /.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_param.txt: -------------------------------------------------------------------------------- 1 | PhysChanIn : 1 2 | PhysChanOut : 1 3 | ChansPerPhyIn : 1 4 | ChansPerPhyOut : 1 5 | InWidth : 8 6 | InFracWidth : 0 7 | OutWidth : 20 8 | OutFullWidth : 20 9 | OutFracWidth : 0 10 | OutFullFracWidth : 0 11 | nChans : 13 12 | nTaps : 13 13 | clockRate : 0.5 14 | inRate : 0.5 15 | interpN : 1 16 | decimN : 1 17 | busDataWidth : 16 18 | bankInWidth : 0 19 | modeWidth : 0 20 | -------------------------------------------------------------------------------- /src/mod_mul.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 调制乘法 3 | */ 4 | module mod_mul(clk,signal,carrier,out); 5 | input clk; 6 | input [1:0] signal; 7 | input signed [7:0] carrier; 8 | output reg signed [7:0] out; 9 | 10 | always @(posedge clk) begin 11 | case(signal) 12 | 2'b00: out<= carrier*3'd1; 13 | 2'b01: out<= carrier*3'd3; 14 | 2'b10: out<= carrier*-3'd1; 15 | 2'b11: out<= carrier*-3'd3; 16 | default: ; 17 | endcase 18 | end 19 | 20 | 21 | endmodule -------------------------------------------------------------------------------- /src/data_create.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 数字信号源 3 | */ 4 | module data_create(clk,reset_n,out); 5 | input clk,reset_n; 6 | output wire out; 7 | 8 | reg [0:15] CODE = 16'b1010_0111_1101_0001; 9 | 10 | reg [3:0] address = 4'b0000; 11 | 12 | assign out = CODE[address]; 13 | 14 | always @(posedge clk or negedge reset_n) begin 15 | if (!reset_n) begin 16 | address<=4'b0000; 17 | end else begin 18 | address<=address+1'b1; 19 | end 20 | end 21 | 22 | endmodule -------------------------------------------------------------------------------- /src/mod_s2p.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 调制串并转换 3 | */ 4 | module mod_s2p(clk_s,clk_p,reset_n,signal,code); 5 | input clk_s,clk_p,reset_n,signal; 6 | output reg [3:0] code; 7 | 8 | reg [3:0] buffer; 9 | 10 | always @(posedge clk_s or negedge reset_n) begin 11 | if(!reset_n) begin 12 | buffer <= 4'b0000; 13 | end else begin 14 | buffer <= {buffer[2:0],signal}; 15 | end 16 | end 17 | 18 | always @(posedge clk_p or negedge reset_n) begin 19 | if(!reset_n) begin 20 | code <= 4'b0000; 21 | end else begin 22 | code <= buffer; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /src/top.v: -------------------------------------------------------------------------------- 1 | 2 | module top(signal_clk,carrier_clk,reset_n,in_data,out_data); 3 | input signal_clk,carrier_clk,reset_n; 4 | output wire in_data,out_data; 5 | 6 | wire signed [8:0] mod_data; 7 | 8 | mod_16QAM mod( 9 | .signal_clk(signal_clk), 10 | .carrier_clk(carrier_clk), 11 | .reset_n(reset_n), 12 | .mod_out(mod_data), 13 | .serial_data(in_data) 14 | ); 15 | 16 | demod_16QAM demod( 17 | .carrier_clk(carrier_clk), 18 | .orgin_clk(signal_clk), 19 | .reset_n(reset_n), 20 | .signal(mod_data), 21 | .demod_out(out_data) 22 | ); 23 | 24 | endmodule -------------------------------------------------------------------------------- /src/demod_mul.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 解调乘法 3 | */ 4 | module demod_mul(clk,carrier_cos,carrier_sin,signal,out_i,out_q); 5 | input clk; 6 | input signed [7:0] carrier_cos; 7 | input signed [7:0] carrier_sin; 8 | input signed [8:0] signal; 9 | output signed [7:0] out_i; 10 | output signed [7:0] out_q; 11 | 12 | reg signed [15:0] mul_i; 13 | reg signed [15:0] mul_q; 14 | 15 | assign out_i = mul_i[15:8]; 16 | assign out_q = mul_q[15:8]; 17 | 18 | always @(posedge clk) begin 19 | mul_i <= carrier_cos * signal; 20 | mul_q <= carrier_sin * signal; 21 | end 22 | 23 | 24 | endmodule -------------------------------------------------------------------------------- /src/freq_div.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 分频 3 | */ 4 | module freq_div #(parameter DIV = 4) (orgin_clk,reset_n,out_clk); 5 | input orgin_clk,reset_n; //输入clk 复位 6 | output reg out_clk; //分频输出 7 | 8 | 9 | localparam COUNTER = DIV/2-1; 10 | 11 | reg [$clog2(COUNTER)-1:0] cnt; 12 | 13 | // 分频 14 | always @(posedge orgin_clk or negedge reset_n) begin 15 | if (!reset_n) begin 16 | cnt <= 0; 17 | out_clk <= 1'b0; 18 | end else if (cnt < COUNTER) begin 19 | cnt <= cnt+1'd1; 20 | out_clk <= out_clk; 21 | end else begin 22 | cnt <= 0; 23 | out_clk <= ~out_clk; 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /src/carrier_generator.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 载波产生 3 | */ 4 | module carrier_generator(clk,reset_n,sin,cos); 5 | input clk,reset_n; 6 | output signed [7:0] sin; 7 | output signed [7:0] cos; 8 | 9 | reg [7:0] address; 10 | 11 | //address生成 12 | always @(posedge clk or negedge reset_n) begin 13 | if (!reset_n) begin 14 | address <= 8'd0; 15 | end else begin 16 | address <= address + 1'b1; 17 | end 18 | end 19 | 20 | //生成sin 21 | sin_generator u_sin( 22 | .clock(clk), 23 | .address(address), 24 | .q(sin) 25 | ); 26 | 27 | //生成cos 28 | cos_generator u_cos( 29 | .clock(clk), 30 | .address(address), 31 | .q(cos) 32 | ); 33 | 34 | endmodule -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_input.txt: -------------------------------------------------------------------------------- 1 | 0 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 0 9 | 0 10 | 0 11 | 0 12 | 0 13 | 0 14 | 2 15 | 3 16 | 0 17 | 0 18 | 0 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 0 31 | 0 32 | 0 33 | 0 34 | 0 35 | 0 36 | 0 37 | 0 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 0 44 | 0 45 | 0 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 0 54 | -31 55 | 26 56 | -5 57 | -69 58 | -5 59 | 116 60 | 90 61 | -72 62 | 75 63 | -33 64 | 11 65 | 104 66 | 79 67 | 0 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | 0 74 | 0 75 | 0 76 | 0 77 | 0 78 | 0 79 | 0 80 | -------------------------------------------------------------------------------- /demod_fir.cmp: -------------------------------------------------------------------------------- 1 | component demod_fir is 2 | port ( 3 | clk : in std_logic := 'X'; -- clk 4 | reset_n : in std_logic := 'X'; -- reset_n 5 | ast_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data 6 | ast_sink_valid : in std_logic := 'X'; -- valid 7 | ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error 8 | ast_source_data : out std_logic_vector(19 downto 0); -- data 9 | ast_source_valid : out std_logic; -- valid 10 | ast_source_error : out std_logic_vector(1 downto 0) -- error 11 | ); 12 | end component demod_fir; 13 | 14 | -------------------------------------------------------------------------------- /demod_fir_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera_ver: ./libraries/altera_ver/ 6 | lpm_ver: ./libraries/lpm_ver/ 7 | sgate_ver: ./libraries/sgate_ver/ 8 | altera_mf_ver: ./libraries/altera_mf_ver/ 9 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 10 | cycloneive_ver: ./libraries/cycloneive_ver/ 11 | altera: ./libraries/altera/ 12 | lpm: ./libraries/lpm/ 13 | sgate: ./libraries/sgate/ 14 | altera_mf: ./libraries/altera_mf/ 15 | altera_lnsim: ./libraries/altera_lnsim/ 16 | cycloneive: ./libraries/cycloneive/ 17 | LIBRARY_SCAN = TRUE 18 | -------------------------------------------------------------------------------- /demod_p2s.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 并转串 3 | */ 4 | module demod_p2s(serial_clk,signal_clk,reset_n,signal,serial); 5 | input serial_clk,signal_clk,reset_n; 6 | input [3:0] signal; 7 | output reg serial; 8 | 9 | reg [3:0] buffer [0:3]; 10 | reg [3:0] cbuffer = 4'b0; 11 | reg [1:0] address = 2'b0; 12 | reg [1:0] counter = 2'd0; 13 | 14 | 15 | always @(posedge signal_clk ) begin 16 | buffer[address+1'b1] <= signal; 17 | end 18 | 19 | always @(posedge serial_clk or negedge reset_n) begin 20 | if(!reset_n) begin 21 | cbuffer<=4'b0; 22 | counter<=2'b11; 23 | address<=2'b0; 24 | serial<=1'b0; 25 | end else begin 26 | counter = counter -1'b1; 27 | if (counter == 2'b11) begin 28 | cbuffer = buffer[address+1'b1]; 29 | address = address +1'b1; 30 | end 31 | serial = cbuffer[counter]; 32 | end 33 | end 34 | 35 | 36 | endmodule -------------------------------------------------------------------------------- /demod_fir_sim.f: -------------------------------------------------------------------------------- 1 | demod_fir_sim/dspba_library_package.vhd 2 | demod_fir_sim/dspba_library.vhd 3 | demod_fir_sim/auk_dspip_math_pkg_hpfir.vhd 4 | demod_fir_sim/auk_dspip_lib_pkg_hpfir.vhd 5 | demod_fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd 6 | demod_fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd 7 | demod_fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd 8 | demod_fir_sim/auk_dspip_roundsat_hpfir.vhd 9 | demod_fir_sim/altera_avalon_sc_fifo.v 10 | demod_fir_sim/demod_fir_rtl_core.vhd 11 | demod_fir_sim/demod_fir_ast.vhd 12 | demod_fir_sim/demod_fir.vhd 13 | demod_fir_sim/demod_fir_nativelink.tcl 14 | demod_fir_sim/demod_fir_msim.tcl 15 | demod_fir_sim/demod_fir_tb.vhd 16 | demod_fir_sim/demod_fir_mlab.m 17 | demod_fir_sim/demod_fir_model.m 18 | demod_fir_sim/demod_fir_coef_int.txt 19 | demod_fir_sim/demod_fir_input.txt 20 | demod_fir_sim/demod_fir_param.txt 21 | -------------------------------------------------------------------------------- /src/demod_dec.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 判决 3 | */ 4 | module demod_dec(fir_data,reset_n,carrier_clk,signal_clk,signal); 5 | input signed [19:0] fir_data; 6 | input reset_n,carrier_clk,signal_clk; 7 | output reg [1:0] signal; 8 | 9 | localparam N = 16'd5000; 10 | reg [1:0] buffer; 11 | reg signed [19:0] fir_buffer; 12 | 13 | always @(posedge carrier_clk or negedge reset_n) begin 14 | if(!reset_n) begin 15 | buffer <= 2'd0; 16 | end else begin 17 | buffer[1] <= (fir_data>0?1'b0:1'b1); //赋值 18 | if(fir_data < 0) begin 19 | fir_buffer <= -fir_data; 20 | end else begin 21 | fir_buffer <= fir_data; 22 | end 23 | buffer[0] <= (fir_buffer>N? 1'b1:1'b0); //赋值 24 | end 25 | end 26 | 27 | always @(posedge signal_clk or negedge reset_n) begin 28 | if(!reset_n) begin 29 | signal<=2'b0; 30 | end else begin 31 | signal<=buffer; 32 | end 33 | end 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /16QAM.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition 21 | # Date created = 16:22:44 December 12, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.1" 26 | DATE = "16:22:44 December 12, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "16QAM" 31 | -------------------------------------------------------------------------------- /demod_fir_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera_ver ./libraries/altera_ver/ 13 | DEFINE lpm_ver ./libraries/lpm_ver/ 14 | DEFINE sgate_ver ./libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 16 | DEFINE cycloneive_ver ./libraries/cycloneive_ver/ 17 | DEFINE altera ./libraries/altera/ 18 | DEFINE lpm ./libraries/lpm/ 19 | DEFINE sgate ./libraries/sgate/ 20 | DEFINE altera_mf ./libraries/altera_mf/ 21 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 22 | DEFINE cycloneive ./libraries/cycloneive/ 23 | -------------------------------------------------------------------------------- /src/mod_16QAM.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 16QAM调制 3 | */ 4 | module mod_16QAM(signal_clk,carrier_clk,reset_n,mod_out,serial_data); 5 | input signal_clk,carrier_clk,reset_n; 6 | output signed [8:0] mod_out; 7 | output wire serial_data; //串行数据 8 | 9 | wire [3:0] p_data; //并行数据 10 | 11 | //载波 12 | wire signed [7:0] carrier_sin; 13 | wire signed [7:0] carrier_cos; 14 | 15 | //调制后载波 16 | wire signed [7:0] carrier_i; 17 | wire signed [7:0] carrier_q; 18 | wire [1:0] signal_I; //I 信号 19 | wire [1:0] signal_Q; //Q 信号 20 | 21 | wire clk_4div; //四分频 22 | 23 | assign signal_I = {p_data[3],p_data[1]}; 24 | assign signal_Q = {p_data[2],p_data[0]}; 25 | //载波输出 26 | assign mod_out = carrier_i + carrier_q; 27 | 28 | //四分频 29 | freq_div #(.DIV(4)) u_div4( 30 | .orgin_clk(signal_clk), 31 | .reset_n(reset_n), 32 | .out_clk(clk_4div) 33 | ); 34 | 35 | //数据源 36 | data_create u_data_create( 37 | .clk(signal_clk), 38 | .reset_n(reset_n), 39 | .out(serial_data) 40 | ); 41 | 42 | //串并转换 43 | mod_s2p u_mod_s2p( 44 | .clk_s(signal_clk), 45 | .clk_p(clk_4div), 46 | .reset_n(reset_n), 47 | .signal(serial_data), 48 | .code(p_data) 49 | ); 50 | 51 | // 载波生成 52 | carrier_generator u_carrier( 53 | .clk(carrier_clk), 54 | .reset_n(reset_n), 55 | .sin(carrier_sin), 56 | .cos(carrier_cos) 57 | ); 58 | 59 | 60 | //载波I 61 | mod_mul mod_mul_i( 62 | .clk(carrier_clk), 63 | .signal(signal_I), 64 | .carrier(carrier_cos), 65 | .out(carrier_i) 66 | ); 67 | 68 | 69 | //载波Q 70 | mod_mul mod_mul_q( 71 | .clk(carrier_clk), 72 | .signal(signal_Q), 73 | .carrier(carrier_sin), 74 | .out(carrier_q) 75 | ); 76 | 77 | endmodule -------------------------------------------------------------------------------- /demod_fir.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 10 | 13 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /demod_fir/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /demod_fir_sim/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files from any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Intel Program License Subscription 7 | -- Agreement, Intel FPGA IP License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.auk_dspip_lib_pkg_hpfir.all; 17 | use work.auk_dspip_math_pkg_hpfir.all; 18 | 19 | entity demod_fir is 20 | port ( 21 | clk : in STD_LOGIC; 22 | reset_n : in STD_LOGIC; 23 | ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*8) * 1 + 0 - 1 downto 0); 24 | ast_sink_valid : in STD_LOGIC; 25 | ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); 26 | ast_source_data : out STD_LOGIC_VECTOR(20 * 1*1 - 1 downto 0); 27 | ast_source_valid : out STD_LOGIC; 28 | ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) 29 | ); 30 | end demod_fir; 31 | 32 | 33 | architecture syn of demod_fir is 34 | component demod_fir_ast 35 | port ( 36 | clk : in STD_LOGIC; 37 | reset_n : in STD_LOGIC; 38 | ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*8) * 1 + 0 - 1 downto 0); 39 | ast_sink_valid : in STD_LOGIC; 40 | ast_sink_ready : out STD_LOGIC; 41 | ast_sink_sop : in STD_LOGIC; 42 | ast_sink_eop : in STD_LOGIC; 43 | ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); 44 | ast_source_data : out STD_LOGIC_VECTOR(1*20 * 1 - 1 downto 0); 45 | ast_source_ready : in STD_LOGIC; 46 | ast_source_valid : out STD_LOGIC; 47 | ast_source_sop : out STD_LOGIC; 48 | ast_source_eop : out STD_LOGIC; 49 | ast_source_channel : out STD_LOGIC_VECTOR(log2_ceil_one(1) - 1 downto 0); 50 | ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) 51 | ); 52 | end component; 53 | 54 | signal coeff_in_read_sig : std_logic; 55 | 56 | begin 57 | 58 | coeff_in_read_sig <= '1'; 59 | 60 | 61 | 62 | demod_fir_ast_inst : demod_fir_ast 63 | port map ( 64 | clk => clk, 65 | reset_n => reset_n, 66 | ast_sink_data => ast_sink_data, 67 | ast_source_data => ast_source_data, 68 | ast_sink_valid => ast_sink_valid, 69 | ast_sink_ready => open, 70 | ast_source_ready => '1', 71 | ast_source_valid => ast_source_valid, 72 | ast_sink_sop => '0', 73 | ast_sink_eop => '0', 74 | ast_sink_error => ast_sink_error, 75 | ast_source_sop => open, 76 | ast_source_eop => open, 77 | ast_source_channel => open, 78 | ast_source_error => ast_source_error 79 | ); 80 | end syn; 81 | 82 | 83 | -------------------------------------------------------------------------------- /demod_fir/demod_fir_0002.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files from any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Intel Program License Subscription 7 | -- Agreement, Intel FPGA IP License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.auk_dspip_lib_pkg_hpfir.all; 17 | use work.auk_dspip_math_pkg_hpfir.all; 18 | 19 | entity demod_fir_0002 is 20 | port ( 21 | clk : in STD_LOGIC; 22 | reset_n : in STD_LOGIC; 23 | ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*8) * 1 + 0 - 1 downto 0); 24 | ast_sink_valid : in STD_LOGIC; 25 | ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); 26 | ast_source_data : out STD_LOGIC_VECTOR(20 * 1*1 - 1 downto 0); 27 | ast_source_valid : out STD_LOGIC; 28 | ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) 29 | ); 30 | end demod_fir_0002; 31 | 32 | 33 | architecture syn of demod_fir_0002 is 34 | component demod_fir_0002_ast 35 | port ( 36 | clk : in STD_LOGIC; 37 | reset_n : in STD_LOGIC; 38 | ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*8) * 1 + 0 - 1 downto 0); 39 | ast_sink_valid : in STD_LOGIC; 40 | ast_sink_ready : out STD_LOGIC; 41 | ast_sink_sop : in STD_LOGIC; 42 | ast_sink_eop : in STD_LOGIC; 43 | ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); 44 | ast_source_data : out STD_LOGIC_VECTOR(1*20 * 1 - 1 downto 0); 45 | ast_source_ready : in STD_LOGIC; 46 | ast_source_valid : out STD_LOGIC; 47 | ast_source_sop : out STD_LOGIC; 48 | ast_source_eop : out STD_LOGIC; 49 | ast_source_channel : out STD_LOGIC_VECTOR(log2_ceil_one(1) - 1 downto 0); 50 | ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) 51 | ); 52 | end component; 53 | 54 | signal coeff_in_read_sig : std_logic; 55 | 56 | begin 57 | 58 | coeff_in_read_sig <= '1'; 59 | 60 | 61 | 62 | demod_fir_0002_ast_inst : demod_fir_0002_ast 63 | port map ( 64 | clk => clk, 65 | reset_n => reset_n, 66 | ast_sink_data => ast_sink_data, 67 | ast_source_data => ast_source_data, 68 | ast_sink_valid => ast_sink_valid, 69 | ast_sink_ready => open, 70 | ast_source_ready => '1', 71 | ast_source_valid => ast_source_valid, 72 | ast_sink_sop => '0', 73 | ast_sink_eop => '0', 74 | ast_sink_error => ast_sink_error, 75 | ast_source_sop => open, 76 | ast_source_eop => open, 77 | ast_source_channel => open, 78 | ast_source_error => ast_source_error 79 | ); 80 | end syn; 81 | 82 | 83 | -------------------------------------------------------------------------------- /demod_fir.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "demod_fir" -library "lib_demod_fir" -name IP_TOOL_NAME "altera_fir_compiler_ii" 2 | set_global_assignment -entity "demod_fir" -library "lib_demod_fir" -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -entity "demod_fir" -library "lib_demod_fir" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_demod_fir" -name SPD_FILE [file join $::quartus(sip_path) "demod_fir.spd"] 5 | 6 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/dspba_library_package.vhd"] 7 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/dspba_library.vhd"] 8 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/auk_dspip_math_pkg_hpfir.vhd"] 9 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/auk_dspip_lib_pkg_hpfir.vhd"] 10 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd"] 11 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd"] 12 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"] 13 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/auk_dspip_roundsat_hpfir.vhd"] 14 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/altera_avalon_sc_fifo.v"] 15 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_rtl_core.vhd"] 16 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_ast.vhd"] 17 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir.vhd"] 18 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_nativelink.tcl"] 19 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_msim.tcl"] 20 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_tb.vhd"] 21 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_mlab.m"] 22 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_model.m"] 23 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_coef_int.txt"] 24 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_input.txt"] 25 | set_global_assignment -library "lib_demod_fir" -name MISC_FILE [file join $::quartus(sip_path) "demod_fir_sim/demod_fir_param.txt"] 26 | -------------------------------------------------------------------------------- /simulation/modelsim/data_create.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "12/16/2020 23:25:03" 21 | 22 | // Verilog Test Bench template for design : data_create 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 1 ps/ 1 ps 28 | module data_create_vlg_tst(); 29 | // constants 30 | // general purpose registers 31 | reg eachvec; 32 | // test vector input registers 33 | reg clk; 34 | reg reset_n; 35 | // wires 36 | wire out; 37 | 38 | // assign statements (if any) 39 | data_create i1 ( 40 | // port map - connection between master ports and signals/registers 41 | .clk(clk), 42 | .out(out), 43 | .reset_n(reset_n) 44 | ); 45 | initial 46 | begin 47 | // code that executes only once 48 | // insert code here --> begin 49 | 50 | // --> end 51 | $display("Running testbench"); 52 | end 53 | always 54 | // optional sensitivity list 55 | // @(event1 or event2 or .... eventn) 56 | begin 57 | // code executes for every event on sensitivity list 58 | // insert code here --> begin 59 | 60 | @eachvec; 61 | // --> end 62 | end 63 | endmodule 64 | 65 | -------------------------------------------------------------------------------- /simulation/modelsim/carrier_generator.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "12/12/2020 22:23:45" 21 | 22 | // Verilog Test Bench template for design : carrier_generator 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 10 ns/ 10 ns 28 | module carrier_generator_vlg_tst(); 29 | // constants 30 | // general purpose registers 31 | 32 | // test vector input registers 33 | reg clk; 34 | reg reset_n; 35 | // wires 36 | wire [7:0] cos; 37 | wire [7:0] sin; 38 | // assign statements (if any) 39 | carrier_generator i1 ( 40 | // port map - connection between master ports and signals/registers 41 | .clk(clk), 42 | .cos(cos), 43 | .reset_n(reset_n), 44 | .sin(sin) 45 | ); 46 | initial 47 | begin 48 | // code that executes only once 49 | // insert code here --> begin 50 | #0 clk = 1'd0; 51 | #0 reset_n = 1'd0; 52 | #3 reset_n = 1'd1; 53 | // --> end 54 | $display("Running testbench"); 55 | end 56 | always 57 | // optional sensitivity list 58 | // @(event1 or event2 or .... eventn) 59 | begin 60 | // code executes for every event on sensitivity list 61 | // insert code here --> begin 62 | #1 clk = ~clk; 63 | 64 | // --> end 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /src/demod_16QAM.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 16QAM解码 3 | */ 4 | module demod_16QAM(carrier_clk,orgin_clk,reset_n,signal,demod_out); 5 | input carrier_clk,reset_n,orgin_clk; 6 | input signed [8:0] signal; //调制输出 7 | output demod_out; 8 | 9 | wire [3:0] p_data; //并行数据 10 | 11 | 12 | wire signed [7:0] mul_i; 13 | wire signed [7:0] mul_q; 14 | 15 | //载波 16 | wire signed [7:0] carrier_sin; 17 | wire signed [7:0] carrier_cos; 18 | 19 | 20 | wire clk_4div; //四分频 21 | wire clk_500k; 22 | 23 | wire [1:0] i_data; 24 | wire [1:0] q_data; 25 | 26 | wire fir_q_vaild; 27 | wire fir_i_vaild; 28 | 29 | //滤波器 30 | reg signed [19:0] fir_i; 31 | reg signed [19:0] fir_q; 32 | wire signed [19:0] fir_i_temp; 33 | wire signed [19:0] fir_q_temp; 34 | 35 | assign p_data = {i_data[1],q_data[1],i_data[0],q_data[0]}; 36 | 37 | //四分频 38 | freq_div #(.DIV(4)) u_div4( 39 | .orgin_clk(orgin_clk), 40 | .reset_n(reset_n), 41 | .out_clk(clk_4div) 42 | ); 43 | 44 | //100分频 45 | freq_div #(.DIV(100)) u_div100( 46 | .orgin_clk(carrier_clk), 47 | .reset_n(reset_n), 48 | .out_clk(clk_500k) 49 | ); 50 | 51 | // 载波生成 52 | carrier_generator u_carrier( 53 | .clk(carrier_clk), 54 | .reset_n(reset_n), 55 | .sin(carrier_sin), 56 | .cos(carrier_cos) 57 | ); 58 | 59 | //乘法 60 | demod_mul u_demod_mul( 61 | .clk(carrier_clk), 62 | .carrier_cos(carrier_cos), 63 | .carrier_sin(carrier_sin), 64 | .signal(signal), 65 | .out_i(mul_i), 66 | .out_q(mul_q) 67 | ); 68 | 69 | //i fir 70 | demod_fir demod_fir_i( 71 | .clk(clk_500k), 72 | .reset_n(reset_n), 73 | .ast_sink_data(mul_i), 74 | .ast_sink_valid(1'b1), 75 | .ast_sink_error(2'b00), 76 | .ast_source_data(fir_i_temp), 77 | .ast_source_valid(fir_i_vaild), 78 | .ast_source_error() 79 | ); 80 | 81 | always @(posedge carrier_clk or negedge reset_n) begin 82 | if(!reset_n) begin 83 | fir_i <= 20'b0; 84 | end else if (fir_i_vaild) begin 85 | fir_i <= fir_i_temp; 86 | end else begin 87 | fir_i <= fir_i; 88 | end 89 | end 90 | 91 | //q fir 92 | demod_fir demod_fir_q( 93 | .clk(clk_500k), 94 | .reset_n(reset_n), 95 | .ast_sink_data(mul_q), 96 | .ast_sink_valid(1'b1), 97 | .ast_sink_error(2'b00), 98 | .ast_source_data(fir_q_temp), 99 | .ast_source_valid(fir_q_vaild), 100 | .ast_source_error() 101 | ); 102 | 103 | always @(posedge carrier_clk or negedge reset_n) begin 104 | if(!reset_n) begin 105 | fir_q <= 20'b0; 106 | end else if (fir_q_vaild) begin 107 | fir_q <= fir_q_temp; 108 | end else begin 109 | fir_q <= fir_q; 110 | end 111 | end 112 | 113 | //i 判决 114 | demod_dec demod_dec_i( 115 | .fir_data(fir_i), 116 | .reset_n(reset_n), 117 | .carrier_clk(carrier_clk), 118 | .signal_clk(orgin_clk), 119 | .signal(i_data) 120 | ); 121 | 122 | //q 判决 123 | demod_dec demod_dec_q( 124 | .fir_data(fir_q), 125 | .reset_n(reset_n), 126 | .carrier_clk(carrier_clk), 127 | .signal_clk(orgin_clk), 128 | .signal(q_data) 129 | ); 130 | 131 | demod_p2s u_demod_p2s( 132 | .serial_clk(orgin_clk), 133 | .signal_clk(clk_4div), 134 | .reset_n(reset_n), 135 | .signal(p_data), 136 | .serial(demod_out) 137 | ); 138 | 139 | endmodule -------------------------------------------------------------------------------- /simulation/modelsim/top.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "12/19/2020 00:33:47" 21 | 22 | // Verilog Test Bench template for design : top 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 10 ns/ 10 ns 28 | module top_vlg_tst(); 29 | // constants 30 | // general purpose registers 31 | // test vector input registers 32 | reg carrier_clk; 33 | reg reset_n; 34 | reg signal_clk; 35 | // wires 36 | wire in_data; 37 | wire out_data; 38 | 39 | // assign statements (if any) 40 | top i1 ( 41 | // port map - connection between master ports and signals/registers 42 | .carrier_clk(carrier_clk), 43 | .in_data(in_data), 44 | .out_data(out_data), 45 | .reset_n(reset_n), 46 | .signal_clk(signal_clk) 47 | ); 48 | initial 49 | begin 50 | // code that executes only once 51 | // insert code here --> begin 52 | 53 | // --> end 54 | #0 reset_n=1'b0; 55 | #0 signal_clk=1'b0; 56 | #0 carrier_clk=1'b0; 57 | #2 reset_n = 1'b1; 58 | end 59 | always 60 | // optional sensitivity list 61 | // @(event1 or event2 or .... eventn) 62 | begin 63 | // code executes for every event on sensitivity list 64 | // insert code here --> begin 65 | #1 carrier_clk = ~carrier_clk; 66 | 67 | // --> end 68 | end 69 | always 70 | begin 71 | #5000 signal_clk =~signal_clk; 72 | end 73 | 74 | endmodule 75 | 76 | -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_nativelink.tcl: -------------------------------------------------------------------------------- 1 | ## ================================================================================ 2 | ## Legal Notice: Copyright (C) 2020 Intel Corporation. All rights reserved. 3 | ## Any megafunction design, and related net list (encrypted or decrypted), 4 | ## support information, device programming or simulation file, and any other 5 | ## associated documentation or information provided by Intel or a partner 6 | ## under Intel's Megafunction Partnership Program may be used only to 7 | ## program PLD devices (but not masked PLD devices) from Intel. Any other 8 | ## use of such megafunction design, net list, support information, device 9 | ## programming or simulation file, or any other related documentation or 10 | ## information is prohibited for any other purpose, including, but not 11 | ## limited to modification, reverse engineering, de-compiling, or use with 12 | ## any other silicon devices, unless such use is explicitly licensed under 13 | ## a separate agreement with Intel or a megafunction partner. Title to 14 | ## the intellectual property, including patents, copyrights, trademarks, 15 | ## trade secrets, or maskworks, embodied in any such megafunction design, 16 | ## net list, support information, device programming or simulation file, or 17 | ## any other related documentation or information provided by Intel or a 18 | ## megafunction partner, remains with Intel, the megafunction partner, or 19 | ## their respective licensors. No other licenses, including any licenses 20 | ## needed under any third party's intellectual property, are provided herein. 21 | ## ================================================================================ 22 | ## 23 | 24 | # Testbench simulation files 25 | set testbench_files [glob -nocomplain -- *.hex] 26 | set input_files [glob -nocomplain -- *input.txt] 27 | set file_dir [file dirname [info script]] 28 | 29 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation 30 | 31 | # Set test bench name 32 | set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation 33 | 34 | # Test bench settings 35 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME DUT -section_id tb 36 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.demod_fir_tb -section_id tb 37 | set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY work -section_id tb 38 | 39 | # Add Testbench files 40 | foreach i $testbench_files { 41 | set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work 42 | } 43 | 44 | if {[file exists $file_dir/demod_fir_coef_reload.txt]} { 45 | set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/demod_fir_coef_reload.txt -section_id tb -library work 46 | } 47 | if {[file exists $file_dir/demod_fir_coef_reload_rtl.txt]} { 48 | set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/demod_fir_coef_reload_rtl.txt -section_id tb -library work 49 | } 50 | set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/demod_fir_input.txt -section_id tb -library work 51 | 52 | set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/demod_fir_tb.vhd -section_id tb -library work 53 | 54 | # Specify testbench mode for nativelink 55 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 56 | 57 | # Specify active testbench for nativelink 58 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation 59 | -------------------------------------------------------------------------------- /simulation/modelsim/mod_16QAM.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "12/16/2020 22:49:17" 21 | 22 | // Verilog Test Bench template for design : mod_16QAM 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 10 ns/ 10 ns 28 | module mod_16QAM_vlg_tst(); 29 | // constants 30 | // general purpose registers 31 | 32 | // test vector input registers 33 | reg carrier_clk; 34 | reg reset_n; 35 | reg signal_clk; 36 | // wires 37 | wire [8:0] mod_out; 38 | wire serial_data; 39 | 40 | // assign statements (if any) 41 | mod_16QAM i1 ( 42 | // port map - connection between master ports and signals/registers 43 | .carrier_clk(carrier_clk), 44 | .mod_out(mod_out), 45 | .serial_data(serial_data), 46 | .signal_clk(signal_clk), 47 | .reset_n(reset_n) 48 | ); 49 | initial 50 | begin 51 | // code that executes only once 52 | // insert code here --> begin 53 | 54 | // --> end 55 | #0 reset_n = 1'b0; 56 | #0 carrier_clk = 1'b0; 57 | #0 signal_clk = 1'b0; 58 | #1 reset_n = 1'b1; 59 | end 60 | always 61 | // optional sensitivity list 62 | // @(event1 or event2 or .... eventn) 63 | begin 64 | // code executes for every event on sensitivity list 65 | // insert code here --> begin 66 | #2 carrier_clk = ~carrier_clk; //25M 67 | 68 | // --> end 69 | end 70 | 71 | always 72 | begin 73 | #500 signal_clk =~signal_clk; //100k 74 | end 75 | endmodule 76 | 77 | -------------------------------------------------------------------------------- /simulation/modelsim/mod_s2p.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "12/16/2020 23:26:31" 21 | 22 | // Verilog Test Bench template for design : mod_s2p 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 1 ps/ 1 ps 28 | module mod_s2p_vlg_tst(); 29 | // constants 30 | // general purpose registers 31 | 32 | // test vector input registers 33 | reg clk_p; 34 | reg clk_s; 35 | reg reset_n; 36 | reg signal; 37 | // wires 38 | wire [3:0] code; 39 | 40 | // assign statements (if any) 41 | mod_s2p i1 ( 42 | // port map - connection between master ports and signals/registers 43 | .clk_p(clk_p), 44 | .clk_s(clk_s), 45 | .code(code), 46 | .reset_n(reset_n), 47 | .signal(signal) 48 | ); 49 | 50 | initial 51 | begin 52 | // code that executes only once 53 | // insert code here --> begin 54 | #0 reset_n=1'b0; 55 | #0 clk_s = 1'b0; 56 | #0 clk_p = 1'b0; 57 | #1 reset_n=1'b1; 58 | // --> end 59 | 60 | end 61 | always 62 | // optional sensitivity list 63 | // @(event1 or event2 or .... eventn) 64 | begin 65 | // code executes for every event on sensitivity list 66 | // insert code here --> begin 67 | #2 clk_s = ~clk_s; 68 | 69 | // --> end 70 | end 71 | 72 | always 73 | begin 74 | #8 clk_p = ~clk_p; 75 | end 76 | 77 | always @(posedge clk_s) begin 78 | signal = {$random} % 2; 79 | end 80 | 81 | endmodule 82 | 83 | -------------------------------------------------------------------------------- /demod_fir/auk_dspip_avalon_streaming_controller_hpfir.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files from any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Intel Program License Subscription 7 | -- Agreement, Intel FPGA IP License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | ------------------------------------------------------------------------- 15 | ------------------------------------------------------------------------- 16 | -- 17 | -- $Revision: #1 $ 18 | -- $Date: 2009/07/29 $ 19 | -- Author : Boon Hong Oh 20 | -- 21 | -- Project : Avalon Streaming Wrapper for HP FIR 22 | -- 23 | -- Description : 24 | -- 25 | -- This file is the Interface controller for the Avalon Streaming Wrapper. 26 | -- The control signals between sink, core, and source modules are communicated 27 | -- via the controller. The stall output is used as the core enable signal in 28 | -- the wrapper. 29 | -- 30 | -- ALTERA Confidential and Proprietary 31 | -- Copyright 2006 (c) Altera Corporation 32 | -- All rights reserved 33 | -- 34 | ------------------------------------------------------------------------- 35 | ------------------------------------------------------------------------- 36 | library ieee; 37 | use ieee.std_logic_1164.all; 38 | use ieee.std_logic_arith.all; 39 | 40 | 41 | entity auk_dspip_avalon_streaming_controller_hpfir is 42 | port( 43 | clk : in std_logic; 44 | --clk_en : in std_logic := '1'; 45 | reset_n : in std_logic; 46 | --ready : in std_logic; 47 | sink_packet_error : in std_logic_vector (1 downto 0); 48 | --sink_stall : in std_logic; 49 | source_stall : in std_logic; 50 | valid : in std_logic; 51 | reset_design : out std_logic; 52 | sink_ready_ctrl : out std_logic; 53 | source_packet_error : out std_logic_vector (1 downto 0) := (others => '0'); 54 | source_valid_ctrl : out std_logic; 55 | stall : out std_logic 56 | ); 57 | 58 | -- Declarations 59 | 60 | end auk_dspip_avalon_streaming_controller_hpfir; 61 | 62 | -- hds interface_end 63 | 64 | architecture struct of auk_dspip_avalon_streaming_controller_hpfir is 65 | 66 | -- signal stall_int : std_logic; 67 | -- signal stall_reg : std_logic; 68 | 69 | -- attribute maxfan : integer; 70 | -- attribute maxfan of stall_reg : signal is 500; 71 | 72 | begin 73 | 74 | reset_design <= not reset_n; 75 | 76 | --should not stop sending data to source module when the sink module is stalled 77 | --should only stop sending when the source module is stalled 78 | 79 | --Disable the FIR core when backpressure 80 | stall <= source_stall; 81 | source_valid_ctrl <= valid; 82 | 83 | -- Sink FIFO and FIR core are disabled at the same time 84 | sink_ready_ctrl <= not(source_stall); 85 | 86 | source_packet_error <= sink_packet_error; 87 | 88 | end struct; 89 | -------------------------------------------------------------------------------- /demod_fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files from any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Intel Program License Subscription 7 | -- Agreement, Intel FPGA IP License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | ------------------------------------------------------------------------- 15 | ------------------------------------------------------------------------- 16 | -- 17 | -- $Revision: #1 $ 18 | -- $Date: 2009/07/29 $ 19 | -- Author : Boon Hong Oh 20 | -- 21 | -- Project : Avalon Streaming Wrapper for HP FIR 22 | -- 23 | -- Description : 24 | -- 25 | -- This file is the Interface controller for the Avalon Streaming Wrapper. 26 | -- The control signals between sink, core, and source modules are communicated 27 | -- via the controller. The stall output is used as the core enable signal in 28 | -- the wrapper. 29 | -- 30 | -- ALTERA Confidential and Proprietary 31 | -- Copyright 2006 (c) Altera Corporation 32 | -- All rights reserved 33 | -- 34 | ------------------------------------------------------------------------- 35 | ------------------------------------------------------------------------- 36 | library ieee; 37 | use ieee.std_logic_1164.all; 38 | use ieee.std_logic_arith.all; 39 | 40 | 41 | entity auk_dspip_avalon_streaming_controller_hpfir is 42 | port( 43 | clk : in std_logic; 44 | --clk_en : in std_logic := '1'; 45 | reset_n : in std_logic; 46 | --ready : in std_logic; 47 | sink_packet_error : in std_logic_vector (1 downto 0); 48 | --sink_stall : in std_logic; 49 | source_stall : in std_logic; 50 | valid : in std_logic; 51 | reset_design : out std_logic; 52 | sink_ready_ctrl : out std_logic; 53 | source_packet_error : out std_logic_vector (1 downto 0) := (others => '0'); 54 | source_valid_ctrl : out std_logic; 55 | stall : out std_logic 56 | ); 57 | 58 | -- Declarations 59 | 60 | end auk_dspip_avalon_streaming_controller_hpfir; 61 | 62 | -- hds interface_end 63 | 64 | architecture struct of auk_dspip_avalon_streaming_controller_hpfir is 65 | 66 | -- signal stall_int : std_logic; 67 | -- signal stall_reg : std_logic; 68 | 69 | -- attribute maxfan : integer; 70 | -- attribute maxfan of stall_reg : signal is 500; 71 | 72 | begin 73 | 74 | reset_design <= not reset_n; 75 | 76 | --should not stop sending data to source module when the sink module is stalled 77 | --should only stop sending when the source module is stalled 78 | 79 | --Disable the FIR core when backpressure 80 | stall <= source_stall; 81 | source_valid_ctrl <= valid; 82 | 83 | -- Sink FIFO and FIR core are disabled at the same time 84 | sink_ready_ctrl <= not(source_stall); 85 | 86 | source_packet_error <= sink_packet_error; 87 | 88 | end struct; 89 | -------------------------------------------------------------------------------- /data/cos.mif: -------------------------------------------------------------------------------- 1 | depth = 256; 2 | width = 8; 3 | address_radix = UNS; 4 | data_radix = DEC; 5 | content begin 6 | 0:42; 7 | 1:42; 8 | 2:42; 9 | 3:42; 10 | 4:42; 11 | 5:42; 12 | 6:42; 13 | 7:41; 14 | 8:41; 15 | 9:41; 16 | 10:41; 17 | 11:40; 18 | 12:40; 19 | 13:40; 20 | 14:40; 21 | 15:39; 22 | 16:39; 23 | 17:38; 24 | 18:38; 25 | 19:38; 26 | 20:37; 27 | 21:37; 28 | 22:36; 29 | 23:35; 30 | 24:35; 31 | 25:34; 32 | 26:34; 33 | 27:33; 34 | 28:32; 35 | 29:32; 36 | 30:31; 37 | 31:30; 38 | 32:30; 39 | 33:29; 40 | 34:28; 41 | 35:27; 42 | 36:27; 43 | 37:26; 44 | 38:25; 45 | 39:24; 46 | 40:23; 47 | 41:22; 48 | 42:22; 49 | 43:21; 50 | 44:20; 51 | 45:19; 52 | 46:18; 53 | 47:17; 54 | 48:16; 55 | 49:15; 56 | 50:14; 57 | 51:13; 58 | 52:12; 59 | 53:11; 60 | 54:10; 61 | 55:9; 62 | 56:8; 63 | 57:7; 64 | 58:6; 65 | 59:5; 66 | 60:4; 67 | 61:3; 68 | 62:2; 69 | 63:1; 70 | 64:0; 71 | 65:-1; 72 | 66:-2; 73 | 67:-3; 74 | 68:-4; 75 | 69:-5; 76 | 70:-6; 77 | 71:-7; 78 | 72:-8; 79 | 73:-9; 80 | 74:-10; 81 | 75:-11; 82 | 76:-12; 83 | 77:-13; 84 | 78:-14; 85 | 79:-15; 86 | 80:-16; 87 | 81:-17; 88 | 82:-18; 89 | 83:-19; 90 | 84:-20; 91 | 85:-21; 92 | 86:-22; 93 | 87:-22; 94 | 88:-23; 95 | 89:-24; 96 | 90:-25; 97 | 91:-26; 98 | 92:-27; 99 | 93:-27; 100 | 94:-28; 101 | 95:-29; 102 | 96:-30; 103 | 97:-30; 104 | 98:-31; 105 | 99:-32; 106 | 100:-32; 107 | 101:-33; 108 | 102:-34; 109 | 103:-34; 110 | 104:-35; 111 | 105:-35; 112 | 106:-36; 113 | 107:-37; 114 | 108:-37; 115 | 109:-38; 116 | 110:-38; 117 | 111:-38; 118 | 112:-39; 119 | 113:-39; 120 | 114:-40; 121 | 115:-40; 122 | 116:-40; 123 | 117:-40; 124 | 118:-41; 125 | 119:-41; 126 | 120:-41; 127 | 121:-41; 128 | 122:-42; 129 | 123:-42; 130 | 124:-42; 131 | 125:-42; 132 | 126:-42; 133 | 127:-42; 134 | 128:-42; 135 | 129:-42; 136 | 130:-42; 137 | 131:-42; 138 | 132:-42; 139 | 133:-42; 140 | 134:-42; 141 | 135:-41; 142 | 136:-41; 143 | 137:-41; 144 | 138:-41; 145 | 139:-40; 146 | 140:-40; 147 | 141:-40; 148 | 142:-40; 149 | 143:-39; 150 | 144:-39; 151 | 145:-38; 152 | 146:-38; 153 | 147:-38; 154 | 148:-37; 155 | 149:-37; 156 | 150:-36; 157 | 151:-35; 158 | 152:-35; 159 | 153:-34; 160 | 154:-34; 161 | 155:-33; 162 | 156:-32; 163 | 157:-32; 164 | 158:-31; 165 | 159:-30; 166 | 160:-30; 167 | 161:-29; 168 | 162:-28; 169 | 163:-27; 170 | 164:-27; 171 | 165:-26; 172 | 166:-25; 173 | 167:-24; 174 | 168:-23; 175 | 169:-22; 176 | 170:-22; 177 | 171:-21; 178 | 172:-20; 179 | 173:-19; 180 | 174:-18; 181 | 175:-17; 182 | 176:-16; 183 | 177:-15; 184 | 178:-14; 185 | 179:-13; 186 | 180:-12; 187 | 181:-11; 188 | 182:-10; 189 | 183:-9; 190 | 184:-8; 191 | 185:-7; 192 | 186:-6; 193 | 187:-5; 194 | 188:-4; 195 | 189:-3; 196 | 190:-2; 197 | 191:-1; 198 | 192:0; 199 | 193:1; 200 | 194:2; 201 | 195:3; 202 | 196:4; 203 | 197:5; 204 | 198:6; 205 | 199:7; 206 | 200:8; 207 | 201:9; 208 | 202:10; 209 | 203:11; 210 | 204:12; 211 | 205:13; 212 | 206:14; 213 | 207:15; 214 | 208:16; 215 | 209:17; 216 | 210:18; 217 | 211:19; 218 | 212:20; 219 | 213:21; 220 | 214:22; 221 | 215:22; 222 | 216:23; 223 | 217:24; 224 | 218:25; 225 | 219:26; 226 | 220:27; 227 | 221:27; 228 | 222:28; 229 | 223:29; 230 | 224:30; 231 | 225:30; 232 | 226:31; 233 | 227:32; 234 | 228:32; 235 | 229:33; 236 | 230:34; 237 | 231:34; 238 | 232:35; 239 | 233:35; 240 | 234:36; 241 | 235:37; 242 | 236:37; 243 | 237:38; 244 | 238:38; 245 | 239:38; 246 | 240:39; 247 | 241:39; 248 | 242:40; 249 | 243:40; 250 | 244:40; 251 | 245:40; 252 | 246:41; 253 | 247:41; 254 | 248:41; 255 | 249:41; 256 | 250:42; 257 | 251:42; 258 | 252:42; 259 | 253:42; 260 | 254:42; 261 | 255:42; 262 | end; -------------------------------------------------------------------------------- /data/sin.mif: -------------------------------------------------------------------------------- 1 | depth = 256; 2 | width = 8; 3 | address_radix = UNS; 4 | data_radix = DEC; 5 | content begin 6 | 0:0; 7 | 1:1; 8 | 2:2; 9 | 3:3; 10 | 4:4; 11 | 5:5; 12 | 6:6; 13 | 7:7; 14 | 8:8; 15 | 9:9; 16 | 10:10; 17 | 11:11; 18 | 12:12; 19 | 13:13; 20 | 14:14; 21 | 15:15; 22 | 16:16; 23 | 17:17; 24 | 18:18; 25 | 19:19; 26 | 20:20; 27 | 21:21; 28 | 22:22; 29 | 23:22; 30 | 24:23; 31 | 25:24; 32 | 26:25; 33 | 27:26; 34 | 28:27; 35 | 29:27; 36 | 30:28; 37 | 31:29; 38 | 32:30; 39 | 33:30; 40 | 34:31; 41 | 35:32; 42 | 36:32; 43 | 37:33; 44 | 38:34; 45 | 39:34; 46 | 40:35; 47 | 41:35; 48 | 42:36; 49 | 43:37; 50 | 44:37; 51 | 45:38; 52 | 46:38; 53 | 47:38; 54 | 48:39; 55 | 49:39; 56 | 50:40; 57 | 51:40; 58 | 52:40; 59 | 53:40; 60 | 54:41; 61 | 55:41; 62 | 56:41; 63 | 57:41; 64 | 58:42; 65 | 59:42; 66 | 60:42; 67 | 61:42; 68 | 62:42; 69 | 63:42; 70 | 64:42; 71 | 65:42; 72 | 66:42; 73 | 67:42; 74 | 68:42; 75 | 69:42; 76 | 70:42; 77 | 71:41; 78 | 72:41; 79 | 73:41; 80 | 74:41; 81 | 75:40; 82 | 76:40; 83 | 77:40; 84 | 78:40; 85 | 79:39; 86 | 80:39; 87 | 81:38; 88 | 82:38; 89 | 83:38; 90 | 84:37; 91 | 85:37; 92 | 86:36; 93 | 87:35; 94 | 88:35; 95 | 89:34; 96 | 90:34; 97 | 91:33; 98 | 92:32; 99 | 93:32; 100 | 94:31; 101 | 95:30; 102 | 96:30; 103 | 97:29; 104 | 98:28; 105 | 99:27; 106 | 100:27; 107 | 101:26; 108 | 102:25; 109 | 103:24; 110 | 104:23; 111 | 105:22; 112 | 106:22; 113 | 107:21; 114 | 108:20; 115 | 109:19; 116 | 110:18; 117 | 111:17; 118 | 112:16; 119 | 113:15; 120 | 114:14; 121 | 115:13; 122 | 116:12; 123 | 117:11; 124 | 118:10; 125 | 119:9; 126 | 120:8; 127 | 121:7; 128 | 122:6; 129 | 123:5; 130 | 124:4; 131 | 125:3; 132 | 126:2; 133 | 127:1; 134 | 128:0; 135 | 129:-1; 136 | 130:-2; 137 | 131:-3; 138 | 132:-4; 139 | 133:-5; 140 | 134:-6; 141 | 135:-7; 142 | 136:-8; 143 | 137:-9; 144 | 138:-10; 145 | 139:-11; 146 | 140:-12; 147 | 141:-13; 148 | 142:-14; 149 | 143:-15; 150 | 144:-16; 151 | 145:-17; 152 | 146:-18; 153 | 147:-19; 154 | 148:-20; 155 | 149:-21; 156 | 150:-22; 157 | 151:-22; 158 | 152:-23; 159 | 153:-24; 160 | 154:-25; 161 | 155:-26; 162 | 156:-27; 163 | 157:-27; 164 | 158:-28; 165 | 159:-29; 166 | 160:-30; 167 | 161:-30; 168 | 162:-31; 169 | 163:-32; 170 | 164:-32; 171 | 165:-33; 172 | 166:-34; 173 | 167:-34; 174 | 168:-35; 175 | 169:-35; 176 | 170:-36; 177 | 171:-37; 178 | 172:-37; 179 | 173:-38; 180 | 174:-38; 181 | 175:-38; 182 | 176:-39; 183 | 177:-39; 184 | 178:-40; 185 | 179:-40; 186 | 180:-40; 187 | 181:-40; 188 | 182:-41; 189 | 183:-41; 190 | 184:-41; 191 | 185:-41; 192 | 186:-42; 193 | 187:-42; 194 | 188:-42; 195 | 189:-42; 196 | 190:-42; 197 | 191:-42; 198 | 192:-42; 199 | 193:-42; 200 | 194:-42; 201 | 195:-42; 202 | 196:-42; 203 | 197:-42; 204 | 198:-42; 205 | 199:-41; 206 | 200:-41; 207 | 201:-41; 208 | 202:-41; 209 | 203:-40; 210 | 204:-40; 211 | 205:-40; 212 | 206:-40; 213 | 207:-39; 214 | 208:-39; 215 | 209:-38; 216 | 210:-38; 217 | 211:-38; 218 | 212:-37; 219 | 213:-37; 220 | 214:-36; 221 | 215:-35; 222 | 216:-35; 223 | 217:-34; 224 | 218:-34; 225 | 219:-33; 226 | 220:-32; 227 | 221:-32; 228 | 222:-31; 229 | 223:-30; 230 | 224:-30; 231 | 225:-29; 232 | 226:-28; 233 | 227:-27; 234 | 228:-27; 235 | 229:-26; 236 | 230:-25; 237 | 231:-24; 238 | 232:-23; 239 | 233:-22; 240 | 234:-22; 241 | 235:-21; 242 | 236:-20; 243 | 237:-19; 244 | 238:-18; 245 | 239:-17; 246 | 240:-16; 247 | 241:-15; 248 | 242:-14; 249 | 243:-13; 250 | 244:-12; 251 | 245:-11; 252 | 246:-10; 253 | 247:-9; 254 | 248:-8; 255 | 249:-7; 256 | 250:-6; 257 | 251:-5; 258 | 252:-4; 259 | 253:-3; 260 | 254:-2; 261 | 255:-1; 262 | end; -------------------------------------------------------------------------------- /simulation/modelsim/demod_16QAM.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "12/18/2020 12:35:16" 21 | 22 | // Verilog Test Bench template for design : demod_16QAM 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 10 ns/ 10 ns 28 | module demod_16QAM_vlg_tst(); 29 | // constants 30 | // general purpose registers 31 | 32 | // test vector input registers 33 | reg carrier_clk; 34 | reg reset_n; 35 | 36 | reg signal_clk; 37 | // wires 38 | wire [8:0] signal; 39 | wire serial_data; 40 | 41 | // assign statements (if any) 42 | demod_16QAM i1 ( 43 | // port map - connection between master ports and signals/registers 44 | .carrier_clk(carrier_clk), 45 | .orgin_clk(signal_clk), 46 | .reset_n(reset_n), 47 | .demod_out(demod_out), 48 | .signal(signal) 49 | ); 50 | 51 | mod_16QAM i2( 52 | .signal_clk(signal_clk), 53 | .carrier_clk(carrier_clk), 54 | .reset_n(reset_n), 55 | .serial_data(serial_data), 56 | .mod_out(signal) 57 | ); 58 | initial 59 | begin 60 | // code that executes only once 61 | // insert code here --> begin 62 | #0 reset_n=1'b0; 63 | #0 signal_clk=1'b0; 64 | #0 carrier_clk=1'b0; 65 | #2 reset_n = 1'b1; 66 | // --> end 67 | end 68 | always 69 | // optional sensitivity list 70 | // @(event1 or event2 or .... eventn) 71 | begin 72 | // code executes for every event on sensitivity list 73 | // insert code here --> begin 74 | #1 carrier_clk = ~carrier_clk; 75 | // --> end 76 | end 77 | 78 | always 79 | begin 80 | #5000 signal_clk =~signal_clk; 81 | end 82 | endmodule 83 | 84 | -------------------------------------------------------------------------------- /simulation/modelsim/data/cos.ver: -------------------------------------------------------------------------------- 1 | @0 2 | 2a 3 | @1 4 | 2a 5 | @2 6 | 2a 7 | @3 8 | 2a 9 | @4 10 | 2a 11 | @5 12 | 2a 13 | @6 14 | 2a 15 | @7 16 | 29 17 | @8 18 | 29 19 | @9 20 | 29 21 | @a 22 | 29 23 | @b 24 | 28 25 | @c 26 | 28 27 | @d 28 | 28 29 | @e 30 | 28 31 | @f 32 | 27 33 | @10 34 | 27 35 | @11 36 | 26 37 | @12 38 | 26 39 | @13 40 | 26 41 | @14 42 | 25 43 | @15 44 | 25 45 | @16 46 | 24 47 | @17 48 | 23 49 | @18 50 | 23 51 | @19 52 | 22 53 | @1a 54 | 22 55 | @1b 56 | 21 57 | @1c 58 | 20 59 | @1d 60 | 20 61 | @1e 62 | 1f 63 | @1f 64 | 1e 65 | @20 66 | 1e 67 | @21 68 | 1d 69 | @22 70 | 1c 71 | @23 72 | 1b 73 | @24 74 | 1b 75 | @25 76 | 1a 77 | @26 78 | 19 79 | @27 80 | 18 81 | @28 82 | 17 83 | @29 84 | 16 85 | @2a 86 | 16 87 | @2b 88 | 15 89 | @2c 90 | 14 91 | @2d 92 | 13 93 | @2e 94 | 12 95 | @2f 96 | 11 97 | @30 98 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-------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_model.m: -------------------------------------------------------------------------------- 1 | % ================================================================================ 2 | % Legal Notice: Copyright (C) 2020 Intel Corporation. All rights reserved. 3 | % Any megafunction design, and related net list (encrypted or decrypted), 4 | % support information, device programming or simulation file, and any other 5 | % associated documentation or information provided by Intel or a partner 6 | % under Intel's Megafunction Partnership Program may be used only to 7 | % program PLD devices (but not masked PLD devices) from Intel. Any other 8 | % use of such megafunction design, net list, support information, device 9 | % programming or simulation file, or any other related documentation or 10 | % information is prohibited for any other purpose, including, but not 11 | % limited to modification, reverse engineering, de-compiling, or use with 12 | % any other silicon devices, unless such use is explicitly licensed under 13 | % a separate agreement with Intel or a megafunction partner. Title to 14 | % the intellectual property, including patents, copyrights, trademarks, 15 | % trade secrets, or maskworks, embodied in any such megafunction design, 16 | % net list, support information, device programming or simulation file, or 17 | % any other related documentation or information provided by Intel or a 18 | % megafunction partner, remains with Intel, the megafunction partner, or 19 | % their respective licensors. No other licenses, including any licenses 20 | % needed under any third party's intellectual property, are provided herein. 21 | % ================================================================================ 22 | % Generated on: 12/18/2020 19:27:40 23 | % Generated by: FIR Compiler II 18.1 24 | %--------------------------------------------------------------------------------------------------------- 25 | % 26 | % THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE! 27 | % 28 | %--------------------------------------------------------------------------------------------------------- 29 | 30 | clear; 31 | 32 | sx = 1; 33 | num_ch = 1; 34 | poly_type = 'single_rate'; 35 | dec_fact = 1; 36 | int_fact = 1; 37 | bankcount = 1; 38 | reconfigurable = false; 39 | mode_mapping = [0]; 40 | for j = 1:sx 41 | % 42 | %open and read data from file 43 | % 44 | file_name = ['demod_fir_input.txt']; 45 | infile = fopen (file_name, 'r'); 46 | 47 | input = fscanf(infile, '%d', [1 inf])'; 48 | real_data = input(:,1); 49 | data = input(:,1); 50 | bank = zeros(size(data)); 51 | 52 | for i = 1 : size(input) 53 | mode(i) = mod(i-1,num_ch); 54 | end 55 | 56 | 57 | 58 | fclose(infile); 59 | 60 | 61 | % array to store output, one row of data for each channel 62 | if (strcmp(poly_type,'single_rate')) 63 | if (floor(length(data)/num_ch)*num_ch~=length(data)) 64 | data=data(1:floor(length(data)/num_ch)*num_ch); 65 | end 66 | elseif (strcmp(poly_type,'decimation')) 67 | if (floor(length(data)/num_ch)*num_ch~=length(data)) 68 | data=data(1:floor(length(data)/num_ch)*num_ch); 69 | end 70 | end 71 | 72 | 73 | single_channel_data = cell(num_ch, 1); 74 | single_channel_bank = cell(num_ch, 1); 75 | output = cell(num_ch, 1); 76 | for j = 1: size(data,1); 77 | time_slot = mod(j-1,num_ch); 78 | if (reconfigurable) 79 | cur_mode = mode(j); 80 | channel = mode_mapping(cur_mode+1,time_slot+1)+1; 81 | else 82 | channel = time_slot+1; 83 | end 84 | single_channel_data{channel} = [single_channel_data{channel} data(j)]; 85 | single_channel_bank{channel} = [single_channel_bank{channel} bank(j)]; 86 | end 87 | 88 | for i = 1 : size(single_channel_bank,1) 89 | if not(isempty(single_channel_bank{i})) 90 | for j = 1:length(single_channel_bank{i}) 91 | for k = 1:int_fact 92 | bank_int((j-1)*int_fact+k) = single_channel_bank{i}(j); 93 | end 94 | end 95 | single_channel_bank{i} = bank_int; 96 | end 97 | end 98 | 99 | 100 | 101 | % run this output through the model 102 | for i = 1 : num_ch 103 | if(not(isempty(single_channel_data{i}))) 104 | output_ch{i} = demod_fir_mlab(single_channel_data{i}, single_channel_bank{i}); 105 | output_ch_eaten{i} = output_ch{i}; 106 | end 107 | end 108 | % reshape the output_channel so that the is channelwise 109 | 110 | 111 | limit = length(data)*int_fact/dec_fact; 112 | out = cell(1, 1); 113 | for j = 1: limit; 114 | time_slot = mod(j-1,num_ch); 115 | if (reconfigurable) 116 | cur_mode = mode(max(floor((j*dec_fact)/int_fact),1)); 117 | channel = mode_mapping(cur_mode+1,time_slot+1)+1; 118 | else 119 | channel = time_slot+1; 120 | end 121 | out{1} = [out{1} output_ch_eaten{channel}(1)]; 122 | output_ch_eaten{channel} = output_ch_eaten{channel}(1,2:end); 123 | end 124 | 125 | 126 | % Write data out to file 127 | file_name = ['demod_fir_model_output']; 128 | 129 | outfile1 = fopen([file_name, '.txt'],'w'); 130 | fprintf(outfile1, '%ld\n', out{1}); 131 | fclose(outfile1); 132 | end 133 | -------------------------------------------------------------------------------- /demod_fir.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 384 216) 24 | (text "demod_fir" (rect 163 -1 204 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 200 20 212)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8))) 30 | (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 144 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 112) 35 | (input) 36 | (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8))) 37 | (text "reset_n" (rect 4 101 46 112)(font "Arial" (font_size 8))) 38 | (line (pt 0 112)(pt 144 112)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 152) 42 | (input) 43 | (text "ast_sink_data[7..0]" (rect 0 0 75 12)(font "Arial" (font_size 8))) 44 | (text "ast_sink_data[7..0]" (rect 4 141 118 152)(font "Arial" (font_size 8))) 45 | (line (pt 0 152)(pt 144 152)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 168) 49 | (input) 50 | (text "ast_sink_valid" (rect 0 0 56 12)(font "Arial" (font_size 8))) 51 | (text "ast_sink_valid" (rect 4 157 88 168)(font "Arial" (font_size 8))) 52 | (line (pt 0 168)(pt 144 168)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 184) 56 | (input) 57 | (text "ast_sink_error[1..0]" (rect 0 0 77 12)(font "Arial" (font_size 8))) 58 | (text "ast_sink_error[1..0]" (rect 4 173 124 184)(font "Arial" (font_size 8))) 59 | (line (pt 0 184)(pt 144 184)(line_width 3)) 60 | ) 61 | (port 62 | (pt 384 72) 63 | (output) 64 | (text "ast_source_data[19..0]" (rect 0 0 90 12)(font "Arial" (font_size 8))) 65 | (text "ast_source_data[19..0]" (rect 270 61 402 72)(font "Arial" (font_size 8))) 66 | (line (pt 384 72)(pt 224 72)(line_width 3)) 67 | ) 68 | (port 69 | (pt 384 88) 70 | (output) 71 | (text "ast_source_valid" (rect 0 0 68 12)(font "Arial" (font_size 8))) 72 | (text "ast_source_valid" (rect 297 77 393 88)(font "Arial" (font_size 8))) 73 | (line (pt 384 88)(pt 224 88)(line_width 1)) 74 | ) 75 | (port 76 | (pt 384 104) 77 | (output) 78 | (text "ast_source_error[1..0]" (rect 0 0 89 12)(font "Arial" (font_size 8))) 79 | (text "ast_source_error[1..0]" (rect 273 93 405 104)(font "Arial" (font_size 8))) 80 | (line (pt 384 104)(pt 224 104)(line_width 3)) 81 | ) 82 | (drawing 83 | (text "clk" (rect 129 43 276 99)(font "Arial" (color 128 0 0)(font_size 9))) 84 | (text "clk" (rect 149 67 316 144)(font "Arial" (color 0 0 0))) 85 | (text "rst" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9))) 86 | (text "reset_n" (rect 149 107 340 224)(font "Arial" (color 0 0 0))) 87 | (text "avalon_streaming_sink" (rect 10 123 146 259)(font "Arial" (color 128 0 0)(font_size 9))) 88 | (text "data" (rect 149 147 322 304)(font "Arial" (color 0 0 0))) 89 | (text "valid" (rect 149 163 328 336)(font "Arial" (color 0 0 0))) 90 | (text "error" (rect 149 179 328 368)(font "Arial" (color 0 0 0))) 91 | (text "avalon_streaming_source" (rect 225 43 588 99)(font "Arial" (color 128 0 0)(font_size 9))) 92 | (text "data" (rect 203 67 430 144)(font "Arial" (color 0 0 0))) 93 | (text "valid" (rect 201 83 432 176)(font "Arial" (color 0 0 0))) 94 | (text "error" (rect 199 99 428 208)(font "Arial" (color 0 0 0))) 95 | (text " altera_fir_compiler_ii " (rect 289 200 722 410)(font "Arial" )) 96 | (line (pt 144 32)(pt 224 32)(line_width 1)) 97 | (line (pt 224 32)(pt 224 200)(line_width 1)) 98 | (line (pt 144 200)(pt 224 200)(line_width 1)) 99 | (line (pt 144 32)(pt 144 200)(line_width 1)) 100 | (line (pt 145 52)(pt 145 76)(line_width 1)) 101 | (line (pt 146 52)(pt 146 76)(line_width 1)) 102 | (line (pt 145 92)(pt 145 116)(line_width 1)) 103 | (line (pt 146 92)(pt 146 116)(line_width 1)) 104 | (line (pt 145 132)(pt 145 188)(line_width 1)) 105 | (line (pt 146 132)(pt 146 188)(line_width 1)) 106 | (line (pt 223 52)(pt 223 108)(line_width 1)) 107 | (line (pt 222 52)(pt 222 108)(line_width 1)) 108 | (line (pt 0 0)(pt 384 0)(line_width 1)) 109 | (line (pt 384 0)(pt 384 216)(line_width 1)) 110 | (line (pt 0 216)(pt 384 216)(line_width 1)) 111 | (line (pt 0 0)(pt 0 216)(line_width 1)) 112 | ) 113 | ) 114 | -------------------------------------------------------------------------------- /ipcores/cos_generator_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: cos_generator.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.0 Build 625 09/12/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module cos_generator ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [7:0] address; 40 | input clock; 41 | output [7:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "./data/cos.hex" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "./data/cos.hex" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator_inst.v FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | -------------------------------------------------------------------------------- /ipcores/sin_generator_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: sin_generator.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.0 Build 625 09/12/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module sin_generator ( 35 | address, 36 | clock, 37 | q); 38 | 39 | input [7:0] address; 40 | input clock; 41 | output [7:0] q; 42 | `ifndef ALTERA_RESERVED_QIS 43 | // synopsys translate_off 44 | `endif 45 | tri1 clock; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_on 48 | `endif 49 | 50 | endmodule 51 | 52 | // ============================================================ 53 | // CNX file retrieval info 54 | // ============================================================ 55 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 56 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 57 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 58 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 59 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 60 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 61 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 62 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 63 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 64 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 65 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 66 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 67 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 68 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 69 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 70 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 71 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 72 | // Retrieval info: PRIVATE: MIFfilename STRING "./data/sin.hex" 73 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 74 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 75 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 76 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 77 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 78 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 79 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 80 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 81 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 82 | // Retrieval info: PRIVATE: rden NUMERIC "0" 83 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 84 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 85 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 86 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 87 | // Retrieval info: CONSTANT: INIT_FILE STRING "./data/sin.hex" 88 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 90 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 91 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 92 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 93 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 94 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 95 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 96 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 97 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 98 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 99 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 100 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 101 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 102 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 103 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.v TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.inc FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.cmp FALSE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.bsf FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator_inst.v FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator_bb.v TRUE 110 | // Retrieval info: LIB_FILE: altera_mf 111 | -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_mlab.m: -------------------------------------------------------------------------------- 1 | % 2 | %THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE! 3 | % 4 | %--------------------------------------------------------------------------------------------------------- 5 | %This is a filter with fixed coefficients. 6 | %This Model Only Support Single Channel Input Data. 7 | %Please input: 8 | %data vector: stimulation(1:n) 9 | 10 | % This Model Only Support FIR_WIDTH to 51 Bits 11 | 12 | %FILTER PARAMETER 13 | %Input Data Width: 8 14 | %Interpolation Factor: 1 15 | %Decimation Factor: 1 16 | %FIR Width (Full Calculation Width Before Output Width Adjust) :20 17 | %----------------------------------------------------------------------------------------------------------- 18 | %MegaWizard Scaled Coefficient Values 19 | 20 | function output = demod_fir_mlab(stimulation, bank); 21 | coef_matrix_in= [2,12,31,59,91,117,127,117,91,59,31,12,2]; 22 | INTER_FACTOR = 1; 23 | DECI_FACTOR = 1; 24 | MSB_RM = 0; 25 | MSB_TYPE = 0; 26 | LSB_RM = 0; 27 | LSB_TYPE = 0; 28 | FIR_WIDTH = 20 + MSB_RM + LSB_RM; 29 | OUT_WIDTH = 20 ; %20 30 | DATA_WIDTH = 8; 31 | 32 | 33 | % check size of inputs. 34 | DY = size(stimulation, 2); 35 | CY = size(coef_matrix_in, 2); 36 | if CY ~= DY * INTER_FACTOR 37 | fprintf('WARNING : coef_matrix size and input data size does not match\n'); 38 | end 39 | 40 | %fill coef_matrix to length of data with the latest coef set 41 | if CY < DY * INTER_FACTOR 42 | coef_matrix = coef_matrix_in(bank + 1, :); 43 | end 44 | 45 | % check if input is integer 46 | int_sti=round(stimulation); 47 | T = (int_sti ~= stimulation); 48 | if (max(T)~=0) 49 | fprintf('WARNING : Integer Input Expected: Rounding Fractional Input to Nearest Integer...\n'); 50 | end 51 | 52 | %Input overflow check 53 | %set max/min for signed 54 | maxdat = 2^(DATA_WIDTH-1)-1; 55 | mindat = -maxdat-1; 56 | 57 | %Saturating Input Value 58 | a=find(int_sti>maxdat); 59 | b=find(int_sti %d \n', int_sti(a(i)), maxdat); 66 | int_sti(a(i)) = maxdat; 67 | end 68 | for i =1:lenb 69 | fprintf('%d < %d \n', int_sti(b(i)), mindat); 70 | int_sti(b(i)) = mindat; 71 | end 72 | end 73 | 74 | % Add interpolation 75 | inter_sti = zeros(1, INTER_FACTOR * length(int_sti)); 76 | inter_sti(1:INTER_FACTOR:INTER_FACTOR * length(int_sti)) = int_sti; 77 | 78 | 79 | for i = 1 : DY *INTER_FACTOR 80 | coef_current = coef_matrix(i,:); 81 | output_temp(i) = simp_adaptive (inter_sti, coef_current, i); 82 | end 83 | 84 | % Truncate output 85 | len1 = length(output_temp); 86 | 87 | switch LSB_TYPE 88 | case 0 89 | %truncate 90 | out_dec = bi_trunc_lsb(output_temp,LSB_RM,FIR_WIDTH); 91 | case 1 92 | %round 93 | out_dec = bi_round(output_temp,LSB_RM, FIR_WIDTH); 94 | end 95 | 96 | switch MSB_TYPE 97 | case 0 98 | %truncate 99 | out_dec = bi_trunc_msb(out_dec,MSB_RM,FIR_WIDTH-LSB_RM); 100 | case 1 101 | %round 102 | out_dec = bi_satu(out_dec,MSB_RM, FIR_WIDTH-LSB_RM); 103 | end 104 | 105 | % choose decimation output in phase=DECI_FACTOR-1 106 | if(DECI_FACTOR == 1) 107 | output = out_dec; 108 | else 109 | output = out_dec(1:DECI_FACTOR:len1); 110 | end 111 | 112 | function[output, outindex] = simp_adaptive (int_sti, coef_current, data_index) 113 | 114 | %Simulation is the whole input sequence 115 | %coef_current is the current coefficient set 116 | %data_index gives the last data to use 117 | % output is the sum of input and coef multiplication 118 | %outindex is the next data_index 119 | 120 | coef_length = length(coef_current); 121 | data_length = length(int_sti); 122 | 123 | if (data_index > data_length) 124 | fprintf('ERROR: DATA INDEX IS LARGER THAN DATA LENGTH!!!\n'); 125 | return 126 | end 127 | min_index = max(data_index - data_length, 1); 128 | max_index = min(data_index, coef_length); 129 | 130 | outindex= data_index+1; 131 | output = int_sti(data_index + 1 - (min_index:max_index)) * coef_current(min_index:max_index).'; 132 | 133 | function output = bi_round(data_in,LSB_RM,ORI_WIDTH) 134 | % LSB_RM is the bit to lose in LSB 135 | % ORI_WIDTH is the original data width 136 | 137 | data = round (data_in / 2^LSB_RM); 138 | 139 | output = bi_satu(data,0,ORI_WIDTH - LSB_RM); 140 | 141 | function output = bi_trunc_lsb(data_in,LSB_RM,ORI_WIDTH) 142 | % LSB_RM is the bit to lose in LSB 143 | % ORI_WIDTH is the original data width 144 | %2's complement system 145 | output = bitshift((2^ORI_WIDTH*(data_in<0)) + (2^LSB_RM)*floor(data_in/(2^LSB_RM)), -LSB_RM) - (2^(ORI_WIDTH-LSB_RM)) *(data_in<0); 146 | 147 | function output = bi_trunc_msb(data_in,MSB_RM,ORI_WIDTH) 148 | % MSB_RM is the bit to lose in LSB 149 | % ORI_WIDTH is the original data width 150 | %2's complement system 151 | data = 2^ORI_WIDTH * (data_in < 0)+ data_in; 152 | erase_num = 2^(ORI_WIDTH - MSB_RM) - 1; 153 | data = bitand(data, erase_num); 154 | output = data - 2^(ORI_WIDTH - MSB_RM)*(bitget(data,ORI_WIDTH - MSB_RM)); 155 | 156 | function output = bi_satu(data_in,MSB_RM,ORI_WIDTH) 157 | % MSB_RM is the bit to lose in LSB 158 | % ORI_WIDTH is the original data width 159 | %2's complement system 160 | maxdat = 2^(ORI_WIDTH - MSB_RM - 1)-1; 161 | mindat = 2^(ORI_WIDTH - MSB_RM - 1)*(-1); 162 | data_in(data_in > maxdat) = maxdat; 163 | data_in(data_in < mindat) = mindat; 164 | output = data_in; 165 | 166 | -------------------------------------------------------------------------------- /demod_fir.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIR II v18.1% 2 | // GENERATION: XML 3 | // demod_fir.v 4 | 5 | // Generated using ACDS version 18.1 625 6 | 7 | `timescale 1 ps / 1 ps 8 | module demod_fir ( 9 | input wire clk, // clk.clk 10 | input wire reset_n, // rst.reset_n 11 | input wire [7:0] ast_sink_data, // avalon_streaming_sink.data 12 | input wire ast_sink_valid, // .valid 13 | input wire [1:0] ast_sink_error, // .error 14 | output wire [19:0] ast_source_data, // avalon_streaming_source.data 15 | output wire ast_source_valid, // .valid 16 | output wire [1:0] ast_source_error // .error 17 | ); 18 | 19 | demod_fir_0002 demod_fir_inst ( 20 | .clk (clk), // clk.clk 21 | .reset_n (reset_n), // rst.reset_n 22 | .ast_sink_data (ast_sink_data), // avalon_streaming_sink.data 23 | .ast_sink_valid (ast_sink_valid), // .valid 24 | .ast_sink_error (ast_sink_error), // .error 25 | .ast_source_data (ast_source_data), // avalon_streaming_source.data 26 | .ast_source_valid (ast_source_valid), // .valid 27 | .ast_source_error (ast_source_error) // .error 28 | ); 29 | 30 | endmodule 31 | // Retrieval info: 32 | // 57 | // Retrieval info: 58 | // Retrieval info: 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // Retrieval info: 70 | // Retrieval info: 71 | // Retrieval info: 72 | // Retrieval info: 73 | // Retrieval info: 74 | // Retrieval info: 75 | // Retrieval info: 76 | // Retrieval info: 77 | // Retrieval info: 78 | // Retrieval info: 79 | // Retrieval info: 80 | // Retrieval info: 81 | // Retrieval info: 82 | // Retrieval info: 83 | // Retrieval info: 84 | // Retrieval info: 85 | // Retrieval info: 86 | // Retrieval info: 87 | // Retrieval info: 88 | // Retrieval info: 89 | // Retrieval info: 90 | // Retrieval info: 91 | // Retrieval info: 92 | // Retrieval info: 93 | // Retrieval info: 94 | // Retrieval info: 95 | // Retrieval info: 96 | // Retrieval info: 97 | // Retrieval info: 98 | // Retrieval info: 99 | // Retrieval info: 100 | // Retrieval info: 101 | // IPFS_FILES : demod_fir.vo 102 | // RELATED_FILES: demod_fir.v, dspba_library_package.vhd, dspba_library.vhd, auk_dspip_math_pkg_hpfir.vhd, auk_dspip_lib_pkg_hpfir.vhd, auk_dspip_avalon_streaming_controller_hpfir.vhd, auk_dspip_avalon_streaming_sink_hpfir.vhd, auk_dspip_avalon_streaming_source_hpfir.vhd, auk_dspip_roundsat_hpfir.vhd, altera_avalon_sc_fifo.v, demod_fir_0002_rtl_core.vhd, demod_fir_0002_ast.vhd, demod_fir_0002.vhd 103 | -------------------------------------------------------------------------------- /ipcores/cos_generator.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: cos_generator.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.0 Build 625 09/12/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module cos_generator ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [7:0] address; 45 | input clock; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [7:0] sub_wire0; 56 | wire [7:0] q = sub_wire0[7:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({8{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | `ifdef NO_PLI 87 | altsyncram_component.init_file = "./data/cos.rif" 88 | `else 89 | altsyncram_component.init_file = "./data/cos.hex" 90 | `endif 91 | , 92 | altsyncram_component.intended_device_family = "Cyclone IV E", 93 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 94 | altsyncram_component.lpm_type = "altsyncram", 95 | altsyncram_component.numwords_a = 256, 96 | altsyncram_component.operation_mode = "ROM", 97 | altsyncram_component.outdata_aclr_a = "NONE", 98 | altsyncram_component.outdata_reg_a = "CLOCK0", 99 | altsyncram_component.widthad_a = 8, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 115 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 119 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 120 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 121 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 122 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 123 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 124 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 125 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 126 | // Retrieval info: PRIVATE: MIFfilename STRING "./data/cos.hex" 127 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 128 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 129 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 130 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 131 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 132 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 133 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 134 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 135 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 136 | // Retrieval info: PRIVATE: rden NUMERIC "0" 137 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 138 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 139 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 140 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 141 | // Retrieval info: CONSTANT: INIT_FILE STRING "./data/cos.hex" 142 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 143 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 144 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 145 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 146 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 147 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 148 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 149 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 150 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 151 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 152 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 153 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 154 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 155 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 156 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 157 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.v TRUE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.inc FALSE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.cmp FALSE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator.bsf FALSE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator_inst.v FALSE 163 | // Retrieval info: GEN_FILE: TYPE_NORMAL cos_generator_bb.v TRUE 164 | // Retrieval info: LIB_FILE: altera_mf 165 | -------------------------------------------------------------------------------- /ipcores/sin_generator.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: sin_generator.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.0 Build 625 09/12/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module sin_generator ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [7:0] address; 45 | input clock; 46 | output [7:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [7:0] sub_wire0; 56 | wire [7:0] q = sub_wire0[7:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({8{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | `ifdef NO_PLI 87 | altsyncram_component.init_file = "./data/sin.rif" 88 | `else 89 | altsyncram_component.init_file = "./data/sin.hex" 90 | `endif 91 | , 92 | altsyncram_component.intended_device_family = "Cyclone IV E", 93 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 94 | altsyncram_component.lpm_type = "altsyncram", 95 | altsyncram_component.numwords_a = 256, 96 | altsyncram_component.operation_mode = "ROM", 97 | altsyncram_component.outdata_aclr_a = "NONE", 98 | altsyncram_component.outdata_reg_a = "CLOCK0", 99 | altsyncram_component.widthad_a = 8, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 115 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 119 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 120 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 121 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 122 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 123 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 124 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 125 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 126 | // Retrieval info: PRIVATE: MIFfilename STRING "./data/sin.hex" 127 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" 128 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 129 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 130 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 131 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 132 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 133 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 134 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" 135 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 136 | // Retrieval info: PRIVATE: rden NUMERIC "0" 137 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 138 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 139 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 140 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 141 | // Retrieval info: CONSTANT: INIT_FILE STRING "./data/sin.hex" 142 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 143 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 144 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 145 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 146 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 147 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 148 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 149 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 150 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 151 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 152 | // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" 153 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 154 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 155 | // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 156 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 157 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 158 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.v TRUE 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.inc FALSE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.cmp FALSE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator.bsf FALSE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator_inst.v FALSE 163 | // Retrieval info: GEN_FILE: TYPE_NORMAL sin_generator_bb.v TRUE 164 | // Retrieval info: LIB_FILE: altera_mf 165 | -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_msim.tcl: -------------------------------------------------------------------------------- 1 | ## ================================================================================ 2 | ## Legal Notice: Copyright (C) 1991-2020 Altera Corporation. All rights reserved. 3 | ## Any megafunction design, and related net list (encrypted or decrypted), 4 | ## support information, device programming or simulation file, and any other 5 | ## associated documentation or information provided by Altera or a partner 6 | ## under Altera's Megafunction Partnership Program may be used only to 7 | ## program PLD devices (but not masked PLD devices) from Altera. Any other 8 | ## use of such megafunction design, net list, support information, device 9 | ## programming or simulation file, or any other related documentation or 10 | ## information is prohibited for any other purpose, including, but not 11 | ## limited to modification, reverse engineering, de-compiling, or use with 12 | ## any other silicon devices, unless such use is explicitly licensed under 13 | ## a separate agreement with Altera or a megafunction partner. Title to 14 | ## the intellectual property, including patents, copyrights, trademarks, 15 | ## trade secrets, or maskworks, embodied in any such megafunction design, 16 | ## net list, support information, device programming or simulation file, or 17 | ## any other related documentation or information provided by Altera or a 18 | ## megafunction partner, remains with Altera, the megafunction partner, or 19 | ## their respective licensors. No other licenses, including any licenses 20 | ## needed under any third party's intellectual property, are provided herein. 21 | ## ================================================================================ 22 | ## 23 | 24 | transcript on 25 | write transcript demod_fir_transcript 26 | 27 | # START MEGAWIZARD INSERT VARIABLES 28 | set top_entity demod_fir 29 | set timing_resolution "1ps" 30 | set core_version 18.1 31 | set device_family "Cyclone IV E" 32 | set quartus_rootdir D:/program/quartus/quartus/ 33 | # Change to "gate_level" for gate-level sim 34 | set sim_type "rtl" 35 | # END MEGAWIZARD INSERT VARIABLES 36 | 37 | set q_sim_lib [file join $quartus_rootdir eda sim_lib] 38 | 39 | # Close existing ModelSim simulation 40 | quit -sim 41 | 42 | if {[file exists [file join simulation modelsim ${top_entity}.vo]] && [string match "gate_level" $sim_type]} { 43 | puts "Info: Gate Level ${top_entity}.vo found" 44 | set language_ext "vo" 45 | set use_ipfs 1 46 | set flow "gate_level" 47 | } elseif {[file exists [file join simulation modelsim ${top_entity}.vho]] && [string match "gate_level" $sim_type]} { 48 | puts "Info: Gate Level ${top_entity}.vho found" 49 | set language_ext "vho" 50 | set use_ipfs 1 51 | set flow "gate_level" 52 | } else { 53 | puts "Info: RTL simulation." 54 | set use_ipfs 0 55 | set flow "rtl" 56 | } 57 | 58 | if {[string match $flow "gate_level"] } { 59 | file copy ${top_entity}_input.txt simulation/modelsim 60 | cd simulation/modelsim 61 | } 62 | 63 | regsub {[ ]+} $device_family "" temp_device_family 64 | regsub {[ ]+} $temp_device_family "" temp_device_family2 65 | set device_lib_name [string tolower $temp_device_family2] 66 | 67 | set libs [list \ 68 | $device_lib_name \ 69 | altera \ 70 | work] 71 | 72 | foreach {lib} $libs { 73 | if {[file exist $lib]} { 74 | catch {eval "file delete -force -- $lib"} fid 75 | puts "file delete command returned $fid\n" 76 | } 77 | if {[file exist $lib] == 0} { 78 | vlib $lib 79 | vmap $lib $lib 80 | } 81 | } 82 | 83 | # RTL Simulation 84 | 85 | # Compile all required simulation library files 86 | set quartus_libs [list \ 87 | altera_mf {altera_mf_components altera_mf} {} {} "$q_sim_lib" \ 88 | lpm {220pack 220model} {220model} {} "$q_sim_lib" \ 89 | sgate {sgate_pack sgate} {sgate} {} "$q_sim_lib" \ 90 | altera_lnsim {altera_lnsim_components} {} {mentor/altera_lnsim_for_vhdl} "$q_sim_lib" \ 91 | twentynm {twentynm_atoms twentynm_components} {} {} "$q_sim_lib" \ 92 | ] 93 | foreach {lib file_vhdl_list file_verilog_list file_sysverilog_list src_files_loc} $quartus_libs { 94 | if {[file exist $lib]} { 95 | catch {eval "file delete -force -- $lib"} fid 96 | puts "file delete command returned $fid\n" 97 | } 98 | if {[file exist $lib] == 0} { 99 | vlib $lib 100 | vmap $lib $lib 101 | } 102 | foreach file_item $file_vhdl_list { 103 | catch {vcom -quiet -explicit -93 -work $lib [file join $src_files_loc ${file_item}.vhd]} err_msg 104 | if {![string match "" $err_msg]} {return $err_msg} 105 | } 106 | foreach file_item $file_verilog_list { 107 | catch {vlog -work $lib [file join $src_files_loc ${file_item}.v]} err_msg 108 | if {![string match "" $err_msg]} {return $err_msg} 109 | } 110 | foreach file_item $file_sysverilog_list { 111 | catch {vlog -work $lib [file join $src_files_loc ${file_item}.sv]} err_msg 112 | if {![string match "" $err_msg]} {return $err_msg} 113 | } 114 | } 115 | 116 | vcom -93 -work altera $q_sim_lib/altera_primitives_components.vhd 117 | vcom -93 -work altera $q_sim_lib/altera_primitives.vhd 118 | 119 | # Compile all FIR Compiler II RTL files 120 | vlog -work work altera_avalon_sc_fifo.v 121 | vcom -work work dspba_library_package.vhd 122 | vcom -work work dspba_library.vhd 123 | vcom -work work auk_dspip_roundsat_hpfir.vhd 124 | vcom -work work auk_dspip_math_pkg_hpfir.vhd 125 | vcom -work work auk_dspip_lib_pkg_hpfir.vhd 126 | vcom -work work auk_dspip_avalon_streaming_controller_hpfir.vhd 127 | vcom -work work auk_dspip_avalon_streaming_sink_hpfir.vhd 128 | vcom -work work auk_dspip_avalon_streaming_source_hpfir.vhd 129 | 130 | set file_list [glob ${top_entity}_rtl*.vhd] 131 | foreach cur_file $file_list { 132 | vcom -work work $cur_file 133 | } 134 | 135 | vcom -work work ${top_entity}_ast.vhd 136 | vcom -work work ${top_entity}.vhd 137 | 138 | vcom -93 -work work ${top_entity}_tb.vhd 139 | 140 | 141 | # Prepare simulation command 142 | 143 | set vsim_cmd vsim 144 | 145 | if {[string match $flow "rtl"]} { 146 | lappend vsim_cmd "-L" "$device_lib_name" "-L" "altera_mf" "-L" "lpm" "-L" "sgate" "-L" "altera" "-L" "altera_lnsim" "-L" "work" 147 | } else { 148 | lappend vsim_cmd "-L" "$device_lib_name" "-L" "altera" "-L" "work" 149 | if {[string match $language_ext "vho"]} { 150 | if {[file exists ${top_entity}_vhd.sdo]} { 151 | lappend vsim_cmd "-sdftyp" "/${top_entity}_tb/DUT=${top_entity}_vhd.sdo"} 152 | } 153 | if {[string match $language_ext "vo"]} { 154 | if {[file exists ${top_entity}_v.sdo]} { 155 | lappend vsim_cmd "-sdftyp" "/${top_entity}_tb/DUT=${top_entity}_v.sdo"} 156 | } 157 | } 158 | 159 | lappend vsim_cmd "work.${top_entity}_tb" "-t" "$timing_resolution" 160 | 161 | catch { eval $vsim_cmd } vsim_msg 162 | puts $vsim_msg 163 | 164 | if {[file exists "wave.do"]} { 165 | do wave.do 166 | } else { 167 | add wave sim:/${top_entity}_tb/* 168 | } 169 | 170 | # Start simulation silently 171 | 172 | set StdArithNoWarnings 1 173 | run 0 ns 174 | set StdArithNoWarnings 0 175 | catch {run -all} run_msg 176 | puts $run_msg 177 | -------------------------------------------------------------------------------- /demod_fir/auk_dspip_roundsat_hpfir.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files from any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Intel Program License Subscription 7 | -- Agreement, Intel FPGA IP License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | ------------------------------------------------------------------------- 15 | ------------------------------------------------------------------------- 16 | -- 17 | -- Revision Control Information 18 | -- 19 | -- $RCSfile: auk_dspip_roundsat_hpfir.vhd,v $ 20 | -- 21 | -- $Revision: #1 $ 22 | -- $Date: 2010/08/19 $ 23 | -- Check in by : $Author: max $ 24 | -- 25 | -- Description : 26 | -- Implement output options for HP-FIR 27 | -- 28 | -- ALTERA Confidential and Proprietary 29 | -- Copyright 2006 (c) Altera Corporation 30 | -- All rights reserved 31 | -- 32 | ------------------------------------------------------------------------- 33 | ------------------------------------------------------------------------- 34 | library ieee; 35 | use ieee.std_logic_1164.all; 36 | use ieee.numeric_std.all; 37 | 38 | 39 | entity auk_dspip_roundsat_hpfir is 40 | generic ( 41 | IN_WIDTH_g : natural := 8; -- i/p data width 42 | REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed 43 | REM_LSB_TYPE_g : string := "trunc"; -- trunc/round 44 | REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed 45 | REM_MSB_TYPE_g : string := "trunc" -- trunc/sat 46 | ); 47 | port ( 48 | clk : in std_logic; 49 | reset_n : in std_logic; 50 | enable : in std_logic; 51 | datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); 52 | valid : out std_logic; 53 | dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0) 54 | ); 55 | end entity auk_dspip_roundsat_hpfir; 56 | 57 | architecture beh of auk_dspip_roundsat_hpfir is 58 | 59 | signal data_lsb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-1 downto 0); 60 | signal valid_lsb : std_logic; 61 | 62 | signal data_msb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 63 | 64 | constant zero_vec : std_logic_vector := std_logic_vector(to_signed(0, REM_LSB_BIT_g)); 65 | 66 | begin -- architecture beh 67 | 68 | ----------------------------------------------------------------------------- 69 | -- lsb : trunc/round-up (symmetric) 70 | ----------------------------------------------------------------------------- 71 | remove_lsb: if REM_LSB_BIT_g > 0 generate 72 | begin 73 | trunc_lsb: if REM_LSB_TYPE_g = "trunc" generate 74 | begin 75 | data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); 76 | valid_lsb <= enable; 77 | end generate trunc_lsb; 78 | rndup_lsb: if REM_LSB_TYPE_g = "round" generate 79 | round_up_sym_p : process (clk, reset_n) 80 | variable OR_accu : std_logic := '0'; 81 | begin 82 | if reset_n = '0' then 83 | data_lsb <= (others => '0'); 84 | valid_lsb <= '0'; 85 | elsif rising_edge(clk) then 86 | if enable = '1' then 87 | OR_accu := '0'; 88 | for i in 0 to REM_LSB_BIT_g-2 loop 89 | OR_accu := OR_accu or datain(i); 90 | end loop; 91 | -- negative value 92 | if (datain(IN_WIDTH_g-1) = '1') then 93 | -- larger than -x.5 : rounded to -x 94 | if (datain(REM_LSB_BIT_g-1)='1' and OR_accu='1') then 95 | data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1); 96 | -- less than or equal -x.5 : rounded to -x + 1 97 | else 98 | data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); 99 | end if; 100 | -- positive value 101 | else 102 | -- maximum positive value 103 | if datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g-1) = std_logic_vector(to_signed(2**(IN_WIDTH_g-REM_LSB_BIT_g)-1, IN_WIDTH_g-REM_LSB_BIT_g+1)) then 104 | data_lsb <= std_logic_vector(to_signed( 2**(IN_WIDTH_g-REM_LSB_BIT_g-1)-1, IN_WIDTH_g-REM_LSB_BIT_g)); 105 | -- larger than or equal x.5 : rounded to x + 1 106 | elsif datain(REM_LSB_BIT_g-1) = '1' then 107 | data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1); 108 | -- less than x.5 : rounded to x 109 | else 110 | data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); 111 | end if; 112 | end if; 113 | end if; 114 | valid_lsb <= enable; 115 | end if; 116 | end process round_up_sym_p; 117 | end generate rndup_lsb; 118 | end generate remove_lsb; 119 | 120 | ----------------------------------------------------------------------------- 121 | -- keep lsb 122 | ----------------------------------------------------------------------------- 123 | keep_lsb: if REM_LSB_BIT_g = 0 generate 124 | begin 125 | data_lsb <= datain; 126 | valid_lsb <= enable; 127 | end generate keep_lsb; 128 | 129 | ----------------------------------------------------------------------------- 130 | -- msb : trunc/saturation 131 | ----------------------------------------------------------------------------- 132 | remove_msb: if REM_MSB_BIT_g > 0 generate 133 | signal min_val, max_val : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 134 | begin 135 | trunc_msb: if REM_MSB_TYPE_g = "trunc" generate 136 | begin 137 | data_msb <= data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 138 | dataout <= data_msb; 139 | valid <= valid_lsb; 140 | end generate trunc_msb; 141 | 142 | sat_msb: if REM_MSB_TYPE_g = "sat" generate 143 | max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '0'; 144 | max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '1'); 145 | min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '1'; 146 | min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '0'); 147 | data_msb <= std_logic_vector(max_val) when signed(data_lsb) > signed(max_val) else 148 | std_logic_vector(min_val) when signed(data_lsb) < signed(min_val) else 149 | data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 150 | msb_p : process (clk, reset_n) 151 | begin 152 | if reset_n = '0' then 153 | dataout <= (others => '0'); 154 | valid <= '0'; 155 | elsif rising_edge(clk) then 156 | if valid_lsb = '1' then 157 | dataout <= data_msb; 158 | end if; 159 | valid <= valid_lsb; 160 | end if; 161 | end process msb_p; 162 | end generate sat_msb; 163 | end generate remove_msb; 164 | 165 | ----------------------------------------------------------------------------- 166 | -- keep msb 167 | ----------------------------------------------------------------------------- 168 | keep_msb: if REM_MSB_BIT_g = 0 generate 169 | begin 170 | data_msb <= data_lsb; 171 | dataout <= data_msb; 172 | valid <= valid_lsb; 173 | end generate keep_msb; 174 | 175 | ----------------------------------------------------------------------------- 176 | -- error checking: 177 | -- Have we got a valid round mode? 178 | -- Is the input greater than the output? 179 | ----------------------------------------------------------------------------- 180 | assert (REM_LSB_TYPE_g = "trunc" or 181 | REM_LSB_TYPE_g = "round" or 182 | REM_MSB_TYPE_g = "trunc" or 183 | REM_MSB_TYPE_g = "sat" 184 | ) report "Please check your round type and its spelling. Currently, we only support trunc, and round for LSB, trunc and sat for MSB" severity error; 185 | 186 | 187 | end architecture beh; 188 | -------------------------------------------------------------------------------- /demod_fir_sim/auk_dspip_roundsat_hpfir.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2018 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files from any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Intel Program License Subscription 7 | -- Agreement, Intel FPGA IP License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | ------------------------------------------------------------------------- 15 | ------------------------------------------------------------------------- 16 | -- 17 | -- Revision Control Information 18 | -- 19 | -- $RCSfile: auk_dspip_roundsat_hpfir.vhd,v $ 20 | -- 21 | -- $Revision: #1 $ 22 | -- $Date: 2010/08/19 $ 23 | -- Check in by : $Author: max $ 24 | -- 25 | -- Description : 26 | -- Implement output options for HP-FIR 27 | -- 28 | -- ALTERA Confidential and Proprietary 29 | -- Copyright 2006 (c) Altera Corporation 30 | -- All rights reserved 31 | -- 32 | ------------------------------------------------------------------------- 33 | ------------------------------------------------------------------------- 34 | library ieee; 35 | use ieee.std_logic_1164.all; 36 | use ieee.numeric_std.all; 37 | 38 | 39 | entity auk_dspip_roundsat_hpfir is 40 | generic ( 41 | IN_WIDTH_g : natural := 8; -- i/p data width 42 | REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed 43 | REM_LSB_TYPE_g : string := "trunc"; -- trunc/round 44 | REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed 45 | REM_MSB_TYPE_g : string := "trunc" -- trunc/sat 46 | ); 47 | port ( 48 | clk : in std_logic; 49 | reset_n : in std_logic; 50 | enable : in std_logic; 51 | datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); 52 | valid : out std_logic; 53 | dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0) 54 | ); 55 | end entity auk_dspip_roundsat_hpfir; 56 | 57 | architecture beh of auk_dspip_roundsat_hpfir is 58 | 59 | signal data_lsb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-1 downto 0); 60 | signal valid_lsb : std_logic; 61 | 62 | signal data_msb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 63 | 64 | constant zero_vec : std_logic_vector := std_logic_vector(to_signed(0, REM_LSB_BIT_g)); 65 | 66 | begin -- architecture beh 67 | 68 | ----------------------------------------------------------------------------- 69 | -- lsb : trunc/round-up (symmetric) 70 | ----------------------------------------------------------------------------- 71 | remove_lsb: if REM_LSB_BIT_g > 0 generate 72 | begin 73 | trunc_lsb: if REM_LSB_TYPE_g = "trunc" generate 74 | begin 75 | data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); 76 | valid_lsb <= enable; 77 | end generate trunc_lsb; 78 | rndup_lsb: if REM_LSB_TYPE_g = "round" generate 79 | round_up_sym_p : process (clk, reset_n) 80 | variable OR_accu : std_logic := '0'; 81 | begin 82 | if reset_n = '0' then 83 | data_lsb <= (others => '0'); 84 | valid_lsb <= '0'; 85 | elsif rising_edge(clk) then 86 | if enable = '1' then 87 | OR_accu := '0'; 88 | for i in 0 to REM_LSB_BIT_g-2 loop 89 | OR_accu := OR_accu or datain(i); 90 | end loop; 91 | -- negative value 92 | if (datain(IN_WIDTH_g-1) = '1') then 93 | -- larger than -x.5 : rounded to -x 94 | if (datain(REM_LSB_BIT_g-1)='1' and OR_accu='1') then 95 | data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1); 96 | -- less than or equal -x.5 : rounded to -x + 1 97 | else 98 | data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); 99 | end if; 100 | -- positive value 101 | else 102 | -- maximum positive value 103 | if datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g-1) = std_logic_vector(to_signed(2**(IN_WIDTH_g-REM_LSB_BIT_g)-1, IN_WIDTH_g-REM_LSB_BIT_g+1)) then 104 | data_lsb <= std_logic_vector(to_signed( 2**(IN_WIDTH_g-REM_LSB_BIT_g-1)-1, IN_WIDTH_g-REM_LSB_BIT_g)); 105 | -- larger than or equal x.5 : rounded to x + 1 106 | elsif datain(REM_LSB_BIT_g-1) = '1' then 107 | data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1); 108 | -- less than x.5 : rounded to x 109 | else 110 | data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); 111 | end if; 112 | end if; 113 | end if; 114 | valid_lsb <= enable; 115 | end if; 116 | end process round_up_sym_p; 117 | end generate rndup_lsb; 118 | end generate remove_lsb; 119 | 120 | ----------------------------------------------------------------------------- 121 | -- keep lsb 122 | ----------------------------------------------------------------------------- 123 | keep_lsb: if REM_LSB_BIT_g = 0 generate 124 | begin 125 | data_lsb <= datain; 126 | valid_lsb <= enable; 127 | end generate keep_lsb; 128 | 129 | ----------------------------------------------------------------------------- 130 | -- msb : trunc/saturation 131 | ----------------------------------------------------------------------------- 132 | remove_msb: if REM_MSB_BIT_g > 0 generate 133 | signal min_val, max_val : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 134 | begin 135 | trunc_msb: if REM_MSB_TYPE_g = "trunc" generate 136 | begin 137 | data_msb <= data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 138 | dataout <= data_msb; 139 | valid <= valid_lsb; 140 | end generate trunc_msb; 141 | 142 | sat_msb: if REM_MSB_TYPE_g = "sat" generate 143 | max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '0'; 144 | max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '1'); 145 | min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '1'; 146 | min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '0'); 147 | data_msb <= std_logic_vector(max_val) when signed(data_lsb) > signed(max_val) else 148 | std_logic_vector(min_val) when signed(data_lsb) < signed(min_val) else 149 | data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 150 | msb_p : process (clk, reset_n) 151 | begin 152 | if reset_n = '0' then 153 | dataout <= (others => '0'); 154 | valid <= '0'; 155 | elsif rising_edge(clk) then 156 | if valid_lsb = '1' then 157 | dataout <= data_msb; 158 | end if; 159 | valid <= valid_lsb; 160 | end if; 161 | end process msb_p; 162 | end generate sat_msb; 163 | end generate remove_msb; 164 | 165 | ----------------------------------------------------------------------------- 166 | -- keep msb 167 | ----------------------------------------------------------------------------- 168 | keep_msb: if REM_MSB_BIT_g = 0 generate 169 | begin 170 | data_msb <= data_lsb; 171 | dataout <= data_msb; 172 | valid <= valid_lsb; 173 | end generate keep_msb; 174 | 175 | ----------------------------------------------------------------------------- 176 | -- error checking: 177 | -- Have we got a valid round mode? 178 | -- Is the input greater than the output? 179 | ----------------------------------------------------------------------------- 180 | assert (REM_LSB_TYPE_g = "trunc" or 181 | REM_LSB_TYPE_g = "round" or 182 | REM_MSB_TYPE_g = "trunc" or 183 | REM_MSB_TYPE_g = "sat" 184 | ) report "Please check your round type and its spelling. Currently, we only support trunc, and round for LSB, trunc and sat for MSB" severity error; 185 | 186 | 187 | end architecture beh; 188 | -------------------------------------------------------------------------------- /demod_fir_sim/demod_fir_ast.vhd: -------------------------------------------------------------------------------- 1 | 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | use work.auk_dspip_lib_pkg_hpfir.all; 7 | use work.auk_dspip_math_pkg_hpfir.all; 8 | 9 | entity demod_fir_ast is 10 | generic ( 11 | INWIDTH : integer := 8; 12 | OUT_WIDTH_UNTRIMMED : integer := 20; 13 | BANKINWIDTH : integer := 0; 14 | REM_LSB_BIT_g : integer := 0; 15 | REM_LSB_TYPE_g : string := "trunc"; 16 | REM_MSB_BIT_g : integer := 0; 17 | REM_MSB_TYPE_g : string := "trunc"; 18 | PHYSCHANIN : integer := 1; 19 | PHYSCHANOUT : integer := 1; 20 | CHANSPERPHYIN : natural := 1; 21 | CHANSPERPHYOUT : natural := 1; 22 | OUTPUTFIFODEPTH : integer := 8; 23 | USE_PACKETS : integer := 0; 24 | MODE_WIDTH : integer := 0; 25 | ENABLE_BACKPRESSURE : boolean := false; 26 | LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1); 27 | NUMCHANS : integer := 1; 28 | DEVICE_FAMILY : string := "Cyclone IV E"; 29 | COMPLEX_CONST : integer := 1 30 | ); 31 | port( 32 | clk : in std_logic; 33 | reset_n : in std_logic; 34 | ast_sink_ready : out std_logic; 35 | ast_source_data : out std_logic_vector(COMPLEX_CONST*(OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0); 36 | ast_sink_data : in std_logic_vector( COMPLEX_CONST*(INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); 37 | ast_sink_valid : in std_logic; 38 | ast_source_valid : out std_logic; 39 | ast_source_ready : in std_logic; 40 | ast_source_eop : out std_logic; 41 | ast_source_sop : out std_logic; 42 | ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0); 43 | ast_sink_eop : in std_logic; 44 | ast_sink_sop : in std_logic; 45 | ast_sink_error : in std_logic_vector (1 downto 0); 46 | ast_source_error : out std_logic_vector (1 downto 0) 47 | ); 48 | attribute altera_attribute : string; 49 | attribute altera_attribute of demod_fir_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036"; 50 | end demod_fir_ast; 51 | 52 | -- Warnings Suppression On 53 | -- altera message_off 10036 54 | 55 | architecture struct of demod_fir_ast is 56 | 57 | constant OUTWIDTH : integer := OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g; 58 | 59 | signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0); 60 | 61 | signal core_channel_out : std_logic_vector(2 -1 downto 0); 62 | signal at_source_channel : std_logic_vector(2 -1 downto 0); 63 | signal sink_packet_error : std_logic_vector(1 downto 0); 64 | signal data_in : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); 65 | signal data_valid : std_logic_vector(0 downto 0); 66 | 67 | signal data_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT -1 downto 0); 68 | signal reset_fir : std_logic; 69 | signal sink_ready_ctrl : std_logic; 70 | signal source_packet_error : std_logic_vector(1 downto 0); 71 | signal source_stall : std_logic; 72 | signal source_valid_ctrl : std_logic; 73 | signal stall : std_logic; 74 | signal valid : std_logic; 75 | signal core_valid : std_logic; 76 | signal enable_in : std_logic_vector(0 downto 0); 77 | 78 | signal outp_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT - 1 downto 0); 79 | signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0); 80 | 81 | signal core_out : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0); 82 | signal core_out_valid : std_logic_vector(0 downto 0); 83 | signal core_out_channel : std_logic_vector(7 downto 0); 84 | 85 | signal core_out_channel_0 : std_logic_vector(7 downto 0); 86 | 87 | 88 | begin 89 | sink : auk_dspip_avalon_streaming_sink_hpfir 90 | generic map ( 91 | WIDTH_g => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH, 92 | DATA_WIDTH => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH, 93 | DATA_PORT_COUNT => 1, 94 | PACKET_SIZE_g => CHANSPERPHYIN) 95 | port map ( 96 | clk => clk, 97 | reset_n => reset_n, 98 | data => data_in, 99 | data_valid => data_valid, 100 | sink_ready_ctrl => sink_ready_ctrl, 101 | packet_error => sink_packet_error, 102 | at_sink_ready => ast_sink_ready, 103 | at_sink_valid => ast_sink_valid, 104 | at_sink_data => ast_sink_data, 105 | at_sink_sop => ast_sink_sop, 106 | at_sink_eop => ast_sink_eop, 107 | at_sink_error => ast_sink_error); 108 | 109 | source : auk_dspip_avalon_streaming_source_hpfir 110 | generic map ( 111 | WIDTH_g => COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT, 112 | DATA_WIDTH => COMPLEX_CONST*OUTWIDTH, 113 | DATA_PORT_COUNT => PHYSCHANOUT, 114 | FIFO_DEPTH_g => OUTPUTFIFODEPTH, 115 | USE_PACKETS => USE_PACKETS, 116 | HAVE_COUNTER_g => false, 117 | PACKET_SIZE_g => CHANSPERPHYOUT, 118 | COUNTER_LIMIT_g => CHANSPERPHYOUT, 119 | ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE) 120 | port map ( 121 | clk => clk, 122 | reset_n => reset_n, 123 | data_in => data_out, 124 | data_count => channel_out, 125 | source_valid_ctrl => source_valid_ctrl, 126 | source_stall => source_stall, 127 | packet_error => source_packet_error, 128 | at_source_ready => ast_source_ready, 129 | at_source_valid => ast_source_valid, 130 | at_source_data => ast_source_data, 131 | at_source_channel => ast_source_channel, 132 | at_source_sop => ast_source_sop, 133 | at_source_eop => ast_source_eop, 134 | at_source_error => ast_source_error); 135 | 136 | 137 | intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir 138 | port map ( 139 | clk => clk, 140 | reset_n => reset_n, 141 | sink_packet_error => sink_packet_error, 142 | source_stall => source_stall, 143 | valid => valid, 144 | reset_design => reset_fir, 145 | sink_ready_ctrl => sink_ready_ctrl, 146 | source_packet_error => source_packet_error, 147 | source_valid_ctrl => source_valid_ctrl, 148 | stall => stall); 149 | 150 | 151 | 152 | multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate 153 | data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)); 154 | end generate multi_data_out; 155 | 156 | channel_pipe_lsb: if REM_LSB_TYPE_g = "round" and REM_LSB_BIT_g > 0 generate 157 | begin 158 | out_lsb_p : process (clk, reset_n) 159 | begin 160 | if reset_n = '0' then 161 | core_out_channel_0 <= (others => '0'); 162 | elsif rising_edge(clk) then 163 | core_out_channel_0 <= core_out_channel; 164 | end if; 165 | end process out_lsb_p; 166 | end generate channel_pipe_lsb; 167 | 168 | channel_wire_lsb: if REM_LSB_TYPE_g = "trunc" or REM_LSB_BIT_g = 0 generate 169 | begin 170 | core_out_channel_0 <= core_out_channel; 171 | end generate channel_wire_lsb; 172 | 173 | channel_pipe_msb: if REM_MSB_TYPE_g = "sat" and REM_MSB_BIT_g > 0 generate 174 | begin 175 | out_p : process (clk, reset_n) 176 | begin 177 | if reset_n = '0' then 178 | channel_out <= (others => '0'); 179 | elsif rising_edge(clk) then 180 | channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0); 181 | end if; 182 | end process out_p; 183 | end generate channel_pipe_msb; 184 | 185 | channel_wire_msb: if REM_MSB_TYPE_g = "trunc" or REM_MSB_BIT_g = 0 generate 186 | begin 187 | channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0); 188 | end generate channel_wire_msb; 189 | 190 | 191 | real_passthrough : if COMPLEX_CONST = 1 generate 192 | 193 | component demod_fir_rtl_core is 194 | port ( 195 | xIn_v : in std_logic_vector(0 downto 0); 196 | xIn_c : in std_logic_vector(7 downto 0); 197 | xIn_0 : in std_logic_vector(8 - 1 downto 0); 198 | xOut_v : out std_logic_vector(0 downto 0); 199 | xOut_c : out std_logic_vector(7 downto 0); 200 | xOut_0 : out std_logic_vector(20- 1 downto 0); 201 | clk : in std_logic; 202 | areset : in std_logic 203 | ); 204 | end component demod_fir_rtl_core; 205 | 206 | 207 | --Complex data re-ordering 208 | signal core_channel_out_core : std_logic_vector(2 -1 downto 0); 209 | signal data_in_core : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); 210 | signal data_valid_core : std_logic_vector(0 downto 0); 211 | signal core_out_core : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0); 212 | signal core_out_valid_core : std_logic_vector(0 downto 0); 213 | signal core_out_channel_core : std_logic_vector(7 downto 0); 214 | 215 | 216 | 217 | begin 218 | hpfircore_core: demod_fir_rtl_core 219 | port map ( 220 | xIn_v => data_valid_core, 221 | xIn_c => "00000000", 222 | xIn_0 => data_in_core((0 + 8) * 0 + 8 - 1 downto (0 + 8) * 0), 223 | xOut_v => core_out_valid_core, 224 | xOut_c => core_out_channel_core, 225 | xOut_0 => core_out_core(20* 0 + 20- 1 downto 20* 0), 226 | clk => clk, 227 | areset => reset_fir 228 | ); 229 | 230 | 231 | 232 | 233 | core_channel_out <= core_channel_out_core; 234 | data_in_core <= data_in; 235 | data_valid_core <= data_valid; 236 | core_out <= core_out_core; 237 | core_out_valid(0) <= core_out_valid_core(0); 238 | core_out_channel <= core_out_channel_core; 239 | 240 | 241 | 242 | gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate 243 | begin 244 | outp_blk : auk_dspip_roundsat_hpfir 245 | generic map ( 246 | IN_WIDTH_g => OUT_WIDTH_UNTRIMMED , 247 | REM_LSB_BIT_g => REM_LSB_BIT_g , 248 | REM_LSB_TYPE_g => REM_LSB_TYPE_g , 249 | REM_MSB_BIT_g => REM_MSB_BIT_g , 250 | REM_MSB_TYPE_g => REM_MSB_TYPE_g 251 | ) 252 | port map ( 253 | clk => clk, 254 | reset_n => reset_n, 255 | enable => core_out_valid(0), 256 | datain => core_out(((i*OUT_WIDTH_UNTRIMMED)+OUT_WIDTH_UNTRIMMED-1) downto (i*OUT_WIDTH_UNTRIMMED)), 257 | valid => outp_blk_valid(i), 258 | dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH)) 259 | ); 260 | end generate gen_outp_blk; 261 | end generate real_passthrough; 262 | 263 | 264 | 265 | valid <= outp_blk_valid(0); 266 | 267 | enable_in(0) <= not stall; 268 | 269 | end struct; 270 | 271 | 272 | 273 | 274 | -------------------------------------------------------------------------------- /demod_fir/demod_fir_0002_ast.vhd: -------------------------------------------------------------------------------- 1 | 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | 6 | use work.auk_dspip_lib_pkg_hpfir.all; 7 | use work.auk_dspip_math_pkg_hpfir.all; 8 | 9 | entity demod_fir_0002_ast is 10 | generic ( 11 | INWIDTH : integer := 8; 12 | OUT_WIDTH_UNTRIMMED : integer := 20; 13 | BANKINWIDTH : integer := 0; 14 | REM_LSB_BIT_g : integer := 0; 15 | REM_LSB_TYPE_g : string := "trunc"; 16 | REM_MSB_BIT_g : integer := 0; 17 | REM_MSB_TYPE_g : string := "trunc"; 18 | PHYSCHANIN : integer := 1; 19 | PHYSCHANOUT : integer := 1; 20 | CHANSPERPHYIN : natural := 1; 21 | CHANSPERPHYOUT : natural := 1; 22 | OUTPUTFIFODEPTH : integer := 8; 23 | USE_PACKETS : integer := 0; 24 | MODE_WIDTH : integer := 0; 25 | ENABLE_BACKPRESSURE : boolean := false; 26 | LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1); 27 | NUMCHANS : integer := 1; 28 | DEVICE_FAMILY : string := "Cyclone IV E"; 29 | COMPLEX_CONST : integer := 1 30 | ); 31 | port( 32 | clk : in std_logic; 33 | reset_n : in std_logic; 34 | ast_sink_ready : out std_logic; 35 | ast_source_data : out std_logic_vector(COMPLEX_CONST*(OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0); 36 | ast_sink_data : in std_logic_vector( COMPLEX_CONST*(INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); 37 | ast_sink_valid : in std_logic; 38 | ast_source_valid : out std_logic; 39 | ast_source_ready : in std_logic; 40 | ast_source_eop : out std_logic; 41 | ast_source_sop : out std_logic; 42 | ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0); 43 | ast_sink_eop : in std_logic; 44 | ast_sink_sop : in std_logic; 45 | ast_sink_error : in std_logic_vector (1 downto 0); 46 | ast_source_error : out std_logic_vector (1 downto 0) 47 | ); 48 | attribute altera_attribute : string; 49 | attribute altera_attribute of demod_fir_0002_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036"; 50 | end demod_fir_0002_ast; 51 | 52 | -- Warnings Suppression On 53 | -- altera message_off 10036 54 | 55 | architecture struct of demod_fir_0002_ast is 56 | 57 | constant OUTWIDTH : integer := OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g; 58 | 59 | signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0); 60 | 61 | signal core_channel_out : std_logic_vector(2 -1 downto 0); 62 | signal at_source_channel : std_logic_vector(2 -1 downto 0); 63 | signal sink_packet_error : std_logic_vector(1 downto 0); 64 | signal data_in : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); 65 | signal data_valid : std_logic_vector(0 downto 0); 66 | 67 | signal data_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT -1 downto 0); 68 | signal reset_fir : std_logic; 69 | signal sink_ready_ctrl : std_logic; 70 | signal source_packet_error : std_logic_vector(1 downto 0); 71 | signal source_stall : std_logic; 72 | signal source_valid_ctrl : std_logic; 73 | signal stall : std_logic; 74 | signal valid : std_logic; 75 | signal core_valid : std_logic; 76 | signal enable_in : std_logic_vector(0 downto 0); 77 | 78 | signal outp_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT - 1 downto 0); 79 | signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0); 80 | 81 | signal core_out : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0); 82 | signal core_out_valid : std_logic_vector(0 downto 0); 83 | signal core_out_channel : std_logic_vector(7 downto 0); 84 | 85 | signal core_out_channel_0 : std_logic_vector(7 downto 0); 86 | 87 | 88 | begin 89 | sink : auk_dspip_avalon_streaming_sink_hpfir 90 | generic map ( 91 | WIDTH_g => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH, 92 | DATA_WIDTH => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH, 93 | DATA_PORT_COUNT => 1, 94 | PACKET_SIZE_g => CHANSPERPHYIN) 95 | port map ( 96 | clk => clk, 97 | reset_n => reset_n, 98 | data => data_in, 99 | data_valid => data_valid, 100 | sink_ready_ctrl => sink_ready_ctrl, 101 | packet_error => sink_packet_error, 102 | at_sink_ready => ast_sink_ready, 103 | at_sink_valid => ast_sink_valid, 104 | at_sink_data => ast_sink_data, 105 | at_sink_sop => ast_sink_sop, 106 | at_sink_eop => ast_sink_eop, 107 | at_sink_error => ast_sink_error); 108 | 109 | source : auk_dspip_avalon_streaming_source_hpfir 110 | generic map ( 111 | WIDTH_g => COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT, 112 | DATA_WIDTH => COMPLEX_CONST*OUTWIDTH, 113 | DATA_PORT_COUNT => PHYSCHANOUT, 114 | FIFO_DEPTH_g => OUTPUTFIFODEPTH, 115 | USE_PACKETS => USE_PACKETS, 116 | HAVE_COUNTER_g => false, 117 | PACKET_SIZE_g => CHANSPERPHYOUT, 118 | COUNTER_LIMIT_g => CHANSPERPHYOUT, 119 | ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE) 120 | port map ( 121 | clk => clk, 122 | reset_n => reset_n, 123 | data_in => data_out, 124 | data_count => channel_out, 125 | source_valid_ctrl => source_valid_ctrl, 126 | source_stall => source_stall, 127 | packet_error => source_packet_error, 128 | at_source_ready => ast_source_ready, 129 | at_source_valid => ast_source_valid, 130 | at_source_data => ast_source_data, 131 | at_source_channel => ast_source_channel, 132 | at_source_sop => ast_source_sop, 133 | at_source_eop => ast_source_eop, 134 | at_source_error => ast_source_error); 135 | 136 | 137 | intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir 138 | port map ( 139 | clk => clk, 140 | reset_n => reset_n, 141 | sink_packet_error => sink_packet_error, 142 | source_stall => source_stall, 143 | valid => valid, 144 | reset_design => reset_fir, 145 | sink_ready_ctrl => sink_ready_ctrl, 146 | source_packet_error => source_packet_error, 147 | source_valid_ctrl => source_valid_ctrl, 148 | stall => stall); 149 | 150 | 151 | 152 | multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate 153 | data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)); 154 | end generate multi_data_out; 155 | 156 | channel_pipe_lsb: if REM_LSB_TYPE_g = "round" and REM_LSB_BIT_g > 0 generate 157 | begin 158 | out_lsb_p : process (clk, reset_n) 159 | begin 160 | if reset_n = '0' then 161 | core_out_channel_0 <= (others => '0'); 162 | elsif rising_edge(clk) then 163 | core_out_channel_0 <= core_out_channel; 164 | end if; 165 | end process out_lsb_p; 166 | end generate channel_pipe_lsb; 167 | 168 | channel_wire_lsb: if REM_LSB_TYPE_g = "trunc" or REM_LSB_BIT_g = 0 generate 169 | begin 170 | core_out_channel_0 <= core_out_channel; 171 | end generate channel_wire_lsb; 172 | 173 | channel_pipe_msb: if REM_MSB_TYPE_g = "sat" and REM_MSB_BIT_g > 0 generate 174 | begin 175 | out_p : process (clk, reset_n) 176 | begin 177 | if reset_n = '0' then 178 | channel_out <= (others => '0'); 179 | elsif rising_edge(clk) then 180 | channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0); 181 | end if; 182 | end process out_p; 183 | end generate channel_pipe_msb; 184 | 185 | channel_wire_msb: if REM_MSB_TYPE_g = "trunc" or REM_MSB_BIT_g = 0 generate 186 | begin 187 | channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0); 188 | end generate channel_wire_msb; 189 | 190 | 191 | real_passthrough : if COMPLEX_CONST = 1 generate 192 | 193 | component demod_fir_0002_rtl_core is 194 | port ( 195 | xIn_v : in std_logic_vector(0 downto 0); 196 | xIn_c : in std_logic_vector(7 downto 0); 197 | xIn_0 : in std_logic_vector(8 - 1 downto 0); 198 | xOut_v : out std_logic_vector(0 downto 0); 199 | xOut_c : out std_logic_vector(7 downto 0); 200 | xOut_0 : out std_logic_vector(20- 1 downto 0); 201 | clk : in std_logic; 202 | areset : in std_logic 203 | ); 204 | end component demod_fir_0002_rtl_core; 205 | 206 | 207 | --Complex data re-ordering 208 | signal core_channel_out_core : std_logic_vector(2 -1 downto 0); 209 | signal data_in_core : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); 210 | signal data_valid_core : std_logic_vector(0 downto 0); 211 | signal core_out_core : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0); 212 | signal core_out_valid_core : std_logic_vector(0 downto 0); 213 | signal core_out_channel_core : std_logic_vector(7 downto 0); 214 | 215 | 216 | 217 | begin 218 | hpfircore_core: demod_fir_0002_rtl_core 219 | port map ( 220 | xIn_v => data_valid_core, 221 | xIn_c => "00000000", 222 | xIn_0 => data_in_core((0 + 8) * 0 + 8 - 1 downto (0 + 8) * 0), 223 | xOut_v => core_out_valid_core, 224 | xOut_c => core_out_channel_core, 225 | xOut_0 => core_out_core(20* 0 + 20- 1 downto 20* 0), 226 | clk => clk, 227 | areset => reset_fir 228 | ); 229 | 230 | 231 | 232 | 233 | core_channel_out <= core_channel_out_core; 234 | data_in_core <= data_in; 235 | data_valid_core <= data_valid; 236 | core_out <= core_out_core; 237 | core_out_valid(0) <= core_out_valid_core(0); 238 | core_out_channel <= core_out_channel_core; 239 | 240 | 241 | 242 | gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate 243 | begin 244 | outp_blk : auk_dspip_roundsat_hpfir 245 | generic map ( 246 | IN_WIDTH_g => OUT_WIDTH_UNTRIMMED , 247 | REM_LSB_BIT_g => REM_LSB_BIT_g , 248 | REM_LSB_TYPE_g => REM_LSB_TYPE_g , 249 | REM_MSB_BIT_g => REM_MSB_BIT_g , 250 | REM_MSB_TYPE_g => REM_MSB_TYPE_g 251 | ) 252 | port map ( 253 | clk => clk, 254 | reset_n => reset_n, 255 | enable => core_out_valid(0), 256 | datain => core_out(((i*OUT_WIDTH_UNTRIMMED)+OUT_WIDTH_UNTRIMMED-1) downto (i*OUT_WIDTH_UNTRIMMED)), 257 | valid => outp_blk_valid(i), 258 | dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH)) 259 | ); 260 | end generate gen_outp_blk; 261 | end generate real_passthrough; 262 | 263 | 264 | 265 | valid <= outp_blk_valid(0); 266 | 267 | enable_in(0) <= not stall; 268 | 269 | end struct; 270 | 271 | 272 | 273 | 274 | -------------------------------------------------------------------------------- /demod_fir_sim/cadence/ncsim_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2020 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 18.1 625 win32 2020.12.18.19:27:43 16 | 17 | # ---------------------------------------- 18 | # ncsim - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script provides commands to simulate the following IP detected in 22 | # your Quartus project: 23 | # demod_fir 24 | # 25 | # Altera recommends that you source this Quartus-generated IP simulation 26 | # script from your own customized top-level script, and avoid editing this 27 | # generated script. 28 | # 29 | # To write a top-level shell script that compiles Altera simulation libraries 30 | # and the Quartus-generated IP in your project, along with your design and 31 | # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below 32 | # into a new file, e.g. named "ncsim.sh", and modify text as directed. 33 | # 34 | # You can also modify the simulation flow to suit your needs. Set the 35 | # following variables to 1 to disable their corresponding processes: 36 | # - SKIP_FILE_COPY: skip copying ROM/RAM initialization files 37 | # - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library 38 | # - SKIP_COM: skip compiling Quartus-generated IP simulation files 39 | # - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation 40 | # 41 | # ---------------------------------------- 42 | # # TOP-LEVEL TEMPLATE - BEGIN 43 | # # 44 | # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to 45 | # # construct paths to the files required to simulate the IP in your Quartus 46 | # # project. By default, the IP script assumes that you are launching the 47 | # # simulator from the IP script location. If launching from another 48 | # # location, set QSYS_SIMDIR to the output directory you specified when you 49 | # # generated the IP script, relative to the directory from which you launch 50 | # # the simulator. In this case, you must also copy the generated files 51 | # # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 52 | # # into the location from which you launch the simulator, or incorporate 53 | # # into any existing library setup. 54 | # # 55 | # # Run Quartus-generated IP simulation script once to compile Quartus EDA 56 | # # simulation libraries and Quartus-generated IP simulation files, and copy 57 | # # any ROM/RAM initialization files to the simulation directory. 58 | # # - If necessary, specify any compilation options: 59 | # # USER_DEFINED_COMPILE_OPTIONS 60 | # # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler 61 | # # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler 62 | # # 63 | # source