├── doc ├── 74390.md ├── 74393.md ├── 74534.md ├── 74670.md ├── 74181.md ├── 74259.md ├── 74377.md ├── 74174.md ├── 74175.md ├── inverters.md ├── arithmetic.md ├── 7405.md ├── 7404.md ├── 7414.md ├── 747266.md ├── 74132.md ├── 74165.md ├── 7402.md ├── 7408.md ├── 7432.md ├── 7486.md ├── 7400.md ├── 7403.md ├── 744049.md ├── 7411.md ├── 7427.md ├── encoders_decoders.md ├── 7410.md ├── 744002.md ├── 744075.md ├── 7421.md ├── 7420.md ├── 74273.md ├── 74244.md ├── 7475.md ├── 74283.md ├── 74373.md ├── 74374.md ├── 74574.md ├── 74595.md ├── 74157.md ├── 74573.md ├── 7474.md ├── 7430.md ├── 74107.md ├── 7473.md ├── 74173.md ├── 74139.md ├── 7493.md ├── 7476.md ├── 74147.md ├── 74153.md ├── 74112.md ├── 74109.md ├── flip_flops.md ├── gates.md ├── 74238.md ├── 7442.md ├── 74137.md ├── 74138.md ├── 7451.md ├── 74163.md ├── 74161.md ├── chip.svg ├── 7485.md ├── 74151.md ├── 74247.md └── 744511.md ├── dia ├── 7400-dip.dia ├── 7400-dip.png ├── 7402-dip.dia ├── 7402-dip.png ├── 7403-dip.dia ├── 7403-dip.png ├── 7404-dip.dia ├── 7404-dip.png ├── 7405-dip.dia ├── 7405-dip.png ├── 7408-dip.dia ├── 7408-dip.png ├── 7410-dip.dia ├── 7410-dip.png ├── 7411-dip.dia ├── 7411-dip.png ├── 7413-dip.dia ├── 7413-dip.png ├── 7421-dip.dia ├── 7421-dip.png ├── 7427-dip.dia ├── 7427-dip.png ├── 7430-dip.dia ├── 7430-dip.png ├── 7432-dip.dia ├── 7432-dip.png ├── 7442-dip.dia ├── 7442-dip.png ├── 7451-dip.dia ├── 7451-dip.png ├── 7473-dip.dia ├── 7473-dip.png ├── 7474-dip.dia ├── 7474-dip.png ├── 7475-dip.dia ├── 7475-dip.png ├── 7476-dip.dia ├── 7476-dip.png ├── 7486-dip.dia ├── 7486-dip.png ├── 74107-dip.dia ├── 74107-dip.png ├── 74109-dip.dia ├── 74109-dip.png ├── 74112-dip.dia ├── 74112-dip.png ├── 74138-dip.dia ├── 74138-dip.png ├── 74139-dip.dia ├── 74139-dip.png ├── 74147-dip.dia ├── 74147-dip.png ├── 74151-dip.dia ├── 74151-dip.png ├── 74153-dip.dia ├── 74153-dip.png ├── 74157-dip.dia ├── 74157-dip.png ├── 74173-dip.dia ├── 74173-dip.png ├── 74175-dip.dia ├── 74175-dip.png ├── 74238-dip.dia ├── 74238-dip.png ├── 74244-dip.dia ├── 74244-dip.png ├── 74273-dip.dia ├── 74273-dip.png ├── 744002-dip.dia ├── 744002-dip.png ├── 744075-dip.dia ├── 744075-dip.png ├── 747266-dip.dia └── 747266-dip.png ├── in-progress ├── 74x299.md └── 74x299.circ ├── guidelines.md ├── LICENSE └── README.md /doc/74390.md: -------------------------------------------------------------------------------- 1 | # 74390 Tbd. 2 | -------------------------------------------------------------------------------- /doc/74393.md: -------------------------------------------------------------------------------- 1 | # 74393 Tbd. 2 | -------------------------------------------------------------------------------- /doc/74534.md: -------------------------------------------------------------------------------- 1 | # 74534 Tbd. 2 | -------------------------------------------------------------------------------- /doc/74670.md: -------------------------------------------------------------------------------- 1 | # 74670: 4 by 4 register file 2 | -------------------------------------------------------------------------------- /doc/74181.md: -------------------------------------------------------------------------------- 1 | # 74181: 4-bit arithmetic logic unit 2 | -------------------------------------------------------------------------------- /doc/74259.md: -------------------------------------------------------------------------------- 1 | # 74259 octal adressable D-type latch 2 | -------------------------------------------------------------------------------- /dia/7400-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7400-dip.dia -------------------------------------------------------------------------------- /dia/7400-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7400-dip.png -------------------------------------------------------------------------------- /dia/7402-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7402-dip.dia -------------------------------------------------------------------------------- /dia/7402-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7402-dip.png -------------------------------------------------------------------------------- /dia/7403-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7403-dip.dia -------------------------------------------------------------------------------- /dia/7403-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7403-dip.png -------------------------------------------------------------------------------- /dia/7404-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7404-dip.dia -------------------------------------------------------------------------------- /dia/7404-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7404-dip.png -------------------------------------------------------------------------------- /dia/7405-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7405-dip.dia -------------------------------------------------------------------------------- /dia/7405-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7405-dip.png -------------------------------------------------------------------------------- /dia/7408-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7408-dip.dia -------------------------------------------------------------------------------- /dia/7408-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7408-dip.png -------------------------------------------------------------------------------- /dia/7410-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7410-dip.dia -------------------------------------------------------------------------------- /dia/7410-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7410-dip.png -------------------------------------------------------------------------------- /dia/7411-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7411-dip.dia -------------------------------------------------------------------------------- /dia/7411-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7411-dip.png -------------------------------------------------------------------------------- /dia/7413-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7413-dip.dia -------------------------------------------------------------------------------- /dia/7413-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7413-dip.png -------------------------------------------------------------------------------- /dia/7421-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7421-dip.dia -------------------------------------------------------------------------------- /dia/7421-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7421-dip.png -------------------------------------------------------------------------------- /dia/7427-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7427-dip.dia -------------------------------------------------------------------------------- /dia/7427-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7427-dip.png -------------------------------------------------------------------------------- /dia/7430-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7430-dip.dia -------------------------------------------------------------------------------- /dia/7430-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7430-dip.png -------------------------------------------------------------------------------- /dia/7432-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7432-dip.dia -------------------------------------------------------------------------------- /dia/7432-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7432-dip.png -------------------------------------------------------------------------------- /dia/7442-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7442-dip.dia -------------------------------------------------------------------------------- /dia/7442-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7442-dip.png -------------------------------------------------------------------------------- /dia/7451-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7451-dip.dia -------------------------------------------------------------------------------- /dia/7451-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7451-dip.png -------------------------------------------------------------------------------- /dia/7473-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7473-dip.dia -------------------------------------------------------------------------------- /dia/7473-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7473-dip.png -------------------------------------------------------------------------------- /dia/7474-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7474-dip.dia -------------------------------------------------------------------------------- /dia/7474-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7474-dip.png -------------------------------------------------------------------------------- /dia/7475-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7475-dip.dia -------------------------------------------------------------------------------- /dia/7475-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7475-dip.png -------------------------------------------------------------------------------- /dia/7476-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7476-dip.dia -------------------------------------------------------------------------------- /dia/7476-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7476-dip.png -------------------------------------------------------------------------------- /dia/7486-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7486-dip.dia -------------------------------------------------------------------------------- /dia/7486-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/7486-dip.png -------------------------------------------------------------------------------- /dia/74107-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74107-dip.dia -------------------------------------------------------------------------------- /dia/74107-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74107-dip.png -------------------------------------------------------------------------------- /dia/74109-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74109-dip.dia -------------------------------------------------------------------------------- /dia/74109-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74109-dip.png -------------------------------------------------------------------------------- /dia/74112-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74112-dip.dia -------------------------------------------------------------------------------- /dia/74112-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74112-dip.png -------------------------------------------------------------------------------- /dia/74138-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74138-dip.dia -------------------------------------------------------------------------------- /dia/74138-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74138-dip.png -------------------------------------------------------------------------------- /dia/74139-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74139-dip.dia -------------------------------------------------------------------------------- /dia/74139-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74139-dip.png -------------------------------------------------------------------------------- /dia/74147-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74147-dip.dia -------------------------------------------------------------------------------- /dia/74147-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74147-dip.png -------------------------------------------------------------------------------- /dia/74151-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74151-dip.dia -------------------------------------------------------------------------------- /dia/74151-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74151-dip.png -------------------------------------------------------------------------------- /dia/74153-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74153-dip.dia -------------------------------------------------------------------------------- /dia/74153-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74153-dip.png -------------------------------------------------------------------------------- /dia/74157-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74157-dip.dia -------------------------------------------------------------------------------- /dia/74157-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74157-dip.png -------------------------------------------------------------------------------- /dia/74173-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74173-dip.dia -------------------------------------------------------------------------------- /dia/74173-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74173-dip.png -------------------------------------------------------------------------------- /dia/74175-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74175-dip.dia -------------------------------------------------------------------------------- /dia/74175-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74175-dip.png -------------------------------------------------------------------------------- /dia/74238-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74238-dip.dia -------------------------------------------------------------------------------- /dia/74238-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74238-dip.png -------------------------------------------------------------------------------- /dia/74244-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74244-dip.dia -------------------------------------------------------------------------------- /dia/74244-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74244-dip.png -------------------------------------------------------------------------------- /dia/74273-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74273-dip.dia -------------------------------------------------------------------------------- /dia/74273-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/74273-dip.png -------------------------------------------------------------------------------- /dia/744002-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/744002-dip.dia -------------------------------------------------------------------------------- /dia/744002-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/744002-dip.png -------------------------------------------------------------------------------- /dia/744075-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/744075-dip.dia -------------------------------------------------------------------------------- /dia/744075-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/744075-dip.png -------------------------------------------------------------------------------- /dia/747266-dip.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/747266-dip.dia -------------------------------------------------------------------------------- /dia/747266-dip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/r0the/logi7400/HEAD/dia/747266-dip.png -------------------------------------------------------------------------------- /doc/74377.md: -------------------------------------------------------------------------------- 1 | # 74377 8-bit register with clock enable 2 | 3 | 4 | ## Datasheets 5 | 6 | - [CD74HC377 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc377) 7 | -------------------------------------------------------------------------------- /doc/74174.md: -------------------------------------------------------------------------------- 1 | # 74174: hex D-type flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 16-pin 5 | - Number of elements: 6 6 | - Trigger: positive edge 7 | 8 | ## Datasheets 9 | 10 | - [CD74HC174 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc174) 11 | - [74HC174, 74HCT174 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT174_Q100.pdf) 12 | -------------------------------------------------------------------------------- /doc/74175.md: -------------------------------------------------------------------------------- 1 | # 74175: quad D-type flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 16-pin 5 | - Number of elements: 4 6 | - Trigger: positive edge 7 | 8 | ## Pin layout 9 | 10 | ![](../dia/74175-dip.png) 11 | 12 | ## Datasheets 13 | 14 | - [CD74HC175 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc175) 15 | - [74HC175, 74HCT174 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT175.pdf) 16 | -------------------------------------------------------------------------------- /doc/inverters.md: -------------------------------------------------------------------------------- 1 | # Inverters 2 | 3 | | Type | Gates | Inputs per gate | Comments | 4 | | ------------------- |:-----:|:---------------:| --------------------- | 5 | | [7404](7404.md) | 6 | 1 | | 6 | | [7405](7405.md) | 6 | 1 | open collector output | 7 | | [7414](7414.md) | 6 | 1 | Schmitt trigger | 8 | | [744049](744049.md) | 6 | 1 | atypical pin layout | 9 | -------------------------------------------------------------------------------- /doc/arithmetic.md: -------------------------------------------------------------------------------- 1 | # Arithmetic and Counters 2 | 3 | ## Arithmetic 4 | 5 | | Type | Description | Bits | 6 | | ----------------- | --------------------- | ---- | 7 | | [7485](7485.md) | magnitude comparator | 4 | 8 | | [74181](74181.md) | arithmetic logic unit | 4 | 9 | | [74283](74283.md) | full adder | 4 | 10 | 11 | ## Ripple Counters 12 | 13 | | Type | Description | Bits | 14 | | ----------------- | ----------- | ---- | 15 | | [7493](7493.md) | | 4 | 16 | 17 | ## Synchronous Counters 18 | 19 | | Type | Description | Bits | 20 | | ----------------- | ----------- | ---- | 21 | | [74161](74161.md) | | 4 | 22 | | [74163](74163.md) | | 4 | 23 | -------------------------------------------------------------------------------- /doc/7405.md: -------------------------------------------------------------------------------- 1 | # 7404: hex inverter, open collector output 2 | 3 | - Type: [inverter](inverters.md) 4 | - DIP: 14-pin 5 | - Number of elements: 6 6 | - Inputs per element: 1 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides six inverters with open collector outputs. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | -------------------- | 17 | | An | input of inverter n | 18 | | Yn | output of inverter n | 19 | 20 | ## Function table 21 | 22 | | An | Yn | 23 | |:---:|:---:| 24 | | L | Z | 25 | | H | L | 26 | 27 | - H: HIGH voltage level 28 | - L: LOW voltage level 29 | - Z: high-impedance OFF-state 30 | 31 | ## Pin layout 32 | 33 | ![](../dia/7405-dip.png) 34 | 35 | ## Datasheets 36 | 37 | - [74HC05, 74HCT05 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT04.pdf) 38 | -------------------------------------------------------------------------------- /doc/7404.md: -------------------------------------------------------------------------------- 1 | # 7404: hex inverter 2 | 3 | - Type: [inverter](inverters.md) 4 | - DIP: 14-pin 5 | - Number of elements: 6 6 | - Inputs per element: 1 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides six inverters. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | -------------------- | 17 | | An | input of inverter n | 18 | | Yn | output of inverter n | 19 | 20 | ## Function table 21 | 22 | | An | Yn | 23 | |:---:|:---:| 24 | | L | H | 25 | | H | L | 26 | 27 | - H: HIGH voltage level 28 | - L: LOW voltage level 29 | 30 | ## Pin layout 31 | 32 | ![](../dia/7404-dip.png) 33 | 34 | ## Datasheets 35 | 36 | - [74HC04, 74HCT04 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT04.pdf) 37 | - [7404, 74LS04, 74S04 by Texas Instruments](http://www.ti.com/lit/ds/symlink/sn74ls04.pdf) 38 | -------------------------------------------------------------------------------- /doc/7414.md: -------------------------------------------------------------------------------- 1 | # 7414: hex Schmitt-trigger inverter 2 | 3 | - Type: [inverter](inverters.md) 4 | - DIP: 14-pin 5 | - Number of elements: 6 6 | - Inputs per element: 1 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides six Schmitt-trigger inverters. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | -------------------- | 17 | | An | input of inverter n | 18 | | Yn | output of inverter n | 19 | 20 | ## Function table 21 | 22 | | An | Yn | 23 | |:---:|:---:| 24 | | L | H | 25 | | H | L | 26 | 27 | - H: HIGH voltage level 28 | - L: LOW voltage level 29 | 30 | ## Pin layout 31 | 32 | ![](../dia/7404-dip.png) 33 | 34 | ## Datasheets 35 | 36 | - [74HC14, 74HCT14 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT14.pdf) 37 | - [7414, 74LS14 by Texas Instruments](http://www.ti.com/lit/ds/symlink/sn5414.pdf) 38 | -------------------------------------------------------------------------------- /doc/747266.md: -------------------------------------------------------------------------------- 1 | # 747266: quad 2-input XNOR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four XNOR gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | H | 26 | | L | H | L | 27 | | H | L | L | 28 | | H | H | H | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/747266-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [CD74HC7266 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc7266) 40 | -------------------------------------------------------------------------------- /doc/74132.md: -------------------------------------------------------------------------------- 1 | # 74132: quad 2-input NAND Schmitt trigger 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four NAND gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | H | 26 | | L | H | H | 27 | | H | L | H | 28 | | H | H | L | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/7400-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [CD74HC132 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc132) 40 | -------------------------------------------------------------------------------- /doc/74165.md: -------------------------------------------------------------------------------- 1 | # 74165: 8-bit parallel in shift register 2 | 3 | - Type: 4 | - DIP: 16-pin 5 | - Input: 8-bit parallel 6 | - Output: 1-bit serial 7 | 8 | ## Description 9 | 10 | TODO 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ---------------------- | ------------- | 16 | | LE | load enable input | active low | 17 | | CLK | clock | positive edge | 18 | | Q7 | serial output | active high | 19 | | R7 | inverted serial output | active low | 20 | | DS | serial data input | active high | 21 | | Dn | parallel data inputs | active high | 22 | | CE | clock enable input | active low | 23 | 24 | 25 | 26 | 27 | ## Datasheets 28 | 29 | - [74HC164 by Texas Instruments](http://www.ti.com/lit/ds/symlink/sn74hc165.pdf) 30 | - [74HC165, 74HCT165 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT165.pdf) 31 | -------------------------------------------------------------------------------- /doc/7402.md: -------------------------------------------------------------------------------- 1 | # 7402: quad 2-input NOR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four NOR gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | H | 26 | | L | H | L | 27 | | H | L | L | 28 | | H | H | L | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/7402-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [CD74HC02 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc02) 40 | - [74HC02, 74HCT02 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT02.pdf) 41 | -------------------------------------------------------------------------------- /doc/7408.md: -------------------------------------------------------------------------------- 1 | # 7408: quad 2-input AND gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four AND gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | L | 26 | | L | H | L | 27 | | H | L | L | 28 | | H | H | H | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/7408-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [CD74HC08 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc08) 40 | - [74HC08, 74HCT08 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT08.pdf) 41 | -------------------------------------------------------------------------------- /doc/7432.md: -------------------------------------------------------------------------------- 1 | # 7432: quad 2-input OR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four OR gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | L | 26 | | L | H | H | 27 | | H | L | H | 28 | | H | H | H | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/7432-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [74HC32, 74HCT32 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT32.pdf) 40 | - [CD74HC32 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc32) 41 | -------------------------------------------------------------------------------- /doc/7486.md: -------------------------------------------------------------------------------- 1 | # 7486: quad 2-input XOR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four XOR gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | L | 26 | | L | H | H | 27 | | H | L | H | 28 | | H | H | L | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/7486-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [CD74HC86 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc86) 40 | - [74HC86, 74HCT86 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT86.pdf) 41 | -------------------------------------------------------------------------------- /doc/7400.md: -------------------------------------------------------------------------------- 1 | # 7400: quad 2-input NAND gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four NAND gates with two inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | H | 26 | | L | H | H | 27 | | H | L | H | 28 | | H | H | L | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | 33 | ## Pin layout 34 | 35 | ![](../dia/7400-dip.png) 36 | 37 | ## Datasheets 38 | 39 | - [CD74HC00 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc00) 40 | - [74HC00, 74HCT00 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT00.pdf) 41 | -------------------------------------------------------------------------------- /doc/7403.md: -------------------------------------------------------------------------------- 1 | # 7403: quad 2-input NAND gate, open collector output 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 4 6 | - Inputs per element: 2 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides four NAND gates with two inputs and an open collector output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Yn | output of gate n | 20 | 21 | ## Function table 22 | 23 | | An | Bn | Yn | 24 | |:---:|:---:|:---:| 25 | | L | L | Z | 26 | | L | H | Z | 27 | | H | L | Z | 28 | | H | H | L | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | - Z: high-impedance OFF-state 33 | 34 | ## Pin layout 35 | 36 | ![](../dia/7403-dip.png) 37 | 38 | ## Datasheets 39 | 40 | - [CD74HC03 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc03) 41 | - [74HC03, 74HCT03 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT03.pdf) 42 | -------------------------------------------------------------------------------- /doc/744049.md: -------------------------------------------------------------------------------- 1 | # 744049: hex inverter 2 | 3 | - Type: [inverter](inverters.md) 4 | - DIP: 16-pin 5 | - Number of elements: 6 6 | - Inputs per element: 1 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides six inverters with over-voltage tolerant inputs. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | -------------------- | 17 | | An | input of inverter n | 18 | | Yn | output of inverter n | 19 | 20 | ## Function table 21 | 22 | | An | Yn | 23 | |:---:|:---:| 24 | | L | H | 25 | | H | L | 26 | 27 | - H: HIGH voltage level 28 | - L: LOW voltage level 29 | 30 | ## Pin layout 31 | 32 | TODO 33 | 34 | | | Pin | Pin | | 35 | |:---:|:---:|:---:|:---:| 36 | | VCC | 1 | 16 | - | 37 | | Y1 | 2 | 15 | Y6 | 38 | | A1 | 3 | 14 | A6 | 39 | | Y2 | 4 | 13 | - | 40 | | A2 | 5 | 12 | Y5 | 41 | | Y3 | 6 | 11 | A5 | 42 | | A3 | 7 | 10 | Y4 | 43 | | GND | 8 | 9 | A4 | 44 | 45 | ## Datasheets 46 | 47 | - [74HC4049 by NXP](http://www.nxp.com/documents/data_sheet/74HC4049.pdf) 48 | -------------------------------------------------------------------------------- /doc/7411.md: -------------------------------------------------------------------------------- 1 | # 7411: triple 3-input AND gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 3 6 | - Inputs per element: 3 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides three AND gates with three inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Yn | output of gate n | 21 | 22 | ## Function table 23 | 24 | | An | Bn | Cn | Yn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | X | X | L | 27 | | H | L | X | L | 28 | | H | H | L | L | 29 | | H | H | H | H | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | 35 | ## Pin layout 36 | 37 | ![](../dia/7411-dip.png) 38 | 39 | ## Datasheets 40 | 41 | - [CD74HC11 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc11) 42 | - [74HC11, 74HCT11 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT11.pdf) 43 | -------------------------------------------------------------------------------- /doc/7427.md: -------------------------------------------------------------------------------- 1 | # 7427: triple 3-input NOR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 3 6 | - Inputs per element: 3 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides three NOR gates with three inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Yn | output of gate n | 21 | 22 | ## Function table 23 | 24 | | An | Bn | Cn | Yn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | L | L | H | 27 | | H | X | X | L | 28 | | X | H | X | L | 29 | | X | X | H | L | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | 35 | ## Pin layout 36 | 37 | ![](../dia/7427-dip.png) 38 | 39 | ## Datasheets 40 | 41 | - [CD74HC27 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc27) 42 | - [74HC27, 74HCT27 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT27.pdf) 43 | -------------------------------------------------------------------------------- /doc/encoders_decoders.md: -------------------------------------------------------------------------------- 1 | # Encoders and Decoders 2 | 3 | ## Encoders 4 | 5 | | Type | Input | Output | 6 | | ------------------- | ------------------ | ---------- | 7 | | [74147](74147.md) | 9 lines active low | 4-bit BCD | 8 | 9 | 10 | ## Decoders 11 | 12 | | Type | Input | Output | 13 | | ------------------- | --------- | --------------------- | 14 | | [7442](7442.md) | 4-bit BCD | 10 lines active low | 15 | | [74138](74138.md) | 3-bit | 8 lines active low | 16 | | [74139](74139.md) | 2-bit | 4 lines active low | 17 | | [74238](74238.md) | 3-bit | 8 lines | 18 | | [74247](74247.md) | 4-bit BCD | 7-segment | 19 | | [744511](744511.md) | 4-bit BCD | 7-segment active low | 20 | 21 | 22 | ## Multiplexers 23 | 24 | | Type | Bits / Elements | Lines | 25 | | ------------------- | --------------- | ------ | 26 | | [74151](74151.md) | 1 | 8 | 27 | | [74153](74153.md) | 2 | 4 | 28 | | [74157](74157.md) | 4 | 2 | 29 | -------------------------------------------------------------------------------- /doc/7410.md: -------------------------------------------------------------------------------- 1 | # 7410: tripe 3-input NAND gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 3 6 | - Inputs per element: 3 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides three NAND gates with three inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Yn | output of gate n | 21 | 22 | ## Function table 23 | 24 | | An | Bn | Cn | Yn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | X | X | H | 27 | | H | L | X | H | 28 | | H | H | L | H | 29 | | H | H | H | L | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | 35 | ## Pin layout 36 | 37 | ![](../dia/7410-dip.png) 38 | 39 | ## Datasheets 40 | 41 | - [CD74HC10 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc10) 42 | - [74HC10, 74HCT10 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT10_Q100.pdf) 43 | -------------------------------------------------------------------------------- /doc/744002.md: -------------------------------------------------------------------------------- 1 | # 744002: dual 4-input NOR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Inputs per element: 4 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides two NOR gates with four inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Dn | fourth input of gate n | 21 | | Yn | output of gate n | 22 | 23 | ## Function table 24 | 25 | | An | Bn | Cn | Dn | Yn | 26 | |:---:|:---:|:---:|:---:|:---:| 27 | | L | L | L | L | H | 28 | | H | X | X | X | L | 29 | | X | H | X | X | L | 30 | | X | X | H | X | L | 31 | | X | X | X | H | L | 32 | 33 | - H: HIGH voltage level 34 | - L: LOW voltage level 35 | - X: don't care 36 | 37 | ## Pin layout 38 | 39 | ![](../dia/744002-dip.png) 40 | 41 | ## Datasheets 42 | 43 | [CD74HC4002 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc4002) 44 | -------------------------------------------------------------------------------- /doc/744075.md: -------------------------------------------------------------------------------- 1 | # 744075: triple 3-input OR gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 3 6 | - Inputs per element: 3 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides three OR gates with three inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Yn | output of gate n | 21 | 22 | ## Function table 23 | 24 | | An | Bn | Cn | Yn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | L | L | L | 27 | | H | X | X | H | 28 | | X | H | X | H | 29 | | X | X | H | H | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | 35 | ## Pin layout 36 | 37 | ![](../dia/744075-dip.png) 38 | 39 | ## Datasheets 40 | 41 | - [74HC4057, 74HCT4075 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT4075.pdf) 42 | - [CD74HC4075 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc4075) 43 | -------------------------------------------------------------------------------- /doc/7421.md: -------------------------------------------------------------------------------- 1 | # 7421: dual 4-input AND hate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Inputs per element: 4 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides two AND gates with four inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Dn | fourth input of gate n | 21 | | Yn | output of gate n | 22 | 23 | ## Function table 24 | 25 | | An | Bn | Cn | Dn | Yn | 26 | |:---:|:---:|:---:|:---:|:---:| 27 | | L | X | X | X | L | 28 | | X | L | X | X | L | 29 | | X | X | L | X | L | 30 | | X | X | X | L | L | 31 | | H | H | H | H | H | 32 | 33 | - H: HIGH voltage level 34 | - L: LOW voltage level 35 | - X: don't care 36 | 37 | ## Pin layout 38 | 39 | ![](../dia/7421-dip.png) 40 | 41 | ## Datasheets 42 | 43 | - [CD74HC21 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc21) 44 | - [74HC21 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC21.pdf) 45 | -------------------------------------------------------------------------------- /doc/7420.md: -------------------------------------------------------------------------------- 1 | # 7420: dual 4-input NAND gate 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Inputs per element: 4 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides two NAND gates with four inputs and an output each. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | ---------------------- | 17 | | An | first input of gate n | 18 | | Bn | second input of gate n | 19 | | Cn | third input of gate n | 20 | | Dn | fourth input of gate n | 21 | | Yn | output of gate n | 22 | 23 | ## Function table 24 | 25 | | An | Bn | Cn | Dn | Yn | 26 | |:---:|:---:|:---:|:---:|:---:| 27 | | L | X | X | X | H | 28 | | X | L | X | X | H | 29 | | X | X | L | X | H | 30 | | X | X | X | L | H | 31 | | H | H | H | H | L | 32 | 33 | - H: HIGH voltage level 34 | - L: LOW voltage level 35 | - X: don't care 36 | 37 | ## Pin layout 38 | 39 | ![](../dia/7413-dip.png) 40 | 41 | ## Datasheets 42 | 43 | - [CD74HC20 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc20) 44 | - [74HC20, 74HCT20 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT20.pdf) 45 | -------------------------------------------------------------------------------- /doc/74273.md: -------------------------------------------------------------------------------- 1 | # 74273: octal D-type flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 20-pin 5 | - Number of elements: 8 6 | - Trigger: positive edge 7 | 8 | ## Description 9 | 10 | Provides eight positive-edge triggered D-type flip-flops with a common asynchronous clear. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ------------------ | ------------- | 16 | | Dn | input n | active high | 17 | | Qn | output n | active high | 18 | | CLK | clock | positive edge | 19 | | CLR | asynchronous clear | active low | 20 | 21 | ## Function table 22 | 23 | | CLR | CLK | Dn | Qn | 24 | |:---:|:---:|:---:|:---:| 25 | | H | X | X | L | 26 | | L | / | H | H | 27 | | L | / | L | L | 28 | | L | X | X | qn0 | 29 | 30 | - H: HIGH voltage level 31 | - L: LOW voltage level 32 | - X: don't care 33 | - /: positive edge 34 | - qn0: previous state of Qn 35 | 36 | ## Pin layout 37 | 38 | ![](../dia/74273-dip.png) 39 | 40 | ## Datasheets 41 | 42 | - [CD74HC273 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc273) 43 | - [74HC273, 74HCT273 by NXT](http://www.nxp.com/documents/data_sheet/74HC_HCT273.pdf) 44 | -------------------------------------------------------------------------------- /doc/74244.md: -------------------------------------------------------------------------------- 1 | # 74244: octal buffer 2 | 3 | - Type: [buffer](buffers.md) 4 | - Number of elements: 2 5 | - Inputs per element: 4 6 | - Outputs per element: 4 7 | - Bits: 2x4 8 | - DIP: 20-pin 9 | 10 | ## Description 11 | 12 | Provides two 4-bit buffers with a tri-state output. 13 | 14 | ## Inputs and outputs 15 | 16 | | Label | Description | Signal | 17 | | ----- | ------------------------------- | ----------- | 18 | | OEA | output enable for first buffer | active low | 19 | | OEB | output enable for second buffer | active low | 20 | | An | input of first buffer | active high | 21 | | Qn | output of first buffer | active high | 22 | | Bn | input of second buffer | active high | 23 | | Rn | output of second buffer | active high | 24 | 25 | ## Function table 26 | 27 | | OEA | An | Qn | 28 | |:---:|:---:|:---:| 29 | | L | L | L | 30 | | L | H | H | 31 | | H | X | Z | 32 | 33 | | OEB | Bn | Rn | 34 | |:---:|:---:|:---:| 35 | | L | L | L | 36 | | L | H | H | 37 | | H | X | Z | 38 | 39 | - H: HIGH voltage level 40 | - L: LOW voltage level 41 | - X: don't care 42 | - Z: high-impedance OFF-state 43 | 44 | ## Pin layout 45 | 46 | ![](../dia/74244-dip.png) 47 | 48 | ## Datasheets 49 | 50 | TODO 51 | -------------------------------------------------------------------------------- /doc/7475.md: -------------------------------------------------------------------------------- 1 | # 7475: quad D-type latch 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 16-pin 5 | - Number of elements: 4 6 | - Trigger: Rising edge 7 | 8 | ## Description 9 | 10 | Provides four positive-edge triggered D-type latches. Two latches share a load enable input each. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ------------------------------- | ----------- | 16 | | Dn | data input of D latch | active high | 17 | | LEnm | load enable for latches n and m | active high | 18 | | Qn | output of latch n | active high | 19 | | Rn | inverted output of latch n | active low | 20 | 21 | ## Function table 22 | 23 | | LEnm | Dn | Qn | Rn | 24 | |:----:|:---:|:---:|:---:| 25 | | H | L | L | H | 26 | | H | H | H | L | 27 | | L | X | qn0 | rn0 | 28 | 29 | - H: HIGH voltage level 30 | - L: LOW voltage level 31 | - X: don't care 32 | - qn0: previous state of output Qn 33 | - rn0: previous state of output Rn 34 | 35 | ## Pin layout 36 | 37 | ![](../dia/7475-dip.png) 38 | 39 | 40 | ## Datasheets 41 | 42 | - [74HC75, 74HCT75 by Texas Instruments](http://www.ti.com/lit/ds/symlink/cd74hc75.pdf) 43 | - [74HC75 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC75.pdf) 44 | -------------------------------------------------------------------------------- /doc/74283.md: -------------------------------------------------------------------------------- 1 | # 74283: 4-bit binary full adder 2 | 3 | - Number of elements: 1 4 | - DIP: 16-pin 5 | 6 | ## Description 7 | 8 | Provides a 4-bit binary full adder. 9 | 10 | ## Inputs and outputs 11 | 12 | | Label | Description | Signal | 13 | | ----- | -------------------------------- | ----------- | 14 | | An | input of bit n of first operand | active high | 15 | | Bn | input of bit n of second operand | active high | 16 | | Yn | output of bit n of result | active high | 17 | | CIN | carry input | active high | 18 | | COUT | carry output | active high | 19 | 20 | ## Function Table 21 | 22 | TODO 23 | 24 | ## Pin Configuration 25 | 26 | TODO 27 | 28 | | | Pin | Pin | | 29 | |:---:|:---:|:---:|:----:| 30 | | Q2 | 1 | 16 | VCC | 31 | | B2 | 2 | 15 | B3 | 32 | | A2 | 3 | 14 | A3 | 33 | | Q1 | 4 | 13 | Q3 | 34 | | A1 | 5 | 12 | A4 | 35 | | B1 | 6 | 11 | B4 | 36 | | CIN | 7 | 10 | Q4 | 37 | | GND | 8 | 9 | COUT | 38 | 39 | ## Datasheets 40 | 41 | - [CD74HC283 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc283) 42 | - [SN74283m SN74LS28, SN74S283 by Texas Instruments](http://www.ti.com.cn/cn/lit/ds/symlink/sn54283.pdf) 43 | - [74HC283 by Philips](http://www.farnell.com/datasheets/1846165.pdf) 44 | -------------------------------------------------------------------------------- /doc/74373.md: -------------------------------------------------------------------------------- 1 | # 74373: octal transparent D-type latch, tri-state output 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 20-pin 5 | - Number of elements: 8 6 | - Trigger: high 7 | - Tri-state output 8 | 9 | ## Description 10 | 11 | Provides eight transparent D-type latches with tri-state output. This chip has a different pin layout than [74573](74573.md) 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------- | ----------- | 17 | | Dn | input n | active high | 18 | | Qn | output n | active high | 19 | | LE | latch enable | active high | 20 | | OE | output enable | active low | 21 | 22 | ## Function table 23 | 24 | | OE | LE | Dn | Qn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | H | H | H | 27 | | L | H | L | L | 28 | | L | L | X | qn0 | 29 | | H | X | X | Z | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | - Z: high-impedance OFF-state 35 | - qn0: previous state of Qn 36 | 37 | ## Pin layout 38 | 39 | TODO 40 | 41 | | | Pin | Pin | | 42 | |:---:|:---:|:---:|:---:| 43 | | OE | 1 | 20 | VCC | 44 | | Q1 | 2 | 19 | Q8 | 45 | | D1 | 3 | 18 | D8 | 46 | | D2 | 4 | 17 | D7 | 47 | | Q2 | 5 | 16 | Q7 | 48 | | Q3 | 6 | 15 | Q6 | 49 | | D3 | 7 | 14 | D6 | 50 | | D4 | 8 | 13 | D5 | 51 | | Q4 | 9 | 12 | Q5 | 52 | | GND | 10 | 11 | LE | 53 | 54 | ## Datasheets 55 | 56 | - [74LS373, 74S373 by Texas Instruments](http://www.farnell.com/datasheets/1965578.pdf) 57 | -------------------------------------------------------------------------------- /doc/74374.md: -------------------------------------------------------------------------------- 1 | # 74374: octal D-type flip-flop, tri-state output 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 20-pin 5 | - Number of elements: 8 6 | - Trigger: positive edge 7 | - Tri-state output 8 | 9 | ## Description 10 | 11 | Provides eight positive-edge triggered D-type flip-flops with tri-state output. This chip has a different pin layout than [74574](74574.md) 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------- | ------------- | 17 | | Dn | input n | active high | 18 | | Qn | output n | active high | 19 | | CLK | clock | positive edge | 20 | | OE | output enable | active low | 21 | 22 | ## Function table 23 | 24 | | OE | CLK | Dn | Qn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | / | H | H | 27 | | L | / | L | L | 28 | | L | L | X | qn0 | 29 | | H | X | X | Z | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | - Z: high-impedance OFF-state 35 | - /: positive edge 36 | - qn0: previous state of Qn 37 | 38 | ## Pin layout 39 | 40 | TODO 41 | 42 | | | Pin | Pin | | 43 | |:---:|:---:|:---:|:---:| 44 | | OE | 1 | 20 | VCC | 45 | | Q1 | 2 | 19 | Q8 | 46 | | D1 | 3 | 18 | D8 | 47 | | D2 | 4 | 17 | D7 | 48 | | Q2 | 5 | 16 | Q7 | 49 | | Q3 | 6 | 15 | Q6 | 50 | | D3 | 7 | 14 | D6 | 51 | | D4 | 8 | 13 | D5 | 52 | | Q4 | 9 | 12 | Q5 | 53 | | GND | 10 | 11 | CLK | 54 | 55 | ## Datasheets 56 | 57 | - [CD74HC374 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc273) 58 | -------------------------------------------------------------------------------- /doc/74574.md: -------------------------------------------------------------------------------- 1 | # 74574: octal D-type flip-flop, tri-state output 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 20-pin 5 | - Number of elements: 8 6 | - Trigger: positive edge 7 | - Tri-state output 8 | 9 | ## Description 10 | 11 | Provides eight positive-edge triggered D-type flip-flops with tri-state output. This chip has a different pin layout than [74374](74374.md) 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------- | ------------- | 17 | | Dn | Input n | active high | 18 | | Qn | Output n | active high | 19 | | CLK | Clock | positive edge | 20 | | OE | Output enable | active low | 21 | 22 | ## Function table 23 | 24 | | OE | CLK | Dn | Qn | 25 | |:---:|:---:|:---:|:---:| 26 | | L | / | H | H | 27 | | L | / | L | L | 28 | | L | L | X | qn0 | 29 | | H | X | X | Z | 30 | 31 | - H: HIGH voltage level 32 | - L: LOW voltage level 33 | - X: don't care 34 | - Z: high-impedance OFF-state 35 | - /: positive edge 36 | - qn0: previous state of Qn 37 | 38 | ## Pin layout 39 | 40 | TODO 41 | 42 | | | Pin | Pin | | 43 | |:---:|:---:|:---:|:---:| 44 | | OE | 1 | 20 | VCC | 45 | | D1 | 2 | 19 | Q1 | 46 | | D2 | 3 | 18 | Q2 | 47 | | D3 | 4 | 17 | Q3 | 48 | | D4 | 5 | 16 | Q4 | 49 | | D5 | 6 | 15 | Q5 | 50 | | D6 | 7 | 14 | Q6 | 51 | | D7 | 8 | 13 | Q7 | 52 | | D8 | 9 | 12 | Q8 | 53 | | GND | 10 | 11 | CLK | 54 | 55 | ## Datasheets 56 | 57 | - [CD74HC574 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc574) 58 | -------------------------------------------------------------------------------- /doc/74595.md: -------------------------------------------------------------------------------- 1 | # 74595: 8-bit shift register, output latches 2 | 3 | - Number of elements: 1 4 | - Inputs per element: 1 5 | - Outputs per element: 8 6 | - DIP: 16-pin 7 | 8 | ## Description 9 | 10 | Provides an 8-bit shift register with output latches and three-state output. 11 | 12 | ## Inputs and Outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | --------------- | ------------- | 16 | | D | serial input | active high | 17 | | Qn | output n | active high | 18 | | Q8S | serial output 8 | active high | 19 | | SCLK | shift clock | positive edge | 20 | | LCLK | latch clock | positive edge | 21 | | OE | output enable | active low | 22 | 23 | ## Function Table 24 | 25 | | OE | LE | D | Qn | 26 | |:---:|:---:|:---:|:---:| 27 | | L | H | H | H | 28 | | L | H | L | L | 29 | | L | L | X | qn0 | 30 | | H | X | X | Z | 31 | 32 | - H: HIGH voltage level 33 | - L: LOW voltage level 34 | - X: don't care 35 | - Z: high-impedance OFF-state 36 | - qn0: previous state of Qn 37 | 38 | ## Pin Configuration 39 | 40 | TODO 41 | 42 | | | Pin | Pin | | 43 | |:---:|:---:|:---:|:---:| 44 | | OE | 1 | 20 | VCC | 45 | | Q1 | 2 | 19 | Q8 | 46 | | D1 | 3 | 18 | D8 | 47 | | D2 | 4 | 17 | D7 | 48 | | Q2 | 5 | 16 | Q7 | 49 | | Q3 | 6 | 15 | Q6 | 50 | | D3 | 7 | 14 | D6 | 51 | | D4 | 8 | 13 | D5 | 52 | | Q4 | 9 | 12 | Q5 | 53 | | GND | 10 | 11 | LE | 54 | 55 | ## Datasheets 56 | 57 | - [74HC595, 74HCT595 by NXP](http://www.nxp.com/documents/data_sheet/74HC_HCT595.pdf) 58 | -------------------------------------------------------------------------------- /doc/74157.md: -------------------------------------------------------------------------------- 1 | # 74157: quad 2-line multiplexer 2 | 3 | - Type: [multiplexer](encoders_decoders.md) 4 | - Number of elements: 4 5 | - Inputs per element: 2 6 | - Outputs per element: 1 7 | - Bits: 4 8 | - DIP: 16-pin 9 | 10 | ## Description 11 | 12 | This multiplexer forwards a four-bit input from one of two sources to the output. 13 | The source is selected by the S0 select pin. A low voltage selected the input A, a high voltage the input B. 14 | 15 | A high voltage on the enable input OE ties the output to low voltage. 16 | 17 | ## Inputs and outputs 18 | 19 | | Label | Description | Signal | 20 | | ----- | --------------------------- | ----------- | 21 | | S0 | data select input 0 | active high | 22 | | OE | enable input | active low | 23 | | An | source A input of element n | active high | 24 | | Bn | source B input of element n | active high | 25 | | Yn | output of line n | active high | 26 | 27 | ## Function table 28 | 29 | | OE | S0 | An | Bn | Yn | 30 | |:---:|:---:|:---:|:---:|:---:| 31 | | H | X | X | X | L | 32 | | L | L | L | X | L | 33 | | L | L | H | X | H | 34 | | L | H | X | L | L | 35 | | L | H | X | H | H | 36 | 37 | - H: HIGH voltage level 38 | - L: LOW voltage level 39 | - X: don't care 40 | 41 | ## Pin layout 42 | 43 | ![](../dia/74157-dip.png) 44 | 45 | 46 | ## Datasheets 47 | 48 | - [CD74HC157 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc157) 49 | - [74HC157, 74HCT157 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT157.pdf) 50 | -------------------------------------------------------------------------------- /doc/74573.md: -------------------------------------------------------------------------------- 1 | # 74573: octal transparent D-type latch, tri-state output 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 20-pin 5 | - Number of elements: 8 6 | - Trigger: high 7 | - Tri-state output 8 | 9 | ## Description 10 | 11 | Provides eight transparent D-type latches with tri-state output. This chip has a 12 | different pin layout than [74373](74373.md) 13 | 14 | ## Inputs and outputs 15 | 16 | | Label | Description | Signal | 17 | | ----- | ------------- | ----------- | 18 | | Dn | input n | active high | 19 | | Qn | output n | active high | 20 | | LE | latch enable | active high | 21 | | OE | output enable | active low | 22 | 23 | ## Function table 24 | 25 | | OE | LE | Dn | Qn | 26 | |:---:|:---:|:---:|:---:| 27 | | L | H | H | H | 28 | | L | H | L | L | 29 | | L | L | X | qn0 | 30 | | H | X | X | Z | 31 | 32 | - H: HIGH voltage level 33 | - L: LOW voltage level 34 | - X: don't care 35 | - Z: high-impedance OFF-state 36 | - qn0: previous state of Qn 37 | 38 | ## Pin layout 39 | 40 | TODO 41 | 42 | | | Pin | Pin | | 43 | |:---:|:---:|:---:|:---:| 44 | | OE | 1 | 20 | VCC | 45 | | D1 | 2 | 19 | Q1 | 46 | | D2 | 3 | 18 | Q2 | 47 | | D3 | 4 | 17 | Q3 | 48 | | D4 | 5 | 16 | Q4 | 49 | | D5 | 6 | 15 | Q5 | 50 | | D6 | 7 | 14 | Q6 | 51 | | D7 | 8 | 13 | Q7 | 52 | | D8 | 9 | 12 | Q8 | 53 | | GND | 10 | 11 | LE | 54 | 55 | ## Datasheets 56 | 57 | - [74HC573, 74HCT573 by NXP](http://www.nxp.com/documents/data_sheet/74HC_HCT573.pdf) 58 | - [74LS573 by Fairchild](https://www.futurlec.com/Datasheet/74ls/74LS573.pdf) 59 | -------------------------------------------------------------------------------- /doc/7474.md: -------------------------------------------------------------------------------- 1 | # 7474: dual D-type flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Trigger: positive edge 7 | - Asynchronous set and clear 8 | 9 | ## Description 10 | 11 | Provides two positive-edge triggered D-type flip-flops with asynchronous set and clear function. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ---------------------------- | ------------- | 17 | | Dn | data input of flip-flop n | active high | 18 | | SETn | asynchronous set input | active low | 19 | | CLRn | asynchronous clear input | active low | 20 | | CLKn | clock for flip-flop n | positive edge | 21 | | Qn | output of flip-flop n | active high | 22 | | Rn | inverted output of flip-flop | active low | 23 | 24 | ## Function table 25 | 26 | | SETn | CLRn | CLKn | Dn | Qn | Rn | 27 | |:----:|:----:|:----:|:---:|:---:|:---:| 28 | | L | H | X | X | H | L | 29 | | H | L | X | X | L | H | 30 | | L | L | X | X | U | U | 31 | | H | H | / | H | H | L | 32 | | H | H | / | L | L | H | 33 | | H | H | L | X | qn0 | rn0 | 34 | 35 | - H: HIGH voltage level 36 | - L: LOW voltage level 37 | - X: don't care 38 | - /: positive edge 39 | - U: unstable/undefined 40 | - qn0: previous state of output Qn 41 | - rn0: previous state of output Rn 42 | 43 | ## Pin layout 44 | 45 | ![](../dia/7474-dip.png) 46 | 47 | ## Datasheets 48 | 49 | - [CD74HC74 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc74) 50 | - [74HC74, 74HCT74 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT74.pdf) 51 | -------------------------------------------------------------------------------- /doc/7430.md: -------------------------------------------------------------------------------- 1 | # 7430: 8-input NAND gate 2 | 3 | - Type: [Gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 1 6 | - Inputs per element: 8 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides a NAND gate with eight inputs. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | 16 | | ----- | --------------------- | 17 | | A | first input of gate | 18 | | B | second input of gate | 19 | | C | third input of gate | 20 | | D | fourth input of gate | 21 | | E | fifth input of gate | 22 | | F | sixth input of gate | 23 | | G | seventh input of gate | 24 | | H | eighth input of gate | 25 | | Y | output of gate | 26 | 27 | ## Function table 28 | 29 | | A | B | C | D | E | F | G | H | Y | 30 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 31 | | L | X | X | X | X | X | X | X | H | 32 | | X | L | X | X | X | X | X | X | H | 33 | | X | X | L | X | X | X | X | X | H | 34 | | X | X | X | L | X | X | X | X | H | 35 | | X | X | X | X | L | X | X | X | H | 36 | | X | X | X | X | X | L | X | X | H | 37 | | X | X | X | X | X | X | L | X | H | 38 | | X | X | X | X | X | X | X | L | H | 39 | | H | H | H | H | H | H | H | H | L | 40 | 41 | - H: HIGH voltage level 42 | - L: LOW voltage level 43 | - X: don't care 44 | 45 | ## Pin layout 46 | 47 | ![](../dia/7430-dip.png) 48 | 49 | ## Datasheets 50 | 51 | - [74HC30, 74HCT30 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT30.pdf) 52 | - [CD74HC30 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc30) 53 | -------------------------------------------------------------------------------- /doc/74107.md: -------------------------------------------------------------------------------- 1 | # 74107: dual J-K flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Trigger: Falling edge 7 | - Asynchronous clear 8 | 9 | ## Description 10 | 11 | Provides two J-K negative-edge triggered flip-flops with asynchronous clear function. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------------------------ | ------------- | 17 | | Jn | J input of flip-flop n | active high | 18 | | Kn | K input of flip-flop n | active high | 19 | | CLRn | asynchronous clear input | active low | 20 | | CLKn | clock for flip-flop n | negative edge | 21 | | Qn | output of flip-flop n | active high | 22 | | Rn | inverted output of flip-flop n | active low | 23 | 24 | ## Function table 25 | 26 | | Function | CLRn | CLKn | Jn | Kn | Qn | Rn | 27 | | ------------------ |:----:|:----:|:---:|:---:|:---:|:---:| 28 | | asynchronous clear | L | X | X | X | L | H | 29 | | hold | H | \\ | L | L | qn0 | rn0 | 30 | | synchronous clear | H | \\ | L | H | L | H | 31 | | synchronous set | H | \\ | H | L | H | L | 32 | | toggle | H | \\ | H | H | rn0 | qn0 | 33 | 34 | - H: HIGH voltage level 35 | - L: LOW voltage level 36 | - X: don't care 37 | - \\: negative edge 38 | - qn0: previous state of output Qn 39 | - rn0: previous state of output Rn 40 | 41 | ## Pin layout 42 | 43 | ![](../dia/74107-dip.png) 44 | 45 | ## Datasheets 46 | 47 | - [CD74HC107 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc107) 48 | - [74HC107, 74HCT107 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT107.pdf) 49 | -------------------------------------------------------------------------------- /doc/7473.md: -------------------------------------------------------------------------------- 1 | # 7473: dual J-K flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Trigger: Falling edge 7 | - Asynchronous clear 8 | 9 | ## Description 10 | 11 | Provides two J-K negative-edge triggered flip-flops with asynchronous clear function. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------------------------ | ------------- | 17 | | Jn | J input of flip-flop n | active high | 18 | | Kn | K input of flip-flop n | active high | 19 | | CLRn | asynchronous clear input | active low | 20 | | CLKn | clock for flip-flop n | negative edge | 21 | | Qn | output of flip-flop n | active high | 22 | | Rn | inverted output of flip-flop n | active low | 23 | 24 | ## Function table 25 | 26 | | Function | CLRn | CLKn | Jn | Kn | Qn | Rn | 27 | | ------------------ |:----:|:----:|:---:|:---:|:---:|:---:| 28 | | asynchronous clear | L | X | X | X | L | H | 29 | | hold | H | \\ | L | L | qn0 | rn0 | 30 | | synchronous clear | H | \\ | L | H | L | H | 31 | | synchronous set | H | \\ | H | L | H | L | 32 | | toggle | H | \\ | H | H | rn0 | qn0 | 33 | | no change | H | H | X | X | qn0 | rn0 | 34 | 35 | - H: HIGH voltage level 36 | - L: LOW voltage level 37 | - X: don't care 38 | - \\: negative edge 39 | - qn0: previous state of output Qn 40 | - rn0: previous state of output Rn 41 | 42 | ## Pin layout 43 | 44 | ![](../dia/7473-dip.png) 45 | 46 | 47 | ## Datasheets 48 | 49 | - [CD74HC73 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc73) 50 | - [74HC73, 74HCT73 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC73.pdf) 51 | -------------------------------------------------------------------------------- /doc/74173.md: -------------------------------------------------------------------------------- 1 | # 74173: quad D-type flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 16-pin 5 | - Number of elements: 4 6 | - Trigger: positive edge 7 | 8 | ## Description 9 | 10 | Provides four positive-edge triggered D-type flip-flops with input enable and output enable. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ------------------------- | ------------- | 16 | | Dn | data input of flip-flop n | active high | 17 | | CE1 | clock enable 1 | active low | 18 | | CE2 | clock enable 2 | active low | 19 | | CLK | common clock | positive edge | 20 | | CLR | common asynchronous clear | active high | 21 | | OE1 | output enable 1 | active low | 22 | | OE2 | output enable 2 | active low | 23 | | Qn | output of flip-flop n | active high | 24 | 25 | ## Function table 26 | 27 | | Function | CLR | CLK | CE1 | CE2 | Dn | Qn | 28 | | ------------------ |:---:|:---:|:---:|:---:|:---:|:---:| 29 | | | L | L | X | X | X | qn0 | 30 | | clock disabled | L | / | H | X | X | qn0 | 31 | | clock disabled | L | / | X | H | X | qn0 | 32 | | synchronous clear | L | / | L | L | L | L | 33 | | synchronous set | L | / | L | L | H | H | 34 | | asynchronous clear | H | X | X | X | X | L | 35 | 36 | - H: HIGH voltage level 37 | - L: LOW voltage level 38 | - X: don't care 39 | - /: positive edge 40 | - qn0: previous state of output Qn 41 | 42 | ## Pin layout 43 | 44 | ![](../dia/74173-dip.png) 45 | 46 | ## Datasheets 47 | 48 | - [CD74HC173 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc173) 49 | - [74HC173, 74HCT173 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT173.pdf) 50 | -------------------------------------------------------------------------------- /doc/74139.md: -------------------------------------------------------------------------------- 1 | # 74139: dual 2-bit to 4-line decoder 2 | 3 | - Type: [decoder](encoders_decoders.md) 4 | - DIP: 16-pin 5 | - Input: 2-bit 6 | - Output: 4 lines 7 | 8 | ## Description 9 | 10 | This chip provides two 2-bit to four line decoders with active low output. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ------------------------------- | ----------- | 16 | | An | encoded input of first decoder | active high | 17 | | Bn | encoded input of second decoder | active high | 18 | | Yn | output of first decoder | active low | 19 | | Zn | output of second decoder | active low | 20 | | OEA | output enable of first decoder | active low | 21 | | OEB | output enable of second decoder | active low | 22 | 23 | ## Function table 24 | 25 | | OEA | A1 | A0 | Y3 | Y2 | Y1 | Y0 | 26 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:| 27 | | H | X | X | X | X | X | H | 28 | | L | L | L | H | H | H | L | 29 | | L | L | H | H | H | L | H | 30 | | L | H | L | H | L | H | H | 31 | | L | H | H | L | H | H | H | 32 | 33 | | OEB | B1 | B0 | Z3 | Z2 | Z1 | Z0 | 34 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:| 35 | | H | X | X | X | X | X | H | 36 | | L | L | L | H | H | H | L | 37 | | L | L | H | H | H | L | H | 38 | | L | H | L | H | L | H | H | 39 | | L | H | H | L | H | H | H | 40 | 41 | - H: HIGH voltage level 42 | - L: LOW voltage level 43 | - X: don't care 44 | 45 | ## Pin layout 46 | 47 | ![](../dia/74139-dip.png) 48 | 49 | ## Datasheets 50 | 51 | - [CD74HC139 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc139) 52 | - [74HC139 74HCT139 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT139.pdf) 53 | -------------------------------------------------------------------------------- /doc/7493.md: -------------------------------------------------------------------------------- 1 | # 7493: 4-bit binary ripple counter 2 | 3 | - Number of elements: 1 4 | - Inputs per element: 0 5 | - Outputs per element: 4 6 | - Bits: 4 7 | - DIP: 14-pin 8 | 9 | ## Description 10 | 11 | TODO 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | --------------------------- | ------------- | 17 | | CLR1 | clear input 1 | active high | 18 | | CLR2 | clear input 2 | active high | 19 | | CLK1 | clock input for lowest bit | negative edge | 20 | | CLK2 | clock input for higher bits | negative edge | 21 | | Qn | counter outputs | active high | 22 | 23 | ## Function table 24 | 25 | | Mode | CLR1 | CLR2 | CLK1 | CLK2 | Q1 | Q2 | Q3 | Q4 | 26 | | ------------------ |:----:|:----:|:----:|:----:|:-----:|:-----:|:-----:|:-----:| 27 | | Reset | H | H | X | X | L | L | L | L | 28 | | Count lowest bit | L | X | \\ | X | count | q2 | q3 | q4 | 29 | | Count lowest bit | X | L | \\ | X | count | q2 | q3 | q4 | 30 | | Count highter bits | L | X | X | \\ | q1 | count | count | count | 31 | | Count highter bits | X | L | X | \\ | q1 | count | count | count | 32 | 33 | - H: HIGH voltage level 34 | - L: LOW voltage level 35 | - q: state of corresponding output one setup time prior to the clock positive edge 36 | - X: Don't care 37 | - \\: negative edge 38 | 39 | ## Pin layout 40 | 41 | TODO 42 | 43 | | | Pin | Pin | | 44 | |:----:|:---:|:---:|:----:| 45 | | CLK2 | 1 | 14 | CLK1 | 46 | | CLR1 | 2 | 13 | - | 47 | | CLR2 | 3 | 12 | Q1 | 48 | | - | 4 | 11 | Q4 | 49 | | VCC | 5 | 10 | GND | 50 | | - | 6 | 9 | Q2 | 51 | | - | 7 | 8 | Q3 | 52 | 53 | ## Datasheets 54 | 55 | - [CD74HC93 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc93) 56 | -------------------------------------------------------------------------------- /doc/7476.md: -------------------------------------------------------------------------------- 1 | # 7476: dual J-K flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 16-pin 5 | - Number of elements: 2 6 | - Trigger: negative edge 7 | - Asynchronous set and clear 8 | 9 | ## Description 10 | 11 | Provides two J-K negative-edge triggered flip-flops with set and clear function. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------------------------ | ------------- | 17 | | Jn | J input of flip flop n | active high | 18 | | Kn | K input of flip flop n | active high | 19 | | SETn | asynchronous set input | active low | 20 | | CLRn | asynchronous clear input | active low | 21 | | CLKn | clock for flip flop n | negative edge | 22 | | Qn | output of flip flop n | active high | 23 | | Rn | inverted output of flip flop n | active low | 24 | 25 | ## Function table 26 | 27 | | Function | SETn | CLRn | CLKn | Jn | Kn | Qn | Rn | 28 | | ------------------ |:----:|:----:|:----:|:---:|:---:|:---:|:---:| 29 | | undetermined | L | L | X | X | X | L | L | 30 | | asynchronous set | L | H | X | X | X | H | L | 31 | | asynchronous clear | H | L | X | X | X | L | H | 32 | | hold | H | H | \\ | L | L | qn0 | rn0 | 33 | | synchronous clear | H | H | \\ | L | H | L | H | 34 | | synchronous set | H | H | \\ | H | L | H | L | 35 | | toggle | H | H | \\ | H | H | rn0 | qn0 | 36 | 37 | - H: HIGH voltage level 38 | - L: LOW voltage level 39 | - X: don't care 40 | - \\: negative edge 41 | - qn0: previous state of output Qn 42 | - rn0: previous state of output Rn 43 | 44 | ## Pin layout 45 | 46 | ![](../dia/7476-dip.png) 47 | 48 | ## Datasheets 49 | 50 | - [7476, 74LS76 by Texas Instruments](http://www.ti.com/lit/ds/symlink/sn5476.pdf) 51 | -------------------------------------------------------------------------------- /doc/74147.md: -------------------------------------------------------------------------------- 1 | # 74147: 10-line to 4-bit BCD priority encoder 2 | 3 | - Type: [encoder](encoders_decoders.md) 4 | - DIP: 16-pin 5 | - Input: 9 lines 6 | - Output: 4-bit BCD 7 | 8 | ## Description 9 | 10 | Encodes nine input lines to a 4-bit binary output. The number of the highest line with a low voltage input is encoded an inverted 4-bit binary number. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ------------ | ---------- | 16 | | Dn | input lines | active low | 17 | | Y1 | bit 0 output | active low | 18 | | Y2 | bit 1 output | active low | 19 | | Y3 | bit 2 output | active low | 20 | | Y4 | bit 3 output | active low | 21 | 22 | ## Function table 23 | 24 | | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | Y4 | Y3 | Y2 | Y1 | 25 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 26 | | H | H | H | H | H | H | H | H | H | H | H | H | H | 27 | | X | X | X | X | X | X | X | X | L | L | H | H | L | 28 | | X | X | X | X | X | X | X | L | H | L | H | H | H | 29 | | X | X | X | X | X | X | L | H | H | H | L | L | L | 30 | | X | X | X | X | X | L | H | H | H | H | L | L | H | 31 | | X | X | X | X | L | H | H | H | H | H | L | H | L | 32 | | X | X | X | L | H | H | H | H | H | H | L | H | H | 33 | | X | X | L | H | H | H | H | H | H | H | H | L | L | 34 | | X | L | H | H | H | H | H | H | H | H | H | L | H | 35 | | L | H | H | H | H | H | H | H | H | H | H | H | L | 36 | 37 | - H: HIGH voltage level 38 | - L: LOW voltage level 39 | - X: don't care 40 | 41 | ## Pin layout 42 | 43 | ![](../dia/74147-dip.png) 44 | 45 | ## Datasheets 46 | 47 | - [CD74HC147 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc147) 48 | -------------------------------------------------------------------------------- /doc/74153.md: -------------------------------------------------------------------------------- 1 | # 74153: dual 4-line multiplexer 2 | 3 | - Type: [multiplexer](encoders_decoders.md) 4 | - Number of elements: 2 5 | - Inputs per element: 4 6 | - Outputs per element: 1 7 | - Bits: 2 8 | - DIP: 16-pin 9 | 10 | ## Description 11 | 12 | This multiplexer forwards a 2-bit input from one of four sources to the output. 13 | 14 | A high voltage on the enable input E ties the output to low voltage. 15 | 16 | ## Inputs and outputs 17 | 18 | | Label | Description | Signal | 19 | | ----- | --------------------------- | ----------- | 20 | | S0 | data select input 0 | active high | 21 | | S1 | data select input 1 | active high | 22 | | OEn | enable input of element n | active low | 23 | | An | source A input of element n | active high | 24 | | Bn | source B input of element n | active high | 25 | | Cn | source C input of element n | active high | 26 | | Dn | source D input of element n | active high | 27 | | Yn | output of element n | active high | 28 | 29 | ## Function table 30 | 31 | | OEn | S1 | S0 | An | Bn | Cn | Dn | Yn | 32 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 33 | | H | X | X | X | X | X | X | L | 34 | | L | L | L | L | X | X | X | L | 35 | | L | L | L | H | X | X | X | H | 36 | | L | L | H | X | L | X | X | L | 37 | | L | L | H | X | H | X | X | H | 38 | | L | H | L | X | X | L | X | L | 39 | | L | H | L | X | X | H | X | H | 40 | | L | H | H | X | X | X | L | L | 41 | | L | H | H | X | X | X | H | H | 42 | 43 | - H: HIGH voltage level 44 | - L: LOW voltage level 45 | - X: don't care 46 | 47 | ## Pin layout 48 | 49 | ![](../dia/74153-dip.png) 50 | 51 | ## Datasheets 52 | 53 | - [CD74HC153 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc153) 54 | - [74HC153, 74HCT153 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT153.pdf) 55 | -------------------------------------------------------------------------------- /doc/74112.md: -------------------------------------------------------------------------------- 1 | # 74112: dual J-K flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 16-pin 5 | - Number of elements: 2 6 | - Trigger: negative edge 7 | - Asynchronous set and clear 8 | 9 | ## Description 10 | 11 | Provides two J-K negative-edge triggered flip-flops with set and clear function. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------------------------ | ------------- | 17 | | Jn | J input of flip flop n | active high | 18 | | Kn | K input of flip flop n | active high | 19 | | SETn | asynchronous set input | active low | 20 | | CLRn | asynchronous clear input | active low | 21 | | CLKn | clock for flip flop n | negative edge | 22 | | Qn | output of flip flop n | active high | 23 | | Rn | inverted output of flip flop n | active low | 24 | 25 | ## Function table 26 | 27 | | Function | SETn | CLRn | CLKn | Jn | Kn | Qn | Rn | 28 | | ------------------ |:----:|:----:|:----:|:---:|:---:|:---:|:---:| 29 | | undetermined | L | L | X | X | X | H | L | 30 | | asynchronous set | L | H | X | X | X | H | L | 31 | | asynchronous clear | H | L | X | X | X | L | H | 32 | | hold | H | H | \\ | L | L | qn0 | rn0 | 33 | | synchronous clear | H | H | \\ | L | H | L | H | 34 | | synchronous set | H | H | \\ | H | L | H | L | 35 | | toggle | H | H | \\ | H | H | rn0 | qn0 | 36 | 37 | - H: HIGH voltage level 38 | - L: LOW voltage level 39 | - X: don't care 40 | - \\: negative edge 41 | - qn0: previous state of output Qn 42 | - rn0: previous state of output Rn 43 | 44 | ## Pin layout 45 | 46 | ![](../dia/74112-dip.png) 47 | 48 | ## Datasheets 49 | 50 | - [CD74HC112 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc112) 51 | - [74HC112, 74HCT112 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT112.pdf) 52 | -------------------------------------------------------------------------------- /doc/74109.md: -------------------------------------------------------------------------------- 1 | # 74109: dual J-not-K flip-flop 2 | 3 | - Type: [flip-flop](flip_flops.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Trigger: Rising edge 7 | - Asynchronous set and clear 8 | 9 | ## Description 10 | 11 | Provides two J-Not-K positive-edge triggered flip-flops with set and clear function. 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------------------------ | ------------- | 17 | | Jn | J input of flip-flop n | active high | 18 | | Kn | K input of flip-flop n | active low | 19 | | SETn | asynchronous set input | active low | 20 | | CLRn | asynchronous clear input | active low | 21 | | CLKn | clock for flip-flop n () | positive edge | 22 | | Qn | output of flip-flop n | active high | 23 | | Rn | inverted output of flip-flop n | active low | 24 | 25 | ## Function table 26 | 27 | | Function | SETn | CLRn | CLKn | Jn | Kn | Qn | Rn | 28 | | ------------------ |:----:|:----:|:----:|:---:|:---:|:---:|:---:| 29 | | undetermined | L | L | X | X | X | H | H | 30 | | asynchronous set | L | H | X | X | X | H | L | 31 | | asynchronous clear | H | L | X | X | X | L | H | 32 | | synchronous clear | H | H | / | L | L | L | H | 33 | | hold | H | H | / | L | H | qn0 | rn0 | 34 | | toggle | H | H | / | H | L | rn0 | qn0 | 35 | | synchronous set | H | H | / | H | H | H | L | 36 | 37 | - H: HIGH voltage level 38 | - L: LOW voltage level 39 | - X: don't care 40 | - /: positive edge 41 | - qn0: previous state of output Qn 42 | - rn0: previous state of output Rn 43 | 44 | ## Pin layout 45 | 46 | ![](../dia/74109-dip.png) 47 | 48 | ## Datasheets 49 | 50 | - [CD74HC1099 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc109) 51 | - [74HC109, 74HCT109 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT109.pdf) 52 | -------------------------------------------------------------------------------- /doc/flip_flops.md: -------------------------------------------------------------------------------- 1 | # Flip-flops and Latches 2 | 3 | ## J-K flip-flops 4 | 5 | | Type | Elements | Trigger | Comments | 6 | | ----------------- |:--------:| ------------- | -------------------------------------------- | 7 | | [7473](7473.md) | 2 | negative edge | asynchronous clear, center supply | 8 | | [7476](7476.md) | 2 | negative edge | asynchronous set and clear, center supply | 9 | | [74107](74107.md) | 2 | negative edge | asynchronous clear | 10 | | [74109](74109.md) | 2 | positive edge | K input inverted, asynchronous set and clear | 11 | | [74112](74112.md) | 2 | negative edge | asynchronous set and clear | 12 | 13 | 14 | ## D-type flip-flops 15 | 16 | | Type | Elements | Trigger | Comments | 17 | | ----------------- |:--------:| ------------- | ------------------------------------ | 18 | | [7474](7474.md) | 2 | positive edge | asynchronous set and clear | 19 | | [74173](74173.md) | 4 | positive edge | tri-state output, asynchronous clear | 20 | | [74174](74174.md) | 6 | positive edge | asynchronous clear | 21 | | [74175](74175.md) | 4 | positive edge | inverted outputs, asynchronous clear | 22 | | [74273](74273.md) | 8 | positive edge | asynchronous clear | 23 | | [74374](74374.md) | 8 | positive edge | tri-state output | 24 | | [74377](74377.md) | 8 | positive edge | clock enable | 25 | | [74574](74574.md) | 8 | positive edge | tri-state output | 26 | 27 | ## D-type latches 28 | 29 | | Type | Elements | Trigger | Comments | 30 | | ----------------- |:--------:| ------- | ---------------- | 31 | | [7475](7475.md) | 4 | high | center supply | 32 | | [74373](74373.md) | 8 | high | tri-state output | 33 | | [74573](74573.md) | 8 | high | tri-state output | 34 | -------------------------------------------------------------------------------- /doc/gates.md: -------------------------------------------------------------------------------- 1 | # Gates 2 | 3 | ## AND gates 4 | 5 | | Type | Gates | Inputs per gate | 6 | | --------------- |:-----:|:---------------:| 7 | | [7408](7408.md) | 4 | 2 | 8 | | [7411](7411.md) | 3 | 3 | 9 | | [7421](7421.md) | 2 | 4 | 10 | 11 | ## NAND gates 12 | 13 | | Type | Gates | Inputs per gate | Comments | 14 | | ----------------- |:-----:|:---------------:| --------------------- | 15 | | [7400](7400.md) | 4 | 2 | | 16 | | [7403](7403.md) | 4 | 2 | open collector output | 17 | | [7410](7410.md) | 3 | 3 | | 18 | | [7420](7420.md) | 2 | 4 | | 19 | | [7430](7430.md) | 1 | 8 | | 20 | | [74132](74132.md) | 4 | 2 | Schmitt trigger | 21 | 22 | ## OR gates 23 | 24 | | Type | Gates | Inputs per gate | 25 | | ------------------- |:-----:|:---------------:| 26 | | [7432](7432.md) | 4 | 2 | 27 | | [744075](744075.md) | 3 | 3 | 28 | 29 | ## NOR gates 30 | 31 | | Type | Gates | Inputs per gate | 32 | | ------------------- |:-----:|:---------------:| 33 | | [7402](7402.md) | 4 | 2 | 34 | | [7427](7427.md) | 3 | 3 | 35 | | [744002](744002.md) | 2 | 4 | 36 | 37 | ## XOR gates 38 | 39 | | Type | Gates | Inputs per gate | 40 | | --------------- |:-----:|:---------------:| 41 | | [7486](7486.md) | 4 | 2 | 42 | 43 | ## XNOR gates 44 | 45 | | Type | Gates | Inputs per gate | 46 | | ------------------- |:-----:|:---------------:| 47 | | [747266](747266.md) | 4 | 2 | 48 | 49 | ## Gate combinations 50 | 51 | | Type | Gates | Inputs per gate | Type | 52 | | ------------------- |:-----:|:---------------:| ------------- | 53 | | [7451](7451.md) | 2 | 2/3 | AND-OR-invert | 54 | -------------------------------------------------------------------------------- /doc/74238.md: -------------------------------------------------------------------------------- 1 | # 74238: 3-bit to 8-line decoder 2 | 3 | - Type: [decoder](encoders_decoders.md) 4 | - DIP: 16-pin 5 | - Input: 3-bit 6 | - Output: 8 lines 7 | 8 | ## Description 9 | 10 | This chip provides an 3-bit to eight line decoder. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | --------------------- | ----------- | 16 | | An | encoded input | active high | 17 | | Yn | output | active high | 18 | | OE1 | output enable input 1 | active low | 19 | | OE2 | output enable input 2 | active low | 20 | | OE3 | output enable input 3 | active high | 21 | 22 | 23 | ## Function table 24 | 25 | | OE1 | OE2 | OE3 | A2 | A1 | A0 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 | 26 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 27 | | H | X | X | X | X | X | L | L | L | L | L | L | L | L | 28 | | X | H | X | X | X | X | L | L | L | L | L | L | L | L | 29 | | X | X | L | X | X | X | L | L | L | L | L | L | L | L | 30 | | L | L | H | L | L | L | L | L | L | L | L | L | L | H | 31 | | L | L | H | L | L | H | L | L | L | L | L | L | H | L | 32 | | L | L | H | L | H | L | L | L | L | L | L | H | L | L | 33 | | L | L | H | L | H | H | L | L | L | L | H | L | L | L | 34 | | L | L | H | H | L | L | L | L | L | H | L | L | L | L | 35 | | L | L | H | H | L | H | L | L | H | L | L | L | L | L | 36 | | L | L | H | H | H | L | L | H | L | L | L | L | L | L | 37 | | L | L | H | H | H | H | H | L | L | L | L | L | L | L | 38 | 39 | 40 | - H: HIGH voltage level 41 | - L: LOW voltage level 42 | - X: don't care 43 | 44 | ## Pin layout 45 | 46 | ![](../dia/74238-dip.png) 47 | 48 | ## Datasheets 49 | 50 | - [CD74HC238 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc238) 51 | -------------------------------------------------------------------------------- /doc/7442.md: -------------------------------------------------------------------------------- 1 | # 7442: 4-bit BCD to 10-line decoder, active low output 2 | 3 | - Type: [decoder](encoders_decoders.md) 4 | - DIP: 16-pin 5 | - Input: 4-bit BCD 6 | - Output: 10 lines 7 | 8 | ## Description 9 | 10 | Decodes a 4-bit BCD to ten output lines. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | ------------ | ----------- | 16 | | Dn | input lines | active high | 17 | | Yn | output lines | active low | 18 | 19 | ## Function table 20 | 21 | | D4 | D3 | D2 | D1 | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | Y8 | Y9 | 22 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 23 | | L | L | L | L | L | H | H | H | H | H | H | H | H | H | 24 | | L | L | L | H | H | L | H | H | H | H | H | H | H | H | 25 | | L | L | H | L | H | H | L | H | H | H | H | H | H | H | 26 | | L | L | H | H | H | H | H | L | H | H | H | H | H | H | 27 | | L | H | L | L | H | H | H | H | L | H | H | H | H | H | 28 | | L | H | L | H | H | H | H | H | H | L | H | H | H | H | 29 | | L | H | H | L | H | H | H | H | H | H | L | H | H | H | 30 | | L | H | H | H | H | H | H | H | H | H | H | L | H | H | 31 | | H | L | L | L | H | H | H | H | H | H | H | H | L | H | 32 | | H | L | L | H | H | H | H | H | H | H | H | H | H | L | 33 | | H | L | H | X | H | H | H | H | H | H | H | H | H | H | 34 | | H | H | X | X | H | H | H | H | H | H | H | H | H | H | 35 | 36 | - H: HIGH voltage level 37 | - L: LOW voltage level 38 | - X: don't care 39 | 40 | ## Pin layout 41 | 42 | ![](../dia/7442-dip.png) 43 | 44 | ## Datasheets 45 | 46 | - [74HC42, 74HCT42 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC42.pdf) 47 | - [7442A, 74LS42 by Texas Instruments](http://www.farnell.com/datasheets/1446836.pdf) 48 | -------------------------------------------------------------------------------- /doc/74137.md: -------------------------------------------------------------------------------- 1 | # 74137: 3-line to 8-line decoder, latched input 2 | 3 | - Type: [decoder](encoders_decoders.md) 4 | - DIP: 16-pin 5 | - Input: 3-bit 6 | - Output: 8 lines 7 | 8 | ## Description 9 | 10 | This chip provides an 3-bit to eight line decoder with active low output. The 3-bit input is loaded in a D-type latch. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | --------------------- | ----------- | 16 | | An | encoded input | active high | 17 | | LE | load enable | active low | 18 | | Yn | output | active low | 19 | | OE1 | output enable input 1 | active high | 20 | | OE2 | output enable input 2 | active low | 21 | 22 | ## Function table 23 | 24 | | LE | OE1 | OE2 | A2 | A1 | A0 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 | 25 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 26 | | X | X | H | X | X | X | H | H | H | H | H | H | H | H | 27 | | X | L | X | X | X | X | H | H | H | H | H | H | H | H | 28 | | L | H | L | L | L | L | H | H | H | H | H | H | H | L | 29 | | L | H | L | L | L | H | H | H | H | H | H | H | L | H | 30 | | L | H | L | L | H | L | H | H | H | H | H | L | H | H | 31 | | L | H | L | L | H | H | H | H | H | H | L | H | H | H | 32 | | L | H | L | H | L | L | H | H | H | L | H | H | H | H | 33 | | L | H | L | H | L | H | H | H | L | H | H | H | H | H | 34 | | L | H | L | H | H | L | H | L | H | H | H | H | H | H | 35 | | L | H | L | H | H | H | L | H | H | H | H | H | H | H | 36 | | H | H | L | X | X | X | y7 | y6 | y5 | y4 | y3 | y2 | y1 | y0 | 37 | 38 | - H: HIGH voltage level 39 | - L: LOW voltage level 40 | - X: don't care 41 | - yn: previous state of output Yn 42 | 43 | ## Pin layout 44 | 45 | ![](../dia/74137-dip.png) 46 | 47 | ## Datasheets 48 | 49 | - [CD74HC137 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc137) 50 | -------------------------------------------------------------------------------- /doc/74138.md: -------------------------------------------------------------------------------- 1 | # 74138: 3-line to 8-line decoder 2 | 3 | - Type: [decoder](encoders_decoders.md) 4 | - DIP: 16-pin 5 | - Input: 3-bit 6 | - Output: 8 lines 7 | 8 | ## Description 9 | 10 | This chip provides an 3-bit to eight line decoder with active low output. 11 | 12 | ## Inputs and outputs 13 | 14 | | Label | Description | Signal | 15 | | ----- | --------------------- | ----------- | 16 | | An | encoded input | active high | 17 | | Yn | output | active low | 18 | | OE1 | output enable input 1 | active low | 19 | | OE2 | output enable input 2 | active low | 20 | | OE3 | output enable input 3 | active high | 21 | 22 | ## Function table 23 | 24 | | OE1 | OE2 | OE3 | A2 | A1 | A0 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 | 25 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:| 26 | | H | X | X | X | X | X | H | H | H | H | H | H | H | H | 27 | | X | H | X | X | X | X | H | H | H | H | H | H | H | H | 28 | | X | X | L | X | X | X | H | H | H | H | H | H | H | H | 29 | | L | L | H | L | L | L | H | H | H | H | H | H | H | L | 30 | | L | L | H | L | L | H | H | H | H | H | H | H | L | H | 31 | | L | L | H | L | H | L | H | H | H | H | H | L | H | H | 32 | | L | L | H | L | H | H | H | H | H | H | L | H | H | H | 33 | | L | L | H | H | L | L | H | H | H | L | H | H | H | H | 34 | | L | L | H | H | L | H | H | H | L | H | H | H | H | H | 35 | | L | L | H | H | H | L | H | L | H | H | H | H | H | H | 36 | | L | L | H | H | H | H | L | H | H | H | H | H | H | H | 37 | 38 | - H: HIGH voltage level 39 | - L: LOW voltage level 40 | - X: don't care 41 | 42 | ## Pin layout 43 | 44 | ![](../dia/74138-dip.png) 45 | 46 | ## Datasheets 47 | 48 | - [CD74HC138 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc138) 49 | - [74HC138, 74HCT138 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT138.pdf) 50 | -------------------------------------------------------------------------------- /in-progress/74x299.md: -------------------------------------------------------------------------------- 1 | # 74x299 - 8-bit bidirectional universal shift/storage register with three-state outputs 2 | 3 | * Number of elements: 8 4 | * Inputs per element: 1 5 | * DIP: 20-pin 6 | 7 | ## Function Table 8 | 9 | 10 | | Function | CLR | S0 | S1 | G1 | G2 | CLK | SL | SR | A/QA | B/QB | C/QC | D/QD | E/QE | F/QF | G/QG | H/GH | QA' | QH' | 11 | |:-----------:|:---:|:---:|:---:|:---:|:---:|:---:|:----:|:----:|:----:|:----:|:----:|:----:|:----:|:----:|:---:|:---:|:---:|:---:| 12 | | Clear | L | X | L | L | L | X | X | X | L | L | L | L | L | L | L | L | L | L | 13 | | Clear | L | L | X | L | L | X | X | X | L | L | L | L | L | L | L | L | L | L | 14 | | Clear | L | H | H | X | X | X | X | X | X | X | X | X | X | X | X | X | L | L | 15 | | Hold | H | L | L | L | L | X | X | X | QA0 | QB0 | QC0 | QD0 | QE0 | QF0 | QG0 | QH0 | QA0 | QH0 | 16 | | Hold | H | X | X | L | L | L | X | X | QA0 | QB0 | QC0 | QD0 | QE0 | QF0 | QG0 | QH0 | QA0 | QH0 | 17 | | Shift Right | H | L | H | L | L | ^ | X | H | H | QAn | QBn | QCn | QDn | QEn | QFn | QGn | H | QGn | 18 | | Shift Right | H | L | H | L | L | ^ | X | L | L | QAn | QBn | QCn | QDn | QEn | QFn | QGn | L | QGn | 19 | | Shift Left | H | H | L | L | L | ^ | H | X | QBn | QCn | QDn | QEn | QFn | QGn | QHn | H | QBn | H | 20 | | Shift Left | H | H | L | L | L | ^ | L | X | QBn | QCn | QDn | QEn | QFn | QGn | QHn | L | QBn | L | 21 | | Load | H | H | H | X | X | ^ | X | X | a | b | c | d | e | f | g | h | a | h | 22 | 23 | H: HIGH voltage level 24 | L: LOW voltage level 25 | X: don't care 26 | a...h: the level of the inputs A through H 27 | 28 | ## Pin Configuration 29 | 30 | | | Pin | Pin | | 31 | |:----:|:---:|:---:|:----:| 32 | | S0 | 1 | 20 | VCC | 33 | | G1 | 2 | 19 | S1 | 34 | | G2 | 3 | 18 | SL | 35 | | G/QG | 4 | 17 | QH' | 36 | | E/QE | 5 | 16 | H/QH | 37 | | C/QC | 6 | 15 | F/QF | 38 | | A/QA | 7 | 14 | D/QD | 39 | | QA' | 8 | 13 | B/QB | 40 | | CLR | 9 | 12 | CLK | 41 | | GND | 10 | 11 | SR | 42 | -------------------------------------------------------------------------------- /doc/7451.md: -------------------------------------------------------------------------------- 1 | # 7451: AND-OR-invert gates 2 | 3 | - Type: [gate](gates.md) 4 | - DIP: 14-pin 5 | - Number of elements: 2 6 | - Inputs per element: 4/6 7 | - Outputs per element: 1 8 | 9 | ## Description 10 | 11 | Provides two AND-OR-invert gates with two or three inputs per NAND gate. The basic model has 12 | only two inputs per NAND gate, the SN74LS51 has an additional input E1 and F1 for each NAND gate 13 | of the first element. 14 | 15 | ## Inputs and outputs 16 | 17 | | Label | Description | 18 | | ----- | ----------------------------------------------------- | 19 | | An | first input of first NAND gate of element n | 20 | | Bn | second input of first NAND gate of element n | 21 | | Cn | optional third input of first NAND gate of element 1 | 22 | | D1 | first input of second NAND gate of element n | 23 | | En | second input of second NAND gate of element n | 24 | | F1 | optional third input of second NAND gate of element 1 | 25 | | Yn | output of element n | 26 | 27 | ## Function table 28 | 29 | Function table for element with four inputs: 30 | 31 | | An | Bn | Dn | En | Yn | 32 | |:---:|:---:|:---:|:---:|:---:| 33 | | L | X | L | X | H | 34 | | L | X | X | L | H | 35 | | X | L | L | X | H | 36 | | X | L | X | L | H | 37 | | H | H | X | X | L | 38 | | X | X | H | H | L | 39 | 40 | Function table for element with six inputs: 41 | 42 | | A1 | B1 | C1 | D1 | E1 | F1 | Yn | 43 | |:---:|:---:|:---:|:---:|:---:|:---:|:---:| 44 | | L | X | X | L | X | X | H | 45 | | L | X | X | X | L | X | H | 46 | | L | X | X | X | X | L | H | 47 | | X | L | X | L | X | X | H | 48 | | X | L | X | X | L | X | H | 49 | | X | L | X | X | X | L | H | 50 | | X | X | L | L | X | X | H | 51 | | X | X | L | X | L | X | H | 52 | | X | X | L | X | X | L | H | 53 | | H | H | H | X | X | X | L | 54 | | X | X | X | H | H | H | L | 55 | 56 | - H: HIGH voltage level 57 | - L: LOW voltage level 58 | - X: don't care 59 | 60 | ## Pin layout 61 | 62 | ![](../dia/7451-dip.png) 63 | 64 | ## Datasheets 65 | 66 | - [SN74LS51 by Texas Instruments](http://www.ti.com/lit/gpn/sn74ls51) 67 | -------------------------------------------------------------------------------- /doc/74163.md: -------------------------------------------------------------------------------- 1 | # 74163: 4-bit synchronous binary counter 2 | 3 | - Number of elements: 1 4 | - Inputs per element: 4 5 | - Outputs per element: 4 6 | - Bits: 4 7 | - DIP: 16-pin 8 | 9 | ## Description 10 | 11 | TODO 12 | 13 | 14 | ## Inputs and outputs 15 | 16 | | Label | Description | Signal | 17 | | ----- | --------------------------- | ------------- | 18 | | CE | synchronous clear enable | active low | 19 | | CLK | clock | positive edge | 20 | | CEP | count enable parallel input | active high | 21 | | CET | count enable trickle input | active high | 22 | | LE | load enable input | active low | 23 | | Dn | data inputs | active high | 24 | | Qn | data outputs | active high | 25 | | TC | terminal count output | active high | 26 | 27 | ## Function table 28 | 29 | | Mode | CE | CLK | CEP | CET | LE | Dn | Qn | TC | 30 | | ------------- |:---:|:---:|:---:|:---:|:---:|:---:|:-----:|:---:| 31 | | Reset | L | / | X | X | X | X | L | L | 32 | | Parallel load | H | / | X | X | l | l | L | L | 33 | | Parallel load | H | / | X | X | l | h | H | t | 34 | | Count | H | / | h | h | h | X | count | t | 35 | | Hold | H | X | l | X | h | X | qn | L | 36 | | Hold | H | X | X | l | h | X | qn | L | 37 | 38 | - H: HIGH voltage level 39 | - L: LOW voltage level 40 | - h: HIGH voltage level one setup time prior to the clock positive edge 41 | - l: LOW voltage level one setup time prior to clock positive edge 42 | - q: state of corresponding output one setup time prior to the clock positive edge 43 | - t: HIGH when CET is HIGH and the counter is at terminal count (HHHH) 44 | - X: Don't care 45 | - /: positive edge 46 | 47 | ## Pin layout 48 | 49 | TODO 50 | 51 | | | Pin | Pin | | 52 | |:---:|:---:|:---:|:---:| 53 | | CE | 1 | 16 | VCC | 54 | | CLK | 2 | 15 | TC | 55 | | D1 | 3 | 14 | Q1 | 56 | | D2 | 4 | 13 | Q2 | 57 | | D3 | 5 | 12 | Q3 | 58 | | D4 | 6 | 11 | Q4 | 59 | | CEP | 7 | 10 | CET | 60 | | GND | 8 | 9 | LE | 61 | 62 | ## Datasheets 63 | 64 | - [CD74HC163 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc163) 65 | - [74HC163, 74HCT163 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC_HCT163.pdf) 66 | -------------------------------------------------------------------------------- /doc/74161.md: -------------------------------------------------------------------------------- 1 | # 74161: 4-bit synchronous binary counter 2 | 3 | - Number of elements: 1 4 | - Inputs per element: 4 5 | - Outputs per element: 4 6 | - Bits: 4 7 | - DIP: 16-pin 8 | 9 | ## Description 10 | 11 | TODO 12 | 13 | ## Inputs and outputs 14 | 15 | | Label | Description | Signal | 16 | | ----- | ------------------------------- | ------------- | 17 | | Dn | data inputs | active high | 18 | | CEP | count Enable Parallel input | active high | 19 | | CET | count Enable Trickle input | active high | 20 | | CLK | clock input | positive edge | 21 | | LE | load enable input | active low | 22 | | CLR | asynchronous master reset input | active low | 23 | | TC | terminal count output | active high | 24 | | Qn | data outputs | active high | 25 | 26 | ## Function table 27 | 28 | | Mode | CLR | CLK | CEP | CET | LE | Dn | Qn | TC | 29 | | ------------- |:---:|:---:|:---:|:---:|:---:|:---:|:-----:|:---:| 30 | | Reset | L | X | X | X | X | X | L | L | 31 | | Parallel load | H | / | X | X | l | l | L | L | 32 | | Parallel load | H | / | X | X | l | h | H | t | 33 | | Count | H | / | h | h | h | X | count | t | 34 | | Hold | H | X | l | X | h | X | qn | t | 35 | | Hold | H | X | X | l | h | X | qn | L | 36 | 37 | - H: HIGH voltage level 38 | - L: LOW voltage level 39 | - h: HIGH voltage level one setup time prior to the clock positive edge 40 | - l: LOW voltage level one setup time prior to clock positive edge 41 | - q: state of corresponding output one setup time prior to the clock positive edge 42 | - t: HIGH when CET is HIGH and the counter is at terminal count (HHHH) 43 | - X: Don't care 44 | - /: positive edge 45 | 46 | ## Pin layout 47 | 48 | TODO 49 | 50 | | | Pin | Pin | | 51 | |:---:|:---:|:---:|:---:| 52 | | CLR | 1 | 16 | VCC | 53 | | CLK | 2 | 15 | TC | 54 | | D1 | 3 | 14 | Q1 | 55 | | D2 | 4 | 13 | Q2 | 56 | | D3 | 5 | 12 | Q3 | 57 | | D4 | 6 | 11 | Q4 | 58 | | CEP | 7 | 10 | CET | 59 | | GND | 8 | 9 | LE | 60 | 61 | ## Datasheets 62 | 63 | - [CD74HC161 by Texas Instruments](http://www.ti.com/lit/gpn/cd74hc161) 64 | - [74HC161 by Nexperia](https://assets.nexperia.com/documents/data-sheet/74HC161.pdf) 65 | -------------------------------------------------------------------------------- /doc/chip.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 19 | 21 | 39 | 41 | 42 | 44 | image/svg+xml 45 | 47 | 48 | 49 | 50 | 51 | 55 | 62 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /doc/7485.md: -------------------------------------------------------------------------------- 1 | # 7475: 4-bit magnitude comparator 2 | 3 | - DIP: 16-pin 4 | - Number of elements: 1 5 | 6 | ## Description 7 | 8 | Provides a four-bit magnitude comparator. 9 | 10 | ## Inputs and outputs 11 | 12 | | Label | Description | Signal | 13 | | ----- | ------------------------- | ----------- | 14 | | An | input of four-bit value A | active high | 15 | | Bn | input of four-bit value B | active high | 16 | | CLT | cascading input of A < B | active high | 17 | | CGT | cascading input of A > B | active high | 18 | | CEQ | cascading input of A = B | active high | 19 | | YLT | output of A < B | active high | 20 | | YGT | output of A > B | active high | 21 | | YEQ | output of A = B | active high | 22 | 23 | ## Function table 24 | 25 | | A4, B4 | A3, B3 | A2, B2 | A1, B1 | CGT | CLT | CEQ | YGT | YLT | YEQ | 26 | |:------:|:------:|:------:|:------:|:---:|:---:|:---:|:---:|:---:|:---:| 27 | | A4>B4 | X | X | X | X | X | X | H | L | L | 28 | | A4B3 | X | X | X | X | X | H | L | L | 30 | | A4=B4 | A3B2 | X | X | X | X | H | L | L | 32 | | A4=B4 | A3=B3 | A2B1 | X | X | X | H | L | L | 34 | | A4=B4 | A3=B3 | A2=B2 | A1 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | 9 | This version of the GNU Lesser General Public License incorporates 10 | the terms and conditions of version 3 of the GNU General Public 11 | License, supplemented by the additional permissions listed below. 12 | 13 | 0. Additional Definitions. 14 | 15 | As used herein, "this License" refers to version 3 of the GNU Lesser 16 | General Public License, and the "GNU GPL" refers to version 3 of the GNU 17 | General Public License. 18 | 19 | "The Library" refers to a covered work governed by this License, 20 | other than an Application or a Combined Work as defined below. 21 | 22 | An "Application" is any work that makes use of an interface provided 23 | by the Library, but which is not otherwise based on the Library. 24 | Defining a subclass of a class defined by the Library is deemed a mode 25 | of using an interface provided by the Library. 26 | 27 | A "Combined Work" is a work produced by combining or linking an 28 | Application with the Library. The particular version of the Library 29 | with which the Combined Work was made is also called the "Linked 30 | Version". 31 | 32 | The "Minimal Corresponding Source" for a Combined Work means the 33 | Corresponding Source for the Combined Work, excluding any source code 34 | for portions of the Combined Work that, considered in isolation, are 35 | based on the Application, and not on the Linked Version. 36 | 37 | The "Corresponding Application Code" for a Combined Work means the 38 | object code and/or source code for the Application, including any data 39 | and utility programs needed for reproducing the Combined Work from the 40 | Application, but excluding the System Libraries of the Combined Work. 41 | 42 | 1. Exception to Section 3 of the GNU GPL. 43 | 44 | You may convey a covered work under sections 3 and 4 of this License 45 | without being bound by section 3 of the GNU GPL. 46 | 47 | 2. Conveying Modified Versions. 48 | 49 | If you modify a copy of the Library, and, in your modifications, a 50 | facility refers to a function or data to be supplied by an Application 51 | that uses the facility (other than as an argument passed when the 52 | facility is invoked), then you may convey a copy of the modified 53 | version: 54 | 55 | a) under this License, provided that you make a good faith effort to 56 | ensure that, in the event an Application does not supply the 57 | function or data, the facility still operates, and performs 58 | whatever part of its purpose remains meaningful, or 59 | 60 | b) under the GNU GPL, with none of the additional permissions of 61 | this License applicable to that copy. 62 | 63 | 3. Object Code Incorporating Material from Library Header Files. 64 | 65 | The object code form of an Application may incorporate material from 66 | a header file that is part of the Library. You may convey such object 67 | code under terms of your choice, provided that, if the incorporated 68 | material is not limited to numerical parameters, data structure 69 | layouts and accessors, or small macros, inline functions and templates 70 | (ten or fewer lines in length), you do both of the following: 71 | 72 | a) Give prominent notice with each copy of the object code that the 73 | Library is used in it and that the Library and its use are 74 | covered by this License. 75 | 76 | b) Accompany the object code with a copy of the GNU GPL and this license 77 | document. 78 | 79 | 4. Combined Works. 80 | 81 | You may convey a Combined Work under terms of your choice that, 82 | taken together, effectively do not restrict modification of the 83 | portions of the Library contained in the Combined Work and reverse 84 | engineering for debugging such modifications, if you also do each of 85 | the following: 86 | 87 | a) Give prominent notice with each copy of the Combined Work that 88 | the Library is used in it and that the Library and its use are 89 | covered by this License. 90 | 91 | b) Accompany the Combined Work with a copy of the GNU GPL and this license 92 | document. 93 | 94 | c) For a Combined Work that displays copyright notices during 95 | execution, include the copyright notice for the Library among 96 | these notices, as well as a reference directing the user to the 97 | copies of the GNU GPL and this license document. 98 | 99 | d) Do one of the following: 100 | 101 | 0) Convey the Minimal Corresponding Source under the terms of this 102 | License, and the Corresponding Application Code in a form 103 | suitable for, and under terms that permit, the user to 104 | recombine or relink the Application with a modified version of 105 | the Linked Version to produce a modified Combined Work, in the 106 | manner specified by section 6 of the GNU GPL for conveying 107 | Corresponding Source. 108 | 109 | 1) Use a suitable shared library mechanism for linking with the 110 | Library. A suitable mechanism is one that (a) uses at run time 111 | a copy of the Library already present on the user's computer 112 | system, and (b) will operate properly with a modified version 113 | of the Library that is interface-compatible with the Linked 114 | Version. 115 | 116 | e) Provide Installation Information, but only if you would otherwise 117 | be required to provide such information under section 6 of the 118 | GNU GPL, and only to the extent that such information is 119 | necessary to install and execute a modified version of the 120 | Combined Work produced by recombining or relinking the 121 | Application with a modified version of the Linked Version. (If 122 | you use option 4d0, the Installation Information must accompany 123 | the Minimal Corresponding Source and Corresponding Application 124 | Code. If you use option 4d1, you must provide the Installation 125 | Information in the manner specified by section 6 of the GNU GPL 126 | for conveying Corresponding Source.) 127 | 128 | 5. Combined Libraries. 129 | 130 | You may place library facilities that are a work based on the 131 | Library side by side in a single library together with other library 132 | facilities that are not Applications and are not covered by this 133 | License, and convey such a combined library under terms of your 134 | choice, if you do both of the following: 135 | 136 | a) Accompany the combined library with a copy of the same work based 137 | on the Library, uncombined with any other library facilities, 138 | conveyed under the terms of this License. 139 | 140 | b) Give prominent notice with the combined library that part of it 141 | is a work based on the Library, and explaining where to find the 142 | accompanying uncombined form of the same work. 143 | 144 | 6. Revised Versions of the GNU Lesser General Public License. 145 | 146 | The Free Software Foundation may publish revised and/or new versions 147 | of the GNU Lesser General Public License from time to time. Such new 148 | versions will be similar in spirit to the present version, but may 149 | differ in detail to address new problems or concerns. 150 | 151 | Each version is given a distinguishing version number. If the 152 | Library as you received it specifies that a certain numbered version 153 | of the GNU Lesser General Public License "or any later version" 154 | applies to it, you have the option of following the terms and 155 | conditions either of that published version or of any later version 156 | published by the Free Software Foundation. If the Library as you 157 | received it does not specify a version number of the GNU Lesser 158 | General Public License, you may choose any version of the GNU Lesser 159 | General Public License ever published by the Free Software Foundation. 160 | 161 | If the Library as you received it specifies that a proxy can decide 162 | whether future versions of the GNU Lesser General Public License shall 163 | apply, that proxy's public statement of acceptance of any version is 164 | permanent authorization for you to choose that version for the 165 | Library. 166 | 167 | 168 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Logi7400 2 | 3 | [Logisim](http://www.cburch.com/logisim/) 7400 series integrated circuits library. 4 | 5 | ## Variants 6 | 7 | There are two variants of the library with different circuit appearances available: 8 | 9 | * In the classic **Logi7400dip** library, the circuit appearance reflects the physical pin layout of the DIP packaged chips. 10 | * The new **Logi7400ic** library provides a logical circuit appearance. 11 | 12 | ## Goal 13 | 14 | This library aims to be a comprehensive 7400 series library for Logisim for designing logical circuits and for educational purposes. 15 | 16 | The library should be compatible both with original [Logisim](http://www.cburch.com/logisim/) and [logisim-evolution](https://github.com/reds-heig/logisim-evolution). 17 | 18 | ## Lists by type 19 | 20 | - [Gates](doc/gates.md) 21 | - [Inverters](doc/inverters.md) 22 | - [Flip-Flops and Latches](doc/flip_flops.md) 23 | - [Encoders and Decoders](doc/encoders_decoders.md) 24 | - [Arithmetic and Counters](doc/arithmetic.md) 25 | 26 | ## Supported Chips 27 | 28 | You're welcome to request missing chips by opening an issue. 29 | 30 | | Chip | Description | Pins | IC | DIP | Status Docs | 31 | | ----------------------- | --------------------------------------------- |:----:| --- | --- | ------------------ | 32 | | [7400](doc/7400.md) | quad 2-input NAND gate | 14 | OK | OK | OK | 33 | | [7402](doc/7402.md) | quad 2-input NOR gate | 14 | OK | OK | OK | 34 | | [7403](doc/7403.md) | quad 2-input NAND gate, open collector output | 14 | OK | OK | OK | 35 | | [7404](doc/7404.md) | hex inverter | 14 | OK | OK | OK | 36 | | [7405](doc/7405.md) | hex inverter, open collector output | 14 | OK | OK | OK | 37 | | [7408](doc/7408.md) | quad 2-input AND gate | 14 | OK | OK | OK | 38 | | [7410](doc/7410.md) | tripe 3-input NAND gate | 14 | OK | OK | OK | 39 | | [7411](doc/7411.md) | tripe 3-input AND gate | 14 | OK | OK | OK | 40 | | [7414](doc/7414.md) | hex Schmitt trigger inverter | 14 | OK | OK | OK | 41 | | [7420](doc/7420.md) | dual 4-input NAND gate | 14 | OK | OK | OK | 42 | | [7421](doc/7421.md) | dual 4-input AND gate | 14 | OK | OK | OK | 43 | | [7427](doc/7427.md) | tripe 3-input NOR gate | 14 | OK | OK | OK | 44 | | [7430](doc/7430.md) | 8-input NAND gate | 14 | OK | OK | OK | 45 | | [7432](doc/7432.md) | quad 2-input OR gate | 14 | OK | OK | OK | 46 | | [7442](doc/7442.md) | 4-bit BCD to 10-line decoder | 16 | OK | OK | OK | 47 | | [7451](doc/7451.md) | AND-OR-invert gates | 14 | OK | OK | OK | 48 | | [7473](doc/7473.md) | dual J-K flip-flop | 14 | OK | OK | OK | 49 | | [7474](doc/7474.md) | dual D-type flip-flop | 14 | OK | OK | OK | 50 | | [7475](doc/7475.md) | quad D-type latch | 16 | OK | -- | old diagram | 51 | | [7476](doc/7476.md) | dual J-K flip-flop | 16 | OK | OK | OK | 52 | | [7485](doc/7485.md) | 4-bit magnitude comparator | 16 | OK | OK | layout missing | 53 | | [7486](doc/7486.md) | quad 2-input XOR gate | 14 | OK | OK | OK | 54 | | [7493](doc/7493.md) | 4-bit binary ripple counter | 14 | OK | -- | layout missing | 55 | | [74107](doc/74107.md) | dual J-K flip-flop | 14 | OK | -- | OK | 56 | | [74109](doc/74109.md) | dual J-not-K flip-flop | 14 | OK | OK | OK | 57 | | [74112](doc/74112.md) | dual J-K flip-flop | 16 | OK | -- | OK | 58 | | [74132](doc/74132.md) | quad 2-input NAND Schmitt trigger | 14 | OK | -- | OK | 59 | | [74137](doc/74137.md) | 3-bit to 8-line decoder, latched input | 16 | -- | -- | layout missing | 60 | | [74138](doc/74138.md) | 3-bit to 8-line decoder | 16 | OK | OK | OK | 61 | | [74139](doc/74139.md) | dual 2-bit to 4-line decoder | 16 | OK | OK | OK | 62 | | [74147](doc/74147.md) | 10-line to 4-bit BCD priority encoder | 16 | OK | OK | OK | 63 | | [74151](doc/74151.md) | 8-line multiplexer | 16 | OK | OK | OK | 64 | | [74153](doc/74153.md) | dual 4-line multiplexer | 16 | OK | OK | old diagram | 65 | | [74157](doc/74157.md) | quad 2-line multiplexer | 16 | OK | OK | old diagram | 66 | | [74161](doc/74161.md) | 4-bit synchronous binary counter | 16 | OK | OK | pin layout missing | 67 | | [74163](doc/74163.md) | 4-bit synchronous binary counter | 16 | OK | OK | pin layout missing | 68 | | [74165](doc/74165.md) | 8-bit parallel in shift register | 16 | -- | -- | missing | 69 | | [74173](doc/74173.md) | quad D-type flip-flop | 16 | OK | -- | OK | 70 | | [74174](doc/74174.md) | hex D-type flip-flop | 16 | -- | -- | missing | 71 | | [74175](doc/74175.md) | quad D-type flip-flop | 16 | OK | -- | missing | 72 | | [74181](doc/74181.md) | 4-bit arithmetic logic unit | | -- | OK | missing | 73 | | [74237](doc/74237.md) | 3-bit to 8-line decoder, latched input | 16 | -- | -- | missing | 74 | | [74238](doc/74238.md) | 3-bit to 8-line decoder | 16 | OK | OK | old diagram | 75 | | [74244](doc/74244.md) | octal buffer | 20 | OK | OK | old diagram | 76 | | [74247](doc/74247.md) | BCD to 7-segment decoder | 16 | -- | OK | pin layout missing | 77 | | [74259](doc/74259.md) | octal adressable D-type latch | | -- | -- | missing | 78 | | [74273](doc/74273.md) | octal D-type flip-flop | 20 | OK | OK | old diagram | 79 | | [74283](doc/74283.md) | 4-bit binary full adder | 16 | OK | OK | pin layout missing | 80 | | [74373](doc/74373.md) | octal transparent D-type latch | 20 | -- | OK | pin layout missing | 81 | | [74374](doc/74374.md) | octal D-type flip-flop | 20 | OK | OK | pin layout missing | 82 | | [74377](doc/74377.md) | 8-bit register with clock enable | 20 | OK | OK | missing | 83 | | [74390](doc/74390.md) | | | -- | -- | missing | 84 | | [74393](doc/74393.md) | | | -- | -- | missing | 85 | | [74534](doc/74534.md) | | | -- | -- | missing | 86 | | [74573](doc/74573.md) | 8-bit D-type latch | 20 | -- | OK | pin layout missing | 87 | | [74574](doc/74574.md) | 8-bit D-type flip-flop | 20 | -- | OK | pin layout missing | 88 | | [74595](doc/74595.md) | 8-bit shift register | 16 | -- | OK | pin layout missing | 89 | | [74670](doc/74670.md) | 4 by 4 register file | | -- | OK | missing | 90 | | [404002](doc/744002.md) | dual 4-input NOR gate | 14 | -- | -- | OK | 91 | | [744049](doc/744049.md) | hex inverter | 16 | -- | OK | pin layout missing | 92 | | [744075](doc/744075.md) | triple 3-input OR gate | 14 | -- | OK | OK | 93 | | [744511](doc/744511.md) | BCD to 7-segment decoder | 16 | -- | OK | pin layout missing | 94 | | [747266](doc/747266.md) | dual 2-input XNOR gate | 14 | -- | -- | OK | 95 | 96 | ## Design Guidelines 97 | 98 | To meet these goals, the following design [guidelines](guidelines.md) are met: 99 | 100 | * Circuits are build from a minimal set of built-in components. 101 | * The pin layout matches the DIP pinout of the corresponding ICs. 102 | * Automated tests are provided. 103 | * Labels must conform to [VHDL](https://en.wikipedia.org/wiki/VHDL), i.e. start with a letter and contain only letters, digits, or underscores. 104 | 105 | ## Credits 106 | 107 | * [logisim_74v1](http://74x.weebly.com/blog/library-of-7400-logic-for-logisim), Public Domain 108 | * [7400 series Logisim library from Ben Oztalay](http://www.cburch.com/logisim/download/7400-lib.zip): Provided on Logisim web site, Public Domain 109 | -------------------------------------------------------------------------------- /in-progress/74x299.circ: -------------------------------------------------------------------------------- 1 | 2 | 3 | This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/). 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | 455 | 456 | 457 | 458 | 459 | 460 | 461 | 462 | 463 | 464 | 465 | 466 | 467 | 468 | 469 | 470 | 471 | 472 | 473 | 474 | 475 | 476 | 477 | 478 | 479 | 480 | 481 | 482 | 483 | 484 | 485 | 486 | 487 | 488 | 489 | 490 | 491 | 492 | 493 | 494 | 495 | 496 | 497 | 498 | 499 | 500 | 501 | 502 | 503 | 504 | 505 | 506 | 507 | 508 | 509 | 510 | 511 | 512 | 513 | 514 | 515 | 516 | 517 | 518 | 519 | 520 | 521 | 522 | 523 | 524 | 525 | 526 | 527 | 528 | 529 | 530 | 531 | 532 | 533 | 534 | 535 | 536 | 537 | 538 | 539 | 540 | 541 | 542 | 543 | 544 | 545 | 546 | 547 | 548 | 549 | 550 | 551 | 552 | 553 | 554 | 555 | 556 | 557 | 558 | 559 | 560 | 561 | 562 | 563 | 564 | 565 | 566 | 567 | 568 | 569 | 570 | 571 | 572 | 573 | 574 | 575 | 576 | 577 | 578 | 579 | 580 | 581 | 582 | 583 | 584 | 585 | 586 | 587 | 588 | 589 | 590 | 591 | 592 | 593 | 594 | 595 | 596 | 597 | 598 | 599 | 600 | 601 | 602 | 603 | 604 | 605 | 606 | 607 | 608 | 609 | 610 | 611 | 612 | 613 | 614 | 615 | 616 | 617 | 618 | 619 | 620 | 621 | 622 | 623 | 624 | 625 | 626 | 627 | 628 | 629 | 630 | 631 | 632 | 633 | 634 | 635 | 636 | 637 | 638 | 639 | 640 | 641 | 642 | 643 | 644 | 645 | 646 | 647 | 648 | 649 | 650 | 651 | 652 | 653 | 654 | 655 | 656 | 657 | 658 | 659 | 660 | 661 | 662 | 663 | 664 | 665 | 666 | 667 | 668 | 669 | 670 | 671 | 672 | 673 | 674 | 675 | 676 | 677 | 678 | 679 | 680 | 681 | 682 | 683 | 684 | 685 | 686 | 687 | 688 | 689 | 690 | 691 | 692 | 693 | 694 | 695 | 696 | 697 | 698 | 699 | 700 | 701 | 702 | 703 | 704 | 705 | 706 | 707 | 708 | 709 | 710 | 711 | 712 | 713 | 714 | 715 | 716 | 717 | 718 | 719 | 720 | 721 | 722 | 723 | 724 | 725 | 726 | 727 | 728 | 729 | 730 | 731 | 732 | 733 | 734 | 735 | 736 | 737 | 738 | 739 | 740 | 741 | 742 | 743 | 744 | 745 | 746 | 747 | 748 | 749 | 750 | 751 | 752 | 753 | 754 | 755 | 756 | 757 | 758 | 759 | 760 | 761 | 762 | 763 | 764 | 765 | 766 | 767 | 768 | 769 | 770 | 771 | 772 | 773 | 774 | 775 | 776 | 777 | 778 | 779 | 780 | 781 | 782 | 783 | 784 | 785 | 786 | 787 | 788 | 789 | 790 | 791 | 792 | 793 | 794 | 795 | 796 | 797 | 798 | 799 | 800 | 801 | 802 | 803 | 804 | 805 | 806 | 807 | 808 | 809 | 810 | 811 | 812 | 813 | 814 | 815 | 816 | 817 | 818 | 819 | 820 | 821 | 822 | 823 | 824 | 825 | 826 | 827 | 828 | 829 | 830 | 831 | 832 | 833 | 834 | 835 | 836 | 837 | 838 | 839 | 840 | 841 | 842 | 843 | 844 | 845 | 846 | 847 | 848 | 849 | 850 | 851 | 852 | 853 | 854 | 855 | 856 | 857 | 858 | 859 | 860 | 861 | 862 | 863 | 864 | 865 | 866 | 867 | 868 | 869 | 870 | 871 | 872 | 873 | 874 | 875 | 876 | 877 | 878 | 879 | 880 | 881 | 882 | 883 | 884 | 885 | 886 | 887 | 888 | 889 | 890 | 891 | 892 | 893 | 894 | 895 | 896 | 897 | 898 | 899 | 900 | 901 | 902 | 903 | 904 | 905 | 906 | 907 | 908 | 909 | 910 | 911 | 912 | 913 | 914 | 915 | 916 | 917 | 918 | 919 | 920 | 921 | 922 | 923 | 924 | 925 | 926 | 927 | 928 | 929 | 930 | 931 | 932 | 933 | 934 | 935 | 936 | 937 | 938 | 939 | 940 | 941 | 942 | 943 | 944 | 945 | 946 | 947 | 948 | 949 | 950 | 951 | 952 | 953 | 954 | 955 | 956 | 957 | 958 | 959 | 960 | 961 | 962 | 963 | 964 | 965 | 966 | 967 | 968 | 969 | 970 | 971 | 972 | 973 | 974 | 975 | 976 | 977 | 978 | 979 | 980 | 981 | 982 | 983 | 984 | 985 | 986 | 987 | 988 | 989 | 990 | 991 | 992 | 993 | 994 | 995 | 996 | 997 | 998 | 999 | 1000 | 1001 | 1002 | 1003 | 1004 | 1005 | 1006 | 1007 | 1008 | 1009 | 1010 | 1011 | 1012 | 1013 | 1014 | 1015 | 1016 | 1017 | 1018 | 1019 | 1020 | 1021 | 1022 | 1023 | 1024 | 1025 | 1026 | 1027 | 1028 | 1029 | 1030 | 1031 | 1032 | 1033 | 1034 | 1035 | 1036 | 1037 | 1038 | 1039 | 1040 | 1041 | 1042 | 1043 | 1044 | 1045 | 1046 | 1047 | 1048 | 1049 | 1050 | 1051 | 1052 | 1053 | 1054 | 1055 | 1056 | 1057 | 1058 | 1059 | 1060 | 1061 | 1062 | 1063 | 1064 | 1065 | 1066 | 1067 | 1068 | 1069 | 1070 | 1071 | 1072 | 1073 | 1074 | 1075 | 1076 | 1077 | 1078 | 1079 | 1080 | 1081 | 1082 | 1083 | 1084 | 1085 | 1086 | 1087 | 1088 | 1089 | 1090 | 1091 | 1092 | 1093 | 1094 | 1095 | 1096 | 1097 | 1098 | 1099 | 1100 | 1101 | 1102 | 1103 | 1104 | 1105 | 1106 | 1107 | 1108 | 1109 | 1110 | 1111 | 1112 | 1113 | 1114 | 1115 | 1116 | 1117 | 1118 | 1119 | 1120 | 1121 | 1122 | 1123 | 1124 | 1125 | 1126 | 1127 | 1128 | 1129 | 1130 | 1131 | 1132 | 1133 | 1134 | 1135 | 1136 | 1137 | 1138 | 1139 | 1140 | 1141 | 1142 | 1143 | 1144 | 1145 | 1146 | 1147 | 1148 | 1149 | 1150 | 1151 | 1152 | 1153 | 1154 | 1155 | 1156 | 1157 | 1158 | 1159 | 1160 | 1161 | 1162 | 1163 | 1164 | 1165 | 1166 | 1167 | 1168 | 1169 | 1170 | 1171 | 1172 | 1173 | 1174 | 1175 | 1176 | 1177 | 1178 | 1179 | 1180 | 1181 | 1182 | 1183 | 1184 | 1185 | 1186 | 1187 | 1188 | 1189 | 1190 | 1191 | 1192 | 1193 | 1194 | 1195 | 1196 | 1197 | 1198 | 1199 | 1200 | 1201 | 1202 | 1203 | 1204 | 1205 | 1206 | 1207 | 1208 | 1209 | 1210 | 1211 | 1212 | 1213 | 1214 | 1215 | 1216 | 1217 | 1218 | 1219 | 1220 | 1221 | 1222 | 1223 | 1224 | 1225 | 1226 | 1227 | 1228 | 1229 | 1230 | 1231 | 1232 | 1233 | 1234 | 1235 | 1236 | 1237 | 1238 | 1239 | 1240 | 1241 | 1242 | 1243 | 1244 | 1245 | 1246 | 1247 | 1248 | 1249 | 1250 | 1251 | 1252 | 1253 | 1254 | 1255 | 1256 | 1257 | 1258 | 1259 | 1260 | 1261 | 1262 | 1263 | 1264 | 1265 | 1266 | 1267 | 1268 | 1269 | 1270 | 1271 | 1272 | 1273 | 1274 | 1275 | 1276 | 1277 | 1278 | 1279 | 1280 | 1281 | 1282 | 1283 | 1284 | 1285 | 1286 | 1287 | 1288 | 1289 | 1290 | 1291 | 1292 | 1293 | 1294 | 1295 | 1296 | 1297 | 1298 | 1299 | 1300 | 1301 | 1302 | 1303 | 1304 | 1305 | 1306 | 1307 | 1308 | 1309 | 1310 | 1311 | 1312 | 1313 | 1314 | 1315 | 1316 | 1317 | 1318 | 1319 | 1320 | 1321 | 1322 | 1323 | 1324 | 1325 | 1326 | 1327 | 1328 | 1329 | 1330 | 1331 | 1332 | 1333 | 1334 | 1335 | 1336 | 1337 | 1338 | 1339 | 1340 | 1341 | 1342 | 1343 | 1344 | 1345 | 1346 | 1347 | 1348 | 1349 | 1350 | 1351 | 1352 | 1353 | 1354 | 1355 | 1356 | 1357 | 1358 | 1359 | 1360 | 1361 | 1362 | 1363 | 1364 | 1365 | 1366 | 1367 | 1368 | 1369 | 1370 | 1371 | 1372 | 1373 | 1374 | 1375 | 1376 | 1377 | 1378 | 1379 | 1380 | 1381 | 1382 | 1383 | 1384 | 1385 | 1386 | 1387 | 1388 | 1389 | 1390 | 1391 | 1392 | 1393 | 1394 | 1395 | 1396 | 1397 | 1398 | 1399 | 1400 | 1401 | 1402 | 1403 | 1404 | 1405 | 1406 | 1407 | 1408 | 1409 | 1410 | 1411 | 1412 | 1413 | 1414 | 1415 | 1416 | 1417 | 1418 | 1419 | 1420 | 1421 | 1422 | 1423 | 1424 | 1425 | 1426 | 1427 | 1428 | 1429 | 1430 | 1431 | 1432 | 1433 | 1434 | 1435 | 1436 | 1437 | 1438 | 1439 | 1440 | 1441 | 1442 | 1443 | 1444 | 1445 | 1446 | 1447 | 1448 | 1449 | 1450 | 1451 | 1452 | 1453 | 1454 | 1455 | 1456 | 1457 | 1458 | 1459 | 1460 | 1461 | 1462 | 1463 | 1464 | 1465 | 1466 | 1467 | 1468 | 1469 | 1470 | 1471 | 1472 | 1473 | 1474 | 1475 | 1476 | 1477 | 1478 | 1479 | 1480 | 1481 | 1482 | 1483 | 1484 | 1485 | 1486 | 1487 | 1488 | 1489 | 1490 | 1491 | 1492 | 1493 | 1494 | 1495 | 1496 | --------------------------------------------------------------------------------