├── VERSION ├── src ├── Processors │ ├── 6502 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── certification.manifest │ │ ├── data │ │ │ ├── languages │ │ │ │ └── 6502.pspec │ │ │ └── manuals │ │ │ │ └── 6502.idx │ │ └── build.gradle │ ├── 8048 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── certification.manifest │ │ ├── data │ │ │ ├── languages │ │ │ │ ├── 8048.ldefs │ │ │ │ └── 8048.cspec │ │ │ └── manuals │ │ │ │ └── 8048.idx │ │ └── build.gradle │ ├── 8051 │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ └── languages │ │ │ ├── 8051.slaspec │ │ │ ├── 80390.slaspec │ │ │ ├── 80251.slaspec │ │ │ ├── mx51.slaspec │ │ │ ├── 8051.opinion │ │ │ └── old │ │ │ └── 8051v1.trans │ ├── 8085 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── certification.manifest │ │ ├── data │ │ │ └── languages │ │ │ │ ├── 8085.ldefs │ │ │ │ └── 8085.cspec │ │ └── build.gradle │ ├── 68000 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── languages │ │ │ │ ├── 68020.slaspec │ │ │ │ ├── 68030.slaspec │ │ │ │ ├── 68040.slaspec │ │ │ │ ├── coldfire.slaspec │ │ │ │ ├── 68000.pspec │ │ │ │ └── 68000.dwarf │ │ │ └── patterns │ │ │ │ └── patternconstraints.xml │ │ └── certification.manifest │ ├── AARCH64 │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── languages │ │ │ ├── AARCH64.slaspec │ │ │ ├── AARCH64BE.slaspec │ │ │ ├── AARCH64_AppleSilicon.slaspec │ │ │ ├── AARCH64.dwarf │ │ │ └── AARCH64_golang.register.info │ │ │ ├── patterns │ │ │ ├── patternconstraints.xml │ │ │ └── prepatternconstraints.xml │ │ │ └── aarch64-pltThunks.xml │ ├── ARM │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── languages │ │ │ ├── ARM4_be.slaspec │ │ │ ├── ARM4_le.slaspec │ │ │ ├── ARM4t_be.slaspec │ │ │ ├── ARM4t_le.slaspec │ │ │ ├── ARM5_be.slaspec │ │ │ ├── ARM5_le.slaspec │ │ │ ├── ARM5t_le.slaspec │ │ │ ├── ARM5t_be.slaspec │ │ │ ├── old │ │ │ │ ├── ARMv5.trans │ │ │ │ └── THUMBv2.trans │ │ │ ├── ARM6_be.slaspec │ │ │ ├── ARM6_le.slaspec │ │ │ ├── ARM7_be.slaspec │ │ │ ├── ARM7_le.slaspec │ │ │ ├── ARM8_be.slaspec │ │ │ ├── ARM8_le.slaspec │ │ │ ├── ARM8m_be.slaspec │ │ │ ├── ARM8m_le.slaspec │ │ │ └── ARM.dwarf │ │ │ └── patterns │ │ │ ├── prepatternconstraints.xml │ │ │ └── patternconstraints.xml │ ├── Atmel │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── languages │ │ │ ├── avr8.slaspec │ │ │ ├── avr8eind.slaspec │ │ │ ├── avr8e.slaspec │ │ │ ├── avr32a.pspec │ │ │ ├── avr8xmega.slaspec │ │ │ ├── avr32.opinion │ │ │ ├── avr32a.ldefs │ │ │ └── avr8.opinion │ │ │ └── patterns │ │ │ └── patternconstraints.xml │ ├── BPF │ │ ├── README.md │ │ ├── Module.manifest │ │ ├── data │ │ │ └── languages │ │ │ │ ├── BPF_le.slaspec │ │ │ │ ├── BPF.pspec │ │ │ │ └── BPF.ldefs │ │ ├── certification.manifest │ │ └── build.gradle │ ├── CP1600 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── CP1600.opinion │ │ │ │ ├── CP1600.pspec │ │ │ │ └── CP1600.ldefs │ │ ├── certification.manifest │ │ └── build.gradle │ ├── CR16 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── CR16B.slaspec │ │ │ │ ├── CR16C.slaspec │ │ │ │ ├── CR16.pspec │ │ │ │ └── CR16.opinion │ │ ├── certification.manifest │ │ └── build.gradle │ ├── DATA │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── data-be-64.slaspec │ │ │ │ ├── data-le-64.slaspec │ │ │ │ ├── data.pspec │ │ │ │ ├── data-ptr16.cspec │ │ │ │ ├── data-ptr32.cspec │ │ │ │ ├── data-ptr64.cspec │ │ │ │ └── data.sinc │ │ └── certification.manifest │ ├── Dalvik │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ └── languages │ │ │ ├── Dalvik_OpCode_73_unused.sinc │ │ │ ├── Dalvik_Base.slaspec │ │ │ ├── Dalvik_OpCode_73_return_void_barrier.sinc │ │ │ ├── Dalvik_OpCode_73_return_void_no_barrier.sinc │ │ │ ├── Dalvik_OpCode_79_unused.sinc │ │ │ ├── Dalvik_OpCode_7A_unused.sinc │ │ │ ├── Dalvik_OpCode_F3_unused.sinc │ │ │ ├── Dalvik_OpCode_F4_unused.sinc │ │ │ ├── Dalvik_OpCode_F7_unused.sinc │ │ │ ├── Dalvik_OpCode_F8_unused.sinc │ │ │ ├── Dalvik_OpCode_F9_unused.sinc │ │ │ ├── Dalvik_OpCode_FA_unused.sinc │ │ │ ├── Dalvik_OpCode_FB_unused.sinc │ │ │ ├── Dalvik_OpCode_FC_unused.sinc │ │ │ ├── Dalvik_OpCode_FD_unused.sinc │ │ │ ├── Dalvik_OpCode_FE_unused.sinc │ │ │ ├── Dalvik_OpCode_FF_unused.sinc │ │ │ ├── Dalvik_OpCode_F5_unused.sinc │ │ │ └── Dalvik_OpCode_F6_unused.sinc │ ├── HCS08 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── HC08.slaspec │ │ │ │ ├── HC05.slaspec │ │ │ │ ├── HCS08.slaspec │ │ │ │ ├── HCS08.opinion │ │ │ │ └── HC08.pspec │ │ └── build.gradle │ ├── HCS12 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── HC12.slaspec │ │ │ │ ├── HCS12.slaspec │ │ │ │ ├── HCS12X.slaspec │ │ │ │ └── HCS12.opinion │ │ └── certification.manifest │ ├── JVM │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── ExtensionPoint.manifest │ │ │ └── languages │ │ │ │ ├── JVM.opinion │ │ │ │ └── JVM.ldefs │ │ ├── certification.manifest │ │ └── resources │ │ │ ├── ArrayLengthTest.java │ │ │ ├── WideInc.java │ │ │ ├── InvokeInterfaceTest.java │ │ │ ├── InvokeDynamicTest.java │ │ │ ├── Throw.java │ │ │ └── MonitorTest.java │ ├── M8C │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── m8c.opinion │ │ │ │ └── m8c.ldefs │ │ ├── certification.manifest │ │ └── build.gradle │ ├── MC6800 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── 6809.pspec │ │ │ │ ├── 6809.slaspec │ │ │ │ ├── H6309.slaspec │ │ │ │ ├── 6805.ldefs │ │ │ │ └── 6805.cspec │ │ ├── certification.manifest │ │ └── build.gradle │ ├── MCS96 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── MCS96.slaspec │ │ │ │ ├── MCS96.pspec │ │ │ │ ├── MCS96.ldefs │ │ │ │ └── MCS96.cspec │ │ ├── certification.manifest │ │ └── build.gradle │ ├── MIPS │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── patterns │ │ │ └── patternconstraints.xml │ │ │ └── languages │ │ │ ├── mips32R6be.slaspec │ │ │ ├── mips32R6le.slaspec │ │ │ ├── mips32be.slaspec │ │ │ ├── mips32le.slaspec │ │ │ ├── mips64be.slaspec │ │ │ └── mips64le.slaspec │ ├── PA-RISC │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── patterns │ │ │ │ ├── patternconstraints.xml │ │ │ │ └── pa-risc_patterns.xml │ │ │ └── languages │ │ │ │ ├── pa-risc32be.slaspec │ │ │ │ ├── pa-risc32.pspec │ │ │ │ ├── pa-risc.opinion │ │ │ │ └── pa-risc.ldefs │ │ └── certification.manifest │ ├── PIC │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── languages │ │ │ ├── pic16.slaspec │ │ │ ├── pic16f.slaspec │ │ │ ├── dsPIC33C.slaspec │ │ │ ├── PIC24E.slaspec │ │ │ ├── PIC24F.slaspec │ │ │ ├── PIC24H.slaspec │ │ │ ├── dsPIC30F.slaspec │ │ │ ├── dsPIC33E.slaspec │ │ │ ├── dsPIC33F.slaspec │ │ │ ├── pic17c7xx.ldefs │ │ │ ├── pic18.ldefs │ │ │ ├── pic16c5x.ldefs │ │ │ ├── pic12c5xx.ldefs │ │ │ ├── pic12c5xx.slaspec │ │ │ ├── pic16c5x.pspec │ │ │ ├── pic16c5x.slaspec │ │ │ ├── PIC24.opinion │ │ │ └── PIC33.dwarf │ │ │ └── manuals │ │ │ ├── PIC-12.idx │ │ │ ├── PIC-16.idx │ │ │ └── PIC-16F.idx │ ├── PowerPC │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── languages │ │ │ ├── ppc_32_le.slaspec │ │ │ ├── ppc_32_4xx_be.slaspec │ │ │ ├── ppc_32_4xx_le.slaspec │ │ │ ├── ppc_64_be.slaspec │ │ │ ├── ppc_64_le.slaspec │ │ │ ├── ppc_32_be.slaspec │ │ │ ├── ppc_32_quicciii_be.slaspec │ │ │ ├── ppc_32_quicciii_le.slaspec │ │ │ ├── old │ │ │ │ └── oldPPC.trans │ │ │ ├── g2.sinc │ │ │ ├── ppc_32_e500mc_le.slaspec │ │ │ ├── evx.sinc │ │ │ └── ppc_32_e500mc_be.slaspec │ │ │ └── patterns │ │ │ └── patternconstraints.xml │ ├── RISCV │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── patterns │ │ │ └── patternconstraints.xml │ │ │ └── languages │ │ │ ├── riscv.zi.sinc │ │ │ ├── riscv.ilp32d.slaspec │ │ │ ├── riscv.lp64d.slaspec │ │ │ ├── RV32I.pspec │ │ │ ├── RV64I.pspec │ │ │ ├── RV32IC.pspec │ │ │ ├── RV64IC.pspec │ │ │ ├── RV32IMC.pspec │ │ │ ├── RV32G.pspec │ │ │ ├── RV64G.pspec │ │ │ ├── RV32GC.pspec │ │ │ ├── RV64GC.pspec │ │ │ └── riscv.rv64q.sinc │ ├── STM8 │ │ ├── Module.manifest │ │ ├── extension.properties │ │ └── data │ │ │ └── languages │ │ │ ├── STM8.pspec │ │ │ ├── STM8_large.slaspec │ │ │ ├── STM8_medium.slaspec │ │ │ └── STM8.ldefs │ ├── Sparc │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── languages │ │ │ │ ├── SparcV9_32.slaspec │ │ │ │ ├── SparcV9_64.slaspec │ │ │ │ ├── SparcV9.pspec │ │ │ │ └── Sparc.opinion │ │ │ └── patterns │ │ │ │ └── patternconstraints.xml │ │ └── certification.manifest │ ├── SuperH4 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── patterns │ │ │ │ ├── patternconstraints.xml │ │ │ │ └── SuperH4_patterns.xml │ │ │ └── languages │ │ │ │ ├── SuperH4_be.slaspec │ │ │ │ ├── old │ │ │ │ ├── SuperH4-BE-16.trans │ │ │ │ └── SuperH4-LE-16.trans │ │ │ │ ├── SuperH4_le.slaspec │ │ │ │ ├── SuperH4.pspec │ │ │ │ └── SuperH4.opinion │ │ └── certification.manifest │ ├── Toy │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ └── languages │ │ │ ├── toy_builder_be.slaspec │ │ │ ├── toy_builder_le.slaspec │ │ │ ├── toy_builder_be_align2.slaspec │ │ │ ├── toy_builder_le_align2.slaspec │ │ │ ├── toy_harvard.pspec │ │ │ ├── toy_be.slaspec │ │ │ ├── toy64_be.slaspec │ │ │ ├── toy64_le.slaspec │ │ │ ├── toy_le.slaspec │ │ │ ├── toy_wsz_be.slaspec │ │ │ ├── toy_wsz_le.slaspec │ │ │ ├── toy64_be_harvard.slaspec │ │ │ ├── toy_be_posStack.slaspec │ │ │ ├── toy64_be_harvard_rev.slaspec │ │ │ ├── old │ │ │ └── v01stuff │ │ │ │ └── toy.sinc │ │ │ └── toy.pspec │ ├── V850 │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── manuals │ │ │ └── v850.idx │ │ │ ├── patterns │ │ │ └── patternconstraints.xml │ │ │ └── languages │ │ │ ├── V850.pspec │ │ │ ├── V850.opinion │ │ │ └── V850.ldefs │ ├── Xtensa │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── patterns │ │ │ │ └── patternconstraints.xml │ │ │ └── languages │ │ │ │ ├── xtensa.opinion │ │ │ │ ├── xtensa.dwarf │ │ │ │ ├── flix.sinc │ │ │ │ ├── xtensa_be.slaspec │ │ │ │ ├── xtensa_le.slaspec │ │ │ │ ├── xtensa.pspec │ │ │ │ ├── xtensa_depbits.sinc │ │ │ │ └── cust.sinc │ │ └── certification.manifest │ ├── Z80 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ └── z180.slaspec │ │ ├── certification.manifest │ │ └── build.gradle │ ├── eBPF │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── eBPF_be.slaspec │ │ │ │ ├── eBPF_le.slaspec │ │ │ │ ├── eBPF.opinion │ │ │ │ └── eBPF.dwarf │ │ └── certification.manifest │ ├── tricore │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ ├── patterns │ │ │ │ └── patternconstraints.xml │ │ │ └── languages │ │ │ │ ├── tricore.opinion │ │ │ │ ├── tricore.slaspec │ │ │ │ └── tricore.pspec │ │ └── certification.manifest │ ├── wasm │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── bin │ │ │ ├── README.txt │ │ │ └── images │ │ │ │ └── README.txt │ │ ├── ghidra_scripts │ │ │ └── README.txt │ │ ├── extension.properties │ │ ├── lib │ │ │ └── README.txt │ │ ├── data │ │ │ ├── languages │ │ │ │ ├── Webassembly.opinion │ │ │ │ ├── Webassembly.cspec │ │ │ │ └── Webassembly.ldefs │ │ │ └── README.txt │ │ └── os │ │ │ ├── linux64 │ │ │ └── README.txt │ │ │ ├── osx64 │ │ │ └── README.txt │ │ │ └── win64 │ │ │ └── README.txt │ ├── x86 │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── languages │ │ │ ├── x86-16.gdis │ │ │ ├── macros.sinc │ │ │ ├── x86-64.slaspec │ │ │ ├── old │ │ │ │ ├── x86RealV1.trans │ │ │ │ ├── x86RealV2.trans │ │ │ │ ├── x86RealV3.trans │ │ │ │ ├── x86_ProtV2.trans │ │ │ │ ├── x86_ProtV3.trans │ │ │ │ ├── x86smmV1.trans │ │ │ │ ├── x86smmV2.trans │ │ │ │ ├── x86smmV3.trans │ │ │ │ ├── x86V1.trans │ │ │ │ ├── x86_64bit_v1.trans │ │ │ │ ├── x86_64bit_compat32_v2.trans │ │ │ │ ├── x86_64bit_compat32_v3.trans │ │ │ │ ├── x86_64bit_v2.trans │ │ │ │ ├── x86_64bit_v3.trans │ │ │ │ ├── x86V2.trans │ │ │ │ └── x86V3.trans │ │ │ ├── x86-32-golang.register.info │ │ │ ├── clwb.sinc │ │ │ ├── x86.slaspec │ │ │ ├── lzcnt.sinc │ │ │ └── x86-64-golang.register.info │ │ │ ├── extensions │ │ │ └── rust │ │ │ │ ├── unix │ │ │ │ ├── try_fixup.xml │ │ │ │ └── probe_fixup.xml │ │ │ │ ├── unix32 │ │ │ │ ├── try_fixup.xml │ │ │ │ └── probe_fixup.xml │ │ │ │ ├── unix64 │ │ │ │ ├── try_fixup.xml │ │ │ │ └── probe_fixup.xml │ │ │ │ ├── windows │ │ │ │ ├── try_fixup.xml │ │ │ │ └── probe_fixup.xml │ │ │ │ ├── windows32 │ │ │ │ ├── try_fixup.xml │ │ │ │ └── probe_fixup.xml │ │ │ │ └── windows64 │ │ │ │ ├── try_fixup.xml │ │ │ │ └── probe_fixup.xml │ │ │ └── patterns │ │ │ ├── x86gcc_prepatterns.xml │ │ │ ├── prepatternconstraints.xml │ │ │ └── x86win_prepatterns.xml │ ├── Loongarch │ │ ├── Module.manifest │ │ ├── README.md │ │ └── data │ │ │ ├── patterns │ │ │ └── patternconstraints.xml │ │ │ └── languages │ │ │ ├── loongarch32.pspec │ │ │ ├── loongarch64.pspec │ │ │ ├── loongarch32_f64.slaspec │ │ │ ├── loongarch32_f32.slaspec │ │ │ ├── loongarch64_f64.slaspec │ │ │ └── loongarch64_f32.slaspec │ ├── M16C │ │ ├── README.md │ │ ├── Module.manifest │ │ ├── certification.manifest │ │ ├── data │ │ │ └── languages │ │ │ │ ├── M16C_60.ldefs │ │ │ │ └── M16C_80.ldefs │ │ └── build.gradle │ ├── SuperH │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── sh-2.slaspec │ │ │ │ ├── sh-1.slaspec │ │ │ │ ├── sh-2a.slaspec │ │ │ │ └── superh.pspec │ │ ├── certification.manifest │ │ └── build.gradle │ ├── TI_MSP430 │ │ ├── Module.manifest │ │ ├── README.md │ │ ├── data │ │ │ └── languages │ │ │ │ ├── TI_MSP430.slaspec │ │ │ │ ├── TI_MSP430X.slaspec │ │ │ │ ├── TI_MSP430.dwarf │ │ │ │ ├── TI_MSP430X.dwarf │ │ │ │ └── ti_msp430.opinion │ │ └── certification.manifest │ ├── sBPF │ │ ├── data │ │ │ └── languages │ │ │ │ ├── sBPF.slaspec │ │ │ │ ├── sBPF.sla │ │ │ │ ├── sBPF.pspec │ │ │ │ ├── sBPF.opinion │ │ │ │ ├── sBPF.ldefs │ │ │ │ └── sBPF.dwarf │ │ └── README.md │ └── hexagon │ │ └── data │ │ └── languages │ │ ├── hexagon.opinion │ │ ├── hexagon.pspec │ │ └── hexagon.ldefs └── decompiler │ └── .gitignore ├── .gitignore ├── GHIDRA_COMMIT ├── .github └── dependabot.yml ├── patches ├── 0023-Undef-LoadImage-for-windows.patch ├── 0091-decompiler-xml-packer.patch ├── 0056-nullderef-workaround.patch ├── 0010-null-subflow.patch ├── 0080-getparent-flow.patch ├── 0090-nocasts-warnings.patch ├── 0024-ignore-symbol-beyond-space.patch ├── 0006-readonly-warning.patch └── 0044-bad-unicode-codepoint.patch └── README.md /VERSION: -------------------------------------------------------------------------------- 1 | 0.6.4 2 | -------------------------------------------------------------------------------- /src/Processors/6502/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/68000/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/8048/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/8051/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/8085/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/ARM/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/ARM/README.md: -------------------------------------------------------------------------------- 1 | # ARM 2 | -------------------------------------------------------------------------------- /src/Processors/Atmel/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/BPF/README.md: -------------------------------------------------------------------------------- 1 | # BPF 2 | -------------------------------------------------------------------------------- /src/Processors/CP1600/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/CR16/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/DATA/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/HCS08/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/HCS12/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/JVM/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/JVM/README.md: -------------------------------------------------------------------------------- 1 | # JVM 2 | -------------------------------------------------------------------------------- /src/Processors/M8C/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/M8C/README.md: -------------------------------------------------------------------------------- 1 | # M8C 2 | -------------------------------------------------------------------------------- /src/Processors/MC6800/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/MCS96/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/MIPS/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/PIC/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/PIC/README.md: -------------------------------------------------------------------------------- 1 | # PIC 2 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/RISCV/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/STM8/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Sparc/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Toy/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Toy/README.md: -------------------------------------------------------------------------------- 1 | # Toy 2 | -------------------------------------------------------------------------------- /src/Processors/V850/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Z80/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/Z80/README.md: -------------------------------------------------------------------------------- 1 | # Z80 2 | -------------------------------------------------------------------------------- /src/Processors/eBPF/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/tricore/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/wasm/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/wasm/README.md: -------------------------------------------------------------------------------- 1 | Wasm 2 | -------------------------------------------------------------------------------- /src/Processors/x86/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/x86/README.md: -------------------------------------------------------------------------------- 1 | # x86 2 | -------------------------------------------------------------------------------- /src/Processors/6502/README.md: -------------------------------------------------------------------------------- 1 | # 6502 2 | -------------------------------------------------------------------------------- /src/Processors/68000/README.md: -------------------------------------------------------------------------------- 1 | # 68000 2 | -------------------------------------------------------------------------------- /src/Processors/8048/README.md: -------------------------------------------------------------------------------- 1 | # 8048 2 | -------------------------------------------------------------------------------- /src/Processors/8051/README.md: -------------------------------------------------------------------------------- 1 | # 8051 2 | -------------------------------------------------------------------------------- /src/Processors/8085/README.md: -------------------------------------------------------------------------------- 1 | # 8085 2 | -------------------------------------------------------------------------------- /src/Processors/Atmel/README.md: -------------------------------------------------------------------------------- 1 | # Atmel 2 | -------------------------------------------------------------------------------- /src/Processors/BPF/Module.manifest: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /src/Processors/CR16/README.md: -------------------------------------------------------------------------------- 1 | # CR16 2 | -------------------------------------------------------------------------------- /src/Processors/DATA/README.md: -------------------------------------------------------------------------------- 1 | # DATA 2 | -------------------------------------------------------------------------------- /src/Processors/HCS08/README.md: -------------------------------------------------------------------------------- 1 | # HCS08 2 | -------------------------------------------------------------------------------- /src/Processors/HCS12/README.md: -------------------------------------------------------------------------------- 1 | # HCS12 2 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/M16C/README.md: -------------------------------------------------------------------------------- 1 | # M16C 2 | -------------------------------------------------------------------------------- /src/Processors/MCS96/README.md: -------------------------------------------------------------------------------- 1 | # MCS96 2 | -------------------------------------------------------------------------------- /src/Processors/MIPS/README.md: -------------------------------------------------------------------------------- 1 | # MIPS 2 | -------------------------------------------------------------------------------- /src/Processors/RISCV/README.md: -------------------------------------------------------------------------------- 1 | # RISCV 2 | -------------------------------------------------------------------------------- /src/Processors/Sparc/README.md: -------------------------------------------------------------------------------- 1 | # Sparc 2 | -------------------------------------------------------------------------------- /src/Processors/SuperH/Module.manifest: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/Module.manifest: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/V850/README.md: -------------------------------------------------------------------------------- 1 | # V850 2 | -------------------------------------------------------------------------------- /src/Processors/eBPF/README.md: -------------------------------------------------------------------------------- 1 | # eBPF 2 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/README.md: -------------------------------------------------------------------------------- 1 | # AARCH64 2 | -------------------------------------------------------------------------------- /src/Processors/CP1600/README.md: -------------------------------------------------------------------------------- 1 | # CP1600 2 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/README.md: -------------------------------------------------------------------------------- 1 | # Dalvik 2 | -------------------------------------------------------------------------------- /src/Processors/MC6800/README.md: -------------------------------------------------------------------------------- 1 | # MC6800 2 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/README.md: -------------------------------------------------------------------------------- 1 | # PA-RISC 2 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/README.md: -------------------------------------------------------------------------------- 1 | # PowerPC 2 | -------------------------------------------------------------------------------- /src/Processors/SuperH/README.md: -------------------------------------------------------------------------------- 1 | # SuperH 2 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/README.md: -------------------------------------------------------------------------------- 1 | # SuperH4 2 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/README.md: -------------------------------------------------------------------------------- 1 | # Xtensa 2 | -------------------------------------------------------------------------------- /src/Processors/tricore/README.md: -------------------------------------------------------------------------------- 1 | # tricore 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ghidra_wasm 2 | ghidra_STM8 3 | ghidra 4 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/README.md: -------------------------------------------------------------------------------- 1 | # Loongarch 2 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/README.md: -------------------------------------------------------------------------------- 1 | # TI_MSP430 2 | -------------------------------------------------------------------------------- /GHIDRA_COMMIT: -------------------------------------------------------------------------------- 1 | 12a8db619544bdba3b951ef5b607eedb05a37c9c 2 | -------------------------------------------------------------------------------- /src/Processors/JVM/data/ExtensionPoint.manifest: -------------------------------------------------------------------------------- 1 | VMInstruction 2 | -------------------------------------------------------------------------------- /src/Processors/68000/data/languages/68020.slaspec: -------------------------------------------------------------------------------- 1 | @include "68000.sinc" 2 | -------------------------------------------------------------------------------- /src/Processors/CP1600/data/languages/CP1600.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /src/Processors/M16C/Module.manifest: -------------------------------------------------------------------------------- 1 | MODULE DEPENDENCY: Ghidra/Framework/SoftwareModeling -------------------------------------------------------------------------------- /src/Processors/68000/data/languages/68030.slaspec: -------------------------------------------------------------------------------- 1 | @define MC68030 "" 2 | @include "68000.sinc" 3 | -------------------------------------------------------------------------------- /src/Processors/68000/data/languages/68040.slaspec: -------------------------------------------------------------------------------- 1 | @define MC68040 "" 2 | @include "68000.sinc" 3 | -------------------------------------------------------------------------------- /src/Processors/BPF/data/languages/BPF_le.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @include "BPF.sinc" -------------------------------------------------------------------------------- /src/Processors/Z80/data/languages/z180.slaspec: -------------------------------------------------------------------------------- 1 | @define Z180 "" 2 | 3 | @include "z80.slaspec" 4 | -------------------------------------------------------------------------------- /src/Processors/8051/data/languages/8051.slaspec: -------------------------------------------------------------------------------- 1 | @define MCS51 "" 2 | 3 | @include "8051_main.sinc" 4 | -------------------------------------------------------------------------------- /src/Processors/wasm/bin/README.txt: -------------------------------------------------------------------------------- 1 | Java source directory to hold module-specific Ghidra scripts. 2 | -------------------------------------------------------------------------------- /src/Processors/8051/data/languages/80390.slaspec: -------------------------------------------------------------------------------- 1 | @define MCS80390 "" 2 | 3 | @include "8051_main.sinc" 4 | -------------------------------------------------------------------------------- /src/Processors/SuperH/data/languages/sh-2.slaspec: -------------------------------------------------------------------------------- 1 | @define SH_VERSION "2" 2 | 3 | @include "superh.sinc" 4 | -------------------------------------------------------------------------------- /src/Processors/eBPF/data/languages/eBPF_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | 3 | @include "eBPF.sinc" 4 | -------------------------------------------------------------------------------- /src/Processors/eBPF/data/languages/eBPF_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | 3 | @include "eBPF.sinc" 4 | -------------------------------------------------------------------------------- /src/Processors/sBPF/data/languages/sBPF.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @include "sBPF.sinc" 4 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/x86-16.gdis: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM4_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | 4 | @include "ARM.sinc" 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/CR16/data/languages/CR16B.slaspec: -------------------------------------------------------------------------------- 1 | 2 | define endian=little; 3 | 4 | @include "CR16B.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/CR16/data/languages/CR16C.slaspec: -------------------------------------------------------------------------------- 1 | 2 | define endian=little; 3 | 4 | @include "CR16C.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/SuperH/data/languages/sh-1.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define SH_VERSION "1" 3 | 4 | @include "superh.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/wasm/ghidra_scripts/README.txt: -------------------------------------------------------------------------------- 1 | Java source directory to hold module-specific Ghidra scripts. 2 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM4_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | 4 | @include "ARM.sinc" 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/Sparc/data/languages/SparcV9_32.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define SIZE "4" 3 | 4 | @include "SparcV9.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/MCS96/data/languages/MCS96.slaspec: -------------------------------------------------------------------------------- 1 | @define C196KB "1" 2 | @define C196KC "1" 3 | 4 | @include "MCS96.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/Sparc/data/languages/SparcV9_64.slaspec: -------------------------------------------------------------------------------- 1 | @define SIZE "8" 2 | 3 | @include "SparcV9.sinc" 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/SuperH/data/languages/sh-2a.slaspec: -------------------------------------------------------------------------------- 1 | @define SH_VERSION "2A" 2 | @define FPU "1" 3 | 4 | @include "superh.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/8051/data/languages/80251.slaspec: -------------------------------------------------------------------------------- 1 | @define MCS251 "" 2 | 3 | @include "8051_main.sinc" 4 | 5 | @include "80251.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data-be-64.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | 3 | @define RAMSIZE "8" 4 | 5 | @include "data.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/STM8/extension.properties: -------------------------------------------------------------------------------- 1 | name=STM8 2 | description=STM8 instruction set 3 | author= 4 | createdOn= 5 | version=9.2 6 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/languages/AARCH64.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define DATA_ENDIAN "little" 3 | 4 | @include "AARCH64instructions.sinc" 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/languages/AARCH64BE.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define DATA_ENDIAN "big" 3 | 4 | @include "AARCH64instructions.sinc" 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM4t_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | 5 | @include "ARM.sinc" 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM4t_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | 5 | @include "ARM.sinc" 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data-le-64.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | 3 | @define RAMSIZE "8" 4 | 5 | @include "data.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/V850/data/manuals/v850.idx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/radareorg/ghidra-native/master/src/Processors/V850/data/manuals/v850.idx -------------------------------------------------------------------------------- /src/Processors/sBPF/README.md: -------------------------------------------------------------------------------- 1 | # sBPF 2 | 3 | The code comes from https://github.com/riptl/ghidra-ebpf.git, modified from eBPF to sBPF. 4 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/data/languages/TI_MSP430.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define REG_SIZE "2" 3 | 4 | @include "TI430Common.sinc" 5 | -------------------------------------------------------------------------------- /src/Processors/sBPF/data/languages/sBPF.sla: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/radareorg/ghidra-native/master/src/Processors/sBPF/data/languages/sBPF.sla -------------------------------------------------------------------------------- /src/Processors/wasm/bin/images/README.txt: -------------------------------------------------------------------------------- 1 | The "src/resources/images" directory is intended to hold all image/icon files used by 2 | this module. 3 | -------------------------------------------------------------------------------- /src/Processors/wasm/extension.properties: -------------------------------------------------------------------------------- 1 | name=@extname@ 2 | description=WebAssembly plugin 3 | author= 4 | createdOn= 5 | version=@extversion@ 6 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic16.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_16" 2 | 3 | @include "pic16.sinc" 4 | 5 | @include "pic16_instructions.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic16f.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_16F" 2 | 3 | @include "pic16.sinc" 4 | 5 | @include "pic16_instructions.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM5_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define VERSION_5 "" 4 | @define VERSION_5E "" 5 | 6 | @include "ARM.sinc" 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM5_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define VERSION_5 "" 4 | @define VERSION_5E "" 5 | 6 | @include "ARM.sinc" 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/HCS08/data/languages/HC08.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HC08 (68HC08) 2 | 3 | @define HC08 "1" 4 | 5 | @include "HCS_HC.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_builder_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "4" 3 | @define DATA_SPACE "ram" 4 | 5 | @include "toy_builder.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/sBPF/data/languages/sBPF.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /src/Processors/68000/data/languages/coldfire.slaspec: -------------------------------------------------------------------------------- 1 | # Motorola's Coldfire processor 2 | 3 | @define COLDFIRE "" 4 | @define MC68040 "" 5 | 6 | @include "68000.sinc" 7 | -------------------------------------------------------------------------------- /src/Processors/CR16/data/languages/CR16.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/HCS08/data/languages/HC05.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HC05 (6805, 68HC05) 2 | 3 | @define HC05 "1" 4 | 5 | @include "HCS_HC.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/HCS08/data/languages/HCS08.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HCS08 (68HCS08) 2 | 3 | @define HCS08 "1" 4 | 5 | @include "HCS_HC.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_builder_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define SIZE "4" 3 | @define DATA_SPACE "ram" 4 | 5 | @include "toy_builder.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/macros.sinc: -------------------------------------------------------------------------------- 1 | macro conditionalAssign(dest, cond, trueVal, falseVal) { 2 | dest = zext(cond) * trueVal | zext(!cond) * falseVal; 3 | } -------------------------------------------------------------------------------- /src/Processors/CP1600/data/languages/CP1600.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/MC6800/data/languages/6809.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/SuperH/data/languages/superh.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/data/languages/TI_MSP430X.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define REG_SIZE "4" 3 | 4 | @include "TI430Common.sinc" 5 | @include "TI430X.sinc" 6 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/x86-64.slaspec: -------------------------------------------------------------------------------- 1 | @define IA64 "IA64" 2 | @include "x86.slaspec" 3 | with : lockprefx=0 { 4 | @include "sgx.sinc" 5 | @include "fma.sinc" 6 | } 7 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr8.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 16-bit addressable code space 2 | 3 | @define PCBYTESIZE "2" 4 | @define HASEIND "0" 5 | 6 | @include "avr8.sinc" 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/STM8/data/languages/STM8.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define DATA_ENDIAN "little" 3 | 4 | @include "AARCH64instructions.sinc" 5 | @include "AARCH64_AMXext.sinc" 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM5t_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | 7 | @include "ARM.sinc" 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr8eind.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 22-bit addressable code space 2 | 3 | @define PCBYTESIZE "3" 4 | @define HASEIND "1" 5 | 6 | @include "avr8.sinc" 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_builder_be_align2.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define DATA_SPACE "ram" 5 | 6 | @include "toy_builder.sinc" 7 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_builder_le_align2.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define DATA_SPACE "ram" 5 | 6 | @include "toy_builder.sinc" 7 | -------------------------------------------------------------------------------- /src/Processors/8051/data/languages/mx51.slaspec: -------------------------------------------------------------------------------- 1 | @define MX51 "" 2 | @define OMIT_RETADDR 1 3 | @define DUAL_DPTR "" 4 | @define DPS_REG_NUM 0xa2 5 | 6 | @include "8051_main.sinc" 7 | @include "mx51.sinc" 8 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM5t_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | 7 | @include "ARM.sinc" 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr8e.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 16-bit addressable code space and support for 2 | 3 | @define PCBYTESIZE "2" 4 | @define HASEIND "1" 5 | 6 | @include "avr8.sinc" 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/dsPIC33C.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | define endian=little; # little endian only 4 | 5 | @define dsPIC33C "1" 6 | 7 | @include "PIC24.sinc" 8 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | AVR8_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/STM8/data/languages/STM8_large.slaspec: -------------------------------------------------------------------------------- 1 | 2 | # ram bus width - 24 bit 3 | # Produces a bit of unclear code, but suitable for any devices 4 | @define RAM_W "3" 5 | 6 | @include "STM8.sinc" 7 | -------------------------------------------------------------------------------- /src/Processors/STM8/data/languages/STM8_medium.slaspec: -------------------------------------------------------------------------------- 1 | 2 | # ram bus width - 16 bit 3 | # warning!! Suitable only for devices with <= 32kB flash!!! 4 | @define RAM_W "2" 5 | 6 | @include "STM8.sinc" 7 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_harvard.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/68000/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 68000_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/patterns/prepatternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | ARM_switch_patterns.xml 4 | 5 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | riscv_gc_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/Sparc/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | SPARC_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | pa-risc_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | SuperH4_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/V850/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | V850_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/tricore/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | tricore_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | AARCH64_LE_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/HCS12/data/languages/HC12.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HC12 (68HC12) 2 | 3 | @define HC12 "1" 4 | 5 | @define SIZE "2" 6 | 7 | @define MAXFLASHPage "0xFF" 8 | 9 | @include "HCS_HC12.sinc" -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | loongarch_patterns.xml 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/wasm/lib/README.txt: -------------------------------------------------------------------------------- 1 | The "lib" directory is intended to hold Jar files which this module 2 | is dependent upon. This directory may be eliminated from a specific 3 | module if no other Jar files are needed. 4 | -------------------------------------------------------------------------------- /src/Processors/HCS12/data/languages/HCS12.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HCS12 (68HCS12) 2 | 3 | @define HCS12 "1" 4 | 5 | @define SIZE "3" 6 | 7 | @define MAXFLASHPage "0xFF" 8 | 9 | @include "HCS_HC12.sinc" -------------------------------------------------------------------------------- /src/Processors/JVM/data/languages/JVM.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/unix/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/unix32/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/unix64/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/windows/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/MC6800/data/languages/6809.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Motorola 6809 2 | 3 | @define M6809 "" 4 | 5 | @include "6x09.sinc" 6 | @include "6x09_push.sinc" 7 | @include "6x09_pull.sinc" 8 | @include "6x09_exg_tfr.sinc" 9 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/data/languages/pa-risc32be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PA-RISC 32 bit big endian 2 | 3 | @define ENDIAN "big" 4 | @define BITS "32" 5 | 6 | @include "pa-risc.sinc" 7 | @include "pa-riscInstructions.sinc" 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/windows32/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/windows64/try_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "4" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy64_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "8" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy64_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define SIZE "8" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define SIZE "4" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "ram" 6 | 7 | @include "toy.sinc" 8 | @include "toyInstructions.sinc" 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/unix/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/unix32/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/unix64/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/CR16/data/languages/CR16.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | xtensa_patterns.xml 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/windows/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/windows32/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/extensions/rust/windows64/probe_fixup.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/wasm/data/languages/Webassembly.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/patterns/prepatternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | AARCH64_win_patterns.xml 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/old/ARMv5.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Sleigh-ARMv5 4 | ARM:LE:32:v5 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/M8C/data/languages/m8c.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/riscv.zi.sinc: -------------------------------------------------------------------------------- 1 | # RV32/RV64 Zifencei Standard Extension 2 | 3 | # fence.i 0000100f ffffffff SIMPLE (0, 0) 4 | :fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0 5 | { 6 | fence.i(); 7 | } 8 | -------------------------------------------------------------------------------- /src/Processors/hexagon/data/languages/hexagon.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /src/Processors/sBPF/data/languages/sBPF.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/tricore/data/languages/tricore.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/HCS12/data/languages/HCS12X.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Freescale HCS12 (68HCS12) 2 | 3 | @define HCS12 "1" 4 | @define HCS12X "1" 5 | @define SIZE "3" 6 | 7 | @define MAXFLASHPage "0xFF" 8 | 9 | @include "HCS_HC12.sinc" 10 | @include "XGATE.sinc" -------------------------------------------------------------------------------- /src/Processors/wasm/os/linux64/README.txt: -------------------------------------------------------------------------------- 1 | The "os/linux64" directory is intended to hold Linux native binaries 2 | which this module is dependent upon. This directory may be eliminated for a specific 3 | module if native binaries are not provided for the corresponding platform. 4 | -------------------------------------------------------------------------------- /src/Processors/wasm/os/osx64/README.txt: -------------------------------------------------------------------------------- 1 | The "os/osx64" directory is intended to hold macOS (OS X) native binaries 2 | which this module is dependent upon. This directory may be eliminated for a specific 3 | module if native binaries are not provided for the corresponding platform. 4 | -------------------------------------------------------------------------------- /src/Processors/wasm/os/win64/README.txt: -------------------------------------------------------------------------------- 1 | The "os/win64" directory is intended to hold MS Windows native binaries (.exe) 2 | which this module is dependent upon. This directory may be eliminated for a specific 3 | module if native binaries are not provided for the corresponding platform. 4 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr32a.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr8xmega.slaspec: -------------------------------------------------------------------------------- 1 | # AVR8 with 22-bit addressable code space 2 | 3 | @define PCBYTESIZE "3" 4 | @define HASEIND "1" 5 | 6 | @define IO_START "0" 7 | @define REGISTER_SPACE "register" 8 | @define EIND "0x3c" 9 | 10 | @include "avr8.sinc" 11 | 12 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM6_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VFPv2 "" 10 | 11 | @include "ARM.sinc" 12 | 13 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM6_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VFPv2 "" 10 | 11 | @include "ARM.sinc" 12 | 13 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_73_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | 4 | :unused_73 is inst0=0x73 5 | { 6 | #no pCode 7 | } 8 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/languages/loongarch32.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/languages/loongarch64.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 10 | 11 | -------------------------------------------------------------------------------- /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | - package-ecosystem: "github-actions" 4 | directory: "/" 5 | schedule: 6 | interval: "weekly" 7 | commit-message: 8 | prefix: "##build " 9 | prefix-development: "##build " 10 | labels: 11 | - buildsystem 12 | -------------------------------------------------------------------------------- /src/decompiler/.gitignore: -------------------------------------------------------------------------------- 1 | coreext_* 2 | ghidraext_* 3 | consoleext_* 4 | libdecomp.a 5 | libdecomp_dbg.a 6 | decomp_dbg 7 | decomp_opt 8 | ghidra_dbg 9 | ghidra_opt 10 | ghidra_test_dbg 11 | sleigh_dbg 12 | com_dbg 13 | com_opt 14 | test_dbg 15 | ghi_dbg 16 | ghi_opt 17 | sla_dbg 18 | sla_opt 19 | 20 | -------------------------------------------------------------------------------- /src/Processors/8051/data/languages/8051.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 32-bit little endian 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @include "ppc_common.sinc" 10 | @include "altivec.sinc" 11 | @include "g2.sinc" 12 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_wsz_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define WORDSIZE "2" 5 | 6 | @define INSTR_PHASE "" # not used by basic toy language 7 | @define DATA_SPACE "ram" 8 | 9 | @include "toy.sinc" 10 | @include "toyInstructions.sinc" 11 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_wsz_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @define ALIGN "2" 3 | @define SIZE "4" 4 | @define WORDSIZE "2" 5 | 6 | @define INSTR_PHASE "" # not used by basic toy language 7 | @define DATA_SPACE "ram" 8 | 9 | @include "toy.sinc" 10 | @include "toyInstructions.sinc" 11 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | MIPS_BE_patterns.xml 4 | 5 | 6 | MIPS_LE_patterns.xml 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/tricore/data/languages/tricore.slaspec: -------------------------------------------------------------------------------- 1 | @define Tricore "" 2 | 3 | @define TRICORE_GENERIC "" 4 | #@define TRICORE_RIDER_D "" 5 | #@define TRICORE_RIDER_B "" 6 | 7 | @define TRICORE_V2 "" 8 | 9 | #@define TRICORE_VERBOSE "" 10 | 11 | define endian=little; 12 | 13 | @include "tricore.sinc" 14 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/data/languages/pa-risc32.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_4xx_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "4xx.sinc" 13 | 14 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | PPC_BE_patterns.xml 4 | 5 | 6 | PPC_LE_patterns.xml 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/xtensa.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/8085/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/8085.cspec||GHIDRA||||END| 5 | data/languages/8085.ldefs||GHIDRA||reviewed||END| 6 | data/languages/8085.pspec||GHIDRA||reviewed||END| 7 | data/languages/8085.slaspec||GHIDRA||||END| 8 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_4xx_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "4xx.sinc" 13 | 14 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_64_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 64-bit big endian 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "8" 6 | @define BIT_64 "64" 7 | @define EATRUNC "ea:4" 8 | 9 | @include "ppc_common.sinc" 10 | @include "altivec.sinc" 11 | @include "g2.sinc" 12 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_64_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 64-bit little endian 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "8" 6 | @define BIT_64 "64" 7 | @define EATRUNC "ea:4" 8 | 9 | @include "ppc_common.sinc" 10 | @include "altivec.sinc" 11 | @include "g2.sinc" 12 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_Base.slaspec: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # Sleigh specification file for DALVIK VM (base set of instructions) 3 | #------------------------------------------------------------------------------------ 4 | 5 | @include "Dalvik_Base.sinc" -------------------------------------------------------------------------------- /src/Processors/MC6800/data/languages/H6309.slaspec: -------------------------------------------------------------------------------- 1 | # sleigh specification file for Hitachi 6309 2 | # Compatible with MC6809 with some extended instructions 3 | # and addressing modes 4 | 5 | @define H6309 "" 6 | 7 | @include "6x09.sinc" 8 | @include "6x09_push.sinc" 9 | @include "6x09_pull.sinc" 10 | @include "6x09_exg_tfr.sinc" 11 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/PIC24E.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define PIC24E "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/PIC24F.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define PIC24F "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/PIC24H.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define PIC24H "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/dsPIC30F.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define dsPIC30F "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/dsPIC33E.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define dsPIC33E "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/dsPIC33F.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines Microchip PIC-24. 2 | 3 | # Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) 4 | 5 | define endian=little; # little endian only 6 | 7 | @define dsPIC33F "1" 8 | 9 | @include "PIC24.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/languages/SuperH4_be.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines SuperH version 4a, but should work against versions 1,2, and 3. 2 | # DSP Extensions are not yet added 3 | 4 | # Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) 5 | 6 | @define ENDIAN "big" 7 | 8 | @include "SuperH4.sinc" 9 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/xtensa.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/languages/mips32R6be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 big endian 2 | 3 | @define ENDIAN "big" 4 | @define FREGSIZE "8" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_dsp.sinc" 12 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/languages/mips32R6le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 little endian 2 | 3 | @define ENDIAN "little" 4 | @define FREGSIZE "8" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_dsp.sinc" -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for PowerPC 32-bit big endian 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "altivec.sinc" 13 | @include "g2.sinc" 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86RealV1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Real Mode 4 | x86:LE:16:Real Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86RealV2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Real Mode 4 | x86:LE:16:Real Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86RealV3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Real Mode 4 | x86:LE:16:Real Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/8048/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/8048.cspec||GHIDRA||||END| 5 | data/languages/8048.ldefs||GHIDRA||||END| 6 | data/languages/8048.pspec||GHIDRA||||END| 7 | data/languages/8048.slaspec||GHIDRA||||END| 8 | data/manuals/8048.idx||GHIDRA||||END| 9 | -------------------------------------------------------------------------------- /src/Processors/BPF/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/BPF.cspec||GHIDRA||||END| 5 | data/languages/BPF.ldefs||GHIDRA||||END| 6 | data/languages/BPF.pspec||GHIDRA||||END| 7 | data/languages/BPF.sinc||GHIDRA||||END| 8 | data/languages/BPF_le.slaspec||GHIDRA||||END| 9 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy64_be_harvard.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "8" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define DATA_SPACE "data" 6 | 7 | @include "toy.sinc" 8 | 9 | define space data type=ram_space size=$(SIZE) wordsize=$(WORDSIZE); 10 | 11 | @include "toyInstructions.sinc" 12 | -------------------------------------------------------------------------------- /src/Processors/eBPF/data/languages/eBPF.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_barrier.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # V(0x73, RETURN_VOID_BARRIER, "return-void-barrier", k10x, false, kNone, kReturn, kVerifyNone) \ 3 | 4 | :return_void_barrier is inst1=0x73 & inst1_padding 5 | { 6 | return [sp]; 7 | } 8 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_quicciii_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "big" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "quicciii.sinc" 13 | @include "evx.sinc" 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/V850/data/languages/V850.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/flix.sinc: -------------------------------------------------------------------------------- 1 | 2 | # FLIX (Flexible Length Instruction eXtension) is a Xtensa processor extension 3 | # that allows for variable-length, multi-op instructions with support from 4 4 | # 16 bytes. Customizable, if found they should be flagged. 5 | 6 | define pcodeop flix; 7 | :FLIX u_4_23 is op0=0xe & u_4_23 { 8 | flix(); 9 | } -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_ProtV2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Protected Mode 4 | x86:LE:16:Protected Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_ProtV3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:16:Protected Mode 4 | x86:LE:16:Protected Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_quicciii_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC 4xx series core 2 | 3 | @define ENDIAN "little" 4 | 5 | @define REGISTER_SIZE "4" 6 | 7 | @define EATRUNC "ea" 8 | 9 | @define CTR_OFFSET "32" 10 | 11 | @include "ppc_common.sinc" 12 | @include "quicciii.sinc" 13 | @include "evx.sinc" 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/riscv.ilp32d.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @define XLEN 4 4 | @define XLEN2 8 5 | @define FLEN 8 6 | 7 | @define MXLEN_1 31 8 | @define MXLEN_2 30 9 | 10 | @define ADDRSIZE "32" 11 | @define FPSIZE "64" 12 | 13 | @include "riscv.reg.sinc" 14 | @include "riscv.table.sinc" 15 | @include "riscv.instr.sinc" 16 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/riscv.lp64d.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | @define XLEN 8 4 | @define XLEN2 16 5 | @define FLEN 8 6 | 7 | @define MXLEN_1 63 8 | @define MXLEN_2 62 9 | 10 | @define ADDRSIZE "64" 11 | @define FPSIZE "64" 12 | 13 | @include "riscv.reg.sinc" 14 | @include "riscv.table.sinc" 15 | @include "riscv.instr.sinc" 16 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/languages/old/SuperH4-BE-16.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | SuperH4:BE:16:default 4 | SuperH4:BE:32:default 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/languages/old/SuperH4-LE-16.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | SuperH4:LE:16:default 4 | SuperH4:LE:32:default 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/V850/data/languages/V850.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /src/Processors/CP1600/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/CP1600.cspec||GHIDRA||||END| 5 | data/languages/CP1600.ldefs||GHIDRA||||END| 6 | data/languages/CP1600.opinion||GHIDRA||||END| 7 | data/languages/CP1600.pspec||GHIDRA||||END| 8 | data/languages/CP1600.slaspec||GHIDRA||||END| 9 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/old/oldPPC.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Sleigh-PowerPC 32-bit 4 | PowerPC:BE:32:default 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_no_barrier.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | # V(0x73, RETURN_VOID_NO_BARRIER, "return-void-no-barrier", k10x, false, kNone, kReturn, kVerifyNone) \ 3 | 4 | :return_void_no_barrier is inst1=0x73 & inst1_padding 5 | { 6 | return [sp]; 7 | } 8 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/g2.sinc: -------------------------------------------------------------------------------- 1 | 2 | define pcodeop tlbli; 3 | define pcodeop tlbld; 4 | 5 | :tlbld B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=978 & BIT_0=0 6 | { 7 | tlbld(B); 8 | } 9 | 10 | :tlbli B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=1010 & BIT_0=0 11 | { 12 | tlbli(B); 13 | } 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86smmV1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:System Management Mode 4 | x86:LE:32:System Management Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86smmV2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:System Management Mode 4 | x86:LE:32:System Management Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86smmV3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:System Management Mode 4 | x86:LE:32:System Management Mode 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr32.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy_be_posStack.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "4" 3 | 4 | @define INSTR_PHASE "" # not used by basic toy language 5 | @define POS_STACK "true" # enables switch in instructions for push/pop to work in positive direction 6 | @define DATA_SPACE "ram" 7 | 8 | @include "toy.sinc" 9 | @include "toyInstructions.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/tricore/data/languages/tricore.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_79_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0x79, UNUSED_79, "unused-79", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_79 is inst0=0x79 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_7A_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0x7A, UNUSED_7A, "unused-7a", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_7a is inst0=0x7a 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F3_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF3, UNUSED_F3, "unused-f3", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f3 is inst0=0xf3 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F4_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF4, UNUSED_F4, "unused-f4", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f4 is inst0=0xf4 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F7_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF7, UNUSED_F7, "unused-f7", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f7 is inst0=0xf7 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F8_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF8, UNUSED_F8, "unused-f8", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f8 is inst0=0xf8 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F9_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF9, UNUSED_F9, "unused-f9", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f9 is inst0=0xf9 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFA, UNUSED_FA, "unused-fa", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fa is inst0=0xfa 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_FB_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFB, UNUSED_FB, "unused-fb", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fb is inst0=0xfb 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_FC_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFC, UNUSED_FC, "unused-fc", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fc is inst0=0xfc 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_FD_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFD, UNUSED_FD, "unused-fd", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fd is inst0=0xfd 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFE, UNUSED_FE, "unused-fe", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_fe is inst0=0xfe 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_FF_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xFF, UNUSED_FF, "unused-ff", k10x, false, kUnknown, 0, kVerifyError) 4 | 5 | :unused_ff is inst0=0xff 6 | { 7 | #no pCode 8 | } 9 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/languages/mips32be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 big endian 2 | 3 | @define ENDIAN "big" 4 | @define FREGSIZE "4" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_mt.sinc" 12 | @include "mips_dsp.sinc" 13 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/xtensa_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @include "xtensaArch.sinc" 3 | @include "xtensaMain.sinc" 4 | 5 | with : phase=1 { 6 | 7 | @include "xtensaInstructions.sinc" 8 | #@include "xtensa_depbits.sinc" #uncomment this to use depbits instruction, collides with floating point 9 | @include "cust.sinc" 10 | @include "flix.sinc" 11 | 12 | } -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/languages/AARCH64.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/languages/mips32le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS32 little endian 2 | 3 | @define ENDIAN "little" 4 | @define FREGSIZE "4" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips_mt.sinc" 12 | @include "mips_dsp.sinc" 13 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/languages/mips64be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS r5000 big endian 2 | 3 | @define ENDIAN "big" 4 | @define MIPS64 "" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips64Instructions.sinc" 12 | @include "mips_dsp.sinc" 13 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM7_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define SIMD "" 12 | @define VFPv3 "" 13 | @define VFPv4 "" 14 | 15 | @include "ARM.sinc" 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/xtensa_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | @include "xtensaArch.sinc" 3 | @include "xtensaMain.sinc" 4 | 5 | with : phase=1 { 6 | 7 | @include "xtensaInstructions.sinc" 8 | #@include "xtensa_depbits.sinc" #uncomment this to use depbits instruction, collides with floating point 9 | @include "cust.sinc" 10 | @include "flix.sinc" 11 | 12 | } 13 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86V1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:default 4 | x86:LE:32:default 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM7_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define SIMD "" 12 | @define VFPv3 "" 13 | @define VFPv4 "" 14 | 15 | @include "ARM.sinc" 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F5_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF5, UNUSED_F5, "unused-f5", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f5 is inst0=0xf5 6 | { 7 | #no pCode 8 | } 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/Dalvik/data/languages/Dalvik_OpCode_F6_unused.sinc: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------------ 2 | #------------------------------------------------------------------------------------ 3 | # V(0xF6, UNUSED_F6, "unused-f6", k10x, false, kUnknown, 0, kVerifyError) \ 4 | 5 | :unused_f6 is inst0=0xf6 6 | { 7 | #no pCode 8 | } 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/languages/loongarch32_f64.slaspec: -------------------------------------------------------------------------------- 1 | @define REGSIZE 4 2 | @define FREGSIZE 8 3 | @define ADDRSIZE 4 4 | @include "loongarch_main.sinc" 5 | @include "loongarch32_instructions.sinc" 6 | @include "loongarch_float.sinc" 7 | @include "loongarch_double.sinc" 8 | 9 | #@include "lasx.sinc" 10 | #@include "lbt.sinc" 11 | #@include "lsx.sinc" 12 | #@include "lvz.sinc" 13 | -------------------------------------------------------------------------------- /src/Processors/M8C/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/build.xml||GHIDRA||||END| 5 | data/languages/m8c.cspec||GHIDRA||||END| 6 | data/languages/m8c.ldefs||GHIDRA||||END| 7 | data/languages/m8c.opinion||GHIDRA||||END| 8 | data/languages/m8c.pspec||GHIDRA||||END| 9 | data/languages/m8c.slaspec||GHIDRA||||END| 10 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_64bit_v1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x64:LE:64:default 4 | x86:LE:64:default 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/HCS08/data/languages/HCS08.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/languages/loongarch32_f32.slaspec: -------------------------------------------------------------------------------- 1 | @define REGSIZE 4 2 | @define FREGSIZE 4 3 | @define ADDRSIZE 4 4 | @include "loongarch_main.sinc" 5 | @include "loongarch32_instructions.sinc" 6 | @include "loongarch_float.sinc" 7 | @include "loongarch_double.sinc" 8 | 9 | 10 | @include "lasx.sinc" 11 | @include "lbt.sinc" 12 | @include "lsx.sinc" 13 | @include "lvz.sinc" 14 | -------------------------------------------------------------------------------- /src/Processors/MIPS/data/languages/mips64le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for MIPS r5000 little endian 2 | 3 | @define ENDIAN "little" 4 | @define MIPS64 "" 5 | @define ISA_VARIANT "" 6 | 7 | @include "mips.sinc" 8 | @include "mips32Instructions.sinc" 9 | @include "mips16.sinc" 10 | @include "mipsmicro.sinc" 11 | @include "mips64Instructions.sinc" 12 | @include "mips_dsp.sinc" 13 | 14 | -------------------------------------------------------------------------------- /src/Processors/8051/data/languages/old/8051v1.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | 8051:BE:16:default 4 | 8051:BE:16:default 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_64bit_compat32_v2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:compat32 4 | x86:LE:64:compat32 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_64bit_compat32_v3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:compat32 4 | x86:LE:64:compat32 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM8_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define VFPv3 "" 14 | @define VFPv4 "" 15 | 16 | @include "ARM.sinc" 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/old/THUMBv2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | Sleigh-THUMBv2 4 | ARM:LE:32:v5t 5 | 6 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM8_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define VFPv3 "" 14 | @define VFPv4 "" 15 | 16 | @include "ARM.sinc" 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/68000/data/languages/68000.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/data/languages/TI_MSP430.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/data/languages/TI_MSP430X.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/x86-32-golang.register.info: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/languages/SuperH4_le.slaspec: -------------------------------------------------------------------------------- 1 | # This module defines SuperH version 4, but should work against versions 1,2, and 3. 2 | # There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable 3 | # with this. 4 | 5 | # Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) 6 | 7 | @define ENDIAN "little" 8 | 9 | @include "SuperH4.sinc" 10 | -------------------------------------------------------------------------------- /src/Processors/MCS96/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/build.xml||GHIDRA||||END| 5 | data/languages/MCS96.cspec||GHIDRA||||END| 6 | data/languages/MCS96.ldefs||GHIDRA||||END| 7 | data/languages/MCS96.pspec||GHIDRA||||END| 8 | data/languages/MCS96.sinc||GHIDRA||||END| 9 | data/languages/MCS96.slaspec||GHIDRA||||END| 10 | data/manuals/MCS96.idx||GHIDRA||||END| 11 | -------------------------------------------------------------------------------- /src/Processors/6502/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/6502.cspec||GHIDRA||||END| 5 | data/languages/6502.ldefs||GHIDRA||||END| 6 | data/languages/6502.pspec||GHIDRA||||END| 7 | data/languages/6502.slaspec||GHIDRA||||END| 8 | data/languages/65c02.slaspec||GHIDRA||||END| 9 | data/manuals/6502.idx||GHIDRA||||END| 10 | data/manuals/65c02.idx||GHIDRA||||END| 11 | -------------------------------------------------------------------------------- /src/Processors/68000/data/languages/68000.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/BPF/data/languages/BPF.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/patterns/patternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | ARM_LE_patterns.xml 4 | 5 | 6 | 7 | ARM_BE_patterns.xml 8 | 9 | 10 | 11 | ARM_LE_patterns.xml 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/languages/loongarch64_f64.slaspec: -------------------------------------------------------------------------------- 1 | @define LA64 "" 2 | 3 | @define REGSIZE 8 4 | @define FREGSIZE 8 5 | @define ADDRSIZE 8 6 | @include "loongarch_main.sinc" 7 | @include "loongarch32_instructions.sinc" 8 | @include "loongarch64_instructions.sinc" 9 | @include "loongarch_float.sinc" 10 | @include "loongarch_double.sinc" 11 | 12 | @include "lasx.sinc" 13 | @include "lbt.sinc" 14 | @include "lsx.sinc" 15 | @include "lvz.sinc" 16 | -------------------------------------------------------------------------------- /src/Processors/MCS96/data/languages/MCS96.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV32I.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV64I.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM8m_be.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "big" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define CDE "" 14 | @define CORTEX "" 15 | @define VFPv3 "" 16 | @define VFPv4 "" 17 | 18 | @include "ARM.sinc" 19 | @include "ARM_CDE.sinc" 20 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM8m_le.slaspec: -------------------------------------------------------------------------------- 1 | 2 | @define ENDIAN "little" 3 | @define T_VARIANT "" 4 | @define VERSION_5 "" 5 | @define VERSION_5E "" 6 | @define VERSION_6 "" 7 | @define VERSION_6K "" 8 | @define VERSION_6T2 "" 9 | @define VERSION_7 "" 10 | @define VERSION_7M "" 11 | @define VERSION_8 "" 12 | @define SIMD "" 13 | @define CDE "" 14 | @define CORTEX "" 15 | @define VFPv3 "" 16 | @define VFPv4 "" 17 | 18 | @include "ARM.sinc" 19 | @include "ARM_CDE.sinc" 20 | -------------------------------------------------------------------------------- /src/Processors/JVM/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/ExtensionPoint.manifest||GHIDRA||||END| 5 | data/build.xml||GHIDRA||||END| 6 | data/languages/JVM.cspec||GHIDRA||||END| 7 | data/languages/JVM.ldefs||GHIDRA||||END| 8 | data/languages/JVM.opinion||GHIDRA||||END| 9 | data/languages/JVM.pspec||GHIDRA||||END| 10 | data/languages/JVM.slaspec||GHIDRA||||END| 11 | data/manuals/JVM.idx||GHIDRA||||END| 12 | -------------------------------------------------------------------------------- /src/Processors/Loongarch/data/languages/loongarch64_f32.slaspec: -------------------------------------------------------------------------------- 1 | @define LA64 "" 2 | 3 | @define REGSIZE 8 4 | @define FREGSIZE 4 5 | @define ADDRSIZE 8 6 | @include "loongarch_main.sinc" 7 | @include "loongarch32_instructions.sinc" 8 | @include "loongarch64_instructions.sinc" 9 | @include "loongarch_float.sinc" 10 | @include "loongarch_double.sinc" 11 | 12 | 13 | @include "lasx.sinc" 14 | @include "lbt.sinc" 15 | @include "lsx.sinc" 16 | @include "lvz.sinc" 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /patches/0023-Undef-LoadImage-for-windows.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/loadimage.hh b/src/decompiler/loadimage.hh 2 | index 59d4c9a..3557744 100644 3 | --- a/src/decompiler/loadimage.hh 4 | +++ b/src/decompiler/loadimage.hh 5 | @@ -21,6 +21,10 @@ 6 | 7 | #include "address.hh" 8 | 9 | +#ifdef LoadImage 10 | +#undef LoadImage 11 | +#endif 12 | + 13 | /// \brief Exception indicating data was not available 14 | /// 15 | /// This exception is thrown when a request for load image 16 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy64_be_harvard_rev.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | @define SIZE "8" 3 | @define WORDSIZE "1" 4 | @define ALIGN "1" 5 | 6 | @define INSTR_PHASE "" # not used by basic toy language 7 | @define DATA_SPACE "data" 8 | 9 | @define ALREADY_ENDIAN_ALIGN 10 | define endian=$(ENDIAN); 11 | define alignment=$(ALIGN); 12 | define space data type=ram_space size=$(SIZE) wordsize=$(WORDSIZE); 13 | 14 | @include "toy.sinc" 15 | 16 | @include "toyInstructions.sinc" 17 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV32IC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV64IC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /patches/0091-decompiler-xml-packer.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/prettyprint.cc b/src/decompiler/prettyprint.cc 2 | index 3e8d18a..4d48bf8 100644 3 | --- a/src/decompiler/prettyprint.cc 4 | +++ b/src/decompiler/prettyprint.cc 5 | @@ -279,7 +279,7 @@ void EmitMarkup::setOutputStream(ostream *t) 6 | if (encoder != (Encoder *)0) 7 | delete encoder; 8 | s = t; 9 | - encoder = new PackedEncode(*s); 10 | + encoder = new XmlEncode(*s); 11 | } 12 | 13 | int4 TokenSplit::countbase = 0; 14 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e500 series core 2 | 3 | #@define E500 4 | 5 | @define ENDIAN "little" 6 | 7 | @define REGISTER_SIZE "4" 8 | 9 | @define EATRUNC "ea" 10 | 11 | # e500mc has 32 bit registers 12 | # 13 | @define CTR_OFFSET "32" 14 | 15 | @define NoLegacyIntegerMultiplyAccumulate "1" 16 | 17 | @include "ppc_common.sinc" 18 | @include "quicciii.sinc" 19 | @include "evx.sinc" 20 | @include "SPEF_SCR.sinc" 21 | 22 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/xtensa.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/eBPF/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/eBPF.cspec||GHIDRA||||END| 5 | data/languages/eBPF.dwarf||GHIDRA||||END| 6 | data/languages/eBPF.ldefs||GHIDRA||||END| 7 | data/languages/eBPF.opinion||GHIDRA||||END| 8 | data/languages/eBPF.pspec||GHIDRA||||END| 9 | data/languages/eBPF.sinc||GHIDRA||||END| 10 | data/languages/eBPF_be.slaspec||GHIDRA||||END| 11 | data/languages/eBPF_le.slaspec||GHIDRA||||END| 12 | -------------------------------------------------------------------------------- /patches/0056-nullderef-workaround.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/merge.hh b/src/decompiler/merge.hh 2 | index bcce463..c965f86 100644 3 | --- a/src/decompiler/merge.hh 4 | +++ b/src/decompiler/merge.hh 5 | @@ -137,6 +137,7 @@ public: 6 | inline bool Merge::compareHighByBlock(const HighVariable *a,const HighVariable *b) 7 | 8 | { 9 | + if (!a || !b) return false; 10 | int4 result = a->getCover().compareTo(b->getCover()); 11 | if ( result == 0 ) { 12 | Varnode *v1 = a->getInstance( 0 ); 13 | -------------------------------------------------------------------------------- /src/Processors/HCS12/data/languages/HCS12.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/Processors/SuperH/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/sh-1.slaspec||GHIDRA||||END| 5 | data/languages/sh-2.slaspec||GHIDRA||||END| 6 | data/languages/sh-2a.slaspec||GHIDRA||||END| 7 | data/languages/superh.cspec||GHIDRA||||END| 8 | data/languages/superh.ldefs||GHIDRA||||END| 9 | data/languages/superh.pspec||GHIDRA||||END| 10 | data/languages/superh.sinc||GHIDRA||||END| 11 | data/languages/superh2a.cspec||GHIDRA||||END| 12 | -------------------------------------------------------------------------------- /src/Processors/hexagon/data/languages/hexagon.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_64bit_v2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:default 4 | x86:LE:64:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86_64bit_v3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:64:default 4 | x86:LE:64:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/DATA/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/data-be-64.slaspec||GHIDRA||||END| 5 | data/languages/data-le-64.slaspec||GHIDRA||||END| 6 | data/languages/data-ptr16.cspec||GHIDRA||||END| 7 | data/languages/data-ptr32.cspec||GHIDRA||||END| 8 | data/languages/data-ptr64.cspec||GHIDRA||||END| 9 | data/languages/data.ldefs||GHIDRA||||END| 10 | data/languages/data.pspec||GHIDRA||||END| 11 | data/languages/data.sinc||GHIDRA||||END| 12 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/evx.sinc: -------------------------------------------------------------------------------- 1 | 2 | @include "Scalar_SPFP.sinc" 3 | @ifdef IS_ISA 4 | @include "SPE_APU.sinc" 5 | @endif 6 | 7 | :lvx vrD, RA_OR_ZERO, RB is OP=31 & vrD & RA_OR_ZERO & RB & XOP_1_10=103 & BIT_0=0 8 | { 9 | ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; 10 | vrD = *:16 ($(EATRUNC)); 11 | } 12 | 13 | :stvx vrS, RA_OR_ZERO, RB is OP=31 & vrS & RA_OR_ZERO & RB & XOP_1_10=231 & BIT_0=0 14 | { 15 | ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; 16 | *:16 ($(EATRUNC)) = vrS; 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV32IMC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/languages/SuperH4.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /patches/0010-null-subflow.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/subflow.cc b/src/decompiler/subflow.cc 2 | index 0c42b50..522c435 100644 3 | --- a/src/decompiler/subflow.cc 4 | +++ b/src/decompiler/subflow.cc 5 | @@ -66,6 +66,9 @@ SubvariableFlow::ReplaceVarnode *SubvariableFlow::setReplacement(Varnode *vn,uin 6 | 7 | { 8 | ReplaceVarnode *res; 9 | + if (vn == nullptr) { 10 | + return nullptr; 11 | + } 12 | if (vn->isMark()) { // Already seen before 13 | map::iterator iter; 14 | iter = varmap.find(vn); 15 | -------------------------------------------------------------------------------- /src/Processors/8085/data/languages/8085.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | Intel 8085 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/clwb.sinc: -------------------------------------------------------------------------------- 1 | define pcodeop clwb; 2 | :CLWB m8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=6 ... { 3 | clwb(m8); 4 | } 5 | 6 | @ifdef IA64 7 | define pcodeop clflushopt; 8 | :CLFLUSHOPT m8 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=7 ... { 9 | clflushopt(m8); 10 | } 11 | @endif 12 | 13 | # Note: PCOMMIT was deprecated prior to it ever being implemented in production processors. 14 | # I never found the encoding for it. Therefore, no constructor. 15 | -------------------------------------------------------------------------------- /src/Processors/M8C/data/languages/m8c.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | Cypress M8C Microcontroller Family 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /patches/0080-getparent-flow.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/flow.cc b/src/decompiler/flow.cc 2 | index 178047f..78565eb 100644 3 | --- a/src/decompiler/flow.cc 4 | +++ b/src/decompiler/flow.cc 5 | @@ -1006,8 +1006,10 @@ void FlowInfo::connectBasic(void) 6 | op = *iter++; 7 | targ_op = *iter2++; 8 | bs = op->getParent(); 9 | - targ_bs = targ_op->getParent(); 10 | - bblocks.addEdge(bs,targ_bs); 11 | + if (targ_op != nullptr) { 12 | + targ_bs = targ_op->getParent(); 13 | + bblocks.addEdge(bs,targ_bs); 14 | + } 15 | } 16 | } 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/BPF/data/languages/BPF.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | BPF processor 32-bit little-endian 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/hexagon/data/languages/hexagon.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | Hexagon Language Module 12 | 13 | 14 | -------------------------------------------------------------------------------- /src/Processors/CP1600/data/languages/CP1600.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | General Instruments CP1600 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/xtensa_depbits.sinc: -------------------------------------------------------------------------------- 1 | # Xtensa Deposit Bits instruction 2 | # This is broken out because it collides with the floating point instructions. It is not included by default 3 | 4 | # DEPBITS - Add (RRR), pg. 394. 5 | shiftimm: simm is u4_20_23 & u1_16 [ simm = u1_16 << 4 + u4_20_23; ] { export *[const]:4 simm; } 6 | :depbits as, at, shiftimm, u4_12_15 is u3_17_19=0x5 & u4_12_15 & as & at & op0 = 0 & shiftimm { 7 | mask:4 = (1 << u4_12_15) - 1; 8 | bits:4 = (as & mask) << shiftimm; 9 | mask = mask << shiftimm; 10 | at = (~mask & at) | bits; 11 | } 12 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/x86.slaspec: -------------------------------------------------------------------------------- 1 | @include "ia.sinc" 2 | @include "lockable.sinc" 3 | with : lockprefx=0 { 4 | @include "avx.sinc" 5 | @include "avx_manual.sinc" 6 | @include "avx2.sinc" 7 | @include "avx2_manual.sinc" 8 | @include "avx512.sinc" 9 | @include "avx512_manual.sinc" 10 | @include "adx.sinc" 11 | @include "clwb.sinc" 12 | @include "pclmulqdq.sinc" 13 | @include "mpx.sinc" 14 | @include "lzcnt.sinc" 15 | @include "bmi1.sinc" 16 | @include "bmi2.sinc" 17 | @include "sha.sinc" 18 | @include "smx.sinc" 19 | @include "cet.sinc" 20 | @include "rdrand.sinc" 21 | } 22 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/data/languages/ti_msp430.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /src/Processors/MC6800/data/languages/6805.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | 6805 Microcontroller Family 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /src/Processors/M16C/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/M16C_60.cspec||GHIDRA||||END| 5 | data/languages/M16C_60.ldefs||GHIDRA||||END| 6 | data/languages/M16C_60.pspec||GHIDRA||||END| 7 | data/languages/M16C_60.slaspec||GHIDRA||||END| 8 | data/languages/M16C_80.cspec||GHIDRA||||END| 9 | data/languages/M16C_80.ldefs||GHIDRA||||END| 10 | data/languages/M16C_80.pspec||GHIDRA||||END| 11 | data/languages/M16C_80.slaspec||GHIDRA||||END| 12 | data/manuals/M16C_60.idx||GHIDRA||||END| 13 | data/manuals/M16C_80.idx||GHIDRA||||END| 14 | -------------------------------------------------------------------------------- /src/Processors/Z80/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/z180.pspec||GHIDRA||||END| 5 | data/languages/z180.slaspec||GHIDRA||||END| 6 | data/languages/z182.pspec||GHIDRA||||END| 7 | data/languages/z80.cspec||GHIDRA||||END| 8 | data/languages/z80.ldefs||GHIDRA||||END| 9 | data/languages/z80.pspec||GHIDRA||||END| 10 | data/languages/z80.slaspec||GHIDRA||||END| 11 | data/languages/z8401x.pspec||GHIDRA||||END| 12 | data/manuals/Z180.idx||GHIDRA||||END| 13 | data/manuals/Z80.idx||GHIDRA||||END| 14 | temp/z8401x.pspec||GHIDRA||||END| 15 | -------------------------------------------------------------------------------- /src/Processors/CR16/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/build.xml||GHIDRA||||END| 5 | data/languages/CR16.cspec||GHIDRA||||END| 6 | data/languages/CR16.ldefs||GHIDRA||||END| 7 | data/languages/CR16.opinion||GHIDRA||reviewed||END| 8 | data/languages/CR16.pspec||GHIDRA||reviewed||END| 9 | data/languages/CR16B.sinc||GHIDRA||reviewed||END| 10 | data/languages/CR16B.slaspec||GHIDRA||reviewed||END| 11 | data/languages/CR16C.sinc||GHIDRA||||END| 12 | data/languages/CR16C.slaspec||GHIDRA||reviewed||END| 13 | data/manuals/CR16.idx||GHIDRA||||END| 14 | -------------------------------------------------------------------------------- /src/Processors/V850/data/languages/V850.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Renesas V850 family 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/manuals/PIC-12.idx: -------------------------------------------------------------------------------- 1 | @PIC12_40139e.pdf [PIC12C5XX 8-Pin, 8-Bit CMOS Microcontrollers (DS40139E)] 2 | ADDWF , 49 3 | ANDLW , 49 4 | ANDWF , 49 5 | BCF , 49 6 | BSF , 50 7 | BTFSC , 50 8 | BTFSS , 50 9 | CALL , 51 10 | CLRF , 51 11 | CLRW , 51 12 | CLRWDT , 51 13 | COMF , 52 14 | DECF , 52 15 | DECFSZ , 52 16 | GOTO , 52 17 | INCF , 53 18 | INCFSZ , 53 19 | IORLW , 53 20 | IORWF , 53 21 | MOVLW , 54 22 | MOVF , 54 23 | MOVWF , 54 24 | NOP , 54 25 | OPTION , 55 26 | RETLW , 55 27 | RLF , 55 28 | RRF , 55 29 | SLEEP , 56 30 | SUBWF , 56 31 | SWAPF , 57 32 | TRIS , 57 33 | XORLW , 57 34 | XORWF , 57 35 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/data/languages/pa-risc.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/8048/data/languages/8048.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 14 | 8048 Microcontroller Family 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /src/Processors/MCS96/data/languages/MCS96.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Intel MCS-96 Microcontroller Family 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic17c7xx.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-17C7xx 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV32G.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV64G.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /src/Processors/JVM/data/languages/JVM.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Generic JVM 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86V2.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:default 4 | x86:LE:32:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/old/x86V3.trans: -------------------------------------------------------------------------------- 1 | 2 | 3 | x86:LE:32:default 4 | x86:LE:32:default 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/Processors/sBPF/data/languages/sBPF.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | sBPF processor 64-bit little-endian 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/pa-risc.ldefs||GHIDRA||||END| 5 | data/languages/pa-risc.opinion||GHIDRA||||END| 6 | data/languages/pa-risc.sinc||GHIDRA||||END| 7 | data/languages/pa-risc32.cspec||GHIDRA||||END| 8 | data/languages/pa-risc32.pspec||GHIDRA||||END| 9 | data/languages/pa-risc32be.slaspec||GHIDRA||reviewed||END| 10 | data/languages/pa-riscInstructions.sinc||GHIDRA||||END| 11 | data/manuals/pa11_acd.idx||GHIDRA||reviewed||END| 12 | data/patterns/pa-risc_patterns.xml||GHIDRA||||END| 13 | data/patterns/patternconstraints.xml||GHIDRA||||END| 14 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic18.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-18 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/old/v01stuff/toy.sinc: -------------------------------------------------------------------------------- 1 | # Main slaspec must define endianness and alignment 2 | 3 | @ifndef WORDSIZE 4 | @define WORDSIZE "1" 5 | @endif 6 | 7 | define space ROM type=ram_space size=$(SIZE) wordsize=$(WORDSIZE) default; 8 | 9 | define space register type=register_space size=2; 10 | 11 | define register offset=0x1000 size=$(SIZE) [ 12 | a0 a1 a2 a3 a4 a5 a6 a7 13 | a8 a9 a10 a11 a12 sp lr pc 14 | ]; 15 | 16 | # STATUS REGISTER MAP: (LOW) 17 | # C - CARRY 18 | # Z - ZERO 19 | # N - NEGATIVE 20 | # V - OVERFLOW 21 | 22 | define register offset=0x1100 size=1 [ 23 | C Z N V 24 | ]; 25 | 26 | -------------------------------------------------------------------------------- /src/Processors/x86/data/patterns/x86gcc_prepatterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 0xff25........ 6 | 0x68......00 7 | 0xe9......ff 8 | 9 | 10 | 11 | 12 | 13 | 14 | 0xf3 0x0f 0x1e 0xfa 15 | 0xf2 0xff 0x25 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV32GC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/RV64GC.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/wasm/data/languages/Webassembly.cspec: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/Processors/x86/data/patterns/prepatternconstraints.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | x86win_prepatterns.xml 6 | 7 | 8 | x86win_prepatterns.xml 9 | 10 | 11 | x86gcc_prepatterns.xml 12 | 13 | 14 | 15 | 16 | 17 | x86gcc_prepatterns.xml 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr32a.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Generic AVR32-A big-endian 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic16c5x.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-16C5x 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic12c5xx.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | PIC-12C5xx 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /patches/0090-nocasts-warnings.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/printc.cc b/src/decompiler/printc.cc 2 | index 64ecda1..a02ca74 100644 3 | --- a/src/decompiler/printc.cc 4 | +++ b/src/decompiler/printc.cc 5 | @@ -3095,6 +3097,7 @@ void PrintC::emitCommentFuncHeader(const Funcdata *fd) 6 | emitLineComment(1,comm); 7 | } 8 | } 9 | +/* 10 | if (option_nocasts) { 11 | if (extralinebreak) 12 | emit->tagLine(); 13 | @@ -3103,6 +3106,7 @@ void PrintC::emitCommentFuncHeader(const Funcdata *fd) 14 | emitLineComment(0,&comm); 15 | extralinebreak = true; 16 | } 17 | +*/ 18 | if (extralinebreak) 19 | emit->tagLine(); // Extra linebreak if comment exists 20 | } 21 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/data/languages/cust.sinc: -------------------------------------------------------------------------------- 1 | # Per the manual: 2 | # CUST0 and CUST1 opcode encodings shown in Table 7–193 are permanently reserved 3 | # for designer-defined opcodes. In the future, customers who use these spaces 4 | # exclusively for their own designer-defined opcodes will be able to add new 5 | # Tensilica-defined options without changing their opcodes or binary executables. 6 | 7 | define pcodeop cust0; 8 | 9 | :cust0 "{op2="^op2^", r="^ar^", s="^as^", t="^at^"}" is op0=0x0 & op1=0x6 & op2 & ar & as & at { 10 | cust0(); 11 | } 12 | 13 | define pcodeop cust1; 14 | 15 | :cust1 "{op2="^op2^", r="^ar^", s="^as^", t="^at^"}" is op0=0x0 & op1=0x7 & op2 & ar & as & at { 16 | cust1(); 17 | } -------------------------------------------------------------------------------- /src/Processors/6502/data/languages/6502.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/sBPF/data/languages/sBPF.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/wasm/data/languages/Webassembly.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 13 | Webassembly Language Module 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/manuals/PIC-16.idx: -------------------------------------------------------------------------------- 1 | @PIC16_33023a.pdf [PICmicro� Mid-Range MCU Family Reference Manual, December 1997 (DS33023A)] 2 | ADDLW , 530 3 | ADDWF , 531 4 | ANDLW , 532 5 | ANDWF , 533 6 | BCF , 534 7 | BSF , 535 8 | BTFSC , 536 9 | BTFSS , 537 10 | CALL , 538 11 | CLRF , 539 12 | CLRW , 540 13 | CLRWDT , 541 14 | COMF , 542 15 | DECF , 543 16 | DECFSZ , 544 17 | GOTO , 545 18 | INCF , 546 19 | INCFSZ , 547 20 | IORLW , 548 21 | IORWF , 549 22 | MOVLW , 550 23 | MOVF , 551 24 | MOVWF , 552 25 | NOP , 553 26 | OPTION , 554 27 | RETFIE , 555 28 | RETLW , 556 29 | RETURN , 557 30 | RLF , 558 31 | RRF , 559 32 | SLEEP , 560 33 | SUBLW , 561 34 | SUBWF , 562 35 | SWAPF , 563 36 | TRIS , 564 37 | XORLW , 565 38 | XORWF , 566 39 | -------------------------------------------------------------------------------- /src/Processors/TI_MSP430/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/TI430Common.sinc||GHIDRA||||END| 5 | data/languages/TI430X.sinc||GHIDRA||||END| 6 | data/languages/TI_MSP430.cspec||GHIDRA||||END| 7 | data/languages/TI_MSP430.dwarf||GHIDRA||||END| 8 | data/languages/TI_MSP430.ldefs||GHIDRA||||END| 9 | data/languages/TI_MSP430.pspec||GHIDRA||||END| 10 | data/languages/TI_MSP430.slaspec||GHIDRA||||END| 11 | data/languages/TI_MSP430X.cspec||GHIDRA||||END| 12 | data/languages/TI_MSP430X.dwarf||GHIDRA||||END| 13 | data/languages/TI_MSP430X.slaspec||GHIDRA||||END| 14 | data/languages/ti_msp430.opinion||GHIDRA||||END| 15 | data/manuals/MSP430.idx||GHIDRA||reviewed||END| 16 | -------------------------------------------------------------------------------- /src/Processors/Atmel/data/languages/avr8.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /src/Processors/MC6800/data/languages/6805.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/data/languages/pa-risc.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | Generic PA-RISC 32-bit big endian 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /src/Processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec: -------------------------------------------------------------------------------- 1 | # SLA specification file for IBM PowerPC e500 series core 2 | 3 | # NOTE: This language variant includes some registers and instructions not supported 4 | # by the actual processor (e.g., floating pointer registers and associated instructions). 5 | # The actual processor only supports a subset of the registers and instructions implemented. 6 | 7 | @define ENDIAN "big" 8 | 9 | @define REGISTER_SIZE "4" 10 | 11 | @define EATRUNC "ea" 12 | 13 | # e500mc has 32 bit registers 14 | # 15 | @define CTR_OFFSET "32" 16 | 17 | @define NoLegacyIntegerMultiplyAccumulate "1" 18 | 19 | @include "ppc_common.sinc" 20 | @include "quicciii.sinc" 21 | @include "evx.sinc" 22 | @include "SPEF_SCR.sinc" 23 | 24 | -------------------------------------------------------------------------------- /src/Processors/Sparc/data/languages/SparcV9.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/languages/SuperH4.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/Processors/eBPF/data/languages/eBPF.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /src/Processors/8048/data/manuals/8048.idx: -------------------------------------------------------------------------------- 1 | @8048.pdf [MCS-48 Microcomputer User's Manual, February 1978] 2 | ADD, 63 3 | ADDC, 63 4 | ANL, 64 5 | ANLD, 65 6 | CALL, 66 7 | CLR, 67 8 | CPL, 67 9 | DA, 68 10 | DEC, 68 11 | DIS, 69 12 | DJNZ, 69 13 | EN, 70 14 | ENT0, 70 15 | IN, 70 16 | INC, 71 17 | INS, 72 18 | JB, 72 19 | JC, 72 20 | JF0, 72 21 | JF1, 73 22 | JMP, 73 23 | JMPP, 73 24 | JNC, 73 25 | JNI, 74 26 | JNT0, 74 27 | JNT1, 74 28 | JNZ, 74 29 | JTF, 75 30 | JT0, 75 31 | JT1, 75 32 | JZ, 75 33 | MOV, 76 34 | MOVD, 79 35 | MOVP, 79 36 | MOVP3, 80 37 | MOVX, 80 38 | NOP, 81 39 | ORL, 81 40 | ORLD, 82 41 | OUTL, 82 42 | RET, 83 43 | RETR, 83 44 | RL, 83 45 | RLC, 84 46 | RR, 84 47 | RRC, 84 48 | SEL, 85 49 | STOP, 86 50 | STRT, 87 51 | SWAP, 87 52 | XCH, 88 53 | XCHD, 88 54 | XRL, 89 55 | -------------------------------------------------------------------------------- /src/Processors/M16C/data/languages/M16C_60.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 16 | Renesas M16C/60 16-Bit MicroComputer 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/M16C/data/languages/M16C_80.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 16 | Renesas M16C/80 16-Bit MicroComputer 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/Sparc/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/Sparc.dwarf||GHIDRA||||END| 5 | data/languages/Sparc.opinion||GHIDRA||||END| 6 | data/languages/SparcV9.ldefs||GHIDRA||||END| 7 | data/languages/SparcV9.pspec||GHIDRA||||END| 8 | data/languages/SparcV9.sinc||GHIDRA||||END| 9 | data/languages/SparcV9_32.cspec||GHIDRA||||END| 10 | data/languages/SparcV9_32.slaspec||GHIDRA||||END| 11 | data/languages/SparcV9_64.cspec||GHIDRA||||END| 12 | data/languages/SparcV9_64.slaspec||GHIDRA||||END| 13 | data/languages/SparcVIS.sinc||GHIDRA||||END| 14 | data/manuals/Sparc.idx||GHIDRA||reviewed||END| 15 | data/patterns/SPARC_patterns.xml||GHIDRA||||END| 16 | data/patterns/patternconstraints.xml||GHIDRA||||END| 17 | -------------------------------------------------------------------------------- /patches/0024-ignore-symbol-beyond-space.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/database.cc b/src/decompiler/database.cc 2 | index 6eab457..8d17f38 100644 3 | --- a/src/decompiler/database.cc 4 | +++ b/src/decompiler/database.cc 5 | @@ -1805,9 +1805,10 @@ SymbolEntry *ScopeInternal::addMapInternal(Symbol *sym,uint4 exfl,const Address 6 | string msg = "Symbol "; 7 | msg += sym->getName(); 8 | msg += " extends beyond the end of the address space"; 9 | - throw LowlevelError(msg); 10 | + fprintf (stderr, "%s\n", msg.c_str()); 11 | + //throw LowlevelError(msg); 12 | } 13 | - 14 | + 15 | list::iterator iter = rangemap->insert(initdata,addr.getOffset(),lastaddress.getOffset()); 16 | // Store reference to map in symbol 17 | sym->mapentry.push_back(iter); 18 | -------------------------------------------------------------------------------- /src/Processors/MC6800/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/6800.ldefs||GHIDRA||||END| 5 | data/languages/6805.cspec||GHIDRA||||END| 6 | data/languages/6805.ldefs||GHIDRA||||END| 7 | data/languages/6805.pspec||GHIDRA||reviewed||END| 8 | data/languages/6805.slaspec||GHIDRA||||END| 9 | data/languages/6809.cspec||GHIDRA||||END| 10 | data/languages/6809.pspec||GHIDRA||||END| 11 | data/languages/6809.slaspec||GHIDRA||||END| 12 | data/languages/6x09.sinc||GHIDRA||||END| 13 | data/languages/6x09_exg_tfr.sinc||GHIDRA||||END| 14 | data/languages/6x09_pull.sinc||GHIDRA||||END| 15 | data/languages/6x09_push.sinc||GHIDRA||||END| 16 | data/languages/H6309.slaspec||GHIDRA||||END| 17 | data/manuals/6809.idx||GHIDRA||||END| 18 | -------------------------------------------------------------------------------- /patches/0006-readonly-warning.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/funcdata_varnode.cc b/src/decompiler/funcdata_varnode.cc 2 | index dad2994..5a43b1d 100644 3 | --- a/src/decompiler/funcdata_varnode.cc 4 | +++ b/src/decompiler/funcdata_varnode.cc 5 | @@ -516,6 +516,7 @@ void Funcdata::transferVarnodeProperties(Varnode *vn,Varnode *newVn,int4 lsbOffs 6 | bool Funcdata::fillinReadOnly(Varnode *vn) 7 | 8 | { 9 | +/* 10 | if (vn->isWritten()) { // Can't replace output with constant 11 | PcodeOp *defop = vn->getDef(); 12 | if (defop->isMarker()) 13 | @@ -534,6 +535,7 @@ bool Funcdata::fillinReadOnly(Varnode *vn) 14 | } 15 | return false; // No change was made 16 | } 17 | +*/ 18 | 19 | if (vn->getSize() > sizeof(uintb)) 20 | return false; // Constant will exceed precision 21 | -------------------------------------------------------------------------------- /src/Processors/JVM/resources/ArrayLengthTest.java: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | class ArrayLengthTest{ 17 | 18 | public int getLength(int[] array){ 19 | return array.length; 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /src/Processors/68000/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/68000.cspec||GHIDRA||||END| 5 | data/languages/68000.dwarf||GHIDRA||||END| 6 | data/languages/68000.ldefs||GHIDRA||||END| 7 | data/languages/68000.opinion||GHIDRA||||END| 8 | data/languages/68000.pspec||GHIDRA||||END| 9 | data/languages/68000.sinc||GHIDRA||||END| 10 | data/languages/68000_register.cspec||GHIDRA||||END| 11 | data/languages/68020.slaspec||GHIDRA||reviewed||END| 12 | data/languages/68030.slaspec||GHIDRA||||END| 13 | data/languages/68040.slaspec||GHIDRA||||END| 14 | data/languages/coldfire.slaspec||GHIDRA||||END| 15 | data/manuals/68000.idx||GHIDRA||||END| 16 | data/patterns/68000_patterns.xml||GHIDRA||||END| 17 | data/patterns/patternconstraints.xml||GHIDRA||||END| 18 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data-ptr16.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data-ptr32.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data-ptr64.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /src/Processors/HCS12/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/build.xml||GHIDRA||||END| 5 | data/languages/HC12.cspec||GHIDRA||||END| 6 | data/languages/HC12.pspec||GHIDRA||||END| 7 | data/languages/HC12.slaspec||GHIDRA||||END| 8 | data/languages/HCS12.cspec||GHIDRA||||END| 9 | data/languages/HCS12.ldefs||GHIDRA||||END| 10 | data/languages/HCS12.opinion||GHIDRA||||END| 11 | data/languages/HCS12.pspec||GHIDRA||||END| 12 | data/languages/HCS12.slaspec||GHIDRA||||END| 13 | data/languages/HCS12X.cspec||GHIDRA||||END| 14 | data/languages/HCS12X.pspec||GHIDRA||||END| 15 | data/languages/HCS12X.slaspec||GHIDRA||||END| 16 | data/languages/HCS_HC12.sinc||GHIDRA||||END| 17 | data/languages/XGATE.sinc||GHIDRA||||END| 18 | data/manuals/HCS12.idx||GHIDRA||||END| 19 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic12c5xx.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_12C5XX" 2 | 3 | @include "pic12.sinc" 4 | 5 | # 6 | # NOTES - 7 | # 1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and 8 | # slightly modified to specify a the correct Register File Map. 9 | # 10 | 11 | # Bank-0 File Registers 12 | define DATA offset=0x00 size=1 [ 13 | INDF TMR0 PCL.0 STATUS.0 FSR.0 OSCCAL GPIO 14 | ]; 15 | 16 | @include "pic12_instructions.sinc" 17 | 18 | # IO Tristate Register 19 | define register offset=0x0020 size=1 [ TRIS ]; 20 | 21 | # TRIS register 22 | trisREG: "6" is f5=0x6 { export TRIS; } 23 | 24 | :TRIS trisREG is op6=0x00 & d=0 & trisREG { 25 | # ---- 0000 0000 0fff 26 | # 0000 0000 0000 0110 -> TRIS 6 27 | trisREG = W; 28 | } 29 | -------------------------------------------------------------------------------- /src/Processors/JVM/resources/WideInc.java: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | class WideInc{ 17 | 18 | public int wideInc(int x){ 19 | int y = x; 20 | y += 0x1234; 21 | return y; 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /src/Processors/JVM/resources/InvokeInterfaceTest.java: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | class InvokeInterfaceTest{ 17 | 18 | public int test1(Comparable x, Comparable y){ 19 | return x.compareTo(y); 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /src/Processors/8085/data/languages/8085.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /src/Processors/PA-RISC/data/patterns/pa-risc_patterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 0xe840c002 7 | 0xe840c000 0x........ 8 | 9 | 10 | 11 | 0x6bc23fd9 12 | 0x6bc23fd9 0x08030241 0x081e0243 13 | 0x........ 0x08030241 14 | 0x........ 0x........ 0x08030241 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/Sparc/data/languages/Sparc.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /src/Processors/Toy/data/languages/toy.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic16c5x.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /src/Processors/wasm/data/README.txt: -------------------------------------------------------------------------------- 1 | The "data" directory is intended to hold data files that will be used by this module and will 2 | not end up in the .jar file, but will be present in the zip or tar file. Typically, data 3 | files are placed here rather than in the resources directory if the user may need to edit them. 4 | 5 | An optional data/languages directory can exist for the purpose of containing various Sleigh language 6 | specification files and importer opinion files. 7 | 8 | The data/build.xml is used for building the contents of the data/languages directory. 9 | 10 | The skel language definition has been commented-out within the skel.ldefs file so that the 11 | skeleton language does not show-up within Ghidra. 12 | 13 | See the Sleigh language documentation (docs/languages/sleigh.htm or sleigh.pdf) for details 14 | on Sleigh language specification syntax. 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/DATA/data/languages/data.sinc: -------------------------------------------------------------------------------- 1 | define endian = $(ENDIAN); 2 | 3 | define alignment = 1; 4 | 5 | define space ram type=ram_space size=8 default; 6 | 7 | define space register type=register_space size=4; 8 | 9 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 10 | # AT LEAST ONE REGISTER, AND STACK POINTER ARE REQUIRED 11 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 12 | 13 | define register offset=0x0 size=8 [ sp r0 ]; 14 | 15 | # Define context bits 16 | define register offset=0x100 size=4 contextreg; 17 | 18 | define context contextreg 19 | test=(0,0) 20 | ; 21 | 22 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 23 | # AT LEAST ONE INSTRUCTION IS REQUIRED 24 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 25 | 26 | :nop is test=1 unimpl 27 | 28 | # # # # # # # # # # # # # # # # # # # # # # # # # # # # 29 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/data/patterns/SuperH4_patterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 0x0b 0x00 0x09 0x00 5 | 0x0b 0x00 0xf6 0x6. 6 | 0x0b 0x00 0x09 0x00 0x00 0x00 7 | 0x0b 0x00 0x.. 0x7f 8 | 9 | 10 | 10011101 11100011 10111... ........ 11 | 0x22 0x4f 12 | 0x22 0x4f 1....... 0x7f 13 | 1....... 0x7f 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ghidra-native 2 | 3 | [![ci](https://github.com/radareorg/ghidra-native/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/radareorg/ghidra-native/actions/workflows/ci.yml) 4 | 5 | This repository contains the native parts of ghidra, aiming to be used from r2ghidra: 6 | 7 | * Sleigh compiler 8 | * Decompiler 9 | 10 | Additionally it also contains the processors needed for it to work. 11 | 12 | This repository is mean to be manually updated from time to time. 13 | 14 | Reasons behind forking ghidra decompiler code: 15 | 16 | * Reduce the amount of noise and confusing subdirectories 17 | * Ease testing and better integration with r2ghidra 18 | * Improve patch maintainance workflows 19 | * Reduce repository size shipping only the native parts (512MB -> 15MB) 20 | * Update processor sleigh and decompiler logic separately 21 | * Add 3rd party processors easily 22 | -------------------------------------------------------------------------------- /src/Processors/ARM/data/languages/ARM.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 18 | 19 | -------------------------------------------------------------------------------- /src/Processors/HCS08/data/languages/HC08.pspec: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/lzcnt.sinc: -------------------------------------------------------------------------------- 1 | macro lzcntflags(input, output) { 2 | ZF = (output == 0); 3 | CF = (input == 0); 4 | # OF, SF, PF, AF are undefined 5 | } 6 | 7 | #### 8 | #### LZCNT instructions 9 | #### 10 | 11 | 12 | :LZCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg16 ... & rm16 { 13 | 14 | Reg16 = lzcount(rm16); 15 | lzcntflags(rm16, Reg16); 16 | } 17 | 18 | :LZCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg32 ... & check_Reg32_dest ... & rm32 { 19 | 20 | Reg32 = lzcount(rm32); 21 | lzcntflags(rm32, Reg32); 22 | build check_Reg32_dest; 23 | } 24 | 25 | @ifdef IA64 26 | :LZCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBD; Reg64 ... & rm64 { 27 | 28 | Reg64 = lzcount(rm64); 29 | lzcntflags(rm64, Reg64); 30 | } 31 | @endif 32 | 33 | -------------------------------------------------------------------------------- /src/Processors/M8C/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors M8C' 20 | -------------------------------------------------------------------------------- /src/Processors/8048/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | 20 | eclipse.project.name = 'Processors 8048' 21 | -------------------------------------------------------------------------------- /src/Processors/8085/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors 8085' 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/BPF/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors BPF' 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/CP1600/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors CP1600' 20 | -------------------------------------------------------------------------------- /src/Processors/tricore/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/build.xml||GHIDRA||||END| 5 | data/languages/tc172x.pspec||GHIDRA||||END| 6 | data/languages/tc176x.pspec||GHIDRA||||END| 7 | data/languages/tc29x.pspec||GHIDRA||||END| 8 | data/languages/tricore.cspec||GHIDRA||||END| 9 | data/languages/tricore.dwarf||GHIDRA||||END| 10 | data/languages/tricore.ldefs||GHIDRA||||END| 11 | data/languages/tricore.opinion||GHIDRA||||END| 12 | data/languages/tricore.pcp.sinc||GHIDRA||||END| 13 | data/languages/tricore.pspec||GHIDRA||||END| 14 | data/languages/tricore.sinc||GHIDRA||||END| 15 | data/languages/tricore.slaspec||GHIDRA||||END| 16 | data/manuals/tricore.idx||GHIDRA||||END| 17 | data/manuals/tricore2.idx||GHIDRA||||END| 18 | data/patterns/patternconstraints.xml||GHIDRA||||END| 19 | data/patterns/tricore_patterns.xml||GHIDRA||||END| 20 | -------------------------------------------------------------------------------- /src/Processors/6502/data/manuals/6502.idx: -------------------------------------------------------------------------------- 1 | @mcs6500_family_programming_manual.pdf [MCS 6500 Microcomputer Family Programming Manual, January 1976] 2 | ADC, 205 3 | AND, 205 4 | ASL, 206 5 | BCC, 206 6 | BCS, 207 7 | BEQ, 207 8 | BIT, 208 9 | BMI, 208 10 | BNE, 209 11 | BPL, 209 12 | BRK, 210 13 | BVC, 210 14 | BVS, 211 15 | CLC, 211 16 | CLD, 212 17 | CLI, 212 18 | CLV, 213 19 | CMP, 213 20 | CPX, 214 21 | CPY, 214 22 | DEC, 215 23 | DEX, 215 24 | DEY, 216 25 | EOR, 216 26 | INC, 217 27 | INX, 217 28 | INY, 218 29 | JMP, 218 30 | JSR, 219 31 | LDA, 219 32 | LDX, 220 33 | LDY, 220 34 | LSR, 221 35 | NOP, 221 36 | ORA, 222 37 | PHA, 222 38 | PHP, 223 39 | PLA, 223 40 | PLP, 224 41 | ROL, 224 42 | ROR, 225 43 | RTI, 225 44 | RTS, 225 45 | SBC, 226 46 | SEC, 226 47 | SED, 227 48 | SEI, 227 49 | STA, 228 50 | STX, 228 51 | STY, 229 52 | TAX, 229 53 | TAY, 230 54 | TSX, 231 55 | TXA, 231 56 | TXS, 231 57 | TYA, 230 58 | -------------------------------------------------------------------------------- /src/Processors/JVM/resources/InvokeDynamicTest.java: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | import java.util.List; 17 | 18 | class InvokeDynamicTest{ 19 | 20 | void printList(List list){ 21 | list.stream().forEach(x -> System.out.println(x)); 22 | return; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /src/Processors/MC6800/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | 20 | eclipse.project.name = 'Processors MC6800' 21 | 22 | -------------------------------------------------------------------------------- /src/Processors/SuperH/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | 20 | eclipse.project.name = 'Processors SuperH' 21 | 22 | -------------------------------------------------------------------------------- /src/Processors/6502/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | 20 | eclipse.project.name = 'Processors 6502' 21 | 22 | 23 | -------------------------------------------------------------------------------- /patches/0044-bad-unicode-codepoint.patch: -------------------------------------------------------------------------------- 1 | diff --git a/src/decompiler/stringmanage.cc b/src/decompiler/stringmanage.cc 2 | index 6e60b4f..fb7e2eb 100644 3 | --- a/src/decompiler/stringmanage.cc 4 | +++ b/src/decompiler/stringmanage.cc 5 | @@ -40,14 +40,14 @@ void StringManager::writeUtf8(ostream &s,int4 codepoint) 6 | int4 size; 7 | 8 | if (codepoint < 0) 9 | - throw LowlevelError("Negative unicode codepoint"); 10 | + return; // throw LowlevelError("Negative unicode codepoint"); 11 | if (codepoint < 128) { 12 | s.put((uint1)codepoint); 13 | return; 14 | } 15 | int4 bits = mostsigbit_set(codepoint) + 1; 16 | if (bits > 21) 17 | - throw LowlevelError("Bad unicode codepoint"); 18 | + return; // throw LowlevelError("Bad unicode codepoint"); 19 | if (bits < 12) { // Encode with two bytes 20 | bytes[0] = 0xc0 ^ ((codepoint >> 6)&0x1f); 21 | bytes[1] = 0x80 ^ (codepoint & 0x3f); 22 | -------------------------------------------------------------------------------- /src/Processors/CR16/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors CR16' 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /src/Processors/Xtensa/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/languages/cust.sinc||GHIDRA||||END| 5 | data/languages/flix.sinc||GHIDRA||||END| 6 | data/languages/xtensa.cspec||GHIDRA||||END| 7 | data/languages/xtensa.dwarf||GHIDRA||||END| 8 | data/languages/xtensa.ldefs||GHIDRA||||END| 9 | data/languages/xtensa.opinion||GHIDRA||||END| 10 | data/languages/xtensa.pspec||GHIDRA||||END| 11 | data/languages/xtensaArch.sinc||GHIDRA||||END| 12 | data/languages/xtensaInstructions.sinc||GHIDRA||||END| 13 | data/languages/xtensaMain.sinc||GHIDRA||||END| 14 | data/languages/xtensa_be.slaspec||GHIDRA||||END| 15 | data/languages/xtensa_depbits.sinc||GHIDRA||||END| 16 | data/languages/xtensa_le.slaspec||GHIDRA||||END| 17 | data/manuals/xtensa.idx||GHIDRA||||END| 18 | data/patterns/patternconstraints.xml||GHIDRA||||END| 19 | data/patterns/xtensa_patterns.xml||GHIDRA||||END| 20 | -------------------------------------------------------------------------------- /src/Processors/JVM/resources/Throw.java: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | class Throw{ 17 | 18 | public int throwIfNull(Object o, int x, int y){ 19 | int a = 0; 20 | int b = 1; 21 | if (o == null){ 22 | throw new NullPointerException(); 23 | } 24 | return a+b+x+y; 25 | } 26 | } 27 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/manuals/PIC-16F.idx: -------------------------------------------------------------------------------- 1 | @PIC16F_40001761E.pdf [Microchip PIC16LF1554/1559 (DS40001761E)] 2 | ADDFSR , 273 3 | ADDLW , 273 4 | ADDWF , 273 5 | ADDWFC , 273 6 | ANDLW , 273 7 | ANDWF , 273 8 | ASRF , 273 9 | BCF , 274 10 | BRA , 274 11 | BRW , 274 12 | BSF , 274 13 | BTFSC , 274 14 | BTFSS , 274 15 | CALL , 275 16 | CALLW , 275 17 | CLRF , 275 18 | CLRW , 275 19 | CLRWDT , 275 20 | COMF , 275 21 | DECF , 275 22 | DECFSZ , 276 23 | GOTO , 276 24 | INCF , 276 25 | INCFSZ , 276 26 | IORLW , 276 27 | IORWF , 276 28 | LSLF , 277 29 | LSRF , 277 30 | MOVF , 277 31 | MOVIW , 278 32 | MOVLB , 278 33 | MOVLP , 278 34 | MOVLW , 278 35 | MOVWF , 278 36 | MOVWI , 279 37 | NOP , 279 38 | OPTION , 279 39 | RESET , 279 40 | RETFIE , 280 41 | RETLW , 280 42 | RETURN , 280 43 | RLF , 280 44 | RRF , 281 45 | SLEEP , 281 46 | SUBLW , 281 47 | SUBWF , 281 48 | SUBWFB , 281 49 | SWAPF , 282 50 | TRIS , 282 51 | XORLW , 282 52 | XORWF , 282 53 | -------------------------------------------------------------------------------- /src/Processors/Z80/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors Z80' 20 | 21 | sleighCompileOptions = [ 22 | '-l' 23 | ] 24 | -------------------------------------------------------------------------------- /src/Processors/HCS08/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors HCS08' 20 | 21 | sleighCompileOptions = [ 22 | '-l' 23 | ] 24 | -------------------------------------------------------------------------------- /src/Processors/M16C/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors M16C' 20 | 21 | sleighCompileOptions = [ 22 | '-l' 23 | ] 24 | -------------------------------------------------------------------------------- /src/Processors/MCS96/build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | eclipse.project.name = 'Processors MCS96' 20 | 21 | sleighCompileOptions = [ 22 | '-l' 23 | ] 24 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/pic16c5x.slaspec: -------------------------------------------------------------------------------- 1 | @define PROCESSOR "PIC_12C5XX" 2 | 3 | @include "pic12.sinc" 4 | 5 | # 6 | # NOTES - 7 | # 1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and 8 | # slightly modified to specify a the correct Register File Map. 9 | # 10 | 11 | # Bank-0 File Registers 12 | define DATA offset=0x00 size=1 [ 13 | INDF TMR0 PCL.0 STATUS.0 FSR.0 PORTA PORTB PORTC 14 | ]; 15 | 16 | @include "pic12_instructions.sinc" 17 | 18 | # IO Tristate Registers 19 | define register offset=0x0020 size=1 [ TRISA TRISB TRISC ]; 20 | 21 | # TRIS register 22 | trisREG: "5" is f5=0x5 { export TRISA; } 23 | trisREG: "6" is f5=0x6 { export TRISB; } 24 | trisREG: "7" is f5=0x7 { export TRISC; } 25 | 26 | :TRIS trisREG is op6=0x00 & d=0 & trisREG { 27 | # ---- 0000 0000 0fff 28 | # 0000 0000 0000 0110 -> TRIS 6 29 | trisREG = W; 30 | } 31 | -------------------------------------------------------------------------------- /src/Processors/RISCV/data/languages/riscv.rv64q.sinc: -------------------------------------------------------------------------------- 1 | # RV64Q Standard Extension (in addition to RV32Q) 2 | 3 | # fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0) 4 | :fcvt.l.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2 5 | { 6 | rd = trunc(frs1); 7 | } 8 | 9 | 10 | # fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0) 11 | :fcvt.lu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3 12 | { 13 | rd = trunc(frs1); 14 | } 15 | 16 | 17 | # fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0) 18 | :fcvt.q.l frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2 19 | { 20 | frd = int2float(rs1); 21 | } 22 | 23 | 24 | # fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0) 25 | :fcvt.q.lu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3 26 | { 27 | frd = int2float(rs1); 28 | } 29 | -------------------------------------------------------------------------------- /src/Processors/SuperH4/certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | README.md||GHIDRA||||END| 4 | data/build.xml||GHIDRA||||END| 5 | data/languages/SuperH4.ldefs||GHIDRA||||END| 6 | data/languages/SuperH4.opinion||GHIDRA||||END| 7 | data/languages/SuperH4.pspec||GHIDRA||||END| 8 | data/languages/SuperH4.sinc||GHIDRA||||END| 9 | data/languages/SuperH4_be.cspec||GHIDRA||||END| 10 | data/languages/SuperH4_be.slaspec||GHIDRA||||END| 11 | data/languages/SuperH4_le.cspec||GHIDRA||||END| 12 | data/languages/SuperH4_le.slaspec||GHIDRA||||END| 13 | data/languages/old/SuperH4-BE-16.lang||GHIDRA||||END| 14 | data/languages/old/SuperH4-BE-16.trans||GHIDRA||||END| 15 | data/languages/old/SuperH4-LE-16.lang||GHIDRA||||END| 16 | data/languages/old/SuperH4-LE-16.trans||GHIDRA||||END| 17 | data/manuals/superh4.idx||GHIDRA||||END| 18 | data/patterns/SuperH4_patterns.xml||GHIDRA||||END| 19 | data/patterns/patternconstraints.xml||GHIDRA||||END| 20 | -------------------------------------------------------------------------------- /src/Processors/8048/data/languages/8048.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/aarch64-pltThunks.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | ...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 8 10 | 0x11 ......10 01...... 0xf9 # ldr x17, [x16, PLTGOT + n * 8] 11 | 0x10 ......10 00...... 0x91 # add x16, x16, :lo12:PLTGOT + n * 8 12 | 0x20 0x02 0x1f 0xd6 # br x17 13 | 14 | 15 | 16 | 17 | ...10000 0x.. 0x.. 1..10000 # adrp x16, PLTGOT + n * 4 18 | 0x11 ......10 01...... 0xb9 # ldr x17, [x16, PLTGOT + n * 4] 19 | 0x10 ......10 00...... 0x11 # add x16, x16, :lo12:PLTGOT + n * 4 20 | 0x20 0x02 0x1f 0xd6 # br x17 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/PIC24.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/Processors/AARCH64/data/languages/AARCH64_golang.register.info: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /src/Processors/STM8/data/languages/STM8.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | STM8 (large memory model) 13 | 14 | 15 | 23 | STM8 (medium memory model) 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /src/Processors/x86/data/patterns/x86win_prepatterns.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 0x8bff 6 | 0x55 7 | 0x8bec 8 | 0x83ec20 9 | 0x8b4508 10 | 0x56 11 | 0x57 12 | 0x6a08 13 | 0x59 14 | 0xbe........ 15 | 0x8d7de0 16 | 0xf3a5 17 | 0x8945f8 18 | 0x8b450c 19 | 0x5f 20 | 0x8945fc 21 | 0x5e 22 | 0x85c0 23 | 0x740c 24 | 0xf60008 25 | 0x7407 26 | 0xc745f4........ 27 | 0x8d45f4 28 | 0x50 29 | 0xff75f0 30 | 0xff75e4 31 | 0xff75e0 32 | 0xff15........ 33 | 0xc9 34 | 0xc20800 35 | 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /src/Processors/MCS96/data/languages/MCS96.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /src/Processors/JVM/resources/MonitorTest.java: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | class MonitorTest{ 17 | 18 | public synchronized int getHashCode(Object o){ 19 | return o.hashCode(); 20 | } 21 | 22 | public int getHashCode2(Object o){ 23 | int x = 0; 24 | synchronized (o){ 25 | x = o.hashCode(); 26 | } 27 | return x; 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /src/Processors/PIC/data/languages/PIC33.dwarf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /src/Processors/x86/data/languages/x86-64-golang.register.info: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | --------------------------------------------------------------------------------