├── disassembler ├── arm64dis.h ├── decode_fields32.h ├── encodings_fmt.h ├── Makefile-asan ├── gofer.c ├── decode.c ├── Makefile-local ├── format.h ├── .gitignore ├── test.c ├── disasm_test.py ├── feature_flags.h ├── pcode.h ├── regs.c ├── decode.h ├── sysregs.h ├── format.c ├── pcode.c ├── decode1.h └── regs.h ├── .gitignore ├── README.md ├── LICENSE ├── meson.build ├── test_disasm.py ├── il_macros.h ├── misc ├── mte.txt └── neon_intrins.py ├── CMakeLists.txt ├── il.h └── test_gen.py /disassembler/arm64dis.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include "decode.h" 4 | #include "format.h" 5 | -------------------------------------------------------------------------------- /disassembler/decode_fields32.h: -------------------------------------------------------------------------------- 1 | /* GENERATED FILE */ 2 | #pragma once 3 | void decode_fields32(enum ENCODING enc, context *ctx, Instruction *dec); 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__ 2 | CMakeFiles 3 | CMakeCache.txt 4 | cmake_install.cmake 5 | Makefile 6 | api 7 | build 8 | libarch_* 9 | arch_*.dll 10 | __pycache__ 11 | -------------------------------------------------------------------------------- /disassembler/encodings_fmt.h: -------------------------------------------------------------------------------- 1 | /* GENERATED FILE */ 2 | #pragma once 3 | #include "encodings_dec.h" 4 | const char *enc_to_str(enum ENCODING); 5 | const char *enc_to_xml(enum ENCODING); 6 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # This module has moved 2 | 3 | This module has been moved to the [Binary Ninja API](https://github.com/Vector35/binaryninja-api/tree/dev/arch/arm64) repository. Please file issues and pull requests there. 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright 2020-2024 Vector 35 Inc. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | -------------------------------------------------------------------------------- /disassembler/Makefile-asan: -------------------------------------------------------------------------------- 1 | DECODE_OBJS = pcode.o decode.o decode0.o decode1.o decode2.o decode_fields32.o decode_scratchpad.o encodings_dec.o 2 | 3 | FORMAT_OBJS = format.o encodings_fmt.o operations.o sysregs.o regs.o 4 | 5 | HEADERS = decode.h decode1.h decode2.h format.h pcode.h operations.h sysregs.h decode_fields32.h encodings_dec.h encodings_fmt.h regs.h 6 | 7 | CFLAGS = -O2 -fsanitize=address -ggdb 8 | 9 | .PHONY: all clean 10 | 11 | all: test 12 | 13 | %.o: %.c %.h 14 | gcc -c $(CFLAGS) $< -o $@ 15 | 16 | test: test.c $(DECODE_OBJS) $(FORMAT_OBJS) 17 | gcc $(CFLAGS) test.c *.o -o test 18 | 19 | clean: 20 | rm -f *.o *.so *.a test 21 | rm -rf gofer.so.dSYM test.dSYM 22 | -------------------------------------------------------------------------------- /disassembler/gofer.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | #include "decode.h" 8 | #include "format.h" 9 | 10 | void disassemble(uint64_t addr, uint8_t *data, int len, char *result, bool verbose) 11 | { 12 | Instruction instr; 13 | memset(&instr, 0, sizeof(instr)); 14 | 15 | aarch64_decompose(*(uint32_t *)data, &instr, addr); 16 | 17 | aarch64_disassemble(&instr, result, 1024); 18 | } 19 | 20 | uint32_t get_encoding(uint8_t *data) 21 | { 22 | Instruction instr; 23 | //printf("sizeof(instr): %lu\n", sizeof(instr)); 24 | //printf("sizeof(instr.encoding): %lu\n", sizeof(instr.encoding)); 25 | memset(&instr, 0, sizeof(instr)); 26 | aarch64_decompose(*(uint32_t *)data, &instr, 0); 27 | return instr.encoding; 28 | } 29 | -------------------------------------------------------------------------------- /meson.build: -------------------------------------------------------------------------------- 1 | project('v35arm64', 'c', meson_version : '>=0.60.0', version : '2.0.2') 2 | 3 | sources = [ 4 | 'disassembler/decode.c', 5 | 'disassembler/decode0.c', 6 | 'disassembler/decode1.c', 7 | 'disassembler/decode2.c', 8 | 'disassembler/decode_fields32.c', 9 | 'disassembler/decode_scratchpad.c', 10 | 'disassembler/encodings_dec.c', 11 | 'disassembler/encodings_fmt.c', 12 | 'disassembler/format.c', 13 | 'disassembler/gofer.c', 14 | 'disassembler/operations.c', 15 | 'disassembler/pcode.c', 16 | 'disassembler/regs.c', 17 | 'disassembler/sysregs.c' 18 | ] 19 | 20 | incs = include_directories(['disassembler']) 21 | libs = both_libraries('v35arm64', sources) 22 | 23 | v35arm64_dep = declare_dependency( 24 | link_with: [libs.get_static_lib()], 25 | include_directories: incs 26 | ) 27 | -------------------------------------------------------------------------------- /disassembler/decode.c: -------------------------------------------------------------------------------- 1 | #include "decode.h" 2 | #include "feature_flags.h" 3 | 4 | int decode_spec(context* ctx, Instruction* dec); // from decode0.cpp 5 | int decode_scratchpad(context* ctx, Instruction* dec); // from decode_scratchpad.c 6 | 7 | int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t address) 8 | { 9 | context ctx = {0}; 10 | ctx.halted = 1; // enable disassembly of exception instructions like DCPS1 11 | ctx.insword = instructionValue; 12 | ctx.address = address; 13 | ctx.features0 = ARCH_FEATURES_ALL; 14 | ctx.features1 = ARCH_FEATURES_ALL; 15 | ctx.EDSCR_HDE = 1; 16 | 17 | /* have the spec-generated code populate all the pcode variables */ 18 | int rc = decode_spec(&ctx, instr); 19 | 20 | if (rc != DECODE_STATUS_OK) 21 | { 22 | /* exceptional cases where we accept a non-OK decode status */ 23 | if (rc == DECODE_STATUS_END_OF_INSTRUCTION && instr->encoding == ENC_HINT_HM_HINTS) 24 | { 25 | while (0) 26 | ; 27 | } 28 | /* no exception! fail! */ 29 | else 30 | return rc; 31 | } 32 | 33 | /* if UDF encoding, return undefined */ 34 | // if(instr->encoding == ENC_UDF_ONLY_PERM_UNDEF) 35 | // return DECODE_STATUS_UNDEFINED; 36 | 37 | /* convert the pcode variables to list of operands, etc. */ 38 | return decode_scratchpad(&ctx, instr); 39 | } 40 | -------------------------------------------------------------------------------- /disassembler/Makefile-local: -------------------------------------------------------------------------------- 1 | # $ make -f Makefile-local 2 | 3 | DECODE_OBJS = pcode.o decode.o decode0.o decode1.o decode2.o decode_fields32.o decode_scratchpad.o encodings_dec.o 4 | 5 | FORMAT_OBJS = format.o encodings_fmt.o operations.o sysregs.o regs.o 6 | 7 | HEADERS = decode.h decode1.h decode2.h format.h pcode.h operations.h sysregs.h decode_fields32.h encodings_dec.h encodings_fmt.h regs.h 8 | 9 | #CFLAGS = -g -Wunused 10 | CFLAGS = -Os 11 | #CFLAGS = -g -Wpedantic 12 | #CFLAGS = -ofast 13 | 14 | #$(info $(GENERATED_OBJECTS)) 15 | 16 | .PHONY: all clean 17 | 18 | all: libdecode.a libformat.a gofer.so test 19 | 20 | %.o: %.c $(HEADERS) 21 | gcc -c $(CFLAGS) $< -o $@ 22 | 23 | libdecode.a: $(DECODE_OBJS) 24 | ar rvs libdecode.a $(DECODE_OBJS) 25 | 26 | libformat.a: $(FORMAT_OBJS) 27 | ar rvs libformat.a $(FORMAT_OBJS) 28 | 29 | #------------------------------------------------------------------------------ 30 | # test tools 31 | #------------------------------------------------------------------------------ 32 | 33 | gofer.so: gofer.c libdecode.a 34 | gcc $(CFLAGS) \ 35 | libdecode.a libformat.a \ 36 | -shared -o gofer.so gofer.c \ 37 | -Wl,-headerpad_max_install_names 38 | #install_name_tool -change libcapstone.3.dylib gofer.so 39 | #install_name_tool -add_rpath `pwd` gofer.so 40 | 41 | test: test.c libdecode.a 42 | gcc $(CFLAGS) test.c libdecode.a libformat.a -o test 43 | 44 | #------------------------------------------------------------------------------ 45 | # 46 | #------------------------------------------------------------------------------ 47 | clean: 48 | rm -f *.o *.so *.a test 49 | rm -rf gofer.so.dSYM test.dSYM 50 | 51 | -------------------------------------------------------------------------------- /disassembler/format.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | 6 | #include "decode.h" 7 | #include "encodings_dec.h" 8 | #include "encodings_fmt.h" 9 | #include "operations.h" 10 | #include "regs.h" 11 | #include "sysregs.h" 12 | 13 | //----------------------------------------------------------------------------- 14 | // disassembly function prototypes, return values 15 | //----------------------------------------------------------------------------- 16 | 17 | /* these get returned by the disassemble_instruction() function */ 18 | enum FailureCode { 19 | DISASM_SUCCESS=0, 20 | INVALID_ARGUMENTS, 21 | FAILED_TO_DISASSEMBLE_OPERAND, 22 | FAILED_TO_DISASSEMBLE_OPERATION, 23 | FAILED_TO_DISASSEMBLE_REGISTER, 24 | FAILED_TO_DECODE_INSTRUCTION, 25 | OUTPUT_BUFFER_TOO_SMALL, 26 | OPERAND_IS_NOT_REGISTER, 27 | NOT_MEMORY_OPERAND 28 | }; 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | // get a text representation of the decomposed instruction 35 | int aarch64_disassemble(Instruction *instruction, char *buf, size_t buf_sz); 36 | 37 | // register (and related) to string 38 | int get_register_full(enum Register, const InstructionOperand *, char *result); 39 | const char *get_register_arrspec(enum Register, const InstructionOperand *); 40 | 41 | // miscellany to string 42 | const char *get_operation(const Instruction *instruction); 43 | const char *get_shift(ShiftType shift); 44 | const char *get_condition(Condition cond); 45 | uint32_t get_implementation_specific( 46 | const InstructionOperand *operand, 47 | char *outBuffer, 48 | uint32_t outBufferSize); 49 | const char *get_arrspec_str(ArrangementSpec arrspec); 50 | const char *get_arrspec_str_truncated(ArrangementSpec arrspec); 51 | 52 | #ifdef __cplusplus 53 | } 54 | #endif 55 | 56 | 57 | -------------------------------------------------------------------------------- /test_disasm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # this tests disassembly through the binja API, ensuring binja <- arch <- disassembler 4 | # 5 | # that's an important distinction versus testing just the disassembler 6 | 7 | import re, struct, os, sys, ctypes 8 | 9 | import binaryninja 10 | print("binaryninja.__file__:", binaryninja.__file__) 11 | 12 | sys.path.append('./disassembler') 13 | import disasm_test 14 | 15 | 16 | arch = None 17 | def disassemble(addr, insnum): 18 | global arch 19 | if not arch: 20 | arch = binaryninja.Architecture['aarch64'] 21 | data = struct.pack('= REG_W0 && (R) <= REG_W31) 15 | #define IS_X_REG(R) ((R) >= REG_X0 && (R) <= REG_X31) 16 | #define IS_V_REG(R) ((R) >= REG_V0 && (R) <= REG_V31) 17 | #define IS_Z_REG(R) ((R) >= REG_Z0 && (R) <= REG_Z31) 18 | #define IS_P_REG(R) ((R) >= REG_P0 && (R) <= REG_P15) 19 | #define IS_ZERO_REG(R) ((R) == REG_XZR || (R) == REG_WZR) 20 | #define IS_SVE_REG(R) (IS_Z_REG(R) || IS_P_REG(R)) 21 | 22 | /* access stuff from operands */ 23 | #define IMM_O(O) (O).immediate 24 | #define REG_O(O) (O).reg[0] 25 | #define REGSZ_O(O) get_register_size(REG_O(O)) /* units: BYTES */ 26 | 27 | /* construct IL from an InstructionOperand */ 28 | #define ILREG_O(O) ExtractRegister(il, O, 0, REGSZ_O(O), false, REGSZ_O(O)) 29 | #define ILSETREG_O(O, VALUE) IS_ZERO_REG(REG_O(O)) ? (VALUE) : il.SetRegister(REGSZ_O(O), REG_O(O), (VALUE)) 30 | #define ILADDREG_O(O, VALUE) il.Add(REGSZ_O(O), ILREG_O(O), (VALUE)) 31 | #define ILCONST_O(SZ, O) ExtractImmediate(il, (O), SZ) 32 | 33 | /* determine stuff from operands */ 34 | #define IS_ASIMD_O(O) ((O).operandClass == REG && IS_V_REG(REG_O(O))) 35 | #define IS_SVE_O(O) ((O).operandClass == REG && IS_SVE_REG(REG_O(O))) 36 | 37 | /* misc */ 38 | #define SETFLAGS (GetFlagWriteTypeForEffect(instr.setflags)) 39 | #define ONES(N) (-1ULL >> (64 - (N))) 40 | #define ABORT_LIFT \ 41 | { \ 42 | il.AddInstruction(il.Unimplemented()); \ 43 | break; \ 44 | } 45 | -------------------------------------------------------------------------------- /disassembler/.gitignore: -------------------------------------------------------------------------------- 1 | # Created by https://www.gitignore.io 2 | 3 | ### Python ### 4 | # Byte-compiled / optimized / DLL files 5 | __pycache__/ 6 | *.py[cod] 7 | 8 | # C extensions 9 | *.so 10 | 11 | # Distribution / packaging 12 | .Python 13 | env/ 14 | build/ 15 | develop-eggs/ 16 | dist/ 17 | downloads/ 18 | eggs/ 19 | .eggs/ 20 | lib/ 21 | lib64/ 22 | parts/ 23 | sdist/ 24 | var/ 25 | *.egg-info/ 26 | .installed.cfg 27 | *.egg 28 | 29 | # PyInstaller 30 | # Usually these files are written by a python script from a template 31 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 32 | *.manifest 33 | *.spec 34 | 35 | # Installer logs 36 | pip-log.txt 37 | pip-delete-this-directory.txt 38 | 39 | # Unit test / coverage reports 40 | htmlcov/ 41 | .tox/ 42 | .coverage 43 | .coverage.* 44 | .cache 45 | nosetests.xml 46 | coverage.xml 47 | *,cover 48 | 49 | # Translations 50 | *.mo 51 | *.pot 52 | 53 | # Django stuff: 54 | *.log 55 | 56 | # Sphinx documentation 57 | docs/_build/ 58 | 59 | # PyBuilder 60 | target/ 61 | 62 | 63 | ### Linux ### 64 | *~ 65 | 66 | # KDE directory preferences 67 | .directory 68 | 69 | # Linux trash folder which might appear on any partition or disk 70 | .Trash-* 71 | 72 | 73 | ### OSX ### 74 | .DS_Store 75 | .AppleDouble 76 | .LSOverride 77 | 78 | # Icon must end with two \r 79 | Icon 80 | 81 | 82 | # Thumbnails 83 | ._* 84 | 85 | # Files that might appear in the root of a volume 86 | .DocumentRevisions-V100 87 | .fseventsd 88 | .Spotlight-V100 89 | .TemporaryItems 90 | .Trashes 91 | .VolumeIcon.icns 92 | 93 | # Directories potentially created on remote AFP share 94 | .AppleDB 95 | .AppleDesktop 96 | Network Trash Folder 97 | Temporary Items 98 | .apdisk 99 | 100 | 101 | ### C ### 102 | # Object files 103 | *.o 104 | *.ko 105 | *.obj 106 | *.elf 107 | 108 | # Precompiled Headers 109 | *.gch 110 | *.pch 111 | 112 | # Libraries 113 | *.lib 114 | *.a 115 | *.la 116 | *.lo 117 | 118 | # Shared objects (inc. Windows DLLs) 119 | *.dll 120 | *.so 121 | *.so.* 122 | *.dylib 123 | 124 | # Executables 125 | *.exe 126 | *.out 127 | *.app 128 | *.i*86 129 | *.x86_64 130 | *.hex 131 | 132 | # Debug files 133 | *.dSYM/ 134 | 135 | -------------------------------------------------------------------------------- /misc/mte.txt: -------------------------------------------------------------------------------- 1 | Memory Tagging Extension (MTE) 2 | - related instructions findable by searching spec for pcode HaveMTEExt() calls, or arch feature ARMv8.5-MemTag 3 | - incomplete list here: https://en.wikichip.org/wiki/arm/mte 4 | 5 | ADDG Add with Tag ADDG_64_addsub_immtags ADDG , , #, # 6 | CMPP Compare with Tag CMPP_SUBPS_64S_dp_2src CMPP , 7 | GMI Tag Mask Insert GMI_64G_dp_2src GMI , , 8 | IRG Insert Random Tag IRG_64I_dp_2src IRG , {, } 9 | LDG Load Allocation Tag LDG_64Loffset_ldsttags LDG , [{, #}] 10 | LDGV Load Tag Vector ??? LDGV , []! 11 | LDGM Load Tag Multiple LDGM_64bulk_ldsttags LDGM , [] 12 | ST2G Store Allocaton Tags ST2G_64Spost_ldsttags ST2G [], # 13 | ST2G_64Spre_ldsttags ST2G [, #]! 14 | ST2G_64Soffset_ldsttags ST2G , [{, #}] 15 | STG Store Allocation Tag STG_64Spost_ldsttags STG [], # 16 | STG_64Spre_ldsttags STG [, #]! 17 | STG_64Soffset_ldsttags STG [{, #}] 18 | STGM Store Tag Multiple STGM_64bulk_ldsttags STGM , [] 19 | STGP Store Allocation Tag and Pair STGP_64_ldstpair_post STGP , , [], # 20 | STGP_64_ldstpair_pre STGP , , [, #]! 21 | STGP_64_ldstpair_off STGP , , [{, #}] 22 | STGV Store Tag Vector ??? STGV , []! 23 | STZ2G Store Allocation Tags, Zeroing STZ2G_64Spost_ldsttags STZ2G [], # 24 | STZ2G_64Spre_ldsttags STZ2G [, #]! 25 | STZ2G_64Soffset_ldsttags STZ2G [{, #}] 26 | STZG Store Allocation Tag, Zeroing STZG_64Spost_ldsttags STZG [], # 27 | STZG_64Spre_ldsttags STZG [, #]! 28 | STZG_64Soffset_ldsttags STZG [{, #}] 29 | STZGM Store Tag and Zero Multiple STZGM_64bulk_ldsttags STZGM , [] 30 | SUBG Subtract with Tag SUBG_64_addsub_immtags SUBG , , #, # 31 | SUBP Subtract Pointer SUBP_64S_dp_2src SUBP , , 32 | SUBPS Subtract Pointer, setting Flags SUBPS_64S_dp_2src SUBPS , , 33 | 34 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.9 FATAL_ERROR) 2 | 3 | project(arch_arm64 CXX C) 4 | 5 | file(GLOB SOURCES 6 | *.cpp 7 | *.c 8 | *.h 9 | disassembler/decode.c 10 | disassembler/format.c 11 | disassembler/sysregs.c 12 | disassembler/regs.c 13 | disassembler/encodings_dec.c 14 | disassembler/encodings_fmt.c 15 | disassembler/operations.c 16 | disassembler/pcode.c 17 | disassembler/decode0.c 18 | disassembler/decode1.c 19 | disassembler/decode2.c 20 | disassembler/decode_fields32.c 21 | disassembler/decode_scratchpad.c 22 | disassembler/*.h) 23 | 24 | if(DEMO) 25 | add_library(${PROJECT_NAME} STATIC ${SOURCES}) 26 | else() 27 | add_library(${PROJECT_NAME} SHARED ${SOURCES}) 28 | endif() 29 | 30 | 31 | if(NOT WIN32) 32 | set_source_files_properties(disassembler/arm64dis.c PROPERTIES COMPILE_FLAGS -fno-strict-aliasing) 33 | endif() 34 | 35 | target_include_directories(${PROJECT_NAME} 36 | PRIVATE ${PROJECT_SOURCE_DIR} 37 | PRIVATE ${PROJECT_SOURCE_DIR}/disassembler) 38 | 39 | if((NOT BN_API_BUILD_EXAMPLES) AND (NOT BN_INTERNAL_BUILD)) 40 | # Out-of-tree build 41 | find_path( 42 | BN_API_PATH 43 | NAMES binaryninjaapi.h 44 | HINTS . .. ../.. binaryninjaapi $ENV{BN_API_PATH} 45 | PATH_SUFFIXES binaryninja-api 46 | REQUIRED 47 | ) 48 | message(STATUS "Found Binary Ninja API Path: ${BN_API_PATH}") 49 | add_subdirectory(${BN_API_PATH} api) 50 | target_link_libraries(${PROJECT_NAME} binaryninjaapi) 51 | else() 52 | if(WIN32) 53 | target_link_directories(${PROJECT_NAME} 54 | PRIVATE ${BN_INSTALL_DIR}) 55 | target_link_libraries(${PROJECT_NAME} binaryninjaapi binaryninjacore) 56 | else() 57 | target_link_libraries(${PROJECT_NAME} binaryninjaapi) 58 | endif() 59 | endif() 60 | 61 | IF(DEFINED ENV{ARM64_WARNINGS}) 62 | MESSAGE(STATUS "ARM64 WARNINGS ON") 63 | target_compile_options(${PROJECT_NAME} PRIVATE -Wall) 64 | ELSE() 65 | MESSAGE(STATUS "ARM64 WARNINGS OFF") 66 | ENDIF() 67 | 68 | set_target_properties(${PROJECT_NAME} PROPERTIES 69 | CXX_STANDARD 17 70 | CXX_VISIBILITY_PRESET hidden 71 | CXX_STANDARD_REQUIRED ON 72 | C_STANDARD 99 73 | C_STANDARD_REQUIRED ON 74 | C_VISIBILITY_PRESET hidden 75 | VISIBILITY_INLINES_HIDDEN ON 76 | POSITION_INDEPENDENT_CODE ON) 77 | 78 | if(BN_INTERNAL_BUILD) 79 | plugin_rpath(${PROJECT_NAME}) 80 | set_target_properties(${PROJECT_NAME} PROPERTIES 81 | LIBRARY_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR} 82 | RUNTIME_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR}) 83 | else() 84 | bn_install_plugin(${PROJECT_NAME}) 85 | endif() 86 | -------------------------------------------------------------------------------- /il.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include "binaryninjaapi.h" 4 | #include "disassembler/arm64dis.h" 5 | #include "disassembler/encodings_dec.h" 6 | #include "disassembler/encodings_fmt.h" 7 | #include "disassembler/operations.h" 8 | 9 | /* Do we lift pointer authentication instructions as intrinsics? 10 | If no, the below define should be preceeded with "//" 11 | If yes, the below define should start with "#define" and intrinsics are used. 12 | This is read by il.cpp and arm64test.py */ 13 | //#define LIFT_PAC_AS_INTRINSIC 1 14 | 15 | #define IL_FLAG_N 31 16 | #define IL_FLAG_Z 30 17 | #define IL_FLAG_C 29 18 | #define IL_FLAG_V 28 19 | 20 | #define IL_FLAG_WRITE_NONE 0 21 | #define IL_FLAG_WRITE_ALL 1 22 | #define IL_FLAG_WRITE_ALL_FLOAT 2 23 | 24 | #define IL_FLAG_CLASS_INT 1 25 | #define IL_FLAG_CLASS_FLOAT 2 26 | 27 | #define IL_FLAG_GROUP_EQ 1 28 | #define IL_FLAG_GROUP_NE 2 29 | #define IL_FLAG_GROUP_CS 3 30 | #define IL_FLAG_GROUP_CC 4 31 | #define IL_FLAG_GROUP_MI 5 32 | #define IL_FLAG_GROUP_PL 6 33 | #define IL_FLAG_GROUP_VS 7 34 | #define IL_FLAG_GROUP_VC 8 35 | #define IL_FLAG_GROUP_HI 9 36 | #define IL_FLAG_GROUP_LS 10 37 | #define IL_FLAG_GROUP_GE 11 38 | #define IL_FLAG_GROUP_LT 12 39 | #define IL_FLAG_GROUP_GT 13 40 | #define IL_FLAG_GROUP_LE 14 41 | 42 | enum Arm64Intrinsic : uint32_t 43 | { 44 | ARM64_INTRIN_AUTDA, 45 | ARM64_INTRIN_AUTDB, 46 | ARM64_INTRIN_AUTIA, 47 | ARM64_INTRIN_AUTIB, 48 | ARM64_INTRIN_DC, 49 | ARM64_INTRIN_DMB, 50 | ARM64_INTRIN_DSB, 51 | ARM64_INTRIN_ESB, 52 | ARM64_INTRIN_HINT_BTI, 53 | ARM64_INTRIN_HINT_CSDB, 54 | ARM64_INTRIN_HINT_DGH, 55 | ARM64_INTRIN_HINT_TSB, 56 | ARM64_INTRIN_ISB, 57 | ARM64_INTRIN_MRS, 58 | ARM64_INTRIN_MSR, 59 | ARM64_INTRIN_PACDA, 60 | ARM64_INTRIN_PACDB, 61 | ARM64_INTRIN_PACGA, 62 | ARM64_INTRIN_PACIA, 63 | ARM64_INTRIN_PACIB, 64 | ARM64_INTRIN_PRFM, 65 | ARM64_INTRIN_PSBCSYNC, 66 | ARM64_INTRIN_SEV, 67 | ARM64_INTRIN_SEVL, 68 | ARM64_INTRIN_WFE, 69 | ARM64_INTRIN_WFI, 70 | ARM64_INTRIN_XPACD, 71 | ARM64_INTRIN_XPACI, 72 | ARM64_INTRIN_YIELD, 73 | ARM64_INTRIN_ERET, 74 | ARM64_INTRIN_CLZ, 75 | ARM64_INTRIN_CLREX, 76 | ARM64_INTRIN_REV, 77 | ARM64_INTRIN_RBIT, 78 | ARM64_INTRIN_AESD, 79 | ARM64_INTRIN_AESE, 80 | ARM64_INTRIN_LDXR, 81 | ARM64_INTRIN_LDXRB, 82 | ARM64_INTRIN_LDXRH, 83 | ARM64_INTRIN_LDAXR, 84 | ARM64_INTRIN_LDAXRB, 85 | ARM64_INTRIN_LDAXRH, 86 | ARM64_INTRIN_STXR, 87 | ARM64_INTRIN_STXRB, 88 | ARM64_INTRIN_STXRH, 89 | ARM64_INTRIN_STLXR, 90 | ARM64_INTRIN_STLXRB, 91 | ARM64_INTRIN_STLXRH, 92 | ARM64_INTRIN_NORMAL_END, /* needed so intrinsics can be extended by other lists, like neon 93 | intrinsics */ 94 | ARM64_INTRIN_INVALID = 0xFFFFFFFF, 95 | }; 96 | 97 | enum Arm64FakeRegister : uint32_t 98 | { 99 | FAKEREG_SYSREG_UNKNOWN = SYSREG_END + 1, 100 | FAKEREG_SYSCALL_INFO = SYSREG_END + 2 101 | }; 102 | 103 | bool GetLowLevelILForInstruction(BinaryNinja::Architecture* arch, uint64_t addr, 104 | BinaryNinja::LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool alignmentRequired); 105 | 106 | BinaryNinja::ExprId ExtractRegister(BinaryNinja::LowLevelILFunction& il, 107 | InstructionOperand& operand, size_t regNum, size_t extractSize, bool signExtend, 108 | size_t resultSize); 109 | -------------------------------------------------------------------------------- /test_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | # utility to generate tests 4 | 5 | import re, sys, codecs 6 | 7 | N_SAMPLES = 8 # number of samples for each encoding 8 | 9 | from arm64test import instr_to_il, il2str 10 | if not sys.argv[1:]: 11 | sys.exit(-1) 12 | 13 | arch = None 14 | def disassemble(addr, data): 15 | global arch 16 | if not arch: 17 | arch = binaryninja.Architecture['aarch64'] 18 | (tokens, length) = arch.get_instruction_text(data, addr) 19 | if not tokens or length==0: 20 | return None 21 | return disasm_test.normalize(''.join([x.text for x in tokens])) 22 | 23 | def print_case(data, comment=''): 24 | ilstr = instr_to_il(data) 25 | il_lines = ilstr.split(';') 26 | print("\t(b'%s', " % (''.join(['\\x%02X'%b for b in data])), end='') 27 | for (i,line) in enumerate(il_lines): 28 | if i!=0: 29 | print('\t\t\t\t\t\t ', end='') 30 | print('\'%s' % line, end='') 31 | if i!=len(il_lines)-1: 32 | print(';\' + \\') 33 | comment = ' # '+comment if comment else '' 34 | print('\'),%s' % comment) 35 | 36 | def gather_samples(mnems, encodings): 37 | encodings = [x.upper() for x in encodings] 38 | 39 | global N_SAMPLES 40 | fpath = './disassembler/test_cases.txt' 41 | with open(fpath) as fp: 42 | lines = fp.readlines() 43 | 44 | samples = 0 45 | current_encoding = None 46 | for line in lines: 47 | if line.startswith('// NOTE:'): continue 48 | if line.startswith('// SYNTAX:'): continue 49 | 50 | if re.match(r'^// .*? .*', line): 51 | m = re.match(r'^// (.*?) .*', line) 52 | 53 | # example: 54 | # // BFCVT_Z_P_Z_S2BF 01100101|opc=10|0010|opc2=10|101|Pg=xxx|Zn=xxxxx|Zd=xxxxx 55 | current_encoding = m.group(1) 56 | samples = 0 57 | continue 58 | 59 | m = re.match(r'^(..)(..)(..)(..) (.*)$', line) 60 | if m: 61 | # example: 62 | # 658AB9BB bfcvt z27.h, p6/m, z13.s 63 | if samples >= N_SAMPLES: 64 | continue 65 | (b0, b1, b2, b3, instxt) = m.group(1,2,3,4,5) 66 | data = codecs.decode(b3+b2+b1+b0, 'hex_codec') 67 | #if not (instxt==mnem or instxt.startswith(mnem+' ')): 68 | 69 | mnemonic_match = [x for x in mnems if instxt.startswith(x)] 70 | encoding_match = current_encoding.upper() in encodings 71 | if not (mnemonic_match or encoding_match): 72 | continue 73 | 74 | #if samples == 0: 75 | # print('\t# %s' % encoding) 76 | print('\t# %s %s' % (instxt.ljust(64), current_encoding)) 77 | print_case(data) 78 | 79 | samples += 1 80 | continue 81 | 82 | print('unable to parse line: %s' % line) 83 | sys.exit(-1) 84 | 85 | # generate lifting tests for a given mnemonic 86 | # example: 87 | # ./test_gen mnemonic ld1 88 | if sys.argv[1] == 'mnemonic': 89 | mnem = sys.argv[2] 90 | print('searching for mnemonic -%s-' % mnem) 91 | gather_samples([mnem], []) 92 | 93 | elif sys.argv[1] == 'encoding': 94 | encname = sys.argv[2] 95 | print('searching for encoding -%s-' % encname) 96 | gather_samples([], [encname]) 97 | 98 | elif sys.argv[1] == 'mte': 99 | mnems = ['addg', 'cmpp', 'gmi', 'irg', 'ldg', 'dgv', 'ldgm', 'st2g', 'stg', 100 | 'stgm', 'stgp', 'stgv', 'stz2g', 'stzg', 'stzgm', 'subg', 'subp', 101 | 'subps'] 102 | gather_samples(mnems, []) 103 | 104 | elif sys.argv[1] == 'recompute_arm64test': 105 | with open('arm64test.py') as fp: 106 | lines = [x.rstrip() for x in fp.readlines()] 107 | 108 | i = 0 109 | while i < len(lines): 110 | m = re.match(r'^\t\(b\'\\x(..)\\x(..)\\x(..)\\x(..)\'.*$', lines[i]) 111 | if not m: 112 | print(lines[i]) 113 | i += 1 114 | continue 115 | 116 | (b0, b1, b2, b3) = m.group(1,2,3,4) 117 | 118 | comment = None 119 | m = re.search(r'# (.*)$', lines[i]) 120 | if m: 121 | comment = m.group(1) 122 | 123 | data = codecs.decode(b0+b1+b2+b3, 'hex_codec') 124 | print_case(data, comment) 125 | 126 | i += 1 127 | while lines[i].startswith('\t\t\t\t\t\t'): 128 | i += 1 129 | 130 | 131 | 132 | 133 | -------------------------------------------------------------------------------- /misc/neon_intrins.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # read neon_intrins.c and generate code for the architecture 3 | 4 | import re 5 | import sys 6 | 7 | from collections import OrderedDict 8 | 9 | # SMMLA Vd.4S,Vn.16B,Vm.16B -> Vd.4S 10 | def get_destination_reg(asig): 11 | try: 12 | (mnem, regs) = re.match(r'^(\w+) (.*)', asig).group(1,2) 13 | except AttributeError: 14 | print('couldn\'t get destination register from -%s-' % asig) 15 | sys.exit(-1) 16 | return regs.split(',')[0] 17 | 18 | def get_reg_size(reg): 19 | if reg in ['Qd', 'Qt']: return 16 20 | if reg in ['Dd', 'Dm']: return 8 21 | if reg=='Sd': return 4 22 | if reg=='Hd': return 2 23 | if reg=='Bd': return 1 24 | 25 | if reg in ['Wd', 'Wn', 'Wm']: return 4 26 | 27 | reg = reg.lower() 28 | if '.1q' in reg: return 16 29 | if '.2d' in reg: return 16 30 | if '.4s' in reg: return 16 31 | if '.8h' in reg: return 16 32 | if '.16b' in reg: return 16 33 | if '.d' in reg: return 8 34 | if '.1d' in reg: return 8 35 | if '.2s' in reg: return 8 36 | if '.4h' in reg: return 8 37 | if '.8b' in reg: return 8 38 | if '.s' in reg: return 4 39 | if '.2h' in reg: return 4 40 | if '.4b' in reg: return 4 41 | if '.h' in reg: return 2 42 | if '.b' in reg: return 1 43 | 44 | print('couldn\'t get size of register -%s-' % reg) 45 | sys.exit(-1) 46 | 47 | def get_write_size(asig): 48 | (mnem, regs) = re.match(r'^(\w+) (.*)', asig).group(1,2) 49 | regs = regs.split(',') 50 | reg0 = regs[0] 51 | 52 | if reg0=='Rd': 53 | # eg: UMOV Rd,Vn.B[lane] means Rd is 1 byte 54 | assert len(regs)==2 55 | return get_reg_size(regs[1]) 56 | 57 | if reg0.startswith('{') and reg0.endswith('}') and ' - ' in reg0: 58 | # eg: ST2 {Vt.16B - Vt2.16B},[Xn] 59 | m = re.match('^.* - (Vt(\d)\..*)}', reg0) 60 | (reg0, num) = m.group(1,2) 61 | return (int(num)+1) * get_reg_size(reg0) 62 | 63 | return get_reg_size(reg0) 64 | 65 | def type_to_binja_types(ntype): 66 | # remove pointer 67 | if ntype.endswith(' const *'): 68 | ntype = ntype[0:-8] 69 | if ntype.endswith(' *'): 70 | ntype = ntype[0:-2] 71 | 72 | binja_type = 'Float' if 'float' in ntype else 'Int' 73 | 74 | # int (for lane or immediate) 75 | if ntype == 'int': 76 | return ['Type::IntegerType(4)'] 77 | 78 | # multiple packed, eg: "uint8x8x2_t" 79 | m = re.match(r'^(\w+?)(\d+)x(\d+)x(\d+)_t$', ntype) 80 | if m: 81 | (base, bit_width, npacked, nregs) = m.group(1,2,3, 4) 82 | return ['Type::%sType(%d)' % (binja_type, int(bit_width)*int(npacked)/8)]*int(nregs) 83 | 84 | # packed in registers, eg: "int8x8_t" 85 | m = re.match(r'^(\w+?)(\d+)x(\d+)_t$', ntype) 86 | if m: 87 | (base, bit_width, npacked) = m.group(1,2,3) 88 | return ['Type::%sType(%d)' % (binja_type, int(bit_width)*int(npacked)/8)] 89 | 90 | # simple, eg: "int8_t" 91 | m = re.match(r'^(\w+?)(\d+)_t$', ntype) 92 | if m: 93 | (base, bit_width) = m.group(1,2) 94 | return ['Type::%sType(%d)' % (binja_type, int(bit_width)/8)] 95 | 96 | print('cannot convert neon type %s into binja type' % ntype) 97 | sys.exit(-1) 98 | 99 | # given an intrinsic's name, argument types, and return type, compute 100 | # the binja intrinsic input types 101 | def resolve_input_types(name, arg_types, return_type): 102 | result = [] 103 | 104 | for at in arg_types: 105 | if at.endswith(' *'): 106 | # eg: int32x4x2_t vld2q_s32(int32_t const * ptr); 107 | assert ('ld' in name) or ('st' in name) 108 | result.extend(neon_type_to_binja_types(return_type)) 109 | else: 110 | result.extend(neon_type_to_binja_types(at)) 111 | 112 | return result 113 | 114 | if __name__ == '__main__': 115 | # parse neon_intrins.c into a "database" 116 | with open('neon_intrins.c') as fp: 117 | lines = [l.strip() for l in fp.readlines()] 118 | 119 | db = OrderedDict() 120 | 121 | for l in lines: 122 | if 'reinterpret' in l: continue 123 | if 'RESULT[' in l: continue 124 | (fsig, asig) = l.split('; // ') 125 | 126 | # function name 127 | m = re.match(r'^(\w+) (\w+)\((.*)\)$', fsig) 128 | fname = m.group(2) 129 | if fname in db: continue 130 | if asig.startswith('RESULT['): continue 131 | 132 | # function arguments 133 | fargs = [m.group(1)] + m.group(3).split(', ') 134 | fargs = [x.replace('const ', '') for x in fargs] 135 | 136 | (operation, operands) = re.match(r'^(\w+?) (.*)$', asig).group(1, 2) 137 | operands = operands.split(',') 138 | 139 | db[fname] = OrderedDict({ 140 | 'fsig': fsig, 141 | 'asig': asig, 142 | 'define': 'ARM64_INTRIN_%s' % fname.upper(), 143 | 'operation': 'ARM64_' + operation, 144 | 'fargs': fargs, 145 | 'operands': operands, 146 | }) 147 | 148 | cmd = sys.argv[1] 149 | 150 | if cmd in ['dump']: 151 | import pprint 152 | pp = pprint.PrettyPrinter() 153 | pp.pprint(db) 154 | 155 | elif cmd in ['enum', 'enumeration']: 156 | # for enum NeonIntrinsic : uint32_t ... 157 | first = True 158 | for fname in db: 159 | extra = '=ARM64_INTRIN_NORMAL_END' if first else '' 160 | print('\t%s%s,' % (db[fname]['define'], extra)) 161 | first = False 162 | 163 | elif cmd in ['name', 'names']: 164 | # for GetIntrinsicName(uint32_t intrinsic) 165 | for fname in db: 166 | print('\t\tcase %s: return "%s";' % (db[fname]['define'], fname)) 167 | 168 | elif cmd in ['all', 'define', 'defines']: 169 | # for GetAllIntrinsics() 170 | collection = [db[fname]['define'] for fname in db] 171 | i = 0 172 | while i outputs 211 | # std::vector inputs 212 | for fname in db: 213 | entry = db[fname] 214 | 215 | print('\t\tcase %s:' % entry['operation']) 216 | print('\t\t{') 217 | print('\t\t\t// fsig: %s' % entry['fsig']) 218 | print('\t\t\t// asig: %s' % entry['asig']) 219 | print('\t\t\t// operands_n: %d' % entry['operands_n']) 220 | print('\t\t\tadd_output(outputs, oper0, inst, INTRIN_TYPE_HINT_%s);' % (' '.join(entry['binja_output_types']).upper())) 221 | for i in range(0, len(entry['binja_input_types'])): 222 | print('\t\t\tadd_input(inputs, oper%d, inst, INTRIN_TYPE_HINT_%s);' % (i+1, entry['binja_input_types'][i].upper())) 223 | print('\t\t\til.AddInstruction(il.Intrinsic(outputs, %s, inputs));' % entry['define']) 224 | print('\t\t}') 225 | print('\t\tbreak;') 226 | 227 | elif cmd in ['test']: 228 | for fname in db: 229 | entry = db[fname] 230 | fargs = entry['fargs'] 231 | operands = entry['operands'] 232 | 233 | print(entry['operation']) 234 | print('fsig: %s' % entry['fsig']) 235 | print('asig: %s' % entry['asig']) 236 | print('fargs: %s' % fargs) 237 | print('operands: %s' % operands) 238 | 239 | # convert OPERATION X,Y,Z[lane] -> 240 | # OPERATION X,Y,Z,Z[lane] 241 | # tmp = [] 242 | # for o in operands: 243 | # m = re.match(r'^(.*)\[lane\d*\]$', o) 244 | # if m: 245 | # tmp.append(m.group(1)) 246 | # tmp.append('lane(%s)' % m.group(1)) 247 | # else: 248 | # tmp.append(o) 249 | # operands = tmp 250 | # convert OPERATION X,Y,#0 -> 251 | # OPERATION X,Y 252 | if re.match(r'^#\d+$', operands[-1]): 253 | operands = operands[:-1] 254 | # 255 | if len(fargs) == len(operands)+1: 256 | operands = [operands[0]] + operands 257 | 258 | if len(operands) != len(fargs): 259 | print('cant reconcile fargs and operands') 260 | if not 'vcopy' in entry['fsig']: 261 | sys.exit(-1) 262 | -------------------------------------------------------------------------------- /disassembler/test.c: -------------------------------------------------------------------------------- 1 | /* 2 | lldb ./cmdline -- single d503201f 3 | b decode 4 | r 5 | */ 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | #include "decode.h" 15 | #include "format.h" 16 | 17 | int verbose = 1; 18 | 19 | char* arrspec_to_str(enum ArrangementSpec as) 20 | { 21 | switch (as) 22 | { 23 | case ARRSPEC_NONE: 24 | return "NONE"; 25 | case ARRSPEC_FULL: 26 | return "FULL"; 27 | case ARRSPEC_2DOUBLES: 28 | return "2DOUBLES"; 29 | case ARRSPEC_4SINGLES: 30 | return "4SINGLES"; 31 | case ARRSPEC_8HALVES: 32 | return "8HALVES"; 33 | case ARRSPEC_16BYTES: 34 | return "16BYTES"; 35 | case ARRSPEC_1DOUBLE: 36 | return "1DOUBLE"; 37 | case ARRSPEC_2SINGLES: 38 | return "2SINGLES"; 39 | case ARRSPEC_4HALVES: 40 | return "4HALVES"; 41 | case ARRSPEC_8BYTES: 42 | return "8BYTES"; 43 | case ARRSPEC_1SINGLE: 44 | return "1SINGLE"; 45 | case ARRSPEC_2HALVES: 46 | return "2HALVES"; 47 | case ARRSPEC_4BYTES: 48 | return "4BYTES"; 49 | case ARRSPEC_1HALF: 50 | return "1HALF"; 51 | case ARRSPEC_1BYTE: 52 | return "1BYTE"; 53 | default: 54 | return "ERROR"; 55 | } 56 | } 57 | 58 | char* oper_class_to_str(enum OperandClass c) 59 | { 60 | switch (c) 61 | { 62 | case NONE: 63 | return "NONE"; 64 | case IMM32: 65 | return "IMM32"; 66 | case IMM64: 67 | return "IMM64"; 68 | case FIMM32: 69 | return "FIMM32"; 70 | case STR_IMM: 71 | return "STR_IMM"; 72 | case REG: 73 | return "REG"; 74 | case MULTI_REG: 75 | return "MULTI_REG"; 76 | case SYS_REG: 77 | return "SYS_REG"; 78 | case MEM_REG: 79 | return "MEM_REG"; 80 | case MEM_PRE_IDX: 81 | return "MEM_PRE_IDX"; 82 | case MEM_POST_IDX: 83 | return "MEM_POST_IDX"; 84 | case MEM_OFFSET: 85 | return "MEM_OFFSET"; 86 | case MEM_EXTENDED: 87 | return "MEM_EXTENDED"; 88 | case SME_TILE: 89 | return "SME_TILE"; 90 | case INDEXED_ELEMENT: 91 | return "INDEXED_ELEMENT"; 92 | case ACCUM_ARRAY: 93 | return "ACCUM_ARRAY"; 94 | case LABEL: 95 | return "LABEL"; 96 | case CONDITION: 97 | return "CONDITION"; 98 | case NAME: 99 | return "NAME"; 100 | case IMPLEMENTATION_SPECIFIC: 101 | return "IMPLEMENTATION_SPECIFIC"; 102 | default: 103 | return "ERROR"; 104 | } 105 | } 106 | 107 | char* cond_to_str(enum Condition c) 108 | { 109 | switch (c) 110 | { 111 | case COND_EQ: 112 | return "eq"; 113 | case COND_NE: 114 | return "ne"; 115 | case COND_CS: 116 | return "cs"; 117 | case COND_CC: 118 | return "cc"; 119 | case COND_MI: 120 | return "mi"; 121 | case COND_PL: 122 | return "pl"; 123 | case COND_VS: 124 | return "vs"; 125 | case COND_VC: 126 | return "vc"; 127 | case COND_HI: 128 | return "hi"; 129 | case COND_LS: 130 | return "ls"; 131 | case COND_GE: 132 | return "ge"; 133 | case COND_LT: 134 | return "lt"; 135 | case COND_GT: 136 | return "gt"; 137 | case COND_LE: 138 | return "le"; 139 | case COND_AL: 140 | return "al"; 141 | case COND_NV: 142 | return "nv"; 143 | default: 144 | return "ERROR"; 145 | } 146 | } 147 | 148 | char* shifttype_to_str(enum ShiftType st) 149 | { 150 | switch (st) 151 | { 152 | case ShiftType_NONE: 153 | return "ShiftType_NONE"; 154 | case ShiftType_LSL: 155 | return "ShiftType_LSL"; 156 | case ShiftType_LSR: 157 | return "ShiftType_LSR"; 158 | case ShiftType_ASR: 159 | return "ShiftType_ASR"; 160 | case ShiftType_ROR: 161 | return "ShiftType_ROR"; 162 | case ShiftType_UXTW: 163 | return "ShiftType_UXTW"; 164 | case ShiftType_SXTW: 165 | return "ShiftType_SXTW"; 166 | case ShiftType_SXTX: 167 | return "ShiftType_SXTX"; 168 | case ShiftType_UXTX: 169 | return "ShiftType_UXTX"; 170 | case ShiftType_SXTB: 171 | return "ShiftType_SXTB"; 172 | case ShiftType_SXTH: 173 | return "ShiftType_SXTH"; 174 | case ShiftType_UXTH: 175 | return "ShiftType_UXTH"; 176 | case ShiftType_UXTB: 177 | return "ShiftType_UXTB"; 178 | case ShiftType_MSL: 179 | return "ShiftType_MSL"; 180 | case ShiftType_END: 181 | return "ShiftType_END"; 182 | default: 183 | return "ERROR"; 184 | } 185 | } 186 | 187 | int disassemble(uint64_t address, uint32_t insword, char* result) 188 | { 189 | int rc; 190 | Instruction instr; 191 | memset(&instr, 0, sizeof(instr)); 192 | 193 | rc = aarch64_decompose(insword, &instr, address); 194 | if (verbose) 195 | printf("aarch64_decompose() returned %d\n", rc); 196 | if (rc) 197 | return rc; 198 | 199 | if (verbose) 200 | { 201 | printf(" instr.insword: %08X\n", instr.insword); 202 | printf(" instr.encoding: %d %s\n", instr.encoding, enc_to_str(instr.encoding)); 203 | printf("instr.operation: %d %s\n", instr.operation, operation_to_str(instr.operation)); 204 | printf(" instr.setflags: %d\n", instr.setflags); 205 | for (int i = 0; i < MAX_OPERANDS && instr.operands[i].operandClass != NONE; i++) 206 | { 207 | printf("instr.operands[%d]\n", i); 208 | 209 | InstructionOperand operand = instr.operands[i]; 210 | 211 | /* class */ 212 | printf("\t.class: %d (\"%s\")\n", operand.operandClass, oper_class_to_str(operand.operandClass)); 213 | switch (operand.operandClass) 214 | { 215 | case CONDITION: 216 | printf("\t\t%d %s\n", operand.cond, cond_to_str(operand.cond)); 217 | break; 218 | case FIMM32: 219 | printf("\t\t%f\n", *(float*)&(operand.immediate)); 220 | break; 221 | case IMM32: 222 | printf("\t.imm32: 0x%llX\n", operand.immediate & 0xFFFFFFFF); 223 | break; 224 | case IMM64: 225 | printf("\t.imm64: 0x%llX\n", operand.immediate); 226 | break; 227 | case NAME: 228 | printf("\t.name: %s\n", operand.name); 229 | break; 230 | default: 231 | break; 232 | } 233 | /* lane */ 234 | if (operand.laneUsed) 235 | printf("\t.lane: %d\n", operand.lane); 236 | /* shift */ 237 | if (operand.shiftType != ShiftType_NONE) 238 | { 239 | printf("\t.shiftType: %d (%s)\n", operand.shiftType, shifttype_to_str(operand.shiftType)); 240 | } 241 | /* arrangement spec */ 242 | printf("\t.arrSpec: %d %s\n", operand.arrSpec, arrspec_to_str(operand.arrSpec)); 243 | } 244 | } 245 | 246 | rc = aarch64_disassemble(&instr, result, 1024); 247 | if (verbose) 248 | printf("aarch64_disassemble() returned %d\n", rc); 249 | if (rc) 250 | return rc; 251 | 252 | return 0; 253 | } 254 | 255 | double subtract_timespecs(struct timespec t1, struct timespec t0) 256 | { 257 | double delta = 0; 258 | 259 | delta += (double)(t1.tv_nsec - t0.tv_nsec) / 1000000000.0; 260 | if (delta < 0) 261 | { 262 | t1.tv_sec -= 1; 263 | delta += 1; 264 | } 265 | 266 | delta += (double)t1.tv_sec - t0.tv_sec; 267 | 268 | return delta; 269 | } 270 | 271 | /* main */ 272 | int main(int ac, char** av) 273 | { 274 | srand(0xCAFE); 275 | 276 | Instruction instr; 277 | uint32_t insword; 278 | char instxt[1024] = {'\0'}; 279 | 280 | double delta; 281 | struct timespec t0, t1; 282 | 283 | if (ac <= 1) 284 | { 285 | printf("example usage:\n"); 286 | printf("\t%s d503201f\n", av[0]); 287 | return -1; 288 | } 289 | 290 | if (!strcmp(av[1], "decode-speed")) 291 | { 292 | verbose = false; 293 | 294 | clock_gettime(CLOCK_MONOTONIC, &t0); 295 | 296 | for (int64_t num_decoded=0; true; num_decoded += 1) 297 | { 298 | insword = (rand() << 16) ^ rand(); 299 | aarch64_decompose(insword, &instr, 0); 300 | if ((num_decoded & 0xFFFFFF) == 0) 301 | { 302 | clock_gettime(CLOCK_MONOTONIC, &t1); 303 | delta = subtract_timespecs(t1, t0); 304 | printf("%lld instructions in %fs, or %.0f instructions/s\n", 305 | num_decoded, delta, num_decoded/delta); 306 | } 307 | } 308 | return 0; 309 | } 310 | 311 | // There's no disassemble speed test yet because randomly generated instruction words often do 312 | // not decode. 313 | 314 | if (!strcmp(av[1], "strain") || !strcmp(av[1], "strainer") || !strcmp(av[1], "stress") || 315 | !strcmp(av[1], "stresser")) 316 | { 317 | verbose = 0; 318 | for (insword = 0; insword != 0xFFFFFFFF; insword++) 319 | { 320 | disassemble(0, insword, instxt); 321 | 322 | if ((insword & 0xFFFFFF) == 0) 323 | printf("%08X: %s\n", insword, instxt); 324 | } 325 | } 326 | 327 | if (!strcmp(av[1], "random")) 328 | { 329 | bool silent = ac > 2 && !strcmp(av[2], "silent"); 330 | verbose = 0; 331 | while (1) 332 | { 333 | insword = (rand() << 16) ^ rand(); 334 | if (disassemble(0, insword, instxt) == 0) 335 | { 336 | if (!silent) 337 | printf("%08X: %s\n", insword, instxt); 338 | } 339 | else 340 | { 341 | if (!silent) 342 | printf("%08X: (error)\n", insword); 343 | } 344 | } 345 | } 346 | 347 | else 348 | { 349 | insword = strtoul(av[1], NULL, 16); 350 | if (disassemble(0, insword, instxt) == 0) 351 | printf("%08X: %s\n", insword, instxt); 352 | } 353 | } 354 | -------------------------------------------------------------------------------- /disassembler/disasm_test.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # run disassembly tests in test_cases.txt 4 | # ensure you built gofer.so (see Makefile-local) 5 | 6 | import os, sys, struct, ctypes, re 7 | 8 | RED = '\x1B[31m' 9 | GREEN = '\x1B[32m' 10 | NORMAL = '\x1B[0m' 11 | 12 | #------------------------------------------------------------------------------ 13 | # disassemble 14 | #------------------------------------------------------------------------------ 15 | 16 | cbuf = None 17 | pfunc_disasm = None 18 | 19 | def normalize(instxt): 20 | #print('normalizing: %s' % instxt) 21 | instxt = instxt.strip() 22 | 23 | # collapse runs of whitespace to one space character 24 | instxt = re.sub('\s+', ' ', instxt) 25 | 26 | # remove comments 27 | if ' //' in instxt: 28 | instxt = instxt[0:instxt.find(' //')] 29 | 30 | # change that range notation 31 | # st4w {z14.s-z17.s}, p2, [x11, x19, lsl #2] 32 | # -> 33 | # st4w {z14.s, z15.s, z16.s, z17.s}, p2, [x11, x19, lsl #2] 34 | m = re.search(r'{z(\d+)\.(.)-z(\d+)\.(.)}', instxt) 35 | if m: 36 | (lhs, suffix_a, rhs, suffix_b) = m.group(1,2,3,4) 37 | assert suffix_a == suffix_b 38 | (lhs, rhs) = (int(lhs), int(rhs)) 39 | if rhs-lhs+1 == 4: 40 | replacement = '{z%d.%s, z%d.%s, z%d.%s, z%d.%s}' % \ 41 | (lhs, suffix_a, (lhs+1)%32, suffix_a, (lhs+2)%32, suffix_a, (lhs+3)%32, suffix_a) 42 | elif rhs-lhs+1 == 3: 43 | replacement = '{z%d.%s, z%d.%s, z%d.%s}' % \ 44 | (lhs, suffix_a, (lhs+1)%32, suffix_a, (lhs+2)%32, suffix_a) 45 | instxt = instxt.replace(m.group(0), replacement) 46 | 47 | # remove spaces from { list } 48 | # eg: { v5.b, v6.b, v7.b, v8.b } -> {v5.b, v6.b, v7.b, v8.b} 49 | instxt = re.sub(r'{ (.*?) }', r'{\1}', instxt) 50 | 51 | # remove leading hex zeros 52 | # 0x00000000071eb000 -> 0x71eb000 53 | instxt = re.sub(r'0x00+', r'0x', instxt) 54 | 55 | # decimal immediates to hex 56 | # add x29, x15, x25, lsl #6 -> add x29, x15, x25, lsl #0x6 57 | for dec_imm in re.findall(r'#\d+[,\]]', instxt): 58 | hex_imm = '#0x%x' % int(dec_imm[1:-1]) + dec_imm[-1] 59 | instxt = instxt.replace(dec_imm, hex_imm, 1) 60 | for dec_imm in re.findall(r'#\d+$', instxt): 61 | if not instxt.endswith(dec_imm): continue 62 | hex_imm = '#0x%x' % int(dec_imm[1:]) 63 | instxt = instxt[0:-len(dec_imm)] + hex_imm 64 | 65 | # #-3.375000000000000000e+00 -> #-3.375 66 | for x in re.findall(r'#[-\+\.\de]{8,}', instxt): 67 | instxt = instxt.replace(x, '#'+str(float(x[1:]))) 68 | 69 | # 0x0.000000 -> 0x0.0 70 | instxt = instxt.replace('0.000000', '0.0') 71 | instxt = instxt.replace('0.000', '0.0') 72 | 73 | # lowercase everything 74 | instxt = instxt.lower() 75 | 76 | # done 77 | return instxt 78 | 79 | def disassemble(addr, insnum): 80 | global cbuf, pfunc_disasm 81 | insword = struct.pack('features0 & ARCH_FEATURE_BF16) 5 | #define HasBTI() (ctx->features0 & ARCH_FEATURE_BTI) 6 | #define HasDGH() (ctx->features0 & ARCH_FEATURE_DGH) 7 | #define HasDotProd() (ctx->features0 & ARCH_FEATURE_DotProd) 8 | #define HasF32MM() (ctx->features0 & ARCH_FEATURE_F32MM) 9 | #define HasF64MM() (ctx->features0 & ARCH_FEATURE_F64MM) 10 | #define HasFCMA() (ctx->features0 & ARCH_FEATURE_FCMA) 11 | #define HasFHM() (ctx->features0 & ARCH_FEATURE_FHM) 12 | #define HasFP16() (ctx->features0 & ARCH_FEATURE_FP16) 13 | #define HasFRINTTS() (ctx->features0 & ARCH_FEATURE_FRINTTS) 14 | #define HasFlagM() (ctx->features0 & ARCH_FEATURE_FlagM) 15 | #define HasFlagM2() (ctx->features0 & ARCH_FEATURE_FlagM2) 16 | #define HasI8MM() (ctx->features0 & ARCH_FEATURE_I8MM) 17 | #define HasJSCVT() (ctx->features0 & ARCH_FEATURE_JSCVT) 18 | #define HasLOR() (ctx->features0 & ARCH_FEATURE_LOR) 19 | #define HasLRCPC() (ctx->features0 & ARCH_FEATURE_LRCPC) 20 | #define HasLRCPC2() (ctx->features0 & ARCH_FEATURE_LRCPC2) 21 | #define HasLS64() (ctx->features0 & ARCH_FEATURE_LS64) 22 | #define HasLS64_V() (ctx->features0 & ARCH_FEATURE_LS64_V) 23 | #define HasLSE() (ctx->features0 & ARCH_FEATURE_LSE) 24 | #define HasMTE() (ctx->features0 & ARCH_FEATURE_MTE) 25 | #define HasMTE2() (ctx->features0 & ARCH_FEATURE_MTE2) 26 | #define HasPAuth() (ctx->features0 & ARCH_FEATURE_PAuth) 27 | #define HasRAS() (ctx->features0 & ARCH_FEATURE_RAS) 28 | #define HasRDM() (ctx->features0 & ARCH_FEATURE_RDM) 29 | #define HasSHA3() (ctx->features0 & ARCH_FEATURE_SHA3) 30 | #define HasSHA512() (ctx->features0 & ARCH_FEATURE_SHA512) 31 | #define HasSM3() (ctx->features0 & ARCH_FEATURE_SM3) 32 | #define HasSM4() (ctx->features0 & ARCH_FEATURE_SM4) 33 | #define HasSME() (ctx->features0 & ARCH_FEATURE_SME) 34 | #define HasSME_F64F64() (ctx->features0 & ARCH_FEATURE_SME_F64F64) 35 | #define HasSME_I16I64() (ctx->features0 & ARCH_FEATURE_SME_I16I64) 36 | #define HasSPE() (ctx->features0 & ARCH_FEATURE_SPE) 37 | #define HasSVE_AES() (ctx->features0 & ARCH_FEATURE_SVE_AES) 38 | #define HasSVE_BitPerm() (ctx->features0 & ARCH_FEATURE_SVE_BitPerm) 39 | #define HasSVE_SHA3() (ctx->features0 & ARCH_FEATURE_SVE_SHA3) 40 | #define HasSVE_SM4() (ctx->features0 & ARCH_FEATURE_SVE_SM4) 41 | #define HasTME() (ctx->features0 & ARCH_FEATURE_TME) 42 | #define HasTRF() (ctx->features0 & ARCH_FEATURE_TRF) 43 | #define HasWFxT() (ctx->features0 & ARCH_FEATURE_WFxT) 44 | #define HasXS() (ctx->features0 & ARCH_FEATURE_XS) 45 | 46 | // 52 HaveXXX() functions used by pcode: 47 | #define HaveAESExt() (ctx->features1 & ARCH_FEATURE_AESExt) 48 | #define HaveAtomicExt() (ctx->features1 & ARCH_FEATURE_AtomicExt) 49 | #define HaveBF16Ext() (ctx->features1 & ARCH_FEATURE_BF16Ext) 50 | #define HaveBTIExt() (ctx->features1 & ARCH_FEATURE_BTIExt) 51 | #define HaveBit128PMULLExt() (ctx->features1 & ARCH_FEATURE_Bit128PMULLExt) 52 | #define HaveCRCExt() (ctx->features1 & ARCH_FEATURE_CRCExt) 53 | #define HaveDGHExt() (ctx->features1 & ARCH_FEATURE_DGHExt) 54 | #define HaveDITExt() (ctx->features1 & ARCH_FEATURE_DITExt) 55 | #define HaveDOTPExt() (ctx->features1 & ARCH_FEATURE_DOTPExt) 56 | #define HaveFCADDExt() (ctx->features1 & ARCH_FEATURE_FCADDExt) 57 | #define HaveFJCVTZSExt() (ctx->features1 & ARCH_FEATURE_FJCVTZSExt) 58 | #define HaveFP16Ext() (ctx->features1 & ARCH_FEATURE_FP16Ext) 59 | #define HaveFP16MulNoRoundingToFP32Ext() (ctx->features1 & ARCH_FEATURE_FP16MulNoRoundingToFP32Ext) 60 | #define HaveFeatLS64() (ctx->features1 & ARCH_FEATURE_FeatLS64) 61 | #define HaveFeatWFxT() (ctx->features1 & ARCH_FEATURE_FeatWFxT) 62 | #define HaveFeatXS() (ctx->features1 & ARCH_FEATURE_FeatXS) 63 | #define HaveFlagFormatExt() (ctx->features1 & ARCH_FEATURE_FlagFormatExt) 64 | #define HaveFlagManipulateExt() (ctx->features1 & ARCH_FEATURE_FlagManipulateExt) 65 | #define HaveFrintExt() (ctx->features1 & ARCH_FEATURE_FrintExt) 66 | #define HaveInt8MatMulExt() (ctx->features1 & ARCH_FEATURE_Int8MatMulExt) 67 | #define HaveMTE2Ext() (ctx->features1 & ARCH_FEATURE_MTE2Ext) 68 | #define HaveMTEExt() (ctx->features1 & ARCH_FEATURE_MTEExt) 69 | #define HaveNVExt() (ctx->features1 & ARCH_FEATURE_NVExt) 70 | #define HavePACExt() (ctx->features1 & ARCH_FEATURE_PACExt) 71 | #define HavePANExt() (ctx->features1 & ARCH_FEATURE_PANExt) 72 | #define HaveQRDMLAHExt() (ctx->features1 & ARCH_FEATURE_QRDMLAHExt) 73 | #define HaveRASExt() (ctx->features1 & ARCH_FEATURE_RASExt) 74 | #define HaveSBExt() (ctx->features1 & ARCH_FEATURE_SBExt) 75 | #define HaveSHA1Ext() (ctx->features1 & ARCH_FEATURE_SHA1Ext) 76 | #define HaveSHA256Ext() (ctx->features1 & ARCH_FEATURE_SHA256Ext) 77 | #define HaveSHA3Ext() (ctx->features1 & ARCH_FEATURE_SHA3Ext) 78 | #define HaveSHA512Ext() (ctx->features1 & ARCH_FEATURE_SHA512Ext) 79 | #define HaveSM3Ext() (ctx->features1 & ARCH_FEATURE_SM3Ext) 80 | #define HaveSM4Ext() (ctx->features1 & ARCH_FEATURE_SM4Ext) 81 | #define HaveSME() (ctx->features1 & ARCH_FEATURE_SME) 82 | #define HaveSMEF64F64() (ctx->features1 & ARCH_FEATURE_SMEF64F64) 83 | #define HaveSMEI16I64() (ctx->features1 & ARCH_FEATURE_SMEI16I64) 84 | #define HaveSSBSExt() (ctx->features1 & ARCH_FEATURE_SSBSExt) 85 | #define HaveSVE() (ctx->features1 & ARCH_FEATURE_SVE) 86 | #define HaveSVE2() (ctx->features1 & ARCH_FEATURE_SVE2) 87 | #define HaveSVE2AES() (ctx->features1 & ARCH_FEATURE_SVE2AES) 88 | #define HaveSVE2BitPerm() (ctx->features1 & ARCH_FEATURE_SVE2BitPerm) 89 | #define HaveSVE2PMULL128() (ctx->features1 & ARCH_FEATURE_SVE2PMULL128) 90 | #define HaveSVE2SHA3() (ctx->features1 & ARCH_FEATURE_SVE2SHA3) 91 | #define HaveSVE2SM4() (ctx->features1 & ARCH_FEATURE_SVE2SM4) 92 | #define HaveSVEFP32MatMulExt() (ctx->features1 & ARCH_FEATURE_SVEFP32MatMulExt) 93 | #define HaveSVEFP64MatMulExt() (ctx->features1 & ARCH_FEATURE_SVEFP64MatMulExt) 94 | #define HaveSelfHostedTrace() (ctx->features1 & ARCH_FEATURE_SelfHostedTrace) 95 | #define HaveStatisticalProfiling() (ctx->features1 & ARCH_FEATURE_StatisticalProfiling) 96 | #define HaveTME() (ctx->features1 & ARCH_FEATURE_TME) 97 | #define HaveUAOExt() (ctx->features1 & ARCH_FEATURE_UAOExt) 98 | #define HaveVirtHostExt() (ctx->features1 & ARCH_FEATURE_VirtHostExt) 99 | 100 | // defines for features referenced at decode 101 | #define ARCH_FEATURE_BF16 ((uint64_t)1<<0) 102 | #define ARCH_FEATURE_BTI ((uint64_t)1<<1) 103 | #define ARCH_FEATURE_DGH ((uint64_t)1<<2) 104 | #define ARCH_FEATURE_DotProd ((uint64_t)1<<3) 105 | #define ARCH_FEATURE_F32MM ((uint64_t)1<<4) 106 | #define ARCH_FEATURE_F64MM ((uint64_t)1<<5) 107 | #define ARCH_FEATURE_FCMA ((uint64_t)1<<6) 108 | #define ARCH_FEATURE_FHM ((uint64_t)1<<7) 109 | #define ARCH_FEATURE_FP16 ((uint64_t)1<<8) 110 | #define ARCH_FEATURE_FRINTTS ((uint64_t)1<<9) 111 | #define ARCH_FEATURE_FlagM ((uint64_t)1<<10) 112 | #define ARCH_FEATURE_FlagM2 ((uint64_t)1<<11) 113 | #define ARCH_FEATURE_I8MM ((uint64_t)1<<12) 114 | #define ARCH_FEATURE_JSCVT ((uint64_t)1<<13) 115 | #define ARCH_FEATURE_LOR ((uint64_t)1<<14) 116 | #define ARCH_FEATURE_LRCPC ((uint64_t)1<<15) 117 | #define ARCH_FEATURE_LRCPC2 ((uint64_t)1<<16) 118 | #define ARCH_FEATURE_LS64 ((uint64_t)1<<17) 119 | #define ARCH_FEATURE_LS64_V ((uint64_t)1<<18) 120 | #define ARCH_FEATURE_LSE ((uint64_t)1<<19) 121 | #define ARCH_FEATURE_MTE ((uint64_t)1<<20) 122 | #define ARCH_FEATURE_MTE2 ((uint64_t)1<<21) 123 | #define ARCH_FEATURE_PAuth ((uint64_t)1<<22) 124 | #define ARCH_FEATURE_RAS ((uint64_t)1<<23) 125 | #define ARCH_FEATURE_RDM ((uint64_t)1<<24) 126 | #define ARCH_FEATURE_SHA3 ((uint64_t)1<<25) 127 | #define ARCH_FEATURE_SHA512 ((uint64_t)1<<26) 128 | #define ARCH_FEATURE_SM3 ((uint64_t)1<<27) 129 | #define ARCH_FEATURE_SM4 ((uint64_t)1<<28) 130 | #define ARCH_FEATURE_SME ((uint64_t)1<<29) 131 | #define ARCH_FEATURE_SME_F64F64 ((uint64_t)1<<30) 132 | #define ARCH_FEATURE_SME_I16I64 ((uint64_t)1<<31) 133 | #define ARCH_FEATURE_SPE ((uint64_t)1<<32) 134 | #define ARCH_FEATURE_SVE_AES ((uint64_t)1<<33) 135 | #define ARCH_FEATURE_SVE_BitPerm ((uint64_t)1<<34) 136 | #define ARCH_FEATURE_SVE_SHA3 ((uint64_t)1<<35) 137 | #define ARCH_FEATURE_SVE_SM4 ((uint64_t)1<<36) 138 | #define ARCH_FEATURE_TME ((uint64_t)1<<37) 139 | #define ARCH_FEATURE_TRF ((uint64_t)1<<38) 140 | #define ARCH_FEATURE_WFxT ((uint64_t)1<<39) 141 | #define ARCH_FEATURE_XS ((uint64_t)1<<40) 142 | 143 | // defines for features referenced by pcode 144 | #define ARCH_FEATURE_AESExt ((uint64_t)1<<0) 145 | #define ARCH_FEATURE_AtomicExt ((uint64_t)1<<1) 146 | #define ARCH_FEATURE_BF16Ext ((uint64_t)1<<2) 147 | #define ARCH_FEATURE_BTIExt ((uint64_t)1<<3) 148 | #define ARCH_FEATURE_Bit128PMULLExt ((uint64_t)1<<4) 149 | #define ARCH_FEATURE_CRCExt ((uint64_t)1<<5) 150 | #define ARCH_FEATURE_DGHExt ((uint64_t)1<<6) 151 | #define ARCH_FEATURE_DITExt ((uint64_t)1<<7) 152 | #define ARCH_FEATURE_DOTPExt ((uint64_t)1<<8) 153 | #define ARCH_FEATURE_FCADDExt ((uint64_t)1<<9) 154 | #define ARCH_FEATURE_FJCVTZSExt ((uint64_t)1<<10) 155 | #define ARCH_FEATURE_FP16Ext ((uint64_t)1<<11) 156 | #define ARCH_FEATURE_FP16MulNoRoundingToFP32Ext ((uint64_t)1<<12) 157 | #define ARCH_FEATURE_FeatLS64 ((uint64_t)1<<13) 158 | #define ARCH_FEATURE_FeatWFxT ((uint64_t)1<<14) 159 | #define ARCH_FEATURE_FeatXS ((uint64_t)1<<15) 160 | #define ARCH_FEATURE_FlagFormatExt ((uint64_t)1<<16) 161 | #define ARCH_FEATURE_FlagManipulateExt ((uint64_t)1<<17) 162 | #define ARCH_FEATURE_FrintExt ((uint64_t)1<<18) 163 | #define ARCH_FEATURE_Int8MatMulExt ((uint64_t)1<<19) 164 | #define ARCH_FEATURE_MTE2Ext ((uint64_t)1<<20) 165 | #define ARCH_FEATURE_MTEExt ((uint64_t)1<<21) 166 | #define ARCH_FEATURE_NVExt ((uint64_t)1<<22) 167 | #define ARCH_FEATURE_PACExt ((uint64_t)1<<23) 168 | #define ARCH_FEATURE_PANExt ((uint64_t)1<<24) 169 | #define ARCH_FEATURE_QRDMLAHExt ((uint64_t)1<<25) 170 | #define ARCH_FEATURE_RASExt ((uint64_t)1<<26) 171 | #define ARCH_FEATURE_SBExt ((uint64_t)1<<27) 172 | #define ARCH_FEATURE_SHA1Ext ((uint64_t)1<<28) 173 | #define ARCH_FEATURE_SHA256Ext ((uint64_t)1<<29) 174 | #define ARCH_FEATURE_SHA3Ext ((uint64_t)1<<30) 175 | #define ARCH_FEATURE_SHA512Ext ((uint64_t)1<<31) 176 | #define ARCH_FEATURE_SM3Ext ((uint64_t)1<<32) 177 | #define ARCH_FEATURE_SM4Ext ((uint64_t)1<<33) 178 | //#define ARCH_FEATURE_SME ((uint64_t)1<<34) 179 | #define ARCH_FEATURE_SMEF64F64 ((uint64_t)1<<35) 180 | #define ARCH_FEATURE_SMEI16I64 ((uint64_t)1<<36) 181 | #define ARCH_FEATURE_SSBSExt ((uint64_t)1<<37) 182 | #define ARCH_FEATURE_SVE ((uint64_t)1<<38) 183 | #define ARCH_FEATURE_SVE2 ((uint64_t)1<<39) 184 | #define ARCH_FEATURE_SVE2AES ((uint64_t)1<<40) 185 | #define ARCH_FEATURE_SVE2BitPerm ((uint64_t)1<<41) 186 | #define ARCH_FEATURE_SVE2PMULL128 ((uint64_t)1<<42) 187 | #define ARCH_FEATURE_SVE2SHA3 ((uint64_t)1<<43) 188 | #define ARCH_FEATURE_SVE2SM4 ((uint64_t)1<<44) 189 | #define ARCH_FEATURE_SVEFP32MatMulExt ((uint64_t)1<<45) 190 | #define ARCH_FEATURE_SVEFP64MatMulExt ((uint64_t)1<<46) 191 | #define ARCH_FEATURE_SelfHostedTrace ((uint64_t)1<<47) 192 | #define ARCH_FEATURE_StatisticalProfiling ((uint64_t)1<<48) 193 | //#define ARCH_FEATURE_TME ((uint64_t)1<<49) 194 | #define ARCH_FEATURE_UAOExt ((uint64_t)1<<50) 195 | #define ARCH_FEATURE_VirtHostExt ((uint64_t)1<<51) 196 | 197 | #define ARCH_FEATURES_ALL 0xFFFFFFFFFFFFFFFF 198 | -------------------------------------------------------------------------------- /disassembler/pcode.h: -------------------------------------------------------------------------------- 1 | #include "feature_flags.h" 2 | 3 | #define INSWORD (ctx->insword) 4 | #define UNDEFINED \ 5 | { \ 6 | return DECODE_STATUS_UNDEFINED; \ 7 | } 8 | #define UNMATCHED \ 9 | { \ 10 | return DECODE_STATUS_UNMATCHED; \ 11 | } 12 | #define RESERVED(X) \ 13 | { \ 14 | return DECODE_STATUS_RESERVED; \ 15 | } 16 | #define UNALLOCATED(X) \ 17 | { \ 18 | dec->encoding = (X); \ 19 | return DECODE_STATUS_UNALLOCATED; \ 20 | } 21 | #define ENDOFINSTRUCTION \ 22 | { \ 23 | return DECODE_STATUS_END_OF_INSTRUCTION; \ 24 | } 25 | #define SEE \ 26 | { \ 27 | return DECODE_STATUS_LOST; \ 28 | } 29 | #define UNREACHABLE \ 30 | { \ 31 | return DECODE_STATUS_UNREACHABLE; \ 32 | } 33 | /* do NOT return immediately! post-decode pcode might still need to run */ 34 | #define OK(X) \ 35 | { \ 36 | instr->encoding = (X); \ 37 | instr->operation = enc_to_oper(X); \ 38 | rc = DECODE_STATUS_OK; \ 39 | } 40 | #define assert(X) \ 41 | if (!(X)) \ 42 | { \ 43 | return DECODE_STATUS_ASSERT_FAILED; \ 44 | } 45 | 46 | #define BITMASK(N) (((uint64_t)1 << (N)) - 1) 47 | #define SLICE(X, MSB, LSB) (((X) >> (LSB)) & BITMASK((MSB) - (LSB) + 1)) /* get bits [MSB,LSB] */ 48 | #define CONCAT(A, B, B_WIDTH) (((A) << (B_WIDTH)) | (B)) 49 | #define NOT(X, X_WIDTH) ((X) ^ BITMASK(X_WIDTH)) 50 | 51 | #define DecodeBitMasksCheckUndefined(N, imms) \ 52 | if ((N == 0 && \ 53 | (imms == 0x3D || imms == 0x3B || imms == 0x37 || imms == 0x2F || imms == 0x1F)) || \ 54 | (N == 1 && imms == 0x3F)) \ 55 | { \ 56 | return DECODE_STATUS_UNDEFINED; \ 57 | } 58 | 59 | #define UINT(x) (unsigned int)(x) 60 | #define SInt(X, X_WIDTH) SignExtend((X), (X_WIDTH)) 61 | #define INT(x) (signed int)(x) 62 | #define ZeroExtend(X, Y) (uint64_t)(X) 63 | #define LSL(X, Y) ((X) << (Y)) 64 | 65 | #define LOG2_TAG_GRANULE 4 66 | #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 67 | 68 | /* pcode -> cpp booleans */ 69 | #define TRUE true 70 | #define FALSE false 71 | 72 | /* these calls just check generated per-iform boolean variables */ 73 | #define EncodingLabeled32Bit() (encoding32) 74 | #define EncodingLabeled64Bit() (encoding64) 75 | 76 | // extras we find in spec tables, etc. 77 | #define HaveTLBIOS() (1) 78 | #define HaveTLBIRANGE() (1) 79 | #define HaveDCCVADP() (1) 80 | #define HaveDCPoP() (1) 81 | 82 | #define SetBTypeCompatible(X) ctx->BTypeCompatible = (X) 83 | #define SetBTypeNext(X) ctx->BTypeNext = (X) 84 | #define Halted() ctx->halted 85 | 86 | enum SystemOp 87 | { 88 | Sys_ERROR = -1, 89 | Sys_AT = 0, 90 | Sys_DC = 1, 91 | Sys_IC = 2, 92 | Sys_TLBI = 3, 93 | Sys_SYS = 4, 94 | }; 95 | 96 | enum ReduceOp 97 | { 98 | ReduceOp_ERROR = 0, 99 | ReduceOp_ADD, 100 | ReduceOp_FADD, 101 | ReduceOp_FMIN, 102 | ReduceOp_FMAX, 103 | ReduceOp_FMINNUM, 104 | ReduceOp_FMAXNUM, 105 | }; 106 | 107 | enum LogicalOp 108 | { 109 | LogicalOp_ERROR = 0, 110 | LogicalOp_AND, 111 | LogicalOp_EOR, 112 | LogicalOp_ORR 113 | }; 114 | 115 | enum BranchType 116 | { 117 | BranchType_ERROR = 0, 118 | BranchType_DIRCALL, // Direct Branch with link 119 | BranchType_INDCALL, // Indirect Branch with link 120 | BranchType_ERET, // Exception return (indirect) 121 | BranchType_DBGEXIT, // Exit from Debug state 122 | BranchType_RET, // Indirect branch with function return hint 123 | BranchType_DIR, // Direct branch 124 | BranchType_INDIR, // Indirect branch 125 | BranchType_EXCEPTION, // Exception entry 126 | BranchType_RESET, // Reset 127 | BranchType_UNKNOWN // Other 128 | }; 129 | 130 | enum VBitOp 131 | { 132 | VBitOp_ERROR = 0, 133 | VBitOp_VBIF, 134 | VBitOp_VBIT, 135 | VBitOp_VBSL, 136 | VBitOp_VEOR 137 | }; 138 | 139 | enum SystemHintOp 140 | { 141 | SystemHintOp_ERROR = 0, 142 | SystemHintOp_NOP, 143 | SystemHintOp_YIELD, 144 | SystemHintOp_WFE, 145 | SystemHintOp_WFI, 146 | SystemHintOp_SEV, 147 | SystemHintOp_SEVL, 148 | SystemHintOp_DGH, 149 | SystemHintOp_ESB, 150 | SystemHintOp_PSB, 151 | SystemHintOp_TSB, 152 | SystemHintOp_BTI, 153 | SystemHintOp_CSDB, 154 | SystemHintOp_WFET, 155 | SystemHintOp_WFIT, 156 | }; 157 | 158 | enum ImmediateOp 159 | { 160 | ImmediateOp_ERROR = 0, 161 | ImmediateOp_MOVI, 162 | ImmediateOp_MVNI, 163 | ImmediateOp_ORR, 164 | ImmediateOp_BIC 165 | }; 166 | 167 | enum AccType 168 | { 169 | AccType_ERROR = 0, 170 | AccType_ATOMICRW, 171 | AccType_ATOMIC, 172 | AccType_LIMITEDORDERED, 173 | AccType_ORDEREDATOMICRW, 174 | AccType_ORDEREDATOMIC, 175 | AccType_ORDERED 176 | }; 177 | 178 | enum CompareOp 179 | { 180 | CompareOp_ERROR = 0, 181 | CompareOp_EQ, 182 | CompareOp_GE, 183 | CompareOp_GT, 184 | CompareOp_LE, 185 | CompareOp_LT 186 | }; 187 | 188 | enum Constraint 189 | { 190 | Constraint_ERROR = 0, 191 | Constraint_DISABLED, 192 | Constraint_FALSE, 193 | Constraint_FAULT, 194 | Constraint_FORCE, 195 | Constraint_LIMITED_ATOMICITY, 196 | Constraint_NONE, 197 | Constraint_NOP, 198 | Constraint_TRUE, 199 | Constraint_UNDEF, 200 | Constraint_UNKNOWN, 201 | Constraint_WBSUPPRESS, 202 | }; 203 | 204 | enum CountOp 205 | { 206 | CountOp_ERROR = 0, 207 | CountOp_CLS, 208 | CountOp_CLZ 209 | }; 210 | 211 | enum DSBAlias 212 | { 213 | DSBAlias_DSB = 0, 214 | DSBAlias_SSBB, 215 | DSBAlias_PSSBB 216 | }; 217 | 218 | enum MBReqDomain 219 | { 220 | MBReqDomain_ERROR = 0, 221 | MBReqDomain_Nonshareable, 222 | MBReqDomain_InnerShareable, 223 | MBReqDomain_OuterShareable, 224 | MBReqDomain_FullSystem 225 | }; 226 | 227 | enum MBReqTypes 228 | { 229 | MBReqTypes_ERROR = 0, 230 | MBReqTypes_Reads, 231 | MBReqTypes_Writes, 232 | MBReqTypes_All 233 | }; 234 | 235 | enum FPUnaryOp 236 | { 237 | FPUnaryOp_ERROR = 0, 238 | FPUnaryOp_ABS, 239 | FPUnaryOp_MOV, 240 | FPUnaryOp_NEG, 241 | FPUnaryOp_SQRT 242 | }; 243 | 244 | enum FPConvOp 245 | { 246 | FPConvOp_ERROR = 0, 247 | FPConvOp_CVT_FtoI, 248 | FPConvOp_CVT_ItoF, 249 | FPConvOp_MOV_FtoI, 250 | FPConvOp_MOV_ItoF, 251 | FPConvOp_CVT_FtoI_JS 252 | }; 253 | 254 | enum FPMaxMinOp 255 | { 256 | FPMaxMinOp_ERROR = 0, 257 | FPMaxMinOp_MAX, 258 | FPMaxMinOp_MIN, 259 | FPMaxMinOp_MAXNUM, 260 | FPMaxMinOp_MINNUM 261 | }; 262 | 263 | enum FPRounding 264 | { 265 | FPRounding_ERROR = 0, 266 | FPRounding_TIEEVEN, 267 | FPRounding_POSINF, 268 | FPRounding_NEGINF, 269 | FPRounding_ZERO, 270 | FPRounding_TIEAWAY, 271 | FPRounding_ODD 272 | }; 273 | 274 | enum MemAtomicOp 275 | { 276 | MemAtomicOp_ERROR = 0, 277 | MemAtomicOp_ADD, 278 | MemAtomicOp_BIC, 279 | MemAtomicOp_EOR, 280 | MemAtomicOp_ORR, 281 | MemAtomicOp_SMAX, 282 | MemAtomicOp_SMIN, 283 | MemAtomicOp_UMAX, 284 | MemAtomicOp_UMIN, 285 | MemAtomicOp_SWP 286 | }; 287 | 288 | enum MemOp 289 | { 290 | MemOp_ERROR = 0, 291 | MemOp_LOAD, 292 | MemOp_STORE, 293 | MemOp_PREFETCH 294 | }; 295 | 296 | enum MoveWideOp 297 | { 298 | MoveWideOp_ERROR = 0, 299 | MoveWideOp_N, 300 | MoveWideOp_Z, 301 | MoveWideOp_K 302 | }; 303 | 304 | enum PSTATEField 305 | { 306 | PSTATEField_ERROR = 0, 307 | PSTATEField_DAIFSet, 308 | PSTATEField_DAIFClr, 309 | PSTATEField_PAN, // Armv8.1 310 | PSTATEField_UAO, // Armv8.2 311 | PSTATEField_DIT, // Armv8.4 312 | PSTATEField_SSBS, 313 | PSTATEField_TCO, // Armv8.5 314 | PSTATEField_SP, 315 | PSTATEField_SVCRZA, 316 | PSTATEField_SVCRSM, 317 | PSTATEField_SVCRSMZA 318 | }; 319 | 320 | enum SVECmp 321 | { 322 | Cmp_ERROR = -1, 323 | Cmp_EQ, 324 | Cmp_NE, 325 | Cmp_GE, 326 | Cmp_GT, 327 | Cmp_LT, 328 | Cmp_LE, 329 | Cmp_UN 330 | }; 331 | 332 | enum PrefetchHint 333 | { 334 | Prefetch_ERROR = -1, 335 | Prefetch_READ, 336 | Prefetch_WRITE, 337 | Prefetch_EXEC 338 | }; 339 | 340 | enum Unpredictable 341 | { 342 | Unpredictable_ERROR = -1, 343 | Unpredictable_VMSR, 344 | Unpredictable_WBOVERLAPLD, 345 | Unpredictable_WBOVERLAPST, 346 | Unpredictable_LDPOVERLAP, 347 | Unpredictable_BASEOVERLAP, 348 | Unpredictable_DATAOVERLAP, 349 | Unpredictable_DEVPAGE2, 350 | Unpredictable_DEVICETAGSTORE, 351 | Unpredictable_INSTRDEVICE, 352 | Unpredictable_RESCPACR, 353 | Unpredictable_RESMAIR, 354 | Unpredictable_RESTEXCB, 355 | Unpredictable_RESDACR, 356 | Unpredictable_RESPRRR, 357 | Unpredictable_RESVTCRS, 358 | Unpredictable_RESTnSZ, 359 | Unpredictable_OORTnSZ, 360 | Unpredictable_LARGEIPA, 361 | Unpredictable_ESRCONDPASS, 362 | Unpredictable_ILZEROIT, 363 | Unpredictable_ILZEROT, 364 | Unpredictable_BPVECTORCATCHPRI, 365 | Unpredictable_VCMATCHHALF, 366 | Unpredictable_VCMATCHDAPA, 367 | Unpredictable_WPMASKANDBAS, 368 | Unpredictable_WPBASCONTIGUOUS, 369 | Unpredictable_RESWPMASK, 370 | Unpredictable_WPMASKEDBITS, 371 | Unpredictable_RESBPWPCTRL, 372 | Unpredictable_BPNOTIMPL, 373 | Unpredictable_RESBPTYPE, 374 | Unpredictable_BPNOTCTXCMP, 375 | Unpredictable_BPMATCHHALF, 376 | Unpredictable_BPMISMATCHHALF, 377 | Unpredictable_RESTARTALIGNPC, 378 | Unpredictable_RESTARTZEROUPPERPC, 379 | Unpredictable_ZEROUPPER, 380 | Unpredictable_ERETZEROUPPERPC, 381 | Unpredictable_A32FORCEALIGNPC, 382 | Unpredictable_SMD, 383 | Unpredictable_NONFAULT, 384 | Unpredictable_SVEZEROUPPER, 385 | Unpredictable_SVELDNFDATA, 386 | Unpredictable_SVELDNFZERO, 387 | Unpredictable_CHECKSPNONEACTIVE, 388 | Unpredictable_AFUPDATE, // AF update for alignment or permission fault, 389 | Unpredictable_IESBinDebug, // Use SCTLR[].IESB in Debug state, 390 | Unpredictable_BADPMSFCR, // Bad settings for PMSFCR_EL1/PMSEVFR_EL1/PMSLATFR_EL1, 391 | Unpredictable_ZEROBTYPE, 392 | Unpredictable_CLEARERRITEZERO, // Clearing sticky errors when instruction in flight, 393 | Unpredictable_ALUEXCEPTIONRETURN, 394 | Unpredictable_DBGxVR_RESS, 395 | Unpredictable_WFxTDEBUG, 396 | Unpredictable_LS64UNSUPPORTED, 397 | }; 398 | 399 | typedef struct DecodeBitMasks_ReturnType_ 400 | { 401 | uint64_t wmask; 402 | uint64_t tmask; 403 | } DecodeBitMasks_ReturnType; 404 | 405 | int HighestSetBit(uint64_t x); 406 | int LowestSetBit(uint64_t x); 407 | 408 | bool BFXPreferred(uint32_t sf, uint32_t uns, uint32_t imms, uint32_t immr); 409 | int BitCount(uint32_t x); 410 | DecodeBitMasks_ReturnType DecodeBitMasks( 411 | uint8_t /*bit*/ immN, uint8_t /*bit(6)*/ imms, uint8_t /*bit(6)*/ immr); 412 | 413 | enum Constraint ConstrainUnpredictable(enum Unpredictable); 414 | bool MoveWidePreferred(uint32_t sf, uint32_t immN, uint32_t imms, uint32_t immr); 415 | bool SVEMoveMaskPreferred(uint32_t imm13); 416 | enum ShiftType DecodeRegExtend(uint8_t op); 417 | enum ShiftType DecodeShift(uint8_t op); 418 | enum SystemOp SysOp(uint32_t op1, uint32_t CRn, uint32_t CRm, uint32_t op2); 419 | uint32_t UInt(uint32_t); 420 | uint32_t BitSlice(uint64_t, int hi, int lo); // including the endpoints 421 | bool IsZero(uint64_t foo); 422 | bool IsOnes(uint64_t foo, int width); 423 | uint64_t Replicate(uint64_t val, uint8_t times, uint64_t width); 424 | uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8); 425 | 426 | bool BTypeCompatible_BTI(uint8_t hintcode, uint8_t pstate_btype); 427 | bool BTypeCompatible_PACIXSP(void); 428 | 429 | enum FPRounding FPDecodeRounding(uint8_t RMode); 430 | enum FPRounding FPRoundingMode(uint64_t fpcr); 431 | 432 | bool HaltingAllowed(void); 433 | void SystemAccessTrap(uint32_t a, uint32_t b); 434 | void CheckSystemAccess(uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t, uint8_t); 435 | 436 | uint64_t VFPExpandImm(uint8_t imm8, unsigned width); 437 | 438 | #define EL0 0 439 | #define EL1 1 440 | #define EL2 2 441 | #define EL3 3 442 | bool EL2Enabled(void); 443 | bool ELUsingAArch32(uint8_t); 444 | 445 | uint64_t FPOne(bool sign, int width); 446 | uint64_t FPTwo(bool sign, int width); 447 | uint64_t FPPointFive(bool sign, int width); 448 | 449 | uint64_t SignExtend(uint64_t x, int width); 450 | -------------------------------------------------------------------------------- /disassembler/regs.c: -------------------------------------------------------------------------------- 1 | #include "regs.h" 2 | 3 | //----------------------------------------------------------------------------- 4 | // registers (and related) to string 5 | //----------------------------------------------------------------------------- 6 | 7 | static const char* RegisterString[] = {"NONE", "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", 8 | "w9", "w10", "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22", 9 | "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr", "wsp", "x0", "x1", "x2", "x3", 10 | "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", 11 | "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", 12 | "xzr", "sp", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", 13 | "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", 14 | "v26", "v27", "v28", "v29", "v30", "v31", "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 15 | "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", "b16", "b17", "b18", "b19", "b20", "b21", 16 | "b22", "b23", "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", "h0", "h1", "h2", 17 | "h3", "h4", "h5", "h6", "h7", "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", "h16", 18 | "h17", "h18", "h19", "h20", "h21", "h22", "h23", "h24", "h25", "h26", "h27", "h28", "h29", 19 | "h30", "h31", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", 20 | "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", 21 | "s25", "s26", "s27", "s28", "s29", "s30", "s31", "d0", "d1", "d2", "d3", "d4", "d5", 22 | "d6", "d7", "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", 23 | "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", "q0", 24 | "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 25 | "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", 26 | "q29", "q30", "q31", 27 | // B vectors 28 | "v0.b[0]", "v0.b[1]", "v0.b[2]", "v0.b[3]", "v0.b[4]", "v0.b[5]", "v0.b[6]", "v0.b[7]", 29 | "v0.b[8]", "v0.b[9]", "v0.b[10]", "v0.b[11]", "v0.b[12]", "v0.b[13]", "v0.b[14]", "v0.b[15]", 30 | "v1.b[0]", "v1.b[1]", "v1.b[2]", "v1.b[3]", "v1.b[4]", "v1.b[5]", "v1.b[6]", "v1.b[7]", 31 | "v1.b[8]", "v1.b[9]", "v1.b[10]", "v1.b[11]", "v1.b[12]", "v1.b[13]", "v1.b[14]", "v1.b[15]", 32 | "v2.b[0]", "v2.b[1]", "v2.b[2]", "v2.b[3]", "v2.b[4]", "v2.b[5]", "v2.b[6]", "v2.b[7]", 33 | "v2.b[8]", "v2.b[9]", "v2.b[10]", "v2.b[11]", "v2.b[12]", "v2.b[13]", "v2.b[14]", "v2.b[15]", 34 | "v3.b[0]", "v3.b[1]", "v3.b[2]", "v3.b[3]", "v3.b[4]", "v3.b[5]", "v3.b[6]", "v3.b[7]", 35 | "v3.b[8]", "v3.b[9]", "v3.b[10]", "v3.b[11]", "v3.b[12]", "v3.b[13]", "v3.b[14]", "v3.b[15]", 36 | "v4.b[0]", "v4.b[1]", "v4.b[2]", "v4.b[3]", "v4.b[4]", "v4.b[5]", "v4.b[6]", "v4.b[7]", 37 | "v4.b[8]", "v4.b[9]", "v4.b[10]", "v4.b[11]", "v4.b[12]", "v4.b[13]", "v4.b[14]", "v4.b[15]", 38 | "v5.b[0]", "v5.b[1]", "v5.b[2]", "v5.b[3]", "v5.b[4]", "v5.b[5]", "v5.b[6]", "v5.b[7]", 39 | "v5.b[8]", "v5.b[9]", "v5.b[10]", "v5.b[11]", "v5.b[12]", "v5.b[13]", "v5.b[14]", "v5.b[15]", 40 | "v6.b[0]", "v6.b[1]", "v6.b[2]", "v6.b[3]", "v6.b[4]", "v6.b[5]", "v6.b[6]", "v6.b[7]", 41 | "v6.b[8]", "v6.b[9]", "v6.b[10]", "v6.b[11]", "v6.b[12]", "v6.b[13]", "v6.b[14]", "v6.b[15]", 42 | "v7.b[0]", "v7.b[1]", "v7.b[2]", "v7.b[3]", "v7.b[4]", "v7.b[5]", "v7.b[6]", "v7.b[7]", 43 | "v7.b[8]", "v7.b[9]", "v7.b[10]", "v7.b[11]", "v7.b[12]", "v7.b[13]", "v7.b[14]", "v7.b[15]", 44 | "v8.b[0]", "v8.b[1]", "v8.b[2]", "v8.b[3]", "v8.b[4]", "v8.b[5]", "v8.b[6]", "v8.b[7]", 45 | "v8.b[8]", "v8.b[9]", "v8.b[10]", "v8.b[11]", "v8.b[12]", "v8.b[13]", "v8.b[14]", "v8.b[15]", 46 | "v9.b[0]", "v9.b[1]", "v9.b[2]", "v9.b[3]", "v9.b[4]", "v9.b[5]", "v9.b[6]", "v9.b[7]", 47 | "v9.b[8]", "v9.b[9]", "v9.b[10]", "v9.b[11]", "v9.b[12]", "v9.b[13]", "v9.b[14]", "v9.b[15]", 48 | "v10.b[0]", "v10.b[1]", "v10.b[2]", "v10.b[3]", "v10.b[4]", "v10.b[5]", "v10.b[6]", "v10.b[7]", 49 | "v10.b[8]", "v10.b[9]", "v10.b[10]", "v10.b[11]", "v10.b[12]", "v10.b[13]", "v10.b[14]", 50 | "v10.b[15]", "v11.b[0]", "v11.b[1]", "v11.b[2]", "v11.b[3]", "v11.b[4]", "v11.b[5]", "v11.b[6]", 51 | "v11.b[7]", "v11.b[8]", "v11.b[9]", "v11.b[10]", "v11.b[11]", "v11.b[12]", "v11.b[13]", 52 | "v11.b[14]", "v11.b[15]", "v12.b[0]", "v12.b[1]", "v12.b[2]", "v12.b[3]", "v12.b[4]", 53 | "v12.b[5]", "v12.b[6]", "v12.b[7]", "v12.b[8]", "v12.b[9]", "v12.b[10]", "v12.b[11]", 54 | "v12.b[12]", "v12.b[13]", "v12.b[14]", "v12.b[15]", "v13.b[0]", "v13.b[1]", "v13.b[2]", 55 | "v13.b[3]", "v13.b[4]", "v13.b[5]", "v13.b[6]", "v13.b[7]", "v13.b[8]", "v13.b[9]", "v13.b[10]", 56 | "v13.b[11]", "v13.b[12]", "v13.b[13]", "v13.b[14]", "v13.b[15]", "v14.b[0]", "v14.b[1]", 57 | "v14.b[2]", "v14.b[3]", "v14.b[4]", "v14.b[5]", "v14.b[6]", "v14.b[7]", "v14.b[8]", "v14.b[9]", 58 | "v14.b[10]", "v14.b[11]", "v14.b[12]", "v14.b[13]", "v14.b[14]", "v14.b[15]", "v15.b[0]", 59 | "v15.b[1]", "v15.b[2]", "v15.b[3]", "v15.b[4]", "v15.b[5]", "v15.b[6]", "v15.b[7]", "v15.b[8]", 60 | "v15.b[9]", "v15.b[10]", "v15.b[11]", "v15.b[12]", "v15.b[13]", "v15.b[14]", "v15.b[15]", 61 | "v16.b[0]", "v16.b[1]", "v16.b[2]", "v16.b[3]", "v16.b[4]", "v16.b[5]", "v16.b[6]", "v16.b[7]", 62 | "v16.b[8]", "v16.b[9]", "v16.b[10]", "v16.b[11]", "v16.b[12]", "v16.b[13]", "v16.b[14]", 63 | "v16.b[15]", "v17.b[0]", "v17.b[1]", "v17.b[2]", "v17.b[3]", "v17.b[4]", "v17.b[5]", "v17.b[6]", 64 | "v17.b[7]", "v17.b[8]", "v17.b[9]", "v17.b[10]", "v17.b[11]", "v17.b[12]", "v17.b[13]", 65 | "v17.b[14]", "v17.b[15]", "v18.b[0]", "v18.b[1]", "v18.b[2]", "v18.b[3]", "v18.b[4]", 66 | "v18.b[5]", "v18.b[6]", "v18.b[7]", "v18.b[8]", "v18.b[9]", "v18.b[10]", "v18.b[11]", 67 | "v18.b[12]", "v18.b[13]", "v18.b[14]", "v18.b[15]", "v19.b[0]", "v19.b[1]", "v19.b[2]", 68 | "v19.b[3]", "v19.b[4]", "v19.b[5]", "v19.b[6]", "v19.b[7]", "v19.b[8]", "v19.b[9]", "v19.b[10]", 69 | "v19.b[11]", "v19.b[12]", "v19.b[13]", "v19.b[14]", "v19.b[15]", "v20.b[0]", "v20.b[1]", 70 | "v20.b[2]", "v20.b[3]", "v20.b[4]", "v20.b[5]", "v20.b[6]", "v20.b[7]", "v20.b[8]", "v20.b[9]", 71 | "v20.b[10]", "v20.b[11]", "v20.b[12]", "v20.b[13]", "v20.b[14]", "v20.b[15]", "v21.b[0]", 72 | "v21.b[1]", "v21.b[2]", "v21.b[3]", "v21.b[4]", "v21.b[5]", "v21.b[6]", "v21.b[7]", "v21.b[8]", 73 | "v21.b[9]", "v21.b[10]", "v21.b[11]", "v21.b[12]", "v21.b[13]", "v21.b[14]", "v21.b[15]", 74 | "v22.b[0]", "v22.b[1]", "v22.b[2]", "v22.b[3]", "v22.b[4]", "v22.b[5]", "v22.b[6]", "v22.b[7]", 75 | "v22.b[8]", "v22.b[9]", "v22.b[10]", "v22.b[11]", "v22.b[12]", "v22.b[13]", "v22.b[14]", 76 | "v22.b[15]", "v23.b[0]", "v23.b[1]", "v23.b[2]", "v23.b[3]", "v23.b[4]", "v23.b[5]", "v23.b[6]", 77 | "v23.b[7]", "v23.b[8]", "v23.b[9]", "v23.b[10]", "v23.b[11]", "v23.b[12]", "v23.b[13]", 78 | "v23.b[14]", "v23.b[15]", "v24.b[0]", "v24.b[1]", "v24.b[2]", "v24.b[3]", "v24.b[4]", 79 | "v24.b[5]", "v24.b[6]", "v24.b[7]", "v24.b[8]", "v24.b[9]", "v24.b[10]", "v24.b[11]", 80 | "v24.b[12]", "v24.b[13]", "v24.b[14]", "v24.b[15]", "v25.b[0]", "v25.b[1]", "v25.b[2]", 81 | "v25.b[3]", "v25.b[4]", "v25.b[5]", "v25.b[6]", "v25.b[7]", "v25.b[8]", "v25.b[9]", "v25.b[10]", 82 | "v25.b[11]", "v25.b[12]", "v25.b[13]", "v25.b[14]", "v25.b[15]", "v26.b[0]", "v26.b[1]", 83 | "v26.b[2]", "v26.b[3]", "v26.b[4]", "v26.b[5]", "v26.b[6]", "v26.b[7]", "v26.b[8]", "v26.b[9]", 84 | "v26.b[10]", "v26.b[11]", "v26.b[12]", "v26.b[13]", "v26.b[14]", "v26.b[15]", "v27.b[0]", 85 | "v27.b[1]", "v27.b[2]", "v27.b[3]", "v27.b[4]", "v27.b[5]", "v27.b[6]", "v27.b[7]", "v27.b[8]", 86 | "v27.b[9]", "v27.b[10]", "v27.b[11]", "v27.b[12]", "v27.b[13]", "v27.b[14]", "v27.b[15]", 87 | "v28.b[0]", "v28.b[1]", "v28.b[2]", "v28.b[3]", "v28.b[4]", "v28.b[5]", "v28.b[6]", "v28.b[7]", 88 | "v28.b[8]", "v28.b[9]", "v28.b[10]", "v28.b[11]", "v28.b[12]", "v28.b[13]", "v28.b[14]", 89 | "v28.b[15]", "v29.b[0]", "v29.b[1]", "v29.b[2]", "v29.b[3]", "v29.b[4]", "v29.b[5]", "v29.b[6]", 90 | "v29.b[7]", "v29.b[8]", "v29.b[9]", "v29.b[10]", "v29.b[11]", "v29.b[12]", "v29.b[13]", 91 | "v29.b[14]", "v29.b[15]", "v30.b[0]", "v30.b[1]", "v30.b[2]", "v30.b[3]", "v30.b[4]", 92 | "v30.b[5]", "v30.b[6]", "v30.b[7]", "v30.b[8]", "v30.b[9]", "v30.b[10]", "v30.b[11]", 93 | "v30.b[12]", "v30.b[13]", "v30.b[14]", "v30.b[15]", "v31.b[0]", "v31.b[1]", "v31.b[2]", 94 | "v31.b[3]", "v31.b[4]", "v31.b[5]", "v31.b[6]", "v31.b[7]", "v31.b[8]", "v31.b[9]", "v31.b[10]", 95 | "v31.b[11]", "v31.b[12]", "v31.b[13]", "v31.b[14]", "v31.b[15]", 96 | // H vectors 97 | "v0.h[0]", "v0.h[1]", "v0.h[2]", "v0.h[3]", "v0.h[4]", "v0.h[5]", "v0.h[6]", "v0.h[7]", 98 | "v1.h[0]", "v1.h[1]", "v1.h[2]", "v1.h[3]", "v1.h[4]", "v1.h[5]", "v1.h[6]", "v1.h[7]", 99 | "v2.h[0]", "v2.h[1]", "v2.h[2]", "v2.h[3]", "v2.h[4]", "v2.h[5]", "v2.h[6]", "v2.h[7]", 100 | "v3.h[0]", "v3.h[1]", "v3.h[2]", "v3.h[3]", "v3.h[4]", "v3.h[5]", "v3.h[6]", "v3.h[7]", 101 | "v4.h[0]", "v4.h[1]", "v4.h[2]", "v4.h[3]", "v4.h[4]", "v4.h[5]", "v4.h[6]", "v4.h[7]", 102 | "v5.h[0]", "v5.h[1]", "v5.h[2]", "v5.h[3]", "v5.h[4]", "v5.h[5]", "v5.h[6]", "v5.h[7]", 103 | "v6.h[0]", "v6.h[1]", "v6.h[2]", "v6.h[3]", "v6.h[4]", "v6.h[5]", "v6.h[6]", "v6.h[7]", 104 | "v7.h[0]", "v7.h[1]", "v7.h[2]", "v7.h[3]", "v7.h[4]", "v7.h[5]", "v7.h[6]", "v7.h[7]", 105 | "v8.h[0]", "v8.h[1]", "v8.h[2]", "v8.h[3]", "v8.h[4]", "v8.h[5]", "v8.h[6]", "v8.h[7]", 106 | "v9.h[0]", "v9.h[1]", "v9.h[2]", "v9.h[3]", "v9.h[4]", "v9.h[5]", "v9.h[6]", "v9.h[7]", 107 | "v10.h[0]", "v10.h[1]", "v10.h[2]", "v10.h[3]", "v10.h[4]", "v10.h[5]", "v10.h[6]", "v10.h[7]", 108 | "v11.h[0]", "v11.h[1]", "v11.h[2]", "v11.h[3]", "v11.h[4]", "v11.h[5]", "v11.h[6]", "v11.h[7]", 109 | "v12.h[0]", "v12.h[1]", "v12.h[2]", "v12.h[3]", "v12.h[4]", "v12.h[5]", "v12.h[6]", "v12.h[7]", 110 | "v13.h[0]", "v13.h[1]", "v13.h[2]", "v13.h[3]", "v13.h[4]", "v13.h[5]", "v13.h[6]", "v13.h[7]", 111 | "v14.h[0]", "v14.h[1]", "v14.h[2]", "v14.h[3]", "v14.h[4]", "v14.h[5]", "v14.h[6]", "v14.h[7]", 112 | "v15.h[0]", "v15.h[1]", "v15.h[2]", "v15.h[3]", "v15.h[4]", "v15.h[5]", "v15.h[6]", "v15.h[7]", 113 | "v16.h[0]", "v16.h[1]", "v16.h[2]", "v16.h[3]", "v16.h[4]", "v16.h[5]", "v16.h[6]", "v16.h[7]", 114 | "v17.h[0]", "v17.h[1]", "v17.h[2]", "v17.h[3]", "v17.h[4]", "v17.h[5]", "v17.h[6]", "v17.h[7]", 115 | "v18.h[0]", "v18.h[1]", "v18.h[2]", "v18.h[3]", "v18.h[4]", "v18.h[5]", "v18.h[6]", "v18.h[7]", 116 | "v19.h[0]", "v19.h[1]", "v19.h[2]", "v19.h[3]", "v19.h[4]", "v19.h[5]", "v19.h[6]", "v19.h[7]", 117 | "v20.h[0]", "v20.h[1]", "v20.h[2]", "v20.h[3]", "v20.h[4]", "v20.h[5]", "v20.h[6]", "v20.h[7]", 118 | "v21.h[0]", "v21.h[1]", "v21.h[2]", "v21.h[3]", "v21.h[4]", "v21.h[5]", "v21.h[6]", "v21.h[7]", 119 | "v22.h[0]", "v22.h[1]", "v22.h[2]", "v22.h[3]", "v22.h[4]", "v22.h[5]", "v22.h[6]", "v22.h[7]", 120 | "v23.h[0]", "v23.h[1]", "v23.h[2]", "v23.h[3]", "v23.h[4]", "v23.h[5]", "v23.h[6]", "v23.h[7]", 121 | "v24.h[0]", "v24.h[1]", "v24.h[2]", "v24.h[3]", "v24.h[4]", "v24.h[5]", "v24.h[6]", "v24.h[7]", 122 | "v25.h[0]", "v25.h[1]", "v25.h[2]", "v25.h[3]", "v25.h[4]", "v25.h[5]", "v25.h[6]", "v25.h[7]", 123 | "v26.h[0]", "v26.h[1]", "v26.h[2]", "v26.h[3]", "v26.h[4]", "v26.h[5]", "v26.h[6]", "v26.h[7]", 124 | "v27.h[0]", "v27.h[1]", "v27.h[2]", "v27.h[3]", "v27.h[4]", "v27.h[5]", "v27.h[6]", "v27.h[7]", 125 | "v28.h[0]", "v28.h[1]", "v28.h[2]", "v28.h[3]", "v28.h[4]", "v28.h[5]", "v28.h[6]", "v28.h[7]", 126 | "v29.h[0]", "v29.h[1]", "v29.h[2]", "v29.h[3]", "v29.h[4]", "v29.h[5]", "v29.h[6]", "v29.h[7]", 127 | "v30.h[0]", "v30.h[1]", "v30.h[2]", "v30.h[3]", "v30.h[4]", "v30.h[5]", "v30.h[6]", "v30.h[7]", 128 | "v31.h[0]", "v31.h[1]", "v31.h[2]", "v31.h[3]", "v31.h[4]", "v31.h[5]", "v31.h[6]", "v31.h[7]", 129 | // S vectors 130 | "v0.s[0]", "v0.s[1]", "v0.s[2]", "v0.s[3]", "v1.s[0]", "v1.s[1]", "v1.s[2]", "v1.s[3]", 131 | "v2.s[0]", "v2.s[1]", "v2.s[2]", "v2.s[3]", "v3.s[0]", "v3.s[1]", "v3.s[2]", "v3.s[3]", 132 | "v4.s[0]", "v4.s[1]", "v4.s[2]", "v4.s[3]", "v5.s[0]", "v5.s[1]", "v5.s[2]", "v5.s[3]", 133 | "v6.s[0]", "v6.s[1]", "v6.s[2]", "v6.s[3]", "v7.s[0]", "v7.s[1]", "v7.s[2]", "v7.s[3]", 134 | "v8.s[0]", "v8.s[1]", "v8.s[2]", "v8.s[3]", "v9.s[0]", "v9.s[1]", "v9.s[2]", "v9.s[3]", 135 | "v10.s[0]", "v10.s[1]", "v10.s[2]", "v10.s[3]", "v11.s[0]", "v11.s[1]", "v11.s[2]", "v11.s[3]", 136 | "v12.s[0]", "v12.s[1]", "v12.s[2]", "v12.s[3]", "v13.s[0]", "v13.s[1]", "v13.s[2]", "v13.s[3]", 137 | "v14.s[0]", "v14.s[1]", "v14.s[2]", "v14.s[3]", "v15.s[0]", "v15.s[1]", "v15.s[2]", "v15.s[3]", 138 | "v16.s[0]", "v16.s[1]", "v16.s[2]", "v16.s[3]", "v17.s[0]", "v17.s[1]", "v17.s[2]", "v17.s[3]", 139 | "v18.s[0]", "v18.s[1]", "v18.s[2]", "v18.s[3]", "v19.s[0]", "v19.s[1]", "v19.s[2]", "v19.s[3]", 140 | "v20.s[0]", "v20.s[1]", "v20.s[2]", "v20.s[3]", "v21.s[0]", "v21.s[1]", "v21.s[2]", "v21.s[3]", 141 | "v22.s[0]", "v22.s[1]", "v22.s[2]", "v22.s[3]", "v23.s[0]", "v23.s[1]", "v23.s[2]", "v23.s[3]", 142 | "v24.s[0]", "v24.s[1]", "v24.s[2]", "v24.s[3]", "v25.s[0]", "v25.s[1]", "v25.s[2]", "v25.s[3]", 143 | "v26.s[0]", "v26.s[1]", "v26.s[2]", "v26.s[3]", "v27.s[0]", "v27.s[1]", "v27.s[2]", "v27.s[3]", 144 | "v28.s[0]", "v28.s[1]", "v28.s[2]", "v28.s[3]", "v29.s[0]", "v29.s[1]", "v29.s[2]", "v29.s[3]", 145 | "v30.s[0]", "v30.s[1]", "v30.s[2]", "v30.s[3]", "v31.s[0]", "v31.s[1]", "v31.s[2]", "v31.s[3]", 146 | // D vectors 147 | "v0.d[0]", "v0.d[1]", "v1.d[0]", "v1.d[1]", "v2.d[0]", "v2.d[1]", "v3.d[0]", "v3.d[1]", 148 | "v4.d[0]", "v4.d[1]", "v5.d[0]", "v5.d[1]", "v6.d[0]", "v6.d[1]", "v7.d[0]", "v7.d[1]", 149 | "v8.d[0]", "v8.d[1]", "v9.d[0]", "v9.d[1]", "v10.d[0]", "v10.d[1]", "v11.d[0]", "v11.d[1]", 150 | "v12.d[0]", "v12.d[1]", "v13.d[0]", "v13.d[1]", "v14.d[0]", "v14.d[1]", "v15.d[0]", "v15.d[1]", 151 | "v16.d[0]", "v16.d[1]", "v17.d[0]", "v17.d[1]", "v18.d[0]", "v18.d[1]", "v19.d[0]", "v19.d[1]", 152 | "v20.d[0]", "v20.d[1]", "v21.d[0]", "v21.d[1]", "v22.d[0]", "v22.d[1]", "v23.d[0]", "v23.d[1]", 153 | "v24.d[0]", "v24.d[1]", "v25.d[0]", "v25.d[1]", "v26.d[0]", "v26.d[1]", "v27.d[0]", "v27.d[1]", 154 | "v28.d[0]", "v28.d[1]", "v29.d[0]", "v29.d[1]", "v30.d[0]", "v30.d[1]", "v31.d[0]", "v31.d[1]", 155 | // SVE 156 | "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", 157 | "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", 158 | "z28", "z29", "z30", "z31", 159 | /* scalable predicate registers */ 160 | "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", 161 | "p15", "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", 162 | "p28", "p29", "p30", "p31", 163 | /* prefetch operations (TODO: remove these as registers) */ 164 | "pldl1keep", "pldl1strm", "pldl2keep", "pldl2strm", "pldl3keep", "pldl3strm", "#0x6", "#0x7", 165 | "plil1keep", "plil1strm", "plil2keep", "plil2strm", "plil3keep", "plil3strm", "#0xe", "#0xf", 166 | "pstl1keep", "pstl1strm", "pstl2keep", "pstl2strm", "pstl3keep", "pstl3strm", "#0x16", "#0x17", 167 | "#0x18", "#0x19", "#0x1a", "#0x1b", "#0x1c", "#0x1d", "#0x1e", "#0x1f", "END"}; 168 | 169 | const char* get_register_name(enum Register r) 170 | { 171 | if (r > REG_NONE && r < REG_END) 172 | return RegisterString[r]; 173 | 174 | return ""; 175 | } 176 | 177 | size_t get_register_size(enum Register r) 178 | { 179 | // Comparison done in order of likelyhood to occur 180 | if ((r >= REG_X0 && r <= REG_SP) || (r >= REG_D0 && r <= REG_D31)) 181 | return 8; 182 | else if ((r >= REG_W0 && r <= REG_WSP) || (r >= REG_S0 && r <= REG_S31)) 183 | return 4; 184 | else if (r >= REG_B0 && r <= REG_B31) 185 | return 1; 186 | else if (r >= REG_H0 && r <= REG_H31) 187 | return 2; 188 | else if ((r >= REG_Q0 && r <= REG_Q31) || (r >= REG_V0 && r <= REG_V31)) 189 | return 16; 190 | else if (r >= REG_V0_B0 && r <= REG_V31_B15) 191 | return 1; 192 | else if (r >= REG_V0_H0 && r <= REG_V31_H7) 193 | return 2; 194 | else if (r >= REG_V0_S0 && r <= REG_V31_S3) 195 | return 4; 196 | else if (r >= REG_V0_D0 && r <= REG_V31_D1) 197 | return 8; 198 | return 0; 199 | } 200 | -------------------------------------------------------------------------------- /disassembler/decode.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #include "feature_flags.h" 9 | #include "operations.h" 10 | 11 | #include "encodings_dec.h" 12 | #include "regs.h" 13 | #include "sysregs.h" 14 | 15 | #ifdef _MSC_VER 16 | #undef REG_NONE // collides with winnt's define 17 | #endif 18 | 19 | #ifdef __cplusplus 20 | #define restrict __restrict 21 | #endif 22 | 23 | typedef union { 24 | unsigned int ui; 25 | float fn; 26 | } ImmFloatUnion; 27 | 28 | /* these are used in lookup tables elsewhere, modify with caution */ 29 | enum ArrangementSpec 30 | { 31 | ARRSPEC_NONE = 0, 32 | 33 | ARRSPEC_FULL = 1, /* 128-bit v-reg unsplit, eg: REG_V0_Q0 */ 34 | 35 | /* 128 bit v-reg considered as... */ 36 | ARRSPEC_2DOUBLES = 2, /* (.2d) two 64-bit double-precision: REG_V0_D1, REG_V0_D0 */ 37 | ARRSPEC_4SINGLES = 38 | 3, /* (.4s) four 32-bit single-precision: REG_V0_S3, REG_V0_S2, REG_V0_S1, REG_V0_S0 */ 39 | ARRSPEC_8HALVES = 40 | 4, /* (.8h) eight 16-bit half-precision: REG_V0_H7, REG_V0_H6, (..., REG_V0_H0 */ 41 | ARRSPEC_16BYTES = 5, /* (.16b) sixteen 8-bit values: REG_V0_B15, REG_V0_B14, (..., REG_V0_B01 */ 42 | 43 | /* low 64-bit of v-reg considered as... */ 44 | ARRSPEC_1DOUBLE = 6, /* (.d) one 64-bit double-precision: REG_V0_D0 */ 45 | ARRSPEC_2SINGLES = 7, /* (.2s) two 32-bit single-precision: REG_V0_S1, REG_V0_S0 */ 46 | ARRSPEC_4HALVES = 47 | 8, /* (.4h) four 16-bit half-precision: REG_V0_H3, REG_V0_H2, REG_V0_H1, REG_V0_H0 */ 48 | ARRSPEC_8BYTES = 9, /* (.8b) eight 8-bit values: REG_V0_B7, REG_V0_B6, (..., REG_V0_B0 */ 49 | 50 | /* low 32-bit of v-reg considered as... */ 51 | ARRSPEC_1SINGLE = 10, /* (.s) one 32-bit single-precision: REG_V0_S0 */ 52 | ARRSPEC_2HALVES = 11, /* (.2h) two 16-bit half-precision: REG_V0_H1, REG_V0_H0 */ 53 | ARRSPEC_4BYTES = 12, /* (.4b) four 8-bit values: REG_V0_B3, REG_V0_B2, REG_V0_B1, REG_V0_B0 */ 54 | 55 | /* low 16-bit of v-reg considered as... */ 56 | ARRSPEC_1HALF = 13, /* (.h) one 16-bit half-precision: REG_V0_H0 */ 57 | 58 | /* low 8-bit of v-reg considered as... */ 59 | ARRSPEC_1BYTE = 14 /* (.b) one 8-bit byte: REG_V0_B0 */ 60 | }; 61 | 62 | enum SliceIndicator 63 | { 64 | SLICE_NONE = -1, 65 | SLICE_HORIZONTAL = 0, /* same values as read from fields32 */ 66 | SLICE_VERTICAL = 1 67 | }; 68 | 69 | //----------------------------------------------------------------------------- 70 | // decode return values 71 | //----------------------------------------------------------------------------- 72 | 73 | #define DECODE_STATUS_OK 0 // success! the resulting named encoding is accurate 74 | #define DECODE_STATUS_RESERVED -1 // spec says this space is reserved, eg: RESERVED_36_asisdsame 75 | #define DECODE_STATUS_UNMATCHED -2 // decoding logic fell through the spec's checks 76 | #define DECODE_STATUS_UNALLOCATED \ 77 | -3 // spec says this space is unallocated, eg: UNALLOCATED_10_branch_reg 78 | #define DECODE_STATUS_UNDEFINED \ 79 | -4 // spec says this encoding is undefined, often due to a disallowed field 80 | // or a missing feature, eg: "if !HaveBF16Ext() then UNDEFINED;" 81 | #define DECODE_STATUS_END_OF_INSTRUCTION \ 82 | -5 // spec decode EndOfInstruction(), instruction executes as NOP 83 | #define DECODE_STATUS_LOST -6 // descended past checks, ie: "SEE encoding_up_higher" 84 | #define DECODE_STATUS_UNREACHABLE -7 // ran into pcode Unreachable() 85 | #define DECODE_STATUS_ASSERT_FAILED -8 // failed an assert 86 | #define DECODE_STATUS_ERROR_OPERANDS -9 87 | 88 | //----------------------------------------------------------------------------- 89 | // floating point condition register values 90 | //----------------------------------------------------------------------------- 91 | 92 | #define FPCR_AHP ((uint64_t)1 << 26) 93 | #define FPCR_DN ((uint64_t)1 << 25) 94 | #define FPCR_FZ ((uint64_t)1 << 24) 95 | #define FPCR_RMode (uint64_t)0xC00000 // [23,22] 96 | #define FPCR_Stride (uint64_t)0x300000 // [21,20] 97 | #define FPCR_FZ16 ((uint64_t)1 << 19) 98 | #define FPCR_Len (uint64_t)0x30000 // [18:16] 99 | #define FPCR_IDE ((uint64_t)1 << 15) 100 | #define FPCR_IXE ((uint64_t)1 << 12) 101 | #define FPCR_UFE ((uint64_t)1 << 11) 102 | #define FPCR_OFE ((uint64_t)1 << 10) 103 | #define FPCR_DZE ((uint64_t)1 << 9) 104 | #define FPCR_IOE ((uint64_t)1 << 8) 105 | 106 | #define FPCR_GET_AHP(X) SLICE(X, 26, 26) 107 | #define FPCR_GET_DN(X) SLICE(X, 25, 25) 108 | #define FPCR_GET_FZ(X) SLICE(X, 24, 24) 109 | #define FPCR_GET_RMode(X) SLICE(X, 23, 22) 110 | #define FPCR_GET_Stride(X) SLICE(X, 21, 20) 111 | #define FPCR_GET_FZ16(X) SLICE(X, 19, 19) 112 | #define FPCR_GET_Len(X) SLICE(X, 18, 16) 113 | #define FPCR_GET_IDE(X) SLICE(X, 15, 15) 114 | #define FPCR_GET_IXE(X) SLICE(X, 12, 12) 115 | #define FPCR_GET_UFE(X) SLICE(X, 11, 11) 116 | #define FPCR_GET_OFE(X) SLICE(X, 10, 10) 117 | #define FPCR_GET_DZE(X) SLICE(X, 9, 9) 118 | #define FPCR_GET_IOE(X) SLICE(X, 8, 8) 119 | 120 | //----------------------------------------------------------------------------- 121 | // disassembly context (INPUT into disassembler) 122 | //----------------------------------------------------------------------------- 123 | 124 | typedef struct context_ 125 | { 126 | uint32_t insword; 127 | uint64_t address; 128 | uint64_t features0; // bitmask of ARCH_FEATURE_XXX 129 | uint64_t features1; // bitmask of ARCH_FEATURE_XXX 130 | // uint32_t exception_level; // used by AArch64.CheckSystemAccess() 131 | // uint32_t security_state; 132 | uint8_t pstate_btype; // used by BTypeCompatible_BTI() 133 | uint8_t pstate_el; 134 | uint8_t pstate_uao; 135 | bool BTypeCompatible; 136 | uint8_t BTypeNext; 137 | bool halted; // is CPU halted? used by Halted() 138 | uint64_t FPCR; // floating point control register 139 | bool EDSCR_HDE; // External Debug Status and Control Register, Halting debug enable 140 | 141 | /* specification scratchpad: ~300 possible named fields */ 142 | uint64_t A; 143 | uint64_t ADD; 144 | uint64_t AccType_NORMAL; 145 | uint64_t AccType_STREAM; 146 | uint64_t AccType_UNPRIV; 147 | uint64_t AccType_VEC; 148 | uint64_t AccType_VECSTREAM; 149 | uint64_t B; 150 | uint64_t C; 151 | uint64_t CRm; 152 | uint64_t CRn; 153 | uint64_t dst, D; 154 | uint64_t E; 155 | uint64_t H; 156 | uint64_t HCR_EL2_E2H, HCR_EL2_NV, HCR_EL2_NV1, HCR_EL2_TGE; 157 | uint64_t k; 158 | uint64_t L; 159 | uint64_t LL; 160 | uint64_t M; 161 | uint64_t N; 162 | uint64_t O; 163 | uint64_t Op0, Op3; 164 | uint64_t P; 165 | uint64_t Pd, Pdm, Pdn, Pg, Pm, Pn, Pt; 166 | uint64_t Q, Qa, Qd, Qm, Qn, Qt, Qt2; 167 | uint64_t reason, retry; 168 | uint64_t R, Ra, Rd, Rdn, Rm, Rmhi, Rn, Rs, Rt, Rt2, Rv; 169 | uint64_t s1, s2, sel1, sel2, S, Sa, Sd, Sm, Sn, St, St2; 170 | uint64_t S10; 171 | uint64_t SCTLR_EL1_UMA; 172 | uint64_t T; 173 | uint64_t U; 174 | uint64_t US; 175 | uint64_t V, Va, Vd, Vdn, Vm, Vn, Vt, Vt2; 176 | uint64_t W, Wa, Wd, Wdn, Wm, Wn, Ws, Wt, Wt2; 177 | uint64_t Xa, Xd, Xdn, Xm, Xn, Xs, Xt, Xt2; 178 | uint64_t Z, Za, Zd, Zda, Zdn, Zm, Zn, Zt; 179 | uint64_t a; 180 | uint64_t abs; 181 | uint64_t ac; 182 | uint64_t acc; 183 | uint64_t acctype; 184 | uint64_t accumulate; 185 | uint64_t alias; 186 | uint64_t amount; 187 | uint64_t and_test; 188 | uint64_t asimdimm; 189 | uint64_t b; 190 | uint64_t b40; 191 | uint64_t b5; 192 | uint64_t bit_pos; 193 | uint64_t bit_val; 194 | uint64_t branch_type; 195 | uint64_t c; 196 | uint64_t cmode; 197 | uint64_t cmp, cmph, cmpl, cmp_eq, cmp_with_zero; 198 | uint64_t comment; 199 | uint64_t comparison; 200 | uint64_t cond; /* careful! this is the pcode scratchpad .cond, NOT the .cond field of a struct 201 | InstructionOperand */ 202 | uint64_t condition; 203 | uint64_t container_size; 204 | uint64_t containers; 205 | uint64_t countop; 206 | uint64_t crc32c; 207 | uint64_t csize; 208 | uint64_t d, da, data, datasize, double_table; 209 | uint64_t dtype, dtypeh, dtypel; 210 | uint64_t d_esize; 211 | uint64_t decrypt; 212 | uint64_t destsize; 213 | uint64_t dm; 214 | uint64_t dn; 215 | uint64_t domain; 216 | uint64_t dst_index; 217 | uint64_t dst_unsigned; 218 | uint64_t dstsize; 219 | uint64_t e; 220 | uint64_t elements; 221 | uint64_t elements_per_container; 222 | uint64_t else_inc; 223 | uint64_t else_inv; 224 | uint64_t elsize; 225 | uint64_t eq; 226 | uint64_t esize; 227 | uint64_t exact; 228 | uint64_t extend; 229 | uint64_t extend_type; 230 | uint64_t f, ff; 231 | uint64_t field; 232 | uint64_t flags; 233 | uint64_t fltsize; 234 | uint64_t fpop; 235 | uint64_t fracbits; 236 | uint64_t ftype; 237 | uint64_t g; 238 | uint64_t h; 239 | uint64_t has_result; 240 | uint64_t hi; 241 | uint64_t hw; 242 | uint64_t i, i1, i2, i2h, i2l, i3h, i3l; 243 | uint64_t idxdsize; 244 | uint64_t imm; 245 | uint64_t imm1; 246 | uint64_t imm12; 247 | uint64_t imm13; 248 | uint64_t imm14; 249 | uint64_t imm16; 250 | uint64_t imm19; 251 | uint64_t imm2; 252 | uint64_t imm26; 253 | uint64_t imm3; 254 | uint64_t imm4; 255 | uint64_t imm5; 256 | uint64_t imm5b; 257 | uint64_t imm6; 258 | uint64_t imm64; 259 | uint64_t imm7; 260 | uint64_t imm8; 261 | uint64_t imm8h; 262 | uint64_t imm8l; 263 | uint64_t imm9; 264 | uint64_t imm9h; 265 | uint64_t imm9l; 266 | uint64_t immb; 267 | uint64_t immh; 268 | uint64_t immhi; 269 | uint64_t immlo; 270 | uint64_t immr; 271 | uint64_t imms; 272 | uint64_t index; 273 | uint64_t init_scale; 274 | uint64_t intsize; 275 | uint64_t int_U; 276 | uint64_t invert; 277 | uint64_t inzero; 278 | uint64_t isBefore; 279 | uint64_t is_tbl; 280 | uint64_t iszero; 281 | uint64_t ldacctype; 282 | uint64_t len; 283 | uint64_t level; 284 | uint64_t lsb; 285 | uint64_t lt; 286 | uint64_t m; 287 | uint64_t mask; 288 | uint64_t mbytes; 289 | uint64_t memop; 290 | uint64_t merging; 291 | uint64_t min; 292 | uint64_t min_EL; 293 | uint64_t minimum; 294 | uint64_t msb; 295 | uint64_t msize; 296 | uint64_t msz; 297 | uint64_t mulx_op; 298 | uint64_t n; 299 | uint64_t ne; 300 | uint64_t need_secure; 301 | uint64_t neg; 302 | uint64_t neg_i; 303 | uint64_t neg_r; 304 | uint64_t negated; 305 | uint64_t nreg; 306 | uint64_t nzcv; 307 | uint64_t nXS; 308 | uint64_t o0, o1, o2, o3; 309 | uint64_t offs_size; 310 | uint64_t offs_unsigned; 311 | uint64_t offset; 312 | uint64_t op1_neg; 313 | uint64_t op1_unsigned; 314 | uint64_t op, op0, op1, op2, op3, op4, op21, op31, op54; 315 | uint64_t op2_unsigned; 316 | uint64_t op3_neg; 317 | uint64_t opa_neg; 318 | uint64_t opc; 319 | uint64_t opc2; 320 | uint64_t opcode, opcode2; 321 | uint64_t operand; 322 | uint64_t operation_; 323 | uint64_t opt, option; 324 | uint64_t osize; 325 | uint64_t pac; 326 | uint64_t page; 327 | uint64_t pair; 328 | uint64_t pairs; 329 | uint64_t part; 330 | uint64_t part1; 331 | uint64_t pat; 332 | uint64_t pattern; 333 | uint64_t poly; 334 | uint64_t pos; 335 | uint64_t position; 336 | uint64_t postindex; 337 | uint64_t pref_hint; 338 | uint64_t prfop; 339 | uint64_t ptype; 340 | uint64_t rd; 341 | uint64_t read; 342 | uint64_t regs; 343 | uint64_t regsize; 344 | uint64_t replicate; 345 | uint64_t rmode; 346 | uint64_t rot; 347 | uint64_t round; 348 | uint64_t rounding; 349 | uint64_t rpt; 350 | uint64_t rsize; 351 | uint64_t rn_unknown, rt_unknown; 352 | uint64_t rw; 353 | uint64_t s; 354 | uint64_t s_esize; 355 | uint64_t saturating; 356 | uint64_t scale; 357 | uint64_t sel; 358 | uint64_t sel_a; 359 | uint64_t sel_b; 360 | uint64_t selem; 361 | uint64_t setflags; 362 | uint64_t sf; 363 | uint64_t sh; 364 | uint64_t shift; 365 | uint64_t shift_amount; 366 | uint64_t shift_type; 367 | uint64_t signal_all_nans; 368 | uint64_t signed_; 369 | uint64_t simm7; 370 | uint64_t size; 371 | uint64_t source_is_sp; 372 | uint64_t src_index; 373 | uint64_t src_unsigned; 374 | uint64_t srcsize; 375 | uint64_t ssize, ssz; 376 | uint64_t stacctype; 377 | uint64_t stream; 378 | uint64_t sub_i; 379 | uint64_t sub_op; 380 | uint64_t sub_r; 381 | uint64_t swsize; 382 | uint64_t sys_crm; 383 | uint64_t sys_crn; 384 | uint64_t sys_op0; 385 | uint64_t sys_op1; 386 | uint64_t sys_op2; 387 | uint64_t sz; 388 | uint64_t t, t2, tb; 389 | uint64_t tag_checked; 390 | uint64_t tag_offset; 391 | uint64_t target_level; 392 | uint64_t tmask; 393 | uint64_t tsize; 394 | uint64_t tsz; 395 | uint64_t tszh; 396 | uint64_t tszl; 397 | uint64_t types; 398 | uint64_t u0, u1; 399 | uint64_t uimm4; 400 | uint64_t uimm6; 401 | uint64_t unpriv_at_el1; 402 | uint64_t unpriv_at_el2; 403 | uint64_t uns; 404 | uint64_t unsigned_; 405 | uint64_t use_key_a; 406 | uint64_t user_access_override; 407 | uint64_t v, vertical; 408 | uint64_t wback; 409 | uint64_t wb_unknown; 410 | uint64_t wmask; 411 | uint64_t writeback; 412 | uint64_t xs; 413 | uint64_t ZAda, ZAd, ZAn, ZAt, Zk, zero_data; 414 | 415 | } context; 416 | 417 | //----------------------------------------------------------------------------- 418 | // Instruction definition (OUTPUT from disassembler) 419 | //----------------------------------------------------------------------------- 420 | 421 | enum OperandClass 422 | { // syntax example 423 | NONE = 0, // --------------------------- --------------------- 424 | IMM32 = 1, 425 | IMM64 = 2, 426 | FIMM32 = 3, 427 | STR_IMM = 4, 428 | REG = 5, 429 | MULTI_REG = 6, 430 | SYS_REG = 7, 431 | MEM_REG = 8, 432 | MEM_PRE_IDX = 9, 433 | MEM_POST_IDX = 10, 434 | MEM_OFFSET = 11, 435 | MEM_EXTENDED = 12, 436 | SME_TILE = 13, 437 | INDEXED_ELEMENT = 14, // .[{, #}] p12.d[w15, #15] 438 | ACCUM_ARRAY = 15, // ZA[, #] ZA[w13, #8] 439 | LABEL = 16, 440 | CONDITION = 17, 441 | NAME = 18, 442 | IMPLEMENTATION_SPECIFIC = 19 443 | }; 444 | 445 | enum Condition 446 | { 447 | COND_EQ, 448 | COND_NE, 449 | COND_CS, 450 | COND_CC, 451 | COND_MI, 452 | COND_PL, 453 | COND_VS, 454 | COND_VC, 455 | COND_HI, 456 | COND_LS, 457 | COND_GE, 458 | COND_LT, 459 | COND_GT, 460 | COND_LE, 461 | COND_AL, 462 | COND_NV, 463 | END_CONDITION 464 | }; 465 | 466 | enum ShiftType 467 | { 468 | ShiftType_NONE, 469 | ShiftType_LSL, 470 | ShiftType_LSR, 471 | ShiftType_ASR, 472 | ShiftType_ROR, 473 | ShiftType_UXTW, 474 | ShiftType_SXTW, 475 | ShiftType_SXTX, 476 | ShiftType_UXTX, 477 | ShiftType_SXTB, 478 | ShiftType_SXTH, 479 | ShiftType_UXTH, 480 | ShiftType_UXTB, 481 | ShiftType_MSL, 482 | ShiftType_END, 483 | }; 484 | 485 | enum Group 486 | { 487 | GROUP_UNALLOCATED, 488 | GROUP_DATA_PROCESSING_IMM, 489 | GROUP_BRANCH_EXCEPTION_SYSTEM, 490 | GROUP_LOAD_STORE, 491 | GROUP_DATA_PROCESSING_REG, 492 | GROUP_DATA_PROCESSING_SIMD, 493 | GROUP_DATA_PROCESSING_SIMD2, 494 | END_GROUP 495 | }; 496 | 497 | enum FlagEffect 498 | { 499 | FLAGEFFECT_NONE=0, // doesn't set flags 500 | FLAGEFFECT_SETS=1, // sets flags, but unknown which type 501 | FLAGEFFECT_SETS_NORMAL=2, // sets flags after normal comparison 502 | FLAGEFFECT_SETS_FLOAT=3 // sets flags after float comparison 503 | }; 504 | 505 | #ifndef __cplusplus 506 | typedef enum SystemReg SystemReg; 507 | typedef enum OperandClass OperandClass; 508 | typedef enum Register Register; 509 | typedef enum Condition Condition; 510 | typedef enum ShiftType ShiftType; 511 | typedef enum Operation Operation; 512 | typedef enum Group Group; 513 | typedef enum ArrangementSpec ArrangementSpec; 514 | typedef enum SliceIndicator SliceIndicator; 515 | #endif 516 | 517 | #define MAX_REGISTERS 5 518 | #define MAX_NAME 16 519 | 520 | struct InstructionOperand 521 | { 522 | OperandClass operandClass; 523 | ArrangementSpec arrSpec; 524 | Register reg[MAX_REGISTERS]; 525 | 526 | /* for class CONDITION */ 527 | Condition cond; 528 | 529 | /* for class IMPLEMENTATION_SPECIFIC */ 530 | uint8_t implspec[MAX_REGISTERS]; 531 | 532 | /* for class SYS_REG */ 533 | SystemReg sysreg; 534 | 535 | bool laneUsed; 536 | uint32_t lane; 537 | uint64_t immediate; 538 | ShiftType shiftType; 539 | bool shiftValueUsed; 540 | uint32_t shiftValue; 541 | ShiftType extend; 542 | bool signedImm; 543 | char pred_qual; // predicate register qualifier ('z' or 'm') 544 | bool mul_vl; // whether MEM_OFFSET has the offset "mul vl" 545 | 546 | /* for class SME_TILE */ 547 | uint16_t tile; 548 | SliceIndicator slice; 549 | 550 | /* for class NAME */ 551 | char name[MAX_NAME]; 552 | }; 553 | 554 | #ifndef __cplusplus 555 | typedef struct InstructionOperand InstructionOperand; 556 | #endif 557 | 558 | #define MAX_OPERANDS 5 559 | 560 | struct Instruction 561 | { 562 | uint32_t insword; 563 | enum ENCODING encoding; 564 | 565 | enum Operation operation; 566 | InstructionOperand operands[MAX_OPERANDS]; 567 | 568 | enum FlagEffect setflags; 569 | }; 570 | 571 | #ifndef __cplusplus 572 | typedef struct Instruction Instruction; 573 | #endif 574 | 575 | #ifdef __cplusplus 576 | extern "C" 577 | { 578 | #endif 579 | 580 | int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t address); 581 | size_t get_register_size(enum Register); 582 | 583 | #ifdef __cplusplus 584 | } 585 | #endif 586 | -------------------------------------------------------------------------------- /disassembler/sysregs.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | enum SystemReg { 4 | SYSREG_NONE=32769, 5 | REG_OSDTRRX_EL1=32770, 6 | REG_DBGBVR0_EL1=32772, 7 | REG_DBGBCR0_EL1=32773, 8 | REG_DBGWVR0_EL1=32774, 9 | REG_DBGWCR0_EL1=32775, 10 | REG_DBGBVR1_EL1=32780, 11 | REG_DBGBCR1_EL1=32781, 12 | REG_DBGWVR1_EL1=32782, 13 | REG_DBGWCR1_EL1=32783, 14 | REG_MDCCINT_EL1=32784, 15 | REG_MDSCR_EL1=32786, 16 | REG_DBGBVR2_EL1=32788, 17 | REG_DBGBCR2_EL1=32789, 18 | REG_DBGWVR2_EL1=32790, 19 | REG_DBGWCR2_EL1=32791, 20 | REG_OSDTRTX_EL1=32794, 21 | REG_DBGBVR3_EL1=32796, 22 | REG_DBGBCR3_EL1=32797, 23 | REG_DBGWVR3_EL1=32798, 24 | REG_DBGWCR3_EL1=32799, 25 | REG_DBGBVR4_EL1=32804, 26 | REG_DBGBCR4_EL1=32805, 27 | REG_DBGWVR4_EL1=32806, 28 | REG_DBGWCR4_EL1=32807, 29 | REG_DBGBVR5_EL1=32812, 30 | REG_DBGBCR5_EL1=32813, 31 | REG_DBGWVR5_EL1=32814, 32 | REG_DBGWCR5_EL1=32815, 33 | REG_OSECCR_EL1=32818, 34 | REG_DBGBVR6_EL1=32820, 35 | REG_DBGBCR6_EL1=32821, 36 | REG_DBGWVR6_EL1=32822, 37 | REG_DBGWCR6_EL1=32823, 38 | REG_DBGBVR7_EL1=32828, 39 | REG_DBGBCR7_EL1=32829, 40 | REG_DBGWVR7_EL1=32830, 41 | REG_DBGWCR7_EL1=32831, 42 | REG_DBGBVR8_EL1=32836, 43 | REG_DBGBCR8_EL1=32837, 44 | REG_DBGWVR8_EL1=32838, 45 | REG_DBGWCR8_EL1=32839, 46 | REG_DBGBVR9_EL1=32844, 47 | REG_DBGBCR9_EL1=32845, 48 | REG_DBGWVR9_EL1=32846, 49 | REG_DBGWCR9_EL1=32847, 50 | REG_DBGBVR10_EL1=32852, 51 | REG_DBGBCR10_EL1=32853, 52 | REG_DBGWVR10_EL1=32854, 53 | REG_DBGWCR10_EL1=32855, 54 | REG_DBGBVR11_EL1=32860, 55 | REG_DBGBCR11_EL1=32861, 56 | REG_DBGWVR11_EL1=32862, 57 | REG_DBGWCR11_EL1=32863, 58 | REG_DBGBVR12_EL1=32868, 59 | REG_DBGBCR12_EL1=32869, 60 | REG_DBGWVR12_EL1=32870, 61 | REG_DBGWCR12_EL1=32871, 62 | REG_DBGBVR13_EL1=32876, 63 | REG_DBGBCR13_EL1=32877, 64 | REG_DBGWVR13_EL1=32878, 65 | REG_DBGWCR13_EL1=32879, 66 | REG_DBGBVR14_EL1=32884, 67 | REG_DBGBCR14_EL1=32885, 68 | REG_DBGWVR14_EL1=32886, 69 | REG_DBGWCR14_EL1=32887, 70 | REG_DBGBVR15_EL1=32892, 71 | REG_DBGBCR15_EL1=32893, 72 | REG_DBGWVR15_EL1=32894, 73 | REG_DBGWCR15_EL1=32895, 74 | REG_OSLAR_EL1=32900, 75 | REG_OSDLR_EL1=32924, 76 | REG_DBGPRCR_EL1=32932, 77 | REG_DBGCLAIMSET_EL1=33734, 78 | REG_DBGCLAIMCLR_EL1=33742, 79 | REG_TRCTRACEIDR=34817, 80 | REG_TRCVICTLR=34818, 81 | REG_TRCSEQEVR0=34820, 82 | REG_TRCCNTRLDVR0=34821, 83 | REG_TRCIMSPEC0=34823, 84 | REG_TRCPRGCTLR=34824, 85 | REG_TRCQCTLR=34825, 86 | REG_TRCVIIECTLR=34826, 87 | REG_TRCSEQEVR1=34828, 88 | REG_TRCCNTRLDVR1=34829, 89 | REG_TRCIMSPEC1=34831, 90 | REG_TRCPROCSELR=34832, 91 | REG_TRCVISSCTLR=34834, 92 | REG_TRCSEQEVR2=34836, 93 | REG_TRCCNTRLDVR2=34837, 94 | REG_TRCIMSPEC2=34839, 95 | REG_TRCVIPCSSCTLR=34842, 96 | REG_TRCCNTRLDVR3=34845, 97 | REG_TRCIMSPEC3=34847, 98 | REG_TRCCONFIGR=34848, 99 | REG_TRCCNTCTLR0=34853, 100 | REG_TRCIMSPEC4=34855, 101 | REG_TRCCNTCTLR1=34861, 102 | REG_TRCIMSPEC5=34863, 103 | REG_TRCAUXCTLR=34864, 104 | REG_TRCSEQRSTEVR=34868, 105 | REG_TRCCNTCTLR2=34869, 106 | REG_TRCIMSPEC6=34871, 107 | REG_TRCSEQSTR=34876, 108 | REG_TRCCNTCTLR3=34877, 109 | REG_TRCIMSPEC7=34879, 110 | REG_TRCEVENTCTL0R=34880, 111 | REG_TRCVDCTLR=34882, 112 | REG_TRCEXTINSELR=34884, 113 | REG_TRCCNTVR0=34885, 114 | REG_TRCEVENTCTL1R=34888, 115 | REG_TRCVDSACCTLR=34890, 116 | REG_TRCEXTINSELR1=34892, 117 | REG_TRCCNTVR1=34893, 118 | REG_TRCRSR=34896, 119 | REG_TRCVDARCCTLR=34898, 120 | REG_TRCEXTINSELR2=34900, 121 | REG_TRCCNTVR2=34901, 122 | REG_TRCSTALLCTLR=34904, 123 | REG_TRCEXTINSELR3=34908, 124 | REG_TRCCNTVR3=34909, 125 | REG_TRCTSCTLR=34912, 126 | REG_TRCSYNCPR=34920, 127 | REG_TRCCCCTLR=34928, 128 | REG_TRCBBCTLR=34936, 129 | REG_TRCRSCTLR16=34945, 130 | REG_TRCSSCCR0=34946, 131 | REG_TRCSSPCICR0=34947, 132 | REG_TRCOSLAR=34948, 133 | REG_TRCRSCTLR17=34953, 134 | REG_TRCSSCCR1=34954, 135 | REG_TRCSSPCICR1=34955, 136 | REG_TRCRSCTLR2=34960, 137 | REG_TRCRSCTLR18=34961, 138 | REG_TRCSSCCR2=34962, 139 | REG_TRCSSPCICR2=34963, 140 | REG_TRCRSCTLR3=34968, 141 | REG_TRCRSCTLR19=34969, 142 | REG_TRCSSCCR3=34970, 143 | REG_TRCSSPCICR3=34971, 144 | REG_TRCRSCTLR4=34976, 145 | REG_TRCRSCTLR20=34977, 146 | REG_TRCSSCCR4=34978, 147 | REG_TRCSSPCICR4=34979, 148 | REG_TRCPDCR=34980, 149 | REG_TRCRSCTLR5=34984, 150 | REG_TRCRSCTLR21=34985, 151 | REG_TRCSSCCR5=34986, 152 | REG_TRCSSPCICR5=34987, 153 | REG_TRCRSCTLR6=34992, 154 | REG_TRCRSCTLR22=34993, 155 | REG_TRCSSCCR6=34994, 156 | REG_TRCSSPCICR6=34995, 157 | REG_TRCRSCTLR7=35000, 158 | REG_TRCRSCTLR23=35001, 159 | REG_TRCSSCCR7=35002, 160 | REG_TRCSSPCICR7=35003, 161 | REG_TRCRSCTLR8=35008, 162 | REG_TRCRSCTLR24=35009, 163 | REG_TRCSSCSR0=35010, 164 | REG_TRCRSCTLR9=35016, 165 | REG_TRCRSCTLR25=35017, 166 | REG_TRCSSCSR1=35018, 167 | REG_TRCRSCTLR10=35024, 168 | REG_TRCRSCTLR26=35025, 169 | REG_TRCSSCSR2=35026, 170 | REG_TRCRSCTLR11=35032, 171 | REG_TRCRSCTLR27=35033, 172 | REG_TRCSSCSR3=35034, 173 | REG_TRCRSCTLR12=35040, 174 | REG_TRCRSCTLR28=35041, 175 | REG_TRCSSCSR4=35042, 176 | REG_TRCRSCTLR13=35048, 177 | REG_TRCRSCTLR29=35049, 178 | REG_TRCSSCSR5=35050, 179 | REG_TRCRSCTLR14=35056, 180 | REG_TRCRSCTLR30=35057, 181 | REG_TRCSSCSR6=35058, 182 | REG_TRCRSCTLR15=35064, 183 | REG_TRCRSCTLR31=35065, 184 | REG_TRCSSCSR7=35066, 185 | REG_TRCACVR0=35072, 186 | REG_TRCACVR8=35073, 187 | REG_TRCACATR0=35074, 188 | REG_TRCACATR8=35075, 189 | REG_TRCDVCVR0=35076, 190 | REG_TRCDVCVR4=35077, 191 | REG_TRCDVCMR0=35078, 192 | REG_TRCDVCMR4=35079, 193 | REG_TRCACVR1=35088, 194 | REG_TRCACVR9=35089, 195 | REG_TRCACATR1=35090, 196 | REG_TRCACATR9=35091, 197 | REG_TRCACVR2=35104, 198 | REG_TRCACVR10=35105, 199 | REG_TRCACATR2=35106, 200 | REG_TRCACATR10=35107, 201 | REG_TRCDVCVR1=35108, 202 | REG_TRCDVCVR5=35109, 203 | REG_TRCDVCMR1=35110, 204 | REG_TRCDVCMR5=35111, 205 | REG_TRCACVR3=35120, 206 | REG_TRCACVR11=35121, 207 | REG_TRCACATR3=35122, 208 | REG_TRCACATR11=35123, 209 | REG_TRCACVR4=35136, 210 | REG_TRCACVR12=35137, 211 | REG_TRCACATR4=35138, 212 | REG_TRCACATR12=35139, 213 | REG_TRCDVCVR2=35140, 214 | REG_TRCDVCVR6=35141, 215 | REG_TRCDVCMR2=35142, 216 | REG_TRCDVCMR6=35143, 217 | REG_TRCACVR5=35152, 218 | REG_TRCACVR13=35153, 219 | REG_TRCACATR5=35154, 220 | REG_TRCACATR13=35155, 221 | REG_TRCACVR6=35168, 222 | REG_TRCACVR14=35169, 223 | REG_TRCACATR6=35170, 224 | REG_TRCACATR14=35171, 225 | REG_TRCDVCVR3=35172, 226 | REG_TRCDVCVR7=35173, 227 | REG_TRCDVCMR3=35174, 228 | REG_TRCDVCMR7=35175, 229 | REG_TRCACVR7=35184, 230 | REG_TRCACVR15=35185, 231 | REG_TRCACATR7=35186, 232 | REG_TRCACATR15=35187, 233 | REG_TRCCIDCVR0=35200, 234 | REG_TRCVMIDCVR0=35201, 235 | REG_TRCCIDCCTLR0=35202, 236 | REG_TRCCIDCCTLR1=35210, 237 | REG_TRCCIDCVR1=35216, 238 | REG_TRCVMIDCVR1=35217, 239 | REG_TRCVMIDCCTLR0=35218, 240 | REG_TRCVMIDCCTLR1=35226, 241 | REG_TRCCIDCVR2=35232, 242 | REG_TRCVMIDCVR2=35233, 243 | REG_TRCCIDCVR3=35248, 244 | REG_TRCVMIDCVR3=35249, 245 | REG_TRCCIDCVR4=35264, 246 | REG_TRCVMIDCVR4=35265, 247 | REG_TRCCIDCVR5=35280, 248 | REG_TRCVMIDCVR5=35281, 249 | REG_TRCCIDCVR6=35296, 250 | REG_TRCVMIDCVR6=35297, 251 | REG_TRCCIDCVR7=35312, 252 | REG_TRCVMIDCVR7=35313, 253 | REG_TRCITCTRL=35716, 254 | REG_TRCCLAIMSET=35782, 255 | REG_TRCCLAIMCLR=35790, 256 | REG_TRCLAR=35814, 257 | REG_TEECR32_EL1=36864, 258 | REG_TEEHBR32_EL1=36992, 259 | REG_DBGDTR_EL0=38944, 260 | REG_DBGDTRTX_EL0=38952, 261 | REG_DBGVCR32_EL2=41016, 262 | REG_SCTLR_EL1=49280, 263 | REG_ACTLR_EL1=49281, 264 | REG_CPACR_EL1=49282, 265 | REG_RGSR_EL1=49285, 266 | REG_GCR_EL1=49286, 267 | REG_TRFCR_EL1=49297, 268 | REG_TTBR0_EL1=49408, 269 | REG_TTBR1_EL1=49409, 270 | REG_TCR_EL1=49410, 271 | REG_APIAKEYLO_EL1=49416, 272 | REG_APIAKEYHI_EL1=49417, 273 | REG_APIBKEYLO_EL1=49418, 274 | REG_APIBKEYHI_EL1=49419, 275 | REG_APDAKEYLO_EL1=49424, 276 | REG_APDAKEYHI_EL1=49425, 277 | REG_APDBKEYLO_EL1=49426, 278 | REG_APDBKEYHI_EL1=49427, 279 | REG_APGAKEYLO_EL1=49432, 280 | REG_APGAKEYHI_EL1=49433, 281 | REG_SPSR_EL1=49664, 282 | REG_ELR_EL1=49665, 283 | REG_SP_EL0=49672, 284 | REG_SPSEL=49680, 285 | REG_CURRENTEL=49682, 286 | REG_PAN=49683, 287 | REG_UAO=49684, 288 | REG_ICC_PMR_EL1=49712, 289 | REG_AFSR0_EL1=49800, 290 | REG_AFSR1_EL1=49801, 291 | REG_ESR_EL1=49808, 292 | REG_ERRSELR_EL1=49817, 293 | REG_ERXCTLR_EL1=49825, 294 | REG_ERXSTATUS_EL1=49826, 295 | REG_ERXADDR_EL1=49827, 296 | REG_ERXPFGCTL_EL1=49829, 297 | REG_ERXPFGCDN_EL1=49830, 298 | REG_ERXMISC0_EL1=49832, 299 | REG_ERXMISC1_EL1=49833, 300 | REG_ERXMISC2_EL1=49834, 301 | REG_ERXMISC3_EL1=49835, 302 | REG_ERXTS_EL1=49839, 303 | REG_TFSR_EL1=49840, 304 | REG_TFSRE0_EL1=49841, 305 | REG_FAR_EL1=49920, 306 | REG_PAR_EL1=50080, 307 | REG_PMSCR_EL1=50376, 308 | REG_PMSICR_EL1=50378, 309 | REG_PMSIRR_EL1=50379, 310 | REG_PMSFCR_EL1=50380, 311 | REG_PMSEVFR_EL1=50381, 312 | REG_PMSLATFR_EL1=50382, 313 | REG_PMSIDR_EL1=50383, 314 | REG_PMBLIMITR_EL1=50384, 315 | REG_PMBPTR_EL1=50385, 316 | REG_PMBSR_EL1=50387, 317 | REG_PMBIDR_EL1=50391, 318 | REG_TRBLIMITR_EL1=50392, 319 | REG_TRBPTR_EL1=50393, 320 | REG_TRBBASER_EL1=50394, 321 | REG_TRBSR_EL1=50395, 322 | REG_TRBMAR_EL1=50396, 323 | REG_TRBTRG_EL1=50398, 324 | REG_PMINTENSET_EL1=50417, 325 | REG_PMINTENCLR_EL1=50418, 326 | REG_PMMIR_EL1=50422, 327 | REG_MAIR_EL1=50448, 328 | REG_AMAIR_EL1=50456, 329 | REG_LORSA_EL1=50464, 330 | REG_LOREA_EL1=50465, 331 | REG_LORN_EL1=50466, 332 | REG_LORC_EL1=50467, 333 | REG_MPAM1_EL1=50472, 334 | REG_MPAM0_EL1=50473, 335 | REG_VBAR_EL1=50688, 336 | REG_RMR_EL1=50690, 337 | REG_DISR_EL1=50697, 338 | REG_ICC_EOIR0_EL1=50753, 339 | REG_ICC_BPR0_EL1=50755, 340 | REG_ICC_AP0R0_EL1=50756, 341 | REG_ICC_AP0R1_EL1=50757, 342 | REG_ICC_AP0R2_EL1=50758, 343 | REG_ICC_AP0R3_EL1=50759, 344 | REG_ICC_AP1R0_EL1=50760, 345 | REG_ICC_AP1R1_EL1=50761, 346 | REG_ICC_AP1R2_EL1=50762, 347 | REG_ICC_AP1R3_EL1=50763, 348 | REG_ICC_DIR_EL1=50777, 349 | REG_ICC_SGI1R_EL1=50781, 350 | REG_ICC_ASGI1R_EL1=50782, 351 | REG_ICC_SGI0R_EL1=50783, 352 | REG_ICC_EOIR1_EL1=50785, 353 | REG_ICC_BPR1_EL1=50787, 354 | REG_ICC_CTLR_EL1=50788, 355 | REG_ICC_SRE_EL1=50789, 356 | REG_ICC_IGRPEN0_EL1=50790, 357 | REG_ICC_IGRPEN1_EL1=50791, 358 | REG_ICC_SEIEN_EL1=50792, 359 | REG_CONTEXTIDR_EL1=50817, 360 | REG_TPIDR_EL1=50820, 361 | REG_SCXTNUM_EL1=50823, 362 | REG_CNTKCTL_EL1=50952, 363 | REG_CSSELR_EL1=53248, 364 | REG_NZCV=55824, 365 | REG_DAIFSET=55825, 366 | REG_DIT=55829, 367 | REG_SSBS=55830, 368 | REG_TCO=55831, 369 | REG_FPCR=55840, 370 | REG_FPSR=55841, 371 | REG_DSPSR_EL0=55848, 372 | REG_DLR_EL0=55849, 373 | REG_PMCR_EL0=56544, 374 | REG_PMCNTENSET_EL0=56545, 375 | REG_PMCNTENCLR_EL0=56546, 376 | REG_PMOVSCLR_EL0=56547, 377 | REG_PMSWINC_EL0=56548, 378 | REG_PMSELR_EL0=56549, 379 | REG_PMCCNTR_EL0=56552, 380 | REG_PMXEVTYPER_EL0=56553, 381 | REG_PMXEVCNTR_EL0=56554, 382 | REG_DAIFCLR=56557, 383 | REG_PMUSERENR_EL0=56560, 384 | REG_PMOVSSET_EL0=56563, 385 | REG_TPIDR_EL0=56962, 386 | REG_TPIDRRO_EL0=56963, 387 | REG_SCXTNUM_EL0=56967, 388 | REG_AMCR_EL0=56976, 389 | REG_AMUSERENR_EL0=56979, 390 | REG_AMCNTENCLR0_EL0=56980, 391 | REG_AMCNTENSET0_EL0=56981, 392 | REG_AMCNTENCLR1_EL0=56984, 393 | REG_AMCNTENSET1_EL0=56985, 394 | REG_AMEVCNTR00_EL0=56992, 395 | REG_AMEVCNTR01_EL0=56993, 396 | REG_AMEVCNTR02_EL0=56994, 397 | REG_AMEVCNTR03_EL0=56995, 398 | REG_AMEVCNTR10_EL0=57056, 399 | REG_AMEVCNTR11_EL0=57057, 400 | REG_AMEVCNTR12_EL0=57058, 401 | REG_AMEVCNTR13_EL0=57059, 402 | REG_AMEVCNTR14_EL0=57060, 403 | REG_AMEVCNTR15_EL0=57061, 404 | REG_AMEVCNTR16_EL0=57062, 405 | REG_AMEVCNTR17_EL0=57063, 406 | REG_AMEVCNTR18_EL0=57064, 407 | REG_AMEVCNTR19_EL0=57065, 408 | REG_AMEVCNTR110_EL0=57066, 409 | REG_AMEVCNTR111_EL0=57067, 410 | REG_AMEVCNTR112_EL0=57068, 411 | REG_AMEVCNTR113_EL0=57069, 412 | REG_AMEVCNTR114_EL0=57070, 413 | REG_AMEVCNTR115_EL0=57071, 414 | REG_AMEVTYPER10_EL0=57072, 415 | REG_AMEVTYPER11_EL0=57073, 416 | REG_AMEVTYPER12_EL0=57074, 417 | REG_AMEVTYPER13_EL0=57075, 418 | REG_AMEVTYPER14_EL0=57076, 419 | REG_AMEVTYPER15_EL0=57077, 420 | REG_AMEVTYPER16_EL0=57078, 421 | REG_AMEVTYPER17_EL0=57079, 422 | REG_AMEVTYPER18_EL0=57080, 423 | REG_AMEVTYPER19_EL0=57081, 424 | REG_AMEVTYPER110_EL0=57082, 425 | REG_AMEVTYPER111_EL0=57083, 426 | REG_AMEVTYPER112_EL0=57084, 427 | REG_AMEVTYPER113_EL0=57085, 428 | REG_AMEVTYPER114_EL0=57086, 429 | REG_AMEVTYPER115_EL0=57087, 430 | REG_CNTFRQ_EL0=57088, 431 | REG_CNTP_TVAL_EL0=57104, 432 | REG_CNTP_CTL_EL0=57105, 433 | REG_CNTP_CVAL_EL0=57106, 434 | REG_CNTV_TVAL_EL0=57112, 435 | REG_CNTV_CTL_EL0=57113, 436 | REG_CNTV_CVAL_EL0=57114, 437 | REG_PMEVCNTR0_EL0=57152, 438 | REG_PMEVCNTR1_EL0=57153, 439 | REG_PMEVCNTR2_EL0=57154, 440 | REG_PMEVCNTR3_EL0=57155, 441 | REG_PMEVCNTR4_EL0=57156, 442 | REG_PMEVCNTR5_EL0=57157, 443 | REG_PMEVCNTR6_EL0=57158, 444 | REG_PMEVCNTR7_EL0=57159, 445 | REG_PMEVCNTR8_EL0=57160, 446 | REG_PMEVCNTR9_EL0=57161, 447 | REG_PMEVCNTR10_EL0=57162, 448 | REG_PMEVCNTR11_EL0=57163, 449 | REG_PMEVCNTR12_EL0=57164, 450 | REG_PMEVCNTR13_EL0=57165, 451 | REG_PMEVCNTR14_EL0=57166, 452 | REG_PMEVCNTR15_EL0=57167, 453 | REG_PMEVCNTR16_EL0=57168, 454 | REG_PMEVCNTR17_EL0=57169, 455 | REG_PMEVCNTR18_EL0=57170, 456 | REG_PMEVCNTR19_EL0=57171, 457 | REG_PMEVCNTR20_EL0=57172, 458 | REG_PMEVCNTR21_EL0=57173, 459 | REG_PMEVCNTR22_EL0=57174, 460 | REG_PMEVCNTR23_EL0=57175, 461 | REG_PMEVCNTR24_EL0=57176, 462 | REG_PMEVCNTR25_EL0=57177, 463 | REG_PMEVCNTR26_EL0=57178, 464 | REG_PMEVCNTR27_EL0=57179, 465 | REG_PMEVCNTR28_EL0=57180, 466 | REG_PMEVCNTR29_EL0=57181, 467 | REG_PMEVCNTR30_EL0=57182, 468 | REG_PMEVTYPER0_EL0=57184, 469 | REG_PMEVTYPER1_EL0=57185, 470 | REG_PMEVTYPER2_EL0=57186, 471 | REG_PMEVTYPER3_EL0=57187, 472 | REG_PMEVTYPER4_EL0=57188, 473 | REG_PMEVTYPER5_EL0=57189, 474 | REG_PMEVTYPER6_EL0=57190, 475 | REG_PMEVTYPER7_EL0=57191, 476 | REG_PMEVTYPER8_EL0=57192, 477 | REG_PMEVTYPER9_EL0=57193, 478 | REG_PMEVTYPER10_EL0=57194, 479 | REG_PMEVTYPER11_EL0=57195, 480 | REG_PMEVTYPER12_EL0=57196, 481 | REG_PMEVTYPER13_EL0=57197, 482 | REG_PMEVTYPER14_EL0=57198, 483 | REG_PMEVTYPER15_EL0=57199, 484 | REG_PMEVTYPER16_EL0=57200, 485 | REG_PMEVTYPER17_EL0=57201, 486 | REG_PMEVTYPER18_EL0=57202, 487 | REG_PMEVTYPER19_EL0=57203, 488 | REG_PMEVTYPER20_EL0=57204, 489 | REG_PMEVTYPER21_EL0=57205, 490 | REG_PMEVTYPER22_EL0=57206, 491 | REG_PMEVTYPER23_EL0=57207, 492 | REG_PMEVTYPER24_EL0=57208, 493 | REG_PMEVTYPER25_EL0=57209, 494 | REG_PMEVTYPER26_EL0=57210, 495 | REG_PMEVTYPER27_EL0=57211, 496 | REG_PMEVTYPER28_EL0=57212, 497 | REG_PMEVTYPER29_EL0=57213, 498 | REG_PMEVTYPER30_EL0=57214, 499 | REG_PMCCFILTR_EL0=57215, 500 | REG_VPIDR_EL2=57344, 501 | REG_VMPIDR_EL2=57349, 502 | REG_SCTLR_EL2=57472, 503 | REG_ACTLR_EL2=57473, 504 | REG_HCR_EL2=57480, 505 | REG_MDCR_EL2=57481, 506 | REG_CPTR_EL2=57482, 507 | REG_HSTR_EL2=57483, 508 | REG_HACR_EL2=57487, 509 | REG_TRFCR_EL2=57489, 510 | REG_SDER32_EL2=57497, 511 | REG_TTBR0_EL2=57600, 512 | REG_TTBR1_EL2=57601, 513 | REG_TCR_EL2=57602, 514 | REG_VTTBR_EL2=57608, 515 | REG_VTCR_EL2=57610, 516 | REG_VNCR_EL2=57616, 517 | REG_VSTTBR_EL2=57648, 518 | REG_VSTCR_EL2=57650, 519 | REG_DACR32_EL2=57728, 520 | REG_SPSR_EL2=57856, 521 | REG_ELR_EL2=57857, 522 | REG_SP_EL1=57864, 523 | REG_SPSR_IRQ=57880, 524 | REG_SPSR_ABT=57881, 525 | REG_SPSR_UND=57882, 526 | REG_SPSR_FIQ=57883, 527 | REG_IFSR32_EL2=57985, 528 | REG_AFSR0_EL2=57992, 529 | REG_AFSR1_EL2=57993, 530 | REG_ESR_EL2=58000, 531 | REG_VSESR_EL2=58003, 532 | REG_FPEXC32_EL2=58008, 533 | REG_TFSR_EL2=58032, 534 | REG_FAR_EL2=58112, 535 | REG_HPFAR_EL2=58116, 536 | REG_PMSCR_EL2=58568, 537 | REG_MAIR_EL2=58640, 538 | REG_AMAIR_EL2=58648, 539 | REG_MPAMHCR_EL2=58656, 540 | REG_MPAMVPMV_EL2=58657, 541 | REG_MPAM2_EL2=58664, 542 | REG_MPAMVPM0_EL2=58672, 543 | REG_MPAMVPM1_EL2=58673, 544 | REG_MPAMVPM2_EL2=58674, 545 | REG_MPAMVPM3_EL2=58675, 546 | REG_MPAMVPM4_EL2=58676, 547 | REG_MPAMVPM5_EL2=58677, 548 | REG_MPAMVPM6_EL2=58678, 549 | REG_MPAMVPM7_EL2=58679, 550 | REG_VBAR_EL2=58880, 551 | REG_RMR_EL2=58882, 552 | REG_VDISR_EL2=58889, 553 | REG_ICH_AP0R0_EL2=58944, 554 | REG_ICH_AP0R1_EL2=58945, 555 | REG_ICH_AP0R2_EL2=58946, 556 | REG_ICH_AP0R3_EL2=58947, 557 | REG_ICH_AP1R0_EL2=58952, 558 | REG_ICH_AP1R1_EL2=58953, 559 | REG_ICH_AP1R2_EL2=58954, 560 | REG_ICH_AP1R3_EL2=58955, 561 | REG_ICH_VSEIR_EL2=58956, 562 | REG_ICC_SRE_EL2=58957, 563 | REG_ICH_HCR_EL2=58968, 564 | REG_ICH_MISR_EL2=58970, 565 | REG_ICH_VMCR_EL2=58975, 566 | REG_ICH_LR0_EL2=58976, 567 | REG_ICH_LR1_EL2=58977, 568 | REG_ICH_LR2_EL2=58978, 569 | REG_ICH_LR3_EL2=58979, 570 | REG_ICH_LR4_EL2=58980, 571 | REG_ICH_LR5_EL2=58981, 572 | REG_ICH_LR6_EL2=58982, 573 | REG_ICH_LR7_EL2=58983, 574 | REG_ICH_LR8_EL2=58984, 575 | REG_ICH_LR9_EL2=58985, 576 | REG_ICH_LR10_EL2=58986, 577 | REG_ICH_LR11_EL2=58987, 578 | REG_ICH_LR12_EL2=58988, 579 | REG_ICH_LR13_EL2=58989, 580 | REG_ICH_LR14_EL2=58990, 581 | REG_ICH_LR15_EL2=58991, 582 | REG_CONTEXTIDR_EL2=59009, 583 | REG_TPIDR_EL2=59010, 584 | REG_SCXTNUM_EL2=59015, 585 | REG_CNTVOFF_EL2=59139, 586 | REG_CNTHCTL_EL2=59144, 587 | REG_CNTHP_TVAL_EL2=59152, 588 | REG_CNTHP_CTL_EL2=59153, 589 | REG_CNTHP_CVAL_EL2=59154, 590 | REG_CNTHV_TVAL_EL2=59160, 591 | REG_CNTHV_CTL_EL2=59161, 592 | REG_CNTHV_CVAL_EL2=59162, 593 | REG_CNTHVS_TVAL_EL2=59168, 594 | REG_CNTHVS_CTL_EL2=59169, 595 | REG_CNTHVS_CVAL_EL2=59170, 596 | REG_CNTHPS_TVAL_EL2=59176, 597 | REG_CNTHPS_CTL_EL2=59177, 598 | REG_CNTHPS_CVAL_EL2=59178, 599 | REG_SCTLR_EL12=59520, 600 | REG_CPACR_EL12=59522, 601 | REG_TRFCR_EL12=59537, 602 | REG_TTBR0_EL12=59648, 603 | REG_TTBR1_EL12=59649, 604 | REG_TCR_EL12=59650, 605 | REG_SPSR_EL12=59904, 606 | REG_ELR_EL12=59905, 607 | REG_AFSR0_EL12=60040, 608 | REG_AFSR1_EL12=60041, 609 | REG_ESR_EL12=60048, 610 | REG_TFSR_EL12=60080, 611 | REG_FAR_EL12=60160, 612 | REG_PMSCR_EL12=60616, 613 | REG_MAIR_EL12=60688, 614 | REG_AMAIR_EL12=60696, 615 | REG_MPAM1_EL12=60712, 616 | REG_VBAR_EL12=60928, 617 | REG_CONTEXTIDR_EL12=61057, 618 | REG_SCXTNUM_EL12=61063, 619 | REG_CNTKCTL_EL12=61192, 620 | REG_CNTP_TVAL_EL02=61200, 621 | REG_CNTP_CTL_EL02=61201, 622 | REG_CNTP_CVAL_EL02=61202, 623 | REG_CNTV_TVAL_EL02=61208, 624 | REG_CNTV_CTL_EL02=61209, 625 | REG_CNTV_CVAL_EL02=61210, 626 | REG_SCTLR_EL3=61568, 627 | REG_ACTLR_EL3=61569, 628 | REG_SCR_EL3=61576, 629 | REG_SDER32_EL3=61577, 630 | REG_CPTR_EL3=61578, 631 | REG_MDCR_EL3=61593, 632 | REG_TTBR0_EL3=61696, 633 | REG_TCR_EL3=61698, 634 | REG_SPSR_EL3=61952, 635 | REG_ELR_EL3=61953, 636 | REG_SP_EL2=61960, 637 | REG_AFSR0_EL3=62088, 638 | REG_AFSR1_EL3=62089, 639 | REG_ESR_EL3=62096, 640 | REG_TFSR_EL3=62128, 641 | REG_FAR_EL3=62208, 642 | REG_MAIR_EL3=62736, 643 | REG_AMAIR_EL3=62744, 644 | REG_MPAM3_EL3=62760, 645 | REG_VBAR_EL3=62976, 646 | REG_RMR_EL3=62978, 647 | REG_ICC_CTLR_EL3=63076, 648 | REG_ICC_SRE_EL3=63077, 649 | REG_ICC_IGRPEN1_EL3=63079, 650 | REG_TPIDR_EL3=63106, 651 | REG_SCXTNUM_EL3=63111, 652 | REG_CNTPS_TVAL_EL1=65296, 653 | REG_CNTPS_CTL_EL1=65297, 654 | REG_CNTPS_CVAL_EL1=65298, 655 | /* exceptional system registers */ 656 | REG_PSTATE_SPSEL=65299, // (op0,op1,crn,crm,op2)=(0,0,4,9,5) doesn't map to [SYSREG_NONE+1, SYSREG_END) 657 | SYSREG_END=65300, 658 | }; 659 | 660 | #ifdef __cplusplus 661 | extern "C" { 662 | #endif 663 | const char *get_system_register_name(enum SystemReg); 664 | const char *get_system_register_name_decomposed(int op0, int op1, int CRn, int CRm, int op2); 665 | #ifdef __cplusplus 666 | } 667 | #endif 668 | 669 | -------------------------------------------------------------------------------- /disassembler/format.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | #include "format.h" 8 | #include "regs.h" 9 | #include "pcode.h" 10 | 11 | const char *get_arrspec_str(ArrangementSpec arrspec) 12 | { 13 | switch(arrspec) { 14 | case ARRSPEC_FULL: return ".1q"; 15 | case ARRSPEC_2DOUBLES: return ".2d"; 16 | case ARRSPEC_4SINGLES: return ".4s"; 17 | case ARRSPEC_8HALVES: return ".8h"; 18 | case ARRSPEC_16BYTES: return ".16b"; 19 | case ARRSPEC_1DOUBLE: return ".1d"; 20 | case ARRSPEC_2SINGLES: return ".2s"; 21 | case ARRSPEC_4HALVES: return ".4h"; 22 | case ARRSPEC_8BYTES: return ".8b"; 23 | case ARRSPEC_1SINGLE: return ".1s"; 24 | case ARRSPEC_2HALVES: return ".2h"; 25 | case ARRSPEC_4BYTES: return ".4b"; 26 | case ARRSPEC_1HALF: return ".1h"; 27 | case ARRSPEC_1BYTE: return ".1b"; 28 | default: return ""; 29 | } 30 | } 31 | 32 | const char *get_arrspec_str_truncated(ArrangementSpec arrspec) 33 | { 34 | switch(arrspec) { 35 | case ARRSPEC_FULL: return ".q"; 36 | case ARRSPEC_2DOUBLES: return ".d"; 37 | case ARRSPEC_4SINGLES: return ".s"; 38 | case ARRSPEC_8HALVES: return ".h"; 39 | case ARRSPEC_16BYTES: return ".b"; 40 | case ARRSPEC_1DOUBLE: return ".d"; 41 | case ARRSPEC_2SINGLES: return ".s"; 42 | case ARRSPEC_4HALVES: return ".h"; 43 | case ARRSPEC_8BYTES: return ".b"; 44 | case ARRSPEC_1SINGLE: return ".s"; 45 | case ARRSPEC_2HALVES: return ".h"; 46 | case ARRSPEC_4BYTES: return ".4b"; // not an error, UDOT_asimdelem_D and SDOT_asimdelem_D use this 47 | case ARRSPEC_1HALF: return ".h"; 48 | case ARRSPEC_1BYTE: return ".b"; 49 | default: return ""; 50 | } 51 | } 52 | 53 | const char *get_register_arrspec(Register reg, const InstructionOperand *operand) 54 | { 55 | if(operand->arrSpec == ARRSPEC_NONE) 56 | return ""; 57 | 58 | bool is_simd = reg >= REG_V0 && reg <= REG_V31; 59 | bool is_sve = reg >= REG_Z0 && reg <= REG_Z31; 60 | bool is_pred = reg >= REG_P0 && reg <= REG_P31; 61 | 62 | if(!is_simd && !is_sve && !is_pred) 63 | return ""; 64 | 65 | if(operand->laneUsed || is_sve || is_pred) 66 | return get_arrspec_str_truncated(operand->arrSpec); 67 | 68 | return get_arrspec_str(operand->arrSpec); 69 | } 70 | 71 | int get_register_full(Register reg, const InstructionOperand *operand, char *result) 72 | { 73 | strcpy(result, get_register_name(reg)); 74 | if(result[0] == '\0') 75 | return -1; 76 | 77 | strcat(result, get_register_arrspec(reg, operand)); 78 | 79 | return 0; 80 | } 81 | 82 | //----------------------------------------------------------------------------- 83 | // miscellany to string 84 | //----------------------------------------------------------------------------- 85 | 86 | uint32_t get_implementation_specific(const InstructionOperand *operand, char *outBuffer, uint32_t outBufferSize) 87 | { 88 | return snprintf(outBuffer, 89 | outBufferSize, 90 | "s%d_%d_c%d_c%d_%d", 91 | operand->implspec[0], 92 | operand->implspec[1], 93 | operand->implspec[2], 94 | operand->implspec[3], 95 | operand->implspec[4]) >= outBufferSize; 96 | } 97 | 98 | const char *get_operation(const Instruction *inst) 99 | { 100 | return operation_to_str(inst->operation); 101 | } 102 | 103 | static const char *ConditionString[] = { 104 | "eq", "ne", "cs", "cc", 105 | "mi", "pl", "vs", "vc", 106 | "hi", "ls", "ge", "lt", 107 | "gt", "le", "al", "nv" 108 | }; 109 | 110 | const char *get_condition(Condition cond) 111 | { 112 | if (cond < 0 || cond >= END_CONDITION) 113 | return NULL; 114 | 115 | return ConditionString[cond]; 116 | } 117 | 118 | static const char *ShiftString[] = { 119 | "NONE", "lsl", "lsr", "asr", 120 | "ror", "uxtw", "sxtw", "sxtx", 121 | "uxtx", "sxtb", "sxth", "uxth", 122 | "uxtb", "msl" 123 | }; 124 | 125 | const char *get_shift(ShiftType shift) 126 | { 127 | if (shift <= ShiftType_NONE || shift >= ShiftType_END) 128 | return NULL; 129 | 130 | return ShiftString[shift]; 131 | } 132 | 133 | //----------------------------------------------------------------------------- 134 | // operand processing helpers 135 | //----------------------------------------------------------------------------- 136 | 137 | static inline uint32_t get_shifted_register( 138 | const InstructionOperand *operand, 139 | uint32_t registerNumber, 140 | char *outBuffer, 141 | uint32_t outBufferSize) 142 | { 143 | char immBuff[32] = {0}; 144 | char shiftBuff[64] = {0}; 145 | 146 | char reg[16]; 147 | if(get_register_full(operand->reg[registerNumber], operand, reg)) 148 | return FAILED_TO_DISASSEMBLE_REGISTER; 149 | 150 | if (operand->shiftType != ShiftType_NONE) 151 | { 152 | if (operand->shiftValueUsed != 0) 153 | { 154 | if (snprintf(immBuff, sizeof(immBuff), " #%#x", operand->shiftValue) >= sizeof(immBuff)) 155 | { 156 | return FAILED_TO_DISASSEMBLE_REGISTER; 157 | } 158 | } 159 | const char *shiftStr = get_shift(operand->shiftType); 160 | if (shiftStr == NULL) 161 | return FAILED_TO_DISASSEMBLE_OPERAND; 162 | snprintf( 163 | shiftBuff, 164 | sizeof(shiftBuff), 165 | ", %s%s", 166 | shiftStr, 167 | immBuff); 168 | } 169 | if (snprintf(outBuffer, outBufferSize, "%s%s", reg, shiftBuff) < 0) 170 | return FAILED_TO_DISASSEMBLE_REGISTER; 171 | return DISASM_SUCCESS; 172 | } 173 | 174 | uint32_t get_memory_operand( 175 | const InstructionOperand *operand, 176 | char *outBuffer, 177 | uint32_t outBufferSize) 178 | { 179 | char immBuff[64]= {0}; 180 | char extendBuff[48] = {0}; 181 | char paramBuff[32] = {0}; 182 | 183 | char reg0[16]={'\0'}, reg1[16]={'\0'}; 184 | if(get_register_full(operand->reg[0], operand, reg0)) 185 | return FAILED_TO_DISASSEMBLE_REGISTER; 186 | 187 | const char *sign = ""; 188 | int64_t imm = operand->immediate; 189 | if (operand->signedImm && (int64_t)imm < 0) 190 | { 191 | sign = "-"; 192 | imm = -imm; 193 | } 194 | 195 | switch (operand->operandClass) 196 | { 197 | case MEM_REG: 198 | if (snprintf(outBuffer, outBufferSize, "[%s]", reg0) >= outBufferSize) 199 | return FAILED_TO_DISASSEMBLE_OPERAND; 200 | break; 201 | 202 | case MEM_PRE_IDX: 203 | if (snprintf(outBuffer, outBufferSize, "[%s, #%s%#" PRIx64 "]!", reg0, sign, (uint64_t)imm) >= outBufferSize) 204 | return FAILED_TO_DISASSEMBLE_OPERAND; 205 | break; 206 | 207 | case MEM_POST_IDX: // [], 208 | if (operand->reg[1] != REG_NONE) { 209 | if(get_register_full((Register)operand->reg[1], operand, reg1)) 210 | return FAILED_TO_DISASSEMBLE_REGISTER; 211 | 212 | snprintf(paramBuff, sizeof(paramBuff), ", %s", reg1); 213 | } 214 | else if (snprintf(paramBuff, sizeof(paramBuff), ", #%s%#" PRIx64, sign, (uint64_t)imm) >= sizeof(paramBuff)) 215 | return FAILED_TO_DISASSEMBLE_OPERAND; 216 | 217 | if (snprintf(outBuffer, outBufferSize, "[%s]%s", reg0, paramBuff) >= outBufferSize) 218 | return FAILED_TO_DISASSEMBLE_OPERAND; 219 | 220 | break; 221 | 222 | case MEM_OFFSET: // [ optional(imm)] 223 | if (operand->immediate != 0) { 224 | const char *mul_vl = operand->mul_vl ? ", mul vl" : ""; 225 | if(snprintf(immBuff, sizeof(immBuff), ", #%s%#" PRIx64 "%s", sign, (uint64_t)imm, mul_vl) >= sizeof(immBuff)) { 226 | return FAILED_TO_DISASSEMBLE_OPERAND; 227 | } 228 | } 229 | 230 | if (snprintf(outBuffer, outBufferSize, "[%s%s]", reg0, immBuff) >= outBufferSize) 231 | return FAILED_TO_DISASSEMBLE_OPERAND; 232 | break; 233 | 234 | case MEM_EXTENDED: 235 | if(get_register_full(operand->reg[1], operand, reg1)) 236 | return FAILED_TO_DISASSEMBLE_REGISTER; 237 | 238 | if (reg0[0] == '\0' || reg1[0] == '\0') { 239 | return FAILED_TO_DISASSEMBLE_OPERAND; 240 | } 241 | 242 | // immBuff, like "#0x0" 243 | if (operand->shiftValueUsed) 244 | if(snprintf(immBuff, sizeof(immBuff), " #%#x", operand->shiftValue) >= sizeof(immBuff)) 245 | return FAILED_TO_DISASSEMBLE_OPERAND; 246 | 247 | // extendBuff, like "lsl #0x0" 248 | if (operand->shiftType != ShiftType_NONE) 249 | { 250 | if (snprintf(extendBuff, sizeof(extendBuff), ", %s%s", 251 | get_shift(operand->shiftType), immBuff) >= sizeof(extendBuff)) 252 | { 253 | return FAILED_TO_DISASSEMBLE_OPERAND; 254 | } 255 | } 256 | 257 | // together, like "[x24, x30, lsl #0x0]" 258 | if (snprintf(outBuffer, outBufferSize, "[%s, %s%s]", reg0, reg1, extendBuff) >= outBufferSize) 259 | return FAILED_TO_DISASSEMBLE_OPERAND; 260 | 261 | break; 262 | default: 263 | return NOT_MEMORY_OPERAND; 264 | } 265 | return DISASM_SUCCESS; 266 | } 267 | 268 | uint32_t get_register(const InstructionOperand *operand, uint32_t registerNumber, char *outBuffer, uint32_t outBufferSize) 269 | { 270 | /* 1) handle system registers */ 271 | if(operand->operandClass == SYS_REG) 272 | { 273 | if (snprintf(outBuffer, outBufferSize, "%s", 274 | get_system_register_name(operand->sysreg)) >= outBufferSize) 275 | return FAILED_TO_DISASSEMBLE_REGISTER; 276 | return 0; 277 | } 278 | 279 | if(operand->operandClass != REG && operand->operandClass != MULTI_REG) 280 | return OPERAND_IS_NOT_REGISTER; 281 | 282 | /* 2) handle shifted registers */ 283 | if (operand->shiftType != ShiftType_NONE) 284 | { 285 | return get_shifted_register(operand, registerNumber, outBuffer, outBufferSize); 286 | } 287 | 288 | char reg_buf[16]; 289 | if(get_register_full(operand->reg[registerNumber], operand, reg_buf)) 290 | return FAILED_TO_DISASSEMBLE_REGISTER; 291 | 292 | /* 3) handle predicate registers */ 293 | if(operand->operandClass == REG && operand->pred_qual && operand->reg[0] >= REG_P0 && operand->reg[0] <= REG_P31) 294 | { 295 | if(snprintf(outBuffer, outBufferSize, "%s/%c", reg_buf, operand->pred_qual) >= outBufferSize) 296 | return FAILED_TO_DISASSEMBLE_REGISTER; 297 | return 0; 298 | } 299 | 300 | /* 4) handle other registers */ 301 | char index[32] = {0}; 302 | if(operand->operandClass == REG && operand->laneUsed) 303 | snprintf(index, sizeof(index), "[%u]", operand->lane); 304 | 305 | if(snprintf(outBuffer, outBufferSize, "%s%s", reg_buf, index) >= outBufferSize) 306 | return FAILED_TO_DISASSEMBLE_REGISTER; 307 | 308 | return 0; 309 | } 310 | 311 | uint32_t get_multireg_operand(const InstructionOperand *operand, char *result, uint32_t result_sz) 312 | { 313 | char lane_str[32] = {0}; 314 | char reg_str[4][32]; 315 | uint32_t elem_n; 316 | int rc; 317 | memset(®_str, 0, sizeof(reg_str)); 318 | 319 | for (elem_n = 0; elem_n < 4 && operand->reg[elem_n] != REG_NONE; elem_n++) 320 | if (get_register(operand, elem_n, reg_str[elem_n], 32) != 0) 321 | return FAILED_TO_DISASSEMBLE_OPERAND; 322 | 323 | if(operand->laneUsed) 324 | snprintf(lane_str, sizeof(lane_str), "[%d]", operand->lane); 325 | 326 | switch (elem_n) 327 | { 328 | case 1: 329 | rc = snprintf(result, result_sz, "{%s}%s", 330 | reg_str[0], lane_str); 331 | break; 332 | case 2: 333 | rc = snprintf(result, result_sz, "{%s, %s}%s", 334 | reg_str[0], reg_str[1], lane_str); 335 | break; 336 | case 3: 337 | rc = snprintf(result, result_sz, "{%s, %s, %s}%s", 338 | reg_str[0], reg_str[1], reg_str[2], lane_str); 339 | break; 340 | case 4: 341 | rc = snprintf(result, result_sz, "{%s, %s, %s, %s}%s", 342 | reg_str[0], reg_str[1], reg_str[2], reg_str[3], lane_str); 343 | break; 344 | default: 345 | return FAILED_TO_DISASSEMBLE_OPERAND; 346 | } 347 | 348 | return rc < 0 ? FAILED_TO_DISASSEMBLE_OPERAND : DISASM_SUCCESS; 349 | } 350 | 351 | uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, char *outBuffer, uint32_t outBufferSize, uint32_t type) 352 | { 353 | char shiftBuff[48] = {0}; 354 | char immBuff[32] = {0}; 355 | const char *sign = ""; 356 | if (instructionOperand == NULL) 357 | return FAILED_TO_DISASSEMBLE_OPERAND; 358 | 359 | uint64_t imm = instructionOperand->immediate; 360 | if (instructionOperand->signedImm == 1 && ((int64_t)imm) < 0) 361 | { 362 | sign = "-"; 363 | imm = -(int64_t)imm; 364 | } 365 | if (instructionOperand->shiftType != ShiftType_NONE) 366 | { 367 | if (instructionOperand->shiftValueUsed != 0) 368 | { 369 | if (snprintf(immBuff, sizeof(immBuff), " #%#x", instructionOperand->shiftValue) >= sizeof(immBuff)) 370 | { 371 | return FAILED_TO_DISASSEMBLE_REGISTER; 372 | } 373 | } 374 | const char *shiftStr = get_shift(instructionOperand->shiftType); 375 | if (shiftStr == NULL) 376 | return FAILED_TO_DISASSEMBLE_OPERAND; 377 | snprintf( 378 | shiftBuff, 379 | sizeof(shiftBuff), 380 | ", %s%s", 381 | shiftStr, 382 | immBuff); 383 | } 384 | if (type == FIMM32) 385 | { 386 | ImmFloatUnion *ifu = (ImmFloatUnion*)(&instructionOperand->immediate); 387 | if (snprintf(outBuffer, outBufferSize, "#%.08f%s", ifu->fn, shiftBuff) >= outBufferSize) 388 | return FAILED_TO_DISASSEMBLE_OPERAND; 389 | } 390 | else if (type == IMM32) 391 | { 392 | if (snprintf(outBuffer, outBufferSize, "#%s%#x%s", sign, (uint32_t)imm, shiftBuff) >= outBufferSize) 393 | return FAILED_TO_DISASSEMBLE_OPERAND; 394 | } 395 | else if (type == LABEL) 396 | { 397 | if (snprintf(outBuffer, outBufferSize, "0x%" PRIx64, (uint64_t)imm) >= outBufferSize) 398 | return FAILED_TO_DISASSEMBLE_OPERAND; 399 | } 400 | else if (type == STR_IMM) 401 | { 402 | if (snprintf(outBuffer, outBufferSize, "%s #0x%" PRIx64, instructionOperand->name, (uint64_t)imm) >= outBufferSize) 403 | return FAILED_TO_DISASSEMBLE_OPERAND; 404 | } 405 | else 406 | { 407 | if (snprintf(outBuffer, outBufferSize, "#%s%#" PRIx64 "%s", 408 | sign, 409 | imm, 410 | shiftBuff) >= outBufferSize) 411 | return FAILED_TO_DISASSEMBLE_OPERAND; 412 | } 413 | return DISASM_SUCCESS; 414 | } 415 | 416 | uint32_t get_sme_tile(const InstructionOperand *operand, char *outBuffer, uint32_t outBufferSize) 417 | { 418 | char base_offset[32] = {'\0'}; 419 | if(operand->reg[0] != REG_NONE) { 420 | if(operand->arrSpec == ARRSPEC_FULL) 421 | snprintf(base_offset, sizeof(base_offset), "[%s]", get_register_name(operand->reg[0])); 422 | else 423 | snprintf(base_offset, sizeof(base_offset), "[%s, #%"PRIu64"]", get_register_name(operand->reg[0]), operand->immediate); 424 | } 425 | 426 | char *slice = ""; 427 | if(operand->slice == SLICE_HORIZONTAL) 428 | slice = "H"; 429 | else if(operand->slice == SLICE_VERTICAL) 430 | slice = "V"; 431 | 432 | if(snprintf(outBuffer, outBufferSize, "Z%d%s%s%s", 433 | operand->tile, 434 | slice, 435 | get_arrspec_str_truncated(operand->arrSpec), 436 | base_offset 437 | ) >= outBufferSize) 438 | return FAILED_TO_DISASSEMBLE_OPERAND; 439 | 440 | return DISASM_SUCCESS; 441 | } 442 | 443 | uint32_t get_indexed_element(const InstructionOperand *operand, char *outBuffer, uint32_t outBufferSize) 444 | { 445 | // make the "{, #}" 446 | char optional_comma_and[32]; 447 | if(operand->immediate) 448 | if(snprintf(optional_comma_and, 32, ", #%" PRIu64, operand->immediate) >= 32) 449 | return FAILED_TO_DISASSEMBLE_OPERAND; 450 | 451 | // .[{, #}] 452 | if(snprintf(outBuffer, outBufferSize, "%s%s[%s%s]", 453 | get_register_name(operand->reg[0]), 454 | get_arrspec_str_truncated(operand->arrSpec), 455 | get_register_name(operand->reg[1]), 456 | optional_comma_and 457 | ) >= outBufferSize) 458 | return FAILED_TO_DISASSEMBLE_OPERAND; 459 | 460 | return DISASM_SUCCESS; 461 | } 462 | 463 | uint32_t get_accum_array(const InstructionOperand *operand, char *outBuffer, uint32_t outBufferSize) 464 | { 465 | if(snprintf(outBuffer, outBufferSize, "ZA[%s, #%" PRIu64 "]", 466 | get_register_name(operand->reg[0]), operand->immediate 467 | ) >= outBufferSize) 468 | return FAILED_TO_DISASSEMBLE_OPERAND; 469 | 470 | return DISASM_SUCCESS; 471 | } 472 | 473 | //----------------------------------------------------------------------------- 474 | // disassemble (decoded Instruction -> string) 475 | //----------------------------------------------------------------------------- 476 | 477 | int aarch64_disassemble(Instruction *instruction, char *buf, size_t buf_sz) 478 | { 479 | char operandStrings[MAX_OPERANDS][130]; 480 | char tmpOperandString[128]; 481 | const char *operand = tmpOperandString; 482 | if (instruction == NULL || buf_sz == 0 || buf == NULL) 483 | return INVALID_ARGUMENTS; 484 | 485 | memset(operandStrings, 0, sizeof(operandStrings)); 486 | const char *operation = get_operation(instruction); 487 | if (operation == NULL) 488 | return FAILED_TO_DISASSEMBLE_OPERATION; 489 | 490 | for(int i=0; ioperands[i].operandClass != NONE; i++) 494 | { 495 | switch (instruction->operands[i].operandClass) 496 | { 497 | case CONDITION: 498 | if (snprintf(tmpOperandString, sizeof(tmpOperandString), "%s", 499 | get_condition((Condition)instruction->operands[i].cond)) >= sizeof(tmpOperandString)) 500 | return FAILED_TO_DISASSEMBLE_OPERAND; 501 | operand = tmpOperandString; 502 | break; 503 | case FIMM32: 504 | case IMM32: 505 | case IMM64: 506 | case LABEL: 507 | case STR_IMM: 508 | if (get_shifted_immediate( 509 | &instruction->operands[i], 510 | tmpOperandString, 511 | sizeof(tmpOperandString), 512 | instruction->operands[i].operandClass) != DISASM_SUCCESS) 513 | return FAILED_TO_DISASSEMBLE_OPERAND; 514 | operand = tmpOperandString; 515 | break; 516 | case REG: 517 | if (get_register( 518 | &instruction->operands[i], 519 | 0, 520 | tmpOperandString, 521 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 522 | return FAILED_TO_DISASSEMBLE_OPERAND; 523 | operand = tmpOperandString; 524 | break; 525 | case SYS_REG: 526 | operand = get_system_register_name(instruction->operands[i].sysreg); 527 | if (operand == NULL) 528 | { 529 | return FAILED_TO_DISASSEMBLE_OPERAND; 530 | } 531 | break; 532 | case MULTI_REG: 533 | if (get_multireg_operand( 534 | &instruction->operands[i], 535 | tmpOperandString, 536 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 537 | { 538 | return FAILED_TO_DISASSEMBLE_OPERAND; 539 | } 540 | operand = tmpOperandString; 541 | break; 542 | case IMPLEMENTATION_SPECIFIC: 543 | if (get_implementation_specific( 544 | &instruction->operands[i], 545 | tmpOperandString, 546 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 547 | { 548 | return FAILED_TO_DISASSEMBLE_OPERAND; 549 | } 550 | operand = tmpOperandString; 551 | break; 552 | case MEM_REG: 553 | case MEM_OFFSET: 554 | case MEM_EXTENDED: 555 | case MEM_PRE_IDX: 556 | case MEM_POST_IDX: 557 | if (get_memory_operand(&instruction->operands[i], 558 | tmpOperandString, 559 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 560 | return FAILED_TO_DISASSEMBLE_OPERAND; 561 | operand = tmpOperandString; 562 | break; 563 | case SME_TILE: 564 | if(get_sme_tile(&instruction->operands[i], 565 | tmpOperandString, 566 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 567 | return FAILED_TO_DISASSEMBLE_OPERAND; 568 | operand = tmpOperandString; 569 | break; 570 | case INDEXED_ELEMENT: 571 | if(get_indexed_element(&instruction->operands[i], 572 | tmpOperandString, 573 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 574 | return FAILED_TO_DISASSEMBLE_OPERAND; 575 | operand = tmpOperandString; 576 | break; 577 | case ACCUM_ARRAY: 578 | if(get_accum_array(&instruction->operands[i], 579 | tmpOperandString, 580 | sizeof(tmpOperandString)) != DISASM_SUCCESS) 581 | return FAILED_TO_DISASSEMBLE_OPERAND; 582 | operand = tmpOperandString; 583 | break; 584 | case NAME: 585 | operand = instruction->operands[i].name; 586 | break; 587 | case NONE: 588 | break; 589 | } 590 | snprintf(operandStrings[i], sizeof(operandStrings[i]), i==0?"\t%s":", %s", operand); 591 | } 592 | memset(buf, 0, buf_sz); 593 | if (snprintf(buf, buf_sz, "%s%s%s%s%s%s", 594 | get_operation(instruction), 595 | operandStrings[0], 596 | operandStrings[1], 597 | operandStrings[2], 598 | operandStrings[3], 599 | operandStrings[4]) >= buf_sz) 600 | return OUTPUT_BUFFER_TOO_SMALL; 601 | return DISASM_SUCCESS; 602 | } 603 | 604 | void print_instruction(Instruction *instr) 605 | { 606 | //printf("print_instruction (TODO)\n"); 607 | } 608 | -------------------------------------------------------------------------------- /disassembler/pcode.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "decode.h" 6 | #include "pcode.h" 7 | 8 | int BitCount(uint32_t x) 9 | { 10 | int result = 0; 11 | while (x) 12 | { 13 | if (x & 1) 14 | result += 1; 15 | x >>= 1; 16 | } 17 | return result; 18 | } 19 | 20 | bool BFXPreferred(uint32_t sf, uint32_t uns, uint32_t imms, uint32_t immr) 21 | { 22 | // must not match UBFIZ/SBFIX alias 23 | if (imms < immr) 24 | return false; 25 | 26 | // must not match LSR/ASR/LSL alias (imms == 31 or 63) 27 | if (imms == ((sf << 5) | 0x1F)) 28 | return false; 29 | 30 | // must not match UXTx/SXTx alias 31 | if (immr == 0) 32 | { 33 | // must not match 32-bit UXT[BH] or SXT[BH] 34 | if (sf == 0 && (imms == 7 || imms == 15)) 35 | return false; 36 | 37 | // must not match 64-bit SXT[BHW] 38 | if ((sf == 1 && uns == 0) && (imms == 7 || imms == 15 || imms == 31)) 39 | return false; 40 | } 41 | 42 | // must be UBFX/SBFX alias 43 | return true; 44 | } 45 | 46 | uint64_t rotate_right(uint64_t x, unsigned width, unsigned amount) 47 | { 48 | amount = amount % width; 49 | x = (x >> amount) | (x << (width - amount)); 50 | x = (width < 64) ? x & (((uint64_t)1 << width) - 1) : x; 51 | return x; 52 | } 53 | 54 | DecodeBitMasks_ReturnType DecodeBitMasks( 55 | uint8_t /*bit*/ immN, uint8_t /*bit(6)*/ imms, uint8_t /*bit(6)*/ immr) 56 | { 57 | int ones_nbits = 0; 58 | if (immN == 1) 59 | ones_nbits = 6; 60 | else if ((imms & 0x3E) == 0x3C) 61 | ones_nbits = 1; 62 | else if ((imms & 0x3C) == 0x38) 63 | ones_nbits = 2; 64 | else if ((imms & 0x38) == 0x30) 65 | ones_nbits = 3; 66 | else if ((imms & 0x30) == 0x20) 67 | ones_nbits = 4; 68 | else if ((imms & 0x20) == 0) 69 | ones_nbits = 5; 70 | // TODO else: return undefined 71 | 72 | /* set 1's in element */ 73 | int ones_n = (imms & ((1 << ones_nbits) - 1)) + 1; 74 | uint64_t result = ((uint64_t)1 << ones_n) - 1; 75 | 76 | /* rotate element */ 77 | int elem_width = 1 << ones_nbits; 78 | result = rotate_right(result, elem_width, immr); 79 | 80 | /* replicate element */ 81 | while (elem_width < 64) 82 | { 83 | result = (result << elem_width) | result; 84 | elem_width *= 2; 85 | } 86 | 87 | DecodeBitMasks_ReturnType dbmrt; 88 | // TODO: do this right 89 | dbmrt.wmask = result; 90 | dbmrt.tmask = result; 91 | return dbmrt; 92 | } 93 | 94 | /* idea to abandon pseudocode and compute+compare actual bitmask 95 | is from NetBSD sys/arch/aarch64/aarch64/disasm.c */ 96 | bool MoveWidePreferred(uint32_t sf, uint32_t immN, uint32_t immS, uint32_t immR) 97 | { 98 | uint32_t splat = (immN << 6) | immS; 99 | if (sf == 1 && !((splat & 0x40) == 0x40)) 100 | return false; 101 | if (sf == 0 && !((splat & 0x60) == 0x00)) 102 | return false; 103 | 104 | DecodeBitMasks_ReturnType dbmrt = DecodeBitMasks(sf, immS, immR); 105 | uint64_t imm = dbmrt.wmask; 106 | 107 | /* MOVZ check, at most 16 zeroes not across halfword (16-bit) boundary */ 108 | if (sf == 0) 109 | imm &= 0xffffffff; 110 | if (((imm & 0xffffffffffff0000) == 0) || ((imm & 0xffffffff0000ffff) == 0) || 111 | ((imm & 0xffff0000ffffffff) == 0) || ((imm & 0x0000ffffffffffff) == 0)) 112 | return true; 113 | 114 | /* MOVN check, at most 16 ones not across halfword (16-bit) boundary */ 115 | imm = ~imm; 116 | if (sf == 0) 117 | imm &= 0xffffffff; 118 | if (((imm & 0xffffffffffff0000) == 0) || ((imm & 0xffffffff0000ffff) == 0) || 119 | ((imm & 0xffff0000ffffffff) == 0) || ((imm & 0x0000ffffffffffff) == 0)) 120 | return true; 121 | 122 | return false; 123 | } 124 | 125 | int HighestSetBit(uint64_t x) 126 | { 127 | for (int i = 63; i >= 0 && x; --i) 128 | { 129 | if (x & 0x8000000000000000) 130 | return i; 131 | x <<= 1; 132 | } 133 | 134 | return -1; 135 | } 136 | 137 | int LowestSetBit(uint64_t x) 138 | { 139 | for (int i = 0; i < 64; ++i) 140 | { 141 | if (x & 1) 142 | return i; 143 | x >>= 1; 144 | } 145 | 146 | return -1; 147 | } 148 | 149 | bool SVEMoveMaskPreferred(uint32_t imm13) 150 | { 151 | // TODO: populate this 152 | return true; 153 | } 154 | 155 | enum ShiftType DecodeRegExtend(uint8_t op) 156 | { 157 | switch (op & 7) 158 | { 159 | case 0b000: 160 | return ShiftType_UXTB; 161 | case 0b001: 162 | return ShiftType_UXTH; 163 | case 0b010: 164 | return ShiftType_UXTW; 165 | case 0b011: 166 | return ShiftType_UXTX; 167 | case 0b100: 168 | return ShiftType_SXTB; 169 | case 0b101: 170 | return ShiftType_SXTH; 171 | case 0b110: 172 | return ShiftType_SXTW; 173 | case 0b111: 174 | return ShiftType_SXTX; 175 | default: 176 | return ShiftType_NONE; 177 | } 178 | } 179 | 180 | enum ShiftType DecodeShift(uint8_t op) 181 | { 182 | switch (op & 3) 183 | { 184 | case 0b00: 185 | return ShiftType_LSL; 186 | case 0b01: 187 | return ShiftType_LSR; 188 | case 0b10: 189 | return ShiftType_ASR; 190 | case 0b11: 191 | return ShiftType_ROR; 192 | default: 193 | return ShiftType_NONE; 194 | } 195 | } 196 | 197 | enum SystemOp SysOp(uint32_t op1, uint32_t CRn, uint32_t CRm, uint32_t op2) 198 | { 199 | uint32_t tmp = (op1 << 11) | (CRn << 7) | (CRm << 3) | op2; 200 | 201 | switch (tmp) 202 | { 203 | case 0b00001111000000: 204 | return Sys_AT; // S1E1R 205 | case 0b10001111000000: 206 | return Sys_AT; // S1E2R 207 | case 0b11001111000000: 208 | return Sys_AT; // S1E3R 209 | case 0b00001111000001: 210 | return Sys_AT; // S1E1W 211 | case 0b00001111001001: 212 | return Sys_AT; // S1E1WP 213 | case 0b10001111000001: 214 | return Sys_AT; // S1E2W 215 | case 0b11001111000001: 216 | return Sys_AT; // S1E3W 217 | case 0b00001111000010: 218 | return Sys_AT; // S1E0R 219 | case 0b00001111000011: 220 | return Sys_AT; // S1E0W 221 | case 0b10001111000100: 222 | return Sys_AT; // S12E1R 223 | case 0b10001111000101: 224 | return Sys_AT; // S12E1W 225 | case 0b10001111000110: 226 | return Sys_AT; // S12E0R 227 | case 0b10001111000111: 228 | return Sys_AT; // S12E0W 229 | case 0b01101110100001: 230 | return Sys_DC; // ZVA 231 | case 0b00001110110001: 232 | return Sys_DC; // IVAC 233 | case 0b00001110110010: 234 | return Sys_DC; // ISW 235 | case 0b01101111010001: 236 | return Sys_DC; // CVAC 237 | case 0b00001111010010: 238 | return Sys_DC; // CSW 239 | case 0b01101111011001: 240 | return Sys_DC; // CVAU 241 | case 0b01101111110001: 242 | return Sys_DC; // CIVAC 243 | case 0b00001111110010: 244 | return Sys_DC; // CISW 245 | case 0b01101111101001: 246 | return Sys_DC; // CVADP 247 | case 0b00001110001000: 248 | return Sys_IC; // IALLUIS 249 | case 0b00001110101000: 250 | return Sys_IC; // IALLU 251 | case 0b01101110101001: 252 | return Sys_IC; // IVAU 253 | case 0b10010000000001: 254 | return Sys_TLBI; // IPAS2E1IS 255 | case 0b10010000000101: 256 | return Sys_TLBI; // IPAS2LE1IS 257 | case 0b00010000011000: 258 | return Sys_TLBI; // VMALLE1IS 259 | case 0b10010000011000: 260 | return Sys_TLBI; // ALLE2IS 261 | case 0b11010000011000: 262 | return Sys_TLBI; // ALLE3IS 263 | case 0b00010000011001: 264 | return Sys_TLBI; // VAE1IS 265 | case 0b10010000011001: 266 | return Sys_TLBI; // VAE2IS 267 | case 0b11010000011001: 268 | return Sys_TLBI; // VAE3IS 269 | case 0b00010000011010: 270 | return Sys_TLBI; // ASIDE1IS 271 | case 0b00010000011011: 272 | return Sys_TLBI; // VAAE1IS 273 | case 0b10010000011100: 274 | return Sys_TLBI; // ALLE1IS 275 | case 0b00010000011101: 276 | return Sys_TLBI; // VALE1IS 277 | case 0b10010000011101: 278 | return Sys_TLBI; // VALE2IS 279 | case 0b11010000011101: 280 | return Sys_TLBI; // VALE3IS 281 | case 0b10010000011110: 282 | return Sys_TLBI; // VMALLS12E1IS 283 | case 0b00010000011111: 284 | return Sys_TLBI; // VAALE1IS 285 | case 0b10010000100001: 286 | return Sys_TLBI; // IPAS2E1 287 | case 0b10010000100101: 288 | return Sys_TLBI; // IPAS2LE1 289 | case 0b00010000111000: 290 | return Sys_TLBI; // VMALLE1 291 | case 0b10010000111000: 292 | return Sys_TLBI; // ALLE2 293 | case 0b11010000111000: 294 | return Sys_TLBI; // ALLE3 295 | case 0b00010000111001: 296 | return Sys_TLBI; // VAE1 297 | case 0b10010000111001: 298 | return Sys_TLBI; // VAE2 299 | case 0b11010000111001: 300 | return Sys_TLBI; // VAE3 301 | case 0b00010000111010: 302 | return Sys_TLBI; // ASIDE1 303 | case 0b00010000111011: 304 | return Sys_TLBI; // VAAE1 305 | case 0b10010000111100: 306 | return Sys_TLBI; // ALLE1 307 | case 0b00010000111101: 308 | return Sys_TLBI; // VALE1 309 | case 0b10010000111101: 310 | return Sys_TLBI; // VALE2 311 | case 0b11010000111101: 312 | return Sys_TLBI; // VALE3 313 | case 0b10010000111110: 314 | return Sys_TLBI; // VMALLS12E1 315 | case 0b00010000111111: 316 | return Sys_TLBI; // VAALE1 317 | default: 318 | return Sys_ERROR; 319 | } 320 | } 321 | 322 | uint32_t UInt(uint32_t foo) 323 | { 324 | return foo; 325 | } 326 | 327 | uint32_t BitSlice(uint64_t foo, int hi, int lo) // including the endpoints 328 | { 329 | int width = hi - lo + 1; 330 | uint64_t mask = (1 << width) - 1; 331 | return (foo >> lo) & mask; 332 | } 333 | 334 | bool IsZero(uint64_t foo) 335 | { 336 | return foo == 0; 337 | } 338 | 339 | bool IsOnes(uint64_t foo, int width) 340 | { 341 | return foo == (1 << width) - 1; 342 | } 343 | 344 | /* Mozilla MPL 345 | TODO: evaluate license, possibly rewrite 346 | https://github.com/Siguza/iometa/blob/master/src/a64.c */ 347 | uint64_t Replicate(uint64_t val, uint8_t times, uint64_t width) 348 | { 349 | // Fast path 350 | switch (times) 351 | { 352 | case 64: 353 | val |= val << width; 354 | width <<= 1; 355 | case 32: 356 | val |= val << width; 357 | width <<= 1; 358 | case 16: 359 | val |= val << width; 360 | width <<= 1; 361 | case 8: 362 | val |= val << width; 363 | width <<= 1; 364 | case 4: 365 | val |= val << width; 366 | width <<= 1; 367 | case 2: 368 | val |= val << width; 369 | case 1: 370 | return val; 371 | case 0: 372 | return 0; 373 | default: 374 | break; 375 | } 376 | // Slow path 377 | uint64_t orig = val; 378 | for (size_t i = 0; i < times; ++i) 379 | { 380 | val <<= width; 381 | val |= orig; 382 | } 383 | return val; 384 | } 385 | 386 | /* Mozilla MPL 387 | TODO: evaluate license, possibly rewrite 388 | https://github.com/Siguza/iometa/blob/master/src/a64.c */ 389 | uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8) 390 | { 391 | uint64_t imm64 = 0; 392 | switch((cmode >> 1) & 0b111) 393 | { 394 | case 0b000: 395 | imm64 = Replicate(imm8, 2, 32); 396 | break; 397 | case 0b001: 398 | imm64 = Replicate(imm8 << 8, 2, 32); 399 | break; 400 | case 0b010: 401 | imm64 = Replicate(imm8 << 16, 2, 32); 402 | break; 403 | case 0b011: 404 | imm64 = Replicate(imm8 << 24, 2, 32); 405 | break; 406 | case 0b100: 407 | imm64 = Replicate(imm8, 4, 16); 408 | break; 409 | case 0b101: 410 | imm64 = Replicate(imm8 << 8, 4, 16); 411 | break; 412 | case 0b110: 413 | imm64 = Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32); 414 | break; 415 | case 0b111: 416 | switch (((cmode & 0b1) << 1) | op) 417 | { 418 | case 0b00: 419 | imm64 = Replicate(imm8, 8, 8); 420 | break; 421 | case 0b01: 422 | #if 0 423 | imm8a = Replicate((imm8 >> 7) & 0b1, 8, 1); 424 | imm8b = Replicate((imm8 >> 6) & 0b1, 8, 1); 425 | imm8c = Replicate((imm8 >> 5) & 0b1, 8, 1); 426 | imm8d = Replicate((imm8 >> 4) & 0b1, 8, 1); 427 | imm8e = Replicate((imm8 >> 3) & 0b1, 8, 1); 428 | imm8f = Replicate((imm8 >> 2) & 0b1, 8, 1); 429 | imm8g = Replicate((imm8 >> 1) & 0b1, 8, 1); 430 | imm8h = Replicate((imm8 ) & 0b1, 8, 1); 431 | imm64 = (imm8a << 0x38) | (imm8b << 0x30) | (imm8c << 0x28) | (imm8d << 0x20) | (imm8e << 0x18) | (imm8f << 0x10) | (imm8g << 0x08) | imm8h; 432 | #else 433 | imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) | 434 | (imm8 << (0x20 - 4)) | (imm8 << (0x28 - 5)) | (imm8 << (0x30 - 6)) | 435 | (imm8 << (0x38 - 7)); 436 | imm64 &= 0x0101010101010101; 437 | imm64 = Replicate(imm64, 8, 1); 438 | #endif 439 | break; 440 | case 0b10: 441 | imm64 = Replicate((((imm8 & 0xc0) ^ 0x80) << 24) | 442 | (Replicate((imm8 >> 6) & 0b1, 5, 1) << 25) | ((imm8 & 0x3f) << 19), 443 | 2, 32); 444 | break; 445 | case 0b11: 446 | imm64 = (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) | 447 | ((imm8 & 0x3f) << 48); 448 | break; 449 | } 450 | break; 451 | } 452 | return imm64; 453 | } 454 | 455 | bool BTypeCompatible_BTI(uint8_t hintcode, uint8_t pstate_btype) 456 | { 457 | switch (hintcode & 3) 458 | { 459 | case 0b00: 460 | return false; 461 | case 0b01: 462 | return pstate_btype != 0b11; 463 | case 0b10: 464 | return pstate_btype != 0b10; 465 | case 0b11: 466 | return true; 467 | } 468 | 469 | return false; /* impossible, but appease compiler */ 470 | } 471 | 472 | bool BTypeCompatible_PACIXSP() 473 | { 474 | // TODO: determine if filling this in is necessary 475 | return true; 476 | } 477 | 478 | enum FPRounding FPDecodeRounding(uint8_t RMode) 479 | { 480 | switch (RMode & 3) 481 | { 482 | case 0b00: 483 | return FPRounding_TIEEVEN; // N 484 | case 0b01: 485 | return FPRounding_POSINF; // P 486 | case 0b10: 487 | return FPRounding_NEGINF; // M 488 | case 0b11: 489 | return FPRounding_ZERO; // Z 490 | } 491 | 492 | return FPRounding_ERROR; 493 | } 494 | 495 | enum FPRounding FPRoundingMode(uint64_t fpcr) 496 | { 497 | return FPDecodeRounding(FPCR_GET_RMode(fpcr)); 498 | } 499 | 500 | bool HaltingAllowed(void) 501 | { 502 | // TODO: determine if filling this in is necessary 503 | return true; 504 | } 505 | 506 | // AArch64.SystemAccessTrap 507 | void SystemAccessTrap(uint32_t a, uint32_t b) 508 | { 509 | // TODO: determine if filling this in is necessary 510 | while (0) 511 | ; 512 | } 513 | 514 | void CheckSystemAccess(uint8_t a, uint8_t b, uint8_t c, uint8_t d, uint8_t e, uint8_t f, uint8_t g) 515 | { 516 | // TODO: determine if filling this in is necessary 517 | while (0) 518 | ; 519 | } 520 | 521 | // from LLVM 522 | // TODO: check license, determine if rewrite needed 523 | uint64_t VFPExpandImm(unsigned char byte, unsigned N) 524 | { 525 | // assert(N == 32 || N == 64); 526 | 527 | uint64_t Result; 528 | unsigned bit6 = SLICE(byte, 6, 6); 529 | if (N == 32) 530 | { 531 | Result = SLICE(byte, 7, 7) << 31 | SLICE(byte, 5, 0) << 19; 532 | if (bit6) 533 | Result |= 0x1f << 25; 534 | else 535 | Result |= 0x1 << 30; 536 | } 537 | else 538 | { 539 | Result = (uint64_t)SLICE(byte, 7, 7) << 63 | (uint64_t)SLICE(byte, 5, 0) << 48; 540 | if (bit6) 541 | Result |= 0xffULL << 54; 542 | else 543 | Result |= 0x1ULL << 62; 544 | } 545 | 546 | // return APInt(N, Result); 547 | return Result; 548 | } 549 | 550 | bool EL2Enabled(void) 551 | { 552 | // TODO: determine if filling this in is necessary 553 | return true; 554 | } 555 | 556 | bool ELUsingAArch32(uint8_t x) 557 | { 558 | // TODO: determine if filling this in is necessary 559 | return true; 560 | } 561 | 562 | uint64_t FPOne(bool sign, int N) 563 | { 564 | // width should be 16, 32, 64 565 | int E, F, exp; 566 | 567 | switch (N) 568 | { 569 | case 16: 570 | E = 5; 571 | case 32: 572 | E = 8; 573 | default: 574 | E = 11; 575 | } 576 | 577 | F = N - (E + 1); 578 | exp = BITMASK(E - 1) << 1; 579 | return (sign << (E - 1 + F)) | (exp << F); 580 | } 581 | 582 | uint64_t FPTwo(bool sign, int N) 583 | { 584 | // width should be 16, 32, 64 585 | //int F; 586 | int E, exp; 587 | 588 | switch (N) 589 | { 590 | case 16: 591 | E = 5; 592 | case 32: 593 | E = 8; 594 | default: 595 | E = 11; 596 | } 597 | 598 | exp = 1 << (E - 1); 599 | return (sign << E)|exp; 600 | } 601 | 602 | uint64_t FPPointFive(bool sign, int N) 603 | { 604 | // width should be 16, 32, 64 605 | int E, F, exp; 606 | 607 | switch (N) 608 | { 609 | case 16: 610 | E = 5; 611 | case 32: 612 | E = 8; 613 | default: 614 | E = 11; 615 | } 616 | 617 | F = N - (E + 1); 618 | exp = BITMASK(E - 2) << 1; 619 | return (sign << (E - 2 + F)) | (exp << F); 620 | } 621 | 622 | uint64_t SignExtend(uint64_t x, int width) 623 | { 624 | uint64_t result = -1; 625 | 626 | if (x & ((uint64_t)1 << (width - 1))) 627 | { 628 | result ^= (((uint64_t)1 << width) - 1); 629 | result |= x; 630 | } 631 | else 632 | { 633 | result = x; 634 | } 635 | 636 | return result; 637 | } 638 | 639 | enum Constraint ConstrainUnpredictable(enum Unpredictable u) 640 | { 641 | switch (u) 642 | { 643 | case Unpredictable_VMSR: 644 | return Constraint_UNDEF; 645 | case Unpredictable_WBOVERLAPLD: 646 | return Constraint_WBSUPPRESS; // return loaded value 647 | case Unpredictable_WBOVERLAPST: 648 | return Constraint_NONE; // store pre-writeback value 649 | case Unpredictable_LDPOVERLAP: 650 | return Constraint_UNDEF; // instruction is UNDEFINED 651 | case Unpredictable_BASEOVERLAP: 652 | return Constraint_NONE; // use original address 653 | case Unpredictable_DATAOVERLAP: 654 | return Constraint_NONE; // store original value 655 | case Unpredictable_DEVPAGE2: 656 | return Constraint_FAULT; // take an alignment fault 657 | case Unpredictable_DEVICETAGSTORE: 658 | return Constraint_NONE; // Do not take a fault 659 | case Unpredictable_INSTRDEVICE: 660 | return Constraint_NONE; // Do not take a fault 661 | case Unpredictable_RESCPACR: 662 | return Constraint_TRUE; // Map to UNKNOWN value 663 | case Unpredictable_RESMAIR: 664 | return Constraint_UNKNOWN; // Map to UNKNOWN value 665 | case Unpredictable_RESTEXCB: 666 | return Constraint_UNKNOWN; // Map to UNKNOWN value 667 | case Unpredictable_RESDACR: 668 | return Constraint_UNKNOWN; // Map to UNKNOWN value 669 | case Unpredictable_RESPRRR: 670 | return Constraint_UNKNOWN; // Map to UNKNOWN value 671 | case Unpredictable_RESVTCRS: 672 | return Constraint_UNKNOWN; // Map to UNKNOWN value 673 | case Unpredictable_RESTnSZ: 674 | return Constraint_FORCE; // Map to the limit value 675 | case Unpredictable_OORTnSZ: 676 | return Constraint_FORCE; // Map to the limit value 677 | case Unpredictable_LARGEIPA: 678 | return Constraint_FORCE; // Restrict the inputsize to the PAMax value 679 | case Unpredictable_ESRCONDPASS: 680 | return Constraint_FALSE; // Report as "AL" 681 | case Unpredictable_ILZEROIT: 682 | return Constraint_FALSE; // Do not zero PSTATE.IT 683 | case Unpredictable_ILZEROT: 684 | return Constraint_FALSE; // Do not zero PSTATE.T 685 | case Unpredictable_BPVECTORCATCHPRI: 686 | return Constraint_TRUE; // Debug Vector Catch: match on 2nd halfword 687 | case Unpredictable_VCMATCHHALF: 688 | return Constraint_FALSE; // No match 689 | case Unpredictable_VCMATCHDAPA: 690 | return Constraint_FALSE; // No match on Data Abort or Prefetch abort 691 | case Unpredictable_WPMASKANDBAS: 692 | return Constraint_FALSE; // Watchpoint disabled 693 | case Unpredictable_WPBASCONTIGUOUS: 694 | return Constraint_FALSE; // Watchpoint disabled 695 | case Unpredictable_RESWPMASK: 696 | return Constraint_DISABLED; // Watchpoint disabled 697 | case Unpredictable_WPMASKEDBITS: 698 | return Constraint_FALSE; // Watchpoint disabled 699 | case Unpredictable_RESBPWPCTRL: 700 | return Constraint_DISABLED; // Breakpoint/watchpoint disabled 701 | case Unpredictable_BPNOTIMPL: 702 | return Constraint_DISABLED; // Breakpoint disabled 703 | case Unpredictable_RESBPTYPE: 704 | return Constraint_DISABLED; // Breakpoint disabled 705 | case Unpredictable_BPNOTCTXCMP: 706 | return Constraint_DISABLED; // Breakpoint disabled 707 | case Unpredictable_BPMATCHHALF: 708 | return Constraint_FALSE; // No match 709 | case Unpredictable_BPMISMATCHHALF: 710 | return Constraint_FALSE; // No match 711 | case Unpredictable_RESTARTALIGNPC: 712 | return Constraint_FALSE; // Do not force alignment 713 | case Unpredictable_RESTARTZEROUPPERPC: 714 | return Constraint_TRUE; // Force zero extension 715 | case Unpredictable_ZEROUPPER: 716 | return Constraint_TRUE; // zero top halves of X registers 717 | case Unpredictable_ERETZEROUPPERPC: 718 | return Constraint_TRUE; // zero top half of PC 719 | case Unpredictable_A32FORCEALIGNPC: 720 | return Constraint_FALSE; // Do not force alignment 721 | case Unpredictable_SMD: 722 | return Constraint_UNDEF; // disabled SMC is Unallocated 723 | case Unpredictable_NONFAULT: 724 | return Constraint_FALSE; // Speculation enabled 725 | case Unpredictable_SVEZEROUPPER: 726 | return Constraint_TRUE; // zero top bits of Z registers 727 | case Unpredictable_SVELDNFDATA: 728 | return Constraint_TRUE; // Load mem data in NF loads 729 | case Unpredictable_SVELDNFZERO: 730 | return Constraint_TRUE; // Write zeros in NF loads 731 | case Unpredictable_CHECKSPNONEACTIVE: 732 | return Constraint_TRUE; // Check SP alignment 733 | case Unpredictable_AFUPDATE: 734 | return Constraint_TRUE; 735 | case Unpredictable_IESBinDebug: 736 | return Constraint_TRUE; 737 | case Unpredictable_BADPMSFCR: 738 | return Constraint_TRUE; 739 | case Unpredictable_ZEROBTYPE: 740 | return Constraint_TRUE; // Save BTYPE in SPSR_ELx/DPSR_EL0 as '00' 741 | case Unpredictable_CLEARERRITEZERO: 742 | return Constraint_FALSE; 743 | case Unpredictable_ALUEXCEPTIONRETURN: 744 | return Constraint_UNDEF; 745 | case Unpredictable_DBGxVR_RESS: 746 | return Constraint_FALSE; 747 | case Unpredictable_WFxTDEBUG: 748 | return Constraint_FALSE; // WFxT in Debug state does not execute as a NOP 749 | case Unpredictable_LS64UNSUPPORTED: 750 | return Constraint_LIMITED_ATOMICITY; // 751 | default: 752 | return Constraint_ERROR; 753 | } 754 | } 755 | -------------------------------------------------------------------------------- /disassembler/decode1.h: -------------------------------------------------------------------------------- 1 | /* GENERATED FILE */ 2 | #pragma once 3 | int decode_iclass_barriers(context *ctx, Instruction *dec); 4 | int decode_iclass_compbranch(context *ctx, Instruction *dec); 5 | int decode_iclass_condbranch(context *ctx, Instruction *dec); 6 | int decode_iclass_exception(context *ctx, Instruction *dec); 7 | int decode_iclass_hints(context *ctx, Instruction *dec); 8 | int decode_iclass_pstate(context *ctx, Instruction *dec); 9 | int decode_iclass_systeminstrs(context *ctx, Instruction *dec); 10 | int decode_iclass_systeminstrswithreg(context *ctx, Instruction *dec); 11 | int decode_iclass_systemmove(context *ctx, Instruction *dec); 12 | int decode_iclass_systemresult(context *ctx, Instruction *dec); 13 | int decode_iclass_testbranch(context *ctx, Instruction *dec); 14 | int decode_iclass_branch_imm(context *ctx, Instruction *dec); 15 | int decode_iclass_branch_reg(context *ctx, Instruction *dec); 16 | int decode_iclass_asisdlse(context *ctx, Instruction *dec); 17 | int decode_iclass_asisdlsep(context *ctx, Instruction *dec); 18 | int decode_iclass_asisdlso(context *ctx, Instruction *dec); 19 | int decode_iclass_asisdlsop(context *ctx, Instruction *dec); 20 | int decode_iclass_memop(context *ctx, Instruction *dec); 21 | int decode_iclass_comswap(context *ctx, Instruction *dec); 22 | int decode_iclass_comswappr(context *ctx, Instruction *dec); 23 | int decode_iclass_ldapstl_unscaled(context *ctx, Instruction *dec); 24 | int decode_iclass_loadlit(context *ctx, Instruction *dec); 25 | int decode_iclass_ldstexclp(context *ctx, Instruction *dec); 26 | int decode_iclass_ldstexclr(context *ctx, Instruction *dec); 27 | int decode_iclass_ldsttags(context *ctx, Instruction *dec); 28 | int decode_iclass_ldstnapair_offs(context *ctx, Instruction *dec); 29 | int decode_iclass_ldstord(context *ctx, Instruction *dec); 30 | int decode_iclass_ldst_immpost(context *ctx, Instruction *dec); 31 | int decode_iclass_ldst_immpre(context *ctx, Instruction *dec); 32 | int decode_iclass_ldst_pac(context *ctx, Instruction *dec); 33 | int decode_iclass_ldst_regoff(context *ctx, Instruction *dec); 34 | int decode_iclass_ldst_unpriv(context *ctx, Instruction *dec); 35 | int decode_iclass_ldst_unscaled(context *ctx, Instruction *dec); 36 | int decode_iclass_ldst_pos(context *ctx, Instruction *dec); 37 | int decode_iclass_ldstpair_off(context *ctx, Instruction *dec); 38 | int decode_iclass_ldstpair_post(context *ctx, Instruction *dec); 39 | int decode_iclass_ldstpair_pre(context *ctx, Instruction *dec); 40 | int decode_iclass_addsub_imm(context *ctx, Instruction *dec); 41 | int decode_iclass_addsub_immtags(context *ctx, Instruction *dec); 42 | int decode_iclass_bitfield(context *ctx, Instruction *dec); 43 | int decode_iclass_extract(context *ctx, Instruction *dec); 44 | int decode_iclass_log_imm(context *ctx, Instruction *dec); 45 | int decode_iclass_movewide(context *ctx, Instruction *dec); 46 | int decode_iclass_pcreladdr(context *ctx, Instruction *dec); 47 | int decode_iclass_addsub_ext(context *ctx, Instruction *dec); 48 | int decode_iclass_addsub_shift(context *ctx, Instruction *dec); 49 | int decode_iclass_addsub_carry(context *ctx, Instruction *dec); 50 | int decode_iclass_condcmp_imm(context *ctx, Instruction *dec); 51 | int decode_iclass_condcmp_reg(context *ctx, Instruction *dec); 52 | int decode_iclass_condsel(context *ctx, Instruction *dec); 53 | int decode_iclass_dp_1src(context *ctx, Instruction *dec); 54 | int decode_iclass_dp_2src(context *ctx, Instruction *dec); 55 | int decode_iclass_dp_3src(context *ctx, Instruction *dec); 56 | int decode_iclass_setf(context *ctx, Instruction *dec); 57 | int decode_iclass_log_shift(context *ctx, Instruction *dec); 58 | int decode_iclass_rmif(context *ctx, Instruction *dec); 59 | int decode_iclass_asimdall(context *ctx, Instruction *dec); 60 | int decode_iclass_asimdins(context *ctx, Instruction *dec); 61 | int decode_iclass_asimdext(context *ctx, Instruction *dec); 62 | int decode_iclass_asimdimm(context *ctx, Instruction *dec); 63 | int decode_iclass_asimdperm(context *ctx, Instruction *dec); 64 | int decode_iclass_asisdone(context *ctx, Instruction *dec); 65 | int decode_iclass_asisdpair(context *ctx, Instruction *dec); 66 | int decode_iclass_asisdshf(context *ctx, Instruction *dec); 67 | int decode_iclass_asisddiff(context *ctx, Instruction *dec); 68 | int decode_iclass_asisdsame(context *ctx, Instruction *dec); 69 | int decode_iclass_asisdsamefp16(context *ctx, Instruction *dec); 70 | int decode_iclass_asisdsame2(context *ctx, Instruction *dec); 71 | int decode_iclass_asisdmisc(context *ctx, Instruction *dec); 72 | int decode_iclass_asisdmiscfp16(context *ctx, Instruction *dec); 73 | int decode_iclass_asisdelem(context *ctx, Instruction *dec); 74 | int decode_iclass_asimdshf(context *ctx, Instruction *dec); 75 | int decode_iclass_asimdtbl(context *ctx, Instruction *dec); 76 | int decode_iclass_asimddiff(context *ctx, Instruction *dec); 77 | int decode_iclass_asimdsame(context *ctx, Instruction *dec); 78 | int decode_iclass_asimdsamefp16(context *ctx, Instruction *dec); 79 | int decode_iclass_asimdsame2(context *ctx, Instruction *dec); 80 | int decode_iclass_asimdmisc(context *ctx, Instruction *dec); 81 | int decode_iclass_asimdmiscfp16(context *ctx, Instruction *dec); 82 | int decode_iclass_asimdelem(context *ctx, Instruction *dec); 83 | int decode_iclass_float2fix(context *ctx, Instruction *dec); 84 | int decode_iclass_float2int(context *ctx, Instruction *dec); 85 | int decode_iclass_cryptoaes(context *ctx, Instruction *dec); 86 | int decode_iclass_crypto4(context *ctx, Instruction *dec); 87 | int decode_iclass_cryptosha3(context *ctx, Instruction *dec); 88 | int decode_iclass_cryptosha512_3(context *ctx, Instruction *dec); 89 | int decode_iclass_crypto3_imm2(context *ctx, Instruction *dec); 90 | int decode_iclass_crypto3_imm6(context *ctx, Instruction *dec); 91 | int decode_iclass_cryptosha2(context *ctx, Instruction *dec); 92 | int decode_iclass_cryptosha512_2(context *ctx, Instruction *dec); 93 | int decode_iclass_floatcmp(context *ctx, Instruction *dec); 94 | int decode_iclass_floatccmp(context *ctx, Instruction *dec); 95 | int decode_iclass_floatsel(context *ctx, Instruction *dec); 96 | int decode_iclass_floatdp1(context *ctx, Instruction *dec); 97 | int decode_iclass_floatdp2(context *ctx, Instruction *dec); 98 | int decode_iclass_floatdp3(context *ctx, Instruction *dec); 99 | int decode_iclass_floatimm(context *ctx, Instruction *dec); 100 | int decode_iclass_perm_undef(context *ctx, Instruction *dec); 101 | int decode_iclass_sve_int_bin_pred_log(context *ctx, Instruction *dec); 102 | int decode_iclass_sve_int_bin_pred_arit_0(context *ctx, Instruction *dec); 103 | int decode_iclass_sve_int_bin_pred_div(context *ctx, Instruction *dec); 104 | int decode_iclass_sve_int_bin_pred_arit_1(context *ctx, Instruction *dec); 105 | int decode_iclass_sve_int_bin_pred_arit_2(context *ctx, Instruction *dec); 106 | int decode_iclass_sve_int_reduce_2(context *ctx, Instruction *dec); 107 | int decode_iclass_sve_int_movprfx_pred(context *ctx, Instruction *dec); 108 | int decode_iclass_sve_int_reduce_0(context *ctx, Instruction *dec); 109 | int decode_iclass_sve_int_reduce_1(context *ctx, Instruction *dec); 110 | int decode_iclass_sve_int_bin_pred_shift_0(context *ctx, Instruction *dec); 111 | int decode_iclass_sve_int_bin_pred_shift_1(context *ctx, Instruction *dec); 112 | int decode_iclass_sve_int_bin_pred_shift_2(context *ctx, Instruction *dec); 113 | int decode_iclass_sve_int_un_pred_arit_1(context *ctx, Instruction *dec); 114 | int decode_iclass_sve_int_un_pred_arit_0(context *ctx, Instruction *dec); 115 | int decode_iclass_sve_int_mlas_vvv_pred(context *ctx, Instruction *dec); 116 | int decode_iclass_sve_int_mladdsub_vvv_pred(context *ctx, Instruction *dec); 117 | int decode_iclass_sve_int_bin_cons_arit_0(context *ctx, Instruction *dec); 118 | int decode_iclass_sve_int_bin_cons_log(context *ctx, Instruction *dec); 119 | int decode_iclass_sve_int_tern_log(context *ctx, Instruction *dec); 120 | int decode_iclass_sve_int_rotate_imm(context *ctx, Instruction *dec); 121 | int decode_iclass_sve_int_index_ii(context *ctx, Instruction *dec); 122 | int decode_iclass_sve_int_index_ir(context *ctx, Instruction *dec); 123 | int decode_iclass_sve_int_index_ri(context *ctx, Instruction *dec); 124 | int decode_iclass_sve_int_index_rr(context *ctx, Instruction *dec); 125 | int decode_iclass_sve_int_arith_vl(context *ctx, Instruction *dec); 126 | int decode_iclass_sve_int_read_vl_a(context *ctx, Instruction *dec); 127 | int decode_iclass_sve_int_mul_b(context *ctx, Instruction *dec); 128 | int decode_iclass_sve_int_sqdmulh(context *ctx, Instruction *dec); 129 | int decode_iclass_sve_int_bin_cons_shift_b(context *ctx, Instruction *dec); 130 | int decode_iclass_sve_int_bin_cons_shift_a(context *ctx, Instruction *dec); 131 | int decode_iclass_sve_int_bin_cons_misc_0_a(context *ctx, Instruction *dec); 132 | int decode_iclass_sve_int_bin_cons_misc_0_d(context *ctx, Instruction *dec); 133 | int decode_iclass_sve_int_bin_cons_misc_0_c(context *ctx, Instruction *dec); 134 | int decode_iclass_sve_int_bin_cons_misc_0_b(context *ctx, Instruction *dec); 135 | int decode_iclass_sve_int_count(context *ctx, Instruction *dec); 136 | int decode_iclass_sve_int_pred_pattern_a(context *ctx, Instruction *dec); 137 | int decode_iclass_sve_int_countvlv1(context *ctx, Instruction *dec); 138 | int decode_iclass_sve_int_pred_pattern_b(context *ctx, Instruction *dec); 139 | int decode_iclass_sve_int_countvlv0(context *ctx, Instruction *dec); 140 | int decode_iclass_sve_int_perm_extract_i(context *ctx, Instruction *dec); 141 | int decode_iclass_sve_intx_perm_extract_i(context *ctx, Instruction *dec); 142 | int decode_iclass_sve_int_perm_bin_long_perm_zz(context *ctx, Instruction *dec); 143 | int decode_iclass_sve_int_log_imm(context *ctx, Instruction *dec); 144 | int decode_iclass_sve_int_dup_mask_imm(context *ctx, Instruction *dec); 145 | int decode_iclass_sve_int_dup_fpimm_pred(context *ctx, Instruction *dec); 146 | int decode_iclass_sve_int_dup_imm_pred(context *ctx, Instruction *dec); 147 | int decode_iclass_sve_int_perm_dup_i(context *ctx, Instruction *dec); 148 | int decode_iclass_sve_int_perm_tbl_3src(context *ctx, Instruction *dec); 149 | int decode_iclass_sve_int_perm_tbl(context *ctx, Instruction *dec); 150 | int decode_iclass_sve_int_perm_dup_r(context *ctx, Instruction *dec); 151 | int decode_iclass_sve_int_perm_insrv(context *ctx, Instruction *dec); 152 | int decode_iclass_sve_int_perm_insrs(context *ctx, Instruction *dec); 153 | int decode_iclass_sve_int_perm_reverse_z(context *ctx, Instruction *dec); 154 | int decode_iclass_sve_int_perm_unpk(context *ctx, Instruction *dec); 155 | int decode_iclass_sve_int_perm_bin_perm_pp(context *ctx, Instruction *dec); 156 | int decode_iclass_sve_int_perm_reverse_p(context *ctx, Instruction *dec); 157 | int decode_iclass_sve_int_perm_punpk(context *ctx, Instruction *dec); 158 | int decode_iclass_sve_int_perm_bin_perm_zz(context *ctx, Instruction *dec); 159 | int decode_iclass_sve_int_perm_compact(context *ctx, Instruction *dec); 160 | int decode_iclass_sve_int_perm_clast_zz(context *ctx, Instruction *dec); 161 | int decode_iclass_sve_int_perm_clast_vz(context *ctx, Instruction *dec); 162 | int decode_iclass_sve_int_perm_clast_rz(context *ctx, Instruction *dec); 163 | int decode_iclass_sve_int_perm_cpy_v(context *ctx, Instruction *dec); 164 | int decode_iclass_sve_int_perm_cpy_r(context *ctx, Instruction *dec); 165 | int decode_iclass_sve_int_perm_last_v(context *ctx, Instruction *dec); 166 | int decode_iclass_sve_int_perm_last_r(context *ctx, Instruction *dec); 167 | int decode_iclass_sve_int_perm_revd(context *ctx, Instruction *dec); 168 | int decode_iclass_sve_int_perm_rev(context *ctx, Instruction *dec); 169 | int decode_iclass_sve_int_perm_splice(context *ctx, Instruction *dec); 170 | int decode_iclass_sve_intx_perm_splice(context *ctx, Instruction *dec); 171 | int decode_iclass_sve_int_sel_vvv(context *ctx, Instruction *dec); 172 | int decode_iclass_sve_int_cmp_0(context *ctx, Instruction *dec); 173 | int decode_iclass_sve_int_cmp_1(context *ctx, Instruction *dec); 174 | int decode_iclass_sve_int_ucmp_vi(context *ctx, Instruction *dec); 175 | int decode_iclass_sve_int_pred_log(context *ctx, Instruction *dec); 176 | int decode_iclass_sve_int_brkp(context *ctx, Instruction *dec); 177 | int decode_iclass_sve_int_break(context *ctx, Instruction *dec); 178 | int decode_iclass_sve_int_brkn(context *ctx, Instruction *dec); 179 | int decode_iclass_sve_int_pfirst(context *ctx, Instruction *dec); 180 | int decode_iclass_sve_int_ptrue(context *ctx, Instruction *dec); 181 | int decode_iclass_sve_int_pnext(context *ctx, Instruction *dec); 182 | int decode_iclass_sve_int_rdffr(context *ctx, Instruction *dec); 183 | int decode_iclass_sve_int_rdffr_2(context *ctx, Instruction *dec); 184 | int decode_iclass_sve_int_ptest(context *ctx, Instruction *dec); 185 | int decode_iclass_sve_int_pfalse(context *ctx, Instruction *dec); 186 | int decode_iclass_sve_int_scmp_vi(context *ctx, Instruction *dec); 187 | int decode_iclass_sve_int_pcount_pred(context *ctx, Instruction *dec); 188 | int decode_iclass_sve_int_count_r(context *ctx, Instruction *dec); 189 | int decode_iclass_sve_int_count_v(context *ctx, Instruction *dec); 190 | int decode_iclass_sve_int_count_r_sat(context *ctx, Instruction *dec); 191 | int decode_iclass_sve_int_count_v_sat(context *ctx, Instruction *dec); 192 | int decode_iclass_sve_int_setffr(context *ctx, Instruction *dec); 193 | int decode_iclass_sve_int_wrffr(context *ctx, Instruction *dec); 194 | int decode_iclass_sve_int_cterm(context *ctx, Instruction *dec); 195 | int decode_iclass_sve_int_while_rr(context *ctx, Instruction *dec); 196 | int decode_iclass_sve_int_whilenc(context *ctx, Instruction *dec); 197 | int decode_iclass_sve_int_pred_dup(context *ctx, Instruction *dec); 198 | int decode_iclass_sve_int_dup_fpimm(context *ctx, Instruction *dec); 199 | int decode_iclass_sve_int_dup_imm(context *ctx, Instruction *dec); 200 | int decode_iclass_sve_int_arith_imm0(context *ctx, Instruction *dec); 201 | int decode_iclass_sve_int_arith_imm1(context *ctx, Instruction *dec); 202 | int decode_iclass_sve_int_arith_imm2(context *ctx, Instruction *dec); 203 | int decode_iclass_sve_intx_dot(context *ctx, Instruction *dec); 204 | int decode_iclass_sve_intx_mixed_dot(context *ctx, Instruction *dec); 205 | int decode_iclass_sve_intx_cdot(context *ctx, Instruction *dec); 206 | int decode_iclass_sve_intx_cmla(context *ctx, Instruction *dec); 207 | int decode_iclass_sve_intx_mlal_long(context *ctx, Instruction *dec); 208 | int decode_iclass_sve_intx_qdmlal_long(context *ctx, Instruction *dec); 209 | int decode_iclass_sve_intx_qrdmlah(context *ctx, Instruction *dec); 210 | int decode_iclass_sve_intx_qdmlalbt(context *ctx, Instruction *dec); 211 | int decode_iclass_sve_intx_pred_arith_binary(context *ctx, Instruction *dec); 212 | int decode_iclass_sve_intx_accumulate_long_pairs(context *ctx, Instruction *dec); 213 | int decode_iclass_sve_intx_arith_binary_pairs(context *ctx, Instruction *dec); 214 | int decode_iclass_sve_intx_pred_arith_unary(context *ctx, Instruction *dec); 215 | int decode_iclass_sve_intx_pred_arith_binary_sat(context *ctx, Instruction *dec); 216 | int decode_iclass_sve_intx_bin_pred_shift_sat_round(context *ctx, Instruction *dec); 217 | int decode_iclass_sve_intx_clamp(context *ctx, Instruction *dec); 218 | int decode_iclass_sve_intx_dot_by_indexed_elem(context *ctx, Instruction *dec); 219 | int decode_iclass_sve_intx_mixed_dot_by_indexed_elem(context *ctx, Instruction *dec); 220 | int decode_iclass_sve_intx_cdot_by_indexed_elem(context *ctx, Instruction *dec); 221 | int decode_iclass_sve_intx_cmla_by_indexed_elem(context *ctx, Instruction *dec); 222 | int decode_iclass_sve_intx_qrdcmla_by_indexed_elem(context *ctx, Instruction *dec); 223 | int decode_iclass_sve_intx_mul_by_indexed_elem(context *ctx, Instruction *dec); 224 | int decode_iclass_sve_intx_mul_long_by_indexed_elem(context *ctx, Instruction *dec); 225 | int decode_iclass_sve_intx_mla_by_indexed_elem(context *ctx, Instruction *dec); 226 | int decode_iclass_sve_intx_mla_long_by_indexed_elem(context *ctx, Instruction *dec); 227 | int decode_iclass_sve_intx_qdmulh_by_indexed_elem(context *ctx, Instruction *dec); 228 | int decode_iclass_sve_intx_qdmul_long_by_indexed_elem(context *ctx, Instruction *dec); 229 | int decode_iclass_sve_intx_qdmla_long_by_indexed_elem(context *ctx, Instruction *dec); 230 | int decode_iclass_sve_intx_qrdmlah_by_indexed_elem(context *ctx, Instruction *dec); 231 | int decode_iclass_sve_intx_cons_arith_long(context *ctx, Instruction *dec); 232 | int decode_iclass_sve_intx_cons_arith_wide(context *ctx, Instruction *dec); 233 | int decode_iclass_sve_intx_cons_mul_long(context *ctx, Instruction *dec); 234 | int decode_iclass_sve_intx_mmla(context *ctx, Instruction *dec); 235 | int decode_iclass_sve_intx_eorx(context *ctx, Instruction *dec); 236 | int decode_iclass_sve_intx_perm_bit(context *ctx, Instruction *dec); 237 | int decode_iclass_sve_intx_shift_long(context *ctx, Instruction *dec); 238 | int decode_iclass_sve_intx_clong(context *ctx, Instruction *dec); 239 | int decode_iclass_sve_intx_shift_insert(context *ctx, Instruction *dec); 240 | int decode_iclass_sve_intx_sra(context *ctx, Instruction *dec); 241 | int decode_iclass_sve_intx_cadd(context *ctx, Instruction *dec); 242 | int decode_iclass_sve_intx_aba(context *ctx, Instruction *dec); 243 | int decode_iclass_sve_intx_aba_long(context *ctx, Instruction *dec); 244 | int decode_iclass_sve_intx_adc_long(context *ctx, Instruction *dec); 245 | int decode_iclass_sve_intx_shift_narrow(context *ctx, Instruction *dec); 246 | int decode_iclass_sve_intx_arith_narrow(context *ctx, Instruction *dec); 247 | int decode_iclass_sve_intx_extract_narrow(context *ctx, Instruction *dec); 248 | int decode_iclass_sve_intx_match(context *ctx, Instruction *dec); 249 | int decode_iclass_sve_intx_histseg(context *ctx, Instruction *dec); 250 | int decode_iclass_sve_intx_histcnt(context *ctx, Instruction *dec); 251 | int decode_iclass_sve_crypto_binary_const(context *ctx, Instruction *dec); 252 | int decode_iclass_sve_crypto_binary_dest(context *ctx, Instruction *dec); 253 | int decode_iclass_sve_crypto_unary(context *ctx, Instruction *dec); 254 | int decode_iclass_sve_fp_fcadd(context *ctx, Instruction *dec); 255 | int decode_iclass_sve_fp_fcvt2(context *ctx, Instruction *dec); 256 | int decode_iclass_sve_fp_pairwise(context *ctx, Instruction *dec); 257 | int decode_iclass_sve_fp_fcmla(context *ctx, Instruction *dec); 258 | int decode_iclass_sve_fp_fma_by_indexed_elem(context *ctx, Instruction *dec); 259 | int decode_iclass_sve_fp_fcmla_by_indexed_elem(context *ctx, Instruction *dec); 260 | int decode_iclass_sve_fp_fmul_by_indexed_elem(context *ctx, Instruction *dec); 261 | int decode_iclass_sve_fp_fdot_by_indexed_elem(context *ctx, Instruction *dec); 262 | int decode_iclass_sve_fp_fma_long_by_indexed_elem(context *ctx, Instruction *dec); 263 | int decode_iclass_sve_fp_fdot(context *ctx, Instruction *dec); 264 | int decode_iclass_sve_fp_fma_long(context *ctx, Instruction *dec); 265 | int decode_iclass_sve_fp_fmmla(context *ctx, Instruction *dec); 266 | int decode_iclass_sve_fp_fast_red(context *ctx, Instruction *dec); 267 | int decode_iclass_sve_fp_2op_u_zd(context *ctx, Instruction *dec); 268 | int decode_iclass_sve_fp_2op_p_pd(context *ctx, Instruction *dec); 269 | int decode_iclass_sve_fp_2op_p_vd(context *ctx, Instruction *dec); 270 | int decode_iclass_sve_fp_3op_u_zd(context *ctx, Instruction *dec); 271 | int decode_iclass_sve_fp_2op_p_zds(context *ctx, Instruction *dec); 272 | int decode_iclass_sve_fp_2op_i_p_zds(context *ctx, Instruction *dec); 273 | int decode_iclass_sve_fp_ftmad(context *ctx, Instruction *dec); 274 | int decode_iclass_sve_fp_2op_p_zd_b_0(context *ctx, Instruction *dec); 275 | int decode_iclass_sve_fp_2op_p_zd_d(context *ctx, Instruction *dec); 276 | int decode_iclass_sve_fp_2op_p_zd_a(context *ctx, Instruction *dec); 277 | int decode_iclass_sve_fp_2op_p_zd_b_1(context *ctx, Instruction *dec); 278 | int decode_iclass_sve_fp_2op_p_zd_c(context *ctx, Instruction *dec); 279 | int decode_iclass_sve_fp_3op_p_pd(context *ctx, Instruction *dec); 280 | int decode_iclass_sve_fp_3op_p_zds_a(context *ctx, Instruction *dec); 281 | int decode_iclass_sve_fp_3op_p_zds_b(context *ctx, Instruction *dec); 282 | int decode_iclass_sve_mem_32b_gld_vs(context *ctx, Instruction *dec); 283 | int decode_iclass_sve_mem_32b_gld_vi(context *ctx, Instruction *dec); 284 | int decode_iclass_sve_mem_32b_gld_sv_a(context *ctx, Instruction *dec); 285 | int decode_iclass_sve_mem_32b_gld_sv_b(context *ctx, Instruction *dec); 286 | int decode_iclass_sve_mem_32b_prfm_sv(context *ctx, Instruction *dec); 287 | int decode_iclass_sve_mem_32b_prfm_vi(context *ctx, Instruction *dec); 288 | int decode_iclass_sve_mem_prfm_si(context *ctx, Instruction *dec); 289 | int decode_iclass_sve_mem_prfm_ss(context *ctx, Instruction *dec); 290 | int decode_iclass_sve_mem_ld_dup(context *ctx, Instruction *dec); 291 | int decode_iclass_sve_mem_32b_pfill(context *ctx, Instruction *dec); 292 | int decode_iclass_sve_mem_32b_fill(context *ctx, Instruction *dec); 293 | int decode_iclass_sve_mem_32b_gldnt_vs(context *ctx, Instruction *dec); 294 | int decode_iclass_sve_mem_cldff_ss(context *ctx, Instruction *dec); 295 | int decode_iclass_sve_mem_cld_si(context *ctx, Instruction *dec); 296 | int decode_iclass_sve_mem_cld_ss(context *ctx, Instruction *dec); 297 | int decode_iclass_sve_mem_cldnf_si(context *ctx, Instruction *dec); 298 | int decode_iclass_sve_mem_cldnt_si(context *ctx, Instruction *dec); 299 | int decode_iclass_sve_mem_cldnt_ss(context *ctx, Instruction *dec); 300 | int decode_iclass_sve_mem_ldqr_si(context *ctx, Instruction *dec); 301 | int decode_iclass_sve_mem_ldqr_ss(context *ctx, Instruction *dec); 302 | int decode_iclass_sve_mem_eld_si(context *ctx, Instruction *dec); 303 | int decode_iclass_sve_mem_eld_ss(context *ctx, Instruction *dec); 304 | int decode_iclass_sve_mem_64b_gld_sv(context *ctx, Instruction *dec); 305 | int decode_iclass_sve_mem_64b_gld_sv2(context *ctx, Instruction *dec); 306 | int decode_iclass_sve_mem_64b_gld_vs2(context *ctx, Instruction *dec); 307 | int decode_iclass_sve_mem_64b_gld_vs(context *ctx, Instruction *dec); 308 | int decode_iclass_sve_mem_64b_gld_vi(context *ctx, Instruction *dec); 309 | int decode_iclass_sve_mem_64b_prfm_sv2(context *ctx, Instruction *dec); 310 | int decode_iclass_sve_mem_64b_prfm_sv(context *ctx, Instruction *dec); 311 | int decode_iclass_sve_mem_64b_prfm_vi(context *ctx, Instruction *dec); 312 | int decode_iclass_sve_mem_64b_gldnt_vs(context *ctx, Instruction *dec); 313 | int decode_iclass_sve_mem_cst_ss(context *ctx, Instruction *dec); 314 | int decode_iclass_sve_mem_pspill(context *ctx, Instruction *dec); 315 | int decode_iclass_sve_mem_spill(context *ctx, Instruction *dec); 316 | int decode_iclass_sve_mem_cstnt_ss(context *ctx, Instruction *dec); 317 | int decode_iclass_sve_mem_est_ss(context *ctx, Instruction *dec); 318 | int decode_iclass_sve_mem_sstnt_32b_vs(context *ctx, Instruction *dec); 319 | int decode_iclass_sve_mem_sstnt_64b_vs(context *ctx, Instruction *dec); 320 | int decode_iclass_sve_mem_sst_vi_b(context *ctx, Instruction *dec); 321 | int decode_iclass_sve_mem_sst_sv2(context *ctx, Instruction *dec); 322 | int decode_iclass_sve_mem_sst_vs2(context *ctx, Instruction *dec); 323 | int decode_iclass_sve_mem_sst_vi_a(context *ctx, Instruction *dec); 324 | int decode_iclass_sve_mem_cstnt_si(context *ctx, Instruction *dec); 325 | int decode_iclass_sve_mem_cst_si(context *ctx, Instruction *dec); 326 | int decode_iclass_sve_mem_est_si(context *ctx, Instruction *dec); 327 | int decode_iclass_sve_mem_sst_sv_b(context *ctx, Instruction *dec); 328 | int decode_iclass_sve_mem_sst_vs_b(context *ctx, Instruction *dec); 329 | int decode_iclass_sve_mem_sst_sv_a(context *ctx, Instruction *dec); 330 | int decode_iclass_sve_mem_sst_vs_a(context *ctx, Instruction *dec); 331 | int decode_iclass_mortlach_b16f32_prod(context *ctx, Instruction *dec); 332 | int decode_iclass_mortlach_f16f32_prod(context *ctx, Instruction *dec); 333 | int decode_iclass_mortlach_f32f32_prod(context *ctx, Instruction *dec); 334 | int decode_iclass_mortlach_i8i32_prod(context *ctx, Instruction *dec); 335 | int decode_iclass_mortlach_f64f64_prod(context *ctx, Instruction *dec); 336 | int decode_iclass_mortlach_i16i64_prod(context *ctx, Instruction *dec); 337 | int decode_iclass_mortlach_insert_pred(context *ctx, Instruction *dec); 338 | int decode_iclass_mortlach_extract_pred(context *ctx, Instruction *dec); 339 | int decode_iclass_mortlach_zero(context *ctx, Instruction *dec); 340 | int decode_iclass_mortlach_addhv(context *ctx, Instruction *dec); 341 | int decode_iclass_mortlach_contig_load(context *ctx, Instruction *dec); 342 | int decode_iclass_mortlach_contig_qload(context *ctx, Instruction *dec); 343 | int decode_iclass_mortlach_ctxt_ldst(context *ctx, Instruction *dec); 344 | int decode_iclass_mortlach_contig_store(context *ctx, Instruction *dec); 345 | int decode_iclass_mortlach_contig_qstore(context *ctx, Instruction *dec); 346 | -------------------------------------------------------------------------------- /disassembler/regs.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | #include 4 | 5 | #undef REG_NONE // collides with winnt's define 6 | 7 | // On RISC-V musl defines REG_SP/REG_S0 in signal.h. 8 | // Similarily, glibc defines REG_SP/REG_S0 in sys/ucontext.h. 9 | #undef REG_SP 10 | #undef REG_S0 11 | #undef REG_S1 12 | #undef REG_S2 13 | #undef REG_S3 14 | #undef REG_S4 15 | #undef REG_S5 16 | #undef REG_S6 17 | 18 | //----------------------------------------------------------------------------- 19 | // registers (non-system) 20 | //----------------------------------------------------------------------------- 21 | 22 | enum Register 23 | { 24 | REG_NONE, 25 | REG_W0, 26 | REG_W1, 27 | REG_W2, 28 | REG_W3, 29 | REG_W4, 30 | REG_W5, 31 | REG_W6, 32 | REG_W7, 33 | REG_W8, 34 | REG_W9, 35 | REG_W10, 36 | REG_W11, 37 | REG_W12, 38 | REG_W13, 39 | REG_W14, 40 | REG_W15, 41 | REG_W16, 42 | REG_W17, 43 | REG_W18, 44 | REG_W19, 45 | REG_W20, 46 | REG_W21, 47 | REG_W22, 48 | REG_W23, 49 | REG_W24, 50 | REG_W25, 51 | REG_W26, 52 | REG_W27, 53 | REG_W28, 54 | REG_W29, 55 | REG_W30, 56 | REG_WZR, 57 | REG_WSP, 58 | REG_X0, 59 | REG_X1, 60 | REG_X2, 61 | REG_X3, 62 | REG_X4, 63 | REG_X5, 64 | REG_X6, 65 | REG_X7, 66 | REG_X8, 67 | REG_X9, 68 | REG_X10, 69 | REG_X11, 70 | REG_X12, 71 | REG_X13, 72 | REG_X14, 73 | REG_X15, 74 | REG_X16, 75 | REG_X17, 76 | REG_X18, 77 | REG_X19, 78 | REG_X20, 79 | REG_X21, 80 | REG_X22, 81 | REG_X23, 82 | REG_X24, 83 | REG_X25, 84 | REG_X26, 85 | REG_X27, 86 | REG_X28, 87 | REG_X29, 88 | REG_X30, 89 | REG_XZR, 90 | REG_SP, 91 | REG_V0, 92 | REG_V1, 93 | REG_V2, 94 | REG_V3, 95 | REG_V4, 96 | REG_V5, 97 | REG_V6, 98 | REG_V7, 99 | REG_V8, 100 | REG_V9, 101 | REG_V10, 102 | REG_V11, 103 | REG_V12, 104 | REG_V13, 105 | REG_V14, 106 | REG_V15, 107 | REG_V16, 108 | REG_V17, 109 | REG_V18, 110 | REG_V19, 111 | REG_V20, 112 | REG_V21, 113 | REG_V22, 114 | REG_V23, 115 | REG_V24, 116 | REG_V25, 117 | REG_V26, 118 | REG_V27, 119 | REG_V28, 120 | REG_V29, 121 | REG_V30, 122 | REG_V31, 123 | REG_B0, 124 | REG_B1, 125 | REG_B2, 126 | REG_B3, 127 | REG_B4, 128 | REG_B5, 129 | REG_B6, 130 | REG_B7, 131 | REG_B8, 132 | REG_B9, 133 | REG_B10, 134 | REG_B11, 135 | REG_B12, 136 | REG_B13, 137 | REG_B14, 138 | REG_B15, 139 | REG_B16, 140 | REG_B17, 141 | REG_B18, 142 | REG_B19, 143 | REG_B20, 144 | REG_B21, 145 | REG_B22, 146 | REG_B23, 147 | REG_B24, 148 | REG_B25, 149 | REG_B26, 150 | REG_B27, 151 | REG_B28, 152 | REG_B29, 153 | REG_B30, 154 | REG_B31, 155 | REG_H0, 156 | REG_H1, 157 | REG_H2, 158 | REG_H3, 159 | REG_H4, 160 | REG_H5, 161 | REG_H6, 162 | REG_H7, 163 | REG_H8, 164 | REG_H9, 165 | REG_H10, 166 | REG_H11, 167 | REG_H12, 168 | REG_H13, 169 | REG_H14, 170 | REG_H15, 171 | REG_H16, 172 | REG_H17, 173 | REG_H18, 174 | REG_H19, 175 | REG_H20, 176 | REG_H21, 177 | REG_H22, 178 | REG_H23, 179 | REG_H24, 180 | REG_H25, 181 | REG_H26, 182 | REG_H27, 183 | REG_H28, 184 | REG_H29, 185 | REG_H30, 186 | REG_H31, 187 | REG_S0, 188 | REG_S1, 189 | REG_S2, 190 | REG_S3, 191 | REG_S4, 192 | REG_S5, 193 | REG_S6, 194 | REG_S7, 195 | REG_S8, 196 | REG_S9, 197 | REG_S10, 198 | REG_S11, 199 | REG_S12, 200 | REG_S13, 201 | REG_S14, 202 | REG_S15, 203 | REG_S16, 204 | REG_S17, 205 | REG_S18, 206 | REG_S19, 207 | REG_S20, 208 | REG_S21, 209 | REG_S22, 210 | REG_S23, 211 | REG_S24, 212 | REG_S25, 213 | REG_S26, 214 | REG_S27, 215 | REG_S28, 216 | REG_S29, 217 | REG_S30, 218 | REG_S31, 219 | REG_D0, 220 | REG_D1, 221 | REG_D2, 222 | REG_D3, 223 | REG_D4, 224 | REG_D5, 225 | REG_D6, 226 | REG_D7, 227 | REG_D8, 228 | REG_D9, 229 | REG_D10, 230 | REG_D11, 231 | REG_D12, 232 | REG_D13, 233 | REG_D14, 234 | REG_D15, 235 | REG_D16, 236 | REG_D17, 237 | REG_D18, 238 | REG_D19, 239 | REG_D20, 240 | REG_D21, 241 | REG_D22, 242 | REG_D23, 243 | REG_D24, 244 | REG_D25, 245 | REG_D26, 246 | REG_D27, 247 | REG_D28, 248 | REG_D29, 249 | REG_D30, 250 | REG_D31, 251 | REG_Q0, 252 | REG_Q1, 253 | REG_Q2, 254 | REG_Q3, 255 | REG_Q4, 256 | REG_Q5, 257 | REG_Q6, 258 | REG_Q7, 259 | REG_Q8, 260 | REG_Q9, 261 | REG_Q10, 262 | REG_Q11, 263 | REG_Q12, 264 | REG_Q13, 265 | REG_Q14, 266 | REG_Q15, 267 | REG_Q16, 268 | REG_Q17, 269 | REG_Q18, 270 | REG_Q19, 271 | REG_Q20, 272 | REG_Q21, 273 | REG_Q22, 274 | REG_Q23, 275 | REG_Q24, 276 | REG_Q25, 277 | REG_Q26, 278 | REG_Q27, 279 | REG_Q28, 280 | REG_Q29, 281 | REG_Q30, 282 | REG_Q31, 283 | // B vector 284 | REG_V0_B0, 285 | REG_V0_B1, 286 | REG_V0_B2, 287 | REG_V0_B3, 288 | REG_V0_B4, 289 | REG_V0_B5, 290 | REG_V0_B6, 291 | REG_V0_B7, 292 | REG_V0_B8, 293 | REG_V0_B9, 294 | REG_V0_B10, 295 | REG_V0_B11, 296 | REG_V0_B12, 297 | REG_V0_B13, 298 | REG_V0_B14, 299 | REG_V0_B15, 300 | REG_V1_B0, 301 | REG_V1_B1, 302 | REG_V1_B2, 303 | REG_V1_B3, 304 | REG_V1_B4, 305 | REG_V1_B5, 306 | REG_V1_B6, 307 | REG_V1_B7, 308 | REG_V1_B8, 309 | REG_V1_B9, 310 | REG_V1_B10, 311 | REG_V1_B11, 312 | REG_V1_B12, 313 | REG_V1_B13, 314 | REG_V1_B14, 315 | REG_V1_B15, 316 | REG_V2_B0, 317 | REG_V2_B1, 318 | REG_V2_B2, 319 | REG_V2_B3, 320 | REG_V2_B4, 321 | REG_V2_B5, 322 | REG_V2_B6, 323 | REG_V2_B7, 324 | REG_V2_B8, 325 | REG_V2_B9, 326 | REG_V2_B10, 327 | REG_V2_B11, 328 | REG_V2_B12, 329 | REG_V2_B13, 330 | REG_V2_B14, 331 | REG_V2_B15, 332 | REG_V3_B0, 333 | REG_V3_B1, 334 | REG_V3_B2, 335 | REG_V3_B3, 336 | REG_V3_B4, 337 | REG_V3_B5, 338 | REG_V3_B6, 339 | REG_V3_B7, 340 | REG_V3_B8, 341 | REG_V3_B9, 342 | REG_V3_B10, 343 | REG_V3_B11, 344 | REG_V3_B12, 345 | REG_V3_B13, 346 | REG_V3_B14, 347 | REG_V3_B15, 348 | REG_V4_B0, 349 | REG_V4_B1, 350 | REG_V4_B2, 351 | REG_V4_B3, 352 | REG_V4_B4, 353 | REG_V4_B5, 354 | REG_V4_B6, 355 | REG_V4_B7, 356 | REG_V4_B8, 357 | REG_V4_B9, 358 | REG_V4_B10, 359 | REG_V4_B11, 360 | REG_V4_B12, 361 | REG_V4_B13, 362 | REG_V4_B14, 363 | REG_V4_B15, 364 | REG_V5_B0, 365 | REG_V5_B1, 366 | REG_V5_B2, 367 | REG_V5_B3, 368 | REG_V5_B4, 369 | REG_V5_B5, 370 | REG_V5_B6, 371 | REG_V5_B7, 372 | REG_V5_B8, 373 | REG_V5_B9, 374 | REG_V5_B10, 375 | REG_V5_B11, 376 | REG_V5_B12, 377 | REG_V5_B13, 378 | REG_V5_B14, 379 | REG_V5_B15, 380 | REG_V6_B0, 381 | REG_V6_B1, 382 | REG_V6_B2, 383 | REG_V6_B3, 384 | REG_V6_B4, 385 | REG_V6_B5, 386 | REG_V6_B6, 387 | REG_V6_B7, 388 | REG_V6_B8, 389 | REG_V6_B9, 390 | REG_V6_B10, 391 | REG_V6_B11, 392 | REG_V6_B12, 393 | REG_V6_B13, 394 | REG_V6_B14, 395 | REG_V6_B15, 396 | REG_V7_B0, 397 | REG_V7_B1, 398 | REG_V7_B2, 399 | REG_V7_B3, 400 | REG_V7_B4, 401 | REG_V7_B5, 402 | REG_V7_B6, 403 | REG_V7_B7, 404 | REG_V7_B8, 405 | REG_V7_B9, 406 | REG_V7_B10, 407 | REG_V7_B11, 408 | REG_V7_B12, 409 | REG_V7_B13, 410 | REG_V7_B14, 411 | REG_V7_B15, 412 | REG_V8_B0, 413 | REG_V8_B1, 414 | REG_V8_B2, 415 | REG_V8_B3, 416 | REG_V8_B4, 417 | REG_V8_B5, 418 | REG_V8_B6, 419 | REG_V8_B7, 420 | REG_V8_B8, 421 | REG_V8_B9, 422 | REG_V8_B10, 423 | REG_V8_B11, 424 | REG_V8_B12, 425 | REG_V8_B13, 426 | REG_V8_B14, 427 | REG_V8_B15, 428 | REG_V9_B0, 429 | REG_V9_B1, 430 | REG_V9_B2, 431 | REG_V9_B3, 432 | REG_V9_B4, 433 | REG_V9_B5, 434 | REG_V9_B6, 435 | REG_V9_B7, 436 | REG_V9_B8, 437 | REG_V9_B9, 438 | REG_V9_B10, 439 | REG_V9_B11, 440 | REG_V9_B12, 441 | REG_V9_B13, 442 | REG_V9_B14, 443 | REG_V9_B15, 444 | REG_V10_B0, 445 | REG_V10_B1, 446 | REG_V10_B2, 447 | REG_V10_B3, 448 | REG_V10_B4, 449 | REG_V10_B5, 450 | REG_V10_B6, 451 | REG_V10_B7, 452 | REG_V10_B8, 453 | REG_V10_B9, 454 | REG_V10_B10, 455 | REG_V10_B11, 456 | REG_V10_B12, 457 | REG_V10_B13, 458 | REG_V10_B14, 459 | REG_V10_B15, 460 | REG_V11_B0, 461 | REG_V11_B1, 462 | REG_V11_B2, 463 | REG_V11_B3, 464 | REG_V11_B4, 465 | REG_V11_B5, 466 | REG_V11_B6, 467 | REG_V11_B7, 468 | REG_V11_B8, 469 | REG_V11_B9, 470 | REG_V11_B10, 471 | REG_V11_B11, 472 | REG_V11_B12, 473 | REG_V11_B13, 474 | REG_V11_B14, 475 | REG_V11_B15, 476 | REG_V12_B0, 477 | REG_V12_B1, 478 | REG_V12_B2, 479 | REG_V12_B3, 480 | REG_V12_B4, 481 | REG_V12_B5, 482 | REG_V12_B6, 483 | REG_V12_B7, 484 | REG_V12_B8, 485 | REG_V12_B9, 486 | REG_V12_B10, 487 | REG_V12_B11, 488 | REG_V12_B12, 489 | REG_V12_B13, 490 | REG_V12_B14, 491 | REG_V12_B15, 492 | REG_V13_B0, 493 | REG_V13_B1, 494 | REG_V13_B2, 495 | REG_V13_B3, 496 | REG_V13_B4, 497 | REG_V13_B5, 498 | REG_V13_B6, 499 | REG_V13_B7, 500 | REG_V13_B8, 501 | REG_V13_B9, 502 | REG_V13_B10, 503 | REG_V13_B11, 504 | REG_V13_B12, 505 | REG_V13_B13, 506 | REG_V13_B14, 507 | REG_V13_B15, 508 | REG_V14_B0, 509 | REG_V14_B1, 510 | REG_V14_B2, 511 | REG_V14_B3, 512 | REG_V14_B4, 513 | REG_V14_B5, 514 | REG_V14_B6, 515 | REG_V14_B7, 516 | REG_V14_B8, 517 | REG_V14_B9, 518 | REG_V14_B10, 519 | REG_V14_B11, 520 | REG_V14_B12, 521 | REG_V14_B13, 522 | REG_V14_B14, 523 | REG_V14_B15, 524 | REG_V15_B0, 525 | REG_V15_B1, 526 | REG_V15_B2, 527 | REG_V15_B3, 528 | REG_V15_B4, 529 | REG_V15_B5, 530 | REG_V15_B6, 531 | REG_V15_B7, 532 | REG_V15_B8, 533 | REG_V15_B9, 534 | REG_V15_B10, 535 | REG_V15_B11, 536 | REG_V15_B12, 537 | REG_V15_B13, 538 | REG_V15_B14, 539 | REG_V15_B15, 540 | REG_V16_B0, 541 | REG_V16_B1, 542 | REG_V16_B2, 543 | REG_V16_B3, 544 | REG_V16_B4, 545 | REG_V16_B5, 546 | REG_V16_B6, 547 | REG_V16_B7, 548 | REG_V16_B8, 549 | REG_V16_B9, 550 | REG_V16_B10, 551 | REG_V16_B11, 552 | REG_V16_B12, 553 | REG_V16_B13, 554 | REG_V16_B14, 555 | REG_V16_B15, 556 | REG_V17_B0, 557 | REG_V17_B1, 558 | REG_V17_B2, 559 | REG_V17_B3, 560 | REG_V17_B4, 561 | REG_V17_B5, 562 | REG_V17_B6, 563 | REG_V17_B7, 564 | REG_V17_B8, 565 | REG_V17_B9, 566 | REG_V17_B10, 567 | REG_V17_B11, 568 | REG_V17_B12, 569 | REG_V17_B13, 570 | REG_V17_B14, 571 | REG_V17_B15, 572 | REG_V18_B0, 573 | REG_V18_B1, 574 | REG_V18_B2, 575 | REG_V18_B3, 576 | REG_V18_B4, 577 | REG_V18_B5, 578 | REG_V18_B6, 579 | REG_V18_B7, 580 | REG_V18_B8, 581 | REG_V18_B9, 582 | REG_V18_B10, 583 | REG_V18_B11, 584 | REG_V18_B12, 585 | REG_V18_B13, 586 | REG_V18_B14, 587 | REG_V18_B15, 588 | REG_V19_B0, 589 | REG_V19_B1, 590 | REG_V19_B2, 591 | REG_V19_B3, 592 | REG_V19_B4, 593 | REG_V19_B5, 594 | REG_V19_B6, 595 | REG_V19_B7, 596 | REG_V19_B8, 597 | REG_V19_B9, 598 | REG_V19_B10, 599 | REG_V19_B11, 600 | REG_V19_B12, 601 | REG_V19_B13, 602 | REG_V19_B14, 603 | REG_V19_B15, 604 | REG_V20_B0, 605 | REG_V20_B1, 606 | REG_V20_B2, 607 | REG_V20_B3, 608 | REG_V20_B4, 609 | REG_V20_B5, 610 | REG_V20_B6, 611 | REG_V20_B7, 612 | REG_V20_B8, 613 | REG_V20_B9, 614 | REG_V20_B10, 615 | REG_V20_B11, 616 | REG_V20_B12, 617 | REG_V20_B13, 618 | REG_V20_B14, 619 | REG_V20_B15, 620 | REG_V21_B0, 621 | REG_V21_B1, 622 | REG_V21_B2, 623 | REG_V21_B3, 624 | REG_V21_B4, 625 | REG_V21_B5, 626 | REG_V21_B6, 627 | REG_V21_B7, 628 | REG_V21_B8, 629 | REG_V21_B9, 630 | REG_V21_B10, 631 | REG_V21_B11, 632 | REG_V21_B12, 633 | REG_V21_B13, 634 | REG_V21_B14, 635 | REG_V21_B15, 636 | REG_V22_B0, 637 | REG_V22_B1, 638 | REG_V22_B2, 639 | REG_V22_B3, 640 | REG_V22_B4, 641 | REG_V22_B5, 642 | REG_V22_B6, 643 | REG_V22_B7, 644 | REG_V22_B8, 645 | REG_V22_B9, 646 | REG_V22_B10, 647 | REG_V22_B11, 648 | REG_V22_B12, 649 | REG_V22_B13, 650 | REG_V22_B14, 651 | REG_V22_B15, 652 | REG_V23_B0, 653 | REG_V23_B1, 654 | REG_V23_B2, 655 | REG_V23_B3, 656 | REG_V23_B4, 657 | REG_V23_B5, 658 | REG_V23_B6, 659 | REG_V23_B7, 660 | REG_V23_B8, 661 | REG_V23_B9, 662 | REG_V23_B10, 663 | REG_V23_B11, 664 | REG_V23_B12, 665 | REG_V23_B13, 666 | REG_V23_B14, 667 | REG_V23_B15, 668 | REG_V24_B0, 669 | REG_V24_B1, 670 | REG_V24_B2, 671 | REG_V24_B3, 672 | REG_V24_B4, 673 | REG_V24_B5, 674 | REG_V24_B6, 675 | REG_V24_B7, 676 | REG_V24_B8, 677 | REG_V24_B9, 678 | REG_V24_B10, 679 | REG_V24_B11, 680 | REG_V24_B12, 681 | REG_V24_B13, 682 | REG_V24_B14, 683 | REG_V24_B15, 684 | REG_V25_B0, 685 | REG_V25_B1, 686 | REG_V25_B2, 687 | REG_V25_B3, 688 | REG_V25_B4, 689 | REG_V25_B5, 690 | REG_V25_B6, 691 | REG_V25_B7, 692 | REG_V25_B8, 693 | REG_V25_B9, 694 | REG_V25_B10, 695 | REG_V25_B11, 696 | REG_V25_B12, 697 | REG_V25_B13, 698 | REG_V25_B14, 699 | REG_V25_B15, 700 | REG_V26_B0, 701 | REG_V26_B1, 702 | REG_V26_B2, 703 | REG_V26_B3, 704 | REG_V26_B4, 705 | REG_V26_B5, 706 | REG_V26_B6, 707 | REG_V26_B7, 708 | REG_V26_B8, 709 | REG_V26_B9, 710 | REG_V26_B10, 711 | REG_V26_B11, 712 | REG_V26_B12, 713 | REG_V26_B13, 714 | REG_V26_B14, 715 | REG_V26_B15, 716 | REG_V27_B0, 717 | REG_V27_B1, 718 | REG_V27_B2, 719 | REG_V27_B3, 720 | REG_V27_B4, 721 | REG_V27_B5, 722 | REG_V27_B6, 723 | REG_V27_B7, 724 | REG_V27_B8, 725 | REG_V27_B9, 726 | REG_V27_B10, 727 | REG_V27_B11, 728 | REG_V27_B12, 729 | REG_V27_B13, 730 | REG_V27_B14, 731 | REG_V27_B15, 732 | REG_V28_B0, 733 | REG_V28_B1, 734 | REG_V28_B2, 735 | REG_V28_B3, 736 | REG_V28_B4, 737 | REG_V28_B5, 738 | REG_V28_B6, 739 | REG_V28_B7, 740 | REG_V28_B8, 741 | REG_V28_B9, 742 | REG_V28_B10, 743 | REG_V28_B11, 744 | REG_V28_B12, 745 | REG_V28_B13, 746 | REG_V28_B14, 747 | REG_V28_B15, 748 | REG_V29_B0, 749 | REG_V29_B1, 750 | REG_V29_B2, 751 | REG_V29_B3, 752 | REG_V29_B4, 753 | REG_V29_B5, 754 | REG_V29_B6, 755 | REG_V29_B7, 756 | REG_V29_B8, 757 | REG_V29_B9, 758 | REG_V29_B10, 759 | REG_V29_B11, 760 | REG_V29_B12, 761 | REG_V29_B13, 762 | REG_V29_B14, 763 | REG_V29_B15, 764 | REG_V30_B0, 765 | REG_V30_B1, 766 | REG_V30_B2, 767 | REG_V30_B3, 768 | REG_V30_B4, 769 | REG_V30_B5, 770 | REG_V30_B6, 771 | REG_V30_B7, 772 | REG_V30_B8, 773 | REG_V30_B9, 774 | REG_V30_B10, 775 | REG_V30_B11, 776 | REG_V30_B12, 777 | REG_V30_B13, 778 | REG_V30_B14, 779 | REG_V30_B15, 780 | REG_V31_B0, 781 | REG_V31_B1, 782 | REG_V31_B2, 783 | REG_V31_B3, 784 | REG_V31_B4, 785 | REG_V31_B5, 786 | REG_V31_B6, 787 | REG_V31_B7, 788 | REG_V31_B8, 789 | REG_V31_B9, 790 | REG_V31_B10, 791 | REG_V31_B11, 792 | REG_V31_B12, 793 | REG_V31_B13, 794 | REG_V31_B14, 795 | REG_V31_B15, 796 | // H vector 797 | REG_V0_H0, 798 | REG_V0_H1, 799 | REG_V0_H2, 800 | REG_V0_H3, 801 | REG_V0_H4, 802 | REG_V0_H5, 803 | REG_V0_H6, 804 | REG_V0_H7, 805 | REG_V1_H0, 806 | REG_V1_H1, 807 | REG_V1_H2, 808 | REG_V1_H3, 809 | REG_V1_H4, 810 | REG_V1_H5, 811 | REG_V1_H6, 812 | REG_V1_H7, 813 | REG_V2_H0, 814 | REG_V2_H1, 815 | REG_V2_H2, 816 | REG_V2_H3, 817 | REG_V2_H4, 818 | REG_V2_H5, 819 | REG_V2_H6, 820 | REG_V2_H7, 821 | REG_V3_H0, 822 | REG_V3_H1, 823 | REG_V3_H2, 824 | REG_V3_H3, 825 | REG_V3_H4, 826 | REG_V3_H5, 827 | REG_V3_H6, 828 | REG_V3_H7, 829 | REG_V4_H0, 830 | REG_V4_H1, 831 | REG_V4_H2, 832 | REG_V4_H3, 833 | REG_V4_H4, 834 | REG_V4_H5, 835 | REG_V4_H6, 836 | REG_V4_H7, 837 | REG_V5_H0, 838 | REG_V5_H1, 839 | REG_V5_H2, 840 | REG_V5_H3, 841 | REG_V5_H4, 842 | REG_V5_H5, 843 | REG_V5_H6, 844 | REG_V5_H7, 845 | REG_V6_H0, 846 | REG_V6_H1, 847 | REG_V6_H2, 848 | REG_V6_H3, 849 | REG_V6_H4, 850 | REG_V6_H5, 851 | REG_V6_H6, 852 | REG_V6_H7, 853 | REG_V7_H0, 854 | REG_V7_H1, 855 | REG_V7_H2, 856 | REG_V7_H3, 857 | REG_V7_H4, 858 | REG_V7_H5, 859 | REG_V7_H6, 860 | REG_V7_H7, 861 | REG_V8_H0, 862 | REG_V8_H1, 863 | REG_V8_H2, 864 | REG_V8_H3, 865 | REG_V8_H4, 866 | REG_V8_H5, 867 | REG_V8_H6, 868 | REG_V8_H7, 869 | REG_V9_H0, 870 | REG_V9_H1, 871 | REG_V9_H2, 872 | REG_V9_H3, 873 | REG_V9_H4, 874 | REG_V9_H5, 875 | REG_V9_H6, 876 | REG_V9_H7, 877 | REG_V10_H0, 878 | REG_V10_H1, 879 | REG_V10_H2, 880 | REG_V10_H3, 881 | REG_V10_H4, 882 | REG_V10_H5, 883 | REG_V10_H6, 884 | REG_V10_H7, 885 | REG_V11_H0, 886 | REG_V11_H1, 887 | REG_V11_H2, 888 | REG_V11_H3, 889 | REG_V11_H4, 890 | REG_V11_H5, 891 | REG_V11_H6, 892 | REG_V11_H7, 893 | REG_V12_H0, 894 | REG_V12_H1, 895 | REG_V12_H2, 896 | REG_V12_H3, 897 | REG_V12_H4, 898 | REG_V12_H5, 899 | REG_V12_H6, 900 | REG_V12_H7, 901 | REG_V13_H0, 902 | REG_V13_H1, 903 | REG_V13_H2, 904 | REG_V13_H3, 905 | REG_V13_H4, 906 | REG_V13_H5, 907 | REG_V13_H6, 908 | REG_V13_H7, 909 | REG_V14_H0, 910 | REG_V14_H1, 911 | REG_V14_H2, 912 | REG_V14_H3, 913 | REG_V14_H4, 914 | REG_V14_H5, 915 | REG_V14_H6, 916 | REG_V14_H7, 917 | REG_V15_H0, 918 | REG_V15_H1, 919 | REG_V15_H2, 920 | REG_V15_H3, 921 | REG_V15_H4, 922 | REG_V15_H5, 923 | REG_V15_H6, 924 | REG_V15_H7, 925 | REG_V16_H0, 926 | REG_V16_H1, 927 | REG_V16_H2, 928 | REG_V16_H3, 929 | REG_V16_H4, 930 | REG_V16_H5, 931 | REG_V16_H6, 932 | REG_V16_H7, 933 | REG_V17_H0, 934 | REG_V17_H1, 935 | REG_V17_H2, 936 | REG_V17_H3, 937 | REG_V17_H4, 938 | REG_V17_H5, 939 | REG_V17_H6, 940 | REG_V17_H7, 941 | REG_V18_H0, 942 | REG_V18_H1, 943 | REG_V18_H2, 944 | REG_V18_H3, 945 | REG_V18_H4, 946 | REG_V18_H5, 947 | REG_V18_H6, 948 | REG_V18_H7, 949 | REG_V19_H0, 950 | REG_V19_H1, 951 | REG_V19_H2, 952 | REG_V19_H3, 953 | REG_V19_H4, 954 | REG_V19_H5, 955 | REG_V19_H6, 956 | REG_V19_H7, 957 | REG_V20_H0, 958 | REG_V20_H1, 959 | REG_V20_H2, 960 | REG_V20_H3, 961 | REG_V20_H4, 962 | REG_V20_H5, 963 | REG_V20_H6, 964 | REG_V20_H7, 965 | REG_V21_H0, 966 | REG_V21_H1, 967 | REG_V21_H2, 968 | REG_V21_H3, 969 | REG_V21_H4, 970 | REG_V21_H5, 971 | REG_V21_H6, 972 | REG_V21_H7, 973 | REG_V22_H0, 974 | REG_V22_H1, 975 | REG_V22_H2, 976 | REG_V22_H3, 977 | REG_V22_H4, 978 | REG_V22_H5, 979 | REG_V22_H6, 980 | REG_V22_H7, 981 | REG_V23_H0, 982 | REG_V23_H1, 983 | REG_V23_H2, 984 | REG_V23_H3, 985 | REG_V23_H4, 986 | REG_V23_H5, 987 | REG_V23_H6, 988 | REG_V23_H7, 989 | REG_V24_H0, 990 | REG_V24_H1, 991 | REG_V24_H2, 992 | REG_V24_H3, 993 | REG_V24_H4, 994 | REG_V24_H5, 995 | REG_V24_H6, 996 | REG_V24_H7, 997 | REG_V25_H0, 998 | REG_V25_H1, 999 | REG_V25_H2, 1000 | REG_V25_H3, 1001 | REG_V25_H4, 1002 | REG_V25_H5, 1003 | REG_V25_H6, 1004 | REG_V25_H7, 1005 | REG_V26_H0, 1006 | REG_V26_H1, 1007 | REG_V26_H2, 1008 | REG_V26_H3, 1009 | REG_V26_H4, 1010 | REG_V26_H5, 1011 | REG_V26_H6, 1012 | REG_V26_H7, 1013 | REG_V27_H0, 1014 | REG_V27_H1, 1015 | REG_V27_H2, 1016 | REG_V27_H3, 1017 | REG_V27_H4, 1018 | REG_V27_H5, 1019 | REG_V27_H6, 1020 | REG_V27_H7, 1021 | REG_V28_H0, 1022 | REG_V28_H1, 1023 | REG_V28_H2, 1024 | REG_V28_H3, 1025 | REG_V28_H4, 1026 | REG_V28_H5, 1027 | REG_V28_H6, 1028 | REG_V28_H7, 1029 | REG_V29_H0, 1030 | REG_V29_H1, 1031 | REG_V29_H2, 1032 | REG_V29_H3, 1033 | REG_V29_H4, 1034 | REG_V29_H5, 1035 | REG_V29_H6, 1036 | REG_V29_H7, 1037 | REG_V30_H0, 1038 | REG_V30_H1, 1039 | REG_V30_H2, 1040 | REG_V30_H3, 1041 | REG_V30_H4, 1042 | REG_V30_H5, 1043 | REG_V30_H6, 1044 | REG_V30_H7, 1045 | REG_V31_H0, 1046 | REG_V31_H1, 1047 | REG_V31_H2, 1048 | REG_V31_H3, 1049 | REG_V31_H4, 1050 | REG_V31_H5, 1051 | REG_V31_H6, 1052 | REG_V31_H7, 1053 | // S vector 1054 | REG_V0_S0, 1055 | REG_V0_S1, 1056 | REG_V0_S2, 1057 | REG_V0_S3, 1058 | REG_V1_S0, 1059 | REG_V1_S1, 1060 | REG_V1_S2, 1061 | REG_V1_S3, 1062 | REG_V2_S0, 1063 | REG_V2_S1, 1064 | REG_V2_S2, 1065 | REG_V2_S3, 1066 | REG_V3_S0, 1067 | REG_V3_S1, 1068 | REG_V3_S2, 1069 | REG_V3_S3, 1070 | REG_V4_S0, 1071 | REG_V4_S1, 1072 | REG_V4_S2, 1073 | REG_V4_S3, 1074 | REG_V5_S0, 1075 | REG_V5_S1, 1076 | REG_V5_S2, 1077 | REG_V5_S3, 1078 | REG_V6_S0, 1079 | REG_V6_S1, 1080 | REG_V6_S2, 1081 | REG_V6_S3, 1082 | REG_V7_S0, 1083 | REG_V7_S1, 1084 | REG_V7_S2, 1085 | REG_V7_S3, 1086 | REG_V8_S0, 1087 | REG_V8_S1, 1088 | REG_V8_S2, 1089 | REG_V8_S3, 1090 | REG_V9_S0, 1091 | REG_V9_S1, 1092 | REG_V9_S2, 1093 | REG_V9_S3, 1094 | REG_V10_S0, 1095 | REG_V10_S1, 1096 | REG_V10_S2, 1097 | REG_V10_S3, 1098 | REG_V11_S0, 1099 | REG_V11_S1, 1100 | REG_V11_S2, 1101 | REG_V11_S3, 1102 | REG_V12_S0, 1103 | REG_V12_S1, 1104 | REG_V12_S2, 1105 | REG_V12_S3, 1106 | REG_V13_S0, 1107 | REG_V13_S1, 1108 | REG_V13_S2, 1109 | REG_V13_S3, 1110 | REG_V14_S0, 1111 | REG_V14_S1, 1112 | REG_V14_S2, 1113 | REG_V14_S3, 1114 | REG_V15_S0, 1115 | REG_V15_S1, 1116 | REG_V15_S2, 1117 | REG_V15_S3, 1118 | REG_V16_S0, 1119 | REG_V16_S1, 1120 | REG_V16_S2, 1121 | REG_V16_S3, 1122 | REG_V17_S0, 1123 | REG_V17_S1, 1124 | REG_V17_S2, 1125 | REG_V17_S3, 1126 | REG_V18_S0, 1127 | REG_V18_S1, 1128 | REG_V18_S2, 1129 | REG_V18_S3, 1130 | REG_V19_S0, 1131 | REG_V19_S1, 1132 | REG_V19_S2, 1133 | REG_V19_S3, 1134 | REG_V20_S0, 1135 | REG_V20_S1, 1136 | REG_V20_S2, 1137 | REG_V20_S3, 1138 | REG_V21_S0, 1139 | REG_V21_S1, 1140 | REG_V21_S2, 1141 | REG_V21_S3, 1142 | REG_V22_S0, 1143 | REG_V22_S1, 1144 | REG_V22_S2, 1145 | REG_V22_S3, 1146 | REG_V23_S0, 1147 | REG_V23_S1, 1148 | REG_V23_S2, 1149 | REG_V23_S3, 1150 | REG_V24_S0, 1151 | REG_V24_S1, 1152 | REG_V24_S2, 1153 | REG_V24_S3, 1154 | REG_V25_S0, 1155 | REG_V25_S1, 1156 | REG_V25_S2, 1157 | REG_V25_S3, 1158 | REG_V26_S0, 1159 | REG_V26_S1, 1160 | REG_V26_S2, 1161 | REG_V26_S3, 1162 | REG_V27_S0, 1163 | REG_V27_S1, 1164 | REG_V27_S2, 1165 | REG_V27_S3, 1166 | REG_V28_S0, 1167 | REG_V28_S1, 1168 | REG_V28_S2, 1169 | REG_V28_S3, 1170 | REG_V29_S0, 1171 | REG_V29_S1, 1172 | REG_V29_S2, 1173 | REG_V29_S3, 1174 | REG_V30_S0, 1175 | REG_V30_S1, 1176 | REG_V30_S2, 1177 | REG_V30_S3, 1178 | REG_V31_S0, 1179 | REG_V31_S1, 1180 | REG_V31_S2, 1181 | REG_V31_S3, 1182 | // D vector 1183 | REG_V0_D0, 1184 | REG_V0_D1, 1185 | REG_V1_D0, 1186 | REG_V1_D1, 1187 | REG_V2_D0, 1188 | REG_V2_D1, 1189 | REG_V3_D0, 1190 | REG_V3_D1, 1191 | REG_V4_D0, 1192 | REG_V4_D1, 1193 | REG_V5_D0, 1194 | REG_V5_D1, 1195 | REG_V6_D0, 1196 | REG_V6_D1, 1197 | REG_V7_D0, 1198 | REG_V7_D1, 1199 | REG_V8_D0, 1200 | REG_V8_D1, 1201 | REG_V9_D0, 1202 | REG_V9_D1, 1203 | REG_V10_D0, 1204 | REG_V10_D1, 1205 | REG_V11_D0, 1206 | REG_V11_D1, 1207 | REG_V12_D0, 1208 | REG_V12_D1, 1209 | REG_V13_D0, 1210 | REG_V13_D1, 1211 | REG_V14_D0, 1212 | REG_V14_D1, 1213 | REG_V15_D0, 1214 | REG_V15_D1, 1215 | REG_V16_D0, 1216 | REG_V16_D1, 1217 | REG_V17_D0, 1218 | REG_V17_D1, 1219 | REG_V18_D0, 1220 | REG_V18_D1, 1221 | REG_V19_D0, 1222 | REG_V19_D1, 1223 | REG_V20_D0, 1224 | REG_V20_D1, 1225 | REG_V21_D0, 1226 | REG_V21_D1, 1227 | REG_V22_D0, 1228 | REG_V22_D1, 1229 | REG_V23_D0, 1230 | REG_V23_D1, 1231 | REG_V24_D0, 1232 | REG_V24_D1, 1233 | REG_V25_D0, 1234 | REG_V25_D1, 1235 | REG_V26_D0, 1236 | REG_V26_D1, 1237 | REG_V27_D0, 1238 | REG_V27_D1, 1239 | REG_V28_D0, 1240 | REG_V28_D1, 1241 | REG_V29_D0, 1242 | REG_V29_D1, 1243 | REG_V30_D0, 1244 | REG_V30_D1, 1245 | REG_V31_D0, 1246 | REG_V31_D1, 1247 | // Q vector is already defined REG_V0, REG_V1, ..., REG_V31 1248 | // SVE 1249 | REG_Z0, 1250 | REG_Z1, 1251 | REG_Z2, 1252 | REG_Z3, 1253 | REG_Z4, 1254 | REG_Z5, 1255 | REG_Z6, 1256 | REG_Z7, 1257 | REG_Z8, 1258 | REG_Z9, 1259 | REG_Z10, 1260 | REG_Z11, 1261 | REG_Z12, 1262 | REG_Z13, 1263 | REG_Z14, 1264 | REG_Z15, 1265 | REG_Z16, 1266 | REG_Z17, 1267 | REG_Z18, 1268 | REG_Z19, 1269 | REG_Z20, 1270 | REG_Z21, 1271 | REG_Z22, 1272 | REG_Z23, 1273 | REG_Z24, 1274 | REG_Z25, 1275 | REG_Z26, 1276 | REG_Z27, 1277 | REG_Z28, 1278 | REG_Z29, 1279 | REG_Z30, 1280 | REG_Z31, 1281 | REG_P0, 1282 | REG_P1, 1283 | REG_P2, 1284 | REG_P3, 1285 | REG_P4, 1286 | REG_P5, 1287 | REG_P6, 1288 | REG_P7, 1289 | REG_P8, 1290 | REG_P9, 1291 | REG_P10, 1292 | REG_P11, 1293 | REG_P12, 1294 | REG_P13, 1295 | REG_P14, 1296 | REG_P15, 1297 | REG_P16, 1298 | REG_P17, 1299 | REG_P18, 1300 | REG_P19, 1301 | REG_P20, 1302 | REG_P21, 1303 | REG_P22, 1304 | REG_P23, 1305 | REG_P24, 1306 | REG_P25, 1307 | REG_P26, 1308 | REG_P27, 1309 | REG_P28, 1310 | REG_P29, 1311 | REG_P30, 1312 | REG_P31, 1313 | REG_PF0, 1314 | REG_PF1, 1315 | REG_PF2, 1316 | REG_PF3, 1317 | REG_PF4, 1318 | REG_PF5, 1319 | REG_PF6, 1320 | REG_PF7, 1321 | REG_PF8, 1322 | REG_PF9, 1323 | REG_PF10, 1324 | REG_PF11, 1325 | REG_PF12, 1326 | REG_PF13, 1327 | REG_PF14, 1328 | REG_PF15, 1329 | REG_PF16, 1330 | REG_PF17, 1331 | REG_PF18, 1332 | REG_PF19, 1333 | REG_PF20, 1334 | REG_PF21, 1335 | REG_PF22, 1336 | REG_PF23, 1337 | REG_PF24, 1338 | REG_PF25, 1339 | REG_PF26, 1340 | REG_PF27, 1341 | REG_PF28, 1342 | REG_PF29, 1343 | REG_PF30, 1344 | REG_PF31, 1345 | REG_END 1346 | }; 1347 | 1348 | #ifdef __cplusplus 1349 | extern "C" 1350 | { 1351 | #endif 1352 | const char* get_register_name(enum Register); 1353 | size_t get_register_size(enum Register); 1354 | #ifdef __cplusplus 1355 | } 1356 | #endif 1357 | --------------------------------------------------------------------------------