├── 4BitMultiplier.v ├── 4BitParalleladder.v ├── 4bit UpdownCounter.v ├── 4bit ripplecarry adder.v ├── 4bit synch counter.v ├── 4bitAsynchcounter.v ├── 8bitRippleCarryAdder.v ├── Accumulator Model.v ├── DFlipFlop.v ├── DUsingJK.v ├── Encoder8by3.v ├── NetLIst for Spartan 3 FPGA Chip.net ├── Psudo random bit generator.v ├── TFlipFlop.v ├── TUsingJK.v ├── TwoBitMagComp.v ├── and_gate.v ├── bcd_7seg.v ├── bcd_excess3.v ├── bin_gray.v ├── countermod10.v ├── decoder2by4.v ├── decoder3by8.v ├── demux1to4.v ├── demux1to8.v ├── excess3tobcd.v ├── full_adder_strucmodel.v ├── full_sub.v ├── full_sub_dataflow.v ├── graytoBin.v ├── half_adder.v ├── half_sub.v ├── jkFlipFlop.v ├── mux2to1 ├── mux4to1.v ├── mux8to1.v ├── mux8to1usingmux2to1 ├── mux8to1usingmux4to1.v ├── nand_gate.v ├── nor_gate.v ├── oneBitMagComparator.v ├── or_gate.v ├── pEncoder.v ├── pipo.v ├── piso.v ├── sipo.v ├── siso.v └── xor_gate.v /4BitMultiplier.v: -------------------------------------------------------------------------------- 1 | module mul(x, y, z); 2 | input [3:0]x,y; 3 | output [7:0]z; 4 | reg [3:0]b; 5 | reg [1:0]a; 6 | integer i=0; 7 | reg e=0; 8 | reg [7:0]z=8'b00000000; 9 | always @ (x or y) 10 | begin 11 | for (i=0;i<=3;i=i+1) 12 | begin 13 | a={x[i],e}; 14 | if (a==2'b01) 15 | begin 16 | z[7:4]=z[7:4]+y; 17 | end 18 | else if (a==2'b10) 19 | begin 20 | b=-y; 21 | z[7:4]=z[7:4]+b; 22 | end 23 | z=z>>1; 24 | z[7]=z[6]; 25 | e=x[i]; 26 | end 27 | end 28 | endmodule 29 | 30 | module testbench(); 31 | reg [3:0]x,y; 32 | wire [7:0]z; 33 | mul aa(x, y, z); 34 | initial 35 | begin 36 | x=4'b0011;y=4'b0101; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /4BitParalleladder.v: -------------------------------------------------------------------------------- 1 | module ha(a,b,s,c); 2 | inputa,b; 3 | outputs,c; 4 | regs,c; 5 | always@(a or b) 6 | begin 7 | case({a,b}) 8 | 2'b00:begin s=0;c=0; end 9 | 2'b01:begin s=1;c=0; end 10 | 2'b10:begin s=1;c=0; end 11 | 2'b11:begin s=0;c=1; end 12 | endcase 13 | end 14 | endmodule 15 | modulefa(a,b,cin,s,c); 16 | inputa,b,cin; 17 | outputs,c; 18 | wire s1,c1,c2; 19 | ha a1(a,b,s1,c1); 20 | ha a2(s1,cin,s,c2); 21 | assign c=c1|c2; 22 | endmodule 23 | module parallel(x, y, as, s, cout); 24 | input [03:0] x; 25 | input [03:0] y; 26 | input as; 27 | output [03:0] s; 28 | outputcout; 29 | wire c0,c1,c2,y0,y1,y2,y3; 30 | assign y0=y[0]^as; 31 | assign y1=y[1]^as; 32 | assign y2=y[2]^as; 33 | assign y3=y[3]^as; 34 | fa a1(x[0],y0,as,s[0],c0); 35 | fa a2(x[1],y1,c0,s[1],c1); 36 | fa a3(x[2],y2,c1,s[2],c2); 37 | fa a4(x[3],y3,c2,s[3],cout); 38 | endmodule 39 | 40 | module testbench(); 41 | reg [3:0]x; 42 | reg [3:0]y; 43 | reg as; 44 | wire [3:0]s; 45 | wirecout; 46 | parallelaaa(x,y,as,s,cout); 47 | initial 48 | begin 49 | as=0;x=4'b0010; 50 | y=4'b0100; 51 | #5 as=1;x=4'b1111;y=4'b1100; 52 | #50 $finish; 53 | end 54 | endmodule 55 | -------------------------------------------------------------------------------- /4bit UpdownCounter.v: -------------------------------------------------------------------------------- 1 | module jkff(j, k, clk, q); 2 | input j,k,clk; 3 | output q; 4 | reg q=0; 5 | always @ (negedge clk) 6 | begin 7 | if (j==0 && k==0) 8 | q<=q; 9 | else if (j==0 && k==1) 10 | q=0; 11 | else if (j==1 && k==0) 12 | q=1; 13 | else 14 | q<=~q; 15 | end 16 | endmodule 17 | module ud(ud, q, c); 18 | input ud,q; 19 | output c; 20 | assign c=(ud&q)|(~ud&~q); 21 | endmodule 22 | module ud4(clk, ud, q); 23 | input clk,ud; 24 | output [3:0]q; 25 | wire q1,q2,q3; 26 | jkff a(1,1,clk,q[0]); 27 | ud a1(ud,q[0],q1); 28 | jkff b(1,1,q1,q[1]); 29 | ud b1(ud,q[1],q2); 30 | jkff c(1,1,q2,q[2]); 31 | ud c1(ud,q[2],q3); 32 | jkff d(1,1,q3,q[3]); 33 | endmodule 34 | 35 | module testbench(); 36 | reg clk,ud; 37 | wire [3:0]q; 38 | ud4 u1(clk,ud,q); 39 | initial 40 | begin 41 | clk=1'b0; 42 | forever #5 clk=~clk; 43 | end 44 | initial 45 | begin 46 | ud=1; 47 | #170 ud=0; 48 | #150 $finish; 49 | end 50 | endmodule 51 | -------------------------------------------------------------------------------- /4bit ripplecarry adder.v: -------------------------------------------------------------------------------- 1 | modulefa(a,b,cin,s,cout); 2 | inputa,b,cin; 3 | outputs,cout; 4 | assign s=a?(b?(cin?1:0):(cin?0:1)):(b?(cin?0:1):(cin?1:0)); 5 | assign cout=a?(b?1:(cin?1:0)):(b?(cin?1:0):0); 6 | endmodule 7 | 8 | module rca4(x, y, cin, s, cout); 9 | input [3:0] x; 10 | input [3:0] y; 11 | inputcin; 12 | output [3:0] s; 13 | outputcout; 14 | wire c0,c1,c2; 15 | fa fa1(x[0],y[0],cin,s[0],c0); 16 | fa fa2(x[1],y[1],c0,s[1],c1); 17 | fa fa3(x[2],y[2],c1,s[2],c2); 18 | fa fa4(x[3],y[3],c2,s[3],cout); 19 | endmodule 20 | 21 | module testbench(); 22 | reg [3:0]x; 23 | reg [3:0]y; 24 | regcin; 25 | wire [3:0]s; 26 | wirecout; 27 | rca4rca(x,y,cin,s,cout); 28 | initial 29 | begin 30 | x=4'b0010;y=4'b0111;cin=0; 31 | #10 $finish; 32 | end 33 | endmodule -------------------------------------------------------------------------------- /4bit synch counter.v: -------------------------------------------------------------------------------- 1 | module c3(clk,clr,o); 2 | input clk,clr; 3 | output [3:0]o; 4 | wire w1,w2; 5 | sajk aa(1,1,clk,clr,o[0]); 6 | sajk bb(o[0],o[0],clk,clr,o[1]); 7 | sajk cc(w1,w1,clk,clr,o[2]); 8 | sajk dd(w2,w2,clk,clr,o[3]); 9 | and(w1,o[0],o[1]); 10 | and(w2,w1,o[2]); 11 | endmodule 12 | 13 | module sajk(j,k,clk,clr,q); 14 | input j,k; 15 | input clk; 16 | input clr; 17 | output q; 18 | reg q; 19 | always@(negedge clk or posedge clr) 20 | begin 21 | if(clr==1) 22 | q<=0; 23 | else 24 | begin 25 | case({j,k}) 26 | 0: q<=q; 27 | 1: q<=0; 28 | 2: q<=1; 29 | 3: q<=~q; 30 | endcase 31 | end 32 | end 33 | endmodule 34 | 35 | 36 | module testbench(); 37 | reg clk,clr; 38 | wire [3:0]o; 39 | c3 tst(clk,clr,o); 40 | always #1 clk=~clk; 41 | initial 42 | begin 43 | clr=1; clk=1; 44 | #4 clr=0; 45 | #40 $finish; 46 | end 47 | endmodule 48 | -------------------------------------------------------------------------------- /4bitAsynchcounter.v: -------------------------------------------------------------------------------- 1 | module c1(clk,clr,o); 2 | input clk,clr; 3 | output [3:0]o; 4 | sajk aa(1,1,clk,clr,o[0]); 5 | sajk bb(1,1,o[0],clr,o[1]); 6 | sajk cc(1,1,o[1],clr,o[2]); 7 | sajk dd(1,1,o[2],clr,o[3]); 8 | endmodule 9 | 10 | module sajk(j,k,clk,clr,q); 11 | input j,k; 12 | input clk; 13 | input clr; 14 | output q; 15 | reg q; 16 | always@(negedge clk or posedge clr) 17 | begin 18 | if(clr==1) 19 | q<=0; 20 | else 21 | begin 22 | case({j,k}) 23 | 0: q<=q; 24 | 1: q<=0; 25 | 2: q<=1; 26 | 3: q<=~q; 27 | endcase 28 | end 29 | end 30 | endmodule 31 | 32 | module testbench(); 33 | reg clk,clr; 34 | wire [3:0]o; 35 | c1 tst(clk,clr,o); 36 | always #1 clk=~clk; 37 | initial 38 | begin 39 | clr=1; clk=1; 40 | #4 clr=0; 41 | #40 $finish; 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /8bitRippleCarryAdder.v: -------------------------------------------------------------------------------- 1 | modulefa(a,b,cin,s,cout); 2 | inputa,b,cin; 3 | outputs,cout; 4 | assign s=a?(b?(cin?1:0):(cin?0:1)):(b?(cin?0:1):(cin?1:0)); 5 | assign cout=a?(b?1:(cin?1:0)):(b?(cin?1:0):0); 6 | endmodule 7 | 8 | module rca4(x, y, cin, s, cout); 9 | input [3:0] x; 10 | input [3:0] y; 11 | inputcin; 12 | output [3:0] s; 13 | outputcout; 14 | wire c0,c1,c2; 15 | fa fa1(x[0],y[0],cin,s[0],c0); 16 | fa fa2(x[1],y[1],c0,s[1],c1); 17 | fa fa3(x[2],y[2],c1,s[2],c2); 18 | fa fa4(x[3],y[3],c2,s[3],cout); 19 | endmodule 20 | module rca8(x, y, cin, s, cout); 21 | input [7:0] x; 22 | input [7:0] y; 23 | inputcin; 24 | output [7:0] s; 25 | outputcout; 26 | wire cout1; 27 | rca4 a1(x[3:0],y[3:0],cin,s[3:0],cout1); 28 | rca4 a2(x[7:4],y[7:4],cout1,s[7:4],cout); 29 | endmodule 30 | 31 | module testbench(); 32 | reg [7:0]x; 33 | reg [7:0]y; 34 | regcin; 35 | wire [7:0]s; 36 | wirecout; 37 | rca8rca(x,y,cin,s,cout); 38 | initial 39 | begin 40 | x=8'b01111010;y=8'b10011010;cin=0; 41 | #10 $finish; 42 | end 43 | endmodule -------------------------------------------------------------------------------- /Accumulator Model.v: -------------------------------------------------------------------------------- 1 | module acc(d,clk,rst,s); 2 | input rst,clk; 3 | input [0:3]d; 4 | reg [0:3]temp=4'b0000; 5 | output [0:3]s; 6 | always @ (negedge clk ) 7 | begin 8 | if (rst==1) 9 | temp=4'h0; 10 | else 11 | temp[0:3]=(temp[0:3]+d[0:3]); 12 | end 13 | assign s[0:3]=temp[0:3]; 14 | endmodule 15 | 16 | module testbench(); 17 | reg rst,clk; 18 | reg [0:3]d; 19 | wire [0:3]s; 20 | acc test(d,clk,rst,s); 21 | initial 22 | begin 23 | clk=1; 24 | forever #5 clk=~clk; 25 | end 26 | initial 27 | begin 28 | d=4'b0101;rst=1; 29 | #10 d=4'b0101;rst=0; 30 | #10 d=4'b0100;rst=0; 31 | #10 d=4'b0110;rst=0; 32 | #10 $finish; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /DFlipFlop.v: -------------------------------------------------------------------------------- 1 | module dd(d,clk,clr,q); 2 | input d,clk,clr; 3 | output q; 4 | reg q; 5 | always@(posedge clk or posedge clr) 6 | begin 7 | if(clr==1) 8 | q=0; 9 | else 10 | q=d; 11 | end 12 | endmodule 13 | 14 | module testbench(); 15 | reg d; 16 | reg clk; 17 | reg clr; 18 | wire q; 19 | dd sa(d,clk,clr,q); 20 | always #1 clk=~clk; 21 | initial 22 | begin 23 | clk=1; 24 | clr=1; 25 | d=0; 26 | #4 d=1; clr=0; 27 | #4 d=0; 28 | #4 d=0; 29 | #4 d=1; 30 | #4 $finish; 31 | end 32 | endmodule -------------------------------------------------------------------------------- /DUsingJK.v: -------------------------------------------------------------------------------- 1 | module dusingjk(d,q,clk,clr); 2 | input d,clk,clr; 3 | output q; 4 | reg q; 5 | jkff sa(d,~d,q,clk,clr); 6 | endmodule 7 | 8 | module testbench(); 9 | reg d; 10 | reg clk; 11 | reg clr; 12 | wire q; 13 | dusingjk sa(d,q,clk,clr); 14 | always #1 clk=~clk; 15 | initial 16 | begin 17 | clk=0; 18 | clr=1; 19 | d=0; 20 | #4 d=1; clr=0; 21 | #4 d=0; 22 | #4 d=0; 23 | #4 d=1; 24 | #4 $finish; 25 | end 26 | endmodule -------------------------------------------------------------------------------- /Encoder8by3.v: -------------------------------------------------------------------------------- 1 | module qwdc(i,o); 2 | input[7:0]i; 3 | output[2:0]o; 4 | or(o[0],i[1],i[3],i[5],i[7]); 5 | or(o[1],i[2],i[3],i[6],i[7]); 6 | or(o[2],i[4],i[6],i[5],i[7]); 7 | endmodule 8 | module testbench(); 9 | reg [7:0]i; 10 | wire [2:0]o; 11 | qwdc aa(i,o); 12 | initial 13 | begin 14 | i=8'b00000001; 15 | #5 i=8'b00000010; 16 | #5 i=8'b10000000; 17 | end 18 | initial 19 | begin 20 | $monitor($time,"i=%b,o=%b",i,o); 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /NetLIst for Spartan 3 FPGA Chip.net: -------------------------------------------------------------------------------- 1 | NETLIST: 2 | UCF for half add: 3 | NET "a" LOC = "F12" ; 4 | NET "b" LOC = "E12" ; 5 | NET "s" LOC = "L13" ; 6 | NET "c" LOC = "L14" ; 7 | UCF for half sub: 8 | NET "a" LOC = "F12" ; 9 | NET "b" LOC = "E12" ; 10 | NET "di" LOC = "L13" ; 11 | NET "bo" LOC = "L14" 12 | UCF for full add: 13 | NET "a" LOC = "F12" ; 14 | NET "b" LOC = "E12" ; 15 | NET "cin" LOC = "F11" ; 16 | NET "s" LOC = "L13" ; 17 | NET "cout" LOC = "L14" 18 | UCF for full sub: 19 | NET "a" LOC = "F12" ; 20 | NET "b" LOC = "E12" ; 21 | NET "c" LOC = "F11" ; 22 | NET "di" LOC = "L13" ; 23 | NET "bo" LOC = "L14" -------------------------------------------------------------------------------- /Psudo random bit generator.v: -------------------------------------------------------------------------------- 1 | module prbs(clk,clr,rand,temp); 2 | input clk,clr; 3 | output [3:0]rand; 4 | wire [3:0]rand; 5 | output [3:0]temp; 6 | reg [3:0]temp=0; 7 | always @ (posedge clk) 8 | begin 9 | if(clr==1) 10 | temp=4'hf; 11 | else 12 | temp={temp[0]^temp[1],temp[3],temp[2],temp[1]}; 13 | end 14 | assign rand[3:0]=temp[3:0]; 15 | endmodule 16 | 17 | module testbench(); 18 | reg clk,clr; 19 | wire [3:0]rand; 20 | prbs test(clk,clr,rand); 21 | initial 22 | begin 23 | clk=1; 24 | forever #5 clk=~clk; 25 | end 26 | initial 27 | begin 28 | clr=1; 29 | #100 clr=0; 30 | #200 $finish; 31 | end 32 | endmodule 33 | -------------------------------------------------------------------------------- /TFlipFlop.v: -------------------------------------------------------------------------------- 1 | module tt(t,clk,clr,q); 2 | input t,clk,clr; 3 | output q; 4 | reg q; 5 | always@(posedge clk or posedge clr) 6 | begin 7 | if(clr==1) 8 | q=0; 9 | else 10 | begin 11 | case(t) 12 | 0: q=q; 13 | 1: q=~q; 14 | endcase 15 | end 16 | end 17 | endmodule 18 | 19 | module testbench(); 20 | reg t; 21 | reg clk; 22 | reg clr; 23 | wire q; 24 | tt sa(t,clk,clr,q); 25 | always #1 clk=~clk; 26 | initial 27 | begin 28 | clk=1; 29 | clr=1; 30 | t=0; 31 | #4 t=1; clr=0; 32 | #4 t=0; 33 | #4 t=0; 34 | #4 t=1; 35 | #4 $finish; 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /TUsingJK.v: -------------------------------------------------------------------------------- 1 | module tusingjk(t,q,clk,clr); 2 | input t,clk,clr; 3 | output q; 4 | jkff(t,t,q,clk,clr); 5 | endmodule 6 | 7 | module testbench(); 8 | reg t; 9 | reg clk; 10 | reg clr; 11 | wire q; 12 | tusingjk sa(t,q,clk,clr); 13 | always #1 clk=~clk; 14 | initial 15 | begin 16 | clk=0; 17 | clr=1; 18 | t=0; 19 | #4 t=1; clr=0; 20 | #4 t=0; 21 | #4 t=0; 22 | #4 t=1; 23 | #4 $finish; 24 | end 25 | endmodule -------------------------------------------------------------------------------- /TwoBitMagComp.v: -------------------------------------------------------------------------------- 1 | module comp2(a0, a1, b0, b1, x, y, z); 2 | input a0; 3 | input a1; 4 | input b0; 5 | input b1; 6 | output x; 7 | output y; 8 | output z; 9 | wire [2:0]m; 10 | wire [2:0]n; 11 | comp1jk(a0,b0,m[2],m[1],m[0]); 12 | comp1jkq(a1,b1,n[2],n[1],n[0]); 13 | assign x=((m[2]==1)|((m[0]==1)&(n[2]==1)))?1:0; 14 | assign y=((m[1]==1)|((m[0]==1)&(n[1]==1)))?1:0; 15 | assign z=((m[0]==1)&(n[0]==1))?1:0; 16 | endmodule 17 | 18 | module testbench(); 19 | reg a0,a1,b0,b1; 20 | wirex,y,z; 21 | comp2dd(a0,a1,b0,b1,x,y,z); 22 | always@(a0 or a1 or b0 or b1); 23 | initial 24 | begin 25 | a0=1;a1=1;b0=1;b1=1; 26 | #5 a0=0;a1=1;b0=1;b1=0; 27 | #5 a0=1;a1=0;b0=0;b1=1; 28 | #50 $finish; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /and_gate.v: -------------------------------------------------------------------------------- 1 | module anndgate(a,b,y); 2 | input a,b; 3 | output y; 4 | reg y; 5 | always@(a,b) 6 | begin 7 | if(a==1&&b==1) 8 | y=1; 9 | else 10 | y=0; 11 | end 12 | endmodule 13 | module testbench(); 14 | reg a,b; 15 | wire y; 16 | anndgate sa(a,b,y); 17 | initial 18 | begin 19 | a=0; b=0; 20 | #5 a=0; b=1; 21 | #5 a=1; b=0; 22 | #5 a=1; b=1; 23 | #5 $finish; 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /bcd_7seg.v: -------------------------------------------------------------------------------- 1 | module sevenseg(d, y); 2 | input [3:0] d; 3 | output [6:0] y; 4 | reg [6:0]y; 5 | always@(d) 6 | begin 7 | case(d) 8 | 4'b0000 : y=7'b1111110; 9 | 4'b0001 : y=7'b0110000; 10 | 4'b0010 : y=7'b1101101; 11 | 4'b0011 : y=7'b1111001; 12 | 4'b0100 : y=7'b0110011; 13 | 4'b0101 : y=7'b1011011; 14 | 4'b0110 : y=7'b1011111; 15 | 4'b0111 : y=7'b1110000; 16 | 4'b1000 : y=7'b1111111; 17 | 4'b1001 : y=7'b1110011; 18 | endcase 19 | end 20 | endmodule 21 | 22 | module testbench(); 23 | reg [3:0]d; 24 | wire [6:0]y; 25 | sevenseg s1(d,y); 26 | initial 27 | begin 28 | d=4'b0000; 29 | #10 d=4'b0001; 30 | #10 d=4'b0010; 31 | #10 d=4'b0011; 32 | #10 d=4'b0100; 33 | #10 d=4'b0101; 34 | #10 d=4'b0110; 35 | #10 d=4'b0111; 36 | #10 d=4'b1000; 37 | #10 d=4'b1001; 38 | #10 $finish; 39 | end 40 | endmodule -------------------------------------------------------------------------------- /bcd_excess3.v: -------------------------------------------------------------------------------- 1 | module be3(d, y); 2 | input [3:0] d; 3 | output [3:0] y; 4 | assign y[0]=~d[0]; 5 | assign y[1]=~(d[0]^d[1]); 6 | assign y[2]=d[2]^((d[0])|(d[1])); 7 | assign y[3]=d[3]|(d[2]&(d[1]|d[0])); 8 | endmodule 9 | 10 | 11 | module testbench(); 12 | reg [3:0]d; 13 | wire [3:0]y; 14 | be3 s1(d,y); 15 | initial 16 | begin 17 | d=4'b0000; 18 | #10 d=4'b0001; 19 | #10 d=4'b0010; 20 | #10 d=4'b0011; 21 | #10 d=4'b0100; 22 | #10 d=4'b0101; 23 | #10 d=4'b0110; 24 | #10 d=4'b0111; 25 | #10 d=4'b1000; 26 | #10 d=4'b1001; 27 | #10 $finish; 28 | end 29 | endmodule -------------------------------------------------------------------------------- /bin_gray.v: -------------------------------------------------------------------------------- 1 | //Dataflow Modelling 2 | module bg(b, g); 3 | input [3:0]b; 4 | output [3:0]g; 5 | assign g[3]=b[3]; 6 | assign g[2]=b[3]^b[2]; 7 | assign g[1]=b[1]^b[2]; 8 | assign g[0]=b[0]^b[1]; 9 | endmodule 10 | 11 | module testbench(); 12 | reg [3:0]b; 13 | wire [3:0]g; 14 | bg b1(b,g); 15 | initial 16 | begin 17 | b=4'd 0; 18 | #5 b=4'd 1; 19 | #5 b=4'd 2; 20 | #5 b=4'd 3; 21 | #5 b=4'd 4; 22 | #5 b=4'd 5; 23 | #5 b=4'd 6; 24 | #5 b=4'd 7; 25 | #5 b=4'd 8; 26 | #5 b=4'd 9; 27 | #5 b=4'd 10; 28 | #5 b=4'd 11; 29 | #5 b=4'd 12; 30 | #5 b=4'd 13; 31 | #5 b=4'd 14; 32 | #5 b=4'd 15; 33 | #5 $finish; 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /countermod10.v: -------------------------------------------------------------------------------- 1 | module c2(clk,clr,o); 2 | input clk,clr; 3 | output [3:0]o; 4 | wire w1,w2; 5 | sajk aa(1,1,clk,w2,o[0]); 6 | sajk bb(1,1,o[0],w2,o[1]); 7 | sajk cc(1,1,o[1],w2,o[2]); 8 | sajk dd(1,1,o[2],w2,o[3]); 9 | and(w1,o[3],o[1]); 10 | or(w2,clr,w1); 11 | endmodule 12 | 13 | 14 | module sajk(j,k,clk,clr,q); 15 | input j,k; 16 | input clk; 17 | input clr; 18 | output q; 19 | reg q; 20 | always@(negedge clk or posedge clr) 21 | begin 22 | if(clr==1) 23 | q<=0; 24 | else 25 | begin 26 | case({j,k}) 27 | 0: q<=q; 28 | 1: q<=0; 29 | 2: q<=1; 30 | 3: q<=~q; 31 | endcase 32 | end 33 | end 34 | endmodule 35 | 36 | 37 | module testbench(); 38 | reg clk,clr; 39 | wire [3:0]o; 40 | c2 tst(clk,clr,o); 41 | always #1 clk=~clk; 42 | initial 43 | begin 44 | clr=1; clk=1; 45 | #4 clr=0; 46 | #40 $finish; 47 | end 48 | endmodule -------------------------------------------------------------------------------- /decoder2by4.v: -------------------------------------------------------------------------------- 1 | module as(y0,y1,y2,y3,a,b,e); 2 | input a,b,e; 3 | output y0,y1,y2,y3; 4 | wire c,d; 5 | not(c,a); 6 | not(d,b); 7 | and(y0,c,d,e); 8 | and(y1,c,b,e); 9 | and(y2,a,d,e); 10 | and(y3,a,b,e); 11 | endmodule 12 | 13 | module testbench(); 14 | reg a,b,e; 15 | wire y0,y1,y2,y3; 16 | as aaa(y0,y1,y2,y3,a,b,e); 17 | initial 18 | begin 19 | a=0;b=0;e=1; 20 | #5 a=0;b=1;e=1; 21 | #50 $finish; 22 | end 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /decoder3by8.v: -------------------------------------------------------------------------------- 1 | module decoder2(a, b, e, y); 2 | input a; 3 | input b; 4 | input e; 5 | output [3:0] y; 6 | and a1(y[0],e,~a,~b); 7 | and a2(y[1],e,~a,b); 8 | and a3(y[2],e,a,~b); 9 | and a4(y[3],e,a,b); 10 | endmodule 11 | 12 | module decoder3(a, b, c, y); 13 | input a; 14 | input b; 15 | input c; 16 | output [7:0] y; 17 | decoder2 d1(b,c,~a,y[3:0]); 18 | decoder2 d2(b,c,a,y[7:4]); 19 | endmodule 20 | 21 | module testbench(); 22 | reg a,b,c; 23 | wire [7:0]y; 24 | decoder3 a1(a,b,c,y); 25 | initial 26 | begin 27 | a=0;b=0;c=0; 28 | #10 a=0;b=0;c=1; 29 | #10 a=0;b=1;c=0; 30 | #10 a=0;b=1;c=1; 31 | #10 a=1;b=0;c=0; 32 | #10 a=1;b=0;c=1; 33 | #10 a=1;b=1;c=0; 34 | #10 a=1;b=1;c=1; 35 | #10 $finish; 36 | end 37 | endmodule -------------------------------------------------------------------------------- /demux1to4.v: -------------------------------------------------------------------------------- 1 | module dmux4(d, s, y); 2 | input d; 3 | input [1:0] s; 4 | output [3:0] y; 5 | assign y[0]=d&(~s[1])&(~s[0]); 6 | assign y[1]=d&(~s[1])&(s[0]); 7 | assign y[2]=d&(s[1])&(~s[0]); 8 | assign y[3]=d&(s[1])&(s[0]); 9 | endmodule 10 | 11 | module testbench(); 12 | reg d; 13 | reg [1:0]s; 14 | wire [3:0]y; 15 | dmux4 d1(d,s,y); 16 | initial 17 | begin 18 | d=1;s=2'b00; 19 | #10 d=1;s=2'b01; 20 | #10 d=1;s=2'b10; 21 | #10 d=1;s=2'b11; 22 | #10 $finish; 23 | end 24 | endmodule -------------------------------------------------------------------------------- /demux1to8.v: -------------------------------------------------------------------------------- 1 | module dmux8(s, d, y); 2 | input [2:0] s; 3 | input d; 4 | output [7:0] y; 5 | reg [7:0]y; 6 | always@(s or d) 7 | if (s==3'd0) 8 | begin 9 | y=8'h00; 10 | y[0]=d; 11 | end 12 | else if (s==3'd1) 13 | begin 14 | y=8'h00; 15 | y[1]=d; 16 | end 17 | else if (s==3'd2) 18 | begin 19 | y=8'h00; 20 | y[2]=d; 21 | end 22 | else if (s==3'd3) 23 | begin 24 | y=8'h00; 25 | y[3]=d; 26 | end 27 | else if (s==3'd4) 28 | begin 29 | y=8'h00; 30 | y[4]=d; 31 | end 32 | else if (s==3'd5) 33 | begin 34 | y=8'h00; 35 | y[5]=d; 36 | end 37 | else if (s==3'd6) 38 | begin 39 | y=8'h00; 40 | y[6]=d; 41 | end 42 | else if (s==3'd7) 43 | begin 44 | y=8'h00; 45 | y[7]=d; 46 | end 47 | endmodule 48 | 49 | module testbench(); 50 | reg d; 51 | reg [2:0]s; 52 | wire [7:0]y; 53 | dmux8 d1(s,d,y); 54 | initial 55 | begin 56 | d=1;s=3'd0; 57 | #10 d=1;s=3'd1; 58 | #10 d=1;s=3'd2; 59 | #10 d=1;s=3'd3; 60 | #10 d=1;s=3'd4; 61 | #10 d=1;s=3'd5; 62 | #10 d=1;s=3'd6; 63 | #10 d=1;s=3'd7; 64 | #10 $finish; 65 | end 66 | endmodule 67 | -------------------------------------------------------------------------------- /excess3tobcd.v: -------------------------------------------------------------------------------- 1 | module e3b(d, y); 2 | input [3:0] d; 3 | output [3:0] y; 4 | assign y[0]=~d[0]; 5 | assign y[1]=d[0]^d[1]; 6 | assign y[2]=d[2]^((~d[0])|(~d[1])); 7 | assign y[3]=(d[2]&d[3])|(d[3]&d[1]&d[0]); 8 | endmodule 9 | 10 | module testbench(); 11 | reg [3:0]d; 12 | wire [3:0]y; 13 | e3b s1(d,y); 14 | initial 15 | begin 16 | d=4'b0011; 17 | #10 d=4'b0100; 18 | #10 d=4'b0101; 19 | #10 d=4'b0110; 20 | #10 d=4'b0111; 21 | #10 d=4'b1000; 22 | #10 d=4'b1001; 23 | #10 d=4'b1010; 24 | #10 d=4'b1011; 25 | #10 d=4'b1100; 26 | #10 $finish; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /full_adder_strucmodel.v: -------------------------------------------------------------------------------- 1 | module sfulladder(a,b,c,cout,sum); 2 | input a,b,c; 3 | output cout,sum; 4 | wire w1,w2,w3; 5 | shalfadder aa(a,b,w1,w2); 6 | shalfadder bb(c,w2,w3,sum); 7 | or(cout,w1,w3); 8 | endmodule 9 | 10 | module testbench(); 11 | reg a,b,c; 12 | wire cout,sum; 13 | sfulladder sa(a,b,c,cout,sum); 14 | always #1 c=~c; 15 | always #2 b=~b; 16 | always #4 a=~a; 17 | initial 18 | begin 19 | a=0; b=0; c=0; 20 | #8 $finish; 21 | end 22 | endmodule -------------------------------------------------------------------------------- /full_sub.v: -------------------------------------------------------------------------------- 1 | module sfullsub(a,b,c,bo,di); 2 | input a,b,c; 3 | output di,bo; 4 | wire w1,w2,w3; 5 | shalfsub aa(a,b,w1,w2); 6 | shalfsub bb(w2,c,w3,di); 7 | or(bo,w1,w3); 8 | endmodule 9 | 10 | module testbench(); 11 | reg a,b,c; 12 | wire bo,di; 13 | sfullsub sa(a,b,c,bo,di); 14 | always #1 c=~c; 15 | always #2 b=~b; 16 | always #4 a=~a; 17 | initial 18 | begin 19 | a=0; b=0; c=0; 20 | #8 $finish; 21 | end 22 | endmodule -------------------------------------------------------------------------------- /full_sub_dataflow.v: -------------------------------------------------------------------------------- 1 | module sfullsub(a,b,c,bo,di); 2 | input a,b,c; 3 | output di,bo; 4 | assign di=a^b^c; 5 | assign bo=(~a&b)|(~a&c)|(b&c); 6 | endmodule 7 | 8 | module testbench(); 9 | reg a,b,c; 10 | wire bo,di; 11 | sfullsub sa(a,b,c,bo,di); 12 | always #1 c=~c; 13 | always #2 b=~b; 14 | always #4 a=~a; 15 | initial 16 | begin 17 | a=0; b=0; c=0; 18 | #8 $finish; 19 | end 20 | endmodule -------------------------------------------------------------------------------- /graytoBin.v: -------------------------------------------------------------------------------- 1 | module gb(y, x); 2 | input [3:0] y; 3 | input [3:0] x; 4 | assign x[0]=y[3]^y[2]^y[1]^y[0]; 5 | assign x[1]=y[3]^y[2]^y[1]; 6 | assign x[2]=y[3]^y[2]; 7 | assign x[3]=y[3]; 8 | endmodule 9 | 10 | module testbench(); 11 | reg [3:0]y; 12 | wire [3:0]x; 13 | gb b1(y,x); 14 | initial 15 | begin 16 | y=4'd0; 17 | #10 y=4'd1; 18 | #10 y=4'd3; 19 | #10 y=4'd2; 20 | #10 y=4'd6; 21 | #10 y=4'd7; 22 | #10 y=4'd5; 23 | #10 y=4'd4; 24 | #10 y=4'd12; 25 | #10 y=4'd13; 26 | #10 y=4'd15; 27 | #10 y=4'd14; 28 | #10 y=4'd10; 29 | #10 y=4'd11; 30 | #10 y=4'd9; 31 | #10 y=4'd8; 32 | #10 $finish; 33 | end 34 | endmodule -------------------------------------------------------------------------------- /half_adder.v: -------------------------------------------------------------------------------- 1 | module halfadder(a,b,sum,carry); 2 | input a,b; 3 | output sum,carry; 4 | xor(sum,a,b); 5 | and(carry,a,b); 6 | endmodule 7 | 8 | module testbench(); 9 | reg a,b; 10 | wire sum,carry; 11 | halfadder h1(a,b,sum,carry); 12 | initial 13 | begin 14 | a=0;b=0; 15 | #5 a=0;b=1; 16 | #5 a=1;b=0; 17 | #5 a=1;b=1; 18 | #5 $finish; 19 | end 20 | endmodule -------------------------------------------------------------------------------- /half_sub.v: -------------------------------------------------------------------------------- 1 | module shalfsub(a,b,bo,di); 2 | input a,b; 3 | output bo,di; 4 | wire x; 5 | assign x=~a; 6 | assign bo=x&b; 7 | assign di=a^b; 8 | endmodule 9 | 10 | module testbench(); 11 | reg a,b; 12 | wire c,s; 13 | shalfsub tst1(a,b,c,s); 14 | initial 15 | begin 16 | a=0; b=0; 17 | #5 a=0; b=1; 18 | #5 a=1; b=0; 19 | #5 a=1; b=1; 20 | #5 $finish; 21 | end 22 | endmodule -------------------------------------------------------------------------------- /jkFlipFlop.v: -------------------------------------------------------------------------------- 1 | module jkff(j,k,q,clk,clr); 2 | input j,k; 3 | input clk; 4 | input clr; 5 | output q; 6 | reg q; 7 | always@(posedge clk or posedge clr) 8 | begin 9 | if(clr==1) 10 | q=0; 11 | else 12 | begin 13 | case({j,k}) 14 | 0: q=q; 15 | 1: q=0; 16 | 2: q=1; 17 | 3: q=~q; 18 | endcase 19 | end 20 | end 21 | endmodule 22 | module testbench(); 23 | reg j,k; 24 | reg clk; 25 | reg clr; 26 | wire q; 27 | jkff sa(j,k,q,clk,clr); 28 | always #1 clk=~clk; 29 | initial 30 | begin 31 | clk=1; 32 | clr=1; 33 | j=0; k=0; 34 | #4 j=1; k=0; clr=0; 35 | #4 j=0; k=0; 36 | #4 j=1; k=1; 37 | #4 j=0; k=1; 38 | #4 $finish; 39 | end 40 | endmodule -------------------------------------------------------------------------------- /mux2to1: -------------------------------------------------------------------------------- 1 | module muxtwo(i1,i2,s,y) 2 | input i1,i2,s; 3 | output y; 4 | assign y=(s?i1:i2); 5 | endmodule 6 | 7 | module testbench(); 8 | reg i1,i2,s; 9 | wire y; 10 | mux m1(i1,i0,s,y) 11 | initial 12 | begin 13 | s=0; i1=1; i2=1; 14 | #5 s=1; i1=0; i2=1; 15 | #5 $finish 16 | end 17 | endmodue -------------------------------------------------------------------------------- /mux4to1.v: -------------------------------------------------------------------------------- 1 | module mux4to1(d,s,y); 2 | input [3:0]d; 3 | input [1:0]s; 4 | output y; 5 | assign y=(s[1]?(s[0]?d[3]:d[2]):(s[0]?d[1]:d[0])); 6 | endmodule 7 | 8 | module testbench(); 9 | reg [1:0]s; 10 | reg [3:0]d; 11 | wire y; 12 | mux4to1 bb(d,s,y); 13 | initial 14 | begin 15 | s=2'b00; d=4'b0001; 16 | #5 s=2'b01;d=4'b0010; 17 | #5 s=2'b10;d=4'b0100; 18 | #5 s=2'b11;d=4'b1000; 19 | #50 $finish; 20 | end 21 | endmodule -------------------------------------------------------------------------------- /mux8to1.v: -------------------------------------------------------------------------------- 1 | module mux8to1(d,s,y); 2 | input [2:0]s; 3 | input [7:0]d; 4 | output y; 5 | reg y; 6 | always @(s or d) 7 | begin 8 | case(s) 9 | 3'b000: y=d[0]; 10 | 3'b001: y=d[1]; 11 | 3'b010: y=d[2]; 12 | 3'b011: y=d[3]; 13 | 3'b100: y=d[4]; 14 | 3'b101: y=d[5]; 15 | 3'b110: y=d[6]; 16 | 3'b111: y=d[7]; 17 | endcase 18 | end 19 | endmodule 20 | 21 | module testbench(); 22 | reg [2:0]s; 23 | reg [7:0]d; 24 | wire y; 25 | mux82 cc(d,s,y); 26 | initial 27 | begin 28 | d=8'b00000001; s=3'b000; 29 | #5 d=8'b00000010; s=3'b001; 30 | #5 d=8'b00000100; s=3'b010; 31 | #5 d=8'b00001000; s=3'b011; 32 | #5 d=8'b00010000; s=3'b100; 33 | #5 d=8'b00100000; s=3'b101; 34 | #5 d=8'b01000000; s=3'b110; 35 | #5 d=8'b10000000; s=3'b111; 36 | #50 $finish; 37 | end 38 | endmodule -------------------------------------------------------------------------------- /mux8to1usingmux2to1: -------------------------------------------------------------------------------- 1 | module mux2(s, d0, d1, y); 2 | input s; 3 | input d0; 4 | input d1; 5 | output y; 6 | assign y=(~s&d0)|(s&d1); 7 | endmodule 8 | 9 | module mux82(s, d, y); 10 | input [2:0] s; 11 | input [7:0] d; 12 | output y; 13 | wire y1,y2,y3,y4,y5,y6; 14 | mux2 m1(s[0],d[0],d[1],y1); 15 | mux2 m2(s[0],d[2],d[3],y2); 16 | mux2 m3(s[0],d[4],d[5],y3); 17 | mux2 m4(s[0],d[6],d[7],y4); 18 | mux2 m5(s[1],y1,y2,y5); 19 | mux2 m6(s[1],y3,y4,y6); 20 | mux2 m7(s[2],y5,y6,y); 21 | endmodule 22 | 23 | module testbench(); 24 | reg [2:0]s; 25 | reg [7:0]d; 26 | wire y; 27 | mux82 cc(d,s,y); 28 | initial 29 | begin 30 | d=8'b00000001; s=3'b000; 31 | #5 d=8'b00000010; s=3'b001; 32 | #5 d=8'b00000100; s=3'b010; 33 | #5 d=8'b00001000; s=3'b011; 34 | #5 d=8'b00010000; s=3'b100; 35 | #5 d=8'b00100000; s=3'b101; 36 | #5 d=8'b01000000; s=3'b110; 37 | #5 d=8'b10000000; s=3'b111; 38 | #50 $finish; 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /mux8to1usingmux4to1.v: -------------------------------------------------------------------------------- 1 | module mux2(s, d0, d1, y); 2 | input s; 3 | input d0; 4 | input d1; 5 | output y; 6 | wire a1; 7 | wire a2; 8 | and aa(a1,~s,d0); 9 | and bb(a2,s,d1); 10 | or cc(y,a1,a2); 11 | endmodule 12 | 13 | module mux4(s, d, y); 14 | input [1:0] s; 15 | input [3:0] d; 16 | output y; 17 | reg y; 18 | always@(s or d) 19 | begin 20 | case(s) 21 | 2'b00 : y=d[0]; 22 | 2'b01 : y=d[1]; 23 | 2'b10 : y=d[2]; 24 | 2'b10 : y=d[3]; 25 | endcase 26 | end 27 | endmodule 28 | 29 | module mux84(s, d, y); 30 | input [2:0] s; 31 | input [7:0] d; 32 | output y; 33 | wire y1,y2; 34 | mux4 aa(s[1:0],d[3:0],y1); 35 | mux4 bb(s[1:0],d[7:4],y2); 36 | mux2 cc(s[2],y1,y2,y); 37 | endmodule 38 | -------------------------------------------------------------------------------- /nand_gate.v: -------------------------------------------------------------------------------- 1 | module nand_gate(a,b,y); 2 | input a,b; 3 | output y; 4 | reg y; 5 | always@(a,b) 6 | begin 7 | if(a==1&&b==1) 8 | y=0; 9 | else 10 | y=0; 11 | end 12 | endmodule 13 | 14 | module testbench(); 15 | reg a,b; 16 | wire y; 17 | nand_gate sa(a,b,y); 18 | initial 19 | begin 20 | a=0; b=0; 21 | #5 a=0; b=1; 22 | #5 a=1; b=0; 23 | #5 a=1; b=1; 24 | #5 $finish; 25 | end 26 | endmodule -------------------------------------------------------------------------------- /nor_gate.v: -------------------------------------------------------------------------------- 1 | module nor_gate(a,b,y); 2 | input a,b; 3 | output y; 4 | reg y; 5 | always@(a,b) 6 | begin 7 | if(a==0&&b==0) 8 | y=1; 9 | else 10 | y=0; 11 | end 12 | endmodule 13 | 14 | module testbench(); 15 | reg a,b; 16 | wire y; 17 | nor_gate sa(a,b,y); 18 | initial 19 | begin 20 | a=0; b=0; 21 | #5 a=0; b=1; 22 | #5 a=1; b=0; 23 | #5 a=1; b=1; 24 | #5 $finish; 25 | end 26 | endmodule -------------------------------------------------------------------------------- /oneBitMagComparator.v: -------------------------------------------------------------------------------- 1 | module comp1(a, b, x, y, z); 2 | input a; 3 | input b; 4 | output x; 5 | output y; 6 | output z; 7 | assign y=(ab)?1:0; 9 | assign z=(a==b)?1:0; 10 | endmodule 11 | 12 | module testbench(); 13 | rega,b; 14 | wirex,y,z; 15 | comp1ck(a,b,x,y,z); 16 | always@(a or b); 17 | initial 18 | begin 19 | a=1;b=1; 20 | #5 a=0;b=1; 21 | #5 a=1;b=0; 22 | #5 a=0;b=0; 23 | end 24 | initial 25 | begin 26 | $monitor($time,"a=%b,b=%b,x=%b,y=%b,z=%b",a,b,x,y,z); 27 | end 28 | endmodule -------------------------------------------------------------------------------- /or_gate.v: -------------------------------------------------------------------------------- 1 | module or_gate(a,b,y); 2 | input a,b; 3 | output y; 4 | or(y,a,b); 5 | endmodule 6 | 7 | module testbench(); 8 | reg a,b; 9 | wire y; 10 | or_gate sa(a,b,y); 11 | initial 12 | begin 13 | a=0; b=0; 14 | #5 a=0; b=1; 15 | #5 a=1; b=0; 16 | #5 a=1; b=1; 17 | #5 $finish; 18 | end 19 | endmodule -------------------------------------------------------------------------------- /pEncoder.v: -------------------------------------------------------------------------------- 1 | module pencoder(d, y, v); 2 | input [3:0] d; 3 | output [1:0] y; 4 | output v; 5 | assign v=d[0]|d[1]|d[2]|d[3]; 6 | assign y[0]=d[3]|(d[1]&~d[2]); 7 | assign y[1]=d[2]|d[3]; 8 | endmodule 9 | 10 | module testbench(); 11 | reg [3:0]d; 12 | wire [1:0]y; 13 | wire v; 14 | pencoder p1(d,y,v); 15 | initial 16 | begin 17 | d=4'd0; 18 | #10 d=4'd1; 19 | #10 d=4'd2; 20 | #10 d=4'd3; 21 | #10 d=4'd4; 22 | #10 d=4'd5; 23 | #10 d=4'd6; 24 | #10 d=4'd7; 25 | #10 d=4'd8; 26 | #10 d=4'd9; 27 | #10 d=4'd10; 28 | #10 d=4'd11; 29 | #10 d=4'd12; 30 | #10 d=4'd13; 31 | #10 d=4'd14; 32 | #10 d=4'd15; 33 | #10 $finish; 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /pipo.v: -------------------------------------------------------------------------------- 1 | module dff(d,clk,q); 2 | input d,clk; 3 | output q; 4 | reg q=0; 5 | always @ (posedge clk) 6 | begin 7 | q<=d; 8 | end 9 | endmodule 10 | module pipo(d, clk, q); 11 | input [3:0]d; 12 | input clk; 13 | output [3:0]q; 14 | dff a(d[3], clk, q[3]); 15 | dff b(d[2], clk, q[2]); 16 | dff c(d[1], clk, q[1]); 17 | dff d(d[0], clk, q[0]); 18 | endmodule 19 | module testbench(); 20 | reg [3:0]d; 21 | reg clk; 22 | wire [3:0]q; 23 | pipo a(d, clk, q); 24 | initial 25 | begin 26 | $monitor($time,"d=%b,clk=%b,q=%b",d,clk,q); 27 | end 28 | initial 29 | begin 30 | clk=1'b0; 31 | forever #5 clk=~clk; 32 | end 33 | initial 34 | begin 35 | d=4'b1001; 36 | #10 d=4'b1011; 37 | #10 d=4’b1111; 38 | #40 $finish; 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /piso.v: -------------------------------------------------------------------------------- 1 | module sl(a, b, sl ,q); 2 | input a,b,sl; 3 | output q; 4 | assign q=(~sl&b)|(sl&a); 5 | endmodule 6 | module dff(d,clk,q); 7 | input d,clk; 8 | output q; 9 | reg q=0; 10 | always @ (posedge clk) 11 | begin 12 | q<=d; 13 | end 14 | endmodule 15 | 16 | module piso(d, clk, sl, q); 17 | input [3:0]d; 18 | input clk,sl; 19 | output q; 20 | wire q1,q2,q3,d1,d2,d3; 21 | dff a(d[3],clk,q1); 22 | sl a1(q1,d[2],sl,d1); 23 | dff b(d1,clk,q2); 24 | sl b1(q2,d[1],sl,d2); 25 | dff c(d2,clk,q3); 26 | sl c1(q3,d[0],sl,d3); 27 | dff d(d3,clk,q); 28 | endmodule 29 | 30 | module testbench(); 31 | reg [3:0]d; 32 | reg clk,sl; 33 | wire q; 34 | piso d1(d, clk, sl, q); 35 | initial 36 | begin 37 | clk=1'b0; 38 | forever #5 clk=~clk; 39 | end 40 | initial 41 | begin 42 | sl=0;d=4'b1011; 43 | #10 sl=1; 44 | #10 sl=1; 45 | #10 sl=1; 46 | #10 sl=0;d=4'b0000; 47 | #100 $finish; 48 | end 49 | endmodule 50 | -------------------------------------------------------------------------------- /sipo.v: -------------------------------------------------------------------------------- 1 | module dff(d,clk,q); 2 | input d,clk; 3 | output q; 4 | reg q=0; 5 | always @ (posedge clk) 6 | begin 7 | q<=d; 8 | end 9 | endmodule 10 | 11 | module sipo(d, clk, q); 12 | input d,clk; 13 | output [3:0]q; 14 | dff aa(d, clk, q[3]); 15 | dff bb(q[3], clk, q[2]); 16 | dff cc(q[2], clk, q[1]); 17 | dff dd(q[1], clk, q[0]); 18 | endmodule 19 | 20 | module testbench(); 21 | reg d,clk; 22 | wire [3:0]q; 23 | sipo a(d, clk, q); 24 | initial 25 | begin 26 | $monitor($time,"d=%b,clk=%b,q=%b",d,clk,q); 27 | end 28 | initial 29 | begin 30 | clk=1'b0; 31 | forever #5 clk=~clk; 32 | end 33 | initial 34 | begin 35 | d=1; 36 | #10 d=0; 37 | #10 d=1; 38 | #10 d=1; 39 | #40 $finish; 40 | end 41 | endmodule -------------------------------------------------------------------------------- /siso.v: -------------------------------------------------------------------------------- 1 | module dff(d,clk,q); 2 | input d,clk; 3 | output q; 4 | reg q=0; 5 | always @ (posedge clk) 6 | begin 7 | q<=d; 8 | end 9 | endmodule 10 | 11 | module siso(d, clk, q); 12 | input d,clk; 13 | output q; 14 | wire q1,q2,q3; 15 | dff a(d, clk, q1); 16 | dff b(q1, clk, q2); 17 | dff c(q2, clk, q3); 18 | dff d1(q3, clk, q); 19 | endmodule 20 | 21 | module testbench(); 22 | reg d,clk; 23 | wire q; 24 | siso a(d, clk, q); 25 | initial 26 | begin 27 | $monitor($time,"d=%b,clk=%b,q=%b",d,clk,q); 28 | end 29 | initial 30 | begin 31 | clk=1'b0; 32 | forever #5 clk=~clk; 33 | end 34 | initial 35 | begin 36 | d=1; 37 | #10 d=0; 38 | #10 d=1; 39 | #10 d=1; 40 | #40 $finish; 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /xor_gate.v: -------------------------------------------------------------------------------- 1 | module xor_gate(a,b,y); 2 | input a,b; 3 | output y; 4 | assign y=a^b; 5 | endmodule 6 | 7 | module testbench(); 8 | reg a,b; 9 | wire y; 10 | xor_gate sa(a,b,y); 11 | initial 12 | begin 13 | a=0; b=0; 14 | #5 a=0; b=1; 15 | #5 a=1; b=0; 16 | #5 a=1; b=1; 17 | #5 $finish; 18 | end 19 | endmodule --------------------------------------------------------------------------------