├── .gitattributes ├── .gitignore ├── CtrlCkt.v ├── D_FF.v ├── FIFO.v ├── README.md ├── buffer.v ├── cacheModule.v ├── comparator.v ├── dataArray.v ├── dataBlock.v ├── dataByte.v ├── dataCache.v ├── decoder2to4.v ├── decoder3to8.v ├── decoder5to32.v ├── encoder4to2.v ├── fourWaySACache.v ├── missRegister.v ├── mux2to1_256b.v ├── mux2to1_2b.v ├── mux2to1_32b.v ├── mux2to1_8b.v ├── mux32to1_8b.v ├── mux4to1_256b.v ├── mux8to1_1b.v ├── mux8to1_24b.v ├── mux8to1_256b.v ├── mux8to1_2b.v ├── priorityArray.v ├── priorityBlock.v ├── priorityEncoder_4x2.v ├── tagArray.v ├── tagBlock.v ├── testbench.v ├── updatePriority.v ├── vaildArray.v └── validityEncoder.v /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | *.sln merge=union 7 | *.csproj merge=union 8 | *.vbproj merge=union 9 | *.fsproj merge=union 10 | *.dbproj merge=union 11 | 12 | # Standard to msysgit 13 | *.doc diff=astextplain 14 | *.DOC diff=astextplain 15 | *.docx diff=astextplain 16 | *.DOCX diff=astextplain 17 | *.dot diff=astextplain 18 | *.DOT diff=astextplain 19 | *.pdf diff=astextplain 20 | *.PDF diff=astextplain 21 | *.rtf diff=astextplain 22 | *.RTF diff=astextplain 23 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # ========================= 18 | # Operating System Files 19 | # ========================= 20 | 21 | # OSX 22 | # ========================= 23 | 24 | .DS_Store 25 | .AppleDouble 26 | .LSOverride 27 | 28 | # Icon must end with two \r 29 | Icon 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear on external disk 35 | .Spotlight-V100 36 | .Trashes 37 | 38 | # Directories potentially created on remote AFP share 39 | .AppleDB 40 | .AppleDesktop 41 | Network Trash Folder 42 | Temporary Items 43 | .apdisk 44 | -------------------------------------------------------------------------------- /CtrlCkt.v: -------------------------------------------------------------------------------- 1 | module CtrlCkt( input clk, input reset, input write, input hit, output reg replace,output reg finalWrite,output reg finalRead,output reg bufferWrite,output reg sel); 2 | reg [3:0] state,next_state; 3 | 4 | always @ (negedge clk or reset) 5 | begin 6 | if(reset==0) state=next_state; 7 | else begin state=0; next_state=0; end 8 | end 9 | 10 | always @ (state or reset) 11 | begin 12 | if(reset==0) 13 | case(state) 14 | 0:begin 15 | replace=0; 16 | finalWrite=0;bufferWrite=0; 17 | sel=0; 18 | finalRead=0; 19 | if(hit && ~write) next_state=1; //read hit 20 | else if(hit && write) next_state=3; //write hit 21 | else next_state=2; 22 | end 23 | 1:begin 24 | replace=0; 25 | finalWrite=0; 26 | if(write) 27 | bufferWrite=1; 28 | else 29 | bufferWrite=0; 30 | sel=0; 31 | finalRead=1; 32 | next_state=0; 33 | end 34 | 2:begin 35 | replace=1; 36 | finalWrite=write;bufferWrite=0; 37 | sel=0; 38 | finalRead=0; 39 | if(write) next_state=3; //write miss 40 | else next_state=1; //read miss 41 | end 42 | 3:begin 43 | replace=0; 44 | finalWrite=1;bufferWrite=0; 45 | sel=1; 46 | finalRead=1; 47 | next_state=1; 48 | end 49 | endcase 50 | end 51 | endmodule -------------------------------------------------------------------------------- /D_FF.v: -------------------------------------------------------------------------------- 1 | module D_FF(input clk, input reset, input write, input d, output reg q); 2 | always @(negedge clk) 3 | if(reset) q=0; 4 | else 5 | if(write) q=d; 6 | endmodule -------------------------------------------------------------------------------- /FIFO.v: -------------------------------------------------------------------------------- 1 | module FIFO(input clk,input reset,input replace,input [2:0] index, input [3:0] validBits, output [1:0] finalWay); 2 | 3 | wire [7:0] decOut; 4 | decoder3to8 ind(index,decOut); 5 | 6 | wire [1:0] priority0,priority1,priority2,priority3, 7 | priorityOut00,priorityOut01,priorityOut02,priorityOut03,priorityOut04,priorityOut05,priorityOut06,priorityOut07, 8 | priorityOut10,priorityOut11,priorityOut12,priorityOut13,priorityOut14,priorityOut15,priorityOut16,priorityOut17, 9 | priorityOut20,priorityOut21,priorityOut22,priorityOut23,priorityOut24,priorityOut25,priorityOut26,priorityOut27, 10 | priorityOut30,priorityOut31,priorityOut32,priorityOut33,priorityOut34,priorityOut35,priorityOut36,priorityOut37; 11 | 12 | wire [7:0] we; 13 | assign we = decOut & {8{replace}}; 14 | priorityArray arr0(clk,reset,we,priority0,priorityOut00,priorityOut01,priorityOut02,priorityOut03,priorityOut04,priorityOut05,priorityOut06,priorityOut07); 15 | priorityArray arr1(clk,reset,we,priority1,priorityOut10,priorityOut11,priorityOut12,priorityOut13,priorityOut14,priorityOut15,priorityOut16,priorityOut17); 16 | priorityArray arr2(clk,reset,we,priority2,priorityOut20,priorityOut21,priorityOut22,priorityOut23,priorityOut24,priorityOut25,priorityOut26,priorityOut27); 17 | priorityArray arr3(clk,reset,we,priority3,priorityOut30,priorityOut31,priorityOut32,priorityOut33,priorityOut34,priorityOut35,priorityOut36,priorityOut37); 18 | 19 | wire [1:0] muxOut0,muxOut1,muxOut2,muxOut3; 20 | mux8to1_2b m0(priorityOut00,priorityOut01,priorityOut02,priorityOut03,priorityOut04,priorityOut05,priorityOut06,priorityOut07,index,muxOut0); 21 | mux8to1_2b m1(priorityOut10,priorityOut11,priorityOut12,priorityOut13,priorityOut14,priorityOut15,priorityOut16,priorityOut17,index,muxOut1); 22 | mux8to1_2b m2(priorityOut20,priorityOut21,priorityOut22,priorityOut23,priorityOut24,priorityOut25,priorityOut26,priorityOut27,index,muxOut2); 23 | mux8to1_2b m3(priorityOut30,priorityOut31,priorityOut32,priorityOut33,priorityOut34,priorityOut35,priorityOut36,priorityOut37,index,muxOut3); 24 | wire validReplace; // it is 0 when replacement is based on atleast 1 invalid cache block 25 | wire [1:0] validWayOut,priorityWayOut; 26 | validityEncoder decision(validBits,validReplace,validWayOut); 27 | priorityEncoder_4x2 encode({muxOut3[1]|muxOut3[0],muxOut2[1]|muxOut2[0],muxOut1[1]|muxOut1[0],muxOut0[1]|muxOut0[0]},priorityWayOut); 28 | 29 | mux2to1_2b mx2b00(validWayOut,priorityWayOut,validReplace,finalWay); 30 | updatePriority update(finalWay,muxOut0,muxOut1,muxOut2,muxOut3,priority0,priority1,priority2,priority3); 31 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 4-way-set-associative-phased-cache-verilog 2 | =================================== 3 | 4 | Verilog implementation of a 4-way Set associative phased cache with a write buffer (write) policy and FIFO replacement policy 5 | 6 | A multicycle datapath design has been used for the implementing the above mentioned cache. 7 | There are 4 states in total (0,1,2 and 3) and transition between the states is done in the CtrlCkt module. 8 | 9 | State 0 - tag comparison to determine cache hit or cache miss 10 | 11 | State 1 - Read from the cache and/or write to the write buffer 12 | 13 | State 2 - Fetch approprite block of data from memeory to the cache (Replace if needed) 14 | 15 | State 3 - Write a byte to the cache (from the CPU) 16 | 17 | 18 | Read hit takes 2 cycles (0-1) 19 | 20 | Read miss takes 3 cycles (0-2-1) 21 | 22 | Write hit takes 3 cycles (0-3-1) 23 | 24 | Write miss takes 4 cycles (0-2-3-1) 25 | 26 | One extra cycle is resulting in each of the above hit/miss conditions because of a requirement of a minimum of 2 cycles for a phased cache. Phased cache poses the condition that read should happen only if and after cache hit/miss has been determined. 27 | -------------------------------------------------------------------------------- /buffer.v: -------------------------------------------------------------------------------- 1 | module buffer(input clock, input reset, input write_en, input [26:0] addr_in, input [255:0] data_in); 2 | reg [283:0] reg_array [0:3]; 3 | reg [1:0] write_ptr; 4 | always @(posedge clock,reset) 5 | begin 6 | if(reset) 7 | write_ptr=2'b00; 8 | else 9 | begin 10 | if (write_en) 11 | begin 12 | reg_array[write_ptr] = {data_in, addr_in, 1'b1}; 13 | if(write_ptr==2'b11) 14 | write_ptr = 2'b00; 15 | else //BUFFER REACHED LAST BLOCK 16 | write_ptr=write_ptr+1; 17 | end 18 | end 19 | end 20 | endmodule -------------------------------------------------------------------------------- /cacheModule.v: -------------------------------------------------------------------------------- 1 | module cacheModule(input clk, input reset, input [31:0] pa, input writeORread, input [7:0] inByte, input [255:0] dataBlock, output [7:0] cacheOutput); 2 | 3 | wire hit,replace,finalWrite, finalRead, bufferWrite,dataSel; 4 | wire [1:0] way,way0,way1; 5 | wire [3:0] validBits; 6 | wire [255:0] writeBlock,bufferBlock; 7 | CtrlCkt controlSignal(clk, reset, writeORread, hit, replace, finalWrite, finalRead, bufferWrite, dataSel); 8 | fourWaySACache tagComp(clk, reset, way, replace | finalWrite, pa[31:8], pa[7:5], hit, way0, validBits); 9 | mux2to1_256b mx256btm0(dataBlock,{32{inByte}}, dataSel,writeBlock); 10 | dataCache dataOp(clk, reset,way,replace | finalWrite, finalRead,dataSel,writeBlock,pa[7:5],pa[4:0],cacheOutput, bufferBlock); 11 | buffer buffCac0(clk, reset,bufferWrite,pa[31:5],bufferBlock); 12 | FIFO fifoReplacement0(clk,reset,replace,pa[7:5], validBits, way1); 13 | mux2to1_2b mx2btm0(way1, way0, finalRead, way); 14 | endmodule -------------------------------------------------------------------------------- /comparator.v: -------------------------------------------------------------------------------- 1 | module comparator(input [23:0] in1, input [23:0] in2,output reg compOut); 2 | always@(in1,in2) 3 | if(in1==in2) begin compOut=1'b1;end 4 | else begin compOut=1'b0;end 5 | endmodule -------------------------------------------------------------------------------- /dataArray.v: -------------------------------------------------------------------------------- 1 | module dataArray(input clk, input reset, input [31:0] we0, input [31:0] we1, input [31:0] we2, input [31:0] we3, input [31:0] we4, input [31:0] we5, input [31:0] we6, input [31:0] we7, input [255:0] block, output [255:0] blockOut0, output [255:0] blockOut1, output [255:0] blockOut2, output [255:0] blockOut3, output [255:0] blockOut4, output [255:0] blockOut5, output [255:0] blockOut6, output [255:0] blockOut7); 2 | dataBlock block0(clk,reset,we0,block,blockOut0); 3 | dataBlock block1(clk,reset,we1,block,blockOut1); 4 | dataBlock block2(clk,reset,we2,block,blockOut2); 5 | dataBlock block3(clk,reset,we3,block,blockOut3); 6 | dataBlock block4(clk,reset,we4,block,blockOut4); 7 | dataBlock block5(clk,reset,we5,block,blockOut5); 8 | dataBlock block6(clk,reset,we6,block,blockOut6); 9 | dataBlock block7(clk,reset,we7,block,blockOut7); 10 | endmodule -------------------------------------------------------------------------------- /dataBlock.v: -------------------------------------------------------------------------------- 1 | module dataBlock(input clk, input reset, input [31:0] write, input [255:0] block,output [255:0] blockData); 2 | dataByte data00(clk,reset,write[0],block[7:0],blockData[7:0]); 3 | dataByte data01(clk,reset,write[1],block[15:8],blockData[15:8]); 4 | dataByte data02(clk,reset,write[2],block[23:16],blockData[23:16]); 5 | dataByte data03(clk,reset,write[3],block[31:24],blockData[31:24]); 6 | dataByte data04(clk,reset,write[4],block[39:32],blockData[39:32]); 7 | dataByte data05(clk,reset,write[5],block[47:40],blockData[47:40]); 8 | dataByte data06(clk,reset,write[6],block[55:48],blockData[55:48]); 9 | dataByte data07(clk,reset,write[7],block[63:56],blockData[63:56]); 10 | dataByte data08(clk,reset,write[8],block[71:64],blockData[71:64]); 11 | dataByte data09(clk,reset,write[9],block[79:72],blockData[79:72]); 12 | dataByte data10(clk,reset,write[10],block[87:80],blockData[87:80]); 13 | dataByte data11(clk,reset,write[11],block[95:88],blockData[95:88]); 14 | dataByte data12(clk,reset,write[12],block[103:96],blockData[103:96]); 15 | dataByte data13(clk,reset,write[13],block[111:104],blockData[111:104]); 16 | dataByte data14(clk,reset,write[14],block[119:112],blockData[119:112]); 17 | dataByte data15(clk,reset,write[15],block[127:120],blockData[127:120]); 18 | dataByte data16(clk,reset,write[16],block[135:128],blockData[135:128]); 19 | dataByte data17(clk,reset,write[17],block[143:136],blockData[143:136]); 20 | dataByte data18(clk,reset,write[18],block[151:144],blockData[151:144]); 21 | dataByte data19(clk,reset,write[19],block[159:152],blockData[159:152]); 22 | dataByte data20(clk,reset,write[20],block[167:160],blockData[167:160]); 23 | dataByte data21(clk,reset,write[21],block[175:168],blockData[175:168]); 24 | dataByte data22(clk,reset,write[22],block[183:176],blockData[183:176]); 25 | dataByte data23(clk,reset,write[23],block[191:184],blockData[191:184]); 26 | dataByte data24(clk,reset,write[24],block[199:192],blockData[199:192]); 27 | dataByte data25(clk,reset,write[25],block[207:200],blockData[207:200]); 28 | dataByte data26(clk,reset,write[26],block[215:208],blockData[215:208]); 29 | dataByte data27(clk,reset,write[27],block[223:216],blockData[223:216]); 30 | dataByte data28(clk,reset,write[28],block[231:224],blockData[231:224]); 31 | dataByte data29(clk,reset,write[29],block[239:232],blockData[239:232]); 32 | dataByte data30(clk,reset,write[30],block[247:240],blockData[247:240]); 33 | dataByte data31(clk,reset,write[31],block[255:248],blockData[255:248]); 34 | endmodule -------------------------------------------------------------------------------- /dataByte.v: -------------------------------------------------------------------------------- 1 | module dataByte(input clk, input reset, input write, input [7:0] data,output [7:0] byteData); 2 | D_FF d00(clk, reset,write,data[0],byteData[0]); 3 | D_FF d01(clk, reset,write,data[1],byteData[1]); 4 | D_FF d02(clk, reset,write,data[2],byteData[2]); 5 | D_FF d03(clk, reset,write,data[3],byteData[3]); 6 | D_FF d04(clk, reset,write,data[4],byteData[4]); 7 | D_FF d05(clk, reset,write,data[5],byteData[5]); 8 | D_FF d06(clk, reset,write,data[6],byteData[6]); 9 | D_FF d07(clk, reset,write,data[7],byteData[7]); 10 | endmodule -------------------------------------------------------------------------------- /dataCache.v: -------------------------------------------------------------------------------- 1 | module dataCache(input clk, input reset, input [1:0] way, input write, input dataRead, input dataSel, input [255:0] block, input [2:0] index,input [4:0] offset,output [7:0] bytedata, output [255:0] selBlock); 2 | wire [3:0] wyOt; 3 | wire [7:0] dcOt,wEn0,wEn1,wEn2,wEn3,muxByte; 4 | wire [31:0] muxWr,decOut; 5 | wire [255:0] muxblockOut0,muxblockOut1,muxblockOut2,muxblockOut3, 6 | blockOut00,blockOut01,blockOut02,blockOut03,blockOut04,blockOut05,blockOut06,blockOut07, 7 | blockOut10,blockOut11,blockOut12,blockOut13,blockOut14,blockOut15,blockOut16,blockOut17, 8 | blockOut20,blockOut21,blockOut22,blockOut23,blockOut24,blockOut25,blockOut26,blockOut27, 9 | blockOut30,blockOut31,blockOut32,blockOut33,blockOut34,blockOut35,blockOut36,blockOut37; 10 | 11 | decoder3to8 indDc(index,dcOt); 12 | decoder2to4 wyDc(way,wyOt); 13 | and nd00(wEn0[0],dcOt[0],wyOt[0]&write);and nd01(wEn0[1],dcOt[1],wyOt[0]&write);and nd02(wEn0[2],dcOt[2],wyOt[0]&write);and nd03(wEn0[3],dcOt[3],wyOt[0]&write); 14 | and nd04(wEn0[4],dcOt[4],wyOt[0]&write);and nd05(wEn0[5],dcOt[5],wyOt[0]&write);and nd06(wEn0[6],dcOt[6],wyOt[0]&write);and nd07(wEn0[7],dcOt[7],wyOt[0]&write); 15 | and nd10(wEn1[0],dcOt[0],wyOt[1]&write);and nd11(wEn1[1],dcOt[1],wyOt[1]&write);and nd12(wEn1[2],dcOt[2],wyOt[1]&write);and nd13(wEn1[3],dcOt[3],wyOt[1]&write); 16 | and nd14(wEn1[4],dcOt[4],wyOt[1]&write);and nd15(wEn1[5],dcOt[5],wyOt[1]&write);and nd16(wEn1[6],dcOt[6],wyOt[1]&write);and nd17(wEn1[7],dcOt[7],wyOt[1]&write); 17 | and nd20(wEn2[0],dcOt[0],wyOt[2]&write);and nd21(wEn2[1],dcOt[1],wyOt[2]&write);and nd22(wEn2[2],dcOt[2],wyOt[2]&write);and nd23(wEn2[3],dcOt[3],wyOt[2]&write); 18 | and nd24(wEn2[4],dcOt[4],wyOt[2]&write);and nd25(wEn2[5],dcOt[5],wyOt[2]&write);and nd26(wEn2[6],dcOt[6],wyOt[2]&write);and nd27(wEn2[7],dcOt[7],wyOt[2]&write); 19 | and nd30(wEn3[0],dcOt[0],wyOt[3]&write);and nd31(wEn3[1],dcOt[1],wyOt[3]&write);and nd32(wEn3[2],dcOt[2],wyOt[3]&write);and nd33(wEn3[3],dcOt[3],wyOt[3]&write); 20 | and nd34(wEn3[4],dcOt[4],wyOt[3]&write);and nd35(wEn3[5],dcOt[5],wyOt[3]&write);and nd36(wEn3[6],dcOt[6],wyOt[3]&write);and nd37(wEn3[7],dcOt[7],wyOt[3]&write); 21 | decoder5to32 offSetDc(offset,decOut); 22 | mux2to1_32b mx32b0({32{1'b1}},decOut, dataSel, muxWr); 23 | dataArray dtWy0(clk,reset,{32{wEn0[0]}} & muxWr,{32{wEn0[1]}} & muxWr,{32{wEn0[2]}} & muxWr,{32{wEn0[3]}} & muxWr,{32{wEn0[4]}} & muxWr,{32{wEn0[5]}} & muxWr,{32{wEn0[6]}} & muxWr,{32{wEn0[7]}} & muxWr,block,blockOut00,blockOut01,blockOut02,blockOut03,blockOut04,blockOut05,blockOut06,blockOut07); 24 | dataArray dtWy1(clk,reset,{32{wEn1[0]}} & muxWr,{32{wEn1[1]}} & muxWr,{32{wEn1[2]}} & muxWr,{32{wEn1[3]}} & muxWr,{32{wEn1[4]}} & muxWr,{32{wEn1[5]}} & muxWr,{32{wEn1[6]}} & muxWr,{32{wEn1[7]}} & muxWr,block,blockOut10,blockOut11,blockOut12,blockOut13,blockOut14,blockOut15,blockOut16,blockOut17); 25 | dataArray dtWy2(clk,reset,{32{wEn2[0]}} & muxWr,{32{wEn2[1]}} & muxWr,{32{wEn2[2]}} & muxWr,{32{wEn2[3]}} & muxWr,{32{wEn2[4]}} & muxWr,{32{wEn2[5]}} & muxWr,{32{wEn2[6]}} & muxWr,{32{wEn2[7]}} & muxWr,block,blockOut20,blockOut21,blockOut22,blockOut23,blockOut24,blockOut25,blockOut26,blockOut27); 26 | dataArray dtWy3(clk,reset,{32{wEn3[0]}} & muxWr,{32{wEn3[1]}} & muxWr,{32{wEn3[2]}} & muxWr,{32{wEn3[3]}} & muxWr,{32{wEn3[4]}} & muxWr,{32{wEn3[5]}} & muxWr,{32{wEn3[6]}} & muxWr,{32{wEn3[7]}} & muxWr,block,blockOut30,blockOut31,blockOut32,blockOut33,blockOut34,blockOut35,blockOut36,blockOut37); 27 | mux8to1_256b mx256b0(blockOut00,blockOut01,blockOut02,blockOut03,blockOut04,blockOut05,blockOut06,blockOut07,index,muxblockOut0); 28 | mux8to1_256b mx256b1(blockOut10,blockOut11,blockOut12,blockOut13,blockOut14,blockOut15,blockOut16,blockOut17,index,muxblockOut1); 29 | mux8to1_256b mx256b2(blockOut20,blockOut21,blockOut22,blockOut23,blockOut24,blockOut25,blockOut26,blockOut27,index,muxblockOut2); 30 | mux8to1_256b mx256b3(blockOut30,blockOut31,blockOut32,blockOut33,blockOut34,blockOut35,blockOut36,blockOut37,index,muxblockOut3); 31 | mux4to1_256b mx4to1b256(muxblockOut0,muxblockOut1,muxblockOut2,muxblockOut3,way,selBlock); 32 | mux32to1_8b mx32b00(selBlock[7:0],selBlock[15:8],selBlock[23:16],selBlock[31:24],selBlock[39:32],selBlock[47:40],selBlock[55:48],selBlock[63:56],selBlock[71:64],selBlock[79:72],selBlock[87:80],selBlock[95:88],selBlock[103:96],selBlock[111:104],selBlock[119:112],selBlock[127:120],selBlock[135:128],selBlock[143:136],selBlock[151:144],selBlock[159:152],selBlock[167:160],selBlock[175:168],selBlock[183:176],selBlock[191:184],selBlock[199:192],selBlock[207:200],selBlock[215:208],selBlock[223:216],selBlock[231:224],selBlock[239:232],selBlock[247:240],selBlock[255:248],offset,muxByte); 33 | mux2to1_8b mx8b(8'd0,muxByte,dataRead,bytedata); 34 | endmodule -------------------------------------------------------------------------------- /decoder2to4.v: -------------------------------------------------------------------------------- 1 | module decoder2to4(input [1:0] in,output reg [3:0] wayOut); 2 | always@(in) 3 | case(in) 4 | 2'b00: wayOut=4'b0001; 5 | 2'b01: wayOut=4'b0010; 6 | 2'b10: wayOut=4'b0100; 7 | 2'b11: wayOut=4'b1000; 8 | endcase 9 | endmodule -------------------------------------------------------------------------------- /decoder3to8.v: -------------------------------------------------------------------------------- 1 | module decoder3to8(input [2:0] in,output reg [7:0] decOut); 2 | always@(in) 3 | case(in) 4 | 3'b000: decOut=8'b00000001; 5 | 3'b001: decOut=8'b00000010; 6 | 3'b010: decOut=8'b00000100; 7 | 3'b011: decOut=8'b00001000; 8 | 3'b100: decOut=8'b00010000; 9 | 3'b101: decOut=8'b00100000; 10 | 3'b110: decOut=8'b01000000; 11 | 3'b111: decOut=8'b10000000; 12 | endcase 13 | endmodule -------------------------------------------------------------------------------- /decoder5to32.v: -------------------------------------------------------------------------------- 1 | module decoder5to32(input [4:0] in,output reg [31:0] decoder_out); 2 | always @ (in) 3 | case (in) 4 | 5'h00 : decoder_out = 32'h00000001; 5 | 5'h01 : decoder_out = 32'h00000002; 6 | 5'h02 : decoder_out = 32'h00000004; 7 | 5'h03 : decoder_out = 32'h00000008; 8 | 5'h04 : decoder_out = 32'h00000010; 9 | 5'h05 : decoder_out = 32'h00000020; 10 | 5'h06 : decoder_out = 32'h00000040; 11 | 5'h07 : decoder_out = 32'h00000080; 12 | 5'h08 : decoder_out = 32'h00000100; 13 | 5'h09 : decoder_out = 32'h00000200; 14 | 5'h0A : decoder_out = 32'h00000400; 15 | 5'h0B : decoder_out = 32'h00000800; 16 | 5'h0C : decoder_out = 32'h00001000; 17 | 5'h0D : decoder_out = 32'h00002000; 18 | 5'h0E : decoder_out = 32'h00004000; 19 | 5'h0F : decoder_out = 32'h00008000; 20 | 5'h10 : decoder_out = 32'h00010000; 21 | 5'h11 : decoder_out = 32'h00020000; 22 | 5'h12 : decoder_out = 32'h00040000; 23 | 5'h13 : decoder_out = 32'h00080000; 24 | 5'h14 : decoder_out = 32'h00100000; 25 | 5'h15 : decoder_out = 32'h00200000; 26 | 5'h16 : decoder_out = 32'h00400000; 27 | 5'h17 : decoder_out = 32'h00800000; 28 | 5'h18 : decoder_out = 32'h01000000; 29 | 5'h19 : decoder_out = 32'h02000000; 30 | 5'h1A : decoder_out = 32'h04000000; 31 | 5'h1B : decoder_out = 32'h08000000; 32 | 5'h1C : decoder_out = 32'h10000000; 33 | 5'h1D : decoder_out = 32'h20000000; 34 | 5'h1E : decoder_out = 32'h40000000; 35 | 5'h1F : decoder_out = 32'h80000000; 36 | endcase 37 | endmodule -------------------------------------------------------------------------------- /encoder4to2.v: -------------------------------------------------------------------------------- 1 | module encoder4to2(input [3:0] in,output reg [1:0] out); 2 | always @ (in) 3 | begin 4 | if(in[0]) out=2'b00; 5 | else if(in[1]) out=2'b01; 6 | else if(in[2]) out=2'b10; 7 | else out=2'b11; 8 | end 9 | endmodule -------------------------------------------------------------------------------- /fourWaySACache.v: -------------------------------------------------------------------------------- 1 | module fourWaySACache(input clk, input reset, input [1:0] way, input replace, input [23:0] tag, input [2:0] index, output iHit, output [1:0] wayOut, output [3:0] validComp); 2 | wire hit,set0,set1,cmpOut0,cmpOut1,cmpOut2,cmpOut3, 3 | validOut00,validOut01,validOut02,validOut03,validOut04,validOut05,validOut06,validOut07, 4 | validOut10,validOut11,validOut12,validOut13,validOut14,validOut15,validOut16,validOut17, 5 | validOut20,validOut21,validOut22,validOut23,validOut24,validOut25,validOut26,validOut27, 6 | validOut30,validOut31,validOut32,validOut33,validOut34,validOut35,validOut36,validOut37; 7 | 8 | wire [3:0] wyOt; 9 | wire [7:0] dcOt, wrEn0,wrEn1,wrEn2,wrEn3; 10 | 11 | wire [23:0] tagComp0,tagComp1,tagComp2,tagComp3, 12 | tagOut00,tagOut01,tagOut02,tagOut03,tagOut04,tagOut05,tagOut06,tagOut07, 13 | tagOut10,tagOut11,tagOut12,tagOut13,tagOut14,tagOut15,tagOut16,tagOut17, 14 | tagOut20,tagOut21,tagOut22,tagOut23,tagOut24,tagOut25,tagOut26,tagOut27, 15 | tagOut30,tagOut31,tagOut32,tagOut33,tagOut34,tagOut35,tagOut36,tagOut37; 16 | 17 | decoder3to8 ind(index, dcOt); 18 | decoder2to4 wydc(way, wyOt); 19 | and an00(wrEn0[0],dcOt[0],wyOt[0]&replace);and an01(wrEn0[1],dcOt[1],wyOt[0]&replace);and an02(wrEn0[2],dcOt[2],wyOt[0]&replace);and an03(wrEn0[3],dcOt[3],wyOt[0]&replace); 20 | and an04(wrEn0[4],dcOt[4],wyOt[0]&replace);and an05(wrEn0[5],dcOt[5],wyOt[0]&replace);and an06(wrEn0[6],dcOt[6],wyOt[0]&replace);and an07(wrEn0[7],dcOt[7],wyOt[0]&replace); 21 | and an10(wrEn1[0],dcOt[0],wyOt[1]&replace);and an11(wrEn1[1],dcOt[1],wyOt[1]&replace);and an12(wrEn1[2],dcOt[2],wyOt[1]&replace);and an13(wrEn1[3],dcOt[3],wyOt[1]&replace); 22 | and an14(wrEn1[4],dcOt[4],wyOt[1]&replace);and an15(wrEn1[5],dcOt[5],wyOt[1]&replace);and an16(wrEn1[6],dcOt[6],wyOt[1]&replace);and an17(wrEn1[7],dcOt[7],wyOt[1]&replace); 23 | and an20(wrEn2[0],dcOt[0],wyOt[2]&replace);and an21(wrEn2[1],dcOt[1],wyOt[2]&replace);and an22(wrEn2[2],dcOt[2],wyOt[2]&replace);and an23(wrEn2[3],dcOt[3],wyOt[2]&replace); 24 | and an24(wrEn2[4],dcOt[4],wyOt[2]&replace);and an25(wrEn2[5],dcOt[5],wyOt[2]&replace);and an26(wrEn2[6],dcOt[6],wyOt[2]&replace);and an27(wrEn2[7],dcOt[7],wyOt[2]&replace); 25 | and an30(wrEn3[0],dcOt[0],wyOt[3]&replace);and an31(wrEn3[1],dcOt[1],wyOt[3]&replace);and an32(wrEn3[2],dcOt[2],wyOt[3]&replace);and an33(wrEn3[3],dcOt[3],wyOt[3]&replace); 26 | and an34(wrEn3[4],dcOt[4],wyOt[3]&replace);and an35(wrEn3[5],dcOt[5],wyOt[3]&replace);and an36(wrEn3[6],dcOt[6],wyOt[3]&replace);and an37(wrEn3[7],dcOt[7],wyOt[3]&replace); 27 | vaildArray vdAr0(clk,reset,wrEn0,1'b1,validOut00,validOut01,validOut02,validOut03,validOut04,validOut05,validOut06,validOut07); 28 | vaildArray vdAr1(clk,reset,wrEn1,1'b1,validOut10,validOut11,validOut12,validOut13,validOut14,validOut15,validOut16,validOut17); 29 | vaildArray vdAr2(clk,reset,wrEn2,1'b1,validOut20,validOut21,validOut22,validOut23,validOut24,validOut25,validOut26,validOut27); 30 | vaildArray vdAr3(clk,reset,wrEn3,1'b1,validOut30,validOut31,validOut32,validOut33,validOut34,validOut35,validOut36,validOut37); 31 | tagArray tgAr0(clk,reset,wrEn0,tag,tagOut00,tagOut01,tagOut02,tagOut03,tagOut04,tagOut05,tagOut06,tagOut07); 32 | tagArray tgAr1(clk,reset,wrEn1,tag,tagOut10,tagOut11,tagOut12,tagOut13,tagOut14,tagOut15,tagOut16,tagOut17); 33 | tagArray tgAr2(clk,reset,wrEn2,tag,tagOut20,tagOut21,tagOut22,tagOut23,tagOut24,tagOut25,tagOut26,tagOut27); 34 | tagArray tgAr3(clk,reset,wrEn3,tag,tagOut30,tagOut31,tagOut32,tagOut33,tagOut34,tagOut35,tagOut36,tagOut37); 35 | mux8to1_24b mx24b0(tagOut00,tagOut01,tagOut02,tagOut03,tagOut04,tagOut05,tagOut06,tagOut07,index,tagComp0); 36 | mux8to1_24b mx24b1(tagOut10,tagOut11,tagOut12,tagOut13,tagOut14,tagOut15,tagOut16,tagOut17,index,tagComp1); 37 | mux8to1_24b mx24b2(tagOut20,tagOut21,tagOut22,tagOut23,tagOut24,tagOut25,tagOut26,tagOut27,index,tagComp2); 38 | mux8to1_24b mx24b3(tagOut30,tagOut31,tagOut32,tagOut33,tagOut34,tagOut35,tagOut36,tagOut37,index,tagComp3); 39 | mux8to1_1b mx1b0(validOut00,validOut01,validOut02,validOut03,validOut04,validOut05,validOut06,validOut07,index,validComp[0]); 40 | mux8to1_1b mx1b1(validOut10,validOut11,validOut12,validOut13,validOut14,validOut15,validOut16,validOut17,index,validComp[1]); 41 | mux8to1_1b mx1b2(validOut20,validOut21,validOut22,validOut23,validOut24,validOut25,validOut26,validOut27,index,validComp[2]); 42 | mux8to1_1b mx1b3(validOut30,validOut31,validOut32,validOut33,validOut34,validOut35,validOut36,validOut37,index,validComp[3]); 43 | comparator cmp0(tag,tagComp0,cmpOut0); 44 | comparator cmp1(tag,tagComp1,cmpOut1); 45 | comparator cmp2(tag,tagComp2,cmpOut2); 46 | comparator cmp3(tag,tagComp3,cmpOut3); 47 | encoder4to2 encodeWay({{cmpOut3 & validComp[3]},{cmpOut2 & validComp[2]},{cmpOut1 & validComp[1]},{cmpOut0 & validComp[0]}}, wayOut); 48 | or in0(set0,cmpOut0 & validComp[0],cmpOut1 & validComp[1]); 49 | or in1(set1,cmpOut2 & validComp[2],cmpOut3 & validComp[3]); 50 | or fin(iHit, set0, set1); 51 | missRegister hitReg(reset,tag,index, iHit, hit); 52 | endmodule -------------------------------------------------------------------------------- /missRegister.v: -------------------------------------------------------------------------------- 1 | module missRegister(input reset,input [23:0] in1, input [2:0] in2, input miss, output reg out); 2 | always@(in1,in2,reset) 3 | begin 4 | if(reset) 5 | out=1'b0; 6 | else 7 | out=miss; 8 | end 9 | endmodule -------------------------------------------------------------------------------- /mux2to1_256b.v: -------------------------------------------------------------------------------- 1 | module mux2to1_256b(input [255:0] in1,input [255:0] in2, input sel,output reg [255:0] muxOut); 2 | always@(in1,in2,sel) 3 | case(sel) 4 | 1'b0: muxOut=in1; 5 | 1'b1: muxOut=in2; 6 | endcase 7 | endmodule -------------------------------------------------------------------------------- /mux2to1_2b.v: -------------------------------------------------------------------------------- 1 | module mux2to1_2b(input [1:0] in1,input [1:0] in2, input sel,output reg [1:0] muxOut); 2 | always@(in1,in2,sel) 3 | case(sel) 4 | 1'b0: muxOut=in1; 5 | 1'b1: muxOut=in2; 6 | endcase 7 | endmodule -------------------------------------------------------------------------------- /mux2to1_32b.v: -------------------------------------------------------------------------------- 1 | module mux2to1_32b(input [31:0] in1, input [31:0] in2, input sel, output reg [31:0] muxOut); 2 | always@(in1 or in2 or sel) 3 | case (sel) 4 | 1'b0: muxOut=in1; 5 | 1'b1: muxOut=in2; 6 | endcase 7 | endmodule -------------------------------------------------------------------------------- /mux2to1_8b.v: -------------------------------------------------------------------------------- 1 | module mux2to1_8b(input [7:0] zero, input [7:0] inpt, input dataRead, output reg [7:0] dataOut); 2 | always@(inpt or zero or dataRead) 3 | case (dataRead) 4 | 1'b0: dataOut=zero; 5 | 1'b1: dataOut=inpt; 6 | endcase 7 | endmodule -------------------------------------------------------------------------------- /mux32to1_8b.v: -------------------------------------------------------------------------------- 1 | module mux32to1_8b(input [7:0] in01,input [7:0] in02, input [7:0] in03, input [7:0] in04, input [7:0] in05,input [7:0] in06, input [7:0] in07, input [7:0] in08, 2 | input [7:0] in09,input [7:0] in10, input [7:0] in11, input [7:0] in12, input [7:0] in13,input [7:0] in14, input [7:0] in15, input [7:0] in16, 3 | input [7:0] in17,input [7:0] in18, input [7:0] in19, input [7:0] in20, input [7:0] in21,input [7:0] in22, input [7:0] in23, input [7:0] in24, 4 | input [7:0] in25,input [7:0] in26, input [7:0] in27, input [7:0] in28, input [7:0] in29,input [7:0] in30, input [7:0] in31, input [7:0] in32, 5 | input[4:0] sel,output reg [7:0] muxOut); 6 | always@(in01,in02,in03,in04,in05,in06,in07,in08,in09,in10,in11,in12,in13,in14,in15,in16,in17,in18,in19,in20,in21,in22,in23,in24,in25,in26,in27,in28,in29,in30,in31,in32,sel) 7 | case(sel) 8 | 5'b00000: muxOut=in01;5'b00001: muxOut=in02;5'b00010: muxOut=in03;5'b00011: muxOut=in04; 9 | 5'b00100: muxOut=in05;5'b00101: muxOut=in06;5'b00110: muxOut=in07;5'b00111: muxOut=in08; 10 | 5'b01000: muxOut=in09;5'b01001: muxOut=in10;5'b01010: muxOut=in11;5'b01011: muxOut=in12; 11 | 5'b01100: muxOut=in13;5'b01101: muxOut=in14;5'b01110: muxOut=in15;5'b01111: muxOut=in16; 12 | 5'b10000: muxOut=in17;5'b10001: muxOut=in18;5'b10010: muxOut=in19;5'b10011: muxOut=in20; 13 | 5'b10100: muxOut=in21;5'b10101: muxOut=in22;5'b10110: muxOut=in23;5'b10111: muxOut=in24; 14 | 5'b11000: muxOut=in25;5'b11001: muxOut=in26;5'b11010: muxOut=in27;5'b11011: muxOut=in28; 15 | 5'b11100: muxOut=in29;5'b11101: muxOut=in30;5'b11110: muxOut=in31;5'b11111: muxOut=in32; 16 | endcase 17 | endmodule -------------------------------------------------------------------------------- /mux4to1_256b.v: -------------------------------------------------------------------------------- 1 | module mux4to1_256b(input [255:0] in1,input [255:0] in2, input [255:0] in3, input [255:0] in4, input[1:0] sel,output reg[255:0] muxOut); 2 | always@(in1,in2,in3,in4,sel) 3 | case(sel) 4 | 2'b00: muxOut=in1; 5 | 2'b01: muxOut=in2; 6 | 2'b10: muxOut=in3; 7 | 2'b11: muxOut=in4; 8 | endcase 9 | endmodule -------------------------------------------------------------------------------- /mux8to1_1b.v: -------------------------------------------------------------------------------- 1 | module mux8to1_1b(input in1, input in2, input in3, input in4, input in5, input in6, input in7, input in8,input[2:0] sel,output reg validOut); 2 | always@(in1,in2,in3,in4,in5,in6,in7,in8,sel) 3 | case(sel) 4 | 3'b000: validOut=in1; 5 | 3'b001: validOut=in2; 6 | 3'b010: validOut=in3; 7 | 3'b011: validOut=in4; 8 | 3'b100: validOut=in5; 9 | 3'b101: validOut=in6; 10 | 3'b110: validOut=in7; 11 | 3'b111: validOut=in8; 12 | endcase 13 | endmodule -------------------------------------------------------------------------------- /mux8to1_24b.v: -------------------------------------------------------------------------------- 1 | module mux8to1_24b(input [23:0] in1,input [23:0] in2, input [23:0] in3, input [23:0] in4, input [23:0] in5,input [23:0] in6, input [23:0] in7, input [23:0] in8, input[2:0] sel,output reg[23:0] tagOut); 2 | always@(in1,in2,in3,in4,in5,in6,in7,in8,sel) 3 | case(sel) 4 | 3'b000: tagOut=in1; 5 | 3'b001: tagOut=in2; 6 | 3'b010: tagOut=in3; 7 | 3'b011: tagOut=in4; 8 | 3'b100: tagOut=in5; 9 | 3'b101: tagOut=in6; 10 | 3'b110: tagOut=in7; 11 | 3'b111: tagOut=in8; 12 | endcase 13 | endmodule -------------------------------------------------------------------------------- /mux8to1_256b.v: -------------------------------------------------------------------------------- 1 | module mux8to1_256b(input [255:0] in1,input [255:0] in2, input [255:0] in3, input [255:0] in4, input [255:0] in5,input [255:0] in6, input [255:0] in7, input [255:0] in8, input[2:0] sel,output reg[255:0] blockOut); 2 | always@(in1,in2,in3,in4,in5,in6,in7,in8,sel) 3 | case(sel) 4 | 3'b000: blockOut=in1; 5 | 3'b001: blockOut=in2; 6 | 3'b010: blockOut=in3; 7 | 3'b011: blockOut=in4; 8 | 3'b100: blockOut=in5; 9 | 3'b101: blockOut=in6; 10 | 3'b110: blockOut=in7; 11 | 3'b111: blockOut=in8; 12 | endcase 13 | endmodule -------------------------------------------------------------------------------- /mux8to1_2b.v: -------------------------------------------------------------------------------- 1 | module mux8to1_2b(input [1:0]in1, input [1:0]in2, input [1:0]in3, input [1:0]in4, input [1:0]in5, input [1:0]in6, input [1:0]in7, input [1:0]in8,input[2:0] sel,output reg [1:0]priorityOut); 2 | always@(in1,in2,in3,in4,in5,in6,in7,in8,sel) 3 | case(sel) 4 | 3'b000: priorityOut=in1; 5 | 3'b001: priorityOut=in2; 6 | 3'b010: priorityOut=in3; 7 | 3'b011: priorityOut=in4; 8 | 3'b100: priorityOut=in5; 9 | 3'b101: priorityOut=in6; 10 | 3'b110: priorityOut=in7; 11 | 3'b111: priorityOut=in8; 12 | endcase 13 | endmodule -------------------------------------------------------------------------------- /priorityArray.v: -------------------------------------------------------------------------------- 1 | module priorityArray(input clk, input reset, input [7:0] we, input [1:0] priority,output [1:0] priorityOut0, 2 | output [1:0] priorityOut1, output [1:0] priorityOut2, output [1:0] priorityOut3,output [1:0] priorityOut4, 3 | output [1:0] priorityOut5, output [1:0] priorityOut6, output [1:0] priorityOut7); 4 | priorityBlock p0(clk,reset,we[0],priority,priorityOut0); 5 | priorityBlock p1(clk,reset,we[1],priority,priorityOut1); 6 | priorityBlock p2(clk,reset,we[2],priority,priorityOut2); 7 | priorityBlock p3(clk,reset,we[3],priority,priorityOut3); 8 | priorityBlock p4(clk,reset,we[4],priority,priorityOut4); 9 | priorityBlock p5(clk,reset,we[5],priority,priorityOut5); 10 | priorityBlock p6(clk,reset,we[6],priority,priorityOut6); 11 | priorityBlock p7(clk,reset,we[7],priority,priorityOut7); 12 | endmodule -------------------------------------------------------------------------------- /priorityBlock.v: -------------------------------------------------------------------------------- 1 | module priorityBlock(input clk, input reset, input write, input [1:0] priority,output [1:0] priorityData); 2 | D_FF d00(clk, reset,write,priority[0],priorityData[0]); 3 | D_FF d01(clk, reset,write,priority[1],priorityData[1]); 4 | endmodule -------------------------------------------------------------------------------- /priorityEncoder_4x2.v: -------------------------------------------------------------------------------- 1 | module priorityEncoder_4x2(input [3:0] in,output reg [1:0] out); 2 | always @ (in) 3 | begin 4 | if(in[3]==0) out=2'b11; 5 | else if(in[2]==0) out=2'b10; 6 | else if(in[1]==0) out=2'b01; 7 | else if(in[0]==0) out=2'b00; 8 | end 9 | endmodule -------------------------------------------------------------------------------- /tagArray.v: -------------------------------------------------------------------------------- 1 | module tagArray(input clk, input reset, input [7:0] we, input [23:0] tag, output [23:0] tagOut0, output [23:0] tagOut1, output [23:0] tagOut2, output [23:0] tagOut3, output [23:0] tagOut4, output [23:0] tagOut5, output [23:0] tagOut6, output [23:0] tagOut7); 2 | tagBlock t0(clk,reset,we[0],tag,tagOut0); 3 | tagBlock t1(clk,reset,we[1],tag,tagOut1); 4 | tagBlock t2(clk,reset,we[2],tag,tagOut2); 5 | tagBlock t3(clk,reset,we[3],tag,tagOut3); 6 | tagBlock t4(clk,reset,we[4],tag,tagOut4); 7 | tagBlock t5(clk,reset,we[5],tag,tagOut5); 8 | tagBlock t6(clk,reset,we[6],tag,tagOut6); 9 | tagBlock t7(clk,reset,we[7],tag,tagOut7); 10 | endmodule -------------------------------------------------------------------------------- /tagBlock.v: -------------------------------------------------------------------------------- 1 | module tagBlock(input clk, input reset, input write, input [23:0] tag,output [23:0] tagData); 2 | D_FF d00(clk, reset,write,tag[0],tagData[0]); 3 | D_FF d01(clk, reset,write,tag[1],tagData[1]); 4 | D_FF d02(clk, reset,write,tag[2],tagData[2]); 5 | D_FF d03(clk, reset,write,tag[3],tagData[3]); 6 | D_FF d04(clk, reset,write,tag[4],tagData[4]); 7 | D_FF d05(clk, reset,write,tag[5],tagData[5]); 8 | D_FF d06(clk, reset,write,tag[6],tagData[6]); 9 | D_FF d07(clk, reset,write,tag[7],tagData[7]); 10 | D_FF d08(clk, reset,write,tag[8],tagData[8]); 11 | D_FF d09(clk, reset,write,tag[9],tagData[9]); 12 | D_FF d10(clk, reset,write,tag[10],tagData[10]); 13 | D_FF d11(clk, reset,write,tag[11],tagData[11]); 14 | D_FF d12(clk, reset,write,tag[12],tagData[12]); 15 | D_FF d13(clk, reset,write,tag[13],tagData[13]); 16 | D_FF d14(clk, reset,write,tag[14],tagData[14]); 17 | D_FF d15(clk, reset,write,tag[15],tagData[15]); 18 | D_FF d16(clk, reset,write,tag[16],tagData[16]); 19 | D_FF d17(clk, reset,write,tag[17],tagData[17]); 20 | D_FF d18(clk, reset,write,tag[18],tagData[18]); 21 | D_FF d19(clk, reset,write,tag[19],tagData[19]); 22 | D_FF d20(clk, reset,write,tag[20],tagData[20]); 23 | D_FF d21(clk, reset,write,tag[21],tagData[21]); 24 | D_FF d22(clk, reset,write,tag[22],tagData[22]); 25 | D_FF d23(clk, reset,write,tag[23],tagData[23]); 26 | endmodule -------------------------------------------------------------------------------- /testbench.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | reg clk, reset, writeORread; 3 | reg [7:0] inbyte; 4 | reg [31:0] pa; 5 | reg [255:0] dataBlock; 6 | wire [7:0] cacheOutput; 7 | cacheModule uut(clk, reset,pa, writeORread, inbyte, dataBlock, cacheOutput); 8 | always #5 clk=~clk; 9 | initial 10 | begin 11 | clk=0; reset=1;//writeORread=0;inbyte=7'd9;dataBlock=256'h123456;pa=32'h9876ABC0; 12 | #10 reset=0;writeORread=0;inbyte=8'd9;dataBlock=256'h123456;pa=32'h9876ABC0;//read miss 13 | #30 writeORread=0;inbyte=8'h77;dataBlock=256'h123456;pa=32'hABCDABC0; //read miss 14 | #30 writeORread=1;inbyte=8'hAA;pa=32'hABCDABC0; //write hit 15 | #30 writeORread=1;inbyte=8'hBB;dataBlock=256'h666666;pa=32'h12345678; //write miss 16 | #40 $finish; 17 | end 18 | endmodule -------------------------------------------------------------------------------- /updatePriority.v: -------------------------------------------------------------------------------- 1 | module updatePriority(input [1:0] way,input [1:0] in0,input [1:0] in1,input [1:0] in2,input [1:0] in3, 2 | output reg [1:0] out0,output reg [1:0] out1,output reg [1:0] out2,output reg [1:0] out3); 3 | always @ (way,in0,in1,in2,in3) 4 | begin 5 | out0=in0; 6 | out1=in1; 7 | out2=in2; 8 | out3=in3; 9 | case(way) 10 | 2'b00: 11 | begin 12 | if(in1>in0) 13 | out1=in1-2'b01; 14 | if(in2>in0) 15 | out2=in2-2'b01; 16 | if(in3>in0) 17 | out3=in3-2'b01; 18 | out0=2'b11; 19 | end 20 | 2'b01: 21 | begin 22 | if(in0>in1) 23 | out0=in0-2'b01; 24 | if(in2>in1) 25 | out2=in2-2'b01; 26 | if(in3>in1) 27 | out3=in3-2'b01; 28 | out1=2'b11; 29 | end 30 | 2'b10: 31 | begin 32 | if(in0>in2) 33 | out0=in0-2'b01; 34 | if(in1>in2) 35 | out1=in1-2'b01; 36 | if(in3>in2) 37 | out3=in3-2'b01; 38 | out2=2'b11; 39 | end 40 | 2'b11: 41 | begin 42 | if(in0>in3) 43 | out0=in0-2'b01; 44 | if(in1>in3) 45 | out1=in1-2'b01; 46 | if(in2>in3) 47 | out2=in2-2'b01; 48 | out3=2'b11; 49 | end 50 | endcase 51 | end 52 | endmodule -------------------------------------------------------------------------------- /vaildArray.v: -------------------------------------------------------------------------------- 1 | module vaildArray(input clk, input reset, input [7:0] we, input validBit,output validOut0, output validOut1, output validOut2, output validOut3,output validOut4, output validOut5, output validOut6, output validOut7); 2 | D_FF v0(clk, reset,we[0],validBit,validOut0); 3 | D_FF v1(clk, reset,we[1],validBit,validOut1); 4 | D_FF v2(clk, reset,we[2],validBit,validOut2); 5 | D_FF v3(clk, reset,we[3],validBit,validOut3); 6 | D_FF v4(clk, reset,we[4],validBit,validOut4); 7 | D_FF v5(clk, reset,we[5],validBit,validOut5); 8 | D_FF v6(clk, reset,we[6],validBit,validOut6); 9 | D_FF v7(clk, reset,we[7],validBit,validOut7); 10 | endmodule -------------------------------------------------------------------------------- /validityEncoder.v: -------------------------------------------------------------------------------- 1 | module validityEncoder(input [3:0] validBits,output reg invalidReplace, output reg [1:0] out); 2 | always @ (validBits) 3 | begin 4 | invalidReplace=1'b0; 5 | if(validBits[0]==0) out=2'b00; 6 | else if(validBits[1]==0) out=2'b01; 7 | else if(validBits[2]==0) out=2'b10; 8 | else if(validBits[3]==0) out=2'b11; 9 | else invalidReplace=1'b1; 10 | end 11 | endmodule --------------------------------------------------------------------------------