├── results_50M
    └── test.txt
├── tracer
    ├── clean_tracer.sh
    ├── make_tracer.sh
    ├── makefile
    ├── makefile.rules
    └── champsim_tracer.cpp
├── BTBX_artifact_results.xlsx
├── src
    ├── uncore.cc
    └── block.cc
├── scripts
    ├── download_dpc3_traces.sh
    ├── dpc3_max_simpoint.txt
    └── multiworkload.cc
├── .gitignore
├── prefetcher
    ├── no.l1d_pref
    ├── no.l2c_pref
    ├── no.llc_pref
    ├── next_line.llc_pref
    ├── no.l1i_pref
    ├── idealL1i.l1i_pref
    ├── next_line.l1d_pref
    ├── next_line.l2c_pref
    ├── next_line.l1i_pref
    ├── ip_stride.l2c_pref
    ├── fdip.l1i_pref
    └── ipc-2020-paper41-code
├── inc
    ├── uncore.h
    ├── memory_class.h
    ├── champsim.h
    ├── dram_controller.h
    ├── spp_dev.h
    ├── set.h
    ├── cache.h
    ├── instruction.h
    ├── block.h
    └── ooo_cpu.h
├── cvp_tracer
    └── README.md
├── branch
    ├── bimodal.bpred
    ├── gshare.bpred
    ├── hashed_perceptron.bpred
    └── perceptron.bpred
├── run_champsim.sh
├── replacement
    ├── lru.llc_repl
    ├── srrip.llc_repl
    ├── base_replacement.cc
    ├── drrip.llc_repl
    └── ship.llc_repl
├── launch
    ├── scripts
    │   └── createConfig.sh
    └── launch.sh
├── Makefile
├── run_4core.sh
├── collectStats
    └── getResults.sh
├── README.md
└── btb
    ├── btb.cc
    ├── convBTB.btb
    └── BTBX.btb


/results_50M/test.txt:
--------------------------------------------------------------------------------
1 | 


--------------------------------------------------------------------------------
/tracer/clean_tracer.sh:
--------------------------------------------------------------------------------
1 | export PIN_ROOT=/home/grads/c/cienlux/task/pin-3.2-81205-gcc-linux
2 | make clean
3 | 


--------------------------------------------------------------------------------
/BTBX_artifact_results.xlsx:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/rakeshdhakla/ChampSim-master-BTBX/HEAD/BTBX_artifact_results.xlsx


--------------------------------------------------------------------------------
/tracer/make_tracer.sh:
--------------------------------------------------------------------------------
1 | export PIN_ROOT=/your/pin/directory/
2 | mkdir -p obj-intel64
3 | make obj-intel64/champsim_tracer.so
4 | 


--------------------------------------------------------------------------------
/src/uncore.cc:
--------------------------------------------------------------------------------
 1 | #include "uncore.h"
 2 | 
 3 | // uncore
 4 | UNCORE uncore;
 5 | 
 6 | // constructor
 7 | UNCORE::UNCORE() {
 8 | 
 9 | }
10 | 


--------------------------------------------------------------------------------
/scripts/download_dpc3_traces.sh:
--------------------------------------------------------------------------------
1 | #!/bin/bash
2 | 
3 | mkdir -p $PWD/../dpc3_traces
4 | while read LINE
5 | do
6 |     wget -P $PWD/../dpc3_traces -c http://hpca23.cse.tamu.edu/champsim-traces/speccpu/$LINE
7 | done < dpc3_max_simpoint.txt
8 | 


--------------------------------------------------------------------------------
/.gitignore:
--------------------------------------------------------------------------------
 1 | prefetcher/l1i_prefetcher.cc
 2 | prefetcher/l1d_prefetcher.cc
 3 | prefetcher/l2c_prefetcher.cc
 4 | prefetcher/llc_prefetcher.cc
 5 | branch/branch_predictor.cc
 6 | replacement/llc_replacement.cc
 7 | 
 8 | inc/champsim.h.bak
 9 | 
10 | bin/
11 | obj/
12 | 


--------------------------------------------------------------------------------
/prefetcher/no.l1d_pref:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | void CACHE::l1d_prefetcher_initialize() 
 4 | {
 5 | 
 6 | }
 7 | 
 8 | void CACHE::l1d_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type)
 9 | {
10 | 
11 | }
12 | 
13 | void CACHE::l1d_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
14 | {
15 | 
16 | }
17 | 
18 | void CACHE::l1d_prefetcher_final_stats()
19 | {
20 | 
21 | }
22 | 


--------------------------------------------------------------------------------
/inc/uncore.h:
--------------------------------------------------------------------------------
 1 | #ifndef UNCORE_H
 2 | #define UNCORE_H
 3 | 
 4 | #include "champsim.h"
 5 | #include "cache.h"
 6 | #include "dram_controller.h"
 7 | //#include "drc_controller.h"
 8 | 
 9 | //#define DRC_MSHR_SIZE 48
10 | 
11 | // uncore
12 | class UNCORE {
13 |   public:
14 | 
15 |     // LLC
16 |     CACHE LLC{"LLC", LLC_SET, LLC_WAY, LLC_SET*LLC_WAY, LLC_WQ_SIZE, LLC_RQ_SIZE, LLC_PQ_SIZE, LLC_MSHR_SIZE};
17 | 
18 |     // DRAM
19 |     MEMORY_CONTROLLER DRAM{"DRAM"}; 
20 | 
21 |     UNCORE(); 
22 | };
23 | 
24 | extern UNCORE uncore;
25 | 
26 | #endif
27 | 


--------------------------------------------------------------------------------
/prefetcher/no.l2c_pref:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | void CACHE::l2c_prefetcher_initialize() 
 4 | {
 5 | 
 6 | }
 7 | 
 8 | uint32_t CACHE::l2c_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in)
 9 | {
10 |   return metadata_in;
11 | }
12 | 
13 | uint32_t CACHE::l2c_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
14 | {
15 |   return metadata_in;
16 | }
17 | 
18 | void CACHE::l2c_prefetcher_final_stats()
19 | {
20 | 
21 | }
22 | 


--------------------------------------------------------------------------------
/prefetcher/no.llc_pref:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | void CACHE::llc_prefetcher_initialize() 
 4 | {
 5 | 
 6 | }
 7 | 
 8 | uint32_t CACHE::llc_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in)
 9 | {
10 |   return metadata_in;
11 | }
12 | 
13 | uint32_t CACHE::llc_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
14 | {
15 |   return metadata_in;
16 | }
17 | 
18 | void CACHE::llc_prefetcher_final_stats()
19 | {
20 | 
21 | }
22 | 


--------------------------------------------------------------------------------
/tracer/makefile:
--------------------------------------------------------------------------------
 1 | ##############################################################
 2 | #
 3 | #                   DO NOT EDIT THIS FILE!
 4 | #
 5 | ##############################################################
 6 | 
 7 | # If the tool is built out of the kit, PIN_ROOT must be specified in the make invocation and point to the kit root.
 8 | ifdef PIN_ROOT
 9 | CONFIG_ROOT := $(PIN_ROOT)/source/tools/Config
10 | else
11 | CONFIG_ROOT := ../Config
12 | endif
13 | include $(CONFIG_ROOT)/makefile.config
14 | include makefile.rules
15 | include $(TOOLS_ROOT)/Config/makefile.default.rules
16 | 
17 | ##############################################################
18 | #
19 | #                   DO NOT EDIT THIS FILE!
20 | #
21 | ##############################################################
22 | 


--------------------------------------------------------------------------------
/prefetcher/next_line.llc_pref:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | void CACHE::llc_prefetcher_initialize() 
 4 | {
 5 |     cout << "LLC Next Line Prefetcher" << endl;
 6 | }
 7 | 
 8 | uint32_t CACHE::llc_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in)
 9 | {
10 |   uint64_t pf_addr = ((addr>>LOG2_BLOCK_SIZE)+1) << LOG2_BLOCK_SIZE;
11 |   prefetch_line(ip, addr, pf_addr, FILL_LLC, 0);
12 | 
13 |   return metadata_in;
14 | }
15 | 
16 | uint32_t CACHE::llc_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
17 | {
18 |   return metadata_in;
19 | }
20 | 
21 | void CACHE::llc_prefetcher_final_stats()
22 | {
23 |   cout << "LLC Next Line Prefetcher Final Stats: none" << endl;
24 | }
25 | 


--------------------------------------------------------------------------------
/scripts/dpc3_max_simpoint.txt:
--------------------------------------------------------------------------------
 1 | 600.perlbench_s-210B.champsimtrace.xz
 2 | 602.gcc_s-734B.champsimtrace.xz
 3 | 603.bwaves_s-3699B.champsimtrace.xz
 4 | 605.mcf_s-665B.champsimtrace.xz
 5 | 607.cactuBSSN_s-2421B.champsimtrace.xz
 6 | 619.lbm_s-4268B.champsimtrace.xz
 7 | 620.omnetpp_s-874B.champsimtrace.xz
 8 | 621.wrf_s-575B.champsimtrace.xz
 9 | 623.xalancbmk_s-700B.champsimtrace.xz
10 | 625.x264_s-18B.champsimtrace.xz
11 | 627.cam4_s-573B.champsimtrace.xz
12 | 628.pop2_s-17B.champsimtrace.xz
13 | 631.deepsjeng_s-928B.champsimtrace.xz
14 | 638.imagick_s-10316B.champsimtrace.xz
15 | 641.leela_s-800B.champsimtrace.xz
16 | 644.nab_s-5853B.champsimtrace.xz
17 | 648.exchange2_s-1699B.champsimtrace.xz
18 | 649.fotonik3d_s-1176B.champsimtrace.xz
19 | 654.roms_s-842B.champsimtrace.xz
20 | 657.xz_s-3167B.champsimtrace.xz
21 | 


--------------------------------------------------------------------------------
/prefetcher/no.l1i_pref:
--------------------------------------------------------------------------------
 1 | #include "ooo_cpu.h"
 2 | 
 3 | void O3_CPU::l1i_prefetcher_initialize() 
 4 | {
 5 | 
 6 | }
 7 | 
 8 | void O3_CPU::l1i_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
 9 | {
10 | 
11 | }
12 | 
13 | void O3_CPU::l1i_prefetcher_cache_operate(uint64_t v_addr, uint8_t cache_hit, uint8_t prefetch_hit)
14 | {
15 | 
16 | }
17 | 
18 | void O3_CPU::l1i_prefetcher_instruction_operate(uint64_t ip)
19 | {
20 | 
21 | }
22 | 
23 | void O3_CPU::l1i_prefetcher_instruction_spec_operate(uint64_t ip)
24 | {
25 | 
26 | }
27 | 
28 | void O3_CPU::l1i_prefetcher_cycle_operate()
29 | {
30 | 
31 | }
32 | 
33 | void O3_CPU::l1i_prefetcher_cache_fill(uint64_t v_addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_v_addr)
34 | {
35 | 
36 | }
37 | 
38 | void O3_CPU::l1i_prefetcher_final_stats()
39 | {
40 | 
41 | }
42 | 


--------------------------------------------------------------------------------
/prefetcher/idealL1i.l1i_pref:
--------------------------------------------------------------------------------
 1 | #include "ooo_cpu.h"
 2 | 
 3 | void O3_CPU::l1i_prefetcher_initialize() 
 4 | {
 5 | 
 6 | }
 7 | 
 8 | void O3_CPU::l1i_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
 9 | {
10 | 
11 | }
12 | 
13 | void O3_CPU::l1i_prefetcher_cache_operate(uint64_t v_addr, uint8_t cache_hit, uint8_t prefetch_hit)
14 | {
15 | 
16 | }
17 | 
18 | void O3_CPU::l1i_prefetcher_instruction_operate(uint64_t ip)
19 | {
20 | 
21 | }
22 | 
23 | void O3_CPU::l1i_prefetcher_instruction_spec_operate(uint64_t ip)
24 | {
25 | 
26 | }
27 | 
28 | void O3_CPU::l1i_prefetcher_cycle_operate()
29 | {
30 | 
31 | }
32 | 
33 | void O3_CPU::l1i_prefetcher_cache_fill(uint64_t v_addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_v_addr)
34 | {
35 | 
36 | }
37 | 
38 | void O3_CPU::l1i_prefetcher_final_stats()
39 | {
40 | 
41 | }
42 | 


--------------------------------------------------------------------------------
/cvp_tracer/README.md:
--------------------------------------------------------------------------------
 1 | The cvp2champsim tracer comes as is with no guarantee that it covers every conversion case.
 2 | 
 3 | The tracer is used to convert the traces from the 2nd Championship Value 
 4 | Prediction (CVP) to a ChampSim-friendly format. 
 5 | 
 6 | CVP-1 Site: https://www.microarch.org/cvp1/
 7 | CVP-2 Site: https://www.microarch.org/cvp1/cvp2/rules.html
 8 | 
 9 | To use the tracer first compile it using g++:
10 | 
11 | g++ cvp2champsim.cc -o cvp_tracer
12 | 
13 | To convert a trace execute:
14 | 
15 | ./cvp_tracer TRACE_NAME.gz
16 | 
17 | The ChampSim trace will be sent to standard output so to keep and compress the 
18 | output trace run:
19 | 
20 | ./cvp_tracer TRACE_NAME.gz | gzip > NEW_TRACE.champsim.gz
21 | 
22 | Adding the "-v" flag will print the dissassembly of the CVP trace to standard 
23 | error output as well as the ChampSim format to standard output.
24 | 


--------------------------------------------------------------------------------
/branch/bimodal.bpred:
--------------------------------------------------------------------------------
 1 | #include "ooo_cpu.h"
 2 | 
 3 | #define BIMODAL_TABLE_SIZE 16384
 4 | #define BIMODAL_PRIME 16381
 5 | #define MAX_COUNTER 3
 6 | int bimodal_table[NUM_CPUS][BIMODAL_TABLE_SIZE];
 7 | 
 8 | void O3_CPU::initialize_branch_predictor()
 9 | {
10 |     cout << "CPU " << cpu << " Bimodal branch predictor" << endl;
11 | 
12 |     for(int i = 0; i < BIMODAL_TABLE_SIZE; i++)
13 |         bimodal_table[cpu][i] = 0;
14 | }
15 | 
16 | uint8_t O3_CPU::predict_branch(uint64_t ip)
17 | {
18 |     uint32_t hash = ip % BIMODAL_PRIME;
19 |     uint8_t prediction = (bimodal_table[cpu][hash] >= ((MAX_COUNTER + 1)/2)) ? 1 : 0;
20 | 
21 |     return prediction;
22 | }
23 | 
24 | void O3_CPU::last_branch_result(uint64_t ip, uint8_t taken)
25 | {
26 |     uint32_t hash = ip % BIMODAL_PRIME;
27 | 
28 |     if (taken && (bimodal_table[cpu][hash] < MAX_COUNTER))
29 |         bimodal_table[cpu][hash]++;
30 |     else if ((taken == 0) && (bimodal_table[cpu][hash] > 0))
31 |         bimodal_table[cpu][hash]--;
32 | }
33 | 


--------------------------------------------------------------------------------
/prefetcher/next_line.l1d_pref:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | void CACHE::l1d_prefetcher_initialize() 
 4 | {
 5 |     cout << "CPU " << cpu << " L1D next line prefetcher" << endl;
 6 | }
 7 | 
 8 | void CACHE::l1d_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type)
 9 | {
10 |     uint64_t pf_addr = ((addr>>LOG2_BLOCK_SIZE)+1) << LOG2_BLOCK_SIZE;
11 | 
12 |     DP ( if (warmup_complete[cpu]) {
13 |     cout << "[" << NAME << "] " << __func__ << hex << " base_cl: " << (addr>>LOG2_BLOCK_SIZE);
14 |     cout << " pf_cl: " << (pf_addr>>LOG2_BLOCK_SIZE) << " ip: " << ip << " cache_hit: " << +cache_hit << " type: " << +type << endl; });
15 | 
16 |     prefetch_line(ip, addr, pf_addr, FILL_L1, 0);
17 | }
18 | 
19 | void CACHE::l1d_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
20 | {
21 | 
22 | }
23 | 
24 | void CACHE::l1d_prefetcher_final_stats()
25 | {
26 |     cout << "CPU " << cpu << " L1D next line prefetcher final stats" << endl;
27 | }
28 | 


--------------------------------------------------------------------------------
/prefetcher/next_line.l2c_pref:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | void CACHE::l2c_prefetcher_initialize() 
 4 | {
 5 |     cout << "CPU " << cpu << " L2C next line prefetcher" << endl;
 6 | }
 7 | 
 8 | uint32_t CACHE::l2c_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in)
 9 | {
10 |     uint64_t pf_addr = ((addr>>LOG2_BLOCK_SIZE)+1) << LOG2_BLOCK_SIZE;
11 | 
12 |     DP ( if (warmup_complete[cpu]) {
13 |     cout << "[" << NAME << "] " << __func__ << hex << " base_cl: " << (addr>>LOG2_BLOCK_SIZE);
14 |     cout << " pf_cl: " << (pf_addr>>LOG2_BLOCK_SIZE) << " ip: " << ip << " cache_hit: " << +cache_hit << " type: " << +type << endl; });
15 | 
16 |     prefetch_line(ip, addr, pf_addr, FILL_L2, 0);
17 | 
18 |     return metadata_in;
19 | }
20 | 
21 | uint32_t CACHE::l2c_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
22 | {
23 |   return metadata_in;
24 | }
25 | 
26 | void CACHE::l2c_prefetcher_final_stats()
27 | {
28 |     cout << "CPU " << cpu << " L2C next line prefetcher final stats" << endl;
29 | }
30 | 


--------------------------------------------------------------------------------
/prefetcher/next_line.l1i_pref:
--------------------------------------------------------------------------------
 1 | #include "ooo_cpu.h"
 2 | 
 3 | void O3_CPU::l1i_prefetcher_initialize() 
 4 | {
 5 |   cout << "CPU " << cpu << " L1I next line prefetcher" << endl;
 6 | }
 7 | 
 8 | void O3_CPU::l1i_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
 9 | {
10 |   
11 | }
12 | 
13 | void O3_CPU::l1i_prefetcher_cache_operate(uint64_t v_addr, uint8_t cache_hit, uint8_t prefetch_hit)
14 | {
15 |   //cout << "access v_addr: 0x" << hex << v_addr << dec << endl;
16 |   
17 |   if((cache_hit == 0) && (L1I.MSHR.occupancy < (L1I.MSHR.SIZE>>1)))
18 |     {
19 |       uint64_t pf_addr = v_addr + (1<<LOG2_BLOCK_SIZE);
20 |       prefetch_code_line(pf_addr);
21 |     }
22 | }
23 | 
24 | void O3_CPU::l1i_prefetcher_cycle_operate()
25 | {
26 | 
27 | }
28 | 
29 | void O3_CPU::l1i_prefetcher_instruction_operate(uint64_t ip)
30 | {
31 | 
32 | }
33 | 
34 | void O3_CPU::l1i_prefetcher_cache_fill(uint64_t v_addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_v_addr)
35 | {
36 |   //cout << hex << "fill: 0x" << v_addr << dec << " " << set << " " << way << " " << (uint32_t)prefetch << " " << hex << "evict: 0x" << evicted_v_addr << dec << endl;
37 | }
38 | 
39 | void O3_CPU::l1i_prefetcher_final_stats()
40 | {
41 |   cout << "CPU " << cpu << " L1I next line prefetcher final stats" << endl;
42 | }
43 | 


--------------------------------------------------------------------------------
/run_champsim.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | if [ "$#" -lt 4 ]; then
 4 |     echo "Illegal number of parameters"
 5 |     echo "Usage: ./run_champsim.sh [BINARY] [N_WARM] [N_SIM] [TRACE] [OPTION]"
 6 |     exit 1
 7 | fi
 8 | 
 9 | TRACE_DIR=$PWD/dpc3_traces
10 | BINARY=${1}
11 | N_WARM=${2}
12 | N_SIM=${3}
13 | TRACE=${4}
14 | OPTION=${5}
15 | 
16 | # Sanity check
17 | if [ -z $TRACE_DIR ] || [ ! -d "$TRACE_DIR" ] ; then
18 |     echo "[ERROR] Cannot find a trace directory: $TRACE_DIR"
19 |     exit 1
20 | fi
21 | 
22 | if [ ! -f "bin/$BINARY" ] ; then
23 |     echo "[ERROR] Cannot find a ChampSim binary: bin/$BINARY"
24 |     exit 1
25 | fi
26 | 
27 | re='^[0-9]+$'
28 | if ! [[ $N_WARM =~ $re ]] || [ -z $N_WARM ] ; then
29 |     echo "[ERROR]: Number of warmup instructions is NOT a number" >&2;
30 |     exit 1
31 | fi
32 | 
33 | re='^[0-9]+$'
34 | if ! [[ $N_SIM =~ $re ]] || [ -z $N_SIM ] ; then
35 |     echo "[ERROR]: Number of simulation instructions is NOT a number" >&2;
36 |     exit 1
37 | fi
38 | 
39 | if [ ! -f "$TRACE_DIR/$TRACE" ] ; then
40 |     echo "[ERROR] Cannot find a trace file: $TRACE_DIR/$TRACE"
41 |     exit 1
42 | fi
43 | 
44 | mkdir -p results_${N_SIM}M
45 | (./bin/${BINARY} -warmup_instructions ${N_WARM}000000 -simulation_instructions ${N_SIM}000000 ${OPTION} -traces ${TRACE_DIR}/${TRACE}) &> results_${N_SIM}M/${TRACE}-${BINARY}${OPTION}.txt
46 | 


--------------------------------------------------------------------------------
/scripts/multiworkload.cc:
--------------------------------------------------------------------------------
 1 | #include <stdio.h>
 2 | #include <stdlib.h>
 3 | #include <random>
 4 | #include <time.h>
 5 | 
 6 | #define NUM_MIX  100
 7 | #define NUM_CPUS 4
 8 | #define NUM_TRACE 20
 9 | 
10 | using namespace std;
11 | default_random_engine generator;
12 | 
13 | int main()
14 | {
15 |     int benchmark[NUM_MIX][NUM_CPUS];
16 |     for (int i=0; i<NUM_MIX; i++)
17 |         for (int j=0; j<NUM_CPUS; j++)
18 |             benchmark[i][j] = -1;
19 | 
20 |     // Random seed
21 |     generator.seed(time(NULL));
22 | 
23 |     // Set range
24 |     const int rand_min = 1;
25 |     const int rand_max = NUM_TRACE; 
26 |     uniform_int_distribution<int> distribution(rand_min, rand_max);
27 | 
28 |     int temp_rand;
29 |     bool do_again = false;
30 |     
31 |     for (int i = 0; i < NUM_MIX; i++) {
32 |         //printf("MIX%2d: ", i+1);
33 |         for (int j = 0; j < NUM_CPUS; j++) {
34 |             do  {
35 |                 do_again = false;
36 |                 temp_rand = distribution(generator); // Generate random integer flat in [rand_min, rand_mix]
37 |                 for (int k = 0; k < j; k++) {
38 |                     if (temp_rand == benchmark[i][k]) {
39 |                         do_again = true;
40 |                         break;
41 |                     }
42 |                 }
43 |             } while (do_again);
44 | 
45 |             benchmark[i][j] = temp_rand;
46 |             printf("%d ", benchmark[i][j]);
47 |         }
48 |         printf("\n");
49 |     }
50 | 
51 |     return 0;
52 | }
53 | 


--------------------------------------------------------------------------------
/replacement/lru.llc_repl:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | // initialize replacement state
 4 | void CACHE::llc_initialize_replacement()
 5 | {
 6 | 
 7 | }
 8 | 
 9 | // find replacement victim
10 | uint32_t CACHE::llc_find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
11 | {
12 |     // baseline LRU
13 |     return lru_victim(cpu, instr_id, set, current_set, ip, full_addr, type); 
14 | }
15 | 
16 | // called on every cache hit and cache fill
17 | void CACHE::llc_update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
18 | {
19 |     string TYPE_NAME;
20 |     if (type == LOAD)
21 |         TYPE_NAME = "LOAD";
22 |     else if (type == RFO)
23 |         TYPE_NAME = "RFO";
24 |     else if (type == PREFETCH)
25 |         TYPE_NAME = "PF";
26 |     else if (type == WRITEBACK)
27 |         TYPE_NAME = "WB";
28 |     else
29 |         assert(0);
30 | 
31 |     if (hit)
32 |         TYPE_NAME += "_HIT";
33 |     else
34 |         TYPE_NAME += "_MISS";
35 | 
36 |     if ((type == WRITEBACK) && ip)
37 |         assert(0);
38 | 
39 |     // uncomment this line to see the LLC accesses
40 |     // cout << "CPU: " << cpu << "  LLC " << setw(9) << TYPE_NAME << " set: " << setw(5) << set << " way: " << setw(2) << way;
41 |     // cout << hex << " paddr: " << setw(12) << paddr << " ip: " << setw(8) << ip << " victim_addr: " << victim_addr << dec << endl;
42 | 
43 |     // baseline LRU
44 |     if (hit && (type == WRITEBACK)) // writeback hit does not update LRU state
45 |         return;
46 | 
47 |     return lru_update(set, way);
48 | }
49 | 
50 | void CACHE::llc_replacement_final_stats()
51 | {
52 | 
53 | }
54 | 


--------------------------------------------------------------------------------
/launch/scripts/createConfig.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | declare -a bench
 4 | declare -a prefetch
 5 | declare -a btb
 6 | 
 7 | PATH_TO_CHAMPSIM=
 8 | 
 9 | bench[0]=client_001
10 | bench[1]=client_002
11 | bench[2]=client_003
12 | bench[3]=client_004
13 | bench[4]=client_005
14 | bench[5]=client_006
15 | bench[6]=client_007
16 | bench[7]=client_008
17 | bench[8]=server_001
18 | bench[9]=server_002
19 | bench[10]=server_003
20 | bench[11]=server_004
21 | bench[12]=server_009
22 | bench[13]=server_010
23 | bench[14]=server_011
24 | bench[15]=server_012
25 | bench[16]=server_013
26 | bench[17]=server_014
27 | bench[18]=server_015
28 | bench[19]=server_016
29 | bench[20]=server_017
30 | bench[21]=server_018
31 | bench[22]=server_019
32 | bench[23]=server_020
33 | bench[24]=server_021
34 | bench[25]=server_022
35 | bench[26]=server_023
36 | bench[27]=server_024
37 | bench[28]=server_025
38 | bench[29]=server_026
39 | bench[30]=server_027
40 | bench[31]=server_028
41 | bench[32]=server_029
42 | bench[33]=server_030
43 | bench[34]=server_031
44 | bench[35]=server_032
45 | bench[36]=server_033
46 | bench[37]=server_034
47 | bench[38]=server_035
48 | bench[39]=server_036
49 | bench[40]=server_037
50 | bench[41]=server_038
51 | bench[42]=server_039
52 | 
53 | prefetch[0]=no
54 | prefetch[1]=fdip
55 | 
56 | btb[0]=convBTB
57 | btb[1]=pdede
58 | btb[2]=BTBX
59 | 
60 | 
61 | for ((j=0;j<2;j=j+1)); do
62 |     for ((i=0;i<43;i=i+1)); do
63 | 	for ((k=0;k<3;k=k+1)); do
64 | 	    script_name="${bench[i]}_${prefetch[j]}_${btb[k]}.sh"
65 | 	    echo "#!/bin/bash" > $script_name
66 | 	    echo "cd ${PATH_TO_CHAMPSIM}" >> $script_name
67 | 	    echo "./run_champsim.sh hashed_perceptron-${btb[k]}-${prefetch[j]}-next_line-spp_dev-no-lru-1core 50 50 ${bench[i]}.champsimtrace.xz" >> $script_name
68 | 	done
69 |     done
70 | done 
71 | 


--------------------------------------------------------------------------------
/Makefile:
--------------------------------------------------------------------------------
 1 | app = champsim
 2 | 
 3 | srcExt = cc
 4 | srcDir = src branch replacement prefetcher btb
 5 | objDir = obj
 6 | binDir = bin
 7 | inc = inc
 8 | 
 9 | debug = 1
10 | 
11 | CFlags = -Wall -O3 -std=c++11
12 | LDFlags =
13 | libs =
14 | libDir =
15 | 
16 | 
17 | #************************ DO NOT EDIT BELOW THIS LINE! ************************
18 | 
19 | ifeq ($(debug),1)
20 | 	debug=-g
21 | else
22 | 	debug=
23 | endif
24 | inc := $(addprefix -I,$(inc))
25 | libs := $(addprefix -l,$(libs))
26 | libDir := $(addprefix -L,$(libDir))
27 | CFlags += -c $(debug) $(inc) $(libDir) $(libs)
28 | sources := $(shell find $(srcDir) -name '*.$(srcExt)')
29 | srcDirs := $(shell find . -name '*.$(srcExt)' -exec dirname {} \; | uniq)
30 | objects := $(patsubst %.$(srcExt),$(objDir)/%.o,$(sources))
31 | 
32 | ifeq ($(srcExt),cc)
33 | 	CC = $(CXX)
34 | else
35 | 	CFlags += -std=gnu99
36 | endif
37 | 
38 | .phony: all clean distclean
39 | 
40 | 
41 | all: $(binDir)/$(app)
42 | 
43 | $(binDir)/$(app): buildrepo $(objects)
44 | 	@mkdir -p `dirname $@`
45 | 	@echo "Linking $@..."
46 | 	@$(CC) $(objects) $(LDFlags) -o $@
47 | 
48 | $(objDir)/%.o: %.$(srcExt)
49 | 	@echo "Generating dependencies for $<..."
50 | 	@$(call make-depend,$<,$@,$(subst .o,.d,$@))
51 | 	@echo "Compiling $<..."
52 | 	@$(CC) $(CFlags) $< -o $@
53 | 
54 | clean:
55 | 	$(RM) -r $(objDir)
56 | 
57 | distclean: clean
58 | 	$(RM) -r $(binDir)/$(app)
59 | 
60 | buildrepo:
61 | 	@$(call make-repo)
62 | 
63 | define make-repo
64 |    for dir in $(srcDirs); \
65 |    do \
66 | 	mkdir -p $(objDir)/$$dir; \
67 |    done
68 | endef
69 | 
70 | 
71 | # usage: $(call make-depend,source-file,object-file,depend-file)
72 | define make-depend
73 |   $(CC) -MM       \
74 |         -MF $3    \
75 |         -MP       \
76 |         -MT $2    \
77 |         $(CFlags) \
78 |         $1
79 | endef
80 | 


--------------------------------------------------------------------------------
/launch/launch.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | declare -a bench
 4 | declare -a prefetch
 5 | declare -a btb
 6 | 
 7 | bench[0]=client_001
 8 | bench[1]=client_002
 9 | bench[2]=client_003
10 | bench[3]=client_004
11 | bench[4]=client_005
12 | bench[5]=client_006
13 | bench[6]=client_007
14 | bench[7]=client_008
15 | bench[8]=server_001
16 | bench[9]=server_002
17 | bench[10]=server_003
18 | bench[11]=server_004
19 | bench[12]=server_009
20 | bench[13]=server_010
21 | bench[14]=server_011
22 | bench[15]=server_012
23 | bench[16]=server_013
24 | bench[17]=server_014
25 | bench[18]=server_015
26 | bench[19]=server_016
27 | bench[20]=server_017
28 | bench[21]=server_018
29 | bench[22]=server_019
30 | bench[23]=server_020
31 | bench[24]=server_021
32 | bench[25]=server_022
33 | bench[26]=server_023
34 | bench[27]=server_024
35 | bench[28]=server_025
36 | bench[29]=server_026
37 | bench[30]=server_027
38 | bench[31]=server_028
39 | bench[32]=server_029
40 | bench[33]=server_030
41 | bench[34]=server_031
42 | bench[35]=server_032
43 | bench[36]=server_033
44 | bench[37]=server_034
45 | bench[38]=server_035
46 | bench[39]=server_036
47 | bench[40]=server_037
48 | bench[41]=server_038
49 | bench[42]=server_039
50 | 
51 | prefetch[0]=no
52 | prefetch[1]=fdip
53 | 
54 | 
55 | btb[0]=convBTB
56 | btb[1]=pdede
57 | btb[2]=BTBX
58 | 
59 | for ((j=0;j<2;j=j+1)); do
60 |     for ((i=0;i<43;i=i+1)); do
61 | 	for ((k=0;k<3;k=k+1)); do
62 |             echo "sbatch --partition=CPUQ --account=share-ie-idi --nodes=1 --ntasks-per-node=1 --mem=3GB --time=0-0:30:00 --job-name=${bench[i]}_${prefetch[j]}_${btb[k]} scripts/${bench[i]}_${prefetch[j]}_${btb[k]}.sh"
63 |             #sbatch --partition=CPUQ --account=share-ie-idi --nodes=1 --ntasks-per-node=1 --mem=3GB --time=0-0:30:00 --job-name=${bench[i]}_${prefetch[j]}_${btb[k]} scripts/${bench[i]}_${prefetch[j]}_${btb[k]}.sh
64 | 	    <cluster_launch_command_here>
65 | 	done
66 |     done
67 | done 
68 | 


--------------------------------------------------------------------------------
/branch/gshare.bpred:
--------------------------------------------------------------------------------
 1 | #include "ooo_cpu.h"
 2 | 
 3 | #define GLOBAL_HISTORY_LENGTH 14
 4 | #define GLOBAL_HISTORY_MASK (1 << GLOBAL_HISTORY_LENGTH) - 1
 5 | int branch_history_vector[NUM_CPUS];
 6 | 
 7 | #define GS_HISTORY_TABLE_SIZE 16384
 8 | int gs_history_table[NUM_CPUS][GS_HISTORY_TABLE_SIZE];
 9 | int my_last_prediction[NUM_CPUS];
10 | 
11 | void O3_CPU::initialize_branch_predictor()
12 | {
13 |     cout << "CPU " << cpu << " GSHARE branch predictor" << endl;
14 | 
15 |     branch_history_vector[cpu] = 0;
16 |     my_last_prediction[cpu] = 0;
17 | 
18 |     for(int i=0; i<GS_HISTORY_TABLE_SIZE; i++)
19 |         gs_history_table[cpu][i] = 2; // 2 is slightly taken
20 | }
21 | 
22 | unsigned int gs_table_hash(uint64_t ip, int bh_vector)
23 | {
24 |     unsigned int hash = ip^(ip>>GLOBAL_HISTORY_LENGTH)^(ip>>(GLOBAL_HISTORY_LENGTH*2))^bh_vector;
25 |     hash = hash%GS_HISTORY_TABLE_SIZE;
26 | 
27 |     //printf("%d\n", hash);
28 | 
29 |     return hash;
30 | }
31 | 
32 | uint8_t O3_CPU::predict_branch(uint64_t ip)
33 | {
34 |     int prediction = 1;
35 | 
36 |     int gs_hash = gs_table_hash(ip, branch_history_vector[cpu]);
37 | 
38 |     if(gs_history_table[cpu][gs_hash] >= 2)
39 |         prediction = 1;
40 |     else
41 |         prediction = 0;
42 | 
43 |     my_last_prediction[cpu] = prediction;
44 | 
45 |     return prediction;
46 | }
47 | 
48 | void O3_CPU::last_branch_result(uint64_t ip, uint8_t taken)
49 | {
50 |     int gs_hash = gs_table_hash(ip, branch_history_vector[cpu]);
51 | 
52 |     if(taken == 1) {
53 |         if(gs_history_table[cpu][gs_hash] < 3)
54 |             gs_history_table[cpu][gs_hash]++;
55 |     } else {
56 |         if(gs_history_table[cpu][gs_hash] > 0)
57 |             gs_history_table[cpu][gs_hash]--;
58 |     }
59 | 
60 |     // update branch history vector
61 |     branch_history_vector[cpu] <<= 1;
62 |     branch_history_vector[cpu] &= GLOBAL_HISTORY_MASK;
63 |     branch_history_vector[cpu] |= taken;
64 | }
65 | 


--------------------------------------------------------------------------------
/run_4core.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | if [ "$#" -lt 8 ] || [ "$#" -gt 9 ]; then
 4 |     echo "Illegal number of parameters"
 5 |     echo "Usage: ./run_4core.sh [BINARY] [N_WARM] [N_SIM] [N_MIX] [TRACE0] [TRACE1] [TRACE2] [TRACE3] [OPTION]"
 6 |     exit 1
 7 | fi
 8 | 
 9 | TRACE_DIR=$PWD/dpc3_traces
10 | BINARY=${1}
11 | N_WARM=${2}
12 | N_SIM=${3}
13 | N_MIX=${4}
14 | TRACE0=${5}
15 | TRACE1=${6}
16 | TRACE2=${7}
17 | TRACE3=${8}
18 | OPTION=${9}
19 | 
20 | # Sanity check
21 | if [ -z $TRACE_DIR ] || [ ! -d "$TRACE_DIR" ] ; then
22 |     echo "[ERROR] Cannot find a trace directory: $TRACE_DIR"
23 |     exit 1
24 | fi
25 | 
26 | if [ ! -f "bin/$BINARY" ] ; then
27 |     echo "[ERROR] Cannot find a ChampSim binary: bin/$BINARY"
28 |     exit 1
29 | fi
30 | 
31 | re='^[0-9]+$'
32 | if ! [[ $N_WARM =~ $re ]] || [ -z $N_WARM ] ; then
33 |     echo "[ERROR]: Number of warmup instructions is NOT a number" >&2;
34 |     exit 1
35 | fi
36 | 
37 | re='^[0-9]+$'
38 | if ! [[ $N_SIM =~ $re ]] || [ -z $N_SIM ] ; then
39 |     echo "[ERROR]: Number of simulation instructions is NOT a number" >&2;
40 |     exit 1
41 | fi
42 | 
43 | if [ ! -f "$TRACE_DIR/$TRACE0" ] ; then
44 |     echo "[ERROR] Cannot find a trace0 file: $TRACE_DIR/$TRACE0"
45 |     exit 1
46 | fi
47 | 
48 | if [ ! -f "$TRACE_DIR/$TRACE1" ] ; then
49 |     echo "[ERROR] Cannot find a trace1 file: $TRACE_DIR/$TRACE1"
50 |     exit 1
51 | fi
52 | 
53 | if [ ! -f "$TRACE_DIR/$TRACE2" ] ; then
54 |     echo "[ERROR] Cannot find a trace2 file: $TRACE_DIR/$TRACE2"
55 |     exit 1
56 | fi
57 | 
58 | if [ ! -f "$TRACE_DIR/$TRACE3" ] ; then
59 |     echo "[ERROR] Cannot find a trace3 file: $TRACE_DIR/$TRACE3"
60 |     exit 1
61 | fi
62 | 
63 | mkdir -p results_4core_${N_SIM}M
64 | (./bin/${BINARY} -warmup_instructions ${N_WARM}000000 -simulation_instructions ${N_SIM}000000 ${OPTION} -traces ${TRACE_DIR}/${TRACE0} ${TRACE_DIR}/${TRACE1} ${TRACE_DIR}/${TRACE2} ${TRACE_DIR}/${TRACE3}) &> results_4core_${N_SIM}M/mix${N_MIX}-${BINARY}${OPTION}.txt
65 | 


--------------------------------------------------------------------------------
/replacement/srrip.llc_repl:
--------------------------------------------------------------------------------
 1 | #include "cache.h"
 2 | 
 3 | #define maxRRPV 3
 4 | uint32_t rrpv[LLC_SET][LLC_WAY];
 5 | 
 6 | // initialize replacement state
 7 | void CACHE::llc_initialize_replacement()
 8 | {
 9 |     cout << "Initialize SRRIP state" << endl;
10 | 
11 |     for (int i=0; i<LLC_SET; i++) {
12 |         for (int j=0; j<LLC_WAY; j++) {
13 |             rrpv[i][j] = maxRRPV;
14 |         }
15 |     }
16 | }
17 | 
18 | // find replacement victim
19 | uint32_t CACHE::llc_find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
20 | {
21 |     // look for the maxRRPV line
22 |     while (1)
23 |     {
24 |         for (int i=0; i<LLC_WAY; i++)
25 |             if (rrpv[set][i] == maxRRPV)
26 |                 return i;
27 | 
28 |         for (int i=0; i<LLC_WAY; i++)
29 |             rrpv[set][i]++;
30 |     }
31 | 
32 |     // WE SHOULD NOT REACH HERE
33 |     assert(0);
34 |     return 0;
35 | }
36 | 
37 | // called on every cache hit and cache fill
38 | void CACHE::llc_update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
39 | {
40 |     string TYPE_NAME;
41 |     if (type == LOAD)
42 |         TYPE_NAME = "LOAD";
43 |     else if (type == RFO)
44 |         TYPE_NAME = "RFO";
45 |     else if (type == PREFETCH)
46 |         TYPE_NAME = "PF";
47 |     else if (type == WRITEBACK)
48 |         TYPE_NAME = "WB";
49 |     else
50 |         assert(0);
51 | 
52 |     if (hit)
53 |         TYPE_NAME += "_HIT";
54 |     else
55 |         TYPE_NAME += "_MISS";
56 | 
57 |     if ((type == WRITEBACK) && ip)
58 |         assert(0);
59 | 
60 |     // uncomment this line to see the LLC accesses
61 |     // cout << "CPU: " << cpu << "  LLC " << setw(9) << TYPE_NAME << " set: " << setw(5) << set << " way: " << setw(2) << way;
62 |     // cout << hex << " paddr: " << setw(12) << paddr << " ip: " << setw(8) << ip << " victim_addr: " << victim_addr << dec << endl;
63 |     
64 |     if (hit)
65 |         rrpv[set][way] = 0;
66 |     else
67 |         rrpv[set][way] = maxRRPV-1;
68 | }
69 | 
70 | // use this function to print out your own stats at the end of simulation
71 | void CACHE::llc_replacement_final_stats()
72 | {
73 | 
74 | }
75 | 


--------------------------------------------------------------------------------
/inc/memory_class.h:
--------------------------------------------------------------------------------
 1 | #ifndef MEMORY_CLASS_H
 2 | #define MEMORY_CLASS_H
 3 | 
 4 | #include "champsim.h"
 5 | #include "block.h"
 6 | 
 7 | // CACHE ACCESS TYPE
 8 | #define LOAD      0
 9 | #define RFO       1
10 | #define PREFETCH  2
11 | #define WRITEBACK 3
12 | #define NUM_TYPES 4
13 | 
14 | extern uint32_t tRP,  // Row Precharge (RP) latency
15 |                 tRCD, // Row address to Column address (RCD) latency
16 |                 tCAS; // Column Address Strobe (CAS) latency
17 | 
18 | extern uint64_t l2pf_access;
19 | 
20 | class MEMORY {
21 |   public:
22 |     // memory interface
23 |     MEMORY *upper_level_icache[NUM_CPUS], *upper_level_dcache[NUM_CPUS], *lower_level, *extra_interface;
24 | 
25 |     // empty queues
26 |     PACKET_QUEUE WQ{"EMPTY", 1}, RQ{"EMPTY", 1}, PQ{"EMPTY", 1}, MSHR{"EMPTY", 1};
27 | 
28 |     // functions
29 |     virtual int  add_rq(PACKET *packet) = 0;
30 |     virtual int  add_wq(PACKET *packet) = 0;
31 |     virtual int  add_pq(PACKET *packet) = 0;
32 |     virtual void return_data(PACKET *packet) = 0;
33 |     virtual void operate() = 0;
34 |     virtual void increment_WQ_FULL(uint64_t address) = 0;
35 |     virtual uint32_t get_occupancy(uint8_t queue_type, uint64_t address) = 0;
36 |     virtual uint32_t get_size(uint8_t queue_type, uint64_t address) = 0;
37 | 
38 |     // stats
39 |     uint64_t ACCESS[NUM_TYPES], HIT[NUM_TYPES], MISS[NUM_TYPES], MSHR_MERGED[NUM_TYPES], STALL[NUM_TYPES];
40 | 
41 |     MEMORY() {
42 |         for (uint32_t i=0; i<NUM_TYPES; i++) {
43 |             ACCESS[i] = 0;
44 |             HIT[i] = 0;
45 |             MISS[i] = 0;
46 |             MSHR_MERGED[i] = 0;
47 |             STALL[i] = 0;
48 |         }
49 |     }
50 | };
51 | 
52 | class BANK_REQUEST {
53 |   public:
54 |     uint64_t cycle_available,
55 |              address,
56 |              full_addr;
57 | 
58 |     uint32_t open_row;
59 | 
60 |     uint8_t working,
61 |             working_type,
62 |             row_buffer_hit,
63 |             drc_hit,
64 |             is_write,
65 |             is_read;
66 | 
67 |     int request_index;
68 | 
69 |     BANK_REQUEST() {
70 |         cycle_available = 0;
71 |         address = 0;
72 |         full_addr = 0;
73 | 
74 |         open_row = UINT32_MAX;
75 | 
76 |         working = 0;
77 |         working_type = 0;
78 |         row_buffer_hit = 0;
79 |         drc_hit = 0;
80 |         is_write = 0;
81 |         is_read = 0;
82 | 
83 |         request_index = -1;
84 |     };
85 | };
86 | 
87 | #endif
88 | 


--------------------------------------------------------------------------------
/collectStats/getResults.sh:
--------------------------------------------------------------------------------
 1 | #!/bin/bash
 2 | 
 3 | declare -a bench
 4 | declare -a prefetch
 5 | declare -a btb 
 6 | 
 7 | rm all_res
 8 | 
 9 | prefetch[0]=no
10 | prefetch[1]=fdip
11 | prefetch[2]=fdip
12 | prefetch[3]=next_line
13 | prefetch[4]=paper30
14 | #prefetch[6]=fdip_IBTB_Tag12_4
15 | #prefetch[7]=fdip_IBTB_Tag10_6
16 | #prefetch[8]=fdip_IBTB_Tag14_2
17 | #prefetch[9]=fdip_IBTB_Tag8_8
18 | #prefetch[10]=fdip_IBTB_New10DSW8
19 | 
20 | runName[0]=no
21 | runName[1]=fdip
22 | runName[2]=fdip
23 | runName[3]=next_line
24 | runName[4]=paper30
25 | #runName[5]=fdip_AlwaysNotTakenCB
26 | #runName[6]=fdip_IBTB_Tag12_4
27 | #runName[7]=fdip_IBTB_Tag10_6
28 | #runName[8]=fdip_IBTB_Tag14_2
29 | #runName[9]=fdip_IBTB_Tag8_8
30 | #runName[10]=fdip_IBTB_Split10DSW8
31 | #runName[4]=fdip_IBTB4
32 | #runName[5]=fdip_STDisp
33 | 
34 | runs=2
35 | 
36 | bench[0]=client_001
37 | bench[1]=client_002
38 | bench[2]=client_003
39 | bench[3]=client_004
40 | bench[4]=client_005
41 | bench[5]=client_006
42 | bench[6]=client_007
43 | bench[7]=client_008
44 | bench[8]=server_001
45 | bench[9]=server_002
46 | bench[10]=server_003
47 | bench[11]=server_004
48 | bench[12]=server_009
49 | bench[13]=server_010
50 | bench[14]=server_011
51 | bench[15]=server_012
52 | bench[16]=server_013
53 | bench[17]=server_014
54 | bench[18]=server_015
55 | bench[19]=server_016
56 | bench[20]=server_017
57 | bench[21]=server_018
58 | bench[22]=server_019
59 | bench[23]=server_020
60 | bench[24]=server_021
61 | bench[25]=server_022
62 | bench[26]=server_023
63 | bench[27]=server_024
64 | bench[28]=server_025
65 | bench[29]=server_026
66 | bench[30]=server_027
67 | bench[31]=server_028
68 | bench[32]=server_029
69 | bench[33]=server_030
70 | bench[34]=server_031
71 | bench[35]=server_032
72 | bench[36]=server_033
73 | bench[37]=server_034
74 | bench[38]=server_035
75 | bench[39]=server_036
76 | bench[40]=server_037
77 | bench[41]=server_038
78 | bench[42]=server_039
79 | 
80 | btb[0]=convBTB
81 | btb[1]=pdede
82 | btb[2]=BTBX
83 | 
84 | 
85 | for ((j=0;j<$runs;j=j+1)); do
86 |     for ((i=0;i<43;i=i+1)); do
87 | 	for ((k=0;k<3;k=k+1)); do
88 |             grep XXX ../results_50M/${bench[i]}.champsimtrace.xz-hashed_perceptron-${btb[k]}-${prefetch[j]}-next_line-spp_dev-no-lru-1core.txt > out_${bench[i]}_${prefetch[j]}_${btb[k]}
89 | 	    sed "s/XXX/${bench[i]} ${runName[j]}_${btb[k]}/g" out_${bench[i]}_${prefetch[j]}_${btb[k]} > Sout_${bench[i]}_${prefetch[j]}_${btb[k]}
90 | 	done
91 |     done
92 | done 
93 | 
94 | rm out_*
95 | cat Sout_* > all_res
96 | rm Sout_*
97 | 


--------------------------------------------------------------------------------
/tracer/makefile.rules:
--------------------------------------------------------------------------------
 1 | ##############################################################
 2 | #
 3 | # This file includes all the test targets as well as all the
 4 | # non-default build rules and test recipes.
 5 | #
 6 | ##############################################################
 7 | 
 8 | 
 9 | ##############################################################
10 | #
11 | # Test targets
12 | #
13 | ##############################################################
14 | 
15 | ###### Place all generic definitions here ######
16 | 
17 | # This defines tests which run tools of the same name.  This is simply for convenience to avoid
18 | # defining the test name twice (once in TOOL_ROOTS and again in TEST_ROOTS).
19 | # Tests defined here should not be defined in TOOL_ROOTS and TEST_ROOTS.
20 | TEST_TOOL_ROOTS := MyPinTool
21 | 
22 | # This defines the tests to be run that were not already defined in TEST_TOOL_ROOTS.
23 | TEST_ROOTS :=
24 | 
25 | # This defines a list of tests that should run in the "short" sanity. Tests in this list must also
26 | # appear either in the TEST_TOOL_ROOTS or the TEST_ROOTS list.
27 | # If the entire directory should be tested in sanity, assign TEST_TOOL_ROOTS and TEST_ROOTS to the
28 | # SANITY_SUBSET variable in the tests section below (see example in makefile.rules.tmpl).
29 | SANITY_SUBSET :=
30 | 
31 | # This defines the tools which will be run during the the tests, and were not already defined in
32 | # TEST_TOOL_ROOTS.
33 | TOOL_ROOTS :=
34 | 
35 | # This defines the static analysis tools which will be run during the the tests. They should not
36 | # be defined in TEST_TOOL_ROOTS. If a test with the same name exists, it should be defined in
37 | # TEST_ROOTS.
38 | # Note: Static analysis tools are in fact executables linked with the Pin Static Analysis Library.
39 | # This library provides a subset of the Pin APIs which allows the tool to perform static analysis
40 | # of an application or dll. Pin itself is not used when this tool runs.
41 | SA_TOOL_ROOTS :=
42 | 
43 | # This defines all the applications that will be run during the tests.
44 | APP_ROOTS :=
45 | 
46 | # This defines any additional object files that need to be compiled.
47 | OBJECT_ROOTS :=
48 | 
49 | # This defines any additional dlls (shared objects), other than the pintools, that need to be compiled.
50 | DLL_ROOTS :=
51 | 
52 | # This defines any static libraries (archives), that need to be built.
53 | LIB_ROOTS :=
54 | 
55 | 
56 | ##############################################################
57 | #
58 | # Test recipes
59 | #
60 | ##############################################################
61 | 
62 | # This section contains recipes for tests other than the default.
63 | # See makefile.default.rules for the default test rules.
64 | # All tests in this section should adhere to the naming convention: <testname>.test
65 | 
66 | 
67 | ##############################################################
68 | #
69 | # Build rules
70 | #
71 | ##############################################################
72 | 
73 | # This section contains the build rules for all binaries that have special build rules.
74 | # See makefile.default.rules for the default build rules.
75 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
 1 | <p align="center">
 2 |   <h1 align="center"> ChampSim </h1>
 3 |   <p> ChampSim is a trace-based simulator for a microarchitecture study. You can sign up to the public mailing list by sending an empty mail to champsim+subscribe@googlegroups.com. <p>
 4 | </p>
 5 | 
 6 | 
 7 | # Compile
 8 | 
 9 | Champsim needs to be compiled with three BTB designs (convBTB, pdede, and BTBX) and two instruction prefetchers (no, fdip).  
10 | 
11 | Important note on compilation: IFETCH_BUFFER needs to be 128 entries when compiling with “fdip” prefetcher and “FETCH_WIDTH*2” entries when compiling with “no” prefetcher. This is because of how instruction fetch is implemented in baseline Champsim. IFETCH_BUFFER size is defined in line 63 of /<Path_to_code>/inc/ooo_cpu.h 
12 | 
13 | Use the following commands to compile the code:
14 | 
15 | (First set “IFETCH_BUFFER” to “FETCH_WIDTH*2” in line 63 of /<Path_to_code>/inc/ooo_cpu.h)
16 | 
17 | ./build_champsim.sh hashed_perceptron convBTB no next_line spp_dev no lru 1
18 | 
19 | ./build_champsim.sh hashed_perceptron pdede no next_line spp_dev no lru 1
20 | 
21 | ./build_champsim.sh hashed_perceptron BTBX no next_line spp_dev no lru 1
22 | 
23 | 
24 | (Set “IFETCH_BUFFER” to “128” in line 63 of /<Path_to_code>/inc/ooo_cpu.h)
25 | 
26 | ./build_champsim.sh hashed_perceptron convBTB fdip next_line spp_dev no lru 1
27 | 
28 | ./build_champsim.sh hashed_perceptron pdede fdip next_line spp_dev no lru 1
29 | 
30 | ./build_champsim.sh hashed_perceptron BTBX fdip next_line spp_dev no lru 1
31 | 
32 | 
33 | # Download IPC-1 trace
34 | 
35 | The traces can be downloaded from https://drive.google.com/file/d/1qs8t8-YWc7lLoYbjbH_d3lf1xdoYBznf/view?usp=sharing
36 | 
37 | Once downloaded, place them in “<Path_to_code>/dpc3_traces/” directory.
38 | 
39 | # Generating configuration files
40 | 
41 | Go to directory /<Path_to_code>/launch/scripts/. In script file createConfig.sh, point PATH_TO_CHAMPSIM to <Path_to_code>. Run this script (./createConfig.sh) to generate config files needed by Champsim.
42 | 
43 | # Run simulation
44 | 
45 | Running all workloads: Go to directory /<Path_to_code>/launch/. In script file launch.sh, replace the line <cluster_launch_command_here> (line 64) with the command to run experiments on your cluster. A sample command is given that runs experiments on our cluster. Running this script (./launch.sh) will run simulations, and the stats will be stored in directory /<Path_to_code>/results_50M/.
46 | 
47 | Running a single workload: Use the following command (in directory /<Path_to_code>/) to run simulation for a single workload:
48 | 
49 | ./run_champsim.sh hashed_perceptron-BTBX-no-next_line-spp_dev-no-lru-1core 50 50 server_001.champsimtrace.xz
50 | 
51 | This command will simulate server_001 workload with BTBX and no instruction prefetching.
52 | 
53 | # Collecting results
54 | 
55 | Go to directory /<Path_to_code>/collectStats/. Run the script getResults.sh, and it will collect results from all workloads and save them in a file “all_res”.
56 | 
57 | # Plotting results
58 | 
59 | Download the “all_res” file. Open the provided excel file "BTBX_artifact_results.xlsx". Click on “Data” in MS-Excel top menu bar. Click on “Refresh All” in “Queries and Connections” ribbon, go to the folder where you stored “all_res” and double click on “all_res”. Now “Offset Distribution”, “MPKI”, and “Performance” sheets in the excel file should have plots for Figure 4, Figure 9, and Figure 10 respectively. 
60 | 
61 | # BTBX-HPCA23
62 | 


--------------------------------------------------------------------------------
/replacement/base_replacement.cc:
--------------------------------------------------------------------------------
  1 | #include "cache.h"
  2 | 
  3 | uint32_t CACHE::find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
  4 | {
  5 |     // baseline LRU replacement policy for other caches 
  6 |     return lru_victim(cpu, instr_id, set, current_set, ip, full_addr, type); 
  7 | }
  8 | 
  9 | void CACHE::update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
 10 | {
 11 |     if (type == WRITEBACK) {
 12 |         if (hit) // wrietback hit does not update LRU state
 13 |             return;
 14 |     }
 15 | 
 16 |     return lru_update(set, way);
 17 | }
 18 | 
 19 | uint32_t CACHE::lru_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
 20 | {
 21 |     uint32_t way = 0;
 22 | 
 23 |     // fill invalid line first
 24 |     for (way=0; way<NUM_WAY; way++) {
 25 |         if (block[set][way].valid == false) {
 26 | 
 27 |             DP ( if (warmup_complete[cpu]) {
 28 |             cout << "[" << NAME << "] " << __func__ << " instr_id: " << instr_id << " invalid set: " << set << " way: " << way;
 29 |             cout << hex << " address: " << (full_addr>>LOG2_BLOCK_SIZE) << " victim address: " << block[set][way].address << " data: " << block[set][way].data;
 30 |             cout << dec << " lru: " << block[set][way].lru << endl; });
 31 | 
 32 |             break;
 33 |         }
 34 |     }
 35 | 
 36 |     // LRU victim
 37 |     if (way == NUM_WAY) {
 38 |         for (way=0; way<NUM_WAY; way++) {
 39 |             if (block[set][way].lru == NUM_WAY-1) {
 40 | 
 41 |                 DP ( if (warmup_complete[cpu]) {
 42 |                 cout << "[" << NAME << "] " << __func__ << " instr_id: " << instr_id << " replace set: " << set << " way: " << way;
 43 |                 cout << hex << " address: " << (full_addr>>LOG2_BLOCK_SIZE) << " victim address: " << block[set][way].address << " data: " << block[set][way].data;
 44 |                 cout << dec << " lru: " << block[set][way].lru << endl; });
 45 | 
 46 |                 break;
 47 |             }
 48 |         }
 49 |     }
 50 | 
 51 |     if (way == NUM_WAY) {
 52 |         cerr << "[" << NAME << "] " << __func__ << " no victim! set: " << set << endl;
 53 |         assert(0);
 54 |     }
 55 | 
 56 |     return way;
 57 | }
 58 | 
 59 | void CACHE::lru_update(uint32_t set, uint32_t way)
 60 | {
 61 |     // update lru replacement state
 62 |     for (uint32_t i=0; i<NUM_WAY; i++) {
 63 |         if (block[set][i].lru < block[set][way].lru) {
 64 |             block[set][i].lru++;
 65 |         }
 66 |     }
 67 |     block[set][way].lru = 0; // promote to the MRU position
 68 | }
 69 | 
 70 | void CACHE::replacement_final_stats()
 71 | {
 72 | 
 73 | }
 74 | 
 75 | #ifdef NO_CRC2_COMPILE
 76 | void InitReplacementState()
 77 | {
 78 |     
 79 | }
 80 | 
 81 | uint32_t GetVictimInSet (uint32_t cpu, uint32_t set, const BLOCK *current_set, uint64_t PC, uint64_t paddr, uint32_t type)
 82 | {
 83 |     return 0;
 84 | }
 85 | 
 86 | void UpdateReplacementState (uint32_t cpu, uint32_t set, uint32_t way, uint64_t paddr, uint64_t PC, uint64_t victim_addr, uint32_t type, uint8_t hit)
 87 | {
 88 |     
 89 | }
 90 | 
 91 | void PrintStats_Heartbeat()
 92 | {
 93 |     
 94 | }
 95 | 
 96 | void PrintStats()
 97 | {
 98 | 
 99 | }
100 | #endif
101 | 


--------------------------------------------------------------------------------
/inc/champsim.h:
--------------------------------------------------------------------------------
  1 | #ifndef CHAMPSIM_H
  2 | #define CHAMPSIM_H
  3 | 
  4 | #include <stdio.h>
  5 | #include <stdint.h>
  6 | #include <stdlib.h>
  7 | #include <unistd.h>
  8 | #include <string.h>
  9 | #include <limits.h>
 10 | #include <time.h>
 11 | #include <assert.h>
 12 | #include <signal.h>
 13 | #include <sys/types.h>
 14 | 
 15 | #include <iostream>
 16 | #include <queue>
 17 | #include <map>
 18 | #include <random>
 19 | #include <string>
 20 | #include <iomanip>
 21 | #include <set>
 22 | #include <list>
 23 | 
 24 | // USEFUL MACROS
 25 | //#define DEBUG_PRINT
 26 | #define SANITY_CHECK
 27 | #define LLC_BYPASS
 28 | #define DRC_BYPASS
 29 | #define NO_CRC2_COMPILE
 30 | 
 31 | #ifdef DEBUG_PRINT
 32 | #define DP(x) x
 33 | #else
 34 | #define DP(x)
 35 | #endif
 36 | 
 37 | // CPU
 38 | #define NUM_CPUS 1
 39 | #define CPU_FREQ 4000
 40 | #define DRAM_IO_FREQ 3200
 41 | #define PAGE_SIZE 4096
 42 | #define LOG2_PAGE_SIZE 12
 43 | 
 44 | // CACHE
 45 | #define BLOCK_SIZE 64
 46 | #define LOG2_BLOCK_SIZE 6
 47 | #define MAX_READ_PER_CYCLE 8
 48 | #define MAX_FILL_PER_CYCLE 1
 49 | 
 50 | #define INFLIGHT 1
 51 | #define COMPLETED 2
 52 | 
 53 | #define FILL_L1    1
 54 | #define FILL_L2    2
 55 | #define FILL_LLC   4
 56 | #define FILL_DRC   8
 57 | #define FILL_DRAM 16
 58 | 
 59 | // DRAM
 60 | #define DRAM_CHANNELS 1      // default: assuming one DIMM per one channel 4GB * 1 => 4GB off-chip memory
 61 | #define LOG2_DRAM_CHANNELS 0
 62 | #define DRAM_RANKS 1         // 512MB * 8 ranks => 4GB per DIMM
 63 | #define LOG2_DRAM_RANKS 0
 64 | #define DRAM_BANKS 8         // 64MB * 8 banks => 512MB per rank
 65 | #define LOG2_DRAM_BANKS 3
 66 | #define DRAM_ROWS 65536      // 2KB * 32K rows => 64MB per bank
 67 | #define LOG2_DRAM_ROWS 16
 68 | #define DRAM_COLUMNS 128      // 64B * 32 column chunks (Assuming 1B DRAM cell * 8 chips * 8 transactions = 64B size of column chunks) => 2KB per row
 69 | #define LOG2_DRAM_COLUMNS 7
 70 | #define DRAM_ROW_SIZE (BLOCK_SIZE*DRAM_COLUMNS/1024)
 71 | 
 72 | #define DRAM_SIZE (DRAM_CHANNELS*DRAM_RANKS*DRAM_BANKS*DRAM_ROWS*DRAM_ROW_SIZE/1024) 
 73 | #define DRAM_PAGES ((DRAM_SIZE<<10)>>2) 
 74 | //#define DRAM_PAGES 10
 75 | 
 76 | using namespace std;
 77 | 
 78 | extern uint8_t warmup_complete[NUM_CPUS], 
 79 |                simulation_complete[NUM_CPUS], 
 80 |                all_warmup_complete, 
 81 |                all_simulation_complete,
 82 |                MAX_INSTR_DESTINATIONS,
 83 |                knob_cloudsuite,
 84 |                knob_low_bandwidth;
 85 | 
 86 | extern uint64_t current_core_cycle[NUM_CPUS], 
 87 |                 stall_cycle[NUM_CPUS], 
 88 |                 last_drc_read_mode, 
 89 |                 last_drc_write_mode,
 90 |                 drc_blocks;
 91 | 
 92 | extern queue <uint64_t> page_queue;
 93 | extern map <uint64_t, uint64_t> page_table, inverse_table, recent_page, unique_cl[NUM_CPUS];
 94 | extern uint64_t previous_ppage, num_adjacent_page, num_cl[NUM_CPUS], allocated_pages, num_page[NUM_CPUS], minor_fault[NUM_CPUS], major_fault[NUM_CPUS];
 95 | 
 96 | void print_stats();
 97 | uint64_t rotl64 (uint64_t n, unsigned int c),
 98 |          rotr64 (uint64_t n, unsigned int c),
 99 |   va_to_pa(uint32_t cpu, uint64_t instr_id, uint64_t va, uint64_t unique_vpage, uint8_t is_code);
100 | 
101 | // log base 2 function from efectiu
102 | int lg2(int n);
103 | 
104 | // smart random number generator
105 | class RANDOM {
106 |   public:
107 |     std::random_device rd;
108 |     std::mt19937_64 engine{rd()};
109 |     std::uniform_int_distribution<uint64_t> dist{0, 0xFFFFFFFFF}; // used to generate random physical page numbers
110 | 
111 |     RANDOM (uint64_t seed) {
112 |         engine.seed(seed);
113 |     }
114 | 
115 |     uint64_t draw_rand() {
116 |         return dist(engine);
117 |     };
118 | };
119 | extern uint64_t champsim_seed;
120 | #endif
121 | 


--------------------------------------------------------------------------------
/inc/dram_controller.h:
--------------------------------------------------------------------------------
  1 | #ifndef DRAM_H
  2 | #define DRAM_H
  3 | 
  4 | #include "memory_class.h"
  5 | 
  6 | // DRAM configuration
  7 | #define DRAM_CHANNEL_WIDTH 8 // 8B
  8 | #define DRAM_WQ_SIZE 64
  9 | #define DRAM_RQ_SIZE 64
 10 | 
 11 | #define tRP_DRAM_NANOSECONDS  12.5
 12 | #define tRCD_DRAM_NANOSECONDS 12.5
 13 | #define tCAS_DRAM_NANOSECONDS 12.5
 14 | 
 15 | // the data bus must wait this amount of time when switching between reads and writes, and vice versa
 16 | #define DRAM_DBUS_TURN_AROUND_TIME ((15*CPU_FREQ)/2000) // 7.5 ns 
 17 | extern uint32_t DRAM_MTPS, DRAM_DBUS_RETURN_TIME;
 18 | 
 19 | // these values control when to send out a burst of writes
 20 | #define DRAM_WRITE_HIGH_WM    ((DRAM_WQ_SIZE*7)>>3) // 7/8th
 21 | #define DRAM_WRITE_LOW_WM     ((DRAM_WQ_SIZE*3)>>2) // 6/8th
 22 | #define MIN_DRAM_WRITES_PER_SWITCH (DRAM_WQ_SIZE*1/4)
 23 | 
 24 | // DRAM
 25 | class MEMORY_CONTROLLER : public MEMORY {
 26 |   public:
 27 |     const string NAME;
 28 | 
 29 |     DRAM_ARRAY dram_array[DRAM_CHANNELS][DRAM_RANKS][DRAM_BANKS];
 30 |     uint64_t dbus_cycle_available[DRAM_CHANNELS], dbus_cycle_congested[DRAM_CHANNELS], dbus_congested[NUM_TYPES+1][NUM_TYPES+1];
 31 |     uint64_t bank_cycle_available[DRAM_CHANNELS][DRAM_RANKS][DRAM_BANKS];
 32 |     uint8_t  do_write, write_mode[DRAM_CHANNELS]; 
 33 |     uint32_t processed_writes, scheduled_reads[DRAM_CHANNELS], scheduled_writes[DRAM_CHANNELS];
 34 |     int fill_level;
 35 | 
 36 |     BANK_REQUEST bank_request[DRAM_CHANNELS][DRAM_RANKS][DRAM_BANKS];
 37 | 
 38 |     // queues
 39 |     PACKET_QUEUE WQ[DRAM_CHANNELS], RQ[DRAM_CHANNELS];
 40 | 
 41 |     // constructor
 42 |     MEMORY_CONTROLLER(string v1) : NAME (v1) {
 43 |         for (uint32_t i=0; i<NUM_TYPES+1; i++) {
 44 |             for (uint32_t j=0; j<NUM_TYPES+1; j++) {
 45 |                 dbus_congested[i][j] = 0;
 46 |             }
 47 |         }
 48 |         do_write = 0;
 49 |         processed_writes = 0;
 50 |         for (uint32_t i=0; i<DRAM_CHANNELS; i++) {
 51 |             dbus_cycle_available[i] = 0;
 52 |             dbus_cycle_congested[i] = 0;
 53 |             write_mode[i] = 0;
 54 |             scheduled_reads[i] = 0;
 55 |             scheduled_writes[i] = 0;
 56 | 
 57 |             for (uint32_t j=0; j<DRAM_RANKS; j++) {
 58 |                 for (uint32_t k=0; k<DRAM_BANKS; k++)
 59 |                     bank_cycle_available[i][j][k] = 0;
 60 |             }
 61 | 
 62 |             WQ[i].NAME = "DRAM_WQ" + to_string(i);
 63 |             WQ[i].SIZE = DRAM_WQ_SIZE;
 64 |             WQ[i].entry = new PACKET [DRAM_WQ_SIZE];
 65 | 
 66 |             RQ[i].NAME = "DRAM_RQ" + to_string(i);
 67 |             RQ[i].SIZE = DRAM_RQ_SIZE;
 68 |             RQ[i].entry = new PACKET [DRAM_RQ_SIZE];
 69 |         }
 70 | 
 71 |         fill_level = FILL_DRAM;
 72 |     };
 73 | 
 74 |     // destructor
 75 |     ~MEMORY_CONTROLLER() {
 76 | 
 77 |     };
 78 | 
 79 |     // functions
 80 |     int  add_rq(PACKET *packet),
 81 |          add_wq(PACKET *packet),
 82 |          add_pq(PACKET *packet);
 83 | 
 84 |     void return_data(PACKET *packet),
 85 |          operate(),
 86 |          increment_WQ_FULL(uint64_t address);
 87 | 
 88 |     uint32_t get_occupancy(uint8_t queue_type, uint64_t address),
 89 |              get_size(uint8_t queue_type, uint64_t address);
 90 | 
 91 |     void schedule(PACKET_QUEUE *queue), process(PACKET_QUEUE *queue),
 92 |          update_schedule_cycle(PACKET_QUEUE *queue),
 93 |          update_process_cycle(PACKET_QUEUE *queue),
 94 |          reset_remain_requests(PACKET_QUEUE *queue, uint32_t channel);
 95 | 
 96 |     uint32_t dram_get_channel(uint64_t address),
 97 |              dram_get_rank   (uint64_t address),
 98 |              dram_get_bank   (uint64_t address),
 99 |              dram_get_row    (uint64_t address),
100 |              dram_get_column (uint64_t address),
101 |              drc_check_hit (uint64_t address, uint32_t cpu, uint32_t channel, uint32_t rank, uint32_t bank, uint32_t row);
102 | 
103 |     uint64_t get_bank_earliest_cycle();
104 | 
105 |     int check_dram_queue(PACKET_QUEUE *queue, PACKET *packet);
106 | };
107 | 
108 | #endif
109 | 


--------------------------------------------------------------------------------
/replacement/drrip.llc_repl:
--------------------------------------------------------------------------------
  1 | #include "cache.h"
  2 | 
  3 | #define maxRRPV 3
  4 | #define NUM_POLICY 2
  5 | #define SDM_SIZE 32
  6 | #define TOTAL_SDM_SETS NUM_CPUS*NUM_POLICY*SDM_SIZE
  7 | #define BIP_MAX 32
  8 | #define PSEL_WIDTH 10
  9 | #define PSEL_MAX ((1<<PSEL_WIDTH)-1)
 10 | #define PSEL_THRS PSEL_MAX/2
 11 | 
 12 | uint32_t rrpv[LLC_SET][LLC_WAY],
 13 |          bip_counter = 0,
 14 |          PSEL[NUM_CPUS];
 15 | unsigned rand_sets[TOTAL_SDM_SETS];
 16 | 
 17 | void CACHE::llc_initialize_replacement()
 18 | {
 19 |     cout << "Initialize DRRIP state" << endl;
 20 | 
 21 |     for(int i=0; i<LLC_SET; i++) {
 22 |         for(int j=0; j<LLC_WAY; j++)
 23 |             rrpv[i][j] = maxRRPV;
 24 |     }
 25 | 
 26 |     // randomly selected sampler sets
 27 |     srand(time(NULL));
 28 |     unsigned long rand_seed = 1;
 29 |     unsigned long max_rand = 1048576;
 30 |     uint32_t my_set = LLC_SET;
 31 |     int do_again = 0;
 32 |     for (int i=0; i<TOTAL_SDM_SETS; i++) {
 33 |         do {
 34 |             do_again = 0;
 35 |             rand_seed = rand_seed * 1103515245 + 12345;
 36 |             rand_sets[i] = ((unsigned) ((rand_seed/65536) % max_rand)) % my_set;
 37 |             printf("Assign rand_sets[%d]: %u  LLC: %u\n", i, rand_sets[i], my_set);
 38 |             for (int j=0; j<i; j++) {
 39 |                 if (rand_sets[i] == rand_sets[j]) {
 40 |                     do_again = 1;
 41 |                     break;
 42 |                 }
 43 |             }
 44 |         } while (do_again);
 45 |         printf("rand_sets[%d]: %d\n", i, rand_sets[i]);
 46 |     }
 47 | 
 48 |     for (int i=0; i<NUM_CPUS; i++)
 49 |         PSEL[i] = 0;
 50 | }
 51 | 
 52 | int is_it_leader(uint32_t cpu, uint32_t set)
 53 | {
 54 |     uint32_t start = cpu * NUM_POLICY * SDM_SIZE,
 55 |              end = start + NUM_POLICY * SDM_SIZE;
 56 | 
 57 |     for (uint32_t i=start; i<end; i++)
 58 |         if (rand_sets[i] == set)
 59 |             return ((i - start) / SDM_SIZE);
 60 | 
 61 |     return -1;
 62 | }
 63 | 
 64 | // called on every cache hit and cache fill
 65 | void CACHE::llc_update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
 66 | {
 67 |     // do not update replacement state for writebacks
 68 |     if (type == WRITEBACK) {
 69 |         rrpv[set][way] = maxRRPV-1;
 70 |         return;
 71 |     }
 72 | 
 73 | 	// cache hit
 74 | 	if (hit) { 
 75 | 		rrpv[set][way] = 0; // for cache hit, DRRIP always promotes a cache line to the MRU position
 76 | 		return;
 77 | 	}
 78 | 
 79 | 	// cache miss
 80 |     int leader = is_it_leader(cpu, set);
 81 | 
 82 |     if (leader == -1) { // follower sets
 83 |         if (PSEL[cpu] > PSEL_THRS) { // follow BIP
 84 |             rrpv[set][way] = maxRRPV;
 85 | 
 86 |             bip_counter++;
 87 |             if (bip_counter == BIP_MAX)
 88 |                 bip_counter = 0;
 89 |             if (bip_counter == 0)
 90 |                 rrpv[set][way] = maxRRPV-1;
 91 |         } else // follow SRRIP
 92 |             rrpv[set][way] = maxRRPV-1;
 93 | 
 94 |     } else if (leader == 0) { // leader 0: BIP
 95 |         if (PSEL[cpu] > 0) PSEL[cpu]--;
 96 |         rrpv[set][way] = maxRRPV;
 97 | 
 98 |         bip_counter++;
 99 |         if (bip_counter == BIP_MAX) bip_counter = 0;
100 |         if (bip_counter == 0) rrpv[set][way] = maxRRPV-1;
101 | 
102 | 	} else if (leader == 1) { // leader 1: SRRIP 
103 |         if (PSEL[cpu] < PSEL_MAX) PSEL[cpu]++;
104 |         rrpv[set][way] = maxRRPV-1;
105 | 
106 |     } else // WE SHOULD NOT REACH HERE
107 |         assert(0);
108 | }
109 | 
110 | // find replacement victim
111 | uint32_t CACHE::llc_find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
112 | {
113 |     // look for the maxRRPV line
114 |     while (1)
115 |     {
116 |         for (int i=0; i<LLC_WAY; i++)
117 |             if (rrpv[set][i] == maxRRPV)
118 |                 return i;
119 | 
120 |         for (int i=0; i<LLC_WAY; i++)
121 |             rrpv[set][i]++;
122 |     }
123 | 
124 |     // WE SHOULD NOT REACH HERE
125 |     assert(0);
126 |     return 0;
127 | }
128 | 
129 | // use this function to print out your own stats at the end of simulation
130 | void CACHE::llc_replacement_final_stats()
131 | {
132 | 
133 | }
134 | 


--------------------------------------------------------------------------------
/prefetcher/ip_stride.l2c_pref:
--------------------------------------------------------------------------------
  1 | //
  2 | // From Data Prefetching Championship Simulator 2
  3 | // Seth Pugsley, seth.h.pugsley@intel.com
  4 | //
  5 | 
  6 | /*
  7 | 
  8 |   This file describes an Instruction Pointer-based (Program Counter-based) stride prefetcher.  
  9 |   The prefetcher detects stride patterns coming from the same IP, and then 
 10 |   prefetches additional cache lines.
 11 | 
 12 |   Prefetches are issued into the L2 or LLC depending on L2 MSHR occupancy.
 13 | 
 14 |  */
 15 | 
 16 | #include "cache.h"
 17 | 
 18 | #define IP_TRACKER_COUNT 1024
 19 | #define PREFETCH_DEGREE 3
 20 | 
 21 | class IP_TRACKER {
 22 |   public:
 23 |     // the IP we're tracking
 24 |     uint64_t ip;
 25 | 
 26 |     // the last address accessed by this IP
 27 |     uint64_t last_cl_addr;
 28 | 
 29 |     // the stride between the last two addresses accessed by this IP
 30 |     int64_t last_stride;
 31 | 
 32 |     // use LRU to evict old IP trackers
 33 |     uint32_t lru;
 34 | 
 35 |     IP_TRACKER () {
 36 |         ip = 0;
 37 |         last_cl_addr = 0;
 38 |         last_stride = 0;
 39 |         lru = 0;
 40 |     };
 41 | };
 42 | 
 43 | IP_TRACKER trackers[IP_TRACKER_COUNT];
 44 | 
 45 | void CACHE::l2c_prefetcher_initialize() 
 46 | {
 47 |     cout << "CPU " << cpu << " L2C IP-based stride prefetcher" << endl;
 48 |     for (int i=0; i<IP_TRACKER_COUNT; i++)
 49 |         trackers[i].lru = i;
 50 | }
 51 | 
 52 | uint32_t CACHE::l2c_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in)
 53 | {
 54 |     // check for a tracker hit
 55 |     uint64_t cl_addr = addr >> LOG2_BLOCK_SIZE;
 56 | 
 57 |     int index = -1;
 58 |     for (index=0; index<IP_TRACKER_COUNT; index++) {
 59 |         if (trackers[index].ip == ip)
 60 |             break;
 61 |     }
 62 | 
 63 |     // this is a new IP that doesn't have a tracker yet, so allocate one
 64 |     if (index == IP_TRACKER_COUNT) {
 65 | 
 66 |         for (index=0; index<IP_TRACKER_COUNT; index++) {
 67 |             if (trackers[index].lru == (IP_TRACKER_COUNT-1))
 68 |                 break;
 69 |         }
 70 | 
 71 |         trackers[index].ip = ip;
 72 |         trackers[index].last_cl_addr = cl_addr;
 73 |         trackers[index].last_stride = 0;
 74 | 
 75 |         //cout << "[IP_STRIDE] MISS index: " << index << " lru: " << trackers[index].lru << " ip: " << hex << ip << " cl_addr: " << cl_addr << dec << endl;
 76 | 
 77 |         for (int i=0; i<IP_TRACKER_COUNT; i++) {
 78 |             if (trackers[i].lru < trackers[index].lru)
 79 |                 trackers[i].lru++;
 80 |         }
 81 |         trackers[index].lru = 0;
 82 | 
 83 |         return metadata_in;
 84 |     }
 85 | 
 86 |     // sanity check
 87 |     // at this point we should know a matching tracker index
 88 |     if (index == -1)
 89 |         assert(0);
 90 | 
 91 |     // calculate the stride between the current address and the last address
 92 |     // this bit appears overly complicated because we're calculating
 93 |     // differences between unsigned address variables
 94 |     int64_t stride = 0;
 95 |     if (cl_addr > trackers[index].last_cl_addr)
 96 |         stride = cl_addr - trackers[index].last_cl_addr;
 97 |     else {
 98 |         stride = trackers[index].last_cl_addr - cl_addr;
 99 |         stride *= -1;
100 |     }
101 | 
102 |     //cout << "[IP_STRIDE] HIT  index: " << index << " lru: " << trackers[index].lru << " ip: " << hex << ip << " cl_addr: " << cl_addr << dec << " stride: " << stride << endl;
103 | 
104 |     // don't do anything if we somehow saw the same address twice in a row
105 |     if (stride == 0)
106 |         return metadata_in;
107 | 
108 |     // only do any prefetching if there's a pattern of seeing the same
109 |     // stride more than once
110 |     if (stride == trackers[index].last_stride) {
111 | 
112 |         // do some prefetching
113 |         for (int i=0; i<PREFETCH_DEGREE; i++) {
114 |             uint64_t pf_address = (cl_addr + (stride*(i+1))) << LOG2_BLOCK_SIZE;
115 | 
116 |             // only issue a prefetch if the prefetch address is in the same 4 KB page 
117 |             // as the current demand access address
118 |             if ((pf_address >> LOG2_PAGE_SIZE) != (addr >> LOG2_PAGE_SIZE))
119 |                 break;
120 | 
121 |             // check the MSHR occupancy to decide if we're going to prefetch to the L2 or LLC
122 |             if (MSHR.occupancy < (MSHR.SIZE>>1))
123 | 	      prefetch_line(ip, addr, pf_address, FILL_L2, 0);
124 |             else
125 | 	      prefetch_line(ip, addr, pf_address, FILL_LLC, 0);
126 |         }
127 |     }
128 | 
129 |     trackers[index].last_cl_addr = cl_addr;
130 |     trackers[index].last_stride = stride;
131 | 
132 |     for (int i=0; i<IP_TRACKER_COUNT; i++) {
133 |         if (trackers[i].lru < trackers[index].lru)
134 |             trackers[i].lru++;
135 |     }
136 |     trackers[index].lru = 0;
137 | 
138 |     return metadata_in;
139 | }
140 | 
141 | uint32_t CACHE::l2c_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
142 | {
143 |   return metadata_in;
144 | }
145 | 
146 | void CACHE::l2c_prefetcher_final_stats()
147 | {
148 |     cout << "CPU " << cpu << " L2C PC-based stride prefetcher final stats" << endl;
149 | }
150 | 


--------------------------------------------------------------------------------
/inc/spp_dev.h:
--------------------------------------------------------------------------------
  1 | #ifndef SPP_H
  2 | #define SPP_H
  3 | 
  4 | // SPP functional knobs
  5 | #define LOOKAHEAD_ON
  6 | #define FILTER_ON
  7 | #define GHR_ON
  8 | #define SPP_SANITY_CHECK
  9 | 
 10 | //#define SPP_DEBUG_PRINT
 11 | #ifdef SPP_DEBUG_PRINT
 12 | #define SPP_DP(x) x
 13 | #else
 14 | #define SPP_DP(x)
 15 | #endif
 16 | 
 17 | // Signature table parameters
 18 | #define ST_SET 1
 19 | #define ST_WAY 256
 20 | #define ST_TAG_BIT 16
 21 | #define ST_TAG_MASK ((1 << ST_TAG_BIT) - 1)
 22 | #define SIG_SHIFT 3
 23 | #define SIG_BIT 12
 24 | #define SIG_MASK ((1 << SIG_BIT) - 1)
 25 | #define SIG_DELTA_BIT 7
 26 | 
 27 | // Pattern table parameters
 28 | #define PT_SET 512
 29 | #define PT_WAY 4
 30 | #define C_SIG_BIT 4
 31 | #define C_DELTA_BIT 4
 32 | #define C_SIG_MAX ((1 << C_SIG_BIT) - 1)
 33 | #define C_DELTA_MAX ((1 << C_DELTA_BIT) - 1)
 34 | 
 35 | // Prefetch filter parameters
 36 | #define QUOTIENT_BIT  10
 37 | #define REMAINDER_BIT 6
 38 | #define HASH_BIT (QUOTIENT_BIT + REMAINDER_BIT + 1)
 39 | #define FILTER_SET (1 << QUOTIENT_BIT)
 40 | #define FILL_THRESHOLD 90
 41 | #define PF_THRESHOLD 25
 42 | 
 43 | // Global register parameters
 44 | #define GLOBAL_COUNTER_BIT 10
 45 | #define GLOBAL_COUNTER_MAX ((1 << GLOBAL_COUNTER_BIT) - 1) 
 46 | #define MAX_GHR_ENTRY 8
 47 | 
 48 | enum FILTER_REQUEST {SPP_L2C_PREFETCH, SPP_LLC_PREFETCH, L2C_DEMAND, L2C_EVICT}; // Request type for prefetch filter
 49 | uint64_t get_hash(uint64_t key);
 50 | 
 51 | class SIGNATURE_TABLE {
 52 |   public:
 53 |     bool     valid[ST_SET][ST_WAY];
 54 |     uint32_t tag[ST_SET][ST_WAY],
 55 |              last_offset[ST_SET][ST_WAY],
 56 |              sig[ST_SET][ST_WAY],
 57 |              lru[ST_SET][ST_WAY];
 58 | 
 59 |     SIGNATURE_TABLE() {
 60 |         cout << "Initialize SIGNATURE TABLE" << endl;
 61 |         cout << "ST_SET: " << ST_SET << endl;
 62 |         cout << "ST_WAY: " << ST_WAY << endl;
 63 |         cout << "ST_TAG_BIT: " << ST_TAG_BIT << endl;
 64 |         cout << "ST_TAG_MASK: " << hex << ST_TAG_MASK << dec << endl;
 65 | 
 66 |         for (uint32_t set = 0; set < ST_SET; set++)
 67 |             for (uint32_t way = 0; way < ST_WAY; way++) {
 68 |                 valid[set][way] = 0;
 69 |                 tag[set][way] = 0;
 70 |                 last_offset[set][way] = 0;
 71 |                 sig[set][way] = 0;
 72 |                 lru[set][way] = way;
 73 |             }
 74 |     };
 75 | 
 76 |     void read_and_update_sig(uint64_t page, uint32_t page_offset, uint32_t &last_sig, uint32_t &curr_sig, int32_t &delta);
 77 | };
 78 | 
 79 | class PATTERN_TABLE {
 80 |   public:
 81 |     int      delta[PT_SET][PT_WAY];
 82 |     uint32_t c_delta[PT_SET][PT_WAY],
 83 |              c_sig[PT_SET];
 84 | 
 85 |     PATTERN_TABLE() {
 86 |         cout << endl << "Initialize PATTERN TABLE" << endl;
 87 |         cout << "PT_SET: " << PT_SET << endl;
 88 |         cout << "PT_WAY: " << PT_WAY << endl;
 89 |         cout << "SIG_DELTA_BIT: " << SIG_DELTA_BIT << endl;
 90 |         cout << "C_SIG_BIT: " << C_SIG_BIT << endl;
 91 |         cout << "C_DELTA_BIT: " << C_DELTA_BIT << endl;
 92 | 
 93 |         for (uint32_t set = 0; set < PT_SET; set++) {
 94 |             for (uint32_t way = 0; way < PT_WAY; way++) {
 95 |                 delta[set][way] = 0;
 96 |                 c_delta[set][way] = 0;
 97 |             }
 98 |             c_sig[set] = 0;
 99 |         }
100 |     }
101 | 
102 |     void update_pattern(uint32_t last_sig, int curr_delta),
103 |          read_pattern(uint32_t curr_sig, int *prefetch_delta, uint32_t *confidence_q, uint32_t &lookahead_way, uint32_t &lookahead_conf, uint32_t &pf_q_tail, uint32_t &depth);
104 | };
105 | 
106 | class PREFETCH_FILTER {
107 |   public:
108 |     uint64_t remainder_tag[FILTER_SET];
109 |     bool     valid[FILTER_SET],  // Consider this as "prefetched"
110 |              useful[FILTER_SET]; // Consider this as "used"
111 | 
112 |     PREFETCH_FILTER() {
113 |         cout << endl << "Initialize PREFETCH FILTER" << endl;
114 |         cout << "FILTER_SET: " << FILTER_SET << endl;
115 | 
116 |         for (uint32_t set = 0; set < FILTER_SET; set++) {
117 |             remainder_tag[set] = 0;
118 |             valid[set] = 0;
119 |             useful[set] = 0;
120 |         }
121 | 
122 |     }
123 | 
124 |     bool     check(uint64_t pf_addr, FILTER_REQUEST filter_request);
125 | };
126 | 
127 | class GLOBAL_REGISTER {
128 |   public:
129 |     // Global counters to calculate global prefetching accuracy
130 |     uint64_t pf_useful,
131 |              pf_issued,
132 |              global_accuracy; // Alpha value in Section III. Equation 3
133 | 
134 |     // Global History Register (GHR) entries
135 |     uint8_t  valid[MAX_GHR_ENTRY];
136 |     uint32_t sig[MAX_GHR_ENTRY],
137 |              confidence[MAX_GHR_ENTRY],
138 |              offset[MAX_GHR_ENTRY];
139 |     int      delta[MAX_GHR_ENTRY];
140 | 
141 |     GLOBAL_REGISTER() {
142 |         pf_useful = 0;
143 |         pf_issued = 0;
144 |         global_accuracy = 0;
145 | 
146 |         for (uint32_t i = 0; i < MAX_GHR_ENTRY; i++) {
147 |             valid[i] = 0;
148 |             sig[i] = 0;
149 |             confidence[i] = 0;
150 |             offset[i] = 0;
151 |             delta[i] = 0;
152 |         }
153 |     }
154 | 
155 |     void update_entry(uint32_t pf_sig, uint32_t pf_confidence, uint32_t pf_offset, int pf_delta);
156 |     uint32_t check_entry(uint32_t page_offset);
157 | };
158 | 
159 | #endif
160 | 


--------------------------------------------------------------------------------
/src/block.cc:
--------------------------------------------------------------------------------
  1 | #include "block.h"
  2 | 
  3 | int PACKET_QUEUE::check_queue(PACKET *packet)
  4 | {
  5 |     if ((head == tail) && occupancy == 0)
  6 |         return -1;
  7 | 
  8 |     if (head < tail) {
  9 |         for (uint32_t i=head; i<tail; i++) {
 10 |             if (NAME == "L1D_WQ") {
 11 |                 if (entry[i].full_addr == packet->full_addr) {
 12 |                     DP (if (warmup_complete[packet->cpu]) {
 13 |                     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id << " same address: " << hex << packet->address;
 14 |                     cout << " full_addr: " << packet->full_addr << dec << " by instr_id: " << entry[i].instr_id << " index: " << i;
 15 |                     cout << " cycle " << packet->event_cycle << endl; });
 16 |                     return i;
 17 |                 }
 18 |             }
 19 |             else {
 20 |                 if (entry[i].address == packet->address) {
 21 |                     DP (if (warmup_complete[packet->cpu]) {
 22 |                     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id << " same address: " << hex << packet->address;
 23 |                     cout << " full_addr: " << packet->full_addr << dec << " by instr_id: " << entry[i].instr_id << " index: " << i;
 24 |                     cout << " cycle " << packet->event_cycle << endl; });
 25 |                     return i;
 26 |                 }
 27 |             }
 28 |         }
 29 |     }
 30 |     else {
 31 |         for (uint32_t i=head; i<SIZE; i++) {
 32 |             if (NAME == "L1D_WQ") {
 33 |                 if (entry[i].full_addr == packet->full_addr) {
 34 |                     DP (if (warmup_complete[packet->cpu]) {
 35 |                     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id << " same address: " << hex << packet->address;
 36 |                     cout << " full_addr: " << packet->full_addr << dec << " by instr_id: " << entry[i].instr_id << " index: " << i;
 37 |                     cout << " cycle " << packet->event_cycle << endl; });
 38 |                     return i;
 39 |                 }
 40 |             }
 41 |             else {
 42 |                 if (entry[i].address == packet->address) {
 43 |                     DP (if (warmup_complete[packet->cpu]) {
 44 |                     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id << " same address: " << hex << packet->address;
 45 |                     cout << " full_addr: " << packet->full_addr << dec << " by instr_id: " << entry[i].instr_id << " index: " << i;
 46 |                     cout << " cycle " << packet->event_cycle << endl; });
 47 |                     return i;
 48 |                 }
 49 |             }
 50 |         }
 51 |         for (uint32_t i=0; i<tail; i++) {
 52 |             if (NAME == "L1D_WQ") {
 53 |                 if (entry[i].full_addr == packet->full_addr) {
 54 |                     DP (if (warmup_complete[packet->cpu]) {
 55 |                     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id << " same address: " << hex << packet->address;
 56 |                     cout << " full_addr: " << packet->full_addr << dec << " by instr_id: " << entry[i].instr_id << " index: " << i;
 57 |                     cout << " cycle " << packet->event_cycle << endl; });
 58 |                     return i;
 59 |                 }
 60 |             }
 61 |             else {
 62 |                 if (entry[i].address == packet->address) {
 63 |                     DP (if (warmup_complete[packet->cpu]) {
 64 |                     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id << " same address: " << hex << packet->address;
 65 |                     cout << " full_addr: " << packet->full_addr << dec << " by instr_id: " << entry[i].instr_id << " index: " << i;
 66 |                     cout << " cycle " << packet->event_cycle << endl; });
 67 |                     return i;
 68 |                 }
 69 |             }
 70 |         }
 71 |     }
 72 | 
 73 |     return -1;
 74 | }
 75 | 
 76 | void PACKET_QUEUE::add_queue(PACKET *packet)
 77 | {
 78 | #ifdef SANITY_CHECK
 79 |     if (occupancy && (head == tail))
 80 |         assert(0);
 81 | #endif
 82 | 
 83 |     // add entry
 84 |     entry[tail] = *packet;
 85 | 
 86 |     DP ( if (warmup_complete[packet->cpu]) {
 87 |     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id;
 88 |     cout << " address: " << hex << entry[tail].address << " full_addr: " << entry[tail].full_addr << dec;
 89 |     cout << " head: " << head << " tail: " << tail << " occupancy: " << occupancy << " event_cycle: " << entry[tail].event_cycle << endl; });
 90 | 
 91 |     occupancy++;
 92 |     tail++;
 93 |     if (tail >= SIZE)
 94 |         tail = 0;
 95 | }
 96 | 
 97 | void PACKET_QUEUE::remove_queue(PACKET *packet)
 98 | {
 99 | #ifdef SANITY_CHECK
100 |     if ((occupancy == 0) && (head == tail))
101 |         assert(0);
102 | #endif
103 | 
104 |     DP ( if (warmup_complete[packet->cpu]) {
105 |     cout << "[" << NAME << "] " << __func__ << " cpu: " << packet->cpu << " instr_id: " << packet->instr_id;
106 |     cout << " address: " << hex << packet->address << " full_addr: " << packet->full_addr << dec << " fill_level: " << packet->fill_level;
107 |     cout << " head: " << head << " tail: " << tail << " occupancy: " << occupancy << " event_cycle: " << packet->event_cycle << endl; });
108 | 
109 |     // reset entry
110 |     PACKET empty_packet;
111 |     *packet = empty_packet;
112 | 
113 |     occupancy--;
114 |     head++;
115 |     if (head >= SIZE)
116 |         head = 0;
117 | }
118 | 


--------------------------------------------------------------------------------
/prefetcher/fdip.l1i_pref:
--------------------------------------------------------------------------------
  1 | #include "ooo_cpu.h"
  2 | #include <stack>
  3 | #include <algorithm>
  4 | #include <math.h>
  5 | 
  6 | 
  7 | /**************************************** Basic Structures **************************************/
  8 | 
  9 | #define MAX_PFETCHQ_ENTRIES 48
 10 | #define MAX_RECENT_PFETCH 10
 11 | 
 12 | 
 13 | /**************************************** Compoenets for prefetching **************************************/
 14 | 
 15 | std::deque<uint64_t> prefetch_queue;	//Storage: 64-bits * 48 (queue size) = 384 bytes
 16 | std::deque<uint64_t> prefetch_queue_spec;	//Storage: 64-bits * 48 (queue size) = 384 bytes
 17 | std::deque<uint64_t> recent_prefetches;	//Storage: 64-bits * 10 (queue size) = 80 bytes
 18 | uint64_t disp[66] = {0};
 19 | uint64_t lowBits[66] = {0};
 20 | 
 21 | /**************************************** Prefetcher Operation **************************************/
 22 | 
 23 | 
 24 | 
 25 | void O3_CPU::l1i_prefetcher_initialize() 
 26 | {
 27 | 
 28 | }
 29 | 
 30 | void O3_CPU::l1i_prefetcher_instruction_operate(uint64_t ip)
 31 | {
 32 | 	prefetch_queue_spec.clear();
 33 | 	uint64_t block_addr = ((ip >> LOG2_BLOCK_SIZE) << LOG2_BLOCK_SIZE);
 34 |         if (block_addr == 0)
 35 |                 return;
 36 | 
 37 | 	std::deque<uint64_t>::iterator it = std::find(prefetch_queue.begin(), prefetch_queue.end(), block_addr);
 38 | 	if (it == prefetch_queue.end()) {
 39 | 		std::deque<uint64_t>::iterator it1 = std::find(recent_prefetches.begin(), recent_prefetches.end(), block_addr);
 40 | 		if (it1 == recent_prefetches.end()) {
 41 | 			prefetch_queue.push_back(block_addr);
 42 | 		}
 43 | 	}
 44 | }
 45 | 
 46 | void O3_CPU::l1i_prefetcher_instruction_spec_operate(uint64_t ip)
 47 | {
 48 | 	uint64_t block_addr = ((ip >> LOG2_BLOCK_SIZE) << LOG2_BLOCK_SIZE);
 49 | 	if (block_addr == 0)
 50 | 		return;
 51 | 
 52 | 	std::deque<uint64_t>::iterator it = std::find(prefetch_queue.begin(), prefetch_queue.end(), block_addr);
 53 | 	if (it == prefetch_queue.end()) {
 54 | 		std::deque<uint64_t>::iterator it1 = std::find(recent_prefetches.begin(), recent_prefetches.end(), block_addr);
 55 | 		if (it1 == recent_prefetches.end()) {
 56 | 			std::deque<uint64_t>::iterator it2 = std::find(prefetch_queue_spec.begin(), prefetch_queue_spec.end(), block_addr);
 57 | 			if (it2 == prefetch_queue_spec.end()) {
 58 | 				prefetch_queue_spec.push_back(block_addr);
 59 | 			}
 60 | 		}
 61 | 	}
 62 | }
 63 | 
 64 | void O3_CPU::l1i_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
 65 | {
 66 |         if (branch_target && branch_type != BRANCH_RETURN) {
 67 |                 /*Find the number of bits needed to encode the target offset*/
 68 |                 uint64_t target_offset; 
 69 |                 if (branch_target > ip) {
 70 |                         target_offset = branch_target - ip;
 71 |                 } else {
 72 |                         target_offset = ip - branch_target;
 73 |                 }
 74 | 
 75 | 		int num_bits = 0;
 76 | 	        if (target_offset) {
 77 |                 	num_bits = (int)(log2((double)target_offset));
 78 |                 	/* The cast "(int)log2" rounds down to lower integer, however we want to round it to upper integer, so add 1 to "num_bits"
 79 |                  	* As an offset can be both positive and negative, we need to add 1 sign bit to "num_bits".
 80 |                  	* */
 81 | 		}
 82 | 
 83 |                 //num_bits += 2; //Not needed if the distance/displacement is in 4 byte instructions instead of bytes
 84 | 
 85 | /**********************************************************************************************************************/
 86 |                 uint64_t diff_bits = (branch_target >> 2) ^ (ip >> 2);
 87 |                 int num_lower_bits = 0;
 88 |                 while (diff_bits != 0) {
 89 |                         diff_bits = diff_bits >> 1;
 90 |                         num_lower_bits++;
 91 |                 }
 92 |                 //cout << "Target " << hex << branch_target << " ip " << ip << " num_bits " << dec << num_bits << " num_lower_bits " << num_lower_bits << endl;
 93 | 
 94 |                 if ((num_bits - 3) > num_lower_bits) {
 95 | 			cout << "Target " << hex << branch_target << " ip " << ip << " num_bits " << dec << num_bits << " num_lower_bits " << num_lower_bits << endl;
 96 |                         cout << "This is wierd" << endl;
 97 |                         assert(0);
 98 |                 }
 99 | 
100 | /*********************************************************************************************************************/
101 | 		//if (branch_type != BRANCH_RETURN) {
102 |                     disp[num_bits]++;
103 | 		    lowBits[num_lower_bits]++;
104 | 		//}
105 |                 assert(num_bits >= 0 && num_bits < 66);
106 | 
107 |         }
108 | 	if (branch_type == BRANCH_RETURN) {
109 | 		    disp[0]++;
110 |                     lowBits[0]++;
111 | 	}
112 | }
113 | 
114 | void O3_CPU::l1i_prefetcher_cache_operate(uint64_t v_addr, uint8_t cache_hit, uint8_t prefetch_hit)
115 | {
116 |   if((cache_hit == 0) && (L1I.MSHR.occupancy < (L1I.MSHR.SIZE>>1)))
117 |     {
118 |       uint64_t pf_addr = v_addr + (1<<LOG2_BLOCK_SIZE);
119 |       prefetch_code_line(pf_addr);
120 |     }
121 | }
122 | 
123 | void O3_CPU::l1i_prefetcher_cycle_operate()
124 | {
125 | 
126 | 	/*Issue prefetches*/
127 | 
128 | 	if (prefetch_queue.size()) {
129 | 		if (L1I.MSHR.occupancy < (L1I.MSHR.SIZE>>1) && L1I.PQ.occupancy < L1I.PQ.SIZE) {
130 | 			prefetch_code_line(prefetch_queue.front());
131 | 			recent_prefetches.push_back(prefetch_queue.front());
132 | 			if (recent_prefetches.size() > MAX_RECENT_PFETCH) {
133 | 				recent_prefetches.pop_front();
134 | 			}
135 | 	
136 | 			prefetch_queue.pop_front();
137 | 		}
138 | 	} else if (prefetch_queue_spec.size()) {
139 | 			if (L1I.MSHR.occupancy < (L1I.MSHR.SIZE>>1) && L1I.PQ.occupancy < L1I.PQ.SIZE) {
140 | 			prefetch_code_line(prefetch_queue_spec.front());
141 | 			recent_prefetches.push_back(prefetch_queue_spec.front());
142 | 			if (recent_prefetches.size() > MAX_RECENT_PFETCH) {
143 | 				recent_prefetches.pop_front();
144 | 			}
145 | 	
146 | 			prefetch_queue_spec.pop_front();
147 | 		}
148 | 	}	
149 | }
150 | 
151 | void O3_CPU::l1i_prefetcher_cache_fill(uint64_t v_addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_v_addr)
152 | {
153 | 
154 | }
155 | 
156 | void O3_CPU::l1i_prefetcher_final_stats()
157 | {
158 |         for(int i = 0; i < 66; i++) {
159 |                 cout << "XXX disp-" << i << " " << disp[i] << endl;
160 |         }
161 | 
162 |         for(int i = 0; i < 66; i++) {
163 |                 cout << "XXX diffBits-" << i << " " << lowBits[i] << endl;
164 |         }
165 | }
166 | 


--------------------------------------------------------------------------------
/inc/set.h:
--------------------------------------------------------------------------------
  1 | /*
  2 |  * This file defines a specalized bitset data structure that uses 64 bit
  3 |  * words to store bits in a set, but does something special for small
  4 |  * sets to make it faster.
  5 |  */
  6 | 
  7 | #ifndef __SET_H
  8 | #define __SET_H
  9 | #include <stdio.h>
 10 | #include <stdlib.h>
 11 | #include <assert.h>
 12 | #include <string.h>
 13 | 
 14 | #define TYPE	unsigned short int
 15 | //#define MAX_SIZE	ROB_SIZE
 16 | // sethpugsley - changed this from ROB_SIZE to allow for non-power-of-2 ROB sizes, like real CPUs have
 17 | // but MAX_SIZE here still requires a power-of-2 number
 18 | #define MAX_SIZE	512
 19 | 
 20 | // tuned empirically
 21 | 
 22 | #define SMALL_SIZE	13
 23 | #define SMALLER_SIZE	6
 24 | 
 25 | class fastset {
 26 | 	union {
 27 | 		// values for a small set
 28 | 		TYPE 
 29 | 			values[SMALL_SIZE];
 30 | 
 31 | 		// the bits representing the set
 32 | 		unsigned long long int 
 33 | 			bits[MAX_SIZE/64];
 34 | 	} data;
 35 | 
 36 | 	int
 37 | 		card;		// cardinality of small set
 38 | 
 39 | 	// set a bit in the bits
 40 | 
 41 | 	void setbit (TYPE x) {
 42 | 		int word = x >> 6;
 43 | 		int bit = x & 63;
 44 | 		data.bits[word] |= 1ull << bit;
 45 | 	}
 46 | 
 47 | 	// get one of the bits
 48 | 
 49 | 	bool getbit (TYPE x) {
 50 | 		int word = x >> 6;
 51 | 		int bit = x & 63;
 52 | 		return (data.bits[word] >> bit) & 1;
 53 | 	}
 54 | 
 55 | 	// insert an item into a small set
 56 | 
 57 | 	void insert_small (TYPE x) {
 58 | 		int i;
 59 | 		for (i=0; i<card; i++) {
 60 | 			TYPE y = data.values[i];
 61 | 			if (y == x) return;
 62 | 			if (y > x) break;
 63 | 		}
 64 | 		// x belongs in i; move everything from v[i] through v[n-1]
 65 | 		// to v[i+1] through v[n]
 66 | 		for (int j=card-1; j>=i; j--) data.values[j+1] = data.values[j];
 67 | 		// the loop seems a little faster than memmove
 68 | 		//memmove (&data.values[i+1], &data.values[i], (sizeof (TYPE) * (card-i)));
 69 | 		data.values[i] = x;
 70 | 		card++;
 71 | 	}
 72 | 
 73 | 
 74 | 	// do a linear search in a small set
 75 | 
 76 | 	bool search_small_linear (TYPE x) {
 77 | 		for (int i=0; i<card; i++) {
 78 | 			TYPE y = data.values[i];
 79 | 			if (y > x) return false;
 80 | 			if (y == x) return true;
 81 | 		}
 82 | 		return false;
 83 | 	}
 84 | 
 85 | 
 86 | 	// search a small set, specializing for the set size
 87 | 
 88 | 	bool search_small (TYPE x) {
 89 | 
 90 | 		// no elements? we're done.
 91 | 
 92 | 		if (!card) return false;
 93 | 
 94 | 		// below a certain size linear search is faster
 95 | 
 96 | 		if (card < SMALLER_SIZE) return search_small_linear (x);
 97 | 
 98 | 		// do a binary search for the item
 99 | 
100 | 		int begin = 0;
101 | 		int end = card-1;
102 | 		int middle = end/2;
103 | 		for (;;) {
104 | 			TYPE y = data.values[middle];
105 | 			if (x < y) {
106 | 				end = middle-1;
107 | 			} else if (x > y) {
108 | 				begin = middle+1;
109 | 			} else return true;
110 | 			if (end < begin) break;
111 | 			middle = (begin + end) / 2;
112 | 			// assert (middle < card && middle >= 0);
113 | 		}
114 | 		return false;
115 | 	}
116 | 
117 | 	// convert a small set into a bitset
118 | 
119 | 	void smalltobit (void) {
120 | 
121 | 		// we have to use a temporary array to hold the small set contents
122 | 		// because the small set and bitset occupy the same memory 
123 | 	
124 | 		TYPE tmp[SMALL_SIZE];
125 | 		memcpy (tmp, data.values, sizeof (TYPE) * card);
126 | 		memset (data.bits, 0, sizeof (data.bits));
127 | 		for (int i=0; i<card; i++) setbit (tmp[i]);
128 | 	}
129 | 
130 | public:
131 | 
132 | 	// constructor
133 | 
134 | 	fastset (void) { card = 0; }
135 | 
136 | 	// destructor
137 | 
138 | 	~fastset (void) { }
139 | 
140 | 	// insert a value into the set
141 | 
142 | 	void insert (TYPE x) {
143 | 		//assert (x < MAX_SIZE);
144 | 
145 | 		// if the set is empty...
146 | 		if (!card) {
147 | 			// now it has a single value
148 | 
149 | 			data.values[card++] = x;
150 | 
151 | 			// and we're done
152 | 
153 | 			return;
154 | 		} 
155 | 
156 | 		// if the set is small
157 | 
158 | 		if (card < SMALL_SIZE) {
159 | 			insert_small (x);
160 | 			if (card == SMALL_SIZE) smalltobit ();
161 | 		} else
162 | 
163 | 		// set the value
164 | 		setbit (x);
165 | 	}
166 | 
167 | 	// search the set for a value
168 | 
169 | 	bool search (TYPE x) {
170 | 		//assert (x < MAX_SIZE);
171 | 
172 | 		// empty?
173 | 		if (!card) return false;
174 | 
175 | 		// singleton?
176 | 		if (card == 1) return data.values[0] == x;
177 | 
178 | 		// small?
179 | 		if (card < SMALL_SIZE) return search_small (x);
180 | 
181 | 		// none of those; extract the bit
182 | 
183 | 		return getbit (x);
184 | 	}
185 | 
186 | 	// this set becomes the union of itself and the other set
187 | 	// (call it "join" because "union" is a C++ keyword)
188 | 
189 | 	void join (fastset & other, int n) {
190 | 
191 | 		// special rules for special sets
192 | 
193 | 		if (!other.card) return;
194 | 
195 | 		if (other.card < SMALL_SIZE) {
196 | 			// not too many values in other; just insert them one by one
197 | 
198 | 			for (int i=0; i<other.card; i++) insert (other.data.values[i]);
199 | 			return;
200 | 		} else if (card < SMALL_SIZE) {
201 | 			// here, we know that other is not small, so we
202 | 			// know we're going to end up with this as a bit
203 | 			// set, so just make it a bit set now and fall 
204 | 			// through to the bitwise ANDing
205 | 			smalltobit ();
206 | 			card = SMALL_SIZE; // fake
207 | 			assert (other.card >= SMALL_SIZE);
208 | 		}
209 | 
210 | 		// lim is the next multiple of 64
211 | 
212 | 		int lim = ((n | 63) + 1) / 64;
213 | 
214 | 		// bitwise OR the other bits into this set
215 | 		for (int i=0; i<lim; i++) data.bits[i] |= other.data.bits[i];
216 | 	}
217 | 
218 | 	// expand the entire set into the array v, returning the cardinality
219 | 
220 | 	int expand (TYPE v[], int n) {
221 | 		if (!card) return 0;
222 | 
223 | 		// a small set can just be copied
224 | 
225 | 		if (card < SMALL_SIZE) {
226 | 			for (int i=0; i<card; i++) v[i] = data.values[i];
227 | 			return card;
228 | 		}
229 | 
230 | 		// go through the bit array looking for elements
231 | 
232 | 		int k = 0;
233 | 		TYPE i;
234 | 		for (i=0; i<n; i+=64) {
235 | 
236 | 			// if this 64 bit subset is not empty, copy it into v
237 | 
238 | 			if (data.bits[i/64]) {
239 | 				for (TYPE j=0; j<64; j++) {
240 | 					TYPE l = i + j;
241 | 					if (l < n) {
242 | 						if (getbit (l)) v[k++] = l;
243 | 					} else break;
244 | 				}
245 | 			}
246 | 		}
247 | 		return k;
248 | 	}
249 | };
250 | 
251 | // this little macro iterates over either the whole set or just the single member
252 | 
253 | #define ITERATE_SET(i,a,n) \
254 | 	TYPE expand_##i[n+1]; \
255 | 	int card_##i = (a).expand (expand_##i, n); \
256 | 	for (int count_##i=0, i=expand_##i[0]; count_##i<card_##i; i=expand_##i[++count_##i])
257 | 
258 | #endif
259 | 


--------------------------------------------------------------------------------
/branch/hashed_perceptron.bpred:
--------------------------------------------------------------------------------
  1 | /*
  2 | 
  3 | This code implements a hashed perceptron branch predictor using geometric
  4 | history lengths and dynamic threshold setting.
  5 | 
  6 | It was written by Daniel A. Jiménez in March 2019. To the extent allowed by
  7 | law, the author abdicates all rights to this work and places it in the public
  8 | domain.
  9 | 
 10 | The original perceptron branch predictor is from Jiménez and Lin, "Dynamic
 11 | Branch Prediction with Perceptrons," HPCA 2001.
 12 | 
 13 | The idea of using multiple independently indexed tables of perceptron weights
 14 | is from Jiménez, "Fast Path-Based Neural Branch Prediction," MICRO 2003 and
 15 | later expanded in "Piecewise Linear Branch Prediction" from ISCA 2005.
 16 | 
 17 | The idea of using hashes of branch history to reduce the number of independent
 18 | tables is documented in three contemporaneous papers:
 19 | 
 20 | 1. Seznec, "Revisiting the Perceptron Predictor," IRISA technical report, 2004.
 21 | 
 22 | 2. Tarjan and Skadron, "Revisiting the Perceptron Predictor Again," UVA
 23 | technical report, 2004, expanded and published in ACM TACO 2005 as "Merging
 24 | path and gshare indexing in perceptron branch prediction"; introduces the term
 25 | "hashed perceptron."
 26 | 
 27 | 3. Loh and Jiménez, "Reducing the Power and Complexity of Path-Based Neural
 28 | Branch Prediction," WCED 2005.
 29 | 
 30 | The ideas of using "geometric history lengths" i.e. hashing into tables with
 31 | histories of exponentially increasing length, as well as dynamically adjusting
 32 | the theta parameter, are from Seznec, "The O-GEHL Branch Predictor," from CBP
 33 | 2004, expanded later as "Analysis of the O-GEometric History Length Branch
 34 | Predictor" in ISCA 2005.
 35 | 
 36 | This code uses these ideas, but prefers simplicity over absolute accuracy (I
 37 | wrote it in about an hour and later spent more time on this comment block than
 38 | I did on the code). These papers and subsequent papers by Jiménez and other
 39 | authors significantly improve the accuracy of perceptron-based predictors but
 40 | involve tricks and analysis beyond the needs of a tool like ChampSim that
 41 | targets cache optimizations. If you want accuracy at any cost, see the winners
 42 | of the latest branch prediction contest, CBP 2016 as of this writing, but
 43 | prepare to have your face melted off by the complexity of the code you find
 44 | there. If you are a student being asked to code a good branch predictor for
 45 | your computer architecture class, don't copy this code; there are much better
 46 | sources for you to plagiarize.
 47 | 
 48 | */
 49 | 
 50 | #include <stdio.h>
 51 | #include <string.h>
 52 | #include <math.h>
 53 | #include <stdlib.h>
 54 | 
 55 | #include "ooo_cpu.h"
 56 | 
 57 | // this many tables
 58 | 
 59 | #define NTABLES	16
 60 | 
 61 | // maximum history length
 62 | 
 63 | #define MAXHIST	232
 64 | 
 65 | // minimum history length (for table 1; table 0 is biases)
 66 | 
 67 | #define MINHIST	3
 68 | 
 69 | // speed for dynamic threshold setting
 70 | 
 71 | #define SPEED	18
 72 | 
 73 | // geometric global history lengths
 74 | 
 75 | int history_lengths[NTABLES] = { 0, 3, 4, 6, 8, 10, 14, 19, 26, 36, 49, 67, 91, 125, 170, MAXHIST };
 76 | 
 77 | // 12-bit indices for the tables
 78 | 
 79 | #define LOG_TABLE_SIZE	12
 80 | #define TABLE_SIZE	(1<<LOG_TABLE_SIZE)
 81 | 
 82 | // this many 12-bit words will be kept in the global history
 83 | 
 84 | #define NGHIST_WORDS	(MAXHIST/LOG_TABLE_SIZE+1)
 85 | 
 86 | // tables of 8-bit weights
 87 | 
 88 | int tables[NUM_CPUS][NTABLES][TABLE_SIZE];
 89 | 
 90 | // words that store the global history
 91 | 
 92 | unsigned int ghist_words[NUM_CPUS][NGHIST_WORDS];
 93 | 
 94 | // remember the indices into the tables from prediction to update
 95 | 
 96 | unsigned int indices[NUM_CPUS][NTABLES];
 97 | 
 98 | // initialize theta to something reasonable, 
 99 | int 
100 | 	theta[NUM_CPUS], 
101 | 
102 | // initialize counter for threshold setting algorithm
103 | 	tc[NUM_CPUS], 	
104 | 
105 | // perceptron sum
106 | 	yout[NUM_CPUS];
107 | 
108 | void O3_CPU::initialize_branch_predictor () {
109 | 	// zero out the weights tables
110 | 
111 | 	memset (tables, 0, sizeof (tables));
112 | 
113 | 	// zero out the global history
114 | 
115 | 	memset (ghist_words, 0, sizeof (ghist_words));
116 | 
117 | 	// make a reasonable theta
118 | 
119 | 	for (int i=0; i<NUM_CPUS; i++) theta[i] = 10;
120 | }
121 | 
122 | uint8_t O3_CPU::predict_branch(uint64_t pc) {
123 | 
124 | 	// initialize perceptron sum
125 | 
126 | 	yout[cpu] = 0;
127 | 
128 | 	// for each table...
129 | 
130 | 	for (int i=0; i<NTABLES; i++) {
131 | 
132 | 		// n is the history length for this table
133 | 
134 | 		int n = history_lengths[i];
135 | 
136 | 		// hash global history bits 0..n-1 into x by XORing the words from the ghist_words array
137 | 
138 | 		unsigned int x = 0;
139 | 
140 | 		// most of the words are 12 bits long
141 | 
142 | 		int most_words = n / LOG_TABLE_SIZE;
143 | 
144 | 		// the last word is fewer than 12 bits
145 | 
146 | 		int last_word = n % LOG_TABLE_SIZE;
147 | 
148 | 		// XOR up to the next-to-the-last word
149 | 
150 | 		int j;
151 | 		for (j=0; j<most_words; j++) x ^= ghist_words[cpu][j];
152 | 
153 | 		// XOR in the last word
154 | 
155 | 		x ^= ghist_words[cpu][j] & ((1<<last_word)-1);
156 | 
157 | 		// XOR in the PC to spread accesses around (like gshare)
158 | 
159 | 		x ^= pc;
160 | 
161 | 		// stay within the table size
162 | 
163 | 		x &= TABLE_SIZE-1;
164 | 
165 | 		// remember this index for update
166 | 
167 | 		indices[cpu][i] = x;
168 | 
169 | 		// add the selected weight to the perceptron sum
170 | 
171 | 		yout[cpu] += tables[cpu][i][x];
172 | 	}
173 | 	return yout[cpu] >= 1;
174 | }
175 | 
176 | void O3_CPU::last_branch_result(uint64_t pc, uint8_t taken) {
177 | 
178 | 	// was this prediction correct?
179 | 
180 | 	bool correct = taken == (yout[cpu] >= 1);
181 | 
182 | 	// insert this branch outcome into the global history
183 | 
184 | 	bool b = taken;
185 | 	for (int i=0; i<NGHIST_WORDS; i++) {
186 | 
187 | 		// shift b into the lsb of the current word
188 | 
189 | 		ghist_words[cpu][i] <<= 1;
190 | 		ghist_words[cpu][i] |= b;
191 | 
192 | 		// get b as the previous msb of the current word
193 | 
194 | 		b = !!(ghist_words[cpu][i] & TABLE_SIZE);
195 | 		ghist_words[cpu][i] &= TABLE_SIZE-1;
196 | 	}
197 | 
198 | 	// get the magnitude of yout
199 | 
200 | 	int a = (yout[cpu] < 0) ? -yout[cpu] : yout[cpu];
201 | 
202 | 	// perceptron learning rule: train if misprediction or weak correct prediction
203 | 
204 | 	if (!correct || a < theta[cpu]) {
205 | 		// update weights
206 | 		for (int i=0; i<NTABLES; i++) {
207 | 			// which weight did we use to compute yout?
208 | 
209 | 			int *c = &tables[cpu][i][indices[cpu][i]];
210 | 
211 | 			// increment if taken, decrement if not, saturating at 127/-128
212 | 
213 | 			if (taken) {
214 | 				if (*c < 127) (*c)++;
215 | 			} else {
216 | 				if (*c > -128) (*c)--;
217 | 			}
218 | 		}
219 | 
220 | 		// dynamic threshold setting from Seznec's O-GEHL paper
221 | 
222 | 		if (!correct) {
223 | 
224 | 			// increase theta after enough mispredictions
225 | 
226 | 			tc[cpu]++;
227 | 			if (tc[cpu] >= SPEED) {
228 | 				theta[cpu]++;
229 | 				tc[cpu] = 0;
230 | 			}
231 | 		} else if (a < theta[cpu]) {
232 | 
233 | 			// decrease theta after enough weak but correct predictions
234 | 
235 | 			tc[cpu]--;
236 | 			if (tc[cpu] <= -SPEED) {
237 | 				theta[cpu]--;
238 | 				tc[cpu] = 0;
239 | 			}
240 | 		}
241 | 	}
242 | }
243 | 


--------------------------------------------------------------------------------
/inc/cache.h:
--------------------------------------------------------------------------------
  1 | #ifndef CACHE_H
  2 | #define CACHE_H
  3 | 
  4 | #include "memory_class.h"
  5 | 
  6 | // PAGE
  7 | extern uint32_t PAGE_TABLE_LATENCY, SWAP_LATENCY;
  8 | 
  9 | // CACHE TYPE
 10 | #define IS_ITLB 0
 11 | #define IS_DTLB 1
 12 | #define IS_STLB 2
 13 | #define IS_L1I  3
 14 | #define IS_L1D  4
 15 | #define IS_L2C  5
 16 | #define IS_LLC  6
 17 | 
 18 | // INSTRUCTION TLB
 19 | #define ITLB_SET 16
 20 | #define ITLB_WAY 4
 21 | #define ITLB_RQ_SIZE 16
 22 | #define ITLB_WQ_SIZE 16
 23 | #define ITLB_PQ_SIZE 0
 24 | #define ITLB_MSHR_SIZE 8
 25 | #define ITLB_LATENCY 1
 26 | 
 27 | // DATA TLB
 28 | #define DTLB_SET 16
 29 | #define DTLB_WAY 4
 30 | #define DTLB_RQ_SIZE 16
 31 | #define DTLB_WQ_SIZE 16
 32 | #define DTLB_PQ_SIZE 0
 33 | #define DTLB_MSHR_SIZE 8
 34 | #define DTLB_LATENCY 1
 35 | 
 36 | // SECOND LEVEL TLB
 37 | #define STLB_SET 128
 38 | #define STLB_WAY 12
 39 | #define STLB_RQ_SIZE 32
 40 | #define STLB_WQ_SIZE 32
 41 | #define STLB_PQ_SIZE 0
 42 | #define STLB_MSHR_SIZE 16
 43 | #define STLB_LATENCY 8
 44 | 
 45 | // L1 INSTRUCTION CACHE
 46 | #define L1I_SET 64
 47 | #define L1I_WAY 8
 48 | #define L1I_RQ_SIZE 64
 49 | #define L1I_WQ_SIZE 64 
 50 | #define L1I_PQ_SIZE 32
 51 | #define L1I_MSHR_SIZE 8
 52 | #define L1I_LATENCY 4
 53 | 
 54 | // L1 DATA CACHE
 55 | #define L1D_SET 64
 56 | #define L1D_WAY 12
 57 | #define L1D_RQ_SIZE 64
 58 | #define L1D_WQ_SIZE 64 
 59 | #define L1D_PQ_SIZE 8
 60 | #define L1D_MSHR_SIZE 16
 61 | #define L1D_LATENCY 5 
 62 | 
 63 | // L2 CACHE
 64 | #define L2C_SET 1024
 65 | #define L2C_WAY 8
 66 | #define L2C_RQ_SIZE 32
 67 | #define L2C_WQ_SIZE 32
 68 | #define L2C_PQ_SIZE 16
 69 | #define L2C_MSHR_SIZE 32
 70 | #define L2C_LATENCY 10  // 4/5 (L1I or L1D) + 10 = 14/15 cycles
 71 | 
 72 | // LAST LEVEL CACHE
 73 | #define LLC_SET NUM_CPUS*2048
 74 | #define LLC_WAY 16
 75 | #define LLC_RQ_SIZE NUM_CPUS*L2C_MSHR_SIZE //48
 76 | #define LLC_WQ_SIZE NUM_CPUS*L2C_MSHR_SIZE //48
 77 | #define LLC_PQ_SIZE NUM_CPUS*32
 78 | #define LLC_MSHR_SIZE NUM_CPUS*64
 79 | #define LLC_LATENCY 20  // 4/5 (L1I or L1D) + 10 + 20 = 34/35 cycles
 80 | 
 81 | class CACHE : public MEMORY {
 82 |   public:
 83 |     uint32_t cpu;
 84 |     const string NAME;
 85 |     const uint32_t NUM_SET, NUM_WAY, NUM_LINE, WQ_SIZE, RQ_SIZE, PQ_SIZE, MSHR_SIZE;
 86 |     uint32_t LATENCY;
 87 |     BLOCK **block;
 88 |     int fill_level;
 89 |     uint32_t MAX_READ, MAX_FILL;
 90 |     uint32_t reads_available_this_cycle;
 91 |     uint8_t cache_type;
 92 | 
 93 |     // prefetch stats
 94 |     uint64_t pf_requested,
 95 |              pf_issued,
 96 |              pf_useful,
 97 |              pf_useless,
 98 |              pf_fill;
 99 | 
100 |     // queues
101 |     PACKET_QUEUE WQ{NAME + "_WQ", WQ_SIZE}, // write queue
102 |                  RQ{NAME + "_RQ", RQ_SIZE}, // read queue
103 |                  PQ{NAME + "_PQ", PQ_SIZE}, // prefetch queue
104 |                  MSHR{NAME + "_MSHR", MSHR_SIZE}, // MSHR
105 |                  PROCESSED{NAME + "_PROCESSED", ROB_SIZE}; // processed queue
106 | 
107 |     uint64_t sim_access[NUM_CPUS][NUM_TYPES],
108 |              sim_hit[NUM_CPUS][NUM_TYPES],
109 |              sim_miss[NUM_CPUS][NUM_TYPES],
110 |              roi_access[NUM_CPUS][NUM_TYPES],
111 |              roi_hit[NUM_CPUS][NUM_TYPES],
112 |              roi_miss[NUM_CPUS][NUM_TYPES];
113 | 
114 |     uint64_t total_miss_latency;
115 |     
116 |     // constructor
117 |     CACHE(string v1, uint32_t v2, int v3, uint32_t v4, uint32_t v5, uint32_t v6, uint32_t v7, uint32_t v8) 
118 |         : NAME(v1), NUM_SET(v2), NUM_WAY(v3), NUM_LINE(v4), WQ_SIZE(v5), RQ_SIZE(v6), PQ_SIZE(v7), MSHR_SIZE(v8) {
119 | 
120 |         LATENCY = 0;
121 | 
122 |         // cache block
123 |         block = new BLOCK* [NUM_SET];
124 |         for (uint32_t i=0; i<NUM_SET; i++) {
125 |             block[i] = new BLOCK[NUM_WAY]; 
126 | 
127 |             for (uint32_t j=0; j<NUM_WAY; j++) {
128 |                 block[i][j].lru = j;
129 |             }
130 |         }
131 | 
132 |         for (uint32_t i=0; i<NUM_CPUS; i++) {
133 |             upper_level_icache[i] = NULL;
134 |             upper_level_dcache[i] = NULL;
135 | 
136 |             for (uint32_t j=0; j<NUM_TYPES; j++) {
137 |                 sim_access[i][j] = 0;
138 |                 sim_hit[i][j] = 0;
139 |                 sim_miss[i][j] = 0;
140 |                 roi_access[i][j] = 0;
141 |                 roi_hit[i][j] = 0;
142 |                 roi_miss[i][j] = 0;
143 |             }
144 |         }
145 | 
146 | 	total_miss_latency = 0;
147 | 
148 |         lower_level = NULL;
149 |         extra_interface = NULL;
150 |         fill_level = -1;
151 |         MAX_READ = 1;
152 |         MAX_FILL = 1;
153 | 
154 |         pf_requested = 0;
155 |         pf_issued = 0;
156 |         pf_useful = 0;
157 |         pf_useless = 0;
158 |         pf_fill = 0;
159 |     };
160 | 
161 |     // destructor
162 |     ~CACHE() {
163 |         for (uint32_t i=0; i<NUM_SET; i++)
164 |             delete[] block[i];
165 |         delete[] block;
166 |     };
167 | 
168 |     // functions
169 |     int  add_rq(PACKET *packet),
170 |          add_wq(PACKET *packet),
171 |          add_pq(PACKET *packet);
172 | 
173 |     void return_data(PACKET *packet),
174 |          operate(),
175 |          increment_WQ_FULL(uint64_t address);
176 | 
177 |     uint32_t get_occupancy(uint8_t queue_type, uint64_t address),
178 |              get_size(uint8_t queue_type, uint64_t address);
179 | 
180 |     int  check_hit(PACKET *packet),
181 |          invalidate_entry(uint64_t inval_addr),
182 |          check_mshr(PACKET *packet),
183 |          prefetch_line(uint64_t ip, uint64_t base_addr, uint64_t pf_addr, int prefetch_fill_level, uint32_t prefetch_metadata),
184 |          kpc_prefetch_line(uint64_t base_addr, uint64_t pf_addr, int prefetch_fill_level, int delta, int depth, int signature, int confidence, uint32_t prefetch_metadata);
185 | 
186 |     void handle_fill(),
187 |          handle_writeback(),
188 |          handle_read(),
189 |          handle_prefetch();
190 | 
191 |     void add_mshr(PACKET *packet),
192 |          update_fill_cycle(),
193 |          llc_initialize_replacement(),
194 |          update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit),
195 |          llc_update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit),
196 |          lru_update(uint32_t set, uint32_t way),
197 |          fill_cache(uint32_t set, uint32_t way, PACKET *packet),
198 |          replacement_final_stats(),
199 |          llc_replacement_final_stats(),
200 |          //prefetcher_initialize(),
201 |          l1d_prefetcher_initialize(),
202 |          l2c_prefetcher_initialize(),
203 |          llc_prefetcher_initialize(),
204 |          prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type),
205 |          l1d_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type),
206 |          prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr),
207 |          l1d_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in),
208 |          //prefetcher_final_stats(),
209 |          l1d_prefetcher_final_stats(),
210 |          l2c_prefetcher_final_stats(),
211 |          llc_prefetcher_final_stats();
212 |     void (*l1i_prefetcher_cache_operate)(uint32_t, uint64_t, uint8_t, uint8_t);
213 |     void (*l1i_prefetcher_cache_fill)(uint32_t, uint64_t, uint32_t, uint32_t, uint8_t, uint64_t);
214 | 
215 |     uint32_t l2c_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in),
216 |          llc_prefetcher_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, uint8_t type, uint32_t metadata_in),
217 |          l2c_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in),
218 |          llc_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in);
219 |     
220 |     uint32_t get_set(uint64_t address),
221 |              get_way(uint64_t address, uint32_t set),
222 |              find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type),
223 |              llc_find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type),
224 |              lru_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type);
225 | };
226 | 
227 | #endif
228 | 


--------------------------------------------------------------------------------
/replacement/ship.llc_repl:
--------------------------------------------------------------------------------
  1 | #include "cache.h"
  2 | #include <cstdlib>
  3 | #include <ctime>
  4 | 
  5 | #define maxRRPV 3
  6 | #define SHCT_SIZE  16384
  7 | #define SHCT_PRIME 16381
  8 | #define SAMPLER_SET (256*NUM_CPUS)
  9 | #define SAMPLER_WAY LLC_WAY
 10 | #define SHCT_MAX 7
 11 | 
 12 | uint32_t rrpv[LLC_SET][LLC_WAY];
 13 | 
 14 | // sampler structure
 15 | class SAMPLER_class
 16 | {
 17 |   public:
 18 |     uint8_t valid,
 19 |             type,
 20 |             used;
 21 | 
 22 |     uint64_t tag, cl_addr, ip;
 23 |     
 24 |     uint32_t lru;
 25 | 
 26 |     SAMPLER_class() {
 27 |         valid = 0;
 28 |         type = 0;
 29 |         used = 0;
 30 | 
 31 |         tag = 0;
 32 |         cl_addr = 0;
 33 |         ip = 0;
 34 | 
 35 |         lru = 0;
 36 |     };
 37 | };
 38 | 
 39 | // sampler
 40 | uint32_t rand_sets[SAMPLER_SET];
 41 | SAMPLER_class sampler[SAMPLER_SET][SAMPLER_WAY];
 42 | 
 43 | // prediction table structure
 44 | class SHCT_class {
 45 |   public:
 46 |     uint32_t counter;
 47 | 
 48 |     SHCT_class() {
 49 |         counter = 0;
 50 |     };
 51 | };
 52 | SHCT_class SHCT[NUM_CPUS][SHCT_SIZE];
 53 | 
 54 | // initialize replacement state
 55 | void CACHE::llc_initialize_replacement()
 56 | {
 57 |     cout << "Initialize SHIP state" << endl;
 58 | 
 59 |     for (int i=0; i<LLC_SET; i++) {
 60 |         for (int j=0; j<LLC_WAY; j++) {
 61 |             rrpv[i][j] = maxRRPV;
 62 |         }
 63 |     }
 64 | 
 65 |     // initialize sampler
 66 |     for (int i=0; i<SAMPLER_SET; i++) {
 67 |         for (int j=0; j<SAMPLER_WAY; j++) {
 68 |             sampler[i][j].lru = j;
 69 |         }
 70 |     }
 71 | 
 72 |     // randomly selected sampler sets
 73 |     srand(time(NULL));
 74 |     unsigned long rand_seed = 1;
 75 |     unsigned long max_rand = 1048576;
 76 |     uint32_t my_set = LLC_SET;
 77 |     int do_again = 0;
 78 |     for (int i=0; i<SAMPLER_SET; i++)
 79 |     {
 80 |         do 
 81 |         {
 82 |             do_again = 0;
 83 |             rand_seed = rand_seed * 1103515245 + 12345;
 84 |             rand_sets[i] = ((unsigned) ((rand_seed/65536) % max_rand)) % my_set;
 85 |             printf("Assign rand_sets[%d]: %u  LLC: %u\n", i, rand_sets[i], my_set);
 86 |             for (int j=0; j<i; j++) 
 87 |             {
 88 |                 if (rand_sets[i] == rand_sets[j]) 
 89 |                 {
 90 |                     do_again = 1;
 91 |                     break;
 92 |                 }
 93 |             }
 94 |         } while (do_again);
 95 |         printf("rand_sets[%d]: %d\n", i, rand_sets[i]);
 96 |     }
 97 | }
 98 | 
 99 | // check if this set is sampled
100 | uint32_t is_it_sampled(uint32_t set)
101 | {
102 |     for (int i=0; i<SAMPLER_SET; i++)
103 |         if (rand_sets[i] == set)
104 |             return i;
105 | 
106 |     return SAMPLER_SET;
107 | }
108 | 
109 | // update sampler
110 | void update_sampler(uint32_t cpu, uint32_t s_idx, uint64_t address, uint64_t ip, uint8_t type)
111 | {
112 |     SAMPLER_class *s_set = sampler[s_idx];
113 |     uint64_t tag = address / (64*LLC_SET); 
114 |     int match = -1;
115 | 
116 |     // check hit
117 |     for (match=0; match<SAMPLER_WAY; match++)
118 |     {
119 |         if (s_set[match].valid && (s_set[match].tag == tag))
120 |         {
121 |             uint32_t SHCT_idx = s_set[match].ip % SHCT_PRIME;
122 |             if (SHCT[cpu][SHCT_idx].counter > 0)
123 |                 SHCT[cpu][SHCT_idx].counter--;
124 | 
125 |             /*
126 |             if (draw_transition)
127 |                 printf("cycle: %lu SHCT: %d ip: 0x%llX SAMPLER_HIT cl_addr: 0x%llX page: 0x%llX block: %ld set: %d\n", 
128 |                 ooo_cpu[cpu].current_cycle, SHCT[cpu][SHCT_idx].dead, s_set[match].ip, address>>6, address>>12, (address>>6) & 0x3F, s_idx);
129 |             */
130 | 
131 |             //s_set[match].ip = ip; // SHIP does not update ip on sampler hit
132 |             s_set[match].type = type; 
133 |             s_set[match].used = 1;
134 |             //D(printf("sampler hit  cpu: %d  set: %d  way: %d  tag: %x  ip: %lx  type: %d  lru: %d\n",
135 |             //            cpu, rand_sets[s_idx], match, tag, ip, type, s_set[match].lru));
136 | 
137 |             break;
138 |         }
139 |     }
140 | 
141 |     // check invalid
142 |     if (match == SAMPLER_WAY)
143 |     {
144 |         for (match=0; match<SAMPLER_WAY; match++)
145 |         {
146 |             if (s_set[match].valid == 0)
147 |             {
148 |                 s_set[match].valid = 1;
149 |                 s_set[match].tag = tag;
150 |                 s_set[match].ip = ip;
151 |                 s_set[match].type = type;
152 |                 s_set[match].used = 0;
153 | 
154 |                 //D(printf("sampler invalid  cpu: %d  set: %d  way: %d  tag: %x  ip: %lx  type: %d  lru: %d\n",
155 |                 //            cpu, rand_sets[s_idx], match, tag, ip, type, s_set[match].lru));
156 |                 break;
157 |             }
158 |         }
159 |     }
160 | 
161 |     // miss
162 |     if (match == SAMPLER_WAY)
163 |     {
164 |         for (match=0; match<SAMPLER_WAY; match++)
165 |         {
166 |             if (s_set[match].lru == (SAMPLER_WAY-1)) // Sampler uses LRU replacement
167 |             {
168 |                 if (s_set[match].used == 0)
169 |                 {
170 |                     uint32_t SHCT_idx = s_set[match].ip % SHCT_PRIME;
171 |                     if (SHCT[cpu][SHCT_idx].counter < SHCT_MAX)
172 |                         SHCT[cpu][SHCT_idx].counter++;
173 | 
174 |                     /*
175 |                     if (draw_transition)
176 |                         printf("cycle: %lu SHCT: %d ip: 0x%llX SAMPLER_MISS cl_addr: 0x%llX page: 0x%llX block: %ld set: %d\n", 
177 |                         ooo_cpu[cpu].current_cycle, SHCT[cpu][SHCT_idx].dead, s_set[match].ip, address>>6, address>>12, (address>>6) & 0x3F, s_idx);
178 |                     */
179 |                 }
180 | 
181 |                 s_set[match].tag = tag;
182 |                 s_set[match].ip = ip;
183 |                 s_set[match].type = type;
184 |                 s_set[match].used = 0;
185 | 
186 |                 //D(printf("sampler miss  cpu: %d  set: %d  way: %d  tag: %x  ip: %lx  type: %d  lru: %d\n",
187 |                 //            cpu, rand_sets[s_idx], match, tag, ip, type, s_set[match].lru));
188 |                 break;
189 |             }
190 |         }
191 |     }
192 | 
193 |     // update LRU state
194 |     uint32_t curr_position = s_set[match].lru;
195 |     for (int i=0; i<SAMPLER_WAY; i++)
196 |     {
197 |         if (s_set[i].lru < curr_position)
198 |             s_set[i].lru++;
199 |     }
200 |     s_set[match].lru = 0;
201 | }
202 | 
203 | // find replacement victim
204 | uint32_t CACHE::llc_find_victim(uint32_t cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
205 | {
206 |     // look for the maxRRPV line
207 |     while (1)
208 |     {
209 |         for (int i=0; i<LLC_WAY; i++)
210 |             if (rrpv[set][i] == maxRRPV)
211 |                 return i;
212 | 
213 |         for (int i=0; i<LLC_WAY; i++)
214 |             rrpv[set][i]++;
215 |     }
216 | 
217 |     // WE SHOULD NOT REACH HERE
218 |     assert(0);
219 |     return 0;
220 | }
221 | 
222 | // called on every cache hit and cache fill
223 | void CACHE::llc_update_replacement_state(uint32_t cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
224 | {
225 |     string TYPE_NAME;
226 |     if (type == LOAD)
227 |         TYPE_NAME = "LOAD";
228 |     else if (type == RFO)
229 |         TYPE_NAME = "RFO";
230 |     else if (type == PREFETCH)
231 |         TYPE_NAME = "PF";
232 |     else if (type == WRITEBACK)
233 |         TYPE_NAME = "WB";
234 |     else
235 |         assert(0);
236 | 
237 |     if (hit)
238 |         TYPE_NAME += "_HIT";
239 |     else
240 |         TYPE_NAME += "_MISS";
241 | 
242 |     if ((type == WRITEBACK) && ip)
243 |         assert(0);
244 | 
245 |     //cout << "CPU: " << cpu << "  LLC " << setw(9) << TYPE_NAME << " set: " << setw(5) << set << " way: " << setw(2) << way;
246 |     //cout << hex << " paddr: " << setw(12) << full_addr << " ip: " << setw(8) << ip << " victim_addr: " << victim_addr << dec << endl;
247 |     
248 |     // handle writeback access
249 |     if (type == WRITEBACK) {
250 |         if (hit)
251 |             return;
252 |         else {
253 |             rrpv[set][way] = maxRRPV-1;
254 |             return;
255 |         }
256 |     }
257 | 
258 |     // update sampler
259 |     uint32_t s_idx = is_it_sampled(set);
260 |     if (s_idx < SAMPLER_SET)
261 |         update_sampler(cpu, s_idx, full_addr, ip, type);
262 | 
263 |     if (hit)
264 |         rrpv[set][way] = 0;
265 |     else {
266 |         // SHIP prediction
267 |         uint32_t SHCT_idx = ip % SHCT_PRIME;
268 | 
269 |         // sanity check
270 |         if (SHCT_idx >= SHCT_PRIME)
271 |             assert(0);
272 | 
273 |         rrpv[set][way] = maxRRPV-1;
274 |         if (SHCT[cpu][SHCT_idx].counter == SHCT_MAX)
275 |             rrpv[set][way] = maxRRPV;
276 |     }
277 | }
278 | 
279 | // use this function to print out your own stats at the end of simulation
280 | void CACHE::llc_replacement_final_stats()
281 | {
282 | 
283 | }
284 | 


--------------------------------------------------------------------------------
/inc/instruction.h:
--------------------------------------------------------------------------------
  1 | #ifndef INSTRUCTION_H
  2 | #define INSTRUCTION_H
  3 | 
  4 | 
  5 | // instruction format
  6 | #define ROB_SIZE 352
  7 | #define LQ_SIZE 128
  8 | #define SQ_SIZE 72
  9 | #define NUM_INSTR_DESTINATIONS_SPARC 4
 10 | #define NUM_INSTR_DESTINATIONS 2
 11 | #define NUM_INSTR_SOURCES 4
 12 | 
 13 | // special registers that help us identify branches
 14 | #define REG_STACK_POINTER 6
 15 | #define REG_FLAGS 25
 16 | #define REG_INSTRUCTION_POINTER 26
 17 | 
 18 | // branch types
 19 | #define NOT_BRANCH           0
 20 | #define BRANCH_DIRECT_JUMP   1
 21 | #define BRANCH_INDIRECT      2
 22 | #define BRANCH_CONDITIONAL   3
 23 | #define BRANCH_DIRECT_CALL   4
 24 | #define BRANCH_INDIRECT_CALL 5
 25 | #define BRANCH_RETURN        6
 26 | #define BRANCH_OTHER         7
 27 | 
 28 | #include "set.h"
 29 | 
 30 | class input_instr {
 31 |   public:
 32 | 
 33 |     // instruction pointer or PC (Program Counter)
 34 |     uint64_t ip;
 35 | 
 36 |     // branch info
 37 |     uint8_t is_branch;
 38 |     uint8_t branch_taken;
 39 | 
 40 |     uint8_t destination_registers[NUM_INSTR_DESTINATIONS]; // output registers
 41 |     uint8_t source_registers[NUM_INSTR_SOURCES]; // input registers
 42 | 
 43 |     uint64_t destination_memory[NUM_INSTR_DESTINATIONS]; // output memory
 44 |     uint64_t source_memory[NUM_INSTR_SOURCES]; // input memory
 45 | 
 46 |     input_instr() {
 47 |         ip = 0;
 48 |         is_branch = 0;
 49 |         branch_taken = 0;
 50 | 
 51 |         for (uint32_t i=0; i<NUM_INSTR_SOURCES; i++) {
 52 |             source_registers[i] = 0;
 53 |             source_memory[i] = 0;
 54 |         }
 55 | 
 56 |         for (uint32_t i=0; i<NUM_INSTR_DESTINATIONS; i++) {
 57 |             destination_registers[i] = 0;
 58 |             destination_memory[i] = 0;
 59 |         }
 60 |     };
 61 | };
 62 | 
 63 | class cloudsuite_instr {
 64 |   public:
 65 | 
 66 |     // instruction pointer or PC (Program Counter)
 67 |     uint64_t ip;
 68 | 
 69 |     // branch info
 70 |     uint8_t is_branch;
 71 |     uint8_t branch_taken;
 72 | 
 73 |     uint8_t destination_registers[NUM_INSTR_DESTINATIONS_SPARC]; // output registers
 74 |     uint8_t source_registers[NUM_INSTR_SOURCES]; // input registers
 75 | 
 76 |     uint64_t destination_memory[NUM_INSTR_DESTINATIONS_SPARC]; // output memory
 77 |     uint64_t source_memory[NUM_INSTR_SOURCES]; // input memory
 78 | 
 79 |     uint8_t asid[2];
 80 | 
 81 |     cloudsuite_instr() {
 82 |         ip = 0;
 83 |         is_branch = 0;
 84 |         branch_taken = 0;
 85 | 
 86 |         for (uint32_t i=0; i<NUM_INSTR_SOURCES; i++) {
 87 |             source_registers[i] = 0;
 88 |             source_memory[i] = 0;
 89 |         }
 90 | 
 91 |         for (uint32_t i=0; i<NUM_INSTR_DESTINATIONS_SPARC; i++) {
 92 |             destination_registers[i] = 0;
 93 |             destination_memory[i] = 0;
 94 |         }
 95 | 
 96 |         asid[0] = UINT8_MAX;
 97 |         asid[1] = UINT8_MAX;
 98 |     };
 99 | };
100 | 
101 | class ooo_model_instr {
102 |   public:
103 |     uint64_t instr_id,
104 |              ip,
105 |              fetch_producer,
106 |              producer_id,
107 |              translated_cycle,
108 |              fetched_cycle,
109 |              execute_begin_cycle,
110 |              retired_cycle,
111 |              event_cycle;
112 | 
113 |     uint8_t is_branch,
114 |             is_memory,
115 |             branch_taken,
116 |             branch_mispredicted,
117 | 	    resolve_cond_branch_in_decode,
118 |             branch_prediction_made,
119 |             translated,
120 |             data_translated,
121 |             source_added[NUM_INSTR_SOURCES],
122 |             destination_added[NUM_INSTR_DESTINATIONS_SPARC],
123 |             is_producer,
124 |             is_consumer,
125 |             reg_RAW_producer,
126 |             reg_ready,
127 |             mem_ready,
128 |             asid[2],
129 |             reg_RAW_checked[NUM_INSTR_SOURCES];
130 | 
131 |     uint8_t branch_type;
132 |     uint64_t branch_target;
133 | 
134 |     uint32_t fetched, scheduled;
135 |     int num_reg_ops, num_mem_ops, num_reg_dependent;
136 | 
137 |     // executed bit is set after all dependencies are eliminated and this instr is chosen on a cycle, according to EXEC_WIDTH
138 |     int executed;
139 | 
140 |     uint8_t destination_registers[NUM_INSTR_DESTINATIONS_SPARC]; // output registers
141 | 
142 |     uint8_t source_registers[NUM_INSTR_SOURCES]; // input registers 
143 | 
144 |     // these are instruction ids of other instructions in the window
145 |     //int64_t registers_instrs_i_depend_on[NUM_INSTR_SOURCES];
146 |     // these are indices of instructions in the window that depend on me
147 |     //uint8_t registers_instrs_depend_on_me[ROB_SIZE], registers_index_depend_on_me[ROB_SIZE][NUM_INSTR_SOURCES];
148 |     fastset
149 | 	registers_instrs_depend_on_me, registers_index_depend_on_me[NUM_INSTR_SOURCES];
150 | 
151 | 
152 |     // memory addresses that may cause dependencies between instructions
153 |     uint64_t instruction_pa, data_pa, virtual_address, physical_address;
154 |     uint64_t destination_memory[NUM_INSTR_DESTINATIONS_SPARC]; // output memory
155 |     uint64_t source_memory[NUM_INSTR_SOURCES]; // input memory
156 |     //int source_memory_outstanding[NUM_INSTR_SOURCES];  // a value of 2 here means the load hasn't been issued yet, 1 means it has been issued, but not returned yet, and 0 means it has returned
157 | 
158 |     // keep around a record of what the original virtual addresses were
159 |     uint64_t destination_virtual_address[NUM_INSTR_DESTINATIONS_SPARC];
160 |     uint64_t source_virtual_address[NUM_INSTR_SOURCES];
161 | 
162 |     // these are instruction ids of other instructions in the window
163 |     //uint32_t memory_instrs_i_depend_on[NUM_INSTR_SOURCES];
164 | 
165 |     // these are indices of instructions in the ROB that depend on me
166 |     //uint8_t memory_instrs_depend_on_me[ROB_SIZE];
167 |     fastset memory_instrs_depend_on_me;
168 | 
169 |     uint32_t lq_index[NUM_INSTR_SOURCES],
170 |              sq_index[NUM_INSTR_DESTINATIONS_SPARC],
171 |              forwarding_index[NUM_INSTR_DESTINATIONS_SPARC];
172 | 
173 |     ooo_model_instr() {
174 |         instr_id = 0;
175 |         ip = 0;
176 |         fetch_producer = 0;
177 |         producer_id = 0;
178 |         translated_cycle = 0;
179 |         fetched_cycle = 0;
180 |         execute_begin_cycle = 0;
181 |         retired_cycle = 0;
182 |         event_cycle = 0;
183 | 
184 |         is_branch = 0;
185 |         is_memory = 0;
186 |         branch_taken = 0;
187 |         branch_mispredicted = 0;
188 | 	resolve_cond_branch_in_decode = 0;
189 | 	branch_prediction_made = 0;
190 |         translated = 0;
191 |         data_translated = 0;
192 |         is_producer = 0;
193 |         is_consumer = 0;
194 |         reg_RAW_producer = 0;
195 |         fetched = 0;
196 |         scheduled = 0;
197 |         executed = 0;
198 |         reg_ready = 0;
199 |         mem_ready = 0;
200 |         asid[0] = UINT8_MAX;
201 |         asid[1] = UINT8_MAX;
202 | 
203 | 	branch_type = NOT_BRANCH;
204 | 	branch_target = 0;
205 | 
206 |         instruction_pa = 0;
207 |         data_pa = 0;
208 |         virtual_address = 0;
209 |         physical_address = 0;
210 | 
211 |         num_reg_ops = 0;
212 |         num_mem_ops = 0;
213 |         num_reg_dependent = 0;
214 | 
215 |         for (uint32_t i=0; i<NUM_INSTR_SOURCES; i++) {
216 |             source_registers[i] = 0;
217 |             source_memory[i] = 0;
218 |             source_virtual_address[i] = 0;
219 |             source_added[i] = 0;
220 |             lq_index[i] = UINT32_MAX;
221 |             reg_RAW_checked[i] = 0;
222 |         }
223 | 
224 |         for (uint32_t i=0; i<NUM_INSTR_DESTINATIONS_SPARC; i++) {
225 |             destination_memory[i] = 0;
226 |             destination_registers[i] = 0;
227 |             destination_virtual_address[i] = 0;
228 |             destination_added[i] = 0;
229 |             sq_index[i] = UINT32_MAX;
230 |             forwarding_index[i] = 0;
231 |         }
232 | 
233 | #if 0
234 |         for (uint32_t i=0; i<ROB_SIZE; i++) {
235 |             registers_instrs_depend_on_me[i] = 0;
236 |             memory_instrs_depend_on_me[i] = 0;
237 | 
238 |             for (uint32_t j=0; j<NUM_INSTR_SOURCES; j++)
239 |                 registers_index_depend_on_me[i][j] = 0;
240 |         }
241 | #endif
242 |     };
243 | 
244 |   void print_instr()
245 |   {
246 |     cout << "*** " << instr_id << " ***" << endl;
247 |     cout << hex << "0x" << (uint64_t)ip << dec << endl;
248 |     cout << (uint32_t)is_branch << " " << (uint32_t)branch_taken << endl;
249 |     for(uint32_t i=0; i<NUM_INSTR_SOURCES; i++)
250 |       {
251 | 	cout << (uint32_t)source_registers[i] << " ";
252 |       }
253 |     cout << endl;
254 |     for(uint32_t i=0; i<NUM_INSTR_SOURCES; i++)
255 |       {
256 | 	cout << hex << "0x" << (uint32_t)source_memory[i] << dec << " ";
257 |       }
258 |     cout << endl;
259 |     for(uint32_t i=0; i<NUM_INSTR_DESTINATIONS; i++)
260 |       {
261 | 	cout << (uint32_t)destination_registers[i] << " ";
262 |       }
263 |     cout << endl;
264 |     for(uint32_t i=0; i<NUM_INSTR_DESTINATIONS; i++)
265 |       {
266 |         cout << hex << "0x" << (uint32_t)destination_memory[i] << dec << " ";
267 |       }
268 |     cout << endl;
269 |     
270 |     cout << endl;
271 |   }
272 | };
273 | 
274 | #endif
275 | 


--------------------------------------------------------------------------------
/inc/block.h:
--------------------------------------------------------------------------------
  1 | #ifndef BLOCK_H
  2 | #define BLOCK_H
  3 | 
  4 | #include "champsim.h"
  5 | #include "instruction.h"
  6 | #include "set.h"
  7 | 
  8 | // CACHE BLOCK
  9 | class BLOCK {
 10 |   public:
 11 |     uint8_t valid,
 12 |             prefetch,
 13 |             dirty,
 14 |             used;
 15 | 
 16 |     int delta,
 17 |         depth,
 18 |         signature,
 19 |         confidence;
 20 | 
 21 |     uint64_t address,
 22 |              full_addr,
 23 |              tag,
 24 |              data,
 25 |              ip,
 26 |              cpu,
 27 |              instr_id;
 28 | 
 29 |     // replacement state
 30 |     uint32_t lru;
 31 | 
 32 |     BLOCK() {
 33 |         valid = 0;
 34 |         prefetch = 0;
 35 |         dirty = 0;
 36 |         used = 0;
 37 | 
 38 |         delta = 0;
 39 |         depth = 0;
 40 |         signature = 0;
 41 |         confidence = 0;
 42 | 
 43 |         address = 0;
 44 |         full_addr = 0;
 45 |         tag = 0;
 46 |         data = 0;
 47 |         cpu = 0;
 48 |         instr_id = 0;
 49 | 
 50 |         lru = 0;
 51 |     };
 52 | };
 53 | 
 54 | // DRAM CACHE BLOCK
 55 | class DRAM_ARRAY {
 56 |   public:
 57 |     BLOCK **block;
 58 | 
 59 |     DRAM_ARRAY() {
 60 |         block = NULL;
 61 |     };
 62 | };
 63 | 
 64 | // message packet
 65 | class PACKET {
 66 |   public:
 67 |     uint8_t instruction, 
 68 |             is_data,
 69 |             fill_l1i,
 70 |             fill_l1d,
 71 |             tlb_access,
 72 |             scheduled,
 73 |             translated,
 74 |             fetched,
 75 |             prefetched,
 76 |             drc_tag_read;
 77 | 
 78 |     int fill_level, 
 79 |         pf_origin_level,
 80 |         rob_signal, 
 81 |         rob_index, 
 82 |         producer,
 83 |         delta,
 84 |         depth,
 85 |         signature,
 86 |         confidence;
 87 | 
 88 |     uint32_t pf_metadata;
 89 | 
 90 |     uint8_t  is_producer, 
 91 |              //rob_index_depend_on_me[ROB_SIZE], 
 92 |              //lq_index_depend_on_me[ROB_SIZE], 
 93 |              //sq_index_depend_on_me[ROB_SIZE], 
 94 |              instr_merged,
 95 |              load_merged, 
 96 |              store_merged,
 97 |              returned,
 98 |              asid[2],
 99 |              type;
100 | 
101 |     fastset
102 |              rob_index_depend_on_me, 
103 |              lq_index_depend_on_me, 
104 |              sq_index_depend_on_me;
105 | 
106 |     uint32_t cpu, data_index, lq_index, sq_index;
107 | 
108 |     uint64_t address, 
109 |              full_addr, 
110 |              instruction_pa,
111 |              data_pa,
112 |              data,
113 |              instr_id,
114 |              ip, 
115 |              event_cycle,
116 |              cycle_enqueued;
117 | 
118 |     PACKET() {
119 |         instruction = 0;
120 |         is_data = 1;
121 | 	fill_l1i = 0;
122 | 	fill_l1d = 0;
123 |         tlb_access = 0;
124 |         scheduled = 0;
125 |         translated = 0;
126 |         fetched = 0;
127 |         prefetched = 0;
128 |         drc_tag_read = 0;
129 | 
130 |         returned = 0;
131 |         asid[0] = UINT8_MAX;
132 |         asid[1] = UINT8_MAX;
133 |         type = 0;
134 | 
135 |         fill_level = -1; 
136 |         rob_signal = -1;
137 |         rob_index = -1;
138 |         producer = -1;
139 |         delta = 0;
140 |         depth = 0;
141 |         signature = 0;
142 |         confidence = 0;
143 | 
144 | #if 0
145 |         for (uint32_t i=0; i<ROB_SIZE; i++) {
146 |             rob_index_depend_on_me[i] = 0;
147 |             lq_index_depend_on_me[i] = 0;
148 |             sq_index_depend_on_me[i] = 0;
149 |         }
150 | #endif
151 |         is_producer = 0;
152 |         instr_merged = 0;
153 |         load_merged = 0;
154 |         store_merged = 0;
155 | 
156 |         cpu = NUM_CPUS;
157 |         data_index = 0;
158 |         lq_index = 0;
159 |         sq_index = 0;
160 | 
161 |         address = 0;
162 |         full_addr = 0;
163 |         instruction_pa = 0;
164 |         data = 0;
165 |         instr_id = 0;
166 |         ip = 0;
167 |         event_cycle = UINT64_MAX;
168 | 	cycle_enqueued = 0;
169 |     };
170 | };
171 | 
172 | // packet queue
173 | class PACKET_QUEUE {
174 |   public:
175 |     string NAME;
176 |     uint32_t SIZE;
177 | 
178 |     uint8_t  is_RQ, 
179 |              is_WQ,
180 |              write_mode;
181 | 
182 |     uint32_t cpu, 
183 |              head, 
184 |              tail, 
185 |              occupancy, 
186 |              num_returned, 
187 |              next_fill_index, 
188 |              next_schedule_index, 
189 |              next_process_index;
190 | 
191 |     uint64_t next_fill_cycle, 
192 |              next_schedule_cycle, 
193 |              next_process_cycle,
194 |              ACCESS,
195 |              FORWARD,
196 |              MERGED,
197 |              TO_CACHE,
198 |              ROW_BUFFER_HIT,
199 |              ROW_BUFFER_MISS,
200 |              FULL;
201 | 
202 |     PACKET *entry, processed_packet[2*MAX_READ_PER_CYCLE];
203 | 
204 |     // constructor
205 |     PACKET_QUEUE(string v1, uint32_t v2) : NAME(v1), SIZE(v2) {
206 |         is_RQ = 0;
207 |         is_WQ = 0;
208 |         write_mode = 0;
209 | 
210 |         cpu = 0; 
211 |         head = 0;
212 |         tail = 0;
213 |         occupancy = 0;
214 |         num_returned = 0;
215 |         next_fill_index = 0;
216 |         next_schedule_index = 0;
217 |         next_process_index = 0;
218 | 
219 |         next_fill_cycle = UINT64_MAX;
220 |         next_schedule_cycle = UINT64_MAX;
221 |         next_process_cycle = UINT64_MAX;
222 | 
223 |         ACCESS = 0;
224 |         FORWARD = 0;
225 |         MERGED = 0;
226 |         TO_CACHE = 0;
227 |         ROW_BUFFER_HIT = 0;
228 |         ROW_BUFFER_MISS = 0;
229 |         FULL = 0;
230 | 
231 |         entry = new PACKET[SIZE]; 
232 |     };
233 | 
234 |     PACKET_QUEUE() {
235 |         is_RQ = 0;
236 |         is_WQ = 0;
237 | 
238 |         cpu = 0; 
239 |         head = 0;
240 |         tail = 0;
241 |         occupancy = 0;
242 |         num_returned = 0;
243 |         next_fill_index = 0;
244 |         next_schedule_index = 0;
245 |         next_process_index = 0;
246 | 
247 |         next_fill_cycle = UINT64_MAX;
248 |         next_schedule_cycle = UINT64_MAX;
249 |         next_process_cycle = UINT64_MAX;
250 | 
251 |         ACCESS = 0;
252 |         FORWARD = 0;
253 |         MERGED = 0;
254 |         TO_CACHE = 0;
255 |         ROW_BUFFER_HIT = 0;
256 |         ROW_BUFFER_MISS = 0;
257 |         FULL = 0;
258 | 
259 |         //entry = new PACKET[SIZE]; 
260 |     };
261 | 
262 |     // destructor
263 |     ~PACKET_QUEUE() {
264 |         delete[] entry;
265 |     };
266 | 
267 |     // functions
268 |     int check_queue(PACKET* packet);
269 |     void add_queue(PACKET* packet),
270 |          remove_queue(PACKET* packet);
271 | };
272 | 
273 | // reorder buffer
274 | class CORE_BUFFER {
275 |   public:
276 |     const string NAME;
277 |     const uint32_t SIZE;
278 |     uint32_t cpu, 
279 |              head, 
280 |              tail,
281 |              occupancy,
282 |              last_read, last_fetch, last_scheduled, 
283 |              inorder_fetch[2],
284 |              next_fetch[2],
285 |              next_schedule;
286 |     uint64_t event_cycle,
287 |              fetch_event_cycle,
288 |              schedule_event_cycle,
289 |              execute_event_cycle,
290 |              lsq_event_cycle,
291 |              retire_event_cycle;
292 | 
293 |     ooo_model_instr *entry;
294 | 
295 |     // constructor
296 |     CORE_BUFFER(string v1, uint32_t v2) : NAME(v1), SIZE(v2) {
297 |         head = 0;
298 |         tail = 0;
299 |         occupancy = 0;
300 | 
301 |         last_read = SIZE-1;
302 |         last_fetch = SIZE-1;
303 |         last_scheduled = 0;
304 | 
305 |         inorder_fetch[0] = 0;
306 |         inorder_fetch[1] = 0;
307 |         next_fetch[0] = 0;
308 |         next_fetch[1] = 0;
309 |         next_schedule = 0;
310 | 
311 |         event_cycle = 0;
312 |         fetch_event_cycle = UINT64_MAX;
313 |         schedule_event_cycle = UINT64_MAX;
314 |         execute_event_cycle = UINT64_MAX;
315 |         lsq_event_cycle = UINT64_MAX;
316 |         retire_event_cycle = UINT64_MAX;
317 | 
318 |         entry = new ooo_model_instr[SIZE];
319 |     };
320 | 
321 |     // destructor
322 |     ~CORE_BUFFER() {
323 |         delete[] entry;
324 |     };
325 | };
326 | 
327 | // load/store queue 
328 | class LSQ_ENTRY {
329 |   public:
330 |     uint64_t instr_id,
331 |              producer_id,
332 |              virtual_address,
333 |              physical_address,
334 |              ip,
335 |              event_cycle;
336 | 
337 |     uint32_t rob_index, data_index, sq_index;
338 | 
339 |     uint8_t translated,
340 |             fetched,
341 |             asid[2];
342 | // forwarding_depend_on_me[ROB_SIZE];
343 |     fastset
344 | 		forwarding_depend_on_me;
345 | 
346 |     // constructor
347 |     LSQ_ENTRY() {
348 |         instr_id = 0;
349 |         producer_id = UINT64_MAX;
350 |         virtual_address = 0;
351 |         physical_address = 0;
352 |         ip = 0;
353 |         event_cycle = 0;
354 | 
355 |         rob_index = 0;
356 |         data_index = 0;
357 |         sq_index = UINT32_MAX;
358 | 
359 |         translated = 0;
360 |         fetched = 0;
361 |         asid[0] = UINT8_MAX;
362 |         asid[1] = UINT8_MAX;
363 | 
364 | #if 0
365 |         for (uint32_t i=0; i<ROB_SIZE; i++)
366 |             forwarding_depend_on_me[i] = 0;
367 | #endif
368 |     };
369 | };
370 | 
371 | class LOAD_STORE_QUEUE {
372 |   public:
373 |     const string NAME;
374 |     const uint32_t SIZE;
375 |     uint32_t occupancy, head, tail;
376 | 
377 |     LSQ_ENTRY *entry;
378 | 
379 |     // constructor
380 |     LOAD_STORE_QUEUE(string v1, uint32_t v2) : NAME(v1), SIZE(v2) {
381 |         occupancy = 0;
382 |         head = 0;
383 |         tail = 0;
384 | 
385 |         entry = new LSQ_ENTRY[SIZE];
386 |     };
387 | 
388 |     // destructor
389 |     ~LOAD_STORE_QUEUE() {
390 |         delete[] entry;
391 |     };
392 | };
393 | #endif
394 | 


--------------------------------------------------------------------------------
/branch/perceptron.bpred:
--------------------------------------------------------------------------------
  1 | /*
  2 |  * Copyright (c) 2001 University of Texas at Austin
  3 |  *
  4 |  * Daniel A. Jimenez
  5 |  * Calvin Lin
  6 |  *
  7 |  * Permission is hereby granted, free of charge, to any person 
  8 |  * obtaining a copy of this software (the "Software"), to deal in
  9 |  * the Software without restriction, including without limitation 
 10 |  * the rights to use, copy, modify, merge, publish, distribute, sublicense, 
 11 |  * and/or sell copies of the Software, and to permit persons to whom the 
 12 |  * Software is furnished to do so, subject to the following conditions:
 13 |  *
 14 |  * The above copyright notice and this permission notice shall be
 15 |  * included in all copies or substantial portions of the Software.
 16 |  *
 17 |  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 18 |  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 19 |  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 20 |  * NONINFRINGEMENT.  IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT
 21 |  * AUSTIN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 22 |  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 23 |  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 24 |  * THE SOFTWARE.
 25 |  *
 26 |  * This file implements the simulated perceptron branch predictor from:
 27 |  *
 28 |  * Jimenez, D. A. & Lin, C., Dynamic branch prediction with perceptrons,
 29 |  * Proceedings of the Seventh International Symposium on High Performance
 30 |  * Computer Architecture (HPCA), Monterrey, NL, Mexico 2001
 31 |  *
 32 |  * The #define's here specify a perceptron predictor with a history
 33 |  * length of 24, 163 perceptrons, and  8-bit weights.  This represents
 34 |  * a hardware budget of (24+1)*8*163 = 32600 bits, or about 4K bytes,
 35 |  * which is comparable to the hardware budget of the Alpha 21264 hybrid
 36 |  * branch predictor.
 37 |  *
 38 |  * There are three important functions defined in this file:
 39 |  * 
 40 |  * 1. void initialize_perceptron_predictor (void);
 41 |  * Initialize the perceptron predictor
 42 |  *
 43 |  * 2. perceptron_state *perceptron_dir_lookup (unsigned int);
 44 |  * Get a branch prediction, given a branch address.  This function returns a
 45 |  * pointer to a 'perceptron_state' struct, which contains the prediction, the
 46 |  * perceptron output, and other information necessary for using and updating
 47 |  * the predictor.  The first member of a 'perceptron_state' struct is a char
 48 |  * that is assigned 3 if the branch is predicted taken, 0 otherwise; this way,
 49 |  * a pointer to 'perceptron_state' can be cast to (char *) and passed around
 50 |  * SimpleScalar as though it were a pointer to a pattern history table entry.
 51 |  *
 52 |  * 3. void perceptron_update (perceptron_state *, int);
 53 |  * Update the branch predictor using the 'perceptron_state' pointer 
 54 |  * returned by perceptron_dir_lookup() and an int that is 1 if the branch
 55 |  * was taken, 0 otherwise.
 56 |  */
 57 | 
 58 | #include "ooo_cpu.h"
 59 | 
 60 | /* history length for the global history shift register */
 61 | 
 62 | #define PERCEPTRON_HISTORY	24
 63 | 
 64 | /* number of perceptrons */
 65 | 
 66 | #define NUM_PERCEPTRONS		163
 67 | 
 68 | /* number of bits per weight */
 69 | 
 70 | #define PERCEPTRON_BITS		8
 71 | 
 72 | /* maximum and minimum weight values */
 73 | 
 74 | #define MAX_WEIGHT		((1<<(PERCEPTRON_BITS-1))-1)
 75 | #define MIN_WEIGHT		(-(MAX_WEIGHT+1))
 76 | 
 77 | /* threshold for training */
 78 | 
 79 | #define THETA			((int) (1.93 * PERCEPTRON_HISTORY + 14))
 80 | 
 81 | /* size of buffer for keeping 'perceptron_state' for update */
 82 | 
 83 | #define NUM_UPDATE_ENTRIES	100
 84 | 
 85 | /* perceptron data structure */
 86 | 
 87 | typedef struct {
 88 | 	int	
 89 | 		/* just a vector of integers */
 90 | 
 91 | 		weights[PERCEPTRON_HISTORY+1];
 92 | } perceptron;
 93 | 
 94 | /* 'perceptron_state' - stores the branch prediction and keeps information
 95 |  * such as output and history needed for updating the perceptron predictor
 96 |  */
 97 | typedef struct {
 98 | 	char	
 99 | 		/* this char emulates a pattern history	table entry
100 | 		 * with a value of 0 for "predict not taken" or 3 for 
101 | 		 * "predict taken," so a perceptron_state pointer can 
102 | 		 * be passed around SimpleScalar's branch prediction 
103 | 		 * infrastructure without changing too much stuff.
104 | 		 */
105 | 		dummy_counter;
106 | 
107 | 	int
108 | 		/* prediction: 1 for taken, 0 for not taken */
109 | 
110 | 		prediction,
111 | 
112 | 		/* perceptron output */
113 | 
114 | 		output;
115 | 
116 | 	unsigned long long int 
117 | 		/* value of the history register yielding this prediction */
118 | 
119 | 		history;
120 | 
121 | 	perceptron
122 | 		/* pointer to the perceptron yielding this prediction */
123 | 
124 | 		*perc;
125 | } perceptron_state;
126 | 
127 | perceptron 
128 | 	/* table of perceptrons */
129 | 
130 | 	perceptrons[NUM_CPUS][NUM_PERCEPTRONS];
131 | 
132 | perceptron_state 
133 | 	/* state for updating perceptron predictor */
134 | 
135 | 	perceptron_state_buf[NUM_CPUS][NUM_UPDATE_ENTRIES];
136 | 
137 | int 
138 | 	/* index of the next "free" perceptron_state */
139 | 
140 | 	perceptron_state_buf_ctr[NUM_CPUS];
141 | 
142 | unsigned long long int
143 | 
144 | 	/* speculative global history - updated by predictor */
145 | 
146 | 	spec_global_history[NUM_CPUS],
147 | 
148 | 	/* real global history - updated when the predictor is updated */
149 | 
150 | 	global_history[NUM_CPUS];
151 | 
152 | perceptron_state *u[NUM_CPUS];
153 | 
154 | /* initialize a single perceptron */
155 | void initialize_perceptron (perceptron *p) {
156 |     int	i;
157 | 
158 |     for (i=0; i<=PERCEPTRON_HISTORY; i++) p->weights[i] = 0;
159 | }
160 | 
161 | void O3_CPU::initialize_branch_predictor()
162 | {
163 |     spec_global_history[cpu] = 0;
164 |     global_history[cpu] = 0;
165 |     perceptron_state_buf_ctr[cpu] = 0;
166 |     for (int i=0; i<NUM_PERCEPTRONS; i++)
167 |         initialize_perceptron (&perceptrons[cpu][i]);
168 | }
169 | 
170 | uint8_t O3_CPU::predict_branch(uint64_t ip)
171 | {
172 |     uint64_t address = ip;
173 | 
174 |     int	
175 |         index,
176 |         i,
177 |         output,
178 |         *w;
179 |     unsigned long long int 
180 |         mask;
181 |     perceptron 
182 |         *p;
183 | 
184 |     /* get a pointer to the next "free" perceptron_state,
185 |      * bumping up the pointer (and possibly letting it wrap around) 
186 |      */
187 | 
188 |     u[cpu] = &perceptron_state_buf[cpu][perceptron_state_buf_ctr[cpu]++];
189 |     if (perceptron_state_buf_ctr[cpu] >= NUM_UPDATE_ENTRIES)
190 |         perceptron_state_buf_ctr[cpu] = 0;
191 | 
192 |     /* hash the address to get an index into the table of perceptrons */
193 | 
194 |     index = address % NUM_PERCEPTRONS;
195 | 
196 |     /* get pointers to that perceptron and its weights */
197 | 
198 |     p = &perceptrons[cpu][index];
199 |     w = &p->weights[0];
200 | 
201 |     /* initialize the output to the bias weight, and bump the pointer
202 |      * to the weights
203 |      */
204 | 
205 |     output = *w++;
206 | 
207 |     /* find the (rest of the) dot product of the history register
208 |      * and the perceptron weights.  note that, instead of actually
209 |      * doing the expensive multiplies, we simply add a weight when the
210 |      * corresponding branch in the history register is taken, or
211 |      * subtract a weight when the branch is not taken.  this also lets
212 |      * us use binary instead of bipolar logic to represent the history
213 |      * register
214 |      */
215 |     for (mask=1,i=0; i<PERCEPTRON_HISTORY; i++,mask<<=1,w++) {
216 |         if (spec_global_history[cpu] & mask)
217 |             output += *w;
218 |         else
219 |             output += -*w;
220 |     }
221 | 
222 |     /* record the various values needed to update the predictor */
223 | 
224 |     u[cpu]->output = output;
225 |     u[cpu]->perc = p;
226 |     u[cpu]->history = spec_global_history[cpu];
227 |     u[cpu]->prediction = output >= 0;
228 |     u[cpu]->dummy_counter = u[cpu]->prediction ? 3 : 0;
229 | 
230 |     /* update the speculative global history register */
231 | 
232 |     spec_global_history[cpu] <<= 1;
233 |     spec_global_history[cpu] |= u[cpu]->prediction;
234 |     return u[cpu]->prediction;
235 | }
236 | 
237 | void O3_CPU::last_branch_result(uint64_t ip, uint8_t taken)
238 | {
239 |     int	
240 |         i,
241 |         y, 
242 |         *w;
243 | 
244 |     unsigned long long int
245 |         mask, 
246 |         history;
247 | 
248 |     /* update the real global history shift register */
249 | 
250 |     global_history[cpu] <<= 1;
251 |     global_history[cpu] |= taken;
252 | 
253 |     /* if this branch was mispredicted, restore the speculative
254 |      * history to the last known real history
255 |      */
256 | 
257 |     if (u[cpu]->prediction != taken) spec_global_history[cpu] = global_history[cpu];
258 | 
259 |     /* if the output of the perceptron predictor is outside of
260 |      * the range [-THETA,THETA] *and* the prediction was correct,
261 |      * then we don't need to adjust the weights
262 |      */
263 | 
264 |     if (u[cpu]->output > THETA)
265 |         y = 1;
266 |     else if (u[cpu]->output < -THETA)
267 |         y = 0;
268 |     else
269 |         y = 2;
270 |     if (y == 1 && taken) return;
271 |     if (y == 0 && !taken) return;
272 | 
273 |     /* w is a pointer to the first weight (the bias weight) */
274 | 
275 |     w = &u[cpu]->perc->weights[0];
276 | 
277 |     /* if the branch was taken, increment the bias weight,
278 |      * else decrement it, with saturating arithmetic
279 |      */
280 | 
281 |     if (taken)
282 |         (*w)++;
283 |     else
284 |         (*w)--;
285 |     if (*w > MAX_WEIGHT) *w = MAX_WEIGHT;
286 |     if (*w < MIN_WEIGHT) *w = MIN_WEIGHT;
287 | 
288 |     /* now w points to the next weight */
289 | 
290 |     w++;
291 | 
292 |     /* get the history that led to this prediction */
293 | 
294 |     history = u[cpu]->history;
295 | 
296 |     /* for each weight and corresponding bit in the history register... */
297 | 
298 |     for (mask=1,i=0; i<PERCEPTRON_HISTORY; i++,mask<<=1,w++) {
299 | 
300 |         /* if the i'th bit in the history positively correlates
301 |          * with this branch outcome, increment the corresponding 
302 |          * weight, else decrement it, with saturating arithmetic
303 |          */
304 | 
305 |         if (!!(history & mask) == taken) { // a common trick to conver to boolean => !!x is 1 iff x is not zero, in this case history is positively correlated with branch outcome
306 |             (*w)++;
307 |             if (*w > MAX_WEIGHT) *w = MAX_WEIGHT;
308 |         } else {
309 |             (*w)--;
310 |             if (*w < MIN_WEIGHT) *w = MIN_WEIGHT;
311 |         }
312 |     }
313 | }
314 | 


--------------------------------------------------------------------------------
/inc/ooo_cpu.h:
--------------------------------------------------------------------------------
  1 | #ifndef OOO_CPU_H
  2 | #define OOO_CPU_H
  3 | 
  4 | #include "cache.h"
  5 | 
  6 | #ifdef CRC2_COMPILE
  7 | #define STAT_PRINTING_PERIOD 1000000
  8 | #else
  9 | #define STAT_PRINTING_PERIOD 10000000
 10 | #endif
 11 | #define DEADLOCK_CYCLE 1000000
 12 | 
 13 | using namespace std;
 14 | 
 15 | // CORE PROCESSOR
 16 | #define FETCH_WIDTH 6
 17 | #define DECODE_WIDTH 6
 18 | #define EXEC_WIDTH 6
 19 | #define LQ_WIDTH 2
 20 | #define SQ_WIDTH 2
 21 | #define RETIRE_WIDTH 4
 22 | #define SCHEDULER_SIZE 128
 23 | #define BRANCH_MISPREDICT_PENALTY 1
 24 | //#define SCHEDULING_LATENCY 0
 25 | //#define EXEC_LATENCY 0
 26 | //#define DECODE_LATENCY 2
 27 | 
 28 | #define STA_SIZE (ROB_SIZE*NUM_INSTR_DESTINATIONS_SPARC)
 29 | 
 30 | extern uint32_t SCHEDULING_LATENCY, EXEC_LATENCY, DECODE_LATENCY;
 31 | 
 32 | struct BTB_outcome {
 33 | 		uint64_t target;
 34 | 		uint8_t branch_type;
 35 | 		uint8_t sequential_BTB_access;
 36 | };
 37 | 
 38 | // cpu
 39 | class O3_CPU {
 40 |   public:
 41 | 	bool skip_next_cycle;
 42 |     uint32_t cpu;
 43 | 
 44 |     // trace
 45 |     FILE *trace_file;
 46 |     char trace_string[1024];
 47 |     char gunzip_command[1024];
 48 | 
 49 |     // instruction
 50 |     input_instr next_instr;
 51 |     input_instr current_instr;
 52 |     cloudsuite_instr current_cloudsuite_instr;
 53 |     uint64_t instr_unique_id, completed_executions, 
 54 |              begin_sim_cycle, begin_sim_instr, 
 55 |              last_sim_cycle, last_sim_instr,
 56 |              finish_sim_cycle, finish_sim_instr,
 57 |              warmup_instructions, simulation_instructions, instrs_to_read_this_cycle, instrs_to_fetch_this_cycle,
 58 |              next_print_instruction, num_retired;
 59 |     uint32_t inflight_reg_executions, inflight_mem_executions, num_searched;
 60 |     uint32_t next_ITLB_fetch;
 61 | 
 62 |     // reorder buffer, load/store queue, register file
 63 |     CORE_BUFFER IFETCH_BUFFER{"IFETCH_BUFFER", /*128*/FETCH_WIDTH*2};
 64 |     CORE_BUFFER DECODE_BUFFER{"DECODE_BUFFER", DECODE_WIDTH*3};
 65 |     CORE_BUFFER ROB{"ROB", ROB_SIZE};
 66 |     LOAD_STORE_QUEUE LQ{"LQ", LQ_SIZE}, SQ{"SQ", SQ_SIZE};
 67 | 
 68 |     // store array, this structure is required to properly handle store instructions
 69 |     uint64_t STA[STA_SIZE], STA_head, STA_tail; 
 70 | 
 71 |     // Ready-To-Execute
 72 |     uint32_t RTE0[ROB_SIZE], RTE0_head, RTE0_tail, 
 73 |              RTE1[ROB_SIZE], RTE1_head, RTE1_tail;  
 74 | 
 75 |     // Ready-To-Load
 76 |     uint32_t RTL0[LQ_SIZE], RTL0_head, RTL0_tail, 
 77 |              RTL1[LQ_SIZE], RTL1_head, RTL1_tail;  
 78 | 
 79 |     // Ready-To-Store
 80 |     uint32_t RTS0[SQ_SIZE], RTS0_head, RTS0_tail,
 81 |              RTS1[SQ_SIZE], RTS1_head, RTS1_tail;
 82 | 
 83 |     // branch
 84 |     int branch_mispredict_stall_fetch; // flag that says that we should stall because a branch prediction was wrong
 85 |     int mispredicted_branch_iw_index; // index in the instruction window of the mispredicted branch.  fetch resumes after the instruction at this index executes
 86 |     uint8_t  fetch_stall;
 87 |     uint64_t fetch_resume_cycle;
 88 |     uint64_t nextInstPC;
 89 |     uint32_t IBUF_occupancy;
 90 |     uint64_t num_branch, branch_mispredictions, branch_direction_mispredictions, branch_target_mispredictions1, branch_target_mispredictions2;
 91 |     uint64_t mispredict_on_btb_hit;
 92 |     uint64_t total_rob_occupancy_at_branch_mispredict;
 93 |   uint64_t total_branch_types[8];
 94 |   uint64_t mispredicted_branch_types[8];
 95 |   uint64_t BTB_reads, BTB_writes, PageBTB_reads, PageBTB_writes, PageBTB_readsBeforeWrite, RegionBTB_reads, RegionBTB_writes, RegionBTB_readsBeforeWrite;
 96 |   std::map<uint64_t, std::set<uint64_t>> branchesInCB;
 97 |   std::set<uint64_t> unique_branchPC;
 98 |     uint64_t offset_size[132];
 99 |     uint64_t BTB_4D_Hits, BTB_6D_Hits, BTB_8D_Hits, BTB_12D_Hits, BTB_18D_Hits, BTB_25D_Hits, BTB_46D_Hits, BTB_Ret_Hits;
100 |     uint64_t BTB_4D_Misses, BTB_6D_Misses, BTB_8D_Misses, BTB_12D_Misses, BTB_18D_Misses, BTB_25D_Misses, BTB_46D_Misses, BTB_Ret_Misses;
101 |            
102 | 
103 |     // TLBs and caches
104 |     CACHE ITLB{"ITLB", ITLB_SET, ITLB_WAY, ITLB_SET*ITLB_WAY, ITLB_WQ_SIZE, ITLB_RQ_SIZE, ITLB_PQ_SIZE, ITLB_MSHR_SIZE},
105 |           DTLB{"DTLB", DTLB_SET, DTLB_WAY, DTLB_SET*DTLB_WAY, DTLB_WQ_SIZE, DTLB_RQ_SIZE, DTLB_PQ_SIZE, DTLB_MSHR_SIZE},
106 |           STLB{"STLB", STLB_SET, STLB_WAY, STLB_SET*STLB_WAY, STLB_WQ_SIZE, STLB_RQ_SIZE, STLB_PQ_SIZE, STLB_MSHR_SIZE},
107 |           L1I{"L1I", L1I_SET, L1I_WAY, L1I_SET*L1I_WAY, L1I_WQ_SIZE, L1I_RQ_SIZE, L1I_PQ_SIZE, L1I_MSHR_SIZE},
108 |           L1D{"L1D", L1D_SET, L1D_WAY, L1D_SET*L1D_WAY, L1D_WQ_SIZE, L1D_RQ_SIZE, L1D_PQ_SIZE, L1D_MSHR_SIZE},
109 |           L2C{"L2C", L2C_SET, L2C_WAY, L2C_SET*L2C_WAY, L2C_WQ_SIZE, L2C_RQ_SIZE, L2C_PQ_SIZE, L2C_MSHR_SIZE};
110 | 
111 |   // trace cache for previously decoded instructions
112 |   
113 |     // constructor
114 |     O3_CPU() {
115 |         cpu = 0;
116 | 
117 |         // trace
118 |         trace_file = NULL;
119 |         skip_next_cycle = false;
120 | 
121 |         // instruction
122 |         instr_unique_id = 0;
123 |         completed_executions = 0;
124 |         begin_sim_cycle = 0;
125 |         begin_sim_instr = 0;
126 |         last_sim_cycle = 0;
127 |         last_sim_instr = 0;
128 |         finish_sim_cycle = 0;
129 |         finish_sim_instr = 0;
130 |         warmup_instructions = 0;
131 |         simulation_instructions = 0;
132 |         instrs_to_read_this_cycle = 0;
133 |         instrs_to_fetch_this_cycle = 0;
134 | 
135 |         next_print_instruction = STAT_PRINTING_PERIOD;
136 |         num_retired = 0;
137 | 
138 |         inflight_reg_executions = 0;
139 |         inflight_mem_executions = 0;
140 |         num_searched = 0;
141 | 
142 |         next_ITLB_fetch = 0;
143 | 
144 |         // branch
145 |         branch_mispredict_stall_fetch = 0;
146 |         mispredicted_branch_iw_index = 0;
147 |         fetch_stall = 0;
148 | 	fetch_resume_cycle = 0;
149 |         nextInstPC = 0;
150 |         IBUF_occupancy = 0;
151 |         num_branch = 0;
152 |         branch_mispredictions = 0;
153 |         branch_direction_mispredictions = 0;
154 |         branch_target_mispredictions1 = 0;
155 |         branch_target_mispredictions2 = 0;
156 |         mispredict_on_btb_hit = 0;
157 | 	for(uint32_t i=0; i<8; i++)
158 | 	  {
159 | 	    total_branch_types[i] = 0;
160 | 	    mispredicted_branch_types[i] = 0;
161 | 	  }
162 | 	BTB_reads = BTB_writes = PageBTB_reads = PageBTB_writes = PageBTB_readsBeforeWrite = RegionBTB_reads = RegionBTB_writes = RegionBTB_readsBeforeWrite = 0;
163 | 	branchesInCB.clear();
164 | 	unique_branchPC.clear();
165 | 	for(uint32_t i=0; i<132; i++)
166 | 	  {
167 | 	    offset_size[i] = 0;
168 | 	  }
169 | 
170 | 	BTB_4D_Hits = BTB_6D_Hits = BTB_8D_Hits = BTB_12D_Hits = BTB_18D_Hits = BTB_25D_Hits = BTB_46D_Hits = BTB_Ret_Hits = 0;
171 | 	BTB_4D_Misses = BTB_6D_Misses = BTB_8D_Misses = BTB_12D_Misses = BTB_18D_Misses = BTB_25D_Misses = BTB_46D_Misses = BTB_Ret_Misses = 0;
172 | 	
173 |         for (uint32_t i=0; i<STA_SIZE; i++)
174 | 	  STA[i] = UINT64_MAX;
175 |         STA_head = 0;
176 |         STA_tail = 0;
177 | 
178 |         for (uint32_t i=0; i<ROB_SIZE; i++) {
179 | 	  RTE0[i] = ROB_SIZE;
180 | 	  RTE1[i] = ROB_SIZE;
181 |         }
182 |         RTE0_head = 0;
183 |         RTE1_head = 0;
184 |         RTE0_tail = 0;
185 |         RTE1_tail = 0;
186 | 
187 |         for (uint32_t i=0; i<LQ_SIZE; i++) {
188 | 	  RTL0[i] = LQ_SIZE;
189 | 	  RTL1[i] = LQ_SIZE;
190 |         }
191 |         RTL0_head = 0;
192 |         RTL1_head = 0;
193 |         RTL0_tail = 0;
194 |         RTL1_tail = 0;
195 | 
196 |         for (uint32_t i=0; i<SQ_SIZE; i++) {
197 | 	  RTS0[i] = SQ_SIZE;
198 | 	  RTS1[i] = SQ_SIZE;
199 |         }
200 |         RTS0_head = 0;
201 |         RTS1_head = 0;
202 |         RTS0_tail = 0;
203 |         RTS1_tail = 0;
204 |     }
205 | 
206 |     // functions
207 |     void read_from_trace(),
208 |          spec_inst_prefetch(),
209 |          fetch_instruction(),
210 |          decode_and_dispatch(),
211 |          schedule_instruction(),
212 |          execute_instruction(),
213 |          schedule_memory_instruction(),
214 |          execute_memory_instruction(),
215 |          do_scheduling(uint32_t rob_index),  
216 |          reg_dependency(uint32_t rob_index),
217 |          do_execution(uint32_t rob_index),
218 |          do_memory_scheduling(uint32_t rob_index),
219 |          operate_lsq(),
220 |          complete_execution(uint32_t rob_index),
221 |          reg_RAW_dependency(uint32_t prior, uint32_t current, uint32_t source_index),
222 |          reg_RAW_release(uint32_t rob_index),
223 |          mem_RAW_dependency(uint32_t prior, uint32_t current, uint32_t data_index, uint32_t lq_index),
224 |          handle_o3_fetch(PACKET *current_packet, uint32_t cache_type),
225 |          handle_merged_translation(PACKET *provider),
226 |          handle_merged_load(PACKET *provider),
227 |          release_load_queue(uint32_t lq_index),
228 |          complete_instr_fetch(PACKET_QUEUE *queue, uint8_t is_it_tlb),
229 |          complete_data_fetch(PACKET_QUEUE *queue, uint8_t is_it_tlb);
230 | 
231 |     void initialize_core();
232 |     void add_load_queue(uint32_t rob_index, uint32_t data_index),
233 |          add_store_queue(uint32_t rob_index, uint32_t data_index),
234 |          execute_store(uint32_t rob_index, uint32_t sq_index, uint32_t data_index);
235 |     int  execute_load(uint32_t rob_index, uint32_t sq_index, uint32_t data_index);
236 |     void check_dependency(int prior, int current);
237 |     void operate_cache();
238 |     void update_rob();
239 |     void retire_rob();
240 | 
241 |     uint32_t  add_to_rob(ooo_model_instr *arch_instr),
242 |               check_rob(uint64_t instr_id);
243 | 
244 |     uint32_t add_to_ifetch_buffer(ooo_model_instr *arch_instr);
245 |     uint32_t add_to_decode_buffer(ooo_model_instr *arch_instr);
246 | 
247 |     uint32_t check_and_add_lsq(uint32_t rob_index);
248 | 
249 |     // branch predictor
250 |     uint8_t predict_branch(uint64_t ip);
251 |     void    initialize_branch_predictor(),
252 |             last_branch_result(uint64_t ip, uint8_t taken);
253 | 
254 |     BTB_outcome btb_prediction(uint64_t ip, uint8_t branch_type);
255 |     void initialize_btb(),
256 |       update_btb(uint64_t ip, uint64_t branch_target, uint8_t taken, uint8_t branch_type);
257 | 
258 |   // code prefetching
259 |   void l1i_prefetcher_initialize();
260 |   void l1i_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target);
261 |   void l1i_prefetcher_instruction_operate(uint64_t ip);
262 |   void l1i_prefetcher_instruction_spec_operate(uint64_t ip);
263 |   void l1i_prefetcher_cache_operate(uint64_t v_addr, uint8_t cache_hit, uint8_t prefetch_hit);
264 |   void l1i_prefetcher_cycle_operate();
265 |   void l1i_prefetcher_cache_fill(uint64_t v_addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_v_addr);
266 |   void l1i_prefetcher_final_stats();
267 |   int prefetch_code_line(uint64_t pf_v_addr); 
268 | };
269 | 
270 | extern O3_CPU ooo_cpu[NUM_CPUS];
271 | 
272 | #endif
273 | 


--------------------------------------------------------------------------------
/prefetcher/ipc-2020-paper41-code:
--------------------------------------------------------------------------------
  1 | #include "ooo_cpu.h"
  2 | #include <stack>
  3 | #include <algorithm>
  4 | #include <math.h>
  5 | 
  6 | 
  7 | /**************************************** Basic Structures **************************************/
  8 | 
  9 | // FTQ entry struct
 10 | struct FTQEntry {
 11 |   bool end_found;
 12 |   uint64_t first_ip;
 13 |   uint64_t last_ip;
 14 |   FTQEntry (bool endFound, uint64_t firstIP, uint64_t lastIP) {
 15 | 	  end_found = endFound;
 16 | 	  first_ip = firstIP;
 17 | 	  last_ip = lastIP;
 18 |   }
 19 | };
 20 | 
 21 | // BTB entry struct
 22 | struct BTBEntry {
 23 |   uint8_t branch_type; //2-bits (We only use four categories: conditional, call, return, and other.)
 24 |   uint64_t tag;		   //16-bits
 25 |   uint64_t target_ip;  //We use four different BTBs based of the number of bits required to encode branch target offset. This field can be 10-bits, 15-bits, 25-bits, or 64-bits.
 26 |   BTBEntry( ) {}
 27 | 
 28 | };
 29 | 
 30 | struct BTB {
 31 | 	std::vector <std::vector<BTBEntry>> theBTB;
 32 | 	uint32_t numSets;
 33 | 	uint32_t assoc;
 34 | 	uint64_t indexMask;
 35 | 	uint32_t numIndexBits;
 36 | 
 37 |     BTB( int32_t Sets, int32_t Assoc )
 38 |       : numSets(Sets)
 39 |         , assoc(Assoc) {
 40 |           //aBTBSize must be a power of 2
 41 |           assert( ((Sets - 1) & (Sets)) == 0);
 42 |           theBTB.resize(Sets);
 43 |           indexMask = Sets - 1;
 44 |           numIndexBits = (uint32_t) log2((double)Sets);
 45 |         }
 46 | 
 47 |     int32_t index(uint64_t ip) {
 48 |     	if (ip & 0x3) {
 49 |     		return ((ip) & indexMask);
 50 |     	} else {
 51 |     		return ((ip >> 2) & indexMask);
 52 |     	}
 53 |     }
 54 | 
 55 |     uint64_t get_tag(uint64_t ip) {
 56 |     	uint64_t addr = ip;
 57 |     	if (!(addr & 0x3)) {
 58 |     		addr = addr >> 2;
 59 |     	}
 60 |     	addr = addr >> numIndexBits;
 61 |     	/* We use a 16-bit tag.
 62 |     	 * The lower 8-bits stay the same as in the full tag.
 63 |     	 * The upper 8-bits are the folded X-OR of the remaining bits of the full tag.
 64 |     	 */
 65 |     	uint64_t tag = addr & 0xFF; //Set the lower 8-bits of the tag
 66 |     	addr = addr >> 8;
 67 |     	int tagMSBs = 0;
 68 |     	/*Get the upper 8-bits (folded X-OR)*/
 69 |     	for (int i = 0; i < 8; i++) {
 70 |     		tagMSBs = tagMSBs ^ (addr & 0xFF);
 71 |     		addr = addr >> 8;
 72 |     	}
 73 |     	/*Concatenate the lower and upper 8-bits of tag*/
 74 |     	tag = tag | (tagMSBs << 8);
 75 |     	return tag;
 76 |     }
 77 | 
 78 |     BTBEntry *get_BTBentry(uint64_t ip){
 79 |     	BTBEntry *entry = NULL;
 80 | 
 81 |     	int idx = index(ip);
 82 |     	uint64_t tag = get_tag(ip);
 83 |     	for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 84 |     		if (theBTB[idx][i].tag == tag) {
 85 |     			return &(theBTB[idx][i]);
 86 |     		}
 87 |     	}
 88 | 
 89 |     	return entry;
 90 |     }
 91 | 
 92 |     void update_BTB(uint64_t ip, uint8_t b_type, uint64_t target){
 93 |     	int idx = index(ip);
 94 |     	uint64_t tag = get_tag(ip);
 95 |     	int way = -1;
 96 |     	for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 97 |     		if (theBTB[idx][i].tag == tag) {
 98 |     			way = i;
 99 |     			break;
100 |     		}
101 |     	}
102 | 
103 |     	if (way == -1) {
104 |     		BTBEntry entry;
105 |     		entry.tag = tag;
106 |     		entry.branch_type = b_type;
107 |     		entry.target_ip = target;
108 | 
109 |     		if (theBTB[idx].size() >= assoc) {
110 |     			theBTB[idx].erase(theBTB[idx].begin());
111 |     		}
112 |     		theBTB[idx].push_back(entry);
113 |     	} else {
114 |     		BTBEntry entry = theBTB[idx][way];
115 |     		entry.branch_type = b_type;
116 |     		if (target != 0) {
117 |     			entry.target_ip = target;
118 |     		}
119 | 
120 |     		//Update LRU
121 |     		theBTB[idx].erase(theBTB[idx].begin() + way);
122 |     		theBTB[idx].push_back(entry);
123 |     	}
124 |     }
125 | 
126 | };
127 | 
128 | 
129 | #define MAX_BTB_LOOKUPs 19
130 | #define MAX_FTQ_ENTRIES 48
131 | #define MAX_PFETCHQ_ENTRIES 48
132 | #define MAX_RECENT_PFETCH 10
133 | #define MAX_RAS_ENTRIES 128
134 | 
135 | 
136 | uint64_t pfetch_ip = 0x0;
137 | uint64_t disp[66] = {0};
138 | 
139 | /**************************************** Compoenets for prefetching **************************************/
140 | 
141 | std::queue<FTQEntry> FTQ;				//Storage: 129-bits (FTQ-entry size) * 48 (number of FTQ entries) = 774 bytes
142 | std::deque<uint64_t> prefetch_queue;	//Storage: 64-bits * 48 (queue size) = 384 bytes
143 | std::deque<uint64_t> recent_prefetches;	//Storage: 64-bits * 10 (queue size) = 80 bytes
144 | 
145 | std::stack<uint64_t> RAS;				//Storage: 64-bits * 128 (size) = 1KB
146 | std::stack<uint64_t> RAS_Pfetch;		//Storage: 64-bits * 128 (size) = 1KB
147 | 
148 | 
149 | BTB BTB_10D(1024, 8);					//Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 10-bit) 28*1024*8 = 28KB
150 | BTB BTB_15D(1024, 7);					//Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 15-bit) 33*1024*7 = 28.875KB
151 | BTB BTB_25D(1024, 8);					//Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 25-bit) 43*1024*8 = 43KB
152 | BTB BTB_64D(256, 4);					//Storage: (tag:16-bit, branch-type: 2-bit,   full-target: 64-bit) 82*256*4  = 10.25KB
153 | 
154 | 
155 | 
156 | /**************************************** Prefetcher Operation **************************************/
157 | 
158 | 
159 | 
160 | void O3_CPU::l1i_prefetcher_initialize() 
161 | {
162 | 
163 | }
164 | 
165 | void O3_CPU::l1i_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
166 | {
167 | 	if (branch_target) {
168 | 		/*Find the number of bits needed to encode the target offset*/
169 | 		uint64_t target_offset;
170 | 		if (branch_target > ip) {
171 | 			target_offset = branch_target - ip;
172 | 		} else {
173 | 			target_offset = ip - branch_target;
174 | 		}
175 | 		int num_bits = (int)(log2((double)target_offset));
176 | 		/* The cast "(int)log2" rounds down to lower integer, however we want to round it to upper integer, so add 1 to "num_bits"
177 | 		 * As an offset can be both positive and negative, we need to add 1 sign bit to "num_bits".
178 | 		 * */
179 | 		num_bits += 2;
180 | 		disp[num_bits]++;
181 | 		assert(num_bits >= 0 && num_bits < 66);
182 | 
183 | 		/*Store (or update) the branch in one of the BTBs based on the number of bits required to encode the target offset*/
184 | 		if (num_bits <= 10) {
185 | 			BTB_10D.update_BTB(ip, branch_type, branch_target);
186 | 		} else if (num_bits <= 15) {
187 | 			BTB_15D.update_BTB(ip, branch_type, branch_target);
188 | 		} else if (num_bits <= 25) {
189 | 			BTB_25D.update_BTB(ip, branch_type, branch_target);
190 | 		} else {
191 | 			BTB_64D.update_BTB(ip, branch_type, branch_target);
192 | 		}
193 | 	}
194 | 
195 | 
196 | 
197 | 	/*Update the return address stack*/
198 | 	if (branch_type == BRANCH_DIRECT_CALL || branch_type == BRANCH_INDIRECT_CALL) {
199 | 		if (RAS.size() < MAX_RAS_ENTRIES) {
200 | 			RAS.push(ip + 4);
201 | 		}
202 | 	} else if (branch_type == BRANCH_RETURN) {
203 | 		if (RAS.size()) {
204 | 			RAS.pop();
205 | 		}
206 | 	}
207 | 
208 | 	/*Check if the prefetch is on the correct execution path. If not, flush the FTQ.*/
209 | 	if (FTQ.size()) {
210 | 		if (!((ip) >= (FTQ.front().first_ip) && (ip) <= (FTQ.front().last_ip))) {
211 | 			FTQ.pop();
212 | 			if (!((ip) >= (FTQ.front().first_ip) && (ip) <= (FTQ.front().last_ip))) {
213 | 				while (!FTQ.empty()) {
214 | 					FTQ.pop();
215 | 				}
216 | 				prefetch_queue.clear();
217 | 			}
218 | 		} else if (FTQ.size() > 1) {
219 | 			std::queue<FTQEntry> tempQ = FTQ;
220 | 			tempQ.pop();
221 | 			uint64_t next_pc = branch_target;
222 | 			if (next_pc == 0) {
223 | 				next_pc = ip + 4;
224 | 			}
225 | 			if (!((next_pc) >= (tempQ.front().first_ip) && (next_pc) <= (tempQ.front().last_ip))) {
226 | 				while (!FTQ.empty()) {
227 | 					FTQ.pop();
228 | 				}
229 | 				prefetch_queue.clear();
230 | 			}
231 | 		}
232 | 	}
233 | 
234 | 	/*Reset the prefethcer if needed*/
235 | 	if (pfetch_ip == 0 || FTQ.size() == 0) {
236 | 		pfetch_ip = branch_target;
237 | 		if (branch_target == 0)
238 | 			pfetch_ip = ip + 4;
239 | 
240 | 		RAS_Pfetch = RAS;
241 | 	}
242 | 
243 | }
244 | 
245 | void O3_CPU::l1i_prefetcher_cache_operate(uint64_t v_addr, uint8_t cache_hit, uint8_t prefetch_hit)
246 | {
247 |   if((cache_hit == 0) && (L1I.MSHR.occupancy < (L1I.MSHR.SIZE>>1)))
248 |     {
249 |       uint64_t pf_addr = v_addr + (1<<LOG2_BLOCK_SIZE);
250 |       prefetch_code_line(pf_addr);
251 |     }
252 | }
253 | 
254 | void O3_CPU::l1i_prefetcher_cycle_operate()
255 | {
256 | 	if (pfetch_ip && FTQ.size() < MAX_FTQ_ENTRIES) {
257 | 
258 | 		uint64_t first_address = pfetch_ip;
259 | 		uint64_t last_address = 0;
260 | 
261 | 		/* As we don't know the instruction boundaries, lookup all the BTBs at byte granularity for a maximum of MAX_BTB_LOOKUPs addresses per cycle.
262 | 		 * Stop on a BTB hit.
263 | 		 * */
264 | 		for (int i = 0; i < MAX_BTB_LOOKUPs; i++) {
265 | 			BTBEntry *entry = BTB_10D.get_BTBentry(pfetch_ip);
266 | 			if (entry == NULL) {
267 | 				entry = BTB_15D.get_BTBentry(pfetch_ip);
268 | 			}
269 | 			if (entry == NULL) {
270 | 				entry = BTB_25D.get_BTBentry(pfetch_ip);
271 | 			}
272 | 			if (entry == NULL) {
273 | 				entry = BTB_64D.get_BTBentry(pfetch_ip);
274 | 			}
275 | 
276 | 			/*If Add the byte address to FTQ and update the "pfetch_ip" for next lookup.*/
277 | 			if (entry == NULL) {
278 | 
279 | 				if (FTQ.size() == 0 || FTQ.back().end_found) {
280 | 					FTQ.push(FTQEntry(false, pfetch_ip, pfetch_ip));
281 | 				} else {
282 | 					FTQ.back().last_ip = pfetch_ip;
283 | 				}
284 | 
285 | 				last_address = pfetch_ip;
286 | 				pfetch_ip++;
287 | 			} else {
288 | 				uint64_t branch_ip, target_ip = 0;
289 | 				branch_ip = pfetch_ip;
290 | 				target_ip = entry->target_ip;
291 | 
292 | 				if (FTQ.size() == 0 || FTQ.back().end_found) {
293 | 					FTQ.push(FTQEntry(true, pfetch_ip, branch_ip));
294 | 				} else {
295 | 					FTQ.back().end_found = true;
296 | 					FTQ.back().last_ip = branch_ip;
297 | 				}
298 | 
299 | 				/*Update "pfetch_ip" based on branch type and branch prediction*/
300 | 				uint8_t branch_taken = true;
301 | 				if (entry->branch_type == BRANCH_CONDITIONAL) {
302 | 					branch_taken = predict_branch(branch_ip);
303 | 					if (branch_taken) {
304 | 						pfetch_ip = target_ip;
305 | 					} else {
306 | 						pfetch_ip = branch_ip + 1;
307 | 					}
308 | 				} else if (entry->branch_type == BRANCH_RETURN) {
309 | 					if (RAS_Pfetch.size()) {
310 | 						pfetch_ip = RAS_Pfetch.top();
311 | 						RAS_Pfetch.pop();
312 | 					} else {
313 | 						pfetch_ip = target_ip;
314 | 					}
315 | 				} else if (entry->branch_type == BRANCH_DIRECT_CALL || entry->branch_type == BRANCH_INDIRECT_CALL) {
316 | 					pfetch_ip = target_ip;
317 | 					if (RAS_Pfetch.size() < MAX_RAS_ENTRIES) {
318 | 						RAS_Pfetch.push(branch_ip + 1);
319 | 					}
320 | 				} else {
321 | 					pfetch_ip = target_ip;
322 | 				}
323 | 
324 | 				if (pfetch_ip == 0) {
325 | 					pfetch_ip = branch_ip + 1;
326 | 				}
327 | 
328 | 				last_address = branch_ip;
329 | 
330 | 				break;
331 | 			}
332 | 		}
333 | 
334 | 		/*Find prefetch candidates*/
335 | 		  uint64_t firstBlock = first_address >> LOG2_BLOCK_SIZE;
336 | 		  uint64_t lastBlock = last_address >> LOG2_BLOCK_SIZE;
337 | 		  int numCacheBlocks = 1 + (lastBlock - firstBlock);
338 | 		  if (numCacheBlocks > 5) //Prefetch throttle.
339 | 		  	numCacheBlocks = 5;
340 | 
341 | 		  for (int i = 0; i < numCacheBlocks; i++) {
342 | 			  uint64_t pfetch_addr = (firstBlock + i) << LOG2_BLOCK_SIZE;
343 | 
344 | 			  bool is_recently_prefetched = false;
345 | 			  std::deque<uint64_t>::iterator it = std::find(prefetch_queue.begin(), prefetch_queue.end(), pfetch_addr);
346 | 			  if (it == prefetch_queue.end()) {
347 | 			  		it = std::find(recent_prefetches.begin(), recent_prefetches.end(), pfetch_addr);
348 | 			  		if (it != recent_prefetches.end()) {
349 | 						is_recently_prefetched = true;
350 | 			  		}
351 | 			  } else {
352 | 			  		is_recently_prefetched = true;
353 | 			  }
354 | 
355 | 			  if (is_recently_prefetched == false && prefetch_queue.size() < MAX_PFETCHQ_ENTRIES) {
356 | 					  prefetch_queue.push_back(pfetch_addr);
357 | 			  }
358 | 		  }
359 | 
360 | 		  /*Issue prefetches*/
361 | 
362 | 			if (prefetch_queue.size() && L1I.MSHR.occupancy < (L1I.MSHR.SIZE>>1) && L1I.PQ.occupancy < L1I.PQ.SIZE) {
363 | 				prefetch_code_line(prefetch_queue.front());
364 | 			  	recent_prefetches.push_back(prefetch_queue.front());
365 | 			  	if (recent_prefetches.size() > MAX_RECENT_PFETCH) {
366 | 			  		recent_prefetches.pop_front();
367 | 			  	}
368 | 
369 | 			  	prefetch_queue.pop_front();
370 | 			}
371 | 	}
372 | 
373 | }
374 | 
375 | void O3_CPU::l1i_prefetcher_cache_fill(uint64_t v_addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_v_addr)
376 | {
377 | 
378 | }
379 | 
380 | void O3_CPU::l1i_prefetcher_final_stats()
381 | {
382 | 	for(int i = 0; i < 66; i++) {
383 | 		cout << "XXX disp-" << i << " " << disp[i] << endl;
384 | 	}
385 | 
386 | }
387 | 


--------------------------------------------------------------------------------
/tracer/champsim_tracer.cpp:
--------------------------------------------------------------------------------
  1 | 
  2 | /*! @file
  3 |  *  This is an example of the PIN tool that demonstrates some basic PIN APIs 
  4 |  *  and could serve as the starting point for developing your first PIN tool
  5 |  */
  6 | 
  7 | #include "pin.H"
  8 | #include <iostream>
  9 | #include <fstream>
 10 | #include <stdlib.h>
 11 | #include <string.h>
 12 | #include <string>
 13 | 
 14 | #define NUM_INSTR_DESTINATIONS 2
 15 | #define NUM_INSTR_SOURCES 4
 16 | 
 17 | using namespace std;
 18 | 
 19 | typedef struct trace_instr_format {
 20 |     unsigned long long int ip;  // instruction pointer (program counter) value
 21 | 
 22 |     unsigned char is_branch;    // is this branch
 23 |     unsigned char branch_taken; // if so, is this taken
 24 | 
 25 |     unsigned char destination_registers[NUM_INSTR_DESTINATIONS]; // output registers
 26 |     unsigned char source_registers[NUM_INSTR_SOURCES];           // input registers
 27 | 
 28 |     unsigned long long int destination_memory[NUM_INSTR_DESTINATIONS]; // output memory
 29 |     unsigned long long int source_memory[NUM_INSTR_SOURCES];           // input memory
 30 | } trace_instr_format_t;
 31 | 
 32 | /* ================================================================== */
 33 | // Global variables 
 34 | /* ================================================================== */
 35 | 
 36 | UINT64 instrCount = 0;
 37 | 
 38 | FILE* out;
 39 | 
 40 | bool output_file_closed = false;
 41 | bool tracing_on = false;
 42 | 
 43 | trace_instr_format_t curr_instr;
 44 | 
 45 | /* ===================================================================== */
 46 | // Command line switches
 47 | /* ===================================================================== */
 48 | KNOB<string> KnobOutputFile(KNOB_MODE_WRITEONCE,  "pintool", "o", "champsim.trace", 
 49 |         "specify file name for Champsim tracer output");
 50 | 
 51 | KNOB<UINT64> KnobSkipInstructions(KNOB_MODE_WRITEONCE, "pintool", "s", "0", 
 52 |         "How many instructions to skip before tracing begins");
 53 | 
 54 | KNOB<UINT64> KnobTraceInstructions(KNOB_MODE_WRITEONCE, "pintool", "t", "1000000", 
 55 |         "How many instructions to trace");
 56 | 
 57 | /* ===================================================================== */
 58 | // Utilities
 59 | /* ===================================================================== */
 60 | 
 61 | /*!
 62 |  *  Print out help message.
 63 |  */
 64 | INT32 Usage()
 65 | {
 66 |     cerr << "This tool creates a register and memory access trace" << endl 
 67 |         << "Specify the output trace file with -o" << endl 
 68 |         << "Specify the number of instructions to skip before tracing with -s" << endl
 69 |         << "Specify the number of instructions to trace with -t" << endl << endl;
 70 | 
 71 |     cerr << KNOB_BASE::StringKnobSummary() << endl;
 72 | 
 73 |     return -1;
 74 | }
 75 | 
 76 | /* ===================================================================== */
 77 | // Analysis routines
 78 | /* ===================================================================== */
 79 | 
 80 | void BeginInstruction(VOID *ip, UINT32 op_code, VOID *opstring)
 81 | {
 82 |     instrCount++;
 83 |     //printf("[%p %u %s ", ip, opcode, (char*)opstring);
 84 | 
 85 |     if(instrCount > KnobSkipInstructions.Value()) 
 86 |     {
 87 |         tracing_on = true;
 88 | 
 89 |         if(instrCount > (KnobTraceInstructions.Value()+KnobSkipInstructions.Value()))
 90 |             tracing_on = false;
 91 |     }
 92 | 
 93 |     if(!tracing_on) 
 94 |         return;
 95 | 
 96 |     // reset the current instruction
 97 |     curr_instr.ip = (unsigned long long int)ip;
 98 | 
 99 |     curr_instr.is_branch = 0;
100 |     curr_instr.branch_taken = 0;
101 | 
102 |     for(int i=0; i<NUM_INSTR_DESTINATIONS; i++) 
103 |     {
104 |         curr_instr.destination_registers[i] = 0;
105 |         curr_instr.destination_memory[i] = 0;
106 |     }
107 | 
108 |     for(int i=0; i<NUM_INSTR_SOURCES; i++) 
109 |     {
110 |         curr_instr.source_registers[i] = 0;
111 |         curr_instr.source_memory[i] = 0;
112 |     }
113 | }
114 | 
115 | void EndInstruction()
116 | {
117 |     //printf("%d]\n", (int)instrCount);
118 | 
119 |     //printf("\n");
120 | 
121 |     if(instrCount > KnobSkipInstructions.Value())
122 |     {
123 |         tracing_on = true;
124 | 
125 |         if(instrCount <= (KnobTraceInstructions.Value()+KnobSkipInstructions.Value()))
126 |         {
127 |             // keep tracing
128 |             fwrite(&curr_instr, sizeof(trace_instr_format_t), 1, out);
129 |         }
130 |         else
131 |         {
132 |             tracing_on = false;
133 |             // close down the file, we're done tracing
134 |             if(!output_file_closed)
135 |             {
136 |                 fclose(out);
137 |                 output_file_closed = true;
138 |             }
139 | 
140 |             exit(0);
141 |         }
142 |     }
143 | }
144 | 
145 | void BranchOrNot(UINT32 taken)
146 | {
147 |     //printf("[%d] ", taken);
148 | 
149 |     curr_instr.is_branch = 1;
150 |     if(taken != 0)
151 |     {
152 |         curr_instr.branch_taken = 1;
153 |     }
154 | }
155 | 
156 | void RegRead(UINT32 i, UINT32 index)
157 | {
158 |     if(!tracing_on) return;
159 | 
160 |     REG r = (REG)i;
161 | 
162 |     /*
163 |        if(r == 26)
164 |        {
165 |     // 26 is the IP, which is read and written by branches
166 |     return;
167 |     }
168 |     */
169 | 
170 |     //cout << r << " " << REG_StringShort((REG)r) << " " ;
171 |     //cout << REG_StringShort((REG)r) << " " ;
172 | 
173 |     //printf("%d ", (int)r);
174 | 
175 |     // check to see if this register is already in the list
176 |     int already_found = 0;
177 |     for(int i=0; i<NUM_INSTR_SOURCES; i++)
178 |     {
179 |         if(curr_instr.source_registers[i] == ((unsigned char)r))
180 |         {
181 |             already_found = 1;
182 |             break;
183 |         }
184 |     }
185 |     if(already_found == 0)
186 |     {
187 |         for(int i=0; i<NUM_INSTR_SOURCES; i++)
188 |         {
189 |             if(curr_instr.source_registers[i] == 0)
190 |             {
191 |                 curr_instr.source_registers[i] = (unsigned char)r;
192 |                 break;
193 |             }
194 |         }
195 |     }
196 | }
197 | 
198 | void RegWrite(REG i, UINT32 index)
199 | {
200 |     if(!tracing_on) return;
201 | 
202 |     REG r = (REG)i;
203 | 
204 |     /*
205 |        if(r == 26)
206 |        {
207 |     // 26 is the IP, which is read and written by branches
208 |     return;
209 |     }
210 |     */
211 | 
212 |     //cout << "<" << r << " " << REG_StringShort((REG)r) << "> ";
213 |     //cout << "<" << REG_StringShort((REG)r) << "> ";
214 | 
215 |     //printf("<%d> ", (int)r);
216 | 
217 |     int already_found = 0;
218 |     for(int i=0; i<NUM_INSTR_DESTINATIONS; i++)
219 |     {
220 |         if(curr_instr.destination_registers[i] == ((unsigned char)r))
221 |         {
222 |             already_found = 1;
223 |             break;
224 |         }
225 |     }
226 |     if(already_found == 0)
227 |     {
228 |         for(int i=0; i<NUM_INSTR_DESTINATIONS; i++)
229 |         {
230 |             if(curr_instr.destination_registers[i] == 0)
231 |             {
232 |                 curr_instr.destination_registers[i] = (unsigned char)r;
233 |                 break;
234 |             }
235 |         }
236 |     }
237 |     /*
238 |        if(index==0)
239 |        {
240 |        curr_instr.destination_register = (unsigned long long int)r;
241 |        }
242 |        */
243 | }
244 | 
245 | void MemoryRead(VOID* addr, UINT32 index, UINT32 read_size)
246 | {
247 |     if(!tracing_on) return;
248 | 
249 |     //printf("0x%llx,%u ", (unsigned long long int)addr, read_size);
250 | 
251 |     // check to see if this memory read location is already in the list
252 |     int already_found = 0;
253 |     for(int i=0; i<NUM_INSTR_SOURCES; i++)
254 |     {
255 |         if(curr_instr.source_memory[i] == ((unsigned long long int)addr))
256 |         {
257 |             already_found = 1;
258 |             break;
259 |         }
260 |     }
261 |     if(already_found == 0)
262 |     {
263 |         for(int i=0; i<NUM_INSTR_SOURCES; i++)
264 |         {
265 |             if(curr_instr.source_memory[i] == 0)
266 |             {
267 |                 curr_instr.source_memory[i] = (unsigned long long int)addr;
268 |                 break;
269 |             }
270 |         }
271 |     }
272 | }
273 | 
274 | void MemoryWrite(VOID* addr, UINT32 index)
275 | {
276 |     if(!tracing_on) return;
277 | 
278 |     //printf("(0x%llx) ", (unsigned long long int) addr);
279 | 
280 |     // check to see if this memory write location is already in the list
281 |     int already_found = 0;
282 |     for(int i=0; i<NUM_INSTR_DESTINATIONS; i++)
283 |     {
284 |         if(curr_instr.destination_memory[i] == ((unsigned long long int)addr))
285 |         {
286 |             already_found = 1;
287 |             break;
288 |         }
289 |     }
290 |     if(already_found == 0)
291 |     {
292 |         for(int i=0; i<NUM_INSTR_DESTINATIONS; i++)
293 |         {
294 |             if(curr_instr.destination_memory[i] == 0)
295 |             {
296 |                 curr_instr.destination_memory[i] = (unsigned long long int)addr;
297 |                 break;
298 |             }
299 |         }
300 |     }
301 |     /*
302 |        if(index==0)
303 |        {
304 |        curr_instr.destination_memory = (long long int)addr;
305 |        }
306 |        */
307 | }
308 | 
309 | /* ===================================================================== */
310 | // Instrumentation callbacks
311 | /* ===================================================================== */
312 | 
313 | // Is called for every instruction and instruments reads and writes
314 | VOID Instruction(INS ins, VOID *v)
315 | {
316 |     // begin each instruction with this function
317 |     UINT32 opcode = INS_Opcode(ins);
318 |     INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)BeginInstruction, IARG_INST_PTR, IARG_UINT32, opcode, IARG_END);
319 | 
320 |     // instrument branch instructions
321 |     if(INS_IsBranch(ins))
322 |         INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)BranchOrNot, IARG_BRANCH_TAKEN, IARG_END);
323 | 
324 |     // instrument register reads
325 |     UINT32 readRegCount = INS_MaxNumRRegs(ins);
326 |     for(UINT32 i=0; i<readRegCount; i++) 
327 |     {
328 |         UINT32 regNum = INS_RegR(ins, i);
329 | 
330 |         INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)RegRead,
331 |                 IARG_UINT32, regNum, IARG_UINT32, i,
332 |                 IARG_END);
333 |     }
334 | 
335 |     // instrument register writes
336 |     UINT32 writeRegCount = INS_MaxNumWRegs(ins);
337 |     for(UINT32 i=0; i<writeRegCount; i++) 
338 |     {
339 |         UINT32 regNum = INS_RegW(ins, i);
340 | 
341 |         INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)RegWrite,
342 |                 IARG_UINT32, regNum, IARG_UINT32, i,
343 |                 IARG_END);
344 |     }
345 | 
346 |     // instrument memory reads and writes
347 |     UINT32 memOperands = INS_MemoryOperandCount(ins);
348 | 
349 |     // Iterate over each memory operand of the instruction.
350 |     for (UINT32 memOp = 0; memOp < memOperands; memOp++) 
351 |     {
352 |         if (INS_MemoryOperandIsRead(ins, memOp)) 
353 |         {
354 |             UINT32 read_size = INS_MemoryReadSize(ins);
355 | 
356 |             INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)MemoryRead,
357 |                     IARG_MEMORYOP_EA, memOp, IARG_UINT32, memOp, IARG_UINT32, read_size,
358 |                     IARG_END);
359 |         }
360 |         if (INS_MemoryOperandIsWritten(ins, memOp)) 
361 |         {
362 |             INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)MemoryWrite,
363 |                     IARG_MEMORYOP_EA, memOp, IARG_UINT32, memOp,
364 |                     IARG_END);
365 |         }
366 |     }
367 | 
368 |     // finalize each instruction with this function
369 |     INS_InsertCall(ins, IPOINT_BEFORE, (AFUNPTR)EndInstruction, IARG_END);
370 | }
371 | 
372 | /*!
373 |  * Print out analysis results.
374 |  * This function is called when the application exits.
375 |  * @param[in]   code            exit code of the application
376 |  * @param[in]   v               value specified by the tool in the 
377 |  *                              PIN_AddFiniFunction function call
378 |  */
379 | VOID Fini(INT32 code, VOID *v)
380 | {
381 |     // close the file if it hasn't already been closed
382 |     if(!output_file_closed) 
383 |     {
384 |         fclose(out);
385 |         output_file_closed = true;
386 |     }
387 | }
388 | 
389 | /*!
390 |  * The main procedure of the tool.
391 |  * This function is called when the application image is loaded but not yet started.
392 |  * @param[in]   argc            total number of elements in the argv array
393 |  * @param[in]   argv            array of command line arguments, 
394 |  *                              including pin -t <toolname> -- ...
395 |  */
396 | int main(int argc, char *argv[])
397 | {
398 |     // Initialize PIN library. Print help message if -h(elp) is specified
399 |     // in the command line or the command line is invalid 
400 |     if( PIN_Init(argc,argv) )
401 |         return Usage();
402 | 
403 |     const char* fileName = KnobOutputFile.Value().c_str();
404 | 
405 |     out = fopen(fileName, "ab");
406 |     if (!out) 
407 |     {
408 |         cout << "Couldn't open output trace file. Exiting." << endl;
409 |         exit(1);
410 |     }
411 | 
412 |     // Register function to be called to instrument instructions
413 |     INS_AddInstrumentFunction(Instruction, 0);
414 | 
415 |     // Register function to be called when the application exits
416 |     PIN_AddFiniFunction(Fini, 0);
417 | 
418 |     //cerr <<  "===============================================" << endl;
419 |     //cerr <<  "This application is instrumented by the Champsim Trace Generator" << endl;
420 |     //cerr <<  "Trace saved in " << KnobOutputFile.Value() << endl;
421 |     //cerr <<  "===============================================" << endl;
422 | 
423 |     // Start the program, never returns
424 |     PIN_StartProgram();
425 | 
426 |     return 0;
427 | }
428 | 
429 | /* ===================================================================== */
430 | /* eof */
431 | /* ===================================================================== */
432 | 


--------------------------------------------------------------------------------
/btb/btb.cc:
--------------------------------------------------------------------------------
  1 | 
  2 | /*
  3 |  * This file implements a basic Branch Target Buffer (BTB) structure.
  4 |  * It uses a set-associative BTB to predict the targets of non-return branches,
  5 |  * and it uses a small Return Address Stack (RAS) to predict the target of
  6 |  * returns.
  7 |  */
  8 | 
  9 | #include "ooo_cpu.h"
 10 | 
 11 | #define BASIC_BTB_SETS 4096
 12 | #define BASIC_BTB_WAYS 4
 13 | #define BASIC_BTB_INDIRECT_SIZE 4096
 14 | #define BASIC_BTB_RAS_SIZE 64
 15 | #define BASIC_BTB_CALL_INSTR_SIZE_TRACKERS 1024
 16 | 
 17 | struct BTBEntry {
 18 |   uint64_t tag;
 19 |   uint64_t target_ip;
 20 |   uint8_t branch_type;
 21 |   uint64_t lru;
 22 | };
 23 | 
 24 | struct BTB {
 25 |         std::vector <std::vector<BTBEntry>> theBTB;
 26 |         uint32_t numSets;
 27 |         uint32_t assoc;
 28 |         uint64_t indexMask;
 29 |         uint32_t numIndexBits;
 30 | 
 31 |     BTB () {}
 32 | 
 33 |     BTB( int32_t Sets, int32_t Assoc )
 34 |       : numSets(Sets)
 35 |         , assoc(Assoc) {
 36 |           //aBTBSize must be a power of 2
 37 |           assert( ((Sets - 1) & (Sets)) == 0);
 38 |           theBTB.resize(Sets);
 39 |           indexMask = Sets - 1;
 40 |           numIndexBits = (uint32_t) log2((double)Sets);
 41 |         }
 42 | 
 43 |     void init_btb (int32_t Sets, int32_t Assoc) {
 44 |     	numSets = Sets;
 45 |     	assoc = Assoc;
 46 |         //aBTBSize must be a power of 2
 47 |         assert( ((Sets - 1) & (Sets)) == 0);
 48 |         theBTB.resize(Sets);
 49 |         indexMask = Sets - 1;
 50 |         numIndexBits = (uint32_t) log2((double)Sets);
 51 |     }
 52 | 
 53 |     int32_t index(uint64_t ip) {
 54 | 		return ((ip >> 2) & indexMask);
 55 |     }
 56 | 
 57 |     uint64_t get_tag(uint64_t ip) {
 58 |     	//return ip;
 59 |         uint64_t addr = ip;
 60 | 		addr = addr >> 2;
 61 |         addr = addr >> numIndexBits;
 62 |         /* We use a 16-bit tag.
 63 |          * The lower 8-bits stay the same as in the full tag.
 64 |          * The upper 8-bits are the folded X-OR of the remaining bits of the full tag.
 65 |          */
 66 |         uint64_t tag = addr & 0xFF; //Set the lower 8-bits of the tag
 67 |         addr = addr >> 8;
 68 |         int tagMSBs = 0;
 69 |         /*Get the upper 8-bits (folded X-OR)*/
 70 |         for (int i = 0; i < 8; i++) {
 71 |                 tagMSBs = tagMSBs ^ (addr & 0xFF);
 72 |                 addr = addr >> 8;
 73 |         }
 74 |         /*Concatenate the lower and upper 8-bits of tag*/
 75 |         tag = tag | (tagMSBs << 8);
 76 |         return tag;
 77 |     }
 78 | 
 79 |     BTBEntry *get_BTBentry(uint64_t ip){
 80 |         BTBEntry *entry = NULL;
 81 | 
 82 |         int idx = index(ip);
 83 |         uint64_t tag = get_tag(ip);
 84 |         for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 85 |                 if (theBTB[idx][i].tag == tag) {
 86 |                         return &(theBTB[idx][i]);
 87 |                 }
 88 |         }
 89 | 
 90 |         return entry;
 91 |     }
 92 | 
 93 |     void update_BTB(uint64_t ip, uint8_t b_type, uint64_t target, uint8_t taken, uint64_t lru_counter){
 94 |         int idx = index(ip);
 95 |         uint64_t tag = get_tag(ip);
 96 |         int way = -1;
 97 |         for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 98 |                 if (theBTB[idx][i].tag == tag) {
 99 |                         way = i;
100 |                         break;
101 |                 }
102 |         }
103 | 
104 |         if (way == -1) {
105 |         	if ((target != 0) && taken) {
106 |                 BTBEntry entry;
107 |                 entry.tag = tag;
108 |                 entry.branch_type = b_type;
109 |                 entry.target_ip = target;
110 |                 entry.lru = lru_counter;
111 | 
112 |                 if (theBTB[idx].size() >= assoc) {
113 |                         theBTB[idx].erase(theBTB[idx].begin());
114 |                 }
115 |                 theBTB[idx].push_back(entry);
116 |         	}
117 |         } else {
118 | 			BTBEntry entry = theBTB[idx][way];
119 | 			entry.branch_type = b_type;
120 | 			if (target != 0) {
121 | 					entry.target_ip = target;
122 | 			}
123 | 			entry.lru = lru_counter;
124 | 
125 | 			//Update LRU
126 | 			theBTB[idx].erase(theBTB[idx].begin() + way);
127 | 			theBTB[idx].push_back(entry);
128 |         }
129 |     }
130 | 
131 |     uint64_t get_lru_value(uint64_t ip) {
132 |         int idx = index(ip);
133 |         uint64_t lru_value;
134 |         if (theBTB[idx].size() < assoc) { //All ways are not yet allocated
135 |         	lru_value = 0;
136 |         } else {
137 |         	lru_value = theBTB[idx][0].lru;
138 |             for (uint32_t i = 1; i < theBTB[idx].size(); i++) { //We should never enter here because head should be LRU
139 |                     if (theBTB[idx][i].lru < lru_value) {
140 |                             assert(0);
141 |                     }
142 |             }
143 |         }
144 | 
145 |         return lru_value;
146 |     }
147 | 
148 | };
149 | 
150 | /*BTB BTB_4D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 10-bit) 28*1024*8 = 28KB
151 | BTB BTB_6D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 15-bit) 33*1024*7 = 28.875KB
152 | BTB BTB_8D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 25-bit) 43*1024*8 = 43KB
153 | BTB BTB_12D(512, 8);                                    //Storage: (tag:16-bit, branch-type: 2-bit,   full-target: 64-bit) 82*256*4  = 10.25KB
154 | BTB BTB_18D(512, 8);
155 | BTB BTB_25D(256, 8);
156 | BTB BTB_46D(128, 8);
157 | BTB BTB_Ret(1024, 8);*/
158 | 
159 | #define NUM_BTB_PARTITIONS 2
160 | BTB btb_partition[NUM_BTB_PARTITIONS];
161 | 
162 | uint64_t basic_btb_lru_counter[NUM_CPUS];
163 | 
164 | uint64_t basic_btb_indirect[NUM_CPUS][BASIC_BTB_INDIRECT_SIZE];
165 | uint64_t basic_btb_conditional_history[NUM_CPUS];
166 | 
167 | uint64_t basic_btb_ras[NUM_CPUS][BASIC_BTB_RAS_SIZE];
168 | int basic_btb_ras_index[NUM_CPUS];
169 | /*
170 |  * The following two variables are used to automatically identify the
171 |  * size of call instructions, in bytes, which tells us the appropriate
172 |  * target for a call's corresponding return.
173 |  * They exist because ChampSim does not model a specific ISA, and
174 |  * different ISAs could use different sizes for call instructions,
175 |  * and even within the same ISA, calls can have different sizes.
176 |  */
177 | uint64_t basic_btb_call_instr_sizes[NUM_CPUS][BASIC_BTB_CALL_INSTR_SIZE_TRACKERS];
178 | 
179 | uint64_t basic_btb_abs_addr_dist(uint64_t addr1, uint64_t addr2) {
180 |   if(addr1 > addr2) {
181 |     return addr1 - addr2;
182 |   }
183 | 
184 |   return addr2 - addr1;
185 | }
186 | 
187 | void push_basic_btb_ras(uint8_t cpu, uint64_t ip) {
188 |   basic_btb_ras_index[cpu]++;
189 |   if (basic_btb_ras_index[cpu] == BASIC_BTB_RAS_SIZE) {
190 |     basic_btb_ras_index[cpu] = 0;
191 |   }
192 | 
193 |   basic_btb_ras[cpu][basic_btb_ras_index[cpu]] = ip;
194 | }
195 | 
196 | uint64_t peek_basic_btb_ras(uint8_t cpu) {
197 |   return basic_btb_ras[cpu][basic_btb_ras_index[cpu]];
198 | }
199 | 
200 | uint64_t pop_basic_btb_ras(uint8_t cpu) {
201 |   uint64_t target = basic_btb_ras[cpu][basic_btb_ras_index[cpu]];
202 |   basic_btb_ras[cpu][basic_btb_ras_index[cpu]] = 0;
203 | 
204 |   basic_btb_ras_index[cpu]--;
205 |   if (basic_btb_ras_index[cpu] == -1) {
206 |     basic_btb_ras_index[cpu] += BASIC_BTB_RAS_SIZE;
207 |   }
208 | 
209 |   return target;
210 | }
211 | 
212 | uint64_t basic_btb_call_size_tracker_hash(uint64_t ip) {
213 |   return (ip & (BASIC_BTB_CALL_INSTR_SIZE_TRACKERS-1));
214 | }
215 | 
216 | uint64_t basic_btb_get_call_size(uint8_t cpu, uint64_t ip) {
217 |   uint64_t size = basic_btb_call_instr_sizes[cpu][basic_btb_call_size_tracker_hash(ip)];
218 | 
219 |   return size;
220 | }
221 | 
222 | int convert_offsetBits_to_partitionID(int num_bits) {
223 | 	return 0;
224 | 	  if (num_bits == 0) {
225 | 		  return 0;
226 | 	  } else if (num_bits <= 4) {
227 | 		  return 1;
228 | 	  } else if (num_bits <= 5) {
229 | 		  return 2;
230 | 	  } else if (num_bits <= 7) {
231 | 		  return 3;
232 | 	  } else if (num_bits <= 9) {
233 | 		  return 4;
234 | 	  } else if (num_bits <= 11) {
235 | 		  return 5;
236 | 	  } else if (num_bits <= 19) {
237 | 		  return 6;
238 | 	  } else if (num_bits <= 25) {
239 | 		  return 7;
240 | 	  } else {
241 | 		  return 8;
242 | 	  }
243 | 	  assert(0);
244 | }
245 | 
246 | int get_lru_partition(int start_partitionID, uint64_t ip) {
247 | 	  int lru_partition = start_partitionID;
248 | 	  uint64_t lru_value = btb_partition[start_partitionID].get_lru_value(ip);
249 | 	  for (int i = start_partitionID + 1; i < NUM_BTB_PARTITIONS; i++) {
250 | 		uint64_t partition_lru_value = btb_partition[i].get_lru_value(ip);
251 | 	    if (partition_lru_value < lru_value) {
252 | 	      lru_partition = i;
253 | 	      lru_value = partition_lru_value;
254 | 	    }
255 | 	  }
256 | 	  return lru_partition;
257 | }
258 | 
259 | void O3_CPU::initialize_btb() {
260 |   std::cout << "Basic BTB sets: " << BASIC_BTB_SETS
261 |             << " ways: " << BASIC_BTB_WAYS
262 |             << " indirect buffer size: " << BASIC_BTB_INDIRECT_SIZE
263 |             << " RAS size: " << BASIC_BTB_RAS_SIZE << std::endl;
264 | 
265 |   for (uint32_t i = 0; i < BASIC_BTB_RAS_SIZE; i++) {
266 |     basic_btb_ras[cpu][i] = 0;
267 |   }
268 |   basic_btb_ras_index[cpu] = 0;
269 |   for (uint32_t i=0; i<BASIC_BTB_CALL_INSTR_SIZE_TRACKERS; i++) {
270 |     basic_btb_call_instr_sizes[cpu][i] = 4;
271 |   }
272 | 
273 |   basic_btb_lru_counter[cpu] = 0;
274 | 
275 |   btb_partition[0].init_btb(256, 7);
276 |   btb_partition[1].init_btb(64, 1);
277 |   //btb_partition[2].init_btb(256, 1);
278 |   //btb_partition[3].init_btb(256, 1);
279 |   //btb_partition[4].init_btb(256, 1);
280 |   //btb_partition[5].init_btb(256, 1);
281 |   //btb_partition[6].init_btb(256, 1);
282 |   //btb_partition[7].init_btb(256, 1);
283 |   //btb_partition[8].init_btb(64, 1);
284 | }
285 | 
286 | BTB_outcome O3_CPU::btb_prediction(uint64_t ip, uint8_t branch_type) {
287 | 	BTBEntry *btb_entry;
288 | 
289 |   for (int i = 0; i < NUM_BTB_PARTITIONS; i++) {
290 | 	  btb_entry = btb_partition[i].get_BTBentry(ip);
291 | 	  if (btb_entry) {
292 | 		  break;
293 | 	  }
294 |   }
295 | 
296 |   if (btb_entry == NULL) {
297 |     // no prediction for this IP
298 |       if (branch_type == BRANCH_DIRECT_CALL || branch_type == BRANCH_INDIRECT_CALL) {
299 | 	  push_basic_btb_ras(cpu, ip);
300 |       }
301 |       BTB_outcome outcome = {0, BRANCH_CONDITIONAL, 2/*To indicate that it was a BTB miss*/};
302 |       	  return outcome;
303 |       //return std::make_pair(0, 0);
304 |   }
305 | 
306 |   branch_type = NOT_BRANCH;
307 |   branch_type = btb_entry->branch_type;
308 | 
309 |   //uint8_t always_taken = false;
310 |   //if (branch_type != BRANCH_CONDITIONAL) {
311 |     //always_taken = true;
312 |   //}
313 | 
314 |   if ((branch_type == BRANCH_DIRECT_CALL) ||
315 |       (branch_type == BRANCH_INDIRECT_CALL)) {
316 |     // add something to the RAS
317 |     push_basic_btb_ras(cpu, ip);
318 |   }
319 | 
320 |   if (branch_type == BRANCH_RETURN) {
321 |     // peek at the top of the RAS
322 |     uint64_t target = peek_basic_btb_ras(cpu);
323 |     // and adjust for the size of the call instr
324 |     target += basic_btb_get_call_size(cpu, target);
325 | 
326 |     BTB_outcome outcome = {target, BRANCH_RETURN, 0};
327 |     return outcome;
328 |     //return std::make_pair(target, always_taken);
329 |   } /*else if ((branch_type == BRANCH_INDIRECT) ||
330 |              (branch_type == BRANCH_INDIRECT_CALL)) {
331 |     return std::make_pair(basic_btb_indirect[cpu][basic_btb_indirect_hash(cpu, ip)], always_taken);
332 |   } */else {
333 |     // use BTB for all other branches + direct calls
334 | 
335 |     BTB_outcome outcome = {btb_entry->target_ip, branch_type, 0};
336 |     return outcome;
337 |     //return std::make_pair(btb_entry->target_ip, always_taken);
338 |   }
339 | 
340 |   assert(0);
341 |   //return std::make_pair(0, always_taken);
342 | }
343 | 
344 | void O3_CPU::update_btb(uint64_t ip, uint64_t branch_target, uint8_t taken,
345 |                         uint8_t branch_type) {
346 |   // updates for indirect branches
347 |   /*if ((branch_type == BRANCH_INDIRECT) ||
348 |       (branch_type == BRANCH_INDIRECT_CALL)) {
349 |     basic_btb_indirect[cpu][basic_btb_indirect_hash(cpu, ip)] = branch_target;
350 |   }
351 |   if (branch_type == BRANCH_CONDITIONAL) {
352 |     basic_btb_conditional_history[cpu] <<= 1;
353 |     if (taken) {
354 |       basic_btb_conditional_history[cpu] |= 1;
355 |     }
356 |   }*/
357 | 
358 |   if (branch_type == BRANCH_RETURN) {
359 |     // recalibrate call-return offset
360 |     // if our return prediction got us into the right ball park, but not the
361 |     // exactly correct byte target, then adjust our call instr size tracker
362 |     uint64_t call_ip = pop_basic_btb_ras(cpu);
363 |     uint64_t estimated_call_instr_size = basic_btb_abs_addr_dist(call_ip, branch_target);
364 |     if (estimated_call_instr_size <= 10) {
365 |       basic_btb_call_instr_sizes[cpu][basic_btb_call_size_tracker_hash(call_ip)] = estimated_call_instr_size;
366 |     }
367 |   } 
368 | 
369 |   BTBEntry *btb_entry;
370 |   int partitionID = -1;
371 |   for (int i = 0; i < NUM_BTB_PARTITIONS; i++) {
372 | 	  btb_entry = btb_partition[i].get_BTBentry(ip);
373 | 	  if (btb_entry) {
374 | 		  partitionID = i;
375 | 		  break;
376 | 	  }
377 |   }
378 | 
379 |   if (btb_entry == NULL) {
380 | 
381 | 	  BTB_writes++;
382 | 
383 | 	  int num_bits;
384 | 	  if (branch_type == BRANCH_RETURN) {
385 | 		  num_bits = 0;
386 | 	  } else {
387 | 		  uint64_t diff_bits = (branch_target >> 2) ^ (ip >> 2);
388 | 		  num_bits = 0;
389 | 		  while (diff_bits != 0) {
390 | 			  diff_bits = diff_bits >> 1;
391 | 			  num_bits++;
392 | 		  }
393 | 	  }
394 | 	  assert(num_bits >= 0 && num_bits < 66);
395 | 
396 | 	  int smallest_offset_partition_id = convert_offsetBits_to_partitionID(num_bits);
397 | 
398 | 	  int partition = get_lru_partition(smallest_offset_partition_id, ip);
399 | 	  assert(partition < NUM_BTB_PARTITIONS);
400 | 
401 | 	  btb_partition[partition].update_BTB(ip, branch_type, branch_target, taken, basic_btb_lru_counter[cpu]);
402 | 	  basic_btb_lru_counter[cpu]++;
403 | 
404 | 
405 |   } else {
406 | 	    // update an existing entry
407 | 	  assert(partitionID != -1);
408 | 	  btb_partition[partitionID].update_BTB(ip, branch_type, branch_target, taken, basic_btb_lru_counter[cpu]);
409 | 	  basic_btb_lru_counter[cpu]++;
410 |   }
411 |   
412 | }
413 | 


--------------------------------------------------------------------------------
/btb/convBTB.btb:
--------------------------------------------------------------------------------
  1 | 
  2 | /*
  3 |  * This file implements a basic Branch Target Buffer (BTB) structure.
  4 |  * It uses a set-associative BTB to predict the targets of non-return branches,
  5 |  * and it uses a small Return Address Stack (RAS) to predict the target of
  6 |  * returns.
  7 |  */
  8 | 
  9 | #include "ooo_cpu.h"
 10 | 
 11 | #define BASIC_BTB_SETS 4096
 12 | #define BASIC_BTB_WAYS 4
 13 | #define BASIC_BTB_INDIRECT_SIZE 4096
 14 | #define BASIC_BTB_RAS_SIZE 64
 15 | #define BASIC_BTB_CALL_INSTR_SIZE_TRACKERS 1024
 16 | 
 17 | struct BTBEntry {
 18 |   uint64_t tag;
 19 |   uint64_t target_ip;
 20 |   uint8_t branch_type;
 21 |   uint64_t lru;
 22 | };
 23 | 
 24 | struct BTB {
 25 |         std::vector <std::vector<BTBEntry>> theBTB;
 26 |         uint32_t numSets;
 27 |         uint32_t assoc;
 28 |         uint64_t indexMask;
 29 |         uint32_t numIndexBits;
 30 | 
 31 |     BTB () {}
 32 | 
 33 |     BTB( int32_t Sets, int32_t Assoc )
 34 |       : numSets(Sets)
 35 |         , assoc(Assoc) {
 36 |           //aBTBSize must be a power of 2
 37 |           assert( ((Sets - 1) & (Sets)) == 0);
 38 |           theBTB.resize(Sets);
 39 |           indexMask = Sets - 1;
 40 |           numIndexBits = (uint32_t) log2((double)Sets);
 41 |         }
 42 | 
 43 |     void init_btb (int32_t Sets, int32_t Assoc) {
 44 |     	numSets = Sets;
 45 |     	assoc = Assoc;
 46 |         //aBTBSize must be a power of 2
 47 |         assert( ((Sets - 1) & (Sets)) == 0);
 48 |         theBTB.resize(Sets);
 49 |         indexMask = Sets - 1;
 50 |         numIndexBits = (uint32_t) log2((double)Sets);
 51 |     }
 52 | 
 53 |     int32_t index(uint64_t ip) {
 54 | 		return ((ip >> 2) & indexMask);
 55 |     }
 56 | 
 57 |     uint64_t get_tag(uint64_t ip) {
 58 |     	//return ip;
 59 |         uint64_t addr = ip;
 60 | 		addr = addr >> 2;
 61 |         addr = addr >> numIndexBits;
 62 |         /* We use a 16-bit tag.
 63 |          * The lower 8-bits stay the same as in the full tag.
 64 |          * The upper 8-bits are the folded X-OR of the remaining bits of the full tag.
 65 |          */
 66 |         uint64_t tag = addr & 0xFF; //Set the lower 8-bits of the tag
 67 |         addr = addr >> 8;
 68 |         int tagMSBs = 0;
 69 |         /*Get the upper 8-bits (folded X-OR)*/
 70 |         for (int i = 0; i < 8; i++) {
 71 |                 tagMSBs = tagMSBs ^ (addr & 0xFF);
 72 |                 addr = addr >> 8;
 73 |         }
 74 |         /*Concatenate the lower and upper 8-bits of tag*/
 75 |         tag = tag | (tagMSBs << 8);
 76 |         return tag;
 77 |     }
 78 | 
 79 |     BTBEntry *get_BTBentry(uint64_t ip){
 80 |         BTBEntry *entry = NULL;
 81 | 
 82 |         int idx = index(ip);
 83 |         uint64_t tag = get_tag(ip);
 84 |         for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 85 |                 if (theBTB[idx][i].tag == tag) {
 86 |                         return &(theBTB[idx][i]);
 87 |                 }
 88 |         }
 89 | 
 90 |         return entry;
 91 |     }
 92 | 
 93 |     void update_BTB(uint64_t ip, uint8_t b_type, uint64_t target, uint8_t taken, uint64_t lru_counter){
 94 |         int idx = index(ip);
 95 |         uint64_t tag = get_tag(ip);
 96 |         int way = -1;
 97 |         for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 98 |                 if (theBTB[idx][i].tag == tag) {
 99 |                         way = i;
100 |                         break;
101 |                 }
102 |         }
103 | 
104 |         if (way == -1) {
105 |         	if ((target != 0) && taken) {
106 |                 BTBEntry entry;
107 |                 entry.tag = tag;
108 |                 entry.branch_type = b_type;
109 |                 entry.target_ip = target;
110 |                 entry.lru = lru_counter;
111 | 
112 |                 if (theBTB[idx].size() >= assoc) {
113 |                         theBTB[idx].erase(theBTB[idx].begin());
114 |                 }
115 |                 theBTB[idx].push_back(entry);
116 |         	}
117 |         } else {
118 | 			BTBEntry entry = theBTB[idx][way];
119 | 			entry.branch_type = b_type;
120 | 			if (target != 0) {
121 | 					entry.target_ip = target;
122 | 			}
123 | 			entry.lru = lru_counter;
124 | 
125 | 			//Update LRU
126 | 			theBTB[idx].erase(theBTB[idx].begin() + way);
127 | 			theBTB[idx].push_back(entry);
128 |         }
129 |     }
130 | 
131 |     uint64_t get_lru_value(uint64_t ip) {
132 |         int idx = index(ip);
133 |         uint64_t lru_value;
134 |         if (theBTB[idx].size() < assoc) { //All ways are not yet allocated
135 |         	lru_value = 0;
136 |         } else {
137 |         	lru_value = theBTB[idx][0].lru;
138 |             for (uint32_t i = 1; i < theBTB[idx].size(); i++) { //We should never enter here because head should be LRU
139 |                     if (theBTB[idx][i].lru < lru_value) {
140 |                             assert(0);
141 |                     }
142 |             }
143 |         }
144 | 
145 |         return lru_value;
146 |     }
147 | 
148 | };
149 | 
150 | /*BTB BTB_4D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 10-bit) 28*1024*8 = 28KB
151 | BTB BTB_6D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 15-bit) 33*1024*7 = 28.875KB
152 | BTB BTB_8D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 25-bit) 43*1024*8 = 43KB
153 | BTB BTB_12D(512, 8);                                    //Storage: (tag:16-bit, branch-type: 2-bit,   full-target: 64-bit) 82*256*4  = 10.25KB
154 | BTB BTB_18D(512, 8);
155 | BTB BTB_25D(256, 8);
156 | BTB BTB_46D(128, 8);
157 | BTB BTB_Ret(1024, 8);*/
158 | 
159 | #define NUM_BTB_PARTITIONS 2
160 | BTB btb_partition[NUM_BTB_PARTITIONS];
161 | 
162 | uint64_t basic_btb_lru_counter[NUM_CPUS];
163 | 
164 | uint64_t basic_btb_indirect[NUM_CPUS][BASIC_BTB_INDIRECT_SIZE];
165 | uint64_t basic_btb_conditional_history[NUM_CPUS];
166 | 
167 | uint64_t basic_btb_ras[NUM_CPUS][BASIC_BTB_RAS_SIZE];
168 | int basic_btb_ras_index[NUM_CPUS];
169 | /*
170 |  * The following two variables are used to automatically identify the
171 |  * size of call instructions, in bytes, which tells us the appropriate
172 |  * target for a call's corresponding return.
173 |  * They exist because ChampSim does not model a specific ISA, and
174 |  * different ISAs could use different sizes for call instructions,
175 |  * and even within the same ISA, calls can have different sizes.
176 |  */
177 | uint64_t basic_btb_call_instr_sizes[NUM_CPUS][BASIC_BTB_CALL_INSTR_SIZE_TRACKERS];
178 | 
179 | uint64_t basic_btb_abs_addr_dist(uint64_t addr1, uint64_t addr2) {
180 |   if(addr1 > addr2) {
181 |     return addr1 - addr2;
182 |   }
183 | 
184 |   return addr2 - addr1;
185 | }
186 | 
187 | void push_basic_btb_ras(uint8_t cpu, uint64_t ip) {
188 |   basic_btb_ras_index[cpu]++;
189 |   if (basic_btb_ras_index[cpu] == BASIC_BTB_RAS_SIZE) {
190 |     basic_btb_ras_index[cpu] = 0;
191 |   }
192 | 
193 |   basic_btb_ras[cpu][basic_btb_ras_index[cpu]] = ip;
194 | }
195 | 
196 | uint64_t peek_basic_btb_ras(uint8_t cpu) {
197 |   return basic_btb_ras[cpu][basic_btb_ras_index[cpu]];
198 | }
199 | 
200 | uint64_t pop_basic_btb_ras(uint8_t cpu) {
201 |   uint64_t target = basic_btb_ras[cpu][basic_btb_ras_index[cpu]];
202 |   basic_btb_ras[cpu][basic_btb_ras_index[cpu]] = 0;
203 | 
204 |   basic_btb_ras_index[cpu]--;
205 |   if (basic_btb_ras_index[cpu] == -1) {
206 |     basic_btb_ras_index[cpu] += BASIC_BTB_RAS_SIZE;
207 |   }
208 | 
209 |   return target;
210 | }
211 | 
212 | uint64_t basic_btb_call_size_tracker_hash(uint64_t ip) {
213 |   return (ip & (BASIC_BTB_CALL_INSTR_SIZE_TRACKERS-1));
214 | }
215 | 
216 | uint64_t basic_btb_get_call_size(uint8_t cpu, uint64_t ip) {
217 |   uint64_t size = basic_btb_call_instr_sizes[cpu][basic_btb_call_size_tracker_hash(ip)];
218 | 
219 |   return size;
220 | }
221 | 
222 | int convert_offsetBits_to_partitionID(int num_bits) {
223 | 	return 0;
224 | 	  if (num_bits == 0) {
225 | 		  return 0;
226 | 	  } else if (num_bits <= 4) {
227 | 		  return 1;
228 | 	  } else if (num_bits <= 5) {
229 | 		  return 2;
230 | 	  } else if (num_bits <= 7) {
231 | 		  return 3;
232 | 	  } else if (num_bits <= 9) {
233 | 		  return 4;
234 | 	  } else if (num_bits <= 11) {
235 | 		  return 5;
236 | 	  } else if (num_bits <= 19) {
237 | 		  return 6;
238 | 	  } else if (num_bits <= 25) {
239 | 		  return 7;
240 | 	  } else {
241 | 		  return 8;
242 | 	  }
243 | 	  assert(0);
244 | }
245 | 
246 | int get_lru_partition(int start_partitionID, uint64_t ip) {
247 | 	  int lru_partition = start_partitionID;
248 | 	  uint64_t lru_value = btb_partition[start_partitionID].get_lru_value(ip);
249 | 	  for (int i = start_partitionID + 1; i < NUM_BTB_PARTITIONS; i++) {
250 | 		uint64_t partition_lru_value = btb_partition[i].get_lru_value(ip);
251 | 	    if (partition_lru_value < lru_value) {
252 | 	      lru_partition = i;
253 | 	      lru_value = partition_lru_value;
254 | 	    }
255 | 	  }
256 | 	  return lru_partition;
257 | }
258 | 
259 | void O3_CPU::initialize_btb() {
260 |   std::cout << "Basic BTB sets: " << BASIC_BTB_SETS
261 |             << " ways: " << BASIC_BTB_WAYS
262 |             << " indirect buffer size: " << BASIC_BTB_INDIRECT_SIZE
263 |             << " RAS size: " << BASIC_BTB_RAS_SIZE << std::endl;
264 | 
265 |   for (uint32_t i = 0; i < BASIC_BTB_RAS_SIZE; i++) {
266 |     basic_btb_ras[cpu][i] = 0;
267 |   }
268 |   basic_btb_ras_index[cpu] = 0;
269 |   for (uint32_t i=0; i<BASIC_BTB_CALL_INSTR_SIZE_TRACKERS; i++) {
270 |     basic_btb_call_instr_sizes[cpu][i] = 4;
271 |   }
272 | 
273 |   basic_btb_lru_counter[cpu] = 0;
274 | 
275 |   btb_partition[0].init_btb(256, 7);
276 |   btb_partition[1].init_btb(64, 1);
277 |   //btb_partition[2].init_btb(256, 1);
278 |   //btb_partition[3].init_btb(256, 1);
279 |   //btb_partition[4].init_btb(256, 1);
280 |   //btb_partition[5].init_btb(256, 1);
281 |   //btb_partition[6].init_btb(256, 1);
282 |   //btb_partition[7].init_btb(256, 1);
283 |   //btb_partition[8].init_btb(64, 1);
284 | }
285 | 
286 | BTB_outcome O3_CPU::btb_prediction(uint64_t ip, uint8_t branch_type) {
287 | 	BTBEntry *btb_entry;
288 | 
289 |   for (int i = 0; i < NUM_BTB_PARTITIONS; i++) {
290 | 	  btb_entry = btb_partition[i].get_BTBentry(ip);
291 | 	  if (btb_entry) {
292 | 		  break;
293 | 	  }
294 |   }
295 | 
296 |   if (btb_entry == NULL) {
297 |     // no prediction for this IP
298 |       if (branch_type == BRANCH_DIRECT_CALL || branch_type == BRANCH_INDIRECT_CALL) {
299 | 	  push_basic_btb_ras(cpu, ip);
300 |       }
301 |       BTB_outcome outcome = {0, BRANCH_CONDITIONAL, 2/*To indicate that it was a BTB miss*/};
302 |       	  return outcome;
303 |       //return std::make_pair(0, 0);
304 |   }
305 | 
306 |   branch_type = NOT_BRANCH;
307 |   branch_type = btb_entry->branch_type;
308 | 
309 |   //uint8_t always_taken = false;
310 |   //if (branch_type != BRANCH_CONDITIONAL) {
311 |     //always_taken = true;
312 |   //}
313 | 
314 |   if ((branch_type == BRANCH_DIRECT_CALL) ||
315 |       (branch_type == BRANCH_INDIRECT_CALL)) {
316 |     // add something to the RAS
317 |     push_basic_btb_ras(cpu, ip);
318 |   }
319 | 
320 |   if (branch_type == BRANCH_RETURN) {
321 |     // peek at the top of the RAS
322 |     uint64_t target = peek_basic_btb_ras(cpu);
323 |     // and adjust for the size of the call instr
324 |     target += basic_btb_get_call_size(cpu, target);
325 | 
326 |     BTB_outcome outcome = {target, BRANCH_RETURN, 0};
327 |     return outcome;
328 |     //return std::make_pair(target, always_taken);
329 |   } /*else if ((branch_type == BRANCH_INDIRECT) ||
330 |              (branch_type == BRANCH_INDIRECT_CALL)) {
331 |     return std::make_pair(basic_btb_indirect[cpu][basic_btb_indirect_hash(cpu, ip)], always_taken);
332 |   } */else {
333 |     // use BTB for all other branches + direct calls
334 | 
335 |     BTB_outcome outcome = {btb_entry->target_ip, branch_type, 0};
336 |     return outcome;
337 |     //return std::make_pair(btb_entry->target_ip, always_taken);
338 |   }
339 | 
340 |   assert(0);
341 |   //return std::make_pair(0, always_taken);
342 | }
343 | 
344 | void O3_CPU::update_btb(uint64_t ip, uint64_t branch_target, uint8_t taken,
345 |                         uint8_t branch_type) {
346 |   // updates for indirect branches
347 |   /*if ((branch_type == BRANCH_INDIRECT) ||
348 |       (branch_type == BRANCH_INDIRECT_CALL)) {
349 |     basic_btb_indirect[cpu][basic_btb_indirect_hash(cpu, ip)] = branch_target;
350 |   }
351 |   if (branch_type == BRANCH_CONDITIONAL) {
352 |     basic_btb_conditional_history[cpu] <<= 1;
353 |     if (taken) {
354 |       basic_btb_conditional_history[cpu] |= 1;
355 |     }
356 |   }*/
357 | 
358 |   if (branch_type == BRANCH_RETURN) {
359 |     // recalibrate call-return offset
360 |     // if our return prediction got us into the right ball park, but not the
361 |     // exactly correct byte target, then adjust our call instr size tracker
362 |     uint64_t call_ip = pop_basic_btb_ras(cpu);
363 |     uint64_t estimated_call_instr_size = basic_btb_abs_addr_dist(call_ip, branch_target);
364 |     if (estimated_call_instr_size <= 10) {
365 |       basic_btb_call_instr_sizes[cpu][basic_btb_call_size_tracker_hash(call_ip)] = estimated_call_instr_size;
366 |     }
367 |   } 
368 | 
369 |   BTBEntry *btb_entry;
370 |   int partitionID = -1;
371 |   for (int i = 0; i < NUM_BTB_PARTITIONS; i++) {
372 | 	  btb_entry = btb_partition[i].get_BTBentry(ip);
373 | 	  if (btb_entry) {
374 | 		  partitionID = i;
375 | 		  break;
376 | 	  }
377 |   }
378 | 
379 |   if (btb_entry == NULL) {
380 | 
381 | 	  BTB_writes++;
382 | 
383 | 	  int num_bits;
384 | 	  if (branch_type == BRANCH_RETURN) {
385 | 		  num_bits = 0;
386 | 	  } else {
387 | 		  uint64_t diff_bits = (branch_target >> 2) ^ (ip >> 2);
388 | 		  num_bits = 0;
389 | 		  while (diff_bits != 0) {
390 | 			  diff_bits = diff_bits >> 1;
391 | 			  num_bits++;
392 | 		  }
393 | 	  }
394 | 	  assert(num_bits >= 0 && num_bits < 66);
395 | 
396 | 	  int smallest_offset_partition_id = convert_offsetBits_to_partitionID(num_bits);
397 | 
398 | 	  int partition = get_lru_partition(smallest_offset_partition_id, ip);
399 | 	  assert(partition < NUM_BTB_PARTITIONS);
400 | 
401 | 	  btb_partition[partition].update_BTB(ip, branch_type, branch_target, taken, basic_btb_lru_counter[cpu]);
402 | 	  basic_btb_lru_counter[cpu]++;
403 | 
404 | 
405 |   } else {
406 | 	    // update an existing entry
407 | 	  assert(partitionID != -1);
408 | 	  btb_partition[partitionID].update_BTB(ip, branch_type, branch_target, taken, basic_btb_lru_counter[cpu]);
409 | 	  basic_btb_lru_counter[cpu]++;
410 |   }
411 |   
412 | }
413 | 


--------------------------------------------------------------------------------
/btb/BTBX.btb:
--------------------------------------------------------------------------------
  1 | 
  2 | /*
  3 |  * This file implements a basic Branch Target Buffer (BTB) structure.
  4 |  * It uses a set-associative BTB to predict the targets of non-return branches,
  5 |  * and it uses a small Return Address Stack (RAS) to predict the target of
  6 |  * returns.
  7 |  */
  8 | 
  9 | #include "ooo_cpu.h"
 10 | 
 11 | #define BASIC_BTB_SETS 4096
 12 | #define BASIC_BTB_WAYS 4
 13 | #define BASIC_BTB_INDIRECT_SIZE 4096
 14 | #define BASIC_BTB_RAS_SIZE 64
 15 | #define BASIC_BTB_CALL_INSTR_SIZE_TRACKERS 1024
 16 | 
 17 | struct BTBEntry {
 18 |   uint64_t tag;
 19 |   uint64_t target_ip;
 20 |   uint8_t branch_type;
 21 |   uint64_t lru;
 22 | };
 23 | 
 24 | struct BTB {
 25 |         std::vector <std::vector<BTBEntry>> theBTB;
 26 |         uint32_t numSets;
 27 |         uint32_t assoc;
 28 |         uint64_t indexMask;
 29 |         uint32_t numIndexBits;
 30 | 
 31 |     BTB () {}
 32 | 
 33 |     BTB( int32_t Sets, int32_t Assoc )
 34 |       : numSets(Sets)
 35 |         , assoc(Assoc) {
 36 |           //aBTBSize must be a power of 2
 37 |           assert( ((Sets - 1) & (Sets)) == 0);
 38 |           theBTB.resize(Sets);
 39 |           indexMask = Sets - 1;
 40 |           numIndexBits = (uint32_t) log2((double)Sets);
 41 |         }
 42 | 
 43 |     void init_btb (int32_t Sets, int32_t Assoc) {
 44 |     	numSets = Sets;
 45 |     	assoc = Assoc;
 46 |         //aBTBSize must be a power of 2
 47 |         assert( ((Sets - 1) & (Sets)) == 0);
 48 |         theBTB.resize(Sets);
 49 |         indexMask = Sets - 1;
 50 |         numIndexBits = (uint32_t) log2((double)Sets);
 51 |     }
 52 | 
 53 |     int32_t index(uint64_t ip) {
 54 | 		return ((ip >> 2) & indexMask);
 55 |     }
 56 | 
 57 |     uint64_t get_tag(uint64_t ip) {
 58 |     	//return ip;
 59 |         uint64_t addr = ip;
 60 | 		addr = addr >> 2;
 61 |         addr = addr >> numIndexBits;
 62 |         /* We use a 16-bit tag.
 63 |          * The lower 8-bits stay the same as in the full tag.
 64 |          * The upper 8-bits are the folded X-OR of the remaining bits of the full tag.
 65 |          */
 66 |         uint64_t tag = addr & 0xFF; //Set the lower 8-bits of the tag
 67 |         addr = addr >> 8;
 68 |         int tagMSBs = 0;
 69 |         /*Get the upper 8-bits (folded X-OR)*/
 70 |         for (int i = 0; i < 8; i++) {
 71 |                 tagMSBs = tagMSBs ^ (addr & 0xFF);
 72 |                 addr = addr >> 8;
 73 |         }
 74 |         /*Concatenate the lower and upper 8-bits of tag*/
 75 |         tag = tag | (tagMSBs << 8);
 76 |         return tag;
 77 |     }
 78 | 
 79 |     BTBEntry *get_BTBentry(uint64_t ip){
 80 |         BTBEntry *entry = NULL;
 81 | 
 82 |         int idx = index(ip);
 83 |         uint64_t tag = get_tag(ip);
 84 |         for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 85 |                 if (theBTB[idx][i].tag == tag) {
 86 |                         return &(theBTB[idx][i]);
 87 |                 }
 88 |         }
 89 | 
 90 |         return entry;
 91 |     }
 92 | 
 93 |     void update_BTB(uint64_t ip, uint8_t b_type, uint64_t target, uint8_t taken, uint64_t lru_counter){
 94 |         int idx = index(ip);
 95 |         uint64_t tag = get_tag(ip);
 96 |         int way = -1;
 97 |         for (uint32_t i = 0; i < theBTB[idx].size(); i++) {
 98 |                 if (theBTB[idx][i].tag == tag) {
 99 |                         way = i;
100 |                         break;
101 |                 }
102 |         }
103 | 
104 |         if (way == -1) {
105 |         	if ((target != 0) && taken) {
106 |                 BTBEntry entry;
107 |                 entry.tag = tag;
108 |                 entry.branch_type = b_type;
109 |                 entry.target_ip = target;
110 |                 entry.lru = lru_counter;
111 | 
112 |                 if (theBTB[idx].size() >= assoc) {
113 |                         theBTB[idx].erase(theBTB[idx].begin());
114 |                 }
115 |                 theBTB[idx].push_back(entry);
116 |         	}
117 |         } else {
118 | 			BTBEntry entry = theBTB[idx][way];
119 | 			entry.branch_type = b_type;
120 | 			if (target != 0) {
121 | 					entry.target_ip = target;
122 | 			}
123 | 			entry.lru = lru_counter;
124 | 
125 | 			//Update LRU
126 | 			theBTB[idx].erase(theBTB[idx].begin() + way);
127 | 			theBTB[idx].push_back(entry);
128 |         }
129 |     }
130 | 
131 |     uint64_t get_lru_value(uint64_t ip) {
132 |         int idx = index(ip);
133 |         uint64_t lru_value;
134 |         if (theBTB[idx].size() < assoc) { //All ways are not yet allocated
135 |         	lru_value = 0;
136 |         } else {
137 |         	lru_value = theBTB[idx][0].lru;
138 |             for (uint32_t i = 1; i < theBTB[idx].size(); i++) { //We should never enter here because head should be LRU
139 |                     if (theBTB[idx][i].lru < lru_value) {
140 |                             assert(0);
141 |                     }
142 |             }
143 |         }
144 | 
145 |         return lru_value;
146 |     }
147 | 
148 | };
149 | 
150 | /*BTB BTB_4D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 10-bit) 28*1024*8 = 28KB
151 | BTB BTB_6D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 15-bit) 33*1024*7 = 28.875KB
152 | BTB BTB_8D(1024, 8);                                   //Storage: (tag:16-bit, branch-type: 2-bit, target-offset: 25-bit) 43*1024*8 = 43KB
153 | BTB BTB_12D(512, 8);                                    //Storage: (tag:16-bit, branch-type: 2-bit,   full-target: 64-bit) 82*256*4  = 10.25KB
154 | BTB BTB_18D(512, 8);
155 | BTB BTB_25D(256, 8);
156 | BTB BTB_46D(128, 8);
157 | BTB BTB_Ret(1024, 8);*/
158 | 
159 | #define NUM_BTB_PARTITIONS 9
160 | BTB btb_partition[NUM_BTB_PARTITIONS];
161 | 
162 | uint64_t basic_btb_lru_counter[NUM_CPUS];
163 | 
164 | uint64_t basic_btb_indirect[NUM_CPUS][BASIC_BTB_INDIRECT_SIZE];
165 | uint64_t basic_btb_conditional_history[NUM_CPUS];
166 | 
167 | uint64_t basic_btb_ras[NUM_CPUS][BASIC_BTB_RAS_SIZE];
168 | int basic_btb_ras_index[NUM_CPUS];
169 | /*
170 |  * The following two variables are used to automatically identify the
171 |  * size of call instructions, in bytes, which tells us the appropriate
172 |  * target for a call's corresponding return.
173 |  * They exist because ChampSim does not model a specific ISA, and
174 |  * different ISAs could use different sizes for call instructions,
175 |  * and even within the same ISA, calls can have different sizes.
176 |  */
177 | uint64_t basic_btb_call_instr_sizes[NUM_CPUS][BASIC_BTB_CALL_INSTR_SIZE_TRACKERS];
178 | 
179 | uint64_t basic_btb_abs_addr_dist(uint64_t addr1, uint64_t addr2) {
180 |   if(addr1 > addr2) {
181 |     return addr1 - addr2;
182 |   }
183 | 
184 |   return addr2 - addr1;
185 | }
186 | 
187 | void push_basic_btb_ras(uint8_t cpu, uint64_t ip) {
188 |   basic_btb_ras_index[cpu]++;
189 |   if (basic_btb_ras_index[cpu] == BASIC_BTB_RAS_SIZE) {
190 |     basic_btb_ras_index[cpu] = 0;
191 |   }
192 | 
193 |   basic_btb_ras[cpu][basic_btb_ras_index[cpu]] = ip;
194 | }
195 | 
196 | uint64_t peek_basic_btb_ras(uint8_t cpu) {
197 |   return basic_btb_ras[cpu][basic_btb_ras_index[cpu]];
198 | }
199 | 
200 | uint64_t pop_basic_btb_ras(uint8_t cpu) {
201 |   uint64_t target = basic_btb_ras[cpu][basic_btb_ras_index[cpu]];
202 |   basic_btb_ras[cpu][basic_btb_ras_index[cpu]] = 0;
203 | 
204 |   basic_btb_ras_index[cpu]--;
205 |   if (basic_btb_ras_index[cpu] == -1) {
206 |     basic_btb_ras_index[cpu] += BASIC_BTB_RAS_SIZE;
207 |   }
208 | 
209 |   return target;
210 | }
211 | 
212 | uint64_t basic_btb_call_size_tracker_hash(uint64_t ip) {
213 |   return (ip & (BASIC_BTB_CALL_INSTR_SIZE_TRACKERS-1));
214 | }
215 | 
216 | uint64_t basic_btb_get_call_size(uint8_t cpu, uint64_t ip) {
217 |   uint64_t size = basic_btb_call_instr_sizes[cpu][basic_btb_call_size_tracker_hash(ip)];
218 | 
219 |   return size;
220 | }
221 | 
222 | int convert_offsetBits_to_partitionID(int num_bits) {
223 | 	  if (num_bits == 0) {
224 | 		  return 0;
225 | 	  } else if (num_bits <= 4) {
226 | 		  return 1;
227 | 	  } else if (num_bits <= 5) {
228 | 		  return 2;
229 | 	  } else if (num_bits <= 7) {
230 | 		  return 3;
231 | 	  } else if (num_bits <= 9) {
232 | 		  return 4;
233 | 	  } else if (num_bits <= 11) {
234 | 		  return 5;
235 | 	  } else if (num_bits <= 19) {
236 | 		  return 6;
237 | 	  } else if (num_bits <= 25) {
238 | 		  return 7;
239 | 	  } else {
240 | 		  return 8;
241 | 	  }
242 | 	  assert(0);
243 | }
244 | 
245 | int get_lru_partition(int start_partitionID, uint64_t ip) {
246 | 	  int lru_partition = start_partitionID;
247 | 	  uint64_t lru_value = btb_partition[start_partitionID].get_lru_value(ip);
248 | 	  for (int i = start_partitionID + 1; i < NUM_BTB_PARTITIONS; i++) {
249 | 		uint64_t partition_lru_value = btb_partition[i].get_lru_value(ip);
250 | 	    if (partition_lru_value < lru_value) {
251 | 	      lru_partition = i;
252 | 	      lru_value = partition_lru_value;
253 | 	    }
254 | 	  }
255 | 	  return lru_partition;
256 | }
257 | 
258 | void O3_CPU::initialize_btb() {
259 |   std::cout << "Basic BTB sets: " << BASIC_BTB_SETS
260 |             << " ways: " << BASIC_BTB_WAYS
261 |             << " indirect buffer size: " << BASIC_BTB_INDIRECT_SIZE
262 |             << " RAS size: " << BASIC_BTB_RAS_SIZE << std::endl;
263 | 
264 |   for (uint32_t i = 0; i < BASIC_BTB_RAS_SIZE; i++) {
265 |     basic_btb_ras[cpu][i] = 0;
266 |   }
267 |   basic_btb_ras_index[cpu] = 0;
268 |   for (uint32_t i=0; i<BASIC_BTB_CALL_INSTR_SIZE_TRACKERS; i++) {
269 |     basic_btb_call_instr_sizes[cpu][i] = 4;
270 |   }
271 | 
272 |   basic_btb_lru_counter[cpu] = 0;
273 | 
274 |   btb_partition[0].init_btb(512, 1);
275 |   btb_partition[1].init_btb(512, 1);
276 |   btb_partition[2].init_btb(512, 1);
277 |   btb_partition[3].init_btb(512, 1);
278 |   btb_partition[4].init_btb(512, 1);
279 |   btb_partition[5].init_btb(512, 1);
280 |   btb_partition[6].init_btb(512, 1);
281 |   btb_partition[7].init_btb(512, 1);
282 |   btb_partition[8].init_btb(64, 1);
283 | }
284 | 
285 | BTB_outcome O3_CPU::btb_prediction(uint64_t ip, uint8_t branch_type) {
286 | 	BTBEntry *btb_entry;
287 | 
288 |   for (int i = 0; i < NUM_BTB_PARTITIONS; i++) {
289 | 	  btb_entry = btb_partition[i].get_BTBentry(ip);
290 | 	  if (btb_entry) {
291 | 		  break;
292 | 	  }
293 |   }
294 | 
295 |   if (btb_entry == NULL) {
296 |     // no prediction for this IP
297 |       if (branch_type == BRANCH_DIRECT_CALL || branch_type == BRANCH_INDIRECT_CALL) {
298 |           push_basic_btb_ras(cpu, ip);
299 |       }
300 |       BTB_outcome outcome = {0, BRANCH_CONDITIONAL, 2/*To indicate that it was a BTB miss*/};
301 |       	  return outcome;
302 |       //return std::make_pair(0, 0);
303 |   }
304 | 
305 |   branch_type = NOT_BRANCH;
306 |   branch_type = btb_entry->branch_type;
307 | 
308 |   //uint8_t always_taken = false;
309 |   //if (branch_type != BRANCH_CONDITIONAL) {
310 |     //always_taken = true;
311 |   //}
312 | 
313 |   if ((branch_type == BRANCH_DIRECT_CALL) ||
314 |       (branch_type == BRANCH_INDIRECT_CALL)) {
315 |     // add something to the RAS
316 |     push_basic_btb_ras(cpu, ip);
317 |   }
318 | 
319 |   if (branch_type == BRANCH_RETURN) {
320 |     // peek at the top of the RAS
321 |     uint64_t target = peek_basic_btb_ras(cpu);
322 |     // and adjust for the size of the call instr
323 |     target += basic_btb_get_call_size(cpu, target);
324 | 
325 |     BTB_outcome outcome = {target, BRANCH_RETURN, 0};
326 |     return outcome;
327 |     //return std::make_pair(target, always_taken);
328 |   } /*else if ((branch_type == BRANCH_INDIRECT) ||
329 |              (branch_type == BRANCH_INDIRECT_CALL)) {
330 |     return std::make_pair(basic_btb_indirect[cpu][basic_btb_indirect_hash(cpu, ip)], always_taken);
331 |   } */else {
332 |     // use BTB for all other branches + direct calls
333 | 
334 |     BTB_outcome outcome = {btb_entry->target_ip, branch_type, 0};
335 |     return outcome;
336 |     //return std::make_pair(btb_entry->target_ip, always_taken);
337 |   }
338 | 
339 |   assert(0);
340 |   //return std::make_pair(0, always_taken);
341 | }
342 | 
343 | void O3_CPU::update_btb(uint64_t ip, uint64_t branch_target, uint8_t taken,
344 |                         uint8_t branch_type) {
345 |   // updates for indirect branches
346 |   /*if ((branch_type == BRANCH_INDIRECT) ||
347 |       (branch_type == BRANCH_INDIRECT_CALL)) {
348 |     basic_btb_indirect[cpu][basic_btb_indirect_hash(cpu, ip)] = branch_target;
349 |   }
350 |   if (branch_type == BRANCH_CONDITIONAL) {
351 |     basic_btb_conditional_history[cpu] <<= 1;
352 |     if (taken) {
353 |       basic_btb_conditional_history[cpu] |= 1;
354 |     }
355 |   }*/
356 | 
357 |   if (branch_type == BRANCH_RETURN) {
358 |     // recalibrate call-return offset
359 |     // if our return prediction got us into the right ball park, but not the
360 |     // exactly correct byte target, then adjust our call instr size tracker
361 |     uint64_t call_ip = pop_basic_btb_ras(cpu);
362 |     uint64_t estimated_call_instr_size = basic_btb_abs_addr_dist(call_ip, branch_target);
363 |     if (estimated_call_instr_size <= 10) {
364 |       basic_btb_call_instr_sizes[cpu][basic_btb_call_size_tracker_hash(call_ip)] = estimated_call_instr_size;
365 |     }
366 |   }
367 | 
368 |   if (taken == false)
369 | 	  return;
370 | 
371 |   BTBEntry *btb_entry;
372 |   int partitionID = -1;
373 |   for (int i = 0; i < NUM_BTB_PARTITIONS; i++) {
374 | 	  btb_entry = btb_partition[i].get_BTBentry(ip);
375 | 	  if (btb_entry) {
376 | 		  partitionID = i;
377 | 		  break;
378 | 	  }
379 |   }
380 | 
381 |   if (btb_entry == NULL) {
382 | 
383 | 	  BTB_writes++;
384 | 
385 | 	  int num_bits;
386 | 	  if (branch_type == BRANCH_RETURN) {
387 | 		  num_bits = 0;
388 | 	  } else {
389 | 		  uint64_t diff_bits = (branch_target >> 2) ^ (ip >> 2);
390 | 		  num_bits = 0;
391 | 		  while (diff_bits != 0) {
392 | 			  diff_bits = diff_bits >> 1;
393 | 			  num_bits++;
394 | 		  }
395 | 	  }
396 | 	  assert(num_bits >= 0 && num_bits < 66);
397 | 
398 | 	  int smallest_offset_partition_id = convert_offsetBits_to_partitionID(num_bits);
399 | 
400 | 	  int partition = get_lru_partition(smallest_offset_partition_id, ip);
401 | 	  assert(partition < NUM_BTB_PARTITIONS);
402 | 
403 | 	  btb_partition[partition].update_BTB(ip, branch_type, branch_target, taken, basic_btb_lru_counter[cpu]);
404 | 	  basic_btb_lru_counter[cpu]++;
405 | 
406 | 
407 |   } else {
408 | 	    // update an existing entry
409 | 	  assert(partitionID != -1);
410 | 	  btb_partition[partitionID].update_BTB(ip, branch_type, branch_target, taken, basic_btb_lru_counter[cpu]);
411 | 	  basic_btb_lru_counter[cpu]++;
412 |   }
413 |   
414 | }
415 | 


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