├── Accelerator-Design ├── pll.qip ├── .qsys_edit │ ├── testSystem_schematic.nlv │ ├── filters.xml │ └── preferences.xml ├── software │ ├── MNIST_CNN_Software │ │ ├── .force_rebuild │ │ ├── .force_relink │ │ ├── generic_tristate_controller_0.flash │ │ ├── mem_init │ │ │ ├── meminit.qip │ │ │ └── meminit.spd │ │ ├── gmon.out │ │ ├── kann_data.h │ │ ├── readme.txt │ │ ├── .project │ │ └── .settings │ │ │ └── language.settings.xml │ ├── MNIST_MLP_Software │ │ ├── .force_rebuild │ │ ├── kann_data.h │ │ ├── readme.txt │ │ ├── .project │ │ └── .settings │ │ │ └── language.settings.xml │ ├── MNIST_CNN_Software_bsp │ │ ├── mnist-nn.zip │ │ ├── drivers │ │ │ └── src │ │ │ │ └── altera_avalon_cfi_flash_amd.c │ │ ├── script │ │ │ └── flash_programmer.sh │ │ ├── .project │ │ ├── .settings │ │ │ └── language.settings.xml │ │ ├── create-this-bsp │ │ ├── HAL │ │ │ ├── inc │ │ │ │ ├── priv │ │ │ │ │ └── alt_busy_sleep.h │ │ │ │ └── sys │ │ │ │ │ └── alt_irq_entry.h │ │ │ └── src │ │ │ │ ├── altera_nios2_qsys_irq.c │ │ │ │ ├── alt_usleep.c │ │ │ │ └── alt_log_macro.S │ │ └── memory.gdb │ └── MNIST_MLP_Software_bsp │ │ ├── mnist-nn.zip │ │ ├── drivers │ │ └── src │ │ │ └── altera_avalon_cfi_flash_amd.c │ │ ├── script │ │ └── flash_programmer.sh │ │ ├── .project │ │ ├── .settings │ │ └── language.settings.xml │ │ ├── create-this-bsp │ │ ├── HAL │ │ ├── inc │ │ │ ├── priv │ │ │ │ └── alt_busy_sleep.h │ │ │ └── sys │ │ │ │ └── alt_irq_entry.h │ │ └── src │ │ │ ├── altera_nios2_qsys_irq.c │ │ │ ├── alt_usleep.c │ │ │ └── alt_log_macro.S │ │ └── memory.gdb ├── nios_system │ ├── testbench │ │ ├── cadence │ │ │ ├── hdl.var │ │ │ └── cds_libs │ │ │ │ ├── altera_common_sv_packages.cds.lib │ │ │ │ ├── cmd_mux.cds.lib │ │ │ │ ├── dma_0.cds.lib │ │ │ │ ├── router.cds.lib │ │ │ │ ├── rsp_mux.cds.lib │ │ │ │ ├── sram_0.cds.lib │ │ │ │ ├── tda.cds.lib │ │ │ │ ├── tdt.cds.lib │ │ │ │ ├── timer_0.cds.lib │ │ │ │ ├── cmd_demux.cds.lib │ │ │ │ ├── cmd_mux_001.cds.lib │ │ │ │ ├── cmd_mux_002.cds.lib │ │ │ │ ├── cmd_mux_005.cds.lib │ │ │ │ ├── cmd_mux_008.cds.lib │ │ │ │ ├── cmd_mux_009.cds.lib │ │ │ │ ├── cmd_mux_010.cds.lib │ │ │ │ ├── irq_mapper.cds.lib │ │ │ │ ├── jtag_uart_0.cds.lib │ │ │ │ ├── nios2_qsys_0.cds.lib │ │ │ │ ├── router_001.cds.lib │ │ │ │ ├── router_002.cds.lib │ │ │ │ ├── router_003.cds.lib │ │ │ │ ├── router_005.cds.lib │ │ │ │ ├── router_006.cds.lib │ │ │ │ ├── router_007.cds.lib │ │ │ │ ├── router_010.cds.lib │ │ │ │ ├── router_013.cds.lib │ │ │ │ ├── router_014.cds.lib │ │ │ │ ├── router_015.cds.lib │ │ │ │ ├── rsp_demux.cds.lib │ │ │ │ ├── rsp_mux_001.cds.lib │ │ │ │ ├── rsp_mux_002.cds.lib │ │ │ │ ├── rsp_mux_003.cds.lib │ │ │ │ ├── avalon_st_adapter.cds.lib │ │ │ │ ├── cmd_demux_001.cds.lib │ │ │ │ ├── cmd_demux_002.cds.lib │ │ │ │ ├── cmd_demux_003.cds.lib │ │ │ │ ├── cmd_demux_004.cds.lib │ │ │ │ ├── error_adapter_0.cds.lib │ │ │ │ ├── mm_interconnect_0.cds.lib │ │ │ │ ├── nios_system_inst.cds.lib │ │ │ │ ├── rsp_demux_001.cds.lib │ │ │ │ ├── rsp_demux_002.cds.lib │ │ │ │ ├── rsp_demux_005.cds.lib │ │ │ │ ├── rsp_demux_009.cds.lib │ │ │ │ ├── rsp_demux_010.cds.lib │ │ │ │ ├── rst_controller.cds.lib │ │ │ │ ├── slave_translator.cds.lib │ │ │ │ ├── avalon_st_adapter_001.cds.lib │ │ │ │ ├── avalon_st_adapter_002.cds.lib │ │ │ │ ├── floating_point_adder_0.cds.lib │ │ │ │ ├── new_sdram_controller_0.cds.lib │ │ │ │ ├── performance_counter_0.cds.lib │ │ │ │ ├── video_alpha_blender_0.cds.lib │ │ │ │ ├── video_rgb_resampler_0.cds.lib │ │ │ │ ├── video_vga_controller_0.cds.lib │ │ │ │ ├── tristate_conduit_bridge_0.cds.lib │ │ │ │ ├── video_dual_clock_buffer_0.cds.lib │ │ │ │ ├── video_pixel_buffer_dma_0.cds.lib │ │ │ │ ├── nios_system_inst_clk_0_bfm.cds.lib │ │ │ │ ├── floating_point_multiplier_0.cds.lib │ │ │ │ ├── nios_system_inst_reset_0_bfm.cds.lib │ │ │ │ ├── generic_tristate_controller_0.cds.lib │ │ │ │ ├── nn_acc_multi_buffer_version_0.cds.lib │ │ │ │ ├── nn_acc_single_buffer_version_0.cds.lib │ │ │ │ ├── nn_acc_single_buffer_version_1.cds.lib │ │ │ │ ├── sram_0_avalon_sram_slave_agent.cds.lib │ │ │ │ ├── nios2_qsys_0_data_master_limiter.cds.lib │ │ │ │ ├── new_sdram_controller_0_my_partner.cds.lib │ │ │ │ ├── video_character_buffer_with_dma_0.cds.lib │ │ │ │ ├── sram_0_avalon_sram_slave_burst_adapter.cds.lib │ │ │ │ ├── sram_0_avalon_sram_slave_agent_rsp_fifo.cds.lib │ │ │ │ ├── tristate_conduit_bridge_0_tcb_translator.cds.lib │ │ │ │ ├── generic_tristate_controller_0_external_mem_bfm.cds.lib │ │ │ │ ├── nios2_qsys_0_custom_instruction_master_translator.cds.lib │ │ │ │ ├── nios2_qsys_0_custom_instruction_master_comb_xconnect.cds.lib │ │ │ │ ├── video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent.cds.lib │ │ │ │ └── video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator.cds.lib │ │ ├── nios_system.ipx │ │ └── nios_system_tb │ │ │ └── simulation │ │ │ └── submodules │ │ │ ├── nios_system_nios2_qsys_0_rf_ram_a.dat │ │ │ ├── nios_system_nios2_qsys_0_rf_ram_b.dat │ │ │ ├── altera_tristate_conduit_bridge_translator.sv │ │ │ ├── altera_inout.sv │ │ │ ├── nios_system_nios2_qsys_0_oci_test_bench.v │ │ │ ├── altera_reset_controller.sdc │ │ │ ├── AcceleratorPackage.sv │ │ │ ├── nios_system_nios2_qsys_0_bht_ram.dat │ │ │ ├── nios_system_irq_mapper.sv │ │ │ └── data_buffer.sv │ └── synthesis │ │ └── submodules │ │ ├── nios_system_nios2_qsys_0.ocp │ │ ├── nios_system_nios2_qsys_0.v │ │ ├── nios_system_nios2_qsys_0_oci_test_bench.v │ │ ├── altera_reset_controller.sdc │ │ └── nios_system_irq_mapper.sv ├── simple_NN_acc.sdc ├── output_files │ └── simple_NN_acc.sld └── simple_NN_acc.qpf ├── vsim.wlf ├── Reference-Software ├── kann-master │ ├── .gitignore │ ├── dna │ │ └── README.md │ ├── doc │ │ ├── images │ │ │ ├── mlp.png │ │ │ ├── rnn.png │ │ │ ├── autodiff.png │ │ │ ├── matmul1.png │ │ │ ├── matmul2.png │ │ │ └── rnn-unroll.png │ │ └── README.md │ ├── kann_extra │ │ └── kann_data.h │ └── LICENSE.txt └── mnist-nn-release0 │ ├── source │ ├── mnist-nn.zip │ ├── mnist-cnn │ │ └── kann_data.h │ └── mnist-mlp │ │ └── kann_data.h │ └── instruction │ └── project_mnist_nn_instruction.pdf ├── README.md ├── tbAccl.do ├── .gitignore └── Custom-Hardware-Blocks ├── AcceleratorPackage.sv ├── data_buffer.sv ├── datapath_tb.sv └── fp_tb.sv /Accelerator-Design/pll.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Accelerator-Design/.qsys_edit/testSystem_schematic.nlv: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/.force_rebuild: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/.force_relink: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software/.force_rebuild: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ramachav/Simple-Neural-Network-Accelerator/HEAD/vsim.wlf -------------------------------------------------------------------------------- /Reference-Software/kann-master/.gitignore: -------------------------------------------------------------------------------- 1 | .*.swp 2 | *.o 3 | *.a 4 | *.kan 5 | *.dSYM 6 | a.out 7 | -------------------------------------------------------------------------------- /Accelerator-Design/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/generic_tristate_controller_0.flash: -------------------------------------------------------------------------------- 1 | S00600002D454C3B 2 | S70500000000FA -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/mem_init/meminit.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SEARCH_PATH $::quartus(qip_path) 2 | -------------------------------------------------------------------------------- /Accelerator-Design/simple_NN_acc.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 20 -waveform {0 10} CLOCK_50 2 | derive_pll_clocks 3 | derive_clock_uncertainty 4 | -------------------------------------------------------------------------------- /Reference-Software/kann-master/dna/README.md: -------------------------------------------------------------------------------- 1 | The examples in this directory have been moved a [separate repo][dna-nn]. 2 | 3 | [dna-nn]: https://github.com/lh3/dna-nn 4 | -------------------------------------------------------------------------------- /Reference-Software/kann-master/doc/images/mlp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ramachav/Simple-Neural-Network-Accelerator/HEAD/Reference-Software/kann-master/doc/images/mlp.png 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-------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/mnist-nn.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ramachav/Simple-Neural-Network-Accelerator/HEAD/Accelerator-Design/software/MNIST_MLP_Software_bsp/mnist-nn.zip -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/synthesis/submodules/nios_system_nios2_qsys_0.ocp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ramachav/Simple-Neural-Network-Accelerator/HEAD/Accelerator-Design/nios_system/synthesis/submodules/nios_system_nios2_qsys_0.ocp -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/synthesis/submodules/nios_system_nios2_qsys_0.v: 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https://raw.githubusercontent.com/ramachav/Simple-Neural-Network-Accelerator/HEAD/Accelerator-Design/software/MNIST_CNN_Software_bsp/drivers/src/altera_avalon_cfi_flash_amd.c -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/drivers/src/altera_avalon_cfi_flash_amd.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ramachav/Simple-Neural-Network-Accelerator/HEAD/Accelerator-Design/software/MNIST_MLP_Software_bsp/drivers/src/altera_avalon_cfi_flash_amd.c -------------------------------------------------------------------------------- /Reference-Software/kann-master/doc/README.md: -------------------------------------------------------------------------------- 1 | This directory contains KANN documentations. 2 | 3 | * [01user.md](01user.md): for API users 4 | 5 | * [02dev.md](02dev.md): for hackers and developers who want to understand the 6 | internals of KANN. 7 | 8 | * 11math.tex (in LaTeX): some math notes. 9 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Simple-Neural-Network-Accelerator 2 | Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerate the inference on a database of 10000 images. The trained model was made using KANN C libraries and the accelerator was synthesized as part of an SoC on an Altera FPGA. 3 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/mem_init/meminit.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Accelerator-Design/output_files/simple_NN_acc.sld: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Reference-Software/kann-master/kann_extra/kann_data.h: -------------------------------------------------------------------------------- 1 | #ifndef KANN_DATA_H 2 | #define KANN_DATA_H 3 | 4 | typedef struct kann_data_t { 5 | int n_row, n_col, n_grp; 6 | float **x; 7 | char **rname, **cname; 8 | int *grp; 9 | } kann_data_t; 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | kann_data_t *kann_data_read(const char *fn); 16 | void kann_data_free(kann_data_t *d); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/kann_data.h: -------------------------------------------------------------------------------- 1 | #ifndef KANN_DATA_H 2 | #define KANN_DATA_H 3 | 4 | typedef struct kann_data_t { 5 | int n_row, n_col, n_grp; 6 | float **x; 7 | char **rname, **cname; 8 | int *grp; 9 | } kann_data_t; 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | kann_data_t *kann_data_read(const char *fn); 16 | void kann_data_free(kann_data_t *d); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software/kann_data.h: -------------------------------------------------------------------------------- 1 | #ifndef KANN_DATA_H 2 | #define KANN_DATA_H 3 | 4 | typedef struct kann_data_t { 5 | int n_row, n_col, n_grp; 6 | float **x; 7 | char **rname, **cname; 8 | int *grp; 9 | } kann_data_t; 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | kann_data_t *kann_data_read(const char *fn); 16 | void kann_data_free(kann_data_t *d); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /Reference-Software/mnist-nn-release0/source/mnist-cnn/kann_data.h: -------------------------------------------------------------------------------- 1 | #ifndef KANN_DATA_H 2 | #define KANN_DATA_H 3 | 4 | typedef struct kann_data_t { 5 | int n_row, n_col, n_grp; 6 | float **x; 7 | char **rname, **cname; 8 | int *grp; 9 | } kann_data_t; 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | kann_data_t *kann_data_read(const char *fn); 16 | void kann_data_free(kann_data_t *d); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /Reference-Software/mnist-nn-release0/source/mnist-mlp/kann_data.h: -------------------------------------------------------------------------------- 1 | #ifndef KANN_DATA_H 2 | #define KANN_DATA_H 3 | 4 | typedef struct kann_data_t { 5 | int n_row, n_col, n_grp; 6 | float **x; 7 | char **rname, **cname; 8 | int *grp; 9 | } kann_data_t; 10 | 11 | #ifdef __cplusplus 12 | extern "C" { 13 | #endif 14 | 15 | kann_data_t *kann_data_read(const char *fn); 16 | void kann_data_free(kann_data_t *d); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/nios_system_nios2_qsys_0_rf_ram_a.dat: -------------------------------------------------------------------------------- 1 | @00 2 | deadbeef 3 | deadbeef 4 | deadbeef 5 | deadbeef 6 | deadbeef 7 | deadbeef 8 | deadbeef 9 | deadbeef 10 | deadbeef 11 | deadbeef 12 | deadbeef 13 | deadbeef 14 | deadbeef 15 | deadbeef 16 | deadbeef 17 | deadbeef 18 | deadbeef 19 | deadbeef 20 | deadbeef 21 | deadbeef 22 | deadbeef 23 | deadbeef 24 | deadbeef 25 | deadbeef 26 | deadbeef 27 | deadbeef 28 | deadbeef 29 | deadbeef 30 | deadbeef 31 | deadbeef 32 | deadbeef 33 | deadbeef 34 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/nios_system_nios2_qsys_0_rf_ram_b.dat: -------------------------------------------------------------------------------- 1 | @00 2 | deadbeef 3 | deadbeef 4 | deadbeef 5 | deadbeef 6 | deadbeef 7 | deadbeef 8 | deadbeef 9 | deadbeef 10 | deadbeef 11 | deadbeef 12 | deadbeef 13 | deadbeef 14 | deadbeef 15 | deadbeef 16 | deadbeef 17 | deadbeef 18 | deadbeef 19 | deadbeef 20 | deadbeef 21 | deadbeef 22 | deadbeef 23 | deadbeef 24 | deadbeef 25 | deadbeef 26 | deadbeef 27 | deadbeef 28 | deadbeef 29 | deadbeef 30 | deadbeef 31 | deadbeef 32 | deadbeef 33 | deadbeef 34 | -------------------------------------------------------------------------------- /Accelerator-Design/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/readme.txt: -------------------------------------------------------------------------------- 1 | This template is starting point for creating a project based on your custom C code. 2 | It will provide you a default project to which you can add your software files. To 3 | add files to a project, manually copy the file into the application directory (e.g. 4 | using Windows Explorer), then right click on your application project and select 5 | refresh. 6 | 7 | You can also add files to the project using the Nios II Software Build Tools for Eclipse import function. 8 | Select File -> Import. 9 | Expand General and select File System in the Import Window and click Next. 10 | Identify the appropriate source and destination directories. 11 | Check the files you want to add and click Finish. 12 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software/readme.txt: -------------------------------------------------------------------------------- 1 | This template is starting point for creating a project based on your custom C code. 2 | It will provide you a default project to which you can add your software files. To 3 | add files to a project, manually copy the file into the application directory (e.g. 4 | using Windows Explorer), then right click on your application project and select 5 | refresh. 6 | 7 | You can also add files to the project using the Nios II Software Build Tools for Eclipse import function. 8 | Select File -> Import. 9 | Expand General and select File System in the Import Window and click Next. 10 | Identify the appropriate source and destination directories. 11 | Check the files you want to add and click Finish. 12 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/script/flash_programmer.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # This file was automatically generated. 4 | # 5 | # It can be overwritten by nios2-flash-programmer-generate or nios2-flash-programmer-gui. 6 | # 7 | 8 | # 9 | # Converting Binary File: /home/ecegrid/a/695r15/ece695r/ramachav_project/Simple-Neural-Network-Accelerator/Accelerator-Design/software/MNIST_CNN_Software_bsp/mnist-nn.zip to: "../flash/mnist-nn_generic_tristate_controller_0.flash" 10 | # 11 | bin2flash --input="/home/ecegrid/a/695r15/ece695r/ramachav_project/Simple-Neural-Network-Accelerator/Accelerator-Design/software/MNIST_CNN_Software_bsp/mnist-nn.zip" --output="../flash/mnist-nn_generic_tristate_controller_0.flash" --location=0x0 --verbose 12 | 13 | # 14 | # Programming File: "../flash/mnist-nn_generic_tristate_controller_0.flash" To Device: generic_tristate_controller_0 15 | # 16 | nios2-flash-programmer "../flash/mnist-nn_generic_tristate_controller_0.flash" --base=0x8800000 --accept-bad-sysid --device=1 --instance=0 '--cable=USB-Blaster on localhost [1-5]' --program --verbose 17 | 18 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/script/flash_programmer.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # This file was automatically generated. 4 | # 5 | # It can be overwritten by nios2-flash-programmer-generate or nios2-flash-programmer-gui. 6 | # 7 | 8 | # 9 | # Converting Binary File: /home/ecegrid/a/695r15/ece695r/ramachav_project/Simple-Neural-Network-Accelerator/Accelerator-Design/software/MNIST_MLP_Software_bsp/mnist-nn.zip to: "../flash/mnist-nn_generic_tristate_controller_0.flash" 10 | # 11 | bin2flash --input="/home/ecegrid/a/695r15/ece695r/ramachav_project/Simple-Neural-Network-Accelerator/Accelerator-Design/software/MNIST_MLP_Software_bsp/mnist-nn.zip" --output="../flash/mnist-nn_generic_tristate_controller_0.flash" --location=0x0 --verbose 12 | 13 | # 14 | # Programming File: "../flash/mnist-nn_generic_tristate_controller_0.flash" To Device: generic_tristate_controller_0 15 | # 16 | nios2-flash-programmer "../flash/mnist-nn_generic_tristate_controller_0.flash" --base=0x8800000 --accept-bad-sysid --device=1 --instance=0 '--cable=USB-Blaster on localhost [1-12]' --program --verbose 17 | 18 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | MNIST_CNN_Software_bsp 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | org.eclipse.cdt.core.ccnature 26 | com.altera.sbtgui.project.SBTGUINature 27 | com.altera.sbtgui.project.SBTGUIBspNature 28 | 29 | 30 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | MNIST_MLP_Software_bsp 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | org.eclipse.cdt.core.ccnature 26 | com.altera.sbtgui.project.SBTGUINature 27 | com.altera.sbtgui.project.SBTGUIBspNature 28 | 29 | 30 | -------------------------------------------------------------------------------- /tbAccl.do: -------------------------------------------------------------------------------- 1 | 2 | quietly set PROJECT_DIR "/home/ecegrid/a/695r15/ece695r/ramachav_project/Simple-Neural-Network-Accelerator" 3 | 4 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/AcceleratorPackage.sv" 5 | 6 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/fp_adder.sv" 7 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/fp_multiplier.sv" 8 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/pipeline_registers.sv" 9 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/data_buffer.sv" 10 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/datapath.sv" 11 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/AcceleratorTopMod.sv" 12 | 13 | vlog -reportprogress 300 -work work "${PROJECT_DIR}/Custom-Hardware-Blocks/tbAccl.sv" 14 | 15 | vsim -novopt work.tbAccl 16 | 17 | 18 | add wave -position insertpoint sim:/tbAccl/accl/* 19 | add wave -position insertpoint sim:/tbAccl/accl/mac/* 20 | add wave -position insertpoint sim:/tbAccl/accl/mac/PIPELINE_REGISTERS/* 21 | 22 | run 200 ns 23 | 24 | -------------------------------------------------------------------------------- /Reference-Software/kann-master/LICENSE.txt: -------------------------------------------------------------------------------- 1 | The MIT License 2 | 3 | Copyright (c) 2018-2019 Dana-Farber Cancer Institute 4 | 2016-2018 Broad Institute 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining 7 | a copy of this software and associated documentation files (the 8 | "Software"), to deal in the Software without restriction, including 9 | without limitation the rights to use, copy, modify, merge, publish, 10 | distribute, sublicense, and/or sell copies of the Software, and to 11 | permit persons to whom the Software is furnished to do so, subject to 12 | the following conditions: 13 | 14 | The above copyright notice and this permission notice shall be 15 | included in all copies or substantial portions of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 | NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 21 | BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 22 | ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 24 | SOFTWARE. 25 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # A gitignore for Altera Quartus II that tries to ignore almost all of the 2 | # automatically Quartus-generated files. This primarily leaves the project, 3 | # settings, source, and constraint files to be added. The files ignored do not 4 | # include the bulk of the MegaFunction Wizard generated files which enables 5 | # a cloned repository to be used (usually) immediately without regenerating 6 | # Altera IP blocks. 7 | 8 | # Need to keep all HDL files and timing constraint files 9 | # *.vhd 10 | # *.v 11 | # *.sdc 12 | 13 | # ignore Quartus II generated folders 14 | *_sim 15 | Accelerator-Design/db 16 | Accelerator-Design/greybox_tmp 17 | Accelerator-Design/incremental_db 18 | Accelerator-Design/simulation 19 | Accelerator-Design/testbench 20 | Accelerator-Design/timing 21 | 22 | Accelerator-Design/nios_system/synthesis 23 | 24 | # ignore Quartus II generated files 25 | *_generation_script* 26 | *_inst.vhd 27 | *.bak 28 | *.cmp 29 | *.done 30 | *.eqn 31 | *.hex 32 | *.html 33 | *.jdi 34 | *.jpg 35 | *.mif 36 | *.pin 37 | *.pof 38 | *.ptf.* 39 | *.qar 40 | *.qarlog 41 | *.qws 42 | *.rpt 43 | *.smsg 44 | *.sof 45 | *.sopc_builder 46 | *.summary 47 | *.tcl 48 | *.txt # Explicitly add any text files used 49 | *~ 50 | *example* 51 | *sopc_* 52 | 53 | #QuestaSim 54 | work/ -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/altera_tristate_conduit_bridge_translator.sv: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ns 3 | 4 | module altera_tristate_conduit_bridge_translator ( 5 | input wire [23-1:0] in_tcm_address_out 6 | ,output wire [23-1:0] tcm_address_out 7 | ,input wire [1-1:0] in_tcm_read_n_out 8 | ,output wire [1-1:0] tcm_read_n_out 9 | ,input wire [1-1:0] in_tcm_write_n_out 10 | ,output wire [1-1:0] tcm_write_n_out 11 | ,inout wire [8-1:0] in_tcm_data_out 12 | ,inout wire [8-1:0] tcm_data_out 13 | ,input wire [1-1:0] in_tcm_chipselect_n_out 14 | ,output wire [1-1:0] tcm_chipselect_n_out 15 | ); 16 | assign tcm_address_out = in_tcm_address_out; 17 | assign tcm_read_n_out = in_tcm_read_n_out; 18 | assign tcm_write_n_out = in_tcm_write_n_out; 19 | altera_inout #( 20 | .WIDTH_A(8), 21 | .WIDTH_B(8) 22 | ) tcm_data_out_inout_module ( 23 | .a(tcm_data_out), 24 | .b(in_tcm_data_out) 25 | ); 26 | assign tcm_chipselect_n_out = in_tcm_chipselect_n_out; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/altera_common_sv_packages.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | -------------------------------------------------------------------------------- /Accelerator-Design/simple_NN_acc.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Intel and sold by Intel or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition 22 | # Date created = 18:29:49 October 22, 2019 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "17.0" 27 | DATE = "18:29:49 October 22, 2019" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "simple_NN_acc" 32 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | MNIST_CNN_Software 4 | 5 | 6 | 7 | 8 | 9 | com.altera.sbtgui.project.makefileBuilder 10 | 11 | 12 | 13 | 14 | com.altera.sbtgui.project.makefileBuilder 15 | 16 | 17 | 18 | 19 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 20 | clean,full,incremental, 21 | 22 | 23 | 24 | 25 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 26 | full,incremental, 27 | 28 | 29 | 30 | 31 | 32 | org.eclipse.cdt.core.cnature 33 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 34 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 35 | org.eclipse.cdt.core.ccnature 36 | com.altera.sbtgui.project.SBTGUINature 37 | com.altera.sbtgui.project.SBTGUIAppNature 38 | com.altera.sbtgui.project.SBTGUIManagedNature 39 | 40 | 41 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | MNIST_MLP_Software 4 | 5 | 6 | 7 | 8 | 9 | com.altera.sbtgui.project.makefileBuilder 10 | 11 | 12 | 13 | 14 | com.altera.sbtgui.project.makefileBuilder 15 | 16 | 17 | 18 | 19 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 20 | clean,full,incremental, 21 | 22 | 23 | 24 | 25 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 26 | full,incremental, 27 | 28 | 29 | 30 | 31 | 32 | org.eclipse.cdt.core.cnature 33 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 34 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 35 | org.eclipse.cdt.core.ccnature 36 | com.altera.sbtgui.project.SBTGUINature 37 | com.altera.sbtgui.project.SBTGUIAppNature 38 | com.altera.sbtgui.project.SBTGUIManagedNature 39 | 40 | 41 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux ./../libraries/cmd_mux/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/dma_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE dma_0 ./../libraries/dma_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router ./../libraries/router/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_mux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_mux ./../libraries/rsp_mux/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/sram_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE sram_0 ./../libraries/sram_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/tda.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE tda ./../libraries/tda/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/tdt.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE tdt ./../libraries/tdt/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/timer_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE timer_0 ./../libraries/timer_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/create-this-bsp: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # This script creates the ucosii_net_zipfs Board Support Package (BSP). 4 | 5 | BSP_TYPE=hal 6 | BSP_DIR=. 7 | SOPC_DIR=../../ 8 | SOPC_FILE=../../nios_system.sopcinfo 9 | NIOS2_BSP_ARGS="" 10 | CPU_NAME= 11 | 12 | if [ -n "$CPU_NAME" ]; then 13 | NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME" 14 | fi 15 | 16 | # Don't run make if create-this-app script is called with --no-make arg 17 | SKIP_MAKE= 18 | while [ $# -gt 0 ] 19 | do 20 | case "$1" in 21 | --no-make) 22 | SKIP_MAKE=1 23 | ;; 24 | *) 25 | NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" 26 | ;; 27 | esac 28 | shift 29 | done 30 | 31 | 32 | # Run nios2-bsp utility to create a hal BSP in this directory 33 | # for the system with a .sopc file in $SOPC_FILE. 34 | # Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. 35 | 36 | if [ -z "$SOPC_FILE" ]; then 37 | echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." 38 | cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS" 39 | else 40 | cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS" 41 | fi 42 | 43 | 44 | echo "create-this-bsp: Running \"$cmd\"" 45 | $cmd || { 46 | echo "$cmd failed" 47 | exit 1 48 | } 49 | if [ -z "$SKIP_MAKE" ]; then 50 | echo "create-this-bsp: Running make" 51 | make 52 | fi 53 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/create-this-bsp: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # This script creates the ucosii_net_zipfs Board Support Package (BSP). 4 | 5 | BSP_TYPE=hal 6 | BSP_DIR=. 7 | SOPC_DIR=../../ 8 | SOPC_FILE=../../nios_system.sopcinfo 9 | NIOS2_BSP_ARGS="" 10 | CPU_NAME= 11 | 12 | if [ -n "$CPU_NAME" ]; then 13 | NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS --cpu-name $CPU_NAME" 14 | fi 15 | 16 | # Don't run make if create-this-app script is called with --no-make arg 17 | SKIP_MAKE= 18 | while [ $# -gt 0 ] 19 | do 20 | case "$1" in 21 | --no-make) 22 | SKIP_MAKE=1 23 | ;; 24 | *) 25 | NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" 26 | ;; 27 | esac 28 | shift 29 | done 30 | 31 | 32 | # Run nios2-bsp utility to create a hal BSP in this directory 33 | # for the system with a .sopc file in $SOPC_FILE. 34 | # Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. 35 | 36 | if [ -z "$SOPC_FILE" ]; then 37 | echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." 38 | cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS" 39 | else 40 | cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS" 41 | fi 42 | 43 | 44 | echo "create-this-bsp: Running \"$cmd\"" 45 | $cmd || { 46 | echo "$cmd failed" 47 | exit 1 48 | } 49 | if [ -z "$SKIP_MAKE" ]; then 50 | echo "create-this-bsp: Running make" 51 | make 52 | fi 53 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_demux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_demux ./../libraries/cmd_demux/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux_001 ./../libraries/cmd_mux_001/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux_002 ./../libraries/cmd_mux_002/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux_005.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux_005 ./../libraries/cmd_mux_005/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux_008.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux_008 ./../libraries/cmd_mux_008/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux_009.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux_009 ./../libraries/cmd_mux_009/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_mux_010.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_mux_010 ./../libraries/cmd_mux_010/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/irq_mapper.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE irq_mapper ./../libraries/irq_mapper/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/jtag_uart_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE jtag_uart_0 ./../libraries/jtag_uart_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios2_qsys_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios2_qsys_0 ./../libraries/nios2_qsys_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_001 ./../libraries/router_001/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_002 ./../libraries/router_002/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_003 ./../libraries/router_003/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_005.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_005 ./../libraries/router_005/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_006.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_006 ./../libraries/router_006/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_007.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_007 ./../libraries/router_007/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_010.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_010 ./../libraries/router_010/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_013.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_013 ./../libraries/router_013/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_014.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_014 ./../libraries/router_014/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/router_015.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE router_015 ./../libraries/router_015/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_demux.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_demux ./../libraries/rsp_demux/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_mux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_mux_001 ./../libraries/rsp_mux_001/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_mux_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_mux_002 ./../libraries/rsp_mux_002/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_mux_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_mux_003 ./../libraries/rsp_mux_003/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/avalon_st_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE avalon_st_adapter ./../libraries/avalon_st_adapter/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_demux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_demux_001 ./../libraries/cmd_demux_001/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_demux_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_demux_002 ./../libraries/cmd_demux_002/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_demux_003.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_demux_003 ./../libraries/cmd_demux_003/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/cmd_demux_004.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE cmd_demux_004 ./../libraries/cmd_demux_004/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/error_adapter_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE error_adapter_0 ./../libraries/error_adapter_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/mm_interconnect_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE mm_interconnect_0 ./../libraries/mm_interconnect_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios_system_inst.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios_system_inst ./../libraries/nios_system_inst/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_demux_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_demux_001 ./../libraries/rsp_demux_001/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_demux_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_demux_002 ./../libraries/rsp_demux_002/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_demux_005.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_demux_005 ./../libraries/rsp_demux_005/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_demux_009.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_demux_009 ./../libraries/rsp_demux_009/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rsp_demux_010.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rsp_demux_010 ./../libraries/rsp_demux_010/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/rst_controller.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE rst_controller ./../libraries/rst_controller/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/slave_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE slave_translator ./../libraries/slave_translator/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/avalon_st_adapter_001.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE avalon_st_adapter_001 ./../libraries/avalon_st_adapter_001/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/avalon_st_adapter_002.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE avalon_st_adapter_002 ./../libraries/avalon_st_adapter_002/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/floating_point_adder_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE floating_point_adder_0 ./../libraries/floating_point_adder_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/new_sdram_controller_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE new_sdram_controller_0 ./../libraries/new_sdram_controller_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/performance_counter_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE performance_counter_0 ./../libraries/performance_counter_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_alpha_blender_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_alpha_blender_0 ./../libraries/video_alpha_blender_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_rgb_resampler_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_rgb_resampler_0 ./../libraries/video_rgb_resampler_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_vga_controller_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_vga_controller_0 ./../libraries/video_vga_controller_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/tristate_conduit_bridge_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE tristate_conduit_bridge_0 ./../libraries/tristate_conduit_bridge_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_dual_clock_buffer_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_dual_clock_buffer_0 ./../libraries/video_dual_clock_buffer_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_pixel_buffer_dma_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_pixel_buffer_dma_0 ./../libraries/video_pixel_buffer_dma_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios_system_inst_clk_0_bfm.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios_system_inst_clk_0_bfm ./../libraries/nios_system_inst_clk_0_bfm/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/floating_point_multiplier_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE floating_point_multiplier_0 ./../libraries/floating_point_multiplier_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/altera_inout.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | 15 | `timescale 1 ns / 1 ns 16 | 17 | module altera_inout #( 18 | parameter WIDTH_A = 1, 19 | parameter WIDTH_B = 1 20 | ) ( 21 | inout wire [WIDTH_A-1:0] a, 22 | inout wire [WIDTH_B-1:0] b 23 | ); 24 | 25 | genvar i; 26 | 27 | generate 28 | if(WIDTH_A <= WIDTH_B) begin 29 | for(i = 0; i < WIDTH_A; i++) begin : width_a_loop 30 | tran (a[i],b[i]); 31 | end 32 | end 33 | else begin 34 | for(i = 0; i < WIDTH_B; i++) begin : width_b_loop 35 | tran (a[i],b[i]); 36 | end 37 | end 38 | endgenerate 39 | 40 | endmodule // altera_inout 41 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios_system_inst_reset_0_bfm.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios_system_inst_reset_0_bfm ./../libraries/nios_system_inst_reset_0_bfm/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/generic_tristate_controller_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE generic_tristate_controller_0 ./../libraries/generic_tristate_controller_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nn_acc_multi_buffer_version_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nn_acc_multi_buffer_version_0 ./../libraries/nn_acc_multi_buffer_version_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nn_acc_single_buffer_version_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nn_acc_single_buffer_version_0 ./../libraries/nn_acc_single_buffer_version_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nn_acc_single_buffer_version_1.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nn_acc_single_buffer_version_1 ./../libraries/nn_acc_single_buffer_version_1/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/sram_0_avalon_sram_slave_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE sram_0_avalon_sram_slave_agent ./../libraries/sram_0_avalon_sram_slave_agent/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/HAL/inc/priv/alt_busy_sleep.h: -------------------------------------------------------------------------------- 1 | #ifndef __ALT_BUSY_SLEEP_H 2 | #define __ALT_BUSY_SLEEP_H 3 | 4 | /* 5 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. 6 | * All rights reserved. 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy 9 | * of this software and associated documentation files (the "Software"), to 10 | * deal in the Software without restriction, including without limitation the 11 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 12 | * sell copies of the Software, and to permit persons to whom the Software is 13 | * furnished to do so, subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in 16 | * all copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 | * DEALINGS IN THE SOFTWARE. 25 | */ 26 | 27 | /* 28 | * The function alt_busy_sleep provides a busy loop implementation of usleep. 29 | * This is used to provide usleep for the standalone HAL, or when the timer is 30 | * unavailable in uC/OS-II. 31 | */ 32 | 33 | extern unsigned int alt_busy_sleep (unsigned int us); 34 | 35 | #endif /* __ALT_BUSY_SLEEP_H */ 36 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/HAL/inc/priv/alt_busy_sleep.h: -------------------------------------------------------------------------------- 1 | #ifndef __ALT_BUSY_SLEEP_H 2 | #define __ALT_BUSY_SLEEP_H 3 | 4 | /* 5 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. 6 | * All rights reserved. 7 | * 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy 9 | * of this software and associated documentation files (the "Software"), to 10 | * deal in the Software without restriction, including without limitation the 11 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 12 | * sell copies of the Software, and to permit persons to whom the Software is 13 | * furnished to do so, subject to the following conditions: 14 | * 15 | * The above copyright notice and this permission notice shall be included in 16 | * all copies or substantial portions of the Software. 17 | * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 | * DEALINGS IN THE SOFTWARE. 25 | */ 26 | 27 | /* 28 | * The function alt_busy_sleep provides a busy loop implementation of usleep. 29 | * This is used to provide usleep for the standalone HAL, or when the timer is 30 | * unavailable in uC/OS-II. 31 | */ 32 | 33 | extern unsigned int alt_busy_sleep (unsigned int us); 34 | 35 | #endif /* __ALT_BUSY_SLEEP_H */ 36 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios2_qsys_0_data_master_limiter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios2_qsys_0_data_master_limiter ./../libraries/nios2_qsys_0_data_master_limiter/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_oci_test_bench.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | // synthesis translate_off 14 | `timescale 1ns / 1ps 15 | // synthesis translate_on 16 | 17 | // turn off superfluous verilog processor warnings 18 | // altera message_level Level1 19 | // altera message_off 10034 10035 10036 10037 10230 10240 10030 20 | 21 | module nios_system_nios2_qsys_0_oci_test_bench ( 22 | // inputs: 23 | dct_buffer, 24 | dct_count, 25 | test_ending, 26 | test_has_ended 27 | ) 28 | ; 29 | 30 | input [ 29: 0] dct_buffer; 31 | input [ 3: 0] dct_count; 32 | input test_ending; 33 | input test_has_ended; 34 | 35 | 36 | 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/HAL/src/altera_nios2_qsys_irq.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. 3 | * All rights reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to 7 | * deal in the Software without restriction, including without limitation the 8 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 9 | * sell copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 | * DEALINGS IN THE SOFTWARE. 22 | * 23 | * altera_nios2_irq.c - Support for Nios II internal interrupt controller. 24 | * 25 | */ 26 | 27 | #include "sys/alt_irq.h" 28 | #include "altera_nios2_qsys_irq.h" 29 | 30 | /* 31 | * To initialize the internal interrupt controller, just clear the IENABLE 32 | * register so that all possible IRQs are disabled. 33 | */ 34 | void altera_nios2_qsys_irq_init(void) 35 | { 36 | NIOS2_WRITE_IENABLE(0); 37 | } 38 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/HAL/src/altera_nios2_qsys_irq.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. 3 | * All rights reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to 7 | * deal in the Software without restriction, including without limitation the 8 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 9 | * sell copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 | * DEALINGS IN THE SOFTWARE. 22 | * 23 | * altera_nios2_irq.c - Support for Nios II internal interrupt controller. 24 | * 25 | */ 26 | 27 | #include "sys/alt_irq.h" 28 | #include "altera_nios2_qsys_irq.h" 29 | 30 | /* 31 | * To initialize the internal interrupt controller, just clear the IENABLE 32 | * register so that all possible IRQs are disabled. 33 | */ 34 | void altera_nios2_qsys_irq_init(void) 35 | { 36 | NIOS2_WRITE_IENABLE(0); 37 | } 38 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/nios_system_nios2_qsys_0_oci_test_bench.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | // synthesis translate_off 14 | `timescale 1ns / 1ps 15 | // synthesis translate_on 16 | 17 | // turn off superfluous verilog processor warnings 18 | // altera message_level Level1 19 | // altera message_off 10034 10035 10036 10037 10230 10240 10030 20 | 21 | module nios_system_nios2_qsys_0_oci_test_bench ( 22 | // inputs: 23 | dct_buffer, 24 | dct_count, 25 | test_ending, 26 | test_has_ended 27 | ) 28 | ; 29 | 30 | input [ 29: 0] dct_buffer; 31 | input [ 3: 0] dct_count; 32 | input test_ending; 33 | input test_has_ended; 34 | 35 | 36 | 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/new_sdram_controller_0_my_partner.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE new_sdram_controller_0_my_partner ./../libraries/new_sdram_controller_0_my_partner/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_character_buffer_with_dma_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_character_buffer_with_dma_0 ./../libraries/video_character_buffer_with_dma_0/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/synthesis/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | set aclr_counter [get_collection_size $aclr_collection] 22 | set clrn_counter [get_collection_size $clrn_collection] 23 | 24 | if {$aclr_counter > 0} { 25 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 26 | } 27 | 28 | if {$clrn_counter > 0} { 29 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 30 | } 31 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/sram_0_avalon_sram_slave_burst_adapter.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE sram_0_avalon_sram_slave_burst_adapter ./../libraries/sram_0_avalon_sram_slave_burst_adapter/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/sram_0_avalon_sram_slave_agent_rsp_fifo.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE sram_0_avalon_sram_slave_agent_rsp_fifo ./../libraries/sram_0_avalon_sram_slave_agent_rsp_fifo/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/tristate_conduit_bridge_0_tcb_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE tristate_conduit_bridge_0_tcb_translator ./../libraries/tristate_conduit_bridge_0_tcb_translator/ 20 | -------------------------------------------------------------------------------- /Custom-Hardware-Blocks/AcceleratorPackage.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * AcceleratorPackage.vhd 3 | * 4 | * Created : 26 Nov 2019, 12:44 PM EST 5 | * Author : Abhishek Bhaumick 6 | * 7 | */ 8 | 9 | 10 | package AcceleratorPackage; 11 | 12 | parameter AddressBitWidth = 10; 13 | parameter DataBitWidth = 32; 14 | 15 | typedef logic [DataBitWidth-1:0] float32b; 16 | typedef logic [DataBitWidth-1:0] AcclDataType; 17 | 18 | function integer clog2; 19 | input integer value; 20 | begin 21 | value = value-1; 22 | for (clog2=0; value>0; clog2=clog2+1) 23 | value = value>>1; 24 | end 25 | endfunction 26 | 27 | 28 | parameter FilterRowSize = 3; 29 | parameter FilterColSize = 3; 30 | parameter FilterLayerSize = 32; 31 | parameter NumFilterCoeffs = FilterRowSize * FilterColSize; 32 | 33 | typedef logic [DataBitWidth-1:0] AcclAddrType; 34 | 35 | const integer NumPartitionBits = 2; 36 | 37 | parameter AddrRoutingBits = 2; 38 | 39 | const AcclAddrType AddrOffsetControl = 10'h000; 40 | const AcclAddrType AddrOffsetCoeff = 10'h100; 41 | const AcclAddrType AddrOffsetData = 10'h200; 42 | const AcclAddrType AddrOffsetResult = 10'h300; 43 | 44 | const logic [AddrRoutingBits-1:0] routeControl = AddrOffsetControl[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 45 | const logic [AddrRoutingBits-1:0] routeCoeff = AddrOffsetCoeff[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 46 | const logic [AddrRoutingBits-1:0] routeData = AddrOffsetData[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 47 | const logic [AddrRoutingBits-1:0] routeResult = AddrOffsetResult[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 48 | 49 | parameter PixelBufferDepth = 16; 50 | parameter PixelBufferCount = 8; 51 | parameter BlockCount = FilterLayerSize / PixelBufferCount; 52 | 53 | typedef enum { 54 | s_Idle, 55 | s_ReadInput, 56 | s_WaitForCalc, 57 | s_ReadResult 58 | } MacStateType; 59 | 60 | parameter MacEngineLatency = 5; 61 | 62 | const AcclDataType FloatValue_1_0 = 'h3f800000; 63 | 64 | parameter ResultBufferSize = 24; 65 | 66 | endpackage -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/AcceleratorPackage.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * AcceleratorPackage.vhd 3 | * 4 | * Created : 26 Nov 2019, 12:44 PM EST 5 | * Author : Abhishek Bhaumick 6 | * 7 | */ 8 | 9 | 10 | package AcceleratorPackage; 11 | 12 | parameter AddressBitWidth = 10; 13 | parameter DataBitWidth = 32; 14 | 15 | typedef logic [DataBitWidth-1:0] float32b; 16 | typedef logic [DataBitWidth-1:0] AcclDataType; 17 | 18 | function integer clog2; 19 | input integer value; 20 | begin 21 | value = value-1; 22 | for (clog2=0; value>0; clog2=clog2+1) 23 | value = value>>1; 24 | end 25 | endfunction 26 | 27 | 28 | parameter FilterRowSize = 3; 29 | parameter FilterColSize = 3; 30 | parameter FilterLayerSize = 32; 31 | parameter NumFilterCoeffs = FilterRowSize * FilterColSize; 32 | 33 | typedef logic [DataBitWidth-1:0] AcclAddrType; 34 | 35 | const integer NumPartitionBits = 2; 36 | 37 | parameter AddrRoutingBits = 2; 38 | 39 | const AcclAddrType AddrOffsetControl = 10'h000; 40 | const AcclAddrType AddrOffsetCoeff = 10'h100; 41 | const AcclAddrType AddrOffsetData = 10'h200; 42 | const AcclAddrType AddrOffsetResult = 10'h300; 43 | 44 | const logic [AddrRoutingBits-1:0] routeControl = AddrOffsetControl[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 45 | const logic [AddrRoutingBits-1:0] routeCoeff = AddrOffsetCoeff[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 46 | const logic [AddrRoutingBits-1:0] routeData = AddrOffsetData[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 47 | const logic [AddrRoutingBits-1:0] routeResult = AddrOffsetResult[AddressBitWidth-1:AddressBitWidth-AddrRoutingBits]; 48 | 49 | parameter PixelBufferDepth = 16; 50 | parameter PixelBufferCount = 8; 51 | parameter BlockCount = FilterLayerSize / PixelBufferCount; 52 | 53 | typedef enum { 54 | s_Idle, 55 | s_ReadInput, 56 | s_WaitForCalc, 57 | s_ReadResult 58 | } MacStateType; 59 | 60 | parameter MacEngineLatency = 5; 61 | 62 | const AcclDataType FloatValue_1_0 = 'h3f800000; 63 | 64 | parameter ResultBufferSize = 24; 65 | 66 | endpackage -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/HAL/src/alt_usleep.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. 3 | * All rights reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to 7 | * deal in the Software without restriction, including without limitation the 8 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 9 | * sell copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 | * DEALINGS IN THE SOFTWARE. 22 | * 23 | * ------------ 24 | * 25 | * Altera does not recommend, suggest or require that this reference design 26 | * file be used in conjunction or combination with any other product. 27 | * 28 | * usleep.c - Microsecond delay routine 29 | */ 30 | 31 | #include 32 | 33 | #include "priv/alt_busy_sleep.h" 34 | #include "os/alt_syscall.h" 35 | 36 | /* 37 | * This function simply calls alt_busy_sleep() to perform the delay. This 38 | * function implements the delay as a calibrated "busy loop". 39 | * 40 | * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h 41 | */ 42 | 43 | 44 | 45 | #if defined (__GNUC__) && __GNUC__ >= 4 46 | int ALT_USLEEP (useconds_t us) 47 | #else 48 | unsigned int ALT_USLEEP (unsigned int us) 49 | #endif 50 | { 51 | return alt_busy_sleep(us); 52 | } 53 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/HAL/src/alt_usleep.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. 3 | * All rights reserved. 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to 7 | * deal in the Software without restriction, including without limitation the 8 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 9 | * sell copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 | * DEALINGS IN THE SOFTWARE. 22 | * 23 | * ------------ 24 | * 25 | * Altera does not recommend, suggest or require that this reference design 26 | * file be used in conjunction or combination with any other product. 27 | * 28 | * usleep.c - Microsecond delay routine 29 | */ 30 | 31 | #include 32 | 33 | #include "priv/alt_busy_sleep.h" 34 | #include "os/alt_syscall.h" 35 | 36 | /* 37 | * This function simply calls alt_busy_sleep() to perform the delay. This 38 | * function implements the delay as a calibrated "busy loop". 39 | * 40 | * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h 41 | */ 42 | 43 | 44 | 45 | #if defined (__GNUC__) && __GNUC__ >= 4 46 | int ALT_USLEEP (useconds_t us) 47 | #else 48 | unsigned int ALT_USLEEP (unsigned int us) 49 | #endif 50 | { 51 | return alt_busy_sleep(us); 52 | } 53 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/synthesis/submodules/nios_system_irq_mapper.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/17.0std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2017/01/22 $ 17 | // $Author: swbranch $ 18 | 19 | // ------------------------------------------------------- 20 | // Altera IRQ Mapper 21 | // 22 | // Parameters 23 | // NUM_RCVRS : 3 24 | // SENDER_IRW_WIDTH : 32 25 | // IRQ_MAP : 0:0,1:1,2:2 26 | // 27 | // ------------------------------------------------------- 28 | 29 | `timescale 1 ns / 1 ns 30 | 31 | module nios_system_irq_mapper 32 | ( 33 | // ------------------- 34 | // Clock & Reset 35 | // ------------------- 36 | input clk, 37 | input reset, 38 | 39 | // ------------------- 40 | // IRQ Receivers 41 | // ------------------- 42 | input receiver0_irq, 43 | input receiver1_irq, 44 | input receiver2_irq, 45 | 46 | // ------------------- 47 | // Command Source (Output) 48 | // ------------------- 49 | output reg [31 : 0] sender_irq 50 | ); 51 | 52 | 53 | always @* begin 54 | sender_irq = 0; 55 | 56 | sender_irq[0] = receiver0_irq; 57 | sender_irq[1] = receiver1_irq; 58 | sender_irq[2] = receiver2_irq; 59 | end 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/nios_system_nios2_qsys_0_bht_ram.dat: -------------------------------------------------------------------------------- 1 | // Contents are randomly generated during RTL generation. 2 | @00 3 | 1 4 | 2 5 | 3 6 | 2 7 | 3 8 | 3 9 | 0 10 | 2 11 | 0 12 | 0 13 | 0 14 | 0 15 | 1 16 | 3 17 | 3 18 | 3 19 | 3 20 | 0 21 | 0 22 | 0 23 | 1 24 | 0 25 | 3 26 | 3 27 | 1 28 | 0 29 | 1 30 | 3 31 | 1 32 | 1 33 | 1 34 | 3 35 | 0 36 | 0 37 | 2 38 | 1 39 | 1 40 | 2 41 | 2 42 | 0 43 | 1 44 | 0 45 | 3 46 | 0 47 | 3 48 | 1 49 | 2 50 | 0 51 | 3 52 | 3 53 | 1 54 | 0 55 | 0 56 | 0 57 | 2 58 | 2 59 | 1 60 | 0 61 | 2 62 | 3 63 | 3 64 | 0 65 | 1 66 | 2 67 | 1 68 | 2 69 | 2 70 | 1 71 | 3 72 | 2 73 | 1 74 | 3 75 | 3 76 | 2 77 | 1 78 | 1 79 | 2 80 | 0 81 | 0 82 | 0 83 | 3 84 | 1 85 | 2 86 | 1 87 | 2 88 | 2 89 | 1 90 | 0 91 | 0 92 | 0 93 | 1 94 | 1 95 | 0 96 | 2 97 | 1 98 | 2 99 | 0 100 | 3 101 | 3 102 | 3 103 | 3 104 | 1 105 | 3 106 | 1 107 | 0 108 | 2 109 | 0 110 | 0 111 | 0 112 | 2 113 | 3 114 | 1 115 | 1 116 | 1 117 | 2 118 | 1 119 | 2 120 | 3 121 | 3 122 | 3 123 | 3 124 | 2 125 | 2 126 | 1 127 | 2 128 | 3 129 | 1 130 | 2 131 | 1 132 | 1 133 | 2 134 | 2 135 | 2 136 | 1 137 | 2 138 | 2 139 | 2 140 | 3 141 | 1 142 | 1 143 | 3 144 | 3 145 | 2 146 | 1 147 | 3 148 | 3 149 | 0 150 | 2 151 | 1 152 | 1 153 | 1 154 | 3 155 | 2 156 | 0 157 | 2 158 | 2 159 | 3 160 | 1 161 | 1 162 | 2 163 | 2 164 | 3 165 | 2 166 | 3 167 | 1 168 | 3 169 | 3 170 | 1 171 | 3 172 | 2 173 | 1 174 | 0 175 | 1 176 | 0 177 | 3 178 | 1 179 | 1 180 | 2 181 | 1 182 | 1 183 | 0 184 | 2 185 | 1 186 | 2 187 | 2 188 | 1 189 | 1 190 | 2 191 | 2 192 | 2 193 | 0 194 | 1 195 | 3 196 | 1 197 | 0 198 | 3 199 | 3 200 | 3 201 | 1 202 | 2 203 | 0 204 | 3 205 | 0 206 | 0 207 | 1 208 | 0 209 | 0 210 | 3 211 | 3 212 | 1 213 | 3 214 | 0 215 | 3 216 | 3 217 | 0 218 | 0 219 | 2 220 | 1 221 | 1 222 | 1 223 | 2 224 | 2 225 | 1 226 | 0 227 | 1 228 | 2 229 | 1 230 | 2 231 | 1 232 | 2 233 | 3 234 | 0 235 | 3 236 | 1 237 | 1 238 | 3 239 | 1 240 | 0 241 | 2 242 | 1 243 | 3 244 | 1 245 | 3 246 | 3 247 | 1 248 | 2 249 | 1 250 | 1 251 | 0 252 | 1 253 | 3 254 | 3 255 | 2 256 | 2 257 | 1 258 | 2 259 | -------------------------------------------------------------------------------- /Custom-Hardware-Blocks/data_buffer.sv: -------------------------------------------------------------------------------- 1 | /******************************************* 2 | * Parameterized Data buffer * 3 | * ECE 69500R SoC Architecture * 4 | * Simple Neural Network Accelerator * 5 | *******************************************/ 6 | 7 | module data_buffer ( 8 | input logic clk, 9 | input logic reset, 10 | input logic read_enable, 11 | input logic write_enable, 12 | input logic [31:0] write_data, 13 | output logic [31:0] read_data, 14 | output logic buffer_full, 15 | output logic buffer_empty 16 | ); 17 | 18 | parameter BUFFER_SIZE = 32; 19 | 20 | logic [$clog2(BUFFER_SIZE):0] write_ptr, nextstate_write_ptr; 21 | logic [$clog2(BUFFER_SIZE):0] read_ptr, nextstate_read_ptr; 22 | logic [31:0] data_buffer_array [0:BUFFER_SIZE-1]; //Buffer to store incoming data. (32 32-bit registers) 23 | 24 | always_ff @ (posedge clk, posedge reset) begin 25 | if(reset) begin 26 | write_ptr <= '0; 27 | data_buffer_array <= '{default:'0}; 28 | end 29 | else if(write_enable) begin 30 | data_buffer_array[write_ptr[$clog2(BUFFER_SIZE)-1:0]] <= write_data; 31 | write_ptr <= nextstate_write_ptr; 32 | end 33 | else begin 34 | write_ptr <= write_ptr; 35 | end 36 | end 37 | 38 | always_ff @ (posedge clk, posedge reset) begin 39 | if(reset) begin 40 | read_ptr <= '0; 41 | end 42 | else if(read_enable) begin 43 | read_ptr <= nextstate_read_ptr; 44 | end 45 | else begin 46 | read_ptr <= read_ptr; 47 | end 48 | end 49 | 50 | assign nextstate_read_ptr = (read_ptr[$clog2(BUFFER_SIZE)-1:0] == (BUFFER_SIZE-1))? { ~read_ptr[$clog2(BUFFER_SIZE)], {$clog2(BUFFER_SIZE){1'b0}} } : (read_ptr + 1); 51 | assign nextstate_write_ptr = (write_ptr[$clog2(BUFFER_SIZE)-1:0] == (BUFFER_SIZE-1))? { ~write_ptr[$clog2(BUFFER_SIZE)], {$clog2(BUFFER_SIZE){1'b0}} } : (write_ptr + 1); 52 | assign buffer_full = (read_ptr[$clog2(BUFFER_SIZE)-1:0] == write_ptr[$clog2(BUFFER_SIZE)-1:0]) & (write_ptr[$clog2(BUFFER_SIZE)] != read_ptr[$clog2(BUFFER_SIZE)]); 53 | assign buffer_empty = (read_ptr == write_ptr); 54 | 55 | assign read_data = data_buffer_array[read_ptr[$clog2(BUFFER_SIZE)-1:0]]; 56 | 57 | endmodule //data_buffer 58 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/nios_system_irq_mapper.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/17.0std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2017/01/22 $ 17 | // $Author: swbranch $ 18 | 19 | // ------------------------------------------------------- 20 | // Altera IRQ Mapper 21 | // 22 | // Parameters 23 | // NUM_RCVRS : 3 24 | // SENDER_IRW_WIDTH : 32 25 | // IRQ_MAP : 0:0,1:1,2:2 26 | // 27 | // ------------------------------------------------------- 28 | 29 | `timescale 1 ns / 1 ns 30 | 31 | module nios_system_irq_mapper 32 | ( 33 | // ------------------- 34 | // Clock & Reset 35 | // ------------------- 36 | input clk, 37 | input reset, 38 | 39 | // ------------------- 40 | // IRQ Receivers 41 | // ------------------- 42 | input receiver0_irq, 43 | input receiver1_irq, 44 | input receiver2_irq, 45 | 46 | // ------------------- 47 | // Command Source (Output) 48 | // ------------------- 49 | output reg [31 : 0] sender_irq 50 | ); 51 | 52 | 53 | always @* begin 54 | sender_irq = 0; 55 | 56 | sender_irq[0] = receiver0_irq; 57 | sender_irq[1] = receiver1_irq; 58 | sender_irq[2] = receiver2_irq; 59 | end 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/nios_system_tb/simulation/submodules/data_buffer.sv: -------------------------------------------------------------------------------- 1 | /******************************************* 2 | * Parameterized Data buffer * 3 | * ECE 69500R SoC Architecture * 4 | * Simple Neural Network Accelerator * 5 | *******************************************/ 6 | 7 | module data_buffer ( 8 | input logic clk, 9 | input logic reset, 10 | input logic read_enable, 11 | input logic write_enable, 12 | input logic [31:0] write_data, 13 | output logic [31:0] read_data, 14 | output logic buffer_full, 15 | output logic buffer_empty 16 | ); 17 | 18 | parameter BUFFER_SIZE = 32; 19 | 20 | logic [$clog2(BUFFER_SIZE):0] write_ptr, nextstate_write_ptr; 21 | logic [$clog2(BUFFER_SIZE):0] read_ptr, nextstate_read_ptr; 22 | logic [31:0] data_buffer_array [0:BUFFER_SIZE-1]; //Buffer to store incoming data. (32 32-bit registers) 23 | 24 | always_ff @ (posedge clk, posedge reset) begin 25 | if(reset) begin 26 | write_ptr <= '0; 27 | data_buffer_array <= '{default:'0}; 28 | end 29 | else if(write_enable) begin 30 | data_buffer_array[write_ptr[$clog2(BUFFER_SIZE)-1:0]] <= write_data; 31 | write_ptr <= nextstate_write_ptr; 32 | end 33 | else begin 34 | write_ptr <= write_ptr; 35 | end 36 | end 37 | 38 | always_ff @ (posedge clk, posedge reset) begin 39 | if(reset) begin 40 | read_ptr <= '0; 41 | end 42 | else if(read_enable) begin 43 | read_ptr <= nextstate_read_ptr; 44 | end 45 | else begin 46 | read_ptr <= read_ptr; 47 | end 48 | end 49 | 50 | assign nextstate_read_ptr = (read_ptr[$clog2(BUFFER_SIZE)-1:0] == (BUFFER_SIZE-1))? { ~read_ptr[$clog2(BUFFER_SIZE)], {$clog2(BUFFER_SIZE){1'b0}} } : (read_ptr + 1); 51 | assign nextstate_write_ptr = (write_ptr[$clog2(BUFFER_SIZE)-1:0] == (BUFFER_SIZE-1))? { ~write_ptr[$clog2(BUFFER_SIZE)], {$clog2(BUFFER_SIZE){1'b0}} } : (write_ptr + 1); 52 | assign buffer_full = (read_ptr[$clog2(BUFFER_SIZE)-1:0] == write_ptr[$clog2(BUFFER_SIZE)-1:0]) & (write_ptr[$clog2(BUFFER_SIZE)] != read_ptr[$clog2(BUFFER_SIZE)]); 53 | assign buffer_empty = (read_ptr == write_ptr); 54 | 55 | assign read_data = data_buffer_array[read_ptr[$clog2(BUFFER_SIZE)-1:0]]; 56 | 57 | endmodule //data_buffer 58 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/HAL/src/alt_log_macro.S: -------------------------------------------------------------------------------- 1 | /* alt_log_macro.S 2 | * 3 | * Implements the function tx_log_str, called by the assembly macro 4 | * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, 5 | * and this function will not be compiled. When logging is on, 6 | * this function is used to print out the strings defined in the beginning 7 | * of alt_log_printf.c, using port information taken from system.h and 8 | * alt_log_printf.h. 9 | * 10 | * This routine only handles strings, and sends a character into the defined 11 | * output device's output buffer when the device is ready. It's intended for 12 | * debugging purposes, where messages can be set to print out at certain 13 | * points in the boot code to indicate the progress of the program. 14 | * 15 | */ 16 | 17 | #ifndef __ALT_LOG_MACROS__ 18 | #define __ALT_LOG_MACROS__ 19 | 20 | /* define this flag to skip assembly-incompatible parts 21 | * of various include files. */ 22 | #define ALT_ASM_SRC 23 | 24 | #ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. 25 | 26 | #include "system.h" 27 | #include "sys/alt_log_printf.h" 28 | 29 | .global tx_log_str 30 | tx_log_str: 31 | /* load base uart / jtag uart address into r6 */ 32 | movhi r6, %hiadj(ALT_LOG_PORT_BASE) 33 | addi r6, r6, %lo(ALT_LOG_PORT_BASE) 34 | tx_next_char: 35 | /* if pointer points to null, return 36 | * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ 37 | ldb r7, (r4) 38 | beq r0, r7, end_tx 39 | 40 | /* check device transmit ready */ 41 | wait_tx_ready_loop: 42 | ldwio r8, ALT_LOG_PRINT_REG_OFFSET(r6) 43 | /*UART, ALT_LOG_PRINT_MSK == 0x40 44 | JTAG UART, ALT_LOG_PRINT_MSK == 0xFFFF0000 */ 45 | andhi r5, r8, %hi(ALT_LOG_PRINT_MSK) 46 | andi r8, r8, %lo(ALT_LOG_PRINT_MSK) 47 | or r5, r5, r8 48 | beq r5, r0, wait_tx_ready_loop 49 | /* write char */ 50 | stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) 51 | /* advance string pointer */ 52 | addi r4, r4, 1 53 | br tx_next_char 54 | end_tx: 55 | ret 56 | 57 | #endif 58 | 59 | #endif /* __ALT_LOG_MACROS__ */ 60 | 61 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/HAL/src/alt_log_macro.S: -------------------------------------------------------------------------------- 1 | /* alt_log_macro.S 2 | * 3 | * Implements the function tx_log_str, called by the assembly macro 4 | * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, 5 | * and this function will not be compiled. When logging is on, 6 | * this function is used to print out the strings defined in the beginning 7 | * of alt_log_printf.c, using port information taken from system.h and 8 | * alt_log_printf.h. 9 | * 10 | * This routine only handles strings, and sends a character into the defined 11 | * output device's output buffer when the device is ready. It's intended for 12 | * debugging purposes, where messages can be set to print out at certain 13 | * points in the boot code to indicate the progress of the program. 14 | * 15 | */ 16 | 17 | #ifndef __ALT_LOG_MACROS__ 18 | #define __ALT_LOG_MACROS__ 19 | 20 | /* define this flag to skip assembly-incompatible parts 21 | * of various include files. */ 22 | #define ALT_ASM_SRC 23 | 24 | #ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. 25 | 26 | #include "system.h" 27 | #include "sys/alt_log_printf.h" 28 | 29 | .global tx_log_str 30 | tx_log_str: 31 | /* load base uart / jtag uart address into r6 */ 32 | movhi r6, %hiadj(ALT_LOG_PORT_BASE) 33 | addi r6, r6, %lo(ALT_LOG_PORT_BASE) 34 | tx_next_char: 35 | /* if pointer points to null, return 36 | * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ 37 | ldb r7, (r4) 38 | beq r0, r7, end_tx 39 | 40 | /* check device transmit ready */ 41 | wait_tx_ready_loop: 42 | ldwio r8, ALT_LOG_PRINT_REG_OFFSET(r6) 43 | /*UART, ALT_LOG_PRINT_MSK == 0x40 44 | JTAG UART, ALT_LOG_PRINT_MSK == 0xFFFF0000 */ 45 | andhi r5, r8, %hi(ALT_LOG_PRINT_MSK) 46 | andi r8, r8, %lo(ALT_LOG_PRINT_MSK) 47 | or r5, r5, r8 48 | beq r5, r0, wait_tx_ready_loop 49 | /* write char */ 50 | stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) 51 | /* advance string pointer */ 52 | addi r4, r4, 1 53 | br tx_next_char 54 | end_tx: 55 | ret 56 | 57 | #endif 58 | 59 | #endif /* __ALT_LOG_MACROS__ */ 60 | 61 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/generic_tristate_controller_0_external_mem_bfm.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE generic_tristate_controller_0_external_mem_bfm ./../libraries/generic_tristate_controller_0_external_mem_bfm/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios2_qsys_0_custom_instruction_master_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios2_qsys_0_custom_instruction_master_translator ./../libraries/nios2_qsys_0_custom_instruction_master_translator/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/memory.gdb: -------------------------------------------------------------------------------- 1 | # memory.gdb - GDB memory region definitions 2 | # 3 | # Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'nios_system' 4 | # SOPC Builder design path: ../../nios_system.sopcinfo 5 | # 6 | # Generated: Tue Dec 03 16:21:40 EST 2019 7 | 8 | # DO NOT MODIFY THIS FILE 9 | # 10 | # Changing this file will have subtle consequences 11 | # which will almost certainly lead to a nonfunctioning 12 | # system. If you do modify this file, be aware that your 13 | # changes will be overwritten and lost when this file 14 | # is generated again. 15 | # 16 | # DO NOT MODIFY THIS FILE 17 | 18 | # License Agreement 19 | # 20 | # Copyright (c) 2008 21 | # Altera Corporation, San Jose, California, USA. 22 | # All rights reserved. 23 | # 24 | # Permission is hereby granted, free of charge, to any person obtaining a 25 | # copy of this software and associated documentation files (the "Software"), 26 | # to deal in the Software without restriction, including without limitation 27 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, 28 | # and/or sell copies of the Software, and to permit persons to whom the 29 | # Software is furnished to do so, subject to the following conditions: 30 | # 31 | # The above copyright notice and this permission notice shall be included in 32 | # all copies or substantial portions of the Software. 33 | # 34 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 35 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 36 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 37 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 38 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 | # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 40 | # DEALINGS IN THE SOFTWARE. 41 | # 42 | # This agreement shall be governed in all respects by the laws of the State 43 | # of California and by the laws of the United States of America. 44 | 45 | # Define memory regions for each memory connected to the CPU. 46 | # The cache attribute is specified which improves GDB performance 47 | # by allowing GDB to cache memory contents on the host. 48 | 49 | # new_sdram_controller_0 50 | memory 0x0 0x8000000 cache 51 | 52 | # generic_tristate_controller_0 53 | memory 0x8800000 0x9000000 cache 54 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/memory.gdb: -------------------------------------------------------------------------------- 1 | # memory.gdb - GDB memory region definitions 2 | # 3 | # Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'nios_system' 4 | # SOPC Builder design path: ../../nios_system.sopcinfo 5 | # 6 | # Generated: Thu Dec 05 21:37:03 EST 2019 7 | 8 | # DO NOT MODIFY THIS FILE 9 | # 10 | # Changing this file will have subtle consequences 11 | # which will almost certainly lead to a nonfunctioning 12 | # system. If you do modify this file, be aware that your 13 | # changes will be overwritten and lost when this file 14 | # is generated again. 15 | # 16 | # DO NOT MODIFY THIS FILE 17 | 18 | # License Agreement 19 | # 20 | # Copyright (c) 2008 21 | # Altera Corporation, San Jose, California, USA. 22 | # All rights reserved. 23 | # 24 | # Permission is hereby granted, free of charge, to any person obtaining a 25 | # copy of this software and associated documentation files (the "Software"), 26 | # to deal in the Software without restriction, including without limitation 27 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, 28 | # and/or sell copies of the Software, and to permit persons to whom the 29 | # Software is furnished to do so, subject to the following conditions: 30 | # 31 | # The above copyright notice and this permission notice shall be included in 32 | # all copies or substantial portions of the Software. 33 | # 34 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 35 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 36 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 37 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 38 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 | # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 40 | # DEALINGS IN THE SOFTWARE. 41 | # 42 | # This agreement shall be governed in all respects by the laws of the State 43 | # of California and by the laws of the United States of America. 44 | 45 | # Define memory regions for each memory connected to the CPU. 46 | # The cache attribute is specified which improves GDB performance 47 | # by allowing GDB to cache memory contents on the host. 48 | 49 | # new_sdram_controller_0 50 | memory 0x0 0x8000000 cache 51 | 52 | # generic_tristate_controller_0 53 | memory 0x8800000 0x9000000 cache 54 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/nios2_qsys_0_custom_instruction_master_comb_xconnect.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE nios2_qsys_0_custom_instruction_master_comb_xconnect ./../libraries/nios2_qsys_0_custom_instruction_master_comb_xconnect/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent ./../libraries/video_pixel_buffer_dma_0_avalon_pixel_dma_master_agent/ 20 | -------------------------------------------------------------------------------- /Custom-Hardware-Blocks/datapath_tb.sv: -------------------------------------------------------------------------------- 1 | /************************************************************* 2 | * Datapath Testbench * 3 | * ECE 69500R SoC Architecture * 4 | * Simple Neural Network Accelerator * 5 | *************************************************************/ 6 | 7 | `timescale 1 ns / 1 ns 8 | 9 | module datapath_tb(); 10 | 11 | reg clk; 12 | reg n_rst; 13 | 14 | wire [31:0] A; 15 | wire [31:0] B; 16 | wire [31:0] AddO; 17 | wire [31:0] MulO; 18 | 19 | datapath DATAPATH (); 20 | 21 | fp_test testAdd 22 | ( 23 | .A(A), .B(B), .AddO(AddO), .MulO(MulO), .clk(clk), .n_rst(n_rst) 24 | ); 25 | 26 | initial begin 27 | $display( "Starting testbench" ); 28 | clk = 0; 29 | n_rst = 0; 30 | #100 31 | n_rst = 1; 32 | end 33 | 34 | always #5 clk = ~clk; 35 | 36 | endmodule // fp_tb 37 | 38 | program fp_test ( 39 | input logic clk, 40 | input logic n_rst, 41 | output logic [31:0] A, 42 | output logic [31:0] B, 43 | input logic [31:0] AddO, 44 | input logic [31:0] MulO 45 | ); 46 | 47 | // Wires and Registers 48 | 49 | bit [31:0] vectorA; 50 | bit [31:0] vectorB; 51 | bit [31:0] vectorAdd; 52 | bit [31:0] vectorMul; 53 | 54 | real realA; 55 | real realB; 56 | real realAdd; 57 | real realMul; 58 | 59 | 60 | task automatic genRands; 61 | begin 62 | vectorA = $random(); 63 | realA = $bitstoshortreal( vectorA ); 64 | 65 | vectorB = $random(); 66 | realB = $bitstoshortreal( vectorB ); 67 | 68 | realAdd = realA + realB; 69 | vectorAdd = $shortrealtobits( realAdd ); 70 | 71 | realMul = realA * realB; 72 | vectorMul = $shortrealtobits( realMul ); 73 | end 74 | endtask //automatic 75 | 76 | initial begin 77 | forever begin 78 | genRands(); 79 | #1; 80 | A = vectorA; 81 | B = vectorB; 82 | #5; 83 | if ( AddO != vectorAdd ) begin 84 | $display( "Add Mismatch : %08X + %08X = %08X --> %08X", vectorA, vectorB, vectorAdd, AddO ); 85 | end 86 | else begin 87 | //$display( "Add Match : %08X + %08X = %08X = %08X", vectorA, vectorB, vectorAdd, AddO ); 88 | end 89 | if ( MulO != vectorMul ) begin 90 | $display( "Mul Mismatch : %08X x %08X = %08X --> %08X", vectorA, vectorB, vectorMul, MulO ); 91 | end 92 | else begin 93 | //$display( "Mul Match : %08X x %08X = %08X = %08X", vectorA, vectorB, vectorMul, MulO ); 94 | end 95 | #4; 96 | end 97 | end 98 | 99 | endprogram 100 | -------------------------------------------------------------------------------- /Custom-Hardware-Blocks/fp_tb.sv: -------------------------------------------------------------------------------- 1 | /************************************************************* 2 | * Floating Point Testbench * 3 | * ECE 69500R SoC Architecture * 4 | * Simple Neural Network Accelerator * 5 | *************************************************************/ 6 | 7 | `timescale 1 ns / 1 ns 8 | 9 | module fp_tb(); 10 | 11 | reg clk; 12 | reg n_rst; 13 | 14 | wire [31:0] A; 15 | wire [31:0] B; 16 | wire [31:0] AddO; 17 | wire [31:0] MulO; 18 | 19 | fp_adder add 20 | ( 21 | .dataa(A), .datab(B), .result(AddO) 22 | ); 23 | 24 | fp_multiplier mul 25 | ( 26 | .dataa(A), .datab(B), .result(MulO) 27 | ); 28 | 29 | fp_test testAdd 30 | ( 31 | .A(A), .B(B), .AddO(AddO), .MulO(MulO), .clk(clk), .n_rst(n_rst) 32 | ); 33 | 34 | initial begin 35 | $display( "Starting testbench" ); 36 | clk = 0; 37 | n_rst = 0; 38 | #100 39 | n_rst = 1; 40 | end 41 | 42 | always #5 clk = ~clk; 43 | 44 | endmodule // fp_tb 45 | 46 | program fp_test ( 47 | input logic clk, 48 | input logic n_rst, 49 | output logic [31:0] A, 50 | output logic [31:0] B, 51 | input logic [31:0] AddO, 52 | input logic [31:0] MulO 53 | ); 54 | 55 | // Wires and Registers 56 | 57 | bit [31:0] vectorA; 58 | bit [31:0] vectorB; 59 | bit [31:0] vectorAdd; 60 | bit [31:0] vectorMul; 61 | 62 | real realA; 63 | real realB; 64 | real realAdd; 65 | real realMul; 66 | 67 | 68 | task automatic genRands; 69 | begin 70 | vectorA = $random(); 71 | realA = $bitstoshortreal( vectorA ); 72 | 73 | vectorB = $random(); 74 | realB = $bitstoshortreal( vectorB ); 75 | 76 | realAdd = realA + realB; 77 | vectorAdd = $shortrealtobits( realAdd ); 78 | 79 | realMul = realA * realB; 80 | vectorMul = $shortrealtobits( realMul ); 81 | end 82 | endtask //automatic 83 | 84 | initial begin 85 | forever begin 86 | genRands(); 87 | #1; 88 | A = vectorA; 89 | B = vectorB; 90 | #5; 91 | if ( AddO != vectorAdd ) begin 92 | $display( "Add Mismatch : %08X + %08X = %08X --> %08X", vectorA, vectorB, vectorAdd, AddO ); 93 | end 94 | else begin 95 | //$display( "Add Match : %08X + %08X = %08X = %08X", vectorA, vectorB, vectorAdd, AddO ); 96 | end 97 | if ( MulO != vectorMul ) begin 98 | $display( "Mul Mismatch : %08X x %08X = %08X --> %08X", vectorA, vectorB, vectorMul, MulO ); 99 | end 100 | else begin 101 | //$display( "Mul Match : %08X x %08X = %08X = %08X", vectorA, vectorB, vectorMul, MulO ); 102 | end 103 | #4; 104 | end 105 | end 106 | 107 | endprogram 108 | -------------------------------------------------------------------------------- /Accelerator-Design/nios_system/testbench/cadence/cds_libs/video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/ 19 | DEFINE video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator ./../libraries/video_pixel_buffer_dma_0_avalon_pixel_dma_master_translator/ 20 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_CNN_Software_bsp/HAL/inc/sys/alt_irq_entry.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * * 3 | * License Agreement * 4 | * * 5 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * 6 | * All rights reserved. * 7 | * * 8 | * Permission is hereby granted, free of charge, to any person obtaining a * 9 | * copy of this software and associated documentation files (the "Software"), * 10 | * to deal in the Software without restriction, including without limitation * 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 12 | * and/or sell copies of the Software, and to permit persons to whom the * 13 | * Software is furnished to do so, subject to the following conditions: * 14 | * * 15 | * The above copyright notice and this permission notice shall be included in * 16 | * all copies or substantial portions of the Software. * 17 | * * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 24 | * DEALINGS IN THE SOFTWARE. * 25 | * * 26 | * This agreement shall be governed in all respects by the laws of the State * 27 | * of California and by the laws of the United States of America. * 28 | * * 29 | ******************************************************************************/ 30 | 31 | /* 32 | * This file pulls in the IRQ entry assembler and C code, which is only 33 | * required if there are any interruptes in the system. 34 | */ 35 | 36 | __asm__( "\n\t.globl alt_irq_entry" ); 37 | 38 | __asm__( "\n\t.globl alt_irq_handler" ); 39 | 40 | -------------------------------------------------------------------------------- /Accelerator-Design/software/MNIST_MLP_Software_bsp/HAL/inc/sys/alt_irq_entry.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * * 3 | * License Agreement * 4 | * * 5 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * 6 | * All rights reserved. * 7 | * * 8 | * Permission is hereby granted, free of charge, to any person obtaining a * 9 | * copy of this software and associated documentation files (the "Software"), * 10 | * to deal in the Software without restriction, including without limitation * 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 12 | * and/or sell copies of the Software, and to permit persons to whom the * 13 | * Software is furnished to do so, subject to the following conditions: * 14 | * * 15 | * The above copyright notice and this permission notice shall be included in * 16 | * all copies or substantial portions of the Software. * 17 | * * 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 24 | * DEALINGS IN THE SOFTWARE. * 25 | * * 26 | * This agreement shall be governed in all respects by the laws of the State * 27 | * of California and by the laws of the United States of America. * 28 | * * 29 | ******************************************************************************/ 30 | 31 | /* 32 | * This file pulls in the IRQ entry assembler and C code, which is only 33 | * required if there are any interruptes in the system. 34 | */ 35 | 36 | __asm__( "\n\t.globl alt_irq_entry" ); 37 | 38 | __asm__( "\n\t.globl alt_irq_handler" ); 39 | 40 | --------------------------------------------------------------------------------