├── Python Code ├── Binfield.ipynb ├── Binfield_final.ipynb ├── Curve_Calculation.ipynb ├── ECDSA.ipynb ├── Ecludian_Algorithm.ipynb ├── Karatsuba_generator_SAA_lower.ipynb ├── Montgomerry_Multiplication.ipynb ├── Multiplication_Moulus.ipynb ├── Point_Addition.ipynb ├── baumer_chain.ipynb ├── encryption.ipynb ├── itoha_tsuiji.ipynb ├── karatsuba.ipynb ├── mul_576_test.ipynb ├── multi_nump.ipynb ├── plot_matlib.ipynb └── readme.md ├── README.md └── Verilog Code ├── doc ├── .ipynb_checkpoints │ ├── Curve_Calculation-checkpoint.ipynb │ ├── ECDSA-checkpoint.ipynb │ └── ks_test-checkpoint.ipynb ├── Curve_Calculation.ipynb ├── ECDSA.ipynb └── ks_test.ipynb ├── hdl └── multipliers │ ├── LOOK_UP_table_module.v │ ├── LUT.v │ ├── Masking_Module.v │ ├── Outer_Ram_Module.v │ ├── Outer_Ram_interface.v │ ├── Ram_Interface_Module.v │ ├── Ram_data_swaping_module.v │ ├── Ram_interface_scalar_mul.v │ ├── Ram_module.v │ ├── Ram_module.v~ │ ├── Ram_module_scalar_mul.v │ ├── Ram_transfer.v │ ├── Ram_transfer_scalar_mul.v │ ├── Square_571.v │ ├── Xor_16_bit.v │ ├── Xor_192.v │ ├── Xor_256_module.v │ ├── Xor_module.v │ ├── Xor_new.v │ ├── Xor_new.v~ │ ├── dma_sample_code.v │ ├── ideal_module.v │ ├── interupt.v~ │ ├── inverse_itoha_tsuji_module.v │ ├── lower_bit_implementation.v │ ├── mul_64_module.v │ ├── multiplication_recursive_module.v │ ├── point_addition_module.v │ ├── point_double_module.v │ ├── redution_256.v │ ├── saa_ks_96.v~ │ ├── scalar_multiplication_module.v │ ├── sqr_slice_testing.v │ ├── state_machine_3.v │ ├── state_machine_inverse.v │ ├── state_machine_scalar_mul.v │ ├── state_machine_scalar_mul.v~ │ └── sync_96.v~ ├── readme.md └── testbench └── ks ├── Makefile ├── result.log ├── results.xml ├── sim_build └── sim.vvp ├── test_ks.py └── test_ks.pyc /Python Code/Curve_Calculation.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "metadata": { 3 | "name": "", 4 | "signature": "sha256:a4342b0c2ab58e438c5b2462f89c79c68399e7bb260fe7fff1fee2bfd6a4ab46" 5 | }, 6 | "nbformat": 3, 7 | "nbformat_minor": 0, 8 | "worksheets": [ 9 | { 10 | "cells": [ 11 | { 12 | "cell_type": "code", 13 | "collapsed": false, 14 | "input": [ 15 | "import numpy as np\n", 16 | "a=np.array([0,1,2,0,0,0,0,0,1])\n", 17 | "print a" 18 | ], 19 | "language": "python", 20 | "metadata": {}, 21 | "outputs": [ 22 | { 23 | "output_type": "stream", 24 | "stream": "stdout", 25 | "text": [ 26 | "[0 1 2 0 0 0 0 0 1]\n" 27 | ] 28 | } 29 | ], 30 | "prompt_number": 1 31 | }, 32 | { 33 | "cell_type": "code", 34 | "collapsed": false, 35 | "input": [ 36 | "import binascii\n", 37 | "import gmpy2\n", 38 | "import random\n", 39 | "def str2nparray( A):\n", 40 | " A = '0'*(8 - len(A)%8) + A\n", 41 | " A = binascii.unhexlify(A)\n", 42 | " A = np.fromstring(A[::-1], dtype='uint32') \n", 43 | " return A\n", 44 | "Polynomial1 = '020000000000000000000000000201'\n", 45 | "Polynomial2 = Polynomial1\n", 46 | "Polynomial1=str2nparray(Polynomial1)\n", 47 | "Curve_len=(len(Polynomial1)-1)*32+gmpy2.bit_length(int(Polynomial1[-1]))-1\n", 48 | "print Curve_len\n", 49 | "X='9d73616f35f4ab1407d73562c10f'\n", 50 | "Y='a52830277958ee84d1315ed31886'\n", 51 | "a='3088250ca6e7c7fe649ce85820f7'\n", 52 | "k=random.randint(1,Curve_len)\n", 53 | "print k" 54 | ], 55 | "language": "python", 56 | "metadata": {}, 57 | "outputs": [ 58 | { 59 | "output_type": "stream", 60 | "stream": "stdout", 61 | "text": [ 62 | "113\n", 63 | "43\n" 64 | ] 65 | } 66 | ], 67 | "prompt_number": 2 68 | }, 69 | { 70 | "cell_type": "code", 71 | "collapsed": false, 72 | "input": [ 73 | "import binascii\n", 74 | "import numpy as np\n", 75 | "import gmpy2\n", 76 | "\n", 77 | "np.set_printoptions(formatter={'int':hex})\n", 78 | "\n", 79 | "def remove_0( A):\n", 80 | " while A[0] == 0:\n", 81 | " if len(A) == 1:\n", 82 | " break\n", 83 | " A = A[1:]\n", 84 | " return A\n", 85 | "def str2nparray( A):\n", 86 | " A = '0'*(8 - len(A)%8) + A\n", 87 | " A = binascii.unhexlify(A)\n", 88 | " A = np.fromstring(A[::-1], dtype='uint32') \n", 89 | " return A\n", 90 | "\n", 91 | " \n", 92 | "def nparray2str2( A):\n", 93 | " c = ''\n", 94 | " d = A.view('uint8')\n", 95 | " for i in d:\n", 96 | " c+=binascii.hexlify(i)\n", 97 | " return c \n", 98 | "Polynomial='20000000000000000000000000000000000000004000000000000000001'\n", 99 | "def Curve_Calculation(Polynomial): \n", 100 | " Curve_Polynomial=np.array([],dtype='uint8') \n", 101 | " Polynomial=str2nparray(Polynomial)\n", 102 | " Curve_len=(len(Polynomial)-1)*32+gmpy2.bit_length(int(Polynomial[-1]))-1\n", 103 | " print hex(Curve_len)\n", 104 | " D=Polynomial.view('uint8')[::-1]\n", 105 | " D=remove_0(D)\n", 106 | " position=np.nonzero(D)\n", 107 | " #print position\n", 108 | " position=position[0]\n", 109 | " #print len(position)\n", 110 | " secnd_chunk=0x00\n", 111 | " secnd_position=0x00\n", 112 | " frst_chunk=D[position[1]]\n", 113 | " frst_position=(position[1]/8)*8+7-(position[1]%8)\n", 114 | "\n", 115 | " if(len(position)==3):\n", 116 | " secnd_chunk=D[position[2]]\n", 117 | " secnd_position=(position[2]/8)*8+7-(position[2]%8)\n", 118 | " Curve_Polynomial=np.array([Curve_len,frst_position,frst_chunk,secnd_position,secnd_chunk],dtype='uint8')\n", 119 | " Curve_Polynomial=nparray2str2(Curve_Polynomial)\n", 120 | " print Curve_Polynomial\n", 121 | " return Curve_Polynomial" 122 | ], 123 | "language": "python", 124 | "metadata": {}, 125 | "outputs": [], 126 | "prompt_number": 15 127 | }, 128 | { 129 | "cell_type": "code", 130 | "collapsed": false, 131 | "input": [ 132 | "Polynomial = '80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000425'\n", 133 | "Curve_Calculation(Polynomial)" 134 | ], 135 | "language": "python", 136 | "metadata": {}, 137 | "outputs": [ 138 | { 139 | "output_type": "stream", 140 | "stream": "stdout", 141 | "text": [ 142 | "0x23b\n", 143 | "3b41044025\n" 144 | ] 145 | }, 146 | { 147 | "metadata": {}, 148 | "output_type": "pyout", 149 | "prompt_number": 17, 150 | "text": [ 151 | "'3b41044025'" 152 | ] 153 | } 154 | ], 155 | "prompt_number": 17 156 | }, 157 | { 158 | "cell_type": "code", 159 | "collapsed": false, 160 | "input": [ 161 | "import asyncio\n", 162 | "\n", 163 | "@asyncio.coroutine\n", 164 | "def factorial(name, number):\n", 165 | " f = 1\n", 166 | " for i in range(2, number+1):\n", 167 | " print(\"Task %s: Compute factorial(%s)...\" % (name, i))\n", 168 | " f *= i\n", 169 | " print(\"Task %s: factorial(%s) = %s\" % (name, number, f))\n", 170 | "\n", 171 | "loop = asyncio.get_event_loop()\n", 172 | "tasks = [\n", 173 | " asyncio.async(factorial(\"A\", 2)),\n", 174 | " asyncio.async(factorial(\"B\", 3)),\n", 175 | " asyncio.async(factorial(\"C\", 4))]\n", 176 | "loop.run_until_complete(asyncio.wait(tasks))\n", 177 | "loop.close()" 178 | ], 179 | "language": "python", 180 | "metadata": {}, 181 | "outputs": [ 182 | { 183 | "ename": "ImportError", 184 | "evalue": "No module named asyncio", 185 | "output_type": "pyerr", 186 | "traceback": [ 187 | "\u001b[1;31m---------------------------------------------------------------------------\u001b[0m\n\u001b[1;31mImportError\u001b[0m Traceback (most recent call last)", 188 | "\u001b[1;32m\u001b[0m in \u001b[0;36m\u001b[1;34m()\u001b[0m\n\u001b[1;32m----> 1\u001b[1;33m \u001b[1;32mimport\u001b[0m \u001b[0masyncio\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0m\u001b[0;32m 2\u001b[0m \u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0;32m 3\u001b[0m \u001b[1;33m@\u001b[0m\u001b[0masyncio\u001b[0m\u001b[1;33m.\u001b[0m\u001b[0mcoroutine\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0;32m 4\u001b[0m \u001b[1;32mdef\u001b[0m \u001b[0mfactorial\u001b[0m\u001b[1;33m(\u001b[0m\u001b[0mname\u001b[0m\u001b[1;33m,\u001b[0m \u001b[0mnumber\u001b[0m\u001b[1;33m)\u001b[0m\u001b[1;33m:\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0;32m 5\u001b[0m \u001b[0mf\u001b[0m \u001b[1;33m=\u001b[0m \u001b[1;36m1\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n", 189 | "\u001b[1;31mImportError\u001b[0m: No module named asyncio" 190 | ] 191 | } 192 | ], 193 | "prompt_number": 23 194 | }, 195 | { 196 | "cell_type": "code", 197 | "collapsed": false, 198 | "input": [ 199 | "hex(571)" 200 | ], 201 | "language": "python", 202 | "metadata": {}, 203 | "outputs": [ 204 | { 205 | "metadata": {}, 206 | "output_type": "pyout", 207 | "prompt_number": 12, 208 | "text": [ 209 | "'0x23b'" 210 | ] 211 | } 212 | ], 213 | "prompt_number": 12 214 | }, 215 | { 216 | "cell_type": "code", 217 | "collapsed": false, 218 | "input": [ 219 | "A='0800000000000000 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000425'" 220 | ], 221 | "language": "python", 222 | "metadata": {}, 223 | "outputs": [ 224 | { 225 | "ename": "SyntaxError", 226 | "evalue": "invalid syntax (, line 2)", 227 | "output_type": "pyerr", 228 | "traceback": [ 229 | "\u001b[1;36m File \u001b[1;32m\"\"\u001b[1;36m, line \u001b[1;32m2\u001b[0m\n\u001b[1;33m A(1:0)\u001b[0m\n\u001b[1;37m ^\u001b[0m\n\u001b[1;31mSyntaxError\u001b[0m\u001b[1;31m:\u001b[0m invalid syntax\n" 230 | ] 231 | } 232 | ], 233 | "prompt_number": 10 234 | }, 235 | { 236 | "cell_type": "code", 237 | "collapsed": false, 238 | "input": [], 239 | "language": "python", 240 | "metadata": {}, 241 | "outputs": [] 242 | } 243 | ], 244 | "metadata": {} 245 | } 246 | ] 247 | } -------------------------------------------------------------------------------- /Python Code/Karatsuba_generator_SAA_lower.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "metadata": { 3 | "name": "", 4 | "signature": "sha256:ed81b07ea4756c59b400c5f83cebce613d0d862975e928030941997b8acbc8a9" 5 | }, 6 | "nbformat": 3, 7 | "nbformat_minor": 0, 8 | "worksheets": [ 9 | { 10 | "cells": [ 11 | { 12 | "cell_type": "code", 13 | "collapsed": false, 14 | "input": [ 15 | "def shift(n):\n", 16 | " print \"module\"+\" \"+\"mul_\"+str(n)+\"(\"\n", 17 | " print \" \"+\"input[\"+str(n-1)+\":0] mul_A,\"\n", 18 | " print \" \"+\"input[\"+str(n-1)+\":0] mul_B,\"\n", 19 | " print \" \"+\"input[\"+str(2*n-1)+\":0] mul_out\"\n", 20 | " print \" \"+\");\"\n", 21 | " print \" wire [\"+str(2*n-1)+\":0]\",\n", 22 | " for i in range(0,n):\n", 23 | " print \"d\"+str(i),\n", 24 | " if(i!=(n-1)):\n", 25 | " print \",\",\n", 26 | " print \";\"\n", 27 | " print\n", 28 | " print \" assign d[\"+str(n-1)+\":0] = mul_A[\"+str(n-1)+\":0];\"\n", 29 | " print \" assign d[\"+str(2*n-1)+\":\"+str(n)+\"]=\"+str(n)+\"'b0;\"\n", 30 | " print \n", 31 | " print \" assign d1 = mul_B[0]?d:\"+str(n)+\"'b0;\"\n", 32 | " for i in range(1,(n-1)):\n", 33 | " print \" assign d\"+str(i+1)+\" = mul_B[\"+str(i)+\"]?d\"+str(i)+\"^d<<\"+str(i)+\":d\"+str(i)+\";\"\n", 34 | " print\n", 35 | " print \" assign mul_out[\"+str(2*n-1)+\":0] = mul_B[\"+str(n-1)+\"]?d\"+str(n-1)+\"^d<<\"+str(n-1)+\":d\"+str(n-1)+\";\"\n", 36 | " print\n", 37 | " print \"endmodule\"\n", 38 | " " 39 | ], 40 | "language": "python", 41 | "metadata": {}, 42 | "outputs": [], 43 | "prompt_number": 3 44 | }, 45 | { 46 | "cell_type": "code", 47 | "collapsed": false, 48 | "input": [ 49 | "def Recursive(n):\n", 50 | " print \"mul_\"+str(n)+\"_module(\"\n", 51 | " print \" input mul_A[\"+str(n-1)+\":0],\"\n", 52 | " print \" input mul_B[\"+str(n-1)+\":0],\"\n", 53 | " print \" output mul_out_\"+str(n)+\"[\"+str(2*n-1)+\":0]\"\n", 54 | " print \" );\"\n", 55 | " print\n", 56 | " print \" wire[\"+str(n-1)+\":0] d0,d1,d3;\"\n", 57 | " if (n%2 == 0):\n", 58 | " print \" wire[\"+str(n-1)+\":0] d2\"\n", 59 | " else:\n", 60 | " print \" wire[\"+str(n-2)+\":0] d2;\"\n", 61 | "\n", 62 | " print\n", 63 | " #code for a0b0\n", 64 | " if (n%2 == 0):\n", 65 | " print \" mul_\"+str(n/2)+\"_module mul_0(\"\n", 66 | " print \" .mul_A(mul_A[\"+str(n/2-1)+\":0]),\"\n", 67 | " print \" .mul_B(mul_B[\"+str(n/2-1)+\":0]),\"\n", 68 | " print \" .mul_out(d0)\"\n", 69 | " print \" );\"\n", 70 | " else:\n", 71 | " print \" mul_\"+str(n/2+1)+\"_module mul_0(\"\n", 72 | " print \" .mul_A(mul_A[\"+str(n/2)+\":0]),\"\n", 73 | " print \" .mul_B(mul_B[\"+str(n/2)+\":0]),\"\n", 74 | " print \" .mul_out(d0)\"\n", 75 | " print \" );\"\n", 76 | " print\n", 77 | "\n", 78 | " #code for a0^a1,b0^b1\n", 79 | " if (n%2 == 0):\n", 80 | " print \" mul_\"+str(n/2)+\"_module mul_1(\"\n", 81 | " print \" .mul_A(mul_A[\"+str(n/2-1)+\":0]^mul_A[\"+str(n-1)+\":\"+str(n/2)+\"]),\"\n", 82 | " print \" .mul_B(mul_B[\"+str(n/2-1)+\":0]^mul_B[\"+str(n-1)+\":\"+str(n/2)+\"]),\"\n", 83 | " print \" .mul_out(d1)\"\n", 84 | " print \" );\"\n", 85 | "\n", 86 | " else:\n", 87 | " print \" mul_\"+str(n/2+1)+\"_module mul_1(\"\n", 88 | " print \" .mul_A({mul_A[\"+str(n/2)+\"],mul_A[\"+str(n/2-1)+\":0]^mul_A[\"+str(n-1)+\":\"+str(n/2+1)+\"])},\"\n", 89 | " print \" .mul_B({mul_B[\"+str(n/2)+\"],mul_B[\"+str(n/2-1)+\":0]^mul_B[\"+str(n-1)+\":\"+str(n/2+1)+\"])},\"\n", 90 | " print \" .mul_out(d1)\"\n", 91 | " print \" );\"\n", 92 | "\n", 93 | " print\n", 94 | "\n", 95 | " #code for a1b1\n", 96 | " if (n%2 == 0):\n", 97 | " print \" mul_\"+str(n/2)+\"_module mul_2(\"\n", 98 | " print \" .mul_A(mul_A[\"+str(n-1)+\":\"+str(n/2)+\"]),\"\n", 99 | " print \" .mul_B(mul_B[\"+str(n-1)+\":\"+str(n/2)+\"]),\"\n", 100 | " print \" .mul_out(d2)\"\n", 101 | " print \" );\"\n", 102 | "\n", 103 | " else:\n", 104 | " print \" mul_\"+str(n/2)+\"_module mul_2(\"\n", 105 | " print \" .mul_A(mul_A[\"+str(n-1)+\":\"+str(n/2+1)+\"]),\"\n", 106 | " print \" .mul_B(mul_B[\"+str(n-1)+\":\"+str(n/2+1)+\"]),\"\n", 107 | " print \" .mul_out(d2)\"\n", 108 | " print \" );\"\n", 109 | "\n", 110 | " print\n", 111 | " print \" assign d3 = d2 ^ d1 ^ d0;\" \n", 112 | " print\n", 113 | " if (n%2 == 0):\n", 114 | " print \" assign mul_out_\"+str(n)+\"= {d2[\"+str(n-1)+\":\"+str(n/2)+\"],d2[\"+str(n/2-1)+\":0]^d3[\"+str(n-1)+\":\"+str(n/2)+\"],d0[\"+str(n-1)+\":\"+str(n/2)+\"]^d3[\"+str(n/2-1)+\":0],d0[\"+str(n/2-1)+\":0]};\"\n", 115 | " else:\n", 116 | " print \" assign mul_out_\"+str(n)+\"= {d2[\"+str(n-2)+\":\"+str(n/2)+\"],d3[\"+str(n-1)+\"],d2[\"+str(n/2-1)+\":0]^d3[\"+str(n-2)+\":\"+str(n/2+1)+\"],d0[\"+str(n)+\":\"+str(n/2+1)+\"]^d3[\"+str(n/2)+\":0],d0[\"+str(n/2)+\":0]};\"\n", 117 | "\n", 118 | " print\n", 119 | " print \"endmodule\"\n", 120 | " return;" 121 | ], 122 | "language": "python", 123 | "metadata": {}, 124 | "outputs": [], 125 | "prompt_number": 4 126 | }, 127 | { 128 | "cell_type": "code", 129 | "collapsed": false, 130 | "input": [ 131 | "print \"ENTER NUMBER BITS FOR WHICH MULTIPLICATION MODULE HAS TO BE GENERATED:\"\n", 132 | "n=input()\n", 133 | "\n", 134 | "a=[n]\n", 135 | "b=Karatsuba_array(n,a)\n", 136 | "for i in range(len(a)):\n", 137 | " for j in range(len(a)):\n", 138 | " if(a[i]>a[j]):\n", 139 | " t=a[i]\n", 140 | " a[i]=a[j]\n", 141 | " a[j]=t\n", 142 | "b=[0]\n", 143 | "k=0;\n", 144 | "for i in range(len(a)):\n", 145 | " if(b[k]!=a[i]):\n", 146 | " k=k+1\n", 147 | " b.append(a[i])\n", 148 | "for i in b:\n", 149 | " if(i):\n", 150 | " if(i>15):\n", 151 | " Recursive(i)\n", 152 | " else:\n", 153 | " shift(i)\n", 154 | " " 155 | ], 156 | "language": "python", 157 | "metadata": {}, 158 | "outputs": [] 159 | }, 160 | { 161 | "cell_type": "code", 162 | "collapsed": false, 163 | "input": [ 164 | "array=[1,2,3]\n", 165 | "array.append(3)\n", 166 | "print array" 167 | ], 168 | "language": "python", 169 | "metadata": {}, 170 | "outputs": [] 171 | }, 172 | { 173 | "cell_type": "code", 174 | "collapsed": false, 175 | "input": [ 176 | "if(95%2==1 and 95>15):\n", 177 | " print \"hello\"" 178 | ], 179 | "language": "python", 180 | "metadata": {}, 181 | "outputs": [ 182 | { 183 | "output_type": "stream", 184 | "stream": "stdout", 185 | "text": [ 186 | "hello\n" 187 | ] 188 | } 189 | ], 190 | "prompt_number": 29 191 | }, 192 | { 193 | "cell_type": "code", 194 | "collapsed": false, 195 | "input": [ 196 | "from sets import Set\n", 197 | "array=[1,2,3,4,5,6,6,7,6,5]\n", 198 | "b=Set(array)\n", 199 | "print b" 200 | ], 201 | "language": "python", 202 | "metadata": {}, 203 | "outputs": [ 204 | { 205 | "output_type": "stream", 206 | "stream": "stdout", 207 | "text": [ 208 | "Set([1, 2, 3, 4, 5, 6, 7])\n" 209 | ] 210 | } 211 | ], 212 | "prompt_number": 17 213 | }, 214 | { 215 | "cell_type": "code", 216 | "collapsed": false, 217 | "input": [ 218 | "range(10,-1,-1)" 219 | ], 220 | "language": "python", 221 | "metadata": {}, 222 | "outputs": [ 223 | { 224 | "metadata": {}, 225 | "output_type": "pyout", 226 | "prompt_number": 33, 227 | "text": [ 228 | "[10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]" 229 | ] 230 | } 231 | ], 232 | "prompt_number": 33 233 | }, 234 | { 235 | "cell_type": "code", 236 | "collapsed": false, 237 | "input": [], 238 | "language": "python", 239 | "metadata": {}, 240 | "outputs": [] 241 | } 242 | ], 243 | "metadata": {} 244 | } 245 | ] 246 | } -------------------------------------------------------------------------------- /Python Code/itoha_tsuiji.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "metadata": { 3 | "name": "", 4 | "signature": "sha256:4910b88cd1af589d9f9a0318024bca504726eebe508c43607764dfb88cf84fdc" 5 | }, 6 | "nbformat": 3, 7 | "nbformat_minor": 0, 8 | "worksheets": [ 9 | { 10 | "cells": [ 11 | { 12 | "cell_type": "code", 13 | "collapsed": false, 14 | "input": [ 15 | "import binascii\n", 16 | "import gmpy2\n", 17 | "import numpy as np\n", 18 | "np.set_printoptions(formatter={'int':hex})\n", 19 | "class Binfield:\n", 20 | " def __init__(self, Polynomial):\n", 21 | " \n", 22 | " Polynomial = binascii.unhexlify(Polynomial)\n", 23 | " Polynomial = np.fromstring(Polynomial, dtype='uint16')\n", 24 | "\n", 25 | " self.Polynomial = Polynomial\n", 26 | " MUL_LUT = []\n", 27 | " LUT = np.array([0x00, 0x01, 0x4, 0x05, 0x10, 0x11, 0x14, 0x15, 0x40, 0x41, 0x44, 0x45, 0x50, 0x51, 0x54, 0x55])\n", 28 | " a = np.arange(256)\n", 29 | " b = [ LUT[a & 0x0F], LUT[(a & 0xF0)>> 4]]\n", 30 | " c = []\n", 31 | " for i in range(0,256):\n", 32 | " a = (b[1][i] << 8) | b[0][i] \n", 33 | " c.append(a)\n", 34 | " self.gen_mod_table()\n", 35 | " self.LUT8 = np.array(c, dtype='uint16')\n", 36 | " \n", 37 | " self.MUL_LUT = np.array([0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b1,\n", 38 | " 0b10,0b11,0b100,0b101,0b110,0b111,0b1000,0b1001,0b1010,0b1011,0b1100,\n", 39 | " 0b1101,0b1110,0b1111,0b0,0b10,0b100,0b110,0b1000,0b1010,0b1100,0b1110,\n", 40 | " 0b10000,0b10010,0b10100,0b10110,0b11000,0b11010,0b11100,0b11110,0b0,0b11,\n", 41 | " 0b110,0b101,0b1100,0b1111,0b1010,0b1001,0b11000,0b11011,0b11110,0b11101,\n", 42 | " 0b10100,0b10111,0b10010,0b10001,0b0,0b100,0b1000,0b1100,0b10000,0b10100,\n", 43 | " 0b11000,0b11100,0b100000,0b100100,0b101000,0b101100,0b110000,0b110100,\n", 44 | " 0b111000,0b111100,0b0,0b101,0b1010,0b1111,0b10100,0b10001,0b11110,0b11011,\n", 45 | " 0b101000,0b101101,0b100010,0b100111,0b111100,0b111001,0b110110,0b110011,\n", 46 | " 0b0,0b110,0b1100,0b1010,0b11000,0b11110,0b10100,0b10010,0b110000,0b110110,\n", 47 | " 0b111100,0b111010,0b101000,0b101110,0b100100,0b100010,0b0,0b111,0b1110,\n", 48 | " 0b1001,0b11100,0b11011,0b10010,0b10101,0b111000,0b111111,0b110110,0b110001,\n", 49 | " 0b100100,0b100011,0b101010,0b101101,0b0,0b1000,0b10000,0b11000,0b100000,\n", 50 | " 0b101000,0b110000,0b111000,0b1000000,0b1001000,0b1010000,0b1011000,\n", 51 | " 0b1100000,0b1101000,0b1110000,0b1111000,0b0,0b1001,0b10010,0b11011,\n", 52 | " 0b100100,0b101101,0b110110,0b111111,0b1001000,0b1000001,0b1011010,\n", 53 | " 0b1010011,0b1101100,0b1100101,0b1111110,0b1110111,0b0,0b1010,0b10100,\n", 54 | " 0b11110,0b101000,0b100010,0b111100,0b110110,0b1010000,0b1011010,0b1000100,\n", 55 | " 0b1001110,0b1111000,0b1110010,0b1101100,0b1100110,0b0,0b1011,0b10110,\n", 56 | " 0b11101,0b101100,0b100111,0b111010,0b110001,0b1011000,0b1010011,0b1001110,\n", 57 | " 0b1000101,0b1110100,0b1111111,0b1100010,0b1101001,0b0,0b1100,0b11000,\n", 58 | " 0b10100,0b110000,0b111100,0b101000,0b100100,0b1100000,0b1101100,0b1111000,\n", 59 | " 0b1110100,0b1010000,0b1011100,0b1001000,0b1000100,0b0,0b1101,0b11010,\n", 60 | " 0b10111,0b110100,0b111001,0b101110,0b100011,0b1101000,0b1100101,0b1110010,\n", 61 | " 0b1111111,0b1011100,0b1010001,0b1000110,0b1001011,0b0,0b1110,0b11100,\n", 62 | " 0b10010,0b111000,0b110110,0b100100,0b101010,0b1110000,0b1111110,0b1101100,\n", 63 | " 0b1100010,0b1001000,0b1000110,0b1010100,0b1011010,0b0,0b1111,0b11110,\n", 64 | " 0b10001,0b111100,0b110011,0b100010,0b101101,0b1111000,0b1110111,0b1100110,\n", 65 | " 0b1101001,0b1000100,0b1001011,0b1011010,0b1010101])\n", 66 | " \n", 67 | " def mul_8_lut(self,a, b):\n", 68 | " a1 = (a&0xf0)>>4\n", 69 | " a0 = (a&0xf)\n", 70 | " b1 = (b&0xf0)>>4\n", 71 | " b0 = (b&0xf)\n", 72 | " d2 = self.MUL_LUT[a1<<4 | b1]\n", 73 | " d1 = self.MUL_LUT[a1<<4 | b0] ^ self.MUL_LUT[a0<<4 | b1]\n", 74 | " d0 = self.MUL_LUT[a0<<4 | b0]\n", 75 | "\n", 76 | " return d2<<8 ^ d1 <<4 ^ d0\n", 77 | " \n", 78 | " def mul_32 (self,a, b):\n", 79 | " a=np.array(a)\n", 80 | " b=np.array(b)\n", 81 | " a=a.view('uint8')\n", 82 | " b = b.view('uint8')\n", 83 | " a=a.tolist()\n", 84 | " b=b.tolist()\n", 85 | " a3=a[0]\n", 86 | " a2 = a[1]\n", 87 | " a1=a[2]\n", 88 | " a0 = a[3]\n", 89 | " b3=b[0]\n", 90 | " b2=b[1]\n", 91 | " b1=b[2]\n", 92 | " b0= b[3]\n", 93 | " phi1=self.mul_8_lut(a3,b3)^ self.mul_8_lut(a2,b2)\n", 94 | " phi2=self.mul_8_lut(a1,b1) ^ self.mul_8_lut(a0,b0)\n", 95 | " phi=phi1^phi2\n", 96 | " d6 = (self.mul_8_lut(a3,b3))\n", 97 | " d5 = (self.mul_8_lut(a3^a2, b3^b2)^phi1) \n", 98 | " d4 = (self.mul_8_lut(a3^a1, b3^b1))^(phi1)^(self.mul_8_lut(a1,b1))\n", 99 | " d3 = (self.mul_8_lut(a3^a0, b3^b0)^self.mul_8_lut(a2^a1, b2^b1)^phi) \n", 100 | " d2 = (self.mul_8_lut(a2^a0, b2^b0)^phi2^self.mul_8_lut(a2,b2))\n", 101 | " d1 = (self.mul_8_lut(a1^a0, b1^b0)^phi2) \n", 102 | " d0 = (self.mul_8_lut(a0,b0))\n", 103 | " \n", 104 | " d11=(d3&0x00ff)<<24 ^ d2<<16 ^ d1<<8 ^ d0\n", 105 | " d12=d6<<16 ^ d5<<8 ^ d4 ^(d3&0xff00)>>8\n", 106 | " \n", 107 | " d=np.array([(d12&0xff000000)>>24^(((d12&0xff0000)>>16)<<8)^(((d12&0xff00)>>8)<<16)^((d12&0xff)<<24) ,\n", 108 | " (d11&0xff000000)>>24^(((d11&0xff0000)>>16)<<8)^(((d11&0xff00)>>8)<<16)^((d11&0xff)<<24)])\n", 109 | "\n", 110 | " return d\n", 111 | " \n", 112 | " \n", 113 | " \n", 114 | " def string_hexa(self,a,b):\n", 115 | " a = binascii.unhexlify(a)\n", 116 | " a = np.fromstring(a, dtype='uint32')\n", 117 | " b = binascii.unhexlify(b)\n", 118 | " b = np.fromstring(b, dtype='uint32')\n", 119 | " \n", 120 | " return self.recursion(a,b) \n", 121 | " \n", 122 | " \n", 123 | " def recursion(self,a,b):\n", 124 | "\n", 125 | " \n", 126 | " l1=len(a)\n", 127 | " l2=len(b)\n", 128 | " \n", 129 | " l=max(l1,l2)\n", 130 | " \n", 131 | " \n", 132 | " if(l==1):\n", 133 | " return self.mul_32(a,b)\n", 134 | " else:\n", 135 | " d0=(self.recursion(a[l/2:l],b[l/2:l]))\n", 136 | " d1=(self.recursion(a[l/2:l],b[0:(l/2)])) ^ (self.recursion(a[0:(l/2)],b[l/2:l]))\n", 137 | " d2=(self.recursion(a[0:(l/2)],b[0:(l/2)]))\n", 138 | " l=len(a)\n", 139 | " for i in range(l):\n", 140 | " d2=np.append(d2,0)\n", 141 | " d0=np.insert(d0,0,0)\n", 142 | " for i in range(l/2):\n", 143 | " d1=np.append(d1,0)\n", 144 | " d1=np.insert(d1,0,0)\n", 145 | " d2=d2^d1^d0\n", 146 | " return d2\n", 147 | " \n", 148 | " \n", 149 | " def square (self, A):\n", 150 | " b = A.view('uint8')\n", 151 | " print b\n", 152 | " c = self.LUT8[b]\n", 153 | " d=c.view('uint32')\n", 154 | " while (d[-1] == 0):\n", 155 | " d = d[:-1] \n", 156 | " return d\n", 157 | " \n", 158 | " def bin_square (self, A):\n", 159 | " A = binascii.unhexlify(A)\n", 160 | " A = np.fromstring(A, dtype='uint32')\n", 161 | " print A#\n", 162 | " return self.square(A)\n", 163 | " \n", 164 | " def gen_mod_table(self):\n", 165 | " index = 0\n", 166 | " p = self.Polynomial.view('uint8')\n", 167 | " for i, v in enumerate(p):\n", 168 | " if v != 0:\n", 169 | " index = i\n", 170 | " break\n", 171 | " p = p[index:]\n", 172 | " f_bit_pos = gmpy2.bit_scan1(int(p[0])) \n", 173 | " length = (len(p)-1) * 8 + f_bit_pos\n", 174 | "\n", 175 | " \n", 176 | " p = np.array(p) #value\n", 177 | " first_byte = (p[-1]%p[0])<<7\n", 178 | " #print \"@@@@\"\n", 179 | " #print first_byte \n", 180 | " p = p/p[0]\n", 181 | " #print p\n", 182 | " pr = np.append(p, first_byte)\n", 183 | " print pr\n", 184 | " pl1 = (pr << 7) & 0xFF\n", 185 | " #print pl1\n", 186 | " pl2 = np.append(np.delete(pr >> 1, 0),0)\n", 187 | " #print pl2\n", 188 | " pl = pl1 ^ pl2\n", 189 | " #print \"@@@@\"\n", 190 | " print pl\n", 191 | " \n", 192 | " index = []\n", 193 | " for i, a in enumerate(zip(pl[1:], pr[1:])):\n", 194 | " #print a\n", 195 | " if ((a[0] != 0) | (a[1] != 0)):\n", 196 | " index.append(i+1)\n", 197 | " \n", 198 | " bit_poly_array = []\n", 199 | " for j in range(8):\n", 200 | " pp1 = (pr << j) & 0xFF\n", 201 | " pp2 = np.append(np.delete(pr >> 8-j, 0),0)\n", 202 | " shifted_plynomial = pp1 ^ pp2\n", 203 | " shifted_plynomial_selected_index = shifted_plynomial[index]\n", 204 | " bit_poly_array.append(shifted_plynomial_selected_index)\n", 205 | " \n", 206 | " Polly_table = []\n", 207 | " for i in range(256):\n", 208 | " val = np.zeros(len(bit_poly_array[0]), dtype='uint8')\n", 209 | " for j in range(8):\n", 210 | " if ((i >> j) & 0x1):\n", 211 | " val = val ^ bit_poly_array[j]\n", 212 | " Polly_table.append(val) \n", 213 | " \n", 214 | " self.Polly_table = Polly_table\n", 215 | " self.Polly_index = index\n", 216 | " self.Polly_length = length\n", 217 | " return 0\n", 218 | " \n", 219 | " def modulus (self, A):\n", 220 | " p = A.view('uint8')\n", 221 | " #print p\n", 222 | " byte_len = self.Polly_length/8\n", 223 | " bit_len = self.Polly_length%8\n", 224 | " print self.Polly_length\n", 225 | " print byte_len, bit_len\n", 226 | " for i,v in enumerate(p[0:-byte_len-1]):\n", 227 | " red_poly = self.Polly_table[v]\n", 228 | " #print red_poly\n", 229 | " for j,k in zip(red_poly, self.Polly_index):\n", 230 | " p[k+i] ^= j\n", 231 | " p[i] = 0\n", 232 | " \n", 233 | " p = p[-byte_len-1:]\n", 234 | " #print p\n", 235 | " r = p[0] & (gmpy2.bit_mask(bit_len) ^ 0xFF)\n", 236 | " red_poly = self.Polly_table[r]\n", 237 | " #print red_poly\n", 238 | " for j,k in zip(red_poly, self.Polly_index):\n", 239 | " if (k < len(p)):\n", 240 | " p[k] ^= j\n", 241 | " p[0] ^= r \n", 242 | " return p\n", 243 | " \n", 244 | " def bin_mod (self, A):\n", 245 | " A = binascii.unhexlify(A)\n", 246 | " A = np.fromstring(A, dtype='uint32') \n", 247 | " print A\n", 248 | " return self.modulus(A)\n", 249 | " \n", 250 | " \n", 251 | " \n", 252 | " def itoh_tsuji(self,A):\n", 253 | " A = binascii.unhexlify(A)\n", 254 | " A = np.fromstring(A, dtype='uint32')\n", 255 | " j=1\n", 256 | " res=[]\n", 257 | " #print A\n", 258 | " for i,v in enumerate(self.Polynomial):\n", 259 | " if(v!=0):\n", 260 | " index=i\n", 261 | " break\n", 262 | " Polynomial=self.Polynomial[index:]\n", 263 | " print Polynomial\n", 264 | " p=(Polynomial[0]&0x00ff)<<8 ^(Polynomial[0]&0xff00)>>8\n", 265 | " #f_bit_pos = gmpy2.bit_scan1(int(Polynomial[0])) \n", 266 | " l1=len(bin(p))-2\n", 267 | " l1=16-l1\n", 268 | " m=len(Polynomial)*16-l1-1\n", 269 | " #rint hex(p),m\n", 270 | " r=2**m-1\n", 271 | " r=r-1\n", 272 | " #print '**'\n", 273 | " #print r\n", 274 | " sq_array=[]\n", 275 | " \n", 276 | " #while(r%j>j):\n", 277 | " # j=j**2\n", 278 | " # sq=self.square(A)\n", 279 | " #sq_array.append(sq)\n", 280 | " # res=res.append(bin_mod(sq))\n", 281 | " #print j\n", 282 | " #r=r%j\n", 283 | " #j=1\n", 284 | " #while(r%j<<)\n", 285 | " return 0\n", 286 | " \n" 287 | ], 288 | "language": "python", 289 | "metadata": {}, 290 | "outputs": [], 291 | "prompt_number": 27 292 | }, 293 | { 294 | "cell_type": "code", 295 | "collapsed": false, 296 | "input": [ 297 | "field=Binfield('00020011')\n", 298 | "field.bin_square('00001011')" 299 | ], 300 | "language": "python", 301 | "metadata": {}, 302 | "outputs": [ 303 | { 304 | "output_type": "stream", 305 | "stream": "stdout", 306 | "text": [ 307 | "[0x1L 0x0L 0x8L 0x80L]\n", 308 | "[0x80L 0x4L 0x40L 0x0L]\n", 309 | "[0x11100000L]\n", 310 | "[0x0 0x0 0x10 0x11]\n" 311 | ] 312 | }, 313 | { 314 | "metadata": {}, 315 | "output_type": "pyout", 316 | "prompt_number": 28, 317 | "text": [ 318 | "array([0x0L, 0x1010100L], dtype=uint32)" 319 | ] 320 | } 321 | ], 322 | "prompt_number": 28 323 | }, 324 | { 325 | "cell_type": "heading", 326 | "level": 6, 327 | "metadata": {}, 328 | "source": [ 329 | "int(0x55)" 330 | ] 331 | } 332 | ], 333 | "metadata": {} 334 | } 335 | ] 336 | } -------------------------------------------------------------------------------- /Python Code/multi_nump.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "metadata": { 3 | "name": "", 4 | "signature": "sha256:511c1ac46172eb3bb348c92849d60893cc099afbaddd1925bd5ebeef000b2348" 5 | }, 6 | "nbformat": 3, 7 | "nbformat_minor": 0, 8 | "worksheets": [ 9 | { 10 | "cells": [ 11 | { 12 | "cell_type": "code", 13 | "collapsed": false, 14 | "input": [ 15 | "import binascii\n", 16 | "import numpy as np\n", 17 | "class Binfield:\n", 18 | " def __init__(self, Polynomial):\n", 19 | " Polynomial = binascii.unhexlify(Polynomial)\n", 20 | " Polynomial = np.fromstring(Polynomial, dtype='uint16')\n", 21 | "\n", 22 | " self.Polynomial = Polynomial\n", 23 | " MUL_LUT = []\n", 24 | " global i\n", 25 | " i=0\n", 26 | " \n", 27 | " self.MUL_LUT = np.array([0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b0,0b1,\n", 28 | " 0b10,0b11,0b100,0b101,0b110,0b111,0b1000,0b1001,0b1010,0b1011,0b1100,\n", 29 | " 0b1101,0b1110,0b1111,0b0,0b10,0b100,0b110,0b1000,0b1010,0b1100,0b1110,\n", 30 | " 0b10000,0b10010,0b10100,0b10110,0b11000,0b11010,0b11100,0b11110,0b0,0b11,\n", 31 | " 0b110,0b101,0b1100,0b1111,0b1010,0b1001,0b11000,0b11011,0b11110,0b11101,\n", 32 | " 0b10100,0b10111,0b10010,0b10001,0b0,0b100,0b1000,0b1100,0b10000,0b10100,\n", 33 | " 0b11000,0b11100,0b100000,0b100100,0b101000,0b101100,0b110000,0b110100,\n", 34 | " 0b111000,0b111100,0b0,0b101,0b1010,0b1111,0b10100,0b10001,0b11110,0b11011,\n", 35 | " 0b101000,0b101101,0b100010,0b100111,0b111100,0b111001,0b110110,0b110011,\n", 36 | " 0b0,0b110,0b1100,0b1010,0b11000,0b11110,0b10100,0b10010,0b110000,0b110110,\n", 37 | " 0b111100,0b111010,0b101000,0b101110,0b100100,0b100010,0b0,0b111,0b1110,\n", 38 | " 0b1001,0b11100,0b11011,0b10010,0b10101,0b111000,0b111111,0b110110,0b110001,\n", 39 | " 0b100100,0b100011,0b101010,0b101101,0b0,0b1000,0b10000,0b11000,0b100000,\n", 40 | " 0b101000,0b110000,0b111000,0b1000000,0b1001000,0b1010000,0b1011000,\n", 41 | " 0b1100000,0b1101000,0b1110000,0b1111000,0b0,0b1001,0b10010,0b11011,\n", 42 | " 0b100100,0b101101,0b110110,0b111111,0b1001000,0b1000001,0b1011010,\n", 43 | " 0b1010011,0b1101100,0b1100101,0b1111110,0b1110111,0b0,0b1010,0b10100,\n", 44 | " 0b11110,0b101000,0b100010,0b111100,0b110110,0b1010000,0b1011010,0b1000100,\n", 45 | " 0b1001110,0b1111000,0b1110010,0b1101100,0b1100110,0b0,0b1011,0b10110,\n", 46 | " 0b11101,0b101100,0b100111,0b111010,0b110001,0b1011000,0b1010011,0b1001110,\n", 47 | " 0b1000101,0b1110100,0b1111111,0b1100010,0b1101001,0b0,0b1100,0b11000,\n", 48 | " 0b10100,0b110000,0b111100,0b101000,0b100100,0b1100000,0b1101100,0b1111000,\n", 49 | " 0b1110100,0b1010000,0b1011100,0b1001000,0b1000100,0b0,0b1101,0b11010,\n", 50 | " 0b10111,0b110100,0b111001,0b101110,0b100011,0b1101000,0b1100101,0b1110010,\n", 51 | " 0b1111111,0b1011100,0b1010001,0b1000110,0b1001011,0b0,0b1110,0b11100,\n", 52 | " 0b10010,0b111000,0b110110,0b100100,0b101010,0b1110000,0b1111110,0b1101100,\n", 53 | " 0b1100010,0b1001000,0b1000110,0b1010100,0b1011010,0b0,0b1111,0b11110,\n", 54 | " 0b10001,0b111100,0b110011,0b100010,0b101101,0b1111000,0b1110111,0b1100110,\n", 55 | " 0b1101001,0b1000100,0b1001011,0b1011010,0b1010101])\n", 56 | " def mul_2 (self,a, b):\n", 57 | " a1 = (a&2)>>1\n", 58 | " a0 = (a&1)\n", 59 | " b1 = (b&2)>>1\n", 60 | " b0 = (b&1)\n", 61 | "\n", 62 | " d2 = (a1 & b1)&1\n", 63 | " d1 = ((a1 & b0) ^ (a0 & b1))&1\n", 64 | " d0 = (a0 & b0)&1\n", 65 | " return d2<<2 | d1 <<1 | d0\n", 66 | "\n", 67 | " def mul_4 (self,a, b):\n", 68 | " a1 = (a&0xC)>>2\n", 69 | " a0 = (a&0x3)\n", 70 | " b1 = (b&0xc)>>2\n", 71 | " b0 = (b&0x3)\n", 72 | "\n", 73 | " d2 = self.mul_2(a1, b1)\n", 74 | " d1 = (self.mul_2(a1, b0) ^ self.mul_2(a0, b1))\n", 75 | " d0 = self.mul_2(a0, b0)\n", 76 | " return d2<<4 ^ d1 <<2 ^ d0\n", 77 | "\n", 78 | " def mul_8 (self,a, b):\n", 79 | " a1 = (a&0xf0)>>4\n", 80 | " a0 = (a&0xf)\n", 81 | " b1 = (b&0xf0)>>4\n", 82 | " b0 = (b&0xf)\n", 83 | "\n", 84 | " d2 = self.mul_4(a1, b1)\n", 85 | " d1 = (self.mul_4(a1, b0) ^ self.mul_4(a0, b1))\n", 86 | " d0 = self.mul_4(a0, b0)\n", 87 | " return d2<<8 ^ d1 <<4 ^ d0\n", 88 | " \n", 89 | " def mul_8_lut (self,a, b):\n", 90 | " a1 = (a&0xf0)>>4\n", 91 | " a0 = (a&0xf)\n", 92 | " b1 = (b&0xf0)>>4\n", 93 | " b0 = (b&0xf)\n", 94 | "\n", 95 | " d2 = self.MUL_LUT[a1<<4 | b1]\n", 96 | " d1 = self.MUL_LUT[a1<<4 | b0] ^ self.MUL_LUT[a0<<4 | b1]\n", 97 | " d0 = self.MUL_LUT[a0<<4 | b0]\n", 98 | " return d2<<8 ^ d1 <<4 ^ d0\n", 99 | " \n", 100 | " \n", 101 | " def mul_8_lut(self,a, b):\n", 102 | " a1 = (a&0xf0)>>4\n", 103 | " a0 = (a&0xf)\n", 104 | " b1 = (b&0xf0)>>4\n", 105 | " b0 = (b&0xf)\n", 106 | " d2 = self.MUL_LUT[a1<<4 | b1]\n", 107 | " d1 = self.MUL_LUT[a1<<4 | b0] ^ self.MUL_LUT[a0<<4 | b1]\n", 108 | " d0 = self.MUL_LUT[a0<<4 | b0]\n", 109 | " return d2<<8 ^ d1 <<4 ^ d0\n", 110 | " \n", 111 | " \n", 112 | " def mul_32 (self,a, b):\n", 113 | " a=np.array([a])\n", 114 | " b=np.array([b])\n", 115 | " #a.astype(int)\n", 116 | " #b.astype(int)\n", 117 | " a=a.view('uint8')\n", 118 | " b = b.view('uint8')\n", 119 | " a=a.tolist()\n", 120 | " b=b.tolist()\n", 121 | " a3=a[0]\n", 122 | " a2 = a[1]\n", 123 | " a1=a[2]\n", 124 | " a0 = a[3]\n", 125 | " b3=b[0]\n", 126 | " b2=b[1]\n", 127 | " b1=b[2]\n", 128 | " b0= b[3]\n", 129 | " #print hex(a3),hex(a2),hex(a1),hex(a0),hex(b3),hex(b2),hex(b1),hex(b0)\n", 130 | " phi1=self.mul_8_lut(a3,b3) ^ self.mul_8_lut(a2,b2)\n", 131 | " phi2=self.mul_8_lut(a1,b1) ^ self.mul_8_lut(a0,b0)\n", 132 | " phi=phi1^phi2\n", 133 | " d6 = int(self.mul_8_lut(a3,b3))\n", 134 | " d5 = int(self.mul_8_lut(a3^a2, b3^b2)^phi1) \n", 135 | " d4 = int(self.mul_8_lut(a3^a1, b3^b1))^(phi1)^self.mul_8_lut(a1,b1)\n", 136 | " d3 = int(self.mul_8_lut(a3^a0, b3^b0)^self.mul_8_lut(a2^a1, b2^b1)^phi) \n", 137 | " \n", 138 | " #d3=d3.view('uint64')\n", 139 | " d2 = self.mul_8_lut(a2^a0, b2^b0)^phi2^self.mul_8_lut(a2,b2)\n", 140 | " d1 = self.mul_8_lut(a1^a0, b1^b0)^phi2 \n", 141 | " d0 = self.mul_8_lut(a0,b0)\n", 142 | " #print hex(d3),hex(d2),hex(d1),hex(d4),hex(d5),hex(d6),(phi1)\n", 143 | " #print hex(a2),hex(a3),hex(b2),hex(b3)\n", 144 | " return ( d6<<48 ^ d5<<40 ^ d4<<32 ^ d3<<24 ^ d2<<16 ^ d1<<8 ^ d0)\n", 145 | " \n", 146 | " \n", 147 | " \n", 148 | " \n", 149 | " \n", 150 | " def recursion(self,a,b):\n", 151 | " global i\n", 152 | " a = binascii.unhexlify(a)\n", 153 | " a = np.fromstring(a, dtype='uint32')\n", 154 | " b = binascii.unhexlify(b)\n", 155 | " b = np.fromstring(b, dtype='uint32')\n", 156 | " \n", 157 | " l1=len(a)\n", 158 | " l2=len(b)\n", 159 | " \n", 160 | " a1=a[0]\n", 161 | " b1=b[0]\n", 162 | " b0=b[1]\n", 163 | " a0=a[1]\n", 164 | " d2=int(self.mul_32(a1,b1))\n", 165 | " d0=int(self.mul_32(a0,b0))\n", 166 | " d1=int(self.mul_32((a1^b0),(a0^b1)))^d0^d2\n", 167 | " return d2<<64 ^ d1<<32 ^d0\n", 168 | " \n", 169 | " " 170 | ], 171 | "language": "python", 172 | "metadata": {}, 173 | "outputs": [], 174 | "prompt_number": 5 175 | }, 176 | { 177 | "cell_type": "code", 178 | "collapsed": false, 179 | "input": [ 180 | "a=Binfield(\"ff00ffff\")\n", 181 | "a.recursion('1300000012345678','2300000080000000')" 182 | ], 183 | "language": "python", 184 | "metadata": {}, 185 | "outputs": [ 186 | { 187 | "output_type": "stream", 188 | "stream": "stdout", 189 | "text": [ 190 | "2 2\n" 191 | ] 192 | }, 193 | { 194 | "metadata": {}, 195 | "output_type": "pyout", 196 | "prompt_number": 6, 197 | "text": [ 198 | "3099801229677303153877121948832497664L" 199 | ] 200 | } 201 | ], 202 | "prompt_number": 6 203 | }, 204 | { 205 | "cell_type": "code", 206 | "collapsed": false, 207 | "input": [], 208 | "language": "python", 209 | "metadata": {}, 210 | "outputs": [] 211 | } 212 | ], 213 | "metadata": {} 214 | } 215 | ] 216 | } -------------------------------------------------------------------------------- /Python Code/readme.md: -------------------------------------------------------------------------------- 1 | This contain the code in python of various algorithm used in implementation of ECC Elliptic Curve Cryptograohy. 2 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Contributed to the development of a Verilog module for FPGA-based High-Throughput Generic ECC Implementation in Binary Extension Field. 2 | 3 | 4 | My contribution includes 5 | 6 | • Design and analysis of 128 bit Hybrid Karatsuba Ofman Combinational Multiplier. 7 | 8 | • Development of Generic Point Addition, Point Doubling, and Scalar Multiplication Module 9 | 10 | • Development of ECDSA host Library 11 | 12 | 13 | 14 | Guides : Abhishek Bajpai, Scientific Officer at BARC 15 | 16 | Saket Saurav, Research Engineer at IIITDM Jabalpur 17 | -------------------------------------------------------------------------------- /Verilog Code/doc/.ipynb_checkpoints/Curve_Calculation-checkpoint.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "metadata": { 3 | "name": "", 4 | "signature": "sha256:283583ef22e283073a4d968f6c0b91ad6a3684882536815ea0ab4b41b8c3b8ac" 5 | }, 6 | "nbformat": 3, 7 | "nbformat_minor": 0, 8 | "worksheets": [ 9 | { 10 | "cells": [ 11 | { 12 | "cell_type": "code", 13 | "collapsed": false, 14 | "input": [ 15 | "import numpy as np\n", 16 | "a=np.array([0,1,2,0,0,0,0,0,1])\n", 17 | "print a" 18 | ], 19 | "language": "python", 20 | "metadata": {}, 21 | "outputs": [ 22 | { 23 | "output_type": "stream", 24 | "stream": "stdout", 25 | "text": [ 26 | "[0 1 2 0 0 0 0 0 1]\n" 27 | ] 28 | } 29 | ], 30 | "prompt_number": 3 31 | }, 32 | { 33 | "cell_type": "code", 34 | "collapsed": false, 35 | "input": [ 36 | "np.nonzero(a)71 0a 02 09 01" 37 | ], 38 | "language": "python", 39 | "metadata": {}, 40 | "outputs": [ 41 | { 42 | "metadata": {}, 43 | "output_type": "pyout", 44 | "prompt_number": 4, 45 | "text": [ 46 | "(array([1, 2, 8]),)" 47 | ] 48 | } 49 | ], 50 | "prompt_number": 4 51 | }, 52 | { 53 | "cell_type": "code", 54 | "collapsed": false, 55 | "input": [ 56 | "import binascii\n", 57 | "import numpy as np\n", 58 | "import gmpy2\n", 59 | "\n", 60 | "\n", 61 | "def remove_0( A):\n", 62 | " while A[0] == 0:\n", 63 | " if len(A) == 1:\n", 64 | " break\n", 65 | " A = A[1:]\n", 66 | " return A\n", 67 | "def str2nparray( A):\n", 68 | " A = '0'*(8 - len(A)%8) + A\n", 69 | " A = binascii.unhexlify(A)\n", 70 | " A = np.fromstring(A[::-1], dtype='uint32') \n", 71 | " return A\n", 72 | "Curve_Polynomial=np.array([],dtype='uint8') \n", 73 | "Polynomial='020000000000000000000000000201'\n", 74 | "Polynomial=str2nparray(Polynomial)\n", 75 | "Curve_len=(len(Polynomail)-1)*32+gmpy2.bit_length(int(Polynomial[-1]))\n", 76 | "D=Polynomial.view('uint8')[::-1]\n", 77 | "D=remove_0(D)\n", 78 | "position=np.nonzero(D)\n", 79 | "print position\n", 80 | "position=position[0]\n", 81 | "frst_chunk=D[position[1]]\n", 82 | "frst_position=(position[1]/8)*8+7-(position[1]%8)\n", 83 | "\n", 84 | "if(len(position==3)):\n", 85 | " secnd_chunk=D[position[2]]\n", 86 | " secnd_position=(position[2]/8)*8+7-(position[2]%8)\n", 87 | "\n" 88 | ], 89 | "language": "python", 90 | "metadata": {}, 91 | "outputs": [ 92 | { 93 | "output_type": "stream", 94 | "stream": "stdout", 95 | "text": [ 96 | "(array([ 0, 13, 14]),)\n" 97 | ] 98 | } 99 | ], 100 | "prompt_number": 26 101 | }, 102 | { 103 | "cell_type": "code", 104 | "collapsed": false, 105 | "input": [ 106 | "print secnd_position" 107 | ], 108 | "language": "python", 109 | "metadata": {}, 110 | "outputs": [ 111 | { 112 | "output_type": "stream", 113 | "stream": "stdout", 114 | "text": [ 115 | "9\n" 116 | ] 117 | } 118 | ], 119 | "prompt_number": 27 120 | }, 121 | { 122 | "cell_type": "code", 123 | "collapsed": false, 124 | "input": [], 125 | "language": "python", 126 | "metadata": {}, 127 | "outputs": [] 128 | } 129 | ], 130 | "metadata": {} 131 | } 132 | ] 133 | } -------------------------------------------------------------------------------- /Verilog Code/doc/Curve_Calculation.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "metadata": { 3 | "name": "", 4 | "signature": "sha256:4f09f0974d9a880c0a217eb3f0f6f80613c491fb62a07e833bb6fc9bb5134be1" 5 | }, 6 | "nbformat": 3, 7 | "nbformat_minor": 0, 8 | "worksheets": [ 9 | { 10 | "cells": [ 11 | { 12 | "cell_type": "code", 13 | "collapsed": false, 14 | "input": [ 15 | "import numpy as np\n", 16 | "a=np.array([0,1,2,0,0,0,0,0,1])\n", 17 | "print a" 18 | ], 19 | "language": "python", 20 | "metadata": {}, 21 | "outputs": [ 22 | { 23 | "output_type": "stream", 24 | "stream": "stdout", 25 | "text": [ 26 | "[0 1 2 0 0 0 0 0 1]\n" 27 | ] 28 | } 29 | ], 30 | "prompt_number": 3 31 | }, 32 | { 33 | "cell_type": "code", 34 | "collapsed": false, 35 | "input": [ 36 | "np.nonzero(a)71 0a 02 09 01" 37 | ], 38 | "language": "python", 39 | "metadata": {}, 40 | "outputs": [ 41 | { 42 | "metadata": {}, 43 | "output_type": "pyout", 44 | "prompt_number": 4, 45 | "text": [ 46 | "(array([1, 2, 8]),)" 47 | ] 48 | } 49 | ], 50 | "prompt_number": 4 51 | }, 52 | { 53 | "cell_type": "code", 54 | "collapsed": false, 55 | "input": [ 56 | "import binascii\n", 57 | "import numpy as np\n", 58 | "import gmpy2\n", 59 | "\n", 60 | "np.set_printoptions(formatter={'int':hex})\n", 61 | "\n", 62 | "def remove_0( A):\n", 63 | " while A[0] == 0:\n", 64 | " if len(A) == 1:\n", 65 | " break\n", 66 | " A = A[1:]\n", 67 | " return A\n", 68 | "def str2nparray( A):\n", 69 | " A = '0'*(8 - len(A)%8) + A\n", 70 | " A = binascii.unhexlify(A)\n", 71 | " A = np.fromstring(A[::-1], dtype='uint32') \n", 72 | " return A\n", 73 | "\n", 74 | " \n", 75 | "def nparray2str2( A):\n", 76 | " c = ''\n", 77 | " d = A.view('uint8')\n", 78 | " for i in d:\n", 79 | " c+=binascii.hexlify(i)\n", 80 | " return c \n", 81 | "Polynomial='0800000000000000000000000000000000000000c9'\n", 82 | "def Curve_Calculation(Polynomial): \n", 83 | " Curve_Polynomial=np.array([],dtype='uint8') \n", 84 | " Polynomial=str2nparray(Polynomial)\n", 85 | " Curve_len=(len(Polynomial)-1)*32+gmpy2.bit_length(int(Polynomial[-1]))-1\n", 86 | " D=Polynomial.view('uint8')[::-1]\n", 87 | " D=remove_0(D)\n", 88 | " position=np.nonzero(D)\n", 89 | " print position\n", 90 | " position=position[0]\n", 91 | " print len(position)\n", 92 | " secnd_chunk=0x00\n", 93 | " secnd_position=0x00\n", 94 | " frst_chunk=D[position[1]]\n", 95 | " frst_position=(position[1]/8)*8+7-(position[1]%8)\n", 96 | "\n", 97 | " if(len(position)==3):\n", 98 | " secnd_chunk=D[position[2]]\n", 99 | " secnd_position=(position[2]/8)*8+7-(position[2]%8)\n", 100 | " Curve_Polynomial=np.array([Curve_len,frst_position,frst_chunk,secnd_position,secnd_chunk],dtype='uint8')\n", 101 | " Curve_Polynomial=nparray2str2(Curve_Polynomial)\n", 102 | " print Curve_Polynomial\n", 103 | " return Curve_Polynomial" 104 | ], 105 | "language": "python", 106 | "metadata": {}, 107 | "outputs": [], 108 | "prompt_number": 9 109 | }, 110 | { 111 | "cell_type": "code", 112 | "collapsed": false, 113 | "input": [ 114 | "Polynomial='\n", 115 | "0800000000000000 \n", 116 | "0000000000000000 \n", 117 | "00000000c9 000000'\n", 118 | "Curve_Calculation(Polynomial)" 119 | ], 120 | "language": "python", 121 | "metadata": {}, 122 | "outputs": [ 123 | { 124 | "output_type": "stream", 125 | "stream": "stdout", 126 | "text": [ 127 | "(array([0x0L, 0x14L]),)\n", 128 | "2\n", 129 | "a313c90000\n" 130 | ] 131 | }, 132 | { 133 | "metadata": {}, 134 | "output_type": "pyout", 135 | "prompt_number": 10, 136 | "text": [ 137 | "'a313c90000'" 138 | ] 139 | } 140 | ], 141 | "prompt_number": 10 142 | }, 143 | { 144 | "cell_type": "code", 145 | "collapsed": false, 146 | "input": [ 147 | "a = np.array([1 , 2])\n", 148 | "b = np.array([1 , 2])\n", 149 | "a=np.concatenate([a,b],axis=0)\n", 150 | "print a" 151 | ], 152 | "language": "python", 153 | "metadata": {}, 154 | "outputs": [ 155 | { 156 | "output_type": "stream", 157 | "stream": "stdout", 158 | "text": [ 159 | "[0x1L 0x2L 0x1L 0x2L]\n" 160 | ] 161 | } 162 | ], 163 | "prompt_number": 49 164 | }, 165 | { 166 | "cell_type": "code", 167 | "collapsed": false, 168 | "input": [ 169 | "hex(163)" 170 | ], 171 | "language": "python", 172 | "metadata": {}, 173 | "outputs": [ 174 | { 175 | "metadata": {}, 176 | "output_type": "pyout", 177 | "prompt_number": 12, 178 | "text": [ 179 | "'0xa3'" 180 | ] 181 | } 182 | ], 183 | "prompt_number": 12 184 | }, 185 | { 186 | "cell_type": "code", 187 | "collapsed": false, 188 | "input": [], 189 | "language": "python", 190 | "metadata": {}, 191 | "outputs": [] 192 | } 193 | ], 194 | "metadata": {} 195 | } 196 | ] 197 | } -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/LOOK_UP_table_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Deepak 5 | // 6 | // Create Date: 17:05:25 07/21/2014 7 | // Design Name: 8 | // Module Name: alignment_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | /*770 Slice Lut*/ 23 | 24 | module LOOK_UP_module#( 25 | parameter IS_ZERO_POS=3'b011 26 | )( 27 | input [63:0] A_Poly, //frst chunk [19:12] scnd chunk [7:0] 28 | input [63:0] B, 29 | output wire [127:0] D_out_1, //frst chunk lut[255:128] secnd chunk Lut[127:0] 30 | output wire [127:0] D_out_2 31 | ); 32 | 33 | 34 | wire [63:0] D,var; 35 | wire [15:0] A_26,B_16,C_16,C_16_XOR; 36 | wire [7:0] A_1,A_2; 37 | wire [3:0] byte_pos_1,byte_pos_2; 38 | 39 | wire [7:0] C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7; 40 | wire [7:0] C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7; 41 | 42 | wire [127:0] Lut_Out, Lut_Out_2; 43 | 44 | //assign D_Out={D_out_1,D_out_2}; 45 | 46 | assign D_out_1=(byte_pos_1==7)?({Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],56'b0}): 47 | ((byte_pos_1==6)?({8'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],48'b0}):((byte_pos_1==5)?({16'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],40'b0}):((byte_pos_1==4)?({24'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],32'b0}):((byte_pos_1==3)?({32'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],24'b0}): 48 | ((byte_pos_1==2)?{40'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],16'b0}: 49 | ((byte_pos_1==1)?{48'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0],8'h0}: 50 | ({56'h0,Lut_Out[127:120],C_Out1_1,C_Out1_2,C_Out1_3,C_Out1_4,C_Out1_5,C_Out1_6,C_Out1_7,Lut_Out[7:0]}))))))); 51 | 52 | 53 | assign D_out_2=(byte_pos_2==7)?({Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],56'b0}): 54 | ((byte_pos_2==6)?({8'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],48'b0}):((byte_pos_2==5)?({16'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],40'b0}):((byte_pos_2==4)?({24'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],32'b0}):((byte_pos_2==3)?({32'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],24'b0}): 55 | ((byte_pos_2==2)?{40'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],16'b0}: 56 | ((byte_pos_2==1)?{48'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0],8'h0}: 57 | ({56'h0,Lut_Out_2[127:120],C_Out2_1,C_Out2_2,C_Out2_3,C_Out2_4,C_Out2_5,C_Out2_6,C_Out2_7,Lut_Out_2[7:0]}))))))); 58 | 59 | 60 | assign A_1=A_Poly[19:12]; 61 | assign byte_pos_1=A_Poly[23:20]; 62 | 63 | assign A_2=A_Poly[7:0]; 64 | assign byte_pos_2=A_Poly[11:8]; 65 | 66 | LUT look_up_table1 ( 67 | .A(A_1), 68 | .B(B[63:56]), 69 | .C(Lut_Out[127:112]) 70 | ); 71 | 72 | LUT look_up_table2 ( 73 | .A(A_1), 74 | .B(B[55:48]), 75 | .C(Lut_Out[111:96]) 76 | ); 77 | LUT look_up_table3 ( 78 | .A(A_1), 79 | .B(B[47:40]), 80 | .C(Lut_Out[95:80]) 81 | ); 82 | LUT look_up_table4 ( 83 | .A(A_1), 84 | .B(B[39:32]), 85 | .C(Lut_Out[79:64]) 86 | ); 87 | LUT look_up_table5 ( 88 | .A(A_1), 89 | .B(B[31:24]), 90 | .C(Lut_Out[63:48]) 91 | ); 92 | LUT look_up_table6 ( 93 | .A(A_1), 94 | .B(B[23:16]), 95 | .C(Lut_Out[47:32]) 96 | ); 97 | LUT look_up_table7 ( 98 | .A(A_1), 99 | .B(B[15:8]), 100 | .C(Lut_Out[31:16]) 101 | ); 102 | LUT look_up_table8 ( 103 | .A(A_1), 104 | .B(B[7:0]), 105 | .C(Lut_Out[15:0]) 106 | ); 107 | 108 | 109 | ////////Second byte reduce table//////// 110 | LUT look_up_table9 ( 111 | .A(A_2), 112 | .B(B[63:56]), 113 | .C(Lut_Out_2[127:112]) 114 | ); 115 | 116 | LUT look_up_table10 ( 117 | .A(A_2), 118 | .B(B[55:48]), 119 | .C(Lut_Out_2[111:96]) 120 | ); 121 | LUT look_up_table11 ( 122 | .A(A_2), 123 | .B(B[47:40]), 124 | .C(Lut_Out_2[95:80]) 125 | ); 126 | LUT look_up_table12 ( 127 | .A(A_2), 128 | .B(B[39:32]), 129 | .C(Lut_Out_2[79:64]) 130 | ); 131 | LUT look_up_table13 ( 132 | .A(A_2), 133 | .B(B[31:24]), 134 | .C(Lut_Out_2[63:48]) 135 | ); 136 | LUT look_up_table14 ( 137 | .A(A_2), 138 | .B(B[23:16]), 139 | .C(Lut_Out_2[47:32]) 140 | ); 141 | LUT look_up_table15 ( 142 | .A(A_2), 143 | .B(B[15:8]), 144 | .C(Lut_Out_2[31:16]) 145 | ); 146 | LUT look_up_table16 ( 147 | .A(A_2), 148 | .B(B[7:0]), 149 | .C(Lut_Out_2[15:0]) 150 | ); 151 | 152 | 153 | XOR Xor_16_1 ( 154 | .A(Lut_Out[119:112]), 155 | .B(Lut_Out[111:104]), 156 | .C(C_Out1_1) 157 | ); 158 | XOR Xor_16_2 ( 159 | .A(Lut_Out[103:96]), 160 | .B(Lut_Out[95:88]), 161 | .C(C_Out1_2) 162 | ); 163 | XOR Xor_16_3 ( 164 | .A(Lut_Out[87:80]), 165 | .B(Lut_Out[79:72]), 166 | .C(C_Out1_3) 167 | ); 168 | XOR Xor_16_4 ( 169 | .A(Lut_Out[71:64]), 170 | .B(Lut_Out[63:56]), 171 | .C(C_Out1_4) 172 | ); 173 | XOR Xor_16_5 ( 174 | .A(Lut_Out[55:48]), 175 | .B(Lut_Out[47:40]), 176 | .C(C_Out1_5) 177 | ); 178 | 179 | XOR Xor_16_6 ( 180 | .A(Lut_Out[39:32]), 181 | .B(Lut_Out[31:24]), 182 | .C(C_Out1_6) 183 | ); 184 | XOR Xor_16_7 ( 185 | .A(Lut_Out[23:16]), 186 | .B(Lut_Out[15:8]), 187 | .C(C_Out1_7) 188 | ); 189 | 190 | XOR Xor_16_8 ( 191 | .A(Lut_Out_2[119:112]), 192 | .B(Lut_Out_2[111:104]), 193 | .C(C_Out2_1) 194 | ); 195 | XOR Xor_16_9 ( 196 | .A(Lut_Out_2[103:96]), 197 | .B(Lut_Out_2[95:88]), 198 | .C(C_Out2_2) 199 | ); 200 | XOR Xor_16_10 ( 201 | .A(Lut_Out_2[87:80]), 202 | .B(Lut_Out_2[79:72]), 203 | .C(C_Out2_3) 204 | ); 205 | XOR Xor_16_11 ( 206 | .A(Lut_Out_2[71:64]), 207 | .B(Lut_Out_2[63:56]), 208 | .C(C_Out2_4) 209 | ); 210 | XOR Xor_16_12 ( 211 | .A(Lut_Out_2[55:48]), 212 | .B(Lut_Out_2[47:40]), 213 | .C(C_Out2_5) 214 | ); 215 | 216 | XOR Xor_16_13 ( 217 | .A(Lut_Out_2[39:32]), 218 | .B(Lut_Out_2[31:24]), 219 | .C(C_Out2_6) 220 | ); 221 | XOR Xor_16_14 ( 222 | .A(Lut_Out_2[23:16]), 223 | .B(Lut_Out_2[15:8]), 224 | .C(C_Out2_7) 225 | ); 226 | 227 | 228 | 229 | 230 | endmodule 231 | 232 | 233 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/LUT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:27:02 07/09/2014 7 | // Design Name: 8 | // Module Name: LUT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | //A reduction Polynomial 23 | //B= input polynomial 24 | 25 | module LUT(input[7:0] A, 26 | input[7:0] B, 27 | output[15:0] C 28 | ); 29 | wire[15:0] d,d2,d3,d4,d5,d6,d7, d1; 30 | assign d[15:8]=A[7:0]; 31 | assign d[7:0]=8'b0; 32 | assign d1=B[7]?d:16'b0; 33 | assign d2=B[6]?d1^d>>1:d1; 34 | assign d3=B[5]?d2^d>>2:d2; 35 | assign d4=B[4]?d3^d>>3:d3; 36 | assign d5=B[3]?d4^d>>4:d4; 37 | assign d6=B[2]?d5^d>>5:d5; 38 | assign d7=B[1]?d6^d>>6:d6; 39 | assign C[15:0]=B[0]?d7^d>>7:d7; 40 | endmodule 41 | 42 | 43 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Masking_Module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:24:28 09/01/2014 7 | // Design Name: 8 | // Module Name: Masking_Module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Masking_Module( 22 | input[63:0] A, 23 | input[7:0] B, 24 | output [63:0] Out 25 | 26 | ); 27 | assign Out=(B==8'h1)?({A[63:1],1'h0}): 28 | ((B==8'h2)?({A[63:2],2'h0}): 29 | ((B==8'h3)?({A[63:3],3'h0}): 30 | ((B==8'h4)?({A[63:4],4'h0}): 31 | ((B==8'h5)?({A[63:5],5'h0}): 32 | ((B==8'h6)?({A[63:6],6'h0}): 33 | ((B==8'h7)?({A[63:7],7'h0}): 34 | ((B==8'h8)?({A[63:8],8'h0}): 35 | ((B==8'h9)?({A[63:9],9'h0}): 36 | ((B==8'ha)?({A[63:10],10'h0}): 37 | ((B==8'hb)?({A[63:11],11'h0}): 38 | ((B==8'hc)?({A[63:12],12'h0}): 39 | ((B==8'hd)?({A[63:13],13'h0}): 40 | ((B==8'he)?({A[63:14],14'h0}): 41 | ((B==8'hf)?({A[63:15],15'h0}): 42 | ((B==8'h10)?({A[63:16],16'h0}): 43 | ((B==8'h11)?({A[63:17],17'h0}): 44 | ((B==8'h12)?({A[63:18],18'h0}): 45 | ((B==8'h13)?({A[63:19],19'h0}): 46 | ((B==8'h14)?({A[63:20],20'h0}): 47 | ((B==8'h15)?({A[63:21],21'h0}): 48 | ((B==8'h16)?({A[63:22],22'h0}): 49 | ((B==8'h17)?({A[63:23],23'h0}): 50 | ((B==8'h18)?({A[63:24],24'h0}): 51 | ((B==8'h19)?({A[63:25],25'h0}): 52 | ((B==8'h1a)?({A[63:26],26'h0}): 53 | ((B==8'h1b)?({A[63:27],27'h0}): 54 | ((B==8'h1c)?({A[63:28],28'h0}): 55 | ((B==8'h1d)?({A[63:29],29'h0}): 56 | ((B==8'h1e)?({A[63:30],30'h0}): 57 | ((B==8'h1f)?({A[63:31],31'h0}): 58 | ((B==8'h20)?({A[63:32],32'h0}): 59 | ((B==8'h21)?({A[63:33],33'h0}): 60 | ((B==8'h22)?({A[63:34],34'h0}): 61 | ((B==8'h23)?({A[63:35],35'h0}): 62 | ((B==8'h24)?({A[63:36],36'h0}): 63 | ((B==8'h25)?({A[63:37],37'h0}): 64 | ((B==8'h26)?({A[63:38],38'h0}): 65 | ((B==8'h27)?({A[63:39],39'h0}): 66 | ((B==8'h28)?({A[63:40],40'h0}): 67 | ((B==8'h29)?({A[63:41],41'h0}): 68 | ((B==8'h2a)?({A[63:42],42'h0}): 69 | ((B==8'h2b)?({A[63:43],43'h0}): 70 | ((B==8'h2c)?({A[63:44],44'h0}): 71 | ((B==8'h2d)?({A[63:45],45'h0}): 72 | ((B==8'h2e)?({A[63:46],46'h0}): 73 | ((B==8'h2f)?({A[63:47],47'h0}): 74 | ((B==8'h30)?({A[63:48],48'h0}): 75 | ((B==8'h31)?({A[63:49],49'h0}): 76 | ((B==8'h32)?({A[63:50],50'h0}): 77 | ((B==8'h33)?({A[63:51],51'h0}): 78 | ((B==8'h34)?({A[63:52],52'h0}): 79 | ((B==8'h35)?({A[63:53],53'h0}): 80 | ((B==8'h36)?({A[63:54],54'h0}): 81 | ((B==8'h37)?({A[63:55],55'h0}): 82 | ((B==8'h38)?({A[63:56],56'h0}): 83 | ((B==8'h39)?({A[63:57],57'h0}): 84 | ((B==8'h3a)?({A[63:58],58'h0}): 85 | ((B==8'h3b)?({A[63:59],59'h0}): 86 | ((B==8'h3c)?({A[63:60],60'h0}): 87 | ((B==8'h3d)?({A[63:61],61'h0}): 88 | ((B==8'h3e)?({A[63:62],62'h0}): 89 | ((B==8'h3f)?({A[63],63'h0}):A)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))); 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Outer_Ram_Module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul and Deepak 5 | // 6 | // Create Date: 05:37:33 01/01/2009 7 | // Design Name: 8 | // Module Name: Outer_Ram_Module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_Module_1#( 22 | parameter DATA = 256, 23 | parameter ADDR = 6)( 24 | input clk, 25 | input a_w, 26 | input b_w, 27 | input wire [(ADDR-1):0] a_adbus, 28 | input wire [(DATA-1):0] a_data_in, 29 | output reg [(DATA-1):0] a_data_out, 30 | input wire [(ADDR-1):0] b_adbus, 31 | input wire [(DATA-1):0] b_data_in, 32 | output reg [(DATA-1):0] b_data_out 33 | ); 34 | 35 | 36 | reg [(DATA-1):0]memory [0:47]; //Declaring Memory 37 | reg [(DATA-1):0] b_data_out1,a_data_out1; 38 | 39 | 40 | always @(posedge clk) begin 41 | if( a_w ) begin 42 | memory[a_adbus] <= a_data_in; 43 | end 44 | a_data_out<=memory[a_adbus]; 45 | end 46 | 47 | always @(posedge clk) begin 48 | if( b_w ) begin 49 | memory[b_adbus] <= b_data_in; 50 | end 51 | b_data_out<=memory[b_adbus]; 52 | 53 | end//end of always module 54 | 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Outer_Ram_interface.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul 5 | // 6 | // Create Date: 05:42:12 01/01/2009 7 | // Design Name: 8 | // Module Name: Outer_Ram_interface 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Outer_Ram_interface#( 22 | parameter Data=256, 23 | parameter Addr=5, 24 | parameter command_len=1) 25 | ( 26 | input wire clk, 27 | //interfacing of Ram for taking Data from outside 28 | input wire a_w, 29 | input wire [Addr:0] a_adbus, 30 | input wire [(Data-1):0] a_data_in, 31 | output wire [(Data-1):0] a_data_out, 32 | //interfacing of Ram with inner module 33 | input wire b_w, 34 | input wire [Addr:0] b_adbus, //address bus 35 | input wire [(Data-1):0] b_data_in, 36 | output wire [(Data-1):0] b_data_out 37 | 38 | 39 | ); 40 | 41 | 42 | 43 | 44 | 45 | Ram_Module_1 Ram_Module_1 ( 46 | .clk(clk), 47 | .a_w(a_w), 48 | .b_w(b_w), 49 | .a_adbus(a_adbus), 50 | .a_data_in(a_data_in), 51 | .a_data_out(a_data_out), 52 | .b_adbus(b_adbus), 53 | .b_data_in(b_data_in), 54 | .b_data_out(b_data_out) 55 | ); 56 | 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_Interface_Module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Barc 4 | // Engineer: Deepak Kapoor (modified) 5 | // 6 | // Create Date: 22:42:05 08/15/2014 7 | // Design Name: 8 | // Module Name: Ram_Interface_Module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_Interface_Module#( 22 | parameter DATA = 256, 23 | parameter ADDR = 3 24 | )( 25 | input clk, 26 | input a_w, 27 | input [5:0] a_adbus, 28 | input wire [(DATA-1):0] a_data_in, 29 | output wire [(DATA-1):0] a_data_out, 30 | 31 | input b_w_A, 32 | 33 | /*For simultaneous Read address Port must be differnt */ 34 | input wire [(ADDR-1):0] b_adbus_A, 35 | input wire [(DATA-1):0] b_data_in_A, 36 | output wire [(DATA-1):0] b_data_out_A, 37 | 38 | input b_w_B, 39 | input wire [(ADDR-1):0] b_adbus_B, 40 | input wire [(DATA-1):0] b_data_in_B, 41 | output wire [(DATA-1):0] b_data_out_B, 42 | 43 | input b_w_C, 44 | input wire [(ADDR-1):0] b_adbus_C, 45 | input wire [(DATA-1):0] b_data_in_C, 46 | output wire [(DATA-1):0] b_data_out_C, 47 | 48 | input b_w_D, 49 | input wire [(ADDR-1):0] b_adbus_D, 50 | input wire [(DATA-1):0] b_data_in_D, 51 | output wire [(DATA-1):0] b_data_out_D, 52 | input wire [3:0] b_command ,//address bus 53 | 54 | output wire [3:0] command //command reg 55 | 56 | ); 57 | 58 | wire [255:0] a_data_in_A,a_data_in_B,a_data_in_C,a_data_in_D; 59 | wire [2:0] a_adbus_A,a_adbus_B,a_adbus_C,a_adbus_D; 60 | wire [255:0] a_data_out_A,a_data_out_B,a_data_out_C,a_data_out_D; 61 | reg [3:0] command1; 62 | 63 | assign command = command1; 64 | 65 | assign a_data_in_A=(a_adbus[5:3]==3'b001)?a_data_in:255'hz; 66 | assign a_adbus_A=(a_adbus[5:3]==3'b001)?a_adbus[2:0]:3'hz; 67 | 68 | assign a_data_in_B=(a_adbus[5:3]==3'b010)?a_data_in:255'hz; 69 | assign a_adbus_B=(a_adbus[5:3]==3'b010)?a_adbus[2:0]:3'hz; 70 | 71 | assign a_data_in_C=(a_adbus[5:3]==3'b011)?a_data_in:255'hz; 72 | assign a_adbus_C=(a_adbus[5:3]==3'b011)?a_adbus[2:0]:3'hz; 73 | 74 | assign a_data_in_D=(a_adbus[5:3]==3'b100)?a_data_in:255'hz; 75 | assign a_adbus_D=(a_adbus[5:3]==3'b100)?a_adbus[2:0]:3'hz; 76 | 77 | 78 | assign a_data_out=(a_adbus[5:3]==3'b001)?a_data_out_A: 79 | ((a_adbus[5:3]==3'b010)?a_data_out_B: 80 | ((a_adbus[5:3]==3'b011)?a_data_out_C: 81 | ((a_adbus[5:3]==3'b100)?a_data_out_D:a_data_out))); 82 | 83 | 84 | 85 | Ram_Module Ram_A ( 86 | .clk(clk), 87 | .a_w(a_w), 88 | .b_w(b_w_A), 89 | .a_adbus(a_adbus_A), 90 | .a_data_in(a_data_in_A), 91 | .a_data_out(a_data_out_A), 92 | .b_adbus(b_adbus_A), 93 | .b_data_in(b_data_in_A), 94 | .b_data_out(b_data_out_A) 95 | ); 96 | 97 | Ram_Module Ram_B ( 98 | .clk(clk), 99 | .a_w(a_w), 100 | .b_w(b_w_B), 101 | .a_adbus(a_adbus_B), 102 | .a_data_in(a_data_in_B), 103 | .a_data_out(a_data_out_B), 104 | .b_adbus(b_adbus_B), 105 | .b_data_in(b_data_in_B), 106 | .b_data_out(b_data_out_B) 107 | ); 108 | 109 | 110 | Ram_Module Ram_C ( 111 | .clk(clk), 112 | .a_w(a_w), 113 | .b_w(b_w_C), 114 | .a_adbus(a_adbus_C), 115 | .a_data_in(a_data_in_C), 116 | .a_data_out(a_data_out_C), 117 | .b_adbus(b_adbus_C), 118 | .b_data_in(b_data_in_C), 119 | .b_data_out(b_data_out_C) 120 | ); 121 | 122 | 123 | Ram_Module Ram_D ( 124 | .clk(clk), 125 | .a_w(a_w), 126 | .b_w(b_w_D), 127 | .a_adbus(a_adbus_D), 128 | .a_data_in(a_data_in_D), 129 | .a_data_out(a_data_out_D), 130 | .b_adbus(b_adbus_D), 131 | .b_data_in(b_data_in_D), 132 | .b_data_out(b_data_out_D) 133 | ); 134 | always @(posedge clk)begin 135 | if (a_w && a_adbus == 4'b0001) begin 136 | command1 <= a_data_in[3:0]; 137 | end 138 | else 139 | command1<=b_command; 140 | 141 | 142 | end 143 | endmodule 144 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_data_swaping_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul and Deepak 5 | // 6 | // Create Date: 02:49:20 09/15/2014 7 | // Design Name: 8 | // Module Name: Ram_data_swaping_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_data_swaping_module#( 22 | parameter Data=255, 23 | parameter Addr =2)( 24 | input wire clk, 25 | input wire [Addr:0] read_addr, 26 | input wire [Addr:0] write_addr, 27 | input wire [1:0] numbr_of_chunk, 28 | 29 | input wire select_Ram_C_Or_D, 30 | input wire select_Ram_A_Or_B, 31 | 32 | ///THis pin gave command to DMA to swap data 33 | output reg select_Ram_C_DMA, 34 | output reg select_Ram_D_DMA, 35 | 36 | output reg b_w_A, 37 | output reg [Addr:0] b_adbus_A, 38 | 39 | output reg b_w_B, 40 | output reg [Addr:0] b_adbus_B, 41 | 42 | output reg [Addr:0] b_adbus_C, 43 | 44 | output reg [Addr:0] b_adbus_D, 45 | 46 | output reg interupt, 47 | input wire [3:0] command, 48 | output reg cmd_swap 49 | ); 50 | //select_Ram_C_Or_D 1:C_Ram 0:D_Ram 51 | //select_Ram_A_Or_B 1:A_Ram 0:B_Ram 52 | initial begin 53 | //swap<=4'hf; 54 | cmd_swap<=1'h0; 55 | interupt<=1'h0; 56 | select_Ram_D_DMA<=1'h0; 57 | select_Ram_C_DMA<=1'h0; 58 | end 59 | reg [3:0] swap; 60 | always @(posedge clk) begin 61 | 62 | if(command==4'h5)begin 63 | swap<=3'h1; 64 | cmd_swap<=1'h1; 65 | end 66 | 67 | case (swap) 68 | 69 | 4'h1:begin 70 | cmd_swap<=1'h1; 71 | swap<=4'h2; 72 | b_adbus_C<=read_addr; 73 | b_adbus_D<=read_addr; 74 | end 75 | 76 | 4'h2:begin 77 | swap<=4'h3; 78 | 79 | end 80 | 81 | 4'h3:begin 82 | if(numbr_of_chunk[1]) 83 | swap<=4'h4; 84 | else begin 85 | swap<=4'h7; 86 | 87 | end 88 | if(select_Ram_C_Or_D) begin 89 | select_Ram_C_DMA<=1'h1; 90 | select_Ram_D_DMA<=1'h0; 91 | end 92 | else begin 93 | select_Ram_C_DMA<=1'h0; 94 | select_Ram_D_DMA<=1'h1; 95 | b_adbus_C<=read_addr-1'h1; 96 | end 97 | if(select_Ram_A_Or_B)begin 98 | b_w_A<=1'h1; 99 | b_w_B<=1'h0; 100 | b_adbus_A<=write_addr; 101 | end 102 | else begin 103 | b_w_B<=1'h1; 104 | b_w_A<=1'h0; 105 | b_adbus_B<=write_addr; 106 | end 107 | end 108 | 109 | 4'h4:begin 110 | if(!select_Ram_C_Or_D) begin 111 | select_Ram_C_DMA<=1'h1; 112 | select_Ram_D_DMA<=1'h0; 113 | end 114 | else begin 115 | 116 | select_Ram_C_DMA<=1'h0; 117 | select_Ram_D_DMA<=1'h1; 118 | end 119 | if(select_Ram_A_Or_B)begin 120 | b_w_B<=1'h0; 121 | b_w_A<=1'h1; 122 | b_adbus_A<=write_addr-1'h1; 123 | 124 | end 125 | else begin 126 | b_w_A<=1'h0; 127 | b_w_B<=1'h1; 128 | b_adbus_B<=write_addr-1'h1; 129 | end 130 | 131 | if(numbr_of_chunk[0]) 132 | swap<=4'h5; 133 | else begin 134 | swap<=4'h7; 135 | interupt<=1'h1; 136 | end 137 | if(select_Ram_C_Or_D) 138 | b_adbus_C<=read_addr-1'h1; 139 | else 140 | b_adbus_D<=read_addr-1'h1; 141 | end 142 | 143 | 4'h5:begin 144 | swap<=4'h6; 145 | end 146 | 147 | 4'h6:begin 148 | swap<=4'h7; 149 | //interupt<=1'h1; 150 | if(select_Ram_C_Or_D) begin 151 | select_Ram_C_DMA<=1'h1; 152 | select_Ram_D_DMA<=1'h0; 153 | end 154 | else begin 155 | select_Ram_C_DMA<=1'h0; 156 | select_Ram_D_DMA<=1'h1; 157 | end 158 | if(select_Ram_A_Or_B)begin 159 | b_w_B<=1'h0; 160 | b_w_A<=1'h1; 161 | b_adbus_A<=write_addr-2'h2; 162 | end 163 | 164 | else begin 165 | b_w_A<=1'h0; 166 | b_w_B<=1'h1; 167 | b_adbus_B<=write_addr-2'h2; 168 | end 169 | end 170 | 171 | 4'h7:begin 172 | swap<=4'h8; 173 | interupt<=1'h1; 174 | end 175 | 176 | 177 | 4'h8:begin 178 | interupt<=1'h0; 179 | cmd_swap<=1'h0; 180 | b_w_B<=1'h0; 181 | b_w_A<=1'h0; 182 | end 183 | endcase 184 | end 185 | endmodule 186 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_interface_scalar_mul.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul 5 | // 6 | // Create Date: 05:42:12 01/01/2009 7 | // Design Name: 8 | // Module Name: Outer_Ram_interface 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_interface_scalar_mul#( 22 | parameter Data=256, 23 | parameter Addr=5, 24 | parameter command_len=1) 25 | ( 26 | input wire clk, 27 | //interfacing of Ram for taking Data from outside 28 | input wire a_w, 29 | input wire [Addr:0] a_adbus, 30 | input wire [(Data-1):0] a_data_in, 31 | output wire [(Data-1):0] a_data_out, 32 | //interfacing of Ram with inner module 33 | input wire b_w, 34 | input wire [Addr:0] b_adbus, //address bus 35 | input wire [(Data-1):0] b_data_in, 36 | output wire [(Data-1):0] b_data_out 37 | ); 38 | 39 | 40 | 41 | 42 | Ram_module_for_scalar_mul Ram_module_for_scalar_mul ( 43 | .clk(clk), 44 | .a_w(a_w), 45 | .b_w(b_w), 46 | .a_adbus(a_adbus), 47 | .a_data_in(a_data_in), 48 | .a_data_out(a_data_out), 49 | .b_adbus(b_adbus), 50 | .b_data_in(b_data_in), 51 | .b_data_out(b_data_out) 52 | ); 53 | 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:58:55 10/14/2014 7 | // Design Name: 8 | // Module Name: Ram_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_Module#( 22 | parameter DATA = 256, 23 | parameter ADDR = 3)( 24 | input clk, 25 | input a_w, 26 | input b_w, 27 | input wire [(ADDR-1):0] a_adbus, 28 | input wire [(DATA-1):0] a_data_in, 29 | output reg [(DATA-1):0] a_data_out, 30 | input wire [(ADDR-1):0] b_adbus, 31 | input wire [(DATA-1):0] b_data_in, 32 | output reg [(DATA-1):0] b_data_out 33 | ); 34 | 35 | 36 | reg [(DATA-1):0]memory [0:7],b_data_out1,a_data_out1; 37 | 38 | //assign a_data_out=a_data_out1; 39 | //assign b_data_out=b_data_out1; 40 | 41 | always @(posedge clk) begin 42 | if( a_w ) begin 43 | memory[a_adbus] <= a_data_in; 44 | end 45 | a_data_out<=memory[a_adbus]; 46 | end 47 | 48 | always @(posedge clk) begin 49 | if( b_w ) begin 50 | memory[b_adbus] <= b_data_in; 51 | end 52 | b_data_out<=memory[b_adbus]; 53 | 54 | end//end of always module 55 | 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_module.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:58:55 10/14/2014 7 | // Design Name: 8 | // Module Name: Ram_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_Module #( 22 | parameter DATA = 256, 23 | parameter ADDR = 3)( 24 | input clk, 25 | input a_w, 26 | input b_w, 27 | input wire [(ADDR-1):0] a_adbus, 28 | input wire [(DATA-1):0] a_data_in, 29 | output reg [(DATA-1):0] a_data_out, 30 | input wire [(ADDR-1):0] b_adbus, 31 | input wire [(DATA-1):0] b_data_in, 32 | output reg [(DATA-1):0] b_data_out 33 | ); 34 | 35 | 36 | reg [(DATA-1):0]memory [0:7],b_data_out1,a_data_out1; 37 | 38 | //assign a_data_out=a_data_out1; 39 | //assign b_data_out=b_data_out1; 40 | initial begin 41 | $dumpfile("test.vcd"); 42 | $dumpvars(); 43 | end 44 | 45 | always @(posedge clk) begin 46 | if( a_w ) begin 47 | memory[a_adbus] <= a_data_in; 48 | end 49 | a_data_out<=memory[a_adbus]; 50 | end 51 | 52 | always @(posedge clk) begin 53 | if( b_w ) begin 54 | memory[b_adbus] <= b_data_in; 55 | end 56 | b_data_out<=memory[b_adbus]; 57 | 58 | end//end of always module 59 | 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_module_scalar_mul.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 11:55:45 10/14/2014 8 | // Design Name: 9 | // Module Name: Ram_module_1 10 | // Project Name: 11 | // Target Devices: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | module Ram_module_for_scalar_mul#( 23 | parameter DATA = 256, 24 | parameter ADDR = 6)( 25 | input clk, 26 | input a_w, 27 | input b_w, 28 | input wire [(ADDR-1):0] a_adbus, 29 | input wire [(DATA-1):0] a_data_in, 30 | output reg [(DATA-1):0] a_data_out, 31 | input wire [(ADDR-1):0] b_adbus, 32 | input wire [(DATA-1):0] b_data_in, 33 | output reg [(DATA-1):0] b_data_out 34 | ); 35 | 36 | 37 | reg [(DATA-1):0]memory [0:41]; 38 | //assign a_data_out=a_data_out1; 39 | //assign b_data_out=b_data_out1; 40 | 41 | always @(posedge clk) begin 42 | if( a_w ) begin 43 | memory[a_adbus] <= a_data_in; 44 | end 45 | a_data_out<=memory[a_adbus]; 46 | end 47 | 48 | always @(posedge clk) begin 49 | if( b_w ) begin 50 | memory[b_adbus] <= b_data_in; 51 | end 52 | b_data_out<=memory[b_adbus]; 53 | 54 | end//end of always module 55 | 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_transfer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul 5 | // 6 | // Create Date: 13:18:11 09/22/2014 7 | // Design Name: 8 | // Module Name: Ram_data_transfer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_data_transfer#( 22 | parameter Data=255)( 23 | 24 | input wire clk, 25 | //Port of 1 Ram outer Ram 26 | output reg w_RAM, 27 | output reg [5:0] adbus_RAM, 28 | output reg [Data:0] data_in_RAM, 29 | input wire [Data:0] data_out_RAM, 30 | 31 | //port f 2nd Ram inner Ram 32 | output reg w_ECC, 33 | output reg [5:0] adbus_ECC, 34 | output reg [Data:0] data_in_ECC, 35 | input wire [Data:0] data_out_ECC, 36 | 37 | 38 | input wire read_write_command, //command for reading from 1 Ram or 2 Ram 39 | 40 | input wire [5:0] read_address, //Read Address where to read from 41 | input wire [5:0] write_address, //Write Addree where to write from 42 | input wire [1:0] no_of_chunks, //Number of chunks to be write to anothr Ram 43 | input wire command, //command to perform or not transfer 44 | output reg interupt //generate interupt on completi 45 | ); 46 | 47 | reg [3:0] fsm; 48 | 49 | initial begin 50 | interupt<=1'h0; 51 | //transfer_running <= 1'h0; 52 | end 53 | 54 | always @(posedge clk)begin 55 | if (command) begin 56 | fsm<=4'h1; 57 | //transfer_running <= 1'h1; 58 | end 59 | 60 | case (fsm) 61 | 4'h1:begin 62 | 63 | 64 | fsm<=4'h2; 65 | if (read_write_command)begin //read 66 | adbus_ECC<=read_address; 67 | end 68 | else begin 69 | adbus_RAM<=read_address; 70 | end 71 | end 72 | 73 | 4'h2:begin 74 | fsm<=4'h3; 75 | 76 | end 77 | 78 | 4'h3:begin 79 | if(no_of_chunks[1]) begin 80 | fsm <= 4'h4; 81 | end 82 | else begin 83 | fsm<=4'h9; 84 | interupt<=1'h1; 85 | end 86 | if (read_write_command) begin //WRITE 87 | w_RAM<=1'h1; 88 | data_in_RAM<=data_out_ECC; 89 | adbus_RAM<=write_address; 90 | end 91 | else begin 92 | w_ECC<=1'h1; 93 | data_in_ECC<=data_out_RAM; 94 | adbus_ECC<=write_address; 95 | end 96 | 97 | 98 | if (read_write_command)begin //read 99 | if(read_address[5]) 100 | adbus_ECC<=(read_address-4'h8)-1'h1; 101 | else 102 | adbus_ECC<=read_address+4'h8; 103 | end 104 | else begin 105 | adbus_RAM<=read_address+1'h1; 106 | end 107 | end 108 | 109 | 4'h4:begin 110 | fsm<=4'h5; 111 | end 112 | 113 | 4'h5:begin 114 | fsm<=4'h6; 115 | if (read_write_command) begin //WRITE 116 | data_in_RAM<=data_out_ECC; 117 | adbus_RAM<=write_address+1'h1; 118 | end 119 | else begin 120 | data_in_ECC<=data_out_RAM; 121 | adbus_ECC<=write_address-1'h1; 122 | end 123 | 124 | 125 | if (read_write_command)begin //read 126 | adbus_ECC<=read_address-1'h1; 127 | end 128 | else begin 129 | adbus_RAM<=read_address+2'h2; 130 | end 131 | end 132 | 133 | 4'h6:begin 134 | 135 | if(no_of_chunks[0]) begin 136 | fsm <= 4'h8; 137 | end 138 | else begin 139 | fsm<=4'h9; 140 | interupt<=1'h1; 141 | end 142 | 143 | 144 | end 145 | 146 | 4'h8:begin 147 | fsm<=4'h9; 148 | interupt<=1'h1; 149 | if (read_write_command)begin //write 150 | data_in_RAM<=data_out_ECC; 151 | adbus_RAM<=write_address+2'h2; 152 | end 153 | else begin 154 | data_in_ECC<=data_out_RAM; 155 | adbus_ECC<=write_address+2'h2; 156 | end 157 | end 158 | 159 | 160 | 161 | 4'h9:begin 162 | w_ECC<=1'h0; 163 | w_RAM<=1'h0; 164 | interupt<=1'h0; 165 | end 166 | 167 | endcase 168 | 169 | end 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Ram_transfer_scalar_mul.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul 5 | // 6 | // Create Date: 13:18:11 09/22/2014 7 | // Design Name: 8 | // Module Name: Ram_data_transfer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Ram_transfer_scalar_mul#( 22 | parameter Data=255)( 23 | 24 | input wire clk, 25 | //Port of 1 Ram outer Ram 26 | output reg b_w, 27 | output reg [5:0] b_adbus, 28 | output reg [Data:0] b_data_in, 29 | input wire [Data:0] b_data_out, 30 | 31 | //port f 2nd Ram inner Ram 32 | output reg a_w, 33 | output reg [5:0] a_adbus, 34 | output reg [Data:0] a_data_in, 35 | input wire [Data:0] a_data_out, 36 | 37 | input wire read_write_command, //command for reading from 1 Ram or 2 Ram 38 | 39 | input wire [5:0] read_address, //Read Address where to read from 40 | input wire [5:0] write_address, //Write Addree where to write from 41 | input wire [1:0] no_of_chunks, //Number of chunks to be write to anothr Ram 42 | input wire command_transfer, //command to perform or not transfer 43 | output reg interupt_transfer, //generate interupt on completion 44 | output reg transfer_running 45 | //???????????????? 46 | 47 | ); 48 | 49 | reg [3:0] fsm; 50 | 51 | 52 | initial begin 53 | interupt_transfer<=1'h0; 54 | transfer_running <= 1'h0; 55 | end 56 | 57 | always @(posedge clk)begin 58 | 59 | 60 | if (command_transfer)begin 61 | fsm <= 4'h1; 62 | end 63 | 64 | case (fsm) 65 | 4'h1:begin 66 | transfer_running <= 1'h1; 67 | fsm<=4'h2; 68 | if (read_write_command)begin //read 69 | a_adbus<=read_address; 70 | end 71 | else begin 72 | b_adbus<=read_address; 73 | end 74 | end 75 | 76 | 4'h2:begin 77 | fsm<=4'h3; 78 | if (read_write_command)begin //read 79 | a_adbus<=read_address+1'h1; 80 | end 81 | else begin 82 | b_adbus<=read_address+1'h1; 83 | end 84 | end 85 | 86 | 4'h3:begin 87 | if(no_of_chunks[1]) begin 88 | fsm <= 4'h4; 89 | end 90 | else begin 91 | fsm<=4'h7; 92 | interupt_transfer<=1'h1; 93 | end 94 | if (read_write_command) begin //WRITE 95 | b_w<=1'h1; 96 | b_data_in<=a_data_out; 97 | b_adbus<=write_address; 98 | end 99 | 100 | else begin 101 | a_w<=1'h1; 102 | a_data_in<=b_data_out; 103 | a_adbus<=write_address; 104 | end 105 | end 106 | 107 | 4'h4:begin 108 | fsm<=4'h5; 109 | if (read_write_command) begin //WRITE 110 | b_data_in<=a_data_out; 111 | b_adbus<=write_address+1'h1; 112 | end 113 | else begin 114 | a_data_in<=b_data_out; 115 | a_adbus<=write_address+1'h1; 116 | end 117 | 118 | 119 | if (read_write_command)begin //read 120 | a_adbus<=read_address+2'h2; 121 | end 122 | else begin 123 | b_adbus<=read_address+2'h2; 124 | end 125 | end 126 | 127 | 4'h5:begin 128 | 129 | if(no_of_chunks[0]) begin 130 | fsm <= 4'h6; 131 | end 132 | else begin 133 | fsm<=4'h7; 134 | interupt_transfer<=1'h1; 135 | end 136 | 137 | 138 | end 139 | 140 | 4'h6:begin 141 | fsm<=4'h7; 142 | interupt_transfer<=1'h1; 143 | if (read_write_command)begin //write 144 | b_data_in<=a_data_out; 145 | b_adbus<=write_address+2'h2; 146 | end 147 | else begin 148 | a_data_in<=b_data_out; 149 | a_adbus<=write_address+2'h2; 150 | end 151 | end 152 | 153 | 4'h7:begin 154 | a_w<=1'h0; 155 | b_w<=1'h0; 156 | interupt_transfer<=1'h0; 157 | //transfer_running<=1'h0; 158 | fsm <= 4'h8; 159 | end 160 | 161 | endcase 162 | 163 | end 164 | 165 | endmodule 166 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Square_571.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:24:00 08/21/2014 7 | // Design Name: 8 | // Module Name: Square_571 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | /*Input from Port A and Output to Port C and Port D alternatively*/ 23 | 24 | 25 | module Square_571#( 26 | parameter ADDR = 3 27 | )( 28 | output reg [2:0] b_adbus_A, 29 | output reg byte_pos_A, 30 | 31 | output reg b_w_C, 32 | output reg [(ADDR-1):0] b_adbus_C, 33 | output reg byte_pos_C, 34 | 35 | 36 | output reg b_w_D, 37 | output reg [(ADDR-1):0] b_adbus_D, 38 | 39 | input wire clk, 40 | input wire [2:0] start_addr, 41 | input wire[3:0] command, 42 | output reg cmd_sqr, 43 | 44 | output reg [2:0] select_line, 45 | output reg interupt, 46 | input wire [9:0] Data_len_Polynomial 47 | ); 48 | 49 | reg [3:0] Sqr; 50 | reg [9:0] Poly_len,Poly_chunk; 51 | 52 | initial begin 53 | cmd_sqr<=1'h0; 54 | select_line=3'h2; 55 | interupt<=1'h0; 56 | end 57 | 58 | 59 | always @(posedge clk)begin 60 | if (command == 4'b010)begin 61 | Sqr <= 4'h2; 62 | end 63 | 64 | case (Sqr) 65 | 66 | 4'h2:begin 67 | cmd_sqr<=1'h1; 68 | Sqr <= 4'h3; 69 | b_adbus_A <= start_addr-((Data_len_Polynomial/9'h100)+1'h1); 70 | byte_pos_A <= 1'h0; 71 | Poly_len<=(Data_len_Polynomial/8'h80)+1'h1; 72 | Poly_chunk<=(Data_len_Polynomial/256)+1'h1; 73 | end 74 | 75 | 4'h3:begin 76 | //write_addr<=start_addr-Poly_chunk; 77 | if(Poly_len%2'h2==0)begin 78 | b_w_D <=1; 79 | b_adbus_D <=start_addr-Poly_chunk; 80 | byte_pos_C<=1'h1; 81 | end 82 | else begin 83 | b_w_C <=1; 84 | b_adbus_C <=start_addr-Poly_chunk; 85 | byte_pos_C<=1'h0; 86 | end 87 | 88 | if(Poly_len==4'h1) begin //check condition whether to perform further squaring or not depending upon poly len 89 | Sqr<=4'hc; //go to C to genearte interupt 90 | interupt<=1'h1; 91 | end 92 | else 93 | Sqr <= 4'h4; 94 | end 95 | 96 | //Reading Msb 97 | 4'h4:begin 98 | b_w_D<=1'h0; 99 | b_w_C<=1'h0; 100 | byte_pos_A <= 2'h1; 101 | Sqr <= 4'h5; 102 | end 103 | 104 | 105 | 4'h5:begin 106 | if(Poly_len%2==0)begin 107 | b_w_C <=1; 108 | b_adbus_C <=start_addr-Poly_chunk; 109 | byte_pos_C<=1'h0; 110 | end 111 | else begin 112 | b_w_D <=1; 113 | b_adbus_D <=start_addr-Poly_chunk+1'h1; 114 | byte_pos_C<=1'h1; 115 | end 116 | Poly_chunk<=Poly_chunk-1'h1; 117 | if(Poly_len==2'h2) begin 118 | Sqr<=4'hc; 119 | interupt<=1'h1; 120 | end 121 | else begin 122 | Sqr <= 4'h6; 123 | b_adbus_A <= start_addr-(Poly_chunk-1'h1); 124 | end 125 | end 126 | 127 | 128 | /*Squaring of 256 done*/ 129 | 130 | 4'h6:begin 131 | b_w_C <=0; 132 | b_w_D <=0; 133 | 134 | byte_pos_A <= 1'h0; 135 | Sqr <= 4'h7; 136 | end 137 | /*Msb Read[255:128]*/ 138 | 139 | 4'h7:begin 140 | if(Poly_len%2==0)begin 141 | b_w_D <=1; 142 | b_adbus_D <=start_addr-Poly_chunk; 143 | byte_pos_C<=1'h1; 144 | end 145 | else begin 146 | b_w_C <=1; 147 | b_adbus_C <=start_addr-Poly_chunk; 148 | byte_pos_C<=1'h0; 149 | end 150 | 151 | if(Poly_len==2'h3) begin 152 | Sqr<=4'hc; 153 | interupt<=1'h1; 154 | end 155 | else 156 | Sqr <= 4'h8; 157 | end 158 | 159 | 4'h8:begin 160 | b_w_D <=1'h0; 161 | b_w_C<=1'h0; 162 | byte_pos_A <= 1'h1; 163 | Sqr <= 4'h9; 164 | 165 | end 166 | 167 | 4'h9:begin 168 | if(Poly_len%2==1)begin 169 | b_w_D <=1; 170 | b_adbus_D <=start_addr-Poly_chunk+1'h1; 171 | byte_pos_C<=1'h1; 172 | end 173 | else begin 174 | b_w_C <=1; 175 | b_adbus_C <=start_addr-Poly_chunk; 176 | byte_pos_C<=1'h0; 177 | end 178 | Poly_chunk<=Poly_chunk-1'h1; 179 | if(Poly_len[2])begin 180 | Sqr<=4'hc; 181 | interupt<=1'h1; 182 | end 183 | else begin 184 | Sqr <= 4'ha; 185 | b_adbus_A <= start_addr-(Poly_chunk-1'h1); 186 | end 187 | end 188 | 189 | 4'ha:begin 190 | b_w_C<=0; 191 | b_w_D<=0; 192 | 193 | byte_pos_A <= 2'h0; 194 | Sqr <= 4'hb; 195 | end 196 | /*Msb Read[255:128]*/ 197 | 198 | 4'hb:begin 199 | Sqr <= 4'hc; 200 | interupt<=1'h1; 201 | b_w_C <=1; 202 | b_adbus_C <= start_addr-Poly_chunk; 203 | byte_pos_C <= 1'h0; 204 | end 205 | 206 | 4'hc:begin 207 | Sqr<=4'hd; 208 | b_w_C<=1'h0; 209 | interupt<=1'h0; 210 | end 211 | 4'hd:begin 212 | cmd_sqr<=1'h0; 213 | end 214 | 215 | endcase 216 | end 217 | 218 | 219 | 220 | 221 | endmodule 222 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Xor_16_bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:39:38 07/24/2014 7 | // Design Name: 8 | // Module Name: Xor_16_bit 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module XOR( 22 | input[7:0] A, 23 | input[7:0] B, 24 | output[7:0] C 25 | ); 26 | 27 | assign C=A^B; 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Xor_192.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:09:30 08/26/2014 7 | // Design Name: 8 | // Module Name: Xor_192 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Xor_256( 22 | input [255:0] A, 23 | input [255:0] B, 24 | output [255:0] Out 25 | ); 26 | 27 | assign Out=A^B; 28 | 29 | 30 | /* 31 | assign Out[7] = A[7]?(B[7]?1'h0:1'h1):1'h0; 32 | assign Out[6] = A[6]?(B[6]?1'h0:1'h1):1'h0; 33 | assign Out[5] = A[5]?(B[5]?1'h0:1'h1):1'h0; 34 | assign Out[4] = A[4]?(B[4]?1'h0:1'h1):1'h0; 35 | assign Out[3] = A[3]?(B[3]?1'h0:1'h1):1'h0; 36 | assign Out[2] = A[2]?(B[2]?1'h0:1'h1):1'h0; 37 | assign Out[1] = A[1]?(B[1]?1'h0:1'h1):1'h0; 38 | assign Out[0] = A[0]?(B[0]?1'h0:1'h1):1'h0; 39 | */ 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Xor_256_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:13:08 09/20/2014 7 | // Design Name: 8 | // Module Name: Xor_256_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Xor_256_module( 22 | input wire [255:0] A, 23 | input wire [255:0] B, 24 | output wire [255:0] C 25 | ); 26 | 27 | assign C = A^B; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Xor_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:31:25 07/21/2014 7 | // Design Name: 8 | // Module Name: Xor_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Xor_module( // 32 slices in 64 and 64 slices in 128 22 | input[135:0] A, 23 | input[135:0] B, 24 | output[135:0] C 25 | ); 26 | 27 | assign C[135:0]=A[135:0]^B[135:0]; 28 | endmodule 29 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Xor_new.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:06:56 09/21/2014 7 | // Design Name: 8 | // Module Name: Sequntial_Xor 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Sequntial_Xor( 22 | 23 | input wire clk, 24 | input wire [3:0] command, 25 | input wire [2:0] start_addr, 26 | 27 | 28 | output reg [2:0] b_adbus_A, 29 | output reg [2:0] b_adbus_B, 30 | 31 | output reg cmd_Xor, 32 | output reg interupt_Xor, 33 | output reg b_w_C, 34 | output reg b_w_D, 35 | 36 | output reg [2:0] b_adbus_C, 37 | output reg [2:0] b_adbus_D, 38 | 39 | output reg [2:0] select_line, 40 | 41 | input wire [9:0] Data_len_Polynomial 42 | ); 43 | 44 | 45 | reg [3:0] fsm; 46 | 47 | initial begin 48 | cmd_Xor<=0; 49 | interupt_Xor<=1'h0; 50 | end 51 | 52 | always @(posedge clk)begin 53 | if(command==4'h6)begin 54 | fsm<=4'h1; 55 | end 56 | case(fsm) 57 | 4'h1:begin 58 | fsm <= 4'h2; 59 | cmd_Xor <= 1; 60 | b_adbus_A <= start_addr-1'h1; //read first 256 61 | b_adbus_B <= start_addr-1'h1; 62 | select_line <= 4'h5; 63 | end 64 | 65 | 4'h2:begin 66 | b_w_C<=1'h1; 67 | b_adbus_C<=start_addr-1'h1; 68 | 69 | if( (Data_len_Polynomial/9'h100) == 2'h0)begin 70 | fsm<=4'h5; 71 | interupt_Xor<=1'h1; 72 | end 73 | else begin 74 | fsm<=4'h3; 75 | b_adbus_A <= start_addr-2'h2; //read second 256 76 | b_adbus_B <= start_addr-2'h2; 77 | end 78 | 79 | end 80 | 81 | 82 | 4'h3:begin 83 | fsm<=4; 84 | b_w_C<=1'h0; 85 | b_w_D<=1'h1; 86 | b_adbus_D<=start_addr-1'h1; 87 | 88 | if( (Data_len_Polynomial/9'h100) == 2'h1)begin 89 | fsm<=4'h5; 90 | interupt_Xor<=1'h1; 91 | end 92 | else begin 93 | fsm<=4'h4; 94 | b_adbus_A <= start_addr-2'h3; //read second 256 95 | b_adbus_B <= start_addr-2'h3; 96 | end 97 | 98 | end 99 | 100 | 4'h4:begin 101 | b_w_D<=1'h0; 102 | b_w_C<=1'h1; 103 | b_adbus_C<=start_addr-2'h2; 104 | fsm<=4'h5; 105 | interupt_Xor<=1; 106 | end 107 | 108 | 4'h5:begin 109 | b_w_C<=1'h0; 110 | interupt_Xor<=1'h0; 111 | fsm<=4'h6; 112 | end 113 | 114 | 115 | 4'h6:begin 116 | cmd_Xor<=1'h0; 117 | end 118 | 119 | endcase 120 | end 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/Xor_new.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:06:56 09/21/2014 7 | // Design Name: 8 | // Module Name: Sequntial_Xor 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Sequntial_Xor( 22 | 23 | input wire clk, 24 | input wire [3:0] command, 25 | input wire [2:0] start_addr, 26 | 27 | 28 | output reg [2:0] b_adbus_A, 29 | output reg [2:0] b_adbus_B, 30 | 31 | output reg cmd_Xor, 32 | output reg interupt_Xor, 33 | output reg b_w_C, 34 | output reg b_w_D, 35 | 36 | output reg [2:0] b_adbus_C, 37 | output reg [2:0] b_adbus_D, 38 | 39 | output reg [2:0] select_line, 40 | 41 | input wire [9:0] Data_len_Polynomial 42 | ); 43 | 44 | 45 | reg [3:0] fsm; 46 | 47 | initial begin 48 | cmd_Xor<=0; 49 | interupt_Xor<=1'h0; 50 | end 51 | 52 | always @(posedge clk)begin 53 | if(command==4'h6)begin 54 | fsm<=4'h1; 55 | end 56 | case(fsm) 57 | 4'h1:begin 58 | fsm <= 4'h2; 59 | cmd_Xor <= 1; 60 | b_adbus_A <= start_addr-1'h1; //read first 256 61 | b_adbus_B <= start_addr-1'h1; 62 | select_line <= 4'h5; 63 | end 64 | 65 | 4'h2:begin 66 | b_w_C<=1'h1; 67 | b_adbus_C<=start_addr-1'h1; 68 | 69 | if( (Data_len_Polynomial/9'h100) == 2'h0)begin 70 | fsm<=4'h5; 71 | interupt_Xor<=1'h1; 72 | end 73 | else begin 74 | fsm<=4'h3; 75 | b_adbus_A <= start_addr-2'h2; //read second 256 76 | b_adbus_B <= start_addr-2'h2; 77 | end 78 | 79 | end 80 | 81 | 82 | 4'h3:begin 83 | fsm<=4; 84 | b_w_C<=1'h0; 85 | b_w_D<=1'h1; 86 | b_adbus_D<=start_addr-1'h1; 87 | 88 | if( (Data_len_Polynomial/9'h100) == 2'h1)begin 89 | fsm<=4'h5; 90 | interupt_Xor<=1'h1; 91 | end 92 | else begin 93 | fsm<=4'h4; 94 | b_adbus_A <= start_addr-2'h3; //read second 256 95 | b_adbus_B <= start_addr-2'h3; 96 | end 97 | 98 | end 99 | 100 | 4'h4:begin 101 | b_w_D<=1'h0; 102 | b_w_C<=1'h1; 103 | b_adbus_C<=start_addr-1'h2; 104 | fsm<=4'h5; 105 | interupt_Xor<=1; 106 | end 107 | 108 | 4'h5:begin 109 | b_w_C<=1'h0; 110 | interupt_Xor<=1'h0; 111 | fsm<=4'h6; 112 | end 113 | 114 | 115 | 4'h6:begin 116 | cmd_Xor<=1'h0; 117 | end 118 | 119 | endcase 120 | end 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/dma_sample_code.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Rahul Yamasani and Deepak Kapoor 5 | // 6 | // Create Date: 10:04:13 08/18/2014 7 | // Design Name: 8 | // Module Name: dma_sample_code 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module dma_module_code#( 22 | parameter DATA = 256, 23 | parameter ADDR = 3, 24 | parameter param=6, 25 | parameter SIZE=64, 26 | parameter MUL=3'b001, 27 | parameter XOR=3'b111, 28 | parameter SQR=3'b010, 29 | parameter REDUCTION =3'b100, 30 | parameter INVERSE =3'b011)( 31 | 32 | input wire clk, 33 | input wire a_w, 34 | input wire [5:0] a_adbus, 35 | input wire [(DATA-1):0] a_data_in, 36 | output wire [(DATA-1):0] a_data_out, 37 | 38 | input wire b_w_A, 39 | input wire [(ADDR-1):0] b_adbus_A, 40 | input wire [1:0] byte_pos_A, 41 | output wire [(DATA-1):0] b_data_out_A, 42 | input wire [(DATA-1):0] b_data_in_A, 43 | 44 | input wire b_w_B, 45 | input wire [(ADDR-1):0] b_adbus_B, 46 | input wire [1:0] byte_pos_B, 47 | input wire [(DATA-1):0] b_data_in_B, 48 | output wire [(DATA-1):0] b_data_out_B, 49 | 50 | 51 | input wire b_w_C, 52 | input wire [(ADDR-1):0] b_adbus_C, 53 | input wire [1:0] byte_pos_C, 54 | output wire [(DATA-1):0] b_data_out_C, 55 | input wire [(DATA-1):0] b_data_in_C, 56 | 57 | input wire b_w_D, 58 | input wire [(ADDR-1):0] b_adbus_D, 59 | input wire [1:0] byte_pos_D, 60 | input wire [(DATA-1):0] b_data_in_D, 61 | output wire [(DATA-1):0] b_data_out_D, 62 | 63 | input wire [135:0] A1, //change 64 | input wire [135:0] B1, 65 | input wire [2:0] select_line, 66 | 67 | output [135:0] C_Out1, 68 | output [127:0] D_Out1, 69 | 70 | output wire [3:0] command, 71 | input wire [3:0] b_command, 72 | 73 | input wire cmd_sqr, 74 | input wire cmd_mul, 75 | input wire cmd_red, 76 | input wire cmd_swap, 77 | input wire cmd_inv, 78 | input wire cmd_xor, 79 | 80 | input wire [2:0] start_addr, 81 | input wire select_Ram_C, 82 | input wire select_Ram_D 83 | ); 84 | 85 | wire [255:0] A,B; 86 | wire [135:0] C_Out; 87 | wire [127:0] D_Out; 88 | wire [255:0] b_data_in_C1,b_data_in_D1,b_data_in_A1,b_data_in_B1; 89 | reg [9:0] count; 90 | reg [2:0] fsm,b_adbus_A1; 91 | wire [2:0] b_adbus_A2; //adress bus goes into Ram_interface 92 | 93 | 94 | 95 | //Ram_interface 96 | Ram_Interface_Module Ram_interface ( 97 | .clk(clk), 98 | .a_w(a_w), 99 | .a_adbus(a_adbus), 100 | .a_data_in(a_data_in), 101 | .a_data_out(a_data_out), 102 | .b_w_A(b_w_A), 103 | .b_adbus_A(b_adbus_A2), 104 | .b_data_in_A(b_data_in_A1), 105 | .b_data_out_A(b_data_out_A), 106 | .b_w_B(b_w_B), 107 | .b_adbus_B(b_adbus_B), 108 | .b_data_in_B(b_data_in_B1), 109 | .b_data_out_B(b_data_out_B), 110 | .b_w_C(b_w_C), 111 | .b_adbus_C(b_adbus_C), 112 | .b_data_in_C(b_data_in_C1), 113 | .b_data_out_C(b_data_out_C), 114 | .b_w_D(b_w_D), 115 | .b_adbus_D(b_adbus_D), 116 | .b_data_in_D(b_data_in_D1), 117 | .b_data_out_D(b_data_out_D), 118 | .b_command(b_command), 119 | .command(command) 120 | 121 | ); 122 | 123 | lower_bit_implementation lower_bit ( 124 | .A(A), 125 | .B(B), 126 | .select_line(select_line), 127 | .C_Out(C_Out), 128 | .D_Out(D_Out) 129 | ); 130 | 131 | assign A =(cmd_sqr && byte_pos_A==2'h1)?({128'h0,b_data_out_A[255:128]}): 132 | (cmd_sqr && byte_pos_A == 2'h0)?({128'h0,b_data_out_A[127:0]}): 133 | (cmd_xor)?b_data_out_A: 134 | (cmd_mul||cmd_red)?{120'h0,A1}:255'hz; 135 | 136 | assign B = (cmd_mul||cmd_red)?{120'h0,B1}: 137 | (cmd_xor)?b_data_out_B:255'hz; 138 | 139 | assign C_Out1 = C_Out; //C_Out is MSB 140 | assign D_Out1 = D_Out; //D_Out1 is LSb 141 | 142 | 143 | assign b_data_in_C1 =(cmd_sqr)?({C_Out[127:0],D_Out}): 144 | (cmd_xor?({C_Out[127:0],D_Out}): 145 | ((cmd_mul||cmd_red)?b_data_in_C:256'hz)); 146 | 147 | 148 | assign b_data_in_D1 =(cmd_sqr)?({C_Out[127:0],D_Out}): 149 | (cmd_xor?({C_Out[127:0],D_Out}): 150 | ((cmd_mul||cmd_red)?b_data_in_D:256'hz)); 151 | 152 | 153 | 154 | assign b_data_in_A1= (cmd_swap && select_Ram_C)?b_data_out_C: 155 | ((cmd_swap && select_Ram_D)?b_data_out_D:b_data_in_A); 156 | 157 | assign b_data_in_B1= (cmd_swap && select_Ram_C)?b_data_out_C: 158 | ((cmd_swap && select_Ram_D)?b_data_out_D:b_data_in_B); 159 | 160 | 161 | assign b_adbus_A2= (cmd_inv && (!cmd_sqr && !cmd_mul && !cmd_swap))?b_adbus_A1:b_adbus_A; 162 | 163 | 164 | endmodule 165 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/ideal_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: Rahul Yamasani 5 | // 6 | // Create Date: 12:45:17 08/21/2014 7 | // Design Name: 8 | // Module Name: ideal_module (modified) 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module sequential_state_module#( 22 | parameter DATA=256, 23 | parameter SQR = 3'b010, 24 | parameter MUL = 3'b001, 25 | parameter RED = 3'b100 26 | )( 27 | input wire clk, 28 | input wire a_w, 29 | input wire [5:0] a_adbus, 30 | input wire [(DATA-1):0] a_data_in, 31 | output wire [(DATA-1):0] a_data_out, 32 | input wire [3:0] b_command, 33 | input wire [2:0] start_addr, 34 | input wire [2:0] write_addr, 35 | 36 | output wire interupt_sqr, 37 | output wire interupt_red, 38 | output wire interupt_swap, 39 | output wire interupt_mul, 40 | output wire interupt_Xor, 41 | 42 | 43 | input wire cmd_inv, 44 | input wire select_Ram_C_Or_D, 45 | input wire select_Ram_A_Or_B, 46 | 47 | input wire [1:0] numbr_of_chunk, 48 | output wire [3:0] command , 49 | 50 | input wire [9:0] Data_len_Polynomial, 51 | input wire [63:0] Data_Polynomial 52 | ); 53 | 54 | wire [1:0] byte_pos_A,byte_pos_B,byte_pos_C,byte_pos_D; 55 | wire [2:0] b_adbus_A,b_adbus_B,b_adbus_C,b_adbus_D; 56 | wire [(DATA-1):0] b_data_out_A,b_data_out_B,b_data_out_C,b_data_out_D; 57 | 58 | wire [127:0] Core_Lsb,Data_64_2_Chunk; 59 | wire [135:0] Core_Msb; 60 | wire [2:0] select_line; 61 | 62 | 63 | 64 | wire [(DATA-1):0] C_data_in1,D_data_in1,A_data_in1,B_data_in1; 65 | wire [135:0] Core_A,Core_B; 66 | reg byte_pos_Reduction; 67 | wire cmd_sqr,cmd_red,cmd_mul; 68 | wire b_w_A,b_w_B,b_w_C,b_w_D; 69 | 70 | dma_module_code dma ( 71 | 72 | .clk(clk), 73 | .a_w(a_w), 74 | .a_adbus(a_adbus), 75 | .a_data_in(a_data_in), 76 | .a_data_out(a_data_out), 77 | 78 | .b_w_A(b_w_A), 79 | .b_adbus_A(b_adbus_A), 80 | .byte_pos_A(byte_pos_A), 81 | .b_data_out_A(b_data_out_A), 82 | .b_data_in_A(A_data_in1), 83 | 84 | .b_w_B(b_w_B), 85 | .b_adbus_B(b_adbus_B), 86 | .byte_pos_B(byte_pos_B), 87 | .b_data_out_B(b_data_out_B), 88 | .b_data_in_B(B_data_in1), 89 | 90 | .b_w_C(b_w_C), 91 | .b_adbus_C(b_adbus_C), 92 | .byte_pos_C(byte_pos_C), 93 | .b_data_in_C(C_data_in1), 94 | .b_data_out_C(b_data_out_C), 95 | 96 | .b_w_D(b_w_D), 97 | .b_adbus_D(b_adbus_D), 98 | .byte_pos_D(byte_pos_D), 99 | .b_data_in_D(D_data_in1), 100 | .b_data_out_D(b_data_out_D), 101 | 102 | .start_addr(start_addr), 103 | /*core variable*/ 104 | .A1(Core_A), 105 | .B1(Core_B), 106 | .select_line(select_line), 107 | .C_Out1(Core_Msb), 108 | .D_Out1(Core_Lsb), 109 | 110 | .command(command), 111 | .b_command(b_command), //address bus for command 112 | 113 | .cmd_red(cmd_red), 114 | .cmd_mul(cmd_mul), 115 | .cmd_sqr(cmd_sqr), 116 | .cmd_swap(cmd_swap), 117 | .cmd_inv(cmd_inv), 118 | .cmd_xor(cmd_Xor), 119 | 120 | .select_Ram_C(select_Ram_C_DMA), 121 | .select_Ram_D(select_Ram_D_DMA) 122 | ); 123 | 124 | wire [2:0] b_adbus_A_sqr,b_adbus_C_sqr,b_adbus_D_sqr; 125 | wire byte_pos_A_sqr,byte_pos_C_sqr; 126 | wire b_w_C_sqr,b_w_D_sqr; 127 | wire [2:0] select_line_sqr; 128 | 129 | 130 | Square_571 sequential_square ( 131 | .clk(clk), 132 | .b_adbus_A(b_adbus_A_sqr), 133 | .byte_pos_A(byte_pos_A_sqr), 134 | 135 | .b_w_C(b_w_C_sqr), 136 | .b_adbus_C(b_adbus_C_sqr), 137 | .byte_pos_C(byte_pos_C_sqr), 138 | 139 | .b_w_D(b_w_D_sqr), 140 | .b_adbus_D(b_adbus_D_sqr), 141 | 142 | .command(command), 143 | .cmd_sqr(cmd_sqr), 144 | 145 | .start_addr(start_addr), 146 | .select_line(select_line_sqr), 147 | .interupt(interupt_sqr), 148 | 149 | .Data_len_Polynomial (Data_len_Polynomial) //register for length of a polynomial 150 | ); 151 | 152 | 153 | wire [2:0] b_adbus_B_red,b_adbus_C_red,b_adbus_D_red; 154 | wire [1:0] byte_pos_C_red; 155 | wire [255:0] b_data_in_C_red,b_data_in_D_red; 156 | wire b_w_C_red,b_w_D_red; 157 | wire [135:0] A1_red,B1_red; 158 | wire [2:0] select_line_red; 159 | 160 | reduction_256_module seq_reduction ( 161 | .Data_Polynomial(Data_Polynomial), 162 | 163 | .b_w_C(b_w_C_red), 164 | .b_adbus_C(b_adbus_C_red), 165 | .b_data_out_C(b_data_out_C), 166 | 167 | .b_data_in_C(b_data_in_C_red), 168 | .b_w_D(b_w_D_red), 169 | .b_adbus_D(b_adbus_D_red), 170 | .b_data_in_D(b_data_in_D_red), 171 | .b_data_out_D(b_data_out_D), 172 | 173 | .clk(clk), 174 | .start_addr(start_addr), 175 | 176 | .A1(A1_red), 177 | .B1(B1_red), 178 | .select_line(select_line_red), 179 | .D_Out1(Core_Msb), 180 | .command(command), 181 | .cmd_red(cmd_red), 182 | 183 | .interupt(interupt_red) 184 | ); 185 | 186 | wire [2:0] b_adbus_A_mul,b_adbus_B_mul,b_adbus_C_mul,b_adbus_D_mul; 187 | wire b_w_C_mul,b_w_D_mul; 188 | wire [2:0] select_line_mul; 189 | wire [127:0] A1_mul,B1_mul; 190 | wire [255:0] b_data_in_C_mul,b_data_in_D_mul; 191 | 192 | multiplication_recursive_module seq_multiplication ( 193 | .clk(clk), 194 | .b_data_out_A(b_data_out_A), 195 | .b_data_out_B(b_data_out_B), 196 | 197 | .Mul_A(A1_mul), 198 | .Mul_B(B1_mul), 199 | 200 | .Mul_out_lsb(Core_Lsb), 201 | .Mul_out_msb(Core_Msb[127:0]), 202 | 203 | .command(command), 204 | .cmd_mul(cmd_mul), 205 | 206 | .start_addr(start_addr), 207 | .select_line(select_line_mul), 208 | .b_adbus_A(b_adbus_A_mul), 209 | .b_adbus_B(b_adbus_B_mul), 210 | .b_adbus_C(b_adbus_C_mul), 211 | .b_adbus_D(b_adbus_D_mul), 212 | 213 | .b_data_in_D(b_data_in_D_mul), 214 | .b_data_in_C(b_data_in_C_mul), 215 | 216 | .b_w_C(b_w_C_mul), 217 | .b_w_D(b_w_D_mul), 218 | .interupt(interupt_mul), 219 | .Data_len_Polynomial (Data_len_Polynomial) 220 | ); 221 | 222 | wire [2:0] b_adbus_C_swap,b_adbus_D_swap,b_adbus_A_swap,b_adbus_B_swap; 223 | wire cmd_swap,cmd_Xor; 224 | 225 | Ram_data_swaping_module Ram_swap ( 226 | .clk(clk), 227 | 228 | .read_addr(start_addr), 229 | .write_addr(write_addr), 230 | 231 | .numbr_of_chunk(numbr_of_chunk), 232 | .select_Ram_C_Or_D(select_Ram_C_Or_D), 233 | .select_Ram_A_Or_B(select_Ram_A_Or_B), 234 | 235 | .b_w_A(b_w_A), 236 | .b_adbus_A(b_adbus_A_swap), 237 | 238 | .b_w_B(b_w_B), 239 | .b_adbus_B(b_adbus_B_swap), 240 | 241 | .b_adbus_C(b_adbus_C_swap), 242 | .b_adbus_D(b_adbus_D_swap), 243 | 244 | .interupt(interupt_swap), 245 | .command(command), 246 | .cmd_swap(cmd_swap), 247 | 248 | .select_Ram_D_DMA(select_Ram_D_DMA), 249 | .select_Ram_C_DMA(select_Ram_C_DMA) 250 | //.select_Ram_A_Or_B_DMA(select_Ram_A_Or_B_DMA) 251 | 252 | ); 253 | 254 | 255 | wire b_w_C_Xor,b_w_D_Xor; 256 | wire [2:0] b_adbus_A_Xor,b_adbus_B_Xor,b_adbus_C_Xor,b_adbus_D_Xor; 257 | wire [2:0] select_line_Xor; 258 | wire select_Ram_C_DMA,select_Ram_D_DMA; 259 | 260 | Sequntial_Xor Sequential_Xor ( 261 | .clk(clk), 262 | .command(command), 263 | .start_addr(start_addr), 264 | .b_adbus_A(b_adbus_A_Xor), 265 | .b_adbus_B(b_adbus_B_Xor), 266 | .cmd_Xor(cmd_Xor), 267 | .interupt_Xor(interupt_Xor), 268 | .b_w_C(b_w_C_Xor), 269 | .b_w_D(b_w_D_Xor), 270 | .b_adbus_C(b_adbus_C_Xor), 271 | .b_adbus_D(b_adbus_D_Xor), 272 | .select_line(select_line_Xor), 273 | 274 | .Data_len_Polynomial(Data_len_Polynomial) 275 | ); 276 | 277 | 278 | 279 | 280 | 281 | 282 | assign b_adbus_A = cmd_swap?(b_adbus_A_swap):cmd_sqr?b_adbus_A_sqr:cmd_mul?b_adbus_A_mul: 283 | cmd_Xor?b_adbus_A_Xor:3'hz; 284 | assign byte_pos_A = cmd_sqr?byte_pos_A_sqr:1'hz; 285 | assign b_adbus_B = cmd_swap?b_adbus_B_swap:(cmd_red?b_adbus_B_red:cmd_mul?b_adbus_B_mul: 286 | cmd_Xor?b_adbus_B_Xor:3'hz); 287 | 288 | assign b_w_C = cmd_red?b_w_C_red:cmd_sqr?b_w_C_sqr:cmd_mul?b_w_C_mul: 289 | cmd_Xor?b_w_C_Xor:1'hz; 290 | 291 | assign b_adbus_C = cmd_swap?b_adbus_C_swap:cmd_red?b_adbus_C_red:(cmd_sqr?b_adbus_C_sqr:cmd_mul?b_adbus_C_mul: 292 | cmd_Xor?b_adbus_C_Xor:3'hz); 293 | 294 | assign byte_pos_C = cmd_red?byte_pos_C_red:cmd_sqr?byte_pos_C_sqr:1'hz; 295 | 296 | assign C_data_in1= cmd_red?b_data_in_C_red:cmd_mul?b_data_in_C_mul:256'hz; 297 | 298 | assign b_w_D = cmd_red?b_w_D_red:cmd_sqr?b_w_D_sqr:cmd_mul?b_w_D_mul: 299 | cmd_Xor?b_w_D_Xor:1'hz; 300 | 301 | assign b_adbus_D = cmd_swap?b_adbus_D_swap:(cmd_red?b_adbus_D_red:cmd_sqr?b_adbus_D_sqr:cmd_mul?b_adbus_D_mul: 302 | cmd_Xor?b_adbus_D_Xor:3'hz); 303 | 304 | assign D_data_in1= cmd_red?b_data_in_D_red:cmd_mul?b_data_in_D_mul:256'hz; 305 | 306 | assign Core_A = cmd_red?A1_red:cmd_mul?{4'h0,A1_mul}:136'hz; 307 | 308 | assign Core_B= cmd_red?B1_red:cmd_mul?{4'h0,B1_mul}:136'hz; 309 | 310 | 311 | assign select_line = cmd_red?select_line_red:cmd_sqr?select_line_sqr:cmd_mul?select_line_mul: 312 | cmd_Xor?select_line_Xor:3'hz; 313 | 314 | 315 | 316 | 317 | 318 | 319 | endmodule 320 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/interupt.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:58:55 10/14/2014 7 | // Design Name: 8 | // Module Name: Ram_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module interupt #( 22 | parameter DATA = 256, 23 | parameter ADDR = 3)( 24 | input clk, 25 | input a_w, 26 | input b_w, 27 | input wire [(ADDR-1):0] a_adbus, 28 | input wire [(DATA-1):0] a_data_in, 29 | output reg [(DATA-1):0] a_data_out, 30 | input wire [(ADDR-1):0] b_adbus, 31 | input wire [(DATA-1):0] b_data_in, 32 | output reg [(DATA-1):0] b_data_out, 33 | output reg interupt_write 34 | ); 35 | 36 | 37 | reg [(DATA-1):0]memory [0:7],b_data_out1,a_data_out1; 38 | 39 | reg [4:0] count; 40 | initial begin 41 | $dumpfile("test.vcd"); 42 | $dumpvars(); 43 | interupt_write<=1'h0; 44 | count <= 5'h0; 45 | end 46 | 47 | always @(posedge clk) begin 48 | 49 | count <= count+1'h1; 50 | if(count[4] && !count[0]) 51 | interupt_wire <= 1'h1; 52 | else 53 | interupt_wire <= 1'h0; 54 | if( a_w ) begin 55 | memory[a_adbus] <= a_data_in; 56 | end 57 | a_data_out<=memory[a_adbus]; 58 | end 59 | 60 | always @(posedge clk) begin 61 | if( b_w ) begin 62 | memory[b_adbus] <= b_data_in; 63 | end 64 | b_data_out<=memory[b_adbus]; 65 | 66 | end//end of always module 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/inverse_itoha_tsuji_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: Rahul Yamasani 5 | // 6 | // Create Date: 00:27:56 09/16/2014 7 | // Design Name: 8 | // Module Name: inverse_itoha_tsuji_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module inverse_itoha_tsuji_module( 22 | 23 | input wire clk, 24 | 25 | output reg [2:0] read_addr_inv, 26 | output reg [2:0] write_addr_inv, 27 | 28 | output reg [3:0] b_command, 29 | 30 | input wire [2:0] start_addr, 31 | input wire interupt_sqr, 32 | input wire interupt_red, 33 | input wire interupt_swap, 34 | input wire interupt_mul, 35 | output reg interupt, 36 | output reg select_Ram_C_Or_D, 37 | output reg select_Ram_A_Or_B, 38 | output reg [1:0] numbr_of_chunk, 39 | input wire [3:0] command, 40 | output reg cmd_inv, 41 | 42 | input wire [9:0] Data_len_Polynomial 43 | ); 44 | 45 | reg [4:0] Inv; 46 | reg [10:0] count,len_Reduction_Polynomial; 47 | reg [2:0] var; 48 | 49 | initial begin 50 | cmd_inv<=1'h0; 51 | Inv<=4'h0; 52 | interupt<=1'h0; 53 | select_Ram_A_Or_B<=1'h0; 54 | select_Ram_C_Or_D<=1'h0; 55 | end 56 | 57 | always @(posedge clk)begin 58 | if(command==4'h3)begin //check command is for inverse or not 59 | Inv<=5'h1; //start fsm 60 | end 61 | 62 | 63 | case(Inv) 64 | 5'h1:begin 65 | Inv<=5'h3; 66 | cmd_inv<=1'h1; 67 | read_addr_inv<=start_addr; 68 | b_command<=4'h2; //command for square operation 69 | end 70 | 71 | 5'h3:begin 72 | b_command<=4'h0; 73 | count<=Data_len_Polynomial-2'h2; 74 | len_Reduction_Polynomial<=Data_len_Polynomial; 75 | if(interupt_sqr) 76 | Inv<=5'h4; 77 | end 78 | 79 | 80 | 5'h4:begin 81 | Inv<=5'h5; 82 | b_command<=4'h4; 83 | read_addr_inv<=start_addr-1'h1; //give addr from where reduction start 84 | 85 | end 86 | 87 | 88 | 5'h5:begin 89 | b_command<=5'h0; 90 | numbr_of_chunk<=Data_len_Polynomial/9'h100+1'h1; 91 | var<=Data_len_Polynomial/8'h80; //to decide where to swap data from 92 | if(interupt_red) 93 | Inv<=4'h6; 94 | 95 | end 96 | 97 | 98 | 5'h6:begin //move square data to A Ram 99 | Inv<=5'h7; 100 | b_command<=4'h5; //command for data swapping 101 | write_addr_inv<=start_addr-1'h1; 102 | if((var[1]&&var[0])||var[2])begin 103 | read_addr_inv<=start_addr-2'h2; 104 | end 105 | else 106 | read_addr_inv<=start_addr-1'h1; 107 | 108 | select_Ram_A_Or_B<=1'h1; 109 | if(var[1]^var[0]) 110 | select_Ram_C_Or_D<=1'h0; 111 | else 112 | select_Ram_C_Or_D<=1'h1; 113 | end 114 | 115 | 116 | 5'h7:begin 117 | b_command<=4'h0; 118 | if(interupt_swap) 119 | Inv<=5'h8; 120 | end 121 | 122 | 5'h8:begin 123 | Inv<=5'h9; 124 | b_command<=4'h5; 125 | select_Ram_A_Or_B<=1'h0; 126 | end 127 | 128 | 5'h9:begin //move data to B polynomial 129 | b_command<=4'h0; 130 | if(interupt_swap) 131 | Inv<=5'ha; 132 | end 133 | 134 | 5'ha:begin //calculation of square 135 | 136 | Inv<=5'hb; 137 | b_command<=4'h2; 138 | count<=count-1'h1; 139 | read_addr_inv<=start_addr; 140 | end 141 | 142 | 143 | 5'hb:begin 144 | b_command<=4'h0; 145 | if(interupt_sqr) 146 | Inv<=5'hc; 147 | end 148 | 149 | 150 | 5'hc:begin 151 | Inv<=5'hd; 152 | b_command<=4'h4; 153 | read_addr_inv<=start_addr-1'h1; //give addr from where reduction start 154 | 155 | end 156 | 157 | 158 | 5'hd:begin 159 | b_command<=5'h0; 160 | if(interupt_red) 161 | Inv<=4'he; 162 | 163 | end 164 | 165 | 166 | 5'he:begin //move square data to A Ram 167 | Inv<=5'hf; 168 | b_command<=4'h5; //command for data swapping 169 | write_addr_inv<=start_addr-1'h1; 170 | if((var[1]&&var[0])||var[2]) 171 | read_addr_inv<=start_addr-2'h2; 172 | else 173 | read_addr_inv<=start_addr-1'h1; 174 | 175 | 176 | select_Ram_A_Or_B<=1'h1; 177 | end 178 | 179 | 5'hf:begin 180 | b_command<=4'h0; 181 | if(interupt_swap) 182 | Inv<=5'h10; 183 | end 184 | 185 | 5'h10:begin //multiplication 186 | Inv<=5'h11; 187 | b_command<=4'h1; 188 | read_addr_inv<=start_addr; 189 | end 190 | 191 | 5'h11:begin 192 | b_command<=4'h0; 193 | if(interupt_mul) 194 | Inv<=5'h12; 195 | end 196 | 197 | 5'h12:begin 198 | Inv<=5'h13; 199 | b_command<=4'h4; 200 | read_addr_inv<=start_addr-1'h1; //give addr from where reduction start 201 | 202 | end 203 | 204 | 205 | 5'h13:begin 206 | b_command<=5'h0; 207 | if(interupt_red) 208 | Inv<=5'h14; 209 | 210 | end 211 | 212 | 213 | 5'h14:begin //move mul data to B Ram 214 | Inv<=5'h15; 215 | b_command<=4'h5; //command for data swapping 216 | write_addr_inv<=start_addr-1'h1; 217 | 218 | 219 | if((var[1]&&var[0])||var[2]) 220 | read_addr_inv<=start_addr-2'h2; 221 | else 222 | read_addr_inv<=start_addr-1'h1; 223 | select_Ram_A_Or_B<=1'h0; //result in B 224 | end 225 | 226 | 5'h15:begin 227 | b_command<=4'h0; 228 | if(count==10'h0) begin 229 | Inv<=5'h16; 230 | interupt<=1'h1; 231 | end 232 | 233 | if(interupt_swap) 234 | Inv<=5'ha; 235 | // Inv<=5'h16; 236 | end 237 | 5'h16:begin 238 | cmd_inv<=1'h0; 239 | interupt<=1'h0; 240 | end 241 | 242 | endcase 243 | 244 | 245 | end 246 | endmodule 247 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/lower_bit_implementation.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: Deepak Kapoor 5 | // 6 | // Create Date: 11:43:05 07/23/2014 7 | // Design Name: 8 | // Module Name: lower_bit_implementation 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module lower_bit_implementation#( 24 | parameter param=7, 25 | parameter SIZE=64, 26 | parameter MUL=3'b001, 27 | parameter SQR=3'b010, 28 | //parameter IS_ZERO_POS=3'b11, 29 | //parameter SHIFT_RIGHT=3'b100, 30 | parameter Xor_256=3'b101, 31 | //parameter SHIFT_LEFT=3'b110, 32 | parameter XOR=3'b111 33 | )( 34 | 35 | //INPUTS 36 | input wire [255:0] A, 37 | input wire [255:0] B, //change 38 | input wire [2:0] select_line, 39 | 40 | //OUTPUT 41 | output[135:0] C_Out, 42 | output[127:0] D_Out 43 | 44 | ); 45 | 46 | //OUTPUT PORTS 47 | wire [135:0] Data_C_Out[param:0]; 48 | wire [127:0] Data_D_Out[param:0]; 49 | 50 | //INPUT PORTS 51 | wire [((2*SIZE)-1):0] Data_A_MUL,Data_B_MUL; 52 | wire [135:0] Data_A_XOR,Data_B_XOR; 53 | // wire [(SIZE-1):0] Data_A_IS_ZERO_POS,Data_B_SHIFT_RIGHT; 54 | //wire [(2*SIZE-1):0] Data_A_SHIFT_RIGHT; 55 | //wire [(3*SIZE-1):0] Data_A_SHIFT_LEFT,Data_B_SHIFT_LEFT; 56 | wire [(2*SIZE-1):0] Data_A_SQR; 57 | 58 | wire [255:0] Data_A_XOR_256 ; 59 | wire [255:0] Data_B_XOR_256 ; 60 | 61 | 62 | assign Data_A_MUL =(select_line==MUL)?A[127:0]:128'hzz; 63 | assign Data_B_MUL=(select_line==MUL)?B[127:0]:128'hzz; 64 | 65 | assign Data_A_XOR =(select_line==XOR)?A[135:0]:135'hzz; 66 | assign Data_B_XOR =(select_line==XOR)?B[135:0]:135'hzz; 67 | 68 | 69 | assign Data_A_XOR_256 =(select_line==Xor_256)?A[255:0]:255'hzz; 70 | assign Data_B_XOR_256 =(select_line==Xor_256)?B[255:0]:255'hzz; 71 | 72 | 73 | //assign Data_A_SHIFT_RIGHT =(select_line==SHIFT_RIGHT)?{64'h0,A[63:0]}:128'h0; 74 | // assign Data_B_SHIFT_RIGHT =(select_line==SHIFT_RIGHT)?B[63:0]:128'h0; 75 | 76 | //assign Data_A_SHIFT_LEFT =(select_line==SHIFT_LEFT)?A:(select_line==SHIFT_LEFT_128)?{64'h00,A}:128'hzz; 77 | // assign Data_B_SHIFT_LEFT =(select_line==SHIFT_LEFT)?B:(select_line==SHIFT_LEFT_128)?B[63:0]:64'hzz; 78 | 79 | 80 | assign Data_A_SQR =(select_line==SQR)?A[127:0]:128'hzz; 81 | 82 | //assign Data_A_IS_ZERO_POS =(select_line==IS_ZERO_POS)?A[63:0]:64'hzz; 83 | //assign Data_D_Out[SHIFT_LEFT_128]=Data_D_Out[SHIFT_LEFT]; 84 | //assign Data_C_Out[SHIFT_LEFT_128]=Data_C_Out[SHIFT_LEFT]; 85 | 86 | mul_128_module mul_128( 87 | .A(Data_A_MUL), 88 | .B(Data_B_MUL), 89 | .mul_128({Data_C_Out[MUL],Data_D_Out[MUL]}) 90 | ); 91 | 92 | 93 | Xor_module xor_135( 94 | .A(Data_A_XOR), 95 | .B(Data_B_XOR), 96 | .C(Data_C_Out[XOR]) 97 | ); 98 | 99 | 100 | 101 | 102 | Xor_256_module xor_256( 103 | .A(Data_A_XOR_256), 104 | .B(Data_B_XOR_256), 105 | .C({Data_C_Out[Xor_256],Data_D_Out[Xor_256]}) 106 | ); 107 | 108 | 109 | 110 | 111 | sqr_128_module square_128( 112 | .A(Data_A_SQR), 113 | .Out({Data_C_Out[SQR],Data_D_Out[SQR]}) 114 | ); 115 | 116 | /*pos_of_one utt5( 117 | .A(Data_A_IS_ZERO_POS), 118 | .C(Data_D_Out[IS_ZERO_POS]) 119 | );*/ 120 | 121 | 122 | /*shift uut3( 123 | .A(Data_A_SHIFT_RIGHT), 124 | .arg(Data_B_SHIFT_RIGHT), 125 | .Out({Data_D_Out[SHIFT_RIGHT]}) 126 | );*/ 127 | 128 | /* shift_left uut6( 129 | .A(Data_A_SHIFT_LEFT), 130 | .arg(Data_B_SHIFT_LEFT), 131 | .Out({Data_C_Out[SHIFT_LEFT],Data_D_Out[SHIFT_LEFT]}) 132 | ); 133 | */ 134 | assign C_Out=Data_C_Out[select_line]; 135 | assign D_Out=Data_D_Out[select_line]; 136 | 137 | endmodule 138 | 139 | 140 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/mul_64_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09:51:19 06/27/2014 7 | // Design Name: 8 | // Module Name: testt 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | /*module mul_2_module( 22 | input[1:0] A, 23 | input[1:0] B, 24 | output[3:0] mul_2 25 | ); 26 | //assign mul_2[0] = A[0]&B[0]; 27 | //assign mul_2[2] = A[1]&B[1]; 28 | assign mul_2[2:0] = { A[1]&B[1],(A[0]^A[1])&(B[0]^B[1]) ^ mul_2[0] ^ mul_2[2],A[0]&B[0]}; 29 | endmodule*/ 30 | 31 | module mul_2_module( 32 | input [1:0] A, 33 | input [1:0] B, 34 | output reg[3:0] C 35 | ); 36 | always @(A or B) 37 | begin 38 | case ({A,B}) 39 | 4'b0000: 40 | C=0; 41 | 4'b0001: 42 | C=0; 43 | 4'b0010: 44 | C=0; 45 | 4'b0011: 46 | C=0; 47 | 4'b0100: 48 | C=0; 49 | 4'b0101: 50 | C=4'b0001; 51 | 4'b0110: 52 | C=4'b0010; 53 | 4'b0111: 54 | C=4'b0011; 55 | 4'b1000: 56 | C=4'b0; 57 | 4'b1001: 58 | C=4'b0010; 59 | 4'b1010: 60 | C=4'b0100; 61 | 4'b1011: 62 | C=4'b0110; 63 | 4'b1100: 64 | C=4'b0; 65 | 4'b1101: 66 | C=4'b0011; 67 | 4'b1110: 68 | C=4'b0110; 69 | 4'b1111: 70 | C=4'b0101; 71 | endcase 72 | end 73 | endmodule 74 | 75 | module mul_4_module( 76 | input[3:0] A, 77 | input[3:0] B, 78 | output[7:0] mul_4 79 | ); 80 | // reg[7:0] mul_4; 81 | wire[3:0] d0,d1,d2,d7; 82 | mul_2_module uut0((A[1:0]),(B[1:0]),(d0)); 83 | mul_2_module uut1((A[1:0]^A[3:2]),(B[1:0]^B[3:2]),(d1)); 84 | mul_2_module uut2(A[3:2],B[3:2],(d2)); 85 | assign d7 = d1^d2^d0; 86 | assign mul_4[7:4]= {d2[3:2],((d2[1:0])^(d7[3:2]))}; 87 | assign mul_4[3:0]= {((d0[3:2])^(d7[1:0])),d0[1:0]}; 88 | assign mul_4[7:0]= {d2[3:2],((d2[1:0])^(d7[3:2])),((d0[3:2])^(d7[1:0])),d0[1:0]}; 89 | 90 | endmodule 91 | 92 | 93 | module mul_8_module( 94 | input[7:0] A, 95 | input[7:0] B, 96 | output[15:0] mul_8 97 | ); 98 | wire[7:0] d0,d1,d2,d7, d8,d4;//;wire[5:0] d7;wire[7:0] d2; 99 | mul_4_module uut5((A[3:0]),(B[3:0]),(d0)); 100 | mul_4_module uut6((A[3:0]^A[7:4]),(B[3:0]^B[7:4]),(d1)); 101 | mul_4_module uut7(A[7:4],B[7:4],(d2)); 102 | assign d7 = d1^d2^d0; 103 | //assign mul_8[15:8] = {d2[7:4],((d2[3:0])^(d7[7:4]))}; 104 | //assign mul_8[7:0]= {((d0[7:4])^(d7[3:0])),d0[3:0]}; 105 | 106 | 107 | assign mul_8[15:0] = {d2[7:4],((d2[3:0])^(d7[7:4])),((d0[7:4])^(d7[3:0])),d0[3:0]}; 108 | 109 | endmodule 110 | /*module mul_16_module( 111 | input[15:0] A, 112 | input[15:0] B, 113 | output[31:0] mul_16 114 | ); 115 | wire[15:0] d0,d1,d2,d7, d8,d4;//;wire[5:0] d7;wire[7:0] d2; 116 | mul_8_module uut5((A[7:0]),(B[7:0]),(d0)); 117 | mul_8_module uut6((A[7:0]^A[15:8]),(B[7:0]^B[15:8]),(d1)); 118 | mul_8_module uut7(A[15:8],B[15:8],(d2)); 119 | assign d7 = d1^d2^d0; 120 | //assign mul_16[31:16] = {d2[15:8],((d2[7:0])^(d7[15:8]))}; 121 | //assign mul_16[15:0]= {((d0[15:8])^(d7[7:0])),d0[7:0]}; 122 | assign mul_16[31:0] = {d2[15:8],((d2[7:0])^(d7[15:8])),((d0[15:8])^(d7[7:0])),d0[7:0]}; 123 | endmodule 124 | 125 | 126 | 127 | module mul_32_module( 128 | input[31:0] A, 129 | input[31:0] B, 130 | output[63:0] mul_32 131 | ); 132 | wire[31:0] d0,d1,d2,d7, d8,d4;//;wire[5:0] d7;wire[7:0] d2; 133 | mul_16_module uut5((A[15:0]),(B[15:0]),(d0)); 134 | mul_16_module uut6((A[15:0]^A[31:16]),(B[15:0]^B[31:16]),(d1)); 135 | mul_16_module uut7(A[31:16],B[31:16],(d2)); 136 | assign d7 = d1^d2^d0; 137 | //assign mul_32[63:32] = {d2[31:16],((d2[15:0])^(d7[31:16]))}; 138 | //assign mul_32[31:0]= {((d0[31:16])^(d7[15:0])),d0[15:0]}; 139 | assign mul_32[63:0] = {d2[31:16],((d2[15:0])^(d7[31:16])),((d0[31:16])^(d7[15:0])),d0[15:0]}; 140 | endmodule*/ 141 | module mul_32_module( 142 | input[31:0] A, 143 | input[31:0] B, 144 | output[63:0] mul_32 145 | ); 146 | wire[15:0] d0,d1,d2,d3,f1,f0,f,c0,c1,c2,c3,c5,c4,c6,g1,g2,g3,g4,g5,g6;//;wire[5:0] d7;wire[7:0] d2; 147 | mul_8_module uut1((A[7:0]),(B[7:0]),(d0)); 148 | mul_8_module uut2((A[15:8]),(B[15:8]),(d1)); 149 | mul_8_module uut3((A[23:16]),(B[23:16]),(d2)); 150 | mul_8_module uut4((A[31:24]),(B[31:24]),(d3)); 151 | assign f1 = d3^d2; 152 | assign f0 = d1^d0; 153 | assign c6=d3; 154 | //assign f=f1^f0; 155 | mul_8_module uut5((A[31:24])^A[23:16],(B[31:24])^B[23:16],g5); 156 | assign c5=g5^f1; 157 | mul_8_module uut6((A[15:8])^A[31:24],(B[15:8])^B[31:24],g4); 158 | assign c4=g4^f1^d1; 159 | 160 | mul_8_module uut7((A[7:0])^A[23:16],(B[7:0])^B[23:16],g2); 161 | assign c2=g2^f0^d2; 162 | 163 | mul_8_module uut8((A[7:0])^A[15:8],(B[7:0])^B[15:8],g1); 164 | assign c1 =g1^f0; 165 | assign c0=d0; 166 | 167 | mul_8_module uut9(A[7:0]^A[23:16]^A[31:24]^A[15:8],B[7:0]^B[23:16]^B[31:24]^B[15:8],g3); 168 | assign c3=g3^c1^c2^c4^c5^c6^c0; 169 | 170 | 171 | assign mul_32 = {c6[15:8],c6[7:0]^c5[15:8],c5[7:0]^c4[15:8],c4[7:0]^c3[15:8],c3[7:0]^c2[15:8],c2[7:0]^c1[15:8],c1[7:0]^c0[15:8],c0[7:0]}; 172 | endmodule 173 | 174 | 175 | module mul_64_module( 176 | input[63:0] A, 177 | input[63:0] B, 178 | output[127:0] mul_64 179 | ); 180 | wire[63:0] d0,d1,d2,d7;//;wire[5:0] d7;wire[7:0] d2; 181 | mul_32_module uut5((A[31:0]),(B[31:0]),(d0)); 182 | mul_32_module uut6((A[31:0]^A[63:32]),(B[31:0]^B[63:32]),(d1)); 183 | mul_32_module uut7(A[63:32],B[63:32],(d2)); 184 | assign d7 = d1^d2^d0; 185 | assign mul_64[127:0] = {d2[63:32],((d2[31:0])^(d7[63:32])),((d0[63:32])^(d7[31:0])),d0[31:0]}; 186 | 187 | endmodule 188 | 189 | 190 | 191 | 192 | module mul_128_module( 193 | input[127:0] A, 194 | input[127:0] B, 195 | output[255:0] mul_128 196 | ); 197 | wire[127:0] d0,d1,d2,d7;//;wire[5:0] d7;wire[7:0] d2; 198 | mul_64_module mul_641((A[63:0]),(B[63:0]),(d0)); 199 | mul_64_module mul_642((A[63:0]^A[127:64]),(B[63:0]^B[127:64]),(d1)); 200 | mul_64_module mul_643(A[127:64],B[127:64],(d2)); 201 | assign d7 = d1^d2^d0; 202 | assign mul_128[255:0] = {d2[127:64],((d2[63:0])^(d7[127:64])),((d0[127:64])^(d7[63:0])),d0[63:0]}; 203 | 204 | endmodule 205 | 206 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/point_addition_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Barc 4 | // Engineer: Rahul 5 | // 6 | // Create Date: 14:51:47 10/09/2014 7 | // Design Name: 8 | // Module Name: point_addition_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | //2'h2 for point double 23 | 24 | module point_addition_module( 25 | input wire clk, 26 | input wire interupt_sqr, 27 | input wire interupt_red, 28 | input wire interupt_swap, 29 | input wire interupt_inv, 30 | input wire interupt_mul, 31 | input wire interupt_Xor, 32 | input wire interupt_transfer, 33 | 34 | output reg [2:0] start_addr, 35 | output reg [3:0] command_ECC, //command for ECC primitive operation 36 | output reg interupt, //interupt on completion of Point Addition 37 | output reg cmd_addition, 38 | 39 | 40 | output reg read_write_command, //enable to transfer data to inner Ram 41 | output reg [5:0] read_address, 42 | output reg [5:0] write_address, 43 | output reg command_transfer, 44 | input wire [9:0] Data_len_Polynomial, 45 | input wire [1:0] command //cmd to perform point doubling 46 | ); 47 | 48 | initial begin 49 | cmd_addition<=1'h0; 50 | interupt<=1'h0; 51 | fsm<=6'h0; 52 | end 53 | 54 | reg [5:0] fsm; 55 | reg [2:0] var; 56 | 57 | always @(posedge clk) begin 58 | 59 | if(command==2'h1) begin 60 | fsm<=6'h1; //start point addition 61 | cmd_addition<=1'h1; 62 | end 63 | 64 | case (fsm) 65 | 6'h1:begin 66 | var<=Data_len_Polynomial/8'h80; 67 | read_write_command<=1'h0; 68 | read_address<=6'h3; 69 | write_address<=6'b001_010; //transfer X1 to A inner Ram 70 | command_transfer<=1'h1; 71 | fsm<=6'h2; 72 | end 73 | 74 | 6'h2:begin 75 | if(interupt_transfer) begin 76 | fsm<=6'h3; 77 | read_write_command<=1'h0; 78 | read_address<=6'h21; 79 | write_address<=6'b010_010; //transfer x2 to B inner Ram 80 | command_transfer<=1'h1; 81 | end 82 | else 83 | command_transfer<=1'h0; 84 | end 85 | 86 | 6'h3:begin 87 | command_transfer<=1'h0; 88 | if(interupt_transfer) begin 89 | fsm<=6'h4; 90 | start_addr<=3'h3; 91 | command_ECC<=4'h6; //X1+x2 Xor 92 | end 93 | end 94 | 95 | 96 | 97 | 6'h4:begin 98 | if(interupt_Xor) begin 99 | fsm<=6'h5; //transfer to outer Ram 100 | read_write_command<=1'h1; 101 | read_address<=6'b011_010; 102 | write_address<=6'hc; 103 | command_transfer<=1'h1; 104 | end 105 | command_ECC<=4'h0; 106 | end 107 | 108 | 6'h5:begin 109 | 110 | if(interupt_transfer) begin 111 | fsm<=6'h6; 112 | command_transfer<=1'h1; 113 | read_write_command<=1'h0; 114 | read_address<=6'hc; 115 | write_address<=6'b001_101; //transfer X1+X2 to inner Ram 116 | end 117 | else 118 | command_transfer<=4'h0; 119 | end 120 | 121 | 6'h6:begin 122 | 123 | if(interupt_transfer) begin 124 | fsm<=6'h7; 125 | command_transfer<=1'h1; 126 | read_write_command<=1'h0; 127 | read_address<=6'h9; //transfer a to inner Ram 128 | write_address<=6'b010_101; 129 | end 130 | else 131 | command_transfer<=1'h0; 132 | end 133 | 134 | 135 | 6'h7:begin 136 | command_transfer<=1'h0; 137 | if(interupt_transfer) begin 138 | fsm<=6'h8; 139 | command_ECC<=4'h6; // xor x1+x2+a 140 | start_addr<=3'h6; 141 | end 142 | end 143 | 144 | 145 | 6'h8:begin 146 | command_ECC<=4'h0; 147 | if(interupt_Xor)begin 148 | fsm<=6'h9; 149 | command_transfer<=1'h1; 150 | read_write_command<=1'h1; 151 | read_address<=6'b011_101; 152 | write_address<=6'hf; //store xor x1+x2+a in outer Ram 153 | 154 | end 155 | end 156 | 157 | 6'h9:begin 158 | if(interupt_transfer) begin 159 | fsm<=6'ha; 160 | command_ECC<=4'h3; //inverse (x1+x2) 161 | start_addr<=3'h6; 162 | end 163 | command_transfer<=4'h0; 164 | end 165 | 166 | 6'ha:begin 167 | command_ECC<=4'h0; 168 | if(interupt_inv) begin 169 | fsm<=6'hb; 170 | read_write_command<=1'h1; 171 | if(var[1]^var[0]) 172 | read_address<=6'b100_101; 173 | else begin 174 | if(var[2]||var[1]) 175 | read_address<=6'b011_100; 176 | else 177 | read_address<=6'b011_101; 178 | end //copy inverse to outer Ram 179 | write_address<=6'h12; 180 | command_transfer<=1'h1; 181 | end 182 | else 183 | command_transfer<=1'h0; 184 | end 185 | 186 | 6'hb:begin 187 | if(interupt_transfer) begin 188 | fsm<=6'hc; 189 | read_write_command<=1'h0; 190 | read_address<=6'h6; //copy y1 to inner Ram 191 | write_address<=6'b010_101; 192 | command_transfer<=1'h1; 193 | end 194 | else 195 | command_transfer<=1'h0; 196 | end 197 | 198 | 6'hc:begin 199 | if(interupt_transfer) begin 200 | fsm<=6'hd; 201 | read_write_command<=1'h0; 202 | read_address<=6'h27; //copy y2 to inner Ram 203 | write_address<=6'b001_101; 204 | command_transfer<=1'h1; 205 | end 206 | else 207 | command_transfer<=1'h0; 208 | end 209 | 210 | 6'hd:begin 211 | command_transfer<=1'h0; 212 | if(interupt_transfer)begin 213 | fsm<=6'he; 214 | command_ECC<=4'h6; 215 | start_addr<=3'h6; //xor y1+y2 216 | end 217 | end 218 | 219 | 220 | 6'he:begin 221 | if(interupt_Xor)begin 222 | fsm<=6'hf; 223 | read_write_command<=1'h1; 224 | read_address<=6'b011_101; 225 | write_address<=6'h15; //store y1+y2 in outer Ram 226 | command_transfer<=1'h1; 227 | end 228 | else 229 | command_ECC<=4'h0; 230 | end 231 | 232 | 233 | 6'hf:begin 234 | if(interupt_transfer)begin 235 | fsm<=6'h10; 236 | read_write_command<=1'h0; 237 | read_address<=6'h15; 238 | write_address<=6'b010_101; //store y1+y2 in inner Ram 239 | command_transfer<=1'h1; 240 | end 241 | else 242 | command_transfer<=3'h0; 243 | end 244 | 245 | 6'h10:begin 246 | if(interupt_transfer) begin 247 | fsm<=6'h11; 248 | read_write_command<=1'h0; 249 | read_address<=6'h12; 250 | write_address<=6'b001_101; //store x1+x2 inverse in inner Ram 251 | command_transfer<=1'h1; 252 | end 253 | else 254 | command_transfer<=3'h0; 255 | end 256 | 257 | 6'h11:begin 258 | command_transfer<=3'h0; 259 | if(interupt_transfer) begin 260 | fsm<=6'h12; 261 | command_ECC<=4'h1; //Mulltiply (y1+y2) * Inv(x1+x2) 262 | start_addr<=3'h6; 263 | end 264 | end 265 | 266 | 6'h12:begin 267 | if(interupt_mul) begin 268 | fsm<=6'h13; 269 | command_ECC<=4'h4; 270 | start_addr<=3'h5; //reduce (y1+y2) * Inv(x1+x2) 271 | end 272 | else 273 | command_ECC<=4'h0; 274 | end 275 | 276 | 277 | 6'h13:begin 278 | command_ECC<=4'h0; 279 | if(interupt_red) begin 280 | fsm<=6'h14; 281 | read_write_command<=1'h1; 282 | if(var[1]^var[0]) 283 | read_address<=6'b100_101; 284 | else begin 285 | if(var[2]||var[1]) 286 | read_address<=6'b011_100; 287 | else 288 | read_address<=6'b011_101; 289 | end 290 | write_address<=6'h18; //store lambda in outer Ram 291 | command_transfer<=1'h1; 292 | end 293 | end 294 | 295 | 6'h14:begin 296 | if(interupt_transfer)begin 297 | fsm<=6'h15; 298 | read_write_command<=1'h0; 299 | read_address<=6'h18; 300 | write_address<=6'b001_101; //store lambda in inner Ram 301 | command_transfer<=1'h1; 302 | end 303 | else 304 | command_transfer<=4'h0; 305 | end 306 | 307 | 6'h15:begin 308 | command_transfer<=4'h0; 309 | if(interupt_transfer)begin 310 | fsm<=6'h16; 311 | command_ECC<=4'h2; //cal lambda^2 312 | start_addr<=3'h6; 313 | end 314 | end 315 | 316 | 6'h16:begin 317 | if(interupt_sqr)begin 318 | fsm<=6'h17; 319 | command_ECC<=4'h4; //reduce lambda sqr 320 | start_addr<=3'h5; 321 | end 322 | else 323 | command_ECC<=4'h0; 324 | end 325 | 326 | 327 | 6'h17:begin 328 | command_ECC<=1'h0; 329 | if(interupt_red)begin 330 | fsm<=6'h18; 331 | read_write_command<=1'h1; 332 | if(var[1]^var[0]) 333 | read_address<=6'b100_101; 334 | else begin 335 | if(var[2]||var[1]) 336 | read_address<=6'b011_100; 337 | else 338 | read_address<=6'b011_101; 339 | end 340 | write_address<=6'h1b; //store lambda^2 in outer Ram 341 | command_transfer<=1'h1; 342 | end 343 | end 344 | 345 | 6'h18:begin 346 | command_transfer<=1'h0; 347 | if(interupt_transfer)begin 348 | fsm<=6'h19; 349 | read_write_command<=1'h0; 350 | read_address<=6'h1b; 351 | write_address<=6'b010_101; //store lambda^2 in inner ram 352 | command_transfer<=1'h1; 353 | end 354 | end 355 | 356 | 6'h19:begin 357 | if(interupt_transfer)begin 358 | command_ECC<=4'h6; 359 | start_addr<=3'h6; //xor lambda^2+lambda 360 | fsm<=6'h1a; 361 | end 362 | command_transfer<=1'h0; 363 | end 364 | 365 | 366 | 6'h1a:begin 367 | command_ECC<=4'h0; 368 | if(interupt_Xor)begin 369 | read_write_command<=1'h1; 370 | read_address<=6'b011_101; 371 | write_address<=6'hc; //store lambda^2 +lambda in outer ram 372 | command_transfer<=1'h1; 373 | fsm<=6'h1b; 374 | end 375 | end 376 | 377 | 6'h1b:begin 378 | if(interupt_transfer) begin 379 | fsm<=6'h1c; 380 | read_write_command<=1'h0; 381 | read_address<=6'hc; 382 | write_address<=6'b001_010; 383 | command_transfer<=1'h1; //store lambda^2+lambda in inner Ram 384 | end 385 | else 386 | command_transfer<=1'h0; 387 | end 388 | 389 | 6'h1c:begin 390 | if(interupt_transfer)begin 391 | fsm<=6'h1d; 392 | read_write_command<=1'h0; 393 | read_address<=6'hf; 394 | write_address<=6'b010_010; //store x1+x2+a in iner ram 395 | command_transfer<=1'h1; 396 | end 397 | else 398 | command_transfer<=1'h0; 399 | end 400 | 401 | 6'h1d:begin 402 | if(interupt_transfer)begin 403 | fsm<=6'h1e; 404 | command_ECC<=4'h6; //calculate x3 405 | start_addr<=3'h3; 406 | end 407 | 408 | command_transfer<=1'h0; 409 | end 410 | 411 | 6'h1e:begin 412 | command_ECC<=1'h0; 413 | if(interupt_Xor)begin 414 | fsm<=6'h1f; 415 | read_write_command<=1'h1; 416 | read_address<=6'b011_010; 417 | write_address<=6'h21; //store x3 in outer ram 418 | command_transfer<=1'h1; 419 | end 420 | end 421 | 422 | 6'h1f:begin 423 | if(interupt_transfer) begin 424 | fsm<=6'h20; 425 | read_write_command<=1'h0; 426 | read_address<=6'h21; 427 | write_address<=6'b001_010; // x3 in inner Ram 428 | command_transfer<=1'h1; 429 | end 430 | else 431 | command_transfer<=1'h0; 432 | end 433 | 434 | 6'h20:begin 435 | if(interupt_transfer)begin 436 | read_write_command<=1'h0; 437 | read_address<=6'h3; 438 | write_address<=6'b010_010; //store x1 in inner Ram 439 | command_transfer<=1'h1; 440 | fsm<=6'h21; 441 | end 442 | else 443 | command_transfer<=1'h0; 444 | end 445 | 446 | 447 | 6'h21:begin 448 | if(interupt_transfer)begin 449 | command_ECC<=4'h6; //Xor x1+x3 450 | start_addr<=3'h3; 451 | fsm<=6'h22; 452 | end 453 | command_transfer<=1'h0; 454 | end 455 | 456 | 457 | 6'h22:begin 458 | command_ECC<=3'h0; 459 | if(interupt_Xor) begin 460 | fsm<=6'h23; 461 | read_write_command<=1'h1; 462 | read_address<=6'b011_010; 463 | write_address<=6'h24; //store x3+x1 in outer ram 464 | command_transfer<=1'h1; 465 | end 466 | end 467 | 468 | 6'h23:begin 469 | if(interupt_transfer)begin 470 | fsm<=6'h24; 471 | read_write_command<=1'h0; 472 | read_address<=6'h24; 473 | write_address<=6'b010_101; //store x1+x3 in inner Ram 474 | command_transfer<=1'h1; 475 | end 476 | else 477 | command_transfer<=1'h0; 478 | end 479 | 480 | 6'h24:begin 481 | command_transfer<=1'h0; 482 | if(interupt_transfer) begin 483 | command_ECC<=4'h1; //mul lambda*(x1+x3) 484 | start_addr<=3'h6; 485 | fsm<=6'h25; 486 | end 487 | end 488 | 489 | 6'h25:begin 490 | if(interupt_mul)begin 491 | command_ECC<=4'h4; //reduce above mul 492 | start_addr<=3'h5; 493 | fsm<=6'h26; 494 | end 495 | else 496 | command_ECC<=4'h0; 497 | end 498 | 499 | 500 | 6'h26:begin 501 | command_ECC<=4'h0; 502 | if(interupt_red)begin 503 | read_write_command<=1'h1; 504 | if(var[1]^var[0]) 505 | read_address<=6'b100_101; 506 | else begin 507 | if(var[2]||var[1]) 508 | read_address<=6'b011_100; 509 | else 510 | read_address<=6'b011_101; 511 | end 512 | write_address<=6'h2a; //store lambda*(x1+x3) in outer Ram 513 | command_transfer<=1'h1; 514 | fsm<=6'h28; 515 | end 516 | end 517 | 518 | 6'h28:begin 519 | if(interupt_transfer)begin 520 | fsm<=6'h29; 521 | read_write_command<=1'h0; 522 | read_address<=6'h6; 523 | write_address<=6'b010_010; //store y1 in inner Ram 524 | command_transfer<=1'h1; 525 | end 526 | else 527 | command_transfer<=1'h0; 528 | end 529 | 530 | 6'h29:begin 531 | command_transfer<=1'h0; 532 | if(interupt_transfer)begin 533 | fsm<=6'h2a; 534 | command_ECC<=4'h6; 535 | start_addr<=3'h3; //xor y1+x3 536 | end 537 | end 538 | 539 | 540 | 6'h2a:begin 541 | command_ECC<=1'h0; 542 | if(interupt_Xor) begin 543 | fsm<=6'h2b; 544 | read_write_command<=1'h1; 545 | read_address<=6'b011_010; 546 | write_address<=6'h2d; //store X3+Y1 in outer Ram 547 | command_transfer<=1'h1; 548 | end 549 | end 550 | 551 | 6'h2b:begin 552 | 553 | if(interupt_transfer) begin 554 | fsm<=6'h2c; 555 | read_write_command<=1'h0; 556 | read_address<=6'h2a; 557 | write_address<=6'b010_010; //store lambda*(x1+x3) in inner ram 558 | command_transfer<=1'h1; 559 | end 560 | else 561 | command_transfer<=1'h0; 562 | end 563 | 564 | 6'h2c:begin 565 | if(interupt_transfer)begin 566 | fsm<=6'h2d; 567 | read_write_command<=1'h0; 568 | read_address<=6'h2d; 569 | write_address<=6'b001_010; //store x3+y2 in inner Ram 570 | command_transfer<=1'h1; 571 | end 572 | else 573 | command_transfer<=1'h0; 574 | end 575 | 576 | 6'h2d:begin 577 | command_transfer<=1'h0; 578 | if(interupt_transfer)begin 579 | command_ECC<=4'h6; 580 | start_addr<=3'h3; //xor to cal Y3 581 | fsm<=6'h2e; 582 | end 583 | end 584 | 585 | 6'h2e:begin 586 | command_ECC<=4'h0; 587 | if(interupt_Xor)begin 588 | fsm<=6'h2f; 589 | read_write_command<=1'h1; 590 | read_address<=6'b011_010; 591 | write_address<=6'h27; //store y3 in outer Ram 592 | command_transfer<=1'h1; 593 | end 594 | end 595 | 596 | 6'h2f:begin 597 | command_transfer<=1'h0; 598 | if(interupt_transfer) begin 599 | fsm<=6'h30; 600 | interupt<=1'h1; 601 | end 602 | end 603 | 604 | 6'h30:begin 605 | cmd_addition<=1'h0; 606 | interupt<=1'h0; 607 | fsm <= 6'h31; 608 | end 609 | 6'h31:begin 610 | fsm <= 6'h32; 611 | end 612 | 613 | 614 | endcase 615 | end 616 | endmodule 617 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/point_double_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Deepak and Rahul 5 | // 6 | // Create Date: 15:05:56 10/09/2014 7 | // Design Name: 8 | // Module Name: point_double_module 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | //1d 1e(for x3) 26 for y3 22 | // 482 380 390 23 | //changing code here 24 | module point_double_module( 25 | input wire clk, 26 | input wire interupt_sqr, 27 | input wire interupt_red, 28 | input wire interupt_swap, 29 | input wire interupt_inv, 30 | input wire interupt_mul, 31 | input wire interupt_Xor, 32 | input wire interupt_transfer, 33 | 34 | output reg [2:0] start_addr, 35 | output reg [3:0] command_ECC, //command for ECC primitive operation 36 | output reg interupt, //interupt on completion of Point Addition 37 | output reg cmd_double, 38 | 39 | 40 | output reg read_write_command, 41 | output reg [5:0] read_address, 42 | output reg [5:0] write_address, 43 | 44 | output reg command_transfer, 45 | input wire [9:0] Data_len_Polynomial, 46 | input wire [1:0] command 47 | ); 48 | initial begin 49 | cmd_double<=1'h0; 50 | interupt<=1'h0; 51 | end 52 | 53 | 54 | reg [6:0] fsm; 55 | reg [2:0] var; 56 | 57 | 58 | always @(posedge clk) begin 59 | if(command==2'h2) begin 60 | fsm<=6'h1; //start point doubling 61 | cmd_double<=1'h1; 62 | end 63 | case (fsm) 64 | 6'h1:begin 65 | var<=Data_len_Polynomial/8'h80; 66 | read_write_command<=1'h0; 67 | read_address<=6'h3; 68 | write_address<=6'b001_010; //transfer X1 to A inner Ram 69 | command_transfer<=1'h1; 70 | fsm<=6'h2; 71 | end 72 | 73 | 6'h2:begin 74 | if(interupt_transfer) begin 75 | fsm<=6'h3; 76 | read_write_command<=1'h0; 77 | read_address<=6'h6; 78 | write_address<=6'b010_010; //transfer y1 to B inner Ram 79 | command_transfer<=1'h1; 80 | end 81 | else 82 | command_transfer<=1'h0; 83 | end 84 | 85 | 6'h3:begin 86 | command_transfer<=1'h0; 87 | if(interupt_transfer) begin 88 | fsm<=6'h4; 89 | start_addr<=3'h3; 90 | command_ECC<=4'h2; //X square 91 | end 92 | end 93 | 94 | 95 | 96 | 6'h4:begin 97 | if(interupt_sqr) begin 98 | fsm<=6'h5; 99 | command_ECC<=4'h4; //reduce Square term 100 | start_addr<=2'h2; 101 | end 102 | else 103 | command_ECC<=4'h0; 104 | end 105 | 106 | 6'h5:begin 107 | command_ECC<=4'h0; 108 | if(interupt_red) begin 109 | fsm<=6'h6; 110 | command_transfer<=1'h1; 111 | read_write_command<=1'h1; 112 | if(var[1]^var[0]) //store x^2 result in outer Ram 113 | read_address<=6'b100_010; 114 | else begin 115 | if(var[2]||var[1]) 116 | read_address<=6'b011_001; 117 | else 118 | read_address<=6'b011_010; 119 | end 120 | write_address<=6'hf; 121 | end 122 | end 123 | 124 | 6'h6:begin 125 | command_transfer<=1'h0; 126 | if(interupt_transfer) begin 127 | fsm<=6'h7; 128 | command_ECC<=4'h3; //x Inverse_operation 129 | start_addr<=4'h3; 130 | end 131 | end 132 | 133 | 134 | 6'h7:begin 135 | command_ECC<=4'h0; 136 | if(interupt_inv)begin 137 | fsm<=6'h8; 138 | command_transfer<=1'h1; 139 | read_write_command<=1'h1; 140 | if(var[1]^var[0]) 141 | read_address<=6'b100_010; 142 | else begin 143 | if(var[2]||var[1]) 144 | read_address<=6'b011_001; 145 | else 146 | read_address<=6'b011_010; 147 | end 148 | write_address<=6'h12; //store x inv res in outer RAM 149 | 150 | end 151 | end 152 | 153 | 6'h8:begin 154 | if(interupt_transfer) begin //copy y1 result to inner Ram 155 | fsm<=6'h9; 156 | read_write_command<=1'h0; 157 | read_address<=6'h6; 158 | write_address<=6'b001_010; 159 | command_transfer<=1'h1; 160 | end 161 | else 162 | command_transfer<=4'h0; 163 | end 164 | 165 | 6'h9:begin 166 | if(interupt_transfer) begin 167 | fsm<=6'ha; 168 | read_write_command<=1'h0; 169 | read_address<=6'h12; //copy inverse to inner Ram 170 | write_address<=6'b010_010; 171 | command_transfer<=1'h1; 172 | end 173 | else 174 | command_transfer<=1'h0; 175 | end 176 | 177 | 6'ha:begin 178 | command_transfer<=1'h0; 179 | if(interupt_transfer) begin 180 | fsm<=6'hb; 181 | command_ECC<=4'h1; //Multiplication (y1)*inv X1) cal of lambda 182 | end 183 | end 184 | 185 | 6'hb:begin 186 | command_ECC<=4'h0; 187 | if(interupt_mul)begin 188 | fsm<=6'hc; 189 | command_ECC<=4'h4; //reduce the above term 190 | start_addr<=3'h2; 191 | end 192 | end 193 | 194 | 6'hc:begin 195 | command_ECC<=3'h0; 196 | if(interupt_red)begin 197 | fsm<=6'hd; 198 | read_write_command<=1'h1; 199 | if(var[1]^var[0]) 200 | read_address<=6'b100_010; 201 | else begin 202 | if(var[2]||var[1]) 203 | read_address<=6'b011_001; 204 | else 205 | read_address<=6'b011_010; 206 | end 207 | write_address<=6'h15; //store y1/x1 in outer Ram 208 | command_transfer<=1'h1; 209 | end 210 | end 211 | 212 | 213 | 6'hd:begin 214 | if(interupt_transfer)begin 215 | fsm<=6'he; 216 | read_write_command<=1'h0; 217 | read_address<=6'h15; 218 | write_address<=6'b001_010; //store y1/x1 in inner Ram 219 | command_transfer<=1'h1; 220 | end 221 | else 222 | command_transfer<=3'h0; 223 | end 224 | 225 | 226 | 6'he:begin 227 | if(interupt_transfer)begin 228 | fsm<=6'hf; 229 | read_write_command<=1'h0; 230 | read_address<=6'h3; 231 | write_address<=6'b010_010; //store x1 in inner Ram 232 | command_transfer<=1'h1; 233 | end 234 | else 235 | command_transfer<=3'h0; 236 | end 237 | 238 | 6'hf:begin 239 | command_transfer<=1'h0; 240 | if(interupt_transfer) begin 241 | fsm<=6'h10; 242 | start_addr<=3'h3; 243 | command_ECC<=4'h6; //x1+y1/x1 244 | end 245 | end 246 | 247 | 6'h10:begin 248 | command_ECC<=3'h0; 249 | if(interupt_Xor) begin 250 | fsm<=6'h11; 251 | read_write_command<=1'h1; 252 | read_address<=6'b011_010; 253 | write_address<=6'hc; //store xor result x1+y1/x1 254 | command_transfer<=1'h1; 255 | end 256 | end 257 | 258 | 6'h11:begin 259 | 260 | if(interupt_transfer) begin 261 | fsm<=6'h29; 262 | read_write_command<=1'h0; 263 | read_address<=6'hc; 264 | write_address<=6'b001_010; //store lambda in inner ram 265 | command_transfer<=1'h1; 266 | end 267 | else 268 | command_transfer<=1'h0; 269 | end 270 | 271 | 272 | 6'h29:begin 273 | command_transfer<=1'h0; 274 | if(interupt_transfer) begin 275 | command_ECC<=4'h2; //square of lambda 276 | start_addr<=3'h3; 277 | fsm<=6'h12; 278 | end 279 | end 280 | 281 | 6'h12:begin 282 | 283 | if(interupt_sqr)begin 284 | fsm<=6'h13; 285 | command_ECC<=4'h4; //reduce Lambda square 286 | start_addr<=3'h2; 287 | end 288 | else 289 | command_ECC<=4'h0; 290 | end 291 | 292 | 6'h13:begin 293 | command_ECC<=4'h0; 294 | if(interupt_red)begin 295 | fsm<=6'h14; 296 | read_write_command<=1'h1; 297 | if(var[1]^var[0]) 298 | read_address<=6'b100_010; 299 | else begin 300 | if(var[2]||var[1]) 301 | read_address<=6'b011_001; 302 | else 303 | read_address<=6'b011_010; 304 | end 305 | write_address<=6'h18; //store lambda^2 in outer ram 306 | command_transfer<=1'h1; 307 | end 308 | end 309 | 310 | 6'h14:begin 311 | if(interupt_transfer)begin 312 | read_write_command<=1'h0; 313 | read_address<=6'h18; 314 | write_address<=6'b010_010; //store lambda sqr in inner ram 315 | command_transfer<=1'h1; 316 | fsm<=6'h15; 317 | end 318 | else 319 | command_transfer<=1'h0; 320 | end 321 | 322 | 323 | 6'h15:begin 324 | command_transfer<=1'h0; 325 | if(interupt_transfer)begin 326 | command_ECC<=4'h6; //xor lamda^2 +lambda 327 | start_addr<=3'h3; 328 | fsm<=6'h16; 329 | end 330 | end 331 | 332 | 6'h16:begin 333 | command_ECC<=4'h0; 334 | if(interupt_Xor)begin 335 | fsm<=6'h1a; 336 | read_write_command<=1'h1; 337 | read_address<=6'b011_010; 338 | write_address<=6'h1b; //store lambda^2+lambda xor in outer ram 339 | command_transfer<=1'h1; 340 | end 341 | end 342 | 343 | 6'h17:begin //remove this cycle 344 | 345 | if(interupt_transfer)begin 346 | read_write_command<=1'h0; 347 | read_address<=6'h0; 348 | write_address<=6'b010_010; //store 1 in inner ram 349 | command_transfer<=1'h1; 350 | fsm<=6'h18; 351 | end 352 | else 353 | command_transfer<=1'h0; 354 | end 355 | 356 | 357 | 6'h18:begin //remove this cycle 358 | command_transfer<=1'h0; 359 | if(interupt_transfer)begin 360 | command_ECC<=4'h6; //xor lamda +1 361 | start_addr<=3'h3; 362 | fsm<=6'h19; 363 | end 364 | end 365 | 366 | 6'h19:begin //remove this cycle 367 | command_ECC<=4'h0; 368 | if(interupt_Xor) begin 369 | fsm<=6'h1a; 370 | read_write_command<=1'h1; 371 | read_address<=6'b011_010; 372 | write_address<=6'h1e; //store 1+lambda xor in outer ram 373 | command_transfer<=1'h1; 374 | end 375 | end 376 | 377 | 6'h1a:begin 378 | if(interupt_transfer)begin 379 | fsm<=6'h1b; 380 | read_write_command<=1'h0; 381 | read_address<=6'h1b; 382 | write_address<=6'b010_010; //store lambda^2+lambda xor in iner ram 383 | command_transfer<=1'h1; 384 | end 385 | else 386 | command_transfer<=1'h0; 387 | end 388 | 389 | 6'h1b:begin 390 | if(interupt_transfer)begin 391 | fsm<=6'h1c; 392 | read_write_command<=1'h0; 393 | read_address<=6'h9; 394 | write_address<=6'b001_010; //store a in inner Ram 395 | command_transfer<=1'h1; 396 | end 397 | else 398 | command_transfer<=1'h0; 399 | end 400 | 401 | 6'h1c:begin 402 | command_transfer<=1'h0; 403 | if(interupt_transfer)begin 404 | fsm<=6'h1d; 405 | command_ECC<=4'h6; //Xor lambda^2+lambda+a 406 | end 407 | end 408 | 409 | 6'h1d:begin 410 | command_ECC<=4'h0; 411 | if(interupt_Xor) begin 412 | fsm<=6'h1e; 413 | read_write_command<=1'h1; 414 | read_address<=6'b011_010; 415 | write_address<=6'h3; // x3 or store result Xor lambda^2+lambda+a 416 | command_transfer<=1'h1; 417 | end 418 | end 419 | 420 | 6'h1e:begin 421 | 422 | if(interupt_transfer)begin 423 | read_write_command<=1'h0; 424 | read_address<=6'h3; 425 | write_address<=6'b001_010; //store x3 in inner Ram 426 | command_transfer<=1'h1; 427 | fsm<=6'h1f; 428 | end 429 | else 430 | command_transfer<=1'h0; 431 | end 432 | 433 | 434 | 6'h1f:begin 435 | 436 | if(interupt_transfer)begin 437 | read_write_command<=1'h0; 438 | read_address<=6'hc; 439 | write_address<=6'b010_010; //store lambda in inner Ram 440 | command_transfer<=1'h1; 441 | fsm<=6'h20; 442 | end 443 | else 444 | command_transfer<=1'h0; 445 | end 446 | 447 | 448 | 6'h20:begin 449 | command_transfer<=1'h0; 450 | if(interupt_transfer) begin 451 | fsm<=6'h21; 452 | command_ECC<=4'h1; //multi (lambda)*X3 453 | end 454 | end 455 | 456 | 6'h21:begin 457 | 458 | if(interupt_mul)begin 459 | command_ECC<=6'h4; 460 | fsm<=6'h22; //reduction (lambda)*X3 461 | start_addr<=3'h2; 462 | end 463 | else 464 | command_ECC<=4'h0; 465 | end 466 | 467 | 6'h22:begin 468 | command_ECC<=4'h0; 469 | if(interupt_red) begin 470 | read_write_command<=1'h1; 471 | if(var[1]^var[0]) 472 | read_address<=6'b100_010; 473 | else begin 474 | if(var[2]||var[1]) 475 | read_address<=6'b011_001; 476 | else 477 | read_address<=6'b011_010; 478 | end 479 | write_address<=6'h24; //store (lambda)*X3 in outer Ram 480 | command_transfer<=1'h1; 481 | fsm<=6'h23; 482 | end 483 | end 484 | 485 | 486 | 487 | 6'h23:begin 488 | if(interupt_transfer)begin 489 | read_write_command<=1'h0; 490 | read_address<=6'h24; 491 | write_address<=6'b001_010; //store (lambda)*X3 in inner Ram 492 | command_transfer<=1'h1; 493 | fsm<=7'h32; 494 | end 495 | else 496 | command_transfer<=1'h0; 497 | end 498 | 499 | 6'h32:begin 500 | if(interupt_transfer)begin 501 | read_write_command<=1'h0; 502 | read_address<=6'h3; 503 | write_address<=6'b010_010; //store X3 in inner Ram 504 | command_transfer<=1'h1; 505 | fsm<=7'h33; 506 | end 507 | else begin 508 | command_transfer<=1'h0; 509 | end 510 | end 511 | 512 | 6'h33:begin 513 | 514 | command_transfer<=1'h0; 515 | if(interupt_transfer)begin 516 | command_ECC<=4'h6; 517 | fsm<=6'h34; //xor (lambda)*X3+X3 518 | start_addr<=4'h3; 519 | end 520 | end 521 | 522 | 6'h34:begin 523 | command_ECC<=4'h0; 524 | if(interupt_Xor) begin 525 | fsm<=6'h35; 526 | read_write_command<=1'h1; 527 | read_address<=6'b011_010; 528 | write_address<=6'h1e; // store (lambda)*X3+X3 in address 1e of outer ram 529 | command_transfer<=1'h1; 530 | end 531 | 532 | end 533 | 534 | 6'h35:begin 535 | if(interupt_transfer)begin 536 | read_write_command<=1'h0; 537 | read_address<=6'h1e; 538 | write_address<=6'b001_010; //store (lambda)*X3+X3 into inner ram 539 | command_transfer<=1'h1; 540 | fsm<=6'h24; 541 | end 542 | else 543 | command_transfer<=1'h0; 544 | end 545 | 546 | 6'h24:begin 547 | if(interupt_transfer)begin 548 | read_write_command<=1'h0; 549 | read_address<=6'hf; 550 | write_address<=6'b010_010; //store x1^2 in inner Ram 551 | command_transfer<=1'h1; 552 | fsm<=6'h25; 553 | end 554 | else 555 | command_transfer<=1'h0; 556 | end 557 | 558 | 6'h25:begin 559 | command_transfer<=1'h0; 560 | if(interupt_transfer)begin 561 | command_ECC<=4'h6; 562 | fsm<=6'h26; //xor x1^2+(lambda)*X3 563 | start_addr<=4'h3; 564 | end 565 | end 566 | 567 | 6'h26:begin 568 | command_ECC<=4'h0; 569 | if(interupt_Xor)begin 570 | read_write_command<=1'h1; 571 | read_address<=6'b011_010; 572 | write_address<=6'h6; //store y3 in outer Ram 573 | command_transfer<=1'h1; 574 | fsm<=6'h27; 575 | end 576 | end 577 | 578 | 579 | 6'h27:begin 580 | command_transfer<=1'h0; 581 | if(interupt_transfer) begin 582 | fsm<=6'h28; 583 | interupt<=1'h1; 584 | end 585 | end 586 | 587 | 6'h28:begin 588 | cmd_double<=1'h0; 589 | interupt<=1'h0; 590 | fsm<=6'h30; 591 | end 592 | 593 | 6'h30:begin 594 | fsm<=6'h31; 595 | end 596 | 597 | 598 | endcase 599 | end 600 | endmodule 601 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/saa_ks_96.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 09:27:55 07/28/2014 7 | // Design Name: 8 | // Module Name: bit_3_karatsuba_testing 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mul_6_shift( //15 lut on implement 22 | input[5:0] A_6, 23 | input[5:0] B_6, 24 | output[11:0] C_6 25 | ); 26 | 27 | wire[11:0] d,d1,d4,d5,d3,d2; 28 | 29 | assign d[5:0]=A_6[5:0]; 30 | assign d[11:6]=46'b0; 31 | assign d1=B_6[0]?d:11'b0; 32 | assign d2=B_6[1]?d1^d<<1:d1; 33 | assign d3=B_6[2]?d2^d<<2:d2; 34 | assign d4=B_6[3]?d3^d<<3:d3; 35 | assign d5=B_6[4]?d4^d<<4:d4; 36 | assign C_6[11:0]=B_6[5]?d5^d<<5:d5; 37 | 38 | 39 | endmodule 40 | 41 | 42 | module mul_12_module_Xor( //63 slices on implementation 43 | input[11:0] A, 44 | input[11:0] B, 45 | output[23:0] mul_12 46 | ); 47 | 48 | wire[11:0] d0,d1,d2,d3; 49 | 50 | mul_6_shift mul_0( 51 | (A[5:0]), 52 | (B[5:0]), 53 | (d0) 54 | ); 55 | 56 | mul_6_shift mul_1( 57 | (A[5:0]^A[11:6]), 58 | (B[5:0]^B[11:6]), 59 | (d1) 60 | ); 61 | 62 | mul_6_shift mul_2( 63 | A[11:6], 64 | B[11:6], 65 | (d2) 66 | ); 67 | 68 | assign mul_12[23:0]= {d2[11:6],d2[5:0]^d0[11:6]^d2[11:6]^d1[11:6],d0[11:6]^d0[5:0]^d2[5:0]^d1[5:0],d0[5:0]}; 69 | 70 | endmodule 71 | 72 | 73 | 74 | 75 | module mul_24_module_Xor( //217 slices on implementation 76 | //o5 &o6 114 77 | input[23:0] A, //O6 103 78 | input[23:0] B, 79 | output[47:0] mul_24 80 | ); 81 | 82 | wire[23:0] d0,d1,d2,d3; 83 | 84 | mul_12_module_Xor mul_0( 85 | (A[11:0]), 86 | (B[11:0]), 87 | (d0) 88 | ); 89 | 90 | mul_12_module_Xor mul_1( 91 | (A[11:0]^A[23:12]), 92 | (B[11:0]^B[23:12]), 93 | (d1) 94 | ); 95 | 96 | mul_12_module_Xor mul_2( 97 | A[23:12], 98 | B[23:12], 99 | (d2) 100 | ); 101 | 102 | assign mul_24[47:0]= {d2[23:12],d2[11:0]^d2[23:12]^d0[23:12]^d1[23:12],d0[23:12]^d2[11:0]^d0[11:0]^d1[11:0],d0[11:0]}; 103 | 104 | endmodule 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | module mul_48_module_Xor( //717 slices on implementation 113 | input[47:0] A, // O6 351 114 | input[47:0] B, // O5 &O6 366 115 | output[95:0] mul_48 116 | ); 117 | 118 | wire[47:0] d0,d1,d2,d3; 119 | 120 | mul_24_module_Xor mul_0( 121 | (A[23:0]), 122 | (B[23:0]), 123 | (d0) 124 | ); 125 | 126 | mul_24_module_Xor mul_1( 127 | (A[23:0]^A[47:24]), 128 | (B[23:0]^B[47:24]), 129 | (d1) 130 | ); 131 | 132 | mul_24_module_Xor mul_2( 133 | A[47:24], 134 | B[47:24], 135 | (d2) 136 | ); 137 | 138 | assign mul_48[95:0]= {d2[47:24],d2[23:0]^d0[47:24]^d1[47:24]^d2[47:24],d0[47:24]^d0[23:0]^d2[23:0]^d1[23:0],d0[23:0]}; 139 | 140 | endmodule 141 | 142 | 143 | 144 | 145 | 146 | 147 | module mul_96_module_Xor( //717 slices on implementation 148 | input[95:0] A, // O6 351 149 | input[95:0] B, // O5 &O6 366 150 | output[190:0] mul_96 151 | ); 152 | 153 | wire[95:0] d0,d1,d2,d3; 154 | 155 | mul_48_module_Xor mul_0( 156 | (A[47:0]), 157 | (B[47:0]), 158 | (d0) 159 | ); 160 | 161 | mul_48_module_Xor mul_1( 162 | (A[47:0]^A[95:48]), 163 | (B[47:0]^B[95:48]), 164 | (d1) 165 | ); 166 | 167 | mul_48_module_Xor mul_2( 168 | A[95:48], 169 | B[95:48], 170 | (d2) 171 | ); 172 | 173 | 174 | assign mul_96[191:0]= {d2[95:48],d2[47:0]^d0[95:48]^d2[95:48]^d1[95:48],d0[95:48]^d0[47:0]^d1[47:0]^d2[47:0],d0[47:0]}; 175 | 176 | endmodule 177 | 178 | 179 | 180 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/scalar_multiplication_module.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /*In this program the first five case are used for sending x1,x2,y1,y2,a into inner ram*/ 4 | ////////////////////////////////////////////////////////////////////////////////// 5 | // Company: 6 | // Engineer: Rahul 7 | // 8 | // Create Date: 15:48:45 10/17/2014 9 | // Design Name: 10 | // Module Name: scalar_multiplication_module 11 | // Project Name: 12 | // Target Devices: 13 | // Tool versions: 14 | // Description: 15 | // 16 | // Dependencies: 17 | // 18 | // Revision: 19 | // Revision 0.01 - File Created 20 | // Additional Comments: 21 | // 22 | ////////////////////////////////////////////////////////////////////////////////// 23 | module scalar_multiplication_module( 24 | 25 | input wire clk, 26 | input wire interupt_point_add, 27 | input wire interupt_point_double, 28 | input wire interupt_ram_transfer, 29 | input wire command_scalar_multiplication, 30 | 31 | output reg read_write_command, 32 | output reg [5:0] read_address, //Read Address where to read from 33 | output reg [5:0] write_address, //Write Address where to write from 34 | output reg interupt_scalar_mul, 35 | output reg cmd_transfer, //for initiating transfer operation 36 | output reg [1:0] command_add_double, 37 | //input wire [1:0] no_of_chunks_frm_tb, 38 | input wire [575:0] scalar_multiplication 39 | //input private key 40 | ); 41 | 42 | reg [4:0] fsm; 43 | reg command_strt; 44 | reg [4:0]count; 45 | reg [575:0] private_key; 46 | reg [3:0] count_check_one; //1024 bit number can have atmost 11 ones 47 | reg check_one; 48 | reg frst_check_one; 49 | reg frst_check,var; 50 | 51 | initial begin 52 | 53 | //private_key <= random_number; 54 | interupt_scalar_mul <= 1'h0; 55 | end 56 | 57 | always @(posedge clk) begin 58 | 59 | //scalar multiplication starts here 60 | if (command_scalar_multiplication)begin 61 | fsm <= 5'h1; 62 | end 63 | 64 | case (fsm) 65 | 66 | 5'h1:begin 67 | fsm <= 5'h2; //sending x1 into addr 3 of inner ram 68 | read_write_command <= 1'h0; 69 | read_address <= 6'h3; 70 | write_address <= 6'h3; 71 | cmd_transfer <= 1'h1; 72 | 73 | private_key <= scalar_multiplication; 74 | 75 | end 76 | 77 | 5'h2:begin 78 | if (interupt_ram_transfer)begin 79 | fsm <= 5'h3; //sending y1 into addr 6 of inner ram 80 | read_write_command <= 1'h0; 81 | read_address <= 6'h6; 82 | write_address <= 6'h6; 83 | cmd_transfer <= 1'h1; 84 | end 85 | else 86 | cmd_transfer<=1'h0; 87 | end 88 | 89 | 5'h3:begin 90 | if (interupt_ram_transfer)begin 91 | fsm <= 5'h4; //writing a into addr 9 of inner ram 92 | read_write_command <= 1'h0; 93 | read_address <= 6'h9; 94 | write_address <= 6'h9; 95 | cmd_transfer <= 1'h1; 96 | private_key <= private_key/2'h2; 97 | check_one <= private_key[0]; 98 | frst_check <= private_key[0]; 99 | var<=private_key[0]; 100 | end 101 | else 102 | cmd_transfer<=1'h0; 103 | end 104 | 105 | 5'h4:begin 106 | if (interupt_ram_transfer)begin //sending x1 into addr 33 of inner ram(point_add) 107 | 108 | if (check_one)begin 109 | fsm <= 5'h5; 110 | read_write_command <= 1'h0; 111 | read_address <= 6'h19; 112 | write_address <= 6'h21; 113 | cmd_transfer <= 1'h1; 114 | end 115 | else 116 | fsm <= 5'h7; 117 | end 118 | else 119 | cmd_transfer<=1'h0; 120 | end 121 | 122 | 5'h5:begin 123 | if (interupt_ram_transfer)begin 124 | fsm <= 5'h6; //sending y1 into addr 39 of inner ram(point_add) 125 | read_write_command <= 1'h0; 126 | read_address <= 6'h1c; 127 | write_address <= 6'h27; 128 | cmd_transfer <= 1'h1; 129 | end 130 | else 131 | cmd_transfer<=1'h0; 132 | end 133 | 134 | 135 | 5'h6:begin 136 | if (interupt_ram_transfer)begin 137 | fsm <= 5'h7; 138 | end 139 | else 140 | cmd_transfer<=1'h0; 141 | end 142 | 143 | 5'h7:begin 144 | 145 | private_key <= private_key/2'h2; 146 | check_one <= private_key[0]; 147 | if (private_key != 576'h0)begin 148 | command_add_double <= 2'h2; 149 | fsm <= 5'h8; 150 | end 151 | else begin 152 | if(var) begin 153 | command_add_double <= 2'h1; 154 | fsm<=5'ha; 155 | end 156 | else 157 | fsm<=5'hb; 158 | end 159 | end 160 | 161 | 5'h8:begin 162 | if (interupt_point_double) begin 163 | 164 | if(!frst_check && check_one) begin 165 | fsm<=5'hc; 166 | frst_check<=1'h1; 167 | end 168 | else begin 169 | if (check_one)begin 170 | //var<=1'h1; 171 | command_add_double <= 2'h1; 172 | fsm <= 5'h9; 173 | end 174 | else 175 | fsm<=5'h7; 176 | end 177 | end 178 | else 179 | command_add_double <= 2'h0; 180 | end 181 | 182 | 5'h9:begin 183 | if (interupt_point_add)begin 184 | fsm <= 5'h7; 185 | end 186 | else 187 | command_add_double <= 2'h0; 188 | end 189 | 190 | 5'ha:begin 191 | if(interupt_point_add)begin 192 | fsm <= 5'hb; //writing x1 into addr 33 of outer ram 193 | end 194 | else 195 | command_add_double<=2'h0; 196 | 197 | end 198 | 199 | 200 | 5'hc:begin 201 | fsm <= 5'hd; //writing x1 into addr 33 of outer ram 202 | read_write_command <= 1'h1; 203 | read_address <= 6'h3; 204 | write_address <= 6'h21; 205 | cmd_transfer <= 1'h1; 206 | end 207 | 208 | 5'hd:begin 209 | if (interupt_ram_transfer)begin 210 | fsm <= 5'he; //writing y1 into addr 39 of outer ram 211 | read_write_command <= 1'h1; 212 | read_address <= 6'h6; 213 | write_address <= 6'h27; 214 | cmd_transfer <= 1'h1; 215 | end 216 | else 217 | cmd_transfer <= 1'h0; 218 | end 219 | 220 | 5'he:begin 221 | if (interupt_ram_transfer)begin 222 | fsm <= 5'hf; //writing x1 into addr 33 of inner ram 223 | read_write_command <= 1'h0; 224 | read_address <= 6'h21; 225 | write_address <= 6'h21; 226 | cmd_transfer <= 1'h1; 227 | end 228 | else 229 | cmd_transfer <= 1'h0; 230 | end 231 | 232 | 5'hf:begin 233 | if (interupt_ram_transfer)begin 234 | fsm <= 5'h10; //writing y1 into addr 39 of inner ram 235 | read_write_command <= 1'h0; 236 | read_address <= 6'h27; 237 | write_address <= 6'h27; 238 | cmd_transfer <= 1'h1; 239 | end 240 | else 241 | cmd_transfer <= 1'h0; 242 | end 243 | 244 | 5'h10:begin 245 | if (interupt_ram_transfer)begin 246 | fsm <= 5'h7; 247 | end 248 | else 249 | cmd_transfer<=1'h0; 250 | end 251 | 252 | 253 | 5'hb:begin 254 | fsm<=5'h11; 255 | read_write_command <= 1'h1; 256 | read_address <= 6'h21; 257 | write_address <= 6'h21; 258 | cmd_transfer <= 1'h1; 259 | end 260 | 261 | 5'h11:begin 262 | if(interupt_ram_transfer)begin 263 | fsm <= 5'h12; //writing y1 into addr 39 of outer ram 264 | read_write_command <= 1'h1; 265 | read_address <= 6'h27; 266 | write_address <= 6'h27; 267 | cmd_transfer <= 1'h1; 268 | end 269 | else 270 | cmd_transfer <= 1'h0; 271 | end 272 | 273 | 5'h12:begin 274 | if(interupt_ram_transfer) begin 275 | interupt_scalar_mul <= 1'h1; 276 | fsm <= 5'h13; 277 | end 278 | else 279 | cmd_transfer <= 1'h0; 280 | end 281 | 282 | 5'h13:begin 283 | interupt_scalar_mul <= 1'h0; 284 | end 285 | 286 | endcase 287 | end 288 | endmodule 289 | 290 | 291 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/sqr_slice_testing.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:04:41 06/30/2014 7 | // Design Name: 8 | // Module Name: sqr_slice_testing 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | //////////////////////////////////////////////////////////////////////////////////// 21 | //module sqr_slice_testing( 22 | 23 | module sqr_4_module( 24 | input[3:0] A, 25 | output wire[7:0] Out_4 26 | ); 27 | // reg[7:0] Out_4; 28 | /* always @(A) 29 | begin 30 | case (A) 31 | 4'b0000:Out_4=8'h00; 32 | 4'b0001:Out_4=8'h01; 33 | 4'b0010:Out_4=8'h04; 34 | 4'b0011:Out_4=8'h05; 35 | 4'b0100:Out_4=8'h10; 36 | 4'b0101:Out_4=8'h11; 37 | 4'b0110:Out_4=8'h14; 38 | 4'b0111:Out_4=8'h15; 39 | 4'b1000:Out_4=8'h40; 40 | 4'b1001:Out_4=8'h41; 41 | 4'b1010:Out_4=8'h44; 42 | 4'b1011:Out_4=8'h45; 43 | 4'b1100:Out_4=8'h50; 44 | 4'b1101:Out_4=8'h51; 45 | 4'b1110:Out_4=8'h54; 46 | 4'b1111:Out_4=8'h55; 47 | endcase 48 | end*/ 49 | assign Out_4 = {1'b0,A[3],1'b0,A[2],1'b0,A[1],1'b0,A[0]}; 50 | endmodule 51 | 52 | module sqr_128_module( 53 | input[127:0] A, 54 | output[255:0] Out 55 | ); 56 | wire [7:0] d1,d0,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20,d21,d22,d23,d24,d25,d26,d27,d28,d29,d30,d31; 57 | 58 | sqr_4_module uut1( 59 | .A(A[3:0]), 60 | .Out_4(d0)); 61 | 62 | sqr_4_module uut ( 63 | .A(A[7:4]), 64 | .Out_4(d1)); 65 | 66 | sqr_4_module uut2 ( 67 | .A(A[11:8]), 68 | .Out_4(d2)); 69 | 70 | sqr_4_module uut3( 71 | .A(A[15:12]), 72 | .Out_4(d3)); 73 | 74 | sqr_4_module uut4 ( 75 | .A(A[19:16]), 76 | .Out_4(d4)); 77 | 78 | sqr_4_module uut5( 79 | .A(A[23:20]), 80 | .Out_4(d5)); 81 | 82 | sqr_4_module uut6 ( 83 | .A(A[27:24]), 84 | .Out_4(d6)); 85 | 86 | sqr_4_module uut7( 87 | .A(A[31:28]), 88 | .Out_4(d7)); 89 | 90 | sqr_4_module uut8( 91 | .A(A[35:32]), 92 | .Out_4(d8)); 93 | 94 | sqr_4_module uut9 ( 95 | .A(A[39:36]), 96 | .Out_4(d9)); 97 | 98 | sqr_4_module uut10 ( 99 | .A(A[43:40]), 100 | .Out_4(d10)); 101 | 102 | sqr_4_module uut11( 103 | .A(A[47:44]), 104 | .Out_4(d11)); 105 | 106 | sqr_4_module uut12 ( 107 | .A(A[51:48]), 108 | .Out_4(d12)); 109 | 110 | sqr_4_module uut13( 111 | .A(A[55:52]), 112 | .Out_4(d13)); 113 | 114 | sqr_4_module uut14 ( 115 | .A(A[59:56]), 116 | .Out_4(d14)); 117 | 118 | sqr_4_module uut15( 119 | .A(A[63:60]), 120 | .Out_4(d15)); 121 | 122 | sqr_4_module uut16 ( 123 | .A(A[67:64]), 124 | .Out_4(d16)); 125 | 126 | sqr_4_module uut17( 127 | .A(A[71:68]), 128 | .Out_4(d17)); 129 | 130 | sqr_4_module uut18( 131 | .A(A[75:72]), 132 | .Out_4(d18)); 133 | 134 | sqr_4_module uut19 ( 135 | .A(A[79:76]), 136 | .Out_4(d19)); 137 | 138 | sqr_4_module uut20 ( 139 | .A(A[83:80]), 140 | .Out_4(d20)); 141 | 142 | sqr_4_module uut21( 143 | .A(A[87:84]), 144 | .Out_4(d21)); 145 | 146 | sqr_4_module uut22 ( 147 | .A(A[91:88]), 148 | .Out_4(d22)); 149 | 150 | sqr_4_module uut23( 151 | .A(A[95:92]), 152 | .Out_4(d23)); 153 | 154 | sqr_4_module uut24 ( 155 | .A(A[99:96]), 156 | .Out_4(d24)); 157 | 158 | sqr_4_module uut25( 159 | .A(A[103:100]), 160 | .Out_4(d25)); 161 | 162 | 163 | 164 | sqr_4_module uut26 ( 165 | .A(A[107:104]), 166 | .Out_4(d26)); 167 | 168 | sqr_4_module uut27( 169 | .A(A[111:108]), 170 | .Out_4(d27)); 171 | 172 | sqr_4_module uut28( 173 | .A(A[115:112]), 174 | .Out_4(d28)); 175 | 176 | sqr_4_module uut29 ( 177 | .A(A[119:116]), 178 | .Out_4(d29)); 179 | 180 | sqr_4_module uut30 ( 181 | .A(A[123:120]), 182 | .Out_4(d30)); 183 | 184 | sqr_4_module uut31( 185 | .A(A[127:124]), 186 | .Out_4(d31)); 187 | 188 | 189 | assign Out[255:0]={d31,d30,d29,d28,d27,d26,d25,d24,d23,d22,d21,d20,d19,d18,d17,d16,d15,d14,d13,d12,d11,d10,d9,d8,d7,d6,d5,d4,d3,d2,d1,d0}; 190 | 191 | endmodule 192 | 193 | 194 | 195 | 196 | 197 | 198 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/state_machine_3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Deepak 5 | // 6 | // Create Date: 13:02:01 09/22/2014 7 | // Design Name: 8 | // Module Name: state 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module state_machine_point_add#( 22 | parameter Data=255, 23 | parameter Addr=5)( 24 | input wire clk, 25 | input wire w_RAM_outer_PORT, 26 | input wire [Addr:0] adbus_RAM_outer_PORT, //Address Bus 27 | input wire [Data:0] data_in_RAM_outer_PORT, //Data bus for taking input 28 | output wire [Data:0] data_out_RAM_outer_PORT, //Data bus for taking output 29 | 30 | input wire [1:0] command, //command to perform point addition and doubling 31 | input wire [1:0] no_of_chunks, 32 | input wire [255:0] Data_Polynomial, 33 | input wire [9:0] Data_len_Polynomial, 34 | 35 | output wire interupt_point_double, 36 | output wire interupt_point_addition 37 | 38 | ); 39 | 40 | reg [Addr:0] address_bus; 41 | reg a_w1; 42 | reg [Addr:0] a_adbus1; 43 | reg [Data:0] a_data_in1; 44 | 45 | wire [Data:0] data_in_ECC,data_in_ECC_transfer,data_out_ECC,data_in_RAM_inner_PORT,data_out_RAM_inner_PORT; 46 | wire [Addr:0] adbus_ECC,adbus_ECC_transfer,adbus_RAM_inner_PORT; 47 | wire [3:0] command_ECC,command_ECC_addition,command_ECC_double; 48 | wire [2:0] start_addr,start_addr_addition,start_addr_double; 49 | wire interupt_sqr,interupt_red,interupt_inv,interupt_swap,interupt_Xor,interupt_mul; 50 | 51 | state_machine_ECC_primitive ECC_primitive_state_machine ( 52 | .clk(clk), 53 | 54 | .a_w(w_ECC), 55 | .a_adbus(adbus_ECC), 56 | .a_data_in(data_in_ECC), 57 | .a_data_out(data_out_ECC), 58 | 59 | .command_ECC(command_ECC), 60 | .start_addr(start_addr), 61 | 62 | .interupt_sqr(interupt_sqr), 63 | .interupt_red(interupt_red), 64 | .interupt_swap(interupt_swap), 65 | .interupt_inv(interupt_inv), 66 | .interupt_mul(interupt_mul), 67 | .interupt_Xor(interupt_Xor), 68 | 69 | .Data_len_Polynomial(Data_len_Polynomial), 70 | .Data_Polynomial(Data_Polynomial[63:0]) 71 | ); 72 | 73 | wire [Addr:0] read_address,read_address_addition,read_address_double, write_address , adbus_outer_transfer, 74 | write_address_addition ,write_address_double ; 75 | wire read_write_command ,interupt_transfer,command_transfer; 76 | 77 | wire [Data:0] data_in_outer_transfer; 78 | wire cmd_double,cmd_addition; 79 | wire w_ECC,w_RAM_inner_PORT; 80 | //Ram transfer module for transferring Data from outer to ECC primivtive Ram 81 | Ram_data_transfer Ram_transfer ( 82 | .clk(clk), 83 | 84 | .w_RAM(w_RAM_inner_PORT), 85 | .adbus_RAM(adbus_RAM_inner_PORT), //port for Ram in this layer 86 | .data_in_RAM(data_in_RAM_inner_PORT), 87 | .data_out_RAM(data_out_RAM_inner_PORT), 88 | 89 | .w_ECC(w_ECC), //port for inner Ram 90 | .adbus_ECC(adbus_ECC), 91 | .data_in_ECC(data_in_ECC), 92 | .data_out_ECC(data_out_ECC), 93 | 94 | .read_write_command(read_write_command), //port for performing operation 95 | .read_address(read_address), 96 | .write_address(write_address), 97 | .no_of_chunks(no_of_chunks), 98 | .command(command_transfer), 99 | 100 | .interupt(interupt_transfer) 101 | ); 102 | 103 | //Ram interface Module 104 | Outer_Ram_interface Ram_interface ( 105 | .clk(clk), 106 | .a_w(w_RAM_outer_PORT), 107 | .a_adbus(adbus_RAM_outer_PORT), //Port to interface Outside 108 | .a_data_in(data_in_RAM_outer_PORT), 109 | .a_data_out(data_out_RAM_outer_PORT), 110 | 111 | .b_w(w_RAM_inner_PORT), 112 | .b_adbus(adbus_RAM_inner_PORT), //Port for interfacing inside 113 | .b_data_in(data_in_RAM_inner_PORT), 114 | .b_data_out(data_out_RAM_inner_PORT) 115 | ); 116 | 117 | wire command_transfer_double, command_transfer_addition; 118 | wire read_write_command_double,read_write_command_addition; 119 | 120 | point_addition_module point_addition ( 121 | .clk(clk), 122 | .interupt_sqr(interupt_sqr), 123 | .interupt_red(interupt_red), 124 | .interupt_swap(interupt_swap), 125 | .interupt_inv(interupt_inv), 126 | .interupt_mul(interupt_mul), 127 | .interupt_Xor(interupt_Xor), 128 | .interupt_transfer(interupt_transfer), 129 | 130 | .start_addr(start_addr_addition), 131 | .command_ECC(command_ECC_addition), 132 | 133 | .interupt(interupt_point_addition), 134 | .cmd_addition(cmd_addition), 135 | 136 | .read_write_command(read_write_command_addition), 137 | .read_address(read_address_addition), 138 | .write_address(write_address_addition), 139 | .Data_len_Polynomial(Data_len_Polynomial), 140 | 141 | .command_transfer(command_transfer_addition), 142 | .command(command) //comand to perform point addition 143 | ); 144 | 145 | 146 | point_double_module point_double ( 147 | .clk(clk), 148 | .interupt_sqr(interupt_sqr), 149 | .interupt_red(interupt_red), 150 | .interupt_swap(interupt_swap), 151 | .interupt_inv(interupt_inv), 152 | .interupt_mul(interupt_mul), 153 | .interupt_Xor(interupt_Xor), 154 | .interupt_transfer(interupt_transfer), 155 | 156 | .start_addr(start_addr_double), //start_addr where to start ECC primitive operation 157 | .command_ECC(command_ECC_double), //command to perform ECC primitive 158 | .interupt(interupt_point_double), 159 | .cmd_double(cmd_double), //enable to perform doubling operation 160 | 161 | .read_write_command(read_write_command_double), 162 | .read_address(read_address_double), 163 | .write_address(write_address_double), 164 | 165 | .command_transfer(command_transfer_double), 166 | .Data_len_Polynomial(Data_len_Polynomial), 167 | .command(command) //command to perform point doubling 168 | ); 169 | 170 | 171 | assign start_addr=cmd_addition?start_addr_addition: 172 | cmd_double?start_addr_double:start_addr; 173 | 174 | 175 | 176 | assign command_ECC=cmd_addition?command_ECC_addition: 177 | cmd_double?command_ECC_double:command_ECC; 178 | 179 | assign read_write_command=cmd_double?read_write_command_double: 180 | cmd_addition?read_write_command_addition:1'hz; 181 | 182 | assign read_address=cmd_double?read_address_double: 183 | cmd_addition?read_address_addition:read_address; 184 | 185 | assign write_address=cmd_double?write_address_double: 186 | cmd_addition?write_address_addition:write_address; 187 | 188 | assign command_transfer=cmd_double?command_transfer_double: 189 | cmd_addition?command_transfer_addition:1'h0; 190 | endmodule 191 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/state_machine_inverse.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: BARC 4 | // Engineer: Deepak 5 | // 6 | // Create Date: 23:57:09 09/15/2014 7 | // Design Name: 8 | // Module Name: state_machine_inverse 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module state_machine_ECC_primitive#( 22 | parameter DATA=256)( 23 | 24 | input wire clk, 25 | input wire a_w, 26 | input wire [5:0] a_adbus, 27 | input wire [(DATA-1):0] a_data_in, 28 | output wire [(DATA-1):0] a_data_out, 29 | 30 | input wire [3:0] command_ECC, 31 | input wire [2:0] start_addr, 32 | output wire interupt_sqr, 33 | output wire interupt_red, 34 | output wire interupt_swap, 35 | output wire interupt_inv, 36 | output wire interupt_mul, 37 | output wire interupt_Xor, 38 | input wire [9:0] Data_len_Polynomial, 39 | input wire [63:0] Data_Polynomial 40 | ); 41 | 42 | wire select_Ram_A_Or_B,select_Ram_C_Or_D,cmd_inv; 43 | wire [1:0] numbr_of_chunk; 44 | wire [2:0] write_addr_inv,read_addr_inv,read_addr_seq,write_addr_seq,b_adbus_A; 45 | wire [3:0] b_command_inv,b_command_seq, command; 46 | 47 | 48 | 49 | sequential_state_module sequential_module ( 50 | .clk(clk), 51 | .a_w(a_w), 52 | .a_adbus(a_adbus), 53 | .a_data_in(a_data_in), 54 | 55 | .a_data_out(a_data_out), 56 | .start_addr(read_addr_seq), 57 | .write_addr(write_addr_seq), 58 | .b_command(b_command_seq), 59 | 60 | .interupt_sqr(interupt_sqr), 61 | .interupt_red(interupt_red), 62 | .interupt_swap(interupt_swap), 63 | .interupt_mul(interupt_mul), 64 | .interupt_Xor(interupt_Xor), 65 | 66 | .select_Ram_C_Or_D(select_Ram_C_Or_D), 67 | .select_Ram_A_Or_B(select_Ram_A_Or_B), 68 | .numbr_of_chunk(numbr_of_chunk), 69 | 70 | .cmd_inv(cmd_inv), 71 | .command (command), 72 | 73 | .Data_len_Polynomial (Data_len_Polynomial), 74 | .Data_Polynomial(Data_Polynomial) 75 | ); 76 | 77 | 78 | inverse_itoha_tsuji_module inverse ( 79 | .clk(clk), 80 | 81 | .read_addr_inv(read_addr_inv), //give addr for square mul reduction 82 | .write_addr_inv(write_addr_inv), 83 | .start_addr(start_addr), 84 | .b_command(b_command_inv), 85 | 86 | .interupt_sqr(interupt_sqr), 87 | .interupt_red(interupt_red), 88 | .interupt_swap(interupt_swap), 89 | .interupt_mul(interupt_mul), 90 | .interupt(interupt_inv), 91 | 92 | .select_Ram_C_Or_D(select_Ram_C_Or_D), 93 | .select_Ram_A_Or_B(select_Ram_A_Or_B), 94 | .numbr_of_chunk(numbr_of_chunk), 95 | .cmd_inv(cmd_inv), 96 | .command (command), 97 | .Data_len_Polynomial (Data_len_Polynomial) 98 | ); 99 | 100 | assign b_command_seq=(cmd_inv)?b_command_inv:command_ECC; 101 | assign read_addr_seq=(cmd_inv)?read_addr_inv:start_addr; 102 | assign write_addr_seq=(cmd_inv)?write_addr_inv:start_addr; 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/state_machine_scalar_mul.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `default_nettype none 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 14:56:23 10/17/2014 8 | // Design Name: 9 | // Module Name: state-machine_scalar_mul 10 | // Project Name: 11 | // Target Devices: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | module state_machine_scalar_mul #( 24 | parameter Data=255, 25 | parameter Addr=5)( 26 | 27 | input wire clk, 28 | input wire a_w, 29 | input wire [Addr:0] a_adbus, //Address Bus 30 | input wire [Data:0] a_data_in, //Data bus for taking input 31 | output wire [Data:0] a_data_out, //Data bus for taking output 32 | input wire command_scalar_multiplication, 33 | input wire start_operation, 34 | output wire interupt_scalar_mul, 35 | output wire interupt_point_addition, 36 | output wire interupt_point_double 37 | ); 38 | 39 | reg [5:0] address_bus; 40 | reg [1:0] no_of_chunks; 41 | reg [Data:0] Data_Polynomial; 42 | reg [9:0] Data_len_Polynomial; 43 | reg [2:0] fsm; 44 | reg [3:0] count; 45 | reg start,select_operation; 46 | reg [5:0] start_address; 47 | 48 | 49 | initial begin 50 | start <= 1'h0; 51 | count <= 2'h0; 52 | start_address<=6'h14; 53 | select_operation <= 1'h0; 54 | 55 | 56 | $dumpfile("test.vcd"); 57 | $dumpvars(); 58 | 59 | end 60 | 61 | 62 | wire [Data:0] data_out_outer; 63 | reg [575:0] private_key; 64 | 65 | always @(posedge clk) begin //calculating Polynomial and length of polynomial 66 | if(start_operation) begin 67 | address_bus<=start_address; 68 | count<=2'h1; 69 | end 70 | if(count[0]) begin 71 | count<=3'h0; 72 | fsm<=3'h1; 73 | address_bus<=start_address+1'h1; 74 | end 75 | 76 | case (fsm) 77 | 78 | 3'h1:begin 79 | Data_Polynomial<=data_out_outer; 80 | address_bus<=start_address+2'h2; 81 | fsm<=3'h2; 82 | end 83 | 84 | 3'h2:begin 85 | fsm<=3'h3; 86 | Data_len_Polynomial<=Data_Polynomial[41:32]; 87 | no_of_chunks=(Data_Polynomial[41:32]/256+1'h1); 88 | private_key[575:512]<=data_out_outer[63:0]; 89 | address_bus<=start_address+2'h3; 90 | end 91 | 92 | 3'h3:begin 93 | fsm<=3'h4; 94 | private_key[511:256]<=data_out_outer; 95 | end 96 | 97 | 3'h4:begin 98 | fsm<=3'h5; 99 | private_key[255:0]<=data_out_outer; 100 | end 101 | endcase 102 | end 103 | 104 | 105 | assign adbus_outer1 = (transfer_running)?adbus_outer_transfer:address_bus; 106 | 107 | wire [Addr:0] adbus_outer1; 108 | 109 | //Ram interface Module for interfacing with Ram in scalar_mulltiplication 110 | Ram_interface_scalar_mul Ram_interface_scalar_mul ( 111 | 112 | //data coming from testbench 113 | .clk(clk), 114 | .a_w(a_w), 115 | .a_adbus(a_adbus), 116 | .a_data_in(a_data_in), 117 | .a_data_out(a_data_out), 118 | 119 | //port for 120 | //ram-interface which inturn interfaces with scalar multiplication module 121 | .b_w(b_outer), 122 | .b_adbus(adbus_outer1), 123 | .b_data_in(data_in_to_outer), 124 | .b_data_out(data_out_outer) 125 | ); 126 | 127 | wire [5:0] adbus_outer_transfer,adbus_inner; 128 | wire [Data:0] data_in_to_outer,data_in_inner,data_out_frm_inner; 129 | 130 | wire cmd_transfer_frm_scalar_mul,interupt_trensfer; 131 | wire w_inner,transfer_running,read_write_command_frm_scalar_mul,interupt_transfer; 132 | wire b_outer; 133 | 134 | Ram_transfer_scalar_mul Ram_transfer_scalar_mul ( 135 | .clk(clk), 136 | .b_w(b_outer), 137 | .b_adbus(adbus_outer_transfer), 138 | .b_data_in(data_in_to_outer), 139 | .b_data_out(data_out_outer), 140 | 141 | .a_w(w_inner), 142 | .a_adbus(adbus_inner), 143 | .a_data_in(data_in_inner), 144 | .a_data_out(data_out_frm_inner), 145 | 146 | 147 | .read_write_command(read_write_command_frm_scalar_mul), 148 | .read_address(read_address), 149 | .write_address(write_address), 150 | .no_of_chunks(no_of_chunks), 151 | .command_transfer(cmd_transfer_frm_scalar_mul), 152 | .interupt_transfer(interupt_transfer), 153 | .transfer_running(transfer_running) 154 | ); 155 | 156 | //connecting port B of Ram_interface_scalar_mul with State machine of Point add and Point Double 157 | state_machine_point_add state_machine_add_double ( 158 | .clk(clk), 159 | .w_RAM_outer_PORT(w_inner), 160 | .adbus_RAM_outer_PORT(adbus_inner), 161 | .data_in_RAM_outer_PORT(data_in_inner), 162 | .data_out_RAM_outer_PORT(data_out_frm_inner), 163 | .no_of_chunks(no_of_chunks), 164 | .command(command_point_add_or_double), 165 | .Data_len_Polynomial(Data_len_Polynomial), 166 | .Data_Polynomial(Data_Polynomial), 167 | .interupt_point_double(interupt_point_double), 168 | .interupt_point_addition(interupt_point_addition) 169 | ); 170 | 171 | wire [5:0] read_address, write_address; 172 | 173 | wire [1:0] command_point_add_or_double; 174 | 175 | // Instantiate the Unit Under Test (UUT) 176 | scalar_multiplication_module scalar_multiplication_module ( 177 | .clk(clk), 178 | 179 | .interupt_point_add(interupt_point_addition), 180 | .interupt_point_double(interupt_point_double), 181 | .interupt_ram_transfer(interupt_transfer), 182 | .command_scalar_multiplication(command_scalar_multiplication), 183 | 184 | .read_write_command(read_write_command_frm_scalar_mul), 185 | .read_address(read_address), 186 | .write_address(write_address), 187 | //.no_of_chunks_frm_tb(no_of_chunks), 188 | .cmd_transfer(cmd_transfer_frm_scalar_mul), 189 | 190 | .interupt_scalar_mul(interupt_scalar_mul), 191 | .command_add_double(command_point_add_or_double), 192 | .scalar_multiplication(private_key) 193 | ); 194 | 195 | endmodule 196 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/state_machine_scalar_mul.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `default_nettype none 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 14:56:23 10/17/2014 8 | // Design Name: 9 | // Module Name: state-machine_scalar_mul 10 | // Project Name: 11 | // Target Devices: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | module state_machine_scalar_mul #( 24 | parameter Data=255, 25 | parameter Addr=5)( 26 | 27 | input wire clk, 28 | input wire a_w, 29 | input wire [Addr:0] a_adbus, //Address Bus 30 | input wire [Data:0] a_data_in, //Data bus for taking input 31 | output wire [Data:0] a_data_out, //Data bus for taking output 32 | input wire command_scalar_multiplication, 33 | input wire start_operation, 34 | output wire interupt_scalar_mul 35 | ); 36 | 37 | reg [5:0] address_bus; 38 | reg [1:0] no_of_chunks; 39 | reg [Data:0] Data_Polynomial; 40 | reg [9:0] Data_len_Polynomial; 41 | reg [2:0] fsm; 42 | reg [3:0] count; 43 | reg start,select_operation; 44 | reg [5:0] start_address; 45 | initial begin 46 | start <= 1'h0; 47 | count <= 2'h0; 48 | start_address<=6'h14; 49 | select_operation <= 1'h0; 50 | 51 | 52 | $dumpfile("test.vcd"); 53 | $dumpvars(); 54 | 55 | end 56 | 57 | 58 | wire [Data:0] data_out_outer; 59 | reg [575:0] private_key; 60 | 61 | always @(posedge clk) begin //calculating Polynomial and length of polynomial 62 | if(start_operation) begin 63 | address_bus<=start_address; 64 | count<=2'h1; 65 | end 66 | if(count[0]) begin 67 | count<=3'h0; 68 | fsm<=3'h1; 69 | address_bus<=start_address+1'h1; 70 | end 71 | 72 | case (fsm) 73 | 74 | 3'h1:begin 75 | Data_Polynomial<=data_out_outer; 76 | address_bus<=start_address+2'h2; 77 | fsm<=3'h2; 78 | end 79 | 80 | 3'h2:begin 81 | fsm<=3'h3; 82 | Data_len_Polynomial<=Data_Polynomial[41:32]; 83 | no_of_chunks=(Data_Polynomial[41:32]/256+1'h1); 84 | private_key[575:512]<=data_out_outer[63:0]; 85 | address_bus<=start_address+2'h3; 86 | end 87 | 88 | 3'h3:begin 89 | fsm<=3'h4; 90 | private_key[511:256]<=data_out_outer; 91 | end 92 | 93 | 3'h4:begin 94 | fsm<=3'h5; 95 | private_key[255:0]<=data_out_outer; 96 | end 97 | endcase 98 | end 99 | 100 | 101 | assign adbus_outer1 = (transfer_running)?adbus_outer_transfer:address_bus; 102 | 103 | wire [Addr:0] adbus_outer1; 104 | 105 | //Ram interface Module for interfacing with Ram in scalar_mulltiplication 106 | Ram_interface_scalar_mul Ram_interface_scalar_mul ( 107 | 108 | //data coming from testbench 109 | .clk(clk), 110 | .a_w(a_w), 111 | .a_adbus(a_adbus), 112 | .a_data_in(a_data_in), 113 | .a_data_out(a_data_out), 114 | 115 | //port for 116 | //ram-interface which inturn interfaces with scalar multiplication module 117 | .b_w(b_outer), 118 | .b_adbus(adbus_outer1), 119 | .b_data_in(data_in_to_outer), 120 | .b_data_out(data_out_outer) 121 | ); 122 | 123 | wire [5:0] adbus_outer_transfer,adbus_inner; 124 | wire [Data:0] data_in_to_outer,data_in_inner,data_out_frm_inner; 125 | 126 | wire cmd_transfer_frm_scalar_mul,interupt_trensfer; 127 | wire w_inner,transfer_running,read_write_command_frm_scalar_mul,interupt_transfer; 128 | wire b_outer; 129 | 130 | Ram_transfer_scalar_mul Ram_transfer_scalar_mul ( 131 | .clk(clk), 132 | .b_w(b_outer), 133 | .b_adbus(adbus_outer_transfer), 134 | .b_data_in(data_in_to_outer), 135 | .b_data_out(data_out_outer), 136 | 137 | .a_w(w_inner), 138 | .a_adbus(adbus_inner), 139 | .a_data_in(data_in_inner), 140 | .a_data_out(data_out_frm_inner), 141 | 142 | 143 | .read_write_command(read_write_command_frm_scalar_mul), 144 | .read_address(read_address), 145 | .write_address(write_address), 146 | .no_of_chunks(no_of_chunks), 147 | .command_transfer(cmd_transfer_frm_scalar_mul), 148 | .interupt_transfer(interupt_transfer), 149 | .transfer_running(transfer_running) 150 | ); 151 | 152 | //connecting port B of Ram_interface_scalar_mul with State machine of Point add and Point Double 153 | state_machine_point_add state_machine_add_double ( 154 | .clk(clk), 155 | .w_RAM_outer_PORT(w_inner), 156 | .adbus_RAM_outer_PORT(adbus_inner), 157 | .data_in_RAM_outer_PORT(data_in_inner), 158 | .data_out_RAM_outer_PORT(data_out_frm_inner), 159 | .no_of_chunks(no_of_chunks), 160 | .command(command_point_add_or_double), 161 | .Data_len_Polynomial(Data_len_Polynomial), 162 | .Data_Polynomial(Data_Polynomial), 163 | .interupt_point_double(interupt_point_double), 164 | .interupt_point_addition(interupt_point_addition) 165 | ); 166 | 167 | wire [5:0] read_address, write_address; 168 | wire interupt_point_double,interupt_point_addition; 169 | wire [1:0] command_point_add_or_double; 170 | 171 | // Instantiate the Unit Under Test (UUT) 172 | scalar_multiplication_module scalar_multiplication_module ( 173 | .clk(clk), 174 | 175 | .interupt_point_add(interupt_point_addition), 176 | .interupt_point_double(interupt_point_double), 177 | .interupt_ram_transfer(interupt_transfer), 178 | .command_scalar_multiplication(command_scalar_multiplication), 179 | 180 | .read_write_command(read_write_command_frm_scalar_mul), 181 | .read_address(read_address), 182 | .write_address(write_address), 183 | .no_of_chunks_frm_tb(no_of_chunks), 184 | .cmd_transfer(cmd_transfer_frm_scalar_mul), 185 | 186 | .interupt_scalar_mul(interupt_scalar_mul), 187 | .command_point_add_or_double(command_point_add_or_double), 188 | .scalar_multiplication(private_key) 189 | ); 190 | 191 | endmodule 192 | -------------------------------------------------------------------------------- /Verilog Code/hdl/multipliers/sync_96.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sync_ks_96( 4 | input clk, 5 | input [95:0] a, // O6 351 6 | input [95:0] b, // O5 &O6 366 7 | output reg [190:0] d 8 | ); 9 | 10 | reg [95:0] A1,B1; 11 | wire [190:0] C1; 12 | 13 | always @(posedge clk)begin 14 | A1 <= a; 15 | B1 <= b; 16 | d <= C1; 17 | 18 | end 19 | 20 | mul_96_module_Xor mul_96( //717 slices on implementation 21 | .A(A1), // O6 35 22 | .B(B1), // O5 &O6 366 23 | .mul_96(C1) 24 | ); 25 | 26 | 27 | initial begin 28 | $dumpfile("test.vcd"); 29 | $dumpvars(); 30 | end 31 | 32 | endmodule 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /Verilog Code/readme.md: -------------------------------------------------------------------------------- 1 | This Repo contains the code of my final year Undergrad project: 2 | 3 | Its a Verilog Code that implemets 4 | 5 | 1. HDL folder: Generic ECC (Elliptic Curve Crptography) designed and optimized for Virtex-6 FPGA 6 | 7 | 2. DOC folder: Cococtb Test bench for verification of verilog code 8 | -------------------------------------------------------------------------------- /Verilog Code/testbench/ks/Makefile: -------------------------------------------------------------------------------- 1 | TOPLEVEL = state_machine_scalar_mul 2 | 3 | PWD = $(shell pwd) 4 | COCOTB = ~/devel/cocotb 5 | SRC = $(PWD)/../../hdl/multipliers 6 | 7 | VERILOG_SOURCES = $(SRC)/state_machine_scalar_mul.v $(SRC)/Ram_interface_scalar_mul.v $(SRC)/Ram_transfer_scalar_mul.v $(SRC)/state_machine_3.v $(SRC)/scalar_multiplication_module.v $(SRC)/Ram_module_scalar_mul.v $(SRC)/state_machine_inverse.v $(SRC)/Ram_transfer.v $(SRC)/Outer_Ram_interface.v $(SRC)/point_addition_module.v $(SRC)/point_double_module.v $(SRC)/Outer_Ram_Module.v $(SRC)/inverse_itoha_tsuji_module.v $(SRC)/ideal_module.v $(SRC)/dma_sample_code.v $(SRC)/Xor_new.v $(SRC)/redution_256.v $(SRC)/Square_571.v $(SRC)/multiplication_recursive_module.v $(SRC)/Ram_data_swaping_module.v $(SRC)/Ram_Interface_Module.v $(SRC)/lower_bit_implementation.v $(SRC)/Masking_Module.v $(SRC)/LOOK_UP_table_module.v $(SRC)/Xor_192.v $(SRC)/LUT.v $(SRC)/Xor_16_bit.v $(SRC)/Ram_module.v $(SRC)/Xor_module.v $(SRC)/Xor_256_module.v $(SRC)/mul_64_module.v $(SRC)/sqr_slice_testing.v 8 | MODULE=test_ks #cocotb,test_discovery,test_external,test_regression 9 | 10 | SIM_ARGS=-vcd 11 | 12 | include $(COCOTB)/makefiles/Makefile.inc 13 | include $(COCOTB)/makefiles/Makefile.sim -------------------------------------------------------------------------------- /Verilog Code/testbench/ks/result.log: -------------------------------------------------------------------------------- 1 | make results.xml 2 | make[1]: Entering directory `/home/lab1/devel/scalar_mul/testbench/ks' 3 | PYTHONPATH=/home/lab1/devel/cocotb/build/libs/x86_64:/home/lab1/devel/cocotb:/home/lab1/devel/scalar_mul/testbench/ks: LD_LIBRARY_PATH=/home/lab1/devel/cocotb/build/libs/x86_64: MODULE=test_ks \ 4 | TESTCASE= TOPLEVEL=state_machine_scalar_mul \ 5 | vvp -M /home/lab1/devel/cocotb/build/libs/x86_64 -m gpivpi sim_build/sim.vvp -vcd 6 | 0.00ns INFO cocotb.gpi gpi_embed.c:205 in embed_sim_init Running on Icarus Verilog version 0.10.0 (devel) 7 | 0.00ns INFO cocotb.gpi gpi_embed.c:206 in embed_sim_init Python interpreter initialised and cocotb loaded! 8 | 0.00ns INFO cocotb.gpi __init__.py:101 in _initialise_testbench Seeding Python random module with 1415708960 9 | 0.00ns INFO cocotb.gpi __init__.py:115 in _initialise_testbench Running tests with Cocotb v0.5 from /home/lab1/devel/cocotb 10 | 0.00ns INFO cocotb.regression regression.py:123 in initialise Found test test_ks.test_ks 11 | 0.00ns INFO cocotb.regression regression.py:194 in execute Running test 1/1: test_ks 12 | 0.00ns INFO cocotb.coroutine.test_ks.0x2f5ca10 decorators.py:176 in send Starting test: "test_ks" 13 | Description: None 14 | Time in 2014-11-11 17:56:31.973324 15 | VCD info: dumpfile test.vcd opened for output. 16 | [0xb4b4658L 0xfb908cL 0x8d3e90c3L 0x410a5446L 0x2df3b3e6L 0xda847cfbL 17 | 0x4cf3a14bL 0x1f6L 0xedf30d8eL 0x54e43247L 0x33ae491L 0xf2a2a886L 18 | 0x5c012f6cL 0xa45194b3L 0xed75c369L 0x1fcL] 19 | Time Out 2014-11-11 18:09:28.531176 20 | [array([0x583cccf6L, 0x102a8ca0L, 0xdcbf8bf6L, 0x29d039beL, 0x3037df72L, 21 | 0xb7ac2a40L, 0xe09655e5L, 0x183L], dtype=uint32), array([0x680be037L, 0x8238f7a1L, 0x30ffbc3eL, 0x2b2df145L, 0x42e2753eL, 22 | 0xa9bb6685L, 0x6eb9b50L, 0xbeL], dtype=uint32)] 23 | 5771.09ns INFO cocotb.regression regression.py:156 in handle_result Test Passed: test_ks 24 | 5771.09ns INFO cocotb.regression regression.py:132 in tear_down Passed 1 tests (0 skipped) 25 | 5771.09ns INFO cocotb.regression regression.py:133 in tear_down Shutting down... 26 | make[1]: Leaving directory `/home/lab1/devel/scalar_mul/testbench/ks' 27 | s' 28 | Time in 2014-11-11 17:53:18.672038 29 | VCD info: dumpfile test.vcd opened for output. 30 | [0xb4b4658L 0xfb908cL 0x8d3e90c3L 0x410a5446L 0x2df3b3e6L 0xda847cfbL 31 | 0x4cf3a14bL 0x1f6L 0xedf30d8eL 0x54e43247L 0x33ae491L 0xf2a2a886L 32 | 0x5c012f6cL 0xa45194b3L 0xed75c369L 0x1fcL] 33 | Time Out 2014-11-11 18:06:22.587298 34 | [array([0x583cccf6L, 0x102a8ca0L, 0xdcbf8bf6L, 0x29d039beL, 0x3037df72L, 35 | 0xb7ac2a40L, 0xe09655e5L, 0x183L], dtype=uint32), array([0x680be037L, 0x8238f7a1L, 0x30ffbc3eL, 0x2b2df145L, 0x42e2753eL, 36 | 0xa9bb6685L, 0x6eb9b50L, 0xbeL], dtype=uint32)] 37 | 5771.09ns INFO cocotb.regression regression.py:156 in handle_result Test Passed: test_ks 38 | 5771.09ns INFO cocotb.regression regression.py:132 in tear_down Passed 1 tests (0 skipped) 39 | 5771.09ns INFO cocotb.regression regression.py:133 in tear_down Shutting down... 40 | make[1]: Leaving directory `/home/lab1/devel/scalar_mul/testbench/ks' 41 | -------------------------------------------------------------------------------- /Verilog Code/testbench/ks/results.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /Verilog Code/testbench/ks/test_ks.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/raya4213/VerilogCodeECC/f69b729a2cc49e1373a3d12be9bf8acdf02a6498/Verilog Code/testbench/ks/test_ks.pyc --------------------------------------------------------------------------------