├── LICENSE ├── README.md ├── images ├── enc-32-rounds.png ├── final-results.png ├── key-exp-32-round.png ├── key-exp-pure-sw.png ├── overall-32-round.png ├── scr1-sim-log.png ├── set round key for decryption.png ├── sm4-enc-alg.png ├── sm4-enc-rf.png ├── sm4-key-alg.png ├── sm4-key-rf.png ├── start-of-sm4_one_round.png ├── the-first-round.png └── time.png ├── modify-the-gnu-toolchains ├── riscv-opc.c └── riscv-opc.h └── scr1 ├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── docs ├── img │ └── scr1_cluster.svg ├── scr1_eas.pdf └── scr1_um.pdf ├── riscv-compliance ├── .gitignore ├── COPYING.BSD ├── COPYING.CC ├── ChangeLog ├── Makefile ├── README.md ├── doc │ ├── .gitignore │ ├── ChangeLog │ ├── Makefile │ ├── README.adoc │ └── custom.wordlist ├── riscv-ovpsim │ ├── ChangeLog.md │ ├── LICENSE.pdf │ ├── README.md │ ├── bin │ │ ├── Linux64 │ │ │ ├── libdwarf-20120410.so │ │ │ ├── libelf.so.0.8.13 │ │ │ ├── libtcl8.4.so │ │ │ ├── riscv64-unknown-elf-gdb │ │ │ └── riscvOVPsim.exe │ │ ├── README.md │ │ └── Windows64 │ │ │ ├── libdwarf-20120410.dll │ │ │ ├── libelf-0.8.13.dll │ │ │ ├── lmgr11_imperas.dll │ │ │ ├── pthreadGC2-w64.dll │ │ │ ├── riscv64-unknown-elf-gdb.exe │ │ │ ├── riscvOVPsim.exe │ │ │ └── tcl85.dll │ ├── doc │ │ ├── README.md │ │ └── riscvOVPsim_User_Guide.pdf │ ├── examples │ │ ├── CoreMark │ │ │ ├── 32_core_portme.c │ │ │ ├── 32_core_portme.h │ │ │ ├── LICENSE.md │ │ │ ├── README.md │ │ │ ├── RUN_RV32_CoreMark.bat │ │ │ ├── RUN_RV32_CoreMark.sh │ │ │ └── coremark.RISCV32.elf │ │ ├── README.md │ │ ├── dhrystone │ │ │ ├── DEBUG_GDB_RV32_dhrystone.bat │ │ │ ├── DEBUG_GDB_RV32_dhrystone.sh │ │ │ ├── README.md │ │ │ ├── RUN_RV32_dhrystone.bat │ │ │ ├── RUN_RV32_dhrystone.sh │ │ │ ├── RUN_RV64_dhrystone.bat │ │ │ ├── RUN_RV64_dhrystone.sh │ │ │ ├── dhrystone.RISCV32.elf │ │ │ ├── dhrystone.RISCV64.elf │ │ │ └── dhrystone.c │ │ ├── fibonacci │ │ │ ├── README.md │ │ │ ├── RUN_RV32_fibonacci.bat │ │ │ ├── RUN_RV32_fibonacci.sh │ │ │ ├── RUN_RV64_fibonacci.bat │ │ │ ├── RUN_RV64_fibonacci.sh │ │ │ ├── RUN_RV64_fibonacci_signature_dump.bat │ │ │ ├── RUN_RV64_fibonacci_signature_dump.sh │ │ │ ├── fibonacci.RISCV32.elf │ │ │ ├── fibonacci.RISCV64.elf │ │ │ └── fibonacci.c │ │ └── linpack │ │ │ ├── README.md │ │ │ ├── RUN_RV32_linpack.bat │ │ │ ├── RUN_RV32_linpack.sh │ │ │ ├── linpack.RISCV32.elf │ │ │ └── linpack.c │ ├── riscvOVPsim.jpg │ └── source │ │ ├── README.md │ │ ├── riscvAttrs.c │ │ ├── riscvBlockState.h │ │ ├── riscvBus.c │ │ ├── riscvBus.h │ │ ├── riscvCSR.c │ │ ├── riscvCSR.h │ │ ├── riscvCSRTypes.h │ │ ├── riscvCluster.c │ │ ├── riscvCluster.h │ │ ├── riscvConfig.h │ │ ├── riscvConfigList.c │ │ ├── riscvDebug.c │ │ ├── riscvDebug.h │ │ ├── riscvDecode.c │ │ ├── riscvDecode.h │ │ ├── riscvDecodeTypes.h │ │ ├── riscvDerivedMorph.h │ │ ├── riscvDisassemble.c │ │ ├── riscvDisassembleFormats.h │ │ ├── riscvDoc.c │ │ ├── riscvDoc.h │ │ ├── riscvExceptionDefinitions.h │ │ ├── riscvExceptionTypes.h │ │ ├── riscvExceptions.c │ │ ├── riscvExceptions.h │ │ ├── riscvFunctions.h │ │ ├── riscvInfo.c │ │ ├── riscvInstructionInfo.h │ │ ├── riscvMain.c │ │ ├── riscvMessage.h │ │ ├── riscvMode.h │ │ ├── riscvModelCallbacks.h │ │ ├── riscvMorph.c │ │ ├── riscvMorph.h │ │ ├── riscvParameters.c │ │ ├── riscvParameters.h │ │ ├── riscvRegisterTypes.h │ │ ├── riscvRegisters.h │ │ ├── riscvSemiHost.c │ │ ├── riscvSoftFloat.c │ │ ├── riscvSoftFloat.h │ │ ├── riscvStructure.h │ │ ├── riscvTypeRefs.h │ │ ├── riscvTypes.h │ │ ├── riscvUtils.c │ │ ├── riscvUtils.h │ │ ├── riscvVM.c │ │ ├── riscvVM.h │ │ ├── riscvVMConstants.h │ │ └── riscvVariant.h ├── riscv-target │ ├── Codasip-simulator │ │ ├── compliance_io.h │ │ ├── compliance_test.h │ │ └── device │ │ │ └── rv32i │ │ │ └── Makefile.include │ ├── README.md │ ├── riscvOVPsim │ │ ├── README.md │ │ ├── compliance_io.h │ │ ├── compliance_test.h │ │ └── device │ │ │ ├── rv32i │ │ │ └── Makefile.include │ │ │ ├── rv32im │ │ │ └── Makefile.include │ │ │ ├── rv32imc │ │ │ └── Makefile.include │ │ │ ├── rv32mi │ │ │ └── Makefile.include │ │ │ ├── rv32si │ │ │ └── Makefile.include │ │ │ ├── rv32ua │ │ │ └── Makefile.include │ │ │ ├── rv32uc │ │ │ └── Makefile.include │ │ │ ├── rv32ud │ │ │ └── Makefile.include │ │ │ ├── rv32uf │ │ │ └── Makefile.include │ │ │ ├── rv32ui │ │ │ └── Makefile.include │ │ │ ├── rv64i │ │ │ └── Makefile.include │ │ │ └── rv64im │ │ │ └── Makefile.include │ ├── rocket │ │ ├── compliance_io.h │ │ ├── compliance_test.h │ │ └── device │ │ │ ├── rv32i │ │ │ └── Makefile.include │ │ │ ├── rv32im │ │ │ └── Makefile.include │ │ │ ├── rv32imc │ │ │ └── Makefile.include │ │ │ ├── rv32mi │ │ │ └── Makefile.include │ │ │ ├── rv32si │ │ │ └── Makefile.include │ │ │ ├── rv32ua │ │ │ └── Makefile.include │ │ │ ├── rv32uc │ │ │ └── Makefile.include │ │ │ ├── rv32ud │ │ │ └── Makefile.include │ │ │ ├── rv32uf │ │ │ └── Makefile.include │ │ │ ├── rv32ui │ │ │ └── Makefile.include │ │ │ ├── rv64i │ │ │ └── Makefile.include │ │ │ └── rv64im │ │ │ └── Makefile.include │ ├── sifive-formal │ │ ├── compliance_io.h │ │ ├── compliance_test.h │ │ ├── device │ │ │ ├── rv32i │ │ │ │ └── Makefile.include │ │ │ ├── rv32ua │ │ │ │ └── Makefile.include │ │ │ ├── rv32uc │ │ │ │ └── Makefile.include │ │ │ ├── rv32uf │ │ │ │ └── Makefile.include │ │ │ └── rv32ui │ │ │ │ └── Makefile.include │ │ └── formalspec-env │ │ │ ├── LICENSE │ │ │ ├── aw_test_macros.h │ │ │ ├── encoding.h │ │ │ ├── p │ │ │ ├── link.ld │ │ │ └── riscv_test.h │ │ │ └── test_macros.h │ └── spike │ │ ├── compliance_io.h │ │ ├── compliance_test.h │ │ └── device │ │ ├── rv32i │ │ └── Makefile.include │ │ ├── rv32im │ │ └── Makefile.include │ │ ├── rv32imc │ │ └── Makefile.include │ │ ├── rv32mi │ │ └── Makefile.include │ │ ├── rv32si │ │ └── Makefile.include │ │ ├── rv32ua │ │ └── Makefile.include │ │ ├── rv32uc │ │ └── Makefile.include │ │ ├── rv32ud │ │ └── Makefile.include │ │ ├── rv32uf │ │ └── Makefile.include │ │ ├── rv32ui │ │ └── Makefile.include │ │ ├── rv64i │ │ └── Makefile.include │ │ └── rv64im │ │ └── Makefile.include ├── riscv-test-env │ ├── LICENSE │ ├── aw_test_macros.h │ ├── encoding.h │ ├── p │ │ ├── link.ld │ │ └── riscv_test.h │ ├── pm │ │ ├── link.ld │ │ └── riscv_test.h │ ├── pt │ │ ├── link.ld │ │ └── riscv_test.h │ ├── test_macros.h │ ├── v │ │ ├── entry.S │ │ ├── link.ld │ │ ├── riscv_test.h │ │ ├── string.c │ │ └── vm.c │ └── verify.sh ├── riscv-test-suite │ ├── README.md │ ├── rv32i │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── I-ADD-01.reference_output │ │ │ ├── I-ADDI-01.reference_output │ │ │ ├── I-AND-01.reference_output │ │ │ ├── I-ANDI-01.reference_output │ │ │ ├── I-AUIPC-01.reference_output │ │ │ ├── I-BEQ-01.reference_output │ │ │ ├── I-BGE-01.reference_output │ │ │ ├── I-BGEU-01.reference_output │ │ │ ├── I-BLT-01.reference_output │ │ │ ├── I-BLTU-01.reference_output │ │ │ ├── I-BNE-01.reference_output │ │ │ ├── I-CSRRC-01.reference_output │ │ │ ├── I-CSRRCI-01.reference_output │ │ │ ├── I-CSRRS-01.reference_output │ │ │ ├── I-CSRRSI-01.reference_output │ │ │ ├── I-CSRRW-01.reference_output │ │ │ ├── I-CSRRWI-01.reference_output │ │ │ ├── I-DELAY_SLOTS-01.reference_output │ │ │ ├── I-EBREAK-01.reference_output │ │ │ ├── I-ECALL-01.reference_output │ │ │ ├── I-ENDIANESS-01.reference_output │ │ │ ├── I-FENCE.I-01.reference_output │ │ │ ├── I-IO.reference_output │ │ │ ├── I-JAL-01.reference_output │ │ │ ├── I-JALR-01.reference_output │ │ │ ├── I-LB-01.reference_output │ │ │ ├── I-LBU-01.reference_output │ │ │ ├── I-LH-01.reference_output │ │ │ ├── I-LHU-01.reference_output │ │ │ ├── I-LUI-01.reference_output │ │ │ ├── I-LW-01.reference_output │ │ │ ├── I-MISALIGN_JMP-01.reference_output │ │ │ ├── I-MISALIGN_LDST-01.reference_output │ │ │ ├── I-NOP-01.reference_output │ │ │ ├── I-OR-01.reference_output │ │ │ ├── I-ORI-01.reference_output │ │ │ ├── I-RF_size-01.reference_output │ │ │ ├── I-RF_width-01.reference_output │ │ │ ├── I-RF_x0-01.reference_output │ │ │ ├── I-SB-01.reference_output │ │ │ ├── I-SH-01.reference_output │ │ │ ├── I-SLL-01.reference_output │ │ │ ├── I-SLLI-01.reference_output │ │ │ ├── I-SLT-01.reference_output │ │ │ ├── I-SLTI-01.reference_output │ │ │ ├── I-SLTIU-01.reference_output │ │ │ ├── I-SLTU-01.reference_output │ │ │ ├── I-SRA-01.reference_output │ │ │ ├── I-SRAI-01.reference_output │ │ │ ├── I-SRL-01.reference_output │ │ │ ├── I-SRLI-01.reference_output │ │ │ ├── I-SUB-01.reference_output │ │ │ ├── I-SW-01.reference_output │ │ │ ├── I-XOR-01.reference_output │ │ │ └── I-XORI-01.reference_output │ │ └── src │ │ │ ├── I-ADD-01.S │ │ │ ├── I-ADDI-01.S │ │ │ ├── I-AND-01.S │ │ │ ├── I-ANDI-01.S │ │ │ ├── I-AUIPC-01.S │ │ │ ├── I-BEQ-01.S │ │ │ ├── I-BGE-01.S │ │ │ ├── I-BGEU-01.S │ │ │ ├── I-BLT-01.S │ │ │ ├── I-BLTU-01.S │ │ │ ├── I-BNE-01.S │ │ │ ├── I-CSRRC-01.S │ │ │ ├── I-CSRRCI-01.S │ │ │ ├── I-CSRRS-01.S │ │ │ ├── I-CSRRSI-01.S │ │ │ ├── I-CSRRW-01.S │ │ │ ├── I-CSRRWI-01.S │ │ │ ├── I-DELAY_SLOTS-01.S │ │ │ ├── I-EBREAK-01.S │ │ │ ├── I-ECALL-01.S │ │ │ ├── I-ENDIANESS-01.S │ │ │ ├── I-FENCE.I-01.S │ │ │ ├── I-IO.S │ │ │ ├── I-JAL-01.S │ │ │ ├── I-JALR-01.S │ │ │ ├── I-LB-01.S │ │ │ ├── I-LBU-01.S │ │ │ ├── I-LH-01.S │ │ │ ├── I-LHU-01.S │ │ │ ├── I-LUI-01.S │ │ │ ├── I-LW-01.S │ │ │ ├── I-MISALIGN_JMP-01.S │ │ │ ├── I-MISALIGN_LDST-01.S │ │ │ ├── I-NOP-01.S │ │ │ ├── I-OR-01.S │ │ │ ├── I-ORI-01.S │ │ │ ├── I-RF_size-01.S │ │ │ ├── I-RF_width-01.S │ │ │ ├── I-RF_x0-01.S │ │ │ ├── I-SB-01.S │ │ │ ├── I-SH-01.S │ │ │ ├── I-SLL-01.S │ │ │ ├── I-SLLI-01.S │ │ │ ├── I-SLT-01.S │ │ │ ├── I-SLTI-01.S │ │ │ ├── I-SLTIU-01.S │ │ │ ├── I-SLTU-01.S │ │ │ ├── I-SRA-01.S │ │ │ ├── I-SRAI-01.S │ │ │ ├── I-SRL-01.S │ │ │ ├── I-SRLI-01.S │ │ │ ├── I-SUB-01.S │ │ │ ├── I-SW-01.S │ │ │ ├── I-XOR-01.S │ │ │ └── I-XORI-01.S │ ├── rv32im │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── DIV.reference_output │ │ │ ├── DIVU.reference_output │ │ │ ├── MUL.reference_output │ │ │ ├── MULH.reference_output │ │ │ ├── MULHSU.reference_output │ │ │ ├── MULHU.reference_output │ │ │ ├── REM.reference_output │ │ │ └── REMU.reference_output │ │ └── src │ │ │ ├── DIV.S │ │ │ ├── DIVU.S │ │ │ ├── MUL.S │ │ │ ├── MULH.S │ │ │ ├── MULHSU.S │ │ │ ├── MULHU.S │ │ │ ├── REM.S │ │ │ └── REMU.S │ ├── rv32imc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── C-ADD.reference_output │ │ │ ├── C-ADDI.reference_output │ │ │ ├── C-ADDI16SP.reference_output │ │ │ ├── C-ADDI4SPN.reference_output │ │ │ ├── C-AND.reference_output │ │ │ ├── C-ANDI.reference_output │ │ │ ├── C-BEQZ.reference_output │ │ │ ├── C-BNEZ.reference_output │ │ │ ├── C-J.reference_output │ │ │ ├── C-JAL.reference_output │ │ │ ├── C-JALR.reference_output │ │ │ ├── C-JR.reference_output │ │ │ ├── C-LI.reference_output │ │ │ ├── C-LUI.reference_output │ │ │ ├── C-LW.reference_output │ │ │ ├── C-LWSP.reference_output │ │ │ ├── C-MV.reference_output │ │ │ ├── C-OR.reference_output │ │ │ ├── C-SLLI.reference_output │ │ │ ├── C-SRAI.reference_output │ │ │ ├── C-SRLI.reference_output │ │ │ ├── C-SUB.reference_output │ │ │ ├── C-SW.reference_output │ │ │ ├── C-SWSP.reference_output │ │ │ └── C-XOR.reference_output │ │ └── src │ │ │ ├── C-ADD.S │ │ │ ├── C-ADDI.S │ │ │ ├── C-ADDI16SP.S │ │ │ ├── C-ADDI4SPN.S │ │ │ ├── C-AND.S │ │ │ ├── C-ANDI.S │ │ │ ├── C-BEQZ.S │ │ │ ├── C-BNEZ.S │ │ │ ├── C-J.S │ │ │ ├── C-JAL.S │ │ │ ├── C-JALR.S │ │ │ ├── C-JR.S │ │ │ ├── C-LI.S │ │ │ ├── C-LUI.S │ │ │ ├── C-LW.S │ │ │ ├── C-LWSP.S │ │ │ ├── C-MV.S │ │ │ ├── C-OR.S │ │ │ ├── C-SLLI.S │ │ │ ├── C-SRAI.S │ │ │ ├── C-SRLI.S │ │ │ ├── C-SUB.S │ │ │ ├── C-SW.S │ │ │ ├── C-SWSP.S │ │ │ └── C-XOR.S │ ├── rv32mi │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── breakpoint.reference_output │ │ │ ├── csr.reference_output │ │ │ ├── illegal.reference_output │ │ │ ├── ma_addr.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── mcsr.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── shamt.reference_output │ │ ├── rv64mi │ │ │ ├── Makefrag │ │ │ ├── access.S │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ └── scall.S │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── breakpoint.S │ │ │ ├── csr.S │ │ │ ├── illegal.S │ │ │ ├── ma_addr.S │ │ │ ├── ma_fetch.S │ │ │ ├── mcsr.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── shamt.S │ ├── rv32si │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── csr.reference_output │ │ │ ├── dirty.reference_output │ │ │ ├── ma_fetch.reference_output │ │ │ ├── sbreak.reference_output │ │ │ ├── scall.reference_output │ │ │ └── wfi.reference_output │ │ ├── rv64si │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── csr.S │ │ │ ├── dirty.S │ │ │ ├── ma_fetch.S │ │ │ ├── sbreak.S │ │ │ ├── scall.S │ │ │ └── wfi.S │ ├── rv32ua │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── amoadd_w.reference_output │ │ │ ├── amoand_w.reference_output │ │ │ ├── amomax_w.reference_output │ │ │ ├── amomaxu_w.reference_output │ │ │ ├── amomin_w.reference_output │ │ │ ├── amominu_w.reference_output │ │ │ ├── amoor_w.reference_output │ │ │ ├── amoswap_w.reference_output │ │ │ ├── amoxor_w.reference_output │ │ │ └── lrsc.reference_output │ │ ├── rv64ua │ │ │ ├── Makefrag │ │ │ ├── amoadd_d.S │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_d.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_d.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_d.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_d.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_d.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_d.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_d.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_d.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── amoadd_w.S │ │ │ ├── amoand_w.S │ │ │ ├── amomax_w.S │ │ │ ├── amomaxu_w.S │ │ │ ├── amomin_w.S │ │ │ ├── amominu_w.S │ │ │ ├── amoor_w.S │ │ │ ├── amoswap_w.S │ │ │ ├── amoxor_w.S │ │ │ └── lrsc.S │ ├── rv32uc │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ └── rvc.reference_output │ │ ├── rv64uc │ │ │ ├── Makefrag │ │ │ └── rvc.S │ │ └── src │ │ │ ├── Makefrag │ │ │ └── rvc.S │ ├── rv32ud │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64ud │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ ├── recoding.S │ │ │ └── structural.S │ │ └── src │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ ├── rv32uf │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── fadd.reference_output │ │ │ ├── fclass.reference_output │ │ │ ├── fcmp.reference_output │ │ │ ├── fcvt.reference_output │ │ │ ├── fcvt_w.reference_output │ │ │ ├── fdiv.reference_output │ │ │ ├── fmadd.reference_output │ │ │ ├── fmin.reference_output │ │ │ ├── ldst.reference_output │ │ │ ├── move.reference_output │ │ │ └── recoding.reference_output │ │ ├── rv64uf │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ │ └── src │ │ │ ├── Makefrag │ │ │ ├── fadd.S │ │ │ ├── fclass.S │ │ │ ├── fcmp.S │ │ │ ├── fcvt.S │ │ │ ├── fcvt_w.S │ │ │ ├── fdiv.S │ │ │ ├── fmadd.S │ │ │ ├── fmin.S │ │ │ ├── ldst.S │ │ │ ├── move.S │ │ │ └── recoding.S │ ├── rv32ui │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── add.reference_output │ │ │ ├── addi.reference_output │ │ │ ├── and.reference_output │ │ │ ├── andi.reference_output │ │ │ ├── auipc.reference_output │ │ │ ├── beq.reference_output │ │ │ ├── bge.reference_output │ │ │ ├── bgeu.reference_output │ │ │ ├── blt.reference_output │ │ │ ├── bltu.reference_output │ │ │ ├── bne.reference_output │ │ │ ├── fence_i.reference_output │ │ │ ├── jal.reference_output │ │ │ ├── jalr.reference_output │ │ │ ├── lb.reference_output │ │ │ ├── lbu.reference_output │ │ │ ├── lh.reference_output │ │ │ ├── lhu.reference_output │ │ │ ├── lui.reference_output │ │ │ ├── lw.reference_output │ │ │ ├── or.reference_output │ │ │ ├── ori.reference_output │ │ │ ├── sb.reference_output │ │ │ ├── sh.reference_output │ │ │ ├── simple.reference_output │ │ │ ├── sll.reference_output │ │ │ ├── slli.reference_output │ │ │ ├── slt.reference_output │ │ │ ├── slti.reference_output │ │ │ ├── sltiu.reference_output │ │ │ ├── sltu.reference_output │ │ │ ├── sra.reference_output │ │ │ ├── srai.reference_output │ │ │ ├── srl.reference_output │ │ │ ├── srli.reference_output │ │ │ ├── sub.reference_output │ │ │ ├── sw.reference_output │ │ │ ├── xor.reference_output │ │ │ └── xori.reference_output │ │ ├── rv64ui │ │ │ ├── Makefrag │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── addiw.S │ │ │ ├── addw.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── ld.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── lwu.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sd.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slliw.S │ │ │ ├── sllw.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── sraiw.S │ │ │ ├── sraw.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── srliw.S │ │ │ ├── srlw.S │ │ │ ├── sub.S │ │ │ ├── subw.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ │ └── src │ │ │ ├── Makefrag.spike │ │ │ ├── add.S │ │ │ ├── addi.S │ │ │ ├── and.S │ │ │ ├── andi.S │ │ │ ├── auipc.S │ │ │ ├── beq.S │ │ │ ├── bge.S │ │ │ ├── bgeu.S │ │ │ ├── blt.S │ │ │ ├── bltu.S │ │ │ ├── bne.S │ │ │ ├── fence_i.S │ │ │ ├── jal.S │ │ │ ├── jalr.S │ │ │ ├── lb.S │ │ │ ├── lbu.S │ │ │ ├── lh.S │ │ │ ├── lhu.S │ │ │ ├── lui.S │ │ │ ├── lw.S │ │ │ ├── or.S │ │ │ ├── ori.S │ │ │ ├── sb.S │ │ │ ├── sh.S │ │ │ ├── simple.S │ │ │ ├── sll.S │ │ │ ├── slli.S │ │ │ ├── slt.S │ │ │ ├── slti.S │ │ │ ├── sltiu.S │ │ │ ├── sltu.S │ │ │ ├── sra.S │ │ │ ├── srai.S │ │ │ ├── srl.S │ │ │ ├── srli.S │ │ │ ├── sub.S │ │ │ ├── sw.S │ │ │ ├── xor.S │ │ │ └── xori.S │ ├── rv64i │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ │ ├── ADDIW.reference_output │ │ │ ├── ADDW.reference_output │ │ │ ├── SLLIW.reference_output │ │ │ ├── SLLW.reference_output │ │ │ ├── SRAIW.reference_output │ │ │ ├── SRAW.reference_output │ │ │ ├── SRLIW.reference_output │ │ │ ├── SRLW.reference_output │ │ │ └── SUBW.reference_output │ │ └── src │ │ │ ├── ADDIW.S │ │ │ ├── ADDW.S │ │ │ ├── SLLIW.S │ │ │ ├── SLLW.S │ │ │ ├── SRAIW.S │ │ │ ├── SRAW.S │ │ │ ├── SRLIW.S │ │ │ ├── SRLW.S │ │ │ └── SUBW.S │ └── rv64im │ │ ├── Makefile │ │ ├── Makefrag │ │ ├── references │ │ ├── DIVW.reference_output │ │ ├── MULW.reference_output │ │ ├── REMUW.reference_output │ │ └── REMW.reference_output │ │ └── src │ │ ├── DIVW.S │ │ ├── MULW.S │ │ ├── REMUW.S │ │ └── REMW.S └── spec │ └── TestFormatSpec.adoc ├── riscv-tests ├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile.in ├── README.md ├── benchmarks │ ├── Makefile │ ├── common │ │ ├── crt.S │ │ ├── syscalls.c │ │ ├── test.ld │ │ └── util.h │ ├── dhrystone │ │ ├── dhrystone.c │ │ ├── dhrystone.h │ │ └── dhrystone_main.c │ ├── median │ │ ├── dataset1.h │ │ ├── median.c │ │ ├── median.h │ │ ├── median_gendata.pl │ │ └── median_main.c │ ├── mm │ │ ├── common.h │ │ ├── gen.scala │ │ ├── mm.c │ │ ├── mm_main.c │ │ └── rb.h │ ├── mt-matmul │ │ ├── dataset.h │ │ ├── matmul.c │ │ ├── matmul_gendata.pl │ │ └── mt-matmul.c │ ├── mt-vvadd │ │ ├── dataset.h │ │ ├── mt-vvadd.c │ │ ├── vvadd.c │ │ └── vvadd_gendata.pl │ ├── multiply │ │ ├── dataset1.h │ │ ├── multiply.c │ │ ├── multiply.h │ │ ├── multiply_gendata.pl │ │ └── multiply_main.c │ ├── pmp │ │ └── pmp.c │ ├── qsort │ │ ├── dataset1.h │ │ ├── qsort_gendata.pl │ │ └── qsort_main.c │ ├── readme.txt │ ├── rsort │ │ ├── dataset1.h │ │ └── rsort.c │ ├── spmv │ │ ├── dataset1.h │ │ ├── spmv_gendata.scala │ │ └── spmv_main.c │ ├── towers │ │ └── towers_main.c │ └── vvadd │ │ ├── dataset1-large.h │ │ ├── dataset1.h │ │ ├── vvadd_gendata.pl │ │ └── vvadd_main.c ├── configure ├── configure.ac ├── debug │ ├── Makefile │ ├── README.md │ ├── gdbserver.py │ ├── openocd.py │ ├── programs │ │ ├── checksum.c │ │ ├── debug.c │ │ ├── encoding.h │ │ ├── entry.S │ │ ├── infinite_loop │ │ ├── infinite_loop.c │ │ ├── init.c │ │ ├── mprv.S │ │ ├── priv.S │ │ ├── regs.S │ │ ├── start.S │ │ ├── step.S │ │ ├── tiny-malloc.c │ │ └── trigger.S │ ├── pylint.rc │ ├── requirements.txt │ ├── targets.py │ ├── targets │ │ ├── HiFive1 │ │ │ ├── link.lds │ │ │ └── openocd.cfg │ │ ├── freedom-e300-sim │ │ │ ├── link.lds │ │ │ └── openocd.cfg │ │ ├── freedom-e300 │ │ │ ├── link.lds │ │ │ └── openocd.cfg │ │ ├── freedom-u500-sim │ │ │ ├── link.lds │ │ │ └── openocd.cfg │ │ ├── freedom-u500 │ │ │ ├── link.lds │ │ │ └── openocd.cfg │ │ └── spike │ │ │ ├── link.lds │ │ │ └── openocd.cfg │ └── testlib.py ├── env │ ├── LICENSE │ ├── encoding.h │ ├── p │ │ ├── link.ld │ │ └── riscv_test.h │ ├── pm │ │ ├── link.ld │ │ └── riscv_test.h │ ├── pt │ │ ├── link.ld │ │ └── riscv_test.h │ └── v │ │ ├── entry.S │ │ ├── link.ld │ │ ├── riscv_test.h │ │ ├── string.c │ │ └── vm.c ├── isa │ ├── .gitignore │ ├── Makefile │ ├── macros │ │ └── scalar │ │ │ └── test_macros.h │ ├── rv32mi │ │ ├── Makefrag │ │ ├── breakpoint.S │ │ ├── csr.S │ │ ├── illegal.S │ │ ├── ma_addr.S │ │ ├── ma_fetch.S │ │ ├── mcsr.S │ │ ├── sbreak.S │ │ ├── scall.S │ │ └── shamt.S │ ├── rv32si │ │ ├── Makefrag │ │ ├── csr.S │ │ ├── dirty.S │ │ ├── ma_fetch.S │ │ ├── sbreak.S │ │ ├── scall.S │ │ └── wfi.S │ ├── rv32ua │ │ ├── Makefrag │ │ ├── amoadd_w.S │ │ ├── amoand_w.S │ │ ├── amomax_w.S │ │ ├── amomaxu_w.S │ │ ├── amomin_w.S │ │ ├── amominu_w.S │ │ ├── amoor_w.S │ │ ├── amoswap_w.S │ │ ├── amoxor_w.S │ │ └── lrsc.S │ ├── rv32uc │ │ ├── Makefrag │ │ └── rvc.S │ ├── rv32uf │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ └── recoding.S │ ├── rv32ui │ │ ├── Makefrag │ │ ├── add.S │ │ ├── addi.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── sub.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S │ ├── rv32um │ │ ├── Makefrag │ │ ├── div.S │ │ ├── divu.S │ │ ├── mul.S │ │ ├── mulh.S │ │ ├── mulhsu.S │ │ ├── mulhu.S │ │ ├── rem.S │ │ └── remu.S │ ├── rv64mi │ │ ├── Makefrag │ │ ├── breakpoint.S │ │ ├── csr.S │ │ ├── illegal.S │ │ ├── ma_addr.S │ │ ├── ma_fetch.S │ │ ├── mcsr.S │ │ ├── sbreak.S │ │ └── scall.S │ ├── rv64si │ │ ├── Makefrag │ │ ├── csr.S │ │ ├── dirty.S │ │ ├── ma_fetch.S │ │ ├── sbreak.S │ │ ├── scall.S │ │ └── wfi.S │ ├── rv64ua │ │ ├── Makefrag │ │ ├── amoadd_d.S │ │ ├── amoadd_w.S │ │ ├── amoand_d.S │ │ ├── amoand_w.S │ │ ├── amomax_d.S │ │ ├── amomax_w.S │ │ ├── amomaxu_d.S │ │ ├── amomaxu_w.S │ │ ├── amomin_d.S │ │ ├── amomin_w.S │ │ ├── amominu_d.S │ │ ├── amominu_w.S │ │ ├── amoor_d.S │ │ ├── amoor_w.S │ │ ├── amoswap_d.S │ │ ├── amoswap_w.S │ │ ├── amoxor_d.S │ │ ├── amoxor_w.S │ │ └── lrsc.S │ ├── rv64uc │ │ ├── Makefrag │ │ └── rvc.S │ ├── rv64ud │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ ├── recoding.S │ │ └── structural.S │ ├── rv64uf │ │ ├── Makefrag │ │ ├── fadd.S │ │ ├── fclass.S │ │ ├── fcmp.S │ │ ├── fcvt.S │ │ ├── fcvt_w.S │ │ ├── fdiv.S │ │ ├── fmadd.S │ │ ├── fmin.S │ │ ├── ldst.S │ │ ├── move.S │ │ └── recoding.S │ ├── rv64ui │ │ ├── Makefrag │ │ ├── add.S │ │ ├── addi.S │ │ ├── addiw.S │ │ ├── addw.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── ld.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── lwu.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sd.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slliw.S │ │ ├── sllw.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── sraiw.S │ │ ├── sraw.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── srliw.S │ │ ├── srlw.S │ │ ├── sub.S │ │ ├── subw.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S │ └── rv64um │ │ ├── Makefrag │ │ ├── div.S │ │ ├── divu.S │ │ ├── divuw.S │ │ ├── divw.S │ │ ├── mul.S │ │ ├── mulh.S │ │ ├── mulhsu.S │ │ ├── mulhu.S │ │ ├── mulw.S │ │ ├── rem.S │ │ ├── remu.S │ │ ├── remuw.S │ │ └── remw.S └── mt │ ├── .gitignore │ ├── Makefile │ ├── ad_matmul.c │ ├── ae_matmul.c │ ├── af_matmul.c │ ├── ag_matmul.c │ ├── ai_matmul.c │ ├── ak_matmul.c │ ├── al_matmul.c │ ├── am_matmul.c │ ├── an_matmul.c │ ├── ap_matmul.c │ ├── aq_matmul.c │ ├── ar_matmul.c │ ├── at_matmul.c │ ├── av_matmul.c │ ├── ay_matmul.c │ ├── az_matmul.c │ ├── bb_matmul.c │ ├── bc_matmul.c │ ├── bf_matmul.c │ ├── bh_matmul.c │ ├── bj_matmul.c │ ├── bk_matmul.c │ ├── bm_matmul.c │ ├── bo_matmul.c │ ├── br_matmul.c │ ├── bs_matmul.c │ ├── ce_matmul.c │ ├── cf_matmul.c │ ├── cg_matmul.c │ ├── ci_matmul.c │ ├── ck_matmul.c │ ├── cl_matmul.c │ ├── cm_matmul.c │ ├── cs_matmul.c │ ├── cv_matmul.c │ ├── cy_matmul.c │ ├── dc_matmul.c │ ├── df_matmul.c │ ├── dm_matmul.c │ ├── do_matmul.c │ ├── dr_matmul.c │ ├── ds_matmul.c │ ├── du_matmul.c │ ├── dv_matmul.c │ ├── vvadd0.c │ ├── vvadd1.c │ ├── vvadd2.c │ ├── vvadd3.c │ └── vvadd4.c ├── run.tcl ├── sim ├── Makefile ├── modelsim.ini ├── tests │ ├── benchmarks │ │ ├── coremark │ │ │ ├── Makefile │ │ │ ├── core_portme.h │ │ │ └── coremark.h │ │ └── dhrystone21 │ │ │ ├── Makefile │ │ │ ├── dhry.h │ │ │ ├── dhry_1.c │ │ │ └── dhry_2.c │ ├── common │ │ ├── LICENSE │ │ ├── common.mk │ │ ├── crt.S │ │ ├── crt_tcm.S │ │ ├── csr.h │ │ ├── link.ld │ │ ├── link_tcm.ld │ │ ├── riscv_csr_encoding.h │ │ ├── riscv_macros.h │ │ ├── sc_print.c │ │ ├── sc_print.h │ │ ├── sc_test.h │ │ └── scr1_specific.h │ ├── hello │ │ ├── Makefile │ │ └── hello.c │ ├── riscv_compliance │ │ ├── Makefile │ │ ├── aw_test_macros.h │ │ ├── compliance_io.h │ │ ├── compliance_test.h │ │ ├── riscv_test.h │ │ └── test_macros.h │ ├── riscv_isa │ │ ├── Makefile │ │ ├── riscv_test.h │ │ ├── rv32_tests.inc │ │ └── test_macros.h │ ├── sm4-isa-ext │ │ ├── Makefile │ │ └── sm4-isa-ext.c │ ├── sm4-wo-isa-ext │ │ ├── .sm4-wo-isa-ext.c.swp │ │ ├── Makefile │ │ └── sm4-wo-isa-ext.c │ └── vectored_isr_sample │ │ ├── Makefile │ │ ├── timer.h │ │ └── v_isr_sample.S ├── verilator_wrap │ ├── scr1_ahb_wrapper.c │ └── scr1_axi_wrapper.c └── work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ └── _vmake └── src ├── ahb_tb.files ├── ahb_top.files ├── axi_tb.files ├── axi_top.files ├── core.files ├── core ├── primitives │ ├── scr1_cg.sv │ └── scr1_reset_cells.sv ├── scr1_clk_ctrl.sv ├── scr1_core_top.sv ├── scr1_dm.sv ├── scr1_dmi.sv ├── scr1_scu.sv ├── scr1_tapc.sv ├── scr1_tapc_shift_reg.sv └── scr1_tapc_synchronizer.sv ├── includes ├── scr1_ahb.svh ├── scr1_arch_description.svh ├── scr1_arch_types.svh ├── scr1_csr.svh ├── scr1_dm.svh ├── scr1_hdu.svh ├── scr1_ipic.svh ├── scr1_memif.svh ├── scr1_riscv_isa_decoding.svh ├── scr1_search_ms1.svh ├── scr1_tapc.svh └── scr1_tdu.svh ├── pipeline ├── sbox.sv ├── scr1_ipic.sv ├── scr1_pipe_csr.sv ├── scr1_pipe_exu.sv ├── scr1_pipe_hdu.sv ├── scr1_pipe_ialu.sv ├── scr1_pipe_idu.sv ├── scr1_pipe_ifu.sv ├── scr1_pipe_lsu.sv ├── scr1_pipe_mprf.sv ├── scr1_pipe_tdu.sv ├── scr1_pipe_top.sv ├── scr1_tracelog.sv └── sm4lt.sv ├── tb ├── scr1_memory_tb_ahb.sv ├── scr1_memory_tb_axi.sv ├── scr1_top_tb_ahb.sv └── scr1_top_tb_axi.sv └── top ├── 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