├── .editorconfig ├── .github └── workflows │ └── main.yml ├── .gitignore ├── 00_Introduction.ipynb ├── 01_Python_concepts.ipynb ├── 02_Python_basics.ipynb ├── 03_Conditions_and_loops.ipynb ├── 04_Python_sequences.ipynb ├── 05_Tuples.ipynb ├── 06_Ranges.ipynb ├── 07_Strings.ipynb ├── 08_Lists.ipynb ├── 09_Sets.ipynb ├── 10_Commonly_used_sequence_operations.ipynb ├── 11_Modules.ipynb ├── 12_Functions.ipynb ├── 13_Exceptions.ipynb ├── 14_Dictionaries.ipynb ├── 15_Generators.ipynb ├── 16_Classes.ipynb ├── 17_Protecting_attributes.ipynb ├── 18_Inheritance.ipynb ├── 19_Design_patterns.ipynb ├── 20_Coroutines ├── Makefile ├── clocker.sv └── testbench.py ├── 21_cocotb_Queue ├── Makefile ├── clocker.sv └── testbench.py ├── 22_Simulating_with_cocotb ├── Makefile ├── counter.sv └── testbench.py ├── 23_Basic_testbench_1.0 ├── Makefile └── testbench.py ├── 24_TinyAluBfm ├── Makefile └── testbench.py ├── 25_Class_based_testbench_2.0 ├── Makefile └── testbench.py ├── 27_uvm_test_testbench_3.0 ├── Makefile └── testbench.py ├── 28_uvm_component ├── Makefile ├── clocker.sv └── testbench.py ├── 29_uvm_env_testbench_4.0 ├── Makefile └── testbench.py ├── 30_Logging ├── Makefile ├── clocker.sv └── testbench.py ├── 31_ConfigDB ├── Makefile ├── clocker.sv └── testbench.py ├── 32_Debugging_the_ConfigDB ├── Makefile ├── clocker.sv └── testbench.py ├── 33_The_UVM_factory ├── Makefile ├── clocker.sv └── testbench.py ├── 34_uvm_factory_testbench_5.0 ├── Makefile └── testbench.py ├── 35_Component_communications ├── Makefile ├── clocker.sv └── testbench.py ├── 36_Analysis_ports ├── Makefile ├── clocker.sv └── testbench.py ├── 37_components_in_testbench_6.0 ├── Makefile └── component_testbench.py ├── 38_connections_in_testbench_6.0 ├── Makefile └── testbench.py ├── 39_uvm_object_in_Python ├── Makefile ├── clocker.sv └── testbench.py ├── 40_Sequence_testbench_7.0 ├── Makefile └── testbench.py ├── 41_Fibonacci_testbench_7.1 ├── Makefile └── testbench.py ├── 42_Fibonacci_get_response_testbench_7.2 ├── Makefile └── testbench.py ├── 43_Virtual_sequence_teestbench_8.0 ├── Makefile └── testbench.py ├── LICENSE ├── README.md ├── cleanall.mk ├── combine_results.py ├── pyproject.toml ├── tinyalu_hdl ├── verilog │ └── tinyalu.sv └── vhdl │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_utils.py └── tox.ini /.editorconfig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/raysalemi/Python4RTLVerification/HEAD/.editorconfig -------------------------------------------------------------------------------- /.github/workflows/main.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/raysalemi/Python4RTLVerification/HEAD/.github/workflows/main.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 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