├── .gitignore ├── 02_Conventional_Testbench ├── dut.f ├── run.do ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_tb.sv └── wave.do ├── 03_Interfaces_and_BFMs ├── coverage.sv ├── dut.f ├── run.do ├── scoreboard.sv ├── tb.f ├── tester.sv ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_pkg.sv └── top.sv ├── 05_Classes_and_Extension ├── classes.sv ├── rectangle_only.sv ├── run_class.do ├── run_rectangle.do ├── run_struct.do ├── structs.sv └── sv.f ├── 06_Polymorphism ├── 01_Not_Virtual │ ├── not_virtual.sv │ ├── run.do │ └── sv.f ├── 02_Virtual │ ├── run.do │ ├── sv.f │ └── virtual.sv └── 03_Pure_Virtual │ ├── pure_virtual.sv │ ├── run.do │ └── sv.f ├── 07_Static_Methods ├── 01_Static_Variables │ ├── run.do │ ├── static_variables.sv │ └── sv.f └── 02_Static_Methods │ ├── run.do │ ├── static_methods.sv │ └── sv.f ├── 08_Parameterized_Classes ├── 01_memory_example │ ├── ram.sv │ ├── run.do │ └── top.sv ├── 02_static │ ├── cages.sv │ ├── run.do │ └── sv.f └── 03_instantiated │ ├── cages.sv │ ├── run.do │ └── sv.f ├── 09_Factory_Pattern ├── factory.sv ├── run.do └── sv.f ├── 10_An_Object_Oriented_Testbench ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── coverage.svh │ ├── scoreboard.svh │ ├── testbench.svh │ └── tester.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 11_UVM_Test ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_tester.svh │ ├── coverage.svh │ ├── random_test.svh │ ├── random_tester.svh │ ├── scoreboard.svh │ └── selfcheck.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 12_UVM_Components ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_tester.svh │ ├── coverage.svh │ ├── random_test.svh │ ├── random_tester.svh │ └── scoreboard.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 13_UVM_Environments ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_tester.svh │ ├── base_tester.svh │ ├── coverage.svh │ ├── env.svh │ ├── random_test.svh │ ├── random_tester.svh │ ├── scoreboard.svh │ └── vcs_base_tester.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 15_Talking_Objects ├── 01_No_Analysis_Port │ ├── #dice_test.svh# │ ├── average.svh │ ├── coverage.svh │ ├── dice_pkg.sv │ ├── dice_roller.svh │ ├── dice_test.svh │ ├── histogram.svh │ ├── run.do │ └── top.sv └── 02_With_Analysis_Port │ ├── average.svh │ ├── coverage.svh │ ├── dice_pkg.sv │ ├── dice_roller.svh │ ├── dice_test.svh │ ├── histogram.svh │ ├── run.do │ └── top.sv ├── 16_Analysis_Ports_In_the_Testbench ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_tester.svh │ ├── base_tester.svh │ ├── command_monitor.svh │ ├── coverage.svh │ ├── env.svh │ ├── random_test.svh │ ├── random_tester.svh │ ├── result_monitor.svh │ ├── scoreboard.svh │ └── vcs_base_tester.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 17_Interthread_Communication ├── 01_Modules │ ├── modules.sv │ └── run.do ├── 02_Blocking │ ├── communication_test.svh │ ├── consumer.svh │ ├── example_pkg.sv │ ├── producer.svh │ ├── run.do │ └── top.sv └── 03_NonBlocking │ ├── communication_test.svh │ ├── consumer.svh │ ├── example_pkg.sv │ ├── producer.svh │ ├── run.do │ └── top.sv ├── 18_Put_and_Get_in_Action ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_tester.svh │ ├── base_tester.svh │ ├── command_monitor.svh │ ├── coverage.svh │ ├── driver.svh │ ├── env.svh │ ├── random_test.svh │ ├── random_tester.svh │ ├── result_monitor.svh │ ├── scoreboard.svh │ └── vcs_base_tester.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 19_UVM_Reporting ├── dut.f ├── run.do ├── run.txt ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_tester.svh │ ├── base_tester.svh │ ├── command_monitor.svh │ ├── coverage.svh │ ├── driver.svh │ ├── env.svh │ ├── random_test.svh │ ├── random_tester.svh │ ├── result_monitor.svh │ ├── scoreboard.svh │ └── vcs_base_tester.svh ├── tinyalu_bfm.sv ├── tinyalu_driver_c.svh ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv ├── tinyalu_tlm_bfm.sv └── top.sv ├── 20_Deep_Operations ├── deep.sv ├── run.do ├── sv.f └── wrong.sv ├── 21_UVM_Transactions ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_test.svh │ ├── add_transaction.svh │ ├── command_monitor.svh │ ├── command_transaction.svh │ ├── coverage.svh │ ├── driver.svh │ ├── env.svh │ ├── random_test.svh │ ├── result_monitor.svh │ ├── result_transaction.svh │ ├── scoreboard.svh │ └── tester.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── 22_UVM_Agents ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_transaction.svh │ ├── command_monitor.svh │ ├── command_transaction.svh │ ├── coverage.svh │ ├── driver.svh │ ├── dual_test.svh │ ├── env.svh │ ├── env_config.svh │ ├── result_monitor.svh │ ├── result_transaction.svh │ ├── scoreboard.svh │ ├── tester.svh │ ├── tinyalu_agent.svh │ └── tinyalu_agent_config.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv ├── tinyalu_tester_module.sv └── top.sv ├── 23_UVM_Sequences ├── dut.f ├── run.do ├── tb.f ├── tb_classes │ ├── add_sequence.svh │ ├── add_sequence_item.svh │ ├── command_monitor.svh │ ├── coverage.svh │ ├── driver.svh │ ├── env.svh │ ├── fibonacci_sequence.svh │ ├── fibonacci_test.svh │ ├── full_test.svh │ ├── maxmult_sequence.svh │ ├── parallel_sequence.svh │ ├── parallel_test.svh │ ├── random_sequence.svh │ ├── reset_sequence.svh │ ├── result_monitor.svh │ ├── result_transaction.svh │ ├── runall_sequence.svh │ ├── scoreboard.svh │ ├── sequence_item.svh │ ├── short_random_sequence.svh │ ├── tinyalu_base_test.svh │ ├── tinyalu_run_sequence.svh │ └── tinyalu_sequence.svh ├── tinyalu_bfm.sv ├── tinyalu_dut │ ├── single_cycle_add_and_xor.vhd │ ├── three_cycle_mult.vhd │ └── tinyalu.vhd ├── tinyalu_macros.svh ├── tinyalu_pkg.sv └── top.sv ├── LICENSE-2.0.txt ├── README.md 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