├── sim ├── hello.mem ├── hello.vmem ├── tb_defines.v ├── vivado_sdf_file_list.txt ├── Makefile ├── iverilog_file_list.txt └── vivado_file_list.txt ├── Makefile ├── ips └── clock_manager │ ├── ip_user_files │ ├── sim_scripts │ │ └── arty_mmcm │ │ │ ├── modelsim │ │ │ ├── arty_mmcm.udo │ │ │ ├── wave.do │ │ │ ├── filelist.f │ │ │ ├── file_info.txt │ │ │ ├── compile.do │ │ │ ├── simulate.do │ │ │ ├── README.txt │ │ │ └── clk_wiz_v5_2_changelog.txt │ │ │ ├── questa │ │ │ ├── arty_mmcm.udo │ │ │ ├── wave.do │ │ │ ├── filelist.f │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── simulate.do │ │ │ ├── compile.do │ │ │ ├── README.txt │ │ │ └── clk_wiz_v5_2_changelog.txt │ │ │ ├── vcs │ │ │ ├── simulate.do │ │ │ ├── filelist.f │ │ │ ├── file_info.txt │ │ │ ├── README.txt │ │ │ └── clk_wiz_v5_2_changelog.txt │ │ │ ├── ies │ │ │ ├── filelist.f │ │ │ ├── simulate.do │ │ │ ├── file_info.txt │ │ │ ├── README.txt │ │ │ └── clk_wiz_v5_2_changelog.txt │ │ │ ├── xsim │ │ │ ├── filelist.f │ │ │ ├── vlog.prj │ │ │ ├── file_info.txt │ │ │ ├── cmd.tcl │ │ │ ├── README.txt │ │ │ ├── clk_wiz_v5_2_changelog.txt │ │ │ └── arty_mmcm.sh │ │ │ └── README.txt │ ├── README.txt │ ├── ip │ │ └── arty_mmcm │ │ │ ├── arty_mmcm_stub.v │ │ │ ├── arty_mmcm_stub.vhdl │ │ │ └── arty_mmcm.veo │ └── mem_init_files │ │ └── clk_wiz_v5_2_changelog.txt │ ├── managed_ip_project │ ├── managed_ip_project.runs │ │ ├── arty_mmcm_synth_1 │ │ │ ├── .vivado.end.rst │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── vivado.pb │ │ │ ├── arty_mmcm.dcp │ │ │ ├── .vivado.begin.rst │ │ │ ├── arty_mmcm_utilization_synth.pb │ │ │ ├── runme.bat │ │ │ ├── htr.txt │ │ │ ├── .Xil │ │ │ │ └── arty_mmcm_propImpl.xdc │ │ │ ├── runme.sh │ │ │ ├── rundef.js │ │ │ ├── ISEWrap.sh │ │ │ ├── project.wdf │ │ │ ├── gen_run.xml │ │ │ ├── dont_touch.xdc │ │ │ └── arty_mmcm.tcl │ │ └── .jobs │ │ │ └── vrs_config_1.xml │ ├── managed_ip_project.cache │ │ └── wt │ │ │ ├── project.wpc │ │ │ ├── synthesis_details.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── synthesis.wdf │ └── managed_ip_project.hw │ │ └── managed_ip_project.lpr │ └── arty_mmcm │ ├── arty_mmcm_board.xdc │ ├── arty_mmcm.dcp │ ├── arty_mmcm_stub.v │ ├── arty_mmcm_stub.vhdl │ ├── arty_mmcm_ooc.xdc │ ├── arty_mmcm.xdc │ ├── arty_mmcm.veo │ ├── arty_mmcm.v │ └── doc │ └── clk_wiz_v5_2_changelog.txt ├── docs ├── arty.png ├── Diagram1.dia ├── mmi_flow.dia ├── arty_small.png └── index.md ├── mkdocs.yml ├── site ├── arty.png ├── Diagram1.dia ├── img │ ├── grid.png │ └── favicon.ico ├── mmi_flow.dia ├── arty_small.png ├── fonts │ ├── fontawesome-webfont.eot │ ├── fontawesome-webfont.ttf │ └── fontawesome-webfont.woff ├── mkdocs │ └── js │ │ ├── search-results-template.mustache │ │ └── search.js ├── sitemap.xml ├── js │ └── base.js ├── license │ └── highlight.js │ │ └── LICENSE ├── css │ ├── highlight.css │ └── base.css └── 404.html ├── patches └── Makefile ├── .gitmodules ├── software ├── gpio_test │ ├── Makefile │ └── gpio_test.c ├── gpio_test_infinite │ ├── Makefile │ └── gpio_test_infinite.c ├── support │ └── exit.c ├── scripts │ ├── lib-nosys.ld │ ├── cmsdk_cm0.ld │ └── sections.ld └── Common.mk ├── verilator_sim ├── Makefile ├── tb_cmsdk_mcu.cpp ├── arty_mmcm.v └── verilator_file_list.txt ├── synt ├── prog.tcl ├── report_bram.tcl ├── Makefile ├── yaml2mmi.py ├── bram.yaml ├── vivado_utils.tcl ├── cortexm0.mmi ├── test.mmi └── test2.mmi ├── .gitignore ├── common ├── Makefile ├── iverilog.py ├── xilinx.py ├── arty.py └── file_list.py ├── README.md ├── rtl ├── bytewrite_ram_1b.v ├── bytewrite_ram_32bits.v ├── arty_mmcm_sim.v └── sync_ram_wf_x32.v └── doc └── programming.org /sim/hello.mem: -------------------------------------------------------------------------------- 1 | hello.vmem32 -------------------------------------------------------------------------------- /sim/hello.vmem: -------------------------------------------------------------------------------- 1 | hello.vmem32 -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | CORTEX0_DS?=../../arm/cortexm0_designstart 2 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/arty_mmcm.udo: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/arty_mmcm.udo: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /docs/arty.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/docs/arty.png -------------------------------------------------------------------------------- /mkdocs.yml: -------------------------------------------------------------------------------- 1 | site_name: My Docs 2 | pages: 3 | - Home : index.md 4 | 5 | theme: cosmo 6 | -------------------------------------------------------------------------------- /site/arty.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/arty.png -------------------------------------------------------------------------------- /docs/Diagram1.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/docs/Diagram1.dia -------------------------------------------------------------------------------- /docs/mmi_flow.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/docs/mmi_flow.dia -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /patches/Makefile: -------------------------------------------------------------------------------- 1 | patch: 2 | patch -d $(DESIGNSTART_TOP) -p1 < ./patch_cm0_designstart.patch 3 | -------------------------------------------------------------------------------- /site/Diagram1.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/Diagram1.dia -------------------------------------------------------------------------------- /site/img/grid.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/img/grid.png -------------------------------------------------------------------------------- /site/mmi_flow.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/mmi_flow.dia -------------------------------------------------------------------------------- /docs/arty_small.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/docs/arty_small.png -------------------------------------------------------------------------------- /site/arty_small.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/arty_small.png -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /site/img/favicon.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/img/favicon.ico -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/ies/filelist.f: -------------------------------------------------------------------------------- 1 | ../../../../arty_mmcm/arty_mmcm_sim_netlist.v 2 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/vcs/filelist.f: -------------------------------------------------------------------------------- 1 | ../../../../arty_mmcm/arty_mmcm_sim_netlist.v 2 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/filelist.f: -------------------------------------------------------------------------------- 1 | ../../../../arty_mmcm/arty_mmcm_sim_netlist.v 2 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/filelist.f: -------------------------------------------------------------------------------- 1 | ../../../../arty_mmcm/arty_mmcm_sim_netlist.v 2 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/filelist.f: -------------------------------------------------------------------------------- 1 | ../../../../arty_mmcm/arty_mmcm_sim_netlist.v 2 | -------------------------------------------------------------------------------- /site/fonts/fontawesome-webfont.eot: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/fonts/fontawesome-webfont.eot -------------------------------------------------------------------------------- /site/fonts/fontawesome-webfont.ttf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/fonts/fontawesome-webfont.ttf -------------------------------------------------------------------------------- /site/fonts/fontawesome-webfont.woff: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/site/fonts/fontawesome-webfont.woff -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "import/amba_components"] 2 | path = import/amba_components 3 | url = https://github.com/rbarzic/amba_components.git 4 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/ips/clock_manager/arty_mmcm/arty_mmcm.dcp -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /site/mkdocs/js/search-results-template.mustache: -------------------------------------------------------------------------------- 1 |
2 |

{{title}}

3 |

{{summary}}

4 |
5 | -------------------------------------------------------------------------------- /software/gpio_test/Makefile: -------------------------------------------------------------------------------- 1 | # GPIO_TEST 2 | 3 | TOP=../.. 4 | 5 | TESTNAME=gpio_test 6 | SOURCES=gpio_test.c ../support/exit.c 7 | 8 | include ../Common.mk 9 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /software/gpio_test_infinite/Makefile: -------------------------------------------------------------------------------- 1 | # GPIO_TEST 2 | 3 | TOP=../.. 4 | 5 | TESTNAME=gpio_test_infinite 6 | SOURCES=gpio_test_infinite.c ../support/exit.c 7 | 8 | include ../Common.mk 9 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.cache/wt/synthesis_details.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 3 | eof:2511430288 4 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib "./../../../../arty_mmcm/arty_mmcm_sim_netlist.v" 2 | 3 | verilog xil_defaultlib "glbl.v" 4 | 5 | nosort 6 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/vivado.pb -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/ies/simulate.do: -------------------------------------------------------------------------------- 1 | set pack_assert_off {numeric_std std_logic_arith} 2 | 3 | database -open waves -into waves.shm -default 4 | probe -create -shm -all -variables -depth 1 5 | 6 | run 7 | exit 8 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:31:00:00 3 | eof:289111512 4 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/arty_mmcm.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/arty_mmcm.dcp -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L unisims_ver -L unimacro_ver -L secureip -L xil_defaultlib -work xil_defaultlib xil_defaultlib.arty_mmcm xil_defaultlib.glbl -o arty_mmcm_opt 2 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/arty_mmcm_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rbarzic/arty-cm0-designstart/HEAD/ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/arty_mmcm_utilization_synth.pb -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | Language File-Name IP Library File-Path 2 | Verilog, arty_mmcm_sim_netlist.v, arty_mmcm, xil_defaultlib, ./../../../../arty_mmcm/arty_mmcm_sim_netlist.v 3 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | Language File-Name IP Library File-Path 2 | Verilog, arty_mmcm_sim_netlist.v, arty_mmcm, xil_defaultlib, ./../../../../arty_mmcm/arty_mmcm_sim_netlist.v 3 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | Language File-Name IP Library File-Path 2 | Verilog, arty_mmcm_sim_netlist.v, arty_mmcm, xil_defaultlib, ./../../../../arty_mmcm/arty_mmcm_sim_netlist.v 3 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | Language File-Name IP Library File-Path 2 | Verilog, arty_mmcm_sim_netlist.v, arty_mmcm, xil_defaultlib, ./../../../../arty_mmcm/arty_mmcm_sim_netlist.v 3 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | Language File-Name IP Library File-Path 2 | Verilog, arty_mmcm_sim_netlist.v, arty_mmcm, xil_defaultlib, ./../../../../arty_mmcm/arty_mmcm_sim_netlist.v 3 | -------------------------------------------------------------------------------- /site/sitemap.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | None/ 7 | 2015-12-22 8 | daily 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib arty_mmcm_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {arty_mmcm.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /verilator_sim/Makefile: -------------------------------------------------------------------------------- 1 | # VERILOG_DEBUG= --debug --gdbbt 2 | 3 | 4 | build: 5 | verilator $(VERILOG_DEBUG) -Wno-fatal -Wall --trace --cc -f verilator_file_list.txt --top-module cmsdk_mcu --exe tb_cmsdk_mcu.cpp 6 | 7 | comp: 8 | make -C obj_dir -j -f Vcmsdk_mcu.mk Vcmsdk_mcu 9 | 10 | run: 11 | obj_dir/Vcmsdk_mcu 12 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib msim 3 | 4 | vlib msim/xil_defaultlib 5 | 6 | vmap xil_defaultlib msim/xil_defaultlib 7 | 8 | vlog -work xil_defaultlib -64 \ 9 | "./../../../../arty_mmcm/arty_mmcm_sim_netlist.v" \ 10 | 11 | 12 | vlog -work xil_defaultlib "glbl.v" 13 | 14 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib msim 3 | 4 | vlib msim/xil_defaultlib 5 | 6 | vmap xil_defaultlib msim/xil_defaultlib 7 | 8 | vlog -work xil_defaultlib -64 -incr \ 9 | "./../../../../arty_mmcm/arty_mmcm_sim_netlist.v" \ 10 | 11 | 12 | vlog -work xil_defaultlib "glbl.v" 13 | 14 | -------------------------------------------------------------------------------- /synt/prog.tcl: -------------------------------------------------------------------------------- 1 | # Programming file using Vivado 2 | # hw_server must be launched first 3 | 4 | open_hw 5 | connect_hw_server -url localhost:3121 6 | current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*] 7 | open_hw_target 8 | set_property PROGRAM.FILE {./rpt/cpu.bit} [lindex [get_hw_devices] 0] 9 | program_hw_devices [lindex [get_hw_devices] 0] 10 | -------------------------------------------------------------------------------- /sim/tb_defines.v: -------------------------------------------------------------------------------- 1 | `define hclk tb_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_cortexm0integration.u_cortexm0.HCLK 2 | `define pc tb_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_cortexm0integration.u_cortexm0.cm0_pc[31:0] 3 | `define r0 tb_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_cortexm0integration.u_cortexm0.cm0_r00[31:0] 4 | 5 | 6 | wire [31:0] pc; 7 | assign pc = `pc; 8 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | set PATH=%SYSTEMROOT%\system32;%PATH% 11 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 12 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.o 3 | *.ko 4 | *.obj 5 | *.elf 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Libraries 12 | *.lib 13 | *.a 14 | *.la 15 | *.lo 16 | 17 | # Shared objects (inc. Windows DLLs) 18 | *.dll 19 | *.so 20 | *.so.* 21 | *.dylib 22 | 23 | # Executables 24 | *.exe 25 | *.out 26 | *.app 27 | *.i*86 28 | *.x86_64 29 | *.hex 30 | 31 | # Debug files 32 | *.dSYM/ 33 | *.pyc 34 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L unisims_ver -L unimacro_ver -L secureip -L xil_defaultlib -lib xil_defaultlib xil_defaultlib.arty_mmcm xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {arty_mmcm.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /site/js/base.js: -------------------------------------------------------------------------------- 1 | 2 | /* Highlight */ 3 | $( document ).ready(function() { 4 | hljs.initHighlightingOnLoad(); 5 | $('table').addClass('table table-striped table-hover'); 6 | }); 7 | 8 | 9 | $('body').scrollspy({ 10 | target: '.bs-sidebar', 11 | }); 12 | 13 | 14 | /* Prevent disabled links from causing a page reload */ 15 | $("li.disabled a").click(function() { 16 | event.preventDefault(); 17 | }); 18 | 19 | 20 | 21 | -------------------------------------------------------------------------------- /synt/report_bram.tcl: -------------------------------------------------------------------------------- 1 | # script to help generation of MMI file 2 | set all_rom_blocks [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "*u_ahb_rom*" }] 3 | puts "# Block ram description" 4 | puts "---" 5 | puts "bram:" 6 | foreach block $all_rom_blocks { 7 | puts "- NAME: [get_property NAME $block]" 8 | puts " SITE: [get_property SITE $block]" 9 | puts " READ_WIDTH_A: [get_property READ_WIDTH_A $block]" 10 | } 11 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado(TM) 3 | # htr.txt: a Vivado-generated description of how-to-repeat the 4 | # the basic steps of a run. Note that runme.bat/sh needs 5 | # to be invoked for Vivado to track run status. 6 | # Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | vivado -log arty_mmcm.vds -m64 -mode batch -messageDb vivado.pb -notrace -source arty_mmcm.tcl 10 | -------------------------------------------------------------------------------- /common/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile to generate tools configuration files 2 | 3 | iverilog: 4 | @python arty.py --topdir=.. --designstart=$(DESIGNSTART_TOP) --iverilog ../sim/iverilog_file_list.txt 5 | 6 | vivado_sim: 7 | @python arty.py --topdir=.. --designstart=$(DESIGNSTART_TOP) --vivado_sim ../sim/vivado_file_list.txt 8 | 9 | vivado_synt: 10 | @python arty.py --topdir=.. --designstart=$(DESIGNSTART_TOP) --vivado_synt ../sim/vivado_file_list.tcl 11 | 12 | 13 | all: iverilog vivado_sim 14 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/.Xil/arty_mmcm_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:/home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xdc rfile:../../../../arty_mmcm/arty_mmcm.xdc id:1 order:EARLY scoped_inst:inst} [current_design] 2 | set_property src_info {type:SCOPED_XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] 3 | set_input_jitter [get_clocks -of_objects [get_ports clk_in]] 0.1 4 | -------------------------------------------------------------------------------- /synt/Makefile: -------------------------------------------------------------------------------- 1 | # Vivado synt script 2 | 3 | 4 | CORTEXM0_DS ?= ../../../arm/cortexm0_designstart 5 | XILINX_PART=xc7a35tcsg324-1 6 | export CORTEXM0_DS 7 | export XILINX_PART 8 | synt: 9 | vivado -mode tcl -source vivado.tcl 10 | 11 | 12 | mmi: 13 | python yaml2mmi.py > cortexm0.mmi 14 | 15 | # use --debug option below if something is wrong after updating the bitstream 16 | update: 17 | updatemem --debug -bit rpt/cpu.bit -meminfo cortexm0.mmi -data ../software/$(TEST)/$(TEST).elf -proc design/cortex -o $(TEST).bit | tee debug.txt 18 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /software/support/exit.c: -------------------------------------------------------------------------------- 1 | void exit(int status) __attribute__ ((section (".tbench"))); 2 | 3 | void exit(int status) { 4 | // asm volatile ("mov r0 "); 5 | // asm volatile ("mov r0,%0 " 6 | // : /* no output register */ 7 | // : "r(status)" 8 | // ); 9 | 10 | // asm("mov %[result], %[value], ror #1" : [result] "=r" (y) : [value] "r" (x)); 11 | __asm ("mov r0, %0" : : "r" (status)); 12 | __asm ("mov r0, %0" : : "r" (status)); 13 | __asm ("mov r0, %0" : : "r" (status)); 14 | __asm ("mov r0, %0" : : "r" (status)); 15 | __asm ("mov r0, %0" : : "r" (status)); 16 | while(1); 17 | } 18 | -------------------------------------------------------------------------------- /software/gpio_test/gpio_test.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "CMSDK_CM0.h" 3 | 4 | #define small_delay __ISB 5 | 6 | void medium_delay() { 7 | for(uint32_t i=0;i<10;i++) { 8 | small_delay(); 9 | } 10 | 11 | } 12 | 13 | void long_delay() { 14 | for(uint32_t i=0;i<50000;i++) { 15 | medium_delay(); 16 | } 17 | 18 | } 19 | 20 | 21 | 22 | int main (void) 23 | { 24 | CMSDK_GPIO0->OUTENABLESET = 0x00000001; 25 | 26 | for(int i =0; i<5; i++) { 27 | CMSDK_GPIO0-> DATAOUT = 0; 28 | small_delay(); 29 | CMSDK_GPIO0-> DATAOUT = 1; 30 | small_delay(); 31 | } 32 | return 0; 33 | 34 | } 35 | -------------------------------------------------------------------------------- /software/gpio_test_infinite/gpio_test_infinite.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "CMSDK_CM0.h" 3 | 4 | #define PIN_LED (0) 5 | #define small_delay __ISB 6 | 7 | 8 | void medium_delay() { 9 | for(uint32_t i=0;i<10;i++) { 10 | small_delay(); 11 | } 12 | 13 | } 14 | 15 | void long_delay() { 16 | for(uint32_t i=0;i<200000;i++) { 17 | medium_delay(); 18 | } 19 | 20 | } 21 | 22 | 23 | 24 | int main (void) 25 | { 26 | CMSDK_GPIO0->OUTENABLESET = 1< DATAOUT = 0< DATAOUT = 1<trace (tfp, 99); 21 | tfp->open ("cmsdk_mcu.vcd"); 22 | // initialize simulation inputs 23 | top->XTAL1 = 1; 24 | top->NRST = 0; 25 | top->nTRST = 0; 26 | top->TDI = 0; 27 | top->SWCLKTCK = 0; 28 | // run simulation for 100 clock periods 29 | for (i=0; i<200000; i++) { 30 | top->NRST = (i > 2); 31 | // dump variables into VCD file and toggle clock 32 | for (clk=0; clk<2; clk++) { 33 | tfp->dump (2*i+clk); 34 | top->XTAL1 = !top->XTAL1; 35 | top->eval (); 36 | } 37 | if (Verilated::gotFinish()) exit(0); 38 | } 39 | tfp->close(); 40 | exit(0); 41 | } 42 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | if [ -z "$PATH" ]; then 10 | PATH=/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2015.3/bin 11 | else 12 | PATH=/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2015.3/bin:$PATH 13 | fi 14 | export PATH 15 | 16 | if [ -z "$LD_LIBRARY_PATH" ]; then 17 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/lib/lin64 18 | else 19 | LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH 20 | fi 21 | export LD_LIBRARY_PATH 22 | 23 | HD_PWD=/home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1 24 | cd "$HD_PWD" 25 | 26 | HD_LOG=runme.log 27 | /bin/touch $HD_LOG 28 | 29 | ISEStep="./ISEWrap.sh" 30 | EAStep() 31 | { 32 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 33 | if [ $? -ne 0 ] 34 | then 35 | exit 36 | fi 37 | } 38 | 39 | EAStep vivado -log arty_mmcm.vds -m64 -mode batch -messageDb vivado.pb -notrace -source arty_mmcm.tcl 40 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2015.3 (lin64) Build 1368829 Mon Sep 28 20:06:39 MDT 2015 4 | // Date : Mon Nov 16 15:47:09 2015 5 | // Host : roba-OptiPlex-7010 running 64-bit Ubuntu 15.04 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.v 8 | // Design : arty_mmcm 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7k70tfbv676-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module arty_mmcm(clk_in, clk_50m, resetn, locked) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_in,clk_50m,resetn,locked" */; 18 | input clk_in; 19 | output clk_50m; 20 | input resetn; 21 | output locked; 22 | endmodule 23 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2015.3 (lin64) Build 1368829 Mon Sep 28 20:06:39 MDT 2015 4 | -- Date : Mon Nov 16 15:47:09 2015 5 | -- Host : roba-OptiPlex-7010 running 64-bit Ubuntu 15.04 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.vhdl 8 | -- Design : arty_mmcm 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7k70tfbv676-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity arty_mmcm is 16 | Port ( 17 | clk_in : in STD_LOGIC; 18 | clk_50m : out STD_LOGIC; 19 | resetn : in STD_LOGIC; 20 | locked : out STD_LOGIC 21 | ); 22 | 23 | end arty_mmcm; 24 | 25 | architecture stub of arty_mmcm is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_in,clk_50m,resetn,locked"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/ip/arty_mmcm/arty_mmcm_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2015.3 (lin64) Build 1368829 Mon Sep 28 20:06:39 MDT 2015 4 | // Date : Mon Nov 16 15:47:09 2015 5 | // Host : roba-OptiPlex-7010 running 64-bit Ubuntu 15.04 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.v 8 | // Design : arty_mmcm 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7k70tfbv676-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module arty_mmcm(clk_in, clk_50m, resetn, locked) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_in,clk_50m,resetn,locked" */; 18 | input clk_in; 19 | output clk_50m; 20 | input resetn; 21 | output locked; 22 | endmodule 23 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/ip/arty_mmcm/arty_mmcm_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2015.3 (lin64) Build 1368829 Mon Sep 28 20:06:39 MDT 2015 4 | -- Date : Mon Nov 16 15:47:09 2015 5 | -- Host : roba-OptiPlex-7010 running 64-bit Ubuntu 15.04 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.vhdl 8 | -- Design : arty_mmcm 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7k70tfbv676-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity arty_mmcm is 16 | Port ( 17 | clk_in : in STD_LOGIC; 18 | clk_50m : out STD_LOGIC; 19 | resetn : in STD_LOGIC; 20 | locked : out STD_LOGIC 21 | ); 22 | 23 | end arty_mmcm; 24 | 25 | architecture stub of arty_mmcm is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "clk_in,clk_50m,resetn,locked"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # arty-designstart-cm0 2 | 3 | [![Join the chat at https://gitter.im/rbarzic/arty-cm0-designstart](https://badges.gitter.im/rbarzic/arty-cm0-designstart.svg)](https://gitter.im/rbarzic/arty-cm0-designstart?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) 4 | 5 | 6 | [![Stories in Ready](https://badge.waffle.io/rbarzic/arty-cm0-designstart.svg?label=Ready&title=Ready)](http://waffle.io/rbarzic/arty-cm0-designstart) 7 | [![Stories in Backlog](https://badge.waffle.io/rbarzic/arty-cm0-designstart.svg?label=Backlog&title=Backlog)](http://waffle.io/rbarzic/arty-cm0-designstart) 8 | 9 | This github repository provides the necessary files to use the 10 | DesignStart Cortex-M0 system on a digilentinc ARTY FPGA board. 11 | 12 | **This project does not include the source code of the DesignStart 13 | Cortex-M0. You have to request it directly from ARM.** 14 | 15 | In addition to allow synthesis of the designstart to a Xilinx target, 16 | this project allows also simulations using the simulation tools : 17 | - Icarus iverilog 18 | - Xilinx simulation tools (xvlog/xelab/xsim) 19 | - Verilator 20 | 21 | 22 | 23 | This project uses submodules. To clone it you need to run the following commands : 24 | 25 | ```bash 26 | git clone git@github.com:rbarzic/arty-cm0-designstart.git 27 | cd arty-cm0-designstart 28 | git submodule init 29 | git submodule update 30 | ``` 31 | 32 | This is work in progress so expect some rough edges 33 | 34 | More documentation is available [here](http://rbarzic.github.io/arty-cm0-designstart/) 35 | -------------------------------------------------------------------------------- /synt/yaml2mmi.py: -------------------------------------------------------------------------------- 1 | import yaml 2 | 3 | header=""" 4 | 5 | 6 | 7 | 9 | 10 | 11 | """ 12 | 13 | 14 | footer=""" 15 | 16 | 17 | 18 | 19 | 21 | 22 | 23 | """ 24 | 25 | bitlane=""" 26 | 27 | 28 | 29 | 30 | 31 | """ 32 | 33 | remap = [3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] 34 | 35 | bram = open("bram.yaml", "r") 36 | doc = yaml.load(bram) 37 | 38 | bit_pos = 0 39 | bit_width = 2 40 | output = header 41 | # for bram in doc['bram']: 42 | for i in range(len(doc['bram'])): 43 | 44 | bram = doc['bram'][remap[i]] 45 | data = dict() 46 | # print bram 47 | 48 | data['lsb'] = bit_pos 49 | data['msb'] = bit_pos + bit_width - 1 50 | data['end_address'] = 16383 51 | data['type'] = 'RAMB36E1' 52 | data['placement'] = bram['SITE'].split('_')[1] # remove RAMB36_ in front of the position string 53 | bit_pos += bit_width 54 | output += bitlane.format(**data) 55 | 56 | output += footer 57 | print output 58 | -------------------------------------------------------------------------------- /rtl/bytewrite_ram_1b.v: -------------------------------------------------------------------------------- 1 | // Single-Port BRAM with Byte-wide Write Enable 2 | // Read-First mode 3 | // Single-process description 4 | // Compact description of the write with a generate-for 5 | // statement 6 | // Column width and number of columns easily configurable 7 | // 8 | // bytewrite_ram_1b.v 9 | // 10 | 11 | module bytewrite_ram_1b (clk, we, addr, din, dout); 12 | 13 | parameter SIZE = 1024; 14 | parameter ADDR_WIDTH = 12; 15 | parameter COL_WIDTH = 8; 16 | parameter NB_COL = 4; 17 | 18 | parameter filename = "code.hex"; 19 | 20 | 21 | input clk; 22 | input [NB_COL-1:0] we; 23 | input [ADDR_WIDTH-1:0] addr; 24 | input [NB_COL*COL_WIDTH-1:0] din; 25 | output reg [NB_COL*COL_WIDTH-1:0] dout; 26 | 27 | reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; 28 | 29 | integer _i; 30 | 31 | initial begin 32 | `ifndef IVERILOG 33 | $readmemh(filename,RAM); 34 | `endif 35 | #10; 36 | // Just for debugging readmemh in case it does not work as expected 37 | for(_i=0;_i<6;_i=_i+1) begin 38 | $display("idx : %d data : %x",_i,RAM[_i]); 39 | end 40 | $display("======================"); 41 | end 42 | 43 | 44 | always @(posedge clk) 45 | begin 46 | dout <= RAM[addr]; 47 | end 48 | 49 | generate genvar i; 50 | for (i = 0; i < NB_COL; i = i+1) 51 | begin 52 | always @(posedge clk) 53 | begin 54 | if (we[i]) 55 | RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; 56 | end 57 | end 58 | endgenerate 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 |
28 | 29 | 30 | -------------------------------------------------------------------------------- /site/license/highlight.js/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2006, Ivan Sagalaev 2 | All rights reserved. 3 | Redistribution and use in source and binary forms, with or without 4 | modification, are permitted provided that the following conditions are met: 5 | 6 | * Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | * Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | * Neither the name of highlight.js nor the names of its contributors 12 | may be used to endorse or promote products derived from this software 13 | without specific prior written permission. 14 | 15 | THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY 16 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 | DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY 19 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 22 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | echo "This script was generated under a different operating system." 8 | echo "Please update the PATH variable below, before executing this script" 9 | exit 10 | 11 | var WshShell = new ActiveXObject( "WScript.Shell" ); 12 | var ProcEnv = WshShell.Environment( "Process" ); 13 | var PathVal = ProcEnv("PATH"); 14 | if ( PathVal.length == 0 ) { 15 | PathVal = "/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2015.3/bin;"; 16 | } else { 17 | PathVal = "/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2015.3/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2015.3/bin;" + PathVal; 18 | } 19 | 20 | ProcEnv("PATH") = PathVal; 21 | 22 | var RDScrFP = WScript.ScriptFullName; 23 | var RDScrN = WScript.ScriptName; 24 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 25 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 26 | eval( EAInclude(ISEJScriptLib) ); 27 | 28 | 29 | ISEStep( "vivado", 30 | "-log arty_mmcm.vds -m64 -mode batch -messageDb vivado.pb -notrace -source arty_mmcm.tcl" ); 31 | 32 | 33 | 34 | function EAInclude( EAInclFilename ) { 35 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 36 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 37 | var EAIFContents = EAInclFile.ReadAll(); 38 | EAInclFile.Close(); 39 | return EAIFContents; 40 | } 41 | -------------------------------------------------------------------------------- /software/scripts/cmsdk_cm0.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Linker script to configure memory regions. 25 | * Need modifying for a specific board. 26 | * FLASH.ORIGIN: starting address of flash 27 | * FLASH.LENGTH: length of flash 28 | * RAM.ORIGIN: starting address of RAM bank 0 29 | * RAM.LENGTH: length of RAM bank 0 30 | */ 31 | 32 | INCLUDE "lib-nosys.ld" 33 | 34 | MEMORY 35 | { 36 | FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K */ 37 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFC00 /* 63K */ 38 | /* 64K is available, but reserve some space for */ 39 | /* 1) debug tester communication for debug tests */ 40 | /* 2) DMA data structure for DMA tests */ 41 | } 42 | 43 | INCLUDE "sections.ld" 44 | -------------------------------------------------------------------------------- /synt/bram.yaml: -------------------------------------------------------------------------------- 1 | # set all_rom_blocks [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "*u_ahb_rom*" }] 2 | # puts "# Block ram description" 3 | # Block ram description 4 | # puts "---" 5 | --- 6 | # puts "bram:" 7 | bram: 8 | # foreach block $all_rom_blocks { 9 | # puts "- NAME: [get_property NAME $block]" 10 | # puts " SITE: [get_property SITE $block]" 11 | # puts " READ_WIDTH_A: [get_property READ_WIDTH_A $block]" 12 | # } 13 | - NAME: u_ahb_rom/U_RAM/RAM_reg_0_0 14 | SITE: RAMB36_X0Y11 15 | READ_WIDTH_A: 2 16 | - NAME: u_ahb_rom/U_RAM/RAM_reg_0_1 17 | SITE: RAMB36_X0Y7 18 | READ_WIDTH_A: 2 19 | - NAME: u_ahb_rom/U_RAM/RAM_reg_0_2 20 | SITE: RAMB36_X1Y8 21 | READ_WIDTH_A: 2 22 | - NAME: u_ahb_rom/U_RAM/RAM_reg_0_3 23 | SITE: RAMB36_X1Y10 24 | READ_WIDTH_A: 2 25 | - NAME: u_ahb_rom/U_RAM/RAM_reg_1_0 26 | SITE: RAMB36_X1Y9 27 | READ_WIDTH_A: 2 28 | - NAME: u_ahb_rom/U_RAM/RAM_reg_1_1 29 | SITE: RAMB36_X0Y10 30 | READ_WIDTH_A: 2 31 | - NAME: u_ahb_rom/U_RAM/RAM_reg_1_2 32 | SITE: RAMB36_X0Y8 33 | READ_WIDTH_A: 2 34 | - NAME: u_ahb_rom/U_RAM/RAM_reg_1_3 35 | SITE: RAMB36_X0Y9 36 | READ_WIDTH_A: 2 37 | - NAME: u_ahb_rom/U_RAM/RAM_reg_2_0 38 | SITE: RAMB36_X1Y7 39 | READ_WIDTH_A: 2 40 | - NAME: u_ahb_rom/U_RAM/RAM_reg_2_1 41 | SITE: RAMB36_X2Y15 42 | READ_WIDTH_A: 2 43 | - NAME: u_ahb_rom/U_RAM/RAM_reg_2_2 44 | SITE: RAMB36_X1Y4 45 | READ_WIDTH_A: 2 46 | - NAME: u_ahb_rom/U_RAM/RAM_reg_2_3 47 | SITE: RAMB36_X1Y14 48 | READ_WIDTH_A: 2 49 | - NAME: u_ahb_rom/U_RAM/RAM_reg_3_0 50 | SITE: RAMB36_X0Y13 51 | READ_WIDTH_A: 2 52 | - NAME: u_ahb_rom/U_RAM/RAM_reg_3_1 53 | SITE: RAMB36_X1Y13 54 | READ_WIDTH_A: 2 55 | - NAME: u_ahb_rom/U_RAM/RAM_reg_3_2 56 | SITE: RAMB36_X0Y12 57 | READ_WIDTH_A: 2 58 | - NAME: u_ahb_rom/U_RAM/RAM_reg_3_3 59 | SITE: RAMB36_X1Y12 60 | READ_WIDTH_A: 2 61 | -------------------------------------------------------------------------------- /synt/vivado_utils.tcl: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------ 2 | # reportCriticalPaths 3 | #------------------------------------------------------------------------ 4 | # This function generates a CSV file that provides a summary of the first 5 | # 50 violations for both Setup and Hold analysis. So a maximum number of 6 | # 100 paths are reported. 7 | #------------------------------------------------------------------------ 8 | proc reportCriticalPaths { fileName } { 9 | # Open the specified output file in write mode 10 | set FH [open $fileName w] 11 | # Write the current date and CSV format to a file header 12 | puts $FH "#\n# File created on [clock format [clock seconds]]\n#\n" 13 | puts $FH "Startpoint,Endpoint,DelayType,Slack,#Levels,#LUTs" 14 | # Iterate through both Min and Max delay types 15 | foreach delayType {max min} { 16 | # Collect details from the 50 worst timing paths for the current analysis 17 | # (max = setup/recovery, min = hold/removal) 18 | # The $path variable contains a Timing Path object. 19 | foreach path [get_timing_paths -delay_type $delayType -max_paths 50 -nworst 1] { 20 | # Get the LUT cells of the timing paths 21 | set luts [get_cells -filter {REF_NAME =~ LUT*} -of_object $path] 22 | # Get the startpoint of the Timing Path object 23 | set startpoint [get_property STARTPOINT_PIN $path] 24 | # Get the endpoint of the Timing Path object 25 | set endpoint [get_property ENDPOINT_PIN $path] 26 | # Get the slack on the Timing Path object 27 | set slack [get_property SLACK $path] 28 | # Get the number of logic levels between startpoint and endpoint 29 | set levels [get_property LOGIC_LEVELS $path] 30 | # Save the collected path details to the CSV file 31 | puts $FH "$startpoint,$endpoint,$delayType,$slack,$levels,[llength $luts]" 32 | } 33 | } 34 | # Close the output file 35 | close $FH 36 | puts "CSV file $fileName has been created.\n" 37 | return 0 38 | }; # End PROC 39 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/ISEWrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # ISEWrap.sh: Vivado Runs Script for UNIX 6 | # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | HD_LOG=$1 10 | shift 11 | 12 | # CHECK for a STOP FILE 13 | if [ -f .stop.rst ] 14 | then 15 | echo "" >> $HD_LOG 16 | echo "*** Halting run - EA reset detected ***" >> $HD_LOG 17 | echo "" >> $HD_LOG 18 | exit 1 19 | fi 20 | 21 | ISE_STEP=$1 22 | shift 23 | 24 | # WRITE STEP HEADER to LOG 25 | echo "" >> $HD_LOG 26 | echo "*** Running $ISE_STEP" >> $HD_LOG 27 | echo " with args $@" >> $HD_LOG 28 | echo "" >> $HD_LOG 29 | 30 | # LAUNCH! 31 | $ISE_STEP "$@" >> $HD_LOG 2>&1 & 32 | 33 | # BEGIN file creation 34 | ISE_PID=$! 35 | if [ X != X$HOSTNAME ] 36 | then 37 | ISE_HOST=$HOSTNAME #bash 38 | else 39 | ISE_HOST=$HOST #csh 40 | fi 41 | ISE_USER=$USER 42 | ISE_BEGINFILE=.$ISE_STEP.begin.rst 43 | /bin/touch $ISE_BEGINFILE 44 | echo "" >> $ISE_BEGINFILE 45 | echo "" >> $ISE_BEGINFILE 46 | echo " " >> $ISE_BEGINFILE 47 | echo " " >> $ISE_BEGINFILE 48 | echo "" >> $ISE_BEGINFILE 49 | 50 | # WAIT for ISEStep to finish 51 | wait $ISE_PID 52 | 53 | # END/ERROR file creation 54 | RETVAL=$? 55 | if [ $RETVAL -eq 0 ] 56 | then 57 | /bin/touch .$ISE_STEP.end.rst 58 | else 59 | /bin/touch .$ISE_STEP.error.rst 60 | fi 61 | 62 | exit $RETVAL 63 | -------------------------------------------------------------------------------- /common/arty.py: -------------------------------------------------------------------------------- 1 | import arty_cm0 2 | import iverilog 3 | import xilinx 4 | import argparse 5 | 6 | 7 | 8 | def get_args(): 9 | """ 10 | Get command line arguments 11 | """ 12 | 13 | parser = argparse.ArgumentParser(description=""" 14 | Put description of application here 15 | """) 16 | parser.add_argument('--iverilog', action='store', dest='iverilog', 17 | help='iverilog file list', default="") 18 | 19 | parser.add_argument('--vivado_sim', action='store', dest='vivado_sim', 20 | help='Vivado simulator file list', default="") 21 | 22 | parser.add_argument('--vivado_synt', action='store', dest='vivado_synt', 23 | help='Vivado synthesis file list (as tcl file)', 24 | default="") 25 | 26 | parser.add_argument('--topdir', action='store', dest='topdir', 27 | help='Top directory for the project', 28 | default="") 29 | 30 | parser.add_argument('--designstart', action='store', dest='designstart', 31 | help='Top directory for the ARM DesignStart forlder', 32 | default="") 33 | 34 | 35 | parser.add_argument('--version', action='version', version='%(prog)s 0.1') 36 | 37 | return parser.parse_args() 38 | 39 | 40 | 41 | args = get_args() 42 | 43 | l, d = arty_cm0.arty_cm0() 44 | 45 | context = dict() 46 | 47 | context['top'] = args.topdir 48 | context['top_ds'] = args.designstart 49 | 50 | 51 | if args.iverilog != "": 52 | print "-I- iverilog generation""" 53 | txt = iverilog.get_iverilog_file_list(l, d, context) 54 | with open(args.iverilog,'w') as f: 55 | f.write(txt) 56 | 57 | if args.vivado_sim != "": 58 | print "-I- Vivado/Sim generation""" 59 | txt = xilinx.get_xvlog_file_list(l, d, context) 60 | with open(args.vivado_sim,'w') as f: 61 | f.write(txt) 62 | 63 | if args.vivado_synt != "": 64 | print "Vivado/Sim generation""" 65 | -------------------------------------------------------------------------------- /verilator_sim/arty_mmcm.v: -------------------------------------------------------------------------------- 1 | //****************************************************************************/ 2 | // Arty CM0 "DesignStart" 3 | // RTL IMPLEMENTATION, Synchronous Version 4 | // 5 | // Copyright (C) yyyy Ronan Barzic - rbarzic@gmail.com 6 | // Date : Tue Nov 17 16:37:55 2015 7 | // 8 | // This program is free software; you can redistribute it and/or 9 | // modify it under the terms of the GNU General Public License 10 | // as published by the Free Software Foundation; either version 2 11 | // of the License, or (at your option) any later version. 12 | // 13 | // This program is distributed in the hope that it will be useful, 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | // GNU General Public License for more details. 17 | // 18 | // You should have received a copy of the GNU General Public License 19 | // along with this program; if not, write to the Free Software 20 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA. 21 | // 22 | // 23 | // Filename : arty_mmcm_sim.v 24 | // 25 | // Description : A behavioural model from the MMCM (Xilinx) clock component 26 | // 27 | // 28 | // 29 | //****************************************************************************/ 30 | 31 | 32 | module arty_mmcm (/*AUTOARG*/ 33 | // Outputs 34 | clk_50m, locked, 35 | // Inputs 36 | clk_in, resetn 37 | ); 38 | 39 | 40 | input clk_in; 41 | output clk_50m; 42 | input resetn; 43 | output locked; 44 | 45 | /*AUTOINPUT*/ 46 | /*AUTOOUTPUT*/ 47 | 48 | /*AUTOREG*/ 49 | // Beginning of automatic regs (for this module's undeclared outputs) 50 | reg clk_50m; 51 | reg locked; 52 | // End of automatics 53 | /*AUTOWIRE*/ 54 | 55 | assign locked = resetn; 56 | assign clk_50m = clk_in; 57 | 58 | 59 | 60 | endmodule // arty_mmcm_sim 61 | /* 62 | Local Variables: 63 | verilog-library-directories:( 64 | "." 65 | ) 66 | End: 67 | */ 68 | -------------------------------------------------------------------------------- /rtl/bytewrite_ram_32bits.v: -------------------------------------------------------------------------------- 1 | // Single-Port BRAM with Byte-wide Write Enable 2 | // Read-First mode 3 | // Single-process description 4 | // Compact description of the write with a generate-for 5 | // statement 6 | // Column width and number of columns easily configurable 7 | // 8 | // bytewrite_ram_32bits.v 9 | // 10 | 11 | module bytewrite_ram_32bits (clk, we, addr, din, dout); 12 | 13 | parameter SIZE = 1024; 14 | parameter ADDR_WIDTH = 12; 15 | 16 | parameter filename = "code.hex"; 17 | 18 | localparam COL_WIDTH = 8; 19 | localparam NB_COL = 4; 20 | 21 | 22 | 23 | 24 | input clk; 25 | input [NB_COL-1:0] we; 26 | input [ADDR_WIDTH-1:0] addr; 27 | input [NB_COL*COL_WIDTH-1:0] din; 28 | output reg [NB_COL*COL_WIDTH-1:0] dout; 29 | 30 | reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; 31 | 32 | integer _i; 33 | 34 | initial begin 35 | `ifndef IVERILOG 36 | $readmemh(filename,RAM); 37 | `endif 38 | #10; 39 | // Just for debugging readmemh in case it does not work as expected 40 | for(_i=0;_i<6;_i=_i+1) begin 41 | $display("idx : %d data : %x",_i,RAM[_i]); 42 | end 43 | $display("======================"); 44 | end 45 | 46 | 47 | always @(posedge clk) 48 | begin 49 | dout <= RAM[addr]; 50 | end 51 | 52 | // Remove the original generate statement to ease Xilinx memory bitstream patching 53 | always @(posedge clk) begin 54 | if (we[0]) 55 | RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH]; 56 | end 57 | 58 | 59 | always @(posedge clk) begin 60 | if (we[1]) 61 | RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH]; 62 | end 63 | 64 | always @(posedge clk) begin 65 | if (we[2]) 66 | RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH]; 67 | end 68 | 69 | 70 | always @(posedge clk) begin 71 | if (we[3]) 72 | RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH]; 73 | end 74 | 75 | 76 | 77 | 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /common/file_list.py: -------------------------------------------------------------------------------- 1 | # functions to help building list of files needed by the various tools 2 | 3 | 4 | def get_file_list(l, context, target): 5 | """ 6 | Return a file list depending of the target, and update pathes 7 | depending of context parameter 8 | 9 | @param l: the definition for all the files/directory used by the project 10 | @type l: list of dictionary 11 | @param context: define the pathes for the files 12 | @type context: string 13 | @param target: for which target we want the file/directory list 14 | @type target: string 15 | @return: list of file matching the context 16 | @rtype: list of string 17 | """ 18 | result = list() 19 | for f in l: 20 | filename = f['file'] 21 | f_targets = f['targets'] 22 | list_of_file_targets = set(f_targets.split(',')) 23 | list_of_wanted_targets = set(target.split(',')) 24 | if set.intersection(list_of_file_targets, list_of_wanted_targets): # noqa 25 | # if target in list_of_target: 26 | result.append(filename.format(**context)) 27 | return result 28 | 29 | 30 | def get_dir_list(ll, context, target): 31 | """ 32 | Return a directory list depending of the target, and update pathes 33 | depending of context parameter 34 | 35 | @param l: the definition for all the directories used by the project 36 | @type l: list of dictionary 37 | @param context: define the pathes for the files 38 | @type context: string 39 | @param target: for which target we want the directory list 40 | @type target: string 41 | @return: list of file matching the context 42 | @rtype: list of string 43 | """ 44 | result = list() 45 | for dd in ll: 46 | dirname = dd['dir'] 47 | d_targets = dd['targets'] 48 | # print ">>>>>>" + dirname 49 | list_of_dir_targets = set(d_targets.split (',')) 50 | list_of_wanted_targets = set(target.split (',')) 51 | 52 | if set.intersection(list_of_dir_targets, list_of_wanted_targets) is not None: # noqa 53 | result.append(dirname.format(**context)) 54 | return result 55 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/project.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:30:00:00 3 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 4 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 5 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:707270726f6a656374:66616c7365:00:00 6 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e666967706172746974696f6e636f756e74:30:00:00 7 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e6669676d6f64756c65636f756e74:30:00:00 8 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:686470726f6a656374:66616c7365:00:00 9 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:706172746974696f6e636f756e74:30:00:00 10 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 11 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 12 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 13 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 14 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:32:00:00 15 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:32:00:00 16 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 17 | 70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76355f325f305c617274795f6d6d636d:636f72655f636f6e7461696e6572:66616c7365:00:00 18 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3764313337376262343030653435313738613865343535383461646531356665:506172656e742050412070726f6a656374204944:00 19 | eof:3910697707 20 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 39 | 40 | 41 | 42 | Vivado Synthesis Defaults 43 | 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xci 5 | # IP: The module: 'arty_mmcm' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_board.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'arty_mmcm'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells inst] 10 | 11 | # XDC: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xdc 12 | # XDC: The top module name and the constraint reference have the same name: 'arty_mmcm'. Do not add the DONT_TOUCH constraint. 13 | #dup# set_property DONT_TOUCH TRUE [get_cells inst] 14 | 15 | # XDC: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_ooc.xdc 16 | # XDC: The top module name and the constraint reference have the same name: 'arty_mmcm'. Do not add the DONT_TOUCH constraint. 17 | #dup# set_property DONT_TOUCH TRUE [get_cells inst] 18 | 19 | # IP: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xci 20 | # IP: The module: 'arty_mmcm' is the root of the design. Do not add the DONT_TOUCH constraint. 21 | 22 | # XDC: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_board.xdc 23 | # XDC: The top module name and the constraint reference have the same name: 'arty_mmcm'. Do not add the DONT_TOUCH constraint. 24 | #dup# set_property DONT_TOUCH TRUE [get_cells inst] 25 | 26 | # XDC: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xdc 27 | # XDC: The top module name and the constraint reference have the same name: 'arty_mmcm'. Do not add the DONT_TOUCH constraint. 28 | #dup# set_property DONT_TOUCH TRUE [get_cells inst] 29 | 30 | # XDC: /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_ooc.xdc 31 | # XDC: The top module name and the constraint reference have the same name: 'arty_mmcm'. Do not add the DONT_TOUCH constraint. 32 | #dup# set_property DONT_TOUCH TRUE [get_cells inst] 33 | -------------------------------------------------------------------------------- /site/css/highlight.css: -------------------------------------------------------------------------------- 1 | /* 2 | This is the GitHub theme for highlight.js 3 | 4 | github.com style (c) Vasily Polovnyov 5 | 6 | */ 7 | 8 | .hljs { 9 | display: block; 10 | overflow-x: auto; 11 | padding: 0.5em; 12 | color: #333; 13 | -webkit-text-size-adjust: none; 14 | } 15 | 16 | .hljs-comment, 17 | .diff .hljs-header, 18 | .hljs-javadoc { 19 | color: #998; 20 | font-style: italic; 21 | } 22 | 23 | .hljs-keyword, 24 | .css .rule .hljs-keyword, 25 | .hljs-winutils, 26 | .nginx .hljs-title, 27 | .hljs-subst, 28 | .hljs-request, 29 | .hljs-status { 30 | color: #333; 31 | font-weight: bold; 32 | } 33 | 34 | .hljs-number, 35 | .hljs-hexcolor, 36 | .ruby .hljs-constant { 37 | color: #008080; 38 | } 39 | 40 | .hljs-string, 41 | .hljs-tag .hljs-value, 42 | .hljs-phpdoc, 43 | .hljs-dartdoc, 44 | .tex .hljs-formula { 45 | color: #d14; 46 | } 47 | 48 | .hljs-title, 49 | .hljs-id, 50 | .scss .hljs-preprocessor { 51 | color: #900; 52 | font-weight: bold; 53 | } 54 | 55 | .hljs-list .hljs-keyword, 56 | .hljs-subst { 57 | font-weight: normal; 58 | } 59 | 60 | .hljs-class .hljs-title, 61 | .hljs-type, 62 | .vhdl .hljs-literal, 63 | .tex .hljs-command { 64 | color: #458; 65 | font-weight: bold; 66 | } 67 | 68 | .hljs-tag, 69 | .hljs-tag .hljs-title, 70 | .hljs-rule .hljs-property, 71 | .django .hljs-tag .hljs-keyword { 72 | color: #000080; 73 | font-weight: normal; 74 | } 75 | 76 | .hljs-attribute, 77 | .hljs-variable, 78 | .lisp .hljs-body, 79 | .hljs-name { 80 | color: #008080; 81 | } 82 | 83 | .hljs-regexp { 84 | color: #009926; 85 | } 86 | 87 | .hljs-symbol, 88 | .ruby .hljs-symbol .hljs-string, 89 | .lisp .hljs-keyword, 90 | .clojure .hljs-keyword, 91 | .scheme .hljs-keyword, 92 | .tex .hljs-special, 93 | .hljs-prompt { 94 | color: #990073; 95 | } 96 | 97 | .hljs-built_in { 98 | color: #0086b3; 99 | } 100 | 101 | .hljs-preprocessor, 102 | .hljs-pragma, 103 | .hljs-pi, 104 | .hljs-doctype, 105 | .hljs-shebang, 106 | .hljs-cdata { 107 | color: #999; 108 | font-weight: bold; 109 | } 110 | 111 | .hljs-deletion { 112 | background: #fdd; 113 | } 114 | 115 | .hljs-addition { 116 | background: #dfd; 117 | } 118 | 119 | .diff .hljs-change { 120 | background: #0086b3; 121 | } 122 | 123 | .hljs-chunk { 124 | color: #aaa; 125 | } 126 | -------------------------------------------------------------------------------- /sim/Makefile: -------------------------------------------------------------------------------- 1 | TEST?=hello 2 | 3 | comp: 4 | iverilog -DIVERILOG -DVCD_DUMP -o tb -c iverilog_file_list.txt 5 | 6 | comp_novcd: 7 | iverilog -DIVERILOG -o tb -c iverilog_file_list.txt 8 | 9 | 10 | run: 11 | vvp tb +program_memory=$(TEST).vmem 12 | 13 | wave: 14 | gtkwave tb_cmsdk_mcu.vcd & 15 | 16 | 17 | help: 18 | @echo "Targets:" 19 | @echo " comp : Compile the design with icarus Verilog (using files listed in iverilog_file_list.txt)" 20 | @echo " run : Run the simulation, generating a vcd file" 21 | @echo " wave : View the vcd file using gtkwave vcd viewer" 22 | 23 | 24 | 25 | 26 | # For flymake on-the-fly code checking 27 | check-syntax: 28 | iverilog -t null -o tb -c iverilog_file_list.txt 29 | 30 | 31 | 32 | # Xilinx : 33 | # xvlog -f xilinx_vlist.txt 34 | # xelab cmsdk_mcu -relax (because of timescale) 35 | # see ug900 36 | #Step2: Elaborating and Creating a Snapshot 37 | #After analysis, elaborate the design and create a snapshot for simulation using the xelab 38 | #command: 39 | #xelab -debug typicalx 40 | #IMPORTANT: You can provide multiple top-level design unit names with xelab. To use the Vivado 41 | #simulator workspace for purposes similar to those used during launch_simulation, you must set 42 | #debug level to typical. 43 | #Step 3: Running Simulation 44 | #After successful completion of the xelab phase, the Vivado simulator creates a snapshot 45 | #used for running simulation. 46 | #To invoke the Vivado simulator workspace, use the following command: 47 | #xsim 48 | # -gui 49 | #To open the wave config file: 50 | #xsim -view -gui 51 | #You can provide multiple wcfg files using multiple -view flags. For example: 52 | #xsim 53 | # -view -view 54 | 55 | xcomp: 56 | xvlog --define NO_TIME_SCALE -f vivado_file_list.txt $(XILINX_VIVADO)/data/verilog/src/glbl.v 57 | 58 | xelab: 59 | xelab -L unisims_ver tb_cmsdk_mcu glbl --relax --debug all 60 | 61 | xsim: 62 | xsim work.tb_cmsdk_mcu#work.glbl -runall 63 | 64 | 65 | # hexdump -v -e '"@%08.8_ax " 1/1 "%02x " "\n"' ../../cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/hello.bin > hello.vmem 66 | 67 | # "OK" format for Xilinx simulation tool 68 | vmem32: 69 | hexdump -v -e ' 1/4 "%08x " "\n"' ../../cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/hello.bin > hello.vmem32 70 | 71 | 72 | 73 | # SDF 74 | # xvlog --define NO_TIME_SCALE --define SDF_SIM -f vivado_sdf_file_list.txt /opt/Xilinx/Vivado/2015.3/data/verilog/src/glbl.v 75 | # xelab -L unisims_ver tb_cmsdk_mcu glbl --relax --debug all --sdftyp cmsdk_mcu=../synt/chip_layout.sdf 76 | # 77 | -------------------------------------------------------------------------------- /rtl/arty_mmcm_sim.v: -------------------------------------------------------------------------------- 1 | //****************************************************************************/ 2 | // Arty CM0 "DesignStart" 3 | // RTL IMPLEMENTATION, Synchronous Version 4 | // 5 | // Copyright (C) yyyy Ronan Barzic - rbarzic@gmail.com 6 | // Date : Tue Nov 17 16:37:55 2015 7 | // 8 | // This program is free software; you can redistribute it and/or 9 | // modify it under the terms of the GNU General Public License 10 | // as published by the Free Software Foundation; either version 2 11 | // of the License, or (at your option) any later version. 12 | // 13 | // This program is distributed in the hope that it will be useful, 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | // GNU General Public License for more details. 17 | // 18 | // You should have received a copy of the GNU General Public License 19 | // along with this program; if not, write to the Free Software 20 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA. 21 | // 22 | // 23 | // Filename : arty_mmcm_sim.v 24 | // 25 | // Description : A behavioural model from the MMCM (Xilinx) clock component 26 | // 27 | // 28 | // 29 | //****************************************************************************/ 30 | 31 | 32 | module arty_mmcm (/*AUTOARG*/ 33 | // Outputs 34 | clk_50m, locked, 35 | // Inputs 36 | clk_in, resetn 37 | ); 38 | 39 | 40 | input clk_in; 41 | output clk_50m; 42 | input resetn; 43 | output locked; 44 | 45 | /*AUTOINPUT*/ 46 | /*AUTOOUTPUT*/ 47 | 48 | /*AUTOREG*/ 49 | // Beginning of automatic regs (for this module's undeclared outputs) 50 | reg clk_50m; 51 | reg locked; 52 | // End of automatics 53 | /*AUTOWIRE*/ 54 | 55 | always @(posedge clk_in or negedge resetn) begin 56 | if(resetn == 1'b0) begin 57 | /*AUTORESET*/ 58 | // Beginning of autoreset for uninitialized flops 59 | clk_50m <= 1'h0; 60 | // End of automatics 61 | end 62 | else begin 63 | clk_50m <= !clk_50m; 64 | end 65 | end 66 | 67 | always @(posedge clk_50m or negedge resetn) begin 68 | if(resetn == 1'b0) begin 69 | /*AUTORESET*/ 70 | // Beginning of autoreset for uninitialized flops 71 | locked = 1'h0; 72 | // End of automatics 73 | end 74 | else begin 75 | locked <= 1'b1; 76 | 77 | end 78 | end 79 | 80 | 81 | 82 | endmodule // arty_mmcm_sim 83 | /* 84 | Local Variables: 85 | verilog-library-directories:( 86 | "." 87 | ) 88 | End: 89 | */ 90 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/ies/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Mon Nov 16 15:47:13 CET 2015 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./arty_mmcm.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes 'setup' function the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched. This generated data can be removed by specifying the '-reset_run' 29 | switch to the './arty_mmcm.sh' script. 30 | 31 | ./arty_mmcm.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files 34 | and library directories, use the -noclean_files switch. 35 | 36 | ./arty_mmcm.sh -noclean_files 37 | 38 | For more information on the script, please type './arty_mmcm.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional files that can be used for 43 | fetching the design files information or for integrating with external custom 44 | scripts. 45 | 46 | Name : filelist.f 47 | Purpose: This file contains a flat list of design files based on the compile 48 | order when export_simulation was executed. By default, the source file 49 | paths are set relative to the current directory. If -absolute_path 50 | switch was specified with export_simulation, then the file paths will 51 | be set absolute. 52 | 53 | Name : file_info.txt 54 | Purpose: This file contains detail design file information based on the compile 55 | order when export_simulation was executed. The file contains information 56 | about the file type, name, whether belongs to IP, associated library and 57 | the file path. 58 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/vcs/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Mon Nov 16 15:47:13 CET 2015 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./arty_mmcm.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes 'setup' function the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched. This generated data can be removed by specifying the '-reset_run' 29 | switch to the './arty_mmcm.sh' script. 30 | 31 | ./arty_mmcm.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files 34 | and library directories, use the -noclean_files switch. 35 | 36 | ./arty_mmcm.sh -noclean_files 37 | 38 | For more information on the script, please type './arty_mmcm.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional files that can be used for 43 | fetching the design files information or for integrating with external custom 44 | scripts. 45 | 46 | Name : filelist.f 47 | Purpose: This file contains a flat list of design files based on the compile 48 | order when export_simulation was executed. By default, the source file 49 | paths are set relative to the current directory. If -absolute_path 50 | switch was specified with export_simulation, then the file paths will 51 | be set absolute. 52 | 53 | Name : file_info.txt 54 | Purpose: This file contains detail design file information based on the compile 55 | order when export_simulation was executed. The file contains information 56 | about the file type, name, whether belongs to IP, associated library and 57 | the file path. 58 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Mon Nov 16 15:47:13 CET 2015 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./arty_mmcm.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes 'setup' function the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched. This generated data can be removed by specifying the '-reset_run' 29 | switch to the './arty_mmcm.sh' script. 30 | 31 | ./arty_mmcm.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files 34 | and library directories, use the -noclean_files switch. 35 | 36 | ./arty_mmcm.sh -noclean_files 37 | 38 | For more information on the script, please type './arty_mmcm.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional files that can be used for 43 | fetching the design files information or for integrating with external custom 44 | scripts. 45 | 46 | Name : filelist.f 47 | Purpose: This file contains a flat list of design files based on the compile 48 | order when export_simulation was executed. By default, the source file 49 | paths are set relative to the current directory. If -absolute_path 50 | switch was specified with export_simulation, then the file paths will 51 | be set absolute. 52 | 53 | Name : file_info.txt 54 | Purpose: This file contains detail design file information based on the compile 55 | order when export_simulation was executed. The file contains information 56 | about the file type, name, whether belongs to IP, associated library and 57 | the file path. 58 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Mon Nov 16 15:47:13 CET 2015 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./arty_mmcm.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes 'setup' function the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched. This generated data can be removed by specifying the '-reset_run' 29 | switch to the './arty_mmcm.sh' script. 30 | 31 | ./arty_mmcm.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files 34 | and library directories, use the -noclean_files switch. 35 | 36 | ./arty_mmcm.sh -noclean_files 37 | 38 | For more information on the script, please type './arty_mmcm.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional files that can be used for 43 | fetching the design files information or for integrating with external custom 44 | scripts. 45 | 46 | Name : filelist.f 47 | Purpose: This file contains a flat list of design files based on the compile 48 | order when export_simulation was executed. By default, the source file 49 | paths are set relative to the current directory. If -absolute_path 50 | switch was specified with export_simulation, then the file paths will 51 | be set absolute. 52 | 53 | Name : file_info.txt 54 | Purpose: This file contains detail design file information based on the compile 55 | order when export_simulation was executed. The file contains information 56 | about the file type, name, whether belongs to IP, associated library and 57 | the file path. 58 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required to 5 | # run the exported script and information about the source files. 6 | # 7 | # Generated by export_simulation on Mon Nov 16 15:47:13 CET 2015 8 | # 9 | ################################################################################ 10 | 11 | 1. How to run the script:- 12 | 13 | From the shell prompt in the current directory, issue the following command:- 14 | 15 | ./arty_mmcm.sh 16 | 17 | This command will launch the 'compile', 'elaborate' and 'simulate' functions 18 | implemented in the script file for the 3-step flow. These functions are called 19 | from the main 'run' function in the script file. 20 | 21 | The 'run' function first executes 'setup' function the purpose of which is to 22 | create simulator specific setup files, create design library mappings and library 23 | directories and copy 'glbl.v' from the Vivado software install location into the 24 | current directory. 25 | 26 | The 'setup' function is also used for removing the simulator generated data in 27 | order to reset the current directory to the original state when export_simulation 28 | was launched. This generated data can be removed by specifying the '-reset_run' 29 | switch to the './arty_mmcm.sh' script. 30 | 31 | ./arty_mmcm.sh -reset_run 32 | 33 | To keep the generated data from the previous run but regenerate the setup files 34 | and library directories, use the -noclean_files switch. 35 | 36 | ./arty_mmcm.sh -noclean_files 37 | 38 | For more information on the script, please type './arty_mmcm.sh -help'. 39 | 40 | 2. Additional design information files:- 41 | 42 | export_simulation generates following additional files that can be used for 43 | fetching the design files information or for integrating with external custom 44 | scripts. 45 | 46 | Name : filelist.f 47 | Purpose: This file contains a flat list of design files based on the compile 48 | order when export_simulation was executed. By default, the source file 49 | paths are set relative to the current directory. If -absolute_path 50 | switch was specified with export_simulation, then the file paths will 51 | be set absolute. 52 | 53 | Name : file_info.txt 54 | Purpose: This file contains detail design file information based on the compile 55 | order when export_simulation was executed. The file contains information 56 | about the file type, name, whether belongs to IP, associated library and 57 | the file path. 58 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm_ooc.xdc: -------------------------------------------------------------------------------- 1 | # file: arty_mmcm_ooc.xdc 2 | # 3 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | ################# 51 | #DEFAULT CLOCK CONSTRAINTS 52 | 53 | ############################################################ 54 | # Clock Period Constraints # 55 | ############################################################ 56 | #create_clock -period 10.0 [get_ports clk_in] 57 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm.xdc: -------------------------------------------------------------------------------- 1 | # file: arty_mmcm.xdc 2 | # 3 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system. If required 52 | # commented constraints can be used in the top level xdc 53 | #---------------------------------------------------------------- 54 | # Connect to input port when clock capable pin is selected for input 55 | create_clock -period 10.0 [get_ports clk_in] 56 | set_input_jitter [get_clocks -of_objects [get_ports clk_in]] 0.1 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /site/css/base.css: -------------------------------------------------------------------------------- 1 | body { 2 | padding-top: 70px; 3 | } 4 | 5 | h1[id]:before, h2[id]:before, h3[id]:before, h4[id]:before, h5[id]:before, h6[id]:before { 6 | content: ""; 7 | display: block; 8 | margin-top: -75px; 9 | height: 75px; 10 | } 11 | 12 | ul.nav li.main { 13 | font-weight: bold; 14 | } 15 | 16 | div.col-md-3 { 17 | padding-left: 0; 18 | } 19 | 20 | div.col-md-9 { 21 | padding-bottom: 100px; 22 | } 23 | 24 | div.source-links { 25 | float: right; 26 | } 27 | 28 | /* 29 | * Side navigation 30 | * 31 | * Scrollspy and affixed enhanced navigation to highlight sections and secondary 32 | * sections of docs content. 33 | */ 34 | 35 | /* By default it's not affixed in mobile views, so undo that */ 36 | .bs-sidebar.affix { 37 | position: static; 38 | } 39 | 40 | .bs-sidebar.well { 41 | padding: 0; 42 | } 43 | 44 | /* First level of nav */ 45 | .bs-sidenav { 46 | margin-top: 30px; 47 | margin-bottom: 30px; 48 | padding-top: 10px; 49 | padding-bottom: 10px; 50 | border-radius: 5px; 51 | } 52 | 53 | /* All levels of nav */ 54 | .bs-sidebar .nav > li > a { 55 | display: block; 56 | padding: 5px 20px; 57 | z-index: 1; 58 | } 59 | .bs-sidebar .nav > li > a:hover, 60 | .bs-sidebar .nav > li > a:focus { 61 | text-decoration: none; 62 | border-right: 1px solid; 63 | } 64 | .bs-sidebar .nav > .active > a, 65 | .bs-sidebar .nav > .active:hover > a, 66 | .bs-sidebar .nav > .active:focus > a { 67 | font-weight: bold; 68 | background-color: transparent; 69 | border-right: 1px solid; 70 | } 71 | 72 | /* Nav: second level (shown on .active) */ 73 | .bs-sidebar .nav .nav { 74 | display: none; /* Hide by default, but at >768px, show it */ 75 | margin-bottom: 8px; 76 | } 77 | .bs-sidebar .nav .nav > li > a { 78 | padding-top: 3px; 79 | padding-bottom: 3px; 80 | padding-left: 30px; 81 | font-size: 90%; 82 | } 83 | 84 | /* Show and affix the side nav when space allows it */ 85 | @media (min-width: 992px) { 86 | .bs-sidebar .nav > .active > ul { 87 | display: block; 88 | } 89 | /* Widen the fixed sidebar */ 90 | .bs-sidebar.affix, 91 | .bs-sidebar.affix-bottom { 92 | width: 213px; 93 | } 94 | .bs-sidebar.affix { 95 | position: fixed; /* Undo the static from mobile first approach */ 96 | top: 80px; 97 | } 98 | .bs-sidebar.affix-bottom { 99 | position: absolute; /* Undo the static from mobile first approach */ 100 | } 101 | .bs-sidebar.affix-bottom .bs-sidenav, 102 | .bs-sidebar.affix .bs-sidenav { 103 | margin-top: 0; 104 | margin-bottom: 0; 105 | } 106 | } 107 | @media (min-width: 1200px) { 108 | /* Widen the fixed sidebar again */ 109 | .bs-sidebar.affix-bottom, 110 | .bs-sidebar.affix { 111 | width: 263px; 112 | } 113 | } 114 | -------------------------------------------------------------------------------- /site/mkdocs/js/search.js: -------------------------------------------------------------------------------- 1 | require([ 2 | base_url + '/mkdocs/js/mustache.min.js', 3 | base_url + '/mkdocs/js/lunr-0.5.7.min.js', 4 | 'text!search-results-template.mustache', 5 | 'text!../search_index.json', 6 | ], function (Mustache, lunr, results_template, data) { 7 | "use strict"; 8 | 9 | function getSearchTerm() 10 | { 11 | var sPageURL = window.location.search.substring(1); 12 | var sURLVariables = sPageURL.split('&'); 13 | for (var i = 0; i < sURLVariables.length; i++) 14 | { 15 | var sParameterName = sURLVariables[i].split('='); 16 | if (sParameterName[0] == 'q') 17 | { 18 | return decodeURIComponent(sParameterName[1].replace(/\+/g, '%20')); 19 | } 20 | } 21 | } 22 | 23 | var index = lunr(function () { 24 | this.field('title', {boost: 10}); 25 | this.field('text'); 26 | this.ref('location'); 27 | }); 28 | 29 | data = JSON.parse(data); 30 | var documents = {}; 31 | 32 | for (var i=0; i < data.docs.length; i++){ 33 | var doc = data.docs[i]; 34 | doc.location = base_url + doc.location; 35 | index.add(doc); 36 | documents[doc.location] = doc; 37 | } 38 | 39 | var search = function(){ 40 | 41 | var query = document.getElementById('mkdocs-search-query').value; 42 | var search_results = document.getElementById("mkdocs-search-results"); 43 | while (search_results.firstChild) { 44 | search_results.removeChild(search_results.firstChild); 45 | } 46 | 47 | if(query === ''){ 48 | return; 49 | } 50 | 51 | var results = index.search(query); 52 | 53 | if (results.length > 0){ 54 | for (var i=0; i < results.length; i++){ 55 | var result = results[i]; 56 | doc = documents[result.ref]; 57 | doc.base_url = base_url; 58 | doc.summary = doc.text.substring(0, 200); 59 | var html = Mustache.to_html(results_template, doc); 60 | search_results.insertAdjacentHTML('beforeend', html); 61 | } 62 | } else { 63 | search_results.insertAdjacentHTML('beforeend', "

No results found

"); 64 | } 65 | 66 | if(jQuery){ 67 | /* 68 | * We currently only automatically hide bootstrap models. This 69 | * requires jQuery to work. 70 | */ 71 | jQuery('#mkdocs_search_modal a').click(function(){ 72 | jQuery('#mkdocs_search_modal').modal('hide'); 73 | }) 74 | } 75 | 76 | }; 77 | 78 | var search_input = document.getElementById('mkdocs-search-query'); 79 | 80 | var term = getSearchTerm(); 81 | if (term){ 82 | search_input.value = term; 83 | search(); 84 | } 85 | 86 | search_input.addEventListener("keyup", search); 87 | 88 | }); 89 | -------------------------------------------------------------------------------- /doc/programming.org: -------------------------------------------------------------------------------- 1 | sudo /opt/Xilinx/Vivado/2015.4/bin/hw_server 2 | Ctr-Z then bg 3 | 4 | vivado -mode tcl 5 | 6 | open_hw 7 | connect_hw_server -url localhost:3121 8 | current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*] 9 | open_hw_target 10 | set_property PROGRAM.FILE {./rpt/cpu.bit} [lindex [get_hw_devices] 0] 11 | program_hw_devices [lindex [get_hw_devices] 0] 12 | 13 | 14 | 15 | 16 | * Memory organization 17 | get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "*u_ahb_rom*" } 18 | 19 | Result : 20 | Seems valid for both RAM and ROM 21 | 22 | RAMB36E1 : 16384x2 (x16 -> 64KB) 23 | 24 | | Instance | DIADI connection | 25 | | u_ahb_rom/U_RAM/RAM_reg_0_0 | [1:0] | 26 | | u_ahb_rom/U_RAM/RAM_reg_0_1 | [3:2] | 27 | | u_ahb_rom/U_RAM/RAM_reg_0_2 | | 28 | | u_ahb_rom/U_RAM/RAM_reg_0_3 | | 29 | | | | 30 | | u_ahb_rom/U_RAM/RAM_reg_1_0 | | 31 | | u_ahb_rom/U_RAM/RAM_reg_1_1 | | 32 | | u_ahb_rom/U_RAM/RAM_reg_1_2 | | 33 | | u_ahb_rom/U_RAM/RAM_reg_1_3 | | 34 | | | | 35 | | u_ahb_rom/U_RAM/RAM_reg_2_0 | | 36 | | u_ahb_rom/U_RAM/RAM_reg_2_1 | | 37 | | u_ahb_rom/U_RAM/RAM_reg_2_2 | | 38 | | u_ahb_rom/U_RAM/RAM_reg_2_3 | | 39 | | | | 40 | | u_ahb_rom/U_RAM/RAM_reg_3_0 | | 41 | | u_ahb_rom/U_RAM/RAM_reg_3_1 | | 42 | | u_ahb_rom/U_RAM/RAM_reg_3_2 | | 43 | | u_ahb_rom/U_RAM/RAM_reg_3_3 | [31:30] | 44 | 45 | 46 | get_property SITE [get_cells u_ahb_rom/U_RAM/RAM_reg_0_0] 47 | -> 48 | RAMB36_X2Y5 49 | 50 | 51 | report_property [get_cells u_ahb_rom/U_RAM/RAM_reg_0_0] 52 | 53 | 54 | set all_rom_blocks [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "*u_ahb_rom*" }] 55 | 56 | foreach block $all_rom_blocks { 57 | puts [concat [get_property NAME $block] ":" [get_property SITE $block] ":" [get_property READ_WIDTH_A $block]] 58 | } 59 | 60 | 61 | get_nets -of_objects [get_pins u_ahb_rom/U_RAM/RAM_reg_0_0/DIADI] 62 | 63 | 64 | 65 | Synthesis mapping updatemem debug 66 | RAM_reg_0_0 RAMB36_X2Y5 -> RAMB36_X0Y6 67 | RAM_reg_0_1 RAMB36_X0Y3 -> RAMB36_X1Y3 68 | RAM_reg_0_2 RAMB36_X1Y3 -> RAMB36_X0Y3 69 | RAM_reg_0_3 RAMB36_X0Y6 -> RAMB36_X2Y5 70 | 71 | RAM_reg_1_0 RAMB36_X0Y8 -> RAMB36_X0Y9 72 | RAM_reg_1_1 RAMB36_X0Y5 -> RAMB36_X0Y7 73 | RAM_reg_1_2 RAMB36_X0Y7 -> RAMB36_X0Y5 74 | RAM_reg_1_3 RAMB36_X0Y9 -> RAMB36_X0Y8 75 | 76 | RAM_reg_2_0 RAMB36_X1Y8 -> X0Y10 77 | RAM_reg_2_1 RAMB36_X2Y3 -> X0Y4 78 | RAM_reg_2_2 RAMB36_X0Y4 -> X2Y3 79 | RAM_reg_2_3 RAMB36_X0Y10 -> X1Y8 80 | 81 | Big versus Little does no seem to change anything 82 | 83 | X0Y12 84 | X0Y13 85 | X2Y10 86 | X0Y11 87 | 88 | updatemem --debug -bit rpt/cpu.bit -meminfo test2.mmi -data gpio_test.elf -proc design/cortex -o test.bit | tee debug.txt 89 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/README.txt: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # README.txt: Please read the sections below to understand the steps required 5 | # to simulate the design for a simulator, the directory structure 6 | # and the generated exported files. 7 | # 8 | ################################################################################ 9 | 10 | 1. Simulate Design 11 | 12 | To simulate design, cd to the simulator directory and execute the script. 13 | 14 | For example:- 15 | 16 | % cd questa 17 | % ./top.sh 18 | 19 | The export simulation flow requires the Xilinx pre-compiled simulation library 20 | components for the target simulator. These components are referred using the 21 | '-lib_map_path' switch. If this switch is specified, then the export simulation 22 | will automatically set this library path in the generated script and update, 23 | copy the simulator setup file(s) in the exported directory. 24 | 25 | If '-lib_map_path' is not specified, then the pre-compiled simulation library 26 | information will not be included in the exported scripts and that may cause 27 | simulation errors when running this script. Alternatively, you can provide the 28 | library information using this switch while executing the generated script. 29 | 30 | For example:- 31 | 32 | % ./top.sh -lib_map_path /design/questa/clibs 33 | 34 | Please refer to the generated script header 'Prerequisite' section for more details. 35 | 36 | 2. Directory Structure 37 | 38 | By default, if the -directory switch is not specified, export_simulation will 39 | create the following directory structure:- 40 | 41 | /export_sim/ 42 | 43 | For example, if the current working directory is /tmp/test, export_simulation 44 | will create the following directory path:- 45 | 46 | /tmp/test/export_sim/questa 47 | 48 | If -directory switch is specified, export_simulation will create a simulator 49 | sub-directory under the specified directory path. 50 | 51 | For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' 52 | command will create the following directory:- 53 | 54 | /tmp/test/my_test_area/func_sim/questa 55 | 56 | By default, if -simulator is not specified, export_simulation will create a 57 | simulator sub-directory for each simulator and export the files for each simulator 58 | in this sub-directory respectively. 59 | 60 | IMPORTANT: Please note that the simulation library path must be specified manually 61 | in the generated script for the respective simulator. Please refer to the generated 62 | script header 'Prerequisite' section for more details. 63 | 64 | 3. Exported script and files 65 | 66 | Export simulation will create the driver shell script, setup files and copy the 67 | design sources in the output directory path. 68 | 69 | By default, when the -script_name switch is not specified, export_simulation will 70 | create the following script name:- 71 | 72 | .sh (Unix) 73 | .bat (Windows) 74 | 75 | When exporting the files for an IP using the -of_objects switch, export_simulation 76 | will create the following script name:- 77 | 78 | .sh (Unix) 79 | .bat (Windows) 80 | 81 | Export simulation will create the setup files for the target simulator specified 82 | with the -simulator switch. 83 | 84 | For example, if the target simulator is "ies", export_simulation will create the 85 | 'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' 86 | file. 87 | 88 | -------------------------------------------------------------------------------- /synt/cortexm0.mmi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 112 | 113 | 114 | 115 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b3730746662763637362d31:00:00 3 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 4 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:617274795f6d6d636d:00:00 5 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 6 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 7 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 8 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 9 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 10 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 11 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 12 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 13 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 14 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e6b5f64637073:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 15 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f6c6f61645f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 16 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 17 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 18 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 19 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:6f75745f6f665f636f6e74657874:00:00 20 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 21 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 22 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 23 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 24 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 25 | 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313973:00:00 26 | 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313334382e3737374d42:00:00 27 | 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3430382e3236324d42:00:00 28 | eof:900169135 29 | -------------------------------------------------------------------------------- /rtl/sync_ram_wf_x32.v: -------------------------------------------------------------------------------- 1 | //****************************************************************************/ 2 | // AMBA conponents 3 | // RTL IMPLEMENTATION, Synchronous Version 4 | // 5 | // Copyright (C) yyyy Ronan Barzic - rbarzic@gmail.com 6 | // Date : Mon Nov 9 10:03:03 2015 7 | // 8 | // This program is free software; you can redistribute it and/or 9 | // modify it under the terms of the GNU General Public License 10 | // as published by the Free Software Foundation; either version 2 11 | // of the License, or (at your option) any later version. 12 | // 13 | // This program is distributed in the hope that it will be useful, 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | // GNU General Public License for more details. 17 | // 18 | // You should have received a copy of the GNU General Public License 19 | // along with this program; if not, write to the Free Software 20 | // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA. 21 | // 22 | // 23 | // Filename : sync_ram_wf_x32.v 24 | // 25 | // Description : 32-bit, byte accessible synchronous RAM model, 26 | // write first 27 | // suitable for FPGA synthesis (Xilinx Block RAM) 28 | // Source : ug901-vivado-synthesis-examples.zip 29 | // 30 | //****************************************************************************/ 31 | 32 | 33 | 34 | module sync_ram_wf_x32 (/*AUTOARG*/ 35 | // Outputs 36 | dout, 37 | // Inputs 38 | clk, web, enb, addr, din 39 | ); 40 | parameter ADDR_WIDTH = 10; 41 | 42 | input clk; 43 | input [3:0]web; 44 | input [3:0]enb; 45 | input [9:0] addr; 46 | input [31:0] din; 47 | output [31:0] dout; 48 | reg [31:0] RAM [(2< $(TESTNAME).lst 73 | # Generate binary file 74 | $(GNU_OBJCOPY) -S $(TESTNAME).elf -O binary $(TESTNAME).bin 75 | # Generate hex file 76 | $(GNU_OBJCOPY) -S $(TESTNAME).elf -O verilog $(TESTNAME).hex 77 | # Suitable for Verilog simulator 78 | hexdump -v -e ' 1/4 "%08x " "\n"' $(TESTNAME).bin > $(TESTNAME).vmem32 # Xilinx 79 | hexdump -v -e '"@%08.8_ax " 1/1 "%02x " "\n"' $(TESTNAME).bin > $(TESTNAME).vmem # iverilog 80 | # Note: 81 | # If the version of object copy you are using does not support verilog hex file output, 82 | # you can generate the hex file from binary file using the following command 83 | # od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 84 | 85 | # Binary 86 | 87 | all_bin: $(TESTNAME).bin 88 | # Generate hex file from binary 89 | od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex 90 | 91 | 92 | # Simulation support 93 | 94 | wave: 95 | gtkwave tb_cmsdk_mcu.vcd & 96 | comp: 97 | make -C $(TOP)/sim comp 98 | 99 | run: 100 | vvp $(TOP)/sim/tb +program_memory=$(TESTNAME).vmem 101 | 102 | # --------------------------------------------------------------------------------------- 103 | # Clean 104 | clean : 105 | @rm -rf *.o 106 | @if [ -e $(TESTNAME).hex ] ; then \ 107 | rm -rf $(TESTNAME).hex ; \ 108 | fi 109 | @if [ -e $(TESTNAME).lst ] ; then \ 110 | rm -rf $(TESTNAME).lst ; \ 111 | fi 112 | @if [ -e $(TESTNAME).ELF ] ; then \ 113 | rm -rf $(TESTNAME).ELF ; \ 114 | fi 115 | @if [ -e $(TESTNAME).bin ] ; then \ 116 | rm -rf $(TESTNAME).bin ; \ 117 | fi 118 | @rm -rf *.crf 119 | @rm -rf *.plg 120 | @rm -rf *.tra 121 | @rm -rf *.htm 122 | @rm -rf *.map 123 | @rm -rf *.dep 124 | @rm -rf *.d 125 | @rm -rf *.lnp 126 | @rm -rf *.bak 127 | @rm -rf *.lst 128 | @rm -rf *.axf 129 | @rm -rf *.sct 130 | @rm -rf *.__i 131 | @rm -rf *._ia 132 | -------------------------------------------------------------------------------- /ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/arty_mmcm.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Synthesis run script generated by Vivado 3 | # 4 | 5 | create_project -in_memory -part xc7k70tfbv676-1 6 | 7 | set_param project.compositeFile.enableAutoGeneration 0 8 | set_param synth.vivado.isSynthRun true 9 | set_msg_config -id {IP_Flow 19-2162} -severity warning -new_severity info 10 | set_property webtalk.parent_dir /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/managed_ip_project/managed_ip_project.cache/wt [current_project] 11 | set_property parent.project_path /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/managed_ip_project/managed_ip_project.xpr [current_project] 12 | set_property default_lib xil_defaultlib [current_project] 13 | set_property target_language Verilog [current_project] 14 | set_property vhdl_version vhdl_2k [current_fileset] 15 | read_ip /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xci 16 | set_property is_locked true [get_files /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.xci] 17 | 18 | read_xdc dont_touch.xdc 19 | set_property used_in_implementation false [get_files dont_touch.xdc] 20 | synth_design -top arty_mmcm -part xc7k70tfbv676-1 -mode out_of_context 21 | rename_ref -prefix_all arty_mmcm_ 22 | write_checkpoint -noxdef arty_mmcm.dcp 23 | catch { report_utilization -file arty_mmcm_utilization_synth.rpt -pb arty_mmcm_utilization_synth.pb } 24 | if { [catch { 25 | file copy -force /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/managed_ip_project/managed_ip_project.runs/arty_mmcm_synth_1/arty_mmcm.dcp /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm.dcp 26 | } _RESULT ] } { 27 | error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." 28 | } 29 | if { [catch { 30 | write_verilog -force -mode synth_stub /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.v 31 | } _RESULT ] } { 32 | puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" 33 | } 34 | if { [catch { 35 | write_vhdl -force -mode synth_stub /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.vhdl 36 | } _RESULT ] } { 37 | puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" 38 | } 39 | if { [catch { 40 | write_verilog -force -mode funcsim /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_sim_netlist.v 41 | } _RESULT ] } { 42 | puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" 43 | } 44 | if { [catch { 45 | write_vhdl -force -mode funcsim /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_sim_netlist.vhdl 46 | } _RESULT ] } { 47 | puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" 48 | } 49 | 50 | if {[file isdir /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/ip_user_files/ip/arty_mmcm]} { 51 | catch { 52 | file copy -force /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.v /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/ip_user_files/ip/arty_mmcm 53 | } 54 | } 55 | 56 | if {[file isdir /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/ip_user_files/ip/arty_mmcm]} { 57 | catch { 58 | file copy -force /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/arty_mmcm/arty_mmcm_stub.vhdl /home/roba/perso/github/arty-designstart-cm0/ips/clock_manager/ip_user_files/ip/arty_mmcm 59 | } 60 | } 61 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/arty_mmcm.v: -------------------------------------------------------------------------------- 1 | // file: arty_mmcm.v 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // CLK_OUT1____50.000______0.000______50.0______151.636_____98.575 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // __primary_________100.000____________0.010 64 | 65 | `timescale 1ps/1ps 66 | 67 | (* CORE_GENERATION_INFO = "arty_mmcm,clk_wiz_v5_2_0,{component_name=arty_mmcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 68 | 69 | module arty_mmcm 70 | ( 71 | // Clock in ports 72 | input clk_in, 73 | // Clock out ports 74 | output clk_50m, 75 | // Status and control signals 76 | input resetn, 77 | output locked 78 | ); 79 | 80 | arty_mmcm_clk_wiz inst 81 | ( 82 | // Clock in ports 83 | .clk_in(clk_in), 84 | // Clock out ports 85 | .clk_50m(clk_50m), 86 | // Status and control signals 87 | .resetn(resetn), 88 | .locked(locked) 89 | ); 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /site/404.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | My Docs 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 57 | 58 |
59 | 60 | 61 |
62 |
63 |

404

64 |

Page not found

65 |
66 |
67 | 68 | 69 |
70 | 71 |
72 |
73 | 74 |

Documentation built with MkDocs.

75 |
76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 108 | 109 | 110 | 111 | -------------------------------------------------------------------------------- /sim/iverilog_file_list.txt: -------------------------------------------------------------------------------- 1 | +incdir+/home/ronan/perso/github/cortexm0_designstart/logical/models/memories/ 2 | +incdir+/home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/ 3 | +incdir+/home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/ 4 | +incdir+/home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/ 5 | +incdir+../import/amba_components/common/include 6 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/CORTEXM0DS.v 7 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/cortexm0ds_logic.v 8 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/models/cells/cm0_dbg_reset_sync.v 9 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_wic.v 10 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v 11 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v 12 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_addr_decode.v 13 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v 14 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v 15 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_ahb_cs_rom_table.v 16 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_sysctrl.v 17 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v 18 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v 19 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v 20 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_stclkctrl.v 21 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 22 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v 23 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v 24 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v 25 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v 26 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v 27 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v 28 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 29 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v 30 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v 31 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave.v 32 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v 33 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_reg.v 34 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v 35 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v 36 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v 37 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v 38 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v 39 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_clkctrl.v 40 | ../rtl/bytewrite_ram_32bits.v 41 | ../rtl/cmsdk_ahb_ram.v 42 | ../import/amba_components/ahb_to_ssram/rtl/verilog/ahb_to_ssram.v 43 | ../rtl/arty_mmcm_sim.v 44 | ../rtl/cmsdk_mcu.v 45 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_uart_capture.v 46 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_clkreset.v 47 | ../sim/tb_cmsdk_mcu.v 48 | -------------------------------------------------------------------------------- /sim/vivado_file_list.txt: -------------------------------------------------------------------------------- 1 | --include /home/ronan/perso/github/cortexm0_designstart/logical/models/memories/ 2 | --include /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/ 3 | --include /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/ 4 | --include /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/ 5 | --include ../import/amba_components/common/include 6 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/CORTEXM0DS.v 7 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/cortexm0ds_logic.v 8 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/models/cells/cm0_dbg_reset_sync.v 9 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_wic.v 10 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v 11 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v 12 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_addr_decode.v 13 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v 14 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v 15 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_ahb_cs_rom_table.v 16 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_sysctrl.v 17 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v 18 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v 19 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v 20 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_stclkctrl.v 21 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 22 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v 23 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v 24 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v 25 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v 26 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v 27 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v 28 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 29 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v 30 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v 31 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave.v 32 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v 33 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_reg.v 34 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v 35 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v 36 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v 37 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v 38 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v 39 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_clkctrl.v 40 | ../rtl/bytewrite_ram_32bits.v 41 | ../rtl/cmsdk_ahb_ram.v 42 | ../import/amba_components/ahb_to_ssram/rtl/verilog/ahb_to_ssram.v 43 | ../ips/clock_manager/arty_mmcm/arty_mmcm_clk_wiz.v 44 | ../ips/clock_manager/arty_mmcm/arty_mmcm.v 45 | ../rtl/cmsdk_mcu.v 46 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_uart_capture.v 47 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_clkreset.v 48 | ../sim/tb_cmsdk_mcu.v 49 | -------------------------------------------------------------------------------- /software/scripts/sections.ld: -------------------------------------------------------------------------------- 1 | /* 2 | *----------------------------------------------------------------------------- 3 | * The confidential and proprietary information contained in this file may 4 | * only be used by a person authorised under and to the extent permitted 5 | * by a subsisting licensing agreement from ARM Limited. 6 | * 7 | * (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates. 8 | * ALL RIGHTS RESERVED 9 | * 10 | * This entire notice must be reproduced on all copies of this file 11 | * and copies of this file may only be made by a person if such person is 12 | * permitted to do so under the terms of a subsisting license agreement 13 | * from ARM Limited. 14 | * 15 | * SVN Information 16 | * 17 | * Checked In : $Date: $ 18 | * 19 | * Revision : $Revision: $ 20 | * 21 | * Release Information : Cortex-M0 DesignStart-r1p0-00rel0 22 | *----------------------------------------------------------------------------- 23 | */ 24 | /* Linker script to place sections and symbol values. Should be used together 25 | * with other linker script that defines memory regions FLASH and RAM. 26 | * It references following symbols, which must be defined in code: 27 | * Reset_Handler : Entry of reset handler 28 | * 29 | * It defines following symbols, which code can use without definition: 30 | * __exidx_start 31 | * __exidx_end 32 | * __etext 33 | * __data_start__ 34 | * __preinit_array_start 35 | * __preinit_array_end 36 | * __init_array_start 37 | * __init_array_end 38 | * __fini_array_start 39 | * __fini_array_end 40 | * __data_end__ 41 | * __bss_start__ 42 | * __bss_end__ 43 | * __end__ 44 | * end 45 | * __HeapLimit 46 | * __StackLimit 47 | * __StackTop 48 | * __stack 49 | */ 50 | ENTRY(Reset_Handler) 51 | 52 | SECTIONS 53 | { 54 | .text : 55 | { 56 | KEEP(*(.isr_vector)) 57 | . = 0x100; 58 | KEEP(*(.tbench)) 59 | *(.text*) 60 | 61 | KEEP(*(.init)) 62 | KEEP(*(.fini)) 63 | 64 | /* .ctors */ 65 | *crtbegin.o(.ctors) 66 | *crtbegin?.o(.ctors) 67 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 68 | *(SORT(.ctors.*)) 69 | *(.ctors) 70 | 71 | /* .dtors */ 72 | *crtbegin.o(.dtors) 73 | *crtbegin?.o(.dtors) 74 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 75 | *(SORT(.dtors.*)) 76 | *(.dtors) 77 | 78 | *(.rodata*) 79 | 80 | KEEP(*(.eh_frame*)) 81 | } > FLASH 82 | 83 | .ARM.extab : 84 | { 85 | *(.ARM.extab* .gnu.linkonce.armextab.*) 86 | } > FLASH 87 | 88 | __exidx_start = .; 89 | .ARM.exidx : 90 | { 91 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 92 | } > FLASH 93 | __exidx_end = .; 94 | 95 | __etext = .; 96 | 97 | .data : AT (__etext) 98 | { 99 | __data_start__ = .; 100 | *(vtable) 101 | *(.data*) 102 | 103 | . = ALIGN(4); 104 | /* preinit data */ 105 | PROVIDE_HIDDEN (__preinit_array_start = .); 106 | KEEP(*(.preinit_array)) 107 | PROVIDE_HIDDEN (__preinit_array_end = .); 108 | 109 | . = ALIGN(4); 110 | /* init data */ 111 | PROVIDE_HIDDEN (__init_array_start = .); 112 | KEEP(*(SORT(.init_array.*))) 113 | KEEP(*(.init_array)) 114 | PROVIDE_HIDDEN (__init_array_end = .); 115 | 116 | 117 | . = ALIGN(4); 118 | /* finit data */ 119 | PROVIDE_HIDDEN (__fini_array_start = .); 120 | KEEP(*(SORT(.fini_array.*))) 121 | KEEP(*(.fini_array)) 122 | PROVIDE_HIDDEN (__fini_array_end = .); 123 | 124 | KEEP(*(.jcr*)) 125 | . = ALIGN(4); 126 | /* All data end */ 127 | __data_end__ = .; 128 | 129 | } > RAM 130 | 131 | .bss : 132 | { 133 | . = ALIGN(4); 134 | __bss_start__ = .; 135 | *(.bss*) 136 | *(COMMON) 137 | . = ALIGN(4); 138 | __bss_end__ = .; 139 | } > RAM 140 | 141 | .heap (COPY): 142 | { 143 | __end__ = .; 144 | end = __end__; 145 | *(.heap*) 146 | __HeapLimit = .; 147 | } > RAM 148 | 149 | /* .stack_dummy section doesn't contains any symbols. It is only 150 | * used for linker to calculate size of stack sections, and assign 151 | * values to stack symbols later */ 152 | .stack_dummy (COPY): 153 | { 154 | *(.stack*) 155 | } > RAM 156 | 157 | /* Set stack top to end of RAM, and stack limit move down by 158 | * size of stack_dummy section */ 159 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 160 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 161 | PROVIDE(__stack = __StackTop); 162 | 163 | /* Check if data + heap + stack exceeds RAM limit */ 164 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 165 | } 166 | -------------------------------------------------------------------------------- /verilator_sim/verilator_file_list.txt: -------------------------------------------------------------------------------- 1 | +incdir+/home/ronan/perso/github/cortexm0_designstart/logical/models/memories/ 2 | +incdir+/home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/ 3 | +incdir+/home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/ 4 | +incdir+/home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/ 5 | +incdir+/home/ronan/perso/github/arty-designstart-cm0/import/amba_components/common/include 6 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/CORTEXM0DS.v 7 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/cortexm0ds_logic.v 8 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/models/cells/cm0_dbg_reset_sync.v 9 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_wic.v 10 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v 11 | /home/ronan/perso/github/cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v 12 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_addr_decode.v 13 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v 14 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v 15 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_ahb_cs_rom_table.v 16 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_sysctrl.v 17 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v 18 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v 19 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v 20 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_stclkctrl.v 21 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v 22 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v 23 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v 24 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v 25 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v 26 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v 27 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v 28 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v 29 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v 30 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v 31 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave.v 32 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v 33 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_reg.v 34 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v 35 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v 36 | /home/ronan/perso/github/cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v 37 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v 38 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v 39 | /home/ronan/perso/github/cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_clkctrl.v 40 | /home/ronan/perso/github/arty-designstart-cm0/rtl/bytewrite_ram_1b.v 41 | /home/ronan/perso/github/arty-designstart-cm0/rtl/cmsdk_ahb_ram.v 42 | /home/ronan/perso/github/arty-designstart-cm0/import/amba_components/ahb_to_ssram/rtl/verilog/ahb_to_ssram.v 43 | /home/ronan/perso/github/arty-designstart-cm0/verilator_sim/arty_mmcm.v 44 | /home/ronan/perso/github/cortexm0_designstart/logical/models/clkgate/cmsdk_clock_gate.v 45 | /home/ronan/perso/github/arty-designstart-cm0/rtl/cmsdk_mcu.v 46 | -------------------------------------------------------------------------------- /docs/index.md: -------------------------------------------------------------------------------- 1 | # Welcome to Arty CM0 DesignStart project 2 | 3 | _Under construction_ 4 | 5 | This github repository provides the necessary files to use the 6 | DesignStart Cortex-M0 system on a Digilent ARTY FPGA board. 7 | 8 | ![Arty board](./arty_small.png) 9 | 10 | **This project does not include the source code of the DesignStart 11 | Cortex-M0. You have to request it directly from ARM.** 12 | 13 | In addition to allow synthesis of the designstart to a Xilinx target, 14 | this project allows also simulations using the simulation tools : 15 | 16 | - Icarus iverilog 17 | - Xilinx simulation tools (xvlog/xelab/xsim) 18 | - Verilator 19 | 20 | 21 | 22 | ## Project layout 23 | 24 | common # shared files for configuring the projects 25 | ips # Modules created using Xilinx Vivado 26 | rtl # Verilog RTL files for the project 27 | sim # Verilog simulation directory 28 | synt # synthesis directory 29 | verilator_sim # Verilator build/simulation directory 30 | software # Local testsuites (asm/c programs) 31 | import # imported github submodules (currently only amba_components) 32 | docs # the mkdocs/markdown sources for this site 33 | site # generated html/js files for this site 34 | 35 | 36 | ## Installation 37 | 38 | ### Cloning from github 39 | 40 | This project uses submodules. To clone it you need to run the following commands : 41 | 42 | ```bash 43 | git clone git@github.com:rbarzic/arty-cm0-designstart.git 44 | cd arty-cm0-designstart 45 | git submodule init 46 | git submodule update 47 | ``` 48 | 49 | ### Setting environment variables 50 | 51 | 52 | The ARM Cortex-MO designstart package is not included in this project. You must download it yourself and setup the `DESIGNSTART_TOP` variable to point to the directory it had be installed in : 53 | 54 | export DESIGNSTART_TOP= 55 | 56 | 57 | ### Patching Cortex-M0 designstart folder 58 | 59 | The code provided by ARM needs to be modified. The changes are gathered in a patch file. 60 | 61 | make -C patches patch 62 | 63 | 64 | ## Compiling test programs 65 | 66 | Test programs are located under the software directory. 67 | 68 | To compile, enter the directory of the program and type : 69 | `make all` 70 | 71 | Several files (bin, hex, vmem and vmem32,..) should be created 72 | 73 | ## Simulation using Icarus iverilog 74 | 75 | Go into a test program directory (under software/xxx) then : 76 | 77 | ```bash 78 | # Compile C code 79 | make all 80 | # build iverilog simulator files 81 | make comp 82 | # run the simulation 83 | make run 84 | 85 | # optionaly, you can look at waveform using gtkwave 86 | make wave 87 | ``` 88 | 89 | Simulation should stop when _main()_ exits or _exit()_ is called directly 90 | 91 | ## Synthesis using Vivado 92 | 93 | The complete flow is shown in the following figure : 94 | 95 | 96 | 97 | 98 | The first part of the flow is the generation of the first bit file. 99 | Verilog files are parsed by Vivado together with constraint files and 100 | a file to initialize the program memory. 101 | 102 | Later, the Vivado utility _updatemem_ is used to change the content of 103 | the program memory without the need for a new synthesys 104 | 105 | Files used by the synthesis flow : 106 | 107 | vivado_utils.tcl # Various _tcl_ functions 108 | vivado.tcl # The main synthesis script 109 | report_bram.tcl # tcl code to output block ram placement (for _updatemem_) 110 | xilinx_constraints.xdc # Constraint file (clock, pads,..) 111 | code.vmem32 # the original content of the program memory 112 | 113 | ### Running the synthesis 114 | 115 | ```bash 116 | make synt 117 | ``` 118 | Files generated by the synthesis flow : 119 | 120 | rpt/cpu.bit # Xilinx bitstream file 121 | chip_layout.v # Post Place&Route Verilog netlist 122 | chip_layout.sdf # Post Place&Route timing backannotation file (SDF) 123 | bram.yaml # Block RAM placement file 124 | 125 | 126 | 127 | 128 | ### Programming the device 129 | 130 | 131 | ### Updating the program memory 132 | 133 | To create a new bit file without launching a new synthesis : 134 | ```bash 135 | 136 | make update TEST= 137 | ``` 138 | where is the name of a test under _software_ 139 | 140 | 141 | 142 | ## Simulation using Vivado 143 | 144 | ### RTL simulation 145 | 146 | ### Post Place&Route backannotated simulation 147 | 148 | ## Simulation using Verilator 149 | -------------------------------------------------------------------------------- /synt/test.mmi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 110 | 111 | -------------------------------------------------------------------------------- /synt/test2.mmi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 110 | 111 | -------------------------------------------------------------------------------- /ips/clock_manager/arty_mmcm/doc/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/mem_init_files/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/ies/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/vcs/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/modelsim/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/questa/clk_wiz_v5_2_changelog.txt: -------------------------------------------------------------------------------- 1 | 2015.3: 2 | * Version 5.2 3 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 4 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 5 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 6 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 7 | * Example design and simulation files are delivered in verilog only 8 | 9 | 2015.2.1: 10 | * Version 5.1 (Rev. 6) 11 | * No changes 12 | 13 | 2015.2: 14 | * Version 5.1 (Rev. 6) 15 | * No changes 16 | 17 | 2015.1: 18 | * Version 5.1 (Rev. 6) 19 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 20 | * Supported devices and production status are now determined automatically, to simplify support for future devices 21 | 22 | 2014.4.1: 23 | * Version 5.1 (Rev. 5) 24 | * No changes 25 | 26 | 2014.4: 27 | * Version 5.1 (Rev. 5) 28 | * Internal device family change, no functional changes 29 | * updates related to the source selection based on board interface for zed board 30 | 31 | 2014.3: 32 | * Version 5.1 (Rev. 4) 33 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 34 | 35 | 2014.2: 36 | * Version 5.1 (Rev. 3) 37 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 38 | 39 | 2014.1: 40 | * Version 5.1 (Rev. 2) 41 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 42 | * Internal device family name change, no functional changes 43 | 44 | 2013.4: 45 | * Version 5.1 (Rev. 1) 46 | * Added support for Ultrascale devices 47 | * Updated Board Flow GUI to select the clock interfaces 48 | * Fixed issue with Stub file parameter error for BUFR output driver 49 | 50 | 2013.3: 51 | * Version 5.1 52 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 53 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 54 | * Fixed precision issues between displayed and actual frequencies 55 | * Added tool tips to GUI 56 | * Added Jitter and Phase error values to IP properties 57 | * Added support for Cadence IES and Synopsys VCS simulators 58 | * Reduced warnings in synthesis and simulation 59 | * Enhanced support for IP Integrator 60 | 61 | 2013.2: 62 | * Version 5.0 (Rev. 1) 63 | * Fixed issue with clock constraints for multiple instances of clocking wizard 64 | * Updated Life-Cycle status of devices 65 | 66 | 2013.1: 67 | * Version 5.0 68 | * Lower case ports for Verilog 69 | * Added Safe Clock Startup and Clock Sequencing 70 | 71 | (c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved. 72 | 73 | This file contains confidential and proprietary information 74 | of Xilinx, Inc. and is protected under U.S. and 75 | international copyright and other intellectual property 76 | laws. 77 | 78 | DISCLAIMER 79 | This disclaimer is not a license and does not grant any 80 | rights to the materials distributed herewith. Except as 81 | otherwise provided in a valid license issued to you by 82 | Xilinx, and to the maximum extent permitted by applicable 83 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 84 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 85 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 86 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 87 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 88 | (2) Xilinx shall not be liable (whether in contract or tort, 89 | including negligence, or under any other theory of 90 | liability) for any loss or damage of any kind or nature 91 | related to, arising under or in connection with these 92 | materials, including for any direct, or any indirect, 93 | special, incidental, or consequential loss or damage 94 | (including loss of data, profits, goodwill, or any type of 95 | loss or damage suffered as a result of any action brought 96 | by a third party) even if such damage or loss was 97 | reasonably foreseeable or Xilinx had been advised of the 98 | possibility of the same. 99 | 100 | CRITICAL APPLICATIONS 101 | Xilinx products are not designed or intended to be fail- 102 | safe, or for use in any application requiring fail-safe 103 | performance, such as life-support or safety devices or 104 | systems, Class III medical devices, nuclear facilities, 105 | applications related to the deployment of airbags, or any 106 | other applications that could lead to death, personal 107 | injury, or severe property or environmental damage 108 | (individually and collectively, "Critical 109 | Applications"). Customer assumes the sole risk and 110 | liability of any use of Xilinx products in Critical 111 | Applications, subject only to applicable laws and 112 | regulations governing limitations on product liability. 113 | 114 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 115 | PART OF THIS FILE AT ALL TIMES. 116 | -------------------------------------------------------------------------------- /ips/clock_manager/ip_user_files/sim_scripts/arty_mmcm/xsim/arty_mmcm.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # Vivado (TM) v2015.3 (64-bit) 3 | # 4 | # Filename : arty_mmcm.sh 5 | # Simulator : Xilinx Vivado Simulator 6 | # Description : Simulation script for compiling, elaborating and verifying the project source files. 7 | # The script will automatically create the design libraries sub-directories in the run 8 | # directory, add the library logical mappings in the simulator setup file, create default 9 | # 'do' file, copy glbl.v into the run directory for verilog sources in the design (if any), 10 | # execute compilation, elaboration and simulation steps. 11 | # 12 | # Generated by Vivado on Mon Nov 16 15:47:13 CET 2015 13 | # IP Build 1367837 on Mon Sep 28 08:56:14 MDT 2015 14 | # 15 | # usage: arty_mmcm.sh [-help] 16 | # usage: arty_mmcm.sh [-lib_map_path] 17 | # usage: arty_mmcm.sh [-noclean_files] 18 | # usage: arty_mmcm.sh [-reset_run] 19 | # 20 | # ******************************************************************************************************** 21 | 22 | # Script info 23 | echo -e "arty_mmcm.sh - Script generated by export_simulation (Vivado v2015.3 (64-bit)-id)\n" 24 | 25 | # Script usage 26 | usage() 27 | { 28 | msg="Usage: arty_mmcm.sh [-help]\n\ 29 | Usage: arty_mmcm.sh [-lib_map_path]\n\ 30 | Usage: arty_mmcm.sh [-reset_run]\n\ 31 | Usage: arty_mmcm.sh [-noclean_files]\n\n\ 32 | [-help] -- Print help information for this script\n\n\ 33 | [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ 34 | using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ 35 | [-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ 36 | from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ 37 | -noclean_files switch.\n\n\ 38 | [-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" 39 | echo -e $msg 40 | exit 1 41 | } 42 | 43 | if [[ ($# == 1 ) && ($1 != "-lib_map_path" && $1 != "-noclean_files" && $1 != "-reset_run" && $1 != "-help" && $1 != "-h") ]]; then 44 | echo -e "ERROR: Unknown option specified '$1' (type \"./arty_mmcm.sh -help\" for more information)\n" 45 | exit 1 46 | fi 47 | 48 | if [[ ($1 == "-help" || $1 == "-h") ]]; then 49 | usage 50 | fi 51 | 52 | # STEP: setup 53 | setup() 54 | { 55 | case $1 in 56 | "-lib_map_path" ) 57 | if [[ ($2 == "") ]]; then 58 | echo -e "ERROR: Simulation library directory path not specified (type \"./arty_mmcm.sh -help\" for more information)\n" 59 | exit 1 60 | fi 61 | # precompiled simulation library directory path 62 | copy_glbl_file 63 | ;; 64 | "-reset_run" ) 65 | reset_run 66 | echo -e "INFO: Simulation run files deleted.\n" 67 | exit 0 68 | ;; 69 | "-noclean_files" ) 70 | # do not remove previous data 71 | ;; 72 | * ) 73 | copy_glbl_file 74 | esac 75 | 76 | # Add any setup/initialization commands here:- 77 | 78 | # 79 | 80 | } 81 | 82 | # Copy glbl.v file into run directory 83 | copy_glbl_file() 84 | { 85 | glbl_file="glbl.v" 86 | src_file="/opt/Xilinx/Vivado/2015.3/data/verilog/src/glbl.v" 87 | if [[ ! -e $glbl_file ]]; then 88 | cp $src_file . 89 | fi 90 | } 91 | 92 | # Remove generated data from the previous run and re-create setup files/library mappings 93 | reset_run() 94 | { 95 | files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb arty_mmcm.wdb xsim.dir) 96 | for (( i=0; i<${#files_to_remove[*]}; i++ )); do 97 | file="${files_to_remove[i]}" 98 | if [[ -e $file ]]; then 99 | rm -rf $file 100 | fi 101 | done 102 | } 103 | 104 | # Main steps 105 | run() 106 | { 107 | setup $1 $2 108 | compile 109 | elaborate 110 | simulate 111 | } 112 | 113 | 114 | # RUN_STEP: 115 | compile() 116 | { 117 | # Command line options 118 | opts_ver="-m64 --relax" 119 | 120 | # Compile design files 121 | xvlog $opts_ver -prj vlog.prj 2>&1 | tee compile.log 122 | 123 | } 124 | 125 | # RUN_STEP: 126 | elaborate() 127 | { 128 | xelab --relax --debug typical --mt auto -wto 7d1377bb400e45178a8e45584ade15fe -m64 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot arty_mmcm xil_defaultlib.arty_mmcm xil_defaultlib.glbl -log elaborate.log 129 | } 130 | 131 | # RUN_STEP: 132 | simulate() 133 | { 134 | xsim arty_mmcm -key {Behavioral:sim_1:Functional:arty_mmcm} -tclbatch cmd.tcl -log simulate.log 135 | } 136 | # Script usage 137 | usage() 138 | { 139 | msg="Usage: arty_mmcm.sh [-help]\n\ 140 | Usage: arty_mmcm.sh [-lib_map_path]\n\ 141 | Usage: arty_mmcm.sh [-reset_run]\n\ 142 | Usage: arty_mmcm.sh [-noclean_files]\n\n\ 143 | [-help] -- Print help information for this script\n\n\ 144 | [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ 145 | using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ 146 | [-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ 147 | from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ 148 | -noclean_files switch.\n\n\ 149 | [-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" 150 | echo -e $msg 151 | exit 1 152 | } 153 | 154 | 155 | # Launch script 156 | run $1 $2 157 | --------------------------------------------------------------------------------