├── APB_interface.v ├── APB_interface_testbench.v ├── README.md ├── SPI_master.v ├── SPI_modes.jpg ├── SPI_slave.v ├── SPI_testmodul_2.v ├── Simulation_public.bmp ├── system_design.jpg └── system_hierarchy.png /APB_interface.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: Péntek Róbert Gergő 5 | // 6 | // Create Date: 17:40:55 04/28/2020 7 | // Design Name: 8 | // Module Name: APB_interface 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module APB_interface_2( 22 | input i_PRESETn, 23 | input i_PCLK, 24 | input i_PSEL0, 25 | input i_PENABLE, 26 | input i_PWRITE, 27 | input [15:0] i_PADDR, 28 | input [7:0] i_PWDATA, 29 | input [7:0] i_PRDATA, 30 | input [9:0] i_BASE_ADDR, 31 | 32 | 33 | output reg o_WR0, //CONFIG_SPI 34 | output reg o_WR1, //TX_SPI 35 | output reg o_WR2, //RX_SPI 36 | output reg o_WR3, //CMD_SPI 37 | 38 | output reg o_DR0, //STATE_SPI 39 | output reg o_DR1, //RX_SPI 40 | output reg o_DR2, //Optional 41 | output reg o_DR3, //Optional 42 | 43 | output PREADY, 44 | 45 | output [7:0] o_PRDATA, 46 | output reg [7:0] o_PWDATA 47 | ); 48 | 49 | assign PREADY= (i_PSEL0 & i_PENABLE); 50 | 51 | 52 | reg SELECT; 53 | reg d_ff; 54 | wire PULSE; 55 | 56 | 57 | 58 | //impulzus generálás 59 | always @(posedge i_PCLK) 60 | 61 | begin 62 | if(i_PRESETn==0) 63 | begin 64 | d_ff<=1'b0; 65 | end 66 | if (i_PENABLE==1) 67 | begin 68 | d_ff<=1'b1; 69 | end 70 | else 71 | begin 72 | d_ff<=1'b0; 73 | end 74 | end 75 | 76 | 77 | assign PULSE=~d_ff & i_PENABLE; 78 | 79 | 80 | //APB_Interface 81 | always @(posedge i_PCLK) 82 | begin 83 | if(i_PRESETn==0) 84 | begin 85 | o_WR0<=0; 86 | o_WR1<=0; 87 | o_WR2<=0; 88 | o_WR3<=0; 89 | 90 | o_DR0<=0; 91 | o_DR1<=0; 92 | o_DR2<=0; 93 | o_DR3<=0; 94 | end 95 | 96 | if(i_PSEL0==1 && i_PADDR[15:6]==i_BASE_ADDR[7:0]) 97 | begin 98 | SELECT<=1; 99 | o_PWDATA = i_PWDATA; 100 | end 101 | else 102 | begin 103 | SELECT<=0; 104 | o_PWDATA = 8'b00000000; 105 | end 106 | if(PULSE==1 && SELECT==1) 107 | begin 108 | case(i_PADDR[5:2]) 109 | 4'b0000:begin o_WR0<=i_PWRITE; o_DR0<=( ! i_PWRITE );end 110 | 4'b0001:begin o_WR1<=i_PWRITE; o_DR1<=( ! i_PWRITE );end 111 | 4'b0010:begin o_WR2<=i_PWRITE; o_DR2<=( ! i_PWRITE );end 112 | 4'b0011:begin o_WR3<=i_PWRITE; o_DR3<=( ! i_PWRITE );end 113 | endcase 114 | end 115 | else 116 | begin 117 | o_WR0<=0; 118 | o_WR1<=0; 119 | o_WR2<=0; 120 | o_WR3<=0; 121 | 122 | o_DR0<=0; 123 | o_DR1<=0; 124 | o_DR2<=0; 125 | o_DR3<=0; 126 | 127 | end 128 | 129 | end//last 130 | 131 | 132 | SPI_testmodul2 SPI_modul2( 133 | .PCLK(i_PCLK), 134 | .PRESETn(i_PRESETn), 135 | .WR0(o_WR0), //CONFIG_SPI 136 | .WR1(o_WR1), //TX_SPI 137 | .WR2(o_WR2), //RX_SPI 138 | .WR3(o_WR3), //CMD_SPI 139 | 140 | .DR0(o_DR0), //STATE_SPI 141 | .DR1(o_DR1), //RX_SPI 142 | .DR2(o_DR2), //Optional 143 | .DR3(o_DR3), //Optional 144 | 145 | .PRDATA(o_PRDATA), 146 | .PWDATA(o_PWDATA) 147 | 148 | ); 149 | 150 | 151 | 152 | endmodule 153 | 154 | 155 | 156 | -------------------------------------------------------------------------------- /APB_interface_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 10ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: Péntek Róbert Gergő 6 | // 7 | // Create Date: 15:32:54 05/24/2020 8 | // Design Name: APB_interface_2 9 | // Module Name: C:/PROG/xilinx/APB_interface/APB_interface2_testbench.v 10 | // Project Name: APB_interface 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module APB_interface2_testbench; 26 | 27 | // Inputs 28 | reg i_PRESETn; 29 | reg i_PCLK; 30 | reg i_PSEL0; 31 | reg i_PENABLE; 32 | reg i_PWRITE; 33 | reg [15:0] i_PADDR; 34 | reg [7:0] i_PWDATA; 35 | reg [7:0] i_PRDATA; 36 | reg [9:0] i_BASE_ADDR; 37 | 38 | // Outputs 39 | wire o_WR0; 40 | wire o_WR1; 41 | wire o_WR2; 42 | wire o_WR3; 43 | wire o_DR0; 44 | wire o_DR1; 45 | wire o_DR2; 46 | wire o_DR3; 47 | wire PREADY; 48 | wire [7:0] o_PWDATA; 49 | wire [7:0] o_PRDATA; 50 | 51 | // Instantiate the Unit Under Test (UUT) 52 | APB_interface_2 uut ( 53 | .i_PRESETn(i_PRESETn), 54 | .i_PCLK(i_PCLK), 55 | .i_PSEL0(i_PSEL0), 56 | .i_PENABLE(i_PENABLE), 57 | .i_PWRITE(i_PWRITE), 58 | .i_PADDR(i_PADDR), 59 | .i_PWDATA(i_PWDATA), 60 | .i_PRDATA(i_PRDATA), 61 | .i_BASE_ADDR(i_BASE_ADDR), 62 | .o_WR0(o_WR0), 63 | .o_WR1(o_WR1), 64 | .o_WR2(o_WR2), 65 | .o_WR3(o_WR3), 66 | .o_DR0(o_DR0), 67 | .o_DR1(o_DR1), 68 | .o_DR2(o_DR2), 69 | .o_DR3(o_DR3), 70 | .PREADY(PREADY), 71 | .o_PWDATA(o_PWDATA), 72 | .o_PRDATA(o_PRDATA) 73 | ); 74 | //READ parameters 75 | localparam STATUS = 4'b0000; 76 | localparam RX = 4'b0001; 77 | 78 | //Write parameters 79 | localparam MODE00 = 2'b00; 80 | localparam MODE01 = 2'b01; 81 | localparam MODE10 = 2'b10; 82 | localparam MODE11 = 2'b11; 83 | 84 | localparam SLAVE0 = 2'b00; 85 | localparam SLAVE1 = 2'b01; 86 | localparam SLAVE2 = 2'b10; 87 | localparam SLAVE3 = 2'b11; 88 | 89 | localparam SCK8 = 2'b00; //8MHZ Ha PCLK 16MHZ!!! 90 | localparam SCK4 = 2'b01; //4MHZ 91 | localparam SCK2 = 2'b10; //2MHZ 92 | localparam SCK1 = 2'b11; //1MHZ 93 | 94 | task APB_READ(input RD); 95 | begin 96 | case(RD) 97 | 4'b0000: i_PADDR=16'b0000000001000000; 98 | 4'b0001: i_PADDR=16'b0000000001000100; 99 | endcase 100 | i_PWRITE=0;i_PSEL0=1; 101 | #6.25 102 | i_PENABLE=1; 103 | #6.25 104 | i_PSEL0=0; i_PENABLE=0; 105 | 106 | end 107 | endtask 108 | 109 | task APB_WRITE(input[1:0] MODE, SLAVE,SCK, input [7:0] DATA); 110 | begin 111 | ///CONFIG write------------------------------------------------------------------------- 112 | 113 | i_PWDATA=({2'b00, MODE, SLAVE, SCK}); 114 | i_PADDR=16'b0000000001000000; i_PWRITE=1; i_PSEL0=1; // CONFIG_REG irása 115 | #6.25 116 | i_PENABLE=1; 117 | #6.25 118 | i_PSEL0=0; i_PENABLE=0;i_PWRITE=0; 119 | ///TX write----------------------------------------------------------------------------- 120 | #6.25 121 | i_PADDR=16'b0000000001000100;i_PWRITE=1;i_PSEL0=1;i_PWDATA=DATA;// TX data 122 | #6.25 123 | i_PENABLE=1; 124 | #6.25 125 | i_PSEL0=0; i_PENABLE=0;i_PWRITE=0; 126 | ///CMD write----------------------------------------------------------------------------- 127 | #6.25 128 | i_PADDR=16'b0000000001001100;i_PWRITE=1;i_PSEL0=1;i_PWDATA=8'b00000010; //CMD REG 129 | #6.25 130 | i_PENABLE=1; 131 | #6.25 132 | i_PSEL0=0; i_PENABLE=0;i_PWRITE=0; 133 | end 134 | endtask 135 | 136 | 137 | initial begin 138 | i_PCLK=1'b0; 139 | forever #3.125 i_PCLK=~i_PCLK; 140 | end 141 | 142 | initial begin 143 | // Initialize Inputs 144 | i_PRESETn = 0; 145 | i_PCLK = 0; 146 | i_PSEL0 = 0; 147 | i_PENABLE = 0; 148 | i_PWRITE = 0; 149 | i_PADDR = 0; 150 | i_PWDATA = 0; 151 | i_PRDATA = 0; 152 | i_BASE_ADDR = 10'b0000000001; 153 | 154 | // Wait 100 ns for global reset to finish 155 | 156 | #3.125 157 | #6.25 158 | i_PRESETn = 1; 159 | #25 160 | APB_WRITE(MODE00,SLAVE0,SCK4,8'b01010101); 161 | #450 162 | APB_READ(RX); 163 | #50 164 | APB_READ(STATUS); 165 | #50 166 | APB_WRITE(MODE01,SLAVE1,SCK8,8'b01010101); 167 | #250 168 | APB_READ(RX); 169 | #50 170 | APB_WRITE(MODE10,SLAVE2,SCK8,8'b01010101); 171 | #250 172 | APB_READ(RX); 173 | #50 174 | APB_WRITE(MODE11,SLAVE3,SCK8,8'b01010101); 175 | #250 176 | APB_READ(RX); 177 | #50 178 | 179 | $stop; 180 | 181 | 182 | 183 | 184 | end 185 | 186 | endmodule 187 | 188 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # verilog_APB_SPI_interface 2 | SPI interface connect to APB BUS with Verilog HDL 3 | 4 | This project implement an SPI module with an APB Bus interface. 5 | The project contains 4 modules: APB_interface, SPI_master, 4 SPI_slave, and the testbench. 6 | Another module is the SPI_testmodul_2. In this part i connect the master and 4 spi slaves to each other. 7 | The test application send 01010101 to the APB interface, the interface give it to the master. 8 | The master write and read the data from the SPI_slaves at same time. 9 | During the test all 4 spi tansmission mode was performed, and each slave send's back their transmisson mode 111100xx, xx: 00 | 01 | 11 | 10 10 | -------------------------------------------------------------------------------- /SPI_master.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: Péntek Róbert Gergő 5 | // 6 | // Create Date: 14:33:56 05/21/2020 7 | // Design Name: 8 | // Module Name: spi_master5 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module spi_master5( 22 | input i_PRESETn, 23 | input i_PCLK, 24 | input i_SPI_CLK, 25 | 26 | input i_WR0, //CONFIG_SPI 27 | input i_WR1, //TX_SPI 28 | input i_WR2, //RX_SPI 29 | input i_WR3, //CMD_SPI 30 | 31 | input i_DR0, //STATE_SPI 32 | input i_DR1, //RX_SPI 33 | input i_DR2, //Optional 34 | input i_DR3, //Optional 35 | 36 | //APB BUSZ adatcsatornák 37 | input [7:0] i_PWDATA, 38 | output[7:0] o_PRDATA, 39 | 40 | //SPI_MASTER 41 | input MISO, 42 | output MOSI, 43 | output wire SCK, 44 | 45 | output reg SS0, 46 | output reg SS1, 47 | output reg SS2, 48 | output reg SS3 49 | ); 50 | 51 | reg [7:0] PRDATA; 52 | assign o_PRDATA=PRDATA; 53 | 54 | 55 | //SPI_REGISTERS-------------------------------------------- 56 | 57 | reg[7:0] CONFIG_REG; 58 | reg[7:0] CMD_REG; 59 | reg[7:0] TX_REG; 60 | reg[7:0] RX_REG; 61 | reg[7:0] STATE_REG; 62 | 63 | //SPI_MASTER 64 | reg SHIFT_IN; 65 | reg[7:0] SHIFT_REG; 66 | 67 | // Allapotgep 68 | reg[1:0] STATE; 69 | reg[4:0] SCK_CNT; 70 | 71 | 72 | //ORAJEL generator 73 | reg [3:0] counter; 74 | reg [3:0] divider; 75 | reg SCK_ENABLE; 76 | reg SPI_CLK; 77 | reg o_SCK; 78 | wire i_SCK; 79 | 80 | assign SCK=o_SCK; 81 | 82 | // P/N EDGE 83 | reg d_ffp; 84 | reg d_ffn; 85 | wire P_EDGE; 86 | wire N_EDGE; 87 | 88 | 89 | 90 | //RESET---------------------------------------------------------------- 91 | 92 | always @(posedge i_PCLK) 93 | begin 94 | if(i_PRESETn==0) 95 | begin 96 | CONFIG_REG<=8'b00000000; 97 | CMD_REG<=8'b00000000; 98 | TX_REG<=8'b00000000; 99 | RX_REG<=8'bZ; 100 | PRDATA<=8'bZ; 101 | SHIFT_REG<=8'bZ; 102 | SHIFT_IN<=1'bZ; 103 | STATE_REG<=8'b00000010; 104 | SCK_ENABLE<=1'b0; 105 | SCK_CNT<=5'b0; 106 | SPI_CLK<=1'b0; 107 | o_SCK<=1'b0; 108 | STATE<=2'b00; 109 | SS0<=1; 110 | SS1<=1; 111 | SS2<=1; 112 | SS3<=1; 113 | end 114 | end 115 | //APB busz változóinak kezelése----------------------------- 116 | 117 | always@(posedge i_PCLK) 118 | begin 119 | case({i_WR0,i_WR1,i_WR2,i_WR3,i_DR0,i_DR1,i_DR2,i_DR3}) 120 | 8'b10000000: CONFIG_REG <= i_PWDATA; 121 | 8'b01000000: SHIFT_REG <= i_PWDATA; 122 | 8'b00100000: RX_REG <= i_PWDATA; 123 | 8'b00010000: CMD_REG <= i_PWDATA; 124 | 8'b00001000: PRDATA <= STATE_REG; 125 | 8'b00000100: PRDATA <= RX_REG; 126 | 8'b00000010: PRDATA <= TX_REG; 127 | 8'b00000001: PRDATA <= CMD_REG; 128 | endcase 129 | end 130 | //SPI_CLK generátor----------------------------------------- 131 | 132 | always @(posedge i_PCLK) 133 | begin 134 | if(SCK_ENABLE==1) 135 | begin 136 | if(counter==divider) 137 | begin 138 | counter<=4'b0000; 139 | SPI_CLK<= ~SPI_CLK; 140 | end 141 | 142 | else 143 | begin 144 | counter<=counter+1'b1; 145 | end 146 | end 147 | 148 | end 149 | 150 | // P/N EDGE generátor-------------------------------------- 151 | 152 | always @(posedge i_PCLK) 153 | begin 154 | if(SCK_ENABLE==1) 155 | begin 156 | if(i_PRESETn==0) 157 | begin 158 | d_ffp<=1'b0; 159 | end 160 | if (SPI_CLK==1) 161 | begin 162 | d_ffp<=1'b1; 163 | end 164 | else 165 | begin 166 | d_ffp<=1'b0; 167 | end 168 | end 169 | end 170 | 171 | assign P_EDGE=SCK_ENABLE? (~d_ffp & SPI_CLK): 1'bZ; // Positive edge 172 | 173 | always @(posedge i_PCLK) 174 | begin 175 | if(SCK_ENABLE==1) 176 | begin 177 | if(i_PRESETn==0) 178 | begin 179 | d_ffn<=1'b0; 180 | end 181 | if (SPI_CLK==0) 182 | begin 183 | d_ffn<=1'b1; 184 | end 185 | else 186 | begin 187 | d_ffn<=1'b0; 188 | end 189 | end 190 | end 191 | 192 | assign N_EDGE=SCK_ENABLE? (~d_ffn & ~SPI_CLK): 1'bZ; // Negativ edge 193 | 194 | // SCK generátor------------------------------------------- 195 | 196 | always @(posedge i_PCLK) 197 | begin 198 | if(SCK_ENABLE==1) 199 | begin 200 | if(P_EDGE) 201 | begin 202 | o_SCK<= 1'b1; 203 | end 204 | if(N_EDGE) 205 | begin 206 | o_SCK<= 1'b0; 207 | end 208 | end 209 | end 210 | 211 | 212 | 213 | 214 | 215 | //Allapotgep---------------------------------------------- 216 | always@(posedge i_PCLK) 217 | begin 218 | //IDLE vagy transfer után 219 | if(STATE==2'b00 &&CMD_REG[1]==0) 220 | begin 221 | RX_REG<=SHIFT_REG; 222 | STATE_REG<=8'b00000010; 223 | end 224 | 225 | //BUSY state 226 | if(STATE==2'b00 && CMD_REG[1]==1) 227 | begin 228 | STATE_REG<=8'b00000000; 229 | SPI_CLK<=CONFIG_REG[5]; 230 | //#4 231 | STATE<=2'b01; 232 | end 233 | // CONFIG 234 | if(STATE==2'b01) 235 | begin 236 | CMD_REG[1]<=1'b0; 237 | counter<= 4'b0000; 238 | SCK_CNT<= 4'b0000; 239 | 240 | case (CONFIG_REG[3:2]) 241 | 2'b00: SS0<=0; 242 | 2'b01: SS1<=0; 243 | 2'b10: SS2<=0; 244 | 2'b11: SS3<=0; 245 | endcase 246 | 247 | case(CONFIG_REG[1:0]) 248 | 2'b00: divider<=4'b0001; 249 | 2'b01: divider<=4'b0011; 250 | 2'b10: divider<=4'b0111; 251 | 2'b11: divider<=4'b1111; 252 | endcase 253 | 254 | STATE<=2'b10; 255 | end 256 | //TRANSFER 257 | if(STATE==2'b10) 258 | begin 259 | SCK_ENABLE<=1'b1; 260 | SHIFT_IN<=MISO; 261 | 262 | if(SCK_CNT<16) 263 | begin 264 | SCK_ENABLE<=1'b1; 265 | end 266 | else 267 | begin 268 | SCK_ENABLE<=1'b0; 269 | STATE<=2'b11; 270 | end 271 | end 272 | //TRANSFER_END 273 | if (STATE==2'b11) 274 | begin 275 | SCK_CNT<= 4'b0000; 276 | SS0<=1; 277 | SS1<=1; 278 | SS2<=1; 279 | SS3<=1; 280 | 281 | STATE<=2'b00; 282 | end 283 | end 284 | 285 | 286 | 287 | 288 | //SPI átvitel 289 | 290 | assign MOSI=(({SS0,SS1,SS2,SS3})!=4'b1111)? SHIFT_REG[7] : 1'bZ; 291 | 292 | always@(posedge i_PCLK) 293 | begin 294 | if(CONFIG_REG[5:4]==2'b00) 295 | begin 296 | if(P_EDGE) 297 | begin 298 | SHIFT_IN<=MISO; 299 | SCK_CNT<=SCK_CNT+1'b1; 300 | end 301 | if(N_EDGE) 302 | begin 303 | SHIFT_REG <= SHIFT_REG << 1; 304 | SHIFT_REG[0]<=SHIFT_IN; 305 | SCK_CNT<=SCK_CNT+1'b1; 306 | end 307 | end 308 | 309 | 310 | 311 | if(CONFIG_REG[5:4]==2'b01) 312 | begin 313 | if(P_EDGE) 314 | begin 315 | SHIFT_REG <= SHIFT_REG << 1; 316 | SHIFT_REG[0]<=SHIFT_IN; 317 | SCK_CNT<=SCK_CNT+1'b1; 318 | end 319 | if(N_EDGE) 320 | begin 321 | SHIFT_IN<=MISO; 322 | SCK_CNT<=SCK_CNT+1'b1; 323 | end 324 | end 325 | 326 | 327 | 328 | 329 | if(CONFIG_REG[5:4]==2'b10) 330 | begin 331 | if(P_EDGE) 332 | begin 333 | SHIFT_REG <= SHIFT_REG << 1; 334 | SHIFT_REG[0]<=SHIFT_IN; 335 | SCK_CNT<=SCK_CNT+1'b1; 336 | end 337 | if(N_EDGE) 338 | begin 339 | SHIFT_IN<=MISO; 340 | SCK_CNT<=SCK_CNT+1'b1; 341 | end 342 | end 343 | 344 | 345 | 346 | if(CONFIG_REG[5:4]==2'b11) 347 | begin 348 | if(P_EDGE) 349 | begin 350 | SHIFT_IN<=MISO; 351 | SCK_CNT<=SCK_CNT+1'b1; 352 | end 353 | if(N_EDGE) 354 | begin 355 | SHIFT_REG <= SHIFT_REG << 1; 356 | SHIFT_REG[0]<=SHIFT_IN; 357 | SCK_CNT<=SCK_CNT+1'b1; 358 | end 359 | end 360 | end 361 | 362 | 363 | 364 | endmodule 365 | 366 | -------------------------------------------------------------------------------- /SPI_modes.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/red435/verilog_APB_SPI_interface/5eef874c23e20e295839f093f4f3c58b2368d2c3/SPI_modes.jpg -------------------------------------------------------------------------------- /SPI_slave.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: Péntek Róbert Gergő 5 | // 6 | // Create Date: 21:44:53 05/21/2020 7 | // Design Name: 8 | // Module Name: SPI_SLAVE 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SPI_SLAVE( 22 | input PRESETn, 23 | input MOSI, 24 | input SCK, 25 | input SS, 26 | input [1:0] MODE, 27 | input [7:0] TEST_DATA, 28 | 29 | output wire MISO 30 | ); 31 | 32 | reg SHIFT_IN; 33 | reg [7:0] SHIFT_REG; 34 | 35 | assign MISO = SS ? 1'bZ : SHIFT_REG[7]; 36 | 37 | 38 | always@ (negedge SS) 39 | begin 40 | SHIFT_IN<=MOSI; 41 | SHIFT_REG<=TEST_DATA;//kezdeti érték 42 | end 43 | 44 | 45 | 46 | always @(posedge SCK) 47 | begin 48 | if(SS==0) 49 | begin 50 | if(MODE==2'b00) 51 | begin 52 | SHIFT_IN<=MOSI; 53 | end 54 | 55 | if(MODE==2'b01) 56 | begin 57 | SHIFT_REG <= SHIFT_REG << 1; 58 | SHIFT_REG[0]<=SHIFT_IN; 59 | end 60 | 61 | if(MODE==2'b10) 62 | begin 63 | SHIFT_REG <= SHIFT_REG << 1; 64 | SHIFT_REG[0]<=SHIFT_IN; 65 | end 66 | 67 | if(MODE==2'b11) 68 | begin 69 | SHIFT_IN<=MOSI; 70 | end 71 | end 72 | end 73 | 74 | always @(negedge SCK) 75 | begin 76 | if(SS==0) 77 | begin 78 | if(MODE==2'b00) 79 | begin 80 | SHIFT_REG <= SHIFT_REG << 1; 81 | SHIFT_REG[0]<=SHIFT_IN; 82 | end 83 | if(MODE==2'b01) 84 | begin 85 | SHIFT_IN<=MOSI; 86 | end 87 | if(MODE==2'b10) 88 | begin 89 | SHIFT_IN<=MOSI; 90 | end 91 | if(MODE==2'b11) 92 | begin 93 | SHIFT_REG <= SHIFT_REG << 1; 94 | SHIFT_REG[0]<=SHIFT_IN; 95 | end 96 | end 97 | end 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /SPI_testmodul_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/red435/verilog_APB_SPI_interface/5eef874c23e20e295839f093f4f3c58b2368d2c3/SPI_testmodul_2.v -------------------------------------------------------------------------------- /Simulation_public.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/red435/verilog_APB_SPI_interface/5eef874c23e20e295839f093f4f3c58b2368d2c3/Simulation_public.bmp -------------------------------------------------------------------------------- /system_design.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/red435/verilog_APB_SPI_interface/5eef874c23e20e295839f093f4f3c58b2368d2c3/system_design.jpg -------------------------------------------------------------------------------- /system_hierarchy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/red435/verilog_APB_SPI_interface/5eef874c23e20e295839f093f4f3c58b2368d2c3/system_hierarchy.png --------------------------------------------------------------------------------