├── LICENSE ├── README.md ├── doc └── pic │ └── banner.png ├── examples ├── 1-pl-only │ ├── Makefile.caas │ ├── Makefile.vivado │ ├── README.md │ ├── caas.conf │ ├── caas.vivado.conf │ ├── pynqz1.xdc │ ├── run_caas.sh │ └── top.v ├── 2-fclk │ ├── Makefile.caas │ ├── Makefile.vivado │ ├── README.md │ ├── caas.conf │ ├── fclk.py │ ├── fclk_high.py │ ├── pynqz1.xdc │ ├── run_caas.sh │ └── top.v ├── 3-emio │ ├── Makefile.caas │ ├── README.md │ ├── caas.conf │ ├── emio.c │ ├── emio.py │ ├── lscript.ld │ ├── pynqz1.xdc │ ├── run_arm_gcc.sh │ ├── run_caas.sh │ └── top.v ├── 4-axi │ ├── Makefile.caas │ ├── README.md │ ├── axi.c │ ├── axi.py │ ├── caas.conf │ ├── lscript.ld │ ├── pynqz1.xdc │ ├── run_caas.sh │ └── top.v ├── 5-uart │ ├── README.md │ └── uart.py ├── 6-noddr-sdboot │ ├── Makefile.caas │ ├── README.md │ ├── caas.conf │ ├── output.bif │ ├── pynqz1.xdc │ ├── run_caas.sh │ ├── sdboot.py │ └── top.v └── only-foss-can-do │ └── 1-apu-oc │ ├── README.md │ ├── apu_oc.py │ ├── blinky.c │ ├── lscript.ld │ └── power.png ├── ps7_init_template ├── ps7_init.c ├── ps7_init.h ├── ps7_init.tcl └── xparameters.h ├── tcl_fuzz ├── create-ps7-project-clkonly-2.tcl ├── create-ps7-project-clkonly.tcl ├── create-ps7-project-full-3.tcl ├── create-ps7-project-full-4.tcl ├── create-ps7-project-full-5.tcl ├── create-ps7-project-full.tcl ├── create-ps7-project-noddr-noperiph-clkonly-2uarts.tcl ├── create-ps7-project-noddr-noperiph-clkonly-bankvoltage.tcl ├── create-ps7-project-noddr-noperiph-clkonly-clkfreq-2.tcl ├── create-ps7-project-noddr-noperiph-clkonly-clkfreq.tcl ├── create-ps7-project-noddr-noperiph-clkonly-sd-emio.tcl ├── create-ps7-project-noddr-noperiph-clkonly-sd.tcl ├── create-ps7-project-noddr-noperiph-clkonly-uart-elsegpio.tcl ├── create-ps7-project-noddr-noperiph-clkonly-uart-emio.tcl ├── create-ps7-project-noddr-noperiph-clkonly-uart.tcl ├── hdf │ ├── noddr-0-2uarts │ │ └── ps7_init_gpl.c │ ├── noddr-0-bankvolt │ │ └── ps7_init_gpl.c │ ├── noddr-0-clkfreq-2 │ │ └── ps7_init_gpl.c │ ├── noddr-0-clkfreq │ │ └── ps7_init_gpl.c │ ├── noddr-0-sd-emio │ │ └── ps7_init_gpl.c │ ├── noddr-0-sd │ │ └── ps7_init_gpl.c │ ├── noddr-0-uart-elsegpio │ │ └── ps7_init_gpl.c │ ├── noddr-0-uart-emio │ │ └── ps7_init_gpl.c │ └── noddr-0-uart │ │ └── ps7_init_gpl.c └── note.txt ├── xsct_tools ├── run_elf.tcl └── run_elf_7030.tcl ├── zynq7000.py ├── zynq7000_register_names.py └── zynq7000_user.py /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2025 regymm 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## GenZ: the open-source Zynq 7000 BSP generator 2 | 3 | ![banner](doc/pic/banner.png) 4 | 5 | [Awesome through 2035!](https://www.hackster.io/news/product-lifecycle-extension-for-all-7-series-xilinx-devices-through-2035-4b690dac2d42) 6 | 7 | GenZ is a FOSS BSP generator for the Zynq 7000 Processing System (PS). It emits the `ps7_init.c`, `ps7_init.h` and `xparameters.h` required for FSBL building and PS software development, from a simple, text-based configuration. 8 | 9 | Together with [OpenXC7](https://github.com/openXC7/), [Xilinx embeddedsw](https://github.com/Xilinx/embeddedsw), and [Antmicro zynq-mkbootimage](https://github.com/antmicro/zynq-mkbootimage), full Zynq 7000 PS/PL development can be done with NO PROPRIETY TOOLS. 10 | 11 | ### Get started 12 | 13 | There's a bunch of examples! 14 | 15 | [PL only](./examples/1-pl-only) 16 | 17 | [FCLK / 🔥High FCLK](./examplex/2-fclk) 18 | 19 | [EMIO](./examples/3-emio) 20 | 21 | [AXI](./examples/4-axi) 22 | 23 | [UART / 🔥High-baud UART](./examples/5-uart) 24 | 25 | [🕊️No DDR SD Boot, Fully-free](./examples/6-noddr-sdboot) 26 | 27 | [🔥ARM overclock](./examples/only-foss-can-do/1-apu-oc) 28 | 29 | ### More information 30 | 31 | [This](./examples/6-noddr-sdboot/README.md) contains detailed instructions and backgrounds to use GenZ. 32 | 33 | [This gist](https://gist.github.com/regymm/1265dd6e9885983dc1d9977e42724319) contains my notes for [PrjXray](https://github.com/openXC7/prjxray), the fuzzer for 7-series FPGAs that generate databases for OpenXC7. 34 | 35 | ### Funding 36 | 37 | This project is funded through [NGI0 Entrust](https://nlnet.nl/entrust), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more at the [NLnet project page](https://nlnet.nl/project/PTP-timingcard-gateware). 38 | 39 | [NLnet foundation logo](https://nlnet.nl) [NGI Zero Logo](https://nlnet.nl/entrust) 40 | -------------------------------------------------------------------------------- /doc/pic/banner.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/regymm/GenZ/842a8f6471bd0b0765f24bc2eaaa1d8f82347dde/doc/pic/banner.png -------------------------------------------------------------------------------- /examples/1-pl-only/Makefile.caas: -------------------------------------------------------------------------------- 1 | DB_DIR ?= /nextpnr-xilinx/xilinx/external/prjxray-db 2 | CHIPDB ?= /chipdb 3 | 4 | BUILDDIR := ${CURDIR}/build 5 | TOP := top 6 | #SOURCES := $(wildcard *.v) 7 | XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 8 | 9 | CHIPFAM := zynq7 10 | PART := xc7z020clg400-1 11 | 12 | LOGFILE := ${BUILDDIR}/top.log 13 | 14 | all: ${CHIPDB} ${BUILDDIR} ${BUILDDIR}/top.bit 15 | 16 | ${BUILDDIR}: 17 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 18 | 19 | ${CHIPDB}: 20 | mkdir -m 777 -p ${CHIPDB} && chown -R nobody ${CHIPDB} | true 21 | 22 | # we run this in parent directory to seeminglessly import user source files 23 | # otherwise have to parse user pattern and add ../ 24 | ${BUILDDIR}/top.json: $(wildcard *.v) 25 | yosys -p "synth_xilinx -flatten -abc9 -arch xc7 -top ${TOP}; write_json ${BUILDDIR}/top.json" $^ >> ${LOGFILE} 2>&1 26 | 27 | # The chip database only needs to be generated once 28 | # that is why we don't clean it with make clean 29 | ${CHIPDB}/${PART}.bin: 30 | pypy3 /nextpnr-xilinx/xilinx/python/bbaexport.py --device ${PART} --bba ${PART}.bba 31 | bbasm -l ${PART}.bba ${CHIPDB}/${PART}.bin 32 | rm -f ${PART}.bba 33 | 34 | ${BUILDDIR}/top.fasm: ${BUILDDIR}/top.json ${CHIPDB}/${PART}.bin 35 | nextpnr-xilinx --chipdb ${CHIPDB}/${PART}.bin --xdc ${XDC} --json ${BUILDDIR}/top.json --fasm $@ >> ${LOGFILE} 2>&1 36 | 37 | ${BUILDDIR}/top.frames: ${BUILDDIR}/top.fasm 38 | fasm2frames --part ${PART} --db-root ${DB_DIR}/${CHIPFAM} $< > $@ 39 | 40 | ${BUILDDIR}/top.bit: ${BUILDDIR}/top.frames 41 | xc7frames2bit --part_file ${DB_DIR}/${CHIPFAM}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@ >> ${LOGFILE} 2>&1 42 | 43 | .PHONY: clean 44 | clean: 45 | @rm -f *.bit 46 | @rm -f *.frames 47 | @rm -f *.fasm 48 | @rm -f *.json 49 | -------------------------------------------------------------------------------- /examples/1-pl-only/Makefile.vivado: -------------------------------------------------------------------------------- 1 | BUILDDIR := ${CURDIR}/build 2 | # TOP := top 3 | # SOURCES := $(wildcard *.v) 4 | # XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 5 | 6 | # PART := xc7z020clg400-1 7 | 8 | LOGFILE := ${BUILDDIR}/top.log 9 | 10 | # Build design 11 | all: ${BUILDDIR}/top.bit 12 | 13 | ${BUILDDIR}: 14 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 15 | 16 | .ONESHELL: 17 | ${BUILDDIR}/vivado.tcl: ${BUILDDIR} 18 | cat << EOF > $@ 19 | # vivado.tcl generated for caas 20 | # can be launched from any directory 21 | cd ${BUILDDIR} 22 | create_project -part xc7z020clg400-1 -force v_proj 23 | set_property target_language Verilog [current_project] 24 | cd .. 25 | read_verilog [glob *.v] 26 | read_xdc [glob $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ] 27 | cd build 28 | synth_design -top top 29 | opt_design 30 | place_design 31 | phys_opt_design 32 | route_design 33 | write_bitstream -verbose -force top.bit 34 | # report_utilization -file util.rpt 35 | # report_timing_summary -file timing.rpt 36 | EOF 37 | 38 | ${BUILDDIR}/top.bit: ${BUILDDIR}/vivado.tcl 39 | cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1 40 | 41 | .PHONY: clean 42 | clean: 43 | rm -rf ${BUILDDIR} 44 | -------------------------------------------------------------------------------- /examples/1-pl-only/README.md: -------------------------------------------------------------------------------- 1 | ### 1. PL only bitstream 2 | 3 | This only uses the fabric, with no connection to the ARM part. The PS7 instantiation is optional. 4 | 5 | On PYNQ-Z1, two LEDs will show a counter, and the other two are controlled by SW1/SW0. 6 | 7 | Build and program bitstream: 8 | 9 | ``` 10 | $ ./run_caas.sh 11 | $ openFPGALoader --board arty build/top.bit 12 | ``` 13 | 14 | Optionally, build with Vivado: 15 | 16 | ``` 17 | $ source /opt/Xilinx/Vivado/2019.1/settings64.sh 18 | $ make -f Makefile.vivado 19 | ``` 20 | -------------------------------------------------------------------------------- /examples/1-pl-only/caas.conf: -------------------------------------------------------------------------------- 1 | [caas] 2 | Server = https://caas.symbioticeda.com:18888/ 3 | 4 | [project] 5 | Backend = openxc7 6 | Part = xc7z020clg400-1 7 | -------------------------------------------------------------------------------- /examples/1-pl-only/caas.vivado.conf: -------------------------------------------------------------------------------- 1 | [caas] 2 | Server = https://caas.symbioticeda.com:18888/ 3 | 4 | [project] 5 | Backend = vivado 6 | Part = xc7z020clg400-1 7 | -------------------------------------------------------------------------------- /examples/1-pl-only/pynqz1.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H16 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | 4 | # Switches 5 | set_property PACKAGE_PIN M20 [get_ports {sw[0]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 7 | set_property PACKAGE_PIN M19 [get_ports {sw[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 9 | 10 | # LEDs 11 | set_property PACKAGE_PIN R14 [get_ports {led[0]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 13 | set_property PACKAGE_PIN P14 [get_ports {led[1]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 15 | set_property PACKAGE_PIN N16 [get_ports {led[2]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 17 | set_property PACKAGE_PIN M14 [get_ports {led[3]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 19 | -------------------------------------------------------------------------------- /examples/1-pl-only/run_caas.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -ex 2 | if [[ $(uname -m) == "aarch64" ]]; then 3 | append="-arm" 4 | else 5 | append="" 6 | fi 7 | 8 | docker run --pull never -it --rm -m 8G \ 9 | -v `pwd`:/mnt \ 10 | -v /chipdb:/chipdb \ 11 | --tmpfs /tmp \ 12 | regymm/openxc7${append} make -C /mnt -f Makefile.caas 13 | -------------------------------------------------------------------------------- /examples/1-pl-only/top.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT 2 | 3 | `timescale 1ns / 1ps 4 | //`define NO_PS7 5 | 6 | module top( 7 | input clk, 8 | output [3:0]led, 9 | input [1:0]sw 10 | ); 11 | 12 | reg [31:0]cnt = 0; 13 | always @ (posedge clk) begin 14 | cnt <= cnt + 1; 15 | end 16 | assign led[3:2] = cnt[28:27]; 17 | assign led[1:0] = sw[1:0]; 18 | 19 | `ifndef NO_PS7 20 | PS7 PS7_inst (); 21 | `endif 22 | endmodule 23 | 24 | -------------------------------------------------------------------------------- /examples/2-fclk/Makefile.caas: -------------------------------------------------------------------------------- 1 | DB_DIR ?= /nextpnr-xilinx/xilinx/external/prjxray-db 2 | CHIPDB ?= /chipdb 3 | 4 | BUILDDIR := ${CURDIR}/build 5 | TOP := top 6 | #SOURCES := $(wildcard *.v) 7 | XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 8 | 9 | CHIPFAM := zynq7 10 | PART := xc7z020clg400-1 11 | 12 | LOGFILE := ${BUILDDIR}/top.log 13 | 14 | all: ${CHIPDB} ${BUILDDIR} ${BUILDDIR}/top.bit 15 | 16 | ${BUILDDIR}: 17 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 18 | 19 | ${CHIPDB}: 20 | mkdir -m 777 -p ${CHIPDB} && chown -R nobody ${CHIPDB} | true 21 | 22 | # we run this in parent directory to seeminglessly import user source files 23 | # otherwise have to parse user pattern and add ../ 24 | ${BUILDDIR}/top.json: $(wildcard *.v) 25 | yosys -p "synth_xilinx -flatten -abc9 -arch xc7 -top ${TOP}; write_json ${BUILDDIR}/top.json" $^ >> ${LOGFILE} 2>&1 26 | 27 | # The chip database only needs to be generated once 28 | # that is why we don't clean it with make clean 29 | ${CHIPDB}/${PART}.bin: 30 | pypy3 /nextpnr-xilinx/xilinx/python/bbaexport.py --device ${PART} --bba ${PART}.bba 31 | bbasm -l ${PART}.bba ${CHIPDB}/${PART}.bin 32 | rm -f ${PART}.bba 33 | 34 | ${BUILDDIR}/top.fasm: ${BUILDDIR}/top.json ${CHIPDB}/${PART}.bin 35 | nextpnr-xilinx --chipdb ${CHIPDB}/${PART}.bin --xdc ${XDC} --json ${BUILDDIR}/top.json --fasm $@ >> ${LOGFILE} 2>&1 36 | 37 | ${BUILDDIR}/top.frames: ${BUILDDIR}/top.fasm 38 | fasm2frames --part ${PART} --db-root ${DB_DIR}/${CHIPFAM} $< > $@ 39 | 40 | ${BUILDDIR}/top.bit: ${BUILDDIR}/top.frames 41 | xc7frames2bit --part_file ${DB_DIR}/${CHIPFAM}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@ >> ${LOGFILE} 2>&1 42 | 43 | .PHONY: clean 44 | clean: 45 | @rm -f *.bit 46 | @rm -f *.frames 47 | @rm -f *.fasm 48 | @rm -f *.json 49 | -------------------------------------------------------------------------------- /examples/2-fclk/Makefile.vivado: -------------------------------------------------------------------------------- 1 | BUILDDIR := ${CURDIR}/build 2 | # TOP := top 3 | # SOURCES := $(wildcard *.v) 4 | # XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 5 | 6 | # PART := xc7z020clg400-1 7 | 8 | LOGFILE := ${BUILDDIR}/top.log 9 | 10 | # Build design 11 | all: ${BUILDDIR}/top.bit 12 | 13 | ${BUILDDIR}: 14 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 15 | 16 | .ONESHELL: 17 | ${BUILDDIR}/vivado.tcl: ${BUILDDIR} 18 | cat << EOF > $@ 19 | # vivado.tcl generated for caas 20 | # can be launched from any directory 21 | cd ${BUILDDIR} 22 | create_project -part xc7z020clg400-1 -force v_proj 23 | set_property target_language Verilog [current_project] 24 | cd .. 25 | read_verilog [glob *.v] 26 | read_xdc [glob $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ] 27 | cd build 28 | synth_design -top top 29 | opt_design 30 | place_design 31 | phys_opt_design 32 | route_design 33 | write_bitstream -verbose -force top.bit 34 | # report_utilization -file util.rpt 35 | # report_timing_summary -file timing.rpt 36 | EOF 37 | 38 | ${BUILDDIR}/top.bit: ${BUILDDIR}/vivado.tcl 39 | cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1 40 | 41 | .PHONY: clean 42 | clean: 43 | rm -rf ${BUILDDIR} 44 | -------------------------------------------------------------------------------- /examples/2-fclk/README.md: -------------------------------------------------------------------------------- 1 | ### 2. Using PS FCLK 2 | 3 | The crystal oscillator on many ZYNQ boards only goes to the ARM cores (PS). The FPGA (PL) part uses FCLKs driven by the PS. 4 | 5 | On PYNQ-Z1, four LEDs shows blinky driven by the 4 FCLKs. 6 | 7 | Build and program bitstream: 8 | 9 | ``` 10 | $ ./run_caas.sh 11 | $ openFPGALoader --board arty build/top.bit 12 | ``` 13 | 14 | Probably, you can't see blinky after programming bitstream, this means FCLKs are not turned on, which is the default behaviour after power-on. Also, Linux will disable unused FCLKs ([reference](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841795/Controlling+FCLKs+in+Linux)). 15 | 16 | [GenZ](https://github.com/regymm/GenZ) can then be used to turn the FCLKs on: 17 | 18 | ``` 19 | $ export PYTHONPATH=../.. 20 | $ python3 fclk.py 21 | (Using XSCT) 22 | $ source /opt/Xilinx/Vivado/2019.1/settings64.sh 23 | $ ../../xsct_tools/run_elf_7030.tcl ps7_init_fclk/ps7_init.tcl 24 | (Using OpenOCD) 25 | TODO 26 | ``` 27 | 28 | After configuring the PS FCLKs, 4 LEDs will blinky at different paces (50, 100, 150, and 200 MHz). 29 | 30 | In Vivado, the maximum FCLK frequency is 250 MHz. With Genz, the frequency can be higher (e.g. 400 MHz on 7010/7020, 600 MHz on 7030). `fclk_high.py` generates higher frequencies. 31 | -------------------------------------------------------------------------------- /examples/2-fclk/caas.conf: -------------------------------------------------------------------------------- 1 | [caas] 2 | Server = https://caas.symbioticeda.com:18888/ 3 | 4 | [project] 5 | Backend = openxc7 6 | Part = xc7z020clg400-1 7 | -------------------------------------------------------------------------------- /examples/2-fclk/fclk.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | z7000_ps_param_fclk_on = { 6 | 'freq' : { 'crystal' : 33.333333333, 7 | 'fclk0' : 50, 8 | 'fclk1' : 100, 9 | 'fclk2' : 150, 10 | 'fclk3' : 200 11 | } 12 | } 13 | 14 | if __name__ == '__main__': 15 | z7 = Zynq7000() 16 | z7.param_load(z7000_ps_param_fclk_on) 17 | z7.ps7_init_gen(zynq7_allregisters) 18 | z7.ps7_init_filewrite('./ps7_init_fclk/') 19 | -------------------------------------------------------------------------------- /examples/2-fclk/fclk_high.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | z7000_ps_param_fclk_on = { 6 | 'freq' : { 'crystal' : 33.333333333, 7 | 'fclk0' : 50, 8 | 'fclk1' : 250, 9 | 'fclk2' : 300, 10 | 'fclk3' : 400 11 | } 12 | } 13 | 14 | if __name__ == '__main__': 15 | z7 = Zynq7000() 16 | z7.param_load(z7000_ps_param_fclk_on) 17 | z7.ps7_init_gen(zynq7_allregisters) 18 | z7.ps7_init_filewrite('./ps7_init_fclk_high/') 19 | -------------------------------------------------------------------------------- /examples/2-fclk/pynqz1.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H16 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | 4 | # Switches 5 | set_property PACKAGE_PIN M20 [get_ports {sw[0]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 7 | set_property PACKAGE_PIN M19 [get_ports {sw[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 9 | 10 | # LEDs 11 | set_property PACKAGE_PIN R14 [get_ports {led[0]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 13 | set_property PACKAGE_PIN P14 [get_ports {led[1]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 15 | set_property PACKAGE_PIN N16 [get_ports {led[2]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 17 | set_property PACKAGE_PIN M14 [get_ports {led[3]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 19 | -------------------------------------------------------------------------------- /examples/2-fclk/run_caas.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -ex 2 | if [[ $(uname -m) == "aarch64" ]]; then 3 | append="-arm" 4 | else 5 | append="" 6 | fi 7 | 8 | docker run --pull never -it --rm -m 8G \ 9 | -v `pwd`:/mnt \ 10 | -v /chipdb:/chipdb \ 11 | --tmpfs /tmp \ 12 | regymm/openxc7${append} make -C /mnt -f Makefile.caas 13 | -------------------------------------------------------------------------------- /examples/2-fclk/top.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT 2 | 3 | `timescale 1ns / 1ps 4 | 5 | module top( 6 | input clk, 7 | output [3:0]led, 8 | input [1:0]sw 9 | ); 10 | wire [3:0]FCLK_CLK_unbuffered; 11 | wire [3:0]FCLK_CLK_buffered; 12 | BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0])); 13 | BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1])); 14 | BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2])); 15 | BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3])); 16 | 17 | PS7 PS7_inst ( 18 | .FCLKCLK (FCLK_CLK_unbuffered), 19 | .FCLKRESETN () // software programmable reset, unused in most cases 20 | ); 21 | 22 | reg [31:0]cnt0 = 0; 23 | always @ (posedge FCLK_CLK_buffered[0]) begin 24 | cnt0 <= cnt0 + 1; 25 | end 26 | reg [31:0]cnt1 = 0; 27 | always @ (posedge FCLK_CLK_buffered[1]) begin 28 | cnt1 <= cnt1 + 1; 29 | end 30 | reg [31:0]cnt2 = 0; 31 | always @ (posedge FCLK_CLK_buffered[2]) begin 32 | cnt2 <= cnt2 + 1; 33 | end 34 | reg [31:0]cnt3 = 0; 35 | always @ (posedge FCLK_CLK_buffered[3]) begin 36 | cnt3 <= cnt3 + 1; 37 | end 38 | assign led = {cnt3[27], cnt2[27], cnt1[27], cnt0[27]}; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /examples/3-emio/Makefile.caas: -------------------------------------------------------------------------------- 1 | DB_DIR ?= /nextpnr-xilinx/xilinx/external/prjxray-db 2 | CHIPDB ?= /chipdb 3 | 4 | BUILDDIR := ${CURDIR}/build 5 | TOP := top 6 | #SOURCES := $(wildcard *.v) 7 | XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 8 | 9 | CHIPFAM := zynq7 10 | PART := xc7z020clg400-1 11 | 12 | LOGFILE := ${BUILDDIR}/top.log 13 | 14 | all: ${CHIPDB} ${BUILDDIR} ${BUILDDIR}/top.bit 15 | 16 | ${BUILDDIR}: 17 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 18 | 19 | ${CHIPDB}: 20 | mkdir -m 777 -p ${CHIPDB} && chown -R nobody ${CHIPDB} | true 21 | 22 | # we run this in parent directory to seeminglessly import user source files 23 | # otherwise have to parse user pattern and add ../ 24 | ${BUILDDIR}/top.json: $(wildcard *.v) 25 | yosys -p "synth_xilinx -flatten -abc9 -arch xc7 -top ${TOP}; write_json ${BUILDDIR}/top.json" $^ >> ${LOGFILE} 2>&1 26 | 27 | # The chip database only needs to be generated once 28 | # that is why we don't clean it with make clean 29 | ${CHIPDB}/${PART}.bin: 30 | pypy3 /nextpnr-xilinx/xilinx/python/bbaexport.py --device ${PART} --bba ${PART}.bba 31 | bbasm -l ${PART}.bba ${CHIPDB}/${PART}.bin 32 | rm -f ${PART}.bba 33 | 34 | ${BUILDDIR}/top.fasm: ${BUILDDIR}/top.json ${CHIPDB}/${PART}.bin 35 | nextpnr-xilinx --chipdb ${CHIPDB}/${PART}.bin --xdc ${XDC} --json ${BUILDDIR}/top.json --fasm $@ >> ${LOGFILE} 2>&1 36 | 37 | ${BUILDDIR}/top.frames: ${BUILDDIR}/top.fasm 38 | fasm2frames --part ${PART} --db-root ${DB_DIR}/${CHIPFAM} $< > $@ 39 | 40 | ${BUILDDIR}/top.bit: ${BUILDDIR}/top.frames 41 | xc7frames2bit --part_file ${DB_DIR}/${CHIPFAM}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@ >> ${LOGFILE} 2>&1 42 | 43 | .PHONY: clean 44 | clean: 45 | @rm -f *.bit 46 | @rm -f *.frames 47 | @rm -f *.fasm 48 | @rm -f *.json 49 | -------------------------------------------------------------------------------- /examples/3-emio/README.md: -------------------------------------------------------------------------------- 1 | ### 3. Using EMIO: The simplest PS/PL communication 2 | 3 | On PYNQ-Z1, use switches to control LEDs, but by the ARM cores (PS), via the EMIO interface. This is a PS/PL communication! The 64-bit EMIO is enough for many low-speed purposes. 4 | 5 | It's made of 3 parts: 6 | - Bitstream wires EMIO port directly to SW/LEDs, in the PL fabric. 7 | - GenZ configures the ARM cores (PLL, etc.). 8 | - A ELF file, compiled by the ordinary GCC toolchain, that periodically assigns LEDs to SWs, is loaded to the ARM cores. 9 | 10 | ``` 11 | $ ./run_caas.sh 12 | $ export PYTHONPATH=../.. 13 | $ python3 emio.py 14 | $ arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-T -Wl,lscript.ld emio.c -o emio -nostdlib 15 | (Using XSCT) 16 | $ source /opt/Xilinx/Vivado/2019.1/settings64.sh 17 | $ ../../xsct_tools/run_elf_7030.tcl ps7_init_emio/ps7_init.tcl build/top.bit emio 18 | ``` 19 | 20 | After configuring everything, the two switches will control two LEDs (LD0, LD1) with a small time delay. 21 | 22 | Also, all `PS7` ports are shown in `top.v`. 23 | -------------------------------------------------------------------------------- /examples/3-emio/caas.conf: -------------------------------------------------------------------------------- 1 | [caas] 2 | Server = https://caas.symbioticeda.com:18888/ 3 | 4 | [project] 5 | Backend = openxc7 6 | Part = xc7z020clg400-1 7 | -------------------------------------------------------------------------------- /examples/3-emio/emio.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | 3 | int main() 4 | { 5 | volatile int* gpio2_dirm = (volatile int*)0xe000a284; 6 | volatile int* gpio2_oen = (volatile int*)0xe000a288; 7 | volatile int* gpio2_data_out = (volatile int*)0xe000a048; 8 | volatile int* gpio2_data_in = (volatile int*)0xe000a068; 9 | int out_pins_mask = 0xf; 10 | int in_pins_mask = 0x30; 11 | 12 | *gpio2_dirm = out_pins_mask; 13 | *gpio2_oen = out_pins_mask; 14 | while (1) { 15 | for (int i = 0; i < 20000000; i++); 16 | /**gpio2_data_out = 0x5;*/ 17 | *gpio2_data_out = *gpio2_data_in >> 4; 18 | } 19 | return 0; 20 | } 21 | -------------------------------------------------------------------------------- /examples/3-emio/emio.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | z7000_ps_param_fclk_on = { 6 | 'freq' : { 'crystal' : 33.333333333 7 | } 8 | } 9 | 10 | if __name__ == '__main__': 11 | z7 = Zynq7000() 12 | z7.param_load(z7000_ps_param_fclk_on) 13 | z7.ps7_init_gen(zynq7_allregisters) 14 | z7.ps7_init_filewrite('./ps7_init_emio/') 15 | -------------------------------------------------------------------------------- /examples/3-emio/lscript.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | 3 | SECTIONS 4 | { 5 | . = 0xFFFF0000; 6 | .text : { *(.text) } 7 | .data : { *(.data) } 8 | .bss : { *(.bss) } 9 | } 10 | -------------------------------------------------------------------------------- /examples/3-emio/pynqz1.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H16 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | 4 | # Switches 5 | set_property PACKAGE_PIN M20 [get_ports {sw[0]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 7 | set_property PACKAGE_PIN M19 [get_ports {sw[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 9 | 10 | # LEDs 11 | set_property PACKAGE_PIN R14 [get_ports {led[0]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 13 | set_property PACKAGE_PIN P14 [get_ports {led[1]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 15 | set_property PACKAGE_PIN N16 [get_ports {led[2]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 17 | set_property PACKAGE_PIN M14 [get_ports {led[3]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 19 | -------------------------------------------------------------------------------- /examples/3-emio/run_arm_gcc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-T -Wl,lscript.ld emio.c -o emio -nostdlib 3 | -------------------------------------------------------------------------------- /examples/3-emio/run_caas.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -ex 2 | if [[ $(uname -m) == "aarch64" ]]; then 3 | append="-arm" 4 | else 5 | append="" 6 | fi 7 | 8 | docker run --pull never -it --rm -m 8G \ 9 | -v `pwd`:/mnt \ 10 | -v /chipdb:/chipdb \ 11 | --tmpfs /tmp \ 12 | regymm/openxc7${append} make -C /mnt -f Makefile.caas 13 | -------------------------------------------------------------------------------- /examples/3-emio/top.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT 2 | `timescale 1ns / 1ps 3 | 4 | module top( 5 | input clk, 6 | output [3:0]led, 7 | input [1:0]sw 8 | ); 9 | 10 | reg [31:0]cnt = 0; 11 | always @ (posedge clk) begin 12 | cnt <= cnt + 1; 13 | end 14 | 15 | wire [63:0] emio_gpio_o; 16 | wire [63:0] emio_gpio_t; 17 | wire [63:0] emio_gpio_i; 18 | 19 | assign led = emio_gpio_o[3:0]; 20 | assign emio_gpio_i = {58'b0, sw, 4'b0}; 21 | 22 | //wire [3:0]FCLK_CLK_unbuffered; 23 | //wire [3:0]FCLK_CLK_buffered; 24 | //wire psclk = FCLK_CLK_buffered[0]; 25 | //BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0])); 26 | 27 | PS7 zynq7 ( 28 | .DMA0DATYPE (), 29 | .DMA0DAVALID (), 30 | .DMA0DRREADY (), 31 | .DMA0RSTN (), 32 | .DMA1DATYPE (), 33 | .DMA1DAVALID (), 34 | .DMA1DRREADY (), 35 | .DMA1RSTN (), 36 | .DMA2DATYPE (), 37 | .DMA2DAVALID (), 38 | .DMA2DRREADY (), 39 | .DMA2RSTN (), 40 | .DMA3DATYPE (), 41 | .DMA3DAVALID (), 42 | .DMA3DRREADY (), 43 | .DMA3RSTN (), 44 | .EMIOCAN0PHYTX (), 45 | .EMIOCAN1PHYTX (), 46 | .EMIOENET0GMIITXD (), 47 | .EMIOENET0GMIITXEN (), 48 | .EMIOENET0GMIITXER (), 49 | .EMIOENET0MDIOMDC (), 50 | .EMIOENET0MDIOO (), 51 | .EMIOENET0MDIOTN (), 52 | .EMIOENET0PTPDELAYREQRX (), 53 | .EMIOENET0PTPDELAYREQTX (), 54 | .EMIOENET0PTPPDELAYREQRX (), 55 | .EMIOENET0PTPPDELAYREQTX (), 56 | .EMIOENET0PTPPDELAYRESPRX (), 57 | .EMIOENET0PTPPDELAYRESPTX (), 58 | .EMIOENET0PTPSYNCFRAMERX (), 59 | .EMIOENET0PTPSYNCFRAMETX (), 60 | .EMIOENET0SOFRX (), 61 | .EMIOENET0SOFTX (), 62 | .EMIOENET1GMIITXD (), 63 | .EMIOENET1GMIITXEN (), 64 | .EMIOENET1GMIITXER (), 65 | .EMIOENET1MDIOMDC (), 66 | .EMIOENET1MDIOO (), 67 | .EMIOENET1MDIOTN (), 68 | .EMIOENET1PTPDELAYREQRX (), 69 | .EMIOENET1PTPDELAYREQTX (), 70 | .EMIOENET1PTPPDELAYREQRX (), 71 | .EMIOENET1PTPPDELAYREQTX (), 72 | .EMIOENET1PTPPDELAYRESPRX (), 73 | .EMIOENET1PTPPDELAYRESPTX (), 74 | .EMIOENET1PTPSYNCFRAMERX (), 75 | .EMIOENET1PTPSYNCFRAMETX (), 76 | .EMIOENET1SOFRX (), 77 | .EMIOENET1SOFTX (), 78 | .EMIOGPIOO (emio_gpio_o), 79 | .EMIOGPIOTN (emio_gpio_t), 80 | .EMIOI2C0SCLO (), 81 | .EMIOI2C0SCLTN (), 82 | .EMIOI2C0SDAO (), 83 | .EMIOI2C0SDATN (), 84 | .EMIOI2C1SCLO (), 85 | .EMIOI2C1SCLTN (), 86 | .EMIOI2C1SDAO (), 87 | .EMIOI2C1SDATN (), 88 | .EMIOPJTAGTDO (), 89 | .EMIOPJTAGTDTN (), 90 | .EMIOSDIO0BUSPOW (), 91 | .EMIOSDIO0BUSVOLT (), 92 | .EMIOSDIO0CLK (), 93 | .EMIOSDIO0CMDO (), 94 | .EMIOSDIO0CMDTN (), 95 | .EMIOSDIO0DATAO (), 96 | .EMIOSDIO0DATATN (), 97 | .EMIOSDIO0LED (), 98 | .EMIOSDIO1BUSPOW (), 99 | .EMIOSDIO1BUSVOLT (), 100 | .EMIOSDIO1CLK (), 101 | .EMIOSDIO1CMDO (), 102 | .EMIOSDIO1CMDTN (), 103 | .EMIOSDIO1DATAO (), 104 | .EMIOSDIO1DATATN (), 105 | .EMIOSDIO1LED (), 106 | .EMIOSPI0MO (), 107 | .EMIOSPI0MOTN (), 108 | .EMIOSPI0SCLKO (), 109 | .EMIOSPI0SCLKTN (), 110 | .EMIOSPI0SO (), 111 | .EMIOSPI0SSNTN (), 112 | .EMIOSPI0SSON (), 113 | .EMIOSPI0STN (), 114 | .EMIOSPI1MO (), 115 | .EMIOSPI1MOTN (), 116 | .EMIOSPI1SCLKO (), 117 | .EMIOSPI1SCLKTN (), 118 | .EMIOSPI1SO (), 119 | .EMIOSPI1SSNTN (), 120 | .EMIOSPI1SSON (), 121 | .EMIOSPI1STN (), 122 | .EMIOTRACECTL (), 123 | .EMIOTRACEDATA (), 124 | .EMIOTTC0WAVEO (), 125 | .EMIOTTC1WAVEO (), 126 | .EMIOUART0DTRN (), 127 | .EMIOUART0RTSN (), 128 | .EMIOUART0TX (), 129 | .EMIOUART1DTRN (), 130 | .EMIOUART1RTSN (), 131 | .EMIOUART1TX (), 132 | .EMIOUSB0PORTINDCTL (), 133 | .EMIOUSB0VBUSPWRSELECT (), 134 | .EMIOUSB1PORTINDCTL (), 135 | .EMIOUSB1VBUSPWRSELECT (), 136 | .EMIOWDTRSTO (), 137 | .EVENTEVENTO (), 138 | .EVENTSTANDBYWFE (), 139 | .EVENTSTANDBYWFI (), 140 | .FCLKCLK (FCLK_CLK_unbuffered), 141 | .FCLKRESETN (), 142 | .FTMTF2PTRIGACK (), 143 | .FTMTP2FDEBUG (), 144 | .FTMTP2FTRIG (), 145 | .IRQP2F (), 146 | .MAXIGP0ARADDR (), 147 | .MAXIGP0ARBURST (), 148 | .MAXIGP0ARCACHE (), 149 | .MAXIGP0ARESETN (), 150 | .MAXIGP0ARID (), 151 | .MAXIGP0ARLEN (), 152 | .MAXIGP0ARLOCK (), 153 | .MAXIGP0ARPROT (), 154 | .MAXIGP0ARQOS (), 155 | .MAXIGP0ARSIZE (), 156 | .MAXIGP0ARVALID (), 157 | .MAXIGP0AWADDR (), 158 | .MAXIGP0AWBURST (), 159 | .MAXIGP0AWCACHE (), 160 | .MAXIGP0AWID (), 161 | .MAXIGP0AWLEN (), 162 | .MAXIGP0AWLOCK (), 163 | .MAXIGP0AWPROT (), 164 | .MAXIGP0AWQOS (), 165 | .MAXIGP0AWSIZE (), 166 | .MAXIGP0AWVALID (), 167 | .MAXIGP0BREADY (), 168 | .MAXIGP0RREADY (), 169 | .MAXIGP0WDATA (), 170 | .MAXIGP0WID (), 171 | .MAXIGP0WLAST (), 172 | .MAXIGP0WSTRB (), 173 | .MAXIGP0WVALID (), 174 | .MAXIGP1ARADDR (), 175 | .MAXIGP1ARBURST (), 176 | .MAXIGP1ARCACHE (), 177 | .MAXIGP1ARESETN (), 178 | .MAXIGP1ARID (), 179 | .MAXIGP1ARLEN (), 180 | .MAXIGP1ARLOCK (), 181 | .MAXIGP1ARPROT (), 182 | .MAXIGP1ARQOS (), 183 | .MAXIGP1ARSIZE (), 184 | .MAXIGP1ARVALID (), 185 | .MAXIGP1AWADDR (), 186 | .MAXIGP1AWBURST (), 187 | .MAXIGP1AWCACHE (), 188 | .MAXIGP1AWID (), 189 | .MAXIGP1AWLEN (), 190 | .MAXIGP1AWLOCK (), 191 | .MAXIGP1AWPROT (), 192 | .MAXIGP1AWQOS (), 193 | .MAXIGP1AWSIZE (), 194 | .MAXIGP1AWVALID (), 195 | .MAXIGP1BREADY (), 196 | .MAXIGP1RREADY (), 197 | .MAXIGP1WDATA (), 198 | .MAXIGP1WID (), 199 | .MAXIGP1WLAST (), 200 | .MAXIGP1WSTRB (), 201 | .MAXIGP1WVALID (), 202 | .SAXIACPARESETN (), 203 | .SAXIACPARREADY (), 204 | .SAXIACPAWREADY (), 205 | .SAXIACPBID (), 206 | .SAXIACPBRESP (), 207 | .SAXIACPBVALID (), 208 | .SAXIACPRDATA (), 209 | .SAXIACPRID (), 210 | .SAXIACPRLAST (), 211 | .SAXIACPRRESP (), 212 | .SAXIACPRVALID (), 213 | .SAXIACPWREADY (), 214 | .SAXIGP0ARESETN (), 215 | .SAXIGP0ARREADY (), 216 | .SAXIGP0AWREADY (), 217 | .SAXIGP0BID (), 218 | .SAXIGP0BRESP (), 219 | .SAXIGP0BVALID (), 220 | .SAXIGP0RDATA (), 221 | .SAXIGP0RID (), 222 | .SAXIGP0RLAST (), 223 | .SAXIGP0RRESP (), 224 | .SAXIGP0RVALID (), 225 | .SAXIGP0WREADY (), 226 | .SAXIGP1ARESETN (), 227 | .SAXIGP1ARREADY (), 228 | .SAXIGP1AWREADY (), 229 | .SAXIGP1BID (), 230 | .SAXIGP1BRESP (), 231 | .SAXIGP1BVALID (), 232 | .SAXIGP1RDATA (), 233 | .SAXIGP1RID (), 234 | .SAXIGP1RLAST (), 235 | .SAXIGP1RRESP (), 236 | .SAXIGP1RVALID (), 237 | .SAXIGP1WREADY (), 238 | .SAXIHP0ARESETN (), 239 | .SAXIHP0ARREADY (), 240 | .SAXIHP0AWREADY (), 241 | .SAXIHP0BID (), 242 | .SAXIHP0BRESP (), 243 | .SAXIHP0BVALID (), 244 | .SAXIHP0RACOUNT (), 245 | .SAXIHP0RCOUNT (), 246 | .SAXIHP0RDATA (), 247 | .SAXIHP0RID (), 248 | .SAXIHP0RLAST (), 249 | .SAXIHP0RRESP (), 250 | .SAXIHP0RVALID (), 251 | .SAXIHP0WACOUNT (), 252 | .SAXIHP0WCOUNT (), 253 | .SAXIHP0WREADY (), 254 | .SAXIHP1ARESETN (), 255 | .SAXIHP1ARREADY (), 256 | .SAXIHP1AWREADY (), 257 | .SAXIHP1BID (), 258 | .SAXIHP1BRESP (), 259 | .SAXIHP1BVALID (), 260 | .SAXIHP1RACOUNT (), 261 | .SAXIHP1RCOUNT (), 262 | .SAXIHP1RDATA (), 263 | .SAXIHP1RID (), 264 | .SAXIHP1RLAST (), 265 | .SAXIHP1RRESP (), 266 | .SAXIHP1RVALID (), 267 | .SAXIHP1WACOUNT (), 268 | .SAXIHP1WCOUNT (), 269 | .SAXIHP1WREADY (), 270 | .SAXIHP2ARESETN (), 271 | .SAXIHP2ARREADY (), 272 | .SAXIHP2AWREADY (), 273 | .SAXIHP2BID (), 274 | .SAXIHP2BRESP (), 275 | .SAXIHP2BVALID (), 276 | .SAXIHP2RACOUNT (), 277 | .SAXIHP2RCOUNT (), 278 | .SAXIHP2RDATA (), 279 | .SAXIHP2RID (), 280 | .SAXIHP2RLAST (), 281 | .SAXIHP2RRESP (), 282 | .SAXIHP2RVALID (), 283 | .SAXIHP2WACOUNT (), 284 | .SAXIHP2WCOUNT (), 285 | .SAXIHP2WREADY (), 286 | .SAXIHP3ARESETN (), 287 | .SAXIHP3ARREADY (), 288 | .SAXIHP3AWREADY (), 289 | .SAXIHP3BID (), 290 | .SAXIHP3BRESP (), 291 | .SAXIHP3BVALID (), 292 | .SAXIHP3RACOUNT (), 293 | .SAXIHP3RCOUNT (), 294 | .SAXIHP3RDATA (), 295 | .SAXIHP3RID (), 296 | .SAXIHP3RLAST (), 297 | .SAXIHP3RRESP (), 298 | .SAXIHP3RVALID (), 299 | .SAXIHP3WACOUNT (), 300 | .SAXIHP3WCOUNT (), 301 | .SAXIHP3WREADY (), 302 | .DDRA (), 303 | .DDRBA (), 304 | .DDRCASB (), 305 | .DDRCKE (), 306 | .DDRCKN (), 307 | .DDRCKP (), 308 | .DDRCSB (), 309 | .DDRDM (), 310 | .DDRDQ (), 311 | .DDRDQSN (), 312 | .DDRDQSP (), 313 | .DDRDRSTB (), 314 | .DDRODT (), 315 | .DDRRASB (), 316 | .DDRVRN (), 317 | .DDRVRP (), 318 | .DDRWEB (), 319 | .MIO (), 320 | .PSCLK (), 321 | .PSPORB (), 322 | .PSSRSTB (), 323 | .DDRARB (), 324 | .DMA0ACLK (), 325 | .DMA0DAREADY (), 326 | .DMA0DRLAST (), 327 | .DMA0DRTYPE (), 328 | .DMA0DRVALID (), 329 | .DMA1ACLK (), 330 | .DMA1DAREADY (), 331 | .DMA1DRLAST (), 332 | .DMA1DRTYPE (), 333 | .DMA1DRVALID (), 334 | .DMA2ACLK (), 335 | .DMA2DAREADY (), 336 | .DMA2DRLAST (), 337 | .DMA2DRTYPE (), 338 | .DMA2DRVALID (), 339 | .DMA3ACLK (), 340 | .DMA3DAREADY (), 341 | .DMA3DRLAST (), 342 | .DMA3DRTYPE (), 343 | .DMA3DRVALID (), 344 | .EMIOCAN0PHYRX (), 345 | .EMIOCAN1PHYRX (), 346 | .EMIOENET0EXTINTIN (), 347 | .EMIOENET0GMIICOL (), 348 | .EMIOENET0GMIICRS (), 349 | .EMIOENET0GMIIRXCLK (), 350 | .EMIOENET0GMIIRXD (), 351 | .EMIOENET0GMIIRXDV (), 352 | .EMIOENET0GMIIRXER (), 353 | .EMIOENET0GMIITXCLK (), 354 | .EMIOENET0MDIOI (), 355 | .EMIOENET1EXTINTIN (), 356 | .EMIOENET1GMIICOL (), 357 | .EMIOENET1GMIICRS (), 358 | .EMIOENET1GMIIRXCLK (), 359 | .EMIOENET1GMIIRXD (), 360 | .EMIOENET1GMIIRXDV (), 361 | .EMIOENET1GMIIRXER (), 362 | .EMIOENET1GMIITXCLK (), 363 | .EMIOENET1MDIOI (), 364 | .EMIOGPIOI (emio_gpio_i), 365 | .EMIOI2C0SCLI (), 366 | .EMIOI2C0SDAI (), 367 | .EMIOI2C1SCLI (), 368 | .EMIOI2C1SDAI (), 369 | .EMIOPJTAGTCK (), 370 | .EMIOPJTAGTDI (), 371 | .EMIOPJTAGTMS (), 372 | .EMIOSDIO0CDN (), 373 | .EMIOSDIO0CLKFB (), 374 | .EMIOSDIO0CMDI (), 375 | .EMIOSDIO0DATAI (), 376 | .EMIOSDIO0WP (), 377 | .EMIOSDIO1CDN (), 378 | .EMIOSDIO1CLKFB (), 379 | .EMIOSDIO1CMDI (), 380 | .EMIOSDIO1DATAI (), 381 | .EMIOSDIO1WP (), 382 | .EMIOSPI0MI (), 383 | .EMIOSPI0SCLKI (), 384 | .EMIOSPI0SI (), 385 | .EMIOSPI0SSIN (), 386 | .EMIOSPI1MI (), 387 | .EMIOSPI1SCLKI (), 388 | .EMIOSPI1SI (), 389 | .EMIOSPI1SSIN (), 390 | .EMIOSRAMINTIN (), 391 | .EMIOTRACECLK (), 392 | .EMIOTTC0CLKI (), 393 | .EMIOTTC1CLKI (), 394 | .EMIOUART0CTSN (), 395 | .EMIOUART0DCDN (), 396 | .EMIOUART0DSRN (), 397 | .EMIOUART0RIN (), 398 | .EMIOUART0RX (), 399 | .EMIOUART1CTSN (), 400 | .EMIOUART1DCDN (), 401 | .EMIOUART1DSRN (), 402 | .EMIOUART1RIN (), 403 | .EMIOUART1RX (), 404 | .EMIOUSB0VBUSPWRFAULT (), 405 | .EMIOUSB1VBUSPWRFAULT (), 406 | .EMIOWDTCLKI (), 407 | .EVENTEVENTI (), 408 | .FCLKCLKTRIGN (), 409 | .FPGAIDLEN (), 410 | .FTMDTRACEINATID (), 411 | .FTMDTRACEINCLOCK (), 412 | .FTMDTRACEINDATA (), 413 | .FTMDTRACEINVALID (), 414 | .FTMTF2PDEBUG (), 415 | .FTMTF2PTRIG (), 416 | .FTMTP2FTRIGACK (), 417 | .IRQF2P (), 418 | .MAXIGP0ACLK (), 419 | .MAXIGP0ARREADY (), 420 | .MAXIGP0AWREADY (), 421 | .MAXIGP0BID (), 422 | .MAXIGP0BRESP (), 423 | .MAXIGP0BVALID (), 424 | .MAXIGP0RDATA (), 425 | .MAXIGP0RID (), 426 | .MAXIGP0RLAST (), 427 | .MAXIGP0RRESP (), 428 | .MAXIGP0RVALID (), 429 | .MAXIGP0WREADY (), 430 | .MAXIGP1ACLK (), 431 | .MAXIGP1ARREADY (), 432 | .MAXIGP1AWREADY (), 433 | .MAXIGP1BID (), 434 | .MAXIGP1BRESP (), 435 | .MAXIGP1BVALID (), 436 | .MAXIGP1RDATA (), 437 | .MAXIGP1RID (), 438 | .MAXIGP1RLAST (), 439 | .MAXIGP1RRESP (), 440 | .MAXIGP1RVALID (), 441 | .MAXIGP1WREADY (), 442 | .SAXIACPACLK (), 443 | .SAXIACPARADDR (), 444 | .SAXIACPARBURST (), 445 | .SAXIACPARCACHE (), 446 | .SAXIACPARID (), 447 | .SAXIACPARLEN (), 448 | .SAXIACPARLOCK (), 449 | .SAXIACPARPROT (), 450 | .SAXIACPARQOS (), 451 | .SAXIACPARSIZE (), 452 | .SAXIACPARUSER (), 453 | .SAXIACPARVALID (), 454 | .SAXIACPAWADDR (), 455 | .SAXIACPAWBURST (), 456 | .SAXIACPAWCACHE (), 457 | .SAXIACPAWID (), 458 | .SAXIACPAWLEN (), 459 | .SAXIACPAWLOCK (), 460 | .SAXIACPAWPROT (), 461 | .SAXIACPAWQOS (), 462 | .SAXIACPAWSIZE (), 463 | .SAXIACPAWUSER (), 464 | .SAXIACPAWVALID (), 465 | .SAXIACPBREADY (), 466 | .SAXIACPRREADY (), 467 | .SAXIACPWDATA (), 468 | .SAXIACPWID (), 469 | .SAXIACPWLAST (), 470 | .SAXIACPWSTRB (), 471 | .SAXIACPWVALID (), 472 | .SAXIGP0ACLK (), 473 | .SAXIGP0ARADDR (), 474 | .SAXIGP0ARBURST (), 475 | .SAXIGP0ARCACHE (), 476 | .SAXIGP0ARID (), 477 | .SAXIGP0ARLEN (), 478 | .SAXIGP0ARLOCK (), 479 | .SAXIGP0ARPROT (), 480 | .SAXIGP0ARQOS (), 481 | .SAXIGP0ARSIZE (), 482 | .SAXIGP0ARVALID (), 483 | .SAXIGP0AWADDR (), 484 | .SAXIGP0AWBURST (), 485 | .SAXIGP0AWCACHE (), 486 | .SAXIGP0AWID (), 487 | .SAXIGP0AWLEN (), 488 | .SAXIGP0AWLOCK (), 489 | .SAXIGP0AWPROT (), 490 | .SAXIGP0AWQOS (), 491 | .SAXIGP0AWSIZE (), 492 | .SAXIGP0AWVALID (), 493 | .SAXIGP0BREADY (), 494 | .SAXIGP0RREADY (), 495 | .SAXIGP0WDATA (), 496 | .SAXIGP0WID (), 497 | .SAXIGP0WLAST (), 498 | .SAXIGP0WSTRB (), 499 | .SAXIGP0WVALID (), 500 | .SAXIGP1ACLK (), 501 | .SAXIGP1ARADDR (), 502 | .SAXIGP1ARBURST (), 503 | .SAXIGP1ARCACHE (), 504 | .SAXIGP1ARID (), 505 | .SAXIGP1ARLEN (), 506 | .SAXIGP1ARLOCK (), 507 | .SAXIGP1ARPROT (), 508 | .SAXIGP1ARQOS (), 509 | .SAXIGP1ARSIZE (), 510 | .SAXIGP1ARVALID (), 511 | .SAXIGP1AWADDR (), 512 | .SAXIGP1AWBURST (), 513 | .SAXIGP1AWCACHE (), 514 | .SAXIGP1AWID (), 515 | .SAXIGP1AWLEN (), 516 | .SAXIGP1AWLOCK (), 517 | .SAXIGP1AWPROT (), 518 | .SAXIGP1AWQOS (), 519 | .SAXIGP1AWSIZE (), 520 | .SAXIGP1AWVALID (), 521 | .SAXIGP1BREADY (), 522 | .SAXIGP1RREADY (), 523 | .SAXIGP1WDATA (), 524 | .SAXIGP1WID (), 525 | .SAXIGP1WLAST (), 526 | .SAXIGP1WSTRB (), 527 | .SAXIGP1WVALID (), 528 | .SAXIHP0ACLK (), 529 | .SAXIHP0ARADDR (), 530 | .SAXIHP0ARBURST (), 531 | .SAXIHP0ARCACHE (), 532 | .SAXIHP0ARID (), 533 | .SAXIHP0ARLEN (), 534 | .SAXIHP0ARLOCK (), 535 | .SAXIHP0ARPROT (), 536 | .SAXIHP0ARQOS (), 537 | .SAXIHP0ARSIZE (), 538 | .SAXIHP0ARVALID (), 539 | .SAXIHP0AWADDR (), 540 | .SAXIHP0AWBURST (), 541 | .SAXIHP0AWCACHE (), 542 | .SAXIHP0AWID (), 543 | .SAXIHP0AWLEN (), 544 | .SAXIHP0AWLOCK (), 545 | .SAXIHP0AWPROT (), 546 | .SAXIHP0AWQOS (), 547 | .SAXIHP0AWSIZE (), 548 | .SAXIHP0AWVALID (), 549 | .SAXIHP0BREADY (), 550 | .SAXIHP0RDISSUECAP1EN (), 551 | .SAXIHP0RREADY (), 552 | .SAXIHP0WDATA (), 553 | .SAXIHP0WID (), 554 | .SAXIHP0WLAST (), 555 | .SAXIHP0WRISSUECAP1EN (), 556 | .SAXIHP0WSTRB (), 557 | .SAXIHP0WVALID (), 558 | .SAXIHP1ACLK (), 559 | .SAXIHP1ARADDR (), 560 | .SAXIHP1ARBURST (), 561 | .SAXIHP1ARCACHE (), 562 | .SAXIHP1ARID (), 563 | .SAXIHP1ARLEN (), 564 | .SAXIHP1ARLOCK (), 565 | .SAXIHP1ARPROT (), 566 | .SAXIHP1ARQOS (), 567 | .SAXIHP1ARSIZE (), 568 | .SAXIHP1ARVALID (), 569 | .SAXIHP1AWADDR (), 570 | .SAXIHP1AWBURST (), 571 | .SAXIHP1AWCACHE (), 572 | .SAXIHP1AWID (), 573 | .SAXIHP1AWLEN (), 574 | .SAXIHP1AWLOCK (), 575 | .SAXIHP1AWPROT (), 576 | .SAXIHP1AWQOS (), 577 | .SAXIHP1AWSIZE (), 578 | .SAXIHP1AWVALID (), 579 | .SAXIHP1BREADY (), 580 | .SAXIHP1RDISSUECAP1EN (), 581 | .SAXIHP1RREADY (), 582 | .SAXIHP1WDATA (), 583 | .SAXIHP1WID (), 584 | .SAXIHP1WLAST (), 585 | .SAXIHP1WRISSUECAP1EN (), 586 | .SAXIHP1WSTRB (), 587 | .SAXIHP1WVALID (), 588 | .SAXIHP2ACLK (), 589 | .SAXIHP2ARADDR (), 590 | .SAXIHP2ARBURST (), 591 | .SAXIHP2ARCACHE (), 592 | .SAXIHP2ARID (), 593 | .SAXIHP2ARLEN (), 594 | .SAXIHP2ARLOCK (), 595 | .SAXIHP2ARPROT (), 596 | .SAXIHP2ARQOS (), 597 | .SAXIHP2ARSIZE (), 598 | .SAXIHP2ARVALID (), 599 | .SAXIHP2AWADDR (), 600 | .SAXIHP2AWBURST (), 601 | .SAXIHP2AWCACHE (), 602 | .SAXIHP2AWID (), 603 | .SAXIHP2AWLEN (), 604 | .SAXIHP2AWLOCK (), 605 | .SAXIHP2AWPROT (), 606 | .SAXIHP2AWQOS (), 607 | .SAXIHP2AWSIZE (), 608 | .SAXIHP2AWVALID (), 609 | .SAXIHP2BREADY (), 610 | .SAXIHP2RDISSUECAP1EN (), 611 | .SAXIHP2RREADY (), 612 | .SAXIHP2WDATA (), 613 | .SAXIHP2WID (), 614 | .SAXIHP2WLAST (), 615 | .SAXIHP2WRISSUECAP1EN (), 616 | .SAXIHP2WSTRB (), 617 | .SAXIHP2WVALID (), 618 | .SAXIHP3ACLK (), 619 | .SAXIHP3ARADDR (), 620 | .SAXIHP3ARBURST (), 621 | .SAXIHP3ARCACHE (), 622 | .SAXIHP3ARID (), 623 | .SAXIHP3ARLEN (), 624 | .SAXIHP3ARLOCK (), 625 | .SAXIHP3ARPROT (), 626 | .SAXIHP3ARQOS (), 627 | .SAXIHP3ARSIZE (), 628 | .SAXIHP3ARVALID (), 629 | .SAXIHP3AWADDR (), 630 | .SAXIHP3AWBURST (), 631 | .SAXIHP3AWCACHE (), 632 | .SAXIHP3AWID (), 633 | .SAXIHP3AWLEN (), 634 | .SAXIHP3AWLOCK (), 635 | .SAXIHP3AWPROT (), 636 | .SAXIHP3AWQOS (), 637 | .SAXIHP3AWSIZE (), 638 | .SAXIHP3AWVALID (), 639 | .SAXIHP3BREADY (), 640 | .SAXIHP3RDISSUECAP1EN (), 641 | .SAXIHP3RREADY (), 642 | .SAXIHP3WDATA (), 643 | .SAXIHP3WID (), 644 | .SAXIHP3WLAST (), 645 | .SAXIHP3WRISSUECAP1EN (), 646 | .SAXIHP3WSTRB (), 647 | .SAXIHP3WVALID () 648 | ); 649 | 650 | endmodule 651 | 652 | -------------------------------------------------------------------------------- /examples/4-axi/Makefile.caas: -------------------------------------------------------------------------------- 1 | DB_DIR ?= /nextpnr-xilinx/xilinx/external/prjxray-db 2 | CHIPDB ?= /chipdb 3 | 4 | BUILDDIR := ${CURDIR}/build 5 | TOP := top 6 | #SOURCES := $(wildcard *.v) 7 | XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 8 | 9 | CHIPFAM := zynq7 10 | PART := xc7z020clg400-1 11 | 12 | LOGFILE := ${BUILDDIR}/top.log 13 | 14 | all: ${CHIPDB} ${BUILDDIR} ${BUILDDIR}/top.bit 15 | 16 | ${BUILDDIR}: 17 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 18 | 19 | ${CHIPDB}: 20 | mkdir -m 777 -p ${CHIPDB} && chown -R nobody ${CHIPDB} | true 21 | 22 | # we run this in parent directory to seeminglessly import user source files 23 | # otherwise have to parse user pattern and add ../ 24 | ${BUILDDIR}/top.json: $(wildcard *.v) 25 | yosys -p "synth_xilinx -flatten -abc9 -arch xc7 -top ${TOP}; write_json ${BUILDDIR}/top.json" $^ >> ${LOGFILE} 2>&1 26 | 27 | # The chip database only needs to be generated once 28 | # that is why we don't clean it with make clean 29 | ${CHIPDB}/${PART}.bin: 30 | pypy3 /nextpnr-xilinx/xilinx/python/bbaexport.py --device ${PART} --bba ${PART}.bba 31 | bbasm -l ${PART}.bba ${CHIPDB}/${PART}.bin 32 | rm -f ${PART}.bba 33 | 34 | ${BUILDDIR}/top.fasm: ${BUILDDIR}/top.json ${CHIPDB}/${PART}.bin 35 | nextpnr-xilinx --chipdb ${CHIPDB}/${PART}.bin --xdc ${XDC} --json ${BUILDDIR}/top.json --fasm $@ >> ${LOGFILE} 2>&1 36 | 37 | ${BUILDDIR}/top.frames: ${BUILDDIR}/top.fasm 38 | fasm2frames --part ${PART} --db-root ${DB_DIR}/${CHIPFAM} $< > $@ 39 | 40 | ${BUILDDIR}/top.bit: ${BUILDDIR}/top.frames 41 | xc7frames2bit --part_file ${DB_DIR}/${CHIPFAM}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@ >> ${LOGFILE} 2>&1 42 | 43 | .PHONY: clean 44 | clean: 45 | @rm -f *.bit 46 | @rm -f *.frames 47 | @rm -f *.fasm 48 | @rm -f *.json 49 | -------------------------------------------------------------------------------- /examples/4-axi/README.md: -------------------------------------------------------------------------------- 1 | ### 4. Using AXI: Gateway to real applications 2 | 3 | Using the M_AXI_GP ports from ARM. Minimal AXI device is implemented in the PL, to test AXI transactions emitted by the ARM core as a host. If your complex AXI device doesn't work, this is the basics to check with! 4 | 5 | It's made of 3 parts: 6 | - Bitstream contains two minimal AXI devices for M_AXI_GP0 and M_AXI_GP1 -- one reads back the writen data, and one reads back a constant. 7 | - GenZ configures the ARM cores (PLL, FCLK, EMIO, etc.). 8 | - A ELF file running in ARM cores, that interacts with the AXI devices in PL -- at 0x40000000 and 0x80000000 (UG585, chap. 4.1). 9 | 10 | ``` 11 | $ ./run_caas.sh 12 | $ export PYTHONPATH=../.. 13 | $ python3 axi.py 14 | $ arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-T -Wl,lscript.ld axi.c -o axi -nostdlib 15 | (Using XSCT) 16 | $ source /opt/Xilinx/Vivado/2019.1/settings64.sh 17 | $ ../../xsct_tools/run_elf_7030.tcl ps7_init_axi/ps7_init.tcl build/top.bit axi 18 | ``` 19 | 20 | The upper (left) two LEDs should be on, indication EMIO is working and AXI transactions have finished. 21 | The lower (right) two LEDs should be off, indicating no error. If 4 LEDs are all on, then probably an AXI transaction hung the ARM cores. In this case, a reset to the ARM cores or a powercycle is needed. 22 | -------------------------------------------------------------------------------- /examples/4-axi/axi.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | 3 | int main() 4 | { 5 | volatile int* gpio2_dirm = (volatile int*)0xe000a284; 6 | volatile int* gpio2_oen = (volatile int*)0xe000a288; 7 | volatile int* gpio2_data_out = (volatile int*)0xe000a048; 8 | volatile int* gpio2_data_in = (volatile int*)0xe000a068; 9 | volatile int* m_axi_gp0 = (volatile int*)0x40000000; 10 | volatile int* m_axi_gp1 = (volatile int*)0x80000000; 11 | int out_pins_mask = 0xf; 12 | int in_pins_mask = 0x30; 13 | 14 | *gpio2_dirm = out_pins_mask; 15 | *gpio2_oen = out_pins_mask; 16 | *gpio2_data_out = 0xf; 17 | int i = 0x12341234; 18 | int err0 = 0; 19 | int err1 = 0; 20 | *m_axi_gp0 = i; 21 | *m_axi_gp1 = i; 22 | err0 = (*m_axi_gp0 == i); 23 | err1 = (*m_axi_gp1 == 0xabcdabcd); 24 | while (1) { 25 | *gpio2_data_out = (1<<3) + (1<<2) + (!err1<<1) + !err0; 26 | i++; 27 | } 28 | return 0; 29 | } 30 | -------------------------------------------------------------------------------- /examples/4-axi/axi.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | z7000_ps_param_fclk_on = { 6 | 'freq' : { 'crystal' : 33.333333333, 7 | 'fclk0' : 50, 8 | 'fclk1' : 100 9 | } 10 | } 11 | 12 | if __name__ == '__main__': 13 | z7 = Zynq7000() 14 | z7.param_load(z7000_ps_param_fclk_on) 15 | z7.ps7_init_gen(zynq7_allregisters) 16 | z7.ps7_init_filewrite('./ps7_init_axi/') 17 | -------------------------------------------------------------------------------- /examples/4-axi/caas.conf: -------------------------------------------------------------------------------- 1 | [caas] 2 | Server = https://caas.symbioticeda.com:18888/ 3 | 4 | [project] 5 | Backend = openxc7 6 | Part = xc7z020clg400-1 7 | -------------------------------------------------------------------------------- /examples/4-axi/lscript.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | 3 | SECTIONS 4 | { 5 | . = 0xFFFF0000; 6 | .text : { *(.text) } 7 | .data : { *(.data) } 8 | .bss : { *(.bss) } 9 | } 10 | -------------------------------------------------------------------------------- /examples/4-axi/pynqz1.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H16 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | 4 | # Switches 5 | set_property PACKAGE_PIN M20 [get_ports {sw[0]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 7 | set_property PACKAGE_PIN M19 [get_ports {sw[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 9 | 10 | # LEDs 11 | set_property PACKAGE_PIN R14 [get_ports {led[0]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 13 | set_property PACKAGE_PIN P14 [get_ports {led[1]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 15 | set_property PACKAGE_PIN N16 [get_ports {led[2]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 17 | set_property PACKAGE_PIN M14 [get_ports {led[3]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 19 | -------------------------------------------------------------------------------- /examples/4-axi/run_caas.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -ex 2 | if [[ $(uname -m) == "aarch64" ]]; then 3 | append="-arm" 4 | else 5 | append="" 6 | fi 7 | 8 | docker run --pull never -it --rm -m 8G \ 9 | -v `pwd`:/mnt \ 10 | -v /chipdb:/chipdb \ 11 | --tmpfs /tmp \ 12 | regymm/openxc7${append} make -C /mnt -f Makefile.caas 13 | -------------------------------------------------------------------------------- /examples/4-axi/top.v: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT 2 | `timescale 1ns / 1ps 3 | 4 | module top( 5 | input clk, 6 | output [3:0]led, 7 | input [1:0]sw 8 | ); 9 | 10 | wire [63:0] emio_gpio_o; 11 | wire [63:0] emio_gpio_t; 12 | wire [63:0] emio_gpio_i; 13 | 14 | assign led = emio_gpio_o[3:0]; 15 | 16 | wire [3:0]FCLK_CLK_unbuffered; 17 | wire [3:0]FCLK_CLK_buffered; 18 | BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0])); 19 | BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1])); 20 | BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2])); 21 | BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3])); 22 | 23 | //M_AXI_GP0 24 | localparam C_M_AXI_GP0_THREAD_ID_WIDTH = 12; 25 | // -- Output 26 | wire M_AXI_GP0_ARESETN; 27 | wire M_AXI_GP0_ARVALID; 28 | wire M_AXI_GP0_AWVALID; 29 | wire M_AXI_GP0_BREADY; 30 | wire M_AXI_GP0_RREADY; 31 | wire M_AXI_GP0_WLAST; 32 | wire M_AXI_GP0_WVALID; 33 | wire [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID; 34 | wire [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID; 35 | wire [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID; 36 | wire [1:0] M_AXI_GP0_ARBURST; 37 | wire [1:0] M_AXI_GP0_ARLOCK; 38 | wire [2:0] M_AXI_GP0_ARSIZE; 39 | wire [1:0] M_AXI_GP0_AWBURST; 40 | wire [1:0] M_AXI_GP0_AWLOCK; 41 | wire [2:0] M_AXI_GP0_AWSIZE; 42 | wire [2:0] M_AXI_GP0_ARPROT; 43 | wire [2:0] M_AXI_GP0_AWPROT; 44 | wire [31:0] M_AXI_GP0_ARADDR; 45 | wire [31:0] M_AXI_GP0_AWADDR; 46 | wire [31:0] M_AXI_GP0_WDATA; 47 | wire [3:0] M_AXI_GP0_ARCACHE; 48 | wire [3:0] M_AXI_GP0_ARLEN; 49 | wire [3:0] M_AXI_GP0_ARQOS; 50 | wire [3:0] M_AXI_GP0_AWCACHE; 51 | wire [3:0] M_AXI_GP0_AWLEN; 52 | wire [3:0] M_AXI_GP0_AWQOS; 53 | wire [3:0] M_AXI_GP0_WSTRB; 54 | // -- Input 55 | wire M_AXI_GP0_ACLK = FCLK_CLK_buffered[0]; 56 | wire M_AXI_GP0_ARREADY = 1; 57 | wire M_AXI_GP0_AWREADY = 1; 58 | wire M_AXI_GP0_BVALID = bvalid; 59 | wire M_AXI_GP0_RLAST = 1; 60 | wire M_AXI_GP0_RVALID = rvalid; 61 | wire M_AXI_GP0_WREADY = 1; 62 | wire [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID = M_AXI_GP0_WID; 63 | wire [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID = M_AXI_GP0_ARID; 64 | wire [1:0] M_AXI_GP0_BRESP = 0; 65 | wire [1:0] M_AXI_GP0_RRESP = 0; 66 | wire [31:0] M_AXI_GP0_RDATA = axiwdata; 67 | 68 | reg [31:0]axiwdata = 0; 69 | reg bvalid = 0; 70 | reg rvalid = 0; 71 | always @ (posedge M_AXI_GP0_ACLK) begin 72 | if (M_AXI_GP0_WVALID & M_AXI_GP0_WREADY) 73 | axiwdata <= M_AXI_GP0_WDATA; 74 | if (M_AXI_GP0_WVALID & M_AXI_GP0_WREADY) begin 75 | bvalid <= 1; 76 | end 77 | if (bvalid & M_AXI_GP0_BREADY) begin 78 | bvalid <= 0; 79 | end 80 | if (M_AXI_GP0_ARVALID & M_AXI_GP0_ARREADY) begin 81 | rvalid <= 1; 82 | end 83 | if (rvalid & M_AXI_GP0_RREADY) begin 84 | rvalid <= 0; 85 | end 86 | end 87 | 88 | //assign led = {bvalid, rvalid, M_AXI_GP0_ARVALID, M_AXI_GP0_RREADY}; 89 | 90 | //M_AXI_GP1 91 | localparam C_M_AXI_GP1_THREAD_ID_WIDTH = 12; 92 | // -- Output 93 | wire M_AXI_GP1_ARESETN; 94 | wire M_AXI_GP1_ARVALID; 95 | wire M_AXI_GP1_AWVALID; 96 | wire M_AXI_GP1_BREADY; 97 | wire M_AXI_GP1_RREADY; 98 | wire M_AXI_GP1_WLAST; 99 | wire M_AXI_GP1_WVALID; 100 | wire [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID; 101 | wire [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID; 102 | wire [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID; 103 | wire [1:0] M_AXI_GP1_ARBURST; 104 | wire [1:0] M_AXI_GP1_ARLOCK; 105 | wire [2:0] M_AXI_GP1_ARSIZE; 106 | wire [1:0] M_AXI_GP1_AWBURST; 107 | wire [1:0] M_AXI_GP1_AWLOCK; 108 | wire [2:0] M_AXI_GP1_AWSIZE; 109 | wire [2:0] M_AXI_GP1_ARPROT; 110 | wire [2:0] M_AXI_GP1_AWPROT; 111 | wire [31:0] M_AXI_GP1_ARADDR; 112 | wire [31:0] M_AXI_GP1_AWADDR; 113 | wire [31:0] M_AXI_GP1_WDATA; 114 | wire [3:0] M_AXI_GP1_ARCACHE; 115 | wire [3:0] M_AXI_GP1_ARLEN; 116 | wire [3:0] M_AXI_GP1_ARQOS; 117 | wire [3:0] M_AXI_GP1_AWCACHE; 118 | wire [3:0] M_AXI_GP1_AWLEN; 119 | wire [3:0] M_AXI_GP1_AWQOS; 120 | wire [3:0] M_AXI_GP1_WSTRB; 121 | // -- Input 122 | wire M_AXI_GP1_ACLK = FCLK_CLK_buffered[1]; 123 | wire M_AXI_GP1_ARREADY = 1; 124 | wire M_AXI_GP1_AWREADY = 1; 125 | wire M_AXI_GP1_BVALID = bvalid1; 126 | wire M_AXI_GP1_RLAST = 1; 127 | wire M_AXI_GP1_RVALID = rvalid1; 128 | wire M_AXI_GP1_WREADY = 1; 129 | wire [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID = M_AXI_GP1_WID; 130 | wire [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID = M_AXI_GP0_ARID; 131 | wire [1:0] M_AXI_GP1_BRESP = 0; 132 | wire [1:0] M_AXI_GP1_RRESP = 0; 133 | wire [31:0] M_AXI_GP1_RDATA = 32'habcdabcd; 134 | 135 | reg [31:0]axiwdata1; 136 | reg bvalid1; 137 | reg rvalid1; 138 | always @ (posedge M_AXI_GP1_ACLK) begin 139 | if (M_AXI_GP1_WVALID & M_AXI_GP1_WREADY) 140 | axiwdata1 <= M_AXI_GP1_WDATA; 141 | if (M_AXI_GP1_WVALID & M_AXI_GP1_WREADY) begin 142 | bvalid1 <= 1; 143 | end 144 | if (bvalid1 & M_AXI_GP1_BREADY) begin 145 | bvalid1 <= 0; 146 | end 147 | if (M_AXI_GP1_ARVALID & M_AXI_GP1_ARREADY) begin 148 | rvalid1 <= 1; 149 | end 150 | if (rvalid1 & M_AXI_GP1_RREADY) begin 151 | rvalid1 <= 0; 152 | end 153 | end 154 | 155 | PS7 zynq7 ( 156 | .DMA0DATYPE (), 157 | .DMA0DAVALID (), 158 | .DMA0DRREADY (), 159 | .DMA0RSTN (), 160 | .DMA1DATYPE (), 161 | .DMA1DAVALID (), 162 | .DMA1DRREADY (), 163 | .DMA1RSTN (), 164 | .DMA2DATYPE (), 165 | .DMA2DAVALID (), 166 | .DMA2DRREADY (), 167 | .DMA2RSTN (), 168 | .DMA3DATYPE (), 169 | .DMA3DAVALID (), 170 | .DMA3DRREADY (), 171 | .DMA3RSTN (), 172 | .EMIOCAN0PHYTX (), 173 | .EMIOCAN1PHYTX (), 174 | .EMIOENET0GMIITXD (), 175 | .EMIOENET0GMIITXEN (), 176 | .EMIOENET0GMIITXER (), 177 | .EMIOENET0MDIOMDC (), 178 | .EMIOENET0MDIOO (), 179 | .EMIOENET0MDIOTN (), 180 | .EMIOENET0PTPDELAYREQRX (), 181 | .EMIOENET0PTPDELAYREQTX (), 182 | .EMIOENET0PTPPDELAYREQRX (), 183 | .EMIOENET0PTPPDELAYREQTX (), 184 | .EMIOENET0PTPPDELAYRESPRX (), 185 | .EMIOENET0PTPPDELAYRESPTX (), 186 | .EMIOENET0PTPSYNCFRAMERX (), 187 | .EMIOENET0PTPSYNCFRAMETX (), 188 | .EMIOENET0SOFRX (), 189 | .EMIOENET0SOFTX (), 190 | .EMIOENET1GMIITXD (), 191 | .EMIOENET1GMIITXEN (), 192 | .EMIOENET1GMIITXER (), 193 | .EMIOENET1MDIOMDC (), 194 | .EMIOENET1MDIOO (), 195 | .EMIOENET1MDIOTN (), 196 | .EMIOENET1PTPDELAYREQRX (), 197 | .EMIOENET1PTPDELAYREQTX (), 198 | .EMIOENET1PTPPDELAYREQRX (), 199 | .EMIOENET1PTPPDELAYREQTX (), 200 | .EMIOENET1PTPPDELAYRESPRX (), 201 | .EMIOENET1PTPPDELAYRESPTX (), 202 | .EMIOENET1PTPSYNCFRAMERX (), 203 | .EMIOENET1PTPSYNCFRAMETX (), 204 | .EMIOENET1SOFRX (), 205 | .EMIOENET1SOFTX (), 206 | .EMIOGPIOO (emio_gpio_o), 207 | .EMIOGPIOTN (emio_gpio_t), 208 | .EMIOI2C0SCLO (), 209 | .EMIOI2C0SCLTN (), 210 | .EMIOI2C0SDAO (), 211 | .EMIOI2C0SDATN (), 212 | .EMIOI2C1SCLO (), 213 | .EMIOI2C1SCLTN (), 214 | .EMIOI2C1SDAO (), 215 | .EMIOI2C1SDATN (), 216 | .EMIOPJTAGTDO (), 217 | .EMIOPJTAGTDTN (), 218 | .EMIOSDIO0BUSPOW (), 219 | .EMIOSDIO0BUSVOLT (), 220 | .EMIOSDIO0CLK (), 221 | .EMIOSDIO0CMDO (), 222 | .EMIOSDIO0CMDTN (), 223 | .EMIOSDIO0DATAO (), 224 | .EMIOSDIO0DATATN (), 225 | .EMIOSDIO0LED (), 226 | .EMIOSDIO1BUSPOW (), 227 | .EMIOSDIO1BUSVOLT (), 228 | .EMIOSDIO1CLK (), 229 | .EMIOSDIO1CMDO (), 230 | .EMIOSDIO1CMDTN (), 231 | .EMIOSDIO1DATAO (), 232 | .EMIOSDIO1DATATN (), 233 | .EMIOSDIO1LED (), 234 | .EMIOSPI0MO (), 235 | .EMIOSPI0MOTN (), 236 | .EMIOSPI0SCLKO (), 237 | .EMIOSPI0SCLKTN (), 238 | .EMIOSPI0SO (), 239 | .EMIOSPI0SSNTN (), 240 | .EMIOSPI0SSON (), 241 | .EMIOSPI0STN (), 242 | .EMIOSPI1MO (), 243 | .EMIOSPI1MOTN (), 244 | .EMIOSPI1SCLKO (), 245 | .EMIOSPI1SCLKTN (), 246 | .EMIOSPI1SO (), 247 | .EMIOSPI1SSNTN (), 248 | .EMIOSPI1SSON (), 249 | .EMIOSPI1STN (), 250 | .EMIOTRACECTL (), 251 | .EMIOTRACEDATA (), 252 | .EMIOTTC0WAVEO (), 253 | .EMIOTTC1WAVEO (), 254 | .EMIOUART0DTRN (), 255 | .EMIOUART0RTSN (), 256 | .EMIOUART0TX (), 257 | .EMIOUART1DTRN (), 258 | .EMIOUART1RTSN (), 259 | .EMIOUART1TX (), 260 | .EMIOUSB0PORTINDCTL (), 261 | .EMIOUSB0VBUSPWRSELECT (), 262 | .EMIOUSB1PORTINDCTL (), 263 | .EMIOUSB1VBUSPWRSELECT (), 264 | .EMIOWDTRSTO (), 265 | .EVENTEVENTO (), 266 | .EVENTSTANDBYWFE (), 267 | .EVENTSTANDBYWFI (), 268 | .FCLKCLK (FCLK_CLK_unbuffered), 269 | .FCLKRESETN (), 270 | .FTMTF2PTRIGACK (), 271 | .FTMTP2FDEBUG (), 272 | .FTMTP2FTRIG (), 273 | .IRQP2F (), 274 | .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), 275 | .MAXIGP0ARBURST (M_AXI_GP0_ARBURST ), 276 | .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE ), 277 | .MAXIGP0ARESETN (M_AXI_GP0_ARESETN ), 278 | .MAXIGP0ARID (M_AXI_GP0_ARID ), 279 | .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), 280 | .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), 281 | .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), 282 | .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), 283 | .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE ), 284 | .MAXIGP0ARVALID (M_AXI_GP0_ARVALID ), 285 | .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), 286 | .MAXIGP0AWBURST (M_AXI_GP0_AWBURST ), 287 | .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE ), 288 | .MAXIGP0AWID (M_AXI_GP0_AWID ), 289 | .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), 290 | .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), 291 | .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), 292 | .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), 293 | .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE ), 294 | .MAXIGP0AWVALID (M_AXI_GP0_AWVALID ), 295 | .MAXIGP0BREADY (M_AXI_GP0_BREADY ), 296 | .MAXIGP0RREADY (M_AXI_GP0_RREADY ), 297 | .MAXIGP0WDATA (M_AXI_GP0_WDATA ), 298 | .MAXIGP0WID (M_AXI_GP0_WID ), 299 | .MAXIGP0WLAST (M_AXI_GP0_WLAST ), 300 | .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), 301 | .MAXIGP0WVALID (M_AXI_GP0_WVALID ), 302 | .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), 303 | .MAXIGP1ARBURST (M_AXI_GP1_ARBURST ), 304 | .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE ), 305 | .MAXIGP1ARESETN (M_AXI_GP1_ARESETN ), 306 | .MAXIGP1ARID (M_AXI_GP1_ARID ), 307 | .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), 308 | .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), 309 | .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), 310 | .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), 311 | .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE ), 312 | .MAXIGP1ARVALID (M_AXI_GP1_ARVALID ), 313 | .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), 314 | .MAXIGP1AWBURST (M_AXI_GP1_AWBURST ), 315 | .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE ), 316 | .MAXIGP1AWID (M_AXI_GP1_AWID ), 317 | .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), 318 | .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), 319 | .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), 320 | .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), 321 | .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE ), 322 | .MAXIGP1AWVALID (M_AXI_GP1_AWVALID ), 323 | .MAXIGP1BREADY (M_AXI_GP1_BREADY ), 324 | .MAXIGP1RREADY (M_AXI_GP1_RREADY ), 325 | .MAXIGP1WDATA (M_AXI_GP1_WDATA ), 326 | .MAXIGP1WID (M_AXI_GP1_WID ), 327 | .MAXIGP1WLAST (M_AXI_GP1_WLAST ), 328 | .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), 329 | .MAXIGP1WVALID (M_AXI_GP1_WVALID ), 330 | .SAXIACPARESETN (), 331 | .SAXIACPARREADY (), 332 | .SAXIACPAWREADY (), 333 | .SAXIACPBID (), 334 | .SAXIACPBRESP (), 335 | .SAXIACPBVALID (), 336 | .SAXIACPRDATA (), 337 | .SAXIACPRID (), 338 | .SAXIACPRLAST (), 339 | .SAXIACPRRESP (), 340 | .SAXIACPRVALID (), 341 | .SAXIACPWREADY (), 342 | .SAXIGP0ARESETN (), 343 | .SAXIGP0ARREADY (), 344 | .SAXIGP0AWREADY (), 345 | .SAXIGP0BID (), 346 | .SAXIGP0BRESP (), 347 | .SAXIGP0BVALID (), 348 | .SAXIGP0RDATA (), 349 | .SAXIGP0RID (), 350 | .SAXIGP0RLAST (), 351 | .SAXIGP0RRESP (), 352 | .SAXIGP0RVALID (), 353 | .SAXIGP0WREADY (), 354 | .SAXIGP1ARESETN (), 355 | .SAXIGP1ARREADY (), 356 | .SAXIGP1AWREADY (), 357 | .SAXIGP1BID (), 358 | .SAXIGP1BRESP (), 359 | .SAXIGP1BVALID (), 360 | .SAXIGP1RDATA (), 361 | .SAXIGP1RID (), 362 | .SAXIGP1RLAST (), 363 | .SAXIGP1RRESP (), 364 | .SAXIGP1RVALID (), 365 | .SAXIGP1WREADY (), 366 | .SAXIHP0ARESETN (), 367 | .SAXIHP0ARREADY (), 368 | .SAXIHP0AWREADY (), 369 | .SAXIHP0BID (), 370 | .SAXIHP0BRESP (), 371 | .SAXIHP0BVALID (), 372 | .SAXIHP0RACOUNT (), 373 | .SAXIHP0RCOUNT (), 374 | .SAXIHP0RDATA (), 375 | .SAXIHP0RID (), 376 | .SAXIHP0RLAST (), 377 | .SAXIHP0RRESP (), 378 | .SAXIHP0RVALID (), 379 | .SAXIHP0WACOUNT (), 380 | .SAXIHP0WCOUNT (), 381 | .SAXIHP0WREADY (), 382 | .SAXIHP1ARESETN (), 383 | .SAXIHP1ARREADY (), 384 | .SAXIHP1AWREADY (), 385 | .SAXIHP1BID (), 386 | .SAXIHP1BRESP (), 387 | .SAXIHP1BVALID (), 388 | .SAXIHP1RACOUNT (), 389 | .SAXIHP1RCOUNT (), 390 | .SAXIHP1RDATA (), 391 | .SAXIHP1RID (), 392 | .SAXIHP1RLAST (), 393 | .SAXIHP1RRESP (), 394 | .SAXIHP1RVALID (), 395 | .SAXIHP1WACOUNT (), 396 | .SAXIHP1WCOUNT (), 397 | .SAXIHP1WREADY (), 398 | .SAXIHP2ARESETN (), 399 | .SAXIHP2ARREADY (), 400 | .SAXIHP2AWREADY (), 401 | .SAXIHP2BID (), 402 | .SAXIHP2BRESP (), 403 | .SAXIHP2BVALID (), 404 | .SAXIHP2RACOUNT (), 405 | .SAXIHP2RCOUNT (), 406 | .SAXIHP2RDATA (), 407 | .SAXIHP2RID (), 408 | .SAXIHP2RLAST (), 409 | .SAXIHP2RRESP (), 410 | .SAXIHP2RVALID (), 411 | .SAXIHP2WACOUNT (), 412 | .SAXIHP2WCOUNT (), 413 | .SAXIHP2WREADY (), 414 | .SAXIHP3ARESETN (), 415 | .SAXIHP3ARREADY (), 416 | .SAXIHP3AWREADY (), 417 | .SAXIHP3BID (), 418 | .SAXIHP3BRESP (), 419 | .SAXIHP3BVALID (), 420 | .SAXIHP3RACOUNT (), 421 | .SAXIHP3RCOUNT (), 422 | .SAXIHP3RDATA (), 423 | .SAXIHP3RID (), 424 | .SAXIHP3RLAST (), 425 | .SAXIHP3RRESP (), 426 | .SAXIHP3RVALID (), 427 | .SAXIHP3WACOUNT (), 428 | .SAXIHP3WCOUNT (), 429 | .SAXIHP3WREADY (), 430 | .DDRA (), 431 | .DDRBA (), 432 | .DDRCASB (), 433 | .DDRCKE (), 434 | .DDRCKN (), 435 | .DDRCKP (), 436 | .DDRCSB (), 437 | .DDRDM (), 438 | .DDRDQ (), 439 | .DDRDQSN (), 440 | .DDRDQSP (), 441 | .DDRDRSTB (), 442 | .DDRODT (), 443 | .DDRRASB (), 444 | .DDRVRN (), 445 | .DDRVRP (), 446 | .DDRWEB (), 447 | .MIO (), 448 | .PSCLK (), 449 | .PSPORB (), 450 | .PSSRSTB (), 451 | .DDRARB (), 452 | .DMA0ACLK (), 453 | .DMA0DAREADY (), 454 | .DMA0DRLAST (), 455 | .DMA0DRTYPE (), 456 | .DMA0DRVALID (), 457 | .DMA1ACLK (), 458 | .DMA1DAREADY (), 459 | .DMA1DRLAST (), 460 | .DMA1DRTYPE (), 461 | .DMA1DRVALID (), 462 | .DMA2ACLK (), 463 | .DMA2DAREADY (), 464 | .DMA2DRLAST (), 465 | .DMA2DRTYPE (), 466 | .DMA2DRVALID (), 467 | .DMA3ACLK (), 468 | .DMA3DAREADY (), 469 | .DMA3DRLAST (), 470 | .DMA3DRTYPE (), 471 | .DMA3DRVALID (), 472 | .EMIOCAN0PHYRX (), 473 | .EMIOCAN1PHYRX (), 474 | .EMIOENET0EXTINTIN (), 475 | .EMIOENET0GMIICOL (), 476 | .EMIOENET0GMIICRS (), 477 | .EMIOENET0GMIIRXCLK (), 478 | .EMIOENET0GMIIRXD (), 479 | .EMIOENET0GMIIRXDV (), 480 | .EMIOENET0GMIIRXER (), 481 | .EMIOENET0GMIITXCLK (), 482 | .EMIOENET0MDIOI (), 483 | .EMIOENET1EXTINTIN (), 484 | .EMIOENET1GMIICOL (), 485 | .EMIOENET1GMIICRS (), 486 | .EMIOENET1GMIIRXCLK (), 487 | .EMIOENET1GMIIRXD (), 488 | .EMIOENET1GMIIRXDV (), 489 | .EMIOENET1GMIIRXER (), 490 | .EMIOENET1GMIITXCLK (), 491 | .EMIOENET1MDIOI (), 492 | .EMIOGPIOI (emio_gpio_i), 493 | .EMIOI2C0SCLI (), 494 | .EMIOI2C0SDAI (), 495 | .EMIOI2C1SCLI (), 496 | .EMIOI2C1SDAI (), 497 | .EMIOPJTAGTCK (), 498 | .EMIOPJTAGTDI (), 499 | .EMIOPJTAGTMS (), 500 | .EMIOSDIO0CDN (), 501 | .EMIOSDIO0CLKFB (), 502 | .EMIOSDIO0CMDI (), 503 | .EMIOSDIO0DATAI (), 504 | .EMIOSDIO0WP (), 505 | .EMIOSDIO1CDN (), 506 | .EMIOSDIO1CLKFB (), 507 | .EMIOSDIO1CMDI (), 508 | .EMIOSDIO1DATAI (), 509 | .EMIOSDIO1WP (), 510 | .EMIOSPI0MI (), 511 | .EMIOSPI0SCLKI (), 512 | .EMIOSPI0SI (), 513 | .EMIOSPI0SSIN (), 514 | .EMIOSPI1MI (), 515 | .EMIOSPI1SCLKI (), 516 | .EMIOSPI1SI (), 517 | .EMIOSPI1SSIN (), 518 | .EMIOSRAMINTIN (), 519 | .EMIOTRACECLK (), 520 | .EMIOTTC0CLKI (), 521 | .EMIOTTC1CLKI (), 522 | .EMIOUART0CTSN (), 523 | .EMIOUART0DCDN (), 524 | .EMIOUART0DSRN (), 525 | .EMIOUART0RIN (), 526 | .EMIOUART0RX (), 527 | .EMIOUART1CTSN (), 528 | .EMIOUART1DCDN (), 529 | .EMIOUART1DSRN (), 530 | .EMIOUART1RIN (), 531 | .EMIOUART1RX (), 532 | .EMIOUSB0VBUSPWRFAULT (), 533 | .EMIOUSB1VBUSPWRFAULT (), 534 | .EMIOWDTCLKI (), 535 | .EVENTEVENTI (), 536 | .FCLKCLKTRIGN (), 537 | .FPGAIDLEN (), 538 | .FTMDTRACEINATID (), 539 | .FTMDTRACEINCLOCK (), 540 | .FTMDTRACEINDATA (), 541 | .FTMDTRACEINVALID (), 542 | .FTMTF2PDEBUG (), 543 | .FTMTF2PTRIG (), 544 | .FTMTP2FTRIGACK (), 545 | .IRQF2P (), 546 | .MAXIGP0ACLK (M_AXI_GP0_ACLK ), 547 | .MAXIGP0ARREADY (M_AXI_GP0_ARREADY ), 548 | .MAXIGP0AWREADY (M_AXI_GP0_AWREADY ), 549 | .MAXIGP0BID (M_AXI_GP0_BID ), 550 | .MAXIGP0BRESP (M_AXI_GP0_BRESP ), 551 | .MAXIGP0BVALID (M_AXI_GP0_BVALID ), 552 | .MAXIGP0RDATA (M_AXI_GP0_RDATA ), 553 | .MAXIGP0RID (M_AXI_GP0_RID ), 554 | .MAXIGP0RLAST (M_AXI_GP0_RLAST ), 555 | .MAXIGP0RRESP (M_AXI_GP0_RRESP ), 556 | .MAXIGP0RVALID (M_AXI_GP0_RVALID ), 557 | .MAXIGP0WREADY (M_AXI_GP0_WREADY ), 558 | .MAXIGP1ACLK (M_AXI_GP1_ACLK ), 559 | .MAXIGP1ARREADY (M_AXI_GP1_ARREADY ), 560 | .MAXIGP1AWREADY (M_AXI_GP1_AWREADY ), 561 | .MAXIGP1BID (M_AXI_GP1_BID ), 562 | .MAXIGP1BRESP (M_AXI_GP1_BRESP ), 563 | .MAXIGP1BVALID (M_AXI_GP1_BVALID ), 564 | .MAXIGP1RDATA (M_AXI_GP1_RDATA ), 565 | .MAXIGP1RID (M_AXI_GP1_RID ), 566 | .MAXIGP1RLAST (M_AXI_GP1_RLAST ), 567 | .MAXIGP1RRESP (M_AXI_GP1_RRESP ), 568 | .MAXIGP1RVALID (M_AXI_GP1_RVALID ), 569 | .MAXIGP1WREADY (M_AXI_GP1_WREADY ), 570 | .SAXIACPACLK (), 571 | .SAXIACPARADDR (), 572 | .SAXIACPARBURST (), 573 | .SAXIACPARCACHE (), 574 | .SAXIACPARID (), 575 | .SAXIACPARLEN (), 576 | .SAXIACPARLOCK (), 577 | .SAXIACPARPROT (), 578 | .SAXIACPARQOS (), 579 | .SAXIACPARSIZE (), 580 | .SAXIACPARUSER (), 581 | .SAXIACPARVALID (), 582 | .SAXIACPAWADDR (), 583 | .SAXIACPAWBURST (), 584 | .SAXIACPAWCACHE (), 585 | .SAXIACPAWID (), 586 | .SAXIACPAWLEN (), 587 | .SAXIACPAWLOCK (), 588 | .SAXIACPAWPROT (), 589 | .SAXIACPAWQOS (), 590 | .SAXIACPAWSIZE (), 591 | .SAXIACPAWUSER (), 592 | .SAXIACPAWVALID (), 593 | .SAXIACPBREADY (), 594 | .SAXIACPRREADY (), 595 | .SAXIACPWDATA (), 596 | .SAXIACPWID (), 597 | .SAXIACPWLAST (), 598 | .SAXIACPWSTRB (), 599 | .SAXIACPWVALID (), 600 | .SAXIGP0ACLK (), 601 | .SAXIGP0ARADDR (), 602 | .SAXIGP0ARBURST (), 603 | .SAXIGP0ARCACHE (), 604 | .SAXIGP0ARID (), 605 | .SAXIGP0ARLEN (), 606 | .SAXIGP0ARLOCK (), 607 | .SAXIGP0ARPROT (), 608 | .SAXIGP0ARQOS (), 609 | .SAXIGP0ARSIZE (), 610 | .SAXIGP0ARVALID (), 611 | .SAXIGP0AWADDR (), 612 | .SAXIGP0AWBURST (), 613 | .SAXIGP0AWCACHE (), 614 | .SAXIGP0AWID (), 615 | .SAXIGP0AWLEN (), 616 | .SAXIGP0AWLOCK (), 617 | .SAXIGP0AWPROT (), 618 | .SAXIGP0AWQOS (), 619 | .SAXIGP0AWSIZE (), 620 | .SAXIGP0AWVALID (), 621 | .SAXIGP0BREADY (), 622 | .SAXIGP0RREADY (), 623 | .SAXIGP0WDATA (), 624 | .SAXIGP0WID (), 625 | .SAXIGP0WLAST (), 626 | .SAXIGP0WSTRB (), 627 | .SAXIGP0WVALID (), 628 | .SAXIGP1ACLK (), 629 | .SAXIGP1ARADDR (), 630 | .SAXIGP1ARBURST (), 631 | .SAXIGP1ARCACHE (), 632 | .SAXIGP1ARID (), 633 | .SAXIGP1ARLEN (), 634 | .SAXIGP1ARLOCK (), 635 | .SAXIGP1ARPROT (), 636 | .SAXIGP1ARQOS (), 637 | .SAXIGP1ARSIZE (), 638 | .SAXIGP1ARVALID (), 639 | .SAXIGP1AWADDR (), 640 | .SAXIGP1AWBURST (), 641 | .SAXIGP1AWCACHE (), 642 | .SAXIGP1AWID (), 643 | .SAXIGP1AWLEN (), 644 | .SAXIGP1AWLOCK (), 645 | .SAXIGP1AWPROT (), 646 | .SAXIGP1AWQOS (), 647 | .SAXIGP1AWSIZE (), 648 | .SAXIGP1AWVALID (), 649 | .SAXIGP1BREADY (), 650 | .SAXIGP1RREADY (), 651 | .SAXIGP1WDATA (), 652 | .SAXIGP1WID (), 653 | .SAXIGP1WLAST (), 654 | .SAXIGP1WSTRB (), 655 | .SAXIGP1WVALID (), 656 | .SAXIHP0ACLK (), 657 | .SAXIHP0ARADDR (), 658 | .SAXIHP0ARBURST (), 659 | .SAXIHP0ARCACHE (), 660 | .SAXIHP0ARID (), 661 | .SAXIHP0ARLEN (), 662 | .SAXIHP0ARLOCK (), 663 | .SAXIHP0ARPROT (), 664 | .SAXIHP0ARQOS (), 665 | .SAXIHP0ARSIZE (), 666 | .SAXIHP0ARVALID (), 667 | .SAXIHP0AWADDR (), 668 | .SAXIHP0AWBURST (), 669 | .SAXIHP0AWCACHE (), 670 | .SAXIHP0AWID (), 671 | .SAXIHP0AWLEN (), 672 | .SAXIHP0AWLOCK (), 673 | .SAXIHP0AWPROT (), 674 | .SAXIHP0AWQOS (), 675 | .SAXIHP0AWSIZE (), 676 | .SAXIHP0AWVALID (), 677 | .SAXIHP0BREADY (), 678 | .SAXIHP0RDISSUECAP1EN (), 679 | .SAXIHP0RREADY (), 680 | .SAXIHP0WDATA (), 681 | .SAXIHP0WID (), 682 | .SAXIHP0WLAST (), 683 | .SAXIHP0WRISSUECAP1EN (), 684 | .SAXIHP0WSTRB (), 685 | .SAXIHP0WVALID (), 686 | .SAXIHP1ACLK (), 687 | .SAXIHP1ARADDR (), 688 | .SAXIHP1ARBURST (), 689 | .SAXIHP1ARCACHE (), 690 | .SAXIHP1ARID (), 691 | .SAXIHP1ARLEN (), 692 | .SAXIHP1ARLOCK (), 693 | .SAXIHP1ARPROT (), 694 | .SAXIHP1ARQOS (), 695 | .SAXIHP1ARSIZE (), 696 | .SAXIHP1ARVALID (), 697 | .SAXIHP1AWADDR (), 698 | .SAXIHP1AWBURST (), 699 | .SAXIHP1AWCACHE (), 700 | .SAXIHP1AWID (), 701 | .SAXIHP1AWLEN (), 702 | .SAXIHP1AWLOCK (), 703 | .SAXIHP1AWPROT (), 704 | .SAXIHP1AWQOS (), 705 | .SAXIHP1AWSIZE (), 706 | .SAXIHP1AWVALID (), 707 | .SAXIHP1BREADY (), 708 | .SAXIHP1RDISSUECAP1EN (), 709 | .SAXIHP1RREADY (), 710 | .SAXIHP1WDATA (), 711 | .SAXIHP1WID (), 712 | .SAXIHP1WLAST (), 713 | .SAXIHP1WRISSUECAP1EN (), 714 | .SAXIHP1WSTRB (), 715 | .SAXIHP1WVALID (), 716 | .SAXIHP2ACLK (), 717 | .SAXIHP2ARADDR (), 718 | .SAXIHP2ARBURST (), 719 | .SAXIHP2ARCACHE (), 720 | .SAXIHP2ARID (), 721 | .SAXIHP2ARLEN (), 722 | .SAXIHP2ARLOCK (), 723 | .SAXIHP2ARPROT (), 724 | .SAXIHP2ARQOS (), 725 | .SAXIHP2ARSIZE (), 726 | .SAXIHP2ARVALID (), 727 | .SAXIHP2AWADDR (), 728 | .SAXIHP2AWBURST (), 729 | .SAXIHP2AWCACHE (), 730 | .SAXIHP2AWID (), 731 | .SAXIHP2AWLEN (), 732 | .SAXIHP2AWLOCK (), 733 | .SAXIHP2AWPROT (), 734 | .SAXIHP2AWQOS (), 735 | .SAXIHP2AWSIZE (), 736 | .SAXIHP2AWVALID (), 737 | .SAXIHP2BREADY (), 738 | .SAXIHP2RDISSUECAP1EN (), 739 | .SAXIHP2RREADY (), 740 | .SAXIHP2WDATA (), 741 | .SAXIHP2WID (), 742 | .SAXIHP2WLAST (), 743 | .SAXIHP2WRISSUECAP1EN (), 744 | .SAXIHP2WSTRB (), 745 | .SAXIHP2WVALID (), 746 | .SAXIHP3ACLK (), 747 | .SAXIHP3ARADDR (), 748 | .SAXIHP3ARBURST (), 749 | .SAXIHP3ARCACHE (), 750 | .SAXIHP3ARID (), 751 | .SAXIHP3ARLEN (), 752 | .SAXIHP3ARLOCK (), 753 | .SAXIHP3ARPROT (), 754 | .SAXIHP3ARQOS (), 755 | .SAXIHP3ARSIZE (), 756 | .SAXIHP3ARVALID (), 757 | .SAXIHP3AWADDR (), 758 | .SAXIHP3AWBURST (), 759 | .SAXIHP3AWCACHE (), 760 | .SAXIHP3AWID (), 761 | .SAXIHP3AWLEN (), 762 | .SAXIHP3AWLOCK (), 763 | .SAXIHP3AWPROT (), 764 | .SAXIHP3AWQOS (), 765 | .SAXIHP3AWSIZE (), 766 | .SAXIHP3AWVALID (), 767 | .SAXIHP3BREADY (), 768 | .SAXIHP3RDISSUECAP1EN (), 769 | .SAXIHP3RREADY (), 770 | .SAXIHP3WDATA (), 771 | .SAXIHP3WID (), 772 | .SAXIHP3WLAST (), 773 | .SAXIHP3WRISSUECAP1EN (), 774 | .SAXIHP3WSTRB (), 775 | .SAXIHP3WVALID () 776 | ); 777 | 778 | endmodule 779 | 780 | -------------------------------------------------------------------------------- /examples/5-uart/README.md: -------------------------------------------------------------------------------- 1 | ### 5. PS UART 2 | 3 | We have been using the PS, but not PS peripherals via MIOs yet! This demonstrates PS UART, as well as how to use the Xilinx embeddedsw library. 4 | 5 | In `uart.py`, a Vivado configurator-like text array is used to disable/enable desired peripherals. We enabled the UART and SD Card (unused here) by setting `_` to `1` in the array. 115200 is the default baud rate. 6 | 7 | In Vivado, maximum UART baud is 921600. Want higher? Just set `'baud':3000000` in the configuration. 3M or 8M baud would just work, the FT2232 USB-UART can also handle that. 8 | 9 | 10 | ``` 11 | # Run GenZ 12 | $ export PYTHONPATH=../.. 13 | $ ./uart.py 14 | # Prepare BSP folder for PYNQ-Z1 15 | $ git clone https://github.com/regymm/embeddedsw --depth=1 16 | $ cp -a embeddedsw/lib/sw_apps/zynq_fsbl/misc/{muzy4,pynqz1} 17 | # Copy the BSP files generated by GenZ 18 | $ cp ps7_init_uart/* embeddedsw/lib/sw_apps/zynq_fsbl/misc/pynqz1 19 | # Compile elf with Xilinx open source embeddedsw library 20 | $ make BOARD=pynqz1 -C embeddedsw/lib/sw_apps/hello_world/src 21 | # Launch the compiled hello world ELF on hardware, no bitstream needed 22 | $ source /opt/Xilinx/Vivado/2019.1/settings64.sh 23 | $ ../../xsct_tools/run_elf_7030.tcl ps7_init_uart/ps7_init.tcl x embeddedsw/lib/sw_apps/hello_world/src/hello-world.elf 24 | 25 | # These texts will be printed in ttyUSB1: 26 | Hello World 27 | Successfully ran Hello World application 28 | ``` 29 | 30 | > For even higher bauds, UG585 page ~619 has information about how UART clocks and divisors work. 31 | 32 | > When using EMIO UART, there's no need to set the parameter array, but an entry like `'uart1': {'baud':115200}` is required. 33 | -------------------------------------------------------------------------------- /examples/5-uart/uart.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | # Set tab to 4 spaces to view correctly! 6 | _=0 7 | 8 | z7000_ps_param_pynqz1 = { 9 | # L0 L1 L2_01 L2_10 L2_11 L3_000 L3_001 L3_010 L3_011 L3_100 L3_101 L3_110 L3_111 10 | 'MIO_PIN_00': [ _*'qspi1 ss_b', x, _*'sram/nor cs0', _*'nand cs0', _*'sd0 power', _*'gpio', x, x, x, x, x, x, ''], 11 | 'MIO_PIN_01': [ _*'qspi0 ss_b', x, _*'sram addr25', _*'sram/nor cs1', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 12 | 'MIO_PIN_02': [ _*'qspi0 io0', _*'trace data8', x, _*'nand alen', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 13 | 'MIO_PIN_03': [ _*'qspi0 io1', _*'trace data9', _*'sram/nor data0', _*'nand we_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 14 | 'MIO_PIN_04': [ _*'qspi0 io2', _*'trace data10', _*'sram/nor data1', _*'nand data2', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 15 | 'MIO_PIN_05': [ _*'qspi0 io3', _*'trace data11', _*'sram/nor data2', _*'nand data0', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 16 | 'MIO_PIN_06': [ _*'qspi0 sclk', _*'trace data12', _*'sram/nor data3', _*'nand data1', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 17 | 'MIO_PIN_07': [ x, _*'trace data13', _*'sram/nor oe_b', _*'nand cle_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 18 | 'MIO_PIN_08': [ _*'qspi fbclk', _*'trace data14', x, _*'nand rd_b', _*'sd0 power', _*'gpio', _*'can1 tx', _*'sram/nor bls_b', x, x, x, x, _*'uart1 txd'], 19 | 'MIO_PIN_09': [ _*'qspi1 sclk', _*'trace data15', _*'sram/nor data6', _*'nand data4', _*'sd1 power', _*'gpio', _*'can1 rx', x, x, x, x, x, _*'uart1 rxd'], 20 | 'MIO_PIN_10': [ _*'qspi1 io0', _*'trace data2', _*'sram/nor data7', _*'nand data5', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 21 | 'MIO_PIN_11': [ _*'qspi1 io1', _*'trace data3', _*'sram/nor data4', _*'nand data6', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 22 | 'MIO_PIN_12': [ _*'qspi1 io2', _*'trace clk', x, _*'nand data7', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 23 | 'MIO_PIN_13': [ _*'qspi1 io3', _*'trace ctrl', x, _*'nand data3', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 24 | 'MIO_PIN_14': [ x, _*'trace data0', x, _*'nand busy', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, 1*'uart0 rxd'], 25 | 'MIO_PIN_15': [ x, _*'trace data1', _*'sram/nor addr0', x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, 1*'uart0 txd'], 26 | 'MIO_PIN_16': [ _*'gem0 tx_clk',_*'trace data4', _*'sram/nor addr1', _*'nand data8', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 27 | 'MIO_PIN_17': [ _*'gem0 txd0', _*'trace data5', _*'sram/nor addr2', _*'nand data9', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 cmd', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 28 | 'MIO_PIN_18': [ _*'gem0 txd1', _*'trace data6', _*'sram/nor addr3', _*'nand data10', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 29 | 'MIO_PIN_19': [ _*'gem0 txd2', _*'trace data7', _*'sram/nor addr4', _*'nand data11', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 30 | 'MIO_PIN_20': [ _*'gem0 txd3', x, _*'sram/nor addr5', _*'nand data12', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 31 | 'MIO_PIN_21': [ _*'gem0 tx_ctl',x, _*'sram/nor addr6', _*'nand data13', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 32 | 'MIO_PIN_22': [ _*'gem0 rx_clk',_*'trace data2', _*'sram/nor addr7', _*'nand data14', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 33 | 'MIO_PIN_23': [ _*'gem0 rxd0', _*'trace data3', _*'sram/nor addr8', _*'nand data15', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 34 | 'MIO_PIN_24': [ _*'gem0 rxd1', _*'trace clk', _*'sram/nor addr9', x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 35 | 'MIO_PIN_25': [ _*'gem0 rxd2', _*'trace ctrl', _*'sram/nor addr10',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 36 | 'MIO_PIN_26': [ _*'gem0 rxd3', _*'trace data0', _*'sram/nor addr11',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 37 | 'MIO_PIN_27': [ _*'gem0 rx_clk',_*'trace data1', _*'sram/nor addr12',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 38 | 'MIO_PIN_28': [ _*'gem1 tx_clk',_*'usb0 data4', _*'sram/nor addr13',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 39 | 'MIO_PIN_29': [ _*'gem1 txd0', _*'usb0 dir', _*'sram/nor addr14',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 40 | 'MIO_PIN_30': [ _*'gem1 txd1', _*'usb0 stp', _*'sram/nor addr15',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 41 | 'MIO_PIN_31': [ _*'gem1 txd2', _*'usb0 nxt', _*'sram/nor addr16',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 42 | 'MIO_PIN_32': [ _*'gem1 txd3', _*'usb0 data0', _*'sram/nor addr17',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 43 | 'MIO_PIN_33': [ _*'gem1 tx_ctl',_*'usb0 data1', _*'sram/nor addr18',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 44 | 'MIO_PIN_34': [ _*'gem1 rx_clk',_*'usb0 data2', _*'sram/nor addr19',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 45 | 'MIO_PIN_35': [ _*'gem1 rxd0', _*'usb0 data3', _*'sram/nor addr20',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 46 | 'MIO_PIN_36': [ _*'gem1 rxd1', _*'usb0 clk', _*'sram/nor addr21',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 47 | 'MIO_PIN_37': [ _*'gem1 rxd2', _*'usb0 data5', _*'sram/nor addr22',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 48 | 'MIO_PIN_38': [ _*'gem1 rxd3', _*'usb0 data6', _*'sram/nor addr23',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 49 | 'MIO_PIN_39': [ _*'gem1 rx_ctl',_*'usb0 data7', _*'sram/nor addr24',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 50 | 'MIO_PIN_40': [ x, _*'usb1 data4', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 51 | 'MIO_PIN_41': [ x, _*'usb1 dir', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 52 | 'MIO_PIN_42': [ x, _*'usb1 stp', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, 1*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 53 | 'MIO_PIN_43': [ x, _*'usb1 nxt', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, 1*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 54 | 'MIO_PIN_44': [ x, _*'usb1 data0', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 55 | 'MIO_PIN_45': [ x, _*'usb1 data1', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 56 | 'MIO_PIN_46': [ x, _*'usb1 data2', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 57 | 'MIO_PIN_47': [ x, _*'usb1 data3', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 58 | 'MIO_PIN_48': [ x, _*'usb1 clk', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 59 | 'MIO_PIN_49': [ x, _*'usb1 data5', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 60 | 'MIO_PIN_50': [ x, _*'usb1 data6', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 61 | 'MIO_PIN_51': [ x, _*'usb1 data7', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 62 | 'MIO_PIN_52': [ x, x, x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'swdt clk', _*'mdio0 clk', _*'mdio1 clk', x, _*'uart1 txd'], 63 | 'MIO_PIN_53': [ x, x, x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'swdt rst', _*'mdio0 data', _*'mdio1 data', x, _*'uart1 rxd'], 64 | 'uart0' : { 'baud': 115200 }, 65 | # 'uart0' : { 'baud': 3000000 }, 66 | # 'uart0' : { 'baud': 8000000 }, 67 | 'freq' : { 'crystal' : 50.000 68 | } 69 | } 70 | 71 | if __name__ == '__main__': 72 | z7 = Zynq7000() 73 | z7.param_load(z7000_ps_param_pynqz1) 74 | z7.ps7_init_gen(zynq7_allregisters) 75 | z7.ps7_init_filewrite('./ps7_init_uart/') 76 | -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/Makefile.caas: -------------------------------------------------------------------------------- 1 | DB_DIR ?= /nextpnr-xilinx/xilinx/external/prjxray-db 2 | CHIPDB ?= /chipdb 3 | 4 | BUILDDIR := ${CURDIR}/build 5 | TOP := top 6 | #SOURCES := $(wildcard *.v) 7 | XDC := $(wildcard $(wildcard *.xdc) $(wildcard *.pcf) $(wildcard *.lpf) $(wildcard *.cst) ) 8 | 9 | CHIPFAM := zynq7 10 | PART := xc7z020clg400-1 11 | 12 | LOGFILE := ${BUILDDIR}/top.log 13 | 14 | all: ${CHIPDB} ${BUILDDIR} ${BUILDDIR}/top.bit 15 | 16 | ${BUILDDIR}: 17 | mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true 18 | 19 | ${CHIPDB}: 20 | mkdir -m 777 -p ${CHIPDB} && chown -R nobody ${CHIPDB} | true 21 | 22 | # we run this in parent directory to seeminglessly import user source files 23 | # otherwise have to parse user pattern and add ../ 24 | ${BUILDDIR}/top.json: $(wildcard *.v) 25 | yosys -p "synth_xilinx -flatten -abc9 -arch xc7 -top ${TOP}; write_json ${BUILDDIR}/top.json" $^ >> ${LOGFILE} 2>&1 26 | 27 | # The chip database only needs to be generated once 28 | # that is why we don't clean it with make clean 29 | ${CHIPDB}/${PART}.bin: 30 | pypy3 /nextpnr-xilinx/xilinx/python/bbaexport.py --device ${PART} --bba ${PART}.bba 31 | bbasm -l ${PART}.bba ${CHIPDB}/${PART}.bin 32 | rm -f ${PART}.bba 33 | 34 | ${BUILDDIR}/top.fasm: ${BUILDDIR}/top.json ${CHIPDB}/${PART}.bin 35 | nextpnr-xilinx --chipdb ${CHIPDB}/${PART}.bin --xdc ${XDC} --json ${BUILDDIR}/top.json --fasm $@ >> ${LOGFILE} 2>&1 36 | 37 | ${BUILDDIR}/top.frames: ${BUILDDIR}/top.fasm 38 | fasm2frames --part ${PART} --db-root ${DB_DIR}/${CHIPFAM} $< > $@ 39 | 40 | ${BUILDDIR}/top.bit: ${BUILDDIR}/top.frames 41 | xc7frames2bit --part_file ${DB_DIR}/${CHIPFAM}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@ >> ${LOGFILE} 2>&1 42 | 43 | .PHONY: clean 44 | clean: 45 | @rm -f *.bit 46 | @rm -f *.frames 47 | @rm -f *.fasm 48 | @rm -f *.json 49 | -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/README.md: -------------------------------------------------------------------------------- 1 | ### 6. No DDR SD Boot 2 | 3 | The bitstream/ELF was by far loaded via JTAG. Here, it's loaded from a SD Card, using the traditional `BOOT.BIN` method. Not a single proprietary tool is required. 4 | 5 | Usually, a linear memory device (like QSPI Flash) is required when doing No DDR bitstream loading. But this is not necessary. By [splitting the bitstream-loading DMA to 0xFFFFFFFF to smaller chunks](https://github.com/regymm/embeddedsw/blob/zynq_noddr/lib/sw_apps/zynq_fsbl/src/pcap.c#L312), loading from SD Card without DDR/Flash is possible with no noticeable speed difference. This can greatly ease the design of Zynq-as-MCU boards without DDR. 6 | 7 | #### BSP 8 | 9 | In this case, bank voltage is set in `sdboot.py`. 10 | 11 | ``` 12 | # Run GenZ, same as in 5-uart 13 | $ export PYTHONPATH=../.. 14 | $ ./sdboot.py 15 | 16 | # Prepare BSP folder for PYNQ-Z1 17 | $ git clone https://github.com/regymm/embeddedsw --depth=1 18 | $ cp -a embeddedsw/lib/sw_apps/zynq_fsbl/misc/{muzy4,pynqz1} 19 | # Copy the BSP files generated by GenZ 20 | $ cp ps7_init_sdboot/* embeddedsw/lib/sw_apps/zynq_fsbl/misc/pynqz1 21 | ``` 22 | 23 | #### FSBL and User App 24 | 25 | Compile elf with Xilinx open source embeddedsw library (User App), enables AXI GPIO test 26 | 27 | ``` 28 | $ make BOARD=pynqz1 "CFLAGS=-DAXI_TEST" -C embeddedsw/lib/sw_apps/hello_world/src 29 | ``` 30 | Compile FSBL with No DDR SDBoot support and debug info 31 | ``` 32 | $ make BOARD=pynqz1 "CFLAGS=-DFSBL_DEBUG_INFO -DNODDR" -C embeddedsw/lib/sw_apps/zynq_fsbl/src 33 | ``` 34 | #### FPGA 35 | 36 | Bitstream for the PL fabric can be generated with [OpenXC7](https://github.com/openXC7/), with demos at [FPGAOL-CE user-examples](https://github.com/FPGAOL-CE/user-examples/tree/main/zynq7000-demos). Makefiles for various FOSS FPGA toolchains can be generated with the [CaaS Wizard](https://github.com/FPGAOL-CE/caas-wizard). 37 | 38 | Without Vivado proprietary IPs, here we demonstrate a simple AXI-Lite GPIO module with a compatible register map. For complex designs with multiple AXI devices, [ZipCPU](https://github.com/ZipCPU/wb2axip/) and [alexforencich](https://github.com/alexforencich/verilog-axi) provide all required AXI interconnects, clock domain crossing, and even wishbone bridges. 39 | 40 | ``` 41 | # With pre-generated Makefiles 42 | $ ./run_caas.sh 43 | 44 | # Build Makefiles from caas.conf 45 | $ git clone https://github.com/FPGAOL-CE/caas-wizard --depth=1 46 | $ ./caas-wizard/caasw.py mfgen --overwrite 47 | $ ./run_caas.sh 48 | ``` 49 | 50 | #### BOOT.BIN 51 | 52 | It's the file to put in SD card (or QSPI flash) for startup. 53 | 54 | ``` 55 | # Prepare BOOT.BIN for SD Boot 56 | $ git clone https://github.com/antmicro/zynq-mkbootimage --depth=1 57 | $ make -C zynq-mkbootimage 58 | 59 | # Prepare bif 60 | $ cat > output.bif << EOF 61 | the_ROM_image: 62 | { 63 | [bootloader]embeddedsw/lib/sw_apps/zynq_fsbl/src/fsbl.elf 64 | build/top.bit 65 | embeddedsw/lib/sw_apps/hello_world/src/hello-world.elf 66 | } 67 | EOF 68 | 69 | # Generate BOOT.BIN 70 | $ ./zynq-mkbootimage/mkbootimage output.bif BOOT.BIN 71 | ``` 72 | 73 | #### Run 74 | 75 | Copy BOOT.BIN to the root of the first FAT32 partition in SD Card, and power on the board with SD boot mode -- can then see LEDs blinking and PS UART output. Enjoy the freedom! 76 | 77 | --- 78 | 79 | 80 | #### Morale 81 | 82 | *Why Twice?* 83 | 84 | In Zynq development, we have great flexibility, but as a result, we often need to set the same thing multiple times -- like specifying which UART to use, specifying crystal frequency, etc. 85 | 86 | There're two levels of parameter specification 87 | 88 | 1. Parts that **only needs to be set once** during startup, done by ps7_init.tcl via JTAG or ps7_init.c via FSBL, including: 89 | - Which MIO pins to use, like MIO 2-3 or MIO 6-7. 90 | - Bank voltage, that affects MIO pin settings 91 | - PLL multipler/divisors 92 | 2. Parts used by software. **Each piece of software** (u-boot, Linux, etc) needs to know these. Here, the parameters back in 1. are in lower, invisible layers. In complex systems, it's usually done by device tree 93 | - UART0 or UART1. As they have different memory addresses. 94 | - ARM core frequency, used by some timers. 95 | - Size of QSPI flash 96 | - Of course, FSBL is also a software, and needs these. 97 | - In this sense, `xparameters.h` is a small "device tree" for Xilinx embeddedsw library. 98 | 99 | To avoid the tedious work of configuring device trees manually for everything, **petalinux** is available. But it's usually a pain to use. Thus, the future roadmap of this project includes implementing a user-friendly petalinux alternative. 100 | 101 | #### Debug 102 | 103 | Can also launch FSBL by JTAG, though it not the designed way. 104 | 105 | > ps7_init.tcl is used for register configuration via JTAG, while ps7_init.c has the same register configuration for FSBL. Launching FSBL by JTAG means configuration is done twice (but it doesn't matter) 106 | 107 | E.g. in JTAG boot mode, FSBL won't run. In SD boot mode, FSBL from JTAG is executed, but it'll load bitstream and user app from SD Card! If the FSBL file size, etc is different from the one on SD card, some headers can't be read successfully. 108 | 109 | 110 | ``` 111 | Xilinx First Stage Boot Loader 112 | Release 2024.1 Jan 16 2025-23:13:16 113 | Devcfg driver initialized 114 | Silicon Version 3.1 115 | Boot mode is JTAG 116 | ``` -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/caas.conf: -------------------------------------------------------------------------------- 1 | [caas] 2 | Server = https://caas.symbioticeda.com:18888/ 3 | 4 | [project] 5 | Backend = openxc7 6 | Part = xc7z020clg400-1 7 | -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/output.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]embeddedsw/lib/sw_apps/zynq_fsbl/src/fsbl.elf 4 | build/top.bit 5 | embeddedsw/lib/sw_apps/hello_world/src/hello-world.elf 6 | } 7 | -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/pynqz1.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H16 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | 4 | # Switches 5 | set_property PACKAGE_PIN M20 [get_ports {sw[0]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 7 | set_property PACKAGE_PIN M19 [get_ports {sw[1]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 9 | 10 | # LEDs 11 | set_property PACKAGE_PIN R14 [get_ports {led[0]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] 13 | set_property PACKAGE_PIN P14 [get_ports {led[1]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 15 | set_property PACKAGE_PIN N16 [get_ports {led[2]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 17 | set_property PACKAGE_PIN M14 [get_ports {led[3]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 19 | -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/run_caas.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -ex 2 | if [[ $(uname -m) == "aarch64" ]]; then 3 | append="-arm" 4 | else 5 | append="" 6 | fi 7 | 8 | docker run --pull never -it --rm -m 8G \ 9 | -v `pwd`:/mnt \ 10 | -v /chipdb:/chipdb \ 11 | --tmpfs /tmp \ 12 | regymm/openxc7${append} make -C /mnt -f Makefile.caas 13 | -------------------------------------------------------------------------------- /examples/6-noddr-sdboot/sdboot.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | # Set tab to 4 spaces to view correctly! 6 | _=0 7 | 8 | z7000_ps_param_pynqz1 = { 9 | # L0 L1 L2_01 L2_10 L2_11 L3_000 L3_001 L3_010 L3_011 L3_100 L3_101 L3_110 L3_111 10 | 'MIO_PIN_00': [ _*'qspi1 ss_b', x, _*'sram/nor cs0', _*'nand cs0', _*'sd0 power', _*'gpio', x, x, x, x, x, x, ''], 11 | 'MIO_PIN_01': [ _*'qspi0 ss_b', x, _*'sram addr25', _*'sram/nor cs1', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 12 | 'MIO_PIN_02': [ _*'qspi0 io0', _*'trace data8', x, _*'nand alen', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 13 | 'MIO_PIN_03': [ _*'qspi0 io1', _*'trace data9', _*'sram/nor data0', _*'nand we_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 14 | 'MIO_PIN_04': [ _*'qspi0 io2', _*'trace data10', _*'sram/nor data1', _*'nand data2', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 15 | 'MIO_PIN_05': [ _*'qspi0 io3', _*'trace data11', _*'sram/nor data2', _*'nand data0', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 16 | 'MIO_PIN_06': [ _*'qspi0 sclk', _*'trace data12', _*'sram/nor data3', _*'nand data1', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 17 | 'MIO_PIN_07': [ x, _*'trace data13', _*'sram/nor oe_b', _*'nand cle_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 18 | 'MIO_PIN_08': [ _*'qspi fbclk', _*'trace data14', x, _*'nand rd_b', _*'sd0 power', _*'gpio', _*'can1 tx', _*'sram/nor bls_b', x, x, x, x, _*'uart1 txd'], 19 | 'MIO_PIN_09': [ _*'qspi1 sclk', _*'trace data15', _*'sram/nor data6', _*'nand data4', _*'sd1 power', _*'gpio', _*'can1 rx', x, x, x, x, x, _*'uart1 rxd'], 20 | 'MIO_PIN_10': [ _*'qspi1 io0', _*'trace data2', _*'sram/nor data7', _*'nand data5', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 21 | 'MIO_PIN_11': [ _*'qspi1 io1', _*'trace data3', _*'sram/nor data4', _*'nand data6', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 22 | 'MIO_PIN_12': [ _*'qspi1 io2', _*'trace clk', x, _*'nand data7', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 23 | 'MIO_PIN_13': [ _*'qspi1 io3', _*'trace ctrl', x, _*'nand data3', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 24 | 'MIO_PIN_14': [ x, _*'trace data0', x, _*'nand busy', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, 1*'uart0 rxd'], 25 | 'MIO_PIN_15': [ x, _*'trace data1', _*'sram/nor addr0', x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, 1*'uart0 txd'], 26 | 'MIO_PIN_16': [ _*'gem0 tx_clk',_*'trace data4', _*'sram/nor addr1', _*'nand data8', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 27 | 'MIO_PIN_17': [ _*'gem0 txd0', _*'trace data5', _*'sram/nor addr2', _*'nand data9', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 cmd', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 28 | 'MIO_PIN_18': [ _*'gem0 txd1', _*'trace data6', _*'sram/nor addr3', _*'nand data10', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 29 | 'MIO_PIN_19': [ _*'gem0 txd2', _*'trace data7', _*'sram/nor addr4', _*'nand data11', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 30 | 'MIO_PIN_20': [ _*'gem0 txd3', x, _*'sram/nor addr5', _*'nand data12', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 31 | 'MIO_PIN_21': [ _*'gem0 tx_ctl',x, _*'sram/nor addr6', _*'nand data13', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 32 | 'MIO_PIN_22': [ _*'gem0 rx_clk',_*'trace data2', _*'sram/nor addr7', _*'nand data14', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 33 | 'MIO_PIN_23': [ _*'gem0 rxd0', _*'trace data3', _*'sram/nor addr8', _*'nand data15', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 34 | 'MIO_PIN_24': [ _*'gem0 rxd1', _*'trace clk', _*'sram/nor addr9', x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 35 | 'MIO_PIN_25': [ _*'gem0 rxd2', _*'trace ctrl', _*'sram/nor addr10',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 36 | 'MIO_PIN_26': [ _*'gem0 rxd3', _*'trace data0', _*'sram/nor addr11',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 37 | 'MIO_PIN_27': [ _*'gem0 rx_clk',_*'trace data1', _*'sram/nor addr12',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 38 | 'MIO_PIN_28': [ _*'gem1 tx_clk',_*'usb0 data4', _*'sram/nor addr13',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 39 | 'MIO_PIN_29': [ _*'gem1 txd0', _*'usb0 dir', _*'sram/nor addr14',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 40 | 'MIO_PIN_30': [ _*'gem1 txd1', _*'usb0 stp', _*'sram/nor addr15',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 41 | 'MIO_PIN_31': [ _*'gem1 txd2', _*'usb0 nxt', _*'sram/nor addr16',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 42 | 'MIO_PIN_32': [ _*'gem1 txd3', _*'usb0 data0', _*'sram/nor addr17',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 43 | 'MIO_PIN_33': [ _*'gem1 tx_ctl',_*'usb0 data1', _*'sram/nor addr18',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 44 | 'MIO_PIN_34': [ _*'gem1 rx_clk',_*'usb0 data2', _*'sram/nor addr19',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 45 | 'MIO_PIN_35': [ _*'gem1 rxd0', _*'usb0 data3', _*'sram/nor addr20',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 46 | 'MIO_PIN_36': [ _*'gem1 rxd1', _*'usb0 clk', _*'sram/nor addr21',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 47 | 'MIO_PIN_37': [ _*'gem1 rxd2', _*'usb0 data5', _*'sram/nor addr22',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 48 | 'MIO_PIN_38': [ _*'gem1 rxd3', _*'usb0 data6', _*'sram/nor addr23',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 49 | 'MIO_PIN_39': [ _*'gem1 rx_ctl',_*'usb0 data7', _*'sram/nor addr24',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 50 | 'MIO_PIN_40': [ x, _*'usb1 data4', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 51 | 'MIO_PIN_41': [ x, _*'usb1 dir', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 52 | 'MIO_PIN_42': [ x, _*'usb1 stp', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, 1*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 53 | 'MIO_PIN_43': [ x, _*'usb1 nxt', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, 1*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 54 | 'MIO_PIN_44': [ x, _*'usb1 data0', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 55 | 'MIO_PIN_45': [ x, _*'usb1 data1', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 56 | 'MIO_PIN_46': [ x, _*'usb1 data2', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 57 | 'MIO_PIN_47': [ x, _*'usb1 data3', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 58 | 'MIO_PIN_48': [ x, _*'usb1 clk', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 59 | 'MIO_PIN_49': [ x, _*'usb1 data5', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 60 | 'MIO_PIN_50': [ x, _*'usb1 data6', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 61 | 'MIO_PIN_51': [ x, _*'usb1 data7', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 62 | 'MIO_PIN_52': [ x, x, x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'swdt clk', _*'mdio0 clk', _*'mdio1 clk', x, _*'uart1 txd'], 63 | 'MIO_PIN_53': [ x, x, x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'swdt rst', _*'mdio0 data', _*'mdio1 data', x, _*'uart1 rxd'], 64 | 'uart0' : { 'baud': 115200 }, 65 | 'freq' : { 'crystal' : 50.0 }, 66 | 'volt' : {'bank0': lvcmos33, 67 | 'bank1': lvcmos18} 68 | } 69 | 70 | if __name__ == '__main__': 71 | z7 = Zynq7000() 72 | z7.param_load(z7000_ps_param_pynqz1) 73 | #z7.SDIO_FREQ.freq = 50 # This affects baud rate?? 74 | z7.ps7_init_gen(zynq7_allregisters) 75 | z7.ps7_init_filewrite('./ps7_init_sdboot/') 76 | -------------------------------------------------------------------------------- /examples/only-foss-can-do/1-apu-oc/README.md: -------------------------------------------------------------------------------- 1 | ### 🔥1. APU Overclock 2 | 3 | We can set the ARM cores' frequency higher than the 667 MHz limit.-- with GenZ, it's as easy as changing one parameter. 4 | 5 | This demo uses the same bitstream as `3-emio`, but the C program is modified to a blinky. Change the APU frequency in `apu_oc.py` and see how far your board can get! 6 | 7 | I got up to 900 MHz with this simplest blinky and loading via JTAG. The power consumption seems to scale linearly with frequency. 8 | 9 | ![](power.png) 10 | 11 | Previously, overclocking (1.1G CPU and 750M DDR) has also been done in [hz12opensource/libresdr](https://github.com/hz12opensource/libresdr/blob/main/patches/fw.diff#L132), by directly modifying the `EMIT_MASKWRITE` arguments. 12 | -------------------------------------------------------------------------------- /examples/only-foss-can-do/1-apu-oc/apu_oc.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # SPDX-License-Identifier: MIT 3 | from zynq7000 import * 4 | 5 | z7000_ps_param_50 = { 6 | 'freq' : { 'crystal' : 33.333333333, 7 | 'apu' : 50.0 8 | } 9 | } 10 | z7000_ps_param_667 = { 11 | 'freq' : { 'crystal' : 33.333333333, 12 | 'apu' : 667.0 13 | } 14 | } 15 | z7000_ps_param_900 = { 16 | 'freq' : { 'crystal' : 33.333333333, 17 | 'apu' : 900.0 18 | } 19 | } 20 | z7000_ps_param_1200 = { 21 | 'freq' : { 'crystal' : 33.333333333, 22 | 'apu' : 1200.0 23 | } 24 | } 25 | 26 | if __name__ == '__main__': 27 | z7 = Zynq7000() 28 | z7.param_load(z7000_ps_param_667) 29 | z7.ps7_init_gen(zynq7_allregisters) 30 | z7.ps7_init_filewrite('./ps7_init_apu_oc/') 31 | -------------------------------------------------------------------------------- /examples/only-foss-can-do/1-apu-oc/blinky.c: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | 3 | int main() 4 | { 5 | volatile int* gpio2_dirm = (volatile int*)0xe000a284; 6 | volatile int* gpio2_oen = (volatile int*)0xe000a288; 7 | volatile int* gpio2_data_out = (volatile int*)0xe000a048; 8 | volatile int* gpio2_data_in = (volatile int*)0xe000a068; 9 | int out_pins_mask = 0xf; 10 | int in_pins_mask = 0x30; 11 | 12 | *gpio2_dirm = out_pins_mask; 13 | *gpio2_oen = out_pins_mask; 14 | int on = 0; 15 | while (1) { 16 | on = !on; 17 | for (int i = 0; i < 20000000; i++); 18 | /**gpio2_data_out = 0x5;*/ 19 | *gpio2_data_out = (on<<3) + (!on<<2) + (on<<1) + !on; 20 | } 21 | return 0; 22 | } 23 | -------------------------------------------------------------------------------- /examples/only-foss-can-do/1-apu-oc/lscript.ld: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | 3 | SECTIONS 4 | { 5 | . = 0xFFFF0000; 6 | .text : { *(.text) } 7 | .data : { *(.data) } 8 | .bss : { *(.bss) } 9 | } 10 | -------------------------------------------------------------------------------- /examples/only-foss-can-do/1-apu-oc/power.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/regymm/GenZ/842a8f6471bd0b0765f24bc2eaaa1d8f82347dde/examples/only-foss-can-do/1-apu-oc/power.png -------------------------------------------------------------------------------- /ps7_init_template/ps7_init.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved. 3 | * 4 | * This program is free software; you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation; either version 2 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License along 15 | * with this program; if not, see 16 | * 17 | * 18 | ******************************************************************************/ 19 | /****************************************************************************/ 20 | /** 21 | * 22 | * @file ps7_init_gpl.c 23 | * 24 | * This file is automatically generated 25 | * 26 | *****************************************************************************/ 27 | 28 | #include "ps7_init.h" 29 | 30 | unsigned long ps7_pll_init_data_3_0[] = { 31 | PS7_PLL_INIT_DATA_TBD 32 | EMIT_EXIT(), 33 | }; 34 | 35 | unsigned long ps7_clock_init_data_3_0[] = { 36 | PS7_CLOCK_INIT_DATA_TBD 37 | EMIT_EXIT(), 38 | }; 39 | 40 | unsigned long ps7_ddr_init_data_3_0[] = { 41 | PS7_DDR_INIT_DATA_TBD 42 | EMIT_EXIT(), 43 | }; 44 | 45 | unsigned long ps7_mio_init_data_3_0[] = { 46 | PS7_MIO_INIT_DATA_TBD 47 | EMIT_EXIT(), 48 | }; 49 | 50 | unsigned long ps7_peripherals_init_data_3_0[] = { 51 | PS7_PERIPHERALS_INIT_DATA_TBD 52 | EMIT_EXIT(), 53 | }; 54 | 55 | unsigned long ps7_post_config_3_0[] = { 56 | PS7_POST_CONFIG_TBD 57 | EMIT_EXIT(), 58 | }; 59 | 60 | unsigned long ps7_debug_3_0[] = { 61 | }; 62 | 63 | #include "xil_io.h" 64 | #define PS7_MASK_POLL_TIME 100000000 65 | 66 | char* 67 | getPS7MessageInfo(unsigned key) { 68 | 69 | char* err_msg = ""; 70 | switch (key) { 71 | case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; 72 | case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; 73 | case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; 74 | case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; 75 | case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; 76 | case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; 77 | default: err_msg = "Undefined error status"; break; 78 | } 79 | 80 | return err_msg; 81 | } 82 | 83 | unsigned long 84 | ps7GetSiliconVersion () { 85 | // Read PS version from MCTRL register [31:28] 86 | unsigned long mask = 0xF0000000; 87 | unsigned long *addr = (unsigned long*) 0XF8007080; 88 | unsigned long ps_version = (*addr & mask) >> 28; 89 | return ps_version; 90 | } 91 | 92 | void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { 93 | volatile unsigned long *addr = (volatile unsigned long*) add; 94 | *addr = ( val & mask ) | ( *addr & ~mask); 95 | xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); 96 | } 97 | 98 | 99 | int mask_poll(unsigned long add , unsigned long mask ) { 100 | volatile unsigned long *addr = (volatile unsigned long*) add; 101 | int i = 0; 102 | while (!(*addr & mask)) { 103 | if (i == PS7_MASK_POLL_TIME) { 104 | return -1; 105 | } 106 | i++; 107 | } 108 | xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); 109 | return 1; 110 | } 111 | 112 | unsigned long mask_read(unsigned long add , unsigned long mask ) { 113 | volatile unsigned long *addr = (volatile unsigned long*) add; 114 | unsigned long val = (*addr & mask); 115 | xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); 116 | return val; 117 | } 118 | 119 | 120 | 121 | int 122 | ps7_config(unsigned long * ps7_config_init) 123 | { 124 | unsigned long *ptr = ps7_config_init; 125 | 126 | unsigned long opcode; // current instruction .. 127 | unsigned long args[16]; // no opcode has so many args ... 128 | int numargs; // number of arguments of this instruction 129 | int j; // general purpose index 130 | 131 | volatile unsigned long *addr; // some variable to make code readable 132 | unsigned long val,mask; // some variable to make code readable 133 | 134 | int finish = -1 ; // loop while this is negative ! 135 | int i = 0; // Timeout variable 136 | 137 | while( finish < 0 ) { 138 | numargs = ptr[0] & 0xF; 139 | opcode = ptr[0] >> 4; 140 | 141 | for( j = 0 ; j < numargs ; j ++ ) 142 | args[j] = ptr[j+1]; 143 | ptr += numargs + 1; 144 | 145 | 146 | switch ( opcode ) { 147 | 148 | case OPCODE_EXIT: 149 | finish = PS7_INIT_SUCCESS; 150 | break; 151 | 152 | case OPCODE_CLEAR: 153 | addr = (unsigned long*) args[0]; 154 | *addr = 0; 155 | break; 156 | 157 | case OPCODE_WRITE: 158 | addr = (unsigned long*) args[0]; 159 | val = args[1]; 160 | *addr = val; 161 | break; 162 | 163 | case OPCODE_MASKWRITE: 164 | addr = (unsigned long*) args[0]; 165 | mask = args[1]; 166 | val = args[2]; 167 | *addr = ( val & mask ) | ( *addr & ~mask); 168 | break; 169 | 170 | case OPCODE_MASKPOLL: 171 | addr = (unsigned long*) args[0]; 172 | mask = args[1]; 173 | i = 0; 174 | while (!(*addr & mask)) { 175 | if (i == PS7_MASK_POLL_TIME) { 176 | finish = PS7_INIT_TIMEOUT; 177 | break; 178 | } 179 | i++; 180 | } 181 | break; 182 | case OPCODE_MASKDELAY: 183 | addr = (unsigned long*) args[0]; 184 | mask = args[1]; 185 | int delay = get_number_of_cycles_for_delay(mask); 186 | perf_reset_and_start_timer(); 187 | while ((*addr < delay)) { 188 | } 189 | break; 190 | default: 191 | finish = PS7_INIT_CORRUPT; 192 | break; 193 | } 194 | } 195 | return finish; 196 | } 197 | 198 | unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; 199 | unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; 200 | unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; 201 | unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; 202 | unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; 203 | 204 | int 205 | ps7_post_config() 206 | { 207 | // Get the PS_VERSION on run time 208 | unsigned long si_ver = ps7GetSiliconVersion (); 209 | int ret = -1; 210 | if (si_ver == PCW_SILICON_VERSION_1) { 211 | while (1); 212 | /*ret = ps7_config (ps7_post_config_1_0);*/ 213 | /*if (ret != PS7_INIT_SUCCESS) return ret;*/ 214 | } else if (si_ver == PCW_SILICON_VERSION_2) { 215 | while (1); 216 | /*ret = ps7_config (ps7_post_config_2_0);*/ 217 | /*if (ret != PS7_INIT_SUCCESS) return ret;*/ 218 | } else { 219 | ret = ps7_config (ps7_post_config_3_0); 220 | if (ret != PS7_INIT_SUCCESS) return ret; 221 | } 222 | return PS7_INIT_SUCCESS; 223 | } 224 | 225 | int 226 | ps7_debug() 227 | { 228 | /*// Get the PS_VERSION on run time*/ 229 | /*unsigned long si_ver = ps7GetSiliconVersion ();*/ 230 | /*int ret = -1;*/ 231 | /*if (si_ver == PCW_SILICON_VERSION_1) {*/ 232 | /*ret = ps7_config (ps7_debug_1_0);*/ 233 | /*if (ret != PS7_INIT_SUCCESS) return ret;*/ 234 | /*} else if (si_ver == PCW_SILICON_VERSION_2) {*/ 235 | /*ret = ps7_config (ps7_debug_2_0);*/ 236 | /*if (ret != PS7_INIT_SUCCESS) return ret;*/ 237 | /*} else {*/ 238 | /*ret = ps7_config (ps7_debug_3_0);*/ 239 | /*if (ret != PS7_INIT_SUCCESS) return ret;*/ 240 | /*}*/ 241 | return PS7_INIT_SUCCESS; 242 | } 243 | 244 | int 245 | ps7_init() 246 | { 247 | // Get the PS_VERSION on run time 248 | unsigned long si_ver = ps7GetSiliconVersion (); 249 | xil_printf ("\n Silicon Version : %d.0, only 3 will be supported!!", si_ver); 250 | int ret; 251 | //int pcw_ver = 0; 252 | 253 | if (si_ver == PCW_SILICON_VERSION_1) { 254 | while (1); 255 | /*ps7_mio_init_data = ps7_mio_init_data_1_0;*/ 256 | /*ps7_pll_init_data = ps7_pll_init_data_1_0;*/ 257 | /*ps7_clock_init_data = ps7_clock_init_data_1_0;*/ 258 | /*ps7_ddr_init_data = ps7_ddr_init_data_1_0;*/ 259 | /*ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;*/ 260 | //pcw_ver = 1; 261 | 262 | } else if (si_ver == PCW_SILICON_VERSION_2) { 263 | while (1); 264 | /*ps7_mio_init_data = ps7_mio_init_data_2_0;*/ 265 | /*ps7_pll_init_data = ps7_pll_init_data_2_0;*/ 266 | /*ps7_clock_init_data = ps7_clock_init_data_2_0;*/ 267 | /*ps7_ddr_init_data = ps7_ddr_init_data_2_0;*/ 268 | /*ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;*/ 269 | //pcw_ver = 2; 270 | 271 | } else { 272 | ps7_mio_init_data = ps7_mio_init_data_3_0; 273 | ps7_pll_init_data = ps7_pll_init_data_3_0; 274 | ps7_clock_init_data = ps7_clock_init_data_3_0; 275 | ps7_ddr_init_data = ps7_ddr_init_data_3_0; 276 | ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; 277 | //pcw_ver = 3; 278 | } 279 | 280 | // MIO init 281 | ret = ps7_config (ps7_mio_init_data); 282 | if (ret != PS7_INIT_SUCCESS) return ret; 283 | 284 | // PLL init 285 | ret = ps7_config (ps7_pll_init_data); 286 | if (ret != PS7_INIT_SUCCESS) return ret; 287 | 288 | // Clock init 289 | ret = ps7_config (ps7_clock_init_data); 290 | if (ret != PS7_INIT_SUCCESS) return ret; 291 | 292 | // DDR init 293 | ret = ps7_config (ps7_ddr_init_data); 294 | if (ret != PS7_INIT_SUCCESS) return ret; 295 | 296 | 297 | 298 | // Peripherals init 299 | ret = ps7_config (ps7_peripherals_init_data); 300 | if (ret != PS7_INIT_SUCCESS) return ret; 301 | //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); 302 | return PS7_INIT_SUCCESS; 303 | } 304 | 305 | 306 | 307 | 308 | /* For delay calculation using global timer */ 309 | 310 | /* start timer */ 311 | void perf_start_clock(void) 312 | { 313 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable 314 | (1 << 3) | // Auto-increment 315 | (0 << 8) // Pre-scale 316 | ); 317 | } 318 | 319 | /* stop timer and reset timer count regs */ 320 | void perf_reset_clock(void) 321 | { 322 | perf_disable_clock(); 323 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; 324 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; 325 | } 326 | 327 | /* Compute mask for given delay in milliseconds*/ 328 | int get_number_of_cycles_for_delay(unsigned int delay) 329 | { 330 | // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) 331 | return (APU_FREQ*delay/(2*1000)); 332 | 333 | } 334 | 335 | /* stop timer */ 336 | void perf_disable_clock(void) 337 | { 338 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; 339 | } 340 | 341 | void perf_reset_and_start_timer() 342 | { 343 | perf_reset_clock(); 344 | perf_start_clock(); 345 | } 346 | 347 | 348 | 349 | 350 | -------------------------------------------------------------------------------- /ps7_init_template/ps7_init.h: -------------------------------------------------------------------------------- 1 | // modifed for GenZ 2 | /****************************************************************************** 3 | * 4 | * Copyright (C) 2018 Xilinx, Inc. All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, see 18 | * 19 | * 20 | ******************************************************************************/ 21 | /****************************************************************************/ 22 | /** 23 | * 24 | * @file ps7_init_gpl.h 25 | * 26 | * This file can be included in FSBL code 27 | * to get prototype of ps7_init() function 28 | * and error codes 29 | * 30 | *****************************************************************************/ 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | 37 | //typedef unsigned int u32; 38 | 39 | 40 | /** do we need to make this name more unique ? **/ 41 | //extern u32 ps7_init_data[]; 42 | extern unsigned long * ps7_ddr_init_data; 43 | extern unsigned long * ps7_mio_init_data; 44 | extern unsigned long * ps7_pll_init_data; 45 | extern unsigned long * ps7_clock_init_data; 46 | extern unsigned long * ps7_peripherals_init_data; 47 | 48 | 49 | 50 | #define OPCODE_EXIT 0U 51 | #define OPCODE_CLEAR 1U 52 | #define OPCODE_WRITE 2U 53 | #define OPCODE_MASKWRITE 3U 54 | #define OPCODE_MASKPOLL 4U 55 | #define OPCODE_MASKDELAY 5U 56 | #define NEW_PS7_ERR_CODE 1 57 | 58 | /* Encode number of arguments in last nibble */ 59 | #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) 60 | #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr 61 | #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val 62 | #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val 63 | #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask 64 | #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask 65 | 66 | /* Returns codes of PS7_Init */ 67 | #define PS7_INIT_SUCCESS (0) // 0 is success in good old C 68 | #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now 69 | #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out 70 | #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init 71 | #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit 72 | #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init 73 | 74 | 75 | /* Silicon Versions */ 76 | #define PCW_SILICON_VERSION_1 0 77 | #define PCW_SILICON_VERSION_2 1 78 | #define PCW_SILICON_VERSION_3 2 79 | 80 | /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ 81 | #define PS7_POST_CONFIG 82 | 83 | /* Freq of all peripherals */ 84 | 85 | #define APU_FREQ APU_FREQ_TBD 86 | #define DDR_FREQ DDR_FREQ_TBD 87 | #define DCI_FREQ DCI_FREQ_TBD 88 | #define QSPI_FREQ QSPI_FREQ_TBD 89 | #define SMC_FREQ SMC_FREQ_TBD 90 | #define ENET0_FREQ ENET0_FREQ_TBD 91 | #define ENET1_FREQ ENET1_FREQ_TBD 92 | #define USB0_FREQ USB0_FREQ_TBD 93 | #define USB1_FREQ USB1_FREQ_TBD 94 | #define SDIO_FREQ SDIO_FREQ_TBD 95 | #define UART_FREQ UART_FREQ_TBD 96 | #define SPI_FREQ SPI_FREQ_TBD 97 | #define I2C_FREQ I2C_FREQ_TBD 98 | #define WDT_FREQ WDT_FREQ_TBD 99 | #define TTC_FREQ TTC_FREQ_TBD 100 | #define CAN_FREQ CAN_FREQ_TBD 101 | #define PCAP_FREQ PCAP_FREQ_TBD 102 | #define TPIU_FREQ TPIU_FREQ_TBD 103 | #define FPGA0_FREQ FPGA0_FREQ_TBD 104 | #define FPGA1_FREQ FPGA1_FREQ_TBD 105 | #define FPGA2_FREQ FPGA2_FREQ_TBD 106 | #define FPGA3_FREQ FPGA3_FREQ_TBD 107 | 108 | 109 | /* For delay calculation using global registers*/ 110 | #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 111 | #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 112 | #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 113 | #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 114 | 115 | int ps7_config( unsigned long*); 116 | int ps7_init(); 117 | int ps7_post_config(); 118 | int ps7_debug(); 119 | char* getPS7MessageInfo(unsigned key); 120 | 121 | void perf_start_clock(void); 122 | void perf_disable_clock(void); 123 | void perf_reset_clock(void); 124 | void perf_reset_and_start_timer(); 125 | int get_number_of_cycles_for_delay(unsigned int delay); 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | -------------------------------------------------------------------------------- /ps7_init_template/ps7_init.tcl: -------------------------------------------------------------------------------- 1 | proc ps7_pll_init_data_3_0 {} { 2 | PS7_PLL_INIT_DATA_TBD 3 | } 4 | proc ps7_clock_init_data_3_0 {} { 5 | PS7_CLOCK_INIT_DATA_TBD 6 | } 7 | proc ps7_mio_init_data_3_0 {} { 8 | PS7_MIO_INIT_DATA_TBD 9 | } 10 | proc ps7_ddr_init_data_3_0 {} { 11 | PS7_DDR_INIT_DATA_TBD 12 | } 13 | proc ps7_peripherals_init_data_3_0 {} { 14 | PS7_PERIPHERALS_INIT_DATA_TBD 15 | } 16 | proc ps7_post_config_3_0 {} { 17 | PS7_POST_CONFIG_TBD 18 | } 19 | 20 | proc mask_poll { addr mask } { 21 | set cnt 1 22 | set val 0 23 | while { $val == 0 } { 24 | set val "0x[string range [mrd $addr] end-8 end]" 25 | set val [expr $val & $mask] 26 | incr cnt 27 | if { $cnt == 100000 } { 28 | puts "MASKPOLL FAILED AT ADDRESS: $addr MASK: $mask" 29 | break 30 | } 31 | } 32 | } 33 | 34 | proc ps7_post_config {} { 35 | set saved_mode [configparams force-mem-accesses] 36 | configparams force-mem-accesses 1 37 | ps7_post_config_3_0 38 | configparams force-mem-accesses $saved_mode 39 | } 40 | 41 | proc ps7_init {} { 42 | ps7_mio_init_data_3_0 43 | ps7_pll_init_data_3_0 44 | ps7_clock_init_data_3_0 45 | ps7_ddr_init_data_3_0 46 | ps7_peripherals_init_data_3_0 47 | } 48 | -------------------------------------------------------------------------------- /ps7_init_template/xparameters.h: -------------------------------------------------------------------------------- 1 | // Modified for GenZ 2 | /****************************************************************************** 3 | * Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. 4 | * Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | * SPDX-License-Identifier: MIT 6 | ******************************************************************************/ 7 | #ifndef XPARAMETERS_H 8 | #define XPARAMETERS_H 9 | 10 | /* Definition for CPU ID */ 11 | #define XPAR_CPU_ID 0U 12 | 13 | /* Canonical definitions for peripheral PS7_CORTEXA9_0 */ 14 | #define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ APU_FREQ_TBD 15 | 16 | #include "xparameters_ps.h" 17 | 18 | #define STDIN_BASEADDRESS UART_BASEADDR_TBD 19 | #define STDOUT_BASEADDRESS UART_BASEADDR_TBD 20 | 21 | /* Platform specific definitions */ 22 | #define PLATFORM_ZYNQ 23 | 24 | /* Definitions for sleep timer configuration */ 25 | #define XSLEEP_TIMER_IS_DEFAULT_TIMER 26 | 27 | /* Definitions for driver DEVCFG */ 28 | #define XPAR_XDCFG_NUM_INSTANCES 1U 29 | /* Canonical definitions for peripheral PS7_DEV_CFG_0 */ 30 | #define XPAR_XDCFG_0_DEVICE_ID 0 31 | #define XPAR_XDCFG_0_BASEADDR 0xF8007000U 32 | #define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU 33 | 34 | /* Definitions for driver DMAPS */ 35 | #define XPAR_XDMAPS_NUM_INSTANCES 2 36 | /* Canonical definitions for peripheral PS7_DMA_NS */ 37 | #define XPAR_XDMAPS_0_DEVICE_ID 0 38 | #define XPAR_XDMAPS_0_BASEADDR 0xF8004000 39 | #define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF 40 | /* Canonical definitions for peripheral PS7_DMA_S */ 41 | #define XPAR_XDMAPS_1_DEVICE_ID 1 42 | #define XPAR_XDMAPS_1_BASEADDR 0xF8003000 43 | #define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF 44 | 45 | 46 | /* Definitions for driver GPIOPS */ 47 | #define XPAR_XGPIOPS_NUM_INSTANCES 1 48 | /* Canonical definitions for peripheral PS7_GPIO_0 */ 49 | #define XPAR_XGPIOPS_0_DEVICE_ID 0 50 | #define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 51 | #define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF 52 | 53 | // QSPI not supported by GenZ for now 54 | /* Definitions for driver QSPIPS */ 55 | #define XPAR_XQSPIPS_NUM_INSTANCES QSPI_NUM_TBD 56 | /* Canonical definitions for peripheral PS7_QSPI_0 */ 57 | #define XPAR_XQSPIPS_0_DEVICE_ID 0 58 | #define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 59 | #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF 60 | #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ QSPI_FREQ_TBD 61 | #define XPAR_XQSPIPS_0_QSPI_MODE 0 62 | #define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 63 | 64 | /* Definitions for driver SCUGIC */ 65 | #define XPAR_XSCUGIC_NUM_INSTANCES 1U 66 | /* Canonical definitions for peripheral PS7_SCUGIC_0 */ 67 | #define XPAR_SCUGIC_0_DEVICE_ID 0U 68 | #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U 69 | #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU 70 | #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U 71 | 72 | /* Definitions for driver SCUTIMER */ 73 | #define XPAR_XSCUTIMER_NUM_INSTANCES 1 74 | /* Canonical definitions for peripheral PS7_SCUTIMER_0 */ 75 | #define XPAR_XSCUTIMER_0_DEVICE_ID 0 76 | #define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 77 | #define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F 78 | 79 | /* Definitions for driver SCUWDT */ 80 | #define XPAR_XSCUWDT_NUM_INSTANCES 1 81 | /* Canonical definitions for peripheral PS7_SCUWDT_0 */ 82 | #define XPAR_SCUWDT_0_DEVICE_ID 0 83 | #define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 84 | #define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF 85 | 86 | /* Definitions for driver SDPS */ 87 | #define XPAR_XSDPS_NUM_INSTANCES SDIO_NUM_TBD 88 | // We just directly generate to XPAR_X.... 89 | /* Definitions for peripheral PS7_SD_0 */ 90 | #define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 91 | /* Canonical definitions for peripheral PS7_SD_0 */ 92 | #define XPAR_XSDPS_0_DEVICE_ID 0 93 | #define XPAR_XSDPS_0_BASEADDR SDIO_BASEADDR_TBD 94 | #define XPAR_XSDPS_0_HIGHADDR SDIO_HIGHADDR_TBD 95 | #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ SDIO_FREQ_TBD 96 | #define XPAR_XSDPS_0_HAS_CD 0 97 | #define XPAR_XSDPS_0_HAS_WP 0 98 | #define XPAR_XSDPS_0_BUS_WIDTH 0 99 | #define XPAR_XSDPS_0_MIO_BANK 0 // unused, don't care 100 | #define XPAR_XSDPS_0_HAS_EMIO 0 // unused, don't care 101 | #define XPAR_XSDPS_0_SLOT_TYPE 0 // unused, don't care 102 | #define XPAR_XSDPS_0_IS_CACHE_COHERENT 0 103 | #define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0 104 | #define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0 105 | #define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0 106 | #define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0 107 | #define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0 108 | #define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0 109 | #define XPAR_XSDPS_0_CLK_200_DDR_OTAP_DLY 0 110 | 111 | /* Definitions for driver UARTPS */ 112 | #define XPAR_XUARTPS_NUM_INSTANCES UART_NUM_TBD 113 | #define XPAR_XUARTPS_0_DEVICE_ID 0 114 | #define XPAR_XUARTPS_0_BASEADDR UART_BASEADDR_TBD 115 | #define XPAR_XUARTPS_0_HIGHADDR UART_HIGHADDR_TBD 116 | #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ UART_FREQ_TBD 117 | #define XPAR_XUARTPS_0_HAS_MODEM 0 118 | 119 | /* Definitions for driver XADCPS */ 120 | #define XPAR_XADCPS_NUM_INSTANCES 1 121 | #define XPAR_XADCPS_0_DEVICE_ID 0 122 | #define XPAR_XADCPS_0_BASEADDR 0xF8007100 123 | #define XPAR_XADCPS_0_HIGHADDR 0xF8007120 124 | 125 | /* Xilinx FAT File System Library (XilFFs) User Settings */ 126 | #define FILE_SYSTEM_INTERFACE_SD 127 | #define FILE_SYSTEM_USE_MKFS 128 | #define FILE_SYSTEM_NUM_LOGIC_VOL 2 129 | #define FILE_SYSTEM_USE_STRFUNC 0 130 | #define FILE_SYSTEM_SET_FS_RPATH 0 131 | #define FILE_SYSTEM_WORD_ACCESS 132 | #endif 133 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-clkonly-2.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_full_clk-2 3 | set HDF_DIR ./hdf 4 | set HDF_FILE clk-2.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {40} CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {600} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {120} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {75} CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {33.333333} CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1}] [get_bd_cells processing_system7_0] 11 | validate_bd_design 12 | save_bd_design 13 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 14 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 15 | update_compile_order -fileset sources_1 16 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 17 | file mkdir ${HDF_DIR} 18 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 19 | file mkdir ${HDF_DIR} 20 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 21 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 22 | 23 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-clkonly.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_full_clk-1 3 | set HDF_DIR ./hdf 4 | set HDF_FILE clk-1.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | validate_bd_design 11 | save_bd_design 12 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 13 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 14 | update_compile_order -fileset sources_1 15 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 16 | file mkdir ${HDF_DIR} 17 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 18 | file mkdir ${HDF_DIR} 19 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 20 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 21 | 22 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-full-3.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_full 3 | set HDF_DIR ./hdf 4 | set HDF_FILE 3.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET1_ENET1_IO {MIO 28 .. 39} CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET1_GRP_MDIO_IO {EMIO} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {MIO 16 .. 21} CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 22 .. 23} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB1_USB1_IO {MIO 40 .. 51} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} CONFIG.PCW_UART1_BAUD_RATE {9600} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] [get_bd_cells processing_system7_0] 12 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 24 | set_property -dict [list CONFIG.PCW_USE_S_AXI_GP1 {0} CONFIG.PCW_USE_S_AXI_ACP {0} CONFIG.PCW_USE_S_AXI_HP1 {0} CONFIG.PCW_USE_S_AXI_HP2 {0} CONFIG.PCW_USE_S_AXI_HP3 {0} CONFIG.PCW_USE_DMA0 {0} CONFIG.PCW_USE_DMA1 {0} CONFIG.PCW_USE_DMA2 {0} CONFIG.PCW_USE_DMA3 {0} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] [get_bd_cells processing_system7_0] 25 | validate_bd_design 26 | save_bd_design 27 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 28 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 29 | update_compile_order -fileset sources_1 30 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 31 | file mkdir ${HDF_DIR} 32 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 33 | file mkdir ${HDF_DIR} 34 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 35 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 36 | 37 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-full-4.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_full 3 | set HDF_DIR ./hdf 4 | set HDF_FILE 4.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET1_ENET1_IO {MIO 28 .. 39} CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET1_GRP_MDIO_IO {EMIO} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {MIO 16 .. 21} CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 22 .. 23} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB1_USB1_IO {MIO 40 .. 51} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} CONFIG.PCW_UART1_BAUD_RATE {9600} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] [get_bd_cells processing_system7_0] 12 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 24 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {0} CONFIG.PCW_EN_CLK2_PORT {0} CONFIG.PCW_EN_CLK3_PORT {0}] [get_bd_cells processing_system7_0] 25 | validate_bd_design 26 | save_bd_design 27 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 28 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 29 | update_compile_order -fileset sources_1 30 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 31 | file mkdir ${HDF_DIR} 32 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 33 | file mkdir ${HDF_DIR} 34 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 35 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 36 | 37 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-full-5.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_full 3 | set HDF_DIR ./hdf 4 | set HDF_FILE 5.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET1_ENET1_IO {MIO 28 .. 39} CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET1_GRP_MDIO_IO {EMIO} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {MIO 16 .. 21} CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 22 .. 23} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB1_USB1_IO {MIO 40 .. 51} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} CONFIG.PCW_UART1_BAUD_RATE {9600} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] [get_bd_cells processing_system7_0] 12 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 24 | set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.12345} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.54321} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.6789} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.9876}] [get_bd_cells processing_system7_0] 25 | validate_bd_design 26 | save_bd_design 27 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 28 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 29 | update_compile_order -fileset sources_1 30 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 31 | file mkdir ${HDF_DIR} 32 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 33 | file mkdir ${HDF_DIR} 34 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 35 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 36 | 37 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-full.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_full 3 | set HDF_DIR ./hdf 4 | set HDF_FILE 2.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET1_ENET1_IO {MIO 28 .. 39} CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {1} CONFIG.PCW_ENET1_GRP_MDIO_IO {EMIO} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {MIO 16 .. 21} CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 22 .. 23} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} CONFIG.PCW_USB1_PERIPHERAL_ENABLE {1} CONFIG.PCW_USB1_USB1_IO {MIO 40 .. 51} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} CONFIG.PCW_UART1_BAUD_RATE {9600} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] [get_bd_cells processing_system7_0] 12 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 24 | validate_bd_design 25 | save_bd_design 26 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 27 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 28 | update_compile_order -fileset sources_1 29 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 30 | file mkdir ${HDF_DIR} 31 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 32 | file mkdir ${HDF_DIR} 33 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 34 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 35 | 36 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-2uarts.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-2uarts.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | 27 | # other options 28 | # set_property -dict [list CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_PULLUP {disabled}] [get_bd_cells processing_system7_0] 29 | #set_property -dict [list CONFIG.PCW_MIO_10_SLEW {fast} CONFIG.PCW_MIO_11_SLEW {fast}] [get_bd_cells processing_system7_0] 30 | 31 | validate_bd_design 32 | save_bd_design 33 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 34 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 35 | update_compile_order -fileset sources_1 36 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 37 | file mkdir ${HDF_DIR} 38 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 39 | file mkdir ${HDF_DIR} 40 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 41 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 42 | 43 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-bankvoltage.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-bankvolt.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | # LVCMOS 3.3V, 2.5V, 1.8V 27 | # HSTL 1.8V 28 | set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V}] [get_bd_cells processing_system7_0] 29 | 30 | validate_bd_design 31 | save_bd_design 32 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 33 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 34 | update_compile_order -fileset sources_1 35 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 36 | file mkdir ${HDF_DIR} 37 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 38 | file mkdir ${HDF_DIR} 39 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 40 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 41 | 42 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-clkfreq-2.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-clkfreq-2.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {60} CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {620} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {30} CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {40} CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50}] [get_bd_cells processing_system7_0] 27 | 28 | 29 | validate_bd_design 30 | save_bd_design 31 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 32 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 33 | update_compile_order -fileset sources_1 34 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 35 | file mkdir ${HDF_DIR} 36 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 37 | file mkdir ${HDF_DIR} 38 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 39 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 40 | 41 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-clkfreq.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-clkfreq.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {40} CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {620} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {30} CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {40} CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50}] [get_bd_cells processing_system7_0] 27 | 28 | 29 | validate_bd_design 30 | save_bd_design 31 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 32 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 33 | update_compile_order -fileset sources_1 34 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 35 | file mkdir ${HDF_DIR} 36 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 37 | file mkdir ${HDF_DIR} 38 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 39 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 40 | 41 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-sd-emio.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-sd-emio.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {EMIO}] [get_bd_cells processing_system7_0] 27 | 28 | 29 | # other options 30 | # set_property -dict [list CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_PULLUP {disabled}] [get_bd_cells processing_system7_0] 31 | #set_property -dict [list CONFIG.PCW_MIO_10_SLEW {fast} CONFIG.PCW_MIO_11_SLEW {fast}] [get_bd_cells processing_system7_0] 32 | 33 | validate_bd_design 34 | save_bd_design 35 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 36 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 37 | update_compile_order -fileset sources_1 38 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 39 | file mkdir ${HDF_DIR} 40 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 41 | file mkdir ${HDF_DIR} 42 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 43 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 44 | 45 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-sd.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-sd.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SD0_SD0_IO {MIO 16 .. 21} ] [get_bd_cells processing_system7_0] 27 | 28 | 29 | # other options 30 | # set_property -dict [list CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_PULLUP {disabled}] [get_bd_cells processing_system7_0] 31 | #set_property -dict [list CONFIG.PCW_MIO_10_SLEW {fast} CONFIG.PCW_MIO_11_SLEW {fast}] [get_bd_cells processing_system7_0] 32 | 33 | validate_bd_design 34 | save_bd_design 35 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 36 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 37 | update_compile_order -fileset sources_1 38 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 39 | file mkdir ${HDF_DIR} 40 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 41 | file mkdir ${HDF_DIR} 42 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 43 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 44 | 45 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-uart-elsegpio.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-uart-elsegpio.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 10 .. 11} CONFIG.PCW_UART0_BAUD_RATE {115200}] [get_bd_cells processing_system7_0] 27 | 28 | set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] [get_bd_cells processing_system7_0] 29 | set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] [get_bd_cells processing_system7_0] 30 | 31 | 32 | # other options 33 | # set_property -dict [list CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_PULLUP {disabled}] [get_bd_cells processing_system7_0] 34 | #set_property -dict [list CONFIG.PCW_MIO_10_SLEW {fast} CONFIG.PCW_MIO_11_SLEW {fast}] [get_bd_cells processing_system7_0] 35 | 36 | validate_bd_design 37 | save_bd_design 38 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 39 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 40 | update_compile_order -fileset sources_1 41 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 42 | file mkdir ${HDF_DIR} 43 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 44 | file mkdir ${HDF_DIR} 45 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 46 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 47 | 48 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-uart-emio.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-uart-emio.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 10 .. 11} CONFIG.PCW_UART0_BAUD_RATE {115200}] [get_bd_cells processing_system7_0] 27 | 28 | # other options 29 | # set_property -dict [list CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_PULLUP {disabled}] [get_bd_cells processing_system7_0] 30 | #set_property -dict [list CONFIG.PCW_MIO_10_SLEW {fast} CONFIG.PCW_MIO_11_SLEW {fast}] [get_bd_cells processing_system7_0] 31 | 32 | validate_bd_design 33 | save_bd_design 34 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 35 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 36 | update_compile_order -fileset sources_1 37 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 38 | file mkdir ${HDF_DIR} 39 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 40 | file mkdir ${HDF_DIR} 41 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 42 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 43 | 44 | -------------------------------------------------------------------------------- /tcl_fuzz/create-ps7-project-noddr-noperiph-clkonly-uart.tcl: -------------------------------------------------------------------------------- 1 | set PROJ_DIR . 2 | set PROJ_NAME ps_project_auto_noddr 3 | set HDF_DIR ./hdf 4 | set HDF_FILE noddr-0-uart.hdf 5 | create_project -force ${PROJ_NAME} ${PROJ_DIR}/${PROJ_NAME} -part xc7z020clg400-1 6 | create_bd_design "design_1" 7 | create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 8 | apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] 9 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] 10 | set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_EN_CLK2_PORT {1} CONFIG.PCW_EN_CLK3_PORT {1} CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} CONFIG.PCW_UIPARAM_DDR_ENABLE {0}] [get_bd_cells processing_system7_0] 11 | set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1} CONFIG.PCW_USE_DMA0 {1} CONFIG.PCW_USE_DMA1 {1} CONFIG.PCW_USE_DMA2 {1} CONFIG.PCW_USE_DMA3 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {0} ] [get_bd_cells processing_system7_0] 12 | delete_bd_objs [get_bd_intf_nets processing_system7_0_DDR] 13 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] 14 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] 15 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP1_ACLK] 16 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_ACP_ACLK] 17 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] 18 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] 19 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] 20 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] 21 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA0_ACLK] 22 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA1_ACLK] 23 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA2_ACLK] 24 | connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/DMA3_ACLK] 25 | 26 | set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART0_UART0_IO {MIO 10 .. 11} CONFIG.PCW_UART0_BAUD_RATE {115200}] [get_bd_cells processing_system7_0] 27 | 28 | # other options 29 | # set_property -dict [list CONFIG.PCW_MIO_10_PULLUP {disabled} CONFIG.PCW_MIO_11_PULLUP {disabled}] [get_bd_cells processing_system7_0] 30 | #set_property -dict [list CONFIG.PCW_MIO_10_SLEW {fast} CONFIG.PCW_MIO_11_SLEW {fast}] [get_bd_cells processing_system7_0] 31 | 32 | validate_bd_design 33 | save_bd_design 34 | make_wrapper -files [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] -top 35 | add_files -norecurse ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v 36 | update_compile_order -fileset sources_1 37 | generate_target all [get_files ${PROJ_DIR}/${PROJ_NAME}/${PROJ_NAME}.srcs/sources_1/bd/design_1/design_1.bd] 38 | file mkdir ${HDF_DIR} 39 | write_hwdef -force -file ${HDF_DIR}/${HDF_FILE} 40 | file mkdir ${HDF_DIR} 41 | file mkdir ${HDF_DIR}/[file rootname ${HDF_FILE}] 42 | exec unzip ${HDF_DIR}/${HDF_FILE} -d ${HDF_DIR}/[file rootname ${HDF_FILE}] 43 | 44 | -------------------------------------------------------------------------------- /tcl_fuzz/note.txt: -------------------------------------------------------------------------------- 1 | 1: all default 2 | 2: full with many parameters 3 | 3: same as 2, but fewer axi --> S_AXI_HP0_FIFO_CTRL, DMA0_REQ, S_AXI_ACP, S_AXI_GP0, S_AXI_HP0, DMA0_ACK, M_AXI_GP0 NOT related to regmap 4 | 4: same as 2, but fewer PL clocks --> FCLK_CLK0-4: 0xF8000170/180/190/1A0, 0x03F03F30U, ~~0x00400500U~~ (divisors, srcsel) 5 | 5: same as 2, but changed DDR DQS to clk delay 6 | bankvolt: bank voltage information not *that* visible 7 | f800012c: clock enable, can just enable all? 8 | -------------------------------------------------------------------------------- /xsct_tools/run_elf.tcl: -------------------------------------------------------------------------------- 1 | #!xsct 2 | connect -url tcp:127.0.0.1:3121 3 | source /home/petergu/ecptrap/zynq-muzy4-ps/zynq-muzy-ps.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl 4 | source ../ps7_init_test/ps7_init.tcl 5 | #rst -system 6 | #after 3000 7 | fpga -file /home/petergu/ecptrap/zynq-muzy4-ps/zynq-muzy-ps.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.bit 8 | configparams force-mem-access 1 9 | targets -set -nocase -filter {name =~"APU*"} -index 0 10 | stop 11 | ps7_init 12 | ps7_post_config 13 | targets -set -nocase -filter {name =~ "ARM*#0"} -index 0 14 | rst -processor 15 | #dow /home/petergu/PTP/zynq-openxc7/embeddedsw/lib/sw_apps/hello_world/src/hello-world.elf 16 | dow /home/petergu/PTP/zynq-openxc7/embeddedsw/lib/sw_apps/zynq_fsbl/src/fsbl.elf 17 | configparams force-mem-access 0 18 | con 19 | -------------------------------------------------------------------------------- /xsct_tools/run_elf_7030.tcl: -------------------------------------------------------------------------------- 1 | #!xsct 2 | puts "$argc $argv" 3 | connect -url tcp:127.0.0.1:3121 4 | if {$argc > 0} { 5 | source [lindex $argv 0] 6 | } else { 7 | source ../ps7_init_fclk/ps7_init.tcl 8 | } 9 | # We program bitstream by hand 10 | if {$argc > 1} { 11 | if {[lindex $argv 1] != "x"} 12 | rst -system 13 | after 3000 14 | fpga -file [lindex $argv 1] 15 | } 16 | configparams force-mem-access 1 17 | targets -set -nocase -filter {name =~"APU*"} -index 0 18 | stop 19 | # The config is for generic Zynq7000, and even works on a 7030! 20 | ps7_init 21 | ps7_post_config 22 | targets -set -nocase -filter {name =~ "ARM*#0"} -index 0 23 | rst -processor 24 | if {$argc > 2} { 25 | dow [lindex $argv 2] 26 | } 27 | # The PS really has no peripherals... 28 | #dow /home/petergu/PTP/zynq-openxc7/embeddedsw/lib/sw_apps/hello_world/src/hello-world.elf 29 | #dow /home/petergu/PTP/zynq-openxc7/embeddedsw/lib/sw_apps/zynq_fsbl/src/fsbl.elf 30 | configparams force-mem-access 0 31 | con 32 | -------------------------------------------------------------------------------- /zynq7000_user.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from zynq7000 import * 3 | 4 | # Set tab to 4 spaces to view correctly! 5 | _=0 6 | z7000_ps_param_muzy4 = { 7 | # L0 L1 L2_01 L2_10 L2_11 L3_000 L3_001 L3_010 L3_011 L3_100 L3_101 L3_110 L3_111 8 | 'MIO_PIN_00': [ _*'qspi1 ss_b', x, _*'sram/nor cs0', _*'nand cs0', _*'sd0 power', _*'gpio', x, x, x, x, x, x, ''], 9 | 'MIO_PIN_01': [ _*'qspi0 ss_b', x, _*'sram addr25', _*'sram/nor cs1', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 10 | 'MIO_PIN_02': [ _*'qspi0 io0', _*'trace data8', x, _*'nand alen', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 11 | 'MIO_PIN_03': [ _*'qspi0 io1', _*'trace data9', _*'sram/nor data0', _*'nand we_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 12 | 'MIO_PIN_04': [ _*'qspi0 io2', _*'trace data10', _*'sram/nor data1', _*'nand data2', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 13 | 'MIO_PIN_05': [ _*'qspi0 io3', _*'trace data11', _*'sram/nor data2', _*'nand data0', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 14 | 'MIO_PIN_06': [ _*'qspi0 sclk', _*'trace data12', _*'sram/nor data3', _*'nand data1', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 15 | 'MIO_PIN_07': [ x, _*'trace data13', _*'sram/nor oe_b', _*'nand cle_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 16 | 'MIO_PIN_08': [ _*'qspi fbclk', _*'trace data14', x, _*'nand rd_b', _*'sd0 power', _*'gpio', _*'can1 tx', _*'sram/nor bls_b', x, x, x, x, _*'uart1 txd'], 17 | 'MIO_PIN_09': [ _*'qspi1 sclk', _*'trace data15', _*'sram/nor data6', _*'nand data4', _*'sd1 power', _*'gpio', _*'can1 rx', x, x, x, x, x, _*'uart1 rxd'], 18 | 'MIO_PIN_10': [ _*'qspi1 io0', _*'trace data2', _*'sram/nor data7', _*'nand data5', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, 1*'uart0 rxd'], 19 | 'MIO_PIN_11': [ _*'qspi1 io1', _*'trace data3', _*'sram/nor data4', _*'nand data6', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, 1*'uart0 txd'], 20 | 'MIO_PIN_12': [ _*'qspi1 io2', _*'trace clk', x, _*'nand data7', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 21 | 'MIO_PIN_13': [ _*'qspi1 io3', _*'trace ctrl', x, _*'nand data3', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 22 | 'MIO_PIN_14': [ x, _*'trace data0', x, _*'nand busy', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 23 | 'MIO_PIN_15': [ x, _*'trace data1', _*'sram/nor addr0', x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 24 | 'MIO_PIN_16': [ _*'gem0 tx_clk',_*'trace data4', _*'sram/nor addr1', _*'nand data8', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', 0*'ttc1 wave', _*'uart1 txd'], 25 | 'MIO_PIN_17': [ _*'gem0 txd0', _*'trace data5', _*'sram/nor addr2', _*'nand data9', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 cmd', _*'spi0 miso', 0*'ttc1 clk', _*'uart1 rxd'], 26 | 'MIO_PIN_18': [ _*'gem0 txd1', _*'trace data6', _*'sram/nor addr3', _*'nand data10', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', 0*'ttc0 wave', _*'uart0 rxd'], 27 | 'MIO_PIN_19': [ _*'gem0 txd2', _*'trace data7', _*'sram/nor addr4', _*'nand data11', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', 0*'ttc0 clk', _*'uart0 txd'], 28 | 'MIO_PIN_20': [ _*'gem0 txd3', x, _*'sram/nor addr5', _*'nand data12', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 29 | 'MIO_PIN_21': [ _*'gem0 tx_ctl',x, _*'sram/nor addr6', _*'nand data13', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 30 | 'MIO_PIN_22': [ _*'gem0 rx_clk',_*'trace data2', _*'sram/nor addr7', _*'nand data14', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 31 | 'MIO_PIN_23': [ _*'gem0 rxd0', _*'trace data3', _*'sram/nor addr8', _*'nand data15', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 32 | 'MIO_PIN_24': [ _*'gem0 rxd1', _*'trace clk', _*'sram/nor addr9', x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 33 | 'MIO_PIN_25': [ _*'gem0 rxd2', _*'trace ctrl', _*'sram/nor addr10',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 34 | 'MIO_PIN_26': [ _*'gem0 rxd3', _*'trace data0', _*'sram/nor addr11',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 35 | 'MIO_PIN_27': [ _*'gem0 rx_clk',_*'trace data1', _*'sram/nor addr12',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 36 | 'MIO_PIN_28': [ _*'gem1 tx_clk',_*'usb0 data4', _*'sram/nor addr13',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 37 | 'MIO_PIN_29': [ _*'gem1 txd0', _*'usb0 dir', _*'sram/nor addr14',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 38 | 'MIO_PIN_30': [ _*'gem1 txd1', _*'usb0 stp', _*'sram/nor addr15',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 39 | 'MIO_PIN_31': [ _*'gem1 txd2', _*'usb0 nxt', _*'sram/nor addr16',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 40 | 'MIO_PIN_32': [ _*'gem1 txd3', _*'usb0 data0', _*'sram/nor addr17',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 41 | 'MIO_PIN_33': [ _*'gem1 tx_ctl',_*'usb0 data1', _*'sram/nor addr18',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 42 | 'MIO_PIN_34': [ _*'gem1 rx_clk',_*'usb0 data2', _*'sram/nor addr19',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 43 | 'MIO_PIN_35': [ _*'gem1 rxd0', _*'usb0 data3', _*'sram/nor addr20',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 44 | 'MIO_PIN_36': [ _*'gem1 rxd1', _*'usb0 clk', _*'sram/nor addr21',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 45 | 'MIO_PIN_37': [ _*'gem1 rxd2', _*'usb0 data5', _*'sram/nor addr22',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 46 | 'MIO_PIN_38': [ _*'gem1 rxd3', _*'usb0 data6', _*'sram/nor addr23',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 47 | 'MIO_PIN_39': [ _*'gem1 rx_ctl',_*'usb0 data7', _*'sram/nor addr24',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 48 | 'MIO_PIN_40': [ x, _*'usb1 data4', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 49 | 'MIO_PIN_41': [ x, _*'usb1 dir', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 50 | 'MIO_PIN_42': [ x, _*'usb1 stp', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, 1*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 51 | 'MIO_PIN_43': [ x, _*'usb1 nxt', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, 1*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 52 | 'MIO_PIN_44': [ x, _*'usb1 data0', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 53 | 'MIO_PIN_45': [ x, _*'usb1 data1', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 54 | 'MIO_PIN_46': [ x, _*'usb1 data2', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 55 | 'MIO_PIN_47': [ x, _*'usb1 data3', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 56 | 'MIO_PIN_48': [ x, _*'usb1 clk', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 57 | 'MIO_PIN_49': [ x, _*'usb1 data5', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 58 | 'MIO_PIN_50': [ x, _*'usb1 data6', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 59 | 'MIO_PIN_51': [ x, _*'usb1 data7', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 60 | 'MIO_PIN_52': [ x, x, x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'swdt clk', _*'mdio0 clk', _*'mdio1 clk', x, _*'uart1 txd'], 61 | 'MIO_PIN_53': [ x, x, x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'swdt rst', _*'mdio0 data', _*'mdio1 data', x, _*'uart1 rxd'], 62 | 'uart0' : { }, 63 | 'uart1' : { 'baud': 9600 }, # we have to explicitly specify in case of EMIO 64 | # 'sd0' : {}, # no need to enable again, it's already in the table 65 | 'freq' : { 'crystal' : 33.333333333, 66 | 'fclk0' : 100, 67 | 'fclk1' : 50, 68 | 'fclk2' : 25 69 | # 'uart' : 100 # can customize peripheral freq, but not recommended 70 | } 71 | } 72 | 73 | z7000_ps_param_pynqz1 = { 74 | # L0 L1 L2_01 L2_10 L2_11 L3_000 L3_001 L3_010 L3_011 L3_100 L3_101 L3_110 L3_111 75 | 'MIO_PIN_00': [ _*'qspi1 ss_b', x, _*'sram/nor cs0', _*'nand cs0', _*'sd0 power', _*'gpio', x, x, x, x, x, x, ''], 76 | 'MIO_PIN_01': [ _*'qspi0 ss_b', x, _*'sram addr25', _*'sram/nor cs1', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 77 | 'MIO_PIN_02': [ _*'qspi0 io0', _*'trace data8', x, _*'nand alen', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 78 | 'MIO_PIN_03': [ _*'qspi0 io1', _*'trace data9', _*'sram/nor data0', _*'nand we_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 79 | 'MIO_PIN_04': [ _*'qspi0 io2', _*'trace data10', _*'sram/nor data1', _*'nand data2', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 80 | 'MIO_PIN_05': [ _*'qspi0 io3', _*'trace data11', _*'sram/nor data2', _*'nand data0', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 81 | 'MIO_PIN_06': [ _*'qspi0 sclk', _*'trace data12', _*'sram/nor data3', _*'nand data1', _*'sd0 power', _*'gpio', x, x, x, x, x, x, x], 82 | 'MIO_PIN_07': [ x, _*'trace data13', _*'sram/nor oe_b', _*'nand cle_b', _*'sd1 power', _*'gpio', x, x, x, x, x, x, x], 83 | 'MIO_PIN_08': [ _*'qspi fbclk', _*'trace data14', x, _*'nand rd_b', _*'sd0 power', _*'gpio', _*'can1 tx', _*'sram/nor bls_b', x, x, x, x, _*'uart1 txd'], 84 | 'MIO_PIN_09': [ _*'qspi1 sclk', _*'trace data15', _*'sram/nor data6', _*'nand data4', _*'sd1 power', _*'gpio', _*'can1 rx', x, x, x, x, x, _*'uart1 rxd'], 85 | 'MIO_PIN_10': [ _*'qspi1 io0', _*'trace data2', _*'sram/nor data7', _*'nand data5', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 86 | 'MIO_PIN_11': [ _*'qspi1 io1', _*'trace data3', _*'sram/nor data4', _*'nand data6', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 87 | 'MIO_PIN_12': [ _*'qspi1 io2', _*'trace clk', x, _*'nand data7', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 88 | 'MIO_PIN_13': [ _*'qspi1 io3', _*'trace ctrl', x, _*'nand data3', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 89 | 'MIO_PIN_14': [ x, _*'trace data0', x, _*'nand busy', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, 1*'uart0 rxd'], 90 | 'MIO_PIN_15': [ x, _*'trace data1', _*'sram/nor addr0', x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, 1*'uart0 txd'], 91 | 'MIO_PIN_16': [ _*'gem0 tx_clk',_*'trace data4', _*'sram/nor addr1', _*'nand data8', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', 0*'ttc1 wave', _*'uart1 txd'], 92 | 'MIO_PIN_17': [ _*'gem0 txd0', _*'trace data5', _*'sram/nor addr2', _*'nand data9', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 cmd', _*'spi0 miso', 0*'ttc1 clk', _*'uart1 rxd'], 93 | 'MIO_PIN_18': [ _*'gem0 txd1', _*'trace data6', _*'sram/nor addr3', _*'nand data10', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', 0*'ttc0 wave', _*'uart0 rxd'], 94 | 'MIO_PIN_19': [ _*'gem0 txd2', _*'trace data7', _*'sram/nor addr4', _*'nand data11', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', 0*'ttc0 clk', _*'uart0 txd'], 95 | 'MIO_PIN_20': [ _*'gem0 txd3', x, _*'sram/nor addr5', _*'nand data12', _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 96 | 'MIO_PIN_21': [ _*'gem0 tx_ctl',x, _*'sram/nor addr6', _*'nand data13', _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 97 | 'MIO_PIN_22': [ _*'gem0 rx_clk',_*'trace data2', _*'sram/nor addr7', _*'nand data14', _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 98 | 'MIO_PIN_23': [ _*'gem0 rxd0', _*'trace data3', _*'sram/nor addr8', _*'nand data15', _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 99 | 'MIO_PIN_24': [ _*'gem0 rxd1', _*'trace clk', _*'sram/nor addr9', x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 100 | 'MIO_PIN_25': [ _*'gem0 rxd2', _*'trace ctrl', _*'sram/nor addr10',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 101 | 'MIO_PIN_26': [ _*'gem0 rxd3', _*'trace data0', _*'sram/nor addr11',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 102 | 'MIO_PIN_27': [ _*'gem0 rx_clk',_*'trace data1', _*'sram/nor addr12',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 103 | 'MIO_PIN_28': [ _*'gem1 tx_clk',_*'usb0 data4', _*'sram/nor addr13',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 104 | 'MIO_PIN_29': [ _*'gem1 txd0', _*'usb0 dir', _*'sram/nor addr14',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 105 | 'MIO_PIN_30': [ _*'gem1 txd1', _*'usb0 stp', _*'sram/nor addr15',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, _*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 106 | 'MIO_PIN_31': [ _*'gem1 txd2', _*'usb0 nxt', _*'sram/nor addr16',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, _*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 107 | 'MIO_PIN_32': [ _*'gem1 txd3', _*'usb0 data0', _*'sram/nor addr17',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, _*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 108 | 'MIO_PIN_33': [ _*'gem1 tx_ctl',_*'usb0 data1', _*'sram/nor addr18',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, _*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 109 | 'MIO_PIN_34': [ _*'gem1 rx_clk',_*'usb0 data2', _*'sram/nor addr19',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 110 | 'MIO_PIN_35': [ _*'gem1 rxd0', _*'usb0 data3', _*'sram/nor addr20',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 111 | 'MIO_PIN_36': [ _*'gem1 rxd1', _*'usb0 clk', _*'sram/nor addr21',x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 112 | 'MIO_PIN_37': [ _*'gem1 rxd2', _*'usb0 data5', _*'sram/nor addr22',x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 113 | 'MIO_PIN_38': [ _*'gem1 rxd3', _*'usb0 data6', _*'sram/nor addr23',x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 114 | 'MIO_PIN_39': [ _*'gem1 rx_ctl',_*'usb0 data7', _*'sram/nor addr24',x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 115 | 'MIO_PIN_40': [ x, _*'usb1 data4', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 sck', _*'spi0 sck', _*'ttc1 wave', _*'uart1 txd'], 116 | 'MIO_PIN_41': [ x, _*'usb1 dir', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 miso', _*'spi0 miso', _*'ttc1 clk', _*'uart1 rxd'], 117 | 'MIO_PIN_42': [ x, _*'usb1 stp', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', x, 1*'sd0 data0', _*'spi0 ss0', _*'ttc0 wave', _*'uart0 rxd'], 118 | 'MIO_PIN_43': [ x, _*'usb1 nxt', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', x, 1*'sd0 data1', _*'spi0 ss1', _*'ttc0 clk', _*'uart0 txd'], 119 | 'MIO_PIN_44': [ x, _*'usb1 data0', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', x, 1*'sd0 data2', _*'spi0 ss2', x, _*'uart1 txd'], 120 | 'MIO_PIN_45': [ x, _*'usb1 data1', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', x, 1*'sd0 data3', _*'spi0 mosi', x, _*'uart1 rxd'], 121 | 'MIO_PIN_46': [ x, _*'usb1 data2', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'pjtag tdi', _*'sd1 data0', _*'spi1 mosi', x, _*'uart0 rxd'], 122 | 'MIO_PIN_47': [ x, _*'usb1 data3', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'pjtag tdo', _*'sd1 cmd', _*'spi1 miso', x, _*'uart0 txd'], 123 | 'MIO_PIN_48': [ x, _*'usb1 clk', x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'pjtag tck', _*'sd1 sck', _*'spi1 sck', x, _*'uart1 txd'], 124 | 'MIO_PIN_49': [ x, _*'usb1 data5', x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'pjtag tms', _*'sd1 data1', _*'spi1 ss0', x, _*'uart1 rxd'], 125 | 'MIO_PIN_50': [ x, _*'usb1 data6', x, x, _*'sd0 power', _*'gpio', _*'can0 rx', _*'i2c0 scl', _*'swdt clk', _*'sd1 data2', _*'spi1 ss1', x, _*'uart0 rxd'], 126 | 'MIO_PIN_51': [ x, _*'usb1 data7', x, x, _*'sd1 power', _*'gpio', _*'can0 tx', _*'i2c0 sda', _*'swdt rst', _*'sd1 data3', _*'spi1 ss2', x, _*'uart0 txd'], 127 | 'MIO_PIN_52': [ x, x, x, x, _*'sd0 power', _*'gpio', _*'can1 tx', _*'i2c1 scl', _*'swdt clk', _*'mdio0 clk', _*'mdio1 clk', x, _*'uart1 txd'], 128 | 'MIO_PIN_53': [ x, x, x, x, _*'sd1 power', _*'gpio', _*'can1 rx', _*'i2c1 sda', _*'swdt rst', _*'mdio0 data', _*'mdio1 data', x, _*'uart1 rxd'], 129 | 'freq' : { 'crystal' : 33.333333333, 130 | 'fclk0' : 10, 131 | 'fclk1' : 50, 132 | 'fclk2' : 25, 133 | 'fclk3' : 12.5, 134 | } 135 | } 136 | 137 | z7000_ps_param_fclk_on = {'freq' : {'crystal' : 40, 138 | 'fclk0' : 10}} 139 | 140 | if __name__ == '__main__': 141 | # Load register fields from fuzzed TCLs 142 | for sample in ['noddr-0-uart', 'noddr-0-sd', 'noddr-0-uart-elsegpio']: 143 | parse_ps7_init_entries_fields("./tcl_fuzz/hdf/" + sample + "/ps7_init_gpl.c") 144 | # zynq7_allregisters.show() 145 | 146 | # Instantiate a PS7 147 | z7 = Zynq7000() 148 | # Load the peripheral configuration, this is necessary 149 | z7.param_load(z7000_ps_param_muzy4) 150 | # Generate all ps7_init parameters, 151 | # user will have chance to inspect/modify before writing to file 152 | z7.ps7_init_gen(zynq7_allregisters) # zynq7_allregisters is global 153 | # Write the parameters to a directory, ready to be used on fsbl, etc 154 | z7.ps7_init_filewrite('./ps7_init_muzy4/') 155 | 156 | z7 = Zynq7000() 157 | z7.param_load(z7000_ps_param_pynqz1) 158 | z7.ps7_init_gen(zynq7_allregisters) 159 | z7.ps7_init_filewrite('./ps7_init_pynqz1/') 160 | 161 | z7 = Zynq7000() 162 | z7.param_load(z7000_ps_param_fclk_on) 163 | z7.ps7_init_gen(zynq7_allregisters) 164 | z7.ps7_init_filewrite('./ps7_init_fclk/') 165 | 166 | # Can freely change internal params 167 | z7.param['freq']['fclk0'] = 250 168 | # Re-calculate params 169 | z7.param_calc() 170 | z7.ps7_init_gen(zynq7_allregisters) 171 | z7.ps7_init_filewrite('./ps7_init_fclk_250/') 172 | 173 | # Overclock the fclk 174 | z7.param['freq']['fclk0'] = 620 175 | # Re-calculate params 176 | z7.param_calc() 177 | z7.ps7_init_gen(zynq7_allregisters) 178 | z7.ps7_init_filewrite('./ps7_init_fclk_oc/') 179 | 180 | --------------------------------------------------------------------------------