├── .gitignore ├── DOC ├── IMG │ ├── CM5.jpg │ ├── PPS.jpg │ ├── RPI5.jpg │ ├── RPI5_PHC2SYS.png │ └── TIMECARD.jpg ├── OCP-TAP │ ├── TimeCard_VerificationProcedure_8-24-2023.docx │ ├── TimecardProgrammingProcedure_8-1-2023.pptx │ └── U-Blox_Programming_TimeCardV9.docx └── Setup-and-Usage.md ├── DRV ├── .gitignore ├── Kconfig ├── Makefile ├── README.md ├── ocp-tap-bar-mem.c ├── ptp_ocp.c └── remake ├── FPGA ├── IPs_3rdParty │ ├── Axi16550 │ │ ├── axi_uart16550.v │ │ ├── axil2mm.v │ │ └── uart16550.v │ ├── AxiGpio │ │ └── axil_gpio.v │ ├── AxiLiteXbar │ │ ├── addrdecode.v │ │ ├── afifo.v │ │ ├── axi2axilite.v │ │ ├── axi2axilsub.v │ │ ├── axi_addr.v │ │ ├── axi_bd_module_gen.py │ │ ├── axilxbar.v │ │ ├── axixclk.v │ │ ├── axixclk_al2al.v │ │ ├── sfifo.v │ │ ├── skidbuffer.v │ │ ├── xbar_2_2.v │ │ ├── xbar_ptp_1_23.v │ │ └── xbar_sys_1_15.v │ ├── PSReset │ │ └── reset_counter.v │ ├── Pcie_7x │ │ ├── axil_to_al.v │ │ ├── axis_pcie_to_al_us.v │ │ ├── pcie_7x.v │ │ ├── pcie_7x_aximm_msi_bd.v │ │ ├── pcie_axi_rx.v │ │ ├── pcie_axi_tx.v │ │ ├── pcie_block.v │ │ ├── pcie_brams.v │ │ ├── pcie_tx_thrtl_ctl.v │ │ ├── pipe_wrapper.v │ │ └── xilinx_pcie_mmcm.v │ └── Xc7Mmcm │ │ ├── mmcm_10_to_200.v │ │ ├── mmcm_200_to_50_200.v │ │ └── mmcm_200_to_50_200_25_50.v ├── IPs_TC │ ├── AdjustableClock │ │ ├── Additional Files │ │ │ ├── Adjustable Clock IP.png │ │ │ ├── Adjustable Clock configuration.png │ │ │ ├── AdjustableClockRegset.xlsx │ │ │ ├── Regset.png │ │ │ ├── Regset10_OffsetIntrv.png │ │ │ ├── Regset11_DriftVal.png │ │ │ ├── Regset12_DriftIntrv.png │ │ │ ├── Regset13_InSyncThresh.png │ │ │ ├── Regset14_OffsetServoI.png │ │ │ ├── Regset15_OffsetServoP.png │ │ │ ├── Regset16_DriftServoP.png │ │ │ ├── Regset17_DriftServoI.png │ │ │ ├── Regset18_ClkOffset.png │ │ │ ├── Regset19_ClkDrift.png │ │ │ ├── Regset1_Control.png │ │ │ ├── Regset2_Status.png │ │ │ ├── Regset3_Select.png │ │ │ ├── Regset4_Version.png │ │ │ ├── Regset5_TimeL.png │ │ │ ├── Regset6_TimeH.png │ │ │ ├── Regset7_AdjL.png │ │ │ ├── Regset8_AdjH.png │ │ │ └── Regset9_OffsetValue.png │ │ ├── AdjustableClock.sv │ │ ├── AdjustableClock_v.v │ │ └── Readme.md │ ├── BufgMux_IPI.v │ ├── ClockDetector │ │ ├── Additional Files │ │ │ ├── ClockDetectorConfig.png │ │ │ ├── ClockDetectorIP.png │ │ │ ├── ClockDetector_Regset.xlsx │ │ │ ├── Regset1_SourceSelected.png │ │ │ ├── Regset2_SourceSelect.png │ │ │ ├── Regset3_Version.png │ │ │ └── Regset_Overview.png │ │ ├── ClockDetector.sv │ │ ├── ClockDetector_v.v │ │ └── Readme.md │ ├── CommunicationSelector │ │ ├── Additional Files │ │ │ ├── Communication Mux.vsdx │ │ │ ├── CommunicationMux.png │ │ │ └── CommunicationSelectorIP.png │ │ ├── CommunicationSelector.v │ │ └── Readme.md │ ├── ConfMaster │ │ ├── Additional Files │ │ │ ├── ConfMasterConfiguration.png │ │ │ ├── ConfMasterIP.png │ │ │ └── ConfigurationTemplate.txt │ │ ├── ConfMaster.sv │ │ ├── ConfMaster_v.v │ │ └── Readme.md │ ├── CoreList │ │ ├── Additional Files │ │ │ ├── Core List Customization options.png │ │ │ ├── CoreList IP.png │ │ │ ├── CoreListRegset.xlsx │ │ │ ├── CoreListRegsetOverview.png │ │ │ ├── CoreListTemplate.txt │ │ │ ├── Regset1.TypeNr.png │ │ │ ├── Regset2.InstanceNr.png │ │ │ ├── Regset3.VersionNr.png │ │ │ ├── Regset4.AddressLow.png │ │ │ ├── Regset5.AddressHigh.png │ │ │ ├── Regset6.Interrupt.png │ │ │ ├── Regset7.Sensitivity.png │ │ │ ├── Regset8_Word1.png │ │ │ ├── Regset8_Word2.png │ │ │ ├── Regset8_Word3.png │ │ │ ├── Regset8_Word4.png │ │ │ ├── Regset8_Word5.png │ │ │ ├── Regset8_Word6.png │ │ │ ├── Regset8_Word7.png │ │ │ ├── Regset8_Word8.png │ │ │ └── Regset8_Word9.png │ │ ├── CoreList.sv │ │ ├── CoreList_v.v │ │ └── Readme.md │ ├── DummyAxiSlave │ │ ├── Additional Files │ │ │ ├── DummyAxiSlave Customization options.png │ │ │ └── DummyAxiSlave IP.png │ │ ├── DummyAxiSlave.sv │ │ ├── DummyAxiSlave_v.v │ │ └── Readme.md │ ├── FpgaVersion │ │ ├── Additional Files │ │ │ ├── FpgaVersion_Config.png │ │ │ ├── FpgaVersion_IP.png │ │ │ ├── FpgaVersion_Regset.xlsx │ │ │ └── FpgaVersion_regset.png │ │ ├── FpgaVersion.sv │ │ ├── FpgaVersion_v.v │ │ └── Readme.md │ ├── FrequencyCounter │ │ ├── Additional Files │ │ │ ├── FrequencyCounterConfig.PNG │ │ │ ├── FrequencyCounterIP.PNG │ │ │ ├── FrequencyCounter_Regset.xlsx │ │ │ ├── Regset1_Control.png │ │ │ ├── Regset2_Frequency.png │ │ │ ├── Regset3_Polarity.png │ │ │ ├── Regset4_Version.png │ │ │ └── RegsetOverview.png │ │ ├── FrequencyCounter.sv │ │ ├── FrequencyCounter_v.v │ │ └── Readme.md │ ├── MsiIrq │ │ ├── Additional Files │ │ │ ├── MsiIrqConfig.PNG │ │ │ └── MsiIrqIP.PNG │ │ ├── MsiIrq.v │ │ └── Readme.md │ ├── PpsGenerator │ │ ├── Additional Files │ │ │ ├── PpsGenGui.png │ │ │ ├── PpsGenIp.png │ │ │ ├── Pps_Generator_Regset.xlsx │ │ │ ├── Regset1_Control.png │ │ │ ├── Regset2_Status.png │ │ │ ├── Regset3_Polarity.png │ │ │ ├── Regset4_Version.png │ │ │ ├── Regset5_Width.png │ │ │ ├── Regset6_Cable.png │ │ │ └── RegsetOverview.png │ │ ├── PpsGenerator.sv │ │ ├── PpsGenerator_v.v │ │ └── Readme.md │ ├── PpsSlave │ │ ├── Additional Files │ │ │ ├── PiServo.png │ │ │ ├── PpsSlave_Config.png │ │ │ ├── PpsSlave_IP.png │ │ │ ├── PpsSlave_Regset.png │ │ │ ├── PpsSlave_Regset.xlsx │ │ │ ├── Reg1_Control.png │ │ │ ├── Reg2_Status.png │ │ │ ├── Reg3_Polarity.png │ │ │ ├── Reg4_Version.png │ │ │ ├── Reg5_PulseWidth.png │ │ │ └── Reg6_CableDelay.png │ │ ├── PpsSlave.sv │ │ ├── PpsSlave_v.v │ │ └── Readme.md │ ├── PpsSourceSelector │ │ ├── Additional Files │ │ │ ├── PpsSourceSelectorIP.png │ │ │ └── PpsSourceSelector_Conf.png │ │ ├── PpsSourceSelector.v │ │ └── Readme.md │ ├── Readme.md │ ├── SignalGenerator │ │ ├── Additional Files │ │ │ ├── Regset10_PulseL.png │ │ │ ├── Regset11_PulseH.png │ │ │ ├── Regset12_PeriodL.png │ │ │ ├── Regset13_PeriodH.png │ │ │ ├── Regset14_Repeat.png │ │ │ ├── Regset1_Control.png │ │ │ ├── Regset2_Status.png │ │ │ ├── Regset3_Polarity.png │ │ │ ├── Regset4_Version.png │ │ │ ├── Regset5_Cable.png │ │ │ ├── Regset6_Irq.png │ │ │ ├── Regset7_Msk.png │ │ │ ├── Regset8_StartL.png │ │ │ ├── Regset9_StartH.png │ │ │ ├── RegsetOverview.png │ │ │ ├── SigGeneratorConfiguration.png │ │ │ ├── SigGeneratorIP.png │ │ │ └── SignalGenerator_Regset.xlsx │ │ ├── Readme.md │ │ ├── SignalGenerator.sv │ │ └── SignalGenerator_v.v │ ├── SignalTimestamper │ │ ├── Additional Files │ │ │ ├── Regset10_TsL.png │ │ │ ├── Regset11_TsH.png │ │ │ ├── Regset12_DataWdth.png │ │ │ ├── Regset13_Data.png │ │ │ ├── Regset1_Control.png │ │ │ ├── Regset2_Status.png │ │ │ ├── Regset3_Polarity.png │ │ │ ├── Regset4_Version.png │ │ │ ├── Regset5_Cable.png │ │ │ ├── Regset6_Irq.png │ │ │ ├── Regset7_Msk.png │ │ │ ├── Regset8_EvtCnt.png │ │ │ ├── Regset9_TsCnt.png │ │ │ ├── RegsetOverview.png │ │ │ ├── SigTimestamper Configuration.png │ │ │ ├── SigTimestamper IP.png │ │ │ └── SignalTimestamper_Regset.xlsx │ │ ├── Readme.md │ │ ├── SignalTimestamper.sv │ │ └── SignalTimestamper_v.v │ ├── SmaSelector │ │ ├── Additional Files │ │ │ ├── Regset1_1_InputSel.png │ │ │ ├── Regset1_2_OutputSel.png │ │ │ ├── Regset1_3_Version.png │ │ │ ├── Regset1_4_InputStatus.png │ │ │ ├── Regset1_Overview.png │ │ │ ├── Regset2_1_InputSel.png │ │ │ ├── Regset2_2_OutputSel.png │ │ │ ├── Regset2_3_Version.png │ │ │ ├── Regset2_Overview.png │ │ │ ├── SmaSelectorConfig.png │ │ │ ├── SmaSelectorIP.png │ │ │ └── SmaSelector_Regset.xlsx │ │ ├── Readme.md │ │ ├── SmaSelector.sv │ │ └── SmaSelector_v.v │ ├── TC_ClockAdjustment.xml │ ├── TC_ClockAdjustment_rtl.xml │ ├── TC_Servo.xml │ ├── TC_Servo_rtl.xml │ ├── TC_Time.xml │ ├── TC_Time_rtl.xml │ ├── TimeCard_Package.svh │ └── TodSlave │ │ ├── Additional Files │ │ ├── Reg10_SatelliteNumber.png │ │ ├── Reg1_Control.png │ │ ├── Reg2_Status.png │ │ ├── Reg3_Polarity.png │ │ ├── Reg4_Version.png │ │ ├── Reg5_Correction.png │ │ ├── Reg6_Baudrate.png │ │ ├── Reg7_UtcStatus.png │ │ ├── Reg8_TimeToLeap.png │ │ ├── Reg9_AntennaStatus.png │ │ ├── TodSlave_Config.png │ │ ├── TodSlave_IP.png │ │ ├── TodSlave_Regset.png │ │ └── TodSlave_Regset.xlsx │ │ ├── Readme.md │ │ ├── TodSlave.sv │ │ └── TodSlave_v.v ├── LICENSE.md └── Targets │ ├── TimeCard_NoVendIPs │ ├── ChangeLog.txt │ ├── Constraints │ │ └── PinoutConstraint.xdc │ ├── CoreListFile.dat │ ├── CoreListFile.txt │ ├── DefaultConfigFile.dat │ ├── DefaultConfigFile.txt │ ├── Prebuilt │ │ └── TimeCardTop.bit │ ├── Readme.md │ ├── TimeCard_NoVendIPs.tcl │ ├── Top │ │ ├── TimeCardNoBd.v │ │ └── TimeCardTop.v │ ├── configfile_convert.py │ └── corelist_convert.py │ └── TimeCard_Verilog │ ├── Additional Files │ ├── AXI_GPIO_Ext.png │ ├── AXI_GPIO_GNSS_MAC.png │ ├── AXI_GPIO_Regset.xlsx │ ├── AddConfigConfirm.png │ ├── AddConfigMem.png │ ├── AllVerilog_Bd.png │ ├── ConfigMemProgram.png │ ├── Graphics.vsd │ ├── HwManager.png │ ├── HwManagerUpdated.png │ ├── SmaConnectors.png │ ├── TimeCardTop.png │ └── tft.exe │ ├── Bd │ └── TimeCardBd.tcl │ ├── Binaries │ ├── TimeCardTop.bin │ └── TimeCardTop.bit │ ├── ChangeLog.txt │ ├── Constraints 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