├── syn ├── platforms │ ├── atlys │ │ ├── platform.batch │ │ ├── platform.ut │ │ └── platform.ucf │ ├── nexys3 │ │ ├── platform.batch │ │ ├── platform.ut │ │ └── platform.ucf │ ├── nexys2-500 │ │ ├── platform.batch │ │ ├── platform.ut │ │ └── platform.ucf │ ├── s3board │ │ ├── platform.batch │ │ ├── platform.ut │ │ └── platform.ucf │ └── nexys2-1200 │ │ ├── platform.batch │ │ ├── platform.ut │ │ └── platform.ucf └── Makefile ├── note.rb ├── .gitignore ├── rtl ├── edge_detect.vhd ├── sinus.vhd ├── makefile ├── pwm.vhd ├── ddfs.vhd ├── squareWaveGenerator.vhd ├── square.vhd ├── midi.vhd ├── uart.vhd ├── channel.vhd ├── midi_tb.vhd └── synth_top.vhd └── layout └── synth_top_nexys3.ucf /syn/platforms/atlys/platform.batch: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file TopLevel.xsvf 3 | addDevice -p 1 -file TopLevel.bit 4 | program -p 1 5 | quit 6 | -------------------------------------------------------------------------------- /syn/platforms/nexys3/platform.batch: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file TopLevel.xsvf 3 | addDevice -p 1 -file TopLevel.bit 4 | program -p 1 5 | quit 6 | -------------------------------------------------------------------------------- /syn/platforms/nexys2-500/platform.batch: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file TopLevel.xsvf 3 | addDevice -p 1 -file TopLevel.bit 4 | addDevice -p 2 -file ${XILINX}/xcf/data/xcf04s.bsd 5 | program -p 1 6 | quit 7 | -------------------------------------------------------------------------------- /syn/platforms/s3board/platform.batch: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file TopLevel.xsvf 3 | addDevice -p 1 -file TopLevel.bit 4 | addDevice -p 2 -file ${XILINX}/xcf/data/xcf02s.bsd 5 | program -p 1 6 | quit 7 | -------------------------------------------------------------------------------- /syn/platforms/nexys2-1200/platform.batch: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file TopLevel.xsvf 3 | addDevice -p 1 -file TopLevel.bit 4 | addDevice -p 2 -file ${XILINX}/xcf/data/xcf04s.bsd 5 | program -p 1 6 | quit 7 | -------------------------------------------------------------------------------- /note.rb: -------------------------------------------------------------------------------- 1 | a = 440 2 | clock = 100 3 | clock = clock*1000000 4 | root = 2**(1.0/12.0) 5 | 6 | freq = Array.new 7 | 8 | (-5..5).each {|j|(-9..2).each {|i|freq.push a/2.0**(j*-1)*(root**i)}} 9 | 10 | (0..127).each {|i| 11 | print "x\"#{"%05x" % ((freq[i]/clock*2**30).to_i)}\", " 12 | #print (clock/freq[i].to_i) 13 | #print ',' 14 | #if (i+1)%12 == 0 15 | #print "\n" 16 | #end 17 | } 18 | 19 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | _ngo 3 | _xmsgs 4 | *.html 5 | *.bgn 6 | *.bit 7 | *.bld 8 | *.drc 9 | *.lso 10 | *.ncd 11 | *.ngc 12 | *.ngd 13 | *.ngr 14 | *.pad 15 | *.par 16 | *.pcf 17 | *.prj 18 | *.ptwx 19 | *.syr 20 | *.unroutes 21 | *.xpi 22 | *.xwbt 23 | *.map 24 | *.mrp 25 | *.ngm 26 | *.xrpt 27 | *.csv 28 | *.txt 29 | *.xml 30 | *.xst 31 | *.log 32 | xst 33 | xlnx_auto_0_xdb 34 | *.swp 35 | .svn 36 | *.swo 37 | *.cf 38 | *.vcd 39 | -------------------------------------------------------------------------------- /syn/platforms/atlys/platform.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Compress 5 | -g CRC:Enable 6 | -g ConfigRate:1 7 | -g ProgPin:PullUp 8 | -g DonePin:PullUp 9 | -g TckPin:PullUp 10 | -g TdiPin:PullUp 11 | -g TdoPin:PullUp 12 | -g TmsPin:PullUp 13 | -g UnusedPin:PullDown 14 | -g UserID:0xFFFFFFFF 15 | -g StartUpClk:CClk 16 | -g DONE_cycle:4 17 | -g GTS_cycle:5 18 | -g GWE_cycle:6 19 | -g LCK_cycle:NoWait 20 | -g Security:None 21 | -g DonePipe:No 22 | -g DriveDone:No 23 | -------------------------------------------------------------------------------- /syn/platforms/nexys3/platform.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Compress 5 | -g CRC:Enable 6 | -g ConfigRate:1 7 | -g ProgPin:PullUp 8 | -g DonePin:PullUp 9 | -g TckPin:PullUp 10 | -g TdiPin:PullUp 11 | -g TdoPin:PullUp 12 | -g TmsPin:PullUp 13 | -g UnusedPin:PullDown 14 | -g UserID:0xFFFFFFFF 15 | -g StartUpClk:CClk 16 | -g DONE_cycle:4 17 | -g GTS_cycle:5 18 | -g GWE_cycle:6 19 | -g LCK_cycle:NoWait 20 | -g Security:None 21 | -g DonePipe:No 22 | -g DriveDone:No 23 | -------------------------------------------------------------------------------- /syn/platforms/nexys2-1200/platform.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Compress 5 | -g CRC:Enable 6 | -g ConfigRate:1 7 | -g ProgPin:PullUp 8 | -g DonePin:PullUp 9 | -g TckPin:PullUp 10 | -g TdiPin:PullUp 11 | -g TdoPin:PullUp 12 | -g TmsPin:PullUp 13 | -g UnusedPin:PullDown 14 | -g UserID:0xFFFFFFFF 15 | -g DCMShutdown:Disable 16 | -g StartUpClk:CClk 17 | -g DONE_cycle:4 18 | -g GTS_cycle:5 19 | -g GWE_cycle:6 20 | -g LCK_cycle:NoWait 21 | -g Security:None 22 | -g DonePipe:No 23 | -g DriveDone:No 24 | -------------------------------------------------------------------------------- /syn/platforms/nexys2-500/platform.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Compress 5 | -g CRC:Enable 6 | -g ConfigRate:1 7 | -g ProgPin:PullUp 8 | -g DonePin:PullUp 9 | -g TckPin:PullUp 10 | -g TdiPin:PullUp 11 | -g TdoPin:PullUp 12 | -g TmsPin:PullUp 13 | -g UnusedPin:PullDown 14 | -g UserID:0xFFFFFFFF 15 | -g DCMShutdown:Disable 16 | -g StartUpClk:CClk 17 | -g DONE_cycle:4 18 | -g GTS_cycle:5 19 | -g GWE_cycle:6 20 | -g LCK_cycle:NoWait 21 | -g Security:None 22 | -g DonePipe:No 23 | -g DriveDone:No 24 | -------------------------------------------------------------------------------- /syn/platforms/s3board/platform.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g Compress 5 | -g CRC:Enable 6 | -g ConfigRate:6 7 | -g CclkPin:PullUp 8 | -g M0Pin:PullUp 9 | -g M1Pin:PullUp 10 | -g M2Pin:PullUp 11 | -g ProgPin:PullUp 12 | -g DonePin:PullUp 13 | -g HswapenPin:PullUp 14 | -g TckPin:PullUp 15 | -g TdiPin:PullUp 16 | -g TdoPin:PullUp 17 | -g TmsPin:PullUp 18 | -g UnusedPin:PullDown 19 | -g UserID:0xFFFFFFFF 20 | -g DCMShutdown:Disable 21 | -g DCIUpdateMode:AsRequired 22 | -g StartUpClk:CClk 23 | -g DONE_cycle:4 24 | -g GTS_cycle:5 25 | -g GWE_cycle:6 26 | -g LCK_cycle:NoWait 27 | -g Match_cycle:Auto 28 | -g Security:None 29 | -g DonePipe:No 30 | -g DriveDone:No 31 | -------------------------------------------------------------------------------- /rtl/edge_detect.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity edge_detect is 5 | port (async_sig : in std_logic; 6 | clk : in std_logic; 7 | --rise : out std_logic); 8 | fall : out std_logic); 9 | end; 10 | 11 | architecture RTL of edge_detect is 12 | begin 13 | process 14 | variable sr : std_logic_vector (3 downto 0) := "0000"; 15 | begin 16 | wait until rising_edge(clk); 17 | -- Flanken erkennen 18 | --rise <= not sr(3) and sr(2); 19 | fall <= not sr(2) and sr(3); 20 | -- Eingang in Schieberegister einlesen 21 | sr := sr(2 downto 0) & async_sig; 22 | end process; 23 | end architecture; 24 | 25 | -------------------------------------------------------------------------------- /rtl/sinus.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | library work; 6 | use work.all; 7 | 8 | entity SinusPWM is 9 | Port ( 10 | clk : in std_logic; 11 | pwmoutput : out std_logic; 12 | akku : in std_logic_vector(17 downto 0) 13 | ); 14 | end SinusPWM; 15 | 16 | architecture rtl of SinusPWM is 17 | 18 | signal sinusplusoffset : std_logic_vector(7 downto 0); 19 | signal sinus : std_logic_vector(7 downto 0); 20 | 21 | begin 22 | 23 | I_ddfs: entity work.ddfs port map(clk,akku,sinus); 24 | sinusplusoffset <= std_logic_vector(unsigned(sinus) +to_unsigned(128,8)); 25 | I_pwm: entity work.PWM port map(clk,sinusplusoffset,pwmoutput); 26 | 27 | end rtl; 28 | 29 | -------------------------------------------------------------------------------- /rtl/makefile: -------------------------------------------------------------------------------- 1 | # Makefile automatically generated by ghdl 2 | # Version: GHDL 0.29 (20100109) [Sokcho edition] - mcode code generator 3 | # Command used to generate this makefile: 4 | # ghdl --gen-makefile midi_tb 5 | 6 | GHDL=ghdl 7 | GHDLFLAGS= 8 | GHDLRUNFLAGS=--stop-time=3000000ns --vcd=midi.vcd 9 | 10 | # Default target : elaborate 11 | all : elab 12 | 13 | # Elaborate target. Almost useless 14 | elab : force 15 | $(GHDL) -c $(GHDLFLAGS) -e midi_tb 16 | 17 | # Run target 18 | run : force 19 | $(GHDL) -c $(GHDLFLAGS) -r midi_tb $(GHDLRUNFLAGS) 20 | 21 | # Targets to analyze libraries 22 | init: force 23 | # /usr/local/ghdl/translate/lib//v93/ieee/../../../../libraries/ieee/std_logic_1164.v93 24 | # /usr/local/ghdl/translate/lib//v93/ieee/../../../../libraries/ieee/std_logic_1164_body.v93 25 | $(GHDL) -a $(GHDLFLAGS) midi_tb.vhd 26 | # /usr/local/ghdl/translate/lib//v93/ieee/../../../../libraries/ieee/numeric_std.v93 27 | # /usr/local/ghdl/translate/lib//v93/ieee/../../../../libraries/ieee/numeric_std-body.v93 28 | $(GHDL) -a $(GHDLFLAGS) uart.vhd 29 | $(GHDL) -a $(GHDLFLAGS) edge_detect.vhd 30 | $(GHDL) -a $(GHDLFLAGS) midi.vhd 31 | 32 | force: 33 | -------------------------------------------------------------------------------- /rtl/pwm.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | library work; 5 | use work.all; 6 | 7 | entity pwm is 8 | Generic( 9 | width: natural := 8; -- Breite 10 | fclk : integer := 100000000; -- Taktfrequenz 11 | fpwm : integer := 100000 -- PWM-Frequenz; 12 | ); 13 | Port( 14 | clk : in std_logic; 15 | pwmvalue : in std_logic_vector (width-1 downto 0); 16 | pwmout : out std_logic 17 | ); 18 | end PWM; 19 | 20 | architecture rtl of pwm is 21 | signal cnt : integer range 0 to 2**width-2 := 0; 22 | signal pre : integer range 0 to fclk/(fpwm*(2**width-2)) := 0; begin 23 | -- Vorteiler teilt FPGA-Takt auf PWM-Frequenz*Zählschritte 24 | process begin 25 | wait until rising_edge(clk); 26 | if (pre= to_integer(unsigned(pwmvalue))) then 48 | pwmout <= '0'; 49 | else 50 | pwmout <= '1'; 51 | end if; 52 | end process; 53 | end rtl; 54 | 55 | -------------------------------------------------------------------------------- /rtl/ddfs.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity ddfs is 6 | Port( 7 | clk : in std_logic; 8 | Freq_Data : in std_logic_vector (17 downto 0); 9 | Dout : out std_logic_vector (7 downto 0) 10 | ); 11 | end ddfs; 12 | architecture rtl of ddfs is 13 | signal Result : signed (7 downto 0); 14 | signal Accum : unsigned (29 downto 0) := (others=>'0'); 15 | signal Address : integer range 0 to 63; 16 | signal RomAddr : integer range 0 to 63; 17 | signal Quadrant : std_logic; 18 | signal Sign : std_logic; 19 | type Rom64x8 is array (0 to 63) of signed (7 downto 0); 20 | constant Sinus_Rom : Rom64x8 := (x"00", x"03", x"06", x"09", x"0c", x"0f", x"12", x"15", x"18", x"1b", x"1e", x"21", x"24", x"27", x"2a", x"2d", x"30", x"33", x"36", x"39", x"3b", x"3e", x"41", x"43", x"46", x"49", x"4b", x"4e", x"50", x"52", x"55", x"57", x"59", x"5b", x"5e", x"60", x"62", x"64", x"66", x"67", x"69", x"6b", x"6c", x"6e", x"70", x"71", x"72", x"74", x"75", x"76", x"77", x"78", x"79", x"7a", x"7b", x"7b", x"7c", x"7d", x"7d", x"7e", x"7e", x"7e", x"7f", x"7f"); 21 | 22 | begin 23 | 24 | -- Phasenakkumulator 25 | process begin 26 | wait until rising_edge(CLK); 27 | Accum <= Accum + unsigned(Freq_Data); 28 | end process; 29 | 30 | -- BROM 31 | process begin 32 | wait until rising_edge(CLK); 33 | RomAddr <= Address; -- getaktete Adresse --> BRAM 34 | end process; 35 | 36 | Result <= signed(Sinus_Rom(RomAddr)); 37 | Quadrant <= Accum(Accum'left-1); 38 | Address <= to_integer(Accum(Accum'high-2 downto Accum'high-7)) when (Quadrant='0') 39 | else 63-to_integer(Accum(Accum'high-2 downto Accum'high-7)); 40 | 41 | process begin 42 | wait until rising_edge(CLK); 43 | Sign <= Accum(Accum'left); 44 | end process; 45 | 46 | Dout <= std_logic_vector(Result) when (Sign='1') else std_logic_vector(0-Result); 47 | end rtl; 48 | 49 | -------------------------------------------------------------------------------- /rtl/squareWaveGenerator.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use ieee.numeric_bit.all; 5 | 6 | library work; 7 | use work.all; 8 | 9 | entity PlayNote is 10 | port ( 11 | clk : in std_logic; 12 | note : in integer; 13 | audio : out std_logic 14 | ); 15 | end playnote; 16 | 17 | architecture Behavioral of PlayNote is 18 | 19 | signal c : integer range 0 to 24999999 := 0; 20 | signal x : std_logic:= '0'; 21 | 22 | type note_type is array(0 to 127)of integer; 23 | signal notes: note_type; 24 | 25 | begin 26 | 27 | --teiler fuer die 127 midi noten, generiert mit dem note.rb script 28 | notes <= ( 29 | 6115610,5772367,5448389,5142594,4853963,4581531,4324389,4081680,3852593,3636363,3432270,3239631, 30 | 3057805,2886183,2724194,2571297,2426981,2290765,2162194,2040840,1926296,1818181,1716135,1619815, 31 | 1528902,1443091,1362097,1285648,1213490,1145382,1081097,1020420,963148 ,909090 ,858067 ,809907, 32 | 764451, 721545, 681048, 642824, 606745, 572691, 540548, 510210,481574 ,454545 ,429033 ,404953, 33 | 382225, 360772, 340524, 321412, 303372, 286345, 270274, 255105,240787 ,227272 ,214516 ,202476, 34 | 191112, 180386, 170262, 160706, 151686, 143172, 135137, 127552,120393 ,113636 ,107258 ,101238, 35 | 95556, 90193, 85131, 80353, 75843, 71586, 67568, 63776,60196 ,56818 ,53629 ,50619, 36 | 47778, 45096, 42565, 40176, 37921, 35793, 33784, 31888,30098 ,28409 ,26814 ,25309, 37 | 23889, 22548, 21282, 20088, 18960, 17896, 16892, 15944,15049 ,14204 ,13407 ,12654, 38 | 11944, 11274, 10641, 10044, 9480, 8948, 8446, 7972,7524 ,7102 ,6703 ,6327, 39 | 5972, 5637, 5320, 5022, 4740, 4474, 4223, 3986 40 | ); 41 | 42 | process(clk) begin 43 | if(rising_edge(clk)) then -- warten bis zum naechsten Takt 44 | if (note < 128) then 45 | if (c temp.batch 48 | # impact -batch temp.batch 49 | # rm -f temp.batch 50 | 51 | $(TOP_LEVEL).bit: platforms/$(PLATFORM)/platform.ut $(TOP_LEVEL).ncd 52 | . $(XILINX); bitgen -intstyle ise -f $+ 53 | 54 | $(TOP_LEVEL).twr: $(TOP_LEVEL).ncd ../layout/$(UCF_FILE) 55 | . $(XILINX); trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml $(TOP_LEVEL).twx $< -o $@ $(TOP_LEVEL).pcf -ucf ../layout/$(UCF_FILE) 56 | 57 | $(TOP_LEVEL).ncd: $(TOP_LEVEL)_map.ncd 58 | . $(XILINX); par -w -intstyle ise -ol high $(PARFLAGS) $< $@ $(TOP_LEVEL).pcf 59 | 60 | $(TOP_LEVEL)_map.ncd: $(TOP_LEVEL).ngd 61 | . $(XILINX); map -intstyle ise -p $(FPGA) $(MAPFLAGS) -ir off -pr off -c 100 -o $@ $< $(TOP_LEVEL).pcf -w 62 | 63 | $(TOP_LEVEL).ngd: $(TOP_LEVEL).ngc ../layout/$(UCF_FILE) 64 | . $(XILINX); ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ../layout/$(UCF_FILE) -p $(FPGA) $< $@ 65 | 66 | $(TOP_LEVEL).ngc: platforms/$(PLATFORM)/platform.xst $(TOP_LEVEL).prj 67 | mkdir -p xst/projnav.tmp 68 | sed s/TopLevel/$(TOP_LEVEL)/g $< > tmp.xst 69 | . $(XILINX); xst -intstyle ise -ifn tmp.xst -ofn $(TOP_LEVEL).syr 70 | 71 | $(TOP_LEVEL).prj: ../rtl/*.vhd* 72 | for i in ../rtl/*.vhd*; do echo "vhdl work $$i"; done > $@ 73 | 74 | prog: $(TOP_LEVEL).bit 75 | sudo /usr/local/bin/djtgcfg prog -i 0 -d Nexys3 -f $(TOP_LEVEL).bit 76 | 77 | clean: 78 | rm -rf *.xsvf *.csvf _ngo *.bgn *.drc *.ncd *.ntrc_log *.prj *.twr *.csv *.html _xmsgs *.bit *.gise *.ngc *.pad *.ptwx *.twx *.ngm *.txt *.xml *.xrpt *.bld *.ise *.ngd *.par *.stx *.map *.twr auto_project_xdb *.cmd_log *.lso *.ngr *.pcf *.syr *.unroutes *.xpi *.mrp xst *.log *.cmd *.xwbt iseconfig xlnx_auto_0_xdb *.xst 79 | -------------------------------------------------------------------------------- /rtl/midi.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | --use ieee.std_logic_arith.all; 5 | --use ieee.std_logic_unsigned.all; 6 | library work; 7 | use work.all; 8 | 9 | entity midi is port( 10 | clk : in std_logic; 11 | midi_in : in std_logic; 12 | midi_new : out std_logic := '0'; 13 | midi_ch : out std_logic_vector(3 downto 0) := "0000"; 14 | midi_note : out std_logic_vector(6 downto 0) := "0000000"; 15 | midi_velo : out std_logic_vector(6 downto 0) := "0000000" 16 | ); 17 | end midi; 18 | 19 | architecture rtl of midi is 20 | type midi_state_type is (status,note_off,note_on,velocity); 21 | signal uart_busy : std_logic; 22 | signal midi_data : std_logic_vector(7 downto 0); 23 | signal midi_state : midi_state_type := status; 24 | signal next_midi_state : midi_state_type := status; 25 | signal falling : std_logic := '0'; 26 | signal off : std_logic := '0'; 27 | 28 | begin 29 | 30 | uart1: entity work.RS232 port map(midi_in,midi_data,uart_busy,open,"00000000",'0',open,clk); 31 | uart_edge: entity work.edge_detect port map(uart_busy,clk,falling); 32 | 33 | process begin 34 | wait until rising_edge(clk); 35 | midi_new <= '0'; 36 | if(falling = '1') then 37 | if(not (midi_data = "11111110" or midi_data = "11111000")) then --active sense or clock 38 | case midi_state is 39 | when status => 40 | --midi_new <= '0'; 41 | if(midi_data(7 downto 4) = "1000") then --note off 42 | midi_state <= note_off; 43 | midi_ch <= midi_data(3 downto 0); 44 | midi_velo <= "0000000"; 45 | off <= '1'; 46 | elsif(midi_data(7 downto 4) = "1001") then --note on 47 | midi_state <= note_on; 48 | midi_ch <= midi_data(3 downto 0); 49 | off <= '0'; 50 | end if; 51 | when note_on => 52 | if(midi_data(7) = '0') then 53 | midi_note <= midi_data(6 downto 0); 54 | midi_state <= velocity; 55 | else 56 | midi_state <= status; 57 | end if; 58 | when note_off => 59 | if(midi_data(7) = '0') then 60 | midi_note <= midi_data(6 downto 0); 61 | midi_state <= velocity; 62 | else 63 | midi_state <= status; 64 | end if; 65 | when velocity => 66 | if(midi_data(7) = '0') then 67 | if(off = '0') then 68 | midi_velo <= midi_data(6 downto 0); 69 | else 70 | midi_velo <= "0000000"; 71 | end if; 72 | midi_state <= status; 73 | midi_new <= '1'; 74 | else 75 | midi_state <= status; 76 | end if; 77 | end case; 78 | end if; 79 | end if; 80 | end process; 81 | end rtl; 82 | 83 | -------------------------------------------------------------------------------- /rtl/uart.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | entity RS232 is 6 | Generic ( Quarz_Taktfrequenz : integer := 100000000; -- Hertz 7 | Baudrate : integer := 31250 -- Bits/Sec 8 | ); 9 | Port ( RXD : in STD_LOGIC; 10 | RX_Data : out STD_LOGIC_VECTOR (7 downto 0); 11 | RX_Busy : out STD_LOGIC; 12 | TXD : out STD_LOGIC; 13 | TX_Data : in STD_LOGIC_VECTOR (7 downto 0); 14 | TX_Start : in STD_LOGIC; 15 | TX_Busy : out STD_LOGIC; 16 | CLK : in STD_LOGIC 17 | ); 18 | end RS232; 19 | 20 | architecture Behavioral of RS232 is 21 | signal txstart : std_logic := '0'; 22 | signal txsr : std_logic_vector (9 downto 0) := "1111111111"; -- Startbit, 8 Datenbits, Stopbit 23 | signal txbitcnt : integer range 0 to 10 := 10; 24 | signal txcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1; 25 | 26 | signal rxd_sr : std_logic_vector (3 downto 0) := "1111"; -- Flankenerkennung und Eintakten 27 | signal rxsr : std_logic_vector (7 downto 0) := "00000000"; -- 8 Datenbits 28 | signal rxbitcnt : integer range 0 to 9 := 9; 29 | signal rxcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1; 30 | 31 | begin 32 | -- Senden 33 | process begin 34 | wait until rising_edge(CLK); 35 | txstart <= TX_Start; 36 | if (TX_Start='1' and txstart='0') then -- steigende Flanke, los gehts 37 | txcnt <= 0; -- Zähler initialisieren 38 | txbitcnt <= 0; 39 | txsr <= '1' & TX_Data & '0'; -- Stopbit, 8 Datenbits, Startbit, rechts gehts los 40 | else 41 | if(txcnt<(Quarz_Taktfrequenz/Baudrate)-1) then 42 | txcnt <= txcnt+1; 43 | else -- nächstes Bit ausgeben 44 | if (txbitcnt<10) then 45 | txcnt <= 0; 46 | txbitcnt <= txbitcnt+1; 47 | txsr <= '1' & txsr(txsr'left downto 1); 48 | end if; 49 | end if; 50 | end if; 51 | end process; 52 | TXD <= txsr(0); -- LSB first 53 | TX_Busy <= '1' when (TX_Start='1' or txbitcnt<10) else '0'; 54 | 55 | -- Empfangen 56 | process begin 57 | wait until rising_edge(CLK); 58 | rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & RXD; 59 | if (rxbitcnt<9) then -- Empfang läuft 60 | if(rxcnt<(Quarz_Taktfrequenz/Baudrate)-1) then 61 | rxcnt <= rxcnt+1; 62 | else 63 | rxcnt <= 0; 64 | rxbitcnt <= rxbitcnt+1; 65 | rxsr <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1); -- rechts schieben, weil LSB first end if; 66 | end if; 67 | else -- warten auf Startbit 68 | if (rxd_sr(3 downto 2) = "10") then -- fallende Flanke Startbit 69 | rxcnt <= ((Quarz_Taktfrequenz/Baudrate)-1)/2; -- erst mal nur halbe Bitzeit abwarten 70 | rxbitcnt <= 0; 71 | end if; 72 | end if; 73 | end process; 74 | RX_Data <= rxsr; 75 | RX_Busy <= '1' when (rxbitcnt<9) else '0'; 76 | 77 | end Behavioral; 78 | -------------------------------------------------------------------------------- /syn/platforms/atlys/platform.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (C) 2009-2011 Chris McClelland 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | # You should have received a copy of the GNU General Public License 15 | # along with this program. If not, see . 16 | # 17 | NET "reset_in" LOC = "T15"; # BRST 18 | 19 | # PortB 20 | NET "fifoData_io<0>" LOC = "A2"; # PB0 21 | NET "fifoData_io<1>" LOC = "D6"; # PB1 22 | NET "fifoData_io<2>" LOC = "C6"; # PB2 23 | NET "fifoData_io<3>" LOC = "B3"; # PB3 24 | NET "fifoData_io<4>" LOC = "A3"; # PB4 25 | NET "fifoData_io<5>" LOC = "B4"; # PB5 26 | NET "fifoData_io<6>" LOC = "A4"; # PB6 27 | NET "fifoData_io<7>" LOC = "C5"; # PB7 28 | 29 | NET "ifclk_in" LOC = "C10"; 30 | NET "gotData_in" LOC = "C15"; # FLAGC 31 | NET "gotRoom_in" LOC = "A9"; # FLAGB 32 | 33 | # PortA 34 | NET "sloe_out" LOC = "A15"; # PA2 35 | NET "fifoAddr_out<0>" LOC = "A14"; # PA4 36 | NET "fifoAddr_out<1>" LOC = "B14"; # PA5 37 | NET "pktEnd_out" LOC = "C4"; # PA6 38 | 39 | NET "slrd_out" LOC = "F13"; 40 | NET "slwr_out" LOC = "E13"; 41 | 42 | # On-board peripheral signals 43 | NET "led_out<0>" LOC = "U18"; 44 | NET "led_out<1>" LOC = "M14"; 45 | NET "led_out<2>" LOC = "N14"; 46 | NET "led_out<3>" LOC = "L14"; 47 | NET "led_out<4>" LOC = "M13"; 48 | NET "led_out<5>" LOC = "D4"; 49 | NET "led_out<6>" LOC = "P16"; 50 | NET "led_out<7>" LOC = "N12"; 51 | 52 | NET "sseg_out<6>" LOC = "U16"; # segment g 53 | NET "sseg_out<5>" LOC = "U15"; # segment f 54 | NET "sseg_out<4>" LOC = "U13"; # segment e 55 | NET "sseg_out<3>" LOC = "M11"; # segment d 56 | NET "sseg_out<2>" LOC = "R11"; # segment c 57 | NET "sseg_out<1>" LOC = "T12"; # segment b 58 | NET "sseg_out<0>" LOC = "N10"; # segment a 59 | NET "sseg_out<7>" LOC = "M10"; # decimal point 60 | 61 | NET "anode_out<0>" LOC = "U11"; 62 | NET "anode_out<1>" LOC = "R10"; 63 | NET "anode_out<2>" LOC = "U10"; 64 | NET "anode_out<3>" LOC = "R8"; 65 | 66 | NET "sw_in<0>" LOC = "A10"; # SW0 67 | NET "sw_in<1>" LOC = "D14"; # SW1 68 | NET "sw_in<2>" LOC = "C14"; # SW2 69 | NET "sw_in<3>" LOC = "P15"; # SW3 70 | NET "sw_in<4>" LOC = "P12"; # SW4 71 | NET "sw_in<5>" LOC = "R5"; # SW5 72 | NET "sw_in<6>" LOC = "T5"; # SW6 73 | NET "sw_in<7>" LOC = "E4"; # SW7 74 | 75 | #======================================================== 76 | # Timing constraint of S3 50-MHz onboard oscillator 77 | # name of the clock signal is clk 78 | #======================================================== 79 | NET "ifclk_in" TNM_NET = "ifclk_in"; 80 | TIMESPEC "TS_clk" = PERIOD "ifclk_in" 20 ns HIGH 50 %; 81 | -------------------------------------------------------------------------------- /syn/platforms/nexys2-500/platform.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (C) 2009-2011 Chris McClelland 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | # You should have received a copy of the GNU General Public License 15 | # along with this program. If not, see . 16 | # 17 | NET "reset_in" LOC = "B18"; # BTN(3) 18 | 19 | # PortB 20 | NET "fifoData_io<0>" LOC = "R14"; # PB0 21 | NET "fifoData_io<1>" LOC = "R13"; # PB1 22 | NET "fifoData_io<2>" LOC = "P13"; # PB2 23 | NET "fifoData_io<3>" LOC = "T12"; # PB3 24 | NET "fifoData_io<4>" LOC = "N11"; # PB4 25 | NET "fifoData_io<5>" LOC = "R11"; # PB5 26 | NET "fifoData_io<6>" LOC = "P10"; # PB6 27 | NET "fifoData_io<7>" LOC = "R10"; # PB7 28 | 29 | NET "ifclk_in" LOC = "T15"; 30 | NET "gotData_in" LOC = "V16"; # FLAGC 31 | NET "gotRoom_in" LOC = "U14"; # FLAGB 32 | 33 | # PortA 34 | NET "sloe_out" LOC = "V15"; # PA2 35 | NET "fifoAddr_out<0>" LOC = "T14"; # PA4 36 | NET "fifoAddr_out<1>" LOC = "V13"; # PA5 37 | NET "pktEnd_out" LOC = "V12"; # PA6 38 | 39 | NET "slrd_out" LOC = "N9"; 40 | NET "slwr_out" LOC = "V9"; 41 | 42 | # On-board peripheral signals 43 | NET "led_out<0>" LOC = "J14"; 44 | NET "led_out<1>" LOC = "J15"; 45 | NET "led_out<2>" LOC = "K15"; 46 | NET "led_out<3>" LOC = "K14"; 47 | NET "led_out<4>" LOC = "E17"; 48 | NET "led_out<5>" LOC = "P15"; 49 | NET "led_out<6>" LOC = "F4"; 50 | NET "led_out<7>" LOC = "R4"; 51 | 52 | NET "sseg_out<6>" LOC = "H14"; # segment g 53 | NET "sseg_out<5>" LOC = "J17"; # segment f 54 | NET "sseg_out<4>" LOC = "G14"; # segment e 55 | NET "sseg_out<3>" LOC = "D16"; # segment d 56 | NET "sseg_out<2>" LOC = "D17"; # segment c 57 | NET "sseg_out<1>" LOC = "F18"; # segment b 58 | NET "sseg_out<0>" LOC = "L18"; # segment a 59 | NET "sseg_out<7>" LOC = "C17"; # decimal point 60 | 61 | NET "anode_out<0>" LOC = "F17"; 62 | NET "anode_out<1>" LOC = "H17"; 63 | NET "anode_out<2>" LOC = "C18"; 64 | NET "anode_out<3>" LOC = "F15"; 65 | 66 | NET "sw_in<0>" LOC = "G18"; # SW0 67 | NET "sw_in<1>" LOC = "H18"; # SW1 68 | NET "sw_in<2>" LOC = "K18"; # SW2 69 | NET "sw_in<3>" LOC = "K17"; # SW3 70 | NET "sw_in<4>" LOC = "L14"; # SW4 71 | NET "sw_in<5>" LOC = "L13"; # SW5 72 | NET "sw_in<6>" LOC = "N17"; # SW6 73 | NET "sw_in<7>" LOC = "R17"; # SW7 74 | 75 | #======================================================== 76 | # Timing constraint of S3 50-MHz onboard oscillator 77 | # name of the clock signal is clk 78 | #======================================================== 79 | NET "ifclk_in" CLOCK_DEDICATED_ROUTE = FALSE; 80 | NET "ifclk_in" TNM_NET = "ifclk_in"; 81 | TIMESPEC "TS_clk" = PERIOD "ifclk_in" 20 ns HIGH 50 %; 82 | -------------------------------------------------------------------------------- /syn/platforms/nexys2-1200/platform.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (C) 2009-2011 Chris McClelland 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | # You should have received a copy of the GNU General Public License 15 | # along with this program. If not, see . 16 | # 17 | NET "reset_in" LOC = "B18"; # BTN(3) 18 | 19 | # PortB 20 | NET "fifoData_io<0>" LOC = "R14"; # PB0 21 | NET "fifoData_io<1>" LOC = "R13"; # PB1 22 | NET "fifoData_io<2>" LOC = "P13"; # PB2 23 | NET "fifoData_io<3>" LOC = "T12"; # PB3 24 | NET "fifoData_io<4>" LOC = "N11"; # PB4 25 | NET "fifoData_io<5>" LOC = "R11"; # PB5 26 | NET "fifoData_io<6>" LOC = "P10"; # PB6 27 | NET "fifoData_io<7>" LOC = "R10"; # PB7 28 | 29 | NET "ifclk_in" LOC = "T15"; 30 | NET "gotData_in" LOC = "V16"; # FLAGC 31 | NET "gotRoom_in" LOC = "U14"; # FLAGB 32 | 33 | # PortA 34 | NET "sloe_out" LOC = "V15"; # PA2 35 | NET "fifoAddr_out<0>" LOC = "T14"; # PA4 36 | NET "fifoAddr_out<1>" LOC = "V13"; # PA5 37 | NET "pktEnd_out" LOC = "V12"; # PA6 38 | 39 | NET "slrd_out" LOC = "N9"; 40 | NET "slwr_out" LOC = "V9"; 41 | 42 | # On-board peripheral signals 43 | NET "led_out<0>" LOC = "J14"; 44 | NET "led_out<1>" LOC = "J15"; 45 | NET "led_out<2>" LOC = "K15"; 46 | NET "led_out<3>" LOC = "K14"; 47 | NET "led_out<4>" LOC = "E16"; 48 | NET "led_out<5>" LOC = "P16"; 49 | NET "led_out<6>" LOC = "E4"; 50 | NET "led_out<7>" LOC = "P4"; 51 | 52 | NET "sseg_out<6>" LOC = "H14"; # segment g 53 | NET "sseg_out<5>" LOC = "J17"; # segment f 54 | NET "sseg_out<4>" LOC = "G14"; # segment e 55 | NET "sseg_out<3>" LOC = "D16"; # segment d 56 | NET "sseg_out<2>" LOC = "D17"; # segment c 57 | NET "sseg_out<1>" LOC = "F18"; # segment b 58 | NET "sseg_out<0>" LOC = "L18"; # segment a 59 | NET "sseg_out<7>" LOC = "C17"; # decimal point 60 | 61 | NET "anode_out<0>" LOC = "F17"; 62 | NET "anode_out<1>" LOC = "H17"; 63 | NET "anode_out<2>" LOC = "C18"; 64 | NET "anode_out<3>" LOC = "F15"; 65 | 66 | NET "sw_in<0>" LOC = "G18"; # SW0 67 | NET "sw_in<1>" LOC = "H18"; # SW1 68 | NET "sw_in<2>" LOC = "K18"; # SW2 69 | NET "sw_in<3>" LOC = "K17"; # SW3 70 | NET "sw_in<4>" LOC = "L14"; # SW4 71 | NET "sw_in<5>" LOC = "L13"; # SW5 72 | NET "sw_in<6>" LOC = "N17"; # SW6 73 | NET "sw_in<7>" LOC = "R17"; # SW7 74 | 75 | #======================================================== 76 | # Timing constraint of S3 50-MHz onboard oscillator 77 | # name of the clock signal is clk 78 | #======================================================== 79 | NET "ifclk_in" CLOCK_DEDICATED_ROUTE = FALSE; 80 | NET "ifclk_in" TNM_NET = "ifclk_in"; 81 | TIMESPEC "TS_clk" = PERIOD "ifclk_in" 20 ns HIGH 50 %; 82 | -------------------------------------------------------------------------------- /syn/platforms/s3board/platform.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (C) 2009-2011 Chris McClelland 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | # You should have received a copy of the GNU General Public License 15 | # along with this program. If not, see . 16 | # 17 | NET "reset_in" LOC = "L14"; # BTN(3) 18 | 19 | # PortB 20 | NET "fifoData_io<0>" LOC = "E6" | IOSTANDARD=LVCMOS33; # PB0 21 | NET "fifoData_io<1>" LOC = "D5" | IOSTANDARD=LVCMOS33; # PB1 22 | NET "fifoData_io<2>" LOC = "C5" | IOSTANDARD=LVCMOS33; # PB2 23 | NET "fifoData_io<3>" LOC = "D6" | IOSTANDARD=LVCMOS33; # PB3 24 | NET "fifoData_io<4>" LOC = "C6" | IOSTANDARD=LVCMOS33; # PB4 25 | NET "fifoData_io<5>" LOC = "E7" | IOSTANDARD=LVCMOS33; # PB5 26 | NET "fifoData_io<6>" LOC = "C7" | IOSTANDARD=LVCMOS33; # PB6 27 | NET "fifoData_io<7>" LOC = "D7" | IOSTANDARD=LVCMOS33; # PB7 28 | 29 | NET "ifclk_in" LOC = "C9" | IOSTANDARD=LVCMOS33; 30 | NET "gotData_in" LOC = "D10" | IOSTANDARD=LVCMOS33; # FLAGC 31 | NET "gotRoom_in" LOC = "D8" | IOSTANDARD=LVCMOS33; # FLAGB 32 | 33 | # PortA 34 | NET "sloe_out" LOC = "A4" | IOSTANDARD=LVCMOS33; # PA2 35 | NET "fifoAddr_out<0>" LOC = "A5" | IOSTANDARD=LVCMOS33; # PA4 36 | NET "fifoAddr_out<1>" LOC = "B6" | IOSTANDARD=LVCMOS33; # PA5 37 | NET "pktEnd_out" LOC = "B7" | IOSTANDARD=LVCMOS33; # PA6 38 | 39 | NET "slrd_out" LOC = "A13" | IOSTANDARD=LVCMOS33; 40 | NET "slwr_out" LOC = "B14" | IOSTANDARD=LVCMOS33; 41 | 42 | # On-board peripheral signals 43 | NET "led_out<0>" LOC = "K12"; 44 | NET "led_out<1>" LOC = "P14"; 45 | NET "led_out<2>" LOC = "L12"; 46 | NET "led_out<3>" LOC = "N14"; 47 | NET "led_out<4>" LOC = "P13"; 48 | NET "led_out<5>" LOC = "N12"; 49 | NET "led_out<6>" LOC = "P12"; 50 | NET "led_out<7>" LOC = "P11"; 51 | 52 | NET "sseg_out<0>" LOC = "E14"; # segment g 53 | NET "sseg_out<1>" LOC = "G13"; # segment f 54 | NET "sseg_out<2>" LOC = "N15"; # segment e 55 | NET "sseg_out<3>" LOC = "P15"; # segment d 56 | NET "sseg_out<4>" LOC = "R16"; # segment c 57 | NET "sseg_out<5>" LOC = "F13"; # segment b 58 | NET "sseg_out<6>" LOC = "N16"; # segment a 59 | NET "sseg_out<7>" LOC = "P16"; # decimal point 60 | 61 | NET "anode_out<0>" LOC = "D14"; 62 | NET "anode_out<1>" LOC = "G14"; 63 | NET "anode_out<2>" LOC = "F14"; 64 | NET "anode_out<3>" LOC = "E13"; 65 | 66 | NET "sw_in<0>" LOC = "F12"; # SW0 67 | NET "sw_in<1>" LOC = "G12"; # SW1 68 | NET "sw_in<2>" LOC = "H14"; # SW2 69 | NET "sw_in<3>" LOC = "H13"; # SW3 70 | NET "sw_in<4>" LOC = "J14"; # SW4 71 | NET "sw_in<5>" LOC = "J13"; # SW5 72 | NET "sw_in<6>" LOC = "K14"; # SW6 73 | NET "sw_in<7>" LOC = "K13"; # SW7 74 | 75 | #======================================================== 76 | # Timing constraint of S3 50-MHz onboard oscillator 77 | # name of the clock signal is clk 78 | #======================================================== 79 | NET "ifclk_in" TNM_NET = "ifclk_in"; 80 | TIMESPEC "TS_clk" = PERIOD "ifclk_in" 20 ns HIGH 50 %; -------------------------------------------------------------------------------- /rtl/channel.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | --use ieee.std_logic_arith.all; 5 | --use ieee.std_logic_unsigned.all; 6 | library work; 7 | use work.all; 8 | 9 | entity channel is port( 10 | clk : in std_logic; 11 | note_on : in std_logic; 12 | note_in : in std_logic_vector(6 downto 0); 13 | velocity : in std_logic_vector(6 downto 0); 14 | volume : in std_logic_vector(6 downto 0); 15 | audio_out: out std_logic_vector(7 downto 0) 16 | ); 17 | end channel; 18 | 19 | architecture rtl of channel is 20 | 21 | type note_type is array (integer range 0 to 2) of std_logic_vector(6 downto 0); 22 | signal note : note_type; 23 | 24 | type volume_type is array (integer range 0 to 2) of std_logic_vector(6 downto 0); 25 | signal volumes : volume_type; 26 | 27 | type audio_type is array (integer range 0 to 2) of std_logic_vector(7 downto 0); 28 | signal audio : audio_type; 29 | 30 | type note_map_type is array (integer range 0 to 2) of std_logic_vector(6 downto 0); 31 | signal note_map : note_map_type; 32 | 33 | signal next_synth : integer range 0 to 2 := 0; 34 | signal tmp : std_logic_vector(13 downto 0); 35 | --signal note : integer := 255; 36 | --signal sound : std_logic := '0'; 37 | --signal ddfsnote : std_logic_vector(17 downto 0) := (others => '0'); 38 | 39 | --type ddfstype is array (0 to 127) of std_logic_vector (19 downto 0); 40 | --signal midi2ddfs : ddfstype := (x"00057", x"0005d", x"00062", x"00068", x"0006e", x"00075", x"0007c", x"00083", x"0008b", x"00093", x"0009c", x"000a5", x"000af", x"000ba", x"000c5", x"000d0", x"000dd", x"000ea", x"000f8", x"00107", x"00116", x"00127", x"00138", x"0014b", x"0015f", x"00174", x"0018a", x"001a1", x"001ba", x"001d4", x"001f0", x"0020e", x"0022d", x"0024e", x"00271", x"00296", x"002be", x"002e8", x"00314", x"00343", x"00374", x"003a9", x"003e1", x"0041c", x"0045a", x"0049d", x"004e3", x"0052d", x"0057c", x"005d0", x"00628", x"00686", x"006e9", x"00752", x"007c2", x"00838", x"008b5", x"0093a", x"009c6", x"00a5b", x"00af9", x"00ba0", x"00c51", x"00d0c", x"00dd3", x"00ea5", x"00f84", x"01071", x"0116b", x"01274", x"0138d", x"014b7", x"015f2", x"01740", x"018a2", x"01a19", x"01ba6", x"01d4b", x"01f09", x"020e2", x"022d6", x"024e8", x"0271a", x"0296e", x"02be4", x"02e80", x"03144", x"03432", x"0374d", x"03a97", x"03e13", x"041c4", x"045ad", x"049d1", x"04e35", x"052dc", x"057c9", x"05d01", x"06289", x"06865", x"06e9a", x"0752e", x"07c26", x"08388", x"08b5a", x"093a3", x"09c6b", x"0a5b8", x"0af92", x"0ba03", x"0c513", x"0d0cb", x"0dd35", x"0ea5c", x"0f84c", x"10710", x"116b4", x"12747", x"138d6", x"14b70", x"15f25", x"17407", x"18a26", x"1a196", x"1ba6b", x"1d4b9", x"1f099", x"20e20"); 41 | begin 42 | 43 | --sin1:entity work.sinuspwm port map(clk,r,ddfsnote); 44 | --clk,note,volume,audio 45 | soundgen:for i in 0 to 2 generate 46 | soundi:entity work.square port map(clk,note_map(i),volumes(i),audio(i)); 47 | end generate; 48 | 49 | audio_out <= std_logic_vector( 50 | unsigned(audio(0))+ 51 | unsigned(audio(1))+ 52 | unsigned(audio(2))--+ 53 | --unsigned(audio(3))--+ 54 | --unsigned(audio(4))+ 55 | --unsigned(audio(5))+ 56 | --unsigned(audio(6))+ 57 | --unsigned(audio(7)) 58 | ); 59 | 60 | process begin 61 | wait until rising_edge(clk); 62 | if(note_on = '1') then 63 | if(velocity = "0000000") then 64 | vol:for i in 0 to 2 loop 65 | if note_map(i) = note_in then 66 | volumes(i) <= "0000000"; 67 | next_synth <= i; 68 | end if; 69 | end loop; 70 | else 71 | note_map(next_synth) <= note_in; 72 | tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(velocity))*to_integer(unsigned(volume)),14)); 73 | volumes(next_synth) <= tmp(13 downto 7); 74 | next_synth <= next_synth + 1; 75 | end if; 76 | end if; 77 | end process; 78 | end rtl; 79 | 80 | -------------------------------------------------------------------------------- /rtl/midi_tb.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:49:01 02/03/2012 6 | -- Design Name: 7 | -- Module Name: /home/rene/test/midi_tb.vhd 8 | -- Project Name: test 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: midi 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY midi_tb IS 36 | END midi_tb; 37 | 38 | ARCHITECTURE behavior OF midi_tb IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT midi 43 | PORT( 44 | clk : IN std_logic; 45 | midi_in : IN std_logic; 46 | midi_new : OUT std_logic; 47 | midi_ch : OUT std_logic_vector(3 downto 0); 48 | midi_note : OUT std_logic_vector(6 downto 0); 49 | midi_velo : OUT std_logic_vector(6 downto 0) 50 | ); 51 | END COMPONENT; 52 | 53 | 54 | --Inputs 55 | signal clk : std_logic := '0'; 56 | signal midi_in : std_logic := '0'; 57 | signal midi_data : std_logic_vector(7 downto 0) := (others => '0'); 58 | signal uart_busy : std_logic := '1'; 59 | 60 | --Outputs 61 | signal midi_new : std_logic; 62 | signal midi_ch : std_logic_vector(3 downto 0); 63 | signal midi_note : std_logic_vector(6 downto 0); 64 | signal midi_velo : std_logic_vector(6 downto 0); 65 | signal data : std_logic_vector(7 downto 0); 66 | -- Clock period definitions 67 | constant clk_period : time := 10 ns; 68 | constant bit_time: time := 1 sec / 31250; 69 | BEGIN 70 | 71 | -- Instantiate the Unit Under Test (UUT) 72 | uut: midi PORT MAP ( 73 | clk => clk, 74 | midi_in => midi_in, 75 | midi_new => midi_new, 76 | midi_ch => midi_ch, 77 | midi_note => midi_note, 78 | midi_velo => midi_velo 79 | ); 80 | 81 | -- Clock process definitions 82 | clk_process :process 83 | begin 84 | clk <= '0'; 85 | wait for clk_period/2; 86 | clk <= '1'; 87 | wait for clk_period/2; 88 | end process; 89 | 90 | 91 | -- Stimulus process 92 | stim_proc: process 93 | begin 94 | -- hold reset state for 100 ns. 95 | midi_in <= '1'; 96 | wait for 100 ns; 97 | 98 | wait for bit_time; 99 | data <= "10010101"; 100 | midi_in <= '0'; 101 | wait for bit_time; 102 | for i in 0 to 7 loop 103 | midi_in <= data(i); 104 | wait for bit_time; 105 | end loop; 106 | midi_in <= '1'; 107 | wait for bit_time; 108 | 109 | wait for bit_time; 110 | data <= "01010101"; 111 | midi_in <= '0'; 112 | wait for bit_time; 113 | for i in 0 to 7 loop 114 | midi_in <= data(i); 115 | wait for bit_time; 116 | end loop; 117 | midi_in <= '1'; 118 | wait for bit_time; 119 | 120 | wait for bit_time; 121 | data <= "01111111"; 122 | midi_in <= '0'; 123 | wait for bit_time; 124 | for i in 0 to 7 loop 125 | midi_in <= data(i); 126 | wait for bit_time; 127 | end loop; 128 | midi_in <= '1'; 129 | wait for bit_time; 130 | 131 | 132 | wait for bit_time; 133 | data <= "10000101"; 134 | midi_in <= '0'; 135 | wait for bit_time; 136 | for i in 0 to 7 loop 137 | midi_in <= data(i); 138 | wait for bit_time; 139 | end loop; 140 | midi_in <= '1'; 141 | wait for bit_time; 142 | 143 | wait for bit_time; 144 | data <= "01010101"; 145 | midi_in <= '0'; 146 | wait for bit_time; 147 | for i in 0 to 7 loop 148 | midi_in <= data(i); 149 | wait for bit_time; 150 | end loop; 151 | midi_in <= '1'; 152 | wait for bit_time; 153 | 154 | wait for bit_time; 155 | data <= "00000000"; 156 | midi_in <= '0'; 157 | wait for bit_time; 158 | for i in 0 to 7 loop 159 | midi_in <= data(i); 160 | wait for bit_time; 161 | end loop; 162 | midi_in <= '1'; 163 | wait for bit_time; 164 | 165 | 166 | 167 | wait for clk_period*10; 168 | -- insert stimulus here 169 | 170 | wait; 171 | end process; 172 | 173 | END; 174 | -------------------------------------------------------------------------------- /syn/platforms/nexys3/platform.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (C) 2009-2011 Chris McClelland 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | # You should have received a copy of the GNU General Public License 15 | # along with this program. If not, see . 16 | # 17 | NET "reset_in" LOC = "B8" | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS 18 | 19 | # PortB 20 | NET "fifoData_io<0>" LOC = "E1" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0 21 | NET "fifoData_io<1>" LOC = "F4" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1 22 | NET "fifoData_io<2>" LOC = "F3" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2 23 | NET "fifoData_io<3>" LOC = "D2" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3 24 | NET "fifoData_io<4>" LOC = "D1" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4 25 | NET "fifoData_io<5>" LOC = "H7" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5 26 | NET "fifoData_io<6>" LOC = "G6" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6 27 | NET "fifoData_io<7>" LOC = "E4" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7 28 | 29 | NET "ifclk_in" LOC = "H2" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41P_GCLK27_M3DQ4, Sch name = U-IFCLK 30 | NET "gotData_in" LOC = "F5" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC 31 | NET "gotRoom_in" LOC = "K4" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB 32 | 33 | # PortA 34 | NET "sloe_out" LOC = "H6" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49P_M3A7, Sch name = U-SLOE 35 | NET "fifoAddr_out<0>" LOC = "H5" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49N_M3A2, Sch name = U-FIFOAD0 36 | NET "fifoAddr_out<1>" LOC = "E3" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50P_M3WE, Sch name = U-FIFOAD1 37 | NET "pktEnd_out" LOC = "D3" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54N_M3A11, Sch name = U-PKTEND 38 | 39 | NET "slrd_out" LOC = "C2" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD 40 | NET "slwr_out" LOC = "C1" | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83N_VREF, Sch name = U-SLWR 41 | 42 | # On-board peripheral signals 43 | NET "led_out<0>" LOC = "U16" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0 44 | NET "led_out<1>" LOC = "V16" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1 45 | NET "led_out<2>" LOC = "U15" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2 46 | NET "led_out<3>" LOC = "V15" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5N, Sch name = LD3 47 | NET "led_out<4>" LOC = "M11" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15P, Sch name = LD4 48 | NET "led_out<5>" LOC = "N11" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15N, Sch name = LD5 49 | NET "led_out<6>" LOC = "R11" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16P, Sch name = LD6 50 | NET "led_out<7>" LOC = "T11" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16N_VREF, Sch name = LD7 51 | 52 | NET "sseg_out<6>" LOC = "L14" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG 53 | NET "sseg_out<5>" LOC = "N14" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF 54 | NET "sseg_out<4>" LOC = "M14" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE 55 | NET "sseg_out<3>" LOC = "U18" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD 56 | NET "sseg_out<2>" LOC = "U17" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC 57 | NET "sseg_out<1>" LOC = "T18" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB 58 | NET "sseg_out<0>" LOC = "T17" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA 59 | NET "sseg_out<7>" LOC = "M13" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP 60 | 61 | NET "anode_out<0>" LOC = "N16" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0 62 | NET "anode_out<1>" LOC = "N15" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1 63 | NET "anode_out<2>" LOC = "P18" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2 64 | NET "anode_out<3>" LOC = "P17" | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3 65 | 66 | NET "sw_in<0>" LOC = "T10" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0 67 | NET "sw_in<1>" LOC = "T9" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1 68 | NET "sw_in<2>" LOC = "V9" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2 69 | NET "sw_in<3>" LOC = "M8" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3 70 | NET "sw_in<4>" LOC = "N8" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4 71 | NET "sw_in<5>" LOC = "U8" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5 72 | NET "sw_in<6>" LOC = "V8" | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6 73 | NET "sw_in<7>" LOC = "T5" | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7 74 | 75 | #======================================================== 76 | # Timing constraint of S3 50-MHz onboard oscillator 77 | # name of the clock signal is clk 78 | #======================================================== 79 | NET "ifclk_in" TNM_NET = "ifclk_in"; 80 | TIMESPEC "TS_clk" = PERIOD "ifclk_in" 20 ns HIGH 50 %; 81 | -------------------------------------------------------------------------------- /rtl/synth_top.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | --use ieee.std_logic_arith.all; 5 | --use ieee.std_logic_unsigned.all; 6 | library work; 7 | use work.all; 8 | 9 | entity synth_top is port( 10 | clk : in std_logic; 11 | midi_in : in std_logic; 12 | midi_out: out std_logic; 13 | AudioR : out std_logic; 14 | AudioL : out std_logic; 15 | sw : in std_logic_vector(7 downto 0); 16 | Led : out std_logic_vector(7 downto 0) 17 | ); 18 | end synth_top; 19 | 20 | architecture rtl of synth_top is 21 | 22 | component pwm is 23 | Generic( 24 | width: natural := 8; -- Breite 25 | fclk : integer := 100000000; -- Taktfrequenz 26 | fpwm : integer := 500000 -- PWM-Frequenz; 27 | ); 28 | Port( 29 | clk : in std_logic; 30 | pwmvalue : in std_logic_vector (width-1 downto 0); 31 | pwmout : out std_logic 32 | ); 33 | end component; 34 | 35 | signal midi_new : std_logic := '0'; 36 | signal midi_ch : std_logic_vector(3 downto 0); 37 | signal midi_note : std_logic_vector(6 downto 0); 38 | signal midi_velo : std_logic_vector(6 downto 0); 39 | signal master : std_logic_vector(7 downto 0); 40 | --signal ddfsnote : std_logic_vector(17 downto 0) := (others => '0'); 41 | signal pwmaudio : std_logic; 42 | 43 | type note_on_type is array (integer range 0 to 15) of std_logic; 44 | signal note_on : note_on_type; 45 | 46 | type note_in_type is array (integer range 0 to 15) of std_logic_vector(6 downto 0); 47 | signal note_in : note_in_type; 48 | 49 | type velocity_type is array (integer range 0 to 15) of std_logic_vector(6 downto 0); 50 | signal velocity : velocity_type; 51 | 52 | type volume_type is array (integer range 0 to 15) of std_logic_vector(6 downto 0); 53 | signal volume : volume_type; 54 | 55 | type audio_type is array (integer range 0 to 15) of std_logic_vector(7 downto 0); 56 | signal audio_ch : audio_type; 57 | 58 | type ddfstype is array (0 to 127) of std_logic_vector (19 downto 0); 59 | signal midi2ddfs : ddfstype := (x"00057", x"0005d", x"00062", x"00068", x"0006e", x"00075", x"0007c", x"00083", x"0008b", x"00093", x"0009c", x"000a5", x"000af", x"000ba", x"000c5", x"000d0", x"000dd", x"000ea", x"000f8", x"00107", x"00116", x"00127", x"00138", x"0014b", x"0015f", x"00174", x"0018a", x"001a1", x"001ba", x"001d4", x"001f0", x"0020e", x"0022d", x"0024e", x"00271", x"00296", x"002be", x"002e8", x"00314", x"00343", x"00374", x"003a9", x"003e1", x"0041c", x"0045a", x"0049d", x"004e3", x"0052d", x"0057c", x"005d0", x"00628", x"00686", x"006e9", x"00752", x"007c2", x"00838", x"008b5", x"0093a", x"009c6", x"00a5b", x"00af9", x"00ba0", x"00c51", x"00d0c", x"00dd3", x"00ea5", x"00f84", x"01071", x"0116b", x"01274", x"0138d", x"014b7", x"015f2", x"01740", x"018a2", x"01a19", x"01ba6", x"01d4b", x"01f09", x"020e2", x"022d6", x"024e8", x"0271a", x"0296e", x"02be4", x"02e80", x"03144", x"03432", x"0374d", x"03a97", x"03e13", x"041c4", x"045ad", x"049d1", x"04e35", x"052dc", x"057c9", x"05d01", x"06289", x"06865", x"06e9a", x"0752e", x"07c26", x"08388", x"08b5a", x"093a3", x"09c6b", x"0a5b8", x"0af92", x"0ba03", x"0c513", x"0d0cb", x"0dd35", x"0ea5c", x"0f84c", x"10710", x"116b4", x"12747", x"138d6", x"14b70", x"15f25", x"17407", x"18a26", x"1a196", x"1ba6b", x"1d4b9", x"1f099", x"20e20"); 60 | 61 | begin 62 | 63 | --sin1:entity work.sinuspwm port map(clk,r,ddfsnote); 64 | --SoundGen_l:entity work.PlayNote port map(clk,note,l); 65 | pwm1:component pwm port map(clk,master,pwmaudio); 66 | 67 | midi:entity work.midi port map(clk,midi_in,midi_new,midi_ch,midi_note,midi_velo); 68 | 69 | channel0 :entity work.channel port map(clk,note_on( 0),note_in( 0),velocity( 0),volume( 0),audio_ch( 0)); 70 | channel1 :entity work.channel port map(clk,note_on( 1),note_in( 1),velocity( 1),volume( 1),audio_ch( 1)); 71 | channel2 :entity work.channel port map(clk,note_on( 2),note_in( 2),velocity( 2),volume( 2),audio_ch( 2)); 72 | channel3 :entity work.channel port map(clk,note_on( 3),note_in( 3),velocity( 3),volume( 3),audio_ch( 3)); 73 | channel4 :entity work.channel port map(clk,note_on( 4),note_in( 4),velocity( 4),volume( 4),audio_ch( 4)); 74 | channel5 :entity work.channel port map(clk,note_on( 5),note_in( 5),velocity( 5),volume( 5),audio_ch( 5)); 75 | channel6 :entity work.channel port map(clk,note_on( 6),note_in( 6),velocity( 6),volume( 6),audio_ch( 6)); 76 | channel7 :entity work.channel port map(clk,note_on( 7),note_in( 7),velocity( 7),volume( 7),audio_ch( 7)); 77 | channel8 :entity work.channel port map(clk,note_on( 8),note_in( 8),velocity( 8),volume( 8),audio_ch( 8)); 78 | channel9 :entity work.channel port map(clk,note_on( 9),note_in( 9),velocity( 9),volume( 9),audio_ch( 9)); 79 | channel10:entity work.channel port map(clk,note_on(10),note_in(10),velocity(10),volume(10),audio_ch(10)); 80 | channel11:entity work.channel port map(clk,note_on(11),note_in(11),velocity(11),volume(11),audio_ch(11)); 81 | channel12:entity work.channel port map(clk,note_on(12),note_in(12),velocity(12),volume(12),audio_ch(12)); 82 | channel13:entity work.channel port map(clk,note_on(13),note_in(13),velocity(13),volume(13),audio_ch(13)); 83 | channel14:entity work.channel port map(clk,note_on(14),note_in(14),velocity(14),volume(14),audio_ch(14)); 84 | channel15:entity work.channel port map(clk,note_on(15),note_in(15),velocity(15),volume(15),audio_ch(15)); 85 | 86 | master <= std_logic_vector(unsigned(audio_ch( 0)) + 87 | unsigned(audio_ch( 1)) + 88 | unsigned(audio_ch( 2)) + 89 | unsigned(audio_ch( 3)) + 90 | unsigned(audio_ch( 4)) + 91 | unsigned(audio_ch( 5)) + 92 | unsigned(audio_ch( 6)) + 93 | unsigned(audio_ch( 7)) + 94 | unsigned(audio_ch( 8)) + 95 | unsigned(audio_ch( 9)) + 96 | unsigned(audio_ch(10)) + 97 | unsigned(audio_ch(11)) + 98 | unsigned(audio_ch(12)) + 99 | unsigned(audio_ch(13)) + 100 | unsigned(audio_ch(14)) + 101 | unsigned(audio_ch(15)) 102 | ); 103 | 104 | AudioL <= pwmaudio; 105 | AudioR <= pwmaudio; 106 | 107 | process begin 108 | wait until rising_edge(clk); 109 | if(midi_new = '1') then 110 | note_on (to_integer(unsigned(midi_ch))) <= '1'; 111 | note_in (to_integer(unsigned(midi_ch))) <= midi_note; 112 | velocity(to_integer(unsigned(midi_ch))) <= midi_velo; 113 | volume (to_integer(unsigned(midi_ch))) <= "0010000"; 114 | else 115 | note_on (to_integer(unsigned(midi_ch))) <= '0'; 116 | end if; 117 | end process; 118 | 119 | --Led(0) <= not midi_in; 120 | Led(0) <= midi_new; 121 | Led(7 downto 1) <= "0000000"; 122 | midi_out <= not midi_in; 123 | end rtl; 124 | -------------------------------------------------------------------------------- /layout/synth_top_nexys3.ucf: -------------------------------------------------------------------------------- 1 | ## This file is a general .ucf for Nexys3 rev B board 2 | ## To use it in a project: 3 | ## - remove or comment the lines corresponding to unused pins 4 | ## - rename the used signals according to the project 5 | 6 | Net "clk" LOC=V10 | IOSTANDARD=LVCMOS33; 7 | Net "clk" TNM_NET = sys_clk_pin; 8 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; 9 | 10 | ## onBoard USB controller 11 | #Net "EppAstb" LOC = H1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA 12 | #Net "EppDstb" LOC = K4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB 13 | #Net "EppWait" LOC = C2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD 14 | #Net "EppDB<0>" LOC = E1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0 15 | #Net "EppDB<1>" LOC = F4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1 16 | #Net "EppDB<2>" LOC = F3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2 17 | #Net "EppDB<3>" LOC = D2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3 18 | #Net "EppDB<4>" LOC = D1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4 19 | #Net "EppDB<5>" LOC = H7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5 20 | #Net "EppDB<6>" LOC = G6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6 21 | #Net "EppDB<7>" LOC = E4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7 22 | 23 | #Net "UsbClk" LOC = H2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41P_GCLK27_M3DQ4, Sch name = U-IFCLK 24 | #Net "UsbDir" LOC = F6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55P_M3A13, Sch name = U-SLCS 25 | 26 | #Net "UsbWR" LOC = C1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83N_VREF, Sch name = U-SLWR 27 | #Net "UsbOE" LOC = H6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49P_M3A7, Sch name = U-SLOE 28 | 29 | #Net "UsbAdr<1>" LOC = E3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50P_M3WE, Sch name = U-FIFOAD1 30 | #Net "UsbAdr<0>" LOC = H5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49N_M3A2, Sch name = U-FIFOAD0 31 | 32 | #Net "UsbPktend" LOC = D3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54N_M3A11, Sch name = U-PKTEND 33 | 34 | #Net "UsbFlag" LOC = F5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC 35 | #Net "UsbMode" LOC = F1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48N_M3BA1, Sch name = U-INT0# 36 | 37 | ## onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash 38 | #Net "MemOE" LOC = L18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46N_FOE_B_M1DQ3, Sch name = P30-OE 39 | #Net "MemWR" LOC = M16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47P_FWE_B_M1DQ0, Sch name = P30-WE 40 | #Net "MemAdv" LOC = H18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43N_GCLK4_M1DQ5, Sch name = P30-ADV 41 | #Net "MemWait" LOC = V4 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63N, Sch name = P30-WAIT 42 | #Net "MemClk" LOC = R10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29P_GCLK3, Sch name = P30-CLK 43 | 44 | #Net "RamCS" LOC = L15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42P_GCLK7_M1UDM, Sch name = MT-CE 45 | #Net "RamCRE" LOC = M18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47N_LDC_M1DQ1, Sch name = MT-CRE 46 | #Net "RamUB" LOC = K15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = MT-UB 47 | #Net "RamLB" LOC = K16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41N_GCLK8_M1CASN, Sch name = MT-LB 48 | 49 | #Net "FlashCS" LOC = L17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46P_FCS_B_M1DQ2, Sch name = P30-CE 50 | #Net "FlashRp" LOC = T4 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63P, Sch name = P30-RST 51 | 52 | #Net "QuadSpiFlashCS" LOC = V3 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L65N_CSO_B_2, Sch name = CS 53 | #Net "QuadSpiFlashSck" LOC = R15 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L1P_CCLK_2, Sch name = SCK 54 | 55 | #Net "MemAdr<1>" LOC = K18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45N_A0_M1LDQSN, Sch name = P30-A0 56 | #Net "MemAdr<2>" LOC = K17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45P_A1_M1LDQS, Sch name = P30-A1 57 | #Net "MemAdr<3>" LOC = J18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44N_A2_M1DQ7, Sch name = P30-A2 58 | #Net "MemAdr<4>" LOC = J16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44P_A3_M1DQ6, Sch name = P30-A3 59 | #Net "MemAdr<5>" LOC = G18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38N_A4_M1CLKN, Sch name = P30-A4 60 | #Net "MemAdr<6>" LOC = G16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38P_A5_M1CLK, Sch name = P30-A5 61 | #Net "MemAdr<7>" LOC = H16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37N_A6_M1A1, Sch name = P30-A6 62 | #Net "MemAdr<8>" LOC = H15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37P_A7_M1A0, Sch name = P30-A7 63 | #Net "MemAdr<9>" LOC = H14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36N_A8_M1BA1, Sch name = P30-A8 64 | #Net "MemAdr<10>" LOC = H13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36P_A9_M1BA0, Sch name = P30-A9 65 | #Net "MemAdr<11>" LOC = F18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35N_A10_M1A2, Sch name = P30-A10 66 | #Net "MemAdr<12>" LOC = F17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35P_A11_M1A7, Sch name = P30-A11 67 | #Net "MemAdr<13>" LOC = K13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34N_A12_M1BA2, Sch name = P30-A12 68 | #Net "MemAdr<14>" LOC = K12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34P_A13_M1WE, Sch name = P30-A13 69 | #Net "MemAdr<15>" LOC = E18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33N_A14_M1A4, Sch name = P30-A14 70 | #Net "MemAdr<16>" LOC = E16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33P_A15_M1A10, Sch name = P30-A15 71 | #Net "MemAdr<17>" LOC = G13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32N_A16_M1A9, Sch name = P30-A16 72 | #Net "MemAdr<18>" LOC = H12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32P_A17_M1A8, Sch name = P30-A17 73 | #Net "MemAdr<19>" LOC = D18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31N_A18_M1A12, Sch name = P30-A18 74 | #Net "MemAdr<20>" LOC = D17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31P_A19_M1CKE, Sch name = P30-A19 75 | #Net "MemAdr<21>" LOC = G14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30N_A20_M1A11, Sch name = P30-A20 76 | #Net "MemAdr<22>" LOC = F14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30P_A21_M1RESET Sch name = P30-A21 77 | #Net "MemAdr<23>" LOC = C18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29N_A22_M1A14, Sch name = P30-A22 78 | #Net "MemAdr<24>" LOC = C17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29P_A23_M1A13, Sch name = P30-A23 79 | #Net "MemAdr<25>" LOC = F16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1N_A24_VREF, Sch name = P30-A24 80 | #Net "MemAdr<26>" LOC = F15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1P_A25, Sch name = P30-A25 81 | 82 | #Net "QuadSpiFlashDB<0>" LOC = T13 | IOSTANDARD = LVCMOS33; #Dual/Quad SPI Flash DB<0>, Bank = MISC, pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI 83 | #Net "MemDB<0>" LOC = R13 | IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<0>, or Dual/Quad SPI Flash DB<1>, Bank = MISC, pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = P30-DQ0 84 | #Net "MemDB<1>" LOC = T14 | IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<1>, or Quad SPI Flash DB<2>, Bank = MISC, pin name = IO_L12P_D1_MISO2_2, Sch name = P30-DQ1 85 | #Net "MemDB<2>" LOC = V14 | IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<2>, or Quad SPI Flash DB<3>, Bank = MISC, pin name = IO_L12N_D2_MISO3_2, Sch name = P30-DQ2 86 | #Net "MemDB<3>" LOC = U5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49P_D3, Sch name = P30-DQ3 87 | #Net "MemDB<4>" LOC = V5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49N_D4, Sch name = P30-DQ4 88 | #Net "MemDB<5>" LOC = R3 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62P_D5, Sch name = P30-DQ5 89 | #Net "MemDB<6>" LOC = T3 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62N_D6, Sch name = P30-DQ6 90 | #Net "MemDB<7>" LOC = R5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L48P_D7, Sch name = P30-DQ7 91 | #Net "MemDB<8>" LOC = N5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64P_D8, Sch name = P30-DQ8 92 | #Net "MemDB<9>" LOC = P6 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64N_D9, Sch name = P30-DQ9 93 | #Net "MemDB<10>" LOC = P12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L13N_D10, Sch name = P30-DQ10 94 | #Net "MemDB<11>" LOC = U13 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14P_D11, Sch name = P30-DQ11 95 | #Net "MemDB<12>" LOC = V13 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14N_D12, Sch name = P30-DQ12 96 | #Net "MemDB<13>" LOC = U10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L30P_GCLK1_D13, Sch name = P30-DQ13 97 | #Net "MemDB<14>" LOC = R8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31P_GCLK31_D14, Sch name = P30-DQ14 98 | #Net "MemDB<15>" LOC = T8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31N_GCLK30_D15, Sch name = P30-DQ15 99 | 100 | ## SMSC ethernet PHY 101 | #Net "PhyRstn" LOC = P3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2N, Sch name = ETH-RST 102 | #Net "PhyCrs" LOC = N3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L1N_VREF, Sch name = ETH-CRS 103 | #Net "PhyCol" LOC = P4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2P, Sch name = ETH-COL 104 | #Net "PhyClk25Mhz" LOC = N4 | IOSTANDARD = LVCMOS33; #Unconnected if R172 is not loaded, Bank = 3, pin name = IO_L1P, Sch name = ETH-CLK25MHZ 105 | 106 | #Net "PhyTxd<3>" LOC = T1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33N_M3DQ13, Sch name = ETH-TXD3 107 | #Net "PhyTxd<2>" LOC = T2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33P_M3DQ12, Sch name = ETH-TXD2 108 | #Net "PhyTxd<1>" LOC = U1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32N_M3DQ15, Sch name = ETH-TXD1 109 | #Net "PhyTxd<0>" LOC = U2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32P_M3DQ14, Sch name = ETH-TXD0 110 | #Net "PhyTxEn" LOC = L2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37P_M3DQ0, Sch name = ETH-TX_EN 111 | #Net "PhyTxClk" LOC = L5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43P_GCLK23_M3RASN, Sch name = ETH-TX_CLK 112 | #Net "PhyTxEr" LOC = P2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34P_M3UDQS, Sch name = ETH-TXD4 113 | 114 | #Net "PhyRxd<3>" LOC = M3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36P_M3DQ8, Sch name = ETH-RXD3 115 | #Net "PhyRxd<2>" LOC = N1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35N_M3DQ11, Sch name = ETH-RXD2 116 | #Net "PhyRxd<1>" LOC = N2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35P_M3DQ10, Sch name = ETH-RXD1 117 | #Net "PhyRxd<0>" LOC = P1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34N_M3UDQSN, Sch name = ETH-RXD0 118 | #Net "PhyRxDv" LOC = L1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37N_M3DQ1, Sch name = ETH-RX_DV 119 | #Net "PhyRxEr" LOC = M1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36N_M3DQ9, Sch name = ETH-RXD4 120 | #Net "PhyRxClk" LOC = H4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44P_GCLK21_M3A5, Sch name = ETH-RX_CLK 121 | 122 | #Net "PhyMdc" LOC = M5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31N_VREF, Sch name = ETH-MDC 123 | #Net "PhyMdio" LOC = L6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31P, Sch name = ETH-MDIO 124 | 125 | ## Pic USB-HID interface 126 | #Net "PS2KeyboardData" LOC = J13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39P_M1A3, Sch name = PIC-SDI1 127 | #Net "PS2KeyboardClk" LOC = L12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5, Sch name = PIC-SCK1 128 | 129 | #NET "PS2MouseData" LOC = K14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39N_M1ODT, Sch name = PIC-SDO1 130 | #NET "PS2MouseClk" LOC = L13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6, Sch name = PIC-SS1 131 | 132 | #Net "PicGpio<0>" LOC = L16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = PIC-GPIO0 133 | #NET "PicGpio<1>" LOC = H17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43P_GCLK5_M1DQ4, Sch name = PIC-GPIO1 134 | 135 | ## Usb-RS232 interface 136 | #Net "RxD" LOC = N17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX 137 | #Net "TxD" LOC = N18 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48N_M1DQ9, Sch name = MCU-TX 138 | 139 | ## 7 segment display 140 | #Net "seg<0>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA 141 | #Net "seg<1>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB 142 | #Net "seg<2>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC 143 | #Net "seg<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD 144 | #Net "seg<4>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE 145 | #Net "seg<5>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF 146 | #Net "seg<6>" LOC = L14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG 147 | #Net "seg<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP 148 | 149 | #Net "an<0>" LOC = N16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0 150 | #Net "an<1>" LOC = N15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1 151 | #Net "an<2>" LOC = P18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2 152 | #Net "an<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3 153 | 154 | ## Leds 155 | Net "Led<0>" LOC = U16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0 156 | Net "Led<1>" LOC = V16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1 157 | Net "Led<2>" LOC = U15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2 158 | Net "Led<3>" LOC = V15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5N, Sch name = LD3 159 | Net "Led<4>" LOC = M11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15P, Sch name = LD4 160 | Net "Led<5>" LOC = N11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15N, Sch name = LD5 161 | Net "Led<6>" LOC = R11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16P, Sch name = LD6 162 | Net "Led<7>" LOC = T11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16N_VREF, Sch name = LD7 163 | 164 | ## Switches 165 | Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0 166 | Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1 167 | Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2 168 | Net "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3 169 | Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4 170 | Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5 171 | Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6 172 | Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7 173 | 174 | ## Buttons 175 | #Net "btns" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS 176 | #Net "btnu" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU 177 | #Net "btnl" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL 178 | #Net "btnd" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND 179 | #Net "btnr" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR 180 | 181 | ## VGA Connector 182 | #NET vgaRed<0> LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0 183 | #NET vgaRed<1> LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED1 184 | #NET vgaRed<2> LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2 185 | #NET vgaGreen<0> LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN0 186 | #NET vgaGreen<1> LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN1 187 | #NET vgaGreen<2> LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2 188 | #NET vgaBlue<1> LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1 189 | #NET vgaBlue<2> LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU2 190 | 191 | #NET "Hsync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC 192 | #NET "Vsync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC 193 | 194 | ## 12 pin connectors 195 | 196 | ##JA 197 | Net "Midi_in" LOC = F12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19P, Sch name = JA1 198 | Net "Midi_out" LOC = E12 | IOSTANDARD = LVCMOS33; 199 | NET "midi_in" CLOCK_DEDICATED_ROUTE = FALSE; 200 | Net "AudioL" LOC = F11 | IOSTANDARD = LVCMOS33; 201 | Net "AudioR" LOC = E11 | IOSTANDARD = LVCMOS33; 202 | #Net "JA<1>" LOC = V12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19N, Sch name = JA2 203 | #Net "JA<2>" LOC = N10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20P, Sch name = JA3 204 | #Net "JA<3>" LOC = P11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20N, Sch name = JA4 205 | #Net "JA<4>" LOC = M10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22P, Sch name = JA7 206 | #Net "JA<5>" LOC = N9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22N, Sch name = JA8 207 | #Net "JA<6>" LOC = U11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23P, Sch name = JA9 208 | #Net "JA<7>" LOC = V11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23N, Sch name = JA10 209 | 210 | ##JB 211 | #Net "JB<0>" LOC = K2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38P_M3DQ2, Sch name = JB1 212 | #Net "JB<1>" LOC = K1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38N_M3DQ3, Sch name = JB2 213 | #Net "JB<2>" LOC = L4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39P_M3LDQS, Sch name = JB3 214 | #Net "JB<3>" LOC = L3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39N_M3LDQSN, Sch name = JB4 215 | #Net "JB<4>" LOC = J3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P_M3DQ6, Sch name = JB7 216 | #Net "JB<5>" LOC = J1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N_M3DQ7, Sch name = JB8 217 | #Net "JB<6>" LOC = K3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N_GCLK24_M3LDM, Sch name = JB9 218 | #Net "JB<7>" LOC = K5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = JB10 219 | 220 | ##JC 221 | #Net "JC<0>" LOC = H3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44N_GCLK20_M3A6, Sch name = JC1 222 | #Net "JC<1>" LOC = L7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45P_M3A3, Sch name = JC2 223 | #Net "JC<2>" LOC = K6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45N_M3ODT, Sch name = JC3 224 | #Net "JC<3>" LOC = G3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46P_M3CLK, Sch name = JC4 225 | #Net "JC<4>" LOC = G1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46N_M3CLKN, Sch name = JC7 226 | #Net "JC<5>" LOC = J7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P_M3A0, Sch name = JC8 227 | #Net "JC<6>" LOC = J6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N_M3A1, Sch name = JC9 228 | #Net "JC<7>" LOC = F2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48P_M3BA0, Sch name = JC10 229 | #Net "DacData" LOC = G1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46N_M3CLKN, Sch name = JC7 230 | #Net "SClk" LOC = J7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P_M3A0, Sch name = JC8 231 | #Net "LRClk" LOC = J6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N_M3A1, Sch name = JC9 232 | #Net "MClk" LOC = F2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48P_M3BA0, Sch name = JC10 233 | 234 | ##JD, LX16 Die only 235 | #Net "JD<0>" LOC = G11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P, Sch name = JD1 236 | #Net "JD<1>" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N, Sch name = JD2 237 | #Net "JD<2>" LOC = F11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P, Sch name = JD3 238 | #Net "JD<3>" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N, Sch name = JD4 239 | #Net "SS" LOC = D12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P, Sch name = JD7 240 | #Net "JD<5>" LOC = C12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N, Sch name = JD8 241 | #Net "MISO" LOC = F12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P, Sch name = JD9 242 | #Net "SCK" LOC = E12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N, Sch name = JD10 243 | 244 | ## VHDCI Connector 245 | #Net "EXP-IO_P<0>" LOC = B2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2P, Sch name = EXP_IO1_P 246 | #Net "EXP-IO_N<0>" LOC = A2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2N, Sch name = EXP_IO1_N 247 | #Net "EXP-IO_P<1>" LOC = D6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3P, Sch name = EXP_IO2_P 248 | #Net "EXP-IO_N<1>" LOC = C6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3N, Sch name = EXP_IO2_N 249 | #Net "EXP-IO_P<2>" LOC = B3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4P, Sch name = EXP_IO3_P 250 | #Net "EXP-IO_N<2>" LOC = A3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4N, Sch name = EXP_IO3_N 251 | #Net "EXP-IO_P<3>" LOC = B4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5P, Sch name = EXP_IO4_P 252 | #Net "EXP-IO_N<3>" LOC = A4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5N, Sch name = EXP_IO4_N 253 | #Net "EXP-IO_P<4>" LOC = C5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6P, Sch name = EXP_IO5_P 254 | #Net "EXP-IO_N<4>" LOC = A5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6N, Sch name = EXP_IO5_N 255 | #Net "EXP-IO_P<5>" LOC = B6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8P, Sch name = EXP_IO6_P 256 | #Net "EXP-IO_N<5>" LOC = A6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8N_VREF, Sch name = EXP_IO6_N 257 | #Net "EXP-IO_P<6>" LOC = C7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10P, Sch name = EXP_IO7_P 258 | #Net "EXP-IO_N<6>" LOC = A7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10N, Sch name = EXP_IO7_N 259 | #Net "EXP-IO_P<7>" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11P, Sch name = EXP_IO8_P 260 | #Net "EXP-IO_N<7>" LOC = C8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11N, Sch name = EXP_IO8_N 261 | #Net "EXP-IO_P<8>" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35P_GCLK17, Sch name = EXP_IO9_P 262 | #Net "EXP-IO_N<8>" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35N_GCLK16, Sch name = EXP_IO9_N 263 | #Net "EXP-IO_P<9>" LOC = D11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36P_GCLK15, Sch name = EXP_IO10_P 264 | #Net "EXP-IO_N<9>" LOC = C11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36N_GCLK14, Sch name = EXP_IO10_N 265 | #Net "EXP-IO_P<10>" LOC = C10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37P_GCLK13, Sch name = EXP_IO11_P 266 | #Net "EXP-IO_N<10>" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37N_GCLK12, Sch name = EXP_IO11_N 267 | #Net "EXP-IO_P<11>" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38P, Sch name = EXP_IO12_P 268 | #Net "EXP-IO_N<11>" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38N_VREF, Sch name = EXP_IO12_N 269 | #Net "EXP-IO_P<12>" LOC = B11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39P, Sch name = EXP_IO13_P 270 | #Net "EXP-IO_N<12>" LOC = A11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39N, Sch name = EXP_IO13_N 271 | #Net "EXP-IO_P<13>" LOC = B12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41P, Sch name = EXP_IO14_P 272 | #Net "EXP-IO_N<13>" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41N, Sch name = EXP_IO14_N 273 | #Net "EXP-IO_P<14>" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50P, Sch name = EXP_IO15_P 274 | #Net "EXP-IO_N<14>" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50N, Sch name = EXP_IO15_N 275 | #Net "EXP-IO_P<15>" LOC = B14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62P, Sch name = EXP_IO16_P 276 | #Net "EXP-IO_N<15>" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62N_VREF, Sch name = EXP_IO16_N 277 | #Net "EXP-IO_P<16>" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63P_SCP7, Sch name = EXP_IO17_P 278 | #Net "EXP-IO_N<16>" LOC = E13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63N_SCP6, Sch name = EXP_IO17_N 279 | #Net "EXP-IO_P<17>" LOC = C15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64P_SCP5, Sch name = EXP_IO18_P 280 | #Net "EXP-IO_N<17>" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64N_SCP4, Sch name = EXP_IO18_N 281 | #Net "EXP-IO_P<18>" LOC = D14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65P_SCP3, Sch name = EXP_IO19_P 282 | #Net "EXP-IO_N<18>" LOC = C14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65N_SCP2, Sch name = EXP_IO19_N 283 | #Net "EXP-IO_P<19>" LOC = B16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66P_SCP1, Sch name = EXP_IO20_P 284 | #Net "EXP-IO_N<19>" LOC = A16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66N_SCP0, Sch name = EXP_IO20_N 285 | --------------------------------------------------------------------------------