├── .gitmodules ├── README.md ├── thinpad_top.srcs ├── sim_1 │ ├── new │ │ ├── clock.v │ │ ├── flag_sync_cpld.v │ │ ├── include │ │ │ ├── UserData.h │ │ │ ├── def.h │ │ │ ├── CUIcommandData.h │ │ │ ├── data.h │ │ │ ├── BankLib.h │ │ │ └── TimingData.h │ │ ├── cpld_model.v │ │ ├── tb.sv │ │ └── sram_model.v │ └── imports │ │ ├── CFImemory64Mb_top.mem │ │ └── CFImemory64Mb_bottom.mem ├── sources_1 │ ├── new │ │ ├── SEG7_LUT.v │ │ ├── vga.v │ │ ├── thinpad_top.v │ │ └── async.v │ └── ip │ │ └── pll_example │ │ └── pll_example.xci └── constrs_1 │ └── new │ └── thinpad_top.xdc ├── .gitlab-ci.yml └── thinpad_top.xpr /.gitmodules: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Thinpad 模板工程 2 | --------------- 3 | 4 | 工程包含示例代码和所有引脚约束，可以直接编译。 5 | 6 | 代码中包含中文注释，编码为utf-8，在Windows版Vivado下可能出现乱码问题。 7 | 请用别的代码编辑器打开文件，并将编码改为GBK。 8 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/clock.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | 3 | module clock ( 4 | output clk_50M, 5 | output clk_11M0592 6 | ); 7 | 8 | reg clk_50M = 0, clk_11M0592 = 0; 9 | 10 | always #(90422/2) clk_11M0592 = ~clk_11M0592; 11 | always #(20000/2) clk_50M = ~clk_50M; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | variables: 2 | GIT_SUBMODULE_STRATEGY: recursive 3 | 4 | stages: 5 | - build 6 | - test 7 | 8 | bitstream: 9 | stage: build 10 | image: vivado2018:2018.3 11 | script: 12 | - env 13 | - /opt/Xilinx/Vivado/2018.3/bin/vivado -mode tcl -source build.tcl thinpad_top.xpr 14 | 15 | artifacts: 16 | paths: 17 | - thinpad_top.runs/impl_1/thinpad_top.bit 18 | - thinpad_top.runs/impl_1/runme.log 19 | - thinpad_top.runs/synth_1/runme.log 20 | 21 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/new/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT ( oSEG1,iDIG ); 2 | input wire[3:0] iDIG; 3 | output wire[7:0] oSEG1; 4 | reg [6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: oSEG = 7'b1110110; // ---t---- 10 | 4'h2: oSEG = 7'b0100001; // | | 11 | 4'h3: oSEG = 7'b0100100; // lt rt 12 | 4'h4: oSEG = 7'b0010110; // | | 13 | 4'h5: oSEG = 7'b0001100; // ---m---- 14 | 4'h6: oSEG = 7'b0001000; // | | 15 | 4'h7: oSEG = 7'b1100110; // lb rb 16 | 4'h8: oSEG = 7'b0000000; // | | 17 | 4'h9: oSEG = 7'b0000110; // ---b---- 18 | 4'ha: oSEG = 7'b0000010; 19 | 4'hb: oSEG = 7'b0011000; 20 | 4'hc: oSEG = 7'b1001001; 21 | 4'hd: oSEG = 7'b0110000; 22 | 4'he: oSEG = 7'b0001001; 23 | 4'hf: oSEG = 7'b0001011; 24 | 4'h0: oSEG = 7'b1000000; 25 | endcase 26 | end 27 | 28 | assign oSEG1 = {~oSEG,1'b0}; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/flag_sync_cpld.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module flag_sync_cpld(/*autoport*/ 3 | //output 4 | FlagOut_clkB, 5 | //input 6 | a_rst_n, 7 | b_rst_n, 8 | clkA, 9 | FlagIn_clkA, 10 | clkB); 11 | 12 | input wire a_rst_n; 13 | input wire b_rst_n; 14 | input wire clkA; 15 | input wire FlagIn_clkA; 16 | input wire clkB; 17 | output wire FlagOut_clkB; 18 | 19 | // this changes level when the FlagIn_clkA is seen in clkA 20 | reg FlagToggle_clkA; 21 | always @(posedge clkA or negedge a_rst_n) 22 | begin 23 | if(!a_rst_n) 24 | FlagToggle_clkA <= 1'b0; 25 | else 26 | FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA; 27 | end 28 | 29 | // which can then be sync-ed to clkB 30 | reg [2:0] SyncA_clkB; 31 | always @(posedge clkB or negedge b_rst_n) 32 | begin 33 | if(!b_rst_n) 34 | SyncA_clkB <= 3'b0; 35 | else 36 | SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA}; 37 | end 38 | 39 | // and recreate the flag in clkB 40 | assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]); 41 | /* 42 | 43 | always #20 clkA = ~clkA; 44 | always #3 clkB = ~clkB; 45 | initial begin 46 | clkB=0; 47 | clkA=0; 48 | FlagToggle_clkA=0; 49 | SyncA_clkB=0; 50 | FlagIn_clkA=0; 51 | @(negedge clkA); 52 | FlagIn_clkA=1; 53 | @(negedge clkA); 54 | FlagIn_clkA=0; 55 | 56 | repeat(5) 57 | @(negedge clkA); 58 | FlagIn_clkA=1; 59 | @(negedge clkA); 60 | FlagIn_clkA=0; 61 | end 62 | 63 | */ 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/new/vga.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // 3 | // WIDTH: bits in register hdata & vdata 4 | // HSIZE: horizontal size of visible field 5 | // HFP: horizontal front of pulse 6 | // HSP: horizontal stop of pulse 7 | // HMAX: horizontal max size of value 8 | // VSIZE: vertical size of visible field 9 | // VFP: vertical front of pulse 10 | // VSP: vertical stop of pulse 11 | // VMAX: vertical max size of value 12 | // HSPP: horizontal synchro pulse polarity (0 - negative, 1 - positive) 13 | // VSPP: vertical synchro pulse polarity (0 - negative, 1 - positive) 14 | // 15 | module vga 16 | #(parameter WIDTH = 0, HSIZE = 0, HFP = 0, HSP = 0, HMAX = 0, VSIZE = 0, VFP = 0, VSP = 0, VMAX = 0, HSPP = 0, VSPP = 0) 17 | ( 18 | input wire clk, 19 | output wire hsync, 20 | output wire vsync, 21 | output reg [WIDTH - 1:0] hdata, 22 | output reg [WIDTH - 1:0] vdata, 23 | output wire data_enable 24 | ); 25 | 26 | // init 27 | initial begin 28 | hdata <= 0; 29 | vdata <= 0; 30 | end 31 | 32 | // hdata 33 | always @ (posedge clk) 34 | begin 35 | if (hdata == (HMAX - 1)) 36 | hdata <= 0; 37 | else 38 | hdata <= hdata + 1; 39 | end 40 | 41 | // vdata 42 | always @ (posedge clk) 43 | begin 44 | if (hdata == (HMAX - 1)) 45 | begin 46 | if (vdata == (VMAX - 1)) 47 | vdata <= 0; 48 | else 49 | vdata <= vdata + 1; 50 | end 51 | end 52 | 53 | // hsync & vsync & blank 54 | assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP; 55 | assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP; 56 | assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE)); 57 | 58 | endmodule -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/include/UserData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // ************************************ 23 | // 24 | // User Data definition file : 25 | // 26 | // here are defined all parameters 27 | // that the user can change 28 | // 29 | // ************************************ 30 | 31 | //`define x128P30T // Select the device. Possible value are: x128P30B, x128P30T 32 | `define x64P30T // x64P30B, x64P30T 33 | 34 | 35 | //!`define organization "top" // top or bottom 36 | `define BLOCKPROTECT "on" // if on the blocks are locked at power-up 37 | `define TimingChecks "on" // on for checking timing constraints 38 | `define t_access 65 // Access Time 65 ns, 75 ns 39 | `define FILENAME_mem "flash_content.mem" // Memory File Name 40 | 41 | 42 | 43 | 44 | `ifdef x128P30B 45 | `define organization "bottom" 46 | `elsif x128P30T 47 | `define organization "top" // top, bottom 48 | `elsif x64P30B 49 | `define organization "bottom" 50 | `elsif x64P30T 51 | `define organization "top" 52 | `else 53 | `define organization "bottom" 54 | `endif 55 | 56 | 57 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/include/def.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // ***************************************** 23 | // Glogal Definition for Device : M58WR128F 24 | // ***************************************** 25 | 26 | // TimeScale Directive 27 | `timescale 1 ns / 1 ns 28 | 29 | `define HIGH 1'b1 30 | `define LOW 1'b0 31 | `define Z 1'bZ 32 | `define X 1'bX 33 | `define FALSE 1'b0 34 | `define TRUE 1'b1 35 | `define UNLOCK 1'b0 // Unlocked Block Lock Status 36 | `define LOCK 1'b1 // Locked Block Lock Status 37 | `define UNLOCKDOWN 1'b0 // UnLocked-down Status 38 | `define LOCKDOWN 1'b1 // Locked-down Status 39 | `define BUSY 1'b0 40 | `define READY 1'b1 41 | `define BYTE_range 7:0 42 | `define WORD_range 15:0 43 | `define LOW_range 7:0 44 | `define HIGH_range 15:8 45 | `define WORDNP 16'hFFFF // Memory not programmed 46 | `define Kbyte 1024 47 | `define Kword 1024 48 | `define INTEGER 15:0 49 | 50 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/cpld_model.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module cpld_model( 3 | input wire clk_uart, //内部串口时钟 4 | input wire uart_rdn, //读串口信号，低有效 5 | input wire uart_wrn, //写串口信号，低有效 6 | output reg uart_dataready, //串口数据准备好 7 | output reg uart_tbre, //发送数据标志 8 | output reg uart_tsre, //数据发送完毕标志 9 | inout wire [7:0]data 10 | ); 11 | reg bus_analyze_clk = 0; 12 | reg clk_out2_rst_n = 0, bus_analyze_clk_rst_n = 0; 13 | wire clk_out2; 14 | 15 | reg [7:0] TxD_data,TxD_data0,TxD_data1; 16 | reg [2:0] cpld_emu_wrn_sync; 17 | reg [2:0] cpld_emu_rdn_sync; 18 | reg [7:0] uart_rx_data; 19 | wire uart_rx_flag; 20 | reg wrn_rise; 21 | 22 | assign data = uart_rdn ? 8'bz : uart_rx_data; 23 | assign #3 clk_out2 = clk_uart; 24 | 25 | initial begin 26 | uart_tsre = 1; 27 | uart_tbre = 1; 28 | uart_dataready = 0; 29 | repeat(2) @(negedge clk_out2); 30 | clk_out2_rst_n = 1; 31 | @(negedge bus_analyze_clk); 32 | bus_analyze_clk_rst_n = 1; 33 | end 34 | 35 | always #2 bus_analyze_clk = ~bus_analyze_clk; 36 | 37 | always @(posedge bus_analyze_clk) begin : proc_Tx 38 | TxD_data0 <= data[7:0]; 39 | TxD_data1 <= TxD_data0; 40 | 41 | cpld_emu_rdn_sync <= {cpld_emu_rdn_sync[1:0],uart_rdn}; 42 | cpld_emu_wrn_sync <= {cpld_emu_wrn_sync[1:0],uart_wrn}; 43 | 44 | if(~cpld_emu_wrn_sync[1] & cpld_emu_wrn_sync[2]) 45 | TxD_data <= TxD_data1; 46 | wrn_rise <= cpld_emu_wrn_sync[1] & ~cpld_emu_wrn_sync[2]; 47 | 48 | if(~cpld_emu_rdn_sync[1] & cpld_emu_rdn_sync[2]) //rdn_fall 49 | uart_dataready <= 1'b0; 50 | else if(uart_rx_flag) 51 | uart_dataready <= 1'b1; 52 | end 53 | 54 | reg [7:0] TxD_data_sync; 55 | wire tx_en; 56 | reg rx_ack = 0; 57 | 58 | always @(posedge clk_out2) begin 59 | TxD_data_sync <= TxD_data; 60 | end 61 | 62 | always @(posedge clk_out2 or negedge uart_wrn) begin : proc_tbre 63 | if(~uart_wrn) begin 64 | uart_tbre <= 0; 65 | end else if(!uart_tsre) begin 66 | uart_tbre <= 1; 67 | end 68 | end 69 | 70 | flag_sync_cpld tx_flag( 71 | .clkA (bus_analyze_clk), 72 | .clkB (clk_out2), 73 | .FlagIn_clkA (wrn_rise), 74 | .FlagOut_clkB(tx_en), 75 | .a_rst_n (bus_analyze_clk_rst_n), 76 | .b_rst_n (clk_out2_rst_n) 77 | ); 78 | 79 | flag_sync_cpld rx_flag( 80 | .clkA (clk_out2), 81 | .clkB (bus_analyze_clk), 82 | .FlagIn_clkA (rx_ack), 83 | .FlagOut_clkB(uart_rx_flag), 84 | .a_rst_n (bus_analyze_clk_rst_n), 85 | .b_rst_n (clk_out2_rst_n) 86 | ); 87 | 88 | always begin 89 | wait(tx_en == 1); 90 | repeat(2) 91 | @(posedge clk_out2); 92 | uart_tsre = 0; 93 | #10000 // 实际串口发送时间更长，为了加快仿真，等待时间较短 94 | $display("send: 0x%02x", TxD_data_sync); 95 | uart_tsre = 1; 96 | end 97 | 98 | task pc_send_byte; 99 | input [7:0] arg; 100 | begin 101 | uart_rx_data = arg; 102 | @(negedge clk_out2); 103 | rx_ack = 1; 104 | @(negedge clk_out2); 105 | rx_ack = 0; 106 | end 107 | endtask 108 | endmodule -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/include/CUIcommandData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // ********************** 23 | // 24 | // COMMAND USER INTERFACE 25 | // 26 | // ********************** 27 | 28 | // Read Commands 29 | 30 | `define RD_cmd 8'hFF // Read Memory Array 31 | `define RSR_cmd 8'h70 // Read Status Register 32 | `define RSIG_cmd 8'h90 // Read Electronic Signature 33 | `define RCFI_cmd 8'h98 // Read CFI 34 | 35 | 36 | // Program/Erase Commands 37 | 38 | `define PG_cmd 8'h40 // Program 39 | `define PES_cmd 8'hB0 // Program/Erase Suspend 40 | `define PER_cmd 8'hD0 // Program/Erase Resume 41 | `define BLKEE_cmd 8'h20 // Block Erase 42 | `define BLKEEconfirm_cmd 8'hD0 // Block Erase Confirm 43 | `define CLRSR_cmd 8'h50 // Clear Status Register 44 | `define PRREG_cmd 8'hC0 // Protection Register Program //verificare se va bene x OTP register program setup 45 | 46 | 47 | // Protect Commands 48 | 49 | `define BL_cmd 8'h60 // Block Lock //setup?? 50 | `define BUL_cmd 8'h60 // Block UnLock 51 | `define BLD_cmd 8'h60 // Block lock-down 52 | `define BLDconfirm_cmd 8'h2F // Block Lock-down confirm 53 | `define BLconfirm_cmd 8'h01 // Block Lock Confirm 54 | `define BULconfirm_cmd 8'hD0 // Block unLock Confirm 55 | 56 | 57 | // Additional Features Commands 58 | 59 | `define PB_cmd 8'hE8 // Program Buffer 60 | `define PBcfm_cmd 8'hD0 // Close Sequence of Program Buffer Command 61 | 62 | 63 | // Configuration Register 64 | 65 | `define SCR_cmd 8'h60 // Set Configuration Register 66 | `define SCRconfirm_cmd 8'h03 // Set Configuration Register confirm 67 | 68 | // Additional Features Commands //aggiunto 69 | `define BLNKCHK_cmd 8'hBC // Blank Check Command 70 | `define BLNKCHKconfirm_cmd 8'hD0 // Blank Check Confirm 71 | 72 | 73 | // Factory Program Commands 74 | `define BuffEnhProgram_cmd 8'h80 // Enhanced Setup Command 75 | `define BuffEnhProgramCfrm_cmd 8'hD0 // Enhanced Setup confirm 76 | 77 | `define EnhSetup_cmd 8'h80 // Enhanced Setup Command 78 | `define EnhSetup_cfrm 8'hD0 // Enhanced Setup confirm 79 | 80 | 81 | // CUI Status 82 | 83 | // Read Bus Status Operation 84 | 85 | `define ReadArray_bus 2'b00 // Read Memory Array 86 | `define ReadSignature_bus 2'b01 // Read Electronic Signature 87 | `define ReadStatusReg_bus 2'b10 // Read Status Register 88 | `define ReadCFI_bus 2'b11 // Read CFI 89 | 90 | 91 | // Program/Erase Controller Status 92 | 93 | `define Free_pes 0 // No Operation 94 | `define Program_pes 1 // Programming 95 | `define BlockErase_pes 2 // Erasing Block 96 | `define ChipErase_pes 3 // Chip Erasing 97 | `define BlockEraseSuspend_pes 4 // Block Erase Suspend 98 | `define ProgramEraseSuspend_pes 5 // Program/Erase Resume 99 | `define ProgramEraseWait_pes 6 // Program/Erase Wait 100 | `define Reset_pes 10 // Reset status 101 | 102 | 103 | 104 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/imports/CFImemory64Mb_top.mem: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | @00010 22 | 23 | 0101_0001 24 | 25 | 0101_0010 26 | 27 | 0101_1001 28 | 29 | @00013 30 | 31 | 0000_0001 32 | 33 | 0000_0000 34 | 35 | @00015 36 | 37 | 0000_1010 38 | 39 | 0000_0001 40 | 41 | @00017 42 | 43 | 0000_0000 44 | 45 | 0000_0000 46 | 47 | @00019 48 | 49 | 0000_0000 50 | 51 | 52 | @0001A 53 | 54 | 0000_0000 55 | 56 | @0001B 57 | 0001_0111 58 | 59 | @0001C 60 | 0010_0000 61 | 62 | @0001D 63 | 64 | 1000_0101 65 | 66 | @0001E 67 | 1001_0101 68 | 69 | @0001F 70 | 0000_0110 71 | 72 | @00020 73 | 74 | 0000_1000 75 | 76 | @00021 77 | 0000_1001 78 | 79 | @00022 80 | 0000_0000 81 | 82 | @00023 83 | 0000_0010 84 | 85 | 86 | 87 | @00024 88 | 0000_0011 89 | 90 | @00025 91 | 0000_0011 92 | 93 | @00026 94 | 0000_0000 95 | 96 | @00027 97 | 0001_1000 //top 98 | 99 | @00028 100 | 0000_0001 101 | 102 | @00029 103 | 0000_0000 104 | 105 | @0002A 106 | 0000_1001 107 | 108 | @0002B 109 | 0000_0000 110 | 111 | @0002C 112 | 0000_0010 113 | 114 | @0002D 115 | 0111_1110 //top 116 | 117 | @0002E 118 | 0000_0000 119 | 120 | @0002F 121 | 0000_0000 //top 122 | 123 | @00030 124 | 0000_0010 //top 125 | 126 | @00031 127 | 0000_0011 //top 128 | 129 | @00032 130 | 0000_0000 131 | 132 | @00033 133 | 1000_0000 //top 134 | 135 | @00034 136 | 0000_0000 //top 137 | 138 | @00035 139 | 0000_0000 140 | 141 | @00036 142 | 0000_0000 143 | 144 | @00037 145 | 0000_0000 146 | 147 | @00038 148 | 0000_0000 149 | 150 | @0010A 151 | 0101_0000 152 | 153 | @0010B 154 | 0101_0010 155 | 156 | @0010C 157 | 0100_1001 158 | 159 | @0010D 160 | 0011_0001 161 | 162 | @0010E 163 | 0011_0101 164 | 165 | @0010F 166 | 1110_0110 167 | 168 | @00110 169 | 0000_0001 170 | 171 | @00111 172 | 0000_0000 173 | 174 | @00112 175 | 0000_0000 176 | 177 | @00113 178 | 0000_0001 179 | 180 | @00114 181 | 0000_0011 182 | 183 | @00115 184 | 0000_0000 185 | 186 | @00116 187 | 0001_1000 188 | 189 | @00117 190 | 1001_0000 191 | 192 | @00118 193 | 0000_0010 194 | 195 | @00119 196 | 1000_0000 197 | 198 | @0011A 199 | 0000_0000 200 | 201 | @0011B 202 | 0000_0011 203 | 204 | @0011C 205 | 0000_0011 206 | 207 | @0011D 208 | 1000_1001 209 | 210 | @0011E 211 | 0000_0000 212 | 213 | @0011F 214 | 0000_0000 215 | 216 | @00120 217 | 0000_0000 218 | 219 | @00121 220 | 0000_0000 221 | 222 | @00122 223 | 0000_0000 224 | 225 | @00123 226 | 0000_0000 227 | 228 | @00124 229 | 0001_0000 230 | 231 | @00125 232 | 0000_0000 233 | 234 | @00126 235 | 0000_0100 236 | 237 | @00127 238 | 0000_0100 239 | 240 | @00128 241 | 0000_0100 242 | 243 | @00129 244 | 0000_0001 245 | 246 | @0012A 247 | 0000_0010 248 | 249 | @0012B 250 | 0000_0011 251 | 252 | @0012C 253 | 0000_0111 254 | 255 | @0012D 256 | 0000_0001 257 | 258 | @0012E 259 | 0010_0100 260 | 261 | @0012F 262 | 0000_0000 263 | 264 | @00130 265 | 0000_0001 266 | 267 | @00131 268 | 0000_0000 269 | 270 | @00132 271 | 0001_0001 272 | 273 | @00133 274 | 0000_0000 275 | 276 | @00134 277 | 0000_0000 278 | 279 | @00135 280 | 0000_0010 281 | 282 | @00136 283 | 0111_1110 //top 284 | 285 | @00137 286 | 0000_0000 287 | 288 | @00138 289 | 0000_0000 //top 290 | 291 | @00139 292 | 0000_0010 //top 293 | 294 | @0013A 295 | 0110_0100 296 | 297 | @0013B 298 | 0000_0000 299 | 300 | @0013C 301 | 0000_0010 302 | 303 | @0013D 304 | 0000_0011 305 | 306 | @0013E 307 | 0000_0000 308 | 309 | @0013F 310 | 1000_0000 311 | 312 | @00140 313 | 0000_0000 314 | 315 | @00141 316 | 0000_0000 317 | 318 | @00142 319 | 0000_0000 320 | 321 | @00143 322 | 1000_0000 323 | 324 | @00144 325 | 0000_0011 //top 326 | 327 | @00145 328 | 0000_0000 329 | 330 | @00146 331 | 1000_0000 //top 332 | 333 | @00147 334 | 0000_0000 //top 335 | 336 | @00148 337 | 0110_0100 338 | 339 | @00149 340 | 0000_0000 341 | 342 | @0014A 343 | 0000_0010 344 | 345 | @0014B 346 | 0000_0011 347 | 348 | @0014C 349 | 0000_0000 350 | 351 | @0014D 352 | 1000_0000 353 | 354 | @0014E 355 | 0000_0000 356 | 357 | @0014F 358 | 0000_0000 359 | 360 | @00150 361 | 0000_0000 362 | 363 | @00151 364 | 1000_0000 365 | 366 | @00152 367 | 1111_1111 368 | 369 | @00153 370 | 1111_1111 371 | 372 | @00154 373 | 1111_1111 374 | 375 | @00155 376 | 1111_1111 377 | 378 | @00156 379 | 1111_1111 380 | 381 | 382 | 383 | 384 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/imports/CFImemory64Mb_bottom.mem: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | @00010 22 | 23 | 0101_0001 24 | 25 | 0101_0010 26 | 27 | 0101_1001 28 | 29 | @00013 30 | 31 | 0000_0001 32 | 33 | 0000_0000 34 | 35 | @00015 36 | 37 | 0000_1010 38 | 39 | 0000_0001 40 | 41 | @00017 42 | 43 | 0000_0000 44 | 45 | 0000_0000 46 | 47 | @00019 48 | 49 | 0000_0000 50 | 51 | 52 | @0001A 53 | 54 | 0000_0000 55 | 56 | 57 | @0001B 58 | 0001_0111 59 | 60 | @0001C 61 | 0010_0000 62 | 63 | @0001D 64 | 65 | 1000_0101 66 | 67 | @0001E 68 | 1001_0101 69 | 70 | @0001F 71 | 0000_0110 72 | 73 | @00020 74 | 75 | 0000_1000 76 | 77 | @00021 78 | 0000_1001 79 | 80 | @00022 81 | 0000_0000 82 | 83 | @00023 84 | 0000_0010 85 | 86 | 87 | 88 | @00024 89 | 0000_0011 90 | 91 | @00025 92 | 0000_0011 93 | 94 | @00026 95 | 0000_0000 96 | 97 | @00027 98 | 0001_1000 99 | 100 | @00028 101 | 0000_0001 102 | 103 | @00029 104 | 0000_0000 105 | 106 | @0002A 107 | 0000_1001 108 | 109 | @0002B 110 | 0000_0000 111 | 112 | @0002C 113 | 0000_0010 114 | 115 | @0002D 116 | 0000_0011 //bottom 117 | 118 | @0002E 119 | 0000_0000 120 | 121 | @0002F 122 | 1000_0000 //bottom 123 | 124 | @00030 125 | 0000_0000 //bottom 126 | 127 | @00031 128 | 0011_1110 //bottom 129 | 130 | @00032 131 | 0000_0000 132 | 133 | @00033 134 | 0000_0000 //bottom 135 | 136 | @00034 137 | 0000_0010 //bottom 138 | 139 | @00035 140 | 0000_0000 141 | 142 | @00036 143 | 0000_0000 144 | 145 | @00037 146 | 0000_0000 147 | 148 | @00038 149 | 0000_0000 150 | 151 | @0010A 152 | 0101_0000 153 | 154 | @0010B 155 | 0101_0010 156 | 157 | @0010C 158 | 0010_1001 159 | 160 | @0010D 161 | 0011_0001 162 | 163 | @0010E 164 | 0011_0101 165 | 166 | @0010F 167 | 1110_0110 168 | 169 | @00110 170 | 0000_0001 171 | 172 | @00111 173 | 0000_0000 174 | 175 | @00112 176 | 0000_0000 177 | 178 | @00113 179 | 0000_0001 180 | 181 | @00114 182 | 0000_0011 183 | 184 | @00115 185 | 0000_0000 186 | 187 | @00116 188 | 0001_1000 189 | 190 | @00117 191 | 1001_0000 192 | 193 | @00118 194 | 0000_0010 195 | 196 | @00119 197 | 1000_0000 198 | 199 | @0011A 200 | 0000_0000 201 | 202 | @0011B 203 | 0000_0011 204 | 205 | @0011C 206 | 0000_0011 207 | 208 | @0011D 209 | 1000_1001 210 | 211 | @0011E 212 | 0000_0000 213 | 214 | @0011F 215 | 0000_0000 216 | 217 | @00120 218 | 0000_0000 219 | 220 | @00121 221 | 0000_0000 222 | 223 | @00122 224 | 0000_0000 225 | 226 | @00123 227 | 0000_0000 228 | 229 | @00124 230 | 0001_0000 231 | 232 | @00125 233 | 0000_0000 234 | 235 | @00126 236 | 0000_0100 237 | 238 | @00127 239 | 0000_0100 240 | 241 | @00128 242 | 0000_0100 243 | 244 | @00129 245 | 0000_0001 246 | 247 | @0012A 248 | 0000_0010 249 | 250 | @0012B 251 | 0000_0011 252 | 253 | @0012C 254 | 0000_0111 255 | 256 | @0012D 257 | 0000_0001 258 | 259 | @0012E 260 | 0010_0100 261 | 262 | @0012F 263 | 0000_0000 264 | 265 | @00130 266 | 0000_0001 267 | 268 | @00131 269 | 0000_0000 270 | 271 | @00132 272 | 0001_0001 273 | 274 | @00133 275 | 0000_0000 276 | 277 | @00134 278 | 0000_0000 279 | 280 | @00135 281 | 0000_0010 282 | 283 | @00136 284 | 0000_0011 //bottom 285 | 286 | @00137 287 | 0000_0000 288 | 289 | @00138 290 | 1000_0000 //bottom 291 | 292 | @00139 293 | 0000_0000 //bottom 294 | 295 | @0013A 296 | 0110_0100 297 | 298 | @0013B 299 | 0000_0000 300 | 301 | @0013C 302 | 0000_0010 303 | 304 | @0013D 305 | 0000_0011 306 | 307 | @0013E 308 | 0000_0000 309 | 310 | @0013F 311 | 1000_0000 312 | 313 | @00140 314 | 0000_0000 315 | 316 | @00141 317 | 0000_0000 318 | 319 | @00142 320 | 0000_0000 321 | 322 | @00143 323 | 1000_0000 324 | 325 | @00144 326 | 0111_1110 //bottom 327 | 328 | @00145 329 | 0000_0000 330 | 331 | @00146 332 | 0000_0000 //bottom 333 | 334 | @00147 335 | 0000_0010 //bottom 336 | 337 | @00148 338 | 0110_0100 339 | 340 | @00149 341 | 0000_0000 342 | 343 | @0014A 344 | 0000_0010 345 | 346 | @0014B 347 | 0000_0011 348 | 349 | @0014C 350 | 0000_0000 351 | 352 | @0014D 353 | 1000_0000 354 | 355 | @0014E 356 | 0000_0000 357 | 358 | @0014F 359 | 0000_0000 360 | 361 | @00150 362 | 0000_0000 363 | 364 | @00151 365 | 1000_0000 366 | 367 | @00152 368 | 1111_1111 369 | 370 | @00153 371 | 1111_1111 372 | 373 | @00154 374 | 1111_1111 375 | 376 | @00155 377 | 1111_1111 378 | 379 | @00156 380 | 1111_1111 381 | 382 | 383 | 384 | 385 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/new/thinpad_top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module thinpad_top( 4 | input wire clk_50M, //50MHz 时钟输入 5 | input wire clk_11M0592, //11.0592MHz 时钟输入 6 | 7 | input wire clock_btn, //BTN5手动时钟按钮开关，带消抖电路，按下时为1 8 | input wire reset_btn, //BTN6手动复位按钮开关，带消抖电路，按下时为1 9 | 10 | input wire[3:0] touch_btn, //BTN1~BTN4，按钮开关，按下时为1 11 | input wire[31:0] dip_sw, //32位拨码开关，拨到“ON”时为1 12 | output wire[15:0] leds, //16位LED，输出时1点亮 13 | output wire[7:0] dpy0, //数码管低位信号，包括小数点，输出1点亮 14 | output wire[7:0] dpy1, //数码管高位信号，包括小数点，输出1点亮 15 | 16 | //CPLD串口控制器信号 17 | output wire uart_rdn, //读串口信号，低有效 18 | output wire uart_wrn, //写串口信号，低有效 19 | input wire uart_dataready, //串口数据准备好 20 | input wire uart_tbre, //发送数据标志 21 | input wire uart_tsre, //数据发送完毕标志 22 | 23 | //BaseRAM信号 24 | inout wire[31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享 25 | output wire[19:0] base_ram_addr, //BaseRAM地址 26 | output wire[3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0 27 | output wire base_ram_ce_n, //BaseRAM片选，低有效 28 | output wire base_ram_oe_n, //BaseRAM读使能，低有效 29 | output wire base_ram_we_n, //BaseRAM写使能，低有效 30 | 31 | //ExtRAM信号 32 | inout wire[31:0] ext_ram_data, //ExtRAM数据 33 | output wire[19:0] ext_ram_addr, //ExtRAM地址 34 | output wire[3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0 35 | output wire ext_ram_ce_n, //ExtRAM片选，低有效 36 | output wire ext_ram_oe_n, //ExtRAM读使能，低有效 37 | output wire ext_ram_we_n, //ExtRAM写使能，低有效 38 | 39 | //直连串口信号 40 | output wire txd, //直连串口发送端 41 | input wire rxd, //直连串口接收端 42 | 43 | //Flash存储器信号，参考 JS28F640 芯片手册 44 | output wire [22:0]flash_a, //Flash地址，a0仅在8bit模式有效，16bit模式无意义 45 | inout wire [15:0]flash_d, //Flash数据 46 | output wire flash_rp_n, //Flash复位信号，低有效 47 | output wire flash_vpen, //Flash写保护信号，低电平时不能擦除、烧写 48 | output wire flash_ce_n, //Flash片选信号，低有效 49 | output wire flash_oe_n, //Flash读使能信号，低有效 50 | output wire flash_we_n, //Flash写使能信号，低有效 51 | output wire flash_byte_n, //Flash 8bit模式选择，低有效。在使用flash的16位模式时请设为1 52 | 53 | //USB 控制器信号，参考 SL811 芯片手册 54 | output wire sl811_a0, 55 | //inout wire[7:0] sl811_d, //USB数据线与网络控制器的dm9k_sd[7:0]共享 56 | output wire sl811_wr_n, 57 | output wire sl811_rd_n, 58 | output wire sl811_cs_n, 59 | output wire sl811_rst_n, 60 | output wire sl811_dack_n, 61 | input wire sl811_intrq, 62 | input wire sl811_drq_n, 63 | 64 | //网络控制器信号，参考 DM9000A 芯片手册 65 | output wire dm9k_cmd, 66 | inout wire[15:0] dm9k_sd, 67 | output wire dm9k_iow_n, 68 | output wire dm9k_ior_n, 69 | output wire dm9k_cs_n, 70 | output wire dm9k_pwrst_n, 71 | input wire dm9k_int, 72 | 73 | //图像输出信号 74 | output wire[2:0] video_red, //红色像素，3位 75 | output wire[2:0] video_green, //绿色像素，3位 76 | output wire[1:0] video_blue, //蓝色像素，2位 77 | output wire video_hsync, //行同步（水平同步）信号 78 | output wire video_vsync, //场同步（垂直同步）信号 79 | output wire video_clk, //像素时钟输出 80 | output wire video_de //行数据有效信号，用于区分消隐区 81 | ); 82 | 83 | /* =========== Demo code begin =========== */ 84 | 85 | // PLL分频示例 86 | wire locked, clk_10M, clk_20M; 87 | pll_example clock_gen 88 | ( 89 | // Clock out ports 90 | .clk_out1(clk_10M), // 时钟输出1，频率在IP配置界面中设置 91 | .clk_out2(clk_20M), // 时钟输出2，频率在IP配置界面中设置 92 | // Status and control signals 93 | .reset(reset_btn), // PLL复位输入 94 | .locked(locked), // 锁定输出，"1"表示时钟稳定，可作为后级电路复位 95 | // Clock in ports 96 | .clk_in1(clk_50M) // 外部时钟输入 97 | ); 98 | 99 | reg reset_of_clk10M; 100 | // 异步复位，同步释放 101 | always@(posedge clk_10M or negedge locked) begin 102 | if(~locked) reset_of_clk10M <= 1'b1; 103 | else reset_of_clk10M <= 1'b0; 104 | end 105 | 106 | always@(posedge clk_10M or posedge reset_of_clk10M) begin 107 | if(reset_of_clk10M)begin 108 | // Your Code 109 | end 110 | else begin 111 | // Your Code 112 | end 113 | end 114 | 115 | // 不使用内存、串口时，禁用其使能信号 116 | assign base_ram_ce_n = 1'b1; 117 | assign base_ram_oe_n = 1'b1; 118 | assign base_ram_we_n = 1'b1; 119 | 120 | assign ext_ram_ce_n = 1'b1; 121 | assign ext_ram_oe_n = 1'b1; 122 | assign ext_ram_we_n = 1'b1; 123 | 124 | assign uart_rdn = 1'b1; 125 | assign uart_wrn = 1'b1; 126 | 127 | // 数码管连接关系示意图，dpy1同理 128 | // p=dpy0[0] // ---a--- 129 | // c=dpy0[1] // | | 130 | // d=dpy0[2] // f b 131 | // e=dpy0[3] // | | 132 | // b=dpy0[4] // ---g--- 133 | // a=dpy0[5] // | | 134 | // f=dpy0[6] // e c 135 | // g=dpy0[7] // | | 136 | // // ---d--- p 137 | 138 | // 7段数码管译码器演示，将number用16进制显示在数码管上面 139 | reg[7:0] number; 140 | SEG7_LUT segL(.oSEG1(dpy0), .iDIG(number[3:0])); //dpy0是低位数码管 141 | SEG7_LUT segH(.oSEG1(dpy1), .iDIG(number[7:4])); //dpy1是高位数码管 142 | 143 | reg[15:0] led_bits; 144 | assign leds = led_bits; 145 | 146 | always@(posedge clock_btn or posedge reset_btn) begin 147 | if(reset_btn)begin //复位按下，设置LED和数码管为初始值 148 | number<=0; 149 | led_bits <= 16'h1; 150 | end 151 | else begin //每次按下时钟按钮，数码管显示值加1，LED循环左移 152 | number <= number+1; 153 | led_bits <= {led_bits[14:0],led_bits[15]}; 154 | end 155 | end 156 | 157 | //直连串口接收发送演示，从直连串口收到的数据再发送出去 158 | wire [7:0] ext_uart_rx; 159 | reg [7:0] ext_uart_buffer, ext_uart_tx; 160 | wire ext_uart_ready, ext_uart_busy; 161 | reg ext_uart_start, ext_uart_avai; 162 | 163 | async_receiver #(.ClkFrequency(50000000),.Baud(9600)) //接收模块，9600无检验位 164 | ext_uart_r( 165 | .clk(clk_50M), //外部时钟信号 166 | .RxD(rxd), //外部串行信号输入 167 | .RxD_data_ready(ext_uart_ready), //数据接收到标志 168 | .RxD_clear(ext_uart_ready), //清除接收标志 169 | .RxD_data(ext_uart_rx) //接收到的一字节数据 170 | ); 171 | 172 | always @(posedge clk_50M) begin //接收到缓冲区ext_uart_buffer 173 | if(ext_uart_ready)begin 174 | ext_uart_buffer <= ext_uart_rx; 175 | ext_uart_avai <= 1; 176 | end else if(!ext_uart_busy && ext_uart_avai)begin 177 | ext_uart_avai <= 0; 178 | end 179 | end 180 | always @(posedge clk_50M) begin //将缓冲区ext_uart_buffer发送出去 181 | if(!ext_uart_busy && ext_uart_avai)begin 182 | ext_uart_tx <= ext_uart_buffer; 183 | ext_uart_start <= 1; 184 | end else begin 185 | ext_uart_start <= 0; 186 | end 187 | end 188 | 189 | async_transmitter #(.ClkFrequency(50000000),.Baud(9600)) //发送模块，9600无检验位 190 | ext_uart_t( 191 | .clk(clk_50M), //外部时钟信号 192 | .TxD(txd), //串行信号输出 193 | .TxD_busy(ext_uart_busy), //发送器忙状态指示 194 | .TxD_start(ext_uart_start), //开始发送信号 195 | .TxD_data(ext_uart_tx) //待发送的数据 196 | ); 197 | 198 | //图像输出演示，分辨率800x600@75Hz，像素时钟为50MHz 199 | wire [11:0] hdata; 200 | assign video_red = hdata < 266 ? 3'b111 : 0; //红色竖条 201 | assign video_green = hdata < 532 && hdata >= 266 ? 3'b111 : 0; //绿色竖条 202 | assign video_blue = hdata >= 532 ? 2'b11 : 0; //蓝色竖条 203 | assign video_clk = clk_50M; 204 | vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 ( 205 | .clk(clk_50M), 206 | .hdata(hdata), //横坐标 207 | .vdata(), //纵坐标 208 | .hsync(video_hsync), 209 | .vsync(video_vsync), 210 | .data_enable(video_de) 211 | ); 212 | /* =========== Demo code end =========== */ 213 | 214 | endmodule 215 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/tb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module tb; 3 | 4 | wire clk_50M, clk_11M0592; 5 | 6 | reg clock_btn = 0; //BTN5手动时钟按钮开关，带消抖电路，按下时为1 7 | reg reset_btn = 0; //BTN6手动复位按钮开关，带消抖电路，按下时为1 8 | 9 | reg[3:0] touch_btn; //BTN1~BTN4，按钮开关，按下时为1 10 | reg[31:0] dip_sw; //32位拨码开关，拨到“ON”时为1 11 | 12 | wire[15:0] leds; //16位LED，输出时1点亮 13 | wire[7:0] dpy0; //数码管低位信号，包括小数点，输出1点亮 14 | wire[7:0] dpy1; //数码管高位信号，包括小数点，输出1点亮 15 | 16 | wire txd; //直连串口发送端 17 | wire rxd; //直连串口接收端 18 | 19 | wire[31:0] base_ram_data; //BaseRAM数据，低8位与CPLD串口控制器共享 20 | wire[19:0] base_ram_addr; //BaseRAM地址 21 | wire[3:0] base_ram_be_n; //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0 22 | wire base_ram_ce_n; //BaseRAM片选，低有效 23 | wire base_ram_oe_n; //BaseRAM读使能，低有效 24 | wire base_ram_we_n; //BaseRAM写使能，低有效 25 | 26 | wire[31:0] ext_ram_data; //ExtRAM数据 27 | wire[19:0] ext_ram_addr; //ExtRAM地址 28 | wire[3:0] ext_ram_be_n; //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0 29 | wire ext_ram_ce_n; //ExtRAM片选，低有效 30 | wire ext_ram_oe_n; //ExtRAM读使能，低有效 31 | wire ext_ram_we_n; //ExtRAM写使能，低有效 32 | 33 | wire [22:0]flash_a; //Flash地址，a0仅在8bit模式有效，16bit模式无意义 34 | wire [15:0]flash_d; //Flash数据 35 | wire flash_rp_n; //Flash复位信号，低有效 36 | wire flash_vpen; //Flash写保护信号，低电平时不能擦除、烧写 37 | wire flash_ce_n; //Flash片选信号，低有效 38 | wire flash_oe_n; //Flash读使能信号，低有效 39 | wire flash_we_n; //Flash写使能信号，低有效 40 | wire flash_byte_n; //Flash 8bit模式选择，低有效。在使用flash的16位模式时请设为1 41 | 42 | wire uart_rdn; //读串口信号，低有效 43 | wire uart_wrn; //写串口信号，低有效 44 | wire uart_dataready; //串口数据准备好 45 | wire uart_tbre; //发送数据标志 46 | wire uart_tsre; //数据发送完毕标志 47 | 48 | //Windows需要注意路径分隔符的转义，例如"D:\\foo\\bar.bin" 49 | parameter BASE_RAM_INIT_FILE = "/tmp/main.bin"; //BaseRAM初始化文件，请修改为实际的绝对路径 50 | parameter EXT_RAM_INIT_FILE = "/tmp/eram.bin"; //ExtRAM初始化文件，请修改为实际的绝对路径 51 | parameter FLASH_INIT_FILE = "/tmp/kernel.elf"; //Flash初始化文件，请修改为实际的绝对路径 52 | 53 | assign rxd = 1'b1; //idle state 54 | 55 | initial begin 56 | //在这里可以自定义测试输入序列，例如： 57 | dip_sw = 32'h2; 58 | touch_btn = 0; 59 | for (integer i = 0; i < 20; i = i+1) begin 60 | #100; //等待100ns 61 | clock_btn = 1; //按下手工时钟按钮 62 | #100; //等待100ns 63 | clock_btn = 0; //松开手工时钟按钮 64 | end 65 | // 模拟PC通过串口发送字符 66 | cpld.pc_send_byte(8'h32); 67 | #10000; 68 | cpld.pc_send_byte(8'h33); 69 | end 70 | 71 | // 待测试用户设计 72 | thinpad_top dut( 73 | .clk_50M(clk_50M), 74 | .clk_11M0592(clk_11M0592), 75 | .clock_btn(clock_btn), 76 | .reset_btn(reset_btn), 77 | .touch_btn(touch_btn), 78 | .dip_sw(dip_sw), 79 | .leds(leds), 80 | .dpy1(dpy1), 81 | .dpy0(dpy0), 82 | .txd(txd), 83 | .rxd(rxd), 84 | .uart_rdn(uart_rdn), 85 | .uart_wrn(uart_wrn), 86 | .uart_dataready(uart_dataready), 87 | .uart_tbre(uart_tbre), 88 | .uart_tsre(uart_tsre), 89 | .base_ram_data(base_ram_data), 90 | .base_ram_addr(base_ram_addr), 91 | .base_ram_ce_n(base_ram_ce_n), 92 | .base_ram_oe_n(base_ram_oe_n), 93 | .base_ram_we_n(base_ram_we_n), 94 | .base_ram_be_n(base_ram_be_n), 95 | .ext_ram_data(ext_ram_data), 96 | .ext_ram_addr(ext_ram_addr), 97 | .ext_ram_ce_n(ext_ram_ce_n), 98 | .ext_ram_oe_n(ext_ram_oe_n), 99 | .ext_ram_we_n(ext_ram_we_n), 100 | .ext_ram_be_n(ext_ram_be_n), 101 | .flash_d(flash_d), 102 | .flash_a(flash_a), 103 | .flash_rp_n(flash_rp_n), 104 | .flash_vpen(flash_vpen), 105 | .flash_oe_n(flash_oe_n), 106 | .flash_ce_n(flash_ce_n), 107 | .flash_byte_n(flash_byte_n), 108 | .flash_we_n(flash_we_n) 109 | ); 110 | // 时钟源 111 | clock osc( 112 | .clk_11M0592(clk_11M0592), 113 | .clk_50M (clk_50M) 114 | ); 115 | // CPLD 串口仿真模型 116 | cpld_model cpld( 117 | .clk_uart(clk_11M0592), 118 | .uart_rdn(uart_rdn), 119 | .uart_wrn(uart_wrn), 120 | .uart_dataready(uart_dataready), 121 | .uart_tbre(uart_tbre), 122 | .uart_tsre(uart_tsre), 123 | .data(base_ram_data[7:0]) 124 | ); 125 | // BaseRAM 仿真模型 126 | sram_model base1(/*autoinst*/ 127 | .DataIO(base_ram_data[15:0]), 128 | .Address(base_ram_addr[19:0]), 129 | .OE_n(base_ram_oe_n), 130 | .CE_n(base_ram_ce_n), 131 | .WE_n(base_ram_we_n), 132 | .LB_n(base_ram_be_n[0]), 133 | .UB_n(base_ram_be_n[1])); 134 | sram_model base2(/*autoinst*/ 135 | .DataIO(base_ram_data[31:16]), 136 | .Address(base_ram_addr[19:0]), 137 | .OE_n(base_ram_oe_n), 138 | .CE_n(base_ram_ce_n), 139 | .WE_n(base_ram_we_n), 140 | .LB_n(base_ram_be_n[2]), 141 | .UB_n(base_ram_be_n[3])); 142 | // ExtRAM 仿真模型 143 | sram_model ext1(/*autoinst*/ 144 | .DataIO(ext_ram_data[15:0]), 145 | .Address(ext_ram_addr[19:0]), 146 | .OE_n(ext_ram_oe_n), 147 | .CE_n(ext_ram_ce_n), 148 | .WE_n(ext_ram_we_n), 149 | .LB_n(ext_ram_be_n[0]), 150 | .UB_n(ext_ram_be_n[1])); 151 | sram_model ext2(/*autoinst*/ 152 | .DataIO(ext_ram_data[31:16]), 153 | .Address(ext_ram_addr[19:0]), 154 | .OE_n(ext_ram_oe_n), 155 | .CE_n(ext_ram_ce_n), 156 | .WE_n(ext_ram_we_n), 157 | .LB_n(ext_ram_be_n[2]), 158 | .UB_n(ext_ram_be_n[3])); 159 | // Flash 仿真模型 160 | x28fxxxp30 #(.FILENAME_MEM(FLASH_INIT_FILE)) flash( 161 | .A(flash_a[1+:22]), 162 | .DQ(flash_d), 163 | .W_N(flash_we_n), // Write Enable 164 | .G_N(flash_oe_n), // Output Enable 165 | .E_N(flash_ce_n), // Chip Enable 166 | .L_N(1'b0), // Latch Enable 167 | .K(1'b0), // Clock 168 | .WP_N(flash_vpen), // Write Protect 169 | .RP_N(flash_rp_n), // Reset/Power-Down 170 | .VDD('d3300), 171 | .VDDQ('d3300), 172 | .VPP('d1800), 173 | .Info(1'b1)); 174 | 175 | initial begin 176 | wait(flash_byte_n == 1'b0); 177 | $display("8-bit Flash interface is not supported in simulation!"); 178 | $display("Please tie flash_byte_n to high"); 179 | $stop; 180 | end 181 | 182 | // 从文件加载 BaseRAM 183 | initial begin 184 | reg [31:0] tmp_array[0:1048575]; 185 | integer n_File_ID, n_Init_Size; 186 | n_File_ID = $fopen(BASE_RAM_INIT_FILE, "rb"); 187 | if(!n_File_ID)begin 188 | n_Init_Size = 0; 189 | $display("Failed to open BaseRAM init file"); 190 | end else begin 191 | n_Init_Size = $fread(tmp_array, n_File_ID); 192 | n_Init_Size /= 4; 193 | $fclose(n_File_ID); 194 | end 195 | $display("BaseRAM Init Size(words): %d",n_Init_Size); 196 | for (integer i = 0; i < n_Init_Size; i++) begin 197 | base1.mem_array0[i] = tmp_array[i][24+:8]; 198 | base1.mem_array1[i] = tmp_array[i][16+:8]; 199 | base2.mem_array0[i] = tmp_array[i][8+:8]; 200 | base2.mem_array1[i] = tmp_array[i][0+:8]; 201 | end 202 | end 203 | 204 | // 从文件加载 ExtRAM 205 | initial begin 206 | reg [31:0] tmp_array[0:1048575]; 207 | integer n_File_ID, n_Init_Size; 208 | n_File_ID = $fopen(EXT_RAM_INIT_FILE, "rb"); 209 | if(!n_File_ID)begin 210 | n_Init_Size = 0; 211 | $display("Failed to open ExtRAM init file"); 212 | end else begin 213 | n_Init_Size = $fread(tmp_array, n_File_ID); 214 | n_Init_Size /= 4; 215 | $fclose(n_File_ID); 216 | end 217 | $display("ExtRAM Init Size(words): %d",n_Init_Size); 218 | for (integer i = 0; i < n_Init_Size; i++) begin 219 | ext1.mem_array0[i] = tmp_array[i][24+:8]; 220 | ext1.mem_array1[i] = tmp_array[i][16+:8]; 221 | ext2.mem_array0[i] = tmp_array[i][8+:8]; 222 | ext2.mem_array1[i] = tmp_array[i][0+:8]; 223 | end 224 | end 225 | endmodule 226 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/new/async.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////// 2 | // RS-232 RX and TX module 3 | // (c) fpga4fun.com & KNJN LLC - 2003 to 2016 4 | 5 | // The RS-232 settings are fixed 6 | // TX: 8-bit data, 2 stop, no-parity 7 | // RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course) 8 | 9 | //`define SIMULATION // in this mode, TX outputs one bit per clock cycle 10 | // and RX receives one bit per clock cycle (for fast simulations) 11 | 12 | //////////////////////////////////////////////////////// 13 | `default_nettype wire 14 | module async_transmitter( 15 | input clk, 16 | input TxD_start, 17 | input [7:0] TxD_data, 18 | output TxD, 19 | output TxD_busy 20 | ); 21 | 22 | // Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data 23 | // TxD_data is latched so that it doesn't have to stay valid while it is being sent 24 | 25 | parameter ClkFrequency = 25000000; // 25MHz 26 | parameter Baud = 115200; 27 | 28 | generate 29 | if(ClkFrequency> 1); 52 | 53 | case(TxD_state) 54 | 4'b0000: if(TxD_start) TxD_state <= 4'b0100; 55 | 4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit 56 | 4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0 57 | 4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1 58 | 4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2 59 | 4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3 60 | 4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4 61 | 4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5 62 | 4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6 63 | 4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7 64 | 4'b0010: if(BitTick) TxD_state <= 4'b0000; // stop1 65 | //4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2 66 | default: if(BitTick) TxD_state <= 4'b0000; 67 | endcase 68 | end 69 | 70 | assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits 71 | endmodule 72 | 73 | 74 | //////////////////////////////////////////////////////// 75 | module async_receiver( 76 | input clk, 77 | input RxD, 78 | output reg RxD_data_ready = 0, 79 | input RxD_clear, 80 | output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted 81 | 82 | // We also detect if a gap occurs in the received stream of characters 83 | // That can be useful if multiple characters are sent in burst 84 | // so that multiple characters can be treated as a "packet" 85 | output RxD_idle, // asserted when no data has been received for a while 86 | output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high) 87 | ); 88 | 89 | parameter ClkFrequency = 25000000; // 25MHz 90 | parameter Baud = 115200; 91 | 92 | parameter Oversampling = 8; // needs to be a power of 2 93 | // we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time 94 | // 8 times oversampling by default, use 16 for higher quality reception 95 | 96 | generate 97 | if(ClkFrequency>log2) log2=log2+1; end endfunction 134 | localparam l2o = log2(Oversampling); 135 | reg [l2o-2:0] OversamplingCnt = 0; 136 | always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1; 137 | wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1); 138 | `endif 139 | 140 | // now we can accumulate the RxD bits in a shift-register 141 | always @(posedge clk) 142 | case(RxD_state) 143 | 4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found? 144 | 4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow 145 | 4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0 146 | 4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1 147 | 4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2 148 | 4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3 149 | 4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4 150 | 4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5 151 | 4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6 152 | 4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7 153 | 4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit 154 | default: RxD_state <= 4'b0000; 155 | endcase 156 | 157 | always @(posedge clk) 158 | if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]}; 159 | 160 | //reg RxD_data_error = 0; 161 | always @(posedge clk) 162 | begin 163 | if(RxD_clear) 164 | RxD_data_ready <= 0; 165 | else 166 | RxD_data_ready <= RxD_data_ready | (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received 167 | //RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received 168 | end 169 | 170 | `ifdef SIMULATION 171 | assign RxD_idle = 0; 172 | `else 173 | reg [l2o+1:0] GapCnt = 0; 174 | always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1; 175 | assign RxD_idle = GapCnt[l2o+1]; 176 | always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0]; 177 | `endif 178 | 179 | endmodule 180 | 181 | 182 | //////////////////////////////////////////////////////// 183 | // dummy module used to be able to raise an assertion in Verilog 184 | module ASSERTION_ERROR(); 185 | endmodule 186 | 187 | 188 | //////////////////////////////////////////////////////// 189 | module BaudTickGen( 190 | input clk, enable, 191 | output tick // generate a tick at the specified baud rate * oversampling 192 | ); 193 | parameter ClkFrequency = 25000000; 194 | parameter Baud = 115200; 195 | parameter Oversampling = 1; 196 | 197 | function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction 198 | localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte 199 | reg [AccWidth:0] Acc = 0; 200 | localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow 201 | localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter); 202 | always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0]; 203 | assign tick = Acc[AccWidth]; 204 | endmodule 205 | 206 | 207 | //////////////////////////////////////////////////////// 208 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/include/data.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | `include "UserData.h" 22 | // ****** 23 | // 24 | // data.h 25 | // 26 | // ****** 27 | 28 | // ******************** 29 | // 30 | // Main Characteristics 31 | // 32 | // ******************** 33 | 34 | `ifdef x128P30B 35 | 36 | `define ADDRBUS_dim 23 // - Address Bus pin numbers 37 | 38 | `elsif x128P30T 39 | 40 | `define ADDRBUS_dim 23 41 | 42 | `else 43 | 44 | `define ADDRBUS_dim 22 45 | 46 | `endif 47 | 48 | `define DATABUS_dim 16 // - Data Bus pin numbers 49 | `define MEMORY_dim 1 << `ADDRBUS_dim // - Memory Dimension 50 | `define LAST_ADDR (`MEMORY_dim) - 1 // - Last Address 51 | 52 | // ******************** 53 | // 54 | // Address & Data range 55 | // 56 | // ******************** 57 | 58 | `define ADDRBUS_range `ADDRBUS_dim - 1 : 0 59 | `define DATABUS_range `DATABUS_dim - 1 : 0 60 | 61 | // ***************** 62 | // 63 | // Init Memory Files 64 | // 65 | // ***************** 66 | 67 | `define CFI_dim 9'h157 68 | `define CFI_range `CFI_dim - 1:9'h10 69 | // ******************* 70 | // 71 | // Protection Register 72 | // 73 | // ******************* 74 | 75 | 76 | `define REG_addrStart 16'h0 77 | `define REG_addrEnd 16'h15 78 | 79 | `define REGSTART_addr 9'h80 // Protection Register Start Address 80 | `define REGEND_addr 9'h109 // Protection Register End Address 81 | `define REG_dim `REGEND_addr - `REGSTART_addr + 1 82 | 83 | `define REG_addrRange `REG_addrEnd:`REG_addrStart 84 | 85 | `define REG_addrbitStart 8'd0 86 | `define REG_addrbitEnd 8'd8 87 | `define REG_addrbitRange `REG_addrbitEnd:`REG_addrbitStart 88 | 89 | `define PROTECTREGLOCK_addr 9'h80 // Protection Register Lock Address 90 | 91 | 92 | `define UDNREGSTART_addr 9'h81 93 | `define UDNREGEND_addr 9'h84 94 | `define UDNprotect_bit 8'hFE 95 | 96 | `define UPREGSTART_addr 9'h85 97 | `define UPREGEND_addr 9'h88 98 | `define UPprotect_bit 8'hFD // serve ad indentificare quale bit deve essere 0 nel lock regi 99 | `define PRL_default 16'h0002 // Protection Register Lock default definito anche in def 100 | 101 | // ***************************** 102 | // 103 | // Extended User OTP 104 | // 105 | // ***************************** 106 | 107 | `define ExtREG_dim 8'h20 108 | 109 | 110 | `define ExtREG_regiondim 8'h8 111 | `define ExtREGSTART_regionaddr 9'h8A // Ext Protection Register Start Address 112 | `define ExtREGEND_regionaddr 9'h109 // Ext Protection Register End Address 113 | 114 | `define ExtPROTECTREGLOCK_addr 9'h89 // Ext Protection Register Lock Address 115 | `define ExtPRL_default 16'hFFFF // Protection Register Lock default 116 | 117 | 118 | 119 | // *********************** 120 | // 121 | // Voltage Characteristics 122 | // 123 | // *********************** 124 | `define Voltage_range 35:0 125 | `define VDDmin 36'd02300 126 | `define VDDmax 36'd03600 127 | `define VDDQmin 36'd02300 128 | `define VDDQmax 36'd03600 129 | `define VPPmin 36'd00900 130 | `define VPPmax 36'd03600 131 | `define VPPHmin 36'd08500 132 | `define VPPHmax 36'd09500 133 | 134 | // ********************** 135 | // 136 | // Configuration Register 137 | // 138 | // ********************** 139 | 140 | `define ConfigurationReg_dim 16 141 | `define ConfigReg_default 16'hBBCF 142 | 143 | // ******************** 144 | // 145 | // Electronic Signature 146 | // 147 | // ******************** 148 | 149 | `define ManufacturerCode 8'h89 150 | 151 | `ifdef x128P30B 152 | 153 | `define TopDeviceCode 8'h18 154 | `define BottomDeviceCode 8'h1B 155 | 156 | `elsif x128P30T 157 | `define TopDeviceCode 8'h18 158 | `define BottomDeviceCode 8'h1B 159 | 160 | `else 161 | `define TopDeviceCode 8'h17 162 | `define BottomDeviceCode 8'h1A 163 | 164 | `endif 165 | 166 | 167 | 168 | `define SignAddress_dim 9 169 | `define SignAddress_range `SignAddress_dim - 1 : 0 170 | 171 | 172 | 173 | // ********************* 174 | // 175 | // Write Buffer constant 176 | // 177 | // ********************* 178 | 179 | 180 | `define ProgramBuffer_addrDim 8 // Program Buffer address dimension 181 | `define ProgramBuffer_addrRange `ProgramBuffer_addrDim - 1:0 182 | `define ProgramBuffer_dim 256 // Buffer Size= 2 ^ ProgramBuffer_addrDim 183 | `define ProgramBuffer_range `ProgramBuffer_dim - 1:0 184 | 185 | // ********************* 186 | // 187 | // Buffer Enhanced Program constant 188 | // 189 | // ********************* 190 | 191 | `define BuffEnhProgramBuffer_dim 256 192 | `define BuffEnhProgramBuffer_range `BuffEnhProgramBuffer_dim - 1 : 0 193 | `define BuffEnhProgramBuffer_addrDim 8 194 | `define BuffEnhProgramBuffer_addrRange `BuffEnhProgramBuffer_addrDim - 1:0 195 | 196 | 197 | // Warning and Error Messages 198 | 199 | `define NoError_msg 0 // No Error Found 200 | `define CmdSeq_msg 1 // Sequence Command Unknown 201 | `define SuspCmd_msg 2 // Cannot execute this command during suspend 202 | `define SuspAcc_msg 3 // Cannot access this address due to suspend 203 | `define AddrRange_msg 4 // Address out of range 204 | `define AddrTog_msg 5 // Cannot change block address during command sequence 205 | `define SuspAccWarn_msg 6 // It isn't possible access this address due to suspend 206 | `define InvVDD_msg 7 // Voltage Supply must be: VDD>VDDmin or VDDVDDmin or VDD `MainBlock_num - 1 && n_block <= `MainBlock_num + `ParameterBlock_num - 1) // parameter block 132 | begin 133 | StartAddr = EndAddr + 1; 134 | EndAddr = StartAddr + `ParameterBlock_size * `Kword - 1; 135 | 136 | end 137 | 138 | else // Main block 139 | begin 140 | StartAddr = EndAddr + 1; 141 | EndAddr = StartAddr + `MainBlock_size * `Kword - 1; 142 | end 143 | 144 | end else begin // organize = "bottom" 145 | 146 | if (n_block == 0) EndAddr = - 1; 147 | 148 | if (n_block > `ParameterBlock_num - 1) 149 | begin 150 | StartAddr = (`ParameterBlock_num * `ParameterBlock_size * `Kword ) + 151 | (n_block - `ParameterBlock_num) * `MainBlock_size * `Kword; 152 | EndAddr = StartAddr + `MainBlock_size * `Kword - 1; 153 | end 154 | //! 155 | else // parameter block 156 | begin 157 | StartAddr = EndAddr + 1; 158 | EndAddr = StartAddr + `ParameterBlock_size * `Kword - 1; 159 | end 160 | 161 | end 162 | 163 | end 164 | endtask 165 | 166 | 167 | 168 | // ********************************************* 169 | // module work.MemoryModule:module (updated) 170 | // FUNCTION getBlock : return block from address 171 | // 172 | // ********************************************* 173 | 174 | function [`INTEGER] getBlock; // BLOCK_dim in binary is 9 bit size 175 | 176 | input address; 177 | 178 | reg [`ADDRBUS_dim - 1 : 0] address; 179 | reg found; 180 | integer count; 181 | 182 | begin 183 | 184 | count = 0; 185 | found = 0; 186 | while ((count <= `BLOCK_dim) && (! found)) 187 | begin 188 | 189 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) found= 1; 190 | else count = count + 1; 191 | 192 | end 193 | 194 | if (!found) $display("%t !Error in Block Library : specified block address is out of range",$time); 195 | 196 | getBlock= count; 197 | 198 | end 199 | endfunction 200 | 201 | 202 | // *************************** 203 | // 204 | // FUNCTION getBlockAddress : 205 | // return the block address 206 | // 207 | // *************************** 208 | 209 | function [`ADDRBUS_dim - 1 : 0] getBlockAddress; 210 | 211 | input block; 212 | 213 | integer block; 214 | 215 | begin 216 | 217 | getBlockAddress = BlockBoundaryStartAddr[block]; 218 | 219 | end 220 | endfunction 221 | 222 | 223 | // ********************************************* 224 | // 225 | // FUNCTION isParameterBlock : 226 | // return true if the address 227 | // is in a parameter block 228 | // 229 | // ********************************************* 230 | 231 | function isParameterBlock; 232 | 233 | input address; 234 | 235 | 236 | reg [`ADDRBUS_dim - 1 : 0] address; 237 | reg prm; 238 | integer count; 239 | 240 | begin 241 | 242 | prm = `FALSE; 243 | if (`organization=="bottom") begin 244 | 245 | for (count = 0; count <= `ParameterBlock_num - 1; count = count + 1) begin: cycle 246 | 247 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 248 | begin 249 | prm= `TRUE; 250 | disable cycle; 251 | end 252 | end 253 | end else begin 254 | for (count = `BLOCK_dim - `ParameterBlock_num + 1; count <= `BLOCK_dim - 1; count = count + 1) begin: cycle1 255 | 256 | 257 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 258 | begin 259 | prm= `TRUE; 260 | disable cycle1; 261 | end 262 | end 263 | end 264 | 265 | isParameterBlock = prm; 266 | 267 | end 268 | endfunction 269 | 270 | 271 | // ********************************************* 272 | // 273 | // FUNCTION isMainBlock : 274 | // return true if the address is in a main block 275 | // 276 | // ********************************************* 277 | 278 | function isMainBlock; 279 | 280 | input address; 281 | 282 | reg [`ADDRBUS_dim - 1 : 0] address; 283 | reg main; 284 | integer count; 285 | 286 | begin 287 | 288 | main = `FALSE; 289 | 290 | if (`organization=="bottom") begin 291 | for (count = `BLOCK_dim - 1; count >= `BLOCK_dim - `ParameterBlock_num + 1; count = count - 1) begin: cycle2 292 | 293 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 294 | begin 295 | main = `TRUE; 296 | disable cycle2; 297 | end 298 | 299 | end 300 | end else begin 301 | for (count = 0; count <= `MainBlock_num - 1; count = count + 1) begin: cycle3 302 | 303 | 304 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 305 | begin 306 | main = `TRUE; 307 | disable cycle3; 308 | end 309 | end 310 | end 311 | isMainBlock = main; 312 | end 313 | endfunction 314 | 315 | 316 | endmodule 317 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/include/TimingData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | `include "data.h" 22 | `include "UserData.h" 23 | 24 | `define Reset_time 300000 25 | 26 | // ********************************************* 27 | // 28 | // Table 29 29 | // Program/Erase Characteristics 30 | // 31 | // ********************************************* 32 | 33 | // Vpp = VppL 34 | 35 | `define ParameterBlockErase_time 400000000// 0.4 sec 36 | `define MainBlockErase_time 500000000 37 | 38 | `define WordProgram_time 40000 // 40 us 39 | `define ParameterBlockProgram_time 64000 // 40 | `define MainBlockProgram_time 256000 // 41 | 42 | `define ProgramSuspendLatency_time 15000 // 15 us 43 | `define EraseSuspendLatency_time 15000 // 15 us 44 | `define MainBlankCheck_time 3200000 45 | // Vpp = VppH 46 | 47 | `define FastParameterBlockErase_time 800000000 // 0.8 sec 48 | `define FastMainBlockErase_time 800000000 // 0.8 sec 49 | `define FastWordProgram_time 40000 50 | `define FastParameterBlockProgram_time 64000 51 | `define FastMainBlockProgram_time 256000 52 | 53 | `define BlockProtect_time 1800 54 | `define BlockUnProtect_time 5000000 55 | 56 | `define ProgramBuffer_time 700000 57 | 58 | 59 | `define EnhBuffProgram_time 512000 // 60 | `define EnhBuffProgramSetupPhase_time 5000 61 | 62 | 63 | 64 | // ********************** 65 | // 66 | // Timing Data Module : 67 | // set timing values 68 | // 69 | // ********************** 70 | 71 | module TimingDataModule; 72 | 73 | // ************************************ 74 | // 75 | // AC Read Specifications 76 | // 77 | // Table 27 78 | // 79 | // ************************************ 80 | 81 | integer tAVAV; // Address Valid to Next Address Valid 82 | integer tAVQV; // Address Valid to Output Valid (Random) 83 | integer tAVQV1; // Address Valid to Output Valid (Page) 84 | integer tELTV; // Chip Enable Low to Wait Valid 85 | integer tELQV; // Chip Enable Low to Output Valid 86 | integer tELQX; // Chip Enable Low to Output Transition 87 | integer tEHTZ; // Chip Enable High to Wait Hi-Z 88 | integer tEHQX;//tOH // Chip Enable High to Output Transition 89 | integer tEHQZ; // Chip Enable High to Output Hi-Z 90 | integer tGLQV; // Output Enable Low to Output Valid 91 | integer tGLQX; // Output Enable Low to Output Transition 92 | integer tGHQZ; // Output Enable High to Output Hi-Z 93 | integer tAVLH;//tAVVH // Address Valid to (ADV#) Latch Enable High 94 | integer tELLH; //tELVH // Chip Enable Low to Latch Enable High 95 | integer tLHAX; //tVHAX // Latch Enable High to Address Transition 96 | integer tLLLH; //tVLVH // Latch Enable Low to Latch Enable High 97 | integer tLLQV; //tVLQV // Latch Enable Low to Output Valid 98 | 99 | integer tGLTV; //// Output Enable Low to Wait Valid 100 | integer tGLTX; //// Output Enable Low to Wait Transition 101 | integer tGHTZ; //// Output Enable high to Wait Hi-Z 102 | 103 | 104 | 105 | 106 | 107 | integer tAVKH; //tAVCH/L // Address Valid to Clock High 108 | integer tELKH; //tELCH // Chip Enable Low to Clock High 109 | integer tEHEL;// tEHEL // Chip Enable High to Chip Enable Low (reading) 110 | integer tKHAX;//tCHAX // Clock High to Address Transition 111 | integer tKHQV; //tCHQV // Clock High to Output Enable Valid 112 | integer tKHTV; //tCHTV // Clock High to Wait Valid 113 | integer tKHQX; //tCHQX // Clock High to Output Enable Transition 114 | integer tKHTX; //tCHTX // Clock High to Wait Transition 115 | integer tLLKH; //tVLCH/L // Latch Enable Low to Clock High 116 | integer tLLKL; //tVLCH/L // Latch Enable Low to Clock High 117 | integer tKHLL; //tCHVL //Clock valid to ADV# setup 118 | integer tKHKH; //tCLK // Clock Period 119 | integer tKHKL; //tCH/CL // Clock High to Clock Low 120 | integer tKLKH; // Clock Low to Clock High 121 | integer tCK_fall; //R203 // Clock Fall Time 122 | integer tCK_rise; // Clock Rise Time 123 | 124 | 125 | // ************************************************* 126 | // 127 | // AC Write Specifications 128 | // 129 | // Table 28 130 | // 131 | // ************************************************* 132 | 133 | integer tAVWH; // Address Valid to Write Enable High 134 | integer tDVWH; // Data Valid to Write Enable High 135 | integer tELWL; // Chip Enable Low to Write Enable Low 136 | integer tWHAV; //W18 // Write Enable High to Address Valid 137 | integer tWHAX; // Write Enable High to Address Transition 138 | integer tWHDX; // Write Enable High to Data Transition 139 | integer tWHEH; // Write Enable High to Chip Enable High 140 | integer tWHGL; // Write Enable High to Output Enable High 141 | integer tWHLL; //W28 tWHVL // Write Enable High to Latch Enable Low 142 | integer tWHWL; // Write Enable High to Latch Enable Low 143 | integer tWHQV; // Write Enable High to Output Enable Valid 144 | integer tWLWH; // Write Enable Low to Write Enable High 145 | integer tQVVPL; //tQVVL // Output (Status Register) Valid to Vpp Low 146 | integer tQVWPL; //tQVBL // Output (Status Register) Valid to Write Protect Low 147 | integer tVPHWH; // Vpp High to Write Enable High 148 | integer tWPHWH; //tBHWH // Write Protect High to Write Enable High 149 | 150 | 151 | integer tELEH; // Chip Enable Low to Chip Enable High 152 | 153 | 154 | //!// ************************************* 155 | //!// 156 | //!// Power and Reset 157 | //!// 158 | //!// Table 20 159 | //!// 160 | //!// ************************************** 161 | 162 | integer tPHWL; //W1 // Reset High to Write Enable Low 163 | integer tPLPH;//P1 // Reset High to Reset Low 164 | 165 | integer tVDHPH; //tVCCPH // Supply voltages High to Reset High 166 | 167 | 168 | 169 | initial begin 170 | 171 | setTiming(`t_access); 172 | 173 | end 174 | 175 | // ********************** 176 | // 177 | // FUNCTION getTime : 178 | // return time value 179 | // 180 | // ********************** 181 | 182 | function getTime; 183 | 184 | input [8*31 : 0] time_str; 185 | 186 | begin 187 | 188 | 189 | 190 | end 191 | endfunction 192 | 193 | // ********************** 194 | // 195 | // Task setTiming : 196 | // set timing values 197 | // 198 | // ********************** 199 | 200 | task setTiming; 201 | 202 | input time_access; 203 | 204 | integer time_access; 205 | 206 | begin 207 | 208 | // *********************************************** 209 | // 210 | // AC Read Specifications 211 | // 212 | // Table 27 213 | // 214 | // *********************************************** 215 | 216 | tELQX = 0; 217 | tEHQX = 0; 218 | tGLQX = 0; 219 | tGHQZ = 15; 220 | tELLH = 10; 221 | 222 | tAVAV = time_access; 223 | tAVQV = time_access; 224 | tELQV = time_access; 225 | tLLQV = time_access; 226 | 227 | tEHTZ = 20; 228 | tAVQV1 = 25; 229 | tELTV = 17; 230 | 231 | tEHEL = 17; 232 | tCK_fall = 3; 233 | tCK_rise = 3; 234 | tEHQZ = 20; 235 | tGLQV = 25; 236 | tAVLH = 10; 237 | tLHAX = 9; 238 | tLLLH = 10; 239 | 240 | tAVKH = 9; 241 | tELKH = 9; 242 | tKHAX = 10; 243 | tKHQV = 17; 244 | tKHTV = 17; 245 | tKHQX = 3; 246 | tKHTX = 3; 247 | tLLKH = 9; 248 | tLLKL = 9; 249 | tKHLL = 3; 250 | tKHKH = 19.2; 251 | tKHKL = 5; 252 | tKLKH = 5; 253 | tGLTV = 17; 254 | tGLTX = 0; 255 | tGHTZ = 20; 256 | 257 | // ************************************************* 258 | // 259 | // AC Write Specifications 260 | // 261 | // Table 28 262 | // 263 | // ************************************************* 264 | 265 | tELWL = 0; 266 | tWHAV = 0; 267 | tWHAX = 0; 268 | tWHDX = 0; 269 | tWHEH = 0; 270 | tWHGL = 0; 271 | tWHLL = 7; 272 | tQVVPL = 0; 273 | tQVWPL = 0; 274 | tVPHWH = 200; 275 | tWPHWH = 200; 276 | tAVWH = 50; 277 | 278 | tDVWH = 50; 279 | tWHWL = 20; 280 | tWHQV = tAVQV + 35; //tAVQV+35 281 | tWLWH = 50; 282 | tELEH = 50; 283 | 284 | // ************************************* 285 | // 286 | // Power and Reset 287 | // 288 | // Table 20 289 | // 290 | // ************************************** 291 | 292 | tPHWL = 150; 293 | tPLPH = 100; 294 | tVDHPH = 60; 295 | 296 | 297 | end 298 | endtask 299 | 300 | endmodule 301 | 302 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sim_1/new/sram_model.v: -------------------------------------------------------------------------------- 1 | //**************************************************************************// 2 | // 3 | // File Name: AS7C34098A.v 4 | // Version: 1.0 5 | // Date: 2 April 2005 6 | // Model: BUS Functional 7 | // Simulator: Cadence verilog-Xl 8 | // 9 | // 10 | // Company: Alliance Semiconductor pvt ltd. 11 | // Part Number: AS7C34098A (256K x 16) 12 | // 13 | // Description: Alliance 4Mb Fast Asynchronous SRAM 14 | // 15 | // Note: The model is Done for 10ns cycle time . To work with other cycle time, 16 | // we have to change the timing parameters according to Data sheet. 17 | // 18 | //**************************************************************************// 19 | 20 | `timescale 1 ns/1 ps 21 | 22 | 23 | module sram_model(Address, DataIO, OE_n, CE_n,WE_n, LB_n, UB_n); 24 | 25 | `define tsim 20000 26 | 27 | // Port Signal Definitions 28 | 29 | input [19:0] Address; 30 | inout [15:0] DataIO ; 31 | input OE_n,CE_n,WE_n, LB_n, UB_n; 32 | 33 | // Write Cycle Timing Parameters 34 | 35 | time twc ; // write cycle time 36 | time tcw ; // Chip enable to write end 37 | time taw ; // address setup to write end 38 | time tas ; // address setup time 39 | time twp1 ; // write pulse width(OE_n =1) 40 | time twp2 ; // write pulse width(OE_n =0) 41 | time twr ; // write recovery time 42 | time tah ; // address hold from end of write 43 | time tdw ; // data valid to write end 44 | time tdh ; // data hold time 45 | time twz ; // write enable to output in high-Z 46 | time tow ; // output active from write end 47 | time tbw ; // byte enable low to write end 48 | 49 | time UB_n_start_time=0,LB_n_start_time=0; 50 | time write_address1_time=0,write_data1_time=0,write_CE_n_start_time1=0,write_WE_n_start_time1=0; 51 | time write_CE_n_start_time=0,write_WE_n_start_time=0,write_address_time=0,write_data_time=0; 52 | time temptaa, temptoe, read_address_add,read_address_oe ; 53 | 54 | 55 | // Read Cycle Timing Parameters 56 | 57 | time trc ; // Read cycle time 58 | time taa ; // Address access time 59 | time tace ; // chip enable access time 60 | time toe ; // output enable access time 61 | time toh ; // output hold from address change 62 | time tclz ; // CE_n low to output in low-Z 63 | time tchz ; // CE_n high to output in High-Z 64 | time tolz ; // OE_n low to output in low-Z 65 | time tohz ; // OE_n high to output in High-Z 66 | time tba ; // LB_n/UB_n access time 67 | time tblz ; // LB_n/UB_n low to output in low-Z 68 | time tbhz ; // LB_n/UB_n high to output in High-Z 69 | time tpu ; // power up time 70 | time tpd ; // power down time 71 | 72 | time read_address_time,read_CE_n_start_time=0,read_WE_n_start_time=0,read_OE_n_start_time=0; 73 | 74 | 75 | 76 | // Internal Signal Definition 77 | // For Write access 78 | reg activate_cebar=0,activate_webar,activate_wecebar=0; 79 | reg initiate_write1,initiate_write2,initiate_write3; 80 | reg WE_dly; 81 | reg [19:0] Address_write1,Address_write2; 82 | reg [7:0] dummy_array0 [1048575:0]; 83 | reg [15:8] dummy_array1 [1048575:0]; 84 | reg [7:0] mem_array0 [1048575:0]; 85 | reg [15:8] mem_array1 [1048575:0]; 86 | reg [15:0] dataIO1; 87 | 88 | //For Read Access 89 | reg [15:0] data_read; 90 | reg [19:0] Address_read1,Address_read2 ; 91 | reg initiate_read1,initiate_read2; 92 | 93 | 94 | 95 | //Intializing values 96 | 97 | initial 98 | begin 99 | // write timings -- 10ns address access time 100 | twc = 10 ; 101 | tcw = 7 ; 102 | taw = 7 ; 103 | tas = 0 ; 104 | twp1 = 7 ; 105 | twp2 = 10 ; 106 | twr = 0 ; 107 | tah = 0 ; 108 | tdw = 5 ; 109 | tdh =0 ; 110 | twz = 5 ; 111 | tow = 3 ; 112 | tbw = 7 ; 113 | // Read timings -- 10ns address access time 114 | trc = 10 ; 115 | taa = 10 ; 116 | tace = 10 ; 117 | toe = 4 ; 118 | toh = 3 ; 119 | tclz = 3 ; 120 | tchz = 5 ; 121 | tolz = 0 ; 122 | tohz = 5 ; 123 | tba = 5 ; 124 | tblz = 0 ; 125 | tbhz = 5 ; 126 | tpu = 0 ; 127 | tpd = 10; 128 | // Internal Time signals 129 | 130 | initiate_write1 = 1'b0; 131 | initiate_write2 = 1'b0; 132 | initiate_write3 = 1'b0; 133 | 134 | data_read = 16'hzz; 135 | initiate_read1 =1'b0; 136 | initiate_read2 =1'b0; 137 | read_address_time =0; 138 | 139 | read_address_add=0; 140 | read_address_oe=0; 141 | temptaa = taa; 142 | temptoe = toe; 143 | 144 | end 145 | 146 | 147 | 148 | //********* start Accessing by CE_n low******* 149 | 150 | always@(negedge CE_n) 151 | begin 152 | activate_cebar <= 1'b0; 153 | activate_wecebar<=1'b0; 154 | write_CE_n_start_time <= $time; 155 | read_CE_n_start_time <=$time; 156 | end 157 | 158 | //**** Write Access ************* 159 | 160 | //****** CE_n controlled *********** 161 | always@(posedge CE_n) 162 | begin 163 | if (($time - write_CE_n_start_time) >= tcw) 164 | begin 165 | if ( (WE_n == 1'b0) && ( ($time - write_WE_n_start_time) >=twp1) ) 166 | begin 167 | Address_write2 <= Address_write1; 168 | dummy_array0[Address_write1] <= dataIO1[7:0]; 169 | dummy_array1[Address_write1] <= dataIO1[15:8] ; 170 | activate_cebar <= 1'b1; 171 | end 172 | else 173 | activate_cebar <= 1'b0; 174 | end 175 | else 176 | begin 177 | activate_cebar <= 1'b0; 178 | end 179 | end 180 | 181 | 182 | //***** UB_n/LB_n change ********* 183 | 184 | always @(negedge UB_n) 185 | begin 186 | UB_n_start_time <= $time; 187 | end 188 | 189 | always @(negedge LB_n) 190 | begin 191 | LB_n_start_time <= $time; 192 | end 193 | 194 | //***** WE_n controlled ********** 195 | 196 | always @(negedge WE_n) 197 | begin 198 | activate_webar <= 1'b0; 199 | activate_wecebar<=1'b0; 200 | write_WE_n_start_time <= $time; 201 | #twz WE_dly <= WE_n; 202 | end 203 | 204 | always @(posedge WE_n ) 205 | begin 206 | WE_dly <= WE_n; 207 | read_WE_n_start_time <=$time; 208 | if (($time - write_WE_n_start_time) >=twp1) 209 | begin 210 | if ( (CE_n == 1'b0) && ( ($time - write_CE_n_start_time) >= tcw) ) 211 | begin 212 | Address_write2 <= Address_write1; 213 | dummy_array0[Address_write1] <= dataIO1[7:0]; 214 | dummy_array1[Address_write1] <= dataIO1[15:8] ; 215 | activate_webar <= 1'b1; 216 | end 217 | else 218 | activate_webar <= 1'b0; 219 | end 220 | else 221 | begin 222 | activate_webar <= 1'b0; 223 | end 224 | end 225 | 226 | //******* WE_n & CE_n controlled ( If both comes to high at the same time)********** 227 | always @(CE_n && WE_n) 228 | begin 229 | if ( (CE_n ==1'b1) && (WE_n ==1'b1) ) 230 | begin 231 | if ( ( ($time - write_WE_n_start_time) >=twp1) && (($time-write_CE_n_start_time) >=tcw)) 232 | begin 233 | Address_write2 <= Address_write1; 234 | dummy_array0[Address_write1] <= dataIO1[7:0]; 235 | dummy_array1[Address_write1] <= dataIO1[15:8] ; 236 | activate_webar <= 1'b1; 237 | end 238 | else 239 | activate_wecebar <= 1'b0 ; 240 | end 241 | else 242 | activate_wecebar <=1'b0; 243 | end 244 | 245 | 246 | 247 | always@(CE_n or WE_n or OE_n or Address or DataIO ) 248 | begin 249 | if ((CE_n==1'b0) && (WE_n ==1'b0)) 250 | begin 251 | Address_write1 <= Address; 252 | Address_write2 <= Address_write1; 253 | dataIO1 <= DataIO; 254 | dummy_array0[Address_write1] <= dataIO1[7:0] ; 255 | dummy_array1[Address_write1] <= dataIO1[15:8] ; 256 | end 257 | end 258 | 259 | 260 | //********* DATAIO changes before write completion, then New write(2) initation ************** 261 | 262 | always @(DataIO) 263 | begin 264 | write_data_time <= $time; 265 | write_data1_time <=write_data_time; 266 | write_WE_n_start_time1 <=$time; 267 | write_CE_n_start_time1 <=$time; 268 | if ( ($time - write_data_time) >= tdw) 269 | begin 270 | if ( (WE_n == 1'b0) && (CE_n == 1'b0)) 271 | begin 272 | if ( ( ($time - write_CE_n_start_time) >=tcw) && ( ($time - write_WE_n_start_time) >=twp1) && (($time - write_address_time) >=twc) ) 273 | initiate_write2 <= 1'b1; 274 | else 275 | initiate_write2 <= 1'b0; 276 | end 277 | end 278 | end 279 | 280 | 281 | //******* Address changes before write completion, then New write(3) initation************************* 282 | 283 | 284 | always @(Address) 285 | begin 286 | write_address_time <= $time; 287 | write_address1_time <= write_address_time; 288 | write_WE_n_start_time1 <=$time; 289 | write_CE_n_start_time1 <=$time; 290 | if ( ($time - write_address_time) >= twc) 291 | begin 292 | if ( (WE_n == 1'b0) && (CE_n ==1'b0)) 293 | begin 294 | if ( ( ($time - write_CE_n_start_time) >=tcw) && ( ($time - write_WE_n_start_time) >=twp1) && (($time - write_data_time) >=tdw) ) 295 | initiate_write3 <= 1'b1; 296 | else 297 | initiate_write3 <= 1'b0; 298 | end 299 | else 300 | initiate_write3 <= 1'b0; 301 | end 302 | else 303 | initiate_write3 <= 1'b0; 304 | end 305 | 306 | 307 | //******* activate_cebar or activate_webar or ini_weceba goes high - initiate write access ************** 308 | 309 | always@(activate_cebar or activate_webar or activate_wecebar) 310 | begin 311 | if ( (activate_cebar == 1'b1) || (activate_webar == 1'b1) || (activate_wecebar == 1'b1) ) 312 | begin 313 | if ( ( ($time - write_data1_time) >= tdw) && ( ($time - write_address1_time) >= twc) ) 314 | initiate_write1 <= 1'b1; 315 | else 316 | initiate_write1 <= 1'b0; 317 | end 318 | else 319 | initiate_write1 <= 1'b0; 320 | end 321 | 322 | 323 | 324 | //***** Write completion (Writing into mem_arrayx[][]) *********** 325 | 326 | always@( initiate_write1 ) 327 | begin 328 | if ( ( ($time - write_WE_n_start_time) >=twp1) && ( ($time - write_CE_n_start_time) >=tcw) ) 329 | begin 330 | if(UB_n == 1'b0 && (($time - UB_n_start_time) >= tbw)) 331 | begin 332 | mem_array1[Address_write2] <= dummy_array1[Address_write2]; 333 | end 334 | if (LB_n == 1'b0 && (($time - LB_n_start_time) >= tbw)) 335 | begin 336 | mem_array0[Address_write2] <= dummy_array0[Address_write2]; 337 | end 338 | end 339 | initiate_write1 <=1'b0; 340 | end 341 | 342 | always @(initiate_write2 ) 343 | begin 344 | if ( ( ($time - write_WE_n_start_time) >=twp1) && ( ($time - write_CE_n_start_time) >=tcw)) 345 | begin 346 | if(UB_n == 1'b0 && (($time - UB_n_start_time) >= tbw)) 347 | begin 348 | mem_array1[Address_write2] <= dummy_array1[Address_write2]; 349 | end 350 | if (LB_n == 1'b0 && (($time - LB_n_start_time) >= tbw)) 351 | begin 352 | mem_array0[Address_write2] <= dummy_array0[Address_write2]; 353 | end 354 | end 355 | 356 | if ( (initiate_write2==1'b1)) 357 | begin 358 | initiate_write2 <=1'b0; 359 | end 360 | end 361 | 362 | always @(initiate_write3 ) 363 | begin 364 | if ( ( ($time - write_WE_n_start_time) >=twp1) && ( ($time - write_CE_n_start_time) >=tcw)) 365 | begin 366 | if(UB_n == 1'b0 && (($time - UB_n_start_time) >= tbw)) 367 | begin 368 | mem_array1[Address_write2] <= dummy_array1[Address_write2]; 369 | end 370 | if (LB_n == 1'b0 && (($time - LB_n_start_time) >= tbw)) 371 | begin 372 | mem_array0[Address_write2] <= dummy_array0[Address_write2]; 373 | end 374 | end 375 | 376 | if ( (initiate_write3==1'b1)) 377 | begin 378 | initiate_write3 <=1'b0; 379 | end 380 | end 381 | 382 | //****** Read Access ******************** 383 | 384 | //******** Address transition initiates the Read access ******** 385 | always@(Address) // Address change exactly =trc 386 | begin 387 | read_address_time <=$time; 388 | Address_read1 <=Address; 389 | Address_read2 <=Address_read1; 390 | if ( ($time - read_address_time) == trc) 391 | begin 392 | if ( (CE_n == 1'b0) && (WE_n == 1'b1) ) 393 | initiate_read1 <= 1'b1; 394 | else 395 | initiate_read1 <= 1'b0; 396 | end 397 | else 398 | initiate_read1 <= 1'b0; 399 | end 400 | 401 | //***** Address valid long time(>=trc)************* 402 | 403 | always #1 404 | begin 405 | if ( ($time - read_address_time) >= trc) 406 | begin 407 | 408 | if ( (CE_n == 1'b0) && (WE_n == 1'b1) ) 409 | begin 410 | Address_read2 <=Address_read1; 411 | initiate_read2 <= 1'b1; 412 | end 413 | else 414 | initiate_read2 <= 1'b0; 415 | end 416 | else 417 | initiate_read2 <= 1'b0; 418 | end 419 | 420 | //********** Register time when OE_n goes low ****** 421 | 422 | always @(negedge OE_n) 423 | begin 424 | read_OE_n_start_time <= $time; 425 | data_read <= 16'bz; 426 | end 427 | 428 | //***** Data drive to data_read when $time >= taa & tace & trc (all are having same times) ****** 429 | 430 | always@(initiate_read1 or initiate_read2) 431 | begin 432 | if ( (initiate_read1 == 1'b1) || (initiate_read2 == 1'b1) ) 433 | begin 434 | if ( (CE_n == 1'b0) && (WE_n ==1'b1)) 435 | begin 436 | if ( ( ($time - read_WE_n_start_time) >=trc) && ( ($time -read_CE_n_start_time) >=tace) && ( ($time - read_OE_n_start_time) >=toe)) 437 | begin 438 | if((LB_n == 1'b0) && (($time - LB_n_start_time) >= tba)) 439 | data_read[7:0] <= mem_array0[Address_read2]; 440 | else 441 | data_read[7:0] <= 8'bzz; 442 | if((UB_n == 1'b0) && ( ($time - UB_n_start_time) >= tba)) 443 | data_read[15:8] <= mem_array1[Address_read2]; 444 | else 445 | data_read[15:8] <= 8'bzz; 446 | end 447 | end 448 | else 449 | #toh data_read <=16'hzzzz; 450 | end 451 | initiate_read1 <=1'b0; 452 | initiate_read2 <=1'b0; 453 | end 454 | 455 | 456 | 457 | //********** Driving DataIO during OE_n low ********* 458 | 459 | wire [15:0] DataIO = (!OE_n && WE_dly) ? data_read[15:0] : 16'bz ; 460 | 461 | 462 | //******* simultion Finish by `tsim *********** 463 | //initial # `tsim $finish; 464 | 465 | 466 | 467 | endmodule 468 | 469 | -------------------------------------------------------------------------------- /thinpad_top.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 206 | 207 | 208 | 209 | 210 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 225 | 226 | 227 | 228 | 229 | 232 | 233 | 235 | 236 | 238 | 239 | 241 | 242 | 244 | 245 | 247 | 248 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | default_dashboard 331 | 332 | 333 | 334 | 335 | 336 | 337 | -------------------------------------------------------------------------------- /thinpad_top.srcs/constrs_1/new/thinpad_top.xdc: -------------------------------------------------------------------------------- 1 | #Clock 2 | set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports clk_50M] ;#50MHz main clock in 3 | set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports clk_11M0592] ;#11.0592MHz clock for UART 4 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_11M0592_IBUF] 5 | 6 | create_clock -period 20.000 -name clk_50M -waveform {0.000 10.000} [get_ports clk_50M] 7 | create_clock -period 90.422 -name clk_11M0592 -waveform {0.000 45.211} [get_ports clk_11M0592] 8 | 9 | #Touch Button 10 | set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS33} [get_ports touch_btn[0]] ;#BTN1 11 | set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS33} [get_ports touch_btn[1]] ;#BTN2 12 | set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS33} [get_ports touch_btn[2]] ;#BTN3 13 | set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS33} [get_ports touch_btn[3]] ;#BTN4 14 | set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports clock_btn] ;#BTN5 15 | set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports reset_btn] ;#BTN6 16 | 17 | #required if touch button used as manual clock source 18 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clock_btn_IBUF] 19 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_btn_IBUF] 20 | 21 | #CPLD 22 | set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS33} [get_ports {uart_wrn}] 23 | set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {uart_rdn}] 24 | set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports {uart_tbre}] 25 | set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports {uart_tsre}] 26 | set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports {uart_dataready}] 27 | 28 | #Ext serial 29 | set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN L19} [get_ports txd] ;#GPIO5 30 | set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN K21} [get_ports rxd] ;#GPIO6 31 | 32 | #USB 33 | set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports sl811_a0] 34 | set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports sl811_wr_n] 35 | set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports sl811_rd_n] 36 | set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports sl811_cs_n] 37 | set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports sl811_rst_n] 38 | set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports sl811_drq_n] 39 | set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS33} [get_ports sl811_dack_n] 40 | set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports sl811_intrq] 41 | 42 | #Ethernet 43 | set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports dm9k_iow_n] 44 | set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports dm9k_ior_n] 45 | set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports dm9k_cs_n] 46 | set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports dm9k_pwrst_n] 47 | set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports dm9k_int] 48 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports dm9k_cmd] 49 | set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[0]}] 50 | set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[1]}] 51 | set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[2]}] 52 | set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[3]}] 53 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[4]}] 54 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[5]}] 55 | set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[6]}] 56 | set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[7]}] 57 | set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[8]}] 58 | set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[9]}] 59 | set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[10]}] 60 | set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[11]}] 61 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[12]}] 62 | set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[13]}] 63 | set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[14]}] 64 | set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {dm9k_sd[15]}] 65 | 66 | #Digital Video 67 | set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports video_clk] 68 | set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports {video_red[2]}] 69 | set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {video_red[1]}] 70 | set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {video_red[0]}] 71 | set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {video_green[2]}] 72 | set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports {video_green[1]}] 73 | set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {video_green[0]}] 74 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {video_blue[1]}] 75 | set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {video_blue[0]}] 76 | set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports video_hsync] 77 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports video_vsync] 78 | set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports video_de] 79 | 80 | #LEDS 81 | set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {leds[0]}] 82 | set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {leds[1]}] 83 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {leds[2]}] 84 | set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {leds[3]}] 85 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {leds[4]}] 86 | set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {leds[5]}] 87 | set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {leds[6]}] 88 | set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33} [get_ports {leds[7]}] 89 | set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {leds[8]}] 90 | set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports {leds[9]}] 91 | set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {leds[10]}] 92 | set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {leds[11]}] 93 | set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {leds[12]}] 94 | set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {leds[13]}] 95 | set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {leds[14]}] 96 | set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {leds[15]}] 97 | 98 | #DPY0 99 | set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports {dpy0[0]}] 100 | set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {dpy0[1]}] 101 | set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {dpy0[2]}] 102 | set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {dpy0[3]}] 103 | set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {dpy0[4]}] 104 | set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {dpy0[5]}] 105 | set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports {dpy0[6]}] 106 | set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS33} [get_ports {dpy0[7]}] 107 | 108 | #DPY1 109 | set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS33} [get_ports {dpy1[0]}] 110 | set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports {dpy1[1]}] 111 | set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports {dpy1[2]}] 112 | set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {dpy1[3]}] 113 | set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports {dpy1[4]}] 114 | set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {dpy1[5]}] 115 | set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {dpy1[6]}] 116 | set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS33} [get_ports {dpy1[7]}] 117 | 118 | #DIP_SW 119 | set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[0]}] 120 | set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[1]}] 121 | set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[2]}] 122 | set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[3]}] 123 | set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[4]}] 124 | set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[5]}] 125 | set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dip_sw[6]}] 126 | set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dip_sw[7]}] 127 | set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[8]}] 128 | set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[9]}] 129 | set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[10]}] 130 | set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[11]}] 131 | set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[12]}] 132 | set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[13]}] 133 | set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports {dip_sw[14]}] 134 | set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_sw[15]}] 135 | set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[16]}] 136 | set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[17]}] 137 | set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[18]}] 138 | set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[19]}] 139 | set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[20]}] 140 | set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {dip_sw[21]}] 141 | set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[22]}] 142 | set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_sw[23]}] 143 | set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[24]}] 144 | set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[25]}] 145 | set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS33} [get_ports {dip_sw[26]}] 146 | set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS33} [get_ports {dip_sw[27]}] 147 | set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {dip_sw[28]}] 148 | set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[29]}] 149 | set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports {dip_sw[30]}] 150 | set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {dip_sw[31]}] 151 | 152 | set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS33} [get_ports {flash_a[0]}] 153 | set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS33} [get_ports {flash_a[1]}] 154 | set_property -dict {PACKAGE_PIN B26 IOSTANDARD LVCMOS33} [get_ports {flash_a[2]}] 155 | set_property -dict {PACKAGE_PIN B25 IOSTANDARD LVCMOS33} [get_ports {flash_a[3]}] 156 | set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS33} [get_ports {flash_a[4]}] 157 | set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS33} [get_ports {flash_a[5]}] 158 | set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS33} [get_ports {flash_a[6]}] 159 | set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports {flash_a[7]}] 160 | set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports {flash_a[8]}] 161 | set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports {flash_a[9]}] 162 | set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports {flash_a[10]}] 163 | set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS33} [get_ports {flash_a[11]}] 164 | set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports {flash_a[12]}] 165 | set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports {flash_a[13]}] 166 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports {flash_a[14]}] 167 | set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {flash_a[15]}] 168 | set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports {flash_a[16]}] 169 | set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports {flash_a[17]}] 170 | set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {flash_a[18]}] 171 | set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {flash_a[19]}] 172 | set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {flash_a[20]}] 173 | set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {flash_a[21]}] 174 | set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {flash_a[22]}] 175 | 176 | set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS33} [get_ports {flash_d[0]}] 177 | set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {flash_d[1]}] 178 | set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports {flash_d[2]}] 179 | set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {flash_d[3]}] 180 | set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {flash_d[4]}] 181 | set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {flash_d[5]}] 182 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {flash_d[6]}] 183 | set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS33} [get_ports {flash_d[7]}] 184 | set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS33} [get_ports {flash_d[8]}] 185 | set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {flash_d[9]}] 186 | set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {flash_d[10]}] 187 | set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {flash_d[11]}] 188 | set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS33} [get_ports {flash_d[12]}] 189 | set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {flash_d[13]}] 190 | set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {flash_d[14]}] 191 | set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {flash_d[15]}] 192 | 193 | set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS33} [get_ports flash_byte_n] 194 | set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports flash_ce_n] 195 | set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports flash_oe_n] 196 | set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports flash_rp_n] 197 | set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports flash_vpen] 198 | set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports flash_we_n] 199 | 200 | set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[0]}] 201 | set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[1]}] 202 | set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[2]}] 203 | set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[3]}] 204 | set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[4]}] 205 | set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[5]}] 206 | set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[6]}] 207 | set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[7]}] 208 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[8]}] 209 | set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[9]}] 210 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[10]}] 211 | set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[11]}] 212 | set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[12]}] 213 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[13]}] 214 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[14]}] 215 | set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[15]}] 216 | set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[16]}] 217 | set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[17]}] 218 | set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[18]}] 219 | set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {base_ram_addr[19]}] 220 | set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[0]}] 221 | set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[1]}] 222 | set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[2]}] 223 | set_property -dict {PACKAGE_PIN D25 IOSTANDARD LVCMOS33} [get_ports {base_ram_be_n[3]}] 224 | set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[0]}] 225 | set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[1]}] 226 | set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[2]}] 227 | set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[3]}] 228 | set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[4]}] 229 | set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[5]}] 230 | set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[6]}] 231 | set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[7]}] 232 | set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[8]}] 233 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[9]}] 234 | set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[10]}] 235 | set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[11]}] 236 | set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[12]}] 237 | set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[13]}] 238 | set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[14]}] 239 | set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[15]}] 240 | set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[16]}] 241 | set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[17]}] 242 | set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[18]}] 243 | set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[19]}] 244 | set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[20]}] 245 | set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[21]}] 246 | set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[22]}] 247 | set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[23]}] 248 | set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[24]}] 249 | set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[25]}] 250 | set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[26]}] 251 | set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[27]}] 252 | set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[28]}] 253 | set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[29]}] 254 | set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[30]}] 255 | set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS33} [get_ports {base_ram_data[31]}] 256 | set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports base_ram_ce_n] 257 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports base_ram_oe_n] 258 | set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS33} [get_ports base_ram_we_n] 259 | 260 | set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[0]}] 261 | set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[1]}] 262 | set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[2]}] 263 | set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[3]}] 264 | set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[4]}] 265 | set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[5]}] 266 | set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[6]}] 267 | set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[7]}] 268 | set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[8]}] 269 | set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[9]}] 270 | set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[10]}] 271 | set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[11]}] 272 | set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[12]}] 273 | set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[13]}] 274 | set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[14]}] 275 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[15]}] 276 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[16]}] 277 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[17]}] 278 | set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[18]}] 279 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {ext_ram_addr[19]}] 280 | set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[0]}] 281 | set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[1]}] 282 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[2]}] 283 | set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_be_n[3]}] 284 | set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[0]}] 285 | set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[1]}] 286 | set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[2]}] 287 | set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[3]}] 288 | set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[4]}] 289 | set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[5]}] 290 | set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[6]}] 291 | set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[7]}] 292 | set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[8]}] 293 | set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[9]}] 294 | set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[10]}] 295 | set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[11]}] 296 | set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[12]}] 297 | set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[13]}] 298 | set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[14]}] 299 | set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[15]}] 300 | set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[16]}] 301 | set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[17]}] 302 | set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[18]}] 303 | set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[19]}] 304 | set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[20]}] 305 | set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[21]}] 306 | set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[22]}] 307 | set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[23]}] 308 | set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[24]}] 309 | set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[25]}] 310 | set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[26]}] 311 | set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[27]}] 312 | set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[28]}] 313 | set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[29]}] 314 | set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[30]}] 315 | set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {ext_ram_data[31]}] 316 | set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports ext_ram_ce_n] 317 | set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports ext_ram_oe_n] 318 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports ext_ram_we_n] 319 | 320 | set_property CFGBVS VCCO [current_design] 321 | set_property CONFIG_VOLTAGE 3.3 [current_design] 322 | 323 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | pll_example 10 | 11 | 12 | false 13 | 100000000 14 | false 15 | 100000000 16 | false 17 | 100000000 18 | false 19 | 100000000 20 | 21 | 22 | 23 | 100000000 24 | 0 25 | 0.000 26 | 27 | 28 | 29 | 100000000 30 | 0 31 | 0.000 32 | 33 | 34 | 35 | 100000000 36 | 0 37 | 0.000 38 | 1 39 | LEVEL_HIGH 40 | 41 | 42 | 43 | 100000000 44 | 0 45 | 0.000 46 | 0 47 | 0 48 | 49 | 100000000 50 | 0 51 | 0.000 52 | 1 53 | 0 54 | 0 55 | 0 56 | 57 | 1 58 | 100000000 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 0 65 | 0 66 | 0 67 | 0 68 | 0 69 | 0 70 | 1 71 | 1 72 | 1 73 | 1 74 | 1 75 | 0.000 76 | AXI4LITE 77 | READ_WRITE 78 | 0 79 | 0 80 | 0 81 | 0 82 | 0 83 | 0 84 | MMCM 85 | cddcdone 86 | cddcreq 87 | 0000 88 | 0000 89 | clkfb_in_n 90 | clkfb_in 91 | clkfb_in_p 92 | SINGLE 93 | clkfb_out_n 94 | clkfb_out 95 | clkfb_out_p 96 | clkfb_stopped 97 | 200.0 98 | 100.0 99 | 0000 100 | 0000 101 | 10.000 102 | 0000 103 | 0000 104 | 20.000 105 | BUFG 106 | 50.0 107 | false 108 | 10.000 109 | 0.000 110 | 50.000 111 | 10 112 | 0.000 113 | 1 114 | 0000 115 | 0000 116 | 100.000 117 | BUFG 118 | 50.0 119 | false 120 | 20.000 121 | 0.000 122 | 50.000 123 | 20 124 | 0.000 125 | 1 126 | 1 127 | 0000 128 | 0000 129 | 100.000 130 | BUFG 131 | 50.000 132 | false 133 | 100.000 134 | 0.000 135 | 50.000 136 | 100.000 137 | 0.000 138 | 1 139 | 0 140 | 0000 141 | 0000 142 | 100.000 143 | BUFG 144 | 50.000 145 | false 146 | 100.000 147 | 0.000 148 | 50.000 149 | 100.000 150 | 0.000 151 | 1 152 | 0 153 | 0000 154 | 0000 155 | 100.000 156 | BUFG 157 | 50.000 158 | false 159 | 100.000 160 | 0.000 161 | 50.000 162 | 100.000 163 | 0.000 164 | 1 165 | 0 166 | 0000 167 | 0000 168 | 100.000 169 | BUFG 170 | 50.000 171 | false 172 | 100.000 173 | 0.000 174 | 50.000 175 | 100.000 176 | 0.000 177 | 1 178 | 0 179 | BUFG 180 | 50.000 181 | false 182 | 100.000 183 | 0.000 184 | 50.000 185 | 100.000 186 | 0.000 187 | 1 188 | 0 189 | VCO 190 | clk_in_sel 191 | clk_out1 192 | clk_out2 193 | clk_out3 194 | clk_out4 195 | clk_out5 196 | clk_out6 197 | clk_out7 198 | CLK_VALID 199 | NA 200 | daddr 201 | dclk 202 | den 203 | din 204 | 0000 205 | 1 206 | 0.5 207 | 0.1 208 | 0.1 209 | 0.1 210 | 0.1 211 | 0.1 212 | dout 213 | drdy 214 | dwe 215 | 0 216 | 0 217 | 0 218 | 0 219 | 0 220 | 0 221 | 0 222 | 0 223 | FDBK_AUTO 224 | 0000 225 | 0000 226 | 0 227 | Input Clock Freq (MHz) Input Jitter (UI) 228 | __primary______________50____________0.010 229 | no_secondary_input_clock 230 | input_clk_stopped 231 | 0 232 | Units_MHz 233 | No_Jitter 234 | locked 235 | 0000 236 | 0000 237 | 0000 238 | false 239 | false 240 | false 241 | false 242 | false 243 | false 244 | false 245 | false 246 | OPTIMIZED 247 | 20.000 248 | 0.000 249 | FALSE 250 | 20.000 251 | 10.0 252 | 100.000 253 | 0.500 254 | 0.000 255 | FALSE 256 | 50 257 | 0.500 258 | 0.000 259 | FALSE 260 | 1 261 | 0.500 262 | 0.000 263 | FALSE 264 | 1 265 | 0.500 266 | 0.000 267 | FALSE 268 | FALSE 269 | 1 270 | 0.500 271 | 0.000 272 | FALSE 273 | 1 274 | 0.500 275 | 0.000 276 | FALSE 277 | 1 278 | 0.500 279 | 0.000 280 | FALSE 281 | FALSE 282 | ZHOLD 283 | 1 284 | None 285 | 0.010 286 | 0.010 287 | FALSE 288 | 2 289 | Output Output Phase Duty Cycle Pk-to-Pk Phase 290 | Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 291 | clk_out1____10.000______0.000______50.0______285.743____164.985 292 | clk_out2____20.000______0.000______50.0______249.363____164.985 293 | no_CLK_OUT3_output 294 | no_CLK_OUT4_output 295 | no_CLK_OUT5_output 296 | no_CLK_OUT6_output 297 | no_CLK_OUT7_output 298 | 0 299 | 0 300 | WAVEFORM 301 | UNKNOWN 302 | false 303 | false 304 | false 305 | false 306 | false 307 | OPTIMIZED 308 | 1 309 | 0.000 310 | 1.000 311 | 1 312 | 0.500 313 | 0.000 314 | 1 315 | 0.500 316 | 0.000 317 | 1 318 | 0.500 319 | 0.000 320 | 1 321 | 0.500 322 | 0.000 323 | 1 324 | 0.500 325 | 0.000 326 | 1 327 | 0.500 328 | 0.000 329 | CLKFBOUT 330 | SYSTEM_SYNCHRONOUS 331 | 1 332 | No notes 333 | 0.010 334 | power_down 335 | 0000 336 | 1 337 | clk_in1 338 | MMCM 339 | AUTO 340 | 50 341 | 0.010 342 | 10.000 343 | Single_ended_clock_capable_pin 344 | psclk 345 | psdone 346 | psen 347 | psincdec 348 | 100.0 349 | 0 350 | reset 351 | 100.000 352 | 0.010 353 | 10.000 354 | clk_in2 355 | Single_ended_clock_capable_pin 356 | CENTER_HIGH 357 | 4000 358 | 0.004 359 | STATUS 360 | 11 361 | 32 362 | 100.0 363 | 100.0 364 | 100.0 365 | 100.0 366 | 0 367 | 0 368 | 0 369 | 0 370 | 0 371 | 0 372 | 0 373 | 0 374 | 0 375 | 0 376 | 0 377 | 1 378 | 0 379 | 0 380 | 1 381 | 0 382 | 0 383 | 0 384 | 1 385 | 0 386 | 1 387 | 0 388 | 0 389 | 0 390 | pll_example 391 | MMCM 392 | false 393 | empty 394 | cddcdone 395 | cddcreq 396 | clkfb_in_n 397 | clkfb_in 398 | clkfb_in_p 399 | SINGLE 400 | clkfb_out_n 401 | clkfb_out 402 | clkfb_out_p 403 | clkfb_stopped 404 | 200.0 405 | 0.010 406 | 100.0 407 | 0.010 408 | BUFG 409 | 285.743 410 | false 411 | 164.985 412 | 50.000 413 | 10 414 | 0.000 415 | 1 416 | true 417 | BUFG 418 | 249.363 419 | false 420 | 164.985 421 | 50.000 422 | 20 423 | 0.000 424 | 1 425 | true 426 | BUFG 427 | 0.0 428 | false 429 | 0.0 430 | 50.000 431 | 100.000 432 | 0.000 433 | 1 434 | false 435 | BUFG 436 | 0.0 437 | false 438 | 0.0 439 | 50.000 440 | 100.000 441 | 0.000 442 | 1 443 | false 444 | BUFG 445 | 0.0 446 | false 447 | 0.0 448 | 50.000 449 | 100.000 450 | 0.000 451 | 1 452 | false 453 | BUFG 454 | 0.0 455 | false 456 | 0.0 457 | 50.000 458 | 100.000 459 | 0.000 460 | 1 461 | false 462 | BUFG 463 | 0.0 464 | false 465 | 0.0 466 | 50.000 467 | 100.000 468 | 0.000 469 | 1 470 | false 471 | 600.000 472 | Custom 473 | Custom 474 | clk_in_sel 475 | clk_out1 476 | false 477 | clk_out2 478 | false 479 | clk_out3 480 | false 481 | clk_out4 482 | false 483 | clk_out5 484 | false 485 | clk_out6 486 | false 487 | clk_out7 488 | false 489 | CLK_VALID 490 | auto 491 | pll_example 492 | daddr 493 | dclk 494 | den 495 | Custom 496 | Custom 497 | din 498 | dout 499 | drdy 500 | dwe 501 | false 502 | false 503 | false 504 | false 505 | false 506 | false 507 | false 508 | false 509 | false 510 | FDBK_AUTO 511 | input_clk_stopped 512 | frequency 513 | Enable_AXI 514 | Units_MHz 515 | Units_UI 516 | UI 517 | No_Jitter 518 | locked 519 | OPTIMIZED 520 | 20.000 521 | 0.000 522 | false 523 | 20.000 524 | 10.0 525 | 100.000 526 | 0.500 527 | 0.000 528 | false 529 | 50 530 | 0.500 531 | 0.000 532 | false 533 | 1 534 | 0.500 535 | 0.000 536 | false 537 | 1 538 | 0.500 539 | 0.000 540 | false 541 | false 542 | 1 543 | 0.500 544 | 0.000 545 | false 546 | 1 547 | 0.500 548 | 0.000 549 | false 550 | 1 551 | 0.500 552 | 0.000 553 | false 554 | false 555 | ZHOLD 556 | 1 557 | None 558 | 0.010 559 | 0.010 560 | false 561 | 2 562 | false 563 | false 564 | WAVEFORM 565 | false 566 | UNKNOWN 567 | OPTIMIZED 568 | 4 569 | 0.000 570 | 10.000 571 | 1 572 | 0.500 573 | 0.000 574 | 1 575 | 0.500 576 | 0.000 577 | 1 578 | 0.500 579 | 0.000 580 | 1 581 | 0.500 582 | 0.000 583 | 1 584 | 0.500 585 | 0.000 586 | 1 587 | 0.500 588 | 0.000 589 | CLKFBOUT 590 | SYSTEM_SYNCHRONOUS 591 | 1 592 | None 593 | 0.010 594 | power_down 595 | 1 596 | clk_in1 597 | MMCM 598 | mmcm_adv 599 | 50 600 | 0.010 601 | 10.000 602 | Single_ended_clock_capable_pin 603 | psclk 604 | psdone 605 | psen 606 | psincdec 607 | 100.0 608 | REL_PRIMARY 609 | Custom 610 | reset 611 | ACTIVE_HIGH 612 | 100.000 613 | 0.010 614 | 10.000 615 | clk_in2 616 | Single_ended_clock_capable_pin 617 | CENTER_HIGH 618 | 250 619 | 0.004 620 | STATUS 621 | empty 622 | 100.0 623 | 100.0 624 | 100.0 625 | 100.0 626 | false 627 | false 628 | false 629 | false 630 | false 631 | false 632 | false 633 | true 634 | false 635 | false 636 | true 637 | false 638 | false 639 | false 640 | true 641 | false 642 | true 643 | false 644 | false 645 | false 646 | artix7 647 | 648 | 649 | xc7a100t 650 | fgg676 651 | VERILOG 652 | 653 | MIXED 654 | -2L 655 | E 656 | TRUE 657 | TRUE 658 | IP_Flow 659 | 2 660 | TRUE 661 | . 662 | 663 | . 664 | 2018.3 665 | OUT_OF_CONTEXT 666 | 667 | 668 | 669 | 670 | 671 | 672 | 673 | 674 | 675 | 676 | 677 | 678 | 679 | 680 | 681 | 682 | 683 | 684 | 685 | 686 | 687 | 688 | 689 | 690 | 691 | 692 | 693 | 694 | 695 | 696 | 697 | 698 | 699 | 700 | 701 | 702 | 703 | 704 | 705 | 706 | 707 | 708 | 709 | 710 | --------------------------------------------------------------------------------