├── sim ├── apb │ ├── veryl │ │ ├── makefile │ │ ├── block_0.veryl │ │ ├── block_1.veryl │ │ ├── local.mk │ │ ├── apb_bridge.veryl │ │ └── Veryl.toml │ ├── vhdl │ │ ├── makefile │ │ └── local.mk │ ├── verilog │ │ ├── makefile │ │ └── local.mk │ ├── systemverilog │ │ ├── makefile │ │ └── local.mk │ └── makefile ├── avalon │ ├── makefile │ ├── verilog │ │ ├── makefile │ │ └── local.mk │ ├── veryl │ │ ├── makefile │ │ ├── block_0.veryl │ │ ├── block_1.veryl │ │ ├── local.mk │ │ ├── avalon_bridge.veryl │ │ └── Veryl.toml │ ├── vhdl │ │ ├── makefile │ │ └── local.mk │ └── systemverilog │ │ ├── makefile │ │ └── local.mk ├── axi4lite │ ├── makefile │ ├── veryl │ │ ├── makefile │ │ ├── block_0.veryl │ │ ├── block_1.veryl │ │ ├── local.mk │ │ ├── Veryl.toml │ │ └── axi4lite_bridge.veryl │ ├── vhdl │ │ ├── makefile │ │ └── local.mk │ ├── verilog │ │ ├── makefile │ │ └── local.mk │ └── systemverilog │ │ ├── makefile │ │ └── local.mk ├── native │ ├── makefile │ ├── verilog │ │ ├── makefile │ │ └── local.mk │ ├── veryl │ │ ├── makefile │ │ ├── block_0.veryl │ │ ├── block_1.veryl │ │ ├── local.mk │ │ └── Veryl.toml │ ├── vhdl │ │ ├── makefile │ │ └── local.mk │ └── systemverilog │ │ ├── makefile │ │ └── local.mk ├── wishbone │ ├── makefile │ ├── veryl │ │ ├── makefile │ │ ├── block_0.veryl │ │ ├── block_1.veryl │ │ ├── local.mk │ │ ├── Veryl.toml │ │ └── wishbone_bridge.veryl │ ├── vhdl │ │ ├── makefile │ │ └── local.mk │ ├── verilog │ │ ├── makefile │ │ └── local.mk │ └── systemverilog │ │ ├── makefile │ │ └── local.mk ├── dsim.mk ├── vivado.mk ├── xcelium.mk ├── common.mk └── vcs.mk ├── config ├── apb.yml ├── avalon.yml ├── native.yml ├── axi4lite.yml └── wishbone.yml ├── .gitignore ├── env ├── env_ral_model.svh ├── env_sequencer.svh ├── env_configuration.svh ├── env_pkg.sv ├── apb2wishbone_bridge.sv ├── apb_env_pkg.sv ├── compile.rb ├── env.svh ├── axi4lite_env_pkg.sv ├── env_ral_monitor.svh └── ral_test.svh ├── setup_submodules.sh ├── rtl ├── compile.rb ├── apb │ ├── block_1.veryl │ └── block_1.sv ├── avalon │ ├── block_1.veryl │ └── block_1.sv ├── wishbone │ ├── block_1.veryl │ └── block_1.sv ├── axi4lite │ ├── block_1.veryl │ └── block_1.sv └── native │ └── block_1.veryl ├── .gitmodules ├── LICENSE ├── README.md └── ral └── block_1_ral_pkg.sv /sim/apb/veryl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/apb/vhdl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/avalon/makefile: -------------------------------------------------------------------------------- 1 | ../apb/makefile -------------------------------------------------------------------------------- /sim/axi4lite/makefile: -------------------------------------------------------------------------------- 1 | ../apb/makefile -------------------------------------------------------------------------------- /sim/native/makefile: -------------------------------------------------------------------------------- 1 | ../apb/makefile -------------------------------------------------------------------------------- /sim/wishbone/makefile: -------------------------------------------------------------------------------- 1 | ../apb/makefile -------------------------------------------------------------------------------- /sim/apb/verilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/avalon/verilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/avalon/veryl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/avalon/vhdl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/axi4lite/veryl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/axi4lite/vhdl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/native/verilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/native/veryl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/native/vhdl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/wishbone/veryl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/wishbone/vhdl/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/apb/systemverilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/avalon/systemverilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/axi4lite/verilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/native/systemverilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/wishbone/verilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/axi4lite/systemverilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/wishbone/systemverilog/makefile: -------------------------------------------------------------------------------- 1 | ../../common.mk -------------------------------------------------------------------------------- /sim/apb/veryl/block_0.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/apb/block_0.veryl -------------------------------------------------------------------------------- /sim/apb/veryl/block_1.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/apb/block_1.veryl -------------------------------------------------------------------------------- /sim/apb/vhdl/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = apb 2 | LANGUAGE = vhdl 3 | -------------------------------------------------------------------------------- /sim/avalon/veryl/block_0.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/avalon/block_0.veryl -------------------------------------------------------------------------------- /sim/avalon/veryl/block_1.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/avalon/block_1.veryl -------------------------------------------------------------------------------- /sim/native/veryl/block_0.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/native/block_0.veryl -------------------------------------------------------------------------------- /sim/native/veryl/block_1.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/native/block_1.veryl -------------------------------------------------------------------------------- /sim/apb/verilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = apb 2 | LANGUAGE = verilog 3 | -------------------------------------------------------------------------------- /sim/apb/veryl/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = apb 3 | LANGUAGE = veryl 4 | -------------------------------------------------------------------------------- /sim/axi4lite/veryl/block_0.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/axi4lite/block_0.veryl -------------------------------------------------------------------------------- /sim/axi4lite/veryl/block_1.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/axi4lite/block_1.veryl -------------------------------------------------------------------------------- /sim/wishbone/veryl/block_0.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/wishbone/block_0.veryl -------------------------------------------------------------------------------- /sim/wishbone/veryl/block_1.veryl: -------------------------------------------------------------------------------- 1 | ../../../rtl/wishbone/block_1.veryl -------------------------------------------------------------------------------- /sim/avalon/veryl/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = avalon 3 | LANGUAGE = veryl 4 | -------------------------------------------------------------------------------- /sim/avalon/vhdl/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = avalon 3 | LANGUAGE = vhdl 4 | -------------------------------------------------------------------------------- /sim/axi4lite/veryl/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = axi4lite 2 | LANGUAGE = veryl 3 | -------------------------------------------------------------------------------- /sim/axi4lite/vhdl/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = axi4lite 2 | LANGUAGE = vhdl 3 | -------------------------------------------------------------------------------- /sim/avalon/verilog/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = avalon 3 | LANGUAGE = verilog 4 | -------------------------------------------------------------------------------- /sim/axi4lite/verilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = axi4lite 2 | LANGUAGE = verilog 3 | -------------------------------------------------------------------------------- /sim/wishbone/veryl/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = wishbone 3 | LANGUAGE = veryl 4 | -------------------------------------------------------------------------------- /sim/apb/systemverilog/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = apb 3 | LANGUAGE = systemverilog 4 | -------------------------------------------------------------------------------- /config/apb.yml: -------------------------------------------------------------------------------- 1 | bus_width: 32 2 | address_width: 16 3 | protocol: apb 4 | -------------------------------------------------------------------------------- /sim/axi4lite/systemverilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = axi4lite 2 | LANGUAGE = systemverilog 3 | -------------------------------------------------------------------------------- /config/avalon.yml: -------------------------------------------------------------------------------- 1 | bus_width: 32 2 | address_width: 16 3 | protocol: avalon 4 | -------------------------------------------------------------------------------- /config/native.yml: -------------------------------------------------------------------------------- 1 | bus_width: 32 2 | address_width: 16 3 | protocol: native 4 | -------------------------------------------------------------------------------- /sim/avalon/systemverilog/local.mk: -------------------------------------------------------------------------------- 1 | 2 | PROTOCOL = avalon 3 | LANGUAGE = systemverilog 4 | -------------------------------------------------------------------------------- /sim/native/veryl/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = native 2 | ENV_TYPE = apb_env 3 | LANGUAGE = veryl 4 | -------------------------------------------------------------------------------- /sim/native/vhdl/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = native 2 | ENV_TYPE = apb_env 3 | LANGUAGE = vhdl 4 | -------------------------------------------------------------------------------- /sim/wishbone/vhdl/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = wishbone 2 | ENV_TYPE = apb_env 3 | LANGUAGE = vhdl 4 | -------------------------------------------------------------------------------- /config/axi4lite.yml: -------------------------------------------------------------------------------- 1 | bus_width: 32 2 | address_width: 16 3 | protocol: axi4lite 4 | -------------------------------------------------------------------------------- /config/wishbone.yml: -------------------------------------------------------------------------------- 1 | bus_width: 32 2 | address_width: 16 3 | protocol: wishbone 4 | -------------------------------------------------------------------------------- /sim/native/verilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = native 2 | ENV_TYPE = apb_env 3 | LANGUAGE = verilog 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | Veryl.lock 2 | rggen_sample_testbench.list.rb 3 | .build/ 4 | dependencies/ 5 | target/ 6 | -------------------------------------------------------------------------------- /sim/wishbone/verilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = wishbone 2 | ENV_TYPE = apb_env 3 | LANGUAGE = verilog 4 | -------------------------------------------------------------------------------- /sim/native/systemverilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = native 2 | ENV_TYPE = apb_env 3 | LANGUAGE = systemverilog 4 | -------------------------------------------------------------------------------- /sim/wishbone/systemverilog/local.mk: -------------------------------------------------------------------------------- 1 | PROTOCOL = wishbone 2 | ENV_TYPE = apb_env 3 | LANGUAGE = systemverilog 4 | -------------------------------------------------------------------------------- /env/env_ral_model.svh: -------------------------------------------------------------------------------- 1 | class env_ral_model extends block_0_block_model #( 2 | .REGISTER_18 (block_1_block_model ), 3 | .INTEGRATE_REGISTER_18 (1 ) 4 | ); 5 | `tue_object_default_constructor(env_ral_model) 6 | `uvm_object_utils(env_ral_model) 7 | endclass 8 | -------------------------------------------------------------------------------- /env/env_sequencer.svh: -------------------------------------------------------------------------------- 1 | class env_sequencer extends tue_sequencer #( 2 | .CONFIGURATION (env_configuration ) 3 | ); 4 | uvm_sequencer_base bus_sequencer; 5 | env_ral_model model; 6 | `tue_component_default_constructor(env_sequencer) 7 | `uvm_component_utils(env_sequencer) 8 | endclass 9 | -------------------------------------------------------------------------------- /env/env_configuration.svh: -------------------------------------------------------------------------------- 1 | class env_configuration extends tue_configuration; 2 | uvm_event reset_event; 3 | 4 | virtual function tue_configuration get_agent_configuration(); 5 | return null; 6 | endfunction 7 | 8 | `tue_object_default_constructor(env_configuration) 9 | `uvm_object_utils(env_configuration) 10 | endclass 11 | -------------------------------------------------------------------------------- /setup_submodules.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash -f 2 | submodules=( 3 | env/tue 4 | env/tvip-common 5 | env/tvip-apb 6 | env/tvip-axi 7 | ral/rggen-sv-ral 8 | rtl/rggen-sv-rtl 9 | rtl/rggen-verilog-rtl 10 | rtl/rggen-vhdl-rtl 11 | ) 12 | 13 | for submodule in ${submodules[@]} ; do 14 | git submodule update --init ${submodule} 15 | done 16 | -------------------------------------------------------------------------------- /sim/avalon/veryl/avalon_bridge.veryl: -------------------------------------------------------------------------------- 1 | pub module avalon_bridge #( 2 | param ADDRESS_WIDTH: u32 = 8 3 | )( 4 | bus_if: modport rggen::rggen_bus_if::slave, 5 | avalon_if: modport rggen::rggen_avalon_if::host 6 | ){ 7 | inst u_bridge: rggen::rggen_avalon_bridge #( 8 | ADDRESS_WIDTH: ADDRESS_WIDTH 9 | )( 10 | bus_if: bus_if, 11 | avalon_if: avalon_if 12 | ); 13 | } 14 | -------------------------------------------------------------------------------- /sim/apb/veryl/apb_bridge.veryl: -------------------------------------------------------------------------------- 1 | pub module apb_bridge #( 2 | param ADDRESS_WIDTH: u32 = 8 3 | )( 4 | i_clk: input clock, 5 | i_rst: input reset, 6 | bus_if: modport rggen::rggen_bus_if::slave, 7 | apb_if: modport rggen::rggen_apb_if::master 8 | ){ 9 | inst u_bridge: rggen::rggen_apb_bridge #( 10 | ADDRESS_WIDTH: ADDRESS_WIDTH 11 | )( 12 | i_clk: i_clk, 13 | i_rst: i_rst, 14 | bus_if: bus_if, 15 | apb_if: apb_if 16 | ); 17 | } 18 | -------------------------------------------------------------------------------- /sim/apb/makefile: -------------------------------------------------------------------------------- 1 | LANG_LIST += systemverilog 2 | LANG_LIST += verilog 3 | LANG_LIST += veryl 4 | LANG_LIST += vhdl 5 | 6 | SIM_LIST := $(addprefix sim_, $(LANG_LIST)) 7 | CLEAN_LIST := $(addprefix clean_, $(LANG_LIST)) 8 | 9 | .PHONY: run_sim run_clean $(SIM_LIST) $(CLEAN_LIST) 10 | 11 | run_sim: $(SIM_LIST) 12 | 13 | run_clean: $(CLEAN_LIST) 14 | 15 | $(SIM_LIST): 16 | $(MAKE) -C $(subst sim_,,$@) all 17 | 18 | $(CLEAN_LIST): 19 | $(MAKE) -C $(subst clean_,,$@) clean_all 20 | -------------------------------------------------------------------------------- /env/env_pkg.sv: -------------------------------------------------------------------------------- 1 | package env_pkg; 2 | import uvm_pkg::*; 3 | import tue_pkg::*; 4 | import block_0_ral_pkg::*; 5 | import block_1_ral_pkg::*; 6 | 7 | `include "uvm_macros.svh" 8 | `include "tue_macros.svh" 9 | `include "rggen_ral_macros.svh" 10 | 11 | `include "env_configuration.svh" 12 | `include "env_ral_model.svh" 13 | `include "env_ral_monitor.svh" 14 | `include "env_sequencer.svh" 15 | `include "env.svh" 16 | `include "ral_test.svh" 17 | endpackage 18 | -------------------------------------------------------------------------------- /sim/apb/veryl/Veryl.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "rggen_sample_testbench" 3 | version = "0.1.0" 4 | authors = ["Taichi Ishitani "] 5 | license = "MIT" 6 | repository = "https://github.com/rggen/rggen-sample-testbench" 7 | 8 | [build] 9 | target = {type = "directory", path = "target"} 10 | filelist_type = "flgen" 11 | omit_project_prefix = true 12 | reset_low_suffix = "_n" 13 | 14 | [dependencies] 15 | "rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" } 16 | -------------------------------------------------------------------------------- /sim/avalon/veryl/Veryl.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "rggen_sample_testbench" 3 | version = "0.1.0" 4 | authors = ["Taichi Ishitani "] 5 | license = "MIT" 6 | repository = "https://github.com/rggen/rggen-sample-testbench" 7 | 8 | [build] 9 | target = {type = "directory", path = "target"} 10 | filelist_type = "flgen" 11 | omit_project_prefix = true 12 | reset_low_suffix = "_n" 13 | 14 | [dependencies] 15 | "rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" } 16 | -------------------------------------------------------------------------------- /sim/axi4lite/veryl/Veryl.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "rggen_sample_testbench" 3 | version = "0.1.0" 4 | authors = ["Taichi Ishitani "] 5 | license = "MIT" 6 | repository = "https://github.com/rggen/rggen-sample-testbench" 7 | 8 | [build] 9 | target = {type = "directory", path = "target"} 10 | filelist_type = "flgen" 11 | omit_project_prefix = true 12 | reset_low_suffix = "_n" 13 | 14 | [dependencies] 15 | "rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" } 16 | -------------------------------------------------------------------------------- /sim/native/veryl/Veryl.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "rggen_sample_testbench" 3 | version = "0.1.0" 4 | authors = ["Taichi Ishitani "] 5 | license = "MIT" 6 | repository = "https://github.com/rggen/rggen-sample-testbench" 7 | 8 | [build] 9 | target = {type = "directory", path = "target"} 10 | filelist_type = "flgen" 11 | omit_project_prefix = true 12 | reset_low_suffix = "_n" 13 | 14 | [dependencies] 15 | "rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" } 16 | -------------------------------------------------------------------------------- /sim/wishbone/veryl/Veryl.toml: -------------------------------------------------------------------------------- 1 | [project] 2 | name = "rggen_sample_testbench" 3 | version = "0.1.0" 4 | authors = ["Taichi Ishitani "] 5 | license = "MIT" 6 | repository = "https://github.com/rggen/rggen-sample-testbench" 7 | 8 | [build] 9 | target = {type = "directory", path = "target"} 10 | filelist_type = "flgen" 11 | omit_project_prefix = true 12 | reset_low_suffix = "_n" 13 | 14 | [dependencies] 15 | "rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" } 16 | -------------------------------------------------------------------------------- /sim/axi4lite/veryl/axi4lite_bridge.veryl: -------------------------------------------------------------------------------- 1 | pub module axi4lite_bridge #( 2 | param ADDRESS_WIDTH: u32 = 16 3 | )( 4 | i_clk: input clock, 5 | i_rst: input reset, 6 | bus_if: modport rggen::rggen_bus_if::slave, 7 | axi4lite_if: modport rggen::rggen_axi4lite_if::master 8 | ) { 9 | inst u_bridge: rggen::rggen_axi4lite_bridge #( 10 | ADDRESS_WIDTH: ADDRESS_WIDTH 11 | )( 12 | i_clk: i_clk, 13 | i_rst: i_rst, 14 | bus_if: bus_if, 15 | axi4lite_if: axi4lite_if 16 | ); 17 | } 18 | -------------------------------------------------------------------------------- /sim/wishbone/veryl/wishbone_bridge.veryl: -------------------------------------------------------------------------------- 1 | pub module wishbone_bridge #( 2 | param ADDRESS_WIDTH: u32 = 8 3 | )( 4 | i_clk: input clock, 5 | i_rst: input reset, 6 | bus_if: modport rggen::rggen_bus_if::slave, 7 | wishbone_if: modport rggen::rggen_wishbone_if::master 8 | ){ 9 | inst u_bridge: rggen::rggen_wishbone_bridge #( 10 | ADDRESS_WIDTH: ADDRESS_WIDTH 11 | )( 12 | i_clk: i_clk, 13 | i_rst: i_rst, 14 | bus_if: bus_if, 15 | wishbone_if: wishbone_if 16 | ); 17 | } 18 | -------------------------------------------------------------------------------- /rtl/compile.rb: -------------------------------------------------------------------------------- 1 | case ENV['LANGUAGE'] 2 | when 'systemverilog' 3 | file_list 'rggen-sv-rtl/compile.rb', from: :current 4 | source_file "#{ENV['PROTOCOL']}/block_0.sv" 5 | source_file "#{ENV['PROTOCOL']}/block_1.sv" 6 | when 'verilog' 7 | file_list 'rggen-verilog-rtl/compile.rb', from: :current 8 | source_file "#{ENV['PROTOCOL']}/block_0.v" 9 | source_file "#{ENV['PROTOCOL']}/block_1.v" 10 | when 'vhdl' 11 | file_list 'rggen-vhdl-rtl/compile.rb', from: :current 12 | source_file "#{ENV['PROTOCOL']}/block_0.vhd" 13 | source_file "#{ENV['PROTOCOL']}/block_1.vhd" 14 | when 'veryl' 15 | file_list 'rggen_sample_testbench.list.rb', from: :cwd 16 | end 17 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "env/tue"] 2 | path = env/tue 3 | url = git@github.com:taichi-ishitani/tue.git 4 | [submodule "env/tvip-apb"] 5 | path = env/tvip-apb 6 | url = git@github.com:taichi-ishitani/tvip-apb.git 7 | [submodule "ral/rggen-sv-ral"] 8 | path = ral/rggen-sv-ral 9 | url = git@github.com:rggen/rggen-sv-ral.git 10 | [submodule "rtl/rggen-sv-rtl"] 11 | path = rtl/rggen-sv-rtl 12 | url = git@github.com:rggen/rggen-sv-rtl.git 13 | [submodule "env/tvip-axi"] 14 | path = env/tvip-axi 15 | url = git@github.com:taichi-ishitani/tvip-axi.git 16 | [submodule "env/tvip-common"] 17 | path = env/tvip-common 18 | url = git@github.com:taichi-ishitani/tvip-common.git 19 | [submodule "rtl/rggen-verilog-rtl"] 20 | path = rtl/rggen-verilog-rtl 21 | url = git@github.com:rggen/rggen-verilog-rtl.git 22 | [submodule "rtl/rggen-vhdl-rtl"] 23 | path = rtl/rggen-vhdl-rtl 24 | url = git@github.com:rggen/rggen-vhdl-rtl.git 25 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019-2025 Taichi Ishitani 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /env/apb2wishbone_bridge.sv: -------------------------------------------------------------------------------- 1 | module apb2wishbone_bridge #( 2 | parameter bit USE_STALL = 1 3 | )( 4 | input var i_clk, 5 | input var i_rst_n, 6 | interface.slave apb_if, 7 | interface.master wishbone_if 8 | ); 9 | logic request_done; 10 | 11 | always_comb begin 12 | wishbone_if.cyc = apb_if.psel && apb_if.penable; 13 | wishbone_if.stb = apb_if.psel && apb_if.penable && (!request_done); 14 | wishbone_if.adr = apb_if.paddr; 15 | wishbone_if.we = apb_if.pwrite; 16 | wishbone_if.dat_w = apb_if.pwdata; 17 | wishbone_if.sel = apb_if.pstrb; 18 | end 19 | 20 | always_comb begin 21 | apb_if.pready = wishbone_if.ack || wishbone_if.err || wishbone_if.rty; 22 | apb_if.prdata = wishbone_if.dat_r; 23 | apb_if.pslverr = wishbone_if.err || wishbone_if.rty; 24 | end 25 | 26 | if (USE_STALL) begin : g_stall 27 | always_ff @(posedge i_clk, negedge i_rst_n) begin 28 | if (!i_rst_n) begin 29 | request_done <= '0; 30 | end 31 | else if (apb_if.pready) begin 32 | request_done <= '0; 33 | end 34 | else if (wishbone_if.stb && (!wishbone_if.stall)) begin 35 | request_done <= '1; 36 | end 37 | end 38 | end 39 | else begin : g_no_stall 40 | always_comb begin 41 | request_done <= '0; 42 | end 43 | end 44 | endmodule 45 | -------------------------------------------------------------------------------- /env/apb_env_pkg.sv: -------------------------------------------------------------------------------- 1 | package apb_env_pkg; 2 | import uvm_pkg::*; 3 | import tue_pkg::*; 4 | import env_pkg::*; 5 | import tvip_apb_pkg::*; 6 | 7 | `include "uvm_macros.svh" 8 | `include "tue_macros.svh" 9 | 10 | typedef env_ral_monitor #( 11 | .ITEM (tvip_apb_master_item ), 12 | .ADAPTER (tvip_apb_master_ral_adapter ), 13 | .PREDICTOR (tvip_apb_master_ral_predictor ) 14 | ) env_apb_ral_monitor; 15 | 16 | class apb_env_configuration extends env_configuration; 17 | tvip_apb_configuration apb_configuration; 18 | 19 | function tue_configuration get_agent_configuration(); 20 | return apb_configuration; 21 | endfunction 22 | 23 | `tue_object_default_constructor(apb_env_configuration) 24 | `uvm_object_utils_begin(apb_env_configuration) 25 | `uvm_field_object(apb_configuration, UVM_DEFAULT) 26 | `uvm_object_utils_end 27 | endclass 28 | 29 | class apb_env extends env_param_base #( 30 | .AGENT (tvip_apb_master_agent ), 31 | .RAL_MONITOR (env_apb_ral_monitor ) 32 | ); 33 | protected function void create_agent(); 34 | agent = tvip_apb_master_agent::type_id::create("agent", this); 35 | agent.set_configuration(configuration.get_agent_configuration()); 36 | endfunction 37 | 38 | `tue_component_default_constructor(apb_env) 39 | `uvm_component_utils(apb_env) 40 | endclass 41 | endpackage 42 | -------------------------------------------------------------------------------- /env/compile.rb: -------------------------------------------------------------------------------- 1 | file_list 'tue/compile.rb', from: :current 2 | file_list 'tvip-common/compile.rb', from: :current 3 | 4 | if ENV['PROTOCOL'] == 'axi4lite' 5 | file_list 'tvip-axi/compile.rb', from: :current 6 | else 7 | file_list 'tvip-apb/compile.rb', from: :current 8 | end 9 | 10 | if ['verilog', 'vhdl', 'veryl'].include? ENV['LANGUAGE'] 11 | file_list 'rtl/rggen-sv-rtl/compile_backdoor.rb', from: :root 12 | end 13 | 14 | if ['verilog', 'vhdl'].include?(ENV['LANGUAGE']) && ENV['PROTOCOL'] != 'native' 15 | source_file 'rtl/rggen-sv-rtl/rggen_rtl_pkg.sv', from: :root 16 | source_file "rtl/rggen-sv-rtl/rggen_#{ENV['PROTOCOL']}_if.sv", from: :root 17 | end 18 | 19 | file_list 'ral/rggen-sv-ral/compile.rb' 20 | source_file 'ral/block_0_ral_pkg.sv', from: :root 21 | source_file 'ral/block_1_ral_pkg.sv', from: :root 22 | 23 | include_directory '.' 24 | source_file 'env_pkg.sv' 25 | 26 | if ENV['PROTOCOL'] == 'avalon' 27 | source_file 'apb_env_pkg.sv' 28 | if ['verilog', 'vhdl'].include? ENV['LANGUAGE'] 29 | source_file "rtl/rggen-sv-rtl/rggen_avalon_if.sv", from: :root 30 | end 31 | elsif ENV['PROTOCOL'] == 'wishbone' 32 | source_file 'apb_env_pkg.sv' 33 | source_file 'apb2wishbone_bridge.sv' 34 | if ENV['LANGUAGE'] != 'systemverilog' 35 | source_file "rtl/rggen-sv-rtl/rggen_apb_if.sv", from: :root 36 | end 37 | elsif ENV['PROTOCOL'] == 'native' 38 | source_file 'apb_env_pkg.sv' 39 | else 40 | source_file "#{ENV['PROTOCOL']}_env_pkg.sv" 41 | end 42 | 43 | source_file "#{ENV['PROTOCOL']}_top.sv" 44 | -------------------------------------------------------------------------------- /env/env.svh: -------------------------------------------------------------------------------- 1 | class env_base extends tue_env #( 2 | .CONFIGURATION (env_configuration ) 3 | ); 4 | env_sequencer sequencer; 5 | 6 | function void build_phase(uvm_phase phase); 7 | super.build_phase(phase); 8 | sequencer = env_sequencer::type_id::create("sequencer", this); 9 | sequencer.set_configuration(configuration); 10 | endfunction 11 | 12 | `tue_component_default_constructor(env_base) 13 | `uvm_component_utils(env_base) 14 | endclass 15 | 16 | class env_param_base #( 17 | type AGENT = uvm_agent, 18 | type RAL_MONITOR = uvm_component 19 | ) extends env_base; 20 | protected AGENT agent; 21 | protected RAL_MONITOR ral_monitor; 22 | 23 | function void build_phase(uvm_phase phase); 24 | super.build_phase(phase); 25 | create_agent(); 26 | create_ral_monitor(); 27 | endfunction 28 | 29 | function void connect_phase(uvm_phase phase); 30 | super.connect_phase(phase); 31 | ral_monitor.connect_sequencer(agent.sequencer); 32 | agent.item_port.connect(ral_monitor.bus_in); 33 | sequencer.bus_sequencer = agent.sequencer; 34 | sequencer.model = ral_monitor.model; 35 | endfunction 36 | 37 | protected virtual function void create_agent(); 38 | endfunction 39 | 40 | protected virtual function void create_ral_monitor(); 41 | ral_monitor = RAL_MONITOR::type_id::create("ral_monitor", this); 42 | ral_monitor.set_configuration(configuration); 43 | endfunction 44 | 45 | `tue_component_default_constructor(env_param_base) 46 | endclass 47 | -------------------------------------------------------------------------------- /sim/dsim.mk: -------------------------------------------------------------------------------- 1 | CLEAN_TARGETS += dvlcom.env 2 | CLEAN_TARGETS += dvhcom.env 3 | CLEAN_TARGETS += dsim.env 4 | CLEAN_TARGETS += dsim_work 5 | CLEAN_TARGETS += */dsim.env 6 | CLEAN_TARGETS += */metrics.db 7 | 8 | DVLCOM_DUT_ARGS += -l dvlcom_dut.log 9 | DVLCOM_DUT_ARGS += -f dut.f 10 | 11 | DVHCOM_DUT_ARGS += -l dvhcom_dut.log 12 | DVHCOM_DUT_ARGS += -f dut.f 13 | 14 | DVLCOM_ENV_ARGS += -uvm $(UVM_VERSION) 15 | DVLCOM_ENV_ARGS += -l dvlcom_env.log 16 | DVLCOM_ENV_ARGS += -f env.f 17 | 18 | DSIM_ELAB_ARGS += -genimage image 19 | DSIM_ELAB_ARGS += -uvm $(UVM_VERSION) 20 | DSIM_ELAB_ARGS += -timescale 1ns/1ps 21 | DSIM_ELAB_ARGS += -l dsim_elab.log 22 | DSIM_ELAB_ARGS += -top work.top 23 | 24 | DSIM_SIM_ARGS += -work ../dsim_work 25 | DSIM_SIM_ARGS += -image image 26 | DSIM_SIM_ARGS += -uvm $(UVM_VERSION) 27 | DSIM_SIM_ARGS += -timescale 1ns/1ps 28 | DSIM_SIM_ARGS += -l dsim_sim.log 29 | DSIM_SIM_ARGS += +UVM_TESTNAME=$(TEST) 30 | 31 | ifeq ($(strip $(DUMP)), vcd) 32 | DSIM_ELAB_ARGS += +acc 33 | DSIM_SIM_ARGS += -waves dump.vcd 34 | endif 35 | 36 | .PHONY: sim_dsim compile_dsim 37 | 38 | sim_dsim: 39 | [ -f dsim_work/image.so ] || $(MAKE) compile_dsim 40 | [ -d $(TEST) ] || mkdir $(TEST) 41 | cd $(TEST); dsim $(DSIM_SIM_ARGS) 42 | 43 | compile_dsim: 44 | ifeq ($(strip $(LANGUAGE)), veryl) 45 | $(MAKE) gen_veryl 46 | endif 47 | ifeq ($(strip $(LANGUAGE)), vhdl) 48 | $(MAKE) dut_vhdl.f 49 | -dlib map -lib ieee ${STD_LIBS}/ieee93 50 | dvhcom $(DVHCOM_DUT_ARGS) 51 | else 52 | $(MAKE) dut.f 53 | dvlcom $(DVLCOM_DUT_ARGS) 54 | endif 55 | $(MAKE) env.f 56 | dvlcom $(DVLCOM_ENV_ARGS) 57 | dsim $(DSIM_ELAB_ARGS) 58 | -------------------------------------------------------------------------------- /sim/vivado.mk: -------------------------------------------------------------------------------- 1 | CLEAN_TARGETS += *.pb 2 | CLEAN_TARGETS += *.jou 3 | CLEAN_TARGETS += *.wdb 4 | CLEAN_TARGETS += vivado_*.str 5 | CLEAN_TARGETS += xsim.dir 6 | CLEAN_TARGETS += .Xil 7 | 8 | XVLOG_ENV_ARGS += -sv 9 | XVLOG_ENV_ARGS += -log xvlog_env.log 10 | XVLOG_ENV_ARGS += -L uvm 11 | XVLOG_ENV_ARGS += -verbose 2 12 | XVLOG_ENV_ARGS += -f env.f 13 | 14 | XVLOG_DUT_ARGS += $(if $(findstring systemverilog, $(LANGUAGE)), -sv, ) 15 | XVLOG_DUT_ARGS += -verbose 2 16 | XVLOG_DUT_ARGS += -log xvlog_dut.log 17 | XVLOG_DUT_ARGS += -f dut.f 18 | 19 | XVHDL_DUT_ARGS += -verbose 2 20 | XVHDL_DUT_ARGS += -log xvhdl_dut.log 21 | XVHDL_DUT_ARGS += -f dut.f 22 | 23 | XELAB_ARGS += -log xelab.log 24 | XELAB_ARGS += -verbose 2 25 | XELAB_ARGS += -timescale 1ns/1ps 26 | XELAB_ARGS += -L uvm 27 | XELAB_ARGS += top 28 | 29 | XSIM_ARGS += work.top 30 | XSIM_ARGS += -log $(TEST)/xsim.log 31 | XSIM_ARGS += -testplusarg "UVM_TESTNAME=$(TEST)" 32 | 33 | ifeq ($(strip $(GUI)), on) 34 | XELAB_ARGS += -debug all 35 | XSIM_ARGS += -gui 36 | else 37 | XSIM_ARGS += -R 38 | endif 39 | 40 | .PHONY: sim_vivado compile_vivado 41 | 42 | sim_vivado: 43 | [ -d xsim.dir ] || $(MAKE) compile_vivado 44 | [ -d $(TEST) ] || mkdir $(TEST) 45 | xsim $(XSIM_ARGS) 46 | 47 | compile_vivado: 48 | ifeq ($(strip $(LANGUAGE)), veryl) 49 | $(MAKE) gen_veryl 50 | endif 51 | ifeq ($(strip $(LANGUAGE)), vhdl) 52 | $(MAKE) dut_vhdl.f 53 | xvhdl $(XVHDL_DUT_ARGS) 54 | else 55 | $(MAKE) dut.f 56 | sed -i -e 's/+define+/-d /g' -e 's/+incdir+/-i /g' dut.f 57 | xvlog $(XVLOG_DUT_ARGS) 58 | endif 59 | $(MAKE) env.f 60 | sed -i -e 's/+define+/-d /g' -e 's/+incdir+/-i /g' env.f 61 | xvlog $(XVLOG_ENV_ARGS) 62 | xelab $(XELAB_ARGS) 63 | -------------------------------------------------------------------------------- /env/axi4lite_env_pkg.sv: -------------------------------------------------------------------------------- 1 | package axi4lite_env_pkg; 2 | import uvm_pkg::*; 3 | import tue_pkg::*; 4 | import env_pkg::*; 5 | import tvip_axi_types_pkg::*; 6 | import tvip_axi_pkg::*; 7 | 8 | `include "uvm_macros.svh" 9 | `include "tue_macros.svh" 10 | 11 | class axi4lite_env_configuration extends env_configuration; 12 | tvip_axi_configuration axi4lite_configuration; 13 | 14 | function tue_configuration get_agent_configuration(); 15 | return axi4lite_configuration; 16 | endfunction 17 | 18 | `tue_object_default_constructor(axi4lite_env_configuration) 19 | `uvm_object_utils_begin(axi4lite_env_configuration) 20 | `uvm_field_object(axi4lite_configuration, UVM_DEFAULT) 21 | `uvm_object_utils_end 22 | endclass 23 | 24 | class axi4lite_env_adapter extends tvip_axi_ral_adapter; 25 | protected function tvip_axi_id get_axi_id(); 26 | return $urandom_range(0, 3); 27 | endfunction 28 | `tue_object_default_constructor(axi4lite_env_adapter) 29 | `uvm_object_utils(axi4lite_env_adapter) 30 | endclass 31 | 32 | typedef env_ral_monitor #( 33 | .ITEM (tvip_axi_item ), 34 | .ADAPTER (axi4lite_env_adapter ), 35 | .PREDICTOR (tvip_axi_ral_predictor ) 36 | ) axi4lite_env_ral_monitor; 37 | 38 | class axi4lite_env extends env_param_base #( 39 | .AGENT (tvip_axi_master_agent ), 40 | .RAL_MONITOR (axi4lite_env_ral_monitor ) 41 | ); 42 | protected function void create_agent(); 43 | agent = tvip_axi_master_agent::type_id::create("agent", this); 44 | agent.set_configuration(configuration.get_agent_configuration()); 45 | endfunction 46 | 47 | `tue_component_default_constructor(axi4lite_env) 48 | `uvm_component_utils(axi4lite_env) 49 | endclass 50 | endpackage 51 | -------------------------------------------------------------------------------- /sim/xcelium.mk: -------------------------------------------------------------------------------- 1 | CLEAN_TARGETS += xcelium.d 2 | CLEAN_TARGETS += *.history 3 | 4 | XRUN_COMMON_ARGS += -64bit 5 | XRUN_COMMON_ARGS += -timedetail 6 | XRUN_COMMON_ARGS += -status 7 | 8 | XRUN_COMPILE_ARGS += -l compile.log 9 | XRUN_COMPILE_ARGS += -elaborate 10 | XRUN_COMPILE_ARGS += -timescale '1ns/1ps' 11 | XRUN_COMPILE_ARGS += -uvmhome CDNS-$(UVM_VERSION) 12 | XRUN_COMPILE_ARGS += -plusperf 13 | XRUN_COMPILE_ARGS += -newperf 14 | XRUN_COMPILE_ARGS += -mccodegen 15 | XRUN_COMPILE_ARGS += -warn_multiple_driver 16 | XRUN_COMPILE_ARGS += -top worklib.top 17 | 18 | XRUN_SIMULATION_ARGS += -l simulation.log 19 | XRUN_SIMULATION_ARGS += -R 20 | XRUN_SIMULATION_ARGS += -xmlibdirname ../xcelium.d 21 | XRUN_SIMULATION_ARGS += -xceligen on 22 | XRUN_SIMULATION_ARGS += -uvmhome CDNS-$(UVM_VERSION) 23 | XRUN_SIMULATION_ARGS += +UVM_TESTNAME=$(TEST) 24 | 25 | ifeq ($(strip $(GUI)), indago) 26 | XRUN_COMPILE_ARGS += -classlinedebug 27 | XRUN_COMPILE_ARGS += -xmdebug 28 | XRUN_COMPILE_ARGS += -lwdgen 29 | XRUN_SIMULATION_ARGS += -mcdump 30 | XRUN_SIMULATION_ARGS += -gui 31 | XRUN_SIMULATION_ARGS += -indago 32 | XRUN_SIMULATION_ARGS += -input @"ida_probe -log" 33 | XRUN_SIMULATION_ARGS += -input @"ida_probe -wave -wave_probe_args=\"-all -depth to_cells\"" 34 | else 35 | XRUN_SIMULATION_ARGS += -run 36 | endif 37 | 38 | XRUN_COMPILE_ARGS += -f dut.f 39 | XRUN_COMPILE_ARGS += -f env.f 40 | 41 | .PHONY: sim_xcelium compile_xcelium 42 | 43 | sim_xcelium: 44 | xmls -64bit -nolog -snapshot | grep SSS || $(MAKE) compile_xcelium 45 | [ -d $(TEST) ] || mkdir $(TEST) 46 | cd $(TEST); xrun $(XRUN_COMMON_ARGS) $(XRUN_SIMULATION_ARGS) 47 | 48 | compile_xcelium: 49 | $(MAKE) env.f 50 | ifeq ($(strip $(LANGUAGE)), veryl) 51 | $(MAKE) gen_veryl 52 | endif 53 | ifeq ($(strip $(LANGUAGE)), vhdl) 54 | $(MAKE) dut_vhdl.f 55 | else 56 | $(MAKE) dut.f 57 | endif 58 | xrun $(XRUN_COMMON_ARGS) $(XRUN_COMPILE_ARGS) 59 | -------------------------------------------------------------------------------- /sim/common.mk: -------------------------------------------------------------------------------- 1 | RGGEN_SAMPLE_TESTBENCH_ROOT = $(shell git rev-parse --show-toplevel) 2 | export RGGEN_SAMPLE_TESTBENCH_ROOT 3 | 4 | LANGUAGE ?= systemverilog 5 | UVM_VERSION ?= 1.2 6 | SIMULATOR ?= vcs 7 | PROTOCOL ?= apb 8 | ENV_TYPE ?= $(PROTOCOL)_env 9 | GUI ?= off 10 | DUMP ?= off 11 | TR_DEBUG ?= off 12 | 13 | include local.mk 14 | 15 | export LANGUAGE 16 | export PROTOCOL 17 | 18 | DEFINES += RGGEN_$(shell echo $(LANGUAGE) | tr a-z A-Z) 19 | DEFINES += RGGEN_ENABLE_SVA 20 | DEFINES += RGGEN_ENABLE_BACKDOOR 21 | DEFINES += RGGEN_ENABLE_ENHANCED_RAL 22 | 23 | TEST_LIST += ral_hw_reset_test 24 | TEST_LIST += ral_bit_bash_test 25 | TEST_LIST += ral_access_test 26 | 27 | CLEAN_TARGETS += *.f 28 | CLEAN_TARGETS += Veryl.lock 29 | CLEAN_TARGETS += dependencies 30 | CLEAN_TARGETS += .build 31 | CLEAN_TARGETS += target 32 | CLEAN_TARGETS += *.rb 33 | 34 | .PHONY: all $(TEST_LIST) clean clean_all gen_veryl check_log dut.f dut_vhdl.f env.f 35 | 36 | all: $(TEST_LIST) check_log 37 | 38 | $(TEST_LIST): 39 | $(MAKE) sim_$(SIMULATOR) TEST=$@ 40 | 41 | clean: 42 | rm -rf $(CLEAN_TARGETS) 43 | 44 | clean_all: 45 | $(MAKE) clean 46 | rm -rf $(TEST_LIST) *.log 47 | 48 | check_log: 49 | grep UVM_ERROR */*.log 50 | grep UVM_FATAL */*.log 51 | 52 | gen_veryl: 53 | veryl build 54 | 55 | dut.f: 56 | flgen --output=dut.f $(addprefix --define-macro=,$(DEFINES)) $(RGGEN_SAMPLE_TESTBENCH_ROOT)/rtl/compile.rb 57 | 58 | dut_vhdl.f: 59 | flgen --output=dut.f --source-file-only $(addprefix --define-macro=,$(DEFINES)) $(RGGEN_SAMPLE_TESTBENCH_ROOT)/rtl/compile.rb 60 | 61 | env.f: 62 | flgen --output=env.f $(addprefix --define-macro=,$(DEFINES)) $(RGGEN_SAMPLE_TESTBENCH_ROOT)/env/compile.rb 63 | 64 | include $(RGGEN_SAMPLE_TESTBENCH_ROOT)/sim/vcs.mk 65 | include $(RGGEN_SAMPLE_TESTBENCH_ROOT)/sim/xcelium.mk 66 | include $(RGGEN_SAMPLE_TESTBENCH_ROOT)/sim/dsim.mk 67 | include $(RGGEN_SAMPLE_TESTBENCH_ROOT)/sim/vivado.mk 68 | -------------------------------------------------------------------------------- /env/env_ral_monitor.svh: -------------------------------------------------------------------------------- 1 | class env_ral_monitor #( 2 | type ITEM = uvm_sequence_item, 3 | type ADAPTER = uvm_reg_adapter, 4 | type PREDICTOR = uvm_reg_predictor #(uvm_reg_item) 5 | ) extends tue_component #( 6 | .CONFIGURATION (env_configuration ) 7 | ); 8 | uvm_analysis_export #(ITEM) bus_in; 9 | 10 | env_ral_model model; 11 | protected ADAPTER adapter; 12 | protected PREDICTOR predictor; 13 | 14 | function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | 17 | bus_in = new("bus_in", this); 18 | adapter = ADAPTER::type_id::create("adapter"); 19 | predictor = PREDICTOR::type_id::create("predictor", this); 20 | 21 | model = env_ral_model::type_id::create("model"); 22 | model.configure(null); 23 | model.default_map.set_base_addr('h1000); 24 | model.build(); 25 | 26 | foreach (model.register_10[i]) begin 27 | model.register_10[i].bit_field_1[0].set_reset(2'h0); 28 | model.register_10[i].bit_field_1[1].set_reset(2'h1); 29 | model.register_10[i].bit_field_1[2].set_reset(2'h2); 30 | model.register_10[i].bit_field_1[3].set_reset(2'h3); 31 | end 32 | 33 | model.set_hdl_path_root("top.u_block_0"); 34 | model.register_18.set_hdl_path_root("top.u_block_1"); 35 | 36 | model.lock_model(); 37 | endfunction 38 | 39 | function void connect_phase(uvm_phase phase); 40 | super.connect_phase(phase); 41 | bus_in.connect(predictor.bus_in); 42 | predictor.map = model.default_map; 43 | predictor.adapter = adapter; 44 | endfunction 45 | 46 | task run_phase(uvm_phase phase); 47 | forever begin 48 | configuration.reset_event.wait_trigger(); 49 | model.reset(); 50 | end 51 | endtask 52 | 53 | function void connect_sequencer(uvm_sequencer_base sequencer); 54 | model.default_map.set_sequencer(sequencer, adapter); 55 | endfunction 56 | 57 | `tue_component_default_constructor(env_ral_monitor) 58 | `uvm_component_param_utils(env_ral_monitor #(ITEM, ADAPTER, PREDICTOR)) 59 | endclass 60 | -------------------------------------------------------------------------------- /sim/vcs.mk: -------------------------------------------------------------------------------- 1 | CLEAN_TARGETS += simv* 2 | CLEAN_TARGETS += AN.DB 3 | CLEAN_TARGETS += csrc 4 | CLEAN_TARGETS += 64 5 | CLEAN_TARGETS += work.lib++ 6 | CLEAN_TARGETS += vc_hdrs.h 7 | 8 | VLOGAN_UVM_ARGS += -full64 9 | VLOGAN_UVM_ARGS += -sverilog 10 | VLOGAN_UVM_ARGS += -timescale=1ns/1ps 11 | VLOGAN_UVM_ARGS += -ntb_opts uvm-$(UVM_VERSION) 12 | VLOGAN_UVM_ARGS += -l vlogan_uvm.log 13 | 14 | VLOGAN_DUT_ARGS += -full64 15 | VLOGAN_DUT_ARGS += $(if $(findstring systemverilog, $(LANGUAGE)), -sverilog, ) 16 | VLOGAN_DUT_ARGS += $(if $(findstring veryl, $(LANGUAGE)), -sverilog, ) 17 | VLOGAN_DUT_ARGS += -timescale=1ns/1ps 18 | VLOGAN_DUT_ARGS += -l vlogan_dut.log 19 | VLOGAN_DUT_ARGS += -f dut.f 20 | 21 | VHDLAN_DUT_ARGS += -full64 22 | VHDLAN_DUT_ARGS += -l vhdlan_dut.log 23 | VHDLAN_DUT_ARGS += -f dut.f 24 | 25 | VLOGAN_ENV_ARGS += -full64 26 | VLOGAN_ENV_ARGS += -sverilog 27 | VLOGAN_ENV_ARGS += -timescale=1ns/1ps 28 | VLOGAN_ENV_ARGS += -ntb_opts uvm-$(UVM_VERSION) 29 | VLOGAN_ENV_ARGS += -l vlogan_env.log 30 | VLOGAN_ENV_ARGS += -f env.f 31 | 32 | VCS_ARGS += -full64 33 | VCS_ARGS += -ntb_opts uvm-$(UVM_VERSION) 34 | VCS_ARGS += -l vcs.log 35 | VCS_ARGS += -top top 36 | 37 | SIMV_ARGS += -l simv.log 38 | SIMV_ARGS += +UVM_TESTNAME=$(TEST) 39 | 40 | ifeq ($(strip $(GUI)), verdi) 41 | VLOGAN_UVM_ARGS += -kdb 42 | VLOGAN_DUT_ARGS += -kdb 43 | VHDLAN_DUT_ARGS += -kdb 44 | VLOGAN_ENV_ARGS += -kdb 45 | VCS_ARGS += -debug_access+all 46 | VCS_ARGS += -kdb 47 | VCS_ARGS += +vcs+fsdbon 48 | SIMV_ARGS += -gui=verdi 49 | SIMV_ARGS += +UVM_VERDI_TRACE=RAL 50 | ifeq ($(strip $(TR_DEBUG)), on) 51 | SIMV_ARGS += +UVM_VERDI_TRACE 52 | SIMV_ARGS += +UVM_TR_RECORD 53 | endif 54 | endif 55 | 56 | ifeq ($(strip $(GUI)), dve) 57 | VCS_ARGS += -debug_access+all 58 | VCS_ARGS += +vcs+vcdpluson 59 | SIMV_ARGS += -gui=dve 60 | endif 61 | 62 | .PHONY: sim_vcs compile_vcs 63 | 64 | sim_vcs: 65 | [ -f simv ] || $(MAKE) compile_vcs 66 | [ -d $(TEST) ] || mkdir $(TEST) 67 | cd $(TEST); ../simv $(SIMV_ARGS) 68 | 69 | compile_vcs: 70 | ifeq ($(strip $(LANGUAGE)), veryl) 71 | $(MAKE) gen_veryl 72 | endif 73 | vlogan $(VLOGAN_UVM_ARGS) 74 | ifeq ($(strip $(LANGUAGE)), vhdl) 75 | $(MAKE) dut_vhdl.f 76 | vhdlan $(VHDLAN_DUT_ARGS) 77 | else 78 | $(MAKE) dut.f 79 | vlogan $(VLOGAN_DUT_ARGS) 80 | endif 81 | $(MAKE) env.f 82 | vlogan $(VLOGAN_ENV_ARGS) 83 | vcs $(VCS_ARGS) 84 | -------------------------------------------------------------------------------- /env/ral_test.svh: -------------------------------------------------------------------------------- 1 | class ral_test_sequence #( 2 | type RAL_SEQUENCE = uvm_sequence 3 | ) extends tue_sequence #( 4 | .CONFIGURATION (env_configuration ) 5 | ); 6 | function new(string name = "ral_test_sequence"); 7 | super.new(name); 8 | set_automatic_phase_objection(1); 9 | endfunction 10 | 11 | task body(); 12 | RAL_SEQUENCE ral_sequence; 13 | `uvm_create(ral_sequence) 14 | ral_sequence.model = p_sequencer.model; 15 | `uvm_send(ral_sequence) 16 | endtask 17 | 18 | `uvm_declare_p_sequencer(env_sequencer) 19 | `uvm_object_param_utils(ral_test_sequence #(RAL_SEQUENCE)) 20 | endclass 21 | 22 | class ral_test_base extends tue_test #( 23 | .CONFIGURATION (env_configuration ) 24 | ); 25 | env_base env; 26 | 27 | function void build_phase(uvm_phase phase); 28 | super.build_phase(phase); 29 | env = env_base::type_id::create("env", this); 30 | env.set_configuration(configuration); 31 | endfunction 32 | 33 | function void start_of_simulation_phase(uvm_phase phase); 34 | super.start_of_simulation_phase(phase); 35 | uvm_config_db #(uvm_object_wrapper)::set( 36 | env.sequencer, "main_phase", "default_sequence", get_main_sequence() 37 | ); 38 | endfunction 39 | 40 | protected virtual function uvm_object_wrapper get_main_sequence(); 41 | return null; 42 | endfunction 43 | 44 | `tue_component_default_constructor(ral_test_base) 45 | endclass 46 | 47 | `ifdef RGGEN_ENABLE_ENHANCED_RAL 48 | typedef tue_reg_hw_reset_seq ral_hw_reset_test_sequence; 49 | typedef tue_reg_bit_bash_seq ral_bit_bash_test_sequence; 50 | typedef tue_reg_access_seq ral_access_test_sequence; 51 | `else 52 | typedef uvm_reg_hw_reset_seq ral_hw_reset_test_sequence; 53 | typedef uvm_reg_bit_bash_seq ral_bit_bash_test_sequence; 54 | typedef uvm_reg_access_seq ral_access_test_sequence; 55 | `endif 56 | 57 | class ral_hw_reset_test extends ral_test_base; 58 | protected virtual function uvm_object_wrapper get_main_sequence(); 59 | return ral_test_sequence #(ral_hw_reset_test_sequence)::type_id::get(); 60 | endfunction 61 | `tue_component_default_constructor(ral_hw_reset_test) 62 | `uvm_component_utils(ral_hw_reset_test) 63 | endclass 64 | 65 | class ral_bit_bash_test extends ral_test_base; 66 | protected virtual function uvm_object_wrapper get_main_sequence(); 67 | return ral_test_sequence #(ral_bit_bash_test_sequence)::type_id::get(); 68 | endfunction 69 | `tue_component_default_constructor(ral_bit_bash_test) 70 | `uvm_component_utils(ral_bit_bash_test) 71 | endclass 72 | 73 | class ral_access_test extends ral_test_base; 74 | protected virtual function uvm_object_wrapper get_main_sequence(); 75 | return ral_test_sequence #(ral_access_test_sequence)::type_id::get(); 76 | endfunction 77 | `tue_component_default_constructor(ral_access_test) 78 | `uvm_component_utils(ral_access_test) 79 | endclass 80 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RgGen Sample Testbench 2 | 3 | This is an sample testbench to demonstrate integrating UVM RAL model generated by `RgGen` into UVM based testbench. 4 | 5 | ## Preparation 6 | 7 | This env uses [flgen](https://github.com/pezy-computing/flgen) to generate *.f files which are given to simulator tools. 8 | Therefore, you need to install the tool before using this env. See its repository for details. 9 | 10 | ## DUT 11 | 12 | In this testbech, CSR modules generated by `RgGen` are used as DUT and there are three types of DUT: 13 | 14 | * DUT with AMBA APB iterface 15 | * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/apb 16 | * DUT with AMBA AXI4-Lite interface 17 | * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/axi4lite 18 | * DUT with Avalon-MM interface 19 | * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/avalon 20 | * DUT with wishbone interface 21 | * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/wishbone 22 | * DUT with native interface 23 | * https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/native 24 | 25 | ## Sample Testcases 26 | 27 | This testbench inclues three sample testcases invoking pre-defined test sequences. 28 | 29 | | Test Name | Test Sequence | 30 | |:------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------| 31 | | ral_hw_reset_test | [uvm_reg_hw_reset_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_hw_reset_seq-svh.html) | 32 | | ral_bit_bash_test | [uvm_reg_bit_bash_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_bit_bash_seq-svh.html) | 33 | | ral_access_test | [uvm_reg_access_seq](https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_access_seq-svh.html) | 34 | 35 | ## Usage 36 | 37 | ### Setup 38 | 39 | This testbench depends on some submodules so you need to get them from GitHub repositries. 40 | To do this, hit the command below on the root of this repositly. 41 | 42 | ``` 43 | $ cd rggen-sample-testbench 44 | $ ./setup_submodules.sh 45 | ``` 46 | 47 | If execution of above commands failed you need to get them from GitHub repositlies directly and set some environment variables. 48 | 49 | ``` 50 | $ git clone https://github.com/taichi-ishitani/tue.git 51 | $ export TUE_HOME=`pwd`/tue 52 | $ git clone https://github.com/taichi-ishitani/tvip-common.git 53 | $ export TVIP_COMMON_HOME=`pwd`/tvip-common 54 | $ git clone https://github.com/taichi-ishitani/tvip-apb.git 55 | $ export TVIP_APB_HOME=`pwd`/tvip-apb 56 | $ git clone https://github.com/taichi-ishitani/tvip-axi.git 57 | $ export TVIP_APB_HOME=`pwd`/tvip-axi 58 | $ git clone https://github.com/rggen/rggen-sv-rtl.git 59 | $ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-rtl 60 | $ git clone https://github.com/rggen/rggen-sv-ral.git 61 | $ export RGGEN_SV_RTL_ROOT=`pwd`/rggen-sv-ral 62 | $ git clone https://github.com/rggen/rggen-verilog-rtl.git 63 | $ export RGGEN_VERILOG_RTL_ROOT=`pwd`/rggen-verilog-rtl 64 | $ git clone https://github.com/rggen/rggen-vhdl-rtl.git 65 | $ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl 66 | ``` 67 | 68 | ### Run Simulation 69 | 70 | Synopsys VCS simulator, Cadence Xcelium simulator, Metrics DSim simulator and AMD Vivado simulator are supported. 71 | 72 | 1. Move to the work directry 73 | * for DUT with AMBA APB interfac 74 | * `sim/apb/systemverilog` 75 | * `sim/apb/verilog` 76 | * `sim/apb/veryl` 77 | * `sim/apb/vhdl` 78 | * for DUT with AMBA AXI4-Lite interface 79 | * `sim/axi4lite/systemverilog` 80 | * `sim/axi4lite/verilog` 81 | * `sim/axi4lite/veryl` 82 | * `sim/axi4lite/vhdl` 83 | * for DUT with Avalon-MM interface 84 | * `sim/avalon/systemverilog` 85 | * `sim/avalon/verilog` 86 | * `sim/avalon/veryl` 87 | * `sim/avalon/vhdl` 88 | * for DUT with wishbone interface 89 | * `sim/wishbone/systemverilog` 90 | * `sim/wishbone/verilog` 91 | * `sim/wishbone/veryl` 92 | * `sim/wishbone/vhdl` 93 | * for DUT with native interface 94 | * `sim/native/systemverilog` 95 | * `sim/native/verilog` 96 | * `sim/native/veryl` 97 | * `sim/native/vhdl` 98 | 99 | 2. Hit `make` command on the work directry 100 | 101 | ``` 102 | $ make 103 | ``` 104 | 105 | By default, all sample testcases will be execluted by VCS simulator. 106 | If you want to use Xcelium, DSim or Vivado simulator, add `SIMULATOR` option to `makefile` command. 107 | 108 | * For Xcelium: 109 | 110 | ``` 111 | $ make SIMULATOR=xcelium 112 | ``` 113 | 114 | * For DSim 115 | 116 | ``` 117 | $ make SIMULATOR=dsim 118 | ``` 119 | 120 | * For Vivado: 121 | 122 | ``` 123 | $ make SIMULATOR=vivado 124 | ``` 125 | 126 | If you want to execute an specific testcase then you need to give its name to `make` command like below. 127 | 128 | ``` 129 | $ make ral_bit_bash_test 130 | ``` 131 | 132 | The `GUI` option is to enable the inteructive debug environment. 133 | To invoke the GUI frontend, give this option to `make` command like below. 134 | 135 | * Frontend: DVE 136 | 137 | ``` 138 | $ make ral_bit_bash_test GUI=dve 139 | ``` 140 | 141 | * Frontend: Verdi 142 | 143 | ``` 144 | $ make ral_bit_bash_test GUI=verdi 145 | ``` 146 | 147 | * Frontend: Indago 148 | 149 | ``` 150 | $ make ral_bit_bash_test SIMULATOR=xcelium GUI=indago 151 | ``` 152 | 153 | * Frontend: Vivado 154 | 155 | ``` 156 | $ make ral_bit_bash_test SIMULATOR=vivado GUI=on 157 | ``` 158 | 159 | ## Contact 160 | 161 | You can post your questions, feedbacks, bug reports, etc. by using following ways. 162 | 163 | * [GitHub Issue Tracker](https://github.com/rggen/rggen-sample-testbench/issues) 164 | * [Discord](https://discord.com/invite/KWya83ZZxr) 165 | * [Mailing List](https://groups.google.com/d/forum/rggen) 166 | * [Mail](mailto:rggen@googlegroups.com) 167 | 168 | ## Copyright & License 169 | 170 | Copyright © 2019-2025 Taichi Ishitani. This testbench is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils. 171 | -------------------------------------------------------------------------------- /ral/block_1_ral_pkg.sv: -------------------------------------------------------------------------------- 1 | package block_1_ral_pkg; 2 | import uvm_pkg::*; 3 | import rggen_ral_pkg::*; 4 | `include "uvm_macros.svh" 5 | `include "rggen_ral_macros.svh" 6 | class register_file_0_register_0_reg_model extends rggen_ral_reg; 7 | rand rggen_ral_field bit_field_0; 8 | function new(string name); 9 | super.new(name, 32, 0); 10 | endfunction 11 | function void build(); 12 | `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, '{}, 1, 0, 0, "") 13 | endfunction 14 | endclass 15 | class register_file_0_register_1_reg_model extends rggen_ral_reg; 16 | rand rggen_ral_field bit_field_0; 17 | function new(string name); 18 | super.new(name, 32, 0); 19 | endfunction 20 | function void build(); 21 | `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, '{}, 1, 0, 0, "") 22 | endfunction 23 | endclass 24 | class register_file_0_reg_file_model extends rggen_ral_reg_file; 25 | rand register_file_0_register_0_reg_model register_0; 26 | rand register_file_0_register_1_reg_model register_1; 27 | function new(string name); 28 | super.new(name, 4, 0); 29 | endfunction 30 | function void build(); 31 | `rggen_ral_create_reg(register_0, '{}, '{}, 7'h00, "RW", "g_register_0.u_register") 32 | `rggen_ral_create_reg(register_1, '{}, '{}, 7'h04, "RW", "g_register_1.u_register") 33 | endfunction 34 | endclass 35 | class register_file_1_register_0_reg_model extends rggen_ral_indirect_reg; 36 | rand rggen_ral_field bit_field_0; 37 | function new(string name); 38 | super.new(name, 32, 0); 39 | endfunction 40 | function void build(); 41 | `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, '{}, 1, 0, 0, "") 42 | endfunction 43 | function void setup_index_fields(); 44 | setup_index_field("register_file_0.register_0.bit_field_0", array_index[0]); 45 | setup_index_field("register_file_0.register_1.bit_field_0", 8'h00); 46 | endfunction 47 | endclass 48 | class register_file_1_register_1_reg_model extends rggen_ral_indirect_reg; 49 | rand rggen_ral_field bit_field_0; 50 | function new(string name); 51 | super.new(name, 32, 0); 52 | endfunction 53 | function void build(); 54 | `rggen_ral_create_field(bit_field_0, 0, 8, "RW", 0, 8'h00, '{}, 1, 0, 0, "") 55 | endfunction 56 | function void setup_index_fields(); 57 | setup_index_field("register_file_0.register_0.bit_field_0", array_index[0]); 58 | setup_index_field("register_file_0.register_1.bit_field_0", 8'h01); 59 | endfunction 60 | endclass 61 | class register_file_1_reg_file_model extends rggen_ral_reg_file; 62 | rand register_file_1_register_0_reg_model register_0[2]; 63 | rand register_file_1_register_1_reg_model register_1[2]; 64 | function new(string name); 65 | super.new(name, 4, 0); 66 | endfunction 67 | function void build(); 68 | `rggen_ral_create_reg(register_0[0], '{0}, '{2}, 7'h00, "RW", "g_register_0.g[0].u_register") 69 | `rggen_ral_create_reg(register_0[1], '{1}, '{2}, 7'h00, "RW", "g_register_0.g[1].u_register") 70 | `rggen_ral_create_reg(register_1[0], '{0}, '{2}, 7'h00, "RW", "g_register_1.g[0].u_register") 71 | `rggen_ral_create_reg(register_1[1], '{1}, '{2}, 7'h00, "RW", "g_register_1.g[1].u_register") 72 | endfunction 73 | endclass 74 | class register_file_2_register_file_0_register_0_reg_model extends rggen_ral_reg; 75 | rand rggen_ral_field bit_field_0[2]; 76 | rand rggen_ral_rwe_field bit_field_1[2]; 77 | rand rggen_ral_rwl_field bit_field_2[2]; 78 | function new(string name); 79 | super.new(name, 32, 0); 80 | endfunction 81 | function void build(); 82 | `rggen_ral_create_field(bit_field_0[0], 0, 4, "RW", 0, 4'h0, '{}, 1, 0, 2, "") 83 | `rggen_ral_create_field(bit_field_0[1], 4, 4, "RW", 0, 4'h0, '{}, 1, 1, 2, "") 84 | `rggen_ral_create_field(bit_field_1[0], 8, 4, "RWE", 0, 4'h0, '{}, 1, 0, 2, "register_file_0.register_0.bit_field_0") 85 | `rggen_ral_create_field(bit_field_1[1], 12, 4, "RWE", 0, 4'h0, '{}, 1, 1, 2, "register_file_0.register_0.bit_field_0") 86 | `rggen_ral_create_field(bit_field_2[0], 16, 4, "RWL", 0, 4'h0, '{}, 1, 0, 2, "register_file_2.register_file_0.register_1.bit_field_0") 87 | `rggen_ral_create_field(bit_field_2[1], 20, 4, "RWL", 0, 4'h0, '{}, 1, 1, 2, "register_file_2.register_file_0.register_1.bit_field_0") 88 | endfunction 89 | endclass 90 | class register_file_2_register_file_0_register_1_reg_model extends rggen_ral_reg; 91 | rand rggen_ral_field bit_field_0[2]; 92 | function new(string name); 93 | super.new(name, 32, 0); 94 | endfunction 95 | function void build(); 96 | `rggen_ral_create_field(bit_field_0[0], 0, 1, "RW", 0, 1'h0, '{}, 1, 0, 2, "") 97 | `rggen_ral_create_field(bit_field_0[1], 1, 1, "RW", 0, 1'h0, '{}, 1, 1, 2, "") 98 | endfunction 99 | endclass 100 | class register_file_2_register_file_0_reg_file_model extends rggen_ral_reg_file; 101 | rand register_file_2_register_file_0_register_0_reg_model register_0[2][3]; 102 | rand register_file_2_register_file_0_register_1_reg_model register_1; 103 | function new(string name); 104 | super.new(name, 4, 0); 105 | endfunction 106 | function void build(); 107 | `rggen_ral_create_reg(register_0[0][0], '{0, 0}, '{2, 3}, 7'h00, "RW", "g_register_0.g[0].g[0].u_register") 108 | `rggen_ral_create_reg(register_0[0][1], '{0, 1}, '{2, 3}, 7'h04, "RW", "g_register_0.g[0].g[1].u_register") 109 | `rggen_ral_create_reg(register_0[0][2], '{0, 2}, '{2, 3}, 7'h08, "RW", "g_register_0.g[0].g[2].u_register") 110 | `rggen_ral_create_reg(register_0[1][0], '{1, 0}, '{2, 3}, 7'h0c, "RW", "g_register_0.g[1].g[0].u_register") 111 | `rggen_ral_create_reg(register_0[1][1], '{1, 1}, '{2, 3}, 7'h10, "RW", "g_register_0.g[1].g[1].u_register") 112 | `rggen_ral_create_reg(register_0[1][2], '{1, 2}, '{2, 3}, 7'h14, "RW", "g_register_0.g[1].g[2].u_register") 113 | `rggen_ral_create_reg(register_1, '{}, '{}, 7'h18, "RW", "g_register_1.u_register") 114 | endfunction 115 | endclass 116 | class register_file_2_reg_file_model extends rggen_ral_reg_file; 117 | rand register_file_2_register_file_0_reg_file_model register_file_0; 118 | function new(string name); 119 | super.new(name, 4, 0); 120 | endfunction 121 | function void build(); 122 | `rggen_ral_create_reg_file(register_file_0, '{}, '{}, 7'h00, "g_register_file_0") 123 | endfunction 124 | endclass 125 | class block_1_block_model extends rggen_ral_block; 126 | rand register_file_0_reg_file_model register_file_0; 127 | rand register_file_1_reg_file_model register_file_1; 128 | rand register_file_2_reg_file_model register_file_2[2]; 129 | function new(string name); 130 | super.new(name, 4, 0); 131 | endfunction 132 | function void build(); 133 | `rggen_ral_create_reg_file(register_file_0, '{}, '{}, 7'h00, "g_register_file_0") 134 | `rggen_ral_create_reg_file(register_file_1, '{}, '{}, 7'h10, "g_register_file_1") 135 | `rggen_ral_create_reg_file(register_file_2[0], '{0}, '{2}, 7'h20, "g_register_file_2.g[0]") 136 | `rggen_ral_create_reg_file(register_file_2[1], '{1}, '{2}, 7'h40, "g_register_file_2.g[1]") 137 | endfunction 138 | endclass 139 | endpackage 140 | -------------------------------------------------------------------------------- /rtl/apb/block_1.veryl: -------------------------------------------------------------------------------- 1 | #[fmt(skip)] 2 | pub module block_1 #( 3 | param ADDRESS_WIDTH: u32 = 7, 4 | param PRE_DECODE: bool = false, 5 | param BASE_ADDRESS: bit = '0, 6 | param ERROR_STATUS: bool = false, 7 | param DEFAULT_READ_DATA: bit<32> = '0, 8 | param INSERT_SLICER: bool = false 9 | )( 10 | i_clk: input clock, 11 | i_rst: input reset, 12 | apb_if: modport rggen::rggen_apb_if::slave, 13 | o_register_file_0_register_0_bit_field_0: output logic<8>, 14 | o_register_file_0_register_1_bit_field_0: output logic<8>, 15 | o_register_file_1_register_0_bit_field_0: output logic<2, 8>, 16 | o_register_file_1_register_1_bit_field_0: output logic<2, 8>, 17 | o_register_file_2_register_file_0_register_0_bit_field_0: output logic<2, 2, 3, 2, 4>, 18 | o_register_file_2_register_file_0_register_0_bit_field_1: output logic<2, 2, 3, 2, 4>, 19 | o_register_file_2_register_file_0_register_0_bit_field_2: output logic<2, 2, 3, 2, 4>, 20 | o_register_file_2_register_file_0_register_1_bit_field_0: output logic<2, 2> 21 | ){ 22 | import rggen::rggen_rtl_pkg::*; 23 | inst register_if: rggen::rggen_register_if[20]#(ADDRESS_WIDTH: 7, BUS_WIDTH: 32, VALUE_WIDTH: 32); 24 | inst u_adapter: rggen::rggen_apb_adapter #( 25 | ADDRESS_WIDTH: ADDRESS_WIDTH, 26 | LOCAL_ADDRESS_WIDTH: 7, 27 | BUS_WIDTH: 32, 28 | REGISTERS: 20, 29 | PRE_DECODE: PRE_DECODE, 30 | BASE_ADDRESS: BASE_ADDRESS, 31 | BYTE_SIZE: 128, 32 | ERROR_STATUS: ERROR_STATUS, 33 | DEFAULT_READ_DATA: DEFAULT_READ_DATA, 34 | INSERT_SLICER: INSERT_SLICER 35 | )( 36 | i_clk: i_clk, 37 | i_rst: i_rst, 38 | apb_if: apb_if, 39 | register_if: register_if 40 | ); 41 | :g_register_file_0 { 42 | :g_register_0 { 43 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 44 | inst u_register: rggen::rggen_default_register #( 45 | READABLE: true, 46 | WRITABLE: true, 47 | ADDRESS_WIDTH: 7, 48 | OFFSET_ADDRESS: 7'h00, 49 | BUS_WIDTH: 32, 50 | DATA_WIDTH: 32, 51 | VALUE_WIDTH: 32, 52 | VALID_BITS: 32'h000000ff 53 | )( 54 | i_clk: i_clk, 55 | i_rst: i_rst, 56 | register_if: register_if[0], 57 | bit_field_if: bit_field_if 58 | ); 59 | :g_bit_field_0 { 60 | const INITIAL_VALUE: bit<8> = 8'h00; 61 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 62 | always_comb { 63 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 64 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 65 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 66 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 67 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 68 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 69 | } 70 | inst u_bit_field: rggen::rggen_bit_field #( 71 | WIDTH: 8, 72 | INITIAL_VALUE: INITIAL_VALUE, 73 | SW_WRITE_ONCE: false, 74 | TRIGGER: false 75 | )( 76 | i_clk: i_clk, 77 | i_rst: i_rst, 78 | bit_field_if: bit_field_sub_if, 79 | o_write_trigger: _, 80 | o_read_trigger: _, 81 | o_value: o_register_file_0_register_0_bit_field_0 82 | ); 83 | } 84 | } 85 | :g_register_1 { 86 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 87 | inst u_register: rggen::rggen_default_register #( 88 | READABLE: true, 89 | WRITABLE: true, 90 | ADDRESS_WIDTH: 7, 91 | OFFSET_ADDRESS: 7'h04, 92 | BUS_WIDTH: 32, 93 | DATA_WIDTH: 32, 94 | VALUE_WIDTH: 32, 95 | VALID_BITS: 32'h000000ff 96 | )( 97 | i_clk: i_clk, 98 | i_rst: i_rst, 99 | register_if: register_if[1], 100 | bit_field_if: bit_field_if 101 | ); 102 | :g_bit_field_0 { 103 | const INITIAL_VALUE: bit<8> = 8'h00; 104 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 105 | always_comb { 106 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 107 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 108 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 109 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 110 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 111 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 112 | } 113 | inst u_bit_field: rggen::rggen_bit_field #( 114 | WIDTH: 8, 115 | INITIAL_VALUE: INITIAL_VALUE, 116 | SW_WRITE_ONCE: false, 117 | TRIGGER: false 118 | )( 119 | i_clk: i_clk, 120 | i_rst: i_rst, 121 | bit_field_if: bit_field_sub_if, 122 | o_write_trigger: _, 123 | o_read_trigger: _, 124 | o_value: o_register_file_0_register_1_bit_field_0 125 | ); 126 | } 127 | } 128 | } 129 | :g_register_file_1 { 130 | :g_register_0 { 131 | for i in 0..2 :g { 132 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 133 | var indirect_match: logic<2>; 134 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 135 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 136 | inst u_register: rggen::rggen_indirect_register #( 137 | READABLE: true, 138 | WRITABLE: true, 139 | ADDRESS_WIDTH: 7, 140 | OFFSET_ADDRESS: 7'h10, 141 | BUS_WIDTH: 32, 142 | DATA_WIDTH: 32, 143 | VALUE_WIDTH: 32, 144 | VALID_BITS: 32'h000000ff, 145 | INDIRECT_MATCH_WIDTH: 2 146 | )( 147 | i_clk: i_clk, 148 | i_rst: i_rst, 149 | register_if: register_if[2+i], 150 | i_indirect_match: indirect_match, 151 | bit_field_if: bit_field_if 152 | ); 153 | :g_bit_field_0 { 154 | const INITIAL_VALUE: bit<8> = 8'h00; 155 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 156 | always_comb { 157 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 158 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 159 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 160 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 161 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 162 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 163 | } 164 | inst u_bit_field: rggen::rggen_bit_field #( 165 | WIDTH: 8, 166 | INITIAL_VALUE: INITIAL_VALUE, 167 | SW_WRITE_ONCE: false, 168 | TRIGGER: false 169 | )( 170 | i_clk: i_clk, 171 | i_rst: i_rst, 172 | bit_field_if: bit_field_sub_if, 173 | o_write_trigger: _, 174 | o_read_trigger: _, 175 | o_value: o_register_file_1_register_0_bit_field_0[i] 176 | ); 177 | } 178 | } 179 | } 180 | :g_register_1 { 181 | for i in 0..2 :g { 182 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 183 | var indirect_match: logic<2>; 184 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 185 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 186 | inst u_register: rggen::rggen_indirect_register #( 187 | READABLE: true, 188 | WRITABLE: true, 189 | ADDRESS_WIDTH: 7, 190 | OFFSET_ADDRESS: 7'h10, 191 | BUS_WIDTH: 32, 192 | DATA_WIDTH: 32, 193 | VALUE_WIDTH: 32, 194 | VALID_BITS: 32'h000000ff, 195 | INDIRECT_MATCH_WIDTH: 2 196 | )( 197 | i_clk: i_clk, 198 | i_rst: i_rst, 199 | register_if: register_if[4+i], 200 | i_indirect_match: indirect_match, 201 | bit_field_if: bit_field_if 202 | ); 203 | :g_bit_field_0 { 204 | const INITIAL_VALUE: bit<8> = 8'h00; 205 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 206 | always_comb { 207 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 208 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 209 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 210 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 211 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 212 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 213 | } 214 | inst u_bit_field: rggen::rggen_bit_field #( 215 | WIDTH: 8, 216 | INITIAL_VALUE: INITIAL_VALUE, 217 | SW_WRITE_ONCE: false, 218 | TRIGGER: false 219 | )( 220 | i_clk: i_clk, 221 | i_rst: i_rst, 222 | bit_field_if: bit_field_sub_if, 223 | o_write_trigger: _, 224 | o_read_trigger: _, 225 | o_value: o_register_file_1_register_1_bit_field_0[i] 226 | ); 227 | } 228 | } 229 | } 230 | } 231 | :g_register_file_2 { 232 | for i in 0..2 :g { 233 | :g_register_file_0 { 234 | :g_register_0 { 235 | for j in 0..2 :g { 236 | for k in 0..3 :g { 237 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 238 | inst u_register: rggen::rggen_default_register #( 239 | READABLE: true, 240 | WRITABLE: true, 241 | ADDRESS_WIDTH: 7, 242 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+(4*(3*j+k) as 7), 243 | BUS_WIDTH: 32, 244 | DATA_WIDTH: 32, 245 | VALUE_WIDTH: 32, 246 | VALID_BITS: 32'h00ffffff 247 | )( 248 | i_clk: i_clk, 249 | i_rst: i_rst, 250 | register_if: register_if[6+7*i+3*j+k], 251 | bit_field_if: bit_field_if 252 | ); 253 | :g_bit_field_0 { 254 | for l in 0..2 :g { 255 | const INITIAL_VALUE: bit<4> = 4'h0; 256 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 257 | always_comb { 258 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 259 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 260 | bit_field_sub_if.mask = bit_field_if.mask[0+4*l+:4]; 261 | bit_field_sub_if.write_data = bit_field_if.write_data[0+4*l+:4]; 262 | bit_field_if.read_data[0+4*l+:4] = bit_field_sub_if.read_data; 263 | bit_field_if.value[0+4*l+:4] = bit_field_sub_if.value; 264 | } 265 | inst u_bit_field: rggen::rggen_bit_field #( 266 | WIDTH: 4, 267 | INITIAL_VALUE: INITIAL_VALUE, 268 | SW_WRITE_ONCE: false, 269 | TRIGGER: false 270 | )( 271 | i_clk: i_clk, 272 | i_rst: i_rst, 273 | bit_field_if: bit_field_sub_if, 274 | o_write_trigger: _, 275 | o_read_trigger: _, 276 | o_value: o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l] 277 | ); 278 | } 279 | } 280 | :g_bit_field_1 { 281 | for l in 0..2 :g { 282 | const INITIAL_VALUE: bit<4> = 4'h0; 283 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 284 | always_comb { 285 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 286 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 287 | bit_field_sub_if.mask = bit_field_if.mask[8+4*l+:4]; 288 | bit_field_sub_if.write_data = bit_field_if.write_data[8+4*l+:4]; 289 | bit_field_if.read_data[8+4*l+:4] = bit_field_sub_if.read_data; 290 | bit_field_if.value[8+4*l+:4] = bit_field_sub_if.value; 291 | } 292 | inst u_bit_field: rggen::rggen_bit_field #( 293 | WIDTH: 4, 294 | INITIAL_VALUE: INITIAL_VALUE, 295 | SW_WRITE_CONTROL: true, 296 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_HIGH 297 | )( 298 | i_clk: i_clk, 299 | i_rst: i_rst, 300 | bit_field_if: bit_field_sub_if, 301 | i_sw_write_enable: register_if[0].value[0+:1], 302 | o_value: o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l] 303 | ); 304 | } 305 | } 306 | :g_bit_field_2 { 307 | for l in 0..2 :g { 308 | const INITIAL_VALUE: bit<4> = 4'h0; 309 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 310 | always_comb { 311 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 312 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 313 | bit_field_sub_if.mask = bit_field_if.mask[16+4*l+:4]; 314 | bit_field_sub_if.write_data = bit_field_if.write_data[16+4*l+:4]; 315 | bit_field_if.read_data[16+4*l+:4] = bit_field_sub_if.read_data; 316 | bit_field_if.value[16+4*l+:4] = bit_field_sub_if.value; 317 | } 318 | inst u_bit_field: rggen::rggen_bit_field #( 319 | WIDTH: 4, 320 | INITIAL_VALUE: INITIAL_VALUE, 321 | SW_WRITE_CONTROL: true, 322 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_LOW 323 | )( 324 | i_clk: i_clk, 325 | i_rst: i_rst, 326 | bit_field_if: bit_field_sub_if, 327 | i_sw_write_enable: register_if[6+7*i+6].value[0+1*l+:1], 328 | o_value: o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l] 329 | ); 330 | } 331 | } 332 | } 333 | } 334 | } 335 | :g_register_1 { 336 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 337 | inst u_register: rggen::rggen_default_register #( 338 | READABLE: true, 339 | WRITABLE: true, 340 | ADDRESS_WIDTH: 7, 341 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+7'h18, 342 | BUS_WIDTH: 32, 343 | DATA_WIDTH: 32, 344 | VALUE_WIDTH: 32, 345 | VALID_BITS: 32'h00000003 346 | )( 347 | i_clk: i_clk, 348 | i_rst: i_rst, 349 | register_if: register_if[6+7*i+6], 350 | bit_field_if: bit_field_if 351 | ); 352 | :g_bit_field_0 { 353 | for j in 0..2 :g { 354 | const INITIAL_VALUE: bit = 1'h0; 355 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 1); 356 | always_comb { 357 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 358 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 359 | bit_field_sub_if.mask = bit_field_if.mask[0+1*j+:1]; 360 | bit_field_sub_if.write_data = bit_field_if.write_data[0+1*j+:1]; 361 | bit_field_if.read_data[0+1*j+:1] = bit_field_sub_if.read_data; 362 | bit_field_if.value[0+1*j+:1] = bit_field_sub_if.value; 363 | } 364 | inst u_bit_field: rggen::rggen_bit_field #( 365 | WIDTH: 1, 366 | INITIAL_VALUE: INITIAL_VALUE, 367 | SW_WRITE_ONCE: false, 368 | TRIGGER: false 369 | )( 370 | i_clk: i_clk, 371 | i_rst: i_rst, 372 | bit_field_if: bit_field_sub_if, 373 | o_write_trigger: _, 374 | o_read_trigger: _, 375 | o_value: o_register_file_2_register_file_0_register_1_bit_field_0[i][j] 376 | ); 377 | } 378 | } 379 | } 380 | } 381 | } 382 | } 383 | } 384 | -------------------------------------------------------------------------------- /rtl/avalon/block_1.veryl: -------------------------------------------------------------------------------- 1 | #[fmt(skip)] 2 | pub module block_1 #( 3 | param ADDRESS_WIDTH: u32 = 7, 4 | param PRE_DECODE: bool = false, 5 | param BASE_ADDRESS: bit = '0, 6 | param ERROR_STATUS: bool = false, 7 | param DEFAULT_READ_DATA: bit<32> = '0, 8 | param INSERT_SLICER: bool = false 9 | )( 10 | i_clk: input clock, 11 | i_rst: input reset, 12 | avalon_if: modport rggen::rggen_avalon_if::agent, 13 | o_register_file_0_register_0_bit_field_0: output logic<8>, 14 | o_register_file_0_register_1_bit_field_0: output logic<8>, 15 | o_register_file_1_register_0_bit_field_0: output logic<2, 8>, 16 | o_register_file_1_register_1_bit_field_0: output logic<2, 8>, 17 | o_register_file_2_register_file_0_register_0_bit_field_0: output logic<2, 2, 3, 2, 4>, 18 | o_register_file_2_register_file_0_register_0_bit_field_1: output logic<2, 2, 3, 2, 4>, 19 | o_register_file_2_register_file_0_register_0_bit_field_2: output logic<2, 2, 3, 2, 4>, 20 | o_register_file_2_register_file_0_register_1_bit_field_0: output logic<2, 2> 21 | ){ 22 | import rggen::rggen_rtl_pkg::*; 23 | inst register_if: rggen::rggen_register_if[20]#(ADDRESS_WIDTH: 7, BUS_WIDTH: 32, VALUE_WIDTH: 32); 24 | inst u_adapter: rggen::rggen_avalon_adapter #( 25 | ADDRESS_WIDTH: ADDRESS_WIDTH, 26 | LOCAL_ADDRESS_WIDTH: 7, 27 | BUS_WIDTH: 32, 28 | REGISTERS: 20, 29 | PRE_DECODE: PRE_DECODE, 30 | BASE_ADDRESS: BASE_ADDRESS, 31 | BYTE_SIZE: 128, 32 | ERROR_STATUS: ERROR_STATUS, 33 | DEFAULT_READ_DATA: DEFAULT_READ_DATA, 34 | INSERT_SLICER: INSERT_SLICER 35 | )( 36 | i_clk: i_clk, 37 | i_rst: i_rst, 38 | avalon_if: avalon_if, 39 | register_if: register_if 40 | ); 41 | :g_register_file_0 { 42 | :g_register_0 { 43 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 44 | inst u_register: rggen::rggen_default_register #( 45 | READABLE: true, 46 | WRITABLE: true, 47 | ADDRESS_WIDTH: 7, 48 | OFFSET_ADDRESS: 7'h00, 49 | BUS_WIDTH: 32, 50 | DATA_WIDTH: 32, 51 | VALUE_WIDTH: 32, 52 | VALID_BITS: 32'h000000ff 53 | )( 54 | i_clk: i_clk, 55 | i_rst: i_rst, 56 | register_if: register_if[0], 57 | bit_field_if: bit_field_if 58 | ); 59 | :g_bit_field_0 { 60 | const INITIAL_VALUE: bit<8> = 8'h00; 61 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 62 | always_comb { 63 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 64 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 65 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 66 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 67 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 68 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 69 | } 70 | inst u_bit_field: rggen::rggen_bit_field #( 71 | WIDTH: 8, 72 | INITIAL_VALUE: INITIAL_VALUE, 73 | SW_WRITE_ONCE: false, 74 | TRIGGER: false 75 | )( 76 | i_clk: i_clk, 77 | i_rst: i_rst, 78 | bit_field_if: bit_field_sub_if, 79 | o_write_trigger: _, 80 | o_read_trigger: _, 81 | o_value: o_register_file_0_register_0_bit_field_0 82 | ); 83 | } 84 | } 85 | :g_register_1 { 86 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 87 | inst u_register: rggen::rggen_default_register #( 88 | READABLE: true, 89 | WRITABLE: true, 90 | ADDRESS_WIDTH: 7, 91 | OFFSET_ADDRESS: 7'h04, 92 | BUS_WIDTH: 32, 93 | DATA_WIDTH: 32, 94 | VALUE_WIDTH: 32, 95 | VALID_BITS: 32'h000000ff 96 | )( 97 | i_clk: i_clk, 98 | i_rst: i_rst, 99 | register_if: register_if[1], 100 | bit_field_if: bit_field_if 101 | ); 102 | :g_bit_field_0 { 103 | const INITIAL_VALUE: bit<8> = 8'h00; 104 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 105 | always_comb { 106 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 107 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 108 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 109 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 110 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 111 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 112 | } 113 | inst u_bit_field: rggen::rggen_bit_field #( 114 | WIDTH: 8, 115 | INITIAL_VALUE: INITIAL_VALUE, 116 | SW_WRITE_ONCE: false, 117 | TRIGGER: false 118 | )( 119 | i_clk: i_clk, 120 | i_rst: i_rst, 121 | bit_field_if: bit_field_sub_if, 122 | o_write_trigger: _, 123 | o_read_trigger: _, 124 | o_value: o_register_file_0_register_1_bit_field_0 125 | ); 126 | } 127 | } 128 | } 129 | :g_register_file_1 { 130 | :g_register_0 { 131 | for i in 0..2 :g { 132 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 133 | var indirect_match: logic<2>; 134 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 135 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 136 | inst u_register: rggen::rggen_indirect_register #( 137 | READABLE: true, 138 | WRITABLE: true, 139 | ADDRESS_WIDTH: 7, 140 | OFFSET_ADDRESS: 7'h10, 141 | BUS_WIDTH: 32, 142 | DATA_WIDTH: 32, 143 | VALUE_WIDTH: 32, 144 | VALID_BITS: 32'h000000ff, 145 | INDIRECT_MATCH_WIDTH: 2 146 | )( 147 | i_clk: i_clk, 148 | i_rst: i_rst, 149 | register_if: register_if[2+i], 150 | i_indirect_match: indirect_match, 151 | bit_field_if: bit_field_if 152 | ); 153 | :g_bit_field_0 { 154 | const INITIAL_VALUE: bit<8> = 8'h00; 155 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 156 | always_comb { 157 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 158 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 159 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 160 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 161 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 162 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 163 | } 164 | inst u_bit_field: rggen::rggen_bit_field #( 165 | WIDTH: 8, 166 | INITIAL_VALUE: INITIAL_VALUE, 167 | SW_WRITE_ONCE: false, 168 | TRIGGER: false 169 | )( 170 | i_clk: i_clk, 171 | i_rst: i_rst, 172 | bit_field_if: bit_field_sub_if, 173 | o_write_trigger: _, 174 | o_read_trigger: _, 175 | o_value: o_register_file_1_register_0_bit_field_0[i] 176 | ); 177 | } 178 | } 179 | } 180 | :g_register_1 { 181 | for i in 0..2 :g { 182 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 183 | var indirect_match: logic<2>; 184 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 185 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 186 | inst u_register: rggen::rggen_indirect_register #( 187 | READABLE: true, 188 | WRITABLE: true, 189 | ADDRESS_WIDTH: 7, 190 | OFFSET_ADDRESS: 7'h10, 191 | BUS_WIDTH: 32, 192 | DATA_WIDTH: 32, 193 | VALUE_WIDTH: 32, 194 | VALID_BITS: 32'h000000ff, 195 | INDIRECT_MATCH_WIDTH: 2 196 | )( 197 | i_clk: i_clk, 198 | i_rst: i_rst, 199 | register_if: register_if[4+i], 200 | i_indirect_match: indirect_match, 201 | bit_field_if: bit_field_if 202 | ); 203 | :g_bit_field_0 { 204 | const INITIAL_VALUE: bit<8> = 8'h00; 205 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 206 | always_comb { 207 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 208 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 209 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 210 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 211 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 212 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 213 | } 214 | inst u_bit_field: rggen::rggen_bit_field #( 215 | WIDTH: 8, 216 | INITIAL_VALUE: INITIAL_VALUE, 217 | SW_WRITE_ONCE: false, 218 | TRIGGER: false 219 | )( 220 | i_clk: i_clk, 221 | i_rst: i_rst, 222 | bit_field_if: bit_field_sub_if, 223 | o_write_trigger: _, 224 | o_read_trigger: _, 225 | o_value: o_register_file_1_register_1_bit_field_0[i] 226 | ); 227 | } 228 | } 229 | } 230 | } 231 | :g_register_file_2 { 232 | for i in 0..2 :g { 233 | :g_register_file_0 { 234 | :g_register_0 { 235 | for j in 0..2 :g { 236 | for k in 0..3 :g { 237 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 238 | inst u_register: rggen::rggen_default_register #( 239 | READABLE: true, 240 | WRITABLE: true, 241 | ADDRESS_WIDTH: 7, 242 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+(4*(3*j+k) as 7), 243 | BUS_WIDTH: 32, 244 | DATA_WIDTH: 32, 245 | VALUE_WIDTH: 32, 246 | VALID_BITS: 32'h00ffffff 247 | )( 248 | i_clk: i_clk, 249 | i_rst: i_rst, 250 | register_if: register_if[6+7*i+3*j+k], 251 | bit_field_if: bit_field_if 252 | ); 253 | :g_bit_field_0 { 254 | for l in 0..2 :g { 255 | const INITIAL_VALUE: bit<4> = 4'h0; 256 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 257 | always_comb { 258 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 259 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 260 | bit_field_sub_if.mask = bit_field_if.mask[0+4*l+:4]; 261 | bit_field_sub_if.write_data = bit_field_if.write_data[0+4*l+:4]; 262 | bit_field_if.read_data[0+4*l+:4] = bit_field_sub_if.read_data; 263 | bit_field_if.value[0+4*l+:4] = bit_field_sub_if.value; 264 | } 265 | inst u_bit_field: rggen::rggen_bit_field #( 266 | WIDTH: 4, 267 | INITIAL_VALUE: INITIAL_VALUE, 268 | SW_WRITE_ONCE: false, 269 | TRIGGER: false 270 | )( 271 | i_clk: i_clk, 272 | i_rst: i_rst, 273 | bit_field_if: bit_field_sub_if, 274 | o_write_trigger: _, 275 | o_read_trigger: _, 276 | o_value: o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l] 277 | ); 278 | } 279 | } 280 | :g_bit_field_1 { 281 | for l in 0..2 :g { 282 | const INITIAL_VALUE: bit<4> = 4'h0; 283 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 284 | always_comb { 285 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 286 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 287 | bit_field_sub_if.mask = bit_field_if.mask[8+4*l+:4]; 288 | bit_field_sub_if.write_data = bit_field_if.write_data[8+4*l+:4]; 289 | bit_field_if.read_data[8+4*l+:4] = bit_field_sub_if.read_data; 290 | bit_field_if.value[8+4*l+:4] = bit_field_sub_if.value; 291 | } 292 | inst u_bit_field: rggen::rggen_bit_field #( 293 | WIDTH: 4, 294 | INITIAL_VALUE: INITIAL_VALUE, 295 | SW_WRITE_CONTROL: true, 296 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_HIGH 297 | )( 298 | i_clk: i_clk, 299 | i_rst: i_rst, 300 | bit_field_if: bit_field_sub_if, 301 | i_sw_write_enable: register_if[0].value[0+:1], 302 | o_value: o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l] 303 | ); 304 | } 305 | } 306 | :g_bit_field_2 { 307 | for l in 0..2 :g { 308 | const INITIAL_VALUE: bit<4> = 4'h0; 309 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 310 | always_comb { 311 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 312 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 313 | bit_field_sub_if.mask = bit_field_if.mask[16+4*l+:4]; 314 | bit_field_sub_if.write_data = bit_field_if.write_data[16+4*l+:4]; 315 | bit_field_if.read_data[16+4*l+:4] = bit_field_sub_if.read_data; 316 | bit_field_if.value[16+4*l+:4] = bit_field_sub_if.value; 317 | } 318 | inst u_bit_field: rggen::rggen_bit_field #( 319 | WIDTH: 4, 320 | INITIAL_VALUE: INITIAL_VALUE, 321 | SW_WRITE_CONTROL: true, 322 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_LOW 323 | )( 324 | i_clk: i_clk, 325 | i_rst: i_rst, 326 | bit_field_if: bit_field_sub_if, 327 | i_sw_write_enable: register_if[6+7*i+6].value[0+1*l+:1], 328 | o_value: o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l] 329 | ); 330 | } 331 | } 332 | } 333 | } 334 | } 335 | :g_register_1 { 336 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 337 | inst u_register: rggen::rggen_default_register #( 338 | READABLE: true, 339 | WRITABLE: true, 340 | ADDRESS_WIDTH: 7, 341 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+7'h18, 342 | BUS_WIDTH: 32, 343 | DATA_WIDTH: 32, 344 | VALUE_WIDTH: 32, 345 | VALID_BITS: 32'h00000003 346 | )( 347 | i_clk: i_clk, 348 | i_rst: i_rst, 349 | register_if: register_if[6+7*i+6], 350 | bit_field_if: bit_field_if 351 | ); 352 | :g_bit_field_0 { 353 | for j in 0..2 :g { 354 | const INITIAL_VALUE: bit = 1'h0; 355 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 1); 356 | always_comb { 357 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 358 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 359 | bit_field_sub_if.mask = bit_field_if.mask[0+1*j+:1]; 360 | bit_field_sub_if.write_data = bit_field_if.write_data[0+1*j+:1]; 361 | bit_field_if.read_data[0+1*j+:1] = bit_field_sub_if.read_data; 362 | bit_field_if.value[0+1*j+:1] = bit_field_sub_if.value; 363 | } 364 | inst u_bit_field: rggen::rggen_bit_field #( 365 | WIDTH: 1, 366 | INITIAL_VALUE: INITIAL_VALUE, 367 | SW_WRITE_ONCE: false, 368 | TRIGGER: false 369 | )( 370 | i_clk: i_clk, 371 | i_rst: i_rst, 372 | bit_field_if: bit_field_sub_if, 373 | o_write_trigger: _, 374 | o_read_trigger: _, 375 | o_value: o_register_file_2_register_file_0_register_1_bit_field_0[i][j] 376 | ); 377 | } 378 | } 379 | } 380 | } 381 | } 382 | } 383 | } 384 | -------------------------------------------------------------------------------- /rtl/wishbone/block_1.veryl: -------------------------------------------------------------------------------- 1 | #[fmt(skip)] 2 | pub module block_1 #( 3 | param ADDRESS_WIDTH: u32 = 7, 4 | param PRE_DECODE: bool = false, 5 | param BASE_ADDRESS: bit = '0, 6 | param ERROR_STATUS: bool = false, 7 | param DEFAULT_READ_DATA: bit<32> = '0, 8 | param INSERT_SLICER: bool = false, 9 | param USE_STALL: bit = 1 10 | )( 11 | i_clk: input clock, 12 | i_rst: input reset, 13 | wishbone_if: modport rggen::rggen_wishbone_if::slave, 14 | o_register_file_0_register_0_bit_field_0: output logic<8>, 15 | o_register_file_0_register_1_bit_field_0: output logic<8>, 16 | o_register_file_1_register_0_bit_field_0: output logic<2, 8>, 17 | o_register_file_1_register_1_bit_field_0: output logic<2, 8>, 18 | o_register_file_2_register_file_0_register_0_bit_field_0: output logic<2, 2, 3, 2, 4>, 19 | o_register_file_2_register_file_0_register_0_bit_field_1: output logic<2, 2, 3, 2, 4>, 20 | o_register_file_2_register_file_0_register_0_bit_field_2: output logic<2, 2, 3, 2, 4>, 21 | o_register_file_2_register_file_0_register_1_bit_field_0: output logic<2, 2> 22 | ){ 23 | import rggen::rggen_rtl_pkg::*; 24 | inst register_if: rggen::rggen_register_if[20]#(ADDRESS_WIDTH: 7, BUS_WIDTH: 32, VALUE_WIDTH: 32); 25 | inst u_adapter: rggen::rggen_wishbone_adapter #( 26 | ADDRESS_WIDTH: ADDRESS_WIDTH, 27 | LOCAL_ADDRESS_WIDTH: 7, 28 | BUS_WIDTH: 32, 29 | REGISTERS: 20, 30 | PRE_DECODE: PRE_DECODE, 31 | BASE_ADDRESS: BASE_ADDRESS, 32 | BYTE_SIZE: 128, 33 | ERROR_STATUS: ERROR_STATUS, 34 | DEFAULT_READ_DATA: DEFAULT_READ_DATA, 35 | INSERT_SLICER: INSERT_SLICER, 36 | USE_STALL: USE_STALL 37 | )( 38 | i_clk: i_clk, 39 | i_rst: i_rst, 40 | wishbone_if: wishbone_if, 41 | register_if: register_if 42 | ); 43 | :g_register_file_0 { 44 | :g_register_0 { 45 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 46 | inst u_register: rggen::rggen_default_register #( 47 | READABLE: true, 48 | WRITABLE: true, 49 | ADDRESS_WIDTH: 7, 50 | OFFSET_ADDRESS: 7'h00, 51 | BUS_WIDTH: 32, 52 | DATA_WIDTH: 32, 53 | VALUE_WIDTH: 32, 54 | VALID_BITS: 32'h000000ff 55 | )( 56 | i_clk: i_clk, 57 | i_rst: i_rst, 58 | register_if: register_if[0], 59 | bit_field_if: bit_field_if 60 | ); 61 | :g_bit_field_0 { 62 | const INITIAL_VALUE: bit<8> = 8'h00; 63 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 64 | always_comb { 65 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 66 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 67 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 68 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 69 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 70 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 71 | } 72 | inst u_bit_field: rggen::rggen_bit_field #( 73 | WIDTH: 8, 74 | INITIAL_VALUE: INITIAL_VALUE, 75 | SW_WRITE_ONCE: false, 76 | TRIGGER: false 77 | )( 78 | i_clk: i_clk, 79 | i_rst: i_rst, 80 | bit_field_if: bit_field_sub_if, 81 | o_write_trigger: _, 82 | o_read_trigger: _, 83 | o_value: o_register_file_0_register_0_bit_field_0 84 | ); 85 | } 86 | } 87 | :g_register_1 { 88 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 89 | inst u_register: rggen::rggen_default_register #( 90 | READABLE: true, 91 | WRITABLE: true, 92 | ADDRESS_WIDTH: 7, 93 | OFFSET_ADDRESS: 7'h04, 94 | BUS_WIDTH: 32, 95 | DATA_WIDTH: 32, 96 | VALUE_WIDTH: 32, 97 | VALID_BITS: 32'h000000ff 98 | )( 99 | i_clk: i_clk, 100 | i_rst: i_rst, 101 | register_if: register_if[1], 102 | bit_field_if: bit_field_if 103 | ); 104 | :g_bit_field_0 { 105 | const INITIAL_VALUE: bit<8> = 8'h00; 106 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 107 | always_comb { 108 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 109 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 110 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 111 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 112 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 113 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 114 | } 115 | inst u_bit_field: rggen::rggen_bit_field #( 116 | WIDTH: 8, 117 | INITIAL_VALUE: INITIAL_VALUE, 118 | SW_WRITE_ONCE: false, 119 | TRIGGER: false 120 | )( 121 | i_clk: i_clk, 122 | i_rst: i_rst, 123 | bit_field_if: bit_field_sub_if, 124 | o_write_trigger: _, 125 | o_read_trigger: _, 126 | o_value: o_register_file_0_register_1_bit_field_0 127 | ); 128 | } 129 | } 130 | } 131 | :g_register_file_1 { 132 | :g_register_0 { 133 | for i in 0..2 :g { 134 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 135 | var indirect_match: logic<2>; 136 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 137 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 138 | inst u_register: rggen::rggen_indirect_register #( 139 | READABLE: true, 140 | WRITABLE: true, 141 | ADDRESS_WIDTH: 7, 142 | OFFSET_ADDRESS: 7'h10, 143 | BUS_WIDTH: 32, 144 | DATA_WIDTH: 32, 145 | VALUE_WIDTH: 32, 146 | VALID_BITS: 32'h000000ff, 147 | INDIRECT_MATCH_WIDTH: 2 148 | )( 149 | i_clk: i_clk, 150 | i_rst: i_rst, 151 | register_if: register_if[2+i], 152 | i_indirect_match: indirect_match, 153 | bit_field_if: bit_field_if 154 | ); 155 | :g_bit_field_0 { 156 | const INITIAL_VALUE: bit<8> = 8'h00; 157 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 158 | always_comb { 159 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 160 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 161 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 162 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 163 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 164 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 165 | } 166 | inst u_bit_field: rggen::rggen_bit_field #( 167 | WIDTH: 8, 168 | INITIAL_VALUE: INITIAL_VALUE, 169 | SW_WRITE_ONCE: false, 170 | TRIGGER: false 171 | )( 172 | i_clk: i_clk, 173 | i_rst: i_rst, 174 | bit_field_if: bit_field_sub_if, 175 | o_write_trigger: _, 176 | o_read_trigger: _, 177 | o_value: o_register_file_1_register_0_bit_field_0[i] 178 | ); 179 | } 180 | } 181 | } 182 | :g_register_1 { 183 | for i in 0..2 :g { 184 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 185 | var indirect_match: logic<2>; 186 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 187 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 188 | inst u_register: rggen::rggen_indirect_register #( 189 | READABLE: true, 190 | WRITABLE: true, 191 | ADDRESS_WIDTH: 7, 192 | OFFSET_ADDRESS: 7'h10, 193 | BUS_WIDTH: 32, 194 | DATA_WIDTH: 32, 195 | VALUE_WIDTH: 32, 196 | VALID_BITS: 32'h000000ff, 197 | INDIRECT_MATCH_WIDTH: 2 198 | )( 199 | i_clk: i_clk, 200 | i_rst: i_rst, 201 | register_if: register_if[4+i], 202 | i_indirect_match: indirect_match, 203 | bit_field_if: bit_field_if 204 | ); 205 | :g_bit_field_0 { 206 | const INITIAL_VALUE: bit<8> = 8'h00; 207 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 208 | always_comb { 209 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 210 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 211 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 212 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 213 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 214 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 215 | } 216 | inst u_bit_field: rggen::rggen_bit_field #( 217 | WIDTH: 8, 218 | INITIAL_VALUE: INITIAL_VALUE, 219 | SW_WRITE_ONCE: false, 220 | TRIGGER: false 221 | )( 222 | i_clk: i_clk, 223 | i_rst: i_rst, 224 | bit_field_if: bit_field_sub_if, 225 | o_write_trigger: _, 226 | o_read_trigger: _, 227 | o_value: o_register_file_1_register_1_bit_field_0[i] 228 | ); 229 | } 230 | } 231 | } 232 | } 233 | :g_register_file_2 { 234 | for i in 0..2 :g { 235 | :g_register_file_0 { 236 | :g_register_0 { 237 | for j in 0..2 :g { 238 | for k in 0..3 :g { 239 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 240 | inst u_register: rggen::rggen_default_register #( 241 | READABLE: true, 242 | WRITABLE: true, 243 | ADDRESS_WIDTH: 7, 244 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+(4*(3*j+k) as 7), 245 | BUS_WIDTH: 32, 246 | DATA_WIDTH: 32, 247 | VALUE_WIDTH: 32, 248 | VALID_BITS: 32'h00ffffff 249 | )( 250 | i_clk: i_clk, 251 | i_rst: i_rst, 252 | register_if: register_if[6+7*i+3*j+k], 253 | bit_field_if: bit_field_if 254 | ); 255 | :g_bit_field_0 { 256 | for l in 0..2 :g { 257 | const INITIAL_VALUE: bit<4> = 4'h0; 258 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 259 | always_comb { 260 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 261 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 262 | bit_field_sub_if.mask = bit_field_if.mask[0+4*l+:4]; 263 | bit_field_sub_if.write_data = bit_field_if.write_data[0+4*l+:4]; 264 | bit_field_if.read_data[0+4*l+:4] = bit_field_sub_if.read_data; 265 | bit_field_if.value[0+4*l+:4] = bit_field_sub_if.value; 266 | } 267 | inst u_bit_field: rggen::rggen_bit_field #( 268 | WIDTH: 4, 269 | INITIAL_VALUE: INITIAL_VALUE, 270 | SW_WRITE_ONCE: false, 271 | TRIGGER: false 272 | )( 273 | i_clk: i_clk, 274 | i_rst: i_rst, 275 | bit_field_if: bit_field_sub_if, 276 | o_write_trigger: _, 277 | o_read_trigger: _, 278 | o_value: o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l] 279 | ); 280 | } 281 | } 282 | :g_bit_field_1 { 283 | for l in 0..2 :g { 284 | const INITIAL_VALUE: bit<4> = 4'h0; 285 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 286 | always_comb { 287 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 288 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 289 | bit_field_sub_if.mask = bit_field_if.mask[8+4*l+:4]; 290 | bit_field_sub_if.write_data = bit_field_if.write_data[8+4*l+:4]; 291 | bit_field_if.read_data[8+4*l+:4] = bit_field_sub_if.read_data; 292 | bit_field_if.value[8+4*l+:4] = bit_field_sub_if.value; 293 | } 294 | inst u_bit_field: rggen::rggen_bit_field #( 295 | WIDTH: 4, 296 | INITIAL_VALUE: INITIAL_VALUE, 297 | SW_WRITE_CONTROL: true, 298 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_HIGH 299 | )( 300 | i_clk: i_clk, 301 | i_rst: i_rst, 302 | bit_field_if: bit_field_sub_if, 303 | i_sw_write_enable: register_if[0].value[0+:1], 304 | o_value: o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l] 305 | ); 306 | } 307 | } 308 | :g_bit_field_2 { 309 | for l in 0..2 :g { 310 | const INITIAL_VALUE: bit<4> = 4'h0; 311 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 312 | always_comb { 313 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 314 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 315 | bit_field_sub_if.mask = bit_field_if.mask[16+4*l+:4]; 316 | bit_field_sub_if.write_data = bit_field_if.write_data[16+4*l+:4]; 317 | bit_field_if.read_data[16+4*l+:4] = bit_field_sub_if.read_data; 318 | bit_field_if.value[16+4*l+:4] = bit_field_sub_if.value; 319 | } 320 | inst u_bit_field: rggen::rggen_bit_field #( 321 | WIDTH: 4, 322 | INITIAL_VALUE: INITIAL_VALUE, 323 | SW_WRITE_CONTROL: true, 324 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_LOW 325 | )( 326 | i_clk: i_clk, 327 | i_rst: i_rst, 328 | bit_field_if: bit_field_sub_if, 329 | i_sw_write_enable: register_if[6+7*i+6].value[0+1*l+:1], 330 | o_value: o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l] 331 | ); 332 | } 333 | } 334 | } 335 | } 336 | } 337 | :g_register_1 { 338 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 339 | inst u_register: rggen::rggen_default_register #( 340 | READABLE: true, 341 | WRITABLE: true, 342 | ADDRESS_WIDTH: 7, 343 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+7'h18, 344 | BUS_WIDTH: 32, 345 | DATA_WIDTH: 32, 346 | VALUE_WIDTH: 32, 347 | VALID_BITS: 32'h00000003 348 | )( 349 | i_clk: i_clk, 350 | i_rst: i_rst, 351 | register_if: register_if[6+7*i+6], 352 | bit_field_if: bit_field_if 353 | ); 354 | :g_bit_field_0 { 355 | for j in 0..2 :g { 356 | const INITIAL_VALUE: bit = 1'h0; 357 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 1); 358 | always_comb { 359 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 360 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 361 | bit_field_sub_if.mask = bit_field_if.mask[0+1*j+:1]; 362 | bit_field_sub_if.write_data = bit_field_if.write_data[0+1*j+:1]; 363 | bit_field_if.read_data[0+1*j+:1] = bit_field_sub_if.read_data; 364 | bit_field_if.value[0+1*j+:1] = bit_field_sub_if.value; 365 | } 366 | inst u_bit_field: rggen::rggen_bit_field #( 367 | WIDTH: 1, 368 | INITIAL_VALUE: INITIAL_VALUE, 369 | SW_WRITE_ONCE: false, 370 | TRIGGER: false 371 | )( 372 | i_clk: i_clk, 373 | i_rst: i_rst, 374 | bit_field_if: bit_field_sub_if, 375 | o_write_trigger: _, 376 | o_read_trigger: _, 377 | o_value: o_register_file_2_register_file_0_register_1_bit_field_0[i][j] 378 | ); 379 | } 380 | } 381 | } 382 | } 383 | } 384 | } 385 | } 386 | -------------------------------------------------------------------------------- /rtl/axi4lite/block_1.veryl: -------------------------------------------------------------------------------- 1 | #[fmt(skip)] 2 | pub module block_1 #( 3 | param ADDRESS_WIDTH: u32 = 7, 4 | param PRE_DECODE: bool = false, 5 | param BASE_ADDRESS: bit = '0, 6 | param ERROR_STATUS: bool = false, 7 | param DEFAULT_READ_DATA: bit<32> = '0, 8 | param INSERT_SLICER: bool = false, 9 | param ID_WIDTH: u32 = 0, 10 | param WRITE_FIRST: bool = true 11 | )( 12 | i_clk: input clock, 13 | i_rst: input reset, 14 | axi4lite_if: modport rggen::rggen_axi4lite_if::slave, 15 | o_register_file_0_register_0_bit_field_0: output logic<8>, 16 | o_register_file_0_register_1_bit_field_0: output logic<8>, 17 | o_register_file_1_register_0_bit_field_0: output logic<2, 8>, 18 | o_register_file_1_register_1_bit_field_0: output logic<2, 8>, 19 | o_register_file_2_register_file_0_register_0_bit_field_0: output logic<2, 2, 3, 2, 4>, 20 | o_register_file_2_register_file_0_register_0_bit_field_1: output logic<2, 2, 3, 2, 4>, 21 | o_register_file_2_register_file_0_register_0_bit_field_2: output logic<2, 2, 3, 2, 4>, 22 | o_register_file_2_register_file_0_register_1_bit_field_0: output logic<2, 2> 23 | ){ 24 | import rggen::rggen_rtl_pkg::*; 25 | inst register_if: rggen::rggen_register_if[20]#(ADDRESS_WIDTH: 7, BUS_WIDTH: 32, VALUE_WIDTH: 32); 26 | inst u_adapter: rggen::rggen_axi4lite_adapter #( 27 | ID_WIDTH: ID_WIDTH, 28 | ADDRESS_WIDTH: ADDRESS_WIDTH, 29 | LOCAL_ADDRESS_WIDTH: 7, 30 | BUS_WIDTH: 32, 31 | REGISTERS: 20, 32 | PRE_DECODE: PRE_DECODE, 33 | BASE_ADDRESS: BASE_ADDRESS, 34 | BYTE_SIZE: 128, 35 | ERROR_STATUS: ERROR_STATUS, 36 | DEFAULT_READ_DATA: DEFAULT_READ_DATA, 37 | INSERT_SLICER: INSERT_SLICER, 38 | WRITE_FIRST: WRITE_FIRST 39 | )( 40 | i_clk: i_clk, 41 | i_rst: i_rst, 42 | axi4lite_if: axi4lite_if, 43 | register_if: register_if 44 | ); 45 | :g_register_file_0 { 46 | :g_register_0 { 47 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 48 | inst u_register: rggen::rggen_default_register #( 49 | READABLE: true, 50 | WRITABLE: true, 51 | ADDRESS_WIDTH: 7, 52 | OFFSET_ADDRESS: 7'h00, 53 | BUS_WIDTH: 32, 54 | DATA_WIDTH: 32, 55 | VALUE_WIDTH: 32, 56 | VALID_BITS: 32'h000000ff 57 | )( 58 | i_clk: i_clk, 59 | i_rst: i_rst, 60 | register_if: register_if[0], 61 | bit_field_if: bit_field_if 62 | ); 63 | :g_bit_field_0 { 64 | const INITIAL_VALUE: bit<8> = 8'h00; 65 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 66 | always_comb { 67 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 68 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 69 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 70 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 71 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 72 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 73 | } 74 | inst u_bit_field: rggen::rggen_bit_field #( 75 | WIDTH: 8, 76 | INITIAL_VALUE: INITIAL_VALUE, 77 | SW_WRITE_ONCE: false, 78 | TRIGGER: false 79 | )( 80 | i_clk: i_clk, 81 | i_rst: i_rst, 82 | bit_field_if: bit_field_sub_if, 83 | o_write_trigger: _, 84 | o_read_trigger: _, 85 | o_value: o_register_file_0_register_0_bit_field_0 86 | ); 87 | } 88 | } 89 | :g_register_1 { 90 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 91 | inst u_register: rggen::rggen_default_register #( 92 | READABLE: true, 93 | WRITABLE: true, 94 | ADDRESS_WIDTH: 7, 95 | OFFSET_ADDRESS: 7'h04, 96 | BUS_WIDTH: 32, 97 | DATA_WIDTH: 32, 98 | VALUE_WIDTH: 32, 99 | VALID_BITS: 32'h000000ff 100 | )( 101 | i_clk: i_clk, 102 | i_rst: i_rst, 103 | register_if: register_if[1], 104 | bit_field_if: bit_field_if 105 | ); 106 | :g_bit_field_0 { 107 | const INITIAL_VALUE: bit<8> = 8'h00; 108 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 109 | always_comb { 110 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 111 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 112 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 113 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 114 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 115 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 116 | } 117 | inst u_bit_field: rggen::rggen_bit_field #( 118 | WIDTH: 8, 119 | INITIAL_VALUE: INITIAL_VALUE, 120 | SW_WRITE_ONCE: false, 121 | TRIGGER: false 122 | )( 123 | i_clk: i_clk, 124 | i_rst: i_rst, 125 | bit_field_if: bit_field_sub_if, 126 | o_write_trigger: _, 127 | o_read_trigger: _, 128 | o_value: o_register_file_0_register_1_bit_field_0 129 | ); 130 | } 131 | } 132 | } 133 | :g_register_file_1 { 134 | :g_register_0 { 135 | for i in 0..2 :g { 136 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 137 | var indirect_match: logic<2>; 138 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 139 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 140 | inst u_register: rggen::rggen_indirect_register #( 141 | READABLE: true, 142 | WRITABLE: true, 143 | ADDRESS_WIDTH: 7, 144 | OFFSET_ADDRESS: 7'h10, 145 | BUS_WIDTH: 32, 146 | DATA_WIDTH: 32, 147 | VALUE_WIDTH: 32, 148 | VALID_BITS: 32'h000000ff, 149 | INDIRECT_MATCH_WIDTH: 2 150 | )( 151 | i_clk: i_clk, 152 | i_rst: i_rst, 153 | register_if: register_if[2+i], 154 | i_indirect_match: indirect_match, 155 | bit_field_if: bit_field_if 156 | ); 157 | :g_bit_field_0 { 158 | const INITIAL_VALUE: bit<8> = 8'h00; 159 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 160 | always_comb { 161 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 162 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 163 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 164 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 165 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 166 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 167 | } 168 | inst u_bit_field: rggen::rggen_bit_field #( 169 | WIDTH: 8, 170 | INITIAL_VALUE: INITIAL_VALUE, 171 | SW_WRITE_ONCE: false, 172 | TRIGGER: false 173 | )( 174 | i_clk: i_clk, 175 | i_rst: i_rst, 176 | bit_field_if: bit_field_sub_if, 177 | o_write_trigger: _, 178 | o_read_trigger: _, 179 | o_value: o_register_file_1_register_0_bit_field_0[i] 180 | ); 181 | } 182 | } 183 | } 184 | :g_register_1 { 185 | for i in 0..2 :g { 186 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 187 | var indirect_match: logic<2>; 188 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 189 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 190 | inst u_register: rggen::rggen_indirect_register #( 191 | READABLE: true, 192 | WRITABLE: true, 193 | ADDRESS_WIDTH: 7, 194 | OFFSET_ADDRESS: 7'h10, 195 | BUS_WIDTH: 32, 196 | DATA_WIDTH: 32, 197 | VALUE_WIDTH: 32, 198 | VALID_BITS: 32'h000000ff, 199 | INDIRECT_MATCH_WIDTH: 2 200 | )( 201 | i_clk: i_clk, 202 | i_rst: i_rst, 203 | register_if: register_if[4+i], 204 | i_indirect_match: indirect_match, 205 | bit_field_if: bit_field_if 206 | ); 207 | :g_bit_field_0 { 208 | const INITIAL_VALUE: bit<8> = 8'h00; 209 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 210 | always_comb { 211 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 212 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 213 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 214 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 215 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 216 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 217 | } 218 | inst u_bit_field: rggen::rggen_bit_field #( 219 | WIDTH: 8, 220 | INITIAL_VALUE: INITIAL_VALUE, 221 | SW_WRITE_ONCE: false, 222 | TRIGGER: false 223 | )( 224 | i_clk: i_clk, 225 | i_rst: i_rst, 226 | bit_field_if: bit_field_sub_if, 227 | o_write_trigger: _, 228 | o_read_trigger: _, 229 | o_value: o_register_file_1_register_1_bit_field_0[i] 230 | ); 231 | } 232 | } 233 | } 234 | } 235 | :g_register_file_2 { 236 | for i in 0..2 :g { 237 | :g_register_file_0 { 238 | :g_register_0 { 239 | for j in 0..2 :g { 240 | for k in 0..3 :g { 241 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 242 | inst u_register: rggen::rggen_default_register #( 243 | READABLE: true, 244 | WRITABLE: true, 245 | ADDRESS_WIDTH: 7, 246 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+(4*(3*j+k) as 7), 247 | BUS_WIDTH: 32, 248 | DATA_WIDTH: 32, 249 | VALUE_WIDTH: 32, 250 | VALID_BITS: 32'h00ffffff 251 | )( 252 | i_clk: i_clk, 253 | i_rst: i_rst, 254 | register_if: register_if[6+7*i+3*j+k], 255 | bit_field_if: bit_field_if 256 | ); 257 | :g_bit_field_0 { 258 | for l in 0..2 :g { 259 | const INITIAL_VALUE: bit<4> = 4'h0; 260 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 261 | always_comb { 262 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 263 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 264 | bit_field_sub_if.mask = bit_field_if.mask[0+4*l+:4]; 265 | bit_field_sub_if.write_data = bit_field_if.write_data[0+4*l+:4]; 266 | bit_field_if.read_data[0+4*l+:4] = bit_field_sub_if.read_data; 267 | bit_field_if.value[0+4*l+:4] = bit_field_sub_if.value; 268 | } 269 | inst u_bit_field: rggen::rggen_bit_field #( 270 | WIDTH: 4, 271 | INITIAL_VALUE: INITIAL_VALUE, 272 | SW_WRITE_ONCE: false, 273 | TRIGGER: false 274 | )( 275 | i_clk: i_clk, 276 | i_rst: i_rst, 277 | bit_field_if: bit_field_sub_if, 278 | o_write_trigger: _, 279 | o_read_trigger: _, 280 | o_value: o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l] 281 | ); 282 | } 283 | } 284 | :g_bit_field_1 { 285 | for l in 0..2 :g { 286 | const INITIAL_VALUE: bit<4> = 4'h0; 287 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 288 | always_comb { 289 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 290 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 291 | bit_field_sub_if.mask = bit_field_if.mask[8+4*l+:4]; 292 | bit_field_sub_if.write_data = bit_field_if.write_data[8+4*l+:4]; 293 | bit_field_if.read_data[8+4*l+:4] = bit_field_sub_if.read_data; 294 | bit_field_if.value[8+4*l+:4] = bit_field_sub_if.value; 295 | } 296 | inst u_bit_field: rggen::rggen_bit_field #( 297 | WIDTH: 4, 298 | INITIAL_VALUE: INITIAL_VALUE, 299 | SW_WRITE_CONTROL: true, 300 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_HIGH 301 | )( 302 | i_clk: i_clk, 303 | i_rst: i_rst, 304 | bit_field_if: bit_field_sub_if, 305 | i_sw_write_enable: register_if[0].value[0+:1], 306 | o_value: o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l] 307 | ); 308 | } 309 | } 310 | :g_bit_field_2 { 311 | for l in 0..2 :g { 312 | const INITIAL_VALUE: bit<4> = 4'h0; 313 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 314 | always_comb { 315 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 316 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 317 | bit_field_sub_if.mask = bit_field_if.mask[16+4*l+:4]; 318 | bit_field_sub_if.write_data = bit_field_if.write_data[16+4*l+:4]; 319 | bit_field_if.read_data[16+4*l+:4] = bit_field_sub_if.read_data; 320 | bit_field_if.value[16+4*l+:4] = bit_field_sub_if.value; 321 | } 322 | inst u_bit_field: rggen::rggen_bit_field #( 323 | WIDTH: 4, 324 | INITIAL_VALUE: INITIAL_VALUE, 325 | SW_WRITE_CONTROL: true, 326 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_LOW 327 | )( 328 | i_clk: i_clk, 329 | i_rst: i_rst, 330 | bit_field_if: bit_field_sub_if, 331 | i_sw_write_enable: register_if[6+7*i+6].value[0+1*l+:1], 332 | o_value: o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l] 333 | ); 334 | } 335 | } 336 | } 337 | } 338 | } 339 | :g_register_1 { 340 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 341 | inst u_register: rggen::rggen_default_register #( 342 | READABLE: true, 343 | WRITABLE: true, 344 | ADDRESS_WIDTH: 7, 345 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+7'h18, 346 | BUS_WIDTH: 32, 347 | DATA_WIDTH: 32, 348 | VALUE_WIDTH: 32, 349 | VALID_BITS: 32'h00000003 350 | )( 351 | i_clk: i_clk, 352 | i_rst: i_rst, 353 | register_if: register_if[6+7*i+6], 354 | bit_field_if: bit_field_if 355 | ); 356 | :g_bit_field_0 { 357 | for j in 0..2 :g { 358 | const INITIAL_VALUE: bit = 1'h0; 359 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 1); 360 | always_comb { 361 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 362 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 363 | bit_field_sub_if.mask = bit_field_if.mask[0+1*j+:1]; 364 | bit_field_sub_if.write_data = bit_field_if.write_data[0+1*j+:1]; 365 | bit_field_if.read_data[0+1*j+:1] = bit_field_sub_if.read_data; 366 | bit_field_if.value[0+1*j+:1] = bit_field_sub_if.value; 367 | } 368 | inst u_bit_field: rggen::rggen_bit_field #( 369 | WIDTH: 1, 370 | INITIAL_VALUE: INITIAL_VALUE, 371 | SW_WRITE_ONCE: false, 372 | TRIGGER: false 373 | )( 374 | i_clk: i_clk, 375 | i_rst: i_rst, 376 | bit_field_if: bit_field_sub_if, 377 | o_write_trigger: _, 378 | o_read_trigger: _, 379 | o_value: o_register_file_2_register_file_0_register_1_bit_field_0[i][j] 380 | ); 381 | } 382 | } 383 | } 384 | } 385 | } 386 | } 387 | } 388 | -------------------------------------------------------------------------------- /rtl/native/block_1.veryl: -------------------------------------------------------------------------------- 1 | #[fmt(skip)] 2 | pub module block_1 #( 3 | param ADDRESS_WIDTH: u32 = 7, 4 | param PRE_DECODE: bool = false, 5 | param BASE_ADDRESS: bit = '0, 6 | param ERROR_STATUS: bool = false, 7 | param DEFAULT_READ_DATA: bit<32> = '0, 8 | param INSERT_SLICER: bool = false, 9 | param STROBE_WIDTH: u32 = 4, 10 | param USE_READ_STROBE: bool = false 11 | )( 12 | i_clk: input clock, 13 | i_rst: input reset, 14 | csrbus_if: modport rggen::rggen_bus_if::slave, 15 | o_register_file_0_register_0_bit_field_0: output logic<8>, 16 | o_register_file_0_register_1_bit_field_0: output logic<8>, 17 | o_register_file_1_register_0_bit_field_0: output logic<2, 8>, 18 | o_register_file_1_register_1_bit_field_0: output logic<2, 8>, 19 | o_register_file_2_register_file_0_register_0_bit_field_0: output logic<2, 2, 3, 2, 4>, 20 | o_register_file_2_register_file_0_register_0_bit_field_1: output logic<2, 2, 3, 2, 4>, 21 | o_register_file_2_register_file_0_register_0_bit_field_2: output logic<2, 2, 3, 2, 4>, 22 | o_register_file_2_register_file_0_register_1_bit_field_0: output logic<2, 2> 23 | ){ 24 | import rggen::rggen_rtl_pkg::*; 25 | inst register_if: rggen::rggen_register_if[20]#(ADDRESS_WIDTH: 7, BUS_WIDTH: 32, VALUE_WIDTH: 32); 26 | inst u_adapter: rggen::rggen_native_adapter #( 27 | ADDRESS_WIDTH: ADDRESS_WIDTH, 28 | LOCAL_ADDRESS_WIDTH: 7, 29 | BUS_WIDTH: 32, 30 | STROBE_WIDTH: STROBE_WIDTH, 31 | REGISTERS: 20, 32 | PRE_DECODE: PRE_DECODE, 33 | BASE_ADDRESS: BASE_ADDRESS, 34 | BYTE_SIZE: 128, 35 | USE_READ_STROBE: USE_READ_STROBE, 36 | ERROR_STATUS: ERROR_STATUS, 37 | DEFAULT_READ_DATA: DEFAULT_READ_DATA, 38 | INSERT_SLICER: INSERT_SLICER 39 | )( 40 | i_clk: i_clk, 41 | i_rst: i_rst, 42 | csrbus_if: csrbus_if, 43 | register_if: register_if 44 | ); 45 | :g_register_file_0 { 46 | :g_register_0 { 47 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 48 | inst u_register: rggen::rggen_default_register #( 49 | READABLE: true, 50 | WRITABLE: true, 51 | ADDRESS_WIDTH: 7, 52 | OFFSET_ADDRESS: 7'h00, 53 | BUS_WIDTH: 32, 54 | DATA_WIDTH: 32, 55 | VALUE_WIDTH: 32, 56 | VALID_BITS: 32'h000000ff 57 | )( 58 | i_clk: i_clk, 59 | i_rst: i_rst, 60 | register_if: register_if[0], 61 | bit_field_if: bit_field_if 62 | ); 63 | :g_bit_field_0 { 64 | const INITIAL_VALUE: bit<8> = 8'h00; 65 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 66 | always_comb { 67 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 68 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 69 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 70 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 71 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 72 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 73 | } 74 | inst u_bit_field: rggen::rggen_bit_field #( 75 | WIDTH: 8, 76 | INITIAL_VALUE: INITIAL_VALUE, 77 | SW_WRITE_ONCE: false, 78 | TRIGGER: false 79 | )( 80 | i_clk: i_clk, 81 | i_rst: i_rst, 82 | bit_field_if: bit_field_sub_if, 83 | o_write_trigger: _, 84 | o_read_trigger: _, 85 | o_value: o_register_file_0_register_0_bit_field_0 86 | ); 87 | } 88 | } 89 | :g_register_1 { 90 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 91 | inst u_register: rggen::rggen_default_register #( 92 | READABLE: true, 93 | WRITABLE: true, 94 | ADDRESS_WIDTH: 7, 95 | OFFSET_ADDRESS: 7'h04, 96 | BUS_WIDTH: 32, 97 | DATA_WIDTH: 32, 98 | VALUE_WIDTH: 32, 99 | VALID_BITS: 32'h000000ff 100 | )( 101 | i_clk: i_clk, 102 | i_rst: i_rst, 103 | register_if: register_if[1], 104 | bit_field_if: bit_field_if 105 | ); 106 | :g_bit_field_0 { 107 | const INITIAL_VALUE: bit<8> = 8'h00; 108 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 109 | always_comb { 110 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 111 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 112 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 113 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 114 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 115 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 116 | } 117 | inst u_bit_field: rggen::rggen_bit_field #( 118 | WIDTH: 8, 119 | INITIAL_VALUE: INITIAL_VALUE, 120 | SW_WRITE_ONCE: false, 121 | TRIGGER: false 122 | )( 123 | i_clk: i_clk, 124 | i_rst: i_rst, 125 | bit_field_if: bit_field_sub_if, 126 | o_write_trigger: _, 127 | o_read_trigger: _, 128 | o_value: o_register_file_0_register_1_bit_field_0 129 | ); 130 | } 131 | } 132 | } 133 | :g_register_file_1 { 134 | :g_register_0 { 135 | for i in 0..2 :g { 136 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 137 | var indirect_match: logic<2>; 138 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 139 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 140 | inst u_register: rggen::rggen_indirect_register #( 141 | READABLE: true, 142 | WRITABLE: true, 143 | ADDRESS_WIDTH: 7, 144 | OFFSET_ADDRESS: 7'h10, 145 | BUS_WIDTH: 32, 146 | DATA_WIDTH: 32, 147 | VALUE_WIDTH: 32, 148 | VALID_BITS: 32'h000000ff, 149 | INDIRECT_MATCH_WIDTH: 2 150 | )( 151 | i_clk: i_clk, 152 | i_rst: i_rst, 153 | register_if: register_if[2+i], 154 | i_indirect_match: indirect_match, 155 | bit_field_if: bit_field_if 156 | ); 157 | :g_bit_field_0 { 158 | const INITIAL_VALUE: bit<8> = 8'h00; 159 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 160 | always_comb { 161 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 162 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 163 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 164 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 165 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 166 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 167 | } 168 | inst u_bit_field: rggen::rggen_bit_field #( 169 | WIDTH: 8, 170 | INITIAL_VALUE: INITIAL_VALUE, 171 | SW_WRITE_ONCE: false, 172 | TRIGGER: false 173 | )( 174 | i_clk: i_clk, 175 | i_rst: i_rst, 176 | bit_field_if: bit_field_sub_if, 177 | o_write_trigger: _, 178 | o_read_trigger: _, 179 | o_value: o_register_file_1_register_0_bit_field_0[i] 180 | ); 181 | } 182 | } 183 | } 184 | :g_register_1 { 185 | for i in 0..2 :g { 186 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 187 | var indirect_match: logic<2>; 188 | assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8); 189 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 190 | inst u_register: rggen::rggen_indirect_register #( 191 | READABLE: true, 192 | WRITABLE: true, 193 | ADDRESS_WIDTH: 7, 194 | OFFSET_ADDRESS: 7'h10, 195 | BUS_WIDTH: 32, 196 | DATA_WIDTH: 32, 197 | VALUE_WIDTH: 32, 198 | VALID_BITS: 32'h000000ff, 199 | INDIRECT_MATCH_WIDTH: 2 200 | )( 201 | i_clk: i_clk, 202 | i_rst: i_rst, 203 | register_if: register_if[4+i], 204 | i_indirect_match: indirect_match, 205 | bit_field_if: bit_field_if 206 | ); 207 | :g_bit_field_0 { 208 | const INITIAL_VALUE: bit<8> = 8'h00; 209 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8); 210 | always_comb { 211 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 212 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 213 | bit_field_sub_if.mask = bit_field_if.mask[0+:8]; 214 | bit_field_sub_if.write_data = bit_field_if.write_data[0+:8]; 215 | bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data; 216 | bit_field_if.value[0+:8] = bit_field_sub_if.value; 217 | } 218 | inst u_bit_field: rggen::rggen_bit_field #( 219 | WIDTH: 8, 220 | INITIAL_VALUE: INITIAL_VALUE, 221 | SW_WRITE_ONCE: false, 222 | TRIGGER: false 223 | )( 224 | i_clk: i_clk, 225 | i_rst: i_rst, 226 | bit_field_if: bit_field_sub_if, 227 | o_write_trigger: _, 228 | o_read_trigger: _, 229 | o_value: o_register_file_1_register_1_bit_field_0[i] 230 | ); 231 | } 232 | } 233 | } 234 | } 235 | :g_register_file_2 { 236 | for i in 0..2 :g { 237 | :g_register_file_0 { 238 | :g_register_0 { 239 | for j in 0..2 :g { 240 | for k in 0..3 :g { 241 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 242 | inst u_register: rggen::rggen_default_register #( 243 | READABLE: true, 244 | WRITABLE: true, 245 | ADDRESS_WIDTH: 7, 246 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+(4*(3*j+k) as 7), 247 | BUS_WIDTH: 32, 248 | DATA_WIDTH: 32, 249 | VALUE_WIDTH: 32, 250 | VALID_BITS: 32'h00ffffff 251 | )( 252 | i_clk: i_clk, 253 | i_rst: i_rst, 254 | register_if: register_if[6+7*i+3*j+k], 255 | bit_field_if: bit_field_if 256 | ); 257 | :g_bit_field_0 { 258 | for l in 0..2 :g { 259 | const INITIAL_VALUE: bit<4> = 4'h0; 260 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 261 | always_comb { 262 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 263 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 264 | bit_field_sub_if.mask = bit_field_if.mask[0+4*l+:4]; 265 | bit_field_sub_if.write_data = bit_field_if.write_data[0+4*l+:4]; 266 | bit_field_if.read_data[0+4*l+:4] = bit_field_sub_if.read_data; 267 | bit_field_if.value[0+4*l+:4] = bit_field_sub_if.value; 268 | } 269 | inst u_bit_field: rggen::rggen_bit_field #( 270 | WIDTH: 4, 271 | INITIAL_VALUE: INITIAL_VALUE, 272 | SW_WRITE_ONCE: false, 273 | TRIGGER: false 274 | )( 275 | i_clk: i_clk, 276 | i_rst: i_rst, 277 | bit_field_if: bit_field_sub_if, 278 | o_write_trigger: _, 279 | o_read_trigger: _, 280 | o_value: o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l] 281 | ); 282 | } 283 | } 284 | :g_bit_field_1 { 285 | for l in 0..2 :g { 286 | const INITIAL_VALUE: bit<4> = 4'h0; 287 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 288 | always_comb { 289 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 290 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 291 | bit_field_sub_if.mask = bit_field_if.mask[8+4*l+:4]; 292 | bit_field_sub_if.write_data = bit_field_if.write_data[8+4*l+:4]; 293 | bit_field_if.read_data[8+4*l+:4] = bit_field_sub_if.read_data; 294 | bit_field_if.value[8+4*l+:4] = bit_field_sub_if.value; 295 | } 296 | inst u_bit_field: rggen::rggen_bit_field #( 297 | WIDTH: 4, 298 | INITIAL_VALUE: INITIAL_VALUE, 299 | SW_WRITE_CONTROL: true, 300 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_HIGH 301 | )( 302 | i_clk: i_clk, 303 | i_rst: i_rst, 304 | bit_field_if: bit_field_sub_if, 305 | i_sw_write_enable: register_if[0].value[0+:1], 306 | o_value: o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l] 307 | ); 308 | } 309 | } 310 | :g_bit_field_2 { 311 | for l in 0..2 :g { 312 | const INITIAL_VALUE: bit<4> = 4'h0; 313 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4); 314 | always_comb { 315 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 316 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 317 | bit_field_sub_if.mask = bit_field_if.mask[16+4*l+:4]; 318 | bit_field_sub_if.write_data = bit_field_if.write_data[16+4*l+:4]; 319 | bit_field_if.read_data[16+4*l+:4] = bit_field_sub_if.read_data; 320 | bit_field_if.value[16+4*l+:4] = bit_field_sub_if.value; 321 | } 322 | inst u_bit_field: rggen::rggen_bit_field #( 323 | WIDTH: 4, 324 | INITIAL_VALUE: INITIAL_VALUE, 325 | SW_WRITE_CONTROL: true, 326 | SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_LOW 327 | )( 328 | i_clk: i_clk, 329 | i_rst: i_rst, 330 | bit_field_if: bit_field_sub_if, 331 | i_sw_write_enable: register_if[6+7*i+6].value[0+1*l+:1], 332 | o_value: o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l] 333 | ); 334 | } 335 | } 336 | } 337 | } 338 | } 339 | :g_register_1 { 340 | inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32); 341 | inst u_register: rggen::rggen_default_register #( 342 | READABLE: true, 343 | WRITABLE: true, 344 | ADDRESS_WIDTH: 7, 345 | OFFSET_ADDRESS: 7'h20+(32*i as 7)+7'h18, 346 | BUS_WIDTH: 32, 347 | DATA_WIDTH: 32, 348 | VALUE_WIDTH: 32, 349 | VALID_BITS: 32'h00000003 350 | )( 351 | i_clk: i_clk, 352 | i_rst: i_rst, 353 | register_if: register_if[6+7*i+6], 354 | bit_field_if: bit_field_if 355 | ); 356 | :g_bit_field_0 { 357 | for j in 0..2 :g { 358 | const INITIAL_VALUE: bit = 1'h0; 359 | inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 1); 360 | always_comb { 361 | bit_field_sub_if.read_valid = bit_field_if.read_valid; 362 | bit_field_sub_if.write_valid = bit_field_if.write_valid; 363 | bit_field_sub_if.mask = bit_field_if.mask[0+1*j+:1]; 364 | bit_field_sub_if.write_data = bit_field_if.write_data[0+1*j+:1]; 365 | bit_field_if.read_data[0+1*j+:1] = bit_field_sub_if.read_data; 366 | bit_field_if.value[0+1*j+:1] = bit_field_sub_if.value; 367 | } 368 | inst u_bit_field: rggen::rggen_bit_field #( 369 | WIDTH: 1, 370 | INITIAL_VALUE: INITIAL_VALUE, 371 | SW_WRITE_ONCE: false, 372 | TRIGGER: false 373 | )( 374 | i_clk: i_clk, 375 | i_rst: i_rst, 376 | bit_field_if: bit_field_sub_if, 377 | o_write_trigger: _, 378 | o_read_trigger: _, 379 | o_value: o_register_file_2_register_file_0_register_1_bit_field_0[i][j] 380 | ); 381 | } 382 | } 383 | } 384 | } 385 | } 386 | } 387 | } 388 | -------------------------------------------------------------------------------- /rtl/apb/block_1.sv: -------------------------------------------------------------------------------- 1 | `ifndef rggen_connect_bit_field_if 2 | `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ 3 | always_comb begin \ 4 | FIF.write_valid = RIF.write_valid; \ 5 | FIF.read_valid = RIF.read_valid; \ 6 | FIF.mask = RIF.mask[LSB+:WIDTH]; \ 7 | FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ 8 | RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ 9 | RIF.value[LSB+:WIDTH] = FIF.value; \ 10 | end 11 | `endif 12 | `ifndef rggen_tie_off_unused_signals 13 | `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ 14 | if (1) begin : __g_tie_off \ 15 | genvar __i; \ 16 | for (__i = 0;__i < WIDTH;++__i) begin : g \ 17 | if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ 18 | always_comb begin \ 19 | RIF.read_data[__i] = '0; \ 20 | RIF.value[__i] = '0; \ 21 | end \ 22 | end \ 23 | end \ 24 | end 25 | `endif 26 | module block_1 27 | import rggen_rtl_pkg::*; 28 | #( 29 | parameter int ADDRESS_WIDTH = 7, 30 | parameter bit PRE_DECODE = 0, 31 | parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, 32 | parameter bit ERROR_STATUS = 0, 33 | parameter bit [31:0] DEFAULT_READ_DATA = '0, 34 | parameter bit INSERT_SLICER = 0 35 | )( 36 | input logic i_clk, 37 | input logic i_rst_n, 38 | rggen_apb_if.slave apb_if, 39 | output logic [7:0] o_register_file_0_register_0_bit_field_0, 40 | output logic [7:0] o_register_file_0_register_1_bit_field_0, 41 | output logic [1:0][7:0] o_register_file_1_register_0_bit_field_0, 42 | output logic [1:0][7:0] o_register_file_1_register_1_bit_field_0, 43 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_0, 44 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_1, 45 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_2, 46 | output logic [1:0][1:0] o_register_file_2_register_file_0_register_1_bit_field_0 47 | ); 48 | rggen_register_if #(7, 32, 32) register_if[20](); 49 | rggen_apb_adapter #( 50 | .ADDRESS_WIDTH (ADDRESS_WIDTH), 51 | .LOCAL_ADDRESS_WIDTH (7), 52 | .BUS_WIDTH (32), 53 | .REGISTERS (20), 54 | .PRE_DECODE (PRE_DECODE), 55 | .BASE_ADDRESS (BASE_ADDRESS), 56 | .BYTE_SIZE (128), 57 | .ERROR_STATUS (ERROR_STATUS), 58 | .DEFAULT_READ_DATA (DEFAULT_READ_DATA), 59 | .INSERT_SLICER (INSERT_SLICER) 60 | ) u_adapter ( 61 | .i_clk (i_clk), 62 | .i_rst_n (i_rst_n), 63 | .apb_if (apb_if), 64 | .register_if (register_if) 65 | ); 66 | generate if (1) begin : g_register_file_0 67 | if (1) begin : g_register_0 68 | rggen_bit_field_if #(32) bit_field_if(); 69 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 70 | rggen_default_register #( 71 | .READABLE (1), 72 | .WRITABLE (1), 73 | .ADDRESS_WIDTH (7), 74 | .OFFSET_ADDRESS (7'h00), 75 | .BUS_WIDTH (32), 76 | .DATA_WIDTH (32), 77 | .VALUE_WIDTH (32) 78 | ) u_register ( 79 | .i_clk (i_clk), 80 | .i_rst_n (i_rst_n), 81 | .register_if (register_if[0]), 82 | .bit_field_if (bit_field_if) 83 | ); 84 | if (1) begin : g_bit_field_0 85 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 86 | rggen_bit_field_if #(8) bit_field_sub_if(); 87 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 88 | rggen_bit_field #( 89 | .WIDTH (8), 90 | .INITIAL_VALUE (INITIAL_VALUE), 91 | .SW_WRITE_ONCE (0), 92 | .TRIGGER (0) 93 | ) u_bit_field ( 94 | .i_clk (i_clk), 95 | .i_rst_n (i_rst_n), 96 | .bit_field_if (bit_field_sub_if), 97 | .o_write_trigger (), 98 | .o_read_trigger (), 99 | .i_sw_write_enable ('1), 100 | .i_hw_write_enable ('0), 101 | .i_hw_write_data ('0), 102 | .i_hw_set ('0), 103 | .i_hw_clear ('0), 104 | .i_value ('0), 105 | .i_mask ('1), 106 | .o_value (o_register_file_0_register_0_bit_field_0), 107 | .o_value_unmasked () 108 | ); 109 | end 110 | end 111 | if (1) begin : g_register_1 112 | rggen_bit_field_if #(32) bit_field_if(); 113 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 114 | rggen_default_register #( 115 | .READABLE (1), 116 | .WRITABLE (1), 117 | .ADDRESS_WIDTH (7), 118 | .OFFSET_ADDRESS (7'h04), 119 | .BUS_WIDTH (32), 120 | .DATA_WIDTH (32), 121 | .VALUE_WIDTH (32) 122 | ) u_register ( 123 | .i_clk (i_clk), 124 | .i_rst_n (i_rst_n), 125 | .register_if (register_if[1]), 126 | .bit_field_if (bit_field_if) 127 | ); 128 | if (1) begin : g_bit_field_0 129 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 130 | rggen_bit_field_if #(8) bit_field_sub_if(); 131 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 132 | rggen_bit_field #( 133 | .WIDTH (8), 134 | .INITIAL_VALUE (INITIAL_VALUE), 135 | .SW_WRITE_ONCE (0), 136 | .TRIGGER (0) 137 | ) u_bit_field ( 138 | .i_clk (i_clk), 139 | .i_rst_n (i_rst_n), 140 | .bit_field_if (bit_field_sub_if), 141 | .o_write_trigger (), 142 | .o_read_trigger (), 143 | .i_sw_write_enable ('1), 144 | .i_hw_write_enable ('0), 145 | .i_hw_write_data ('0), 146 | .i_hw_set ('0), 147 | .i_hw_clear ('0), 148 | .i_value ('0), 149 | .i_mask ('1), 150 | .o_value (o_register_file_0_register_1_bit_field_0), 151 | .o_value_unmasked () 152 | ); 153 | end 154 | end 155 | end endgenerate 156 | generate if (1) begin : g_register_file_1 157 | if (1) begin : g_register_0 158 | genvar i; 159 | for (i = 0;i < 2;++i) begin : g 160 | rggen_bit_field_if #(32) bit_field_if(); 161 | logic [1:0] indirect_match; 162 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 163 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 164 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 165 | rggen_indirect_register #( 166 | .READABLE (1), 167 | .WRITABLE (1), 168 | .ADDRESS_WIDTH (7), 169 | .OFFSET_ADDRESS (7'h10), 170 | .BUS_WIDTH (32), 171 | .DATA_WIDTH (32), 172 | .VALUE_WIDTH (32), 173 | .INDIRECT_MATCH_WIDTH (2) 174 | ) u_register ( 175 | .i_clk (i_clk), 176 | .i_rst_n (i_rst_n), 177 | .register_if (register_if[2+i]), 178 | .i_indirect_match (indirect_match), 179 | .bit_field_if (bit_field_if) 180 | ); 181 | if (1) begin : g_bit_field_0 182 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 183 | rggen_bit_field_if #(8) bit_field_sub_if(); 184 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 185 | rggen_bit_field #( 186 | .WIDTH (8), 187 | .INITIAL_VALUE (INITIAL_VALUE), 188 | .SW_WRITE_ONCE (0), 189 | .TRIGGER (0) 190 | ) u_bit_field ( 191 | .i_clk (i_clk), 192 | .i_rst_n (i_rst_n), 193 | .bit_field_if (bit_field_sub_if), 194 | .o_write_trigger (), 195 | .o_read_trigger (), 196 | .i_sw_write_enable ('1), 197 | .i_hw_write_enable ('0), 198 | .i_hw_write_data ('0), 199 | .i_hw_set ('0), 200 | .i_hw_clear ('0), 201 | .i_value ('0), 202 | .i_mask ('1), 203 | .o_value (o_register_file_1_register_0_bit_field_0[i]), 204 | .o_value_unmasked () 205 | ); 206 | end 207 | end 208 | end 209 | if (1) begin : g_register_1 210 | genvar i; 211 | for (i = 0;i < 2;++i) begin : g 212 | rggen_bit_field_if #(32) bit_field_if(); 213 | logic [1:0] indirect_match; 214 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 215 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 216 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 217 | rggen_indirect_register #( 218 | .READABLE (1), 219 | .WRITABLE (1), 220 | .ADDRESS_WIDTH (7), 221 | .OFFSET_ADDRESS (7'h10), 222 | .BUS_WIDTH (32), 223 | .DATA_WIDTH (32), 224 | .VALUE_WIDTH (32), 225 | .INDIRECT_MATCH_WIDTH (2) 226 | ) u_register ( 227 | .i_clk (i_clk), 228 | .i_rst_n (i_rst_n), 229 | .register_if (register_if[4+i]), 230 | .i_indirect_match (indirect_match), 231 | .bit_field_if (bit_field_if) 232 | ); 233 | if (1) begin : g_bit_field_0 234 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 235 | rggen_bit_field_if #(8) bit_field_sub_if(); 236 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 237 | rggen_bit_field #( 238 | .WIDTH (8), 239 | .INITIAL_VALUE (INITIAL_VALUE), 240 | .SW_WRITE_ONCE (0), 241 | .TRIGGER (0) 242 | ) u_bit_field ( 243 | .i_clk (i_clk), 244 | .i_rst_n (i_rst_n), 245 | .bit_field_if (bit_field_sub_if), 246 | .o_write_trigger (), 247 | .o_read_trigger (), 248 | .i_sw_write_enable ('1), 249 | .i_hw_write_enable ('0), 250 | .i_hw_write_data ('0), 251 | .i_hw_set ('0), 252 | .i_hw_clear ('0), 253 | .i_value ('0), 254 | .i_mask ('1), 255 | .o_value (o_register_file_1_register_1_bit_field_0[i]), 256 | .o_value_unmasked () 257 | ); 258 | end 259 | end 260 | end 261 | end endgenerate 262 | generate if (1) begin : g_register_file_2 263 | genvar i; 264 | for (i = 0;i < 2;++i) begin : g 265 | if (1) begin : g_register_file_0 266 | if (1) begin : g_register_0 267 | genvar j; 268 | genvar k; 269 | for (j = 0;j < 2;++j) begin : g 270 | for (k = 0;k < 3;++k) begin : g 271 | rggen_bit_field_if #(32) bit_field_if(); 272 | `rggen_tie_off_unused_signals(32, 32'h00ffffff, bit_field_if) 273 | rggen_default_register #( 274 | .READABLE (1), 275 | .WRITABLE (1), 276 | .ADDRESS_WIDTH (7), 277 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'(4*(3*j+k))), 278 | .BUS_WIDTH (32), 279 | .DATA_WIDTH (32), 280 | .VALUE_WIDTH (32) 281 | ) u_register ( 282 | .i_clk (i_clk), 283 | .i_rst_n (i_rst_n), 284 | .register_if (register_if[6+7*i+3*j+k]), 285 | .bit_field_if (bit_field_if) 286 | ); 287 | if (1) begin : g_bit_field_0 288 | genvar l; 289 | for (l = 0;l < 2;++l) begin : g 290 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 291 | rggen_bit_field_if #(4) bit_field_sub_if(); 292 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+4*l, 4) 293 | rggen_bit_field #( 294 | .WIDTH (4), 295 | .INITIAL_VALUE (INITIAL_VALUE), 296 | .SW_WRITE_ONCE (0), 297 | .TRIGGER (0) 298 | ) u_bit_field ( 299 | .i_clk (i_clk), 300 | .i_rst_n (i_rst_n), 301 | .bit_field_if (bit_field_sub_if), 302 | .o_write_trigger (), 303 | .o_read_trigger (), 304 | .i_sw_write_enable ('1), 305 | .i_hw_write_enable ('0), 306 | .i_hw_write_data ('0), 307 | .i_hw_set ('0), 308 | .i_hw_clear ('0), 309 | .i_value ('0), 310 | .i_mask ('1), 311 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l]), 312 | .o_value_unmasked () 313 | ); 314 | end 315 | end 316 | if (1) begin : g_bit_field_1 317 | genvar l; 318 | for (l = 0;l < 2;++l) begin : g 319 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 320 | rggen_bit_field_if #(4) bit_field_sub_if(); 321 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+4*l, 4) 322 | rggen_bit_field #( 323 | .WIDTH (4), 324 | .INITIAL_VALUE (INITIAL_VALUE), 325 | .SW_WRITE_CONTROL (1), 326 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) 327 | ) u_bit_field ( 328 | .i_clk (i_clk), 329 | .i_rst_n (i_rst_n), 330 | .bit_field_if (bit_field_sub_if), 331 | .o_write_trigger (), 332 | .o_read_trigger (), 333 | .i_sw_write_enable (register_if[0].value[0+:1]), 334 | .i_hw_write_enable ('0), 335 | .i_hw_write_data ('0), 336 | .i_hw_set ('0), 337 | .i_hw_clear ('0), 338 | .i_value ('0), 339 | .i_mask ('1), 340 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l]), 341 | .o_value_unmasked () 342 | ); 343 | end 344 | end 345 | if (1) begin : g_bit_field_2 346 | genvar l; 347 | for (l = 0;l < 2;++l) begin : g 348 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 349 | rggen_bit_field_if #(4) bit_field_sub_if(); 350 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16+4*l, 4) 351 | rggen_bit_field #( 352 | .WIDTH (4), 353 | .INITIAL_VALUE (INITIAL_VALUE), 354 | .SW_WRITE_CONTROL (1), 355 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) 356 | ) u_bit_field ( 357 | .i_clk (i_clk), 358 | .i_rst_n (i_rst_n), 359 | .bit_field_if (bit_field_sub_if), 360 | .o_write_trigger (), 361 | .o_read_trigger (), 362 | .i_sw_write_enable (register_if[6+7*i+6].value[0+1*l+:1]), 363 | .i_hw_write_enable ('0), 364 | .i_hw_write_data ('0), 365 | .i_hw_set ('0), 366 | .i_hw_clear ('0), 367 | .i_value ('0), 368 | .i_mask ('1), 369 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l]), 370 | .o_value_unmasked () 371 | ); 372 | end 373 | end 374 | end 375 | end 376 | end 377 | if (1) begin : g_register_1 378 | rggen_bit_field_if #(32) bit_field_if(); 379 | `rggen_tie_off_unused_signals(32, 32'h00000003, bit_field_if) 380 | rggen_default_register #( 381 | .READABLE (1), 382 | .WRITABLE (1), 383 | .ADDRESS_WIDTH (7), 384 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'h18), 385 | .BUS_WIDTH (32), 386 | .DATA_WIDTH (32), 387 | .VALUE_WIDTH (32) 388 | ) u_register ( 389 | .i_clk (i_clk), 390 | .i_rst_n (i_rst_n), 391 | .register_if (register_if[6+7*i+6]), 392 | .bit_field_if (bit_field_if) 393 | ); 394 | if (1) begin : g_bit_field_0 395 | genvar j; 396 | for (j = 0;j < 2;++j) begin : g 397 | localparam bit INITIAL_VALUE = 1'h0; 398 | rggen_bit_field_if #(1) bit_field_sub_if(); 399 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+1*j, 1) 400 | rggen_bit_field #( 401 | .WIDTH (1), 402 | .INITIAL_VALUE (INITIAL_VALUE), 403 | .SW_WRITE_ONCE (0), 404 | .TRIGGER (0) 405 | ) u_bit_field ( 406 | .i_clk (i_clk), 407 | .i_rst_n (i_rst_n), 408 | .bit_field_if (bit_field_sub_if), 409 | .o_write_trigger (), 410 | .o_read_trigger (), 411 | .i_sw_write_enable ('1), 412 | .i_hw_write_enable ('0), 413 | .i_hw_write_data ('0), 414 | .i_hw_set ('0), 415 | .i_hw_clear ('0), 416 | .i_value ('0), 417 | .i_mask ('1), 418 | .o_value (o_register_file_2_register_file_0_register_1_bit_field_0[i][j]), 419 | .o_value_unmasked () 420 | ); 421 | end 422 | end 423 | end 424 | end 425 | end 426 | end endgenerate 427 | endmodule 428 | -------------------------------------------------------------------------------- /rtl/avalon/block_1.sv: -------------------------------------------------------------------------------- 1 | `ifndef rggen_connect_bit_field_if 2 | `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ 3 | always_comb begin \ 4 | FIF.write_valid = RIF.write_valid; \ 5 | FIF.read_valid = RIF.read_valid; \ 6 | FIF.mask = RIF.mask[LSB+:WIDTH]; \ 7 | FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ 8 | RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ 9 | RIF.value[LSB+:WIDTH] = FIF.value; \ 10 | end 11 | `endif 12 | `ifndef rggen_tie_off_unused_signals 13 | `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ 14 | if (1) begin : __g_tie_off \ 15 | genvar __i; \ 16 | for (__i = 0;__i < WIDTH;++__i) begin : g \ 17 | if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ 18 | always_comb begin \ 19 | RIF.read_data[__i] = '0; \ 20 | RIF.value[__i] = '0; \ 21 | end \ 22 | end \ 23 | end \ 24 | end 25 | `endif 26 | module block_1 27 | import rggen_rtl_pkg::*; 28 | #( 29 | parameter int ADDRESS_WIDTH = 7, 30 | parameter bit PRE_DECODE = 0, 31 | parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, 32 | parameter bit ERROR_STATUS = 0, 33 | parameter bit [31:0] DEFAULT_READ_DATA = '0, 34 | parameter bit INSERT_SLICER = 0 35 | )( 36 | input logic i_clk, 37 | input logic i_rst_n, 38 | rggen_avalon_if.agent avalon_if, 39 | output logic [7:0] o_register_file_0_register_0_bit_field_0, 40 | output logic [7:0] o_register_file_0_register_1_bit_field_0, 41 | output logic [1:0][7:0] o_register_file_1_register_0_bit_field_0, 42 | output logic [1:0][7:0] o_register_file_1_register_1_bit_field_0, 43 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_0, 44 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_1, 45 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_2, 46 | output logic [1:0][1:0] o_register_file_2_register_file_0_register_1_bit_field_0 47 | ); 48 | rggen_register_if #(7, 32, 32) register_if[20](); 49 | rggen_avalon_adapter #( 50 | .ADDRESS_WIDTH (ADDRESS_WIDTH), 51 | .LOCAL_ADDRESS_WIDTH (7), 52 | .BUS_WIDTH (32), 53 | .REGISTERS (20), 54 | .PRE_DECODE (PRE_DECODE), 55 | .BASE_ADDRESS (BASE_ADDRESS), 56 | .BYTE_SIZE (128), 57 | .ERROR_STATUS (ERROR_STATUS), 58 | .DEFAULT_READ_DATA (DEFAULT_READ_DATA), 59 | .INSERT_SLICER (INSERT_SLICER) 60 | ) u_adapter ( 61 | .i_clk (i_clk), 62 | .i_rst_n (i_rst_n), 63 | .avalon_if (avalon_if), 64 | .register_if (register_if) 65 | ); 66 | generate if (1) begin : g_register_file_0 67 | if (1) begin : g_register_0 68 | rggen_bit_field_if #(32) bit_field_if(); 69 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 70 | rggen_default_register #( 71 | .READABLE (1), 72 | .WRITABLE (1), 73 | .ADDRESS_WIDTH (7), 74 | .OFFSET_ADDRESS (7'h00), 75 | .BUS_WIDTH (32), 76 | .DATA_WIDTH (32), 77 | .VALUE_WIDTH (32) 78 | ) u_register ( 79 | .i_clk (i_clk), 80 | .i_rst_n (i_rst_n), 81 | .register_if (register_if[0]), 82 | .bit_field_if (bit_field_if) 83 | ); 84 | if (1) begin : g_bit_field_0 85 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 86 | rggen_bit_field_if #(8) bit_field_sub_if(); 87 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 88 | rggen_bit_field #( 89 | .WIDTH (8), 90 | .INITIAL_VALUE (INITIAL_VALUE), 91 | .SW_WRITE_ONCE (0), 92 | .TRIGGER (0) 93 | ) u_bit_field ( 94 | .i_clk (i_clk), 95 | .i_rst_n (i_rst_n), 96 | .bit_field_if (bit_field_sub_if), 97 | .o_write_trigger (), 98 | .o_read_trigger (), 99 | .i_sw_write_enable ('1), 100 | .i_hw_write_enable ('0), 101 | .i_hw_write_data ('0), 102 | .i_hw_set ('0), 103 | .i_hw_clear ('0), 104 | .i_value ('0), 105 | .i_mask ('1), 106 | .o_value (o_register_file_0_register_0_bit_field_0), 107 | .o_value_unmasked () 108 | ); 109 | end 110 | end 111 | if (1) begin : g_register_1 112 | rggen_bit_field_if #(32) bit_field_if(); 113 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 114 | rggen_default_register #( 115 | .READABLE (1), 116 | .WRITABLE (1), 117 | .ADDRESS_WIDTH (7), 118 | .OFFSET_ADDRESS (7'h04), 119 | .BUS_WIDTH (32), 120 | .DATA_WIDTH (32), 121 | .VALUE_WIDTH (32) 122 | ) u_register ( 123 | .i_clk (i_clk), 124 | .i_rst_n (i_rst_n), 125 | .register_if (register_if[1]), 126 | .bit_field_if (bit_field_if) 127 | ); 128 | if (1) begin : g_bit_field_0 129 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 130 | rggen_bit_field_if #(8) bit_field_sub_if(); 131 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 132 | rggen_bit_field #( 133 | .WIDTH (8), 134 | .INITIAL_VALUE (INITIAL_VALUE), 135 | .SW_WRITE_ONCE (0), 136 | .TRIGGER (0) 137 | ) u_bit_field ( 138 | .i_clk (i_clk), 139 | .i_rst_n (i_rst_n), 140 | .bit_field_if (bit_field_sub_if), 141 | .o_write_trigger (), 142 | .o_read_trigger (), 143 | .i_sw_write_enable ('1), 144 | .i_hw_write_enable ('0), 145 | .i_hw_write_data ('0), 146 | .i_hw_set ('0), 147 | .i_hw_clear ('0), 148 | .i_value ('0), 149 | .i_mask ('1), 150 | .o_value (o_register_file_0_register_1_bit_field_0), 151 | .o_value_unmasked () 152 | ); 153 | end 154 | end 155 | end endgenerate 156 | generate if (1) begin : g_register_file_1 157 | if (1) begin : g_register_0 158 | genvar i; 159 | for (i = 0;i < 2;++i) begin : g 160 | rggen_bit_field_if #(32) bit_field_if(); 161 | logic [1:0] indirect_match; 162 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 163 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 164 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 165 | rggen_indirect_register #( 166 | .READABLE (1), 167 | .WRITABLE (1), 168 | .ADDRESS_WIDTH (7), 169 | .OFFSET_ADDRESS (7'h10), 170 | .BUS_WIDTH (32), 171 | .DATA_WIDTH (32), 172 | .VALUE_WIDTH (32), 173 | .INDIRECT_MATCH_WIDTH (2) 174 | ) u_register ( 175 | .i_clk (i_clk), 176 | .i_rst_n (i_rst_n), 177 | .register_if (register_if[2+i]), 178 | .i_indirect_match (indirect_match), 179 | .bit_field_if (bit_field_if) 180 | ); 181 | if (1) begin : g_bit_field_0 182 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 183 | rggen_bit_field_if #(8) bit_field_sub_if(); 184 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 185 | rggen_bit_field #( 186 | .WIDTH (8), 187 | .INITIAL_VALUE (INITIAL_VALUE), 188 | .SW_WRITE_ONCE (0), 189 | .TRIGGER (0) 190 | ) u_bit_field ( 191 | .i_clk (i_clk), 192 | .i_rst_n (i_rst_n), 193 | .bit_field_if (bit_field_sub_if), 194 | .o_write_trigger (), 195 | .o_read_trigger (), 196 | .i_sw_write_enable ('1), 197 | .i_hw_write_enable ('0), 198 | .i_hw_write_data ('0), 199 | .i_hw_set ('0), 200 | .i_hw_clear ('0), 201 | .i_value ('0), 202 | .i_mask ('1), 203 | .o_value (o_register_file_1_register_0_bit_field_0[i]), 204 | .o_value_unmasked () 205 | ); 206 | end 207 | end 208 | end 209 | if (1) begin : g_register_1 210 | genvar i; 211 | for (i = 0;i < 2;++i) begin : g 212 | rggen_bit_field_if #(32) bit_field_if(); 213 | logic [1:0] indirect_match; 214 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 215 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 216 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 217 | rggen_indirect_register #( 218 | .READABLE (1), 219 | .WRITABLE (1), 220 | .ADDRESS_WIDTH (7), 221 | .OFFSET_ADDRESS (7'h10), 222 | .BUS_WIDTH (32), 223 | .DATA_WIDTH (32), 224 | .VALUE_WIDTH (32), 225 | .INDIRECT_MATCH_WIDTH (2) 226 | ) u_register ( 227 | .i_clk (i_clk), 228 | .i_rst_n (i_rst_n), 229 | .register_if (register_if[4+i]), 230 | .i_indirect_match (indirect_match), 231 | .bit_field_if (bit_field_if) 232 | ); 233 | if (1) begin : g_bit_field_0 234 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 235 | rggen_bit_field_if #(8) bit_field_sub_if(); 236 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 237 | rggen_bit_field #( 238 | .WIDTH (8), 239 | .INITIAL_VALUE (INITIAL_VALUE), 240 | .SW_WRITE_ONCE (0), 241 | .TRIGGER (0) 242 | ) u_bit_field ( 243 | .i_clk (i_clk), 244 | .i_rst_n (i_rst_n), 245 | .bit_field_if (bit_field_sub_if), 246 | .o_write_trigger (), 247 | .o_read_trigger (), 248 | .i_sw_write_enable ('1), 249 | .i_hw_write_enable ('0), 250 | .i_hw_write_data ('0), 251 | .i_hw_set ('0), 252 | .i_hw_clear ('0), 253 | .i_value ('0), 254 | .i_mask ('1), 255 | .o_value (o_register_file_1_register_1_bit_field_0[i]), 256 | .o_value_unmasked () 257 | ); 258 | end 259 | end 260 | end 261 | end endgenerate 262 | generate if (1) begin : g_register_file_2 263 | genvar i; 264 | for (i = 0;i < 2;++i) begin : g 265 | if (1) begin : g_register_file_0 266 | if (1) begin : g_register_0 267 | genvar j; 268 | genvar k; 269 | for (j = 0;j < 2;++j) begin : g 270 | for (k = 0;k < 3;++k) begin : g 271 | rggen_bit_field_if #(32) bit_field_if(); 272 | `rggen_tie_off_unused_signals(32, 32'h00ffffff, bit_field_if) 273 | rggen_default_register #( 274 | .READABLE (1), 275 | .WRITABLE (1), 276 | .ADDRESS_WIDTH (7), 277 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'(4*(3*j+k))), 278 | .BUS_WIDTH (32), 279 | .DATA_WIDTH (32), 280 | .VALUE_WIDTH (32) 281 | ) u_register ( 282 | .i_clk (i_clk), 283 | .i_rst_n (i_rst_n), 284 | .register_if (register_if[6+7*i+3*j+k]), 285 | .bit_field_if (bit_field_if) 286 | ); 287 | if (1) begin : g_bit_field_0 288 | genvar l; 289 | for (l = 0;l < 2;++l) begin : g 290 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 291 | rggen_bit_field_if #(4) bit_field_sub_if(); 292 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+4*l, 4) 293 | rggen_bit_field #( 294 | .WIDTH (4), 295 | .INITIAL_VALUE (INITIAL_VALUE), 296 | .SW_WRITE_ONCE (0), 297 | .TRIGGER (0) 298 | ) u_bit_field ( 299 | .i_clk (i_clk), 300 | .i_rst_n (i_rst_n), 301 | .bit_field_if (bit_field_sub_if), 302 | .o_write_trigger (), 303 | .o_read_trigger (), 304 | .i_sw_write_enable ('1), 305 | .i_hw_write_enable ('0), 306 | .i_hw_write_data ('0), 307 | .i_hw_set ('0), 308 | .i_hw_clear ('0), 309 | .i_value ('0), 310 | .i_mask ('1), 311 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l]), 312 | .o_value_unmasked () 313 | ); 314 | end 315 | end 316 | if (1) begin : g_bit_field_1 317 | genvar l; 318 | for (l = 0;l < 2;++l) begin : g 319 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 320 | rggen_bit_field_if #(4) bit_field_sub_if(); 321 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+4*l, 4) 322 | rggen_bit_field #( 323 | .WIDTH (4), 324 | .INITIAL_VALUE (INITIAL_VALUE), 325 | .SW_WRITE_CONTROL (1), 326 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) 327 | ) u_bit_field ( 328 | .i_clk (i_clk), 329 | .i_rst_n (i_rst_n), 330 | .bit_field_if (bit_field_sub_if), 331 | .o_write_trigger (), 332 | .o_read_trigger (), 333 | .i_sw_write_enable (register_if[0].value[0+:1]), 334 | .i_hw_write_enable ('0), 335 | .i_hw_write_data ('0), 336 | .i_hw_set ('0), 337 | .i_hw_clear ('0), 338 | .i_value ('0), 339 | .i_mask ('1), 340 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l]), 341 | .o_value_unmasked () 342 | ); 343 | end 344 | end 345 | if (1) begin : g_bit_field_2 346 | genvar l; 347 | for (l = 0;l < 2;++l) begin : g 348 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 349 | rggen_bit_field_if #(4) bit_field_sub_if(); 350 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16+4*l, 4) 351 | rggen_bit_field #( 352 | .WIDTH (4), 353 | .INITIAL_VALUE (INITIAL_VALUE), 354 | .SW_WRITE_CONTROL (1), 355 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) 356 | ) u_bit_field ( 357 | .i_clk (i_clk), 358 | .i_rst_n (i_rst_n), 359 | .bit_field_if (bit_field_sub_if), 360 | .o_write_trigger (), 361 | .o_read_trigger (), 362 | .i_sw_write_enable (register_if[6+7*i+6].value[0+1*l+:1]), 363 | .i_hw_write_enable ('0), 364 | .i_hw_write_data ('0), 365 | .i_hw_set ('0), 366 | .i_hw_clear ('0), 367 | .i_value ('0), 368 | .i_mask ('1), 369 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l]), 370 | .o_value_unmasked () 371 | ); 372 | end 373 | end 374 | end 375 | end 376 | end 377 | if (1) begin : g_register_1 378 | rggen_bit_field_if #(32) bit_field_if(); 379 | `rggen_tie_off_unused_signals(32, 32'h00000003, bit_field_if) 380 | rggen_default_register #( 381 | .READABLE (1), 382 | .WRITABLE (1), 383 | .ADDRESS_WIDTH (7), 384 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'h18), 385 | .BUS_WIDTH (32), 386 | .DATA_WIDTH (32), 387 | .VALUE_WIDTH (32) 388 | ) u_register ( 389 | .i_clk (i_clk), 390 | .i_rst_n (i_rst_n), 391 | .register_if (register_if[6+7*i+6]), 392 | .bit_field_if (bit_field_if) 393 | ); 394 | if (1) begin : g_bit_field_0 395 | genvar j; 396 | for (j = 0;j < 2;++j) begin : g 397 | localparam bit INITIAL_VALUE = 1'h0; 398 | rggen_bit_field_if #(1) bit_field_sub_if(); 399 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+1*j, 1) 400 | rggen_bit_field #( 401 | .WIDTH (1), 402 | .INITIAL_VALUE (INITIAL_VALUE), 403 | .SW_WRITE_ONCE (0), 404 | .TRIGGER (0) 405 | ) u_bit_field ( 406 | .i_clk (i_clk), 407 | .i_rst_n (i_rst_n), 408 | .bit_field_if (bit_field_sub_if), 409 | .o_write_trigger (), 410 | .o_read_trigger (), 411 | .i_sw_write_enable ('1), 412 | .i_hw_write_enable ('0), 413 | .i_hw_write_data ('0), 414 | .i_hw_set ('0), 415 | .i_hw_clear ('0), 416 | .i_value ('0), 417 | .i_mask ('1), 418 | .o_value (o_register_file_2_register_file_0_register_1_bit_field_0[i][j]), 419 | .o_value_unmasked () 420 | ); 421 | end 422 | end 423 | end 424 | end 425 | end 426 | end endgenerate 427 | endmodule 428 | -------------------------------------------------------------------------------- /rtl/wishbone/block_1.sv: -------------------------------------------------------------------------------- 1 | `ifndef rggen_connect_bit_field_if 2 | `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ 3 | always_comb begin \ 4 | FIF.write_valid = RIF.write_valid; \ 5 | FIF.read_valid = RIF.read_valid; \ 6 | FIF.mask = RIF.mask[LSB+:WIDTH]; \ 7 | FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ 8 | RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ 9 | RIF.value[LSB+:WIDTH] = FIF.value; \ 10 | end 11 | `endif 12 | `ifndef rggen_tie_off_unused_signals 13 | `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ 14 | if (1) begin : __g_tie_off \ 15 | genvar __i; \ 16 | for (__i = 0;__i < WIDTH;++__i) begin : g \ 17 | if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ 18 | always_comb begin \ 19 | RIF.read_data[__i] = '0; \ 20 | RIF.value[__i] = '0; \ 21 | end \ 22 | end \ 23 | end \ 24 | end 25 | `endif 26 | module block_1 27 | import rggen_rtl_pkg::*; 28 | #( 29 | parameter int ADDRESS_WIDTH = 7, 30 | parameter bit PRE_DECODE = 0, 31 | parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, 32 | parameter bit ERROR_STATUS = 0, 33 | parameter bit [31:0] DEFAULT_READ_DATA = '0, 34 | parameter bit INSERT_SLICER = 0, 35 | parameter bit USE_STALL = 1 36 | )( 37 | input logic i_clk, 38 | input logic i_rst_n, 39 | rggen_wishbone_if.slave wishbone_if, 40 | output logic [7:0] o_register_file_0_register_0_bit_field_0, 41 | output logic [7:0] o_register_file_0_register_1_bit_field_0, 42 | output logic [1:0][7:0] o_register_file_1_register_0_bit_field_0, 43 | output logic [1:0][7:0] o_register_file_1_register_1_bit_field_0, 44 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_0, 45 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_1, 46 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_2, 47 | output logic [1:0][1:0] o_register_file_2_register_file_0_register_1_bit_field_0 48 | ); 49 | rggen_register_if #(7, 32, 32) register_if[20](); 50 | rggen_wishbone_adapter #( 51 | .ADDRESS_WIDTH (ADDRESS_WIDTH), 52 | .LOCAL_ADDRESS_WIDTH (7), 53 | .BUS_WIDTH (32), 54 | .REGISTERS (20), 55 | .PRE_DECODE (PRE_DECODE), 56 | .BASE_ADDRESS (BASE_ADDRESS), 57 | .BYTE_SIZE (128), 58 | .ERROR_STATUS (ERROR_STATUS), 59 | .DEFAULT_READ_DATA (DEFAULT_READ_DATA), 60 | .INSERT_SLICER (INSERT_SLICER), 61 | .USE_STALL (USE_STALL) 62 | ) u_adapter ( 63 | .i_clk (i_clk), 64 | .i_rst_n (i_rst_n), 65 | .wishbone_if (wishbone_if), 66 | .register_if (register_if) 67 | ); 68 | generate if (1) begin : g_register_file_0 69 | if (1) begin : g_register_0 70 | rggen_bit_field_if #(32) bit_field_if(); 71 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 72 | rggen_default_register #( 73 | .READABLE (1), 74 | .WRITABLE (1), 75 | .ADDRESS_WIDTH (7), 76 | .OFFSET_ADDRESS (7'h00), 77 | .BUS_WIDTH (32), 78 | .DATA_WIDTH (32), 79 | .VALUE_WIDTH (32) 80 | ) u_register ( 81 | .i_clk (i_clk), 82 | .i_rst_n (i_rst_n), 83 | .register_if (register_if[0]), 84 | .bit_field_if (bit_field_if) 85 | ); 86 | if (1) begin : g_bit_field_0 87 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 88 | rggen_bit_field_if #(8) bit_field_sub_if(); 89 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 90 | rggen_bit_field #( 91 | .WIDTH (8), 92 | .INITIAL_VALUE (INITIAL_VALUE), 93 | .SW_WRITE_ONCE (0), 94 | .TRIGGER (0) 95 | ) u_bit_field ( 96 | .i_clk (i_clk), 97 | .i_rst_n (i_rst_n), 98 | .bit_field_if (bit_field_sub_if), 99 | .o_write_trigger (), 100 | .o_read_trigger (), 101 | .i_sw_write_enable ('1), 102 | .i_hw_write_enable ('0), 103 | .i_hw_write_data ('0), 104 | .i_hw_set ('0), 105 | .i_hw_clear ('0), 106 | .i_value ('0), 107 | .i_mask ('1), 108 | .o_value (o_register_file_0_register_0_bit_field_0), 109 | .o_value_unmasked () 110 | ); 111 | end 112 | end 113 | if (1) begin : g_register_1 114 | rggen_bit_field_if #(32) bit_field_if(); 115 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 116 | rggen_default_register #( 117 | .READABLE (1), 118 | .WRITABLE (1), 119 | .ADDRESS_WIDTH (7), 120 | .OFFSET_ADDRESS (7'h04), 121 | .BUS_WIDTH (32), 122 | .DATA_WIDTH (32), 123 | .VALUE_WIDTH (32) 124 | ) u_register ( 125 | .i_clk (i_clk), 126 | .i_rst_n (i_rst_n), 127 | .register_if (register_if[1]), 128 | .bit_field_if (bit_field_if) 129 | ); 130 | if (1) begin : g_bit_field_0 131 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 132 | rggen_bit_field_if #(8) bit_field_sub_if(); 133 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 134 | rggen_bit_field #( 135 | .WIDTH (8), 136 | .INITIAL_VALUE (INITIAL_VALUE), 137 | .SW_WRITE_ONCE (0), 138 | .TRIGGER (0) 139 | ) u_bit_field ( 140 | .i_clk (i_clk), 141 | .i_rst_n (i_rst_n), 142 | .bit_field_if (bit_field_sub_if), 143 | .o_write_trigger (), 144 | .o_read_trigger (), 145 | .i_sw_write_enable ('1), 146 | .i_hw_write_enable ('0), 147 | .i_hw_write_data ('0), 148 | .i_hw_set ('0), 149 | .i_hw_clear ('0), 150 | .i_value ('0), 151 | .i_mask ('1), 152 | .o_value (o_register_file_0_register_1_bit_field_0), 153 | .o_value_unmasked () 154 | ); 155 | end 156 | end 157 | end endgenerate 158 | generate if (1) begin : g_register_file_1 159 | if (1) begin : g_register_0 160 | genvar i; 161 | for (i = 0;i < 2;++i) begin : g 162 | rggen_bit_field_if #(32) bit_field_if(); 163 | logic [1:0] indirect_match; 164 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 165 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 166 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 167 | rggen_indirect_register #( 168 | .READABLE (1), 169 | .WRITABLE (1), 170 | .ADDRESS_WIDTH (7), 171 | .OFFSET_ADDRESS (7'h10), 172 | .BUS_WIDTH (32), 173 | .DATA_WIDTH (32), 174 | .VALUE_WIDTH (32), 175 | .INDIRECT_MATCH_WIDTH (2) 176 | ) u_register ( 177 | .i_clk (i_clk), 178 | .i_rst_n (i_rst_n), 179 | .register_if (register_if[2+i]), 180 | .i_indirect_match (indirect_match), 181 | .bit_field_if (bit_field_if) 182 | ); 183 | if (1) begin : g_bit_field_0 184 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 185 | rggen_bit_field_if #(8) bit_field_sub_if(); 186 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 187 | rggen_bit_field #( 188 | .WIDTH (8), 189 | .INITIAL_VALUE (INITIAL_VALUE), 190 | .SW_WRITE_ONCE (0), 191 | .TRIGGER (0) 192 | ) u_bit_field ( 193 | .i_clk (i_clk), 194 | .i_rst_n (i_rst_n), 195 | .bit_field_if (bit_field_sub_if), 196 | .o_write_trigger (), 197 | .o_read_trigger (), 198 | .i_sw_write_enable ('1), 199 | .i_hw_write_enable ('0), 200 | .i_hw_write_data ('0), 201 | .i_hw_set ('0), 202 | .i_hw_clear ('0), 203 | .i_value ('0), 204 | .i_mask ('1), 205 | .o_value (o_register_file_1_register_0_bit_field_0[i]), 206 | .o_value_unmasked () 207 | ); 208 | end 209 | end 210 | end 211 | if (1) begin : g_register_1 212 | genvar i; 213 | for (i = 0;i < 2;++i) begin : g 214 | rggen_bit_field_if #(32) bit_field_if(); 215 | logic [1:0] indirect_match; 216 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 217 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 218 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 219 | rggen_indirect_register #( 220 | .READABLE (1), 221 | .WRITABLE (1), 222 | .ADDRESS_WIDTH (7), 223 | .OFFSET_ADDRESS (7'h10), 224 | .BUS_WIDTH (32), 225 | .DATA_WIDTH (32), 226 | .VALUE_WIDTH (32), 227 | .INDIRECT_MATCH_WIDTH (2) 228 | ) u_register ( 229 | .i_clk (i_clk), 230 | .i_rst_n (i_rst_n), 231 | .register_if (register_if[4+i]), 232 | .i_indirect_match (indirect_match), 233 | .bit_field_if (bit_field_if) 234 | ); 235 | if (1) begin : g_bit_field_0 236 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 237 | rggen_bit_field_if #(8) bit_field_sub_if(); 238 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 239 | rggen_bit_field #( 240 | .WIDTH (8), 241 | .INITIAL_VALUE (INITIAL_VALUE), 242 | .SW_WRITE_ONCE (0), 243 | .TRIGGER (0) 244 | ) u_bit_field ( 245 | .i_clk (i_clk), 246 | .i_rst_n (i_rst_n), 247 | .bit_field_if (bit_field_sub_if), 248 | .o_write_trigger (), 249 | .o_read_trigger (), 250 | .i_sw_write_enable ('1), 251 | .i_hw_write_enable ('0), 252 | .i_hw_write_data ('0), 253 | .i_hw_set ('0), 254 | .i_hw_clear ('0), 255 | .i_value ('0), 256 | .i_mask ('1), 257 | .o_value (o_register_file_1_register_1_bit_field_0[i]), 258 | .o_value_unmasked () 259 | ); 260 | end 261 | end 262 | end 263 | end endgenerate 264 | generate if (1) begin : g_register_file_2 265 | genvar i; 266 | for (i = 0;i < 2;++i) begin : g 267 | if (1) begin : g_register_file_0 268 | if (1) begin : g_register_0 269 | genvar j; 270 | genvar k; 271 | for (j = 0;j < 2;++j) begin : g 272 | for (k = 0;k < 3;++k) begin : g 273 | rggen_bit_field_if #(32) bit_field_if(); 274 | `rggen_tie_off_unused_signals(32, 32'h00ffffff, bit_field_if) 275 | rggen_default_register #( 276 | .READABLE (1), 277 | .WRITABLE (1), 278 | .ADDRESS_WIDTH (7), 279 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'(4*(3*j+k))), 280 | .BUS_WIDTH (32), 281 | .DATA_WIDTH (32), 282 | .VALUE_WIDTH (32) 283 | ) u_register ( 284 | .i_clk (i_clk), 285 | .i_rst_n (i_rst_n), 286 | .register_if (register_if[6+7*i+3*j+k]), 287 | .bit_field_if (bit_field_if) 288 | ); 289 | if (1) begin : g_bit_field_0 290 | genvar l; 291 | for (l = 0;l < 2;++l) begin : g 292 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 293 | rggen_bit_field_if #(4) bit_field_sub_if(); 294 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+4*l, 4) 295 | rggen_bit_field #( 296 | .WIDTH (4), 297 | .INITIAL_VALUE (INITIAL_VALUE), 298 | .SW_WRITE_ONCE (0), 299 | .TRIGGER (0) 300 | ) u_bit_field ( 301 | .i_clk (i_clk), 302 | .i_rst_n (i_rst_n), 303 | .bit_field_if (bit_field_sub_if), 304 | .o_write_trigger (), 305 | .o_read_trigger (), 306 | .i_sw_write_enable ('1), 307 | .i_hw_write_enable ('0), 308 | .i_hw_write_data ('0), 309 | .i_hw_set ('0), 310 | .i_hw_clear ('0), 311 | .i_value ('0), 312 | .i_mask ('1), 313 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l]), 314 | .o_value_unmasked () 315 | ); 316 | end 317 | end 318 | if (1) begin : g_bit_field_1 319 | genvar l; 320 | for (l = 0;l < 2;++l) begin : g 321 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 322 | rggen_bit_field_if #(4) bit_field_sub_if(); 323 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+4*l, 4) 324 | rggen_bit_field #( 325 | .WIDTH (4), 326 | .INITIAL_VALUE (INITIAL_VALUE), 327 | .SW_WRITE_CONTROL (1), 328 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) 329 | ) u_bit_field ( 330 | .i_clk (i_clk), 331 | .i_rst_n (i_rst_n), 332 | .bit_field_if (bit_field_sub_if), 333 | .o_write_trigger (), 334 | .o_read_trigger (), 335 | .i_sw_write_enable (register_if[0].value[0+:1]), 336 | .i_hw_write_enable ('0), 337 | .i_hw_write_data ('0), 338 | .i_hw_set ('0), 339 | .i_hw_clear ('0), 340 | .i_value ('0), 341 | .i_mask ('1), 342 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l]), 343 | .o_value_unmasked () 344 | ); 345 | end 346 | end 347 | if (1) begin : g_bit_field_2 348 | genvar l; 349 | for (l = 0;l < 2;++l) begin : g 350 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 351 | rggen_bit_field_if #(4) bit_field_sub_if(); 352 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16+4*l, 4) 353 | rggen_bit_field #( 354 | .WIDTH (4), 355 | .INITIAL_VALUE (INITIAL_VALUE), 356 | .SW_WRITE_CONTROL (1), 357 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) 358 | ) u_bit_field ( 359 | .i_clk (i_clk), 360 | .i_rst_n (i_rst_n), 361 | .bit_field_if (bit_field_sub_if), 362 | .o_write_trigger (), 363 | .o_read_trigger (), 364 | .i_sw_write_enable (register_if[6+7*i+6].value[0+1*l+:1]), 365 | .i_hw_write_enable ('0), 366 | .i_hw_write_data ('0), 367 | .i_hw_set ('0), 368 | .i_hw_clear ('0), 369 | .i_value ('0), 370 | .i_mask ('1), 371 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l]), 372 | .o_value_unmasked () 373 | ); 374 | end 375 | end 376 | end 377 | end 378 | end 379 | if (1) begin : g_register_1 380 | rggen_bit_field_if #(32) bit_field_if(); 381 | `rggen_tie_off_unused_signals(32, 32'h00000003, bit_field_if) 382 | rggen_default_register #( 383 | .READABLE (1), 384 | .WRITABLE (1), 385 | .ADDRESS_WIDTH (7), 386 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'h18), 387 | .BUS_WIDTH (32), 388 | .DATA_WIDTH (32), 389 | .VALUE_WIDTH (32) 390 | ) u_register ( 391 | .i_clk (i_clk), 392 | .i_rst_n (i_rst_n), 393 | .register_if (register_if[6+7*i+6]), 394 | .bit_field_if (bit_field_if) 395 | ); 396 | if (1) begin : g_bit_field_0 397 | genvar j; 398 | for (j = 0;j < 2;++j) begin : g 399 | localparam bit INITIAL_VALUE = 1'h0; 400 | rggen_bit_field_if #(1) bit_field_sub_if(); 401 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+1*j, 1) 402 | rggen_bit_field #( 403 | .WIDTH (1), 404 | .INITIAL_VALUE (INITIAL_VALUE), 405 | .SW_WRITE_ONCE (0), 406 | .TRIGGER (0) 407 | ) u_bit_field ( 408 | .i_clk (i_clk), 409 | .i_rst_n (i_rst_n), 410 | .bit_field_if (bit_field_sub_if), 411 | .o_write_trigger (), 412 | .o_read_trigger (), 413 | .i_sw_write_enable ('1), 414 | .i_hw_write_enable ('0), 415 | .i_hw_write_data ('0), 416 | .i_hw_set ('0), 417 | .i_hw_clear ('0), 418 | .i_value ('0), 419 | .i_mask ('1), 420 | .o_value (o_register_file_2_register_file_0_register_1_bit_field_0[i][j]), 421 | .o_value_unmasked () 422 | ); 423 | end 424 | end 425 | end 426 | end 427 | end 428 | end endgenerate 429 | endmodule 430 | -------------------------------------------------------------------------------- /rtl/axi4lite/block_1.sv: -------------------------------------------------------------------------------- 1 | `ifndef rggen_connect_bit_field_if 2 | `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \ 3 | always_comb begin \ 4 | FIF.write_valid = RIF.write_valid; \ 5 | FIF.read_valid = RIF.read_valid; \ 6 | FIF.mask = RIF.mask[LSB+:WIDTH]; \ 7 | FIF.write_data = RIF.write_data[LSB+:WIDTH]; \ 8 | RIF.read_data[LSB+:WIDTH] = FIF.read_data; \ 9 | RIF.value[LSB+:WIDTH] = FIF.value; \ 10 | end 11 | `endif 12 | `ifndef rggen_tie_off_unused_signals 13 | `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \ 14 | if (1) begin : __g_tie_off \ 15 | genvar __i; \ 16 | for (__i = 0;__i < WIDTH;++__i) begin : g \ 17 | if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \ 18 | always_comb begin \ 19 | RIF.read_data[__i] = '0; \ 20 | RIF.value[__i] = '0; \ 21 | end \ 22 | end \ 23 | end \ 24 | end 25 | `endif 26 | module block_1 27 | import rggen_rtl_pkg::*; 28 | #( 29 | parameter int ADDRESS_WIDTH = 7, 30 | parameter bit PRE_DECODE = 0, 31 | parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0, 32 | parameter bit ERROR_STATUS = 0, 33 | parameter bit [31:0] DEFAULT_READ_DATA = '0, 34 | parameter bit INSERT_SLICER = 0, 35 | parameter int ID_WIDTH = 0, 36 | parameter bit WRITE_FIRST = 1 37 | )( 38 | input logic i_clk, 39 | input logic i_rst_n, 40 | rggen_axi4lite_if.slave axi4lite_if, 41 | output logic [7:0] o_register_file_0_register_0_bit_field_0, 42 | output logic [7:0] o_register_file_0_register_1_bit_field_0, 43 | output logic [1:0][7:0] o_register_file_1_register_0_bit_field_0, 44 | output logic [1:0][7:0] o_register_file_1_register_1_bit_field_0, 45 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_0, 46 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_1, 47 | output logic [1:0][1:0][2:0][1:0][3:0] o_register_file_2_register_file_0_register_0_bit_field_2, 48 | output logic [1:0][1:0] o_register_file_2_register_file_0_register_1_bit_field_0 49 | ); 50 | rggen_register_if #(7, 32, 32) register_if[20](); 51 | rggen_axi4lite_adapter #( 52 | .ID_WIDTH (ID_WIDTH), 53 | .ADDRESS_WIDTH (ADDRESS_WIDTH), 54 | .LOCAL_ADDRESS_WIDTH (7), 55 | .BUS_WIDTH (32), 56 | .REGISTERS (20), 57 | .PRE_DECODE (PRE_DECODE), 58 | .BASE_ADDRESS (BASE_ADDRESS), 59 | .BYTE_SIZE (128), 60 | .ERROR_STATUS (ERROR_STATUS), 61 | .DEFAULT_READ_DATA (DEFAULT_READ_DATA), 62 | .INSERT_SLICER (INSERT_SLICER), 63 | .WRITE_FIRST (WRITE_FIRST) 64 | ) u_adapter ( 65 | .i_clk (i_clk), 66 | .i_rst_n (i_rst_n), 67 | .axi4lite_if (axi4lite_if), 68 | .register_if (register_if) 69 | ); 70 | generate if (1) begin : g_register_file_0 71 | if (1) begin : g_register_0 72 | rggen_bit_field_if #(32) bit_field_if(); 73 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 74 | rggen_default_register #( 75 | .READABLE (1), 76 | .WRITABLE (1), 77 | .ADDRESS_WIDTH (7), 78 | .OFFSET_ADDRESS (7'h00), 79 | .BUS_WIDTH (32), 80 | .DATA_WIDTH (32), 81 | .VALUE_WIDTH (32) 82 | ) u_register ( 83 | .i_clk (i_clk), 84 | .i_rst_n (i_rst_n), 85 | .register_if (register_if[0]), 86 | .bit_field_if (bit_field_if) 87 | ); 88 | if (1) begin : g_bit_field_0 89 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 90 | rggen_bit_field_if #(8) bit_field_sub_if(); 91 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 92 | rggen_bit_field #( 93 | .WIDTH (8), 94 | .INITIAL_VALUE (INITIAL_VALUE), 95 | .SW_WRITE_ONCE (0), 96 | .TRIGGER (0) 97 | ) u_bit_field ( 98 | .i_clk (i_clk), 99 | .i_rst_n (i_rst_n), 100 | .bit_field_if (bit_field_sub_if), 101 | .o_write_trigger (), 102 | .o_read_trigger (), 103 | .i_sw_write_enable ('1), 104 | .i_hw_write_enable ('0), 105 | .i_hw_write_data ('0), 106 | .i_hw_set ('0), 107 | .i_hw_clear ('0), 108 | .i_value ('0), 109 | .i_mask ('1), 110 | .o_value (o_register_file_0_register_0_bit_field_0), 111 | .o_value_unmasked () 112 | ); 113 | end 114 | end 115 | if (1) begin : g_register_1 116 | rggen_bit_field_if #(32) bit_field_if(); 117 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 118 | rggen_default_register #( 119 | .READABLE (1), 120 | .WRITABLE (1), 121 | .ADDRESS_WIDTH (7), 122 | .OFFSET_ADDRESS (7'h04), 123 | .BUS_WIDTH (32), 124 | .DATA_WIDTH (32), 125 | .VALUE_WIDTH (32) 126 | ) u_register ( 127 | .i_clk (i_clk), 128 | .i_rst_n (i_rst_n), 129 | .register_if (register_if[1]), 130 | .bit_field_if (bit_field_if) 131 | ); 132 | if (1) begin : g_bit_field_0 133 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 134 | rggen_bit_field_if #(8) bit_field_sub_if(); 135 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 136 | rggen_bit_field #( 137 | .WIDTH (8), 138 | .INITIAL_VALUE (INITIAL_VALUE), 139 | .SW_WRITE_ONCE (0), 140 | .TRIGGER (0) 141 | ) u_bit_field ( 142 | .i_clk (i_clk), 143 | .i_rst_n (i_rst_n), 144 | .bit_field_if (bit_field_sub_if), 145 | .o_write_trigger (), 146 | .o_read_trigger (), 147 | .i_sw_write_enable ('1), 148 | .i_hw_write_enable ('0), 149 | .i_hw_write_data ('0), 150 | .i_hw_set ('0), 151 | .i_hw_clear ('0), 152 | .i_value ('0), 153 | .i_mask ('1), 154 | .o_value (o_register_file_0_register_1_bit_field_0), 155 | .o_value_unmasked () 156 | ); 157 | end 158 | end 159 | end endgenerate 160 | generate if (1) begin : g_register_file_1 161 | if (1) begin : g_register_0 162 | genvar i; 163 | for (i = 0;i < 2;++i) begin : g 164 | rggen_bit_field_if #(32) bit_field_if(); 165 | logic [1:0] indirect_match; 166 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 167 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 168 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00; 169 | rggen_indirect_register #( 170 | .READABLE (1), 171 | .WRITABLE (1), 172 | .ADDRESS_WIDTH (7), 173 | .OFFSET_ADDRESS (7'h10), 174 | .BUS_WIDTH (32), 175 | .DATA_WIDTH (32), 176 | .VALUE_WIDTH (32), 177 | .INDIRECT_MATCH_WIDTH (2) 178 | ) u_register ( 179 | .i_clk (i_clk), 180 | .i_rst_n (i_rst_n), 181 | .register_if (register_if[2+i]), 182 | .i_indirect_match (indirect_match), 183 | .bit_field_if (bit_field_if) 184 | ); 185 | if (1) begin : g_bit_field_0 186 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 187 | rggen_bit_field_if #(8) bit_field_sub_if(); 188 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 189 | rggen_bit_field #( 190 | .WIDTH (8), 191 | .INITIAL_VALUE (INITIAL_VALUE), 192 | .SW_WRITE_ONCE (0), 193 | .TRIGGER (0) 194 | ) u_bit_field ( 195 | .i_clk (i_clk), 196 | .i_rst_n (i_rst_n), 197 | .bit_field_if (bit_field_sub_if), 198 | .o_write_trigger (), 199 | .o_read_trigger (), 200 | .i_sw_write_enable ('1), 201 | .i_hw_write_enable ('0), 202 | .i_hw_write_data ('0), 203 | .i_hw_set ('0), 204 | .i_hw_clear ('0), 205 | .i_value ('0), 206 | .i_mask ('1), 207 | .o_value (o_register_file_1_register_0_bit_field_0[i]), 208 | .o_value_unmasked () 209 | ); 210 | end 211 | end 212 | end 213 | if (1) begin : g_register_1 214 | genvar i; 215 | for (i = 0;i < 2;++i) begin : g 216 | rggen_bit_field_if #(32) bit_field_if(); 217 | logic [1:0] indirect_match; 218 | `rggen_tie_off_unused_signals(32, 32'h000000ff, bit_field_if) 219 | assign indirect_match[0] = register_if[0].value[0+:8] == 8'(i); 220 | assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01; 221 | rggen_indirect_register #( 222 | .READABLE (1), 223 | .WRITABLE (1), 224 | .ADDRESS_WIDTH (7), 225 | .OFFSET_ADDRESS (7'h10), 226 | .BUS_WIDTH (32), 227 | .DATA_WIDTH (32), 228 | .VALUE_WIDTH (32), 229 | .INDIRECT_MATCH_WIDTH (2) 230 | ) u_register ( 231 | .i_clk (i_clk), 232 | .i_rst_n (i_rst_n), 233 | .register_if (register_if[4+i]), 234 | .i_indirect_match (indirect_match), 235 | .bit_field_if (bit_field_if) 236 | ); 237 | if (1) begin : g_bit_field_0 238 | localparam bit [7:0] INITIAL_VALUE = 8'h00; 239 | rggen_bit_field_if #(8) bit_field_sub_if(); 240 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8) 241 | rggen_bit_field #( 242 | .WIDTH (8), 243 | .INITIAL_VALUE (INITIAL_VALUE), 244 | .SW_WRITE_ONCE (0), 245 | .TRIGGER (0) 246 | ) u_bit_field ( 247 | .i_clk (i_clk), 248 | .i_rst_n (i_rst_n), 249 | .bit_field_if (bit_field_sub_if), 250 | .o_write_trigger (), 251 | .o_read_trigger (), 252 | .i_sw_write_enable ('1), 253 | .i_hw_write_enable ('0), 254 | .i_hw_write_data ('0), 255 | .i_hw_set ('0), 256 | .i_hw_clear ('0), 257 | .i_value ('0), 258 | .i_mask ('1), 259 | .o_value (o_register_file_1_register_1_bit_field_0[i]), 260 | .o_value_unmasked () 261 | ); 262 | end 263 | end 264 | end 265 | end endgenerate 266 | generate if (1) begin : g_register_file_2 267 | genvar i; 268 | for (i = 0;i < 2;++i) begin : g 269 | if (1) begin : g_register_file_0 270 | if (1) begin : g_register_0 271 | genvar j; 272 | genvar k; 273 | for (j = 0;j < 2;++j) begin : g 274 | for (k = 0;k < 3;++k) begin : g 275 | rggen_bit_field_if #(32) bit_field_if(); 276 | `rggen_tie_off_unused_signals(32, 32'h00ffffff, bit_field_if) 277 | rggen_default_register #( 278 | .READABLE (1), 279 | .WRITABLE (1), 280 | .ADDRESS_WIDTH (7), 281 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'(4*(3*j+k))), 282 | .BUS_WIDTH (32), 283 | .DATA_WIDTH (32), 284 | .VALUE_WIDTH (32) 285 | ) u_register ( 286 | .i_clk (i_clk), 287 | .i_rst_n (i_rst_n), 288 | .register_if (register_if[6+7*i+3*j+k]), 289 | .bit_field_if (bit_field_if) 290 | ); 291 | if (1) begin : g_bit_field_0 292 | genvar l; 293 | for (l = 0;l < 2;++l) begin : g 294 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 295 | rggen_bit_field_if #(4) bit_field_sub_if(); 296 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+4*l, 4) 297 | rggen_bit_field #( 298 | .WIDTH (4), 299 | .INITIAL_VALUE (INITIAL_VALUE), 300 | .SW_WRITE_ONCE (0), 301 | .TRIGGER (0) 302 | ) u_bit_field ( 303 | .i_clk (i_clk), 304 | .i_rst_n (i_rst_n), 305 | .bit_field_if (bit_field_sub_if), 306 | .o_write_trigger (), 307 | .o_read_trigger (), 308 | .i_sw_write_enable ('1), 309 | .i_hw_write_enable ('0), 310 | .i_hw_write_data ('0), 311 | .i_hw_set ('0), 312 | .i_hw_clear ('0), 313 | .i_value ('0), 314 | .i_mask ('1), 315 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l]), 316 | .o_value_unmasked () 317 | ); 318 | end 319 | end 320 | if (1) begin : g_bit_field_1 321 | genvar l; 322 | for (l = 0;l < 2;++l) begin : g 323 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 324 | rggen_bit_field_if #(4) bit_field_sub_if(); 325 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+4*l, 4) 326 | rggen_bit_field #( 327 | .WIDTH (4), 328 | .INITIAL_VALUE (INITIAL_VALUE), 329 | .SW_WRITE_CONTROL (1), 330 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH) 331 | ) u_bit_field ( 332 | .i_clk (i_clk), 333 | .i_rst_n (i_rst_n), 334 | .bit_field_if (bit_field_sub_if), 335 | .o_write_trigger (), 336 | .o_read_trigger (), 337 | .i_sw_write_enable (register_if[0].value[0+:1]), 338 | .i_hw_write_enable ('0), 339 | .i_hw_write_data ('0), 340 | .i_hw_set ('0), 341 | .i_hw_clear ('0), 342 | .i_value ('0), 343 | .i_mask ('1), 344 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l]), 345 | .o_value_unmasked () 346 | ); 347 | end 348 | end 349 | if (1) begin : g_bit_field_2 350 | genvar l; 351 | for (l = 0;l < 2;++l) begin : g 352 | localparam bit [3:0] INITIAL_VALUE = 4'h0; 353 | rggen_bit_field_if #(4) bit_field_sub_if(); 354 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16+4*l, 4) 355 | rggen_bit_field #( 356 | .WIDTH (4), 357 | .INITIAL_VALUE (INITIAL_VALUE), 358 | .SW_WRITE_CONTROL (1), 359 | .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW) 360 | ) u_bit_field ( 361 | .i_clk (i_clk), 362 | .i_rst_n (i_rst_n), 363 | .bit_field_if (bit_field_sub_if), 364 | .o_write_trigger (), 365 | .o_read_trigger (), 366 | .i_sw_write_enable (register_if[6+7*i+6].value[0+1*l+:1]), 367 | .i_hw_write_enable ('0), 368 | .i_hw_write_data ('0), 369 | .i_hw_set ('0), 370 | .i_hw_clear ('0), 371 | .i_value ('0), 372 | .i_mask ('1), 373 | .o_value (o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l]), 374 | .o_value_unmasked () 375 | ); 376 | end 377 | end 378 | end 379 | end 380 | end 381 | if (1) begin : g_register_1 382 | rggen_bit_field_if #(32) bit_field_if(); 383 | `rggen_tie_off_unused_signals(32, 32'h00000003, bit_field_if) 384 | rggen_default_register #( 385 | .READABLE (1), 386 | .WRITABLE (1), 387 | .ADDRESS_WIDTH (7), 388 | .OFFSET_ADDRESS (7'h20+7'(32*i)+7'h18), 389 | .BUS_WIDTH (32), 390 | .DATA_WIDTH (32), 391 | .VALUE_WIDTH (32) 392 | ) u_register ( 393 | .i_clk (i_clk), 394 | .i_rst_n (i_rst_n), 395 | .register_if (register_if[6+7*i+6]), 396 | .bit_field_if (bit_field_if) 397 | ); 398 | if (1) begin : g_bit_field_0 399 | genvar j; 400 | for (j = 0;j < 2;++j) begin : g 401 | localparam bit INITIAL_VALUE = 1'h0; 402 | rggen_bit_field_if #(1) bit_field_sub_if(); 403 | `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+1*j, 1) 404 | rggen_bit_field #( 405 | .WIDTH (1), 406 | .INITIAL_VALUE (INITIAL_VALUE), 407 | .SW_WRITE_ONCE (0), 408 | .TRIGGER (0) 409 | ) u_bit_field ( 410 | .i_clk (i_clk), 411 | .i_rst_n (i_rst_n), 412 | .bit_field_if (bit_field_sub_if), 413 | .o_write_trigger (), 414 | .o_read_trigger (), 415 | .i_sw_write_enable ('1), 416 | .i_hw_write_enable ('0), 417 | .i_hw_write_data ('0), 418 | .i_hw_set ('0), 419 | .i_hw_clear ('0), 420 | .i_value ('0), 421 | .i_mask ('1), 422 | .o_value (o_register_file_2_register_file_0_register_1_bit_field_0[i][j]), 423 | .o_value_unmasked () 424 | ); 425 | end 426 | end 427 | end 428 | end 429 | end 430 | end endgenerate 431 | endmodule 432 | --------------------------------------------------------------------------------