├── AHB ├── ahb3lite_apb_bridge │ ├── LICENSE.txt │ ├── README.md │ └── rtl │ │ └── verilog │ │ └── ahb3lite_apb_bridge.sv ├── ahb3lite_interconnect │ ├── README.md │ ├── bench │ │ └── verilog │ │ │ ├── AHB3LiteBus.sv │ │ │ ├── AHB3LiteDrv.sv │ │ │ ├── AHB3LiteMon.sv │ │ │ ├── AHB3Lite_hdr.sv │ │ │ ├── AHBBusTr.sv │ │ │ ├── BaseConfig.sv │ │ │ ├── BaseDrv.sv │ │ │ ├── BaseMon.sv │ │ │ ├── BaseScoreBoard.sv │ │ │ ├── BaseTr.sv │ │ │ ├── BusGenerator.sv │ │ │ ├── BusTr.sv │ │ │ ├── Config.sv │ │ │ ├── Environment.sv │ │ │ ├── ScoreBoard.sv │ │ │ ├── ahb3lite_if.sv │ │ │ ├── test.sv │ │ │ └── testbench_top.sv │ └── rtl │ │ └── verilog │ │ ├── LICENSE.txt │ │ ├── ahb3lite_interconnect.sv │ │ ├── ahb3lite_interconnect_master_port.sv │ │ └── ahb3lite_interconnect_slave_port.sv ├── ahb3lite_memory │ ├── README.md │ └── rtl │ │ └── verilog │ │ ├── LICENSE.txt │ │ └── ahb3lite_sram1rw.sv └── ahb3lite_pkg │ ├── README.md │ └── rtl │ └── verilog │ └── ahb3lite_pkg.sv ├── APB ├── apb4_gpio │ ├── README.md │ └── rtl │ │ └── verilog │ │ ├── LICENSE.txt │ │ └── apb_gpio.sv └── apb4_mux │ ├── README.md │ └── rtl │ └── verilog │ ├── LICENSE.txt │ └── apb_mux.sv └── README.md /AHB/ahb3lite_apb_bridge/LICENSE.txt: -------------------------------------------------------------------------------- 1 | PLEASE CAREFULLY REVIEW THE FOLLOWING TERMS AND CONDITIONS BEFORE DOWNLOADING 2 | AND USING THE LICENSED MATERIALS. 3 | THIS LICENSE AGREEMENT ("AGREEMENT") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER 4 | A SINGLE INDIVIDUAL, OR A SINGLE LEGAL ENTITY)("YOU") AND ROA LOGIC BV ("ROA 5 | LOGIC") COVERING THE PRODUCTS OR SERVICES YOU PURCHASE FROM ROA LOGIC. 6 | 7 | By downloading and/or using or installing products from Roa Logic you 8 | automatically agree to and are bound by the terms and conditions of this 9 | agreement. 10 | 11 | PLEASE NOTE THAT THIS AGREEMENT IS INTENDED FOR NON-COMMERCIAL USE OF THE 12 | PRODUCT. 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You agree to comply fully 116 | with all laws and regulations of the United States, European Union, and 117 | other countries to ensure that the product is not: 118 | - exported directly, or indirectly, in violation of export laws; 119 | - intended to be used for any purposes prohibited by export laws, including, 120 | but not limited to, nuclear, chemical, or biological weapons proliferation. 121 | 122 | 123 | 8. APPLICABLE LAW AND CHOICE OF FORUM 124 | 8.1. All agreements and contracts between you and Roa Logic, which these 125 | conditions are applicable to, shall be governed by Dutch law with the 126 | exclusion of the uniform UN Convention on Contracts for the 127 | International Sale of Goods (CISG) and other bilateral or multilateral 128 | treaties for the purpose of unifying international sales. 129 | 8.2. The competent courts in the district where Roa Logic has its registered 130 | office in the Netherlands has jurisdiction over all disputes concerning 131 | rights and obligations associated with the contractual relations. 132 | 8.3. Conversion 133 | If any clause or sentence of this agreement is held by a court of law to 134 | be illegal or unenforceable, the remaining provisions of the agreement 135 | remain in effect. The failure of Roa Logic to enforce any of the 136 | provisions in the agreement does not constitute a waiver of Roa Logic's 137 | rights to enforce any provision of the agreement in the future. 138 | 139 | -------------------------------------------------------------------------------- /AHB/ahb3lite_apb_bridge/README.md: -------------------------------------------------------------------------------- 1 | # ahb3lite_apb_bridge 2 | Fully Parameterised Asynchronous AHB3-Lite to APB Bridge. 3 | 4 |

Functionality

5 | This IP contains 2 interfaces; an AHB3-Lite Slave interface and an APB Master interface. Any transactions received on the AHB Slave interface are translated into APB transactions on the APB master interface. If the APB datawidth is less than the AHB datawidth, then the core automatically generates APB burst transactions. 6 | The interfaces can be on separate clock domains. The Bridge handles the clock domain crossing. 7 | 8 | Notes: 9 | - APB clock frequency must be equal or less than AHB clock frequency 10 | - APB Datawidth must be equal or less than AHB data width 11 | - APB and AHB datawidths must be multiples of bytes 12 | 13 |

Interfaces

14 | - AHB3-Lite slave interface 15 | - APB master interface 16 | 17 |

Dependencies

18 | This release requires the ahb3lite package found here https://github.com/RoaLogic/AMBA/tree/master/AHB/ahb3lite_pkg 19 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/README.md: -------------------------------------------------------------------------------- 1 | # ahb3lite_interconnect 2 | Fully Parameterised AHB3-Lite SoC Interconnect 3 | 4 | This project contains a fully parameterised AHB3-Multi-layer Interconnect switch for AHB3-Lite based SoCs. 5 | 6 |

License

7 | The RTL is released under a non-commercial license, the testbench is released under GNU-GPL3. 8 | 9 | For commercial applications/purposes, please contact us to reach an agreement with us based on our commercial license terms. 10 | 11 |

Dependencies

12 | This release requires the ahb3lite package found here https://github.com/RoaLogic/AMBA/tree/master/AHB/ahb3lite_pkg 13 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/bench/verilog/AHB3LiteBus.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // Bus Generator Transaction Class // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restrictions, provided that this copyright statement is // 25 | // not removed from the file and that any derivative work // 26 | // contains the original copyright notice and the associated // 27 | // disclaimer. // 28 | // // 29 | // This soure file is free software; you can redistribute // 30 | // it and/or modify it under the terms of the GNU General // 31 | // Public License as published by the Free Software // 32 | // Foundation, either version 3 of the License, or (at your // 33 | // option) any later versions. // 34 | // The current text of the License can be found at: // 35 | // http://www.gnu.org/licenses/gpl.html // 36 | // // 37 | // This source file is distributed in the hope that it will // 38 | // be useful, but WITHOUT ANY WARRANTY; without even the // 39 | // implied warranty of MERCHANTABILITY or FITTNESS FOR A // 40 | // PARTICULAR PURPOSE. See the GNU General Public License for // 41 | // more details. // 42 | // // 43 | ///////////////////////////////////////////////////////////////// 44 | 45 | 46 | class BusGenerator extends BaseTr; 47 | bit TrWrite; //read/write transaction 48 | int TrType; 49 | int TrSize; 50 | 51 | 52 | extern function new(); 53 | extern virtual function bit compare (input BaseTr to); 54 | extern virtual function BaseTr copy (input BaseTr to=null); 55 | extern virtual function void display (input string prefix=""); 56 | endclass : BusGenerator 57 | 58 | 59 | ///////////////////////////////////////////////////////////////// 60 | // 61 | // Class Methods 62 | // 63 | function BusGenerator::new(); 64 | super.new(); 65 | endfunction : new 66 | 67 | 68 | function bit BusGenerator::compare (input BaseTr to); 69 | BusGenerator cmp; 70 | 71 | if (!$cast(cmp, to)) //is 'to' the correct type? 72 | $finish; 73 | 74 | return ( (this.TrWrite == cmp.TrWrite ) && 75 | (this.TrType == cmp.TrType ) && 76 | (this.TrSize == cmp.TrSize )); 77 | endfunction : compare 78 | 79 | 80 | function BaseTr BusGenerator::copy (input BaseTr to=null); 81 | BusGenerator cp; 82 | 83 | if (to==null) cp = new(); 84 | else $cast(cp, to); 85 | 86 | 87 | endfunction : copy 88 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/bench/verilog/AHB3LiteDrv.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3Lite Driver Class // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restrictions, provided that this copyright statement is // 25 | // not removed from the file and that any derivative work // 26 | // contains the original copyright notice and the associated // 27 | // disclaimer. // 28 | // // 29 | // This soure file is free software; you can redistribute // 30 | // it and/or modify it under the terms of the GNU General // 31 | // Public License as published by the Free Software // 32 | // Foundation, either version 3 of the License, or (at your // 33 | // option) any later versions. // 34 | // The current text of the License can be found at: // 35 | // http://www.gnu.org/licenses/gpl.html // 36 | // // 37 | // This source file is distributed in the hope that it will // 38 | // be useful, but WITHOUT ANY WARRANTY; without even the // 39 | // implied warranty of MERCHANTABILITY or FITTNESS FOR A // 40 | // PARTICULAR PURPOSE. See the GNU General Public License for // 41 | // more details. // 42 | // // 43 | ///////////////////////////////////////////////////////////////// 44 | 45 | `include "AHB3Lite_hdr.sv" 46 | 47 | class AHB3LiteDrv extends BaseDrv; 48 | virtual ahb3lite_if.master master; //Virtual interface; master 49 | ScoreBoard scb; //ScoreBoard 50 | 51 | function new(input mailbox gen2drv, 52 | input event drv2gen, 53 | input int PortId, 54 | input ScoreBoard scb, 55 | input virtual ahb3lite_if.master master); 56 | 57 | super.new(gen2drv,drv2gen,PortId); 58 | this.scb = scb; 59 | this.master = master; 60 | endfunction : new 61 | 62 | extern virtual task run(); 63 | extern task initialize(); 64 | extern task wait4hready(); 65 | extern task ahb_cmd(input AHBBusTr tr); 66 | extern task ahb_data(input AHBBusTr tr); 67 | 68 | extern function bit[2:0] BytesPerTransfer2HSIZE(input int unsigned BytesPerTransfer); 69 | extern function bit[2:0] TransferSize2HBURST(input int unsigned TransferSize); 70 | endclass : AHB3LiteDrv 71 | 72 | 73 | ///////////////////////////////////////////////////////////////// 74 | // 75 | // Class Methods 76 | // 77 | 78 | //------------------------------------- 79 | //Put AHB3-Lite bus in initial state 80 | task AHB3LiteDrv::initialize(); 81 | master.HTRANS <= HTRANS_IDLE; 82 | 83 | //wait for reset to negate 84 | @(posedge master.HRESETn); 85 | endtask : initialize 86 | 87 | 88 | //------------------------------------- 89 | //Wait for HREADY to assert 90 | task AHB3LiteDrv::wait4hready(); 91 | do 92 | @(master.cb_master); 93 | while (master.cb_master.HREADY !== 1'b1); 94 | endtask : wait4hready 95 | 96 | 97 | //------------------------------------- 98 | //Drive AHB3-Lite bus 99 | //Get transactions from mailbox and translate them into AHB3Lite signals 100 | task AHB3LiteDrv::run(); 101 | AHBBusTr tr; 102 | 103 | forever 104 | begin 105 | if (!master.HRESETn) initialize(); 106 | 107 | //read new transaction 108 | gen2drv.get(tr); 109 | 110 | //generate transfers 111 | /*!! tr.TransferSize==0 means an IDLE transfer; no data !!*/ 112 | fork 113 | ahb_cmd(tr); 114 | ahb_data(tr); 115 | join_any 116 | 117 | //signal transfer-complete to driver 118 | ->drv2gen; 119 | end 120 | endtask : run 121 | 122 | 123 | //------------------------------------- 124 | //AHB command signals 125 | task AHB3LiteDrv::ahb_cmd(input AHBBusTr tr); 126 | byte address[]; 127 | int cnt; 128 | 129 | //wait for HREADY 130 | wait4hready(); 131 | 132 | //first cycle of a (potential) burst 133 | master.cb_master.HSEL <= 1'b1; 134 | master.cb_master.HTRANS <= tr.TransferSize > 0 ? HTRANS_NONSEQ : HTRANS_IDLE; 135 | master.cb_master.HWRITE <= tr.Write; 136 | master.cb_master.HBURST <= TransferSize2HBURST(tr.TransferSize); 137 | master.cb_master.HSIZE <= BytesPerTransfer2HSIZE(tr.BytesPerTransfer); 138 | master.cb_master.HMASTLOCK <= 1'b0; //TODO: test 139 | 140 | if (tr.TransferSize > 0) 141 | begin 142 | address = tr.AddressQueue[0]; 143 | foreach (address[i]) master.cb_master.HADDR[i*8 +: 8] <= address[i]; 144 | 145 | //Next cycles (optional) 146 | cnt = 1; 147 | repeat (tr.TransferSize -1) 148 | begin 149 | //wait for HREADY 150 | wait4hready(); 151 | 152 | master.cb_master.HTRANS <= HTRANS_SEQ; 153 | 154 | address = tr.AddressQueue[cnt++]; 155 | foreach (address[i]) master.cb_master.HADDR[i*8 +: 8] <= address[i]; 156 | end 157 | end 158 | else 159 | master.cb_master.HADDR <= 'hx; 160 | 161 | 162 | endtask : ahb_cmd 163 | 164 | 165 | //------------------------------------- 166 | //Transfer AHB data 167 | task AHB3LiteDrv::ahb_data(input AHBBusTr tr); 168 | byte address[], 169 | data[]; 170 | int unsigned data_offset, cnt; 171 | 172 | //Data transfer starts 1 bus-cycle after command/address 173 | wait4hready(); 174 | 175 | if (tr.TransferSize > 0) 176 | begin 177 | //First data from queue (for write cycle) 178 | cnt = 0; 179 | 180 | //where to start? 181 | address = tr.AddressQueue[0]; //Get first address of burst 182 | data_offset = address[0] & 'hff; //Get start address's LSB in UNSIGNED format 183 | data_offset %= ((tr.DataSize+7)/8); 184 | 185 | if (!tr.Write) 186 | begin 187 | //Extra cycle for reading (actually this is the 1st) 188 | wait4hready(); 189 | 190 | //set HWDATA='xxxx' 191 | master.cb_master.HWDATA <= 'hx; 192 | end 193 | 194 | //transfer bytes 195 | repeat (tr.TransferSize) 196 | begin 197 | //wait for HREADY 198 | wait4hready(); 199 | 200 | if (tr.Write) 201 | begin 202 | //write data 203 | data = tr.DataQueue[cnt++]; 204 | 205 | foreach (data[i]) 206 | master.cb_master.HWDATA[(i + data_offset)*8 +: 8] <= data[i]; 207 | end 208 | else 209 | begin 210 | //This is a read cycle. Read data from HRDATA 211 | data = new[ tr.BytesPerTransfer ]; 212 | 213 | foreach (data[i]) 214 | data[i] = master.cb_master.HRDATA[(i + data_offset)*8 +: 8]; 215 | 216 | tr.DataQueue.push_back(data); 217 | end 218 | 219 | data_offset = (data_offset + tr.BytesPerTransfer) % ((tr.DataSize+7)/8); 220 | end 221 | end 222 | 223 | 224 | //Done transmit; send transaction to scoreboard 225 | scb.save_expected(tr); 226 | 227 | 228 | // tr.display($sformatf("@%0t: Drv%0d: ", $time, PortId)); 229 | endtask : ahb_data 230 | 231 | 232 | //------------------------------------- 233 | //calculate HSIZE 234 | function bit[2:0] AHB3LiteDrv::BytesPerTransfer2HSIZE(input int unsigned BytesPerTransfer); 235 | case (BytesPerTransfer) 236 | 0: return 0; 237 | 1: return HSIZE_BYTE; 238 | 2: return HSIZE_HWORD; 239 | 4: return HSIZE_WORD; 240 | 8: return HSIZE_DWORD; 241 | default: $error("Unsupported number of bytes per transfer %0d", BytesPerTransfer); 242 | endcase 243 | endfunction : BytesPerTransfer2HSIZE 244 | 245 | 246 | //------------------------------------- 247 | //Generate HBURST 248 | function bit[2:0] AHB3LiteDrv::TransferSize2HBURST(input int unsigned TransferSize); 249 | case (TransferSize) 250 | 1 : return HBURST_SINGLE; 251 | 4 : return HBURST_INCR4; 252 | 8 : return HBURST_INCR8; 253 | 16 : return HBURST_INCR16; 254 | default: return HBURST_INCR; 255 | endcase 256 | endfunction : TransferSize2HBURST 257 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/bench/verilog/AHB3LiteMon.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3Lite Monitor Class // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restrictions, provided that this copyright statement is // 25 | // not removed from the file and that any derivative work // 26 | // contains the original copyright notice and the associated // 27 | // disclaimer. // 28 | // // 29 | // This soure file is free software; you can redistribute // 30 | // it and/or modify it under the terms of the GNU General // 31 | // Public License as published by the Free Software // 32 | // Foundation, either version 3 of the License, or (at your // 33 | // option) any later versions. // 34 | // The current text of the License can be found at: // 35 | // http://www.gnu.org/licenses/gpl.html // 36 | // // 37 | // This source file is distributed in the hope that it will // 38 | // be useful, but WITHOUT ANY WARRANTY; without even the // 39 | // implied warranty of MERCHANTABILITY or FITTNESS FOR A // 40 | // PARTICULAR PURPOSE. See the GNU General Public License for // 41 | // more details. // 42 | // // 43 | ///////////////////////////////////////////////////////////////// 44 | 45 | 46 | //`define DEBUG 47 | 48 | `include "AHB3Lite_hdr.sv" 49 | 50 | class AHB3LiteMon extends BaseMon; 51 | virtual ahb3lite_if.slave slave; //Virtual IF, Slave Port 52 | ScoreBoard scb; //ScoreBoard 53 | AHBBusTr tr; //current transfer 54 | 55 | function new(input int PortId, 56 | input ScoreBoard scb, 57 | input virtual ahb3lite_if.slave slave); 58 | 59 | super.new(PortId); 60 | this.scb = scb; 61 | this.slave = slave; 62 | endfunction : new 63 | 64 | extern virtual task run(); 65 | extern task initialize(); 66 | extern task wait4transfer(); 67 | extern task wait4hready(); 68 | extern task ahb_hreadyout(); 69 | extern task ahb_setup(input AHBBusTr tr); 70 | extern task ahb_next(input AHBBusTr tr); 71 | extern task ahb_data(input AHBBusTr tr); 72 | 73 | extern function byte_array_t getHADDR(ref byte_array_t arg); 74 | extern function int unsigned HSIZE2BytesPerTransfer(input logic [2:0] HSIZE); 75 | extern function int unsigned HBURST2TransferSize(input logic [2:0] HBURST); 76 | endclass : AHB3LiteMon 77 | 78 | 79 | ///////////////////////////////////////////////////////////////// 80 | // 81 | // Class Methods 82 | // 83 | 84 | //------------------------------------- 85 | //Reset Response 86 | task AHB3LiteMon::initialize(); 87 | slave.HREADYOUT <= 1'b1; 88 | slave.HRESP <= HRESP_OKAY; 89 | 90 | //wait for reset to negate 91 | @(posedge slave.HRESETn); 92 | endtask : initialize 93 | 94 | 95 | //------------------------------------- 96 | //AHB3-Lite response 97 | //Get transactions from AHB slave signals and respond 98 | task AHB3LiteMon::run(); 99 | 100 | forever 101 | begin 102 | if (!slave.HRESETn) initialize(); 103 | 104 | //wait for a new transfer 105 | wait4transfer(); 106 | 107 | //generate new transaction (stores received signals and data) 108 | tr = new(slave.HADDR_SIZE, slave.HDATA_SIZE); 109 | ahb_setup(tr); 110 | 111 | fork 112 | ahb_next(tr); 113 | ahb_data(tr); 114 | join_any 115 | end 116 | endtask : run 117 | 118 | 119 | //------------------------------------- 120 | //Check if slave is addressed 121 | task AHB3LiteMon::wait4transfer(); 122 | while (!slave.cb_slave.HREADY || 123 | !slave.cb_slave.HSEL || 124 | slave.cb_slave.HTRANS == HTRANS_IDLE) 125 | begin 126 | @(slave.cb_slave); 127 | slave.HREADYOUT <= 1'b1; 128 | end 129 | endtask : wait4transfer 130 | 131 | 132 | //------------------------------------- 133 | //Wait for HREADY to assert 134 | task AHB3LiteMon::wait4hready(); 135 | while (slave.cb_slave.HREADY !== 1'b1 || slave.cb_slave.HTRANS == HTRANS_BUSY) @(slave.cb_slave); 136 | endtask : wait4hready 137 | 138 | 139 | //------------------------------------- 140 | //Create new BusTransaction (receive side) 141 | // 142 | //When we get here, the previous transaction completed (HREADY='1') 143 | task AHB3LiteMon::ahb_setup(input AHBBusTr tr); 144 | byte address[]; 145 | 146 | //Get AHB Setup cycle signals 147 | address = new[ (tr.AddressSize+7)/8 ]; 148 | getHADDR(address); 149 | tr.AddressQueue.push_back( address ); 150 | 151 | tr.BytesPerTransfer = HSIZE2BytesPerTransfer(slave.cb_slave.HSIZE); 152 | tr.TransferSize = 1; //set to 1. Actually count transfers per burst 153 | tr.Write = slave.cb_slave.HWRITE; 154 | endtask : ahb_setup 155 | 156 | 157 | //------------------------------------- 158 | //Get next transfer 159 | // 160 | //When we get here, we only stored the data of the 1st cycle of the transaction 161 | //and we're still in the 1st cycle 162 | task AHB3LiteMon::ahb_next(input AHBBusTr tr); 163 | byte address[]; 164 | 165 | //progress bus cycle (2nd cycle of burst) 166 | //HREADY='1' (from 'wait4transfer'), so proceed 1 cycle 167 | @(slave.cb_slave); 168 | 169 | //$display ("%0t %0d %0d %0d %0d", $time, PortId, slave.cb_slave.HSEL, slave.cb_slave.HTRANS, slave.cb_slave.HREADY); 170 | 171 | while (slave.cb_slave.HSEL == 1'b1 && 172 | (slave.cb_slave.HTRANS == HTRANS_SEQ || slave.cb_slave.HTRANS == HTRANS_BUSY || slave.cb_slave.HREADY !== 1'b1) ) 173 | begin 174 | if (slave.cb_slave.HREADY && slave.cb_slave.HTRANS == HTRANS_SEQ) 175 | begin 176 | address = new[ (tr.AddressSize+7)/8 ]; 177 | getHADDR(address); 178 | tr.AddressQueue.push_back( address ); 179 | 180 | //one more cycle in this burst. Increase TransferSize 181 | tr.TransferSize++; 182 | end 183 | 184 | @(slave.cb_slave); 185 | end 186 | endtask : ahb_next 187 | 188 | 189 | //------------------------------------- 190 | //AHB Data task 191 | // 192 | //When we get here, we only stored the data of the 1st cycle of the transaction 193 | //and we're still in the 1st cycle 194 | //We're in control of HREADY (actually HREADYOUT) 195 | task AHB3LiteMon::ahb_data(input AHBBusTr tr); 196 | byte data[], address[]; 197 | byte data_queue[$]; 198 | int unsigned data_offset, 199 | cnt; 200 | 201 | //what's the start address? 202 | address = tr.AddressQueue[0]; 203 | 204 | //what's the offset in the databus? 205 | data_offset = address[0] & 'hff; //get address LSB in UNSIGNED format 206 | data_offset %= ((tr.DataSize+7)/8); 207 | 208 | cnt = 0; 209 | while (cnt !== tr.TransferSize) 210 | begin 211 | //increase transfer counter 212 | cnt++; 213 | 214 | //generate new 'data' object 215 | data = new[ tr.BytesPerTransfer ]; 216 | 217 | //send/receive actual data 218 | if (tr.Write) 219 | begin 220 | //This is a write cycle 221 | 222 | //generate HREADYOUT (delay) 223 | ahb_hreadyout(); 224 | 225 | //proceed to next cycle of burst (this drives HREADYOUT high) 226 | @(slave.cb_slave); 227 | 228 | //and read data from HWDATA (while HREADYOUT is high) 229 | foreach (data[i]) 230 | data[i] = slave.cb_slave.HWDATA[(i + data_offset)*8 +: 8]; 231 | end 232 | else 233 | begin 234 | //This is a read cycle 235 | 236 | //generate HREADYOUT (delay) 237 | ahb_hreadyout(); 238 | 239 | //Provide data on HRDATA 240 | foreach (data[i]) 241 | begin 242 | data[i] = $random; 243 | slave.cb_slave.HRDATA[(i + data_offset)*8 +: 8] <= data[i]; 244 | end 245 | 246 | //and proceed to next cycle of burst 247 | //This drives HREADYOUT high and drives the data 248 | @(slave.cb_slave); 249 | end 250 | 251 | //push handle into the queue 252 | tr.DataQueue.push_back(data); 253 | 254 | data_offset = (data_offset + tr.BytesPerTransfer) % ((tr.DataSize+7)/8); 255 | end 256 | 257 | 258 | //check transaction 259 | if (tr.Write == 0) #1; 260 | scb.check_actual(tr, PortId); 261 | 262 | 263 | `ifdef DEBUG 264 | //Execute here to ensure last data cycle completes before display 265 | //and 'tr' doesn't get mixed up with new transaction 266 | tr.display($sformatf("@%0t Mon%0d: ", $time, PortId)); 267 | `endif 268 | endtask : ahb_data 269 | 270 | 271 | //------------------------------------- 272 | //Generate HREADYOUT 273 | //Generate useful HREADYOUT delays 274 | task AHB3LiteMon::ahb_hreadyout(); 275 | //useful delays; 276 | // no delay : 0 277 | // some delay : 1, 2, 278 | // burst delay : 4, 8, 16 (check for buffer overrun) 279 | 280 | int delay_opt, 281 | delay, 282 | cnt; 283 | 284 | //generate HREADYOUT 285 | delay_opt = $urandom_range(0,5); //pick a number between 0 and 5 286 | 287 | case (delay_opt) 288 | 0: delay = 0; 289 | 1: delay = 1; 290 | 2: delay = 2; 291 | 3: delay = 4; 292 | 4: delay = 8; 293 | 5: delay = 16; 294 | endcase 295 | 296 | //drive HREADYOUT low for the duration of the delay 297 | for (int n=1; n < delay; n++) 298 | begin 299 | slave.cb_slave.HREADYOUT <= 1'b0; 300 | @(slave.cb_slave); 301 | end 302 | 303 | //drive HREADYOUT high 304 | slave.cb_slave.HREADYOUT <= 1'b1; 305 | endtask : ahb_hreadyout 306 | 307 | 308 | //------------------------------------- 309 | //Gets current HADDR 310 | function byte_array_t AHB3LiteMon::getHADDR(ref byte_array_t arg); 311 | foreach (arg[i]) arg[i] = slave.cb_slave.HADDR[i*8 +: 8]; 312 | 313 | return arg; 314 | endfunction : getHADDR 315 | 316 | 317 | //------------------------------------- 318 | //Convert HSIZE to Bytes-per-Transfer 319 | function int unsigned AHB3LiteMon::HSIZE2BytesPerTransfer(input logic [2:0] HSIZE); 320 | case (HSIZE) 321 | HSIZE_BYTE : return 1; 322 | HSIZE_HWORD: return 2; 323 | HSIZE_WORD : return 4; 324 | HSIZE_DWORD: return 8; 325 | default : $error("@%0t: Unsupported HSIZE(%3b)", $time, HSIZE); 326 | endcase 327 | endfunction : HSIZE2BytesPerTransfer 328 | 329 | 330 | //------------------------------------- 331 | //Convert HBURST to TransferSize 332 | function int unsigned AHB3LiteMon::HBURST2TransferSize(input logic [2:0] HBURST); 333 | int unsigned TransferSize; 334 | 335 | case (HBURST) 336 | HBURST_SINGLE: return 1; 337 | HBURST_INCR4 : return 4; 338 | HBURST_INCR8 : return 8; 339 | HBURST_INCR16: return 16; 340 | HBURST_INCR : return 0; 341 | default : begin 342 | $error("@%0t: Unsupported HBURST(%3b)", $time, HBURST); 343 | TransferSize = 0; 344 | end 345 | endcase 346 | endfunction : HBURST2TransferSize 347 | 348 | 349 | `ifdef DEBUG 350 | `undef DEBUG 351 | `endif 352 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/bench/verilog/AHB3Lite_hdr.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3Lite Header, used by Driver+Monitor // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restrictions, provided that this copyright statement is // 25 | // not removed from the file and that any derivative work // 26 | // contains the original copyright notice and the associated // 27 | // disclaimer. // 28 | // // 29 | // This soure file is free software; you can redistribute // 30 | // it and/or modify it under the terms of the GNU General // 31 | // Public License as published by the Free Software // 32 | // Foundation, either version 3 of the License, or (at your // 33 | // option) any later versions. // 34 | // The current text of the License can be found at: // 35 | // http://www.gnu.org/licenses/gpl.html // 36 | // // 37 | // This source file is distributed in the hope that it will // 38 | // be useful, but WITHOUT ANY WARRANTY; without even the // 39 | // implied warranty of MERCHANTABILITY or FITTNESS FOR A // 40 | // PARTICULAR PURPOSE. See the GNU General Public License for // 41 | // more details. // 42 | // // 43 | ///////////////////////////////////////////////////////////////// 44 | 45 | `ifndef AHB3LITE_HDR 46 | `define AHB3LITE_HDR 47 | 48 | typedef byte byte_array_t[]; 49 | `endif 50 | 51 | //import is required in each file 52 | import ahb3lite_pkg::*; 53 | 54 | 55 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/bench/verilog/AHBBusTr.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3Lite Bus Transaction Class // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restrictions, provided that this copyright statement is // 25 | // not removed from the file and that any derivative work // 26 | // contains the original copyright notice and the associated // 27 | // disclaimer. // 28 | // // 29 | // This soure file is free software; you can redistribute // 30 | // it and/or modify it under the terms of the GNU General // 31 | // Public License as published by the Free Software // 32 | // Foundation, either version 3 of the License, or (at your // 33 | // option) any later versions. // 34 | // The current text of the License can be found at: // 35 | // http://www.gnu.org/licenses/gpl.html // 36 | // // 37 | // This source file is distributed in the hope that it will // 38 | // be useful, but WITHOUT ANY WARRANTY; without even the // 39 | // implied warranty of MERCHANTABILITY or FITTNESS FOR A // 40 | // PARTICULAR PURPOSE. See the GNU General Public License for // 41 | // more details. // 42 | // // 43 | ///////////////////////////////////////////////////////////////// 44 | 45 | //`define DEBUG 46 | 47 | //------------------------------------- 48 | // AHB Bus Class 49 | // Specialisation for AHB, from Bus-class 50 | 51 | //typedef enum {byte='b000, hword='b001, word='b010, dword='b011} tHSIZE; 52 | //typedef enum {single='b000, incr='b001, incr4='b011, incr8='b101, incr16='b111} tHBURST; 53 | 54 | `include "AHB3Lite_hdr.sv" 55 | 56 | class AHBBusTr extends BusTr; 57 | extern function new(input int unsigned AddressSize, DataSize); 58 | extern virtual function BaseTr copy (input BaseTr to=null); 59 | extern virtual function void randomize_bus; 60 | extern function void idle; 61 | extern function byte_array_t NextAddress(byte_array_t address); 62 | 63 | endclass : AHBBusTr 64 | 65 | 66 | ///////////////////////////////////////////////////////////////// 67 | // 68 | // Class Methods 69 | // 70 | 71 | //------------------------------------- 72 | //Constructor 73 | function AHBBusTr::new(input int unsigned AddressSize, DataSize); 74 | super.new(AddressSize,DataSize); 75 | 76 | `ifdef DEBUG 77 | $display("AHBBusTr::new"); 78 | `endif 79 | endfunction : new 80 | 81 | 82 | //------------------------------------- 83 | //Make a copy of this object 84 | //Keep $cast happy 85 | function BaseTr AHBBusTr::copy (input BaseTr to); 86 | AHBBusTr cp; 87 | cp = new(AddressSize,DataSize); 88 | 89 | return super.copy(cp); 90 | endfunction : copy 91 | 92 | 93 | //------------------------------------- 94 | //Randomize class variables 95 | function void AHBBusTr::randomize_bus (); 96 | byte address[], 97 | data[]; 98 | int unsigned address_check; 99 | 100 | 101 | //write or read? 102 | //Translates directly to HWRITE 103 | Write = $urandom_range(1); 104 | 105 | //Bytes-per-Transfer 106 | //Translates directly to HSIZE 107 | BytesPerTransfer = 1 << $urandom_range( $clog2( (DataSize+7)/8 ) ); 108 | 109 | //number of bytes to transfers 110 | //Translates to HBURST (and HTRANS) 111 | TransferSize = $urandom_range(5); //This encodes HBURST 112 | case (TransferSize) 113 | 0: TransferSize = 0; //IDLE 114 | 1: TransferSize = 1; //Single 115 | 2: TransferSize = $urandom_range(31); //INCR burst 116 | 3: TransferSize = 4; //INCR4 117 | 4: TransferSize = 8; //INCR8 118 | 5: TransferSize = 16; //INCR16 119 | endcase 120 | 121 | 122 | //Start Address 123 | //Translates to HADDR 124 | //TODO: AHB specifications say Address-burst must not cross 1KB boundary 125 | AddressQueue.delete(); 126 | 127 | //chose a start address 128 | address = new[ (AddressSize+7)/8 ]; 129 | foreach (address[i]) address[i] = $urandom(); 130 | 131 | //Ensure burst doesn't cross 1K boundary (as specified by AMBA specs) 132 | if (AddressSize > 10) 133 | begin 134 | //get Address[9:0] 135 | address_check[ 7 :0] = address[0]; 136 | address_check[15 :8] = address[1]; 137 | //$display("Check address boundary %02x%02x %4x", address[1],address[0], address_check); 138 | //$display("%x, %0d, %0d -> %0x", address_check[9:0], TransferSize, BytesPerTransfer, address_check[9:0] + (TransferSize * BytesPerTransfer) ); 139 | 140 | //Now check if the total address crosses the 1K boundary 141 | if (address_check[9:0] + (TransferSize * BytesPerTransfer) > 2**10) 142 | begin 143 | //$display("Address crosses 1k boundary: %x", address); 144 | //start at 1K boundary 145 | address[0] = 0; 146 | address[1] &= 'hc0; 147 | address[1] += 'h40; 148 | end 149 | end 150 | 151 | //clear LSBs based on BytesPerTransfer 152 | address[0] = address[0] & (8'hFF << $clog2(BytesPerTransfer)); 153 | AddressQueue.push_back(address); 154 | 155 | for (int i=0; i> Riviera-Pro Bug << 72 | */ 73 | // master = $root.testbench_top.ahb_master; 74 | master[0] = $root.testbench_top.ahb_master[0]; 75 | master[1] = $root.testbench_top.ahb_master[1]; 76 | master[2] = $root.testbench_top.ahb_master[2]; 77 | 78 | // slave = $root.testbench_top.ahb_slave; 79 | slave[0] = $root.testbench_top.ahb_slave[0]; 80 | slave[1] = $root.testbench_top.ahb_slave[1]; 81 | slave[2] = $root.testbench_top.ahb_slave[2]; 82 | slave[3] = $root.testbench_top.ahb_slave[3]; 83 | slave[4] = $root.testbench_top.ahb_slave[4]; 84 | 85 | env = new(master,slave,mst_priority,addr_base,addr_mask); 86 | env.gen_cfg(); 87 | env.build(); 88 | env.run(); 89 | env.wrap_up(); 90 | end 91 | 92 | endprogram : test 93 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/bench/verilog/testbench_top.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3-Lite Interconnect Switch Testbench (Top level) // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restrictions, provided that this copyright statement is // 25 | // not removed from the file and that any derivative work // 26 | // contains the original copyright notice and the associated // 27 | // disclaimer. // 28 | // // 29 | // This soure file is free software; you can redistribute // 30 | // it and/or modify it under the terms of the GNU General // 31 | // Public License as published by the Free Software // 32 | // Foundation, either version 3 of the License, or (at your // 33 | // option) any later versions. // 34 | // The current text of the License can be found at: // 35 | // http://www.gnu.org/licenses/gpl.html // 36 | // // 37 | // This source file is distributed in the hope that it will // 38 | // be useful, but WITHOUT ANY WARRANTY; without even the // 39 | // implied warranty of MERCHANTABILITY or FITTNESS FOR A // 40 | // PARTICULAR PURPOSE. See the GNU General Public License for // 41 | // more details. // 42 | // // 43 | ///////////////////////////////////////////////////////////////// 44 | 45 | module testbench_top; 46 | parameter MASTERS = 3; //Number of master ports 47 | parameter SLAVES = 5; //Number of slave ports 48 | 49 | parameter HADDR_SIZE = 16; 50 | parameter HDATA_SIZE = 32; 51 | 52 | 53 | ///////////////////////////////////////////////////////// 54 | // 55 | // Variables 56 | // 57 | genvar m, s; 58 | 59 | logic [ 2:0] mst_priority [MASTERS]; 60 | logic [HADDR_SIZE -1:0] slv_addr_mask [SLAVES ]; 61 | logic [HADDR_SIZE -1:0] slv_addr_base [SLAVES ]; 62 | 63 | logic mst_HSEL [MASTERS], 64 | slv_HSEL [SLAVES ]; 65 | logic [HADDR_SIZE -1:0] mst_HADDR [MASTERS], 66 | slv_HADDR [SLAVES ]; 67 | logic [HDATA_SIZE -1:0] mst_HWDATA [MASTERS], 68 | slv_HWDATA [SLAVES ]; 69 | logic [HDATA_SIZE -1:0] mst_HRDATA [MASTERS], 70 | slv_HRDATA [SLAVES ]; 71 | logic mst_HWRITE [MASTERS], 72 | slv_HWRITE [SLAVES ]; 73 | logic [ 2:0] mst_HSIZE [MASTERS], 74 | slv_HSIZE [SLAVES ]; 75 | logic [ 2:0] mst_HBURST [MASTERS], 76 | slv_HBURST [SLAVES ]; 77 | logic [ 3:0] mst_HPROT [MASTERS], 78 | slv_HPROT [SLAVES ]; 79 | logic [ 1:0] mst_HTRANS [MASTERS], 80 | slv_HTRANS [SLAVES ]; 81 | logic mst_HMASTLOCK [MASTERS], 82 | slv_HMASTLOCK [SLAVES ]; 83 | logic mst_HREADY [MASTERS], 84 | slv_HREADY [SLAVES ]; 85 | logic mst_HREADYOUT [MASTERS], 86 | slv_HREADYOUT [SLAVES ]; 87 | logic mst_HRESP [MASTERS], 88 | slv_HRESP [SLAVES ]; 89 | 90 | 91 | ///////////////////////////////////////////////////////// 92 | // 93 | // Clock & Reset 94 | // 95 | bit HCLK, HRESETn; 96 | initial begin : gen_HCLK 97 | HCLK <= 1'b0; 98 | forever #10 HCLK = ~ HCLK; 99 | end : gen_HCLK 100 | 101 | initial begin : gen_HRESETn; 102 | HRESETn <= 1'b0; 103 | #32; 104 | HRESETn <= 1'b1; 105 | end : gen_HRESETn; 106 | 107 | 108 | ///////////////////////////////////////////////////////// 109 | // 110 | // Master & Slave Model ports 111 | // 112 | ahb3lite_if #(HADDR_SIZE, HDATA_SIZE) ahb_master[MASTERS] (HCLK,HRESETn); 113 | ahb3lite_if #(HADDR_SIZE, HDATA_SIZE) ahb_slave [SLAVES ] (HCLK,HRESETn); 114 | 115 | 116 | ///////////////////////////////////////////////////////// 117 | // 118 | // Master->Slave mapping 119 | // 120 | //TODO: Move into tb() 121 | assign slv_addr_base[0] = 'h0000; 122 | assign slv_addr_base[1] = 'h2000; 123 | assign slv_addr_base[2] = 'h3000; 124 | assign slv_addr_base[3] = 'h4000; 125 | assign slv_addr_base[4] = 'h8000; 126 | 127 | assign slv_addr_mask[0] = 'he000; 128 | assign slv_addr_mask[1] = 'hf000; 129 | assign slv_addr_mask[2] = 'hf000; 130 | assign slv_addr_mask[3] = 'hc000; 131 | assign slv_addr_mask[4] = 'h8000; 132 | 133 | 134 | ///////////////////////////////////////////////////////// 135 | // 136 | // Map SystemVerilog Interface to ports 137 | // 138 | generate 139 | for (m=0;m HREADY logic (only 1 master/slave connection) 152 | assign mst_HREADY [m] = mst_HREADYOUT[m]; 153 | 154 | assign ahb_master[m].HRDATA = mst_HRDATA[m]; 155 | assign ahb_master[m].HREADY = mst_HREADY[m]; 156 | assign ahb_master[m].HRESP = mst_HRESP [m]; 157 | end 158 | 159 | for (s=0;sSlave 224 | generate 225 | for (s=0; sMaster 250 | generate 251 | for (m=0; m> 1; 145 | endfunction //onehot2int 146 | 147 | 148 | ////////////////////////////////////////////////////////////////// 149 | // 150 | // Module Body 151 | // 152 | 153 | 154 | /* 155 | * Register Address Phase Signals 156 | */ 157 | always @(posedge HCLK,negedge HRESETn) 158 | if (!HRESETn ) regHTRANS <= HTRANS_IDLE; 159 | else if ( mst_HREADY ) regHTRANS <= mst_HSEL ? mst_HTRANS : HTRANS_IDLE; 160 | 161 | always @(posedge HCLK) 162 | if (mst_HREADY) 163 | begin 164 | regpriority <= mst_priority; 165 | regHADDR <= mst_HADDR; 166 | regHWDATA <= mst_HWDATA; 167 | regHWRITE <= mst_HWRITE; 168 | regHSIZE <= mst_HSIZE; 169 | regHBURST <= mst_HBURST; 170 | regHPROT <= mst_HPROT; 171 | regHMASTLOCK <= mst_HMASTLOCK; 172 | end 173 | 174 | /* 175 | * Generate local HREADY response 176 | */ 177 | always @(posedge HCLK,negedge HRESETn) 178 | if (!HRESETn ) local_HREADYOUT <= 1'b1; 179 | else if ( mst_HREADY) local_HREADYOUT <= (mst_HTRANS == HTRANS_IDLE) | ~mst_HSEL; 180 | 181 | /* 182 | * Access granted state machine 183 | * 184 | * NO_ACCESS : reset state 185 | * If there's no access requested, stay in this state 186 | * If there's an access requested and we get an access-grant, go to ACCESS state 187 | * else the access is pending 188 | * 189 | * ACCESS_PENDING: Intermediate state to hold bus-command (HTRANS, ...) 190 | * ACCESS_GRANTED: while access requested and granted stay in this state 191 | * else go to NO_ACCESS 192 | */ 193 | 194 | always @(posedge HCLK,negedge HRESETn) 195 | if (!HRESETn) access_state <= NO_ACCESS; 196 | else 197 | case (access_state) 198 | NO_ACCESS : if (~|current_HSEL && ~|pending_HSEL ) access_state <= NO_ACCESS; 199 | else if ( |(current_HSEL & master_granted) ) access_state <= ACCESS_GRANTED; 200 | else access_state <= ACCESS_PENDING; 201 | 202 | ACCESS_PENDING: if ( |(pending_HSEL & master_granted) && 203 | slvHREADY[slave_sel] ) access_state <= ACCESS_GRANTED; 204 | 205 | ACCESS_GRANTED: if (mst_HREADY && ~|current_HSEL ) access_state <= NO_ACCESS; 206 | else if (mst_HREADY && ~|(current_HSEL & master_granted & slvHREADY) ) access_state <= ACCESS_PENDING; 207 | endcase 208 | 209 | 210 | assign no_access = access_state == NO_ACCESS; 211 | assign access_pending = access_state == ACCESS_PENDING; 212 | assign access_granted = access_state == ACCESS_GRANTED; 213 | 214 | /* 215 | * Generate burst counter 216 | */ 217 | always @(posedge HCLK) 218 | if (mst_HREADY) 219 | if (mst_HTRANS == HTRANS_NONSEQ) 220 | begin 221 | case (mst_HBURST) 222 | HBURST_WRAP4 : burst_cnt <= 'd2; 223 | HBURST_INCR4 : burst_cnt <= 'd2; 224 | HBURST_WRAP8 : burst_cnt <= 'd6; 225 | HBURST_INCR8 : burst_cnt <= 'd6; 226 | HBURST_WRAP16: burst_cnt <= 'd14; 227 | HBURST_INCR16: burst_cnt <= 'd14; 228 | default : burst_cnt <= 'd0; 229 | endcase 230 | end 231 | else 232 | begin 233 | burst_cnt <= burst_cnt - 'h1; 234 | end 235 | 236 | /* 237 | * Indicate that the slave may switch masters on the NEXT cycle 238 | */ 239 | always_comb 240 | case (access_state) 241 | NO_ACCESS : can_switch = ~|(current_HSEL & master_granted); 242 | ACCESS_PENDING: can_switch = ~|(pending_HSEL & master_granted); 243 | ACCESS_GRANTED: can_switch = ~mst_HSEL | 244 | (mst_HSEL & ~mst_HMASTLOCK & mst_HREADY & 245 | ( (mst_HTRANS == HTRANS_IDLE ) | 246 | (mst_HTRANS == HTRANS_NONSEQ & mst_HBURST == HBURST_SINGLE ) | 247 | (mst_HTRANS == HTRANS_SEQ & mst_HBURST != HBURST_INCR & ~|burst_cnt) ) 248 | ); 249 | endcase 250 | 251 | 252 | /* 253 | * Decode slave-request; which AHB slave (master-port) to address? 254 | * 255 | * Send out connection request to slave-port 256 | * Slave-port replies by asserting master_gnt 257 | * TODO: check for illegal combinations (more than 1 slvHSEL asserted) 258 | */ 259 | generate 260 | for (s=0; s slv_HREADYOUT) 290 | assign slvpriority = mux_sel ? mst_priority : regpriority; 291 | 292 | 293 | /* 294 | * Incoming data (to masters) 295 | */ 296 | assign mst_HRDATA = slvHRDATA[slave_sel]; 297 | assign mst_HREADYOUT = access_granted ? slvHREADY[slave_sel] : local_HREADYOUT; //master's HREADYOUT is driven by slave's HREADY (slv_HREADY -> mst_HREADYOUT) 298 | assign mst_HRESP = access_granted ? slvHRESP [slave_sel] : HRESP_OKAY; 299 | endmodule 300 | 301 | 302 | -------------------------------------------------------------------------------- /AHB/ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_port.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3-Lite Interconnect Switch (Multi-Layer Switch) // 17 | // Slave Port (AHB Master) // 18 | // // 19 | ///////////////////////////////////////////////////////////////// 20 | // // 21 | // Copyright (C) 2016 ROA Logic BV // 22 | // www.roalogic.com // 23 | // // 24 | // Unless specifically agreed in writing, this software is // 25 | // licensed under the RoaLogic Non-Commercial License // 26 | // version-1.0 (the "License"), a copy of which is included // 27 | // with this file or may be found on the RoaLogic website // 28 | // http://www.roalogic.com. You may not use the file except // 29 | // in compliance with the License. // 30 | // // 31 | // THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY // 32 | // EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. // 33 | // See the License for permissions and limitations under the // 34 | // License. // 35 | // // 36 | ///////////////////////////////////////////////////////////////// 37 | 38 | 39 | module ahb3lite_interconnect_slave_port #( 40 | parameter HADDR_SIZE = 32, 41 | parameter HDATA_SIZE = 32, 42 | parameter MASTERS = 3, //number of slave-ports 43 | parameter SLAVES = 8 //number of master-ports 44 | ) 45 | ( 46 | input HRESETn, 47 | HCLK, 48 | 49 | //AHB Slave Interfaces (receive data from AHB Masters) 50 | //AHB Masters conect to these ports 51 | input [MASTERS-1:0][ 2:0] mstpriority, 52 | input [MASTERS-1:0] mstHSEL, 53 | input [MASTERS-1:0][HADDR_SIZE -1:0] mstHADDR, 54 | input [MASTERS-1:0][HDATA_SIZE -1:0] mstHWDATA, 55 | output [HDATA_SIZE -1:0] mstHRDATA, 56 | input [MASTERS-1:0] mstHWRITE, 57 | input [MASTERS-1:0][ 2:0] mstHSIZE, 58 | input [MASTERS-1:0][ 2:0] mstHBURST, 59 | input [MASTERS-1:0][ 3:0] mstHPROT, 60 | input [MASTERS-1:0][ 1:0] mstHTRANS, 61 | input [MASTERS-1:0] mstHMASTLOCK, 62 | input [MASTERS-1:0] mstHREADY, //HREADY input from master-bus 63 | output mstHREADYOUT, //HREADYOUT output to master-bus 64 | output mstHRESP, 65 | 66 | //AHB Master Interfaces (send data to AHB slaves) 67 | //AHB Slaves connect to these ports 68 | output slv_HSEL, 69 | output [HADDR_SIZE-1:0] slv_HADDR, 70 | output [HDATA_SIZE-1:0] slv_HWDATA, 71 | input [HDATA_SIZE-1:0] slv_HRDATA, 72 | output slv_HWRITE, 73 | output [ 2:0] slv_HSIZE, 74 | output [ 2:0] slv_HBURST, 75 | output [ 3:0] slv_HPROT, 76 | output [ 1:0] slv_HTRANS, 77 | output slv_HMASTLOCK, 78 | output slv_HREADYOUT, 79 | input slv_HREADY, 80 | input slv_HRESP, 81 | 82 | input [MASTERS -1:0] can_switch, 83 | output reg [MASTERS -1:0] granted_master 84 | ); 85 | ////////////////////////////////////////////////////////////////// 86 | // 87 | // Constants 88 | // 89 | import ahb3lite_pkg::*; 90 | 91 | localparam MASTER_BITS = $clog2(MASTERS); 92 | 93 | 94 | ////////////////////////////////////////////////////////////////// 95 | // 96 | // Variables 97 | // 98 | logic [ 2:0] requested_priority_lvl; //requested priority level 99 | logic [MASTERS -1:0] priority_masters; //all masters at this priority level 100 | 101 | logic [MASTERS -1:0] pending_master, //next master waiting to be served 102 | last_granted_master; //for requested priority level 103 | logic [ 2:0][MASTERS-1:0] last_granted_masters; //per priority level, for round-robin 104 | 105 | 106 | logic [MASTER_BITS-1:0] granted_master_idx, //granted master as index 107 | granted_master_idx_dly; //deleayed granted master index (for HWDATA) 108 | 109 | logic can_switch_master; //Slave may switch to a new master 110 | 111 | 112 | genvar m; 113 | 114 | 115 | ////////////////////////////////////////////////////////////////// 116 | // 117 | // Tasks 118 | // 119 | 120 | 121 | ////////////////////////////////////////////////////////////////// 122 | // 123 | // Functions 124 | // 125 | function integer onehot2int; 126 | input [SLAVES-1:0] onehot; 127 | 128 | for (onehot2int = -1; |onehot; onehot2int++) onehot = onehot >>1; 129 | endfunction //onehot2int 130 | 131 | 132 | function [2:0] highest_requested_priority ( 133 | input [MASTERS-1:0] hsel, 134 | input [MASTERS-1:0][2:0] priorities 135 | ); 136 | 137 | highest_requested_priority = 0; 138 | for (int n=0; n highest_requested_priority) highest_requested_priority = priorities[n]; 140 | endfunction //highest_requested_priority 141 | 142 | 143 | function [MASTERS-1:0] requesters; 144 | input [MASTERS-1:0] hsel; 145 | input [MASTERS-1:0][2:0] priorities; 146 | input [2:0] priority_select; 147 | 148 | for (int n=0; nDependencies 5 | This release requires the 6 | - ahb3lite package found here https://github.com/RoaLogic/AMBA/tree/master/AHB/ahb3lite_pkg 7 | - memorys IPs found here https://github.com/RoaLogic/memory 8 | 9 | 10 |

License

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You agree to comply fully 116 | with all laws and regulations of the United States, European Union, and 117 | other countries to ensure that the product is not: 118 | - exported directly, or indirectly, in violation of export laws; 119 | - intended to be used for any purposes prohibited by export laws, including, 120 | but not limited to, nuclear, chemical, or biological weapons proliferation. 121 | 122 | 123 | 8. APPLICABLE LAW AND CHOICE OF FORUM 124 | 8.1. All agreements and contracts between you and Roa Logic, which these 125 | conditions are applicable to, shall be governed by Dutch law with the 126 | exclusion of the uniform UN Convention on Contracts for the 127 | International Sale of Goods (CISG) and other bilateral or multilateral 128 | treaties for the purpose of unifying international sales. 129 | 8.2. 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The failure of Roa Logic to enforce any of the 136 | provisions in the agreement does not constitute a waiver of Roa Logic's 137 | rights to enforce any provision of the agreement in the future. 138 | 139 | -------------------------------------------------------------------------------- /AHB/ahb3lite_memory/rtl/verilog/ahb3lite_sram1rw.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AHB3-Lite Single Port SRAM // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // Unless specifically agreed in writing, this software is // 24 | // licensed under the RoaLogic Non-Commercial License // 25 | // version-1.0 (the "License"), a copy of which is included // 26 | // with this file or may be found on the RoaLogic website // 27 | // http://www.roalogic.com. You may not use the file except // 28 | // in compliance with the License. // 29 | // // 30 | // THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY // 31 | // EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. // 32 | // See the License for permissions and limitations under the // 33 | // License. // 34 | // // 35 | ///////////////////////////////////////////////////////////////// 36 | 37 | 38 | module ahb3lite_sram1rw #( 39 | parameter MEM_SIZE = 0, //Memory in Bytes 40 | parameter MEM_DEPTH = 256, //Memory depth 41 | parameter HADDR_SIZE = 8, 42 | parameter HDATA_SIZE = 32, 43 | parameter TECHNOLOGY = "GENERIC", 44 | parameter REGISTERED_OUTPUT = "NO" 45 | ) 46 | ( 47 | input HRESETn, 48 | HCLK, 49 | 50 | //AHB Slave Interfaces (receive data from AHB Masters) 51 | //AHB Masters connect to these ports 52 | input HSEL, 53 | input [HADDR_SIZE-1:0] HADDR, 54 | input [HDATA_SIZE-1:0] HWDATA, 55 | output reg [HDATA_SIZE-1:0] HRDATA, 56 | input HWRITE, 57 | input [ 2:0] HSIZE, 58 | input [ 2:0] HBURST, 59 | input [ 3:0] HPROT, 60 | input [ 1:0] HTRANS, 61 | output reg HREADYOUT, 62 | input HREADY, 63 | output HRESP 64 | ); 65 | 66 | 67 | ////////////////////////////////////////////////////////////////// 68 | // 69 | // Constants 70 | // 71 | import ahb3lite_pkg::*; 72 | 73 | localparam BE_SIZE = (HDATA_SIZE+7)/8; 74 | 75 | localparam MEM_SIZE_DEPTH = 8*MEM_SIZE / HDATA_SIZE; 76 | localparam REAL_MEM_DEPTH = MEM_DEPTH > MEM_SIZE_DEPTH ? MEM_DEPTH : MEM_SIZE_DEPTH; 77 | localparam MEM_ABITS = $clog2(REAL_MEM_DEPTH); 78 | localparam MEM_ABITS_LSB = $clog2(BE_SIZE); 79 | 80 | 81 | ////////////////////////////////////////////////////////////////// 82 | // 83 | // Variables 84 | // 85 | logic we; 86 | logic [BE_SIZE -1:0] be; 87 | logic [HADDR_SIZE-1:0] waddr; 88 | logic contention; 89 | logic ready; 90 | 91 | logic [HDATA_SIZE-1:0] dout; 92 | 93 | 94 | ////////////////////////////////////////////////////////////////// 95 | // 96 | // Functions 97 | // 98 | function logic [6:0] address_mask; 99 | //default value, prevent warnings 100 | address_mask = 0; 101 | 102 | //Which bits in HADDR should be taken into account? 103 | case (HDATA_SIZE) 104 | 1024: address_mask = 7'b111_1111; 105 | 512: address_mask = 7'b011_1111; 106 | 256: address_mask = 7'b001_1111; 107 | 128: address_mask = 7'b000_1111; 108 | 64: address_mask = 7'b000_0111; 109 | 32: address_mask = 7'b000_0011; 110 | 16: address_mask = 7'b000_0001; 111 | default: address_mask = 7'b000_0000; 112 | endcase 113 | endfunction //address_mask 114 | 115 | 116 | function logic [BE_SIZE-1:0] gen_be; 117 | input [ 2:0] hsize; 118 | input [HADDR_SIZE-1:0] haddr; 119 | 120 | logic [127:0] full_be; 121 | logic [ 6:0] haddr_masked; 122 | 123 | //get number of active lanes for a 1024bit databus (max width) for this HSIZE 124 | case (hsize) 125 | HSIZE_B1024: full_be = 'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff; 126 | HSIZE_B512 : full_be = 'hffff_ffff_ffff_ffff; 127 | HSIZE_B256 : full_be = 'hffff_ffff; 128 | HSIZE_B128 : full_be = 'hffff; 129 | HSIZE_DWORD: full_be = 'hff; 130 | HSIZE_WORD : full_be = 'hf; 131 | HSIZE_HWORD: full_be = 'h3; 132 | default : full_be = 'h1; 133 | endcase 134 | 135 | //generate masked address 136 | haddr_masked = haddr & address_mask(); 137 | 138 | //create PSTRB 139 | gen_be = full_be[BE_SIZE-1:0] << haddr_masked; 140 | endfunction //gen_be 141 | 142 | 143 | ////////////////////////////////////////////////////////////////// 144 | // 145 | // Module Body 146 | // 147 | 148 | //generate internal write signal 149 | //This causes read/write contention, which is handled by memory 150 | always @(posedge HCLK) 151 | if (HREADY) we <= HSEL & HWRITE & (HTRANS != HTRANS_BUSY) & (HTRANS != HTRANS_IDLE); 152 | else we <= 1'b0; 153 | 154 | //decode Byte-Enables 155 | always @(posedge HCLK) 156 | if (HREADY) be <= gen_be(HSIZE,HADDR); 157 | 158 | //store write address 159 | always @(posedge HCLK) 160 | if (HREADY) waddr <= HADDR; 161 | 162 | 163 | //Is there read/write contention on the memory? 164 | assign contention = (waddr[MEM_ABITS_LSB +: MEM_ABITS] == HADDR[MEM_ABITS_LSB +: MEM_ABITS]) & we & 165 | HSEL & HREADY & ~HWRITE & (HTRANS != HTRANS_BUSY) & (HTRANS != HTRANS_IDLE); 166 | 167 | //if all bytes were written contention is/can be handled by memory 168 | //otherwise stall a cycle (forced by N3S) 169 | //We could do an exception for N3S here, but this file should be technology agnostic 170 | assign ready = ~(contention & ~&be); 171 | 172 | 173 | /* 174 | * Hookup Memory Wrapper 175 | * Use two-port memory, due to pipelined AHB bus; 176 | * the actual write to memory is 1 cycle late, causing read/write overlap 177 | * This assumes there are input registers on the memory 178 | */ 179 | rl_ram_1r1w #( 180 | .ABITS ( MEM_ABITS ), 181 | .DBITS ( HDATA_SIZE ), 182 | .TECHNOLOGY ( TECHNOLOGY ) ) 183 | ram_inst ( 184 | .rstn ( HRESETn ), 185 | .clk ( HCLK ), 186 | 187 | .waddr ( waddr[MEM_ABITS_LSB +: MEM_ABITS] ), 188 | .we ( we ), 189 | .be ( be ), 190 | .din ( HWDATA ), 191 | 192 | .raddr ( HADDR[MEM_ABITS_LSB +: MEM_ABITS] ), 193 | .dout ( dout ) 194 | ); 195 | 196 | //AHB bus response 197 | assign HRESP = HRESP_OKAY; //always OK 198 | 199 | generate 200 | if (REGISTERED_OUTPUT == "NO") 201 | begin 202 | always @(posedge HCLK,negedge HRESETn) 203 | if (!HRESETn) HREADYOUT <= 1'b1; 204 | else HREADYOUT <= ready; 205 | 206 | always_comb HRDATA = dout; 207 | end 208 | else 209 | begin 210 | always @(posedge HCLK,negedge HRESETn) 211 | if (!HRESETn) HREADYOUT <= 1'b1; 212 | else if (HTRANS == HTRANS_NONSEQ && !HWRITE) HREADYOUT <= 1'b0; 213 | else HREADYOUT <= 1'b1; 214 | 215 | always @(posedge HCLK) 216 | if (HREADY) HRDATA <= dout; 217 | end 218 | endgenerate 219 | 220 | endmodule 221 | -------------------------------------------------------------------------------- /AHB/ahb3lite_pkg/README.md: -------------------------------------------------------------------------------- 1 | # ahb3lite_pkg 2 | Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces 3 | -------------------------------------------------------------------------------- /AHB/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // AMBA AHB3-Lite Package // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2015-2016 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // This source file may be used and distributed without // 24 | // restriction provided that this copyright statement is not // 25 | // removed from the file and that any derivative work contains // 26 | // the original copyright notice and the associated disclaimer.// 27 | // // 28 | // THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // 29 | // EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // 30 | // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // 31 | // FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // 32 | // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // 33 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // 34 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // 35 | // GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // 36 | // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // 37 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // 38 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // 39 | // OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // 40 | // POSSIBILITY OF SUCH DAMAGE. // 41 | // // 42 | ///////////////////////////////////////////////////////////////// 43 | 44 | 45 | /************************************************ 46 | * AHB3 Lite Package 47 | */ 48 | package ahb3lite_pkg; 49 | //HTRANS 50 | parameter [1:0] HTRANS_IDLE = 2'b00, 51 | HTRANS_BUSY = 2'b01, 52 | HTRANS_NONSEQ = 2'b10, 53 | HTRANS_SEQ = 2'b11; 54 | 55 | //HSIZE 56 | parameter [2:0] HSIZE_B8 = 3'b000, 57 | HSIZE_B16 = 3'b001, 58 | HSIZE_B32 = 3'b010, 59 | HSIZE_B64 = 3'b011, 60 | HSIZE_B128 = 3'b100, //4-word line 61 | HSIZE_B256 = 3'b101, //8-word line 62 | HSIZE_B512 = 3'b110, 63 | HSIZE_B1024 = 3'b111, 64 | HSIZE_BYTE = HSIZE_B8, 65 | HSIZE_HWORD = HSIZE_B16, 66 | HSIZE_WORD = HSIZE_B32, 67 | HSIZE_DWORD = HSIZE_B64; 68 | 69 | //HBURST 70 | parameter [2:0] HBURST_SINGLE = 3'b000, 71 | HBURST_INCR = 3'b001, 72 | HBURST_WRAP4 = 3'b010, 73 | HBURST_INCR4 = 3'b011, 74 | HBURST_WRAP8 = 3'b100, 75 | HBURST_INCR8 = 3'b101, 76 | HBURST_WRAP16 = 3'b110, 77 | HBURST_INCR16 = 3'b111; 78 | 79 | //HPROT 80 | parameter [3:0] HPROT_OPCODE = 4'b0000, 81 | HPROT_DATA = 4'b0001, 82 | HPROT_USER = 4'b0000, 83 | HPROT_PRIVILEGED = 4'b0010, 84 | HPROT_NON_BUFFERABLE = 4'b0000, 85 | HPROT_BUFFERABLE = 4'b0100, 86 | HPROT_NON_CACHEABLE = 4'b0000, 87 | HPROT_CACHEABLE = 4'b1000; 88 | 89 | //HRESP 90 | parameter HRESP_OKAY = 1'b0, 91 | HRESP_ERROR = 1'b1; 92 | 93 | endpackage 94 | 95 | 96 | 97 | /************************************************ 98 | * AHB3 Lite Interface 99 | */ 100 | `ifndef AHB3_INTERFACES 101 | `define AHB3_INTERFACES 102 | interface ahb3lite_bus #( 103 | parameter HADDR_SIZE = 32, 104 | parameter HDATA_SIZE = 32 105 | ) 106 | ( 107 | input logic HCLK,HRESETn 108 | ); 109 | logic HSEL; 110 | logic [HADDR_SIZE -1:0] HADDR; 111 | logic [HDATA_SIZE -1:0] HWDATA; 112 | logic [HDATA_SIZE -1:0] HRDATA; 113 | logic HWRITE; 114 | logic [ 2:0] HSIZE; 115 | logic [ 3:0] HBURST; 116 | logic [ 3:0] HPROT; 117 | logic [ 1:0] HTRANS; 118 | logic HMASTLOCK; 119 | logic HREADY; 120 | logic HREADYOUT; 121 | logic HRESP; 122 | 123 | `ifdef SIM 124 | // Master CB Interface Definitions 125 | clocking cb_master @(posedge HCLK); 126 | output HSEL; 127 | output HADDR; 128 | output HWDATA; 129 | input HRDATA; 130 | output HWRITE; 131 | output HSIZE; 132 | output HBURST; 133 | output HPROT; 134 | output HTRANS; 135 | output HMASTLOCK; 136 | input HREADY; 137 | input HRESP; 138 | endclocking 139 | 140 | modport master_cb ( 141 | clocking cb_master, 142 | input HRESETn 143 | ); 144 | 145 | // Slave Interface Definitions 146 | clocking cb_slave @(posedge HCLK); 147 | input HSEL; 148 | input HADDR; 149 | input HWDATA; 150 | output HRDATA; 151 | input HWRITE; 152 | input HSIZE; 153 | input HBURST; 154 | input HPROT; 155 | input HTRANS; 156 | input HMASTLOCK; 157 | input HREADY; 158 | output HREADYOUT; 159 | output HRESP; 160 | endclocking 161 | 162 | modport slave_cb ( 163 | clocking cb_slave, 164 | input HRESETn 165 | ); 166 | `endif 167 | 168 | modport master ( 169 | input HRESETn, 170 | input HCLK, 171 | output HSEL, 172 | output HADDR, 173 | output HWDATA, 174 | input HRDATA, 175 | output HWRITE, 176 | output HSIZE, 177 | output HBURST, 178 | output HPROT, 179 | output HTRANS, 180 | output HMASTLOCK, 181 | input HREADY, 182 | input HRESP 183 | ); 184 | 185 | modport slave ( 186 | input HRESETn, 187 | input HCLK, 188 | input HSEL, 189 | input HADDR, 190 | input HWDATA, 191 | output HRDATA, 192 | input HWRITE, 193 | input HSIZE, 194 | input HBURST, 195 | input HPROT, 196 | input HTRANS, 197 | input HMASTLOCK, 198 | input HREADY, 199 | output HREADYOUT, 200 | output HRESP 201 | ); 202 | endinterface 203 | 204 | 205 | /************************************************ 206 | * APB Lite Interface 207 | */ 208 | interface apb_bus #( 209 | parameter PADDR_SIZE = 6, 210 | parameter PDATA_SIZE = 8 211 | ) 212 | ( 213 | input logic PCLK,PRESETn 214 | ); 215 | logic PSEL; 216 | logic PENABLE; 217 | logic [ 2:0] PPROT; 218 | logic PWRITE; 219 | logic [PDATA_SIZE/8-1:0] PSTRB; 220 | logic [PADDR_SIZE -1:0] PADDR; 221 | logic [PDATA_SIZE -1:0] PWDATA; 222 | logic [PDATA_SIZE -1:0] PRDATA; 223 | logic PREADY; 224 | logic PSLVERR; 225 | 226 | modport master ( 227 | input PRESETn, 228 | input PCLK, 229 | output PSEL, 230 | output PENABLE, 231 | output PPROT, 232 | output PADDR, 233 | output PWRITE, 234 | output PSTRB, 235 | output PWDATA, 236 | input PRDATA, 237 | input PREADY, 238 | input PSLVERR 239 | ); 240 | 241 | modport slave ( 242 | import is_read, is_write, 243 | 244 | input PRESETn, 245 | input PCLK, 246 | input PSEL, 247 | input PENABLE, 248 | input PPROT, 249 | input PADDR, 250 | input PWRITE, 251 | input PSTRB, 252 | input PWDATA, 253 | output PRDATA, 254 | output PREADY, 255 | output PSLVERR 256 | ); 257 | 258 | //Is this a valid read access? 259 | function automatic is_read(); 260 | return PSEL & PENABLE & ~PWRITE; 261 | endfunction 262 | 263 | //Is this a valid write access? 264 | function automatic is_write(); 265 | return PSEL & PENABLE & PWRITE; 266 | endfunction 267 | 268 | //Is this a valid write to address 0x...? 269 | //Take 'address' as an argument 270 | function automatic is_write_to_adr(input integer bits, input [PADDR_SIZE-1:0] address); 271 | logic [$bits(PADDR)-1:0] mask; 272 | 273 | mask = -1 >> ($bits(PADDR) -bits); //only 'bits' LSBs should be '1' 274 | return is_write() & ( (PADDR & mask) == (address & mask) ); 275 | endfunction 276 | 277 | //What data is written? 278 | //- Handles PSTRB, takes previous register/data value as an argument 279 | function automatic [PDATA_SIZE-1:0] get_write_value (input [PDATA_SIZE-1:0] orig_val); 280 | for (int n=0; n < PDATA_SIZE/8; n++) 281 | get_write_value[n*8 +: 8] = PSTRB[n] ? PWDATA[n*8 +: 8] : orig_val[n*8 +: 8]; 282 | endfunction 283 | 284 | 285 | //Is this the 'setup' phase of the transfer? 286 | function automatic is_setup_phase(); 287 | return PSEL & ~PENABLE; 288 | endfunction 289 | 290 | 291 | //Negate PREADY, Negate PSLVERR 292 | task set_not_ready(); 293 | PREADY = 1'b0; 294 | PSLVERR = 1'b0; 295 | endtask 296 | 297 | //Assert PREADY, Negate PSLVERR 298 | task set_ready(); 299 | PREADY = 1'b1; 300 | PSLVERR = 1'b0; 301 | endtask 302 | 303 | //Assert PREADY, Assert PSLVERR 304 | task set_error(); 305 | PREADY = 1'b1; 306 | PSLVERR = 1'b1; 307 | endtask 308 | endinterface 309 | `endif 310 | -------------------------------------------------------------------------------- /APB/apb4_gpio/README.md: -------------------------------------------------------------------------------- 1 | # apb4_gpio 2 | Fully parameterized APB4 General-Purpose-IO 3 | 4 |

Functionality

5 | Configurable General Purpose IO with an APB4 interface 6 | -------------------------------------------------------------------------------- /APB/apb4_gpio/rtl/verilog/LICENSE.txt: -------------------------------------------------------------------------------- 1 | PLEASE CAREFULLY REVIEW THE FOLLOWING TERMS AND CONDITIONS BEFORE DOWNLOADING 2 | AND USING THE LICENSED MATERIALS. 3 | THIS LICENSE AGREEMENT ("AGREEMENT") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER 4 | A SINGLE INDIVIDUAL, OR A SINGLE LEGAL ENTITY)("YOU") AND ROA LOGIC BV ("ROA 5 | LOGIC") COVERING THE PRODUCTS OR SERVICES YOU PURCHASE FROM ROA LOGIC. 6 | 7 | By downloading and/or using or installing products from Roa Logic you 8 | automatically agree to and are bound by the terms and conditions of this 9 | agreement. 10 | 11 | PLEASE NOTE THAT THIS AGREEMENT IS INTENDED FOR NON-COMMERCIAL USE OF THE 12 | PRODUCT. IF YOU INTENT TO USE ROA LOGIC PRODUCTS FOR COMMERCIAL PURPOSES, 13 | THEN PLEASE CONTACT info@roalogic.com TO ARRANGE AN AGREEMENT WITH US BASED 14 | ON OUR COMMERCIAL LICENSE TERMS 15 | 16 | 17 | 1. DEFINITIONS 18 | 1.1. "Intellectual Property" means any or all of the following and all rights 19 | in, arising out of, or associated with: 20 | 1.1.1. all inventions (whether patentable or not), invention disclosures, 21 | improvements, trade secrets, proprietary information, know how, 22 | technology, algorithms, techniques, methods, devices, technical data, 23 | customer lists, and all documentation embodying or evidencing any of 24 | the foregoing; 25 | 1.1.2. all computer software, source codes, object codes, firmware, 26 | development tools, files, records, data, and all media on which any of 27 | the foregoing is recorded 28 | 29 | 1.2. "Product" means an Intellectual Property block consisting of, but not 30 | limited to, Verilog, VHDL, and/or SystemVerilog design files, 31 | specifications, block diagrams and documentation. 32 | 33 | 1.3. "Physical Implementation" means any implementation in programmable or 34 | non-programmable technologies including, but not limited to Field 35 | Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices 36 | (CPLDs), Application Specific Integrated Circuits (ASICs), Application 37 | Specific Standard Products (ASSPs) 38 | 39 | 1.4. "Silicon Device(s)" means any customer Physical Implementation containing 40 | a unique part number. 41 | 42 | 1.5. "You" the opposite contract party as referred to in article 6:231, 43 | subsection c, of the Dutch Civil Code, being the party to whom an offer 44 | is made by Roa Logic, or with whom an agreement is concluded by Roa Logic, 45 | or to whom the Product is supplied. 46 | 47 | 48 | 2. LICENSE TO USE. 49 | 2.1. Roa Logic hereby grants you a limited, non-exclusive, non-transferable, 50 | no-charge, and royalty-free copyright license to use, modify, and 51 | distribute the Product provided you do so for non-commercial (personal, 52 | educational, research and development, demonstration) purposes. 53 | Specifically you are allowed to: 54 | 2.1.1. use the Product in your design to create, simulate, implement, 55 | manufacture, and use a Silicon Device provided you don't do so to make 56 | a profit; 57 | 2.1.2. distribute the Product, provided the original disclaimer and copyright 58 | notice are retained and this Agreement is part of the distribution. 59 | 2.2. Roa Logic hereby grants limited, non-exclusive, non-transferable, 60 | no-charge, and royalty-free patent license to use, modify, and 61 | distribute the Product provided you do so for non-commercial (personal, 62 | educational, research and development, demonstration) purposes, where 63 | such license only applies to those patent claims licensable by Roa Logic. 64 | 65 | 66 | 3. OWNERSHIP 67 | 3.1. The Product, its documentation, and any associated material is owned by 68 | Roa Logic and is protected by copyright and other intellectual property 69 | right laws. 70 | 3.2. Any modification or addition to the Product, documentation, and any 71 | associated materials or derivatives thereof, that You intentionally 72 | submit to Roa Logic for inclusion in the Product will become part of the 73 | Product and thus owned and copyrighted by Roa Logic. By submitting any 74 | material for inclusion you wave any ownership, copyright, and patent 75 | rights and claims for the use of the submitted material in the Product. 76 | "Submitting" means any form of electronic, verbal, or written 77 | communication sent to Roa Logic or its representatives, including, but 78 | not limited to, email, mailing lists, source repositories, and issue 79 | tracking systems for the purpose of discussing and improving the Product 80 | 3.3. You shall not remove any copyright, disclaimers, or other notices from 81 | any parts of the Product. 82 | 83 | 84 | 4. RIGHT OF EQUITABLE RELIEF 85 | You acknowledge and agree that violation of this agreement may cause 86 | Roa Logic irreparable injury for which an adequate remedy at law may not be 87 | available. 88 | Therefore Roa Logic shall be entitled to seek all remedies that may be 89 | available under equity, including immediate injunctive relief, in addition 90 | to whatever remedies may be available at law. 91 | 92 | 93 | 5. DISCLAIMER OF WARRANTY 94 | The Product is provided “AS IS”. Roa Logic has no obligation to provide 95 | maintenance or support services in connection with the Product. 96 | ROA LOGIC DISCLAIMS ALL WARRANTIES, CONDITONS AND REPRESENTATIONS, EXPRESS, 97 | IMPLIED, OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, THOSE RELATED TO 98 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, SATISFACTORY QUALITY, 99 | ACCURACY OR COMPLETENESS OR RESULTS, CONFORMANCE WITH DESCRIPTION, AND 100 | NON-INFRINGEMENT. 101 | 102 | 103 | 6. LIMITATION OF LIABILITY 104 | TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL ROA LOGIC OR 105 | YOU BE LIABLE TO THE OTHER OR ANY THIRD PARTY FOR ANY INDIRECT, SPECIAL, 106 | CONSEQUENTIAL OR INCIDENTAL DAMAGES WHATSOEVER (INCLUDING, BUT NOT 107 | LIMITED TO, DAMAGES FOR LOSS OF PROFIT, BUSINESS INTERRUPTIONS OR LOSS 108 | OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT 109 | WHETHER BASED ON A CLAIM UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, 110 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 111 | 112 | 113 | 7. EXPORT RESTRICTIONS 114 | The Product may be subject to U.S. or E.U. export laws and may be subject to 115 | export or import regulations in other countries. You agree to comply fully 116 | with all laws and regulations of the United States, European Union, and 117 | other countries to ensure that the product is not: 118 | - exported directly, or indirectly, in violation of export laws; 119 | - intended to be used for any purposes prohibited by export laws, including, 120 | but not limited to, nuclear, chemical, or biological weapons proliferation. 121 | 122 | 123 | 8. APPLICABLE LAW AND CHOICE OF FORUM 124 | 8.1. All agreements and contracts between you and Roa Logic, which these 125 | conditions are applicable to, shall be governed by Dutch law with the 126 | exclusion of the uniform UN Convention on Contracts for the 127 | International Sale of Goods (CISG) and other bilateral or multilateral 128 | treaties for the purpose of unifying international sales. 129 | 8.2. The competent courts in the district where Roa Logic has its registered 130 | office in the Netherlands has jurisdiction over all disputes concerning 131 | rights and obligations associated with the contractual relations. 132 | 8.3. Conversion 133 | If any clause or sentence of this agreement is held by a court of law to 134 | be illegal or unenforceable, the remaining provisions of the agreement 135 | remain in effect. The failure of Roa Logic to enforce any of the 136 | provisions in the agreement does not constitute a waiver of Roa Logic's 137 | rights to enforce any provision of the agreement in the future. 138 | 139 | -------------------------------------------------------------------------------- /APB/apb4_gpio/rtl/verilog/apb_gpio.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // APB GPIO // 17 | // // 18 | ///////////////////////////////////////////////////////////////// 19 | // // 20 | // Copyright (C) 2016-2017 ROA Logic BV // 21 | // www.roalogic.com // 22 | // // 23 | // Unless specifically agreed in writing, this software is // 24 | // licensed under the RoaLogic Non-Commercial License // 25 | // version-1.0 (the "License"), a copy of which is included // 26 | // with this file or may be found on the RoaLogic website // 27 | // http://www.roalogic.com. You may not use the file except // 28 | // in compliance with the License. // 29 | // // 30 | // THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY // 31 | // EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. // 32 | // See the License for permissions and limitations under the // 33 | // License. // 34 | // // 35 | ///////////////////////////////////////////////////////////////// 36 | 37 | 38 | /* 39 | * address description comment 40 | * 0x0 mode register 0=push-pull 41 | * 1=open-drain 42 | * 0x1 direction register 0=input 43 | * 1=output 44 | * 0x2 output register mode-register=0? 0=drive pad low 45 | * 1=drive pad high 46 | * mode-register=1? 0=drive pad low 47 | * 1=open-drain 48 | * 0x3 input register returns data at pad 49 | */ 50 | 51 | module apb_gpio #( 52 | PDATA_SIZE = 8 53 | ) 54 | ( 55 | input PRESETn, 56 | PCLK, 57 | input PSEL, 58 | input PENABLE, 59 | input [ 2:0] PADDR, 60 | input PWRITE, 61 | input [PDATA_SIZE/8-1:0] PSTRB, 62 | input [PDATA_SIZE -1:0] PWDATA, 63 | output reg [PDATA_SIZE -1:0] PRDATA, 64 | output PREADY, 65 | output PSLVERR, 66 | 67 | input [PDATA_SIZE -1:0] gpio_i, 68 | output reg [PDATA_SIZE -1:0] gpio_o, 69 | gpio_oe 70 | ); 71 | ////////////////////////////////////////////////////////////////// 72 | // 73 | // Constants 74 | // 75 | import ahb3lite_pkg::*; 76 | 77 | localparam PADDR_SIZE = 3; 78 | 79 | 80 | localparam MODE = 0, 81 | DIRECTION = 1, 82 | OUTPUT = 2, 83 | INPUT = 3, 84 | IOC = 4, //Interrupt-on-change 85 | IPENDING = 5; //Interrupt-pending 86 | 87 | 88 | //number of synchronisation flipflop stages on GPIO inputs 89 | localparam INPUT_STAGES = 3; 90 | 91 | 92 | ////////////////////////////////////////////////////////////////// 93 | // 94 | // Variables 95 | // 96 | 97 | //Control registers 98 | logic [PDATA_SIZE-1:0] mode_reg; 99 | logic [PDATA_SIZE-1:0] dir_reg; 100 | logic [PDATA_SIZE-1:0] out_reg; 101 | logic [PDATA_SIZE-1:0] in_reg; 102 | 103 | 104 | //Input register, to prevent metastability 105 | logic [PDATA_SIZE-1:0] input_regs [INPUT_STAGES]; 106 | 107 | integer n; 108 | 109 | 110 | ////////////////////////////////////////////////////////////////// 111 | // 112 | // Functions 113 | // 114 | 115 | //Is this a valid read access? 116 | function automatic is_read(); 117 | return PSEL & PENABLE & ~PWRITE; 118 | endfunction 119 | 120 | //Is this a valid write access? 121 | function automatic is_write(); 122 | return PSEL & PENABLE & PWRITE; 123 | endfunction 124 | 125 | //Is this a valid write to address 0x...? 126 | //Take 'address' as an argument 127 | function automatic is_write_to_adr(input integer bits, input [PADDR_SIZE-1:0] address); 128 | logic [$bits(PADDR)-1:0] mask; 129 | 130 | mask = (1 << bits) -1; //only 'bits' LSBs should be '1' 131 | return is_write() & ( (PADDR & mask) == (address & mask) ); 132 | endfunction 133 | 134 | //What data is written? 135 | //- Handles PSTRB, takes previous register/data value as an argument 136 | function automatic [PDATA_SIZE-1:0] get_write_value (input [PDATA_SIZE-1:0] orig_val); 137 | for (int n=0; n < PDATA_SIZE/8; n++) 138 | get_write_value[n*8 +: 8] = PSTRB[n] ? PWDATA[n*8 +: 8] : orig_val[n*8 +: 8]; 139 | endfunction 140 | 141 | 142 | ////////////////////////////////////////////////////////////////// 143 | // 144 | // Module Body 145 | // 146 | 147 | /* 148 | * APB accesses 149 | */ 150 | //The core supports zero-wait state accesses on all transfers. 151 | //It is allowed to driver PREADY with a steady signal 152 | assign PREADY = 1'b1; //always ready 153 | assign PSLVERR = 1'b0; //Never an error 154 | 155 | 156 | /* 157 | * APB Writes 158 | */ 159 | //APB write to Mode register 160 | always @(posedge PCLK,negedge PRESETn) 161 | if (!PRESETn ) mode_reg <= 'h0; 162 | else if ( is_write_to_adr(2,MODE)) mode_reg <= get_write_value(mode_reg); 163 | 164 | 165 | //APB write to Direction register 166 | always @(posedge PCLK,negedge PRESETn) 167 | if (!PRESETn ) dir_reg <= 'h0; 168 | else if ( is_write_to_adr(2,DIRECTION)) dir_reg <= get_write_value(dir_reg); 169 | 170 | 171 | //APB write to Output register 172 | //treat writes to Input register same 173 | always @(posedge PCLK,negedge PRESETn) 174 | if (!PRESETn ) out_reg <= 'h0; 175 | else if ( is_write_to_adr(2,OUTPUT) || 176 | is_write_to_adr(2,INPUT ) ) out_reg <= get_write_value(out_reg); 177 | 178 | 179 | /* 180 | * APB Reads 181 | */ 182 | always @(posedge PCLK) 183 | case (PADDR[1:0]) 184 | MODE : PRDATA <= mode_reg; 185 | DIRECTION: PRDATA <= dir_reg; 186 | OUTPUT : PRDATA <= out_reg; 187 | INPUT : PRDATA <= in_reg; 188 | endcase 189 | 190 | 191 | /* 192 | * Internals 193 | */ 194 | always @(posedge PCLK) 195 | for (n=0; nFunctionality 5 | The APB4 Mux enables a single APB4 Master to communicate with multiple APB4 slaves (peripherals). 6 | -------------------------------------------------------------------------------- /APB/apb4_mux/rtl/verilog/LICENSE.txt: -------------------------------------------------------------------------------- 1 | PLEASE CAREFULLY REVIEW THE FOLLOWING TERMS AND CONDITIONS BEFORE DOWNLOADING 2 | AND USING THE LICENSED MATERIALS. 3 | THIS LICENSE AGREEMENT ("AGREEMENT") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER 4 | A SINGLE INDIVIDUAL, OR A SINGLE LEGAL ENTITY)("YOU") AND ROA LOGIC BV ("ROA 5 | LOGIC") COVERING THE PRODUCTS OR SERVICES YOU PURCHASE FROM ROA LOGIC. 6 | 7 | By downloading and/or using or installing products from Roa Logic you 8 | automatically agree to and are bound by the terms and conditions of this 9 | agreement. 10 | 11 | PLEASE NOTE THAT THIS AGREEMENT IS INTENDED FOR NON-COMMERCIAL USE OF THE 12 | PRODUCT. IF YOU INTENT TO USE ROA LOGIC PRODUCTS FOR COMMERCIAL PURPOSES, 13 | THEN PLEASE CONTACT info@roalogic.com TO ARRANGE AN AGREEMENT WITH US BASED 14 | ON OUR COMMERCIAL LICENSE TERMS 15 | 16 | 17 | 1. DEFINITIONS 18 | 1.1. "Intellectual Property" means any or all of the following and all rights 19 | in, arising out of, or associated with: 20 | 1.1.1. all inventions (whether patentable or not), invention disclosures, 21 | improvements, trade secrets, proprietary information, know how, 22 | technology, algorithms, techniques, methods, devices, technical data, 23 | customer lists, and all documentation embodying or evidencing any of 24 | the foregoing; 25 | 1.1.2. all computer software, source codes, object codes, firmware, 26 | development tools, files, records, data, and all media on which any of 27 | the foregoing is recorded 28 | 29 | 1.2. "Product" means an Intellectual Property block consisting of, but not 30 | limited to, Verilog, VHDL, and/or SystemVerilog design files, 31 | specifications, block diagrams and documentation. 32 | 33 | 1.3. "Physical Implementation" means any implementation in programmable or 34 | non-programmable technologies including, but not limited to Field 35 | Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices 36 | (CPLDs), Application Specific Integrated Circuits (ASICs), Application 37 | Specific Standard Products (ASSPs) 38 | 39 | 1.4. "Silicon Device(s)" means any customer Physical Implementation containing 40 | a unique part number. 41 | 42 | 1.5. "You" the opposite contract party as referred to in article 6:231, 43 | subsection c, of the Dutch Civil Code, being the party to whom an offer 44 | is made by Roa Logic, or with whom an agreement is concluded by Roa Logic, 45 | or to whom the Product is supplied. 46 | 47 | 48 | 2. LICENSE TO USE. 49 | 2.1. Roa Logic hereby grants you a limited, non-exclusive, non-transferable, 50 | no-charge, and royalty-free copyright license to use, modify, and 51 | distribute the Product provided you do so for non-commercial (personal, 52 | educational, research and development, demonstration) purposes. 53 | Specifically you are allowed to: 54 | 2.1.1. use the Product in your design to create, simulate, implement, 55 | manufacture, and use a Silicon Device provided you don't do so to make 56 | a profit; 57 | 2.1.2. distribute the Product, provided the original disclaimer and copyright 58 | notice are retained and this Agreement is part of the distribution. 59 | 2.2. Roa Logic hereby grants limited, non-exclusive, non-transferable, 60 | no-charge, and royalty-free patent license to use, modify, and 61 | distribute the Product provided you do so for non-commercial (personal, 62 | educational, research and development, demonstration) purposes, where 63 | such license only applies to those patent claims licensable by Roa Logic. 64 | 65 | 66 | 3. OWNERSHIP 67 | 3.1. The Product, its documentation, and any associated material is owned by 68 | Roa Logic and is protected by copyright and other intellectual property 69 | right laws. 70 | 3.2. Any modification or addition to the Product, documentation, and any 71 | associated materials or derivatives thereof, that You intentionally 72 | submit to Roa Logic for inclusion in the Product will become part of the 73 | Product and thus owned and copyrighted by Roa Logic. By submitting any 74 | material for inclusion you wave any ownership, copyright, and patent 75 | rights and claims for the use of the submitted material in the Product. 76 | "Submitting" means any form of electronic, verbal, or written 77 | communication sent to Roa Logic or its representatives, including, but 78 | not limited to, email, mailing lists, source repositories, and issue 79 | tracking systems for the purpose of discussing and improving the Product 80 | 3.3. You shall not remove any copyright, disclaimers, or other notices from 81 | any parts of the Product. 82 | 83 | 84 | 4. RIGHT OF EQUITABLE RELIEF 85 | You acknowledge and agree that violation of this agreement may cause 86 | Roa Logic irreparable injury for which an adequate remedy at law may not be 87 | available. 88 | Therefore Roa Logic shall be entitled to seek all remedies that may be 89 | available under equity, including immediate injunctive relief, in addition 90 | to whatever remedies may be available at law. 91 | 92 | 93 | 5. DISCLAIMER OF WARRANTY 94 | The Product is provided “AS IS”. Roa Logic has no obligation to provide 95 | maintenance or support services in connection with the Product. 96 | ROA LOGIC DISCLAIMS ALL WARRANTIES, CONDITONS AND REPRESENTATIONS, EXPRESS, 97 | IMPLIED, OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, THOSE RELATED TO 98 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, SATISFACTORY QUALITY, 99 | ACCURACY OR COMPLETENESS OR RESULTS, CONFORMANCE WITH DESCRIPTION, AND 100 | NON-INFRINGEMENT. 101 | 102 | 103 | 6. LIMITATION OF LIABILITY 104 | TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL ROA LOGIC OR 105 | YOU BE LIABLE TO THE OTHER OR ANY THIRD PARTY FOR ANY INDIRECT, SPECIAL, 106 | CONSEQUENTIAL OR INCIDENTAL DAMAGES WHATSOEVER (INCLUDING, BUT NOT 107 | LIMITED TO, DAMAGES FOR LOSS OF PROFIT, BUSINESS INTERRUPTIONS OR LOSS 108 | OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT 109 | WHETHER BASED ON A CLAIM UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, 110 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 111 | 112 | 113 | 7. EXPORT RESTRICTIONS 114 | The Product may be subject to U.S. or E.U. export laws and may be subject to 115 | export or import regulations in other countries. You agree to comply fully 116 | with all laws and regulations of the United States, European Union, and 117 | other countries to ensure that the product is not: 118 | - exported directly, or indirectly, in violation of export laws; 119 | - intended to be used for any purposes prohibited by export laws, including, 120 | but not limited to, nuclear, chemical, or biological weapons proliferation. 121 | 122 | 123 | 8. APPLICABLE LAW AND CHOICE OF FORUM 124 | 8.1. All agreements and contracts between you and Roa Logic, which these 125 | conditions are applicable to, shall be governed by Dutch law with the 126 | exclusion of the uniform UN Convention on Contracts for the 127 | International Sale of Goods (CISG) and other bilateral or multilateral 128 | treaties for the purpose of unifying international sales. 129 | 8.2. The competent courts in the district where Roa Logic has its registered 130 | office in the Netherlands has jurisdiction over all disputes concerning 131 | rights and obligations associated with the contractual relations. 132 | 8.3. Conversion 133 | If any clause or sentence of this agreement is held by a court of law to 134 | be illegal or unenforceable, the remaining provisions of the agreement 135 | remain in effect. The failure of Roa Logic to enforce any of the 136 | provisions in the agreement does not constitute a waiver of Roa Logic's 137 | rights to enforce any provision of the agreement in the future. 138 | 139 | -------------------------------------------------------------------------------- /APB/apb4_mux/rtl/verilog/apb_mux.sv: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////// 2 | // // 3 | // ██████╗ ██████╗ █████╗ // 4 | // ██╔══██╗██╔═══██╗██╔══██╗ // 5 | // ██████╔╝██║ ██║███████║ // 6 | // ██╔══██╗██║ ██║██╔══██║ // 7 | // ██║ ██║╚██████╔╝██║ ██║ // 8 | // ╚═╝ ╚═╝ ╚═════╝ ╚═╝ ╚═╝ // 9 | // ██╗ ██████╗ ██████╗ ██╗ ██████╗ // 10 | // ██║ ██╔═══██╗██╔════╝ ██║██╔════╝ // 11 | // ██║ ██║ ██║██║ ███╗██║██║ // 12 | // ██║ ██║ ██║██║ ██║██║██║ // 13 | // ███████╗╚██████╔╝╚██████╔╝██║╚██████╗ // 14 | // ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═════╝ // 15 | // // 16 | // APB Mux - Allows multiple slaves on one APB bus // 17 | // Generates slave PSELs // 18 | // Decodes PREADY, PSLVERR, PRDATA // 19 | // // 20 | ///////////////////////////////////////////////////////////////// 21 | // // 22 | // Copyright (C) 2016-2017 ROA Logic BV // 23 | // www.roalogic.com // 24 | // // 25 | // Unless specifically agreed in writing, this software is // 26 | // licensed under the RoaLogic Non-Commercial License // 27 | // version-1.0 (the "License"), a copy of which is included // 28 | // with this file or may be found on the RoaLogic website // 29 | // http://www.roalogic.com. You may not use the file except // 30 | // in compliance with the License. // 31 | // // 32 | // THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY // 33 | // EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. // 34 | // See the License for permissions and limitations under the // 35 | // License. // 36 | // // 37 | ///////////////////////////////////////////////////////////////// 38 | 39 | 40 | module apb_mux #( 41 | parameter PADDR_SIZE = 8, 42 | PDATA_SIZE = 8, 43 | SLAVES = 8 44 | ) 45 | ( 46 | //Common signals 47 | input PRESETn, 48 | PCLK, 49 | 50 | //To/From APB master 51 | input MST_PSEL, 52 | input [PADDR_SIZE-1:0] MST_PADDR, //MSBs of address bus 53 | output [PDATA_SIZE-1:0] MST_PRDATA, 54 | output MST_PREADY, 55 | output MST_PSLVERR, 56 | 57 | //To/from APB slaves 58 | input [PADDR_SIZE-1:0] slv_addr [SLAVES], //address compare for each slave 59 | input [PADDR_SIZE-1:0] slv_mask [SLAVES], 60 | output SLV_PSEL [SLAVES], 61 | input [PDATA_SIZE-1:0] SLV_PRDATA [SLAVES], 62 | input SLV_PREADY [SLAVES], 63 | input SLV_PSLVERR[SLAVES] 64 | ); 65 | ////////////////////////////////////////////////////////////////// 66 | // 67 | // Constants 68 | // 69 | import ahb3lite_pkg::*; 70 | 71 | 72 | ////////////////////////////////////////////////////////////////// 73 | // 74 | // Variables 75 | // 76 | logic [SLAVES-1:0][PDATA_SIZE-1:0] prdata; 77 | logic [SLAVES-1:0] pready; 78 | logic [SLAVES-1:0] pslverr; 79 | 80 | logic [PDATA_SIZE-1:0][SLAVES-1:0] prdata_switched; 81 | 82 | 83 | genvar s,b; 84 | 85 | 86 | ////////////////////////////////////////////////////////////////// 87 | // 88 | // Module Body 89 | // 90 | generate 91 | for (s=0;s