├── BUILD ├── vivado ├── files.tcl ├── constraints.tcl ├── basic_create_bitstream.tcl ├── BUILD ├── basic_place.tcl ├── basic_place_optimize.tcl ├── basic_optimize.tcl ├── basic_synthesis.tcl ├── basic_route.tcl └── rules.bzl ├── WORKSPACE ├── .gitignore ├── clash ├── BUILD.clash ├── BUILD └── rules.bzl ├── README.md └── LICENSE /BUILD: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /vivado/files.tcl: -------------------------------------------------------------------------------- 1 | {LOAD_FILES} 2 | -------------------------------------------------------------------------------- /vivado/constraints.tcl: -------------------------------------------------------------------------------- 1 | {LOAD_XDC} 2 | -------------------------------------------------------------------------------- /WORKSPACE: -------------------------------------------------------------------------------- 1 | workspace(name = "fpga_rules") 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bazel-bin 2 | bazel-out 3 | bazel-fpga-rules 4 | bazel-testlogs 5 | *.swp 6 | -------------------------------------------------------------------------------- /clash/BUILD.clash: -------------------------------------------------------------------------------- 1 | exports_files( 2 | glob(["**/*"], allow_empty = False) 3 | ) 4 | 5 | package(default_visibility = ["//visibility:public"]) 6 | 7 | filegroup( 8 | name = "files", 9 | srcs = glob(["**/*"], allow_empty = False) 10 | ) 11 | -------------------------------------------------------------------------------- /vivado/basic_create_bitstream.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | set PROJ_NAME {PROJECT_NAME} 4 | set PROJ_DIR {BASE_DIR} 5 | 6 | set_param general.maxThreads 8 7 | open_checkpoint {CHECKPOINT} 8 | 9 | #write_debug_probes -force $PROJ_DIR/${PROJ_NAME}.ltx 10 | write_bitstream -force $PROJ_DIR/${PROJ_NAME}.bit -bin_file 11 | -------------------------------------------------------------------------------- /vivado/BUILD: -------------------------------------------------------------------------------- 1 | exports_files([ 2 | "basic_create_bitstream.tcl", 3 | "basic_synthesis.tcl", 4 | "basic_optimize.tcl", 5 | "basic_place.tcl", 6 | "basic_place_optimize.tcl", 7 | "basic_route.tcl", 8 | "constraints.tcl", 9 | "files.tcl", 10 | ]) 11 | 12 | package(default_visibility = ["//visibility:public"]) 13 | 14 | -------------------------------------------------------------------------------- /vivado/basic_place.tcl: -------------------------------------------------------------------------------- 1 | 2 | set PROJ_NAME {PROJECT_NAME} 3 | set PROJ_DIR {BASE_DIR} 4 | 5 | set_param general.maxThreads 8 6 | open_checkpoint {CHECKPOINT} 7 | 8 | place_design -directive Explore 9 | report_timing_summary -file $PROJ_DIR/${PROJ_NAME}.rpt 10 | report_utilization -file $PROJ_DIR/${PROJ_NAME}.rpt 11 | write_checkpoint -force $PROJ_DIR/${PROJ_NAME}.dcp 12 | -------------------------------------------------------------------------------- /vivado/basic_place_optimize.tcl: -------------------------------------------------------------------------------- 1 | 2 | set PROJ_NAME {PROJECT_NAME} 3 | set PROJ_DIR {BASE_DIR} 4 | 5 | set_param general.maxThreads 8 6 | open_checkpoint {CHECKPOINT} 7 | 8 | phys_opt_design -directive AggressiveExplore 9 | report_timing_summary -file $PROJ_DIR/${PROJ_NAME}.rpt 10 | report_utilization -file $PROJ_DIR/${PROJ_NAME}.rpt 11 | write_checkpoint -force $PROJ_DIR/${PROJ_NAME}.dcp 12 | -------------------------------------------------------------------------------- /clash/BUILD: -------------------------------------------------------------------------------- 1 | load(":rules.bzl", "compile_clash_toolchain") 2 | 3 | package(default_visibility = ["//visibility:public"]) 4 | 5 | toolchain_type(name = "toolchain_type") 6 | 7 | compile_clash_toolchain( 8 | name = "clash_toolchain_impl", 9 | ) 10 | 11 | toolchain( 12 | name = "toolchain", 13 | toolchain = "clash_toolchain_impl", 14 | toolchain_type = "//clash:toolchain_type", 15 | ) 16 | -------------------------------------------------------------------------------- /vivado/basic_optimize.tcl: -------------------------------------------------------------------------------- 1 | 2 | set PROJ_NAME {PROJECT_NAME} 3 | set PROJ_DIR {BASE_DIR} 4 | 5 | set_param general.maxThreads 8 6 | open_checkpoint {CHECKPOINT} 7 | 8 | opt_design -directive Explore 9 | report_timing_summary -file $PROJ_DIR/${PROJ_NAME}_timing.rpt 10 | report_utilization -file $PROJ_DIR/${PROJ_NAME}_utilization.rpt 11 | write_checkpoint -force $PROJ_DIR/${PROJ_NAME}.dcp 12 | ## Upgrade DSP connection warnings (like "Invalid PCIN Connection for OPMODE value") to 13 | ## an error because this is an error post route 14 | set_property SEVERITY {ERROR} [get_drc_checks DSPS-*] 15 | ## Run DRC on opt design to catch early issues like comb loops 16 | report_drc -file $PROJ_DIR/${PROJ_NAME}.rpt 17 | 18 | -------------------------------------------------------------------------------- /vivado/basic_synthesis.tcl: -------------------------------------------------------------------------------- 1 | 2 | ####################################################################################### 3 | # User Settings 4 | ####################################################################################### 5 | 6 | # global settings 7 | set PROJ_NAME {PROJECT_NAME} 8 | set PROJ_DIR {BASE_DIR} 9 | set PART_NAME {PART_NAME} 10 | set TOP_MODULE {TOP_MODULE} 11 | 12 | # synthesis related settings 13 | set SYNTH_ARGS "" 14 | {SYNTH_ARGS} 15 | 16 | set_part $PART_NAME 17 | 18 | source {FILES_TCL} 19 | source {CONSTRAINTS_TCL} 20 | ## Synthesize Design 21 | set_param general.maxThreads 8 22 | eval "synth_design $SYNTH_ARGS -top $TOP_MODULE -part $PART_NAME" 23 | report_timing_summary -file $PROJ_DIR/${PROJ_NAME}.rpt 24 | report_utilization -file $PROJ_DIR/${PROJ_NAME}.rpt 25 | write_checkpoint -force $PROJ_DIR/${PROJ_NAME}.dcp 26 | -------------------------------------------------------------------------------- /vivado/basic_route.tcl: -------------------------------------------------------------------------------- 1 | 2 | set PROJ_NAME {PROJECT_NAME} 3 | set PROJ_DIR {BASE_DIR} 4 | 5 | set_param general.maxThreads 8 6 | open_checkpoint {CHECKPOINT} 7 | 8 | route_design -directive Explore 9 | report_timing_summary -file $PROJ_DIR/${PROJ_NAME}_timings.rpt 10 | report_utilization -hierarchical -file $PROJ_DIR/${PROJ_NAME}_utilization.rpt 11 | report_route_status -file $PROJ_DIR/${PROJ_NAME}_status.rpt 12 | report_io -file $PROJ_DIR/${PROJ_NAME}_io.rpt 13 | report_power -file $PROJ_DIR/${PROJ_NAME}_power.rpt 14 | report_design_analysis -logic_level_distribution \ 15 | -of_timing_paths [get_timing_paths -max_paths 10000 \ 16 | -slack_lesser_than 0] \ 17 | -file $PROJ_DIR/${PROJ_NAME}_vios.rpt 18 | write_checkpoint -force $PROJ_DIR/${PROJ_NAME}_post_route.dcp 19 | 20 | set WNS [get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] 21 | puts "Post Route WNS = $WNS" 22 | 23 | write_checkpoint -force $PROJ_DIR/${PROJ_NAME}.dcp 24 | -------------------------------------------------------------------------------- /clash/rules.bzl: -------------------------------------------------------------------------------- 1 | load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") 2 | load("@bazel_tools//tools/build_defs/repo:git.bzl", "git_repository") 3 | 4 | ClashInfo = provider( 5 | doc = "Information on the clash compiler", 6 | fields = ["clash_path"] 7 | ) 8 | 9 | def _clash_toolchain_impl(ctx): 10 | toolchain_info = platform_common.ToolchainInfo( 11 | clash_info = ClashInfo( 12 | clash_path = ctx.attr.clash_path 13 | ) 14 | ) 15 | 16 | return [toolchain_info] 17 | 18 | clash_toolchain = rule( 19 | implementation = _clash_toolchain_impl, 20 | attrs = { 21 | "clash_path": attr.label(allow_single_file = True) 22 | } 23 | ) 24 | 25 | def _compile_clash_toolchain_impl(ctx): 26 | output = ctx.actions.declare_file("horse") 27 | 28 | args = ctx.actions.args() 29 | 30 | args.add_all([ 31 | ctx.file._shell_nix 32 | ]) 33 | 34 | ctx.actions.run_shell( 35 | command = "nix-shell --run $1", 36 | arguments = [args], 37 | inputs = ctx.files._srcs, 38 | outputs = [ output ], 39 | use_default_shell_env = True, 40 | ) 41 | 42 | toolchain_info = platform_common.ToolchainInfo( 43 | clash_info = ClashInfo( 44 | clash_path = output 45 | ), 46 | ) 47 | 48 | return [toolchain_info] 49 | 50 | compile_clash_toolchain = rule( 51 | implementation = _compile_clash_toolchain_impl, 52 | attrs = { 53 | "_shell_nix": attr.label(allow_single_file = True, default = "@clash_repo//:shell.nix"), 54 | "_srcs": attr.label_list(allow_files = True, default = ["@clash_repo//:files"]) 55 | } 56 | ) 57 | 58 | def _clash_to_vhdl_impl(ctx): 59 | outputs = [] 60 | 61 | for output in ctx.attr.outputs: 62 | outputs += [ctx.actions.declare_file(output)] 63 | 64 | args = ctx.actions.args() 65 | 66 | args.add_all([ 67 | ctx.file.top_entity, 68 | ctx.genfiles_dir.path 69 | ]) 70 | 71 | ctx.actions.run_shell( 72 | command = "clash --vhdl $1 -outputdir $2", 73 | arguments = [args], 74 | inputs = ctx.files.srcs + [ctx.file.top_entity], 75 | outputs = outputs, 76 | use_default_shell_env = True, 77 | ) 78 | 79 | return [DefaultInfo(files = depset(outputs))] 80 | 81 | clash_to_vhdl = rule( 82 | implementation = _clash_to_vhdl_impl, 83 | attrs = { 84 | "srcs": attr.label_list(allow_files = [".hs"]), 85 | "outputs": attr.string_list(allow_empty = False), 86 | "top_entity": attr.label(allow_single_file = [".hs"]), 87 | #"_clash_shell": attr.label(allow_single_file = True, default = "@clash_repo//:shell.nix") 88 | }, 89 | toolchains = ["@fpga_rules//clash:toolchain_type"] 90 | ) 91 | 92 | def _clash_to_verilog_impl(ctx): 93 | outputs = [] 94 | 95 | for output in ctx.attr.outputs: 96 | outputs += [ctx.actions.declare_file(output)] 97 | 98 | args = ctx.actions.args() 99 | 100 | args.add_all([ 101 | ctx.file.top_entity, 102 | ctx.genfiles_dir.path 103 | ]) 104 | 105 | ctx.actions.run_shell( 106 | command = "clash --verilog $1 -outputdir $2", 107 | arguments = [args], 108 | inputs = ctx.files.srcs + [ctx.file.top_entity], 109 | outputs = outputs, 110 | use_default_shell_env = True, 111 | ) 112 | 113 | return [DefaultInfo(files = depset(outputs))] 114 | 115 | clash_to_verilog = rule( 116 | implementation = _clash_to_verilog_impl, 117 | attrs = { 118 | "srcs": attr.label_list(allow_files = [".hs"]), 119 | "outputs": attr.string_list(allow_empty = False), 120 | "top_entity": attr.label(allow_single_file = [".hs"]), 121 | #"_clash_shell": attr.label(allow_single_file = True, default = "@clash_repo//:shell.nix") 122 | }, 123 | toolchains = ["@fpga_rules//clash:toolchain_type"] 124 | ) 125 | 126 | def load_clash_deps(): 127 | http_archive( 128 | name = "clash_repo", 129 | urls = ["https://github.com/clash-lang/clash-compiler/archive/1.2.tar.gz"], 130 | build_file = "@fpga_rules//clash:BUILD.clash", 131 | strip_prefix = "clash-compiler-1.2" 132 | ) 133 | 134 | native.register_toolchains( 135 | "@fpga_rules//clash:toolchain" 136 | ) 137 | 138 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA Rules for Bazel 2 | Why is turning vhdl and verilog into a bitstream so hard? Development in this space in encumbered by proprietary tooling not built for integration into build systems. You generally have two options: 3 | 1) Create project files full of magic that nobody really wants that do all of the steps for you. These are generally tied to a proprietary IDE and aren't portable at all. I really just want to use VSCode or vim. 4 | 2) Write tcl scripts, invoking arcane commands you scry from an 1800 page reference manual in a very particular order. Again, not portable, but at least you can break the process into stages and control it from outside the tool. 5 | 6 | These Bazel rules seek to ameliorate these woes by generating tcl scripts that do the one fucking thing you want with an FPGA: turn my HDL and constraints into a bitstream so you can download it onto your FPGA and make some lights blink. 7 | 8 | ## Vivado rules 9 | `vivado.bzl` provides Bazel rules to turn HDL into a bitstrean that you can download to your FPGA. 10 | 11 | To synthesize, map, place, route, and generate a bitstream from your constraints (.xdc files) and HDL (Verilog and/or VHDL), simply use the `fpga_bitsream` rule: 12 | 13 | ``` 14 | fpga_bitstream( 15 | name = "blinkenlights", 16 | srcs = [ 17 | "vhdl/BlinkenLights/topentity.vhdl", 18 | "vhdl/BlinkenLights/blinkenlights_types.vhdl" 19 | ], 20 | part = "xc7z020clg400-1", 21 | constraints = [ 22 | "const.xdc" 23 | ], 24 | topEntity = "topEntity", 25 | optimize = False 26 | ) 27 | ``` 28 | 29 | You can also compose these rules as you see fit and write your own synthesis rules that interop. `fpga_bitstream` internally invokes the `synthesize`, `optimize` (if optimize eq True), `place`, `place_optimize` (if optimize eq True) , `route`, and `create_bitstrem` rules chained in a linear sequence. Each stage of the workflow generates a tcl file from a template and loads and/or writes a checkpoint. So long as your rule emits a checkpoint as its only output, the `optmize`, `place`, `place_optimize`, `route`, and `create_bitstream` rules should be able to consume the results of your rule. 30 | 31 | ## Requirements 32 | I tested these rules in Debian with Windows Subsystem for Linux. If they work in this exotic setup, they'll almost certainly work on any Linux distro with Vivado installed. 33 | 34 | 1. Install Vivado to /tools/Xilinx (the default location on Linux). Future work to inject toolchains will allow other setups. 35 | 2. Take a dependency on these rules in your Bazel `WORKSPACE` file. Probably a `git_repository` rule. 36 | 3. Add the following to your .bazelrc file (preferably, the .bazelrc in your enlistment): 37 | `` 38 | build --action_env=HOME 39 | `` 40 | Vivado looks for random crap in your home directory and path concatenation will fail if you don't do this. 41 | 42 | ### WSL 43 | Installing Vivado on WSL requires an X11 server. However, running startx fails in WSL for me, so I had to install VcXsrv. 44 | 1. Install [VcXsrv](http://vcxsrv.sourceforge) in the host Windows OS. 45 | 2. I couldn't get the cable driver to work in WSL. To work around this, install Vivado Lab Edition on the host Windows environment. 46 | 47 | ### Notes 48 | * The Bazel rules right now hard-code the 2019.2 release of Vivado. I plan to fix this in the future using Bazeal macros to create toolchain definitions. 49 | 50 | ## Downloading a bitstream 51 | 1. Start `hw_server` in a terminal. By default, this is under `/tools/Xilinx/2019.2/bin` On WSL, do this in the host Windows OS (By default, in `C:\Xilinx\Vivado\2019.2\bin`). 52 | 2. Put the following tcl commands into a connect_hw_server.tcl 53 | ``` 54 | # Connect to the Digilent Cable on localhost:3121 55 | open_hw_manager 56 | connect_hw_server -url localhost:3121 57 | current_hw_target [get_hw_targets] 58 | open_hw_target 59 | ``` 60 | 3. Put the more tcl commands into another tcl script called program_device.tcl: 61 | ``` 62 | # Program and Refresh the Device 63 | current_hw_device [lindex [get_hw_devices] 1] 64 | refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 1] 65 | set_property PROGRAM.FILE {bazel-bin/blinkenlights_bitstream.bit} [lindex [get_hw_devices] 1] 66 | program_hw_devices [lindex [get_hw_devices] 1] 67 | refresh_hw_device [lindex [get_hw_devices] 1] 68 | ``` 69 | 4. Start Vivdo in tcl mode `vivado -mode tcl` 70 | 5. Run `source connect_hw_server.tcl`. This takes a while, so you will probably want to keep this vivado session open while you work. 71 | 6. Each time you want to download to the board, run `source program_device.tcl`. 72 | 73 | ### Notes 74 | The commands above are specific to the Digilent Zybo Z7-10 board with the Xilinx XC7Z010-1CLG400C-1 FPGA. This FPGA features an ARM Cortex and an FPGA in a SoC package. The 0th device is the ARM processor, and 1st device is the FPGA. Hence, the `1` in all the [lindex [get_hw_devices] 1] calls. 75 | 76 | Your FPGA is probably different. To find the device number you want, start Vivado in tcl mode, `source connect_hw_server.tcl`, then run `get_hw_devices`. This will give you list of things you can program on your FPGA. Change the 1 to i where i is the ith device `get_hw_devices` returns. 77 | 78 | ## Acknowlegements 79 | These rules internally generate tcl scripts from a template and call `vivado -mode batch gen.tcl`. The [Hardware Jedi](https://hwjedi.wordpress.com/2017/01/29/vivado-non-project-mode-part-ii-building-off-a-solid-foundation/) provides an excellent guide on how to not use projects in Vivado. These rules generate what is effectively templated tcl broken into stages from derived from this guide. 80 | 81 | ## Quartus 82 | I don't have an Altera FPGA, so no rules for you. 83 | 84 | ## Symbiflow 85 | TODO. 86 | -------------------------------------------------------------------------------- /vivado/rules.bzl: -------------------------------------------------------------------------------- 1 | 2 | def _synthesize(ctx): 3 | files_tcl_content = "" 4 | 5 | for file in ctx.files.srcs: 6 | if file.extension == "v" or file.extension == "vh": 7 | files_tcl_content += "read_verilog " + file.path + "\n" 8 | elif file.extension == "vhd" or file.extension == "vhdl": 9 | files_tcl_content += "read_vhdl " + file.path + "\n" 10 | elif file.extension == "xci": 11 | files_tcl_content += "read_ip " + file.path + "\n" 12 | else: 13 | fail("Unknown HDL file:" + file.path) 14 | 15 | files_tcl = ctx.actions.declare_file(ctx.attr.name + "_files.tcl") 16 | 17 | ctx.actions.expand_template( 18 | template = ctx.file._files_tcl_template, 19 | output = files_tcl, 20 | substitutions = { 21 | "{LOAD_FILES}": files_tcl_content 22 | } 23 | ) 24 | 25 | constraints_tcl_content = "" 26 | 27 | for file in ctx.files.constraints: 28 | constraints_tcl_content += "read_xdc " + file.path + "\n" 29 | 30 | constraints_tcl = ctx.actions.declare_file(ctx.attr.name + "_contraints.tcl") 31 | 32 | ctx.actions.expand_template( 33 | template = ctx.file._constraints_template, 34 | output = constraints_tcl, 35 | substitutions = { 36 | "{LOAD_XDC}": constraints_tcl_content 37 | } 38 | ) 39 | 40 | build_tcl = ctx.actions.declare_file(ctx.attr.name + "_synthesis.tcl") 41 | 42 | synth_args = "" 43 | 44 | for arg in ctx.attr.synth_args: 45 | synth_args += "append" + arg 46 | 47 | ctx.actions.expand_template( 48 | template = ctx.file.build_template, 49 | output = build_tcl, 50 | substitutions = { 51 | "{PROJECT_NAME}": ctx.attr.name, 52 | "{PART_NAME}": ctx.attr.part, 53 | "{FILES_TCL}": files_tcl.path, 54 | "{CONSTRAINTS_TCL}": constraints_tcl.path, 55 | "{TOP_MODULE}": ctx.attr.topEntity, 56 | "{SYNTH_ARGS}": synth_args, 57 | "{BASE_DIR}": ctx.genfiles_dir.path 58 | } 59 | ) 60 | 61 | vivado_inputs = ctx.files.srcs + ctx.files.constraints + [ 62 | files_tcl, 63 | constraints_tcl, 64 | build_tcl 65 | ] 66 | 67 | checkpoint = ctx.actions.declare_file(ctx.attr.name + ".dcp") 68 | 69 | log_file = ctx.actions.declare_file(ctx.attr.name + ".log") 70 | journal_file = ctx.actions.declare_file(ctx.attr.name + ".jou") 71 | 72 | args = ctx.actions.args() 73 | 74 | args.add_all([ 75 | build_tcl, 76 | log_file, 77 | journal_file 78 | ]) 79 | 80 | ctx.actions.run_shell( 81 | command = "/tools/Xilinx/Vivado/2019.2/bin/vivado -mode batch -source $1 -log $2 -journal $3", 82 | arguments = [args], 83 | inputs = vivado_inputs, 84 | outputs = [ checkpoint, log_file, journal_file ], 85 | progress_message = "vivado_synthesis", 86 | use_default_shell_env = True, 87 | ) 88 | 89 | return [DefaultInfo(files = depset( 90 | [checkpoint] 91 | ))] 92 | 93 | synthesize = rule( 94 | implementation = _synthesize, 95 | attrs = { 96 | "srcs": attr.label_list(allow_files = [ ".v", "vh", ".vhd", ".vhdl", "xci" ]), 97 | "constraints": attr.label_list(allow_files = [".xdc"]), 98 | "topEntity": attr.string(), 99 | "part": attr.string(), 100 | "_files_tcl_template": attr.label( allow_single_file = True, default = Label("//vivado:files.tcl")), 101 | "_constraints_template": attr.label( allow_single_file = True, default = Label("//vivado:constraints.tcl")), 102 | "build_template": attr.label( allow_single_file = True, default = Label("//vivado:basic_synthesis.tcl")), 103 | "synth_args": attr.string_list(allow_empty = True, default = []), 104 | }, 105 | ) 106 | 107 | def _run_tcl_from_checkpoint_impl(ctx): 108 | tcl = ctx.actions.declare_file(ctx.file.build_template.basename + ".tcl") 109 | 110 | ctx.actions.expand_template( 111 | template = ctx.file.build_template, 112 | output = tcl, 113 | substitutions = { 114 | "{PROJECT_NAME}": ctx.attr.name, 115 | "{BASE_DIR}": ctx.genfiles_dir.path, 116 | "{CHECKPOINT}": ctx.file.checkpoint.path 117 | } 118 | ) 119 | 120 | args = ctx.actions.args() 121 | 122 | log_file = ctx.actions.declare_file(ctx.attr.name + ".log") 123 | journal_file = ctx.actions.declare_file(ctx.attr.name + ".jou") 124 | 125 | args.add_all([ 126 | tcl, 127 | log_file, 128 | journal_file, 129 | ]) 130 | 131 | output = ctx.actions.declare_file(ctx.attr.name + ".dcp") 132 | 133 | ctx.actions.run_shell( 134 | command = "/tools/Xilinx/Vivado/2019.2/bin/vivado -mode batch -source $1 -log $2 -journal $3", 135 | arguments = [args], 136 | inputs = [ctx.file.checkpoint, tcl], 137 | outputs = [ output, log_file, journal_file ], 138 | progress_message = "vivado_run_tcl " + tcl.basename, 139 | use_default_shell_env = True, 140 | ) 141 | 142 | return [DefaultInfo(files = depset([ 143 | output 144 | ]))] 145 | 146 | optimize_design = rule( 147 | implementation = _run_tcl_from_checkpoint_impl, 148 | attrs = { 149 | "checkpoint": attr.label(allow_single_file = [".dcp"]), 150 | "build_template": attr.label(allow_single_file = True, default = "//vivado:basic_optimize.tcl" ), 151 | } 152 | ) 153 | 154 | place = rule( 155 | implementation = _run_tcl_from_checkpoint_impl, 156 | attrs = { 157 | "checkpoint": attr.label(allow_single_file = [".dcp"]), 158 | "build_template": attr.label(allow_single_file = True, default = "//vivado:basic_place.tcl" ), 159 | } 160 | ) 161 | 162 | place_optimize = rule( 163 | implementation = _run_tcl_from_checkpoint_impl, 164 | attrs = { 165 | "checkpoint": attr.label(allow_single_file = [".dcp"]), 166 | "build_template": attr.label(allow_single_file = True, default = "//vivado:basic_place_optimize.tcl" ), 167 | } 168 | ) 169 | 170 | route = rule( 171 | implementation = _run_tcl_from_checkpoint_impl, 172 | attrs = { 173 | "checkpoint": attr.label(allow_single_file = [".dcp"]), 174 | "build_template": attr.label(allow_single_file = True, default = "//vivado:basic_route.tcl" ), 175 | } 176 | ) 177 | 178 | def _run_tcl_template(ctx): 179 | tcl = ctx.actions.declare_file(ctx.file.build_template.basename + ".tcl") 180 | 181 | ctx.actions.expand_template( 182 | template = ctx.file.build_template, 183 | output = tcl, 184 | substitutions = { 185 | "{PROJECT_NAME}": ctx.attr.name, 186 | "{BASE_DIR}": ctx.genfiles_dir.path, 187 | } 188 | ) 189 | 190 | args = ctx.actions.args() 191 | 192 | log_file = ctx.actions.declare_file(ctx.attr.name + ".log") 193 | journal_file = ctx.actions.declare_file(ctx.attr.name + ".jou") 194 | 195 | args.add_all([ 196 | tcl, 197 | log_file, 198 | journal_file, 199 | ]) 200 | 201 | outputs = [] 202 | 203 | for out in ctx.attr.outs: 204 | outputs += [ctx.actions.declare_file(out)] 205 | 206 | ctx.actions.run_shell( 207 | command = "/tools/Xilinx/Vivado/2019.2/bin/vivado -mode batch -source $1 -log $2 -journal $3", 208 | arguments = [args], 209 | inputs = [tcl], 210 | outputs = outputs + [ log_file, journal_file ], 211 | progress_message = "vivado_run_tcl " + tcl.basename, 212 | use_default_shell_env = True, 213 | ) 214 | 215 | return [DefaultInfo(files = depset( 216 | outputs 217 | ))] 218 | 219 | 220 | run_tcl_template = rule( 221 | implementation = _run_tcl_template, 222 | attrs = { 223 | "build_template": attr.label(allow_single_file = True), 224 | "outs": attr.string_list(allow_empty = False) 225 | } 226 | ) 227 | 228 | def _create_bitstream_impl(ctx): 229 | tcl = ctx.actions.declare_file(ctx.file.build_template.basename + ".tcl") 230 | 231 | ctx.actions.expand_template( 232 | template = ctx.file.build_template, 233 | output = tcl, 234 | substitutions = { 235 | "{PROJECT_NAME}": ctx.attr.name, 236 | "{BASE_DIR}": ctx.genfiles_dir.path, 237 | "{CHECKPOINT}": ctx.file.checkpoint.path 238 | } 239 | ) 240 | 241 | args = ctx.actions.args() 242 | 243 | log_file = ctx.actions.declare_file(ctx.attr.name + ".log") 244 | journal_file = ctx.actions.declare_file(ctx.attr.name + ".jou") 245 | 246 | args.add_all([ 247 | tcl, 248 | log_file, 249 | journal_file, 250 | ]) 251 | 252 | bitstream = ctx.actions.declare_file(ctx.attr.name + ".bit") 253 | #debug_probes = ctx.actions.declare_file(ctx.attr.name + ".ltx") 254 | 255 | ctx.actions.run_shell( 256 | command = "/tools/Xilinx/Vivado/2019.2/bin/vivado -mode batch -source $1 -log $2 -journal $3", 257 | arguments = [args], 258 | inputs = [ctx.file.checkpoint, tcl], 259 | outputs = [ 260 | bitstream, 261 | #debug_probes, 262 | log_file, 263 | journal_file 264 | ], 265 | progress_message = "vivado_run_tcl " + tcl.basename, 266 | use_default_shell_env = True, 267 | ) 268 | 269 | return [DefaultInfo(files = depset([ 270 | bitstream, 271 | #debug_probes 272 | ]))] 273 | 274 | create_bitstream = rule( 275 | implementation = _create_bitstream_impl, 276 | attrs = { 277 | "checkpoint": attr.label(allow_single_file = [".dcp"]), 278 | "build_template": attr.label(allow_single_file = True, default = "//vivado:basic_create_bitstream.tcl" ), 279 | } 280 | ) 281 | 282 | # Takes verilog and/or vhdl source files and generates a bitstream. 283 | def fpga_bitstream( 284 | name, 285 | srcs, 286 | constraints, 287 | part, 288 | topEntity, 289 | optimize = True, 290 | ): 291 | 292 | synthesize( 293 | name = name + "_synthesis", 294 | srcs = srcs, 295 | part = part, 296 | constraints = constraints, 297 | topEntity = topEntity, 298 | ) 299 | 300 | if optimize: 301 | optimize_design( 302 | name = name + "_optimize", 303 | checkpoint = ":" + name + "_synthesis" 304 | ) 305 | place_checkpoint = ":" + name + "_optimize" 306 | else: 307 | place_checkpoint = ":" + name + "_synthesis" 308 | 309 | place( 310 | name = name + "_place", 311 | checkpoint = place_checkpoint 312 | ) 313 | 314 | if optimize: 315 | place_optimize( 316 | name = name + "_place_optimize", 317 | checkpoint = ":" + name + "_place", 318 | ) 319 | route_checkpoint = ":" + name + "_place_optimize" 320 | else: 321 | route_checkpoint = ":" + name + "_place" 322 | 323 | route( 324 | name = name + "_route", 325 | checkpoint = route_checkpoint, 326 | ) 327 | 328 | create_bitstream( 329 | name = name + "_bitstream", 330 | checkpoint = ":" + name + "_route", 331 | ) 332 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | {one line to give the program's name and a brief idea of what it does.} 635 | Copyright (C) {year} {name of author} 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | {project} Copyright (C) {year} {fullname} 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | --------------------------------------------------------------------------------