├── .gitignore ├── README.md ├── build.sh ├── config └── diffconfig ├── overlay ├── package │ ├── base-files │ │ └── files │ │ │ └── lib │ │ │ └── functions │ │ │ ├── leds.sh │ │ │ └── system.sh │ └── firmware │ │ └── ipq-wifi │ │ ├── Makefile │ │ └── board-meraki_mr33.bin └── target │ └── linux │ └── ipq806x │ ├── base-files │ ├── etc │ │ ├── board.d │ │ │ └── 02_network │ │ └── hotplug.d │ │ │ └── firmware │ │ │ └── 11-ath10k-caldata │ └── lib │ │ ├── preinit │ │ └── 05_set_iface_mac_ipq806x.sh │ │ └── upgrade │ │ ├── merakinand.sh │ │ └── platform.sh │ ├── config-4.9 │ ├── files-4.9 │ └── arch │ │ └── arm │ │ └── boot │ │ └── dts │ │ └── qcom-ipq4029-mr33.dts │ ├── image │ └── Makefile │ └── patches-4.9 │ ├── 0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch │ ├── 0069-arm-boot-add-dts-files.patch │ ├── 131-pinctrl-qcom-ipq4019-add-remaining-pin-definitions.patch │ ├── 132-pinctrl-qcom-add-support-to-configure-ipq40xx-GPIO_P.patch │ ├── 712-mr33-essedma.patch │ ├── 855-clk-qcom-ipq4019-add-ess-reset.patch │ ├── 857-ipq40xx-Fix-mdio-driver-to-work-with-IPQ40xx-SoC.patch │ ├── 900-ipq4019-pcie-dts-nodes.patch │ └── 901-ipq4019-pcie.patch └── remove-files /.gitignore: -------------------------------------------------------------------------------- 1 | openwrt/ 2 | lede/ 3 | *.DS_Store 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # LEDE-MR33 2 | Bringup for the Cisco Meraki MR33 Access Point on LEDE! 3 | 4 | Currently based on commit [74beb6f7104e7d5003adc061e0df8016484a6730](https://github.com/openwrt/openwrt/commit/74beb6f7104e7d5003adc061e0df8016484a6730) 5 | 6 | And the following cherry picks: 7 | * https://patchwork.ozlabs.org/patch/752962/ for switch defines (pinctl part merged upstream) 8 | * https://git.lede-project.org/?p=lede/blogic/staging.git;a=commit;h=af81e7775f99b82933101f9bc5b6d83decc37fa4 for PCI-E Wireless 9 | * https://patchwork.ozlabs.org/patch/774684/ for 2nd i2c interface 10 | 11 | Building 12 | ----- 13 | #### Build Only 14 | `./build.sh` 15 | 16 | #### Modify Configs and Build 17 | `./build.sh modify` 18 | 19 | Note that you will need to run a modify on the first compile to select the ipq806x target, MR33 device in the LEDE menuconfig. 20 | 21 | Booting & Flashing 22 | ----- 23 | Booting and flashing documentation can be found on [Google Drive](https://drive.google.com/drive/folders/1jJa8LzYnY830v3nBZdOgAk0YQK6OdbSS) 24 | 25 | To Do 26 | ----- 27 | ##### MR33 28 | * Writeup flashing/booting process 29 | 30 | Working 31 | ----- 32 | ##### MR33 33 | * NAND 34 | * Bluetooth - See this [Commit](https://github.com/riptidewave93/LEDE-MR33/commit/43ca7f34e0437ef9384fc38f1c4de6a843f1dd98). 35 | * SoC Wireless 36 | * PCIe Wireless 37 | * Ethernet (IGMP and tagged VLAN might need further testing) 38 | * LED's/GPIOs 39 | * Reset button 40 | * Serial (It's TTL-232R-3V3 with 115200-N-8-1) 41 | * System Integration 42 | * Kernel Device Profile 43 | * SysUpgrade 44 | 45 | Notice 46 | ------ 47 | No promises this won't brick your unit, and no promises that this will even work! 48 | 49 | Hello Cisco/Meraki, please send me free stuff! 50 | -------------------------------------------------------------------------------- /build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | firstbuild=0 4 | clonedir=./openwrt 5 | cpu_num=$(grep -c processor /proc/cpuinfo) 6 | 7 | # Print messages in cyan blue 8 | Msg() { 9 | echo -e "\e[96m$1\e[39m" 10 | } 11 | 12 | # Do we want menuconfig's and an option to save configs? 13 | if [ "$1" = "modify" ]; then 14 | modify=1 15 | else 16 | modify=0 17 | fi 18 | 19 | Msg "Starting Build Process!" 20 | 21 | if [ ! -d "$clonedir" ]; then 22 | firstbuild=1 23 | Msg "Cloning Repo..." 24 | git clone https://github.com/openwrt/openwrt $clonedir 25 | cd $clonedir 26 | git reset --hard 74beb6f7104e7d5003adc061e0df8016484a6730 27 | cd - > /dev/null 28 | fi 29 | 30 | if [ "$firstbuild" -eq "1" ] && [ -d "./patches" ]; then 31 | Msg "Applying Patches..." 32 | cd $clonedir 33 | for patch in ../patches/*.patch 34 | do 35 | Msg "Applying $patch" 36 | git apply $patch 37 | done 38 | cd - > /dev/null 39 | fi 40 | 41 | if [ "$firstbuild" -eq "0" ]; then 42 | Msg "Cleaning Builddir..." 43 | cd $clonedir 44 | rm -rf ./bin 45 | make clean 46 | cd - > /dev/null 47 | fi 48 | 49 | Msg "Applying overlay..." 50 | cp -R ./overlay/* $clonedir/ 51 | 52 | if [ -r "remove-files" ]; then 53 | Msg "Removing unwanted files from overlay..." 54 | for victim in $(cat remove-files); do 55 | [ -r "$clonedir/$victim" ] && rm -r "$clonedir/$victim" 56 | done 57 | fi 58 | 59 | if [ "$firstbuild" -eq "1" ]; then 60 | Msg "Installing feeds..." 61 | cd $clonedir 62 | ./scripts/feeds update -a 63 | ./scripts/feeds install -a 64 | if [ -f "../config/diffconfig" ]; then 65 | Msg "Applying and Expanding config..." 66 | cp ../config/diffconfig ./.config 67 | make defconfig 68 | fi 69 | cd - > /dev/null 70 | fi 71 | 72 | if [ "$modify" -eq "1" ]; then 73 | cd $clonedir 74 | Msg "Loading Menuconfig" 75 | make menuconfig -j$cpu_num V=s 76 | cd - > /dev/null 77 | fi 78 | 79 | Msg "Building Time!!!" 80 | cd $clonedir 81 | make -j$cpu_num V=s 82 | 83 | if [ $? -ne 0 ]; then 84 | cd - > /dev/null 85 | Msg "Build Failed!" 86 | exit 1 87 | else 88 | cd - > /dev/null 89 | Msg "Compile Complete!" 90 | fi 91 | 92 | Msg "Build.sh Finished!" 93 | -------------------------------------------------------------------------------- /config/diffconfig: -------------------------------------------------------------------------------- 1 | CONFIG_TARGET_ipq806x=y 2 | CONFIG_TARGET_ipq806x_DEVICE_meraki_mr33=y 3 | CONFIG_TARGET_BOARD="ipq806x" 4 | CONFIG_ETHTOOL_PRETTY_DUMP=y 5 | CONFIG_OPENSSL_WITH_DEPRECATED=y 6 | CONFIG_OPENSSL_WITH_EC=y 7 | CONFIG_OPENSSL_WITH_NPN=y 8 | CONFIG_OPENSSL_WITH_PSK=y 9 | CONFIG_OPENSSL_WITH_SRP=y 10 | CONFIG_PACKAGE_ethtool=y 11 | CONFIG_PACKAGE_libiwinfo-lua=y 12 | CONFIG_PACKAGE_liblua=y 13 | CONFIG_PACKAGE_libopenssl=y 14 | CONFIG_PACKAGE_libubus-lua=y 15 | CONFIG_PACKAGE_libuci-lua=y 16 | CONFIG_PACKAGE_libunwind=y 17 | CONFIG_PACKAGE_libustream-openssl=y 18 | CONFIG_PACKAGE_lua=y 19 | CONFIG_PACKAGE_luci=y 20 | CONFIG_PACKAGE_luci-app-firewall=y 21 | CONFIG_PACKAGE_luci-base=y 22 | CONFIG_PACKAGE_luci-lib-ip=y 23 | CONFIG_PACKAGE_luci-lib-jsonc=y 24 | CONFIG_PACKAGE_luci-lib-nixio=y 25 | CONFIG_PACKAGE_luci-mod-admin-full=y 26 | CONFIG_PACKAGE_luci-proto-ipv6=y 27 | CONFIG_PACKAGE_luci-proto-ppp=y 28 | CONFIG_PACKAGE_luci-ssl-openssl=y 29 | CONFIG_PACKAGE_luci-theme-bootstrap=y 30 | CONFIG_PACKAGE_openssl-util=y 31 | CONFIG_PACKAGE_rpcd=y 32 | CONFIG_PACKAGE_uhttpd=y 33 | CONFIG_PACKAGE_uhttpd-mod-ubus=y 34 | CONFIG_PKG_ASLR_PIE=y 35 | CONFIG_TARGET_INITRAMFS_COMPRESSION_LZMA=y 36 | CONFIG_TARGET_ROOTFS_INITRAMFS=y 37 | -------------------------------------------------------------------------------- /overlay/package/base-files/files/lib/functions/leds.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Copyright (C) 2013 OpenWrt.org 3 | 4 | get_dt_led() { 5 | local label 6 | local ledpath 7 | local basepath="/proc/device-tree" 8 | local nodepath="$basepath/aliases/led-$1" 9 | 10 | [ -f "$nodepath" ] && ledpath=$(cat "$nodepath") 11 | [ -n "$ledpath" ] && \ 12 | label=$(cat "$basepath$ledpath/label" 2>/dev/null) || \ 13 | label=$(cat "$basepath$ledpath/chan-name" 2>/dev/null) || \ 14 | echo "led label not found" 1>&2 15 | 16 | echo "$label" 17 | } 18 | 19 | led_set_attr() { 20 | [ -f "/sys/class/leds/$1/$2" ] && echo "$3" > "/sys/class/leds/$1/$2" 21 | } 22 | 23 | led_timer() { 24 | led_set_attr $1 "trigger" "timer" 25 | led_set_attr $1 "delay_on" "$2" 26 | led_set_attr $1 "delay_off" "$3" 27 | } 28 | 29 | led_on() { 30 | led_set_attr $1 "trigger" "none" 31 | led_set_attr $1 "brightness" 255 32 | } 33 | 34 | led_off() { 35 | led_set_attr $1 "trigger" "none" 36 | led_set_attr $1 "brightness" 0 37 | } 38 | 39 | status_led_set_timer() { 40 | led_timer $status_led "$1" "$2" 41 | [ -n "$status_led2" ] && led_timer $status_led2 "$1" "$2" 42 | } 43 | 44 | status_led_set_heartbeat() { 45 | led_set_attr $status_led "trigger" "heartbeat" 46 | } 47 | 48 | status_led_on() { 49 | led_on $status_led 50 | [ -n "$status_led2" ] && led_on $status_led2 51 | } 52 | 53 | status_led_off() { 54 | led_off $status_led 55 | [ -n "$status_led2" ] && led_off $status_led2 56 | } 57 | 58 | status_led_blink_slow() { 59 | led_timer $status_led 1000 1000 60 | } 61 | 62 | status_led_blink_fast() { 63 | led_timer $status_led 100 100 64 | } 65 | 66 | status_led_blink_preinit() { 67 | led_timer $status_led 100 100 68 | } 69 | 70 | status_led_blink_failsafe() { 71 | led_timer $status_led 50 50 72 | } 73 | 74 | status_led_blink_preinit_regular() { 75 | led_timer $status_led 200 200 76 | } 77 | -------------------------------------------------------------------------------- /overlay/package/base-files/files/lib/functions/system.sh: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2006-2013 OpenWrt.org 2 | 3 | get_mac_binary() { 4 | local path="$1" 5 | local offset="$2" 6 | 7 | if [ -z "$path" ]; then 8 | echo "get_mac_binary: file $path not found!" >&2 9 | return 10 | fi 11 | 12 | hexdump -v -n 6 -s $offset -e '5/1 "%02x:" 1/1 "%02x"' $path 2>/dev/null 13 | } 14 | 15 | find_mtd_chardev() { 16 | local INDEX=$(find_mtd_index "$1") 17 | local PREFIX=/dev/mtd 18 | 19 | [ -d /dev/mtd ] && PREFIX=/dev/mtd/ 20 | echo "${INDEX:+$PREFIX$INDEX}" 21 | } 22 | 23 | mtd_get_mac_ascii() 24 | { 25 | local mtdname="$1" 26 | local key="$2" 27 | local part 28 | local mac_dirty 29 | 30 | part=$(find_mtd_part "$mtdname") 31 | if [ -z "$part" ]; then 32 | echo "mtd_get_mac_ascii: partition $mtdname not found!" >&2 33 | return 34 | fi 35 | 36 | mac_dirty=$(strings "$part" | sed -n 's/^'"$key"'=//p') 37 | 38 | # "canonicalize" mac 39 | [ -n "$mac_dirty" ] && macaddr_canonicalize "$mac_dirty" 40 | } 41 | 42 | mtd_get_mac_binary() { 43 | local mtdname="$1" 44 | local offset="$2" 45 | local part 46 | 47 | part=$(find_mtd_part "$mtdname") 48 | get_mac_binary "$part" "$offset" 49 | } 50 | 51 | mtd_get_mac_binary_ubi() { 52 | local mtdname="$1" 53 | local offset="$2" 54 | 55 | . /lib/upgrade/nand.sh 56 | 57 | local ubidev=$(nand_find_ubi $CI_UBIPART) 58 | local part=$(nand_find_volume $ubidev $1) 59 | 60 | if [ -z "$part" ]; then 61 | echo "mtd_get_mac_binary: ubi volume $mtdname not found!" >&2 62 | return 63 | fi 64 | 65 | hexdump -v -n 6 -s $offset -e '5/1 "%02x:" 1/1 "%02x"' /dev/$part 2>/dev/null 66 | } 67 | 68 | mtd_get_part_size() { 69 | local part_name=$1 70 | local first dev size erasesize name 71 | while read dev size erasesize name; do 72 | name=${name#'"'}; name=${name%'"'} 73 | if [ "$name" = "$part_name" ]; then 74 | echo $((0x$size)) 75 | break 76 | fi 77 | done < /proc/mtd 78 | } 79 | 80 | macaddr_add() { 81 | local mac=$1 82 | local val=$2 83 | local oui=${mac%:*:*:*} 84 | local nic=${mac#*:*:*:} 85 | 86 | nic=$(printf "%06x" $((0x${nic//:/} + $val & 0xffffff)) | sed 's/^\(.\{2\}\)\(.\{2\}\)\(.\{2\}\)/\1:\2:\3/') 87 | echo $oui:$nic 88 | } 89 | 90 | macaddr_setbit_la() 91 | { 92 | local mac=$1 93 | 94 | printf "%02x:%s" $((0x${mac%%:*} | 0x02)) ${mac#*:} 95 | } 96 | 97 | macaddr_2bin() 98 | { 99 | local mac=$1 100 | 101 | echo -ne \\x${mac//:/\\x} 102 | } 103 | 104 | macaddr_canonicalize() 105 | { 106 | local mac="$1" 107 | local canon="" 108 | 109 | mac=$(echo -n $mac | tr -d \") 110 | [ ${#mac} -gt 17 ] && return 111 | [ -n "${mac//[a-fA-F0-9\.: -]/}" ] && return 112 | 113 | for octet in ${mac//[\.:-]/ }; do 114 | case "${#octet}" in 115 | 1) 116 | octet="0${octet}" 117 | ;; 118 | 2) 119 | ;; 120 | 4) 121 | octet="${octet:0:2} ${octet:2:2}" 122 | ;; 123 | 12) 124 | octet="${octet:0:2} ${octet:2:2} ${octet:4:2} ${octet:6:2} ${octet:8:2} ${octet:10:2}" 125 | ;; 126 | *) 127 | return 128 | ;; 129 | esac 130 | canon=${canon}${canon:+ }${octet} 131 | done 132 | 133 | [ ${#canon} -ne 17 ] && return 134 | 135 | printf "%02x:%02x:%02x:%02x:%02x:%02x" 0x${canon// / 0x} 2>/dev/null 136 | } 137 | -------------------------------------------------------------------------------- /overlay/package/firmware/ipq-wifi/Makefile: -------------------------------------------------------------------------------- 1 | include $(TOPDIR)/rules.mk 2 | include $(INCLUDE_DIR)/version.mk 3 | 4 | PKG_NAME:=ipq-wifi 5 | PKG_RELEASE:=1 6 | 7 | include $(INCLUDE_DIR)/package.mk 8 | 9 | define Build/Prepare 10 | mkdir -p $(PKG_BUILD_DIR) 11 | endef 12 | 13 | define Build/Compile 14 | endef 15 | 16 | ALLWIFIBOARDS:=avm_fritzbox-4040 openmesh_a42 meraki_mr33 17 | ALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ipq-wifi-$(BOARD)) 18 | 19 | define Package/ipq-wifi-default 20 | SUBMENU:=ath10k IPQ4019 Boarddata 21 | SECTION:=firmware 22 | CATEGORY:=Firmware 23 | DEPENDS:=@TARGET_ipq806x +ath10k-firmware-qca4019 24 | TITLE:=Custom Board 25 | endef 26 | 27 | define generate-ipq-wifi-package 28 | define Package/ipq-wifi-$(1) 29 | $(call Package/ipq-wifi-default) 30 | TITLE:=Board for $(3) 31 | CONFLICTS:=$(PREV_BOARD) 32 | endef 33 | 34 | define Package/ipq-wifi-$(1)/description 35 | This device custom package board-2.bin overwrites the board-2.bin 36 | file which is supplied by the ath10k-firmware-qca4019 package. 37 | 38 | This is package is only necessary for the $(3). 39 | Don't install it for any other device! 40 | endef 41 | 42 | define Package/ipq-wifi-$(1)/install-overlay 43 | $(INSTALL_DIR) $$(1)/lib/firmware/ath10k/QCA4019/hw1.0 44 | $(INSTALL_DATA) ./$(2) $$(1)/lib/firmware/ath10k/QCA4019/hw1.0/board-2.bin 45 | endef 46 | 47 | PREV_BOARD+=ipq-wifi-$(1) 48 | endef 49 | 50 | $(eval $(call generate-ipq-wifi-package,avm_fritzbox-4040,board-avm_fritzbox-4040.bin,AVM FRITZ!Box 4040)) 51 | $(eval $(call generate-ipq-wifi-package,openmesh_a42,board-openmesh_a42.bin,OpenMesh A42)) 52 | $(eval $(call generate-ipq-wifi-package,meraki_mr33,board-meraki_mr33.bin,Cisco Meraki MR33)) 53 | 54 | $(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE)))) 55 | -------------------------------------------------------------------------------- /overlay/package/firmware/ipq-wifi/board-meraki_mr33.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riptidewave93/LEDE-MR33/1734e288fd4e5e3a6fca50a11b8b2d3ffba98e28/overlay/package/firmware/ipq-wifi/board-meraki_mr33.bin -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/base-files/etc/board.d/02_network: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 | # Copyright (c) 2011-2015 OpenWrt.org 5 | # 6 | 7 | . /lib/functions/uci-defaults.sh 8 | . /lib/functions/system.sh 9 | 10 | board_config_update 11 | 12 | board=$(board_name) 13 | 14 | case "$board" in 15 | avm,fritzbox-4040) 16 | ucidef_set_interfaces_lan_wan "eth0" "eth1" 17 | ucidef_add_switch "switch0" \ 18 | "0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" 19 | ;; 20 | linksys,ea8500) 21 | hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) 22 | ucidef_add_switch "switch0" \ 23 | "0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" 24 | ucidef_set_interface_macaddr "lan" "$hw_mac_addr" 25 | ucidef_set_interface_macaddr "wan" "$hw_mac_addr" 26 | ;; 27 | meraki,mr33) 28 | ucidef_set_interface_lan "eth0" 29 | ;; 30 | netgear,d7800 |\ 31 | netgear,r7500 |\ 32 | netgear,r7500v2 |\ 33 | netgear,r7800 |\ 34 | qcom,ipq8064-ap148 |\ 35 | tplink,vr2600v) 36 | ucidef_add_switch "switch0" \ 37 | "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" 38 | ;; 39 | openmesh,a42) 40 | ucidef_set_interfaces_lan_wan "eth1" "eth0" 41 | ;; 42 | qcom,ipq8064-db149) 43 | ucidef_set_interface_lan "eth1 eth2 eth3" 44 | ucidef_add_switch "switch0" \ 45 | "1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0" 46 | ;; 47 | tplink,c2600) 48 | ucidef_add_switch "switch0" \ 49 | "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0" 50 | ;; 51 | zyxel,nbg6817) 52 | hw_mac_addr=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr) 53 | ucidef_add_switch "switch0" \ 54 | "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" 55 | ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)" 56 | ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)" 57 | ;; 58 | *) 59 | echo "Unsupported hardware. Network interfaces not intialized" 60 | ;; 61 | esac 62 | 63 | board_config_flush 64 | 65 | exit 0 66 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # xor multiple hex values of the same length 4 | xor() { 5 | local val 6 | local ret="0x$1" 7 | local retlen=${#1} 8 | 9 | shift 10 | while [ -n "$1" ]; do 11 | val="0x$1" 12 | ret=$((ret ^ val)) 13 | shift 14 | done 15 | 16 | printf "%0${retlen}x" "$ret" 17 | } 18 | 19 | ath10kcal_die() { 20 | echo "ath10cal: " "$*" 21 | exit 1 22 | } 23 | 24 | ath10kcal_from_file() { 25 | local source=$1 26 | local offset=$2 27 | local count=$3 28 | 29 | dd if=$source of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ 30 | ath10kcal_die "failed to extract calibration data from $source" 31 | } 32 | 33 | ath10kcal_extract() { 34 | local part=$1 35 | local offset=$2 36 | local count=$3 37 | local mtd 38 | 39 | mtd=$(find_mtd_chardev $part) 40 | [ -n "$mtd" ] || \ 41 | ath10kcal_die "no mtd device found for partition $part" 42 | 43 | dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ 44 | ath10kcal_die "failed to extract calibration data from $mtd" 45 | } 46 | 47 | ath10kcal_ubi_extract() { 48 | local part=$1 49 | local offset=$2 50 | local count=$3 51 | local ubi 52 | 53 | . /lib/upgrade/nand.sh 54 | 55 | ubi=$(nand_find_volume $(nand_find_ubi $CI_UBIPART) $part) 56 | [ -n "$ubi" ] || \ 57 | ath10kcal_die "no UBI volume found for $part" 58 | 59 | dd if=/dev/$ubi of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ 60 | ath10kcal_die "failed to extract calibration data from $ubi" 61 | } 62 | 63 | ath10kcal_patch_mac() { 64 | local mac=$1 65 | 66 | [ -z "$mac" ] && return 67 | 68 | macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=6 count=6 69 | } 70 | 71 | ath10kcal_patch_mac_crc() { 72 | local mac=$1 73 | local mac_offset=6 74 | local chksum_offset=2 75 | local xor_mac 76 | local xor_fw_mac 77 | local xor_fw_chksum 78 | 79 | xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE) 80 | xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}" 81 | 82 | ath10kcal_patch_mac "$mac" && { 83 | xor_mac=${mac//:/} 84 | xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}" 85 | 86 | xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE) 87 | xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac) 88 | 89 | printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \ 90 | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=$chksum_offset count=2 91 | } 92 | } 93 | 94 | [ -e /lib/firmware/$FIRMWARE ] && exit 0 95 | 96 | . /lib/functions.sh 97 | . /lib/functions/system.sh 98 | 99 | board=$(board_name) 100 | 101 | 102 | case "$FIRMWARE" in 103 | "ath10k/pre-cal-ahb-a000000.wifi.bin") 104 | case "$board" in 105 | avm,fritzbox-4040) 106 | /usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config") 107 | ;; 108 | meraki,mr33) 109 | ath10kcal_ubi_extract "ART" 4096 12064 110 | ath10kcal_patch_mac_crc $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) +2) 111 | ;; 112 | openmesh,a42) 113 | ath10kcal_extract "0:ART" 4096 12064 114 | ;; 115 | qcom,ap-dk01.1-c1) 116 | ath10kcal_extract "ART" 4096 12064 117 | ;; 118 | esac 119 | ;; 120 | "ath10k/pre-cal-ahb-a800000.wifi.bin") 121 | case "$board" in 122 | avm,fritzbox-4040) 123 | /usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config") 124 | ;; 125 | meraki,mr33) 126 | ath10kcal_ubi_extract "ART" 20480 12064 127 | ath10kcal_patch_mac_crc $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) +3) 128 | ;; 129 | openmesh,a42) 130 | ath10kcal_extract "0:ART" 20480 12064 131 | ;; 132 | qcom,ap-dk01.1-c1) 133 | ath10kcal_extract "ART" 20480 12064 134 | ;; 135 | esac 136 | ;; 137 | "ath10k/cal-pci-0000:01:00.0.bin") 138 | case "$board" in 139 | meraki,mr33) 140 | ath10kcal_ubi_extract "ART" 36864 12064 141 | ath10kcal_patch_mac $(macaddr_add $(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) +1) 142 | ;; 143 | esac 144 | ;; 145 | "ath10k/pre-cal-pci-0000:01:00.0.bin") 146 | case $board in 147 | linksys,ea8500) 148 | hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) 149 | ath10kcal_extract "art" 4096 12064 150 | ;; 151 | netgear,d7800 |\ 152 | netgear,r7500v2 |\ 153 | netgear,r7800) 154 | ath10kcal_extract "art" 4096 12064 155 | ;; 156 | tplink,c2600) 157 | ath10kcal_extract "radio" 4096 12064 158 | # ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 8) -1) 159 | ;; 160 | tplink,vr2600v) 161 | ath10kcal_extract "ART" 4096 12064 162 | ;; 163 | zyxel,nbg6817) 164 | ath10kcal_extract "0:ART" 4096 12064 165 | ;; 166 | esac 167 | ;; 168 | "ath10k/pre-cal-pci-0001:01:00.0.bin") 169 | case $board in 170 | linksys,ea8500) 171 | hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) 172 | ath10kcal_extract "art" 20480 12064 173 | ;; 174 | netgear,d7800 |\ 175 | netgear,r7500v2 |\ 176 | netgear,r7800) 177 | ath10kcal_extract "art" 20480 12064 178 | ;; 179 | tplink,c2600) 180 | ath10kcal_extract "radio" 20480 12064 181 | # ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 8) -2) 182 | ;; 183 | tplink,vr2600v) 184 | ath10kcal_extract "ART" 20480 12064 185 | ;; 186 | zyxel,nbg6817) 187 | ath10kcal_extract "0:ART" 20480 12064 188 | ;; 189 | esac 190 | ;; 191 | *) 192 | exit 1 193 | ;; 194 | esac 195 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/base-files/lib/preinit/05_set_iface_mac_ipq806x.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | . /lib/functions.sh 4 | 5 | preinit_set_mac_address() { 6 | case $(board_name) in 7 | meraki,mr33) 8 | mac_lan=$(get_mac_binary "/sys/bus/i2c/devices/0-0050/eeprom" 102) 9 | [ -n "$mac_lan" ] && ip link set dev eth0 address "$mac_lan" 10 | ;; 11 | esac 12 | } 13 | 14 | boot_hook_add preinit_main preinit_set_mac_address 15 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/base-files/lib/upgrade/merakinand.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | # Copyright (C) 2017 Chris Blake 4 | # 5 | # Custom upgrade script for Meraki NAND devices 6 | # 7 | 8 | . /lib/functions.sh 9 | . /lib/functions/system.sh 10 | 11 | get_magic_at() { 12 | local mtddev=$1 13 | local pos=$2 14 | dd bs=1 count=2 skip=$pos if=$mtddev 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' 15 | } 16 | 17 | meraki_is_caldata_valid() { 18 | local board=$1 19 | local mtddev=$2 20 | local magic 21 | 22 | case "$board" in 23 | "meraki,mr33") 24 | magic=$(get_magic_at $mtddev 4096) 25 | [ "$magic" != "202f" ] && return 0 26 | 27 | magic=$(get_magic_at $mtddev 20480) 28 | [ "$magic" != "202f" ] && return 0 29 | 30 | magic=$(get_magic_at $mtddev 36864) 31 | [ "$magic" != "4408" ] && return 0 32 | 33 | return 1 34 | ;; 35 | *) 36 | return 1 37 | ;; 38 | esac 39 | } 40 | 41 | merakinand_copy_caldata() { 42 | local cal_src=$1 43 | local cal_dst=$2 44 | local ubidev="$(nand_find_ubi $CI_UBIPART)" 45 | local board_name="$(board_name)" 46 | local rootfs_size="$(ubinfo /dev/ubi0 -N rootfs_data | grep "Size" | awk '{ print $6 }')" 47 | 48 | # Setup partitions using board name, in case of future platforms 49 | case "$board_name" in 50 | "meraki,mr33") 51 | # Src is MTD 52 | mtd_src="$(find_mtd_chardev $cal_src)" 53 | [ -n "$mtd_src" ] || { 54 | echo "no mtd device found for partition $cal_src" 55 | exit 1 56 | } 57 | 58 | # Dest is UBI 59 | # TODO: possibly add create (hard to do when rootfs_data is expanded & mounted) 60 | # Would need to be done from ramdisk 61 | mtd_dst="$(nand_find_volume $ubidev $cal_dst)" 62 | [ -n "$mtd_dst" ] || { 63 | echo "no ubi device found for partition $cal_dst" 64 | exit 1 65 | } 66 | 67 | meraki_is_caldata_valid "$board_name" "$mtd_src" && { 68 | echo "no valid calibration data found in $cal_src" 69 | exit 1 70 | } 71 | 72 | meraki_is_caldata_valid "$board_name" "/dev/$mtd_dst" && { 73 | echo "Copying calibration data from $cal_src to $cal_dst..." 74 | dd if="$mtd_src" of=/tmp/caldata.tmp 2>/dev/null 75 | ubiupdatevol "/dev/$mtd_dst" /tmp/caldata.tmp 76 | rm /tmp/caldata.tmp 77 | sync 78 | } 79 | return 0 80 | ;; 81 | *) 82 | echo "Unsupported device $board_name"; 83 | return 1 84 | ;; 85 | esac 86 | } 87 | 88 | platform_do_upgrade_merakinand() { 89 | local tar_file="$1" 90 | local board_name="$(board_name)" 91 | 92 | # Do we need to do any platform tweaks? 93 | case "$board_name" in 94 | "meraki,mr33") 95 | # Check and create UBI caldata if it's invalid 96 | merakinand_copy_caldata "ART" "ART" 97 | 98 | nand_do_upgrade $1 99 | ;; 100 | *) 101 | echo "Unsupported device $board_name"; 102 | exit 1 103 | ;; 104 | esac 105 | } 106 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/base-files/lib/upgrade/platform.sh: -------------------------------------------------------------------------------- 1 | PART_NAME=firmware 2 | REQUIRE_IMAGE_METADATA=1 3 | 4 | RAMFS_COPY_BIN='fw_printenv fw_setenv' 5 | RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' 6 | 7 | platform_check_image() { 8 | return 0; 9 | } 10 | 11 | platform_do_upgrade() { 12 | case "$(board_name)" in 13 | linksys,ea8500) 14 | platform_do_upgrade_linksys "$ARGV" 15 | ;; 16 | netgear,d7800 |\ 17 | netgear,r7500 |\ 18 | netgear,r7500v2 |\ 19 | netgear,r7800 |\ 20 | qcom,ap-dk04.1-c1 |\ 21 | qcom,ipq8064-ap148 |\ 22 | zyxel,nbg6817) 23 | nand_do_upgrade "$ARGV" 24 | ;; 25 | meraki,mr33) 26 | CI_KERNPART="part.safe" 27 | platform_do_upgrade_merakinand "$ARGV" 28 | ;; 29 | openmesh,a42) 30 | PART_NAME="inactive" 31 | platform_do_upgrade_openmesh "$ARGV" 32 | ;; 33 | tplink,c2600) 34 | PART_NAME="os-image:rootfs" 35 | MTD_CONFIG_ARGS="-s 0x200000" 36 | default_do_upgrade "$ARGV" 37 | ;; 38 | tplink,vr2600v) 39 | PART_NAME="kernel:rootfs" 40 | MTD_CONFIG_ARGS="-s 0x200000" 41 | default_do_upgrade "$ARGV" 42 | ;; 43 | *) 44 | default_do_upgrade "$ARGV" 45 | ;; 46 | esac 47 | } 48 | 49 | platform_nand_pre_upgrade() { 50 | case "$(board_name)" in 51 | zyxel,nbg6817) 52 | zyxel_do_upgrade "$1" 53 | ;; 54 | esac 55 | } 56 | 57 | blink_led() { 58 | . /etc/diag.sh; set_state upgrade 59 | } 60 | 61 | append sysupgrade_pre_upgrade blink_led 62 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/config-4.9: -------------------------------------------------------------------------------- 1 | CONFIG_ALIGNMENT_TRAP=y 2 | # CONFIG_AMBA_PL08X is not set 3 | CONFIG_APQ_GCC_8084=y 4 | CONFIG_APQ_MMCC_8084=y 5 | CONFIG_AR40XX_PHY=y 6 | CONFIG_AR8216_PHY=y 7 | CONFIG_ARCH_CLOCKSOURCE_DATA=y 8 | CONFIG_ARCH_HAS_ELF_RANDOMIZE=y 9 | CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y 10 | CONFIG_ARCH_HAS_SG_CHAIN=y 11 | CONFIG_ARCH_HAS_TICK_BROADCAST=y 12 | CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y 13 | CONFIG_ARCH_HIBERNATION_POSSIBLE=y 14 | CONFIG_ARCH_IPQ40XX=y 15 | # CONFIG_ARCH_MDM9615 is not set 16 | CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y 17 | CONFIG_ARCH_MSM8960=y 18 | CONFIG_ARCH_MSM8974=y 19 | CONFIG_ARCH_MSM8X60=y 20 | CONFIG_ARCH_MULTIPLATFORM=y 21 | # CONFIG_ARCH_MULTI_CPU_AUTO is not set 22 | CONFIG_ARCH_MULTI_V6_V7=y 23 | CONFIG_ARCH_MULTI_V7=y 24 | CONFIG_ARCH_NR_GPIO=0 25 | CONFIG_ARCH_QCOM=y 26 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set 27 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set 28 | CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y 29 | CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y 30 | CONFIG_ARCH_SUPPORTS_UPROBES=y 31 | CONFIG_ARCH_SUSPEND_POSSIBLE=y 32 | CONFIG_ARCH_USE_BUILTIN_BSWAP=y 33 | CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y 34 | CONFIG_ARCH_WANT_GENERAL_HUGETLB=y 35 | CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y 36 | CONFIG_ARM=y 37 | CONFIG_ARM_AMBA=y 38 | CONFIG_ARM_APPENDED_DTB=y 39 | CONFIG_ARM_ARCH_TIMER=y 40 | CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y 41 | CONFIG_ARM_ATAG_DTB_COMPAT=y 42 | # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set 43 | # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set 44 | CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y 45 | CONFIG_ARM_CPUIDLE=y 46 | CONFIG_ARM_CPU_SUSPEND=y 47 | # CONFIG_ARM_CPU_TOPOLOGY is not set 48 | CONFIG_ARM_GIC=y 49 | CONFIG_ARM_HAS_SG_CHAIN=y 50 | CONFIG_ARM_L1_CACHE_SHIFT=6 51 | CONFIG_ARM_L1_CACHE_SHIFT_6=y 52 | # CONFIG_ARM_LPAE is not set 53 | CONFIG_ARM_PATCH_IDIV=y 54 | CONFIG_ARM_PATCH_PHYS_VIRT=y 55 | CONFIG_ARM_QCOM_CPUFREQ=y 56 | CONFIG_ARM_QCOM_CPUIDLE=y 57 | # CONFIG_ARM_SMMU is not set 58 | # CONFIG_ARM_SP805_WATCHDOG is not set 59 | CONFIG_ARM_THUMB=y 60 | # CONFIG_ARM_THUMBEE is not set 61 | CONFIG_ARM_UNWIND=y 62 | CONFIG_ARM_VIRT_EXT=y 63 | CONFIG_AT803X_PHY=y 64 | # CONFIG_BINFMT_FLAT is not set 65 | CONFIG_BLK_DEV_LOOP=y 66 | CONFIG_BLK_MQ_PCI=y 67 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 68 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 69 | CONFIG_BOUNCE=y 70 | CONFIG_BUS_TOPOLOGY_ADHOC=y 71 | # CONFIG_CACHE_L2X0 is not set 72 | CONFIG_CLKDEV_LOOKUP=y 73 | CONFIG_CLKSRC_OF=y 74 | CONFIG_CLKSRC_PROBE=y 75 | CONFIG_CLKSRC_QCOM=y 76 | CONFIG_CLONE_BACKWARDS=y 77 | CONFIG_COMMON_CLK=y 78 | CONFIG_COMMON_CLK_QCOM=y 79 | CONFIG_CPUFREQ_DT=y 80 | CONFIG_CPUFREQ_DT_PLATDEV=y 81 | CONFIG_CPU_32v6K=y 82 | CONFIG_CPU_32v7=y 83 | CONFIG_CPU_ABRT_EV7=y 84 | # CONFIG_CPU_BIG_ENDIAN is not set 85 | # CONFIG_CPU_BPREDICT_DISABLE is not set 86 | CONFIG_CPU_CACHE_V7=y 87 | CONFIG_CPU_CACHE_VIPT=y 88 | CONFIG_CPU_COPY_V6=y 89 | CONFIG_CPU_CP15=y 90 | CONFIG_CPU_CP15_MMU=y 91 | CONFIG_CPU_FREQ=y 92 | CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 93 | # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set 94 | CONFIG_CPU_FREQ_GOV_ATTR_SET=y 95 | CONFIG_CPU_FREQ_GOV_COMMON=y 96 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set 97 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y 98 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y 99 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set 100 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set 101 | CONFIG_CPU_FREQ_STAT=y 102 | CONFIG_CPU_HAS_ASID=y 103 | # CONFIG_CPU_ICACHE_DISABLE is not set 104 | CONFIG_CPU_IDLE=y 105 | CONFIG_CPU_IDLE_GOV_LADDER=y 106 | CONFIG_CPU_IDLE_GOV_MENU=y 107 | CONFIG_CPU_PABRT_V7=y 108 | CONFIG_CPU_PM=y 109 | CONFIG_CPU_RMAP=y 110 | CONFIG_CPU_THERMAL=y 111 | CONFIG_CPU_TLB_V7=y 112 | CONFIG_CPU_V7=y 113 | CONFIG_CRC16=y 114 | # CONFIG_CRC32_SARWATE is not set 115 | CONFIG_CRC32_SLICEBY8=y 116 | CONFIG_CRYPTO_AEAD=y 117 | CONFIG_CRYPTO_AEAD2=y 118 | CONFIG_CRYPTO_CBC=y 119 | CONFIG_CRYPTO_CTR=y 120 | CONFIG_CRYPTO_DEFLATE=y 121 | CONFIG_CRYPTO_DES=y 122 | CONFIG_CRYPTO_DEV_QCE=y 123 | CONFIG_CRYPTO_DRBG=y 124 | CONFIG_CRYPTO_DRBG_HMAC=y 125 | CONFIG_CRYPTO_DRBG_MENU=y 126 | CONFIG_CRYPTO_ECB=y 127 | CONFIG_CRYPTO_GF128MUL=y 128 | CONFIG_CRYPTO_HASH=y 129 | CONFIG_CRYPTO_HASH2=y 130 | CONFIG_CRYPTO_HMAC=y 131 | CONFIG_CRYPTO_HW=y 132 | CONFIG_CRYPTO_JITTERENTROPY=y 133 | CONFIG_CRYPTO_LZO=y 134 | CONFIG_CRYPTO_MANAGER=y 135 | CONFIG_CRYPTO_MANAGER2=y 136 | CONFIG_CRYPTO_NULL=y 137 | CONFIG_CRYPTO_NULL2=y 138 | CONFIG_CRYPTO_RNG=y 139 | CONFIG_CRYPTO_RNG2=y 140 | CONFIG_CRYPTO_RNG_DEFAULT=y 141 | CONFIG_CRYPTO_SEQIV=y 142 | CONFIG_CRYPTO_SHA256=y 143 | CONFIG_CRYPTO_WORKQUEUE=y 144 | CONFIG_CRYPTO_XTS=y 145 | CONFIG_DCACHE_WORD_ACCESS=y 146 | CONFIG_DEBUG_GPIO=y 147 | CONFIG_DEBUG_LL=y 148 | CONFIG_DEBUG_LL_INCLUDE="debug/msm.S" 149 | CONFIG_DEBUG_QCOM_UARTDM=y 150 | # CONFIG_DEBUG_UART_8250 is not set 151 | CONFIG_DEBUG_UART_PHYS=0x16340000 152 | CONFIG_DEBUG_UART_VIRT=0xf6340000 153 | CONFIG_DEBUG_UNCOMPRESS=y 154 | # CONFIG_DEBUG_USER is not set 155 | CONFIG_DMADEVICES=y 156 | CONFIG_DMA_ENGINE=y 157 | CONFIG_DMA_OF=y 158 | CONFIG_DMA_VIRTUAL_CHANNELS=y 159 | CONFIG_DTC=y 160 | CONFIG_DT_IDLE_STATES=y 161 | # CONFIG_DWMAC_GENERIC is not set 162 | CONFIG_DWMAC_IPQ806X=y 163 | CONFIG_DYNAMIC_DEBUG=y 164 | CONFIG_EARLY_PRINTK=y 165 | CONFIG_EDAC_ATOMIC_SCRUB=y 166 | CONFIG_EDAC_SUPPORT=y 167 | CONFIG_EEPROM_AT24=y 168 | CONFIG_ESSEDMA=y 169 | CONFIG_ETHERNET_PACKET_MANGLE=y 170 | CONFIG_FIXED_PHY=y 171 | CONFIG_FIX_EARLYCON_MEM=y 172 | CONFIG_GENERIC_ALLOCATOR=y 173 | CONFIG_GENERIC_BUG=y 174 | CONFIG_GENERIC_CLOCKEVENTS=y 175 | CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y 176 | CONFIG_GENERIC_EARLY_IOREMAP=y 177 | CONFIG_GENERIC_IDLE_POLL_SETUP=y 178 | CONFIG_GENERIC_IO=y 179 | CONFIG_GENERIC_IRQ_SHOW=y 180 | CONFIG_GENERIC_IRQ_SHOW_LEVEL=y 181 | CONFIG_GENERIC_MSI_IRQ=y 182 | CONFIG_GENERIC_MSI_IRQ_DOMAIN=y 183 | CONFIG_GENERIC_PCI_IOMAP=y 184 | CONFIG_GENERIC_PHY=y 185 | CONFIG_GENERIC_PINCONF=y 186 | CONFIG_GENERIC_SCHED_CLOCK=y 187 | CONFIG_GENERIC_SMP_IDLE_THREAD=y 188 | CONFIG_GENERIC_STRNCPY_FROM_USER=y 189 | CONFIG_GENERIC_STRNLEN_USER=y 190 | CONFIG_GENERIC_TIME_VSYSCALL=y 191 | CONFIG_GPIOLIB=y 192 | CONFIG_GPIOLIB_IRQCHIP=y 193 | CONFIG_GPIO_SYSFS=y 194 | CONFIG_GPIO_WATCHDOG=y 195 | # CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set 196 | CONFIG_HANDLE_DOMAIN_IRQ=y 197 | CONFIG_HARDIRQS_SW_RESEND=y 198 | CONFIG_HAS_DMA=y 199 | CONFIG_HAS_IOMEM=y 200 | CONFIG_HAS_IOPORT_MAP=y 201 | # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set 202 | CONFIG_HAVE_ARCH_AUDITSYSCALL=y 203 | CONFIG_HAVE_ARCH_BITREVERSE=y 204 | CONFIG_HAVE_ARCH_JUMP_LABEL=y 205 | CONFIG_HAVE_ARCH_KGDB=y 206 | CONFIG_HAVE_ARCH_PFN_VALID=y 207 | CONFIG_HAVE_ARCH_SECCOMP_FILTER=y 208 | CONFIG_HAVE_ARCH_TRACEHOOK=y 209 | CONFIG_HAVE_ARM_ARCH_TIMER=y 210 | CONFIG_HAVE_ARM_SMCCC=y 211 | # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set 212 | CONFIG_HAVE_CBPF_JIT=y 213 | CONFIG_HAVE_CC_STACKPROTECTOR=y 214 | CONFIG_HAVE_CLK=y 215 | CONFIG_HAVE_CLK_PREPARE=y 216 | CONFIG_HAVE_CONTEXT_TRACKING=y 217 | CONFIG_HAVE_C_RECORDMCOUNT=y 218 | CONFIG_HAVE_DEBUG_KMEMLEAK=y 219 | CONFIG_HAVE_DMA_API_DEBUG=y 220 | CONFIG_HAVE_DMA_CONTIGUOUS=y 221 | CONFIG_HAVE_DYNAMIC_FTRACE=y 222 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y 223 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 224 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 225 | CONFIG_HAVE_FUNCTION_TRACER=y 226 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y 227 | CONFIG_HAVE_IDE=y 228 | CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y 229 | CONFIG_HAVE_MEMBLOCK=y 230 | CONFIG_HAVE_MOD_ARCH_SPECIFIC=y 231 | CONFIG_HAVE_NET_DSA=y 232 | CONFIG_HAVE_OPROFILE=y 233 | CONFIG_HAVE_OPTPROBES=y 234 | CONFIG_HAVE_PERF_EVENTS=y 235 | CONFIG_HAVE_PERF_REGS=y 236 | CONFIG_HAVE_PERF_USER_STACK_DUMP=y 237 | CONFIG_HAVE_PROC_CPU=y 238 | CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y 239 | CONFIG_HAVE_SMP=y 240 | CONFIG_HAVE_SYSCALL_TRACEPOINTS=y 241 | CONFIG_HAVE_UID16=y 242 | CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y 243 | CONFIG_HIGHMEM=y 244 | # CONFIG_HIGHPTE is not set 245 | CONFIG_HWMON=y 246 | CONFIG_HWSPINLOCK=y 247 | CONFIG_HWSPINLOCK_QCOM=y 248 | CONFIG_HW_RANDOM=y 249 | CONFIG_HW_RANDOM_MSM=y 250 | CONFIG_HZ_FIXED=0 251 | CONFIG_I2C=y 252 | CONFIG_I2C_BOARDINFO=y 253 | CONFIG_I2C_CHARDEV=y 254 | CONFIG_I2C_HELPER_AUTO=y 255 | CONFIG_I2C_QUP=y 256 | CONFIG_INITRAMFS_SOURCE="" 257 | CONFIG_IOMMU_HELPER=y 258 | # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set 259 | # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set 260 | CONFIG_IOMMU_SUPPORT=y 261 | CONFIG_IPQ_GCC_4019=y 262 | CONFIG_IPQ_GCC_806X=y 263 | # CONFIG_IPQ_LCC_806X is not set 264 | CONFIG_IRQCHIP=y 265 | CONFIG_IRQ_DOMAIN=y 266 | CONFIG_IRQ_DOMAIN_HIERARCHY=y 267 | CONFIG_IRQ_FORCED_THREADING=y 268 | CONFIG_IRQ_WORK=y 269 | CONFIG_KPSS_XCC=y 270 | CONFIG_KRAITCC=y 271 | CONFIG_KRAIT_CLOCKS=y 272 | CONFIG_KRAIT_L2_ACCESSORS=y 273 | CONFIG_LEDS_LP5562=y 274 | CONFIG_LIBFDT=y 275 | CONFIG_LOCKUP_DETECTOR=y 276 | CONFIG_LOCK_SPIN_ON_OWNER=y 277 | CONFIG_LZO_COMPRESS=y 278 | CONFIG_LZO_DECOMPRESS=y 279 | CONFIG_MDIO_BITBANG=y 280 | CONFIG_MDIO_BOARDINFO=y 281 | CONFIG_MDIO_GPIO=y 282 | CONFIG_MDIO_IPQ40XX=y 283 | # CONFIG_MDM_GCC_9615 is not set 284 | # CONFIG_MDM_LCC_9615 is not set 285 | # CONFIG_MFD_MAX77620 is not set 286 | CONFIG_MFD_QCOM_RPM=y 287 | # CONFIG_MFD_SPMI_PMIC is not set 288 | CONFIG_MFD_SYSCON=y 289 | CONFIG_MIGHT_HAVE_CACHE_L2X0=y 290 | CONFIG_MIGHT_HAVE_PCI=y 291 | CONFIG_MMC=y 292 | CONFIG_MMC_ARMMMCI=y 293 | CONFIG_MMC_BLOCK=y 294 | CONFIG_MMC_BLOCK_MINORS=16 295 | CONFIG_MMC_QCOM_DML=y 296 | CONFIG_MMC_SDHCI=y 297 | CONFIG_MMC_SDHCI_MSM=y 298 | # CONFIG_MMC_SDHCI_PCI is not set 299 | CONFIG_MMC_SDHCI_PLTFM=y 300 | # CONFIG_MMC_TIFM_SD is not set 301 | CONFIG_MODULES_USE_ELF_REL=y 302 | CONFIG_MSM_BUS_SCALING=y 303 | CONFIG_MSM_GCC_8660=y 304 | # CONFIG_MSM_GCC_8916 is not set 305 | CONFIG_MSM_GCC_8960=y 306 | CONFIG_MSM_GCC_8974=y 307 | # CONFIG_MSM_GCC_8996 is not set 308 | # CONFIG_MSM_IOMMU is not set 309 | # CONFIG_MSM_LCC_8960 is not set 310 | CONFIG_MSM_MMCC_8960=y 311 | CONFIG_MSM_MMCC_8974=y 312 | # CONFIG_MSM_MMCC_8996 is not set 313 | CONFIG_MTD_CMDLINE_PARTS=y 314 | CONFIG_MTD_M25P80=y 315 | CONFIG_MTD_NAND=y 316 | CONFIG_MTD_NAND_ECC=y 317 | CONFIG_MTD_NAND_QCOM=y 318 | # CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set 319 | CONFIG_MTD_QCOM_SMEM_PARTS=y 320 | CONFIG_MTD_SPI_NOR=y 321 | CONFIG_MTD_SPLIT_FIRMWARE=y 322 | CONFIG_MTD_SPLIT_FIT_FW=y 323 | CONFIG_MTD_UBI=y 324 | CONFIG_MTD_UBI_BEB_LIMIT=20 325 | CONFIG_MTD_UBI_BLOCK=y 326 | # CONFIG_MTD_UBI_FASTMAP is not set 327 | # CONFIG_MTD_UBI_GLUEBI is not set 328 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 329 | CONFIG_MULTI_IRQ_HANDLER=y 330 | CONFIG_MUTEX_SPIN_ON_OWNER=y 331 | CONFIG_NEED_DMA_MAP_STATE=y 332 | CONFIG_NEON=y 333 | CONFIG_NET_DSA=y 334 | CONFIG_NET_DSA_HWMON=y 335 | CONFIG_NET_DSA_QCA8K=y 336 | CONFIG_NET_DSA_TAG_QCA=y 337 | CONFIG_NET_FLOW_LIMIT=y 338 | CONFIG_NET_PTP_CLASSIFY=y 339 | CONFIG_NET_SWITCHDEV=y 340 | CONFIG_NLS=y 341 | CONFIG_NO_BOOTMEM=y 342 | CONFIG_NO_HZ=y 343 | CONFIG_NO_HZ_COMMON=y 344 | CONFIG_NO_HZ_IDLE=y 345 | CONFIG_NR_CPUS=4 346 | CONFIG_NVMEM=y 347 | CONFIG_OF=y 348 | CONFIG_OF_ADDRESS=y 349 | CONFIG_OF_ADDRESS_PCI=y 350 | CONFIG_OF_EARLY_FLATTREE=y 351 | CONFIG_OF_FLATTREE=y 352 | CONFIG_OF_GPIO=y 353 | CONFIG_OF_IRQ=y 354 | CONFIG_OF_MDIO=y 355 | CONFIG_OF_NET=y 356 | CONFIG_OF_PCI=y 357 | CONFIG_OF_PCI_IRQ=y 358 | CONFIG_OF_RESERVED_MEM=y 359 | CONFIG_OLD_SIGACTION=y 360 | CONFIG_OLD_SIGSUSPEND3=y 361 | CONFIG_PADATA=y 362 | CONFIG_PAGE_OFFSET=0xC0000000 363 | CONFIG_PCI=y 364 | CONFIG_PCIEAER=y 365 | CONFIG_PCIEPORTBUS=y 366 | CONFIG_PCIE_DW=y 367 | CONFIG_PCIE_QCOM=y 368 | CONFIG_PCI_DEBUG=y 369 | CONFIG_PCI_DISABLE_COMMON_QUIRKS=y 370 | CONFIG_PCI_DOMAINS=y 371 | CONFIG_PCI_DOMAINS_GENERIC=y 372 | CONFIG_PCI_MSI=y 373 | CONFIG_PCI_MSI_IRQ_DOMAIN=y 374 | CONFIG_PERF_USE_VMALLOC=y 375 | CONFIG_PGTABLE_LEVELS=2 376 | CONFIG_PHYLIB=y 377 | # CONFIG_PHY_QCOM_APQ8064_SATA is not set 378 | CONFIG_PHY_QCOM_IPQ806X_SATA=y 379 | # CONFIG_PHY_QCOM_UFS is not set 380 | CONFIG_PINCTRL=y 381 | CONFIG_PINCTRL_APQ8064=y 382 | # CONFIG_PINCTRL_APQ8084 is not set 383 | CONFIG_PINCTRL_IPQ4019=y 384 | CONFIG_PINCTRL_IPQ8064=y 385 | # CONFIG_PINCTRL_MDM9615 is not set 386 | CONFIG_PINCTRL_MSM=y 387 | # CONFIG_PINCTRL_MSM8660 is not set 388 | # CONFIG_PINCTRL_MSM8916 is not set 389 | # CONFIG_PINCTRL_MSM8960 is not set 390 | # CONFIG_PINCTRL_MSM8996 is not set 391 | CONFIG_PINCTRL_MSM8X74=y 392 | # CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set 393 | # CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set 394 | # CONFIG_PL330_DMA is not set 395 | CONFIG_PM_OPP=y 396 | CONFIG_POWER_RESET=y 397 | # CONFIG_POWER_RESET_BRCMKONA is not set 398 | CONFIG_POWER_RESET_MSM=y 399 | CONFIG_POWER_SUPPLY=y 400 | CONFIG_PPS=y 401 | CONFIG_PRINTK_TIME=y 402 | CONFIG_PTP_1588_CLOCK=y 403 | CONFIG_QCOM_ADM=y 404 | CONFIG_QCOM_BAM_DMA=y 405 | CONFIG_QCOM_CLK_RPM=y 406 | # CONFIG_QCOM_EBI2 is not set 407 | CONFIG_QCOM_GDSC=y 408 | CONFIG_QCOM_GSBI=y 409 | CONFIG_QCOM_HFPLL=y 410 | CONFIG_QCOM_PM=y 411 | # CONFIG_QCOM_Q6V5_PIL is not set 412 | CONFIG_QCOM_QFPROM=y 413 | CONFIG_QCOM_RPMCC=y 414 | CONFIG_QCOM_SCM=y 415 | CONFIG_QCOM_SCM_32=y 416 | # CONFIG_QCOM_SMD is not set 417 | CONFIG_QCOM_SMEM=y 418 | # CONFIG_QCOM_SMP2P is not set 419 | # CONFIG_QCOM_SMSM is not set 420 | CONFIG_QCOM_TCSR=y 421 | CONFIG_QCOM_TSENS=y 422 | # CONFIG_QCOM_WCNSS_PIL is not set 423 | CONFIG_QCOM_WDT=y 424 | # CONFIG_QRTR is not set 425 | CONFIG_RAS=y 426 | CONFIG_RATIONAL=y 427 | CONFIG_RCU_CPU_STALL_TIMEOUT=21 428 | CONFIG_RCU_STALL_COMMON=y 429 | CONFIG_REGMAP=y 430 | CONFIG_REGMAP_I2C=y 431 | CONFIG_REGMAP_MMIO=y 432 | CONFIG_REGMAP_SPI=y 433 | CONFIG_REGULATOR=y 434 | CONFIG_REGULATOR_FIXED_VOLTAGE=y 435 | CONFIG_REGULATOR_QCOM_RPM=y 436 | # CONFIG_REGULATOR_QCOM_SPMI is not set 437 | CONFIG_RESET_CONTROLLER=y 438 | CONFIG_RFS_ACCEL=y 439 | # CONFIG_RPMSG_QCOM_SMD is not set 440 | CONFIG_RPS=y 441 | CONFIG_RTC_CLASS=y 442 | # CONFIG_RTC_DRV_CMOS is not set 443 | CONFIG_RTC_I2C_AND_SPI=y 444 | CONFIG_RWSEM_SPIN_ON_OWNER=y 445 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y 446 | # CONFIG_SCHED_INFO is not set 447 | # CONFIG_SCSI_DMA is not set 448 | CONFIG_SERIAL_8250_FSL=y 449 | # CONFIG_SERIAL_AMBA_PL010 is not set 450 | # CONFIG_SERIAL_AMBA_PL011 is not set 451 | CONFIG_SERIAL_MSM=y 452 | CONFIG_SERIAL_MSM_CONSOLE=y 453 | CONFIG_SMP=y 454 | CONFIG_SMP_ON_UP=y 455 | CONFIG_SPARSE_IRQ=y 456 | CONFIG_SPI=y 457 | # CONFIG_SPI_CADENCE_QUADSPI is not set 458 | CONFIG_SPI_MASTER=y 459 | CONFIG_SPI_QUP=y 460 | CONFIG_SPMI=y 461 | CONFIG_SPMI_MSM_PMIC_ARB=y 462 | CONFIG_SRCU=y 463 | CONFIG_STMMAC_ETH=y 464 | CONFIG_STMMAC_PLATFORM=y 465 | CONFIG_SWCONFIG=y 466 | CONFIG_SWCONFIG_LEDS=y 467 | CONFIG_SWIOTLB=y 468 | CONFIG_SWPHY=y 469 | CONFIG_SWP_EMULATE=y 470 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y 471 | CONFIG_THERMAL=y 472 | CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y 473 | CONFIG_THERMAL_GOV_STEP_WISE=y 474 | CONFIG_THERMAL_HWMON=y 475 | CONFIG_THERMAL_OF=y 476 | # CONFIG_THUMB2_KERNEL is not set 477 | CONFIG_TICK_CPU_ACCOUNTING=y 478 | CONFIG_TREE_RCU=y 479 | CONFIG_UBIFS_FS=y 480 | CONFIG_UBIFS_FS_ADVANCED_COMPR=y 481 | CONFIG_UBIFS_FS_LZO=y 482 | CONFIG_UBIFS_FS_ZLIB=y 483 | CONFIG_UEVENT_HELPER_PATH="" 484 | CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" 485 | CONFIG_USB=y 486 | CONFIG_USB_COMMON=y 487 | # CONFIG_USB_EHCI_HCD is not set 488 | CONFIG_USB_IPQ4019_PHY=y 489 | CONFIG_USB_SUPPORT=y 490 | # CONFIG_USB_UHCI_HCD is not set 491 | CONFIG_USE_OF=y 492 | CONFIG_VDSO=y 493 | CONFIG_VECTORS_BASE=0xffff0000 494 | CONFIG_VFP=y 495 | CONFIG_VFPv3=y 496 | CONFIG_WATCHDOG_CORE=y 497 | CONFIG_XPS=y 498 | CONFIG_XZ_DEC_ARM=y 499 | CONFIG_XZ_DEC_BCJ=y 500 | CONFIG_ZBOOT_ROM_BSS=0 501 | CONFIG_ZBOOT_ROM_TEXT=0 502 | CONFIG_ZLIB_DEFLATE=y 503 | CONFIG_ZLIB_INFLATE=y 504 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4029-mr33.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Source for Meraki MR33 (Stinkbug) 3 | * 4 | * Copyright (C) 2017 Chris Blake 5 | * Copyright (C) 2017 Christian Lamparter 6 | * 7 | * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427 8 | * 9 | * This file is licensed under the terms of the GNU General Public 10 | * License version 2. This program is licensed "as is" without 11 | * any warranty of any kind, whether express or implied. 12 | */ 13 | 14 | #include "qcom-ipq4019.dtsi" 15 | #include "qcom-ipq4019-bus.dtsi" 16 | #include 17 | #include 18 | #include 19 | 20 | / { 21 | model = "Meraki MR33 Access Point"; 22 | compatible = "meraki,mr33", "qcom,ipq4019"; 23 | 24 | aliases { 25 | i2c1 = &i2c_1; 26 | led-boot = &status_green; 27 | led-failsafe = &status_red; 28 | led-running = &status_green; 29 | led-upgrade = &power_orange; 30 | }; 31 | 32 | /* Do we really need this defined? */ 33 | memory { 34 | device_type = "memory"; 35 | reg = <0x80000000 0x10000000>; 36 | }; 37 | 38 | reserved-memory { 39 | #address-cells = <0x1>; 40 | #size-cells = <0x1>; 41 | ranges; 42 | 43 | tz_apps@87b80000 { 44 | reg = <0x87b80000 0x280000>; 45 | reusable; 46 | }; 47 | 48 | smem@87e00000 { 49 | reg = <0x87e00000 0x080000>; 50 | no-map; 51 | }; 52 | 53 | tz@87e80000 { 54 | reg = <0x87e80000 0x180000>; 55 | no-map; 56 | }; 57 | }; 58 | 59 | soc { 60 | mdio@90000 { 61 | status = "okay"; 62 | pinctrl-0 = <&mdio_pins>; 63 | pinctrl-names = "default"; 64 | phy-reset-gpio = <&tlmm 47 0>; 65 | }; 66 | 67 | counter@4a1000 { 68 | compatible = "qcom,qca-gcnt"; 69 | reg = <0x4a1000 0x4>; 70 | }; 71 | 72 | pinctrl@1000000 { 73 | mdio_pins: mdio_pinmux { 74 | mux_1 { 75 | pins = "gpio6"; 76 | function = "mdio"; 77 | bias-disable; 78 | }; 79 | mux_2 { 80 | pins = "gpio7"; 81 | function = "mdc"; 82 | bias-disable; 83 | }; 84 | }; 85 | 86 | serial_0_pins: serial_pinmux { 87 | mux { 88 | pins = "gpio16", "gpio17"; 89 | function = "blsp_uart0"; 90 | bias-disable; 91 | }; 92 | }; 93 | 94 | serial_1_pins: serial1_pinmux { 95 | mux { 96 | /* We use the i2c-0 pins for serial_1 */ 97 | pins = "gpio8", "gpio9"; 98 | function = "blsp_uart1"; 99 | bias-disable; 100 | }; 101 | }; 102 | 103 | i2c_0_pins: i2c_0_pinmux { 104 | pinmux { 105 | function = "blsp_i2c0"; 106 | pins = "gpio20", "gpio21"; 107 | }; 108 | pinconf { 109 | pins = "gpio20", "gpio21"; 110 | drive-strength = <16>; 111 | bias-disable; 112 | }; 113 | }; 114 | 115 | i2c_1_pins: i2c_1_pinmux { 116 | pinmux { 117 | function = "blsp_i2c1"; 118 | pins = "gpio34", "gpio35"; 119 | }; 120 | pinconf { 121 | pins = "gpio34", "gpio35"; 122 | drive-strength = <16>; 123 | bias-disable; 124 | }; 125 | }; 126 | 127 | nand_pins: nand_pins { 128 | pullups { 129 | pins = "gpio52", "gpio53", "gpio58", 130 | "gpio59"; 131 | function = "qpic"; 132 | bias-pull-up; 133 | }; 134 | 135 | pulldowns { 136 | pins = "gpio54", "gpio55", "gpio56", 137 | "gpio57", "gpio60", "gpio61", 138 | "gpio62", "gpio63", "gpio64", 139 | "gpio65", "gpio66", "gpio67", 140 | "gpio68", "gpio69"; 141 | function = "qpic"; 142 | bias-pull-down; 143 | }; 144 | }; 145 | }; 146 | 147 | ess_tcsr@1953000 { 148 | compatible = "qcom,tcsr"; 149 | reg = <0x1953000 0x1000>; 150 | qcom,ess-interface-select = ; 151 | }; 152 | 153 | tcsr@1949000 { 154 | compatible = "qcom,tcsr"; 155 | reg = <0x1949000 0x100>; 156 | qcom,wifi_glb_cfg = ; 157 | }; 158 | 159 | tcsr@1957000 { 160 | compatible = "qcom,tcsr"; 161 | reg = <0x1957000 0x100>; 162 | qcom,wifi_noc_memtype_m0_m2 = ; 163 | }; 164 | 165 | blsp_dma: dma@7884000 { 166 | status = "okay"; 167 | }; 168 | 169 | serial@78af000 { 170 | pinctrl-0 = <&serial_0_pins>; 171 | pinctrl-names = "default"; 172 | status = "okay"; 173 | }; 174 | 175 | serial@78b0000 { 176 | pinctrl-0 = <&serial_1_pins>; 177 | pinctrl-names = "default"; 178 | status = "okay"; 179 | }; 180 | 181 | i2c_0: i2c@78b7000 { 182 | reg = <0x78b7000 0x600>; 183 | status = "okay"; 184 | at24@50 { 185 | compatible = "atmel,24c64"; 186 | pagesize = <32>; 187 | reg = <0x50>; 188 | read-only; /* This holds our MAC & Meraki board-data */ 189 | }; 190 | }; 191 | 192 | /* Missing in IPQ4019 define */ 193 | i2c_1: i2c@78b8000 { 194 | compatible = "qcom,i2c-qup-v2.2.1"; 195 | reg = <0x78b8000 0x600>; 196 | interrupts = ; 197 | clocks = <&gcc GCC_BLSP1_AHB_CLK>, 198 | <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 199 | clock-names = "iface", "core"; 200 | #address-cells = <1>; 201 | #size-cells = <0>; 202 | dmas = <&blsp_dma 11>, <&blsp_dma 10>; 203 | dma-names = "rx", "tx"; 204 | pinctrl-0 = <&i2c_1_pins>; 205 | pinctrl-names = "default"; 206 | status = "okay"; 207 | 208 | lp5562 { 209 | enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>; 210 | compatible = "ti,lp5562"; 211 | clock-mode = /bits/8 <2>; 212 | reg = <0x30>; 213 | 214 | /* RGB led */ 215 | status_red: chan0 { 216 | chan-name = "mr33:red:status"; 217 | led-cur = /bits/ 8 <0x20>; 218 | max-cur = /bits/ 8 <0x60>; 219 | }; 220 | 221 | status_green: chan1 { 222 | chan-name = "mr33:green:status"; 223 | led-cur = /bits/ 8 <0x20>; 224 | max-cur = /bits/ 8 <0x60>; 225 | }; 226 | 227 | chan2 { 228 | chan-name = "mr33:blue:status"; 229 | led-cur = /bits/ 8 <0x20>; 230 | max-cur = /bits/ 8 <0x60>; 231 | }; 232 | 233 | chan3 { 234 | chan-name = "mr33:white:status"; 235 | led-cur = /bits/ 8 <0x20>; 236 | max-cur = /bits/ 8 <0x60>; 237 | }; 238 | }; 239 | }; 240 | 241 | dma@8e04000 { 242 | status = "okay"; 243 | }; 244 | 245 | crypto@8e3a000 { 246 | status = "okay"; 247 | }; 248 | 249 | wifi@a000000 { 250 | status = "okay"; 251 | }; 252 | 253 | wifi@a800000 { 254 | status = "okay"; 255 | }; 256 | 257 | watchdog@b017000 { 258 | status = "okay"; 259 | }; 260 | 261 | ess-switch@c000000 { 262 | switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */ 263 | switch_lan_bmp = <0x0>; /* lan port bitmap */ 264 | switch_wan_bmp = <0x10>; /* wan port bitmap */ 265 | }; 266 | 267 | edma@c080000 { 268 | qcom,single-phy; 269 | qcom,num_gmac = <1>; 270 | phy-mode = "rgmii-rxid"; 271 | status = "okay"; 272 | 273 | gmac0 { 274 | qcom,phy_mdio_addr = <1>; 275 | qcom,poll_required = <1>; 276 | vlan_tag = <0 0x20>; 277 | }; 278 | }; 279 | }; 280 | 281 | gpio-keys { 282 | compatible = "gpio-keys"; 283 | 284 | reset { 285 | label = "reset"; 286 | gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; 287 | linux,code = ; 288 | }; 289 | }; 290 | 291 | gpio-leds { 292 | compatible = "gpio-leds"; 293 | 294 | power_orange: power { 295 | label = "mr33:orange:power"; 296 | gpios = <&tlmm 49 GPIO_ACTIVE_LOW>; 297 | panic-indicator; 298 | }; 299 | }; 300 | 301 | gpio_export { 302 | compatible = "gpio-export"; 303 | 304 | nload_ble { 305 | gpio-export,name = "nload_ble"; 306 | gpio-export,output = <1>; 307 | gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; 308 | }; 309 | 310 | nreset_ble { 311 | gpio-export,name = "nreset_ble"; 312 | gpio-export,output = <1>; 313 | gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; 314 | }; 315 | 316 | on_adpt_pwr_src { 317 | gpio-export,name = "on_adpt_pwr_src"; 318 | gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; 319 | }; 320 | }; 321 | }; 322 | 323 | &pcie0 { 324 | status = "okay"; 325 | perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>; 326 | wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; 327 | }; 328 | 329 | &qpic_bam { 330 | status = "okay"; 331 | }; 332 | 333 | &nand { 334 | pinctrl-0 = <&nand_pins>; 335 | pinctrl-names = "default"; 336 | status = "okay"; 337 | 338 | nandcs@0 { 339 | partitions { 340 | compatible = "fixed-partitions"; 341 | #address-cells = <1>; 342 | #size-cells = <1>; 343 | 344 | partition@0 { 345 | label = "sbl1"; 346 | reg = <0x000000000000 0x000000100000>; 347 | read-only; 348 | }; 349 | partition@1 { 350 | label = "mibib"; 351 | reg = <0x000000100000 0x000000100000>; 352 | read-only; 353 | }; 354 | partition@2 { 355 | label = "bootconfig"; 356 | reg = <0x000000200000 0x000000100000>; 357 | read-only; 358 | }; 359 | partition@3 { 360 | label = "qsee"; 361 | reg = <0x000000300000 0x000000100000>; 362 | read-only; 363 | }; 364 | partition@4 { 365 | label = "qsee_alt"; 366 | reg = <0x000000400000 0x000000100000>; 367 | read-only; 368 | }; 369 | partition@5 { 370 | label = "cdt"; 371 | reg = <0x000000500000 0x000000080000>; 372 | read-only; 373 | }; 374 | partition@6 { 375 | label = "cdt_alt"; 376 | reg = <0x000000580000 0x000000080000>; 377 | read-only; 378 | }; 379 | partition@7 { 380 | label = "ddrparams"; 381 | reg = <0x000000600000 0x000000080000>; 382 | read-only; 383 | }; 384 | partition@8 { 385 | label = "u-boot"; 386 | reg = <0x000000700000 0x000000200000>; 387 | read-only; 388 | }; 389 | partition@9 { 390 | label = "u-boot-backup"; 391 | reg = <0x000000900000 0x000000200000>; 392 | read-only; 393 | }; 394 | partition@10 { 395 | label = "ART"; 396 | reg = <0x000000b00000 0x000000080000>; 397 | read-only; 398 | }; 399 | partition@11 { 400 | label = "ubi"; 401 | reg = <0x000000c00000 0x000007000000>; 402 | }; 403 | }; 404 | }; 405 | }; 406 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/image/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2014 The Linux Foundation. All rights reserved. 2 | # 3 | include $(TOPDIR)/rules.mk 4 | include $(INCLUDE_DIR)/image.mk 5 | 6 | define Device/Default 7 | PROFILES := Default 8 | KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts) 9 | KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs 10 | KERNEL_PREFIX := $$(IMAGE_PREFIX) 11 | KERNEL_LOADADDR = 0x42208000 12 | SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) 13 | IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata 14 | IMAGE/sysupgrade.bin/squashfs := 15 | endef 16 | 17 | define Device/LegacyImage 18 | KERNEL_SUFFIX := -uImage 19 | KERNEL = kernel-bin | append-dtb | uImage none 20 | KERNEL_NAME := zImage 21 | endef 22 | 23 | define Device/FitImage 24 | KERNEL_SUFFIX := -fit-uImage.itb 25 | KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb 26 | KERNEL_NAME := Image 27 | endef 28 | 29 | define Device/FitImageLzma 30 | KERNEL_SUFFIX := -fit-uImage.itb 31 | KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb 32 | KERNEL_NAME := Image 33 | endef 34 | 35 | define Device/UbiFit 36 | KERNEL_IN_UBI := 1 37 | IMAGES := nand-factory.ubi nand-sysupgrade.bin 38 | IMAGE/nand-factory.ubi := append-ubi 39 | IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata 40 | endef 41 | 42 | define Device/DniImage 43 | KERNEL_SUFFIX := -uImage 44 | KERNEL = kernel-bin | append-dtb | uImage none 45 | KERNEL_NAME := zImage 46 | NETGEAR_BOARD_ID := 47 | NETGEAR_HW_ID := 48 | UBINIZE_OPTS := -E 5 49 | IMAGES := factory.img sysupgrade.bin 50 | IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakeroot-hdr | pad-to $$$$(KERNEL_SIZE) | append-ubi | netgear-dni 51 | IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakeroot-hdr | sysupgrade-tar kernel=$$$$@ | append-metadata 52 | endef 53 | DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID 54 | 55 | define Device/TpSafeImage 56 | KERNEL_SUFFIX := -uImage 57 | KERNEL = kernel-bin | append-dtb | uImage none 58 | KERNEL_NAME := zImage 59 | TPLINK_BOARD_ID := 60 | IMAGES := factory.bin sysupgrade.bin 61 | IMAGE/factory.bin := append-rootfs | tplink-safeloader factory 62 | IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | append-metadata 63 | endef 64 | DEVICE_VARS += TPLINK_BOARD_ID 65 | 66 | define Device/ZyXELImage 67 | KERNEL_SUFFIX := -uImage 68 | KERNEL = kernel-bin | append-dtb | uImage none | pad-to $${KERNEL_SIZE} 69 | KERNEL_NAME := zImage 70 | IMAGES := sysupgrade.bin mmcblk0p5-rootfs.bin mmcblk0p4-kernel.bin 71 | IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$${BLOCKSIZE} | sysupgrade-tar rootfs=$$$$@ | append-metadata 72 | IMAGE/mmcblk0p5-rootfs.bin := append-rootfs | pad-rootfs | pad-to $$$${BLOCKSIZE} 73 | IMAGE/mmcblk0p4-kernel.bin := append-kernel 74 | endef 75 | 76 | define Device/avm_fritzbox-4040 77 | $(call Device/FitImageLzma) 78 | DEVICE_DTS := qcom-ipq4019-fritz4040 79 | KERNEL_LOADADDR := 0x80208000 80 | BLOCKSIZE := 4k 81 | PAGESIZE := 256 82 | BOARD_NAME := fritz4040 83 | DEVICE_TITLE := AVM Fritz!Box 4040 84 | IMAGE_SIZE := 29753344 85 | IMAGES = sysupgrade.bin 86 | IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata 87 | DEVICE_PACKAGES := ipq-wifi-fritz4040 fritz-tffs fritz-caldata u-boot-fritz4040 88 | endef 89 | TARGET_DEVICES += avm_fritzbox-4040 90 | 91 | define Device/linksys_ea8500 92 | $(call Device/LegacyImage) 93 | DEVICE_DTS := qcom-ipq8064-ea8500 94 | PAGESIZE := 2048 95 | BLOCKSIZE := 128k 96 | KERNEL_SIZE := 3072k 97 | KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakeroot-hdr 98 | BOARD_NAME := ea8500 99 | SUPPORTED_DEVICES += ea8500 100 | UBINIZE_OPTS := -E 5 101 | IMAGES := factory.bin sysupgrade.bin 102 | IMAGE/factory.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-ubi 103 | DEVICE_TITLE := Linksys EA8500 104 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 105 | endef 106 | TARGET_DEVICES += linksys_ea8500 107 | 108 | define Device/meraki_mr33 109 | $(call Device/FitImage) 110 | DEVICE_DTS := qcom-ipq4029-mr33 111 | KERNEL_LOADADDR := 0x80208000 112 | BLOCKSIZE := 4k 113 | PAGESIZE := 256 114 | DEVICE_TITLE := Meraki MR33 115 | IMAGES = sysupgrade.bin 116 | DEVICE_PACKAGES := -swconfig ipq-wifi-meraki_mr33 ath10k-firmware-qca9887 117 | endef 118 | TARGET_DEVICES += meraki_mr33 119 | 120 | define Device/netgear_d7800 121 | $(call Device/DniImage) 122 | DEVICE_DTS := qcom-ipq8064-d7800 123 | KERNEL_SIZE := 2097152 124 | NETGEAR_BOARD_ID := D7800 125 | NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4 126 | BLOCKSIZE := 128k 127 | PAGESIZE := 2048 128 | BOARD_NAME := d7800 129 | SUPPORTED_DEVICES += d7800 130 | DEVICE_TITLE := Netgear Nighthawk X4 D7800 131 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 132 | endef 133 | TARGET_DEVICES += netgear_d7800 134 | 135 | define Device/netgear_r7500 136 | $(call Device/DniImage) 137 | DEVICE_DTS := qcom-ipq8064-r7500 138 | KERNEL_SIZE := 2097152 139 | NETGEAR_BOARD_ID := R7500 140 | NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4 141 | BLOCKSIZE := 128k 142 | PAGESIZE := 2048 143 | BOARD_NAME := r7500 144 | SUPPORTED_DEVICES += r7500 145 | DEVICE_TITLE := Netgear Nighthawk X4 R7500 146 | DEVICE_PACKAGES := ath10k-firmware-qca988x 147 | endef 148 | TARGET_DEVICES += netgear_r7500 149 | 150 | define Device/netgear_r7500v2 151 | $(call Device/DniImage) 152 | DEVICE_DTS := qcom-ipq8064-r7500v2 153 | KERNEL_SIZE := 2097152 154 | NETGEAR_BOARD_ID := R7500v2 155 | NETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4 156 | BLOCKSIZE := 128k 157 | PAGESIZE := 2048 158 | BOARD_NAME := r7500v2 159 | SUPPORTED_DEVICES += r7500v2 160 | DEVICE_TITLE := Netgear Nighthawk X4 R7500v2 161 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 ath10k-firmware-qca988x 162 | endef 163 | TARGET_DEVICES += netgear_r7500v2 164 | 165 | define Device/netgear_r7800 166 | $(call Device/DniImage) 167 | DEVICE_DTS := qcom-ipq8065-r7800 168 | KERNEL_SIZE := 2097152 169 | NETGEAR_BOARD_ID := R7800 170 | NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade 171 | BLOCKSIZE := 128k 172 | PAGESIZE := 2048 173 | BOARD_NAME := r7800 174 | SUPPORTED_DEVICES += r7800 175 | DEVICE_TITLE := Netgear Nighthawk X4S R7800 176 | DEVICE_PACKAGES := ath10k-firmware-qca9984 177 | endef 178 | TARGET_DEVICES += netgear_r7800 179 | 180 | define Device/openmesh_a42 181 | $(call Device/FitImageLzma) 182 | DEVICE_DTS := qcom-ipq4019-a42 183 | KERNEL_LOADADDR := 0x80208000 184 | BLOCKSIZE := 64k 185 | SUPPORTED_DEVICES := openmesh,a42 186 | DEVICE_TITLE := OpenMesh A42 187 | KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) 188 | IMAGE_SIZE := 15616k 189 | IMAGES = factory.bin sysupgrade.bin 190 | IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42 191 | IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata 192 | DEVICE_PACKAGES := ath10k-firmware-qca4019 uboot-envtools ipq-wifi-openmesh_a42 193 | endef 194 | TARGET_DEVICES += openmesh_a42 195 | 196 | define Device/qcom_ap-dk01.1-c1 197 | DEVICE_TITLE := QCA AP-DK01.1-C1 198 | BOARD_NAME := ap-dk01.1-c1 199 | DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1 200 | KERNEL_LOADADDR := 0x80208000 201 | KERNEL_INSTALL := 1 202 | KERNEL_SIZE := 4096k 203 | IMAGE_SIZE := 26624k 204 | $(call Device/FitImage) 205 | IMAGES := sysupgrade.bin 206 | IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata 207 | DEVICE_PACKAGES := ath10k-firmware-qca4019 208 | endef 209 | TARGET_DEVICES += qcom_ap-dk01.1-c1 210 | 211 | define Device/qcom_ap-dk04.1-c1 212 | $(call Device/FitImage) 213 | $(call Device/UbiFit) 214 | DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1 215 | KERNEL_LOADADDR := 0x80208000 216 | KERNEL_INSTALL := 1 217 | KERNEL_SIZE := 4048k 218 | BLOCKSIZE := 128k 219 | PAGESIZE := 2048 220 | BOARD_NAME := ap-dk04.1-c1 221 | DEVICE_TITLE := QCA AP-DK04.1-C1 222 | endef 223 | TARGET_DEVICES += qcom_ap-dk04.1-c1 224 | 225 | define Device/qcom_ipq8064-ap148 226 | $(call Device/FitImage) 227 | $(call Device/UbiFit) 228 | DEVICE_DTS := qcom-ipq8064-ap148 229 | KERNEL_INSTALL := 1 230 | BLOCKSIZE := 128k 231 | PAGESIZE := 2048 232 | BOARD_NAME := ap148 233 | SUPPORTED_DEVICES += ap148 234 | DEVICE_TITLE := Qualcomm AP148 235 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 236 | endef 237 | TARGET_DEVICES += qcom_ipq8064-ap148 238 | 239 | define Device/qcom_ipq8064-ap148-legacy 240 | $(call Device/LegacyImage) 241 | $(call Device/UbiFit) 242 | DEVICE_DTS := qcom-ipq8064-ap148 243 | BLOCKSIZE := 128k 244 | PAGESIZE := 2048 245 | BOARD_NAME := ap148 246 | SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148 247 | DEVICE_TITLE := Qualcomm AP148 (legacy) 248 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 249 | endef 250 | TARGET_DEVICES += qcom_ipq8064-ap148-legacy 251 | 252 | define Device/qcom_ipq8064-db149 253 | $(call Device/FitImage) 254 | DEVICE_DTS := qcom-ipq8064-db149 255 | KERNEL_INSTALL := 1 256 | BOARD_NAME := db149 257 | DEVICE_TITLE := Qualcomm DB149 258 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 259 | endef 260 | TARGET_DEVICES += qcom_ipq8064-db149 261 | 262 | define Device/tplink_c2600 263 | $(call Device/TpSafeImage) 264 | DEVICE_DTS := qcom-ipq8064-c2600 265 | BLOCKSIZE := 128k 266 | PAGESIZE := 2048 267 | BOARD_NAME := c2600 268 | SUPPORTED_DEVICES += c2600 269 | TPLINK_BOARD_ID := C2600 270 | DEVICE_TITLE := TP-Link Archer C2600 271 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 272 | endef 273 | TARGET_DEVICES += tplink_c2600 274 | 275 | define Device/tplink_vr2600v 276 | KERNEL_SUFFIX := -uImage 277 | KERNEL = kernel-bin | append-dtb | uImage none 278 | KERNEL_NAME := zImage 279 | KERNEL_SIZE := 2097152 280 | DEVICE_DTS := qcom-ipq8064-vr2600v 281 | BLOCKSIZE := 128k 282 | PAGESIZE := 2048 283 | BOARD_NAME := vr2600v 284 | SUPPORTED_DEVICES += vr2600v 285 | DEVICE_TITLE := TP-Link Archer VR2600v 286 | DEVICE_PACKAGES := ath10k-firmware-qca99x0 287 | IMAGES := sysupgrade.bin 288 | IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata 289 | endef 290 | TARGET_DEVICES += tplink_vr2600v 291 | 292 | define Device/zyxel_nbg6817 293 | DEVICE_DTS := qcom-ipq8065-nbg6817 294 | KERNEL_SIZE := 4096k 295 | BLOCKSIZE := 64k 296 | BOARD_NAME := nbg6817 297 | SUPPORTED_DEVICES += nbg6817 298 | DEVICE_TITLE := ZyXEL NBG6817 299 | DEVICE_PACKAGES := ath10k-firmware-qca9984 e2fsprogs kmod-fs-ext4 losetup 300 | $(call Device/ZyXELImage) 301 | endef 302 | TARGET_DEVICES += zyxel_nbg6817 303 | 304 | $(eval $(call BuildImage)) 305 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch: -------------------------------------------------------------------------------- 1 | From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001 2 | From: Matthew McClintock 3 | Date: Thu, 17 Mar 2016 15:01:09 -0500 4 | Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq 5 | support 6 | 7 | This adds some operating points for cpu frequeny scaling 8 | 9 | Signed-off-by: Matthew McClintock 10 | --- 11 | arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++-------- 12 | 1 file changed, 26 insertions(+), 8 deletions(-) 13 | 14 | --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi 15 | +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi 16 | @@ -40,14 +40,7 @@ 17 | reg = <0x0>; 18 | clocks = <&gcc GCC_APPS_CLK_SRC>; 19 | clock-frequency = <0>; 20 | - operating-points = < 21 | - /* kHz uV (fixed) */ 22 | - 48000 1100000 23 | - 200000 1100000 24 | - 500000 1100000 25 | - 666000 1100000 26 | - >; 27 | - clock-latency = <256000>; 28 | + operating-points-v2 = <&cpu0_opp_table>; 29 | }; 30 | 31 | cpu@1 { 32 | @@ -59,6 +52,7 @@ 33 | reg = <0x1>; 34 | clocks = <&gcc GCC_APPS_CLK_SRC>; 35 | clock-frequency = <0>; 36 | + operating-points-v2 = <&cpu0_opp_table>; 37 | }; 38 | 39 | cpu@2 { 40 | @@ -70,6 +64,7 @@ 41 | reg = <0x2>; 42 | clocks = <&gcc GCC_APPS_CLK_SRC>; 43 | clock-frequency = <0>; 44 | + operating-points-v2 = <&cpu0_opp_table>; 45 | }; 46 | 47 | cpu@3 { 48 | @@ -81,6 +76,29 @@ 49 | reg = <0x3>; 50 | clocks = <&gcc GCC_APPS_CLK_SRC>; 51 | clock-frequency = <0>; 52 | + operating-points-v2 = <&cpu0_opp_table>; 53 | + }; 54 | + }; 55 | + 56 | + cpu0_opp_table: opp_table0 { 57 | + compatible = "operating-points-v2"; 58 | + opp-shared; 59 | + 60 | + opp-48000000 { 61 | + opp-hz = /bits/ 64 <48000000>; 62 | + clock-latency-ns = <256000>; 63 | + }; 64 | + opp-200000000 { 65 | + opp-hz = /bits/ 64 <200000000>; 66 | + clock-latency-ns = <256000>; 67 | + }; 68 | + opp-500000000 { 69 | + opp-hz = /bits/ 64 <500000000>; 70 | + clock-latency-ns = <256000>; 71 | + }; 72 | + opp-716800000 { 73 | + opp-hz = /bits/ 64 <716800000>; 74 | + clock-latency-ns = <256000>; 75 | }; 76 | }; 77 | 78 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch: -------------------------------------------------------------------------------- 1 | From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001 2 | From: John Crispin 3 | Date: Thu, 9 Mar 2017 11:03:18 +0100 4 | Subject: [PATCH 69/69] arm: boot: add dts files 5 | 6 | Signed-off-by: John Crispin 7 | --- 8 | arch/arm/boot/dts/Makefile | 8 ++++++++ 9 | 1 file changed, 8 insertions(+) 10 | 11 | --- a/arch/arm/boot/dts/Makefile 12 | +++ b/arch/arm/boot/dts/Makefile 13 | @@ -616,9 +616,20 @@ dtb-$(CONFIG_ARCH_QCOM) += \ 14 | qcom-apq8074-dragonboard.dtb \ 15 | qcom-apq8084-ifc6540.dtb \ 16 | qcom-apq8084-mtp.dtb \ 17 | + qcom-ipq4019-a42.dtb \ 18 | qcom-ipq4019-ap.dk01.1-c1.dtb \ 19 | qcom-ipq4019-ap.dk04.1-c1.dtb \ 20 | + qcom-ipq4019-fritz4040.dtb \ 21 | + qcom-ipq4029-mr33.dtb \ 22 | qcom-ipq8064-ap148.dtb \ 23 | + qcom-ipq8064-c2600.dtb \ 24 | + qcom-ipq8064-d7800.dtb \ 25 | + qcom-ipq8064-db149.dtb \ 26 | + qcom-ipq8064-ea8500.dtb \ 27 | + qcom-ipq8064-r7500.dtb \ 28 | + qcom-ipq8064-r7500v2.dtb \ 29 | + qcom-ipq8065-nbg6817.dtb \ 30 | + qcom-ipq8065-r7800.dtb \ 31 | qcom-msm8660-surf.dtb \ 32 | qcom-msm8960-cdp.dtb \ 33 | qcom-msm8974-lge-nexus5-hammerhead.dtb \ 34 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/131-pinctrl-qcom-ipq4019-add-remaining-pin-definitions.patch: -------------------------------------------------------------------------------- 1 | From 941e3869bdeddb2bebcc52ebfd57efe014887bc6 Mon Sep 17 00:00:00 2001 2 | Message-Id: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com> 3 | In-Reply-To: 4 | References: 5 | From: Ram Chandra Jangir 6 | Date: Wed, 10 May 2017 12:51:51 +0200 7 | Subject: [PATCH v3 2/3] pinctrl: qcom: ipq4019: add most remaining pin 8 | definitions 9 | To: linux-gpio@vger.kernel.org, 10 | devicetree@vger.kernel.org 11 | Cc: Linus Walleij , 12 | Rob Herring , 13 | Mark Rutland 14 | 15 | This patch adds multiple pinctrl functions and mappings 16 | for SDIO, NAND, I2S, WIFI, PCIE, LEDs, etc... that have 17 | been missing from the current minimal version. 18 | 19 | This patch has been updated from the original version 20 | that was posted by Ram Chandra Jangir on the LEDE-DEV ML: 21 | . A short 22 | summary of the changes are documented in the device-tree 23 | patch of this series: 24 | "dt-bindings: pinctrl: add most other IPQ4019 pin functions and groups" 25 | 26 | Cc: Bjorn Andersson 27 | Cc: John Crispin 28 | Signed-off-by: Ram Chandra Jangir 29 | Signed-off-by: Christian Lamparter 30 | --- 31 | drivers/pinctrl/qcom/pinctrl-ipq4019.c | 431 ++++++++++++++++++++++++++------- 32 | 1 file changed, 346 insertions(+), 85 deletions(-) 33 | 34 | --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 35 | +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c 36 | @@ -277,12 +277,49 @@ DECLARE_QCA_GPIO_PINS(99); 37 | 38 | enum ipq4019_functions { 39 | qca_mux_gpio, 40 | - qca_mux_blsp_uart1, 41 | + qca_mux_aud_pin, 42 | + qca_mux_audio_pwm, 43 | qca_mux_blsp_i2c0, 44 | qca_mux_blsp_i2c1, 45 | - qca_mux_blsp_uart0, 46 | - qca_mux_blsp_spi1, 47 | qca_mux_blsp_spi0, 48 | + qca_mux_blsp_spi1, 49 | + qca_mux_blsp_uart0, 50 | + qca_mux_blsp_uart1, 51 | + qca_mux_chip_rst, 52 | + qca_mux_i2s_rx, 53 | + qca_mux_i2s_spdif_in, 54 | + qca_mux_i2s_spdif_out, 55 | + qca_mux_i2s_td, 56 | + qca_mux_i2s_tx, 57 | + qca_mux_jtag, 58 | + qca_mux_led0, 59 | + qca_mux_led1, 60 | + qca_mux_led2, 61 | + qca_mux_led3, 62 | + qca_mux_led4, 63 | + qca_mux_led5, 64 | + qca_mux_led6, 65 | + qca_mux_led7, 66 | + qca_mux_led8, 67 | + qca_mux_led9, 68 | + qca_mux_led10, 69 | + qca_mux_led11, 70 | + qca_mux_mdc, 71 | + qca_mux_mdio, 72 | + qca_mux_pcie, 73 | + qca_mux_pmu, 74 | + qca_mux_prng_rosc, 75 | + qca_mux_qpic, 76 | + qca_mux_rgmii, 77 | + qca_mux_rmii, 78 | + qca_mux_sdio, 79 | + qca_mux_smart0, 80 | + qca_mux_smart1, 81 | + qca_mux_smart2, 82 | + qca_mux_smart3, 83 | + qca_mux_tm, 84 | + qca_mux_wifi0, 85 | + qca_mux_wifi1, 86 | qca_mux_NA, 87 | }; 88 | 89 | @@ -303,108 +340,331 @@ static const char * const gpio_groups[] 90 | "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 91 | "gpio99", 92 | }; 93 | - 94 | -static const char * const blsp_uart1_groups[] = { 95 | - "gpio8", "gpio9", "gpio10", "gpio11", 96 | +static const char * const aud_pin_groups[] = { 97 | + "gpio48", "gpio49", "gpio50", "gpio51", 98 | +}; 99 | +static const char * const audio_pwm_groups[] = { 100 | + "gpio30", "gpio31", "gpio32", "gpio33", "gpio64", "gpio65", "gpio66", 101 | + "gpio67", 102 | }; 103 | static const char * const blsp_i2c0_groups[] = { 104 | "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59", 105 | }; 106 | -static const char * const blsp_spi0_groups[] = { 107 | - "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", 108 | - "gpio54", "gpio55", "gpio56", "gpio57", 109 | -}; 110 | static const char * const blsp_i2c1_groups[] = { 111 | "gpio12", "gpio13", "gpio34", "gpio35", 112 | }; 113 | -static const char * const blsp_uart0_groups[] = { 114 | - "gpio16", "gpio17", "gpio60", "gpio61", 115 | +static const char * const blsp_spi0_groups[] = { 116 | + "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", "gpio54", "gpio55", 117 | + "gpio56", "gpio57", 118 | }; 119 | static const char * const blsp_spi1_groups[] = { 120 | "gpio44", "gpio45", "gpio46", "gpio47", 121 | }; 122 | +static const char * const blsp_uart0_groups[] = { 123 | + "gpio16", "gpio17", "gpio60", "gpio61", 124 | +}; 125 | +static const char * const blsp_uart1_groups[] = { 126 | + "gpio8", "gpio9", "gpio10", "gpio11", 127 | +}; 128 | +static const char * const chip_rst_groups[] = { 129 | + "gpio62", 130 | +}; 131 | +static const char * const i2s_rx_groups[] = { 132 | + "gpio0", "gpio1", "gpio2", "gpio20", "gpio21", "gpio22", "gpio23", 133 | + "gpio58", "gpio60", "gpio61", "gpio63", 134 | +}; 135 | +static const char * const i2s_spdif_in_groups[] = { 136 | + "gpio34", "gpio59", "gpio63", 137 | +}; 138 | +static const char * const i2s_spdif_out_groups[] = { 139 | + "gpio35", "gpio62", "gpio63", 140 | +}; 141 | +static const char * const i2s_td_groups[] = { 142 | + "gpio27", "gpio28", "gpio29", "gpio54", "gpio55", "gpio56", "gpio63", 143 | +}; 144 | +static const char * const i2s_tx_groups[] = { 145 | + "gpio24", "gpio25", "gpio26", "gpio52", "gpio53", "gpio57", "gpio60", 146 | + "gpio61", 147 | +}; 148 | +static const char * const jtag_groups[] = { 149 | + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 150 | +}; 151 | +static const char * const led0_groups[] = { 152 | + "gpio16", "gpio36", "gpio60", 153 | +}; 154 | +static const char * const led1_groups[] = { 155 | + "gpio17", "gpio37", "gpio61", 156 | +}; 157 | +static const char * const led2_groups[] = { 158 | + "gpio36", "gpio38", "gpio58", 159 | +}; 160 | +static const char * const led3_groups[] = { 161 | + "gpio39", 162 | +}; 163 | +static const char * const led4_groups[] = { 164 | + "gpio40", 165 | +}; 166 | +static const char * const led5_groups[] = { 167 | + "gpio44", 168 | +}; 169 | +static const char * const led6_groups[] = { 170 | + "gpio45", 171 | +}; 172 | +static const char * const led7_groups[] = { 173 | + "gpio46", 174 | +}; 175 | +static const char * const led8_groups[] = { 176 | + "gpio47", 177 | +}; 178 | +static const char * const led9_groups[] = { 179 | + "gpio48", 180 | +}; 181 | +static const char * const led10_groups[] = { 182 | + "gpio49", 183 | +}; 184 | +static const char * const led11_groups[] = { 185 | + "gpio50", 186 | +}; 187 | +static const char * const mdc_groups[] = { 188 | + "gpio7", "gpio52", 189 | +}; 190 | +static const char * const mdio_groups[] = { 191 | + "gpio6", "gpio53", 192 | +}; 193 | +static const char * const pcie_groups[] = { 194 | + "gpio39", "gpio52", 195 | +}; 196 | +static const char * const pmu_groups[] = { 197 | + "gpio54", "gpio55", 198 | +}; 199 | +static const char * const prng_rosc_groups[] = { 200 | + "gpio53", 201 | +}; 202 | +static const char * const qpic_groups[] = { 203 | + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", 204 | + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 205 | + "gpio66", "gpio67", "gpio68", "gpio69", 206 | +}; 207 | +static const char * const rgmii_groups[] = { 208 | + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 209 | + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", 210 | +}; 211 | +static const char * const rmii_groups[] = { 212 | + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 213 | + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 214 | + "gpio50", "gpio51", 215 | +}; 216 | +static const char * const sdio_groups[] = { 217 | + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 218 | + "gpio30", "gpio31", "gpio32", 219 | +}; 220 | +static const char * const smart0_groups[] = { 221 | + "gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46", 222 | + "gpio47", 223 | +}; 224 | +static const char * const smart1_groups[] = { 225 | + "gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60", 226 | + "gpio61", 227 | +}; 228 | +static const char * const smart2_groups[] = { 229 | + "gpio40", "gpio41", "gpio48", "gpio49", 230 | +}; 231 | +static const char * const smart3_groups[] = { 232 | + "gpio58", "gpio59", "gpio60", "gpio61", 233 | +}; 234 | +static const char * const tm_groups[] = { 235 | + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", 236 | + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 237 | +}; 238 | +static const char * const wifi0_groups[] = { 239 | + "gpio37", "gpio40", "gpio41", "gpio42", "gpio50", "gpio51", "gpio52", 240 | + "gpio53", "gpio56", "gpio57", "gpio58", "gpio98", 241 | +}; 242 | +static const char * const wifi1_groups[] = { 243 | + "gpio37", "gpio40", "gpio41", "gpio43", "gpio50", "gpio51", "gpio52", 244 | + "gpio53", "gpio56", "gpio57", "gpio58", "gpio98", 245 | +}; 246 | 247 | static const struct msm_function ipq4019_functions[] = { 248 | - FUNCTION(gpio), 249 | - FUNCTION(blsp_uart1), 250 | + FUNCTION(aud_pin), 251 | + FUNCTION(audio_pwm), 252 | FUNCTION(blsp_i2c0), 253 | FUNCTION(blsp_i2c1), 254 | - FUNCTION(blsp_uart0), 255 | - FUNCTION(blsp_spi1), 256 | FUNCTION(blsp_spi0), 257 | + FUNCTION(blsp_spi1), 258 | + FUNCTION(blsp_uart0), 259 | + FUNCTION(blsp_uart1), 260 | + FUNCTION(chip_rst), 261 | + FUNCTION(gpio), 262 | + FUNCTION(i2s_rx), 263 | + FUNCTION(i2s_spdif_in), 264 | + FUNCTION(i2s_spdif_out), 265 | + FUNCTION(i2s_td), 266 | + FUNCTION(i2s_tx), 267 | + FUNCTION(jtag), 268 | + FUNCTION(led0), 269 | + FUNCTION(led1), 270 | + FUNCTION(led2), 271 | + FUNCTION(led3), 272 | + FUNCTION(led4), 273 | + FUNCTION(led5), 274 | + FUNCTION(led6), 275 | + FUNCTION(led7), 276 | + FUNCTION(led8), 277 | + FUNCTION(led9), 278 | + FUNCTION(led10), 279 | + FUNCTION(led11), 280 | + FUNCTION(mdc), 281 | + FUNCTION(mdio), 282 | + FUNCTION(pcie), 283 | + FUNCTION(pmu), 284 | + FUNCTION(prng_rosc), 285 | + FUNCTION(qpic), 286 | + FUNCTION(rgmii), 287 | + FUNCTION(rmii), 288 | + FUNCTION(sdio), 289 | + FUNCTION(smart0), 290 | + FUNCTION(smart1), 291 | + FUNCTION(smart2), 292 | + FUNCTION(smart3), 293 | + FUNCTION(tm), 294 | + FUNCTION(wifi0), 295 | + FUNCTION(wifi1), 296 | }; 297 | 298 | static const struct msm_pingroup ipq4019_groups[] = { 299 | - PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 300 | - PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 301 | - PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 302 | - PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 303 | - PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 304 | - PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 305 | - PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 306 | - PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 307 | - PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 308 | - PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 309 | - PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 310 | - PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 311 | - PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 312 | - PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 313 | - PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 314 | - PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 315 | - PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 316 | - PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 317 | + PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 318 | + NA, NA), 319 | + PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 320 | + NA, NA), 321 | + PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 322 | + NA, NA), 323 | + PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 324 | + PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 325 | + PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 326 | + NA), 327 | + PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 328 | + PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 329 | + PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, 330 | + NA, NA, NA), 331 | + PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, 332 | + NA, NA, NA), 333 | + PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, 334 | + NA, NA, NA), 335 | + PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, 336 | + NA, NA, NA), 337 | + PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, 338 | + NA, NA, NA), 339 | + PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, 340 | + NA, NA, NA), 341 | + PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 342 | + NA), 343 | + PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 344 | + NA), 345 | + PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA, 346 | + NA, NA, NA), 347 | + PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA, 348 | + NA, NA, NA), 349 | PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 350 | PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 351 | - PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 352 | - PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 353 | - PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 354 | - PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 355 | - PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 356 | - PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 357 | - PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 358 | - PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 359 | - PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 360 | - PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 361 | - PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 362 | - PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 363 | - PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 364 | - PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 365 | - PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 366 | - PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 367 | - PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 368 | - PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 369 | - PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 370 | - PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 371 | - PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 372 | - PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 373 | - PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 374 | - PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 375 | - PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 376 | - PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 377 | - PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 378 | - PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 379 | - PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 380 | - PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 381 | - PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 382 | - PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 383 | - PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 384 | - PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 385 | - PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 386 | - PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 387 | - PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 388 | - PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 389 | - PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 390 | - PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 391 | - PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 392 | - PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 393 | - PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 394 | - PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 395 | - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 396 | - PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 397 | - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 398 | - PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 399 | - PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 400 | - PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 401 | + PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 402 | + NA, NA), 403 | + PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 404 | + NA, NA), 405 | + PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 406 | + NA), 407 | + PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 408 | + NA, NA), 409 | + PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 410 | + NA, NA), 411 | + PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 412 | + NA, NA), 413 | + PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, 414 | + NA, NA), 415 | + PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, 416 | + NA, NA), 417 | + PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, 418 | + NA, NA), 419 | + PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, 420 | + NA, NA), 421 | + PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, 422 | + NA, NA, NA), 423 | + PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, 424 | + NA, NA, NA), 425 | + PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, 426 | + NA, NA, NA), 427 | + PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 428 | + NA, NA), 429 | + PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA, 430 | + NA, NA, NA, NA), 431 | + PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA, 432 | + NA, NA, NA, NA), 433 | + PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 434 | + NA), 435 | + PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA, 436 | + NA, NA), 437 | + PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 438 | + NA), 439 | + PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 440 | + NA), 441 | + PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA, 442 | + NA, NA, NA), 443 | + PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA, 444 | + NA, NA, NA), 445 | + PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 446 | + NA), 447 | + PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 448 | + NA), 449 | + PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA, 450 | + NA, NA, NA), 451 | + PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA, 452 | + NA, NA, NA, NA, NA), 453 | + PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA, 454 | + NA, NA, NA), 455 | + PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA, 456 | + NA, NA, NA), 457 | + PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA, 458 | + NA, NA, NA), 459 | + PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA, 460 | + NA, NA, NA), 461 | + PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA, 462 | + NA, NA, NA, NA), 463 | + PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, 464 | + NA, NA, NA), 465 | + PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA, 466 | + NA, NA, NA), 467 | + PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA, 468 | + NA, NA, NA, NA, NA), 469 | + PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, 470 | + NA, NA, NA), 471 | + PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, 472 | + NA, NA, NA), 473 | + PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA, 474 | + NA, NA, NA, NA), 475 | + PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA, 476 | + NA, NA, NA, NA), 477 | + PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm, 478 | + wifi0, wifi1, NA, NA, NA), 479 | + PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA, 480 | + NA, NA, tm, NA, NA, NA), 481 | + PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx, 482 | + NA, NA, NA, NA, NA, tm, NA), 483 | + PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx, 484 | + NA, NA, NA, NA, NA, tm, NA), 485 | + PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA, 486 | + tm, NA, NA, NA), 487 | + PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out, 488 | + i2s_spdif_in, NA, NA, NA, NA, tm, NA), 489 | + PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 490 | + NA, NA), 491 | + PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 492 | + NA, NA), 493 | + PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 494 | + NA, NA), 495 | + PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 496 | + NA, NA), 497 | + PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 498 | + PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 499 | PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 500 | PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 501 | PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 502 | @@ -433,7 +693,8 @@ static const struct msm_pingroup ipq4019 503 | PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 504 | PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 505 | PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 506 | - PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 507 | + PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, 508 | + NA), 509 | PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 510 | }; 511 | 512 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/132-pinctrl-qcom-add-support-to-configure-ipq40xx-GPIO_P.patch: -------------------------------------------------------------------------------- 1 | From 895bbe5061fe2a6825503f57263a4eff9bb78a3c Mon Sep 17 00:00:00 2001 2 | Message-Id: <895bbe5061fe2a6825503f57263a4eff9bb78a3c.1500038134.git.chunkeey@googlemail.com> 3 | In-Reply-To: <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com> 4 | References: 5 | <941e3869bdeddb2bebcc52ebfd57efe014887bc6.1500038134.git.chunkeey@googlemail.com> 6 | From: Ram Chandra Jangir 7 | Date: Sun, 4 Jun 2017 21:38:21 +0200 8 | Subject: [PATCH v3 3/3] pinctrl: msm: add support to configure ipq40xx 9 | GPIO_PULL bits 10 | To: linux-gpio@vger.kernel.org, 11 | devicetree@vger.kernel.org 12 | Cc: Linus Walleij , 13 | Rob Herring , 14 | Mark Rutland 15 | 16 | GPIO_PULL bits configurations in TLMM_GPIO_CFG register 17 | differs for IPQ40xx from rest of the other qcom SoCs. 18 | As it does not support the keeper state and therefore can't 19 | support bias-bus-hold property. 20 | 21 | This patch adds a pull_no_keeper setting which configures the 22 | msm_gpio_pull bits for ipq40xx. This is required to fix the 23 | proper configurations of gpio-pull bits for nand pins mux. 24 | 25 | IPQ40xx SoC: 26 | 2'b10: Internal pull up enable. 27 | 2'b11: Unsupport 28 | 29 | For other SoC's: 30 | 2'b10: Keeper 31 | 2'b11: Pull-Up 32 | 33 | Note: Due to pull_no_keeper length, all kerneldoc entries 34 | in the msm_pinctrl_soc_data struct had to be realigned. 35 | 36 | Reviewed-by: Bjorn Andersson 37 | Signed-off-by: Ram Chandra Jangir 38 | Signed-off-by: Christian Lamparter 39 | --- 40 | drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 + 41 | drivers/pinctrl/qcom/pinctrl-msm.c | 25 +++++++++++++++++++------ 42 | drivers/pinctrl/qcom/pinctrl-msm.h | 16 +++++++++------- 43 | 3 files changed, 29 insertions(+), 13 deletions(-) 44 | 45 | --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c 46 | +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c 47 | @@ -706,6 +706,7 @@ static const struct msm_pinctrl_soc_data 48 | .groups = ipq4019_groups, 49 | .ngroups = ARRAY_SIZE(ipq4019_groups), 50 | .ngpios = 100, 51 | + .pull_no_keeper = true, 52 | }; 53 | 54 | static int ipq4019_pinctrl_probe(struct platform_device *pdev) 55 | --- a/drivers/pinctrl/qcom/pinctrl-msm.c 56 | +++ b/drivers/pinctrl/qcom/pinctrl-msm.c 57 | @@ -203,10 +203,11 @@ static int msm_config_reg(struct msm_pin 58 | return 0; 59 | } 60 | 61 | -#define MSM_NO_PULL 0 62 | -#define MSM_PULL_DOWN 1 63 | -#define MSM_KEEPER 2 64 | -#define MSM_PULL_UP 3 65 | +#define MSM_NO_PULL 0 66 | +#define MSM_PULL_DOWN 1 67 | +#define MSM_KEEPER 2 68 | +#define MSM_PULL_UP_NO_KEEPER 2 69 | +#define MSM_PULL_UP 3 70 | 71 | static unsigned msm_regval_to_drive(u32 val) 72 | { 73 | @@ -244,10 +245,16 @@ static int msm_config_group_get(struct p 74 | arg = arg == MSM_PULL_DOWN; 75 | break; 76 | case PIN_CONFIG_BIAS_BUS_HOLD: 77 | + if (pctrl->soc->pull_no_keeper) 78 | + return -ENOTSUPP; 79 | + 80 | arg = arg == MSM_KEEPER; 81 | break; 82 | case PIN_CONFIG_BIAS_PULL_UP: 83 | - arg = arg == MSM_PULL_UP; 84 | + if (pctrl->soc->pull_no_keeper) 85 | + arg = arg == MSM_PULL_UP_NO_KEEPER; 86 | + else 87 | + arg = arg == MSM_PULL_UP; 88 | break; 89 | case PIN_CONFIG_DRIVE_STRENGTH: 90 | arg = msm_regval_to_drive(arg); 91 | @@ -310,10 +317,16 @@ static int msm_config_group_set(struct p 92 | arg = MSM_PULL_DOWN; 93 | break; 94 | case PIN_CONFIG_BIAS_BUS_HOLD: 95 | + if (pctrl->soc->pull_no_keeper) 96 | + return -ENOTSUPP; 97 | + 98 | arg = MSM_KEEPER; 99 | break; 100 | case PIN_CONFIG_BIAS_PULL_UP: 101 | - arg = MSM_PULL_UP; 102 | + if (pctrl->soc->pull_no_keeper) 103 | + arg = MSM_PULL_UP_NO_KEEPER; 104 | + else 105 | + arg = MSM_PULL_UP; 106 | break; 107 | case PIN_CONFIG_DRIVE_STRENGTH: 108 | /* Check for invalid values */ 109 | --- a/drivers/pinctrl/qcom/pinctrl-msm.h 110 | +++ b/drivers/pinctrl/qcom/pinctrl-msm.h 111 | @@ -99,13 +99,14 @@ struct msm_pingroup { 112 | 113 | /** 114 | * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 115 | - * @pins: An array describing all pins the pin controller affects. 116 | - * @npins: The number of entries in @pins. 117 | - * @functions: An array describing all mux functions the SoC supports. 118 | - * @nfunctions: The number of entries in @functions. 119 | - * @groups: An array describing all pin groups the pin SoC supports. 120 | - * @ngroups: The numbmer of entries in @groups. 121 | - * @ngpio: The number of pingroups the driver should expose as GPIOs. 122 | + * @pins: An array describing all pins the pin controller affects. 123 | + * @npins: The number of entries in @pins. 124 | + * @functions: An array describing all mux functions the SoC supports. 125 | + * @nfunctions: The number of entries in @functions. 126 | + * @groups: An array describing all pin groups the pin SoC supports. 127 | + * @ngroups: The numbmer of entries in @groups. 128 | + * @ngpio: The number of pingroups the driver should expose as GPIOs. 129 | + * @pull_no_keeper: The SoC does not support keeper bias. 130 | */ 131 | struct msm_pinctrl_soc_data { 132 | const struct pinctrl_pin_desc *pins; 133 | @@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data { 134 | const struct msm_pingroup *groups; 135 | unsigned ngroups; 136 | unsigned ngpios; 137 | + bool pull_no_keeper; 138 | }; 139 | 140 | int msm_pinctrl_probe(struct platform_device *pdev, 141 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/712-mr33-essedma.patch: -------------------------------------------------------------------------------- 1 | --- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c 2 | +++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c 3 | @@ -17,6 +17,11 @@ 4 | #include 5 | #include 6 | #include 7 | +#include 8 | +#include 9 | +#include 10 | +#include 11 | +#include 12 | #include "edma.h" 13 | #include "ess_edma.h" 14 | 15 | @@ -83,7 +88,103 @@ void edma_read_reg(u16 reg_addr, volatil 16 | *reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr)); 17 | } 18 | 19 | -/* edma_change_tx_coalesce() 20 | +static void ess_write_reg(struct edma_common_info *edma, u16 reg_addr, u32 reg_value) 21 | +{ 22 | + writel(reg_value, ((void __iomem *) 23 | + ((unsigned long)edma->ess_hw_addr + reg_addr))); 24 | +} 25 | + 26 | +static void ess_read_reg(struct edma_common_info *edma, u16 reg_addr, 27 | + volatile u32 *reg_value) 28 | +{ 29 | + *reg_value = readl((void __iomem *) 30 | + ((unsigned long)edma->ess_hw_addr + reg_addr)); 31 | +} 32 | + 33 | +static int ess_reset(struct edma_common_info *edma) 34 | +{ 35 | + struct device_node *switch_node = NULL; 36 | + struct reset_control *ess_rst; 37 | + u32 regval; 38 | + 39 | + switch_node = of_find_node_by_name(NULL, "ess-switch"); 40 | + if (!switch_node) { 41 | + pr_err("switch-node not found\n"); 42 | + return -EINVAL; 43 | + } 44 | + 45 | + ess_rst = of_reset_control_get(switch_node, "ess_rst"); 46 | + of_node_put(switch_node); 47 | + 48 | + if (IS_ERR(ess_rst)) { 49 | + pr_err("failed to find ess_rst!\n"); 50 | + return -ENOENT; 51 | + } 52 | + 53 | + reset_control_assert(ess_rst); 54 | + msleep(10); 55 | + reset_control_deassert(ess_rst); 56 | + msleep(100); 57 | + reset_control_put(ess_rst); 58 | + 59 | + /* Enable only port 5 <--> port 0 60 | + * bits 0:6 bitmap of ports it can fwd to */ 61 | +#define SET_PORT_BMP(r,v) \ 62 | + ess_read_reg(edma, r, ®val); \ 63 | + ess_write_reg(edma, r, ((regval & ~0x3F) | v)); 64 | + 65 | + SET_PORT_BMP(ESS_PORT0_LOOKUP_CTRL,0x20); 66 | + SET_PORT_BMP(ESS_PORT1_LOOKUP_CTRL,0x00); 67 | + SET_PORT_BMP(ESS_PORT2_LOOKUP_CTRL,0x00); 68 | + SET_PORT_BMP(ESS_PORT3_LOOKUP_CTRL,0x00); 69 | + SET_PORT_BMP(ESS_PORT4_LOOKUP_CTRL,0x00); 70 | + SET_PORT_BMP(ESS_PORT5_LOOKUP_CTRL,0x01); 71 | + ess_write_reg(edma, ESS_RGMII_CTRL, 0x400); 72 | + ess_write_reg(edma, ESS_PORT0_STATUS, ESS_PORT_1G_FDX); 73 | + ess_write_reg(edma, ESS_PORT5_STATUS, ESS_PORT_1G_FDX); 74 | + ess_write_reg(edma, ESS_PORT0_HEADER_CTRL, 0); 75 | +#undef SET_PORT_BMP 76 | + 77 | + /* forward multicast and broadcast frames to CPU */ 78 | + ess_write_reg(edma, ESS_FWD_CTRL1, 79 | + (ESS_PORTS_ALL << ESS_FWD_CTRL1_UC_FLOOD_S) | 80 | + (ESS_PORTS_ALL << ESS_FWD_CTRL1_MC_FLOOD_S) | 81 | + (ESS_PORTS_ALL << ESS_FWD_CTRL1_BC_FLOOD_S)); 82 | + 83 | + return 0; 84 | +} 85 | + 86 | +void ess_set_port_status_speed(struct edma_common_info *edma, 87 | + struct phy_device *phydev, uint8_t port_id) 88 | +{ 89 | + uint16_t reg_off = ESS_PORT0_STATUS + (4 * port_id); 90 | + uint32_t reg_val = 0; 91 | + 92 | + ess_read_reg(edma, reg_off, ®_val); 93 | + 94 | + /* reset the speed bits [0:1] */ 95 | + reg_val &= ~ESS_PORT_STATUS_SPEED_INV; 96 | + 97 | + /* set the new speed */ 98 | + switch(phydev->speed) { 99 | + case SPEED_1000: reg_val |= ESS_PORT_STATUS_SPEED_1000; break; 100 | + case SPEED_100: reg_val |= ESS_PORT_STATUS_SPEED_100; break; 101 | + case SPEED_10: reg_val |= ESS_PORT_STATUS_SPEED_10; break; 102 | + default: reg_val |= ESS_PORT_STATUS_SPEED_INV; break; 103 | + } 104 | + 105 | + /* check full/half duplex */ 106 | + if (phydev->duplex) { 107 | + reg_val |= ESS_PORT_STATUS_DUPLEX_MODE; 108 | + } else { 109 | + reg_val &= ~ESS_PORT_STATUS_DUPLEX_MODE; 110 | + } 111 | + 112 | + ess_write_reg(edma, reg_off, reg_val); 113 | +} 114 | + 115 | +/* 116 | + * edma_change_tx_coalesce() 117 | * change tx interrupt moderation timer 118 | */ 119 | void edma_change_tx_coalesce(int usecs) 120 | @@ -551,6 +652,31 @@ static struct ctl_table edma_table[] = { 121 | {} 122 | }; 123 | 124 | +static int ess_parse(struct edma_common_info *edma) 125 | +{ 126 | + struct device_node *switch_node; 127 | + int ret = -EINVAL; 128 | + 129 | + switch_node = of_find_node_by_name(NULL, "ess-switch"); 130 | + if (!switch_node) { 131 | + pr_err("cannot find ess-switch node\n"); 132 | + goto out; 133 | + } 134 | + 135 | + edma->ess_hw_addr = of_io_request_and_map(switch_node, 136 | + 0, KBUILD_MODNAME); 137 | + if (!edma->ess_hw_addr) { 138 | + pr_err("%s ioremap fail.", __func__); 139 | + goto out; 140 | + } 141 | + 142 | + edma->ess_clk = of_clk_get_by_name(switch_node, "ess_clk"); 143 | + ret = clk_prepare_enable(edma->ess_clk); 144 | +out: 145 | + of_node_put(switch_node); 146 | + return ret; 147 | +} 148 | + 149 | /* edma_axi_netdev_ops 150 | * Describe the operations supported by registered netdevices 151 | * 152 | @@ -787,6 +913,17 @@ static int edma_axi_probe(struct platfor 153 | miibus = mdio_data->mii_bus; 154 | } 155 | 156 | + if (of_property_read_bool(np, "qcom,single-phy") && 157 | + edma_cinfo->num_gmac == 1) { 158 | + err = ess_parse(edma_cinfo); 159 | + if (!err) 160 | + err = ess_reset(edma_cinfo); 161 | + if (err) 162 | + goto err_single_phy_init; 163 | + else 164 | + edma_cinfo->is_single_phy = true; 165 | + } 166 | + 167 | for_each_available_child_of_node(np, pnp) { 168 | const char *mac_addr; 169 | 170 | @@ -1074,11 +1211,15 @@ static int edma_axi_probe(struct platfor 171 | 172 | for (i = 0; i < edma_cinfo->num_gmac; i++) { 173 | if (adapter[i]->poll_required) { 174 | + int phy_mode = of_get_phy_mode(np); 175 | + 176 | + if (phy_mode < 0) 177 | + phy_mode = PHY_INTERFACE_MODE_SGMII; 178 | adapter[i]->phydev = 179 | phy_connect(edma_netdev[i], 180 | (const char *)adapter[i]->phy_id, 181 | &edma_adjust_link, 182 | - PHY_INTERFACE_MODE_SGMII); 183 | + phy_mode); 184 | if (IS_ERR(adapter[i]->phydev)) { 185 | dev_dbg(&pdev->dev, "PHY attach FAIL"); 186 | err = -EIO; 187 | @@ -1125,6 +1266,9 @@ err_rmap_alloc_fail: 188 | for (i = 0; i < edma_cinfo->num_gmac; i++) 189 | unregister_netdev(edma_netdev[i]); 190 | err_register: 191 | +err_single_phy_init: 192 | + iounmap(edma_cinfo->ess_hw_addr); 193 | + clk_disable_unprepare(edma_cinfo->ess_clk); 194 | err_mdiobus_init_fail: 195 | edma_free_rx_rings(edma_cinfo); 196 | err_rx_rinit: 197 | @@ -1185,6 +1329,8 @@ static int edma_axi_remove(struct platfo 198 | del_timer_sync(&edma_stats_timer); 199 | edma_free_irqs(adapter); 200 | unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr); 201 | + iounmap(edma_cinfo->ess_hw_addr); 202 | + clk_disable_unprepare(edma_cinfo->ess_clk); 203 | edma_free_tx_resources(edma_cinfo); 204 | edma_free_rx_resources(edma_cinfo); 205 | edma_free_tx_rings(edma_cinfo); 206 | --- a/drivers/net/ethernet/qualcomm/essedma/edma.c 207 | +++ b/drivers/net/ethernet/qualcomm/essedma/edma.c 208 | @@ -161,8 +161,10 @@ static void edma_configure_rx(struct edm 209 | /* Set Rx FIFO threshold to start to DMA data to host */ 210 | rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE; 211 | 212 | - /* Set RX remove vlan bit */ 213 | - rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN; 214 | + if (!edma_cinfo->is_single_phy) { 215 | + /* Set RX remove vlan bit */ 216 | + rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN; 217 | + } 218 | 219 | edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data); 220 | } 221 | @@ -1295,6 +1297,10 @@ void edma_adjust_link(struct net_device 222 | if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) { 223 | dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed); 224 | adapter->link_state = __EDMA_LINKUP; 225 | + if (adapter->edma_cinfo->is_single_phy) { 226 | + ess_set_port_status_speed(adapter->edma_cinfo, phydev, 227 | + ffs(adapter->dp_bitmap) - 1); 228 | + } 229 | netif_carrier_on(netdev); 230 | if (netif_running(netdev)) 231 | netif_tx_wake_all_queues(netdev); 232 | @@ -1388,10 +1394,12 @@ netdev_tx_t edma_xmit(struct sk_buff *sk 233 | } 234 | 235 | /* Check and mark VLAN tag offload */ 236 | - if (skb_vlan_tag_present(skb)) 237 | - flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG; 238 | - else if (adapter->default_vlan_tag) 239 | - flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG; 240 | + if (!adapter->edma_cinfo->is_single_phy) { 241 | + if (unlikely(skb_vlan_tag_present(skb))) 242 | + flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG; 243 | + else if (adapter->default_vlan_tag) 244 | + flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG; 245 | + } 246 | 247 | /* Check and mark checksum offload */ 248 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) 249 | --- a/drivers/net/ethernet/qualcomm/essedma/edma.h 250 | +++ b/drivers/net/ethernet/qualcomm/essedma/edma.h 251 | @@ -31,6 +31,7 @@ 252 | #include 253 | #include 254 | #include 255 | +#include 256 | #include 257 | #include 258 | #include 259 | @@ -331,6 +332,10 @@ struct edma_common_info { 260 | struct edma_hw hw; /* edma hw specific structure */ 261 | struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */ 262 | spinlock_t stats_lock; /* protect edma stats area for updation */ 263 | + 264 | + bool is_single_phy; 265 | + void __iomem *ess_hw_addr; 266 | + struct clk *ess_clk; 267 | }; 268 | 269 | /* transimit packet descriptor (tpd) ring */ 270 | @@ -444,4 +449,6 @@ void edma_change_tx_coalesce(int usecs); 271 | void edma_change_rx_coalesce(int usecs); 272 | void edma_get_tx_rx_coalesce(u32 *reg_val); 273 | void edma_clear_irq_status(void); 274 | +void ess_set_port_status_speed(struct edma_common_info *edma_cinfo, 275 | + struct phy_device *phydev, uint8_t port_id); 276 | #endif /* _EDMA_H_ */ 277 | --- a/drivers/net/ethernet/qualcomm/essedma/ess_edma.h 278 | +++ b/drivers/net/ethernet/qualcomm/essedma/ess_edma.h 279 | @@ -329,4 +329,61 @@ struct edma_hw; 280 | #define EDMA_RRD_PRIORITY_MASK 0x7 281 | #define EDMA_RRD_PORT_TYPE_SHIFT 7 282 | #define EDMA_RRD_PORT_TYPE_MASK 0x1F 283 | + 284 | +#define ESS_RGMII_CTRL 0x0004 285 | + 286 | +/* Port status registers */ 287 | +#define ESS_PORT0_STATUS 0x007C 288 | +#define ESS_PORT1_STATUS 0x0080 289 | +#define ESS_PORT2_STATUS 0x0084 290 | +#define ESS_PORT3_STATUS 0x0088 291 | +#define ESS_PORT4_STATUS 0x008C 292 | +#define ESS_PORT5_STATUS 0x0090 293 | + 294 | +#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80 295 | +#define ESS_PORT_STATUS_DUPLEX_MODE 0x40 296 | +#define ESS_PORT_STATUS_RX_FLOW_EN 0x20 297 | +#define ESS_PORT_STATUS_TX_FLOW_EN 0x10 298 | +#define ESS_PORT_STATUS_RX_MAC_EN 0x08 299 | +#define ESS_PORT_STATUS_TX_MAC_EN 0x04 300 | +#define ESS_PORT_STATUS_SPEED_INV 0x03 301 | +#define ESS_PORT_STATUS_SPEED_1000 0x02 302 | +#define ESS_PORT_STATUS_SPEED_100 0x01 303 | +#define ESS_PORT_STATUS_SPEED_10 0x00 304 | + 305 | +#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \ 306 | + ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \ 307 | + ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000) 308 | + 309 | +#define PHY_STATUS_REG 0x11 310 | +#define PHY_STATUS_SPEED 0xC000 311 | +#define PHY_STATUS_SPEED_SHIFT 14 312 | +#define PHY_STATUS_DUPLEX 0x2000 313 | +#define PHY_STATUS_DUPLEX_SHIFT 13 314 | +#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800 315 | +#define PHY_STATUS_CARRIER 0x0400 316 | +#define PHY_STATUS_CARRIER_SHIFT 10 317 | + 318 | +/* Port lookup control registers */ 319 | +#define ESS_PORT0_LOOKUP_CTRL 0x0660 320 | +#define ESS_PORT1_LOOKUP_CTRL 0x066C 321 | +#define ESS_PORT2_LOOKUP_CTRL 0x0678 322 | +#define ESS_PORT3_LOOKUP_CTRL 0x0684 323 | +#define ESS_PORT4_LOOKUP_CTRL 0x0690 324 | +#define ESS_PORT5_LOOKUP_CTRL 0x069C 325 | + 326 | +#define ESS_PORT0_HEADER_CTRL 0x009C 327 | + 328 | +#define ESS_PORTS_ALL 0x3f 329 | + 330 | +#define ESS_FWD_CTRL1 0x0624 331 | +#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7) 332 | +#define ESS_FWD_CTRL1_UC_FLOOD_S 0 333 | +#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7) 334 | +#define ESS_FWD_CTRL1_MC_FLOOD_S 8 335 | +#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7) 336 | +#define ESS_FWD_CTRL1_BC_FLOOD_S 16 337 | +#define ESS_FWD_CTRL1_IGMP BITS(24, 7) 338 | +#define ESS_FWD_CTRL1_IGMP_S 24 339 | + 340 | #endif /* _ESS_EDMA_H_ */ 341 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/855-clk-qcom-ipq4019-add-ess-reset.patch: -------------------------------------------------------------------------------- 1 | From 7efb48a343ca368f83359d3a7087dd5ab25a283a Mon Sep 17 00:00:00 2001 2 | From: Ram Chandra Jangir 3 | Date: Tue, 28 Mar 2017 22:35:33 +0530 4 | Subject: [PATCH 5/8] clk: qcom: ipq4019: add ess reset 5 | 6 | Added the ESS reset in IPQ4019 GCC. 7 | 8 | Signed-off-by: Ram Chandra Jangir 9 | --- 10 | drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++ 11 | include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++ 12 | 2 files changed, 22 insertions(+) 13 | 14 | --- a/drivers/clk/qcom/gcc-ipq4019.c 15 | +++ b/drivers/clk/qcom/gcc-ipq4019.c 16 | @@ -1299,6 +1299,17 @@ static const struct qcom_reset_map gcc_i 17 | [GCC_TCSR_BCR] = {0x22000, 0}, 18 | [GCC_MPM_BCR] = {0x24000, 0}, 19 | [GCC_SPDM_BCR] = {0x25000, 0}, 20 | + [ESS_MAC1_ARES] = {0x1200C, 0}, 21 | + [ESS_MAC2_ARES] = {0x1200C, 1}, 22 | + [ESS_MAC3_ARES] = {0x1200C, 2}, 23 | + [ESS_MAC4_ARES] = {0x1200C, 3}, 24 | + [ESS_MAC5_ARES] = {0x1200C, 4}, 25 | + [ESS_PSGMII_ARES] = {0x1200C, 5}, 26 | + [ESS_MAC1_CLK_DIS] = {0x1200C, 8}, 27 | + [ESS_MAC2_CLK_DIS] = {0x1200C, 9}, 28 | + [ESS_MAC3_CLK_DIS] = {0x1200C, 10}, 29 | + [ESS_MAC4_CLK_DIS] = {0x1200C, 11}, 30 | + [ESS_MAC5_CLK_DIS] = {0x1200C, 12}, 31 | }; 32 | 33 | static const struct regmap_config gcc_ipq4019_regmap_config = { 34 | --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h 35 | +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h 36 | @@ -154,5 +154,16 @@ 37 | #define GCC_QDSS_BCR 69 38 | #define GCC_MPM_BCR 70 39 | #define GCC_SPDM_BCR 71 40 | +#define ESS_MAC1_ARES 72 41 | +#define ESS_MAC2_ARES 73 42 | +#define ESS_MAC3_ARES 74 43 | +#define ESS_MAC4_ARES 75 44 | +#define ESS_MAC5_ARES 76 45 | +#define ESS_PSGMII_ARES 77 46 | +#define ESS_MAC1_CLK_DIS 78 47 | +#define ESS_MAC2_CLK_DIS 79 48 | +#define ESS_MAC3_CLK_DIS 80 49 | +#define ESS_MAC4_CLK_DIS 81 50 | +#define ESS_MAC5_CLK_DIS 82 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/857-ipq40xx-Fix-mdio-driver-to-work-with-IPQ40xx-SoC.patch: -------------------------------------------------------------------------------- 1 | From 1d8433be4af4a5862b8805a5668d404bd6fde945 Mon Sep 17 00:00:00 2001 2 | From: Ram Chandra Jangir 3 | Date: Tue, 28 Mar 2017 22:32:07 +0530 4 | Subject: [PATCH] ipq40xx: Fix mdio driver to work with IPQ40xx SoC 5 | 6 | - Add phy-reset-gpio support in probe function to fix hang 7 | at board booting. 8 | - Add proper assignment of mii_bus read/write operations 9 | 10 | Signed-off-by: Ram Chandra Jangir 11 | --- 12 | drivers/net/phy/mdio-ipq40xx.c | 56 +++++++++++++++++++++++++++++++++++++++--- 13 | 1 file changed, 53 insertions(+), 3 deletions(-) 14 | 15 | --- a/drivers/net/phy/mdio-ipq40xx.c 16 | +++ b/drivers/net/phy/mdio-ipq40xx.c 17 | @@ -22,6 +22,7 @@ 18 | #include 19 | #include 20 | #include 21 | +#include 22 | 23 | #define MDIO_CTRL_0_REG 0x40 24 | #define MDIO_CTRL_1_REG 0x44 25 | @@ -122,11 +123,61 @@ static int ipq40xx_mdio_write(struct mii 26 | return 0; 27 | } 28 | 29 | +static int ipq40xx_phy_reset(struct platform_device *pdev) 30 | +{ 31 | + struct device_node *mdio_node; 32 | + int phy_reset_gpio_number; 33 | + int ret; 34 | + 35 | + mdio_node = of_find_node_by_name(NULL, "mdio"); 36 | + if (!mdio_node) { 37 | + dev_err(&pdev->dev, "Could not find mdio node\n"); 38 | + return -ENOENT; 39 | + } 40 | + 41 | + ret = of_get_named_gpio(mdio_node, "phy-reset-gpio", 0); 42 | + if (ret < 0) { 43 | + dev_warn(&pdev->dev, "Could not find DT gpio phy-reset-gpio missing/malformed:%d\n",ret); 44 | + ret = 0; 45 | + return ret; 46 | + } 47 | + 48 | + phy_reset_gpio_number = ret; 49 | + 50 | + ret = gpio_request(phy_reset_gpio_number, "phy-reset-gpio"); 51 | + if (ret) { 52 | + dev_err(&pdev->dev, "Can't get phy-reset-gpio %d\n", ret); 53 | + return ret; 54 | + } 55 | + 56 | + ret = gpio_direction_output(phy_reset_gpio_number, 0x0); 57 | + if (ret) { 58 | + dev_err(&pdev->dev, 59 | + "Can't set direction for phy-reset-gpio %d\n", ret); 60 | + goto phy_reset_out; 61 | + } 62 | + 63 | + usleep_range(1000, 10005); 64 | + 65 | + gpio_set_value(phy_reset_gpio_number, 0x01); 66 | + 67 | +phy_reset_out: 68 | + gpio_free(phy_reset_gpio_number); 69 | + 70 | + return ret; 71 | +} 72 | + 73 | static int ipq40xx_mdio_probe(struct platform_device *pdev) 74 | { 75 | struct ipq40xx_mdio_data *am; 76 | struct resource *res; 77 | - int i; 78 | + int i, ret; 79 | + 80 | + ret = ipq40xx_phy_reset(pdev); 81 | + if (ret) { 82 | + dev_err(&pdev->dev, "Could not find qca8075 reset gpio\n"); 83 | + return ret; 84 | + } 85 | 86 | am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL); 87 | if (!am) 88 | @@ -151,8 +202,8 @@ static int ipq40xx_mdio_probe(struct pla 89 | writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG); 90 | 91 | am->mii_bus->name = "ipq40xx_mdio"; 92 | - am->mii_bus->read = ipq40xx_mdio_read; 93 | - am->mii_bus->write = ipq40xx_mdio_write; 94 | + am->mii_bus->read = &ipq40xx_mdio_read; 95 | + am->mii_bus->write = &ipq40xx_mdio_write; 96 | memcpy(am->mii_bus->irq, am->phy_irq, sizeof(am->phy_irq)); 97 | am->mii_bus->priv = am; 98 | am->mii_bus->parent = &pdev->dev; 99 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/900-ipq4019-pcie-dts-nodes.patch: -------------------------------------------------------------------------------- 1 | --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi 2 | +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi 3 | @@ -633,5 +633,72 @@ 4 | nand-bus-width = <8>; 5 | }; 6 | }; 7 | + 8 | + pcie0: pci@40000000 { 9 | + compatible = "qcom,pcie-ipq4019"; 10 | + reg = <0x40000000 0xf1d 11 | + 0x40000f20 0xa8 12 | + 0x80000 0x2000 13 | + 0x40100000 0x1000>; 14 | + reg-names = "dbi", "elbi", "parf", "config"; 15 | + device_type = "pci"; 16 | + linux,pci-domain = <0>; 17 | + bus-range = <0x00 0xff>; 18 | + num-lanes = <1>; 19 | + #address-cells = <3>; 20 | + #size-cells = <2>; 21 | + 22 | + ranges = <0x81000000 0 0x40200000 0x40200000 23 | + 0 0x00100000 /* downstream I/O */ 24 | + 0x82000000 0 0x40300000 0x40300000 25 | + 0 0x100000 /* non-prefetchable memory */ 26 | + 0x82000000 0 0x40400000 0x40400000 27 | + 0 0x200000>; /* non-prefetchable memory */ 28 | + interrupts = <0 141 0>; 29 | + interrupt-names = "msi"; 30 | + #interrupt-cells = <1>; 31 | + interrupt-map-mask = <0 0 0 0x7>; 32 | + interrupt-map = <0 0 0 1 &intc 0 142 33 | + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 34 | + <0 0 0 2 &intc 0 143 35 | + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 36 | + <0 0 0 3 &intc 0 144 37 | + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 38 | + <0 0 0 4 &intc 0 145 39 | + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 40 | + clocks = <&gcc GCC_PCIE_AHB_CLK>, 41 | + <&gcc GCC_PCIE_AXI_M_CLK>, 42 | + <&gcc GCC_PCIE_AXI_S_CLK>; 43 | + clock-names = "ahb", 44 | + "axi_m", 45 | + "axi_s"; 46 | + 47 | + resets = <&gcc PCIE_AXI_M_ARES>, 48 | + <&gcc PCIE_AXI_S_ARES>, 49 | + <&gcc PCIE_PIPE_ARES>, 50 | + <&gcc PCIE_AXI_M_VMIDMT_ARES>, 51 | + <&gcc PCIE_AXI_S_XPU_ARES>, 52 | + <&gcc PCIE_PARF_XPU_ARES>, 53 | + <&gcc PCIE_PHY_ARES>, 54 | + <&gcc PCIE_AXI_M_STICKY_ARES>, 55 | + <&gcc PCIE_PIPE_STICKY_ARES>, 56 | + <&gcc PCIE_PWR_ARES>, 57 | + <&gcc PCIE_AHB_ARES>, 58 | + <&gcc PCIE_PHY_AHB_ARES>; 59 | + reset-names = "axi_m", 60 | + "axi_s", 61 | + "pipe", 62 | + "axi_m_vmid", 63 | + "axi_s_xpu", 64 | + "parf", 65 | + "phy", 66 | + "axi_m_sticky", 67 | + "pipe_sticky", 68 | + "pwr", 69 | + "ahb", 70 | + "phy_ahb"; 71 | + status = "disabled"; 72 | + }; 73 | + 74 | }; 75 | }; 76 | -------------------------------------------------------------------------------- /overlay/target/linux/ipq806x/patches-4.9/901-ipq4019-pcie.patch: -------------------------------------------------------------------------------- 1 | --- a/drivers/pci/host/pcie-qcom.c 2 | +++ b/drivers/pci/host/pcie-qcom.c 3 | @@ -100,6 +100,13 @@ 4 | #define PCIE20_MPS_MASK __mask(7, 5) 5 | #define PCIE20_MPS(x) __set(x, 7, 5) 6 | 7 | +#define PCIE20_PARF_SYS_CTRL 0x00 8 | +#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 9 | +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 10 | +#define PCIE20_PARF_LTSSM 0x1B0 11 | +#define PCIE20_PARF_SID_OFFSET 0x234 12 | +#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C 13 | + 14 | struct qcom_pcie_resources_v0 { 15 | struct clk *iface_clk; 16 | struct clk *core_clk; 17 | @@ -127,9 +134,31 @@ struct qcom_pcie_resources_v1 { 18 | struct regulator *vdda; 19 | }; 20 | 21 | +struct qcom_pcie_resources_v3 { 22 | + struct clk *ahb_clk; 23 | + struct clk *axi_m_clk; 24 | + struct clk *axi_s_clk; 25 | + struct reset_control *axi_m_reset; 26 | + struct reset_control *axi_s_reset; 27 | + struct reset_control *pipe_reset; 28 | + struct reset_control *axi_m_vmid_reset; 29 | + struct reset_control *axi_s_xpu_reset; 30 | + struct reset_control *parf_reset; 31 | + struct reset_control *phy_reset; 32 | + struct reset_control *axi_m_sticky_reset; 33 | + struct reset_control *pipe_sticky_reset; 34 | + struct reset_control *pwr_reset; 35 | + struct reset_control *ahb_reset; 36 | + struct reset_control *phy_ahb_reset; 37 | + struct regulator *vdda; 38 | + struct regulator *vdda_phy; 39 | + struct regulator *vdda_refclk; 40 | +}; 41 | + 42 | union qcom_pcie_resources { 43 | struct qcom_pcie_resources_v0 v0; 44 | struct qcom_pcie_resources_v1 v1; 45 | + struct qcom_pcie_resources_v3 v3; 46 | }; 47 | 48 | struct qcom_pcie; 49 | @@ -138,6 +167,7 @@ struct qcom_pcie_ops { 50 | int (*get_resources)(struct qcom_pcie *pcie); 51 | int (*init)(struct qcom_pcie *pcie); 52 | void (*deinit)(struct qcom_pcie *pcie); 53 | + void (*ltssm_enable)(struct qcom_pcie *pcie); 54 | }; 55 | 56 | struct qcom_pcie { 57 | @@ -182,17 +212,34 @@ static irqreturn_t qcom_pcie_msi_irq_han 58 | return dw_handle_msi_irq(pp); 59 | } 60 | 61 | -static int qcom_pcie_establish_link(struct qcom_pcie *pcie) 62 | +static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie) 63 | { 64 | u32 val; 65 | 66 | - if (dw_pcie_link_up(&pcie->pp)) 67 | - return 0; 68 | - 69 | /* enable link training */ 70 | val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); 71 | val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE; 72 | writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); 73 | +} 74 | + 75 | +static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie) 76 | +{ 77 | + u32 val; 78 | + 79 | + /* enable link training */ 80 | + val = readl(pcie->parf + PCIE20_PARF_LTSSM); 81 | + val |= BIT(8); 82 | + writel(val, pcie->parf + PCIE20_PARF_LTSSM); 83 | +} 84 | + 85 | +static int qcom_pcie_establish_link(struct qcom_pcie *pcie) 86 | +{ 87 | + if (dw_pcie_link_up(&pcie->pp)) 88 | + return 0; 89 | + 90 | + /* Enable Link Training state machine */ 91 | + if (pcie->ops->ltssm_enable) 92 | + pcie->ops->ltssm_enable(pcie); 93 | 94 | return dw_pcie_wait_for_link(&pcie->pp); 95 | } 96 | @@ -665,12 +712,337 @@ static const struct qcom_pcie_ops ops_v0 97 | .get_resources = qcom_pcie_get_resources_v0, 98 | .init = qcom_pcie_init_v0, 99 | .deinit = qcom_pcie_deinit_v0, 100 | + .ltssm_enable = qcom_pcie_v0_v1_ltssm_enable, 101 | }; 102 | 103 | static const struct qcom_pcie_ops ops_v1 = { 104 | .get_resources = qcom_pcie_get_resources_v1, 105 | .init = qcom_pcie_init_v1, 106 | .deinit = qcom_pcie_deinit_v1, 107 | + .ltssm_enable = qcom_pcie_v0_v1_ltssm_enable, 108 | +}; 109 | + 110 | +static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie) 111 | +{ 112 | + struct qcom_pcie_resources_v3 *res = &pcie->res.v3; 113 | + struct device *dev = pcie->pp.dev; 114 | + 115 | + res->vdda = devm_regulator_get(dev, "vdda"); 116 | + if (IS_ERR(res->vdda)) 117 | + return PTR_ERR(res->vdda); 118 | + 119 | + res->vdda_phy = devm_regulator_get(dev, "vdda_phy"); 120 | + if (IS_ERR(res->vdda_phy)) 121 | + return PTR_ERR(res->vdda_phy); 122 | + 123 | + res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk"); 124 | + if (IS_ERR(res->vdda_refclk)) 125 | + return PTR_ERR(res->vdda_refclk); 126 | + 127 | + res->ahb_clk = devm_clk_get(dev, "ahb"); 128 | + if (IS_ERR(res->ahb_clk)) 129 | + return PTR_ERR(res->ahb_clk); 130 | + 131 | + res->axi_m_clk = devm_clk_get(dev, "axi_m"); 132 | + if (IS_ERR(res->axi_m_clk)) 133 | + return PTR_ERR(res->axi_m_clk); 134 | + 135 | + res->axi_s_clk = devm_clk_get(dev, "axi_s"); 136 | + if (IS_ERR(res->axi_s_clk)) 137 | + return PTR_ERR(res->axi_s_clk); 138 | + 139 | + res->axi_m_reset = devm_reset_control_get(dev, "axi_m"); 140 | + if (IS_ERR(res->axi_m_reset)) 141 | + return PTR_ERR(res->axi_m_reset); 142 | + 143 | + res->axi_s_reset = devm_reset_control_get(dev, "axi_s"); 144 | + if (IS_ERR(res->axi_s_reset)) 145 | + return PTR_ERR(res->axi_s_reset); 146 | + 147 | + res->pipe_reset = devm_reset_control_get(dev, "pipe"); 148 | + if (IS_ERR(res->pipe_reset)) 149 | + return PTR_ERR(res->pipe_reset); 150 | + 151 | + res->axi_m_vmid_reset = devm_reset_control_get(dev, "axi_m_vmid"); 152 | + if (IS_ERR(res->axi_m_vmid_reset)) 153 | + return PTR_ERR(res->axi_m_vmid_reset); 154 | + 155 | + res->axi_s_xpu_reset = devm_reset_control_get(dev, "axi_s_xpu"); 156 | + if (IS_ERR(res->axi_s_xpu_reset)) 157 | + return PTR_ERR(res->axi_s_xpu_reset); 158 | + 159 | + res->parf_reset = devm_reset_control_get(dev, "parf"); 160 | + if (IS_ERR(res->parf_reset)) 161 | + return PTR_ERR(res->parf_reset); 162 | + 163 | + res->phy_reset = devm_reset_control_get(dev, "phy"); 164 | + if (IS_ERR(res->phy_reset)) 165 | + return PTR_ERR(res->phy_reset); 166 | + 167 | + res->axi_m_sticky_reset = devm_reset_control_get(dev, "axi_m_sticky"); 168 | + if (IS_ERR(res->axi_m_sticky_reset)) 169 | + return PTR_ERR(res->axi_m_sticky_reset); 170 | + 171 | + res->pipe_sticky_reset = devm_reset_control_get(dev, "pipe_sticky"); 172 | + if (IS_ERR(res->pipe_sticky_reset)) 173 | + return PTR_ERR(res->pipe_sticky_reset); 174 | + 175 | + res->pwr_reset = devm_reset_control_get(dev, "pwr"); 176 | + if (IS_ERR(res->pwr_reset)) 177 | + return PTR_ERR(res->pwr_reset); 178 | + 179 | + res->ahb_reset = devm_reset_control_get(dev, "ahb"); 180 | + if (IS_ERR(res->ahb_reset)) 181 | + return PTR_ERR(res->ahb_reset); 182 | + 183 | + res->phy_ahb_reset = devm_reset_control_get(dev, "phy_ahb"); 184 | + if (IS_ERR(res->phy_ahb_reset)) 185 | + return PTR_ERR(res->phy_ahb_reset); 186 | + 187 | + return 0; 188 | +} 189 | + 190 | +static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie) 191 | +{ 192 | + struct qcom_pcie_resources_v3 *res = &pcie->res.v3; 193 | + 194 | + reset_control_assert(res->axi_m_reset); 195 | + reset_control_assert(res->axi_s_reset); 196 | + reset_control_assert(res->pipe_reset); 197 | + reset_control_assert(res->pipe_sticky_reset); 198 | + reset_control_assert(res->phy_reset); 199 | + reset_control_assert(res->phy_ahb_reset); 200 | + reset_control_assert(res->axi_m_sticky_reset); 201 | + reset_control_assert(res->pwr_reset); 202 | + reset_control_assert(res->ahb_reset); 203 | + clk_disable_unprepare(res->ahb_clk); 204 | + clk_disable_unprepare(res->axi_m_clk); 205 | + clk_disable_unprepare(res->axi_s_clk); 206 | + regulator_disable(res->vdda); 207 | + regulator_disable(res->vdda_phy); 208 | + regulator_disable(res->vdda_refclk); 209 | +} 210 | + 211 | +static int qcom_pcie_init_v3(struct qcom_pcie *pcie) 212 | +{ 213 | + struct qcom_pcie_resources_v3 *res = &pcie->res.v3; 214 | + struct device *dev = pcie->pp.dev; 215 | + u32 val; 216 | + int ret; 217 | + 218 | + ret = reset_control_assert(res->axi_m_reset); 219 | + if (ret) { 220 | + dev_err(dev, "cannot assert axi master reset\n"); 221 | + return ret; 222 | + } 223 | + 224 | + ret = reset_control_assert(res->axi_s_reset); 225 | + if (ret) { 226 | + dev_err(dev, "cannot asser axi slave reset\n"); 227 | + return ret; 228 | + } 229 | + 230 | + usleep_range(10000, 12000); 231 | + 232 | + ret = reset_control_assert(res->pipe_reset); 233 | + if (ret) { 234 | + dev_err(dev, "cannot assert pipe reset\n"); 235 | + return ret; 236 | + } 237 | + 238 | + ret = reset_control_assert(res->pipe_sticky_reset); 239 | + if (ret) { 240 | + dev_err(dev, "cannot assert pipe sticky reset\n"); 241 | + return ret; 242 | + } 243 | + 244 | + ret = reset_control_assert(res->phy_reset); 245 | + if (ret) { 246 | + dev_err(dev, "cannot assert phy reset\n"); 247 | + return ret; 248 | + } 249 | + 250 | + ret = reset_control_assert(res->phy_ahb_reset); 251 | + if (ret) { 252 | + dev_err(dev, "cannot assert phy ahb reset\n"); 253 | + return ret; 254 | + } 255 | + 256 | + usleep_range(10000, 12000); 257 | + 258 | + ret = reset_control_assert(res->axi_m_sticky_reset); 259 | + if (ret) { 260 | + dev_err(dev, "cannot assert axi master sticky reset\n"); 261 | + return ret; 262 | + } 263 | + 264 | + ret = reset_control_assert(res->pwr_reset); 265 | + if (ret) { 266 | + dev_err(dev, "cannot assert power reset\n"); 267 | + return ret; 268 | + } 269 | + 270 | + ret = reset_control_assert(res->ahb_reset); 271 | + if (ret) { 272 | + dev_err(dev, "cannot assert ahb reset\n"); 273 | + return ret; 274 | + } 275 | + 276 | + usleep_range(10000, 12000); 277 | + 278 | + ret = reset_control_deassert(res->phy_ahb_reset); 279 | + if (ret) { 280 | + dev_err(dev, "cannot deassert phy ahb reset\n"); 281 | + return ret; 282 | + } 283 | + 284 | + ret = reset_control_deassert(res->phy_reset); 285 | + if (ret) { 286 | + dev_err(dev, "cannot deassert phy reset\n"); 287 | + goto err_rst_phy; 288 | + } 289 | + 290 | + ret = reset_control_deassert(res->pipe_reset); 291 | + if (ret) { 292 | + dev_err(dev, "cannot deassert pipe reset\n"); 293 | + goto err_rst_pipe; 294 | + } 295 | + 296 | + ret = reset_control_deassert(res->pipe_sticky_reset); 297 | + if (ret) { 298 | + dev_err(dev, "cannot deassert pipe sticky reset\n"); 299 | + goto err_rst_pipe_sticky; 300 | + } 301 | + 302 | + usleep_range(10000, 12000); 303 | + 304 | + ret = reset_control_deassert(res->axi_m_reset); 305 | + if (ret) { 306 | + dev_err(dev, "cannot deassert axi master reset\n"); 307 | + goto err_rst_axi_m; 308 | + } 309 | + 310 | + ret = reset_control_deassert(res->axi_m_sticky_reset); 311 | + if (ret) { 312 | + dev_err(dev, "cannot deassert axi master sticky reset\n"); 313 | + goto err_rst_axi_m_sticky; 314 | + } 315 | + 316 | + ret = reset_control_deassert(res->axi_s_reset); 317 | + if (ret) { 318 | + dev_err(dev, "cannot deassert axi slave reset\n"); 319 | + goto err_rst_axi_s; 320 | + } 321 | + 322 | + ret = reset_control_deassert(res->pwr_reset); 323 | + if (ret) { 324 | + dev_err(dev, "cannot deassert power reset\n"); 325 | + goto err_rst_pwr; 326 | + } 327 | + 328 | + ret = reset_control_deassert(res->ahb_reset); 329 | + if (ret) { 330 | + dev_err(dev, "cannot deassert ahb reset\n"); 331 | + goto err_rst_ahb; 332 | + } 333 | + 334 | + usleep_range(10000, 12000); 335 | + 336 | + ret = regulator_enable(res->vdda); 337 | + if (ret) { 338 | + dev_err(dev, "cannot enable vdda regulator\n"); 339 | + goto err_vdda; 340 | + } 341 | + 342 | + ret = regulator_enable(res->vdda_refclk); 343 | + if (ret) { 344 | + dev_err(dev, "cannot enable vdda_refclk regulator\n"); 345 | + goto err_refclk; 346 | + } 347 | + 348 | + ret = regulator_enable(res->vdda_phy); 349 | + if (ret) { 350 | + dev_err(dev, "cannot enable vdda_phy regulator\n"); 351 | + goto err_vdda_phy; 352 | + } 353 | + 354 | + ret = clk_prepare_enable(res->ahb_clk); 355 | + if (ret) { 356 | + dev_err(dev, "cannot prepare/enable iface clock\n"); 357 | + goto err_ahb; 358 | + } 359 | + 360 | + ret = clk_prepare_enable(res->axi_m_clk); 361 | + if (ret) { 362 | + dev_err(dev, "cannot prepare/enable core clock\n"); 363 | + goto err_clk_axi_m; 364 | + } 365 | + 366 | + ret = clk_prepare_enable(res->axi_s_clk); 367 | + if (ret) { 368 | + dev_err(dev, "cannot prepare/enable phy clock\n"); 369 | + goto err_clk_axi_s; 370 | + } 371 | + 372 | + /* enable PCIe clocks and resets */ 373 | + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); 374 | + val &= !BIT(0); 375 | + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); 376 | + 377 | + /* change DBI base address */ 378 | + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); 379 | + 380 | + /* MAC PHY_POWERDOWN MUX DISABLE */ 381 | + val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); 382 | + val &= ~BIT(29); 383 | + writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); 384 | + 385 | + val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 386 | + val |= BIT(4); 387 | + writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); 388 | + 389 | + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); 390 | + val |= BIT(31); 391 | + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); 392 | + 393 | + return 0; 394 | + 395 | +err_clk_axi_s: 396 | + clk_disable_unprepare(res->axi_m_clk); 397 | +err_clk_axi_m: 398 | + clk_disable_unprepare(res->ahb_clk); 399 | +err_ahb: 400 | + regulator_disable(res->vdda_phy); 401 | +err_vdda_phy: 402 | + regulator_disable(res->vdda_refclk); 403 | +err_refclk: 404 | + regulator_disable(res->vdda); 405 | +err_vdda: 406 | + reset_control_assert(res->ahb_reset); 407 | +err_rst_ahb: 408 | + reset_control_assert(res->pwr_reset); 409 | +err_rst_pwr: 410 | + reset_control_assert(res->axi_s_reset); 411 | +err_rst_axi_s: 412 | + reset_control_assert(res->axi_m_sticky_reset); 413 | +err_rst_axi_m_sticky: 414 | + reset_control_assert(res->axi_m_reset); 415 | +err_rst_axi_m: 416 | + reset_control_assert(res->pipe_sticky_reset); 417 | +err_rst_pipe_sticky: 418 | + reset_control_assert(res->pipe_reset); 419 | +err_rst_pipe: 420 | + reset_control_assert(res->phy_reset); 421 | +err_rst_phy: 422 | + reset_control_assert(res->phy_ahb_reset); 423 | + return ret; 424 | +} 425 | + 426 | +static const struct qcom_pcie_ops ops_v3 = { 427 | + .get_resources = qcom_pcie_get_resources_v3, 428 | + .init = qcom_pcie_init_v3, 429 | + .deinit = qcom_pcie_deinit_v3, 430 | + .ltssm_enable = qcom_pcie_v2_ltssm_enable, 431 | }; 432 | 433 | static int qcom_pcie_probe(struct platform_device *pdev) 434 | @@ -784,6 +1156,7 @@ static const struct of_device_id qcom_pc 435 | { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 }, 436 | { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 }, 437 | { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 }, 438 | + { .compatible = "qcom,pcie-ipq4019", .data = &ops_v3 }, 439 | { } 440 | }; 441 | 442 | -------------------------------------------------------------------------------- /remove-files: -------------------------------------------------------------------------------- 1 | target/linux/ipq806x/patches-4.9/852-ipq4019-pinctrl-Updated-various-Pin-definitions.patch 2 | target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch 3 | target/linux/ipq806x/patches-4.9/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch 4 | target/linux/ipq806x/patches-4.9/864-06-dts-ipq4019-fix-max-cpu-speed.patch 5 | --------------------------------------------------------------------------------