├── ssrv-on-scr1 ├── fpga │ ├── DE2_115 │ │ ├── dualram.qip │ │ ├── plll.qip │ │ ├── DE2_115.sld │ │ ├── DE2_115.done │ │ ├── DE2_115.qws │ │ ├── DE2_115.sof │ │ ├── DE2_115.fit.rpt │ │ ├── DE2_115.qpf │ │ ├── PLLJ_PLLSPE_INFO.txt │ │ ├── DE2_115.jdi │ │ ├── DE2_115.map.summary │ │ ├── DE2_115.fit.summary │ │ ├── DE2_115.fit.smsg │ │ └── DE2_115.sdc │ ├── scr1 │ │ ├── ahb_tb.files │ │ ├── axi_tb.files │ │ ├── axi_top.files │ │ ├── ahb_top.files │ │ ├── core.files │ │ ├── core │ │ │ ├── primitives │ │ │ │ └── scr1_cg.sv │ │ │ └── scr1_clk_ctrl.sv │ │ ├── includes │ │ │ ├── scr1_ahb.svh │ │ │ ├── scr1_memif.svh │ │ │ ├── scr1_arch_types.svh │ │ │ ├── scr1_tapc.svh │ │ │ ├── scr1_ipic.svh │ │ │ └── scr1_search_ms1.svh │ │ └── pipeline │ │ │ └── scr1_pipe_mprf.sv │ ├── pll │ │ ├── plll_inst.v │ │ ├── plll.qip │ │ └── plll.ppf │ ├── ram │ │ ├── dualram.qip │ │ └── dualram_inst.v │ ├── readme.md │ └── rtl │ │ ├── define.v │ │ └── instrman.v ├── sim │ ├── scr1 │ │ ├── sim │ │ │ ├── sim.do │ │ │ ├── tests │ │ │ │ ├── riscv_isa │ │ │ │ │ ├── test_macros.h │ │ │ │ │ ├── riscv_test.h │ │ │ │ │ ├── rv32_tests.inc │ │ │ │ │ └── Makefile │ │ │ │ ├── riscv_compliance │ │ │ │ │ ├── riscv_test.h │ │ │ │ │ ├── check.c │ │ │ │ │ ├── compliance_test.h │ │ │ │ │ └── compliance_io.h │ │ │ │ ├── common │ │ │ │ │ ├── sc_print.h │ │ │ │ │ ├── scr1_specific.h │ │ │ │ │ ├── sc_test.h │ │ │ │ │ ├── LICENSE │ │ │ │ │ ├── link.ld │ │ │ │ │ ├── link_tcm.ld │ │ │ │ │ └── crt.S │ │ │ │ ├── vectored_isr_sample │ │ │ │ │ ├── Makefile │ │ │ │ │ └── timer.h │ │ │ │ └── benchmarks │ │ │ │ │ ├── dhrystone21 │ │ │ │ │ └── Makefile │ │ │ │ │ └── coremark │ │ │ │ │ └── Makefile │ │ │ ├── readme.txt │ │ │ ├── compile.do │ │ │ ├── verilator_wrap │ │ │ │ ├── scr1_axi_wrapper.c │ │ │ │ └── scr1_ahb_wrapper.c │ │ │ └── Makefile │ │ ├── src │ │ │ ├── ahb_tb.files │ │ │ ├── axi_tb.files │ │ │ ├── axi_top.files │ │ │ ├── ahb_top.files │ │ │ ├── core.files │ │ │ ├── core │ │ │ │ ├── primitives │ │ │ │ │ └── scr1_cg.sv │ │ │ │ └── scr1_clk_ctrl.sv │ │ │ ├── includes │ │ │ │ ├── scr1_ahb.svh │ │ │ │ ├── scr1_memif.svh │ │ │ │ ├── scr1_arch_types.svh │ │ │ │ ├── scr1_tapc.svh │ │ │ │ ├── scr1_ipic.svh │ │ │ │ └── scr1_search_ms1.svh │ │ │ └── pipeline │ │ │ │ └── scr1_pipe_mprf.sv │ │ └── build │ │ │ ├── div.elf │ │ │ ├── divu.elf │ │ │ ├── mul.elf │ │ │ ├── mulh.elf │ │ │ ├── rem.elf │ │ │ ├── remu.elf │ │ │ ├── mulhsu.elf │ │ │ ├── mulhu.elf │ │ │ ├── coremark_i.elf │ │ │ ├── coremark_ic.elf │ │ │ ├── coremark_imc.elf │ │ │ ├── dhrystone21_i_max.elf │ │ │ ├── dhrystone21_ic_max.elf │ │ │ ├── dhrystone21_imc_max.elf │ │ │ ├── dhrystone21_i_noinline.elf │ │ │ ├── dhrystone21_ic_noinline.elf │ │ │ ├── dhrystone21_imc_noinline.elf │ │ │ ├── test_info │ │ │ ├── rem.hex │ │ │ ├── remu.hex │ │ │ ├── div.hex │ │ │ └── divu.hex │ ├── readme.md │ └── rtl │ │ ├── define.v │ │ └── instrman.v └── readme.md ├── scr1 ├── sim │ ├── sim.do │ ├── tests │ │ ├── riscv_isa │ │ │ ├── test_macros.h │ │ │ ├── riscv_test.h │ │ │ ├── rv32_tests.inc │ │ │ └── Makefile │ │ ├── riscv_compliance │ │ │ ├── riscv_test.h │ │ │ ├── check.c │ │ │ ├── compliance_test.h │ │ │ └── compliance_io.h │ │ ├── common │ │ │ ├── sc_print.h │ │ │ ├── scr1_specific.h │ │ │ ├── sc_test.h │ │ │ ├── LICENSE │ │ │ ├── link.ld │ │ │ ├── link_tcm.ld │ │ │ └── crt.S │ │ ├── vectored_isr_sample │ │ │ ├── Makefile │ │ │ └── timer.h │ │ └── benchmarks │ │ │ ├── dhrystone21 │ │ │ └── Makefile │ │ │ └── coremark │ │ │ └── Makefile │ ├── readme.txt │ ├── compile.do │ ├── verilator_wrap │ │ ├── scr1_axi_wrapper.c │ │ └── scr1_ahb_wrapper.c │ └── Makefile ├── build │ ├── div.elf │ ├── mul.elf │ ├── rem.elf │ ├── divu.elf │ ├── mulh.elf │ ├── mulhsu.elf │ ├── mulhu.elf │ ├── remu.elf │ ├── coremark_i.elf │ ├── coremark_ic.elf │ ├── coremark_imc.elf │ ├── dhrystone21_i_max.elf │ ├── dhrystone21_ic_max.elf │ ├── dhrystone21_imc_max.elf │ ├── dhrystone21_i_noinline.elf │ ├── dhrystone21_ic_noinline.elf │ ├── dhrystone21_imc_noinline.elf │ ├── test_info │ ├── rem.hex │ ├── remu.hex │ ├── div.hex │ └── divu.hex └── src │ ├── ahb_tb.files │ ├── axi_tb.files │ ├── axi_top.files │ ├── ahb_top.files │ ├── core.files │ ├── core │ ├── primitives │ │ └── scr1_cg.sv │ └── scr1_clk_ctrl.sv │ ├── includes │ ├── scr1_ahb.svh │ ├── scr1_memif.svh │ ├── scr1_arch_types.svh │ ├── scr1_tapc.svh │ ├── scr1_ipic.svh │ └── scr1_search_ms1.svh │ └── pipeline │ └── scr1_pipe_mprf.sv ├── wiki ├── SSRV全解析.pdf └── png │ ├── fpga.PNG │ ├── diagram.png │ ├── ProjBuffer.PNG │ ├── hierarchy.png │ └── ssrv-on-scr1.png ├── .gitignore ├── .gitattributes └── rtl ├── define.v └── instrman.v /ssrv-on-scr1/fpga/DE2_115/dualram.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/plll.qip: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.sld: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.done: -------------------------------------------------------------------------------- 1 | Thu Aug 06 14:09:40 2020 2 | -------------------------------------------------------------------------------- /scr1/sim/sim.do: -------------------------------------------------------------------------------- 1 | vsim work.scr1_top_tb_ahb work.tb_ssrv -voptargs=+acc -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/sim.do: -------------------------------------------------------------------------------- 1 | vsim work.scr1_top_tb_ahb -voptargs=+acc -------------------------------------------------------------------------------- /wiki/SSRV全解析.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/wiki/SSRV全解析.pdf -------------------------------------------------------------------------------- /scr1/build/div.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/div.elf -------------------------------------------------------------------------------- /scr1/build/mul.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/mul.elf -------------------------------------------------------------------------------- /scr1/build/rem.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/rem.elf -------------------------------------------------------------------------------- /scr1/src/ahb_tb.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_tracelog.sv 2 | tb/scr1_memory_tb_ahb.sv 3 | tb/scr1_top_tb_ahb.sv -------------------------------------------------------------------------------- /scr1/src/axi_tb.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_tracelog.sv 2 | tb/scr1_memory_tb_axi.sv 3 | tb/scr1_top_tb_axi.sv -------------------------------------------------------------------------------- /wiki/png/fpga.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/wiki/png/fpga.PNG -------------------------------------------------------------------------------- /scr1/build/divu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/divu.elf -------------------------------------------------------------------------------- /scr1/build/mulh.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/mulh.elf -------------------------------------------------------------------------------- /scr1/build/mulhsu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/mulhsu.elf -------------------------------------------------------------------------------- /scr1/build/mulhu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/mulhu.elf -------------------------------------------------------------------------------- /scr1/build/remu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/remu.elf -------------------------------------------------------------------------------- /wiki/png/diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/wiki/png/diagram.png -------------------------------------------------------------------------------- /wiki/png/ProjBuffer.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/wiki/png/ProjBuffer.PNG -------------------------------------------------------------------------------- /wiki/png/hierarchy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/wiki/png/hierarchy.png -------------------------------------------------------------------------------- /scr1/build/coremark_i.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/coremark_i.elf -------------------------------------------------------------------------------- /scr1/build/coremark_ic.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/coremark_ic.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/ahb_tb.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_tracelog.sv 2 | tb/scr1_memory_tb_ahb.sv 3 | tb/scr1_top_tb_ahb.sv -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/axi_tb.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_tracelog.sv 2 | tb/scr1_memory_tb_axi.sv 3 | tb/scr1_top_tb_axi.sv -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/ahb_tb.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_tracelog.sv 2 | tb/scr1_memory_tb_ahb.sv 3 | tb/scr1_top_tb_ahb.sv -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/axi_tb.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_tracelog.sv 2 | tb/scr1_memory_tb_axi.sv 3 | tb/scr1_top_tb_axi.sv -------------------------------------------------------------------------------- /wiki/png/ssrv-on-scr1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/wiki/png/ssrv-on-scr1.png -------------------------------------------------------------------------------- /scr1/build/coremark_imc.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/coremark_imc.elf -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_isa/test_macros.h: -------------------------------------------------------------------------------- 1 | #ifndef __TEST__MACROS__H 2 | #define __TEST__MACROS__H 3 | 4 | 5 | #endif 6 | -------------------------------------------------------------------------------- /scr1/build/dhrystone21_i_max.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/dhrystone21_i_max.elf -------------------------------------------------------------------------------- /scr1/build/dhrystone21_ic_max.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/dhrystone21_ic_max.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/pll/plll_inst.v: -------------------------------------------------------------------------------- 1 | plll plll_inst ( 2 | .inclk0 ( inclk0_sig ), 3 | .c0 ( c0_sig ), 4 | .c1 ( c1_sig ) 5 | ); 6 | -------------------------------------------------------------------------------- /scr1/build/dhrystone21_imc_max.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/dhrystone21_imc_max.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/div.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/div.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/divu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/divu.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/mul.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/mul.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/mulh.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/mulh.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/rem.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/rem.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/remu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/remu.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_isa/test_macros.h: -------------------------------------------------------------------------------- 1 | #ifndef __TEST__MACROS__H 2 | #define __TEST__MACROS__H 3 | 4 | 5 | #endif 6 | -------------------------------------------------------------------------------- /scr1/build/dhrystone21_i_noinline.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/dhrystone21_i_noinline.elf -------------------------------------------------------------------------------- /scr1/build/dhrystone21_ic_noinline.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/dhrystone21_ic_noinline.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/fpga/DE2_115/DE2_115.qws -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/fpga/DE2_115/DE2_115.sof -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/mulhsu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/mulhsu.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/mulhu.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/mulhu.elf -------------------------------------------------------------------------------- /scr1/build/dhrystone21_imc_noinline.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/scr1/build/dhrystone21_imc_noinline.elf -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_compliance/riscv_test.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _RISCV_TEST_H 3 | #define _RISCV_TEST_H 4 | 5 | #include "test_macros.h" 6 | 7 | #endif -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/fpga/DE2_115/DE2_115.fit.rpt -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/coremark_i.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/coremark_i.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/coremark_ic.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/coremark_ic.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/coremark_imc.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/coremark_imc.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_compliance/riscv_test.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _RISCV_TEST_H 3 | #define _RISCV_TEST_H 4 | 5 | #include "test_macros.h" 6 | 7 | #endif -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.qpf: -------------------------------------------------------------------------------- 1 | DATE = "11:10:04 October 27, 2017" 2 | QUARTUS_VERSION = "14.0" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "DE2_115" 7 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/dhrystone21_i_max.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/dhrystone21_i_max.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/dhrystone21_ic_max.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/dhrystone21_ic_max.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/dhrystone21_imc_max.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/dhrystone21_imc_max.elf -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_isa/riscv_test.h: -------------------------------------------------------------------------------- 1 | #ifndef __RISCV__TEST__H 2 | #define __RISCV__TEST__H 3 | 4 | #include "riscv_macros.h" 5 | 6 | #endif // #ifndef __RISCV__TEST__H 7 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/dhrystone21_i_noinline.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/dhrystone21_i_noinline.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/dhrystone21_ic_noinline.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/dhrystone21_ic_noinline.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/dhrystone21_imc_noinline.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/ssrv-on-scr1/sim/scr1/build/dhrystone21_imc_noinline.elf -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/PLLJ_PLLSPE_INFO.txt: -------------------------------------------------------------------------------- 1 | PLL_Name plll:i_clock|altpll:altpll_component|plll_altpll:auto_generated|pll1 2 | PLLJITTER 36 3 | PLLSPEmax 84 4 | PLLSPEmin -53 5 | 6 | -------------------------------------------------------------------------------- /scr1/src/axi_top.files: -------------------------------------------------------------------------------- 1 | top/scr1_dmem_router.sv 2 | top/scr1_imem_router.sv 3 | top/scr1_dp_memory.sv 4 | top/scr1_tcm.sv 5 | top/scr1_timer.sv 6 | top/scr1_mem_axi.sv 7 | top/scr1_top_axi.sv -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_isa/riscv_test.h: -------------------------------------------------------------------------------- 1 | #ifndef __RISCV__TEST__H 2 | #define __RISCV__TEST__H 3 | 4 | #include "riscv_macros.h" 5 | 6 | #endif // #ifndef __RISCV__TEST__H 7 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/axi_top.files: -------------------------------------------------------------------------------- 1 | top/scr1_dmem_router.sv 2 | top/scr1_imem_router.sv 3 | top/scr1_dp_memory.sv 4 | top/scr1_tcm.sv 5 | top/scr1_timer.sv 6 | top/scr1_mem_axi.sv 7 | top/scr1_top_axi.sv -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/axi_top.files: -------------------------------------------------------------------------------- 1 | top/scr1_dmem_router.sv 2 | top/scr1_imem_router.sv 3 | top/scr1_dp_memory.sv 4 | top/scr1_tcm.sv 5 | top/scr1_timer.sv 6 | top/scr1_mem_axi.sv 7 | top/scr1_top_axi.sv -------------------------------------------------------------------------------- /scr1/src/ahb_top.files: -------------------------------------------------------------------------------- 1 | top/scr1_dmem_router.sv 2 | top/scr1_imem_router.sv 3 | top/scr1_dp_memory.sv 4 | top/scr1_tcm.sv 5 | top/scr1_timer.sv 6 | top/scr1_dmem_ahb.sv 7 | top/scr1_imem_ahb.sv 8 | top/scr1_top_ahb.sv 9 | top/scr1_mem_axi.sv 10 | top/scr1_top_axi.sv 11 | -------------------------------------------------------------------------------- /scr1/sim/tests/common/sc_print.h: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// 4 | 5 | #ifndef SC_PRINT_H 6 | #define SC_PRINT_H 7 | 8 | extern int sc_printf(const char* fmt, ...); 9 | 10 | #endif // SC_PRINT_H -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/ahb_top.files: -------------------------------------------------------------------------------- 1 | top/scr1_dmem_router.sv 2 | top/scr1_imem_router.sv 3 | top/scr1_dp_memory.sv 4 | top/scr1_tcm.sv 5 | top/scr1_timer.sv 6 | top/scr1_dmem_ahb.sv 7 | top/scr1_imem_ahb.sv 8 | top/scr1_top_ahb.sv 9 | top/scr1_mem_axi.sv 10 | top/scr1_top_axi.sv 11 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/ahb_top.files: -------------------------------------------------------------------------------- 1 | top/scr1_dmem_router.sv 2 | top/scr1_imem_router.sv 3 | top/scr1_dp_memory.sv 4 | top/scr1_tcm.sv 5 | top/scr1_timer.sv 6 | top/scr1_dmem_ahb.sv 7 | top/scr1_imem_ahb.sv 8 | top/scr1_top_ahb.sv 9 | top/scr1_mem_axi.sv 10 | top/scr1_top_axi.sv 11 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/sc_print.h: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// 4 | 5 | #ifndef SC_PRINT_H 6 | #define SC_PRINT_H 7 | 8 | extern int sc_printf(const char* fmt, ...); 9 | 10 | #endif // SC_PRINT_H -------------------------------------------------------------------------------- /scr1/build/test_info: -------------------------------------------------------------------------------- 1 | #coremark_i.hex 2 | #coremark_ic.hex 3 | coremark_imc.hex 4 | #dhrystone21_i_max.hex 5 | #dhrystone21_i_noinline.hex 6 | #dhrystone21_ic_max.hex 7 | #dhrystone21_ic_noinline.hex 8 | dhrystone21_imc_max.hex 9 | dhrystone21_imc_noinline.hex 10 | #div.hex 11 | #divu.hex 12 | #mul.hex 13 | #mulh.hex 14 | #mulhsu.hex 15 | #mulhu.hex 16 | #rem.hex 17 | #remu.hex 18 | 19 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/test_info: -------------------------------------------------------------------------------- 1 | #coremark_i.hex 2 | #coremark_ic.hex 3 | coremark_imc.hex 4 | #dhrystone21_i_max.hex 5 | #dhrystone21_i_noinline.hex 6 | #dhrystone21_ic_max.hex 7 | #dhrystone21_ic_noinline.hex 8 | dhrystone21_imc_max.hex 9 | dhrystone21_imc_noinline.hex 10 | #div.hex 11 | #divu.hex 12 | #mul.hex 13 | #mulh.hex 14 | #mulhsu.hex 15 | #mulhu.hex 16 | #rem.hex 17 | #remu.hex 18 | 19 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/ram/dualram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dualram.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dualram_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dualram_bb.v"] 6 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/ram/dualram_inst.v: -------------------------------------------------------------------------------- 1 | dualram dualram_inst ( 2 | .address_a ( address_a_sig ), 3 | .address_b ( address_b_sig ), 4 | .byteena_b ( byteena_b_sig ), 5 | .clock ( clock_sig ), 6 | .data_a ( data_a_sig ), 7 | .data_b ( data_b_sig ), 8 | .rden_a ( rden_a_sig ), 9 | .rden_b ( rden_b_sig ), 10 | .wren_a ( wren_a_sig ), 11 | .wren_b ( wren_b_sig ), 12 | .q_a ( q_a_sig ), 13 | .q_b ( q_b_sig ) 14 | ); 15 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows thumbnail cache files 2 | Thumbs.db 3 | ehthumbs.db 4 | ehthumbs_vista.db 5 | 6 | # Folder config file 7 | Desktop.ini 8 | 9 | # Recycle Bin used on file shares 10 | $RECYCLE.BIN/ 11 | 12 | # Windows Installer files 13 | *.cab 14 | *.msi 15 | *.msm 16 | *.msp 17 | 18 | # Windows shortcuts 19 | *.lnk 20 | 21 | # ========================= 22 | # Operating System Files 23 | # ========================= 24 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_compliance/check.c: -------------------------------------------------------------------------------- 1 | #include "stdint.h" 2 | 3 | int check(void) 4 | { 5 | static const uint32_t ref[] = { 6 | #include "" 7 | }; 8 | 9 | extern uint32_t begin_signature; 10 | const uint32_t *my_res = &begin_signature; 11 | int i; 12 | 13 | for (i = 0; i < sizeof(ref)/sizeof(*ref); i++) { 14 | if (my_res[i] != ref[i]) { 15 | return -1; 16 | } 17 | } 18 | return 0; 19 | } -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/pll/plll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "plll.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "plll_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "plll_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "plll.ppf"] 7 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/pll/plll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_compliance/check.c: -------------------------------------------------------------------------------- 1 | #include "stdint.h" 2 | 3 | int check(void) 4 | { 5 | static const uint32_t ref[] = { 6 | #include "" 7 | }; 8 | 9 | extern uint32_t begin_signature; 10 | const uint32_t *my_res = &begin_signature; 11 | int i; 12 | 13 | for (i = 0; i < sizeof(ref)/sizeof(*ref); i++) { 14 | if (my_res[i] != ref[i]) { 15 | return -1; 16 | } 17 | } 18 | return 0; 19 | } -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Thu Aug 06 13:47:14 2020 2 | Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Standard Edition 3 | Revision Name : DE2_115 4 | Top-level Entity Name : DE2_115 5 | Family : Cyclone IV E 6 | Total logic elements : 38,920 7 | Total combinational functions : 38,850 8 | Dedicated logic registers : 5,467 9 | Total registers : 5467 10 | Total pins : 436 11 | Total virtual pins : 0 12 | Total memory bits : 524,288 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 1 15 | -------------------------------------------------------------------------------- /scr1/src/core.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_pipe_hdu.sv 2 | pipeline/scr1_pipe_tdu.sv 3 | pipeline/scr1_ipic.sv 4 | pipeline/scr1_pipe_csr.sv 5 | pipeline/scr1_pipe_exu.sv 6 | pipeline/scr1_pipe_ialu.sv 7 | pipeline/scr1_pipe_idu.sv 8 | pipeline/scr1_pipe_ifu.sv 9 | pipeline/scr1_pipe_lsu.sv 10 | pipeline/scr1_pipe_mprf.sv 11 | pipeline/scr1_pipe_top.sv 12 | core/primitives/scr1_reset_cells.sv 13 | core/primitives/scr1_cg.sv 14 | core/scr1_clk_ctrl.sv 15 | core/scr1_tapc_shift_reg.sv 16 | core/scr1_tapc.sv 17 | core/scr1_tapc_synchronizer.sv 18 | core/scr1_core_top.sv 19 | core/scr1_dm.sv 20 | core/scr1_dmi.sv 21 | core/scr1_scu.sv 22 | -------------------------------------------------------------------------------- /scr1/sim/tests/common/scr1_specific.h: -------------------------------------------------------------------------------- 1 | #ifndef __SCR1__SPECIFIC 2 | #define __SCR1__SPECIFIC 3 | 4 | #define mcounten 0x7E0 5 | 6 | // Memory-mapped registers 7 | #define mtime_ctrl 0x00490000 8 | #define mtime_div 0x00490004 9 | #define mtime 0x00490008 10 | #define mtimeh 0x0049000C 11 | #define mtimecmp 0x00490010 12 | #define mtimecmph 0x00490014 13 | 14 | #define SCR1_MTIME_CTRL_EN 0 15 | #define SCR1_MTIME_CTRL_CLKSRC 1 16 | 17 | #define SCR1_MTIME_CTRL_WR_MASK 0x3 18 | #define SCR1_MTIME_DIV_WR_MASK 0x3FF 19 | 20 | #endif // _SCR1__SPECIFIC 21 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/core.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_pipe_hdu.sv 2 | pipeline/scr1_pipe_tdu.sv 3 | pipeline/scr1_ipic.sv 4 | pipeline/scr1_pipe_csr.sv 5 | pipeline/scr1_pipe_exu.sv 6 | pipeline/scr1_pipe_ialu.sv 7 | pipeline/scr1_pipe_idu.sv 8 | pipeline/scr1_pipe_ifu.sv 9 | pipeline/scr1_pipe_lsu.sv 10 | pipeline/scr1_pipe_mprf.sv 11 | pipeline/scr1_pipe_top.sv 12 | core/primitives/scr1_reset_cells.sv 13 | core/primitives/scr1_cg.sv 14 | core/scr1_clk_ctrl.sv 15 | core/scr1_tapc_shift_reg.sv 16 | core/scr1_tapc.sv 17 | core/scr1_tapc_synchronizer.sv 18 | core/scr1_core_top.sv 19 | core/scr1_dm.sv 20 | core/scr1_dmi.sv 21 | core/scr1_scu.sv 22 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/scr1_specific.h: -------------------------------------------------------------------------------- 1 | #ifndef __SCR1__SPECIFIC 2 | #define __SCR1__SPECIFIC 3 | 4 | #define mcounten 0x7E0 5 | 6 | // Memory-mapped registers 7 | #define mtime_ctrl 0x00490000 8 | #define mtime_div 0x00490004 9 | #define mtime 0x00490008 10 | #define mtimeh 0x0049000C 11 | #define mtimecmp 0x00490010 12 | #define mtimecmph 0x00490014 13 | 14 | #define SCR1_MTIME_CTRL_EN 0 15 | #define SCR1_MTIME_CTRL_CLKSRC 1 16 | 17 | #define SCR1_MTIME_CTRL_WR_MASK 0x3 18 | #define SCR1_MTIME_DIV_WR_MASK 0x3FF 19 | 20 | #endif // _SCR1__SPECIFIC 21 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/core.files: -------------------------------------------------------------------------------- 1 | pipeline/scr1_pipe_hdu.sv 2 | pipeline/scr1_pipe_tdu.sv 3 | pipeline/scr1_ipic.sv 4 | pipeline/scr1_pipe_csr.sv 5 | pipeline/scr1_pipe_exu.sv 6 | pipeline/scr1_pipe_ialu.sv 7 | pipeline/scr1_pipe_idu.sv 8 | pipeline/scr1_pipe_ifu.sv 9 | pipeline/scr1_pipe_lsu.sv 10 | pipeline/scr1_pipe_mprf.sv 11 | pipeline/scr1_pipe_top.sv 12 | core/primitives/scr1_reset_cells.sv 13 | core/primitives/scr1_cg.sv 14 | core/scr1_clk_ctrl.sv 15 | core/scr1_tapc_shift_reg.sv 16 | core/scr1_tapc.sv 17 | core/scr1_tapc_synchronizer.sv 18 | core/scr1_core_top.sv 19 | core/scr1_dm.sv 20 | core/scr1_dmi.sv 21 | core/scr1_scu.sv 22 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Thu Aug 06 14:07:48 2020 2 | Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Standard Edition 3 | Revision Name : DE2_115 4 | Top-level Entity Name : DE2_115 5 | Family : Cyclone IV E 6 | Device : EP4CE115F29C7 7 | Timing Models : Final 8 | Total logic elements : 38,917 / 114,480 ( 34 % ) 9 | Total combinational functions : 38,854 / 114,480 ( 34 % ) 10 | Dedicated logic registers : 5,467 / 114,480 ( 5 % ) 11 | Total registers : 5467 12 | Total pins : 436 / 529 ( 82 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 524,288 / 3,981,312 ( 13 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % ) 16 | Total PLLs : 1 / 4 ( 25 % ) 17 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176238): Start inferring scan chains for DSP blocks 6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 9 | -------------------------------------------------------------------------------- /scr1/src/core/primitives/scr1_cg.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief SCR1 clock gate primitive 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | 8 | `ifdef SCR1_CLKCTRL_EN 9 | module scr1_cg ( 10 | input logic clk, 11 | input logic clk_en, 12 | input logic test_mode, 13 | output logic clk_out 14 | ); 15 | 16 | // The code below is a clock gate model for simulation. 17 | // For synthesis, it should be replaced by implementation-specific 18 | // clock gate code. 19 | 20 | logic latch_en; 21 | 22 | always_latch begin 23 | if (~clk) begin 24 | latch_en <= test_mode | clk_en; 25 | end 26 | end 27 | 28 | assign clk_out = latch_en & clk; 29 | 30 | endmodule : scr1_cg 31 | 32 | `endif // SCR1_CLKCTRL_EN -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/core/primitives/scr1_cg.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief SCR1 clock gate primitive 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | 8 | `ifdef SCR1_CLKCTRL_EN 9 | module scr1_cg ( 10 | input logic clk, 11 | input logic clk_en, 12 | input logic test_mode, 13 | output logic clk_out 14 | ); 15 | 16 | // The code below is a clock gate model for simulation. 17 | // For synthesis, it should be replaced by implementation-specific 18 | // clock gate code. 19 | 20 | logic latch_en; 21 | 22 | always_latch begin 23 | if (~clk) begin 24 | latch_en <= test_mode | clk_en; 25 | end 26 | end 27 | 28 | assign clk_out = latch_en & clk; 29 | 30 | endmodule : scr1_cg 31 | 32 | `endif // SCR1_CLKCTRL_EN -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/core/primitives/scr1_cg.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief SCR1 clock gate primitive 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | 8 | `ifdef SCR1_CLKCTRL_EN 9 | module scr1_cg ( 10 | input logic clk, 11 | input logic clk_en, 12 | input logic test_mode, 13 | output logic clk_out 14 | ); 15 | 16 | // The code below is a clock gate model for simulation. 17 | // For synthesis, it should be replaced by implementation-specific 18 | // clock gate code. 19 | 20 | logic latch_en; 21 | 22 | always_latch begin 23 | if (~clk) begin 24 | latch_en <= test_mode | clk_en; 25 | end 26 | end 27 | 28 | assign clk_out = latch_en & clk; 29 | 30 | endmodule : scr1_cg 31 | 32 | `endif // SCR1_CLKCTRL_EN -------------------------------------------------------------------------------- /scr1/sim/tests/common/sc_test.h: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// 4 | 5 | #ifndef SC_TEST_H 6 | #define SC_TEST_H 7 | 8 | #ifdef ASM 9 | 10 | #define report_results(result) \ 11 | li a0, result; \ 12 | la t0, sc_exit; \ 13 | jr t0; 14 | 15 | .pushsection sc_test_section, "ax" 16 | sc_exit: j SIM_EXIT; 17 | .align 5 18 | .popsection 19 | #define sc_pass report_results(0x0) 20 | #define sc_fail report_results(0x1) 21 | 22 | #else 23 | 24 | extern void sc_exit(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3) 25 | __attribute__ ((noinline, noreturn)); 26 | 27 | static inline void __attribute__ ((noreturn)) 28 | report_results(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3) 29 | { 30 | sc_exit(result, res0, res1, res2, res3); 31 | } 32 | 33 | #endif 34 | 35 | #endif // SC_TEST_H 36 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/sc_test.h: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// 4 | 5 | #ifndef SC_TEST_H 6 | #define SC_TEST_H 7 | 8 | #ifdef ASM 9 | 10 | #define report_results(result) \ 11 | li a0, result; \ 12 | la t0, sc_exit; \ 13 | jr t0; 14 | 15 | .pushsection sc_test_section, "ax" 16 | sc_exit: j SIM_EXIT; 17 | .align 5 18 | .popsection 19 | #define sc_pass report_results(0x0) 20 | #define sc_fail report_results(0x1) 21 | 22 | #else 23 | 24 | extern void sc_exit(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3) 25 | __attribute__ ((noinline, noreturn)); 26 | 27 | static inline void __attribute__ ((noreturn)) 28 | report_results(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3) 29 | { 30 | sc_exit(result, res0, res1, res2, res3); 31 | } 32 | 33 | #endif 34 | 35 | #endif // SC_TEST_H 36 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/readme.md: -------------------------------------------------------------------------------- 1 | * sim/ 2 | 3 | It likes the simulation environment of SSRV, but the difference is that the instruction bus bit width is fixed to 32 bit and could not be adjusted to other values. 4 | 5 | The simulation could be switched from SSRV to SCR1 by commenting the verilog defination "USE_SSRV" of "rtl/define_para.v". 6 | 7 | * rtl/ 8 | 9 | "ssrv_pipe_top.sv" instantiates "ssrv_top" and " scr1_pipe_csr". It is the top module of SSRV CPU core. You can treat "rtl/" as a whole set of SSRV CPU core. 10 | 11 | * scr1/ 12 | 13 | This directory is inherited from SCR1, which provides a whole simulation package. 14 | 15 | build/ --- compiled hex/elf/dump files 16 | 17 | src/ --- source files of SCR1, which includes RTL and testbench files. 18 | 19 | sim/ --- where to start simulation and compile work library. 20 | 21 | Just enter sim/scr1/sim/ and run "compile.do" and "sim.do". 22 | -------------------------------------------------------------------------------- /scr1/sim/readme.txt: -------------------------------------------------------------------------------- 1 | A successful simulation includes two step: 1, compile all source files; 2, find top testbench files and run simulation command to them. 2 | There are two "do" files：compile.do--do the first thing; sim.do--run siumlation command for testbench files. 3 | These two "do" files are aimed to the simulation tool: MODELSIM. If you use different tools, please modify them manually. There are some tips here: 4 | 1, compile.do 5 | ---Two included directories: ../src/includes/ （SCR1) ../../rtl/ (This core) 6 | ---tb_ssrv.v is a link file between SCR1 and this core. Files in "rtl" directory are synthesizable. 7 | 2, sim.do 8 | --- scr1_top_tb_ahb: testbench file of SCR1. SCR1 may have another testbench file: scr1_top_tb_axi.sv, aimed to AXI interface. This AXI top file is not modified to suit this core. If you want to use it, you should reference to "scr1_top_tb_ahb.sv" and modify it manually. 9 | ---tb_ssrv: testbench file of this core. It does not work individually. It should go with SCR1's simulation environment. -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/readme.txt: -------------------------------------------------------------------------------- 1 | A successful simulation includes two step: 1, compile all source files; 2, find top testbench files and run simulation command to them. 2 | There are two "do" files：compile.do--do the first thing; sim.do--run siumlation command for testbench files. 3 | These two "do" files are aimed to the simulation tool: MODELSIM. If you use different tools, please modify them manually. There are some tips here: 4 | 1, compile.do 5 | ---Two included directories: ../src/includes/ （SCR1) ../../rtl/ (This core) 6 | ---tb_ssrv.v is a link file between SCR1 and this core. Files in "rtl" directory are synthesizable. 7 | 2, sim.do 8 | --- scr1_top_tb_ahb: testbench file of SCR1. SCR1 may have another testbench file: scr1_top_tb_axi.sv, aimed to AXI interface. This AXI top file is not modified to suit this core. If you want to use it, you should reference to "scr1_top_tb_ahb.sv" and modify it manually. 9 | ---tb_ssrv: testbench file of this core. It does not work individually. It should go with SCR1's simulation environment. -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/readme.md: -------------------------------------------------------------------------------- 1 | * fpga/ 2 | 3 | The FPGA demonstration project is based on Altera DE2-115 development board. 4 | 5 | * DE2-115/ 6 | 7 | The main directory of this FPGA project. Open " DE2_115.qsf" file to find more details. DE2-115.v is the top module. 8 | 9 | * pll/ 10 | 11 | A PLL ip generated by "MegaWizard Plug-In Manager", which will turn a 50 MHz clock to a 30 MHz clock. 12 | 13 | * ram/ 14 | 15 | A 64KB dual-port ram generated by "MegaWizard Plug-In Manager", which contains a mif file: code.mif. This mif file is converted from build/ dhrystone21_imc_noinline.hex. 16 | 17 | * rtl/ --- The SSRV CPU core. 18 | 19 | * scr1/ --- SCR1 source files. 20 | 21 | * test/ 22 | 23 | Two synthesizable files: rxtx.v, which is a simple UART verilog file; and "ssrv_memory.v, which instantiates the 64KB dualport ram. 24 | 25 | The FPGA board should be connected with a UART terminal, which has a configuration of 9600, even, 1 stop bit. You can change the baud rate through the parameters of rxtx.v. Please open DE2-115.v, find the instantiation of rxtx and give your "mhz" and "baud". 26 | 27 | 28 | -------------------------------------------------------------------------------- /scr1/sim/tests/vectored_isr_sample/Makefile: -------------------------------------------------------------------------------- 1 | src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | CFLAGS += $(FLAGS) \ 4 | -static -std=gnu99 -fno-common -fno-builtin-printf \ 5 | -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) 6 | LDFLAGS += -nostartfiles -nostdlib -march=rv32$(ARCH) -mabi=$(ABI) 7 | 8 | VPATH += $(src_dir) $(inc_dir) 9 | incs += -I$(src_dir) -I$(inc_dir) 10 | 11 | asm_src := v_isr_sample.S 12 | 13 | ifdef TCM 14 | ld_script := $(inc_dir)/link_tcm.ld 15 | else 16 | ld_script := $(inc_dir)/link.ld 17 | endif 18 | 19 | 20 | 21 | asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) 22 | 23 | default: $(bld_dir)/v_isr_sample.elf $(bld_dir)/v_isr_sample.hex $(bld_dir)/v_isr_sample.dump 24 | 25 | $(bld_dir)/%.o: %.S 26 | $(RISCV_GCC) $(CFLAGS) -DASM -c $(incs) $< -o $@ 27 | 28 | $(bld_dir)/v_isr_sample.elf: $(ld_script) $(asm_objs) 29 | $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) 30 | 31 | $(bld_dir)/v_isr_sample.hex: $(bld_dir)/v_isr_sample.elf 32 | $(RISCV_OBJCOPY) $^ $@ 33 | 34 | $(bld_dir)/v_isr_sample.dump: $(bld_dir)/v_isr_sample.elf 35 | $(RISCV_OBJDUMP) $^ > $@ 36 | 37 | clean: 38 | $(RM)$(asm_objs) $(bld_dir)/v_isr_sample.elf $(bld_dir)/v_isr_sample.hex $(bld_dir)/v_isr_sample.dump -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/vectored_isr_sample/Makefile: -------------------------------------------------------------------------------- 1 | src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | CFLAGS += $(FLAGS) \ 4 | -static -std=gnu99 -fno-common -fno-builtin-printf \ 5 | -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) 6 | LDFLAGS += -nostartfiles -nostdlib -march=rv32$(ARCH) -mabi=$(ABI) 7 | 8 | VPATH += $(src_dir) $(inc_dir) 9 | incs += -I$(src_dir) -I$(inc_dir) 10 | 11 | asm_src := v_isr_sample.S 12 | 13 | ifdef TCM 14 | ld_script := $(inc_dir)/link_tcm.ld 15 | else 16 | ld_script := $(inc_dir)/link.ld 17 | endif 18 | 19 | 20 | 21 | asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) 22 | 23 | default: $(bld_dir)/v_isr_sample.elf $(bld_dir)/v_isr_sample.hex $(bld_dir)/v_isr_sample.dump 24 | 25 | $(bld_dir)/%.o: %.S 26 | $(RISCV_GCC) $(CFLAGS) -DASM -c $(incs) $< -o $@ 27 | 28 | $(bld_dir)/v_isr_sample.elf: $(ld_script) $(asm_objs) 29 | $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) 30 | 31 | $(bld_dir)/v_isr_sample.hex: $(bld_dir)/v_isr_sample.elf 32 | $(RISCV_OBJCOPY) $^ $@ 33 | 34 | $(bld_dir)/v_isr_sample.dump: $(bld_dir)/v_isr_sample.elf 35 | $(RISCV_OBJDUMP) $^ > $@ 36 | 37 | clean: 38 | $(RM)$(asm_objs) $(bld_dir)/v_isr_sample.elf $(bld_dir)/v_isr_sample.hex $(bld_dir)/v_isr_sample.dump -------------------------------------------------------------------------------- /scr1/sim/compile.do: -------------------------------------------------------------------------------- 1 | vlog -work work -mfcu -sv "+nowarnSVCHK" +incdir+../src/includes/ +incdir+../../rtl/ \ 2 | ../src/pipeline/scr1_pipe_hdu.sv ../src/pipeline/scr1_pipe_tdu.sv ../src/pipeline/scr1_ipic.sv ../src/pipeline/scr1_pipe_csr.sv ../src/pipeline/scr1_pipe_exu.sv ../src/pipeline/scr1_pipe_ialu.sv ../src/pipeline/scr1_pipe_idu.sv ../src/pipeline/scr1_pipe_ifu.sv ../src/pipeline/scr1_pipe_lsu.sv ../src/pipeline/scr1_pipe_mprf.sv ../src/pipeline/scr1_pipe_top.sv ../src/core/primitives/scr1_reset_cells.sv ../src/core/primitives/scr1_cg.sv ../src/core/scr1_clk_ctrl.sv ../src/core/scr1_tapc_shift_reg.sv ../src/core/scr1_tapc.sv ../src/core/scr1_tapc_synchronizer.sv ../src/core/scr1_core_top.sv ../src/core/scr1_dm.sv ../src/core/scr1_dmi.sv ../src/core/scr1_scu.sv ../src/top/scr1_dmem_router.sv ../src/top/scr1_imem_router.sv ../src/top/scr1_dp_memory.sv ../src/top/scr1_tcm.sv ../src/top/scr1_timer.sv ../src/top/scr1_dmem_ahb.sv ../src/top/scr1_imem_ahb.sv ../src/top/scr1_top_ahb.sv ../src/top/scr1_mem_axi.sv ../src/top/scr1_top_axi.sv ../src/pipeline/scr1_tracelog.sv ../src/tb/scr1_memory_tb_ahb.sv ../src/tb/scr1_top_tb_ahb.sv \ 3 | ../../rtl/ssrv_top.v \ 4 | ../../rtl/sys_csr.v \ 5 | ../../rtl/mul.v \ 6 | ../../rtl/mprf.v \ 7 | ../../rtl/membuf.v \ 8 | ../../rtl/alu.v \ 9 | ../../rtl/schedule.v \ 10 | ../../rtl/instrman.v \ 11 | ../../rtl/instrbits.v \ 12 | ../../rtl/predictor.v \ 13 | ../../rtl/lsu.v \ 14 | ../../testbench/tb_ssrv.v -------------------------------------------------------------------------------- /scr1/sim/verilator_wrap/scr1_axi_wrapper.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include "Vscr1_top_tb_axi.h" 5 | #ifdef VCD_TRACE 6 | #include "verilated_vcd_c.h" 7 | #endif // #ifdef VCD_TRACE 8 | 9 | #define STRINGIFY(s) _STRINGIFY(s) 10 | #define _STRINGIFY(s) #s 11 | 12 | Vscr1_top_tb_axi *top; 13 | 14 | vluint64_t main_time = 0; 15 | 16 | int main(int argc, char** argv) { 17 | Verilated::commandArgs(argc, argv); 18 | 19 | top = new Vscr1_top_tb_axi; 20 | #ifdef VCD_TRACE 21 | Verilated::traceEverOn(true); 22 | VerilatedVcdC* tfp = new VerilatedVcdC; 23 | #ifdef TRACE_LVLV 24 | top->trace(tfp, TRACE_LVLV); 25 | #else 26 | top->trace(tfp, 99); // Trace 99 levels of hierarchy by default 27 | #endif // #ifdef TRACE_LVLV 28 | 29 | #ifdef VCD_FNAME 30 | tfp->open(STRINGIFY(VCD_FNAME)); 31 | #else 32 | tfp->open("./simx.vcd"); 33 | #endif // #ifdef VCD_FNAME 34 | #endif // #ifdef VCD_TRACE 35 | 36 | while (!Verilated::gotFinish()) { 37 | if ((main_time % 10) == 1) { 38 | top->clk = 1; 39 | } 40 | if ((main_time % 10) == 6) { 41 | top->clk = 0; 42 | } 43 | top->eval(); 44 | main_time++; 45 | #ifdef VCD_TRACE 46 | tfp->dump(main_time); 47 | #endif // #ifdef VCD_TRACE 48 | } 49 | top->final(); 50 | #ifdef VCD_TRACE 51 | tfp->close(); 52 | #endif // #ifdef VCD_TRACE 53 | delete top; 54 | } 55 | 56 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/compile.do: -------------------------------------------------------------------------------- 1 | vlog -work work -mfcu -sv "+nowarnSVCHK" +incdir+../src/includes/ +incdir+../../rtl/ \ 2 | ../src/pipeline/scr1_pipe_hdu.sv ../src/pipeline/scr1_pipe_tdu.sv ../src/pipeline/scr1_ipic.sv ../src/pipeline/scr1_pipe_csr.sv ../src/pipeline/scr1_pipe_exu.sv ../src/pipeline/scr1_pipe_ialu.sv ../src/pipeline/scr1_pipe_idu.sv ../src/pipeline/scr1_pipe_ifu.sv ../src/pipeline/scr1_pipe_lsu.sv ../src/pipeline/scr1_pipe_mprf.sv ../src/pipeline/scr1_pipe_top.sv ../src/core/primitives/scr1_reset_cells.sv ../src/core/primitives/scr1_cg.sv ../src/core/scr1_clk_ctrl.sv ../src/core/scr1_tapc_shift_reg.sv ../src/core/scr1_tapc.sv ../src/core/scr1_tapc_synchronizer.sv ../src/core/scr1_core_top.sv ../src/core/scr1_dm.sv ../src/core/scr1_dmi.sv ../src/core/scr1_scu.sv ../src/top/scr1_dmem_router.sv ../src/top/scr1_imem_router.sv ../src/top/scr1_dp_memory.sv ../src/top/scr1_tcm.sv ../src/top/scr1_timer.sv ../src/top/scr1_dmem_ahb.sv ../src/top/scr1_imem_ahb.sv ../src/top/scr1_top_ahb.sv ../src/top/scr1_mem_axi.sv ../src/top/scr1_top_axi.sv ../src/pipeline/scr1_tracelog.sv ../src/tb/scr1_memory_tb_ahb.sv ../src/tb/scr1_top_tb_ahb.sv \ 3 | ../../rtl/ssrv_top.v \ 4 | ../../rtl/sys_csr.v \ 5 | ../../rtl/mul.v \ 6 | ../../rtl/mprf.v \ 7 | ../../rtl/membuf.v \ 8 | ../../rtl/alu.v \ 9 | ../../rtl/predictor.v \ 10 | ../../rtl/schedule.v \ 11 | ../../rtl/instrman.v \ 12 | ../../rtl/instrbits.v \ 13 | ../../rtl/lsu.v \ 14 | ../../rtl/ssrv_pipe_top.sv -------------------------------------------------------------------------------- /scr1/sim/verilator_wrap/scr1_ahb_wrapper.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include "Vscr1_top_tb_ahb.h" 5 | #ifdef VCD_TRACE 6 | #include "verilated_vcd_c.h" 7 | #endif // #ifdef VCD_TRACE 8 | 9 | #define STRINGIFY(s) _STRINGIFY(s) 10 | #define _STRINGIFY(s) #s 11 | 12 | Vscr1_top_tb_ahb *top; 13 | 14 | vluint64_t main_time = 0; 15 | 16 | int main(int argc, char** argv) { 17 | Verilated::commandArgs(argc, argv); 18 | 19 | top = new Vscr1_top_tb_ahb; 20 | 21 | #ifdef VCD_TRACE 22 | Verilated::traceEverOn(true); 23 | VerilatedVcdC* tfp = new VerilatedVcdC; 24 | #ifdef TRACE_LVLV 25 | top->trace(tfp, TRACE_LVLV); 26 | #else 27 | top->trace(tfp, 99); // Trace 99 levels of hierarchy by default 28 | #endif // #ifdef TRACE_LVLV 29 | 30 | #ifdef VCD_FNAME 31 | tfp->open(STRINGIFY(VCD_FNAME)); 32 | #else 33 | tfp->open("./simx.vcd"); 34 | #endif // #ifdef VCD_FNAME 35 | #endif // #ifdef VCD_TRACE 36 | 37 | while (!Verilated::gotFinish()) { 38 | if ((main_time % 10) == 1) { 39 | top->clk = 1; 40 | } 41 | if ((main_time % 10) == 6) { 42 | top->clk = 0; 43 | } 44 | top->eval(); 45 | main_time++; 46 | #ifdef VCD_TRACE 47 | tfp->dump(main_time); 48 | #endif // #ifdef VCD_TRACE 49 | } 50 | top->final(); 51 | #ifdef VCD_TRACE 52 | tfp->close(); 53 | #endif // #ifdef VCD_TRACE 54 | delete top; 55 | } 56 | 57 | -------------------------------------------------------------------------------- /scr1/src/core/scr1_clk_ctrl.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief SCR1 clock control 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | 8 | `ifdef SCR1_CLKCTRL_EN 9 | module scr1_clk_ctrl ( 10 | input logic clk, 11 | input logic rst_n, 12 | input logic test_mode, 13 | 14 | input logic sleep_pipe, 15 | input logic wake_pipe, 16 | 17 | output logic clkout, // always on 18 | output logic clkout_pipe, 19 | output logic clk_pipe_en, 20 | output logic clkout_dbgc // always on (for now) 21 | ); 22 | 23 | assign clkout = clk; 24 | assign clkout_dbgc = clk; 25 | 26 | always_ff @(posedge clk, negedge rst_n) begin 27 | if (~rst_n) begin 28 | clk_pipe_en <= 1'b1; 29 | end else begin 30 | if (clk_pipe_en) begin 31 | if (sleep_pipe & ~wake_pipe) begin 32 | clk_pipe_en <= 1'b0; 33 | end 34 | end else begin // ~clk_pipe_en 35 | if (wake_pipe) begin 36 | clk_pipe_en <= 1'b1; 37 | end 38 | end // pipeline 39 | end 40 | end 41 | 42 | scr1_cg i_scr1_cg_pipe ( 43 | .clk (clk ), 44 | .clk_en (clk_pipe_en), 45 | .test_mode (test_mode ), 46 | .clk_out (clkout_pipe) 47 | ); 48 | 49 | endmodule : scr1_clk_ctrl 50 | 51 | `endif // SCR1_CLKCTRL_EN -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/verilator_wrap/scr1_axi_wrapper.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include "Vscr1_top_tb_axi.h" 5 | #ifdef VCD_TRACE 6 | #include "verilated_vcd_c.h" 7 | #endif // #ifdef VCD_TRACE 8 | 9 | #define STRINGIFY(s) _STRINGIFY(s) 10 | #define _STRINGIFY(s) #s 11 | 12 | Vscr1_top_tb_axi *top; 13 | 14 | vluint64_t main_time = 0; 15 | 16 | int main(int argc, char** argv) { 17 | Verilated::commandArgs(argc, argv); 18 | 19 | top = new Vscr1_top_tb_axi; 20 | #ifdef VCD_TRACE 21 | Verilated::traceEverOn(true); 22 | VerilatedVcdC* tfp = new VerilatedVcdC; 23 | #ifdef TRACE_LVLV 24 | top->trace(tfp, TRACE_LVLV); 25 | #else 26 | top->trace(tfp, 99); // Trace 99 levels of hierarchy by default 27 | #endif // #ifdef TRACE_LVLV 28 | 29 | #ifdef VCD_FNAME 30 | tfp->open(STRINGIFY(VCD_FNAME)); 31 | #else 32 | tfp->open("./simx.vcd"); 33 | #endif // #ifdef VCD_FNAME 34 | #endif // #ifdef VCD_TRACE 35 | 36 | while (!Verilated::gotFinish()) { 37 | if ((main_time % 10) == 1) { 38 | top->clk = 1; 39 | } 40 | if ((main_time % 10) == 6) { 41 | top->clk = 0; 42 | } 43 | top->eval(); 44 | main_time++; 45 | #ifdef VCD_TRACE 46 | tfp->dump(main_time); 47 | #endif // #ifdef VCD_TRACE 48 | } 49 | top->final(); 50 | #ifdef VCD_TRACE 51 | tfp->close(); 52 | #endif // #ifdef VCD_TRACE 53 | delete top; 54 | } 55 | 56 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/verilator_wrap/scr1_ahb_wrapper.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include "Vscr1_top_tb_ahb.h" 5 | #ifdef VCD_TRACE 6 | #include "verilated_vcd_c.h" 7 | #endif // #ifdef VCD_TRACE 8 | 9 | #define STRINGIFY(s) _STRINGIFY(s) 10 | #define _STRINGIFY(s) #s 11 | 12 | Vscr1_top_tb_ahb *top; 13 | 14 | vluint64_t main_time = 0; 15 | 16 | int main(int argc, char** argv) { 17 | Verilated::commandArgs(argc, argv); 18 | 19 | top = new Vscr1_top_tb_ahb; 20 | 21 | #ifdef VCD_TRACE 22 | Verilated::traceEverOn(true); 23 | VerilatedVcdC* tfp = new VerilatedVcdC; 24 | #ifdef TRACE_LVLV 25 | top->trace(tfp, TRACE_LVLV); 26 | #else 27 | top->trace(tfp, 99); // Trace 99 levels of hierarchy by default 28 | #endif // #ifdef TRACE_LVLV 29 | 30 | #ifdef VCD_FNAME 31 | tfp->open(STRINGIFY(VCD_FNAME)); 32 | #else 33 | tfp->open("./simx.vcd"); 34 | #endif // #ifdef VCD_FNAME 35 | #endif // #ifdef VCD_TRACE 36 | 37 | while (!Verilated::gotFinish()) { 38 | if ((main_time % 10) == 1) { 39 | top->clk = 1; 40 | } 41 | if ((main_time % 10) == 6) { 42 | top->clk = 0; 43 | } 44 | top->eval(); 45 | main_time++; 46 | #ifdef VCD_TRACE 47 | tfp->dump(main_time); 48 | #endif // #ifdef VCD_TRACE 49 | } 50 | top->final(); 51 | #ifdef VCD_TRACE 52 | tfp->close(); 53 | #endif // #ifdef VCD_TRACE 54 | delete top; 55 | } 56 | 57 | -------------------------------------------------------------------------------- /scr1/src/includes/scr1_ahb.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_AHB_SVH 2 | `define SCR1_AHB_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief AHB header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | parameter SCR1_AHB_WIDTH = 32; 11 | 12 | // Encoding for HTRANS signal 13 | parameter logic [1:0] SCR1_HTRANS_IDLE = 2'b00; 14 | parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10; 15 | parameter logic [1:0] SCR1_HTRANS_ERR = 'x; 16 | 17 | // Encoding for HBURST signal 18 | parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000; 19 | parameter logic [2:0] SCR1_HBURST_ERR = 'x; 20 | 21 | // Encoding for HSIZE signal 22 | parameter logic [2:0] SCR1_HSIZE_8B = 3'b000; 23 | parameter logic [2:0] SCR1_HSIZE_16B = 3'b001; 24 | parameter logic [2:0] SCR1_HSIZE_32B = 3'b010; 25 | parameter logic [2:0] SCR1_HSIZE_ERR = 'x; 26 | 27 | // Encoding HPROT signal 28 | // HPROT[0] : 0 - instr; 1 - data 29 | // HPROT[1] : 0 - user; 1 - privilege 30 | // HPROT[2] : 0 - not buffer; 1 - buffer 31 | // HPROT[3] : 0 - cacheable; 1 - cacheable 32 | parameter SCR1_HPROT_DATA = 0; 33 | parameter SCR1_HPROT_PRV = 1; 34 | parameter SCR1_HPROT_BUF = 2; 35 | parameter SCR1_HPROT_CACHE = 3; 36 | 37 | // Encoding HRESP signal 38 | parameter logic SCR1_HRESP_OKAY = 1'b0; 39 | parameter logic SCR1_HRESP_ERROR = 1'b1; 40 | parameter logic SCR1_HRESP_ERR = 1'bx; 41 | 42 | `endif // SCR1_AHB_SVH 43 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/core/scr1_clk_ctrl.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief SCR1 clock control 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | 8 | `ifdef SCR1_CLKCTRL_EN 9 | module scr1_clk_ctrl ( 10 | input logic clk, 11 | input logic rst_n, 12 | input logic test_mode, 13 | 14 | input logic sleep_pipe, 15 | input logic wake_pipe, 16 | 17 | output logic clkout, // always on 18 | output logic clkout_pipe, 19 | output logic clk_pipe_en, 20 | output logic clkout_dbgc // always on (for now) 21 | ); 22 | 23 | assign clkout = clk; 24 | assign clkout_dbgc = clk; 25 | 26 | always_ff @(posedge clk, negedge rst_n) begin 27 | if (~rst_n) begin 28 | clk_pipe_en <= 1'b1; 29 | end else begin 30 | if (clk_pipe_en) begin 31 | if (sleep_pipe & ~wake_pipe) begin 32 | clk_pipe_en <= 1'b0; 33 | end 34 | end else begin // ~clk_pipe_en 35 | if (wake_pipe) begin 36 | clk_pipe_en <= 1'b1; 37 | end 38 | end // pipeline 39 | end 40 | end 41 | 42 | scr1_cg i_scr1_cg_pipe ( 43 | .clk (clk ), 44 | .clk_en (clk_pipe_en), 45 | .test_mode (test_mode ), 46 | .clk_out (clkout_pipe) 47 | ); 48 | 49 | endmodule : scr1_clk_ctrl 50 | 51 | `endif // SCR1_CLKCTRL_EN -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/core/scr1_clk_ctrl.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief SCR1 clock control 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | 8 | `ifdef SCR1_CLKCTRL_EN 9 | module scr1_clk_ctrl ( 10 | input logic clk, 11 | input logic rst_n, 12 | input logic test_mode, 13 | 14 | input logic sleep_pipe, 15 | input logic wake_pipe, 16 | 17 | output logic clkout, // always on 18 | output logic clkout_pipe, 19 | output logic clk_pipe_en, 20 | output logic clkout_dbgc // always on (for now) 21 | ); 22 | 23 | assign clkout = clk; 24 | assign clkout_dbgc = clk; 25 | 26 | always_ff @(posedge clk, negedge rst_n) begin 27 | if (~rst_n) begin 28 | clk_pipe_en <= 1'b1; 29 | end else begin 30 | if (clk_pipe_en) begin 31 | if (sleep_pipe & ~wake_pipe) begin 32 | clk_pipe_en <= 1'b0; 33 | end 34 | end else begin // ~clk_pipe_en 35 | if (wake_pipe) begin 36 | clk_pipe_en <= 1'b1; 37 | end 38 | end // pipeline 39 | end 40 | end 41 | 42 | scr1_cg i_scr1_cg_pipe ( 43 | .clk (clk ), 44 | .clk_en (clk_pipe_en), 45 | .test_mode (test_mode ), 46 | .clk_out (clkout_pipe) 47 | ); 48 | 49 | endmodule : scr1_clk_ctrl 50 | 51 | `endif // SCR1_CLKCTRL_EN -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/includes/scr1_ahb.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_AHB_SVH 2 | `define SCR1_AHB_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief AHB header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | parameter SCR1_AHB_WIDTH = 32; 11 | 12 | // Encoding for HTRANS signal 13 | parameter logic [1:0] SCR1_HTRANS_IDLE = 2'b00; 14 | parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10; 15 | parameter logic [1:0] SCR1_HTRANS_ERR = 'x; 16 | 17 | // Encoding for HBURST signal 18 | parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000; 19 | parameter logic [2:0] SCR1_HBURST_ERR = 'x; 20 | 21 | // Encoding for HSIZE signal 22 | parameter logic [2:0] SCR1_HSIZE_8B = 3'b000; 23 | parameter logic [2:0] SCR1_HSIZE_16B = 3'b001; 24 | parameter logic [2:0] SCR1_HSIZE_32B = 3'b010; 25 | parameter logic [2:0] SCR1_HSIZE_ERR = 'x; 26 | 27 | // Encoding HPROT signal 28 | // HPROT[0] : 0 - instr; 1 - data 29 | // HPROT[1] : 0 - user; 1 - privilege 30 | // HPROT[2] : 0 - not buffer; 1 - buffer 31 | // HPROT[3] : 0 - cacheable; 1 - cacheable 32 | parameter SCR1_HPROT_DATA = 0; 33 | parameter SCR1_HPROT_PRV = 1; 34 | parameter SCR1_HPROT_BUF = 2; 35 | parameter SCR1_HPROT_CACHE = 3; 36 | 37 | // Encoding HRESP signal 38 | parameter logic SCR1_HRESP_OKAY = 1'b0; 39 | parameter logic SCR1_HRESP_ERROR = 1'b1; 40 | parameter logic SCR1_HRESP_ERR = 1'bx; 41 | 42 | `endif // SCR1_AHB_SVH 43 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/includes/scr1_ahb.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_AHB_SVH 2 | `define SCR1_AHB_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief AHB header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | parameter SCR1_AHB_WIDTH = 32; 11 | 12 | // Encoding for HTRANS signal 13 | parameter logic [1:0] SCR1_HTRANS_IDLE = 2'b00; 14 | parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10; 15 | parameter logic [1:0] SCR1_HTRANS_ERR = 'x; 16 | 17 | // Encoding for HBURST signal 18 | parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000; 19 | parameter logic [2:0] SCR1_HBURST_ERR = 'x; 20 | 21 | // Encoding for HSIZE signal 22 | parameter logic [2:0] SCR1_HSIZE_8B = 3'b000; 23 | parameter logic [2:0] SCR1_HSIZE_16B = 3'b001; 24 | parameter logic [2:0] SCR1_HSIZE_32B = 3'b010; 25 | parameter logic [2:0] SCR1_HSIZE_ERR = 'x; 26 | 27 | // Encoding HPROT signal 28 | // HPROT[0] : 0 - instr; 1 - data 29 | // HPROT[1] : 0 - user; 1 - privilege 30 | // HPROT[2] : 0 - not buffer; 1 - buffer 31 | // HPROT[3] : 0 - cacheable; 1 - cacheable 32 | parameter SCR1_HPROT_DATA = 0; 33 | parameter SCR1_HPROT_PRV = 1; 34 | parameter SCR1_HPROT_BUF = 2; 35 | parameter SCR1_HPROT_CACHE = 3; 36 | 37 | // Encoding HRESP signal 38 | parameter logic SCR1_HRESP_OKAY = 1'b0; 39 | parameter logic SCR1_HRESP_ERROR = 1'b1; 40 | parameter logic SCR1_HRESP_ERR = 1'bx; 41 | 42 | `endif // SCR1_AHB_SVH 43 | -------------------------------------------------------------------------------- /scr1/sim/tests/common/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012-2015, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012-2015, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /scr1/src/includes/scr1_memif.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_MEMIF_SVH 2 | `define SCR1_MEMIF_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Memory interface definitions file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | //------------------------------------------------------------------------------- 11 | // Memory command enum 12 | //------------------------------------------------------------------------------- 13 | typedef enum logic { 14 | SCR1_MEM_CMD_RD = 1'b0, 15 | SCR1_MEM_CMD_WR = 1'b1, 16 | SCR1_MEM_CMD_ERROR = 'x 17 | } type_scr1_mem_cmd_e; 18 | 19 | //------------------------------------------------------------------------------- 20 | // Memory data width enum 21 | //------------------------------------------------------------------------------- 22 | typedef enum logic[1:0] { 23 | SCR1_MEM_WIDTH_BYTE = 2'b00, 24 | SCR1_MEM_WIDTH_HWORD = 2'b01, 25 | SCR1_MEM_WIDTH_WORD = 2'b10, 26 | SCR1_MEM_WIDTH_ERROR = 'x 27 | } type_scr1_mem_width_e; 28 | 29 | //------------------------------------------------------------------------------- 30 | // Memory response enum 31 | //------------------------------------------------------------------------------- 32 | typedef enum logic[1:0] { 33 | SCR1_MEM_RESP_NOTRDY = 2'b00, 34 | SCR1_MEM_RESP_RDY_OK = 2'b01, 35 | SCR1_MEM_RESP_RDY_ER = 2'b10, 36 | SCR1_MEM_RESP_ERROR = 'x 37 | } type_scr1_mem_resp_e; 38 | 39 | `endif // SCR1_MEMIF_SVH 40 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/includes/scr1_memif.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_MEMIF_SVH 2 | `define SCR1_MEMIF_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Memory interface definitions file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | //------------------------------------------------------------------------------- 11 | // Memory command enum 12 | //------------------------------------------------------------------------------- 13 | typedef enum logic { 14 | SCR1_MEM_CMD_RD = 1'b0, 15 | SCR1_MEM_CMD_WR = 1'b1, 16 | SCR1_MEM_CMD_ERROR = 'x 17 | } type_scr1_mem_cmd_e; 18 | 19 | //------------------------------------------------------------------------------- 20 | // Memory data width enum 21 | //------------------------------------------------------------------------------- 22 | typedef enum logic[1:0] { 23 | SCR1_MEM_WIDTH_BYTE = 2'b00, 24 | SCR1_MEM_WIDTH_HWORD = 2'b01, 25 | SCR1_MEM_WIDTH_WORD = 2'b10, 26 | SCR1_MEM_WIDTH_ERROR = 'x 27 | } type_scr1_mem_width_e; 28 | 29 | //------------------------------------------------------------------------------- 30 | // Memory response enum 31 | //------------------------------------------------------------------------------- 32 | typedef enum logic[1:0] { 33 | SCR1_MEM_RESP_NOTRDY = 2'b00, 34 | SCR1_MEM_RESP_RDY_OK = 2'b01, 35 | SCR1_MEM_RESP_RDY_ER = 2'b10, 36 | SCR1_MEM_RESP_ERROR = 'x 37 | } type_scr1_mem_resp_e; 38 | 39 | `endif // SCR1_MEMIF_SVH 40 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/includes/scr1_memif.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_MEMIF_SVH 2 | `define SCR1_MEMIF_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Memory interface definitions file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | //------------------------------------------------------------------------------- 11 | // Memory command enum 12 | //------------------------------------------------------------------------------- 13 | typedef enum logic { 14 | SCR1_MEM_CMD_RD = 1'b0, 15 | SCR1_MEM_CMD_WR = 1'b1, 16 | SCR1_MEM_CMD_ERROR = 'x 17 | } type_scr1_mem_cmd_e; 18 | 19 | //------------------------------------------------------------------------------- 20 | // Memory data width enum 21 | //------------------------------------------------------------------------------- 22 | typedef enum logic[1:0] { 23 | SCR1_MEM_WIDTH_BYTE = 2'b00, 24 | SCR1_MEM_WIDTH_HWORD = 2'b01, 25 | SCR1_MEM_WIDTH_WORD = 2'b10, 26 | SCR1_MEM_WIDTH_ERROR = 'x 27 | } type_scr1_mem_width_e; 28 | 29 | //------------------------------------------------------------------------------- 30 | // Memory response enum 31 | //------------------------------------------------------------------------------- 32 | typedef enum logic[1:0] { 33 | SCR1_MEM_RESP_NOTRDY = 2'b00, 34 | SCR1_MEM_RESP_RDY_OK = 2'b01, 35 | SCR1_MEM_RESP_RDY_ER = 2'b10, 36 | SCR1_MEM_RESP_ERROR = 'x 37 | } type_scr1_mem_resp_e; 38 | 39 | `endif // SCR1_MEMIF_SVH 40 | -------------------------------------------------------------------------------- /scr1/sim/tests/benchmarks/dhrystone21/Makefile: -------------------------------------------------------------------------------- 1 | src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | FLAGS = -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto 4 | FLAGS_STR = "$(FLAGS)" 5 | 6 | CFLAGS := $(FLAGS) $(EXT_CFLAGS) \ 7 | -static -std=gnu99 -fno-common -fno-builtin-printf \ 8 | -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) \ 9 | -DFLAGS_STR=\"$(FLAGS_STR)\" \ 10 | -DSELF_TIMED=1 -DTIME=1 11 | LDFLAGS := -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI) 12 | VPATH += $(src_dir) $(inc_dir) 13 | incs += -I$(src_dir) -I$(inc_dir) 14 | 15 | ifdef TCM 16 | ld_script := $(inc_dir)/link_tcm.ld 17 | asm_src := crt_tcm.S 18 | else 19 | ld_script := $(inc_dir)/link.ld 20 | asm_src := crt.S 21 | endif 22 | 23 | c_src := sc_print.c dhry_1.c dhry_2.c 24 | 25 | c_objs := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src))) 26 | asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) 27 | 28 | default: $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump 29 | 30 | $(bld_dir)/%.o: %.S 31 | $(RISCV_GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $(incs) $< -o $@ 32 | 33 | $(bld_dir)/%.o: %.c 34 | $(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@ 35 | 36 | $(bld_dir)/dhrystone21.elf: $(ld_script) $(c_objs) $(asm_objs) 37 | $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) 38 | 39 | $(bld_dir)/dhrystone21.hex: $(bld_dir)/dhrystone21.elf 40 | $(RISCV_OBJCOPY) $^ $@ 41 | 42 | $(bld_dir)/dhrystone21.dump: $(bld_dir)/dhrystone21.elf 43 | $(RISCV_OBJDUMP) $^ > $@ 44 | 45 | clean: 46 | $(RM) $(c_objs) $(asm_objs) $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/benchmarks/dhrystone21/Makefile: -------------------------------------------------------------------------------- 1 | src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | FLAGS = -O3 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto 4 | FLAGS_STR = "$(FLAGS)" 5 | 6 | CFLAGS := $(FLAGS) $(EXT_CFLAGS) \ 7 | -static -std=gnu99 -fno-common -fno-builtin-printf \ 8 | -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) \ 9 | -DFLAGS_STR=\"$(FLAGS_STR)\" \ 10 | -DSELF_TIMED=1 -DTIME=1 11 | LDFLAGS := -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI) 12 | VPATH += $(src_dir) $(inc_dir) 13 | incs += -I$(src_dir) -I$(inc_dir) 14 | 15 | ifdef TCM 16 | ld_script := $(inc_dir)/link_tcm.ld 17 | asm_src := crt_tcm.S 18 | else 19 | ld_script := $(inc_dir)/link.ld 20 | asm_src := crt.S 21 | endif 22 | 23 | c_src := sc_print.c dhry_1.c dhry_2.c 24 | 25 | c_objs := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src))) 26 | asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) 27 | 28 | default: $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump 29 | 30 | $(bld_dir)/%.o: %.S 31 | $(RISCV_GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $(incs) $< -o $@ 32 | 33 | $(bld_dir)/%.o: %.c 34 | $(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@ 35 | 36 | $(bld_dir)/dhrystone21.elf: $(ld_script) $(c_objs) $(asm_objs) 37 | $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) 38 | 39 | $(bld_dir)/dhrystone21.hex: $(bld_dir)/dhrystone21.elf 40 | $(RISCV_OBJCOPY) $^ $@ 41 | 42 | $(bld_dir)/dhrystone21.dump: $(bld_dir)/dhrystone21.elf 43 | $(RISCV_OBJDUMP) $^ > $@ 44 | 45 | clean: 46 | $(RM) $(c_objs) $(asm_objs) $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump -------------------------------------------------------------------------------- /rtl/define.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | //Copyright 2019 Li Xinbing 4 | // 5 | //Licensed under the Apache License, Version 2.0 (the "License"); 6 | //you may not use this file except in compliance with the License. 7 | //You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | //Unless required by applicable law or agreed to in writing, software 12 | //distributed under the License is distributed on an "AS IS" BASIS, 13 | //WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | //See the License for the specific language governing permissions and 15 | //limitations under the License. 16 | // 17 | ///////////////////////////////////////////////////////////////////////////////////// 18 | 19 | 20 | `ifndef RTL_DEF 21 | `define RTL_DEF 22 | 23 | //`timescale 1 ns/1 ps 24 | 25 | //index definition 26 | `define IDX(x,y) ((x)*(y))+:(y) 27 | `define N(n) [(n)-1:0] 28 | 29 | //port ddefinition 30 | `define IN(n) input [(n)-1:0] 31 | `define OUT(n) output [(n)-1:0] 32 | `define OUTW(n) output wire [(n)-1:0] 33 | `define OUTR(n) output reg [(n)-1:0] 34 | 35 | //wire & reg definition 36 | `define WIRE(n) wire [(n)-1:0] 37 | `define REG(n) reg [(n)-1:0] 38 | 39 | //combanation logic definition 40 | `define COMB always @* 41 | 42 | //sequential logic definitiaon 43 | `define FF(clk) always @ ( posedge (clk) ) 44 | `define FFpos(clk, rst,signal,bits) always @ ( posedge clk or posedge rst ) if ( rst ) signal <= bits; else 45 | `define FFneg(clk,rstn,signal,bits) always @ ( posedge clk or negedge rstn ) if ( ~(rstn) ) signal <= bits; else 46 | `define FFx(signal,bits) always @ ( posedge clk or posedge rst ) if ( rst ) signal <= bits; else 47 | 48 | //others 49 | `include "define_para.v" 50 | 51 | `endif 52 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/rtl/define.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | //Copyright 2019 Li Xinbing 4 | // 5 | //Licensed under the Apache License, Version 2.0 (the "License"); 6 | //you may not use this file except in compliance with the License. 7 | //You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | //Unless required by applicable law or agreed to in writing, software 12 | //distributed under the License is distributed on an "AS IS" BASIS, 13 | //WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | //See the License for the specific language governing permissions and 15 | //limitations under the License. 16 | // 17 | ///////////////////////////////////////////////////////////////////////////////////// 18 | 19 | 20 | `ifndef RTL_DEF 21 | `define RTL_DEF 22 | 23 | //`timescale 1 ns/1 ps 24 | 25 | //index definition 26 | `define IDX(x,y) ((x)*(y))+:(y) 27 | `define N(n) [(n)-1:0] 28 | 29 | //port ddefinition 30 | `define IN(n) input [(n)-1:0] 31 | `define OUT(n) output [(n)-1:0] 32 | `define OUTW(n) output wire [(n)-1:0] 33 | `define OUTR(n) output reg [(n)-1:0] 34 | 35 | //wire & reg definition 36 | `define WIRE(n) wire [(n)-1:0] 37 | `define REG(n) reg [(n)-1:0] 38 | 39 | //combanation logic definition 40 | `define COMB always @* 41 | 42 | //sequential logic definitiaon 43 | `define FF(clk) always @ ( posedge (clk) ) 44 | `define FFpos(clk, rst,signal,bits) always @ ( posedge clk or posedge rst ) if ( rst ) signal <= bits; else 45 | `define FFneg(clk,rstn,signal,bits) always @ ( posedge clk or negedge rstn ) if ( ~(rstn) ) signal <= bits; else 46 | `define FFx(signal,bits) always @ ( posedge clk or posedge rst ) if ( rst ) signal <= bits; else 47 | 48 | //others 49 | `include "define_para.v" 50 | 51 | `endif 52 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/rtl/define.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | //Copyright 2019 Li Xinbing 4 | // 5 | //Licensed under the Apache License, Version 2.0 (the "License"); 6 | //you may not use this file except in compliance with the License. 7 | //You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | //Unless required by applicable law or agreed to in writing, software 12 | //distributed under the License is distributed on an "AS IS" BASIS, 13 | //WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | //See the License for the specific language governing permissions and 15 | //limitations under the License. 16 | // 17 | ///////////////////////////////////////////////////////////////////////////////////// 18 | 19 | 20 | `ifndef RTL_DEF 21 | `define RTL_DEF 22 | 23 | //`timescale 1 ns/1 ps 24 | 25 | //index definition 26 | `define IDX(x,y) ((x)*(y))+:(y) 27 | `define N(n) [(n)-1:0] 28 | 29 | //port ddefinition 30 | `define IN(n) input [(n)-1:0] 31 | `define OUT(n) output [(n)-1:0] 32 | `define OUTW(n) output wire [(n)-1:0] 33 | `define OUTR(n) output reg [(n)-1:0] 34 | 35 | //wire & reg definition 36 | `define WIRE(n) wire [(n)-1:0] 37 | `define REG(n) reg [(n)-1:0] 38 | 39 | //combanation logic definition 40 | `define COMB always @* 41 | 42 | //sequential logic definitiaon 43 | `define FF(clk) always @ ( posedge (clk) ) 44 | `define FFpos(clk, rst,signal,bits) always @ ( posedge clk or posedge rst ) if ( rst ) signal <= bits; else 45 | `define FFneg(clk,rstn,signal,bits) always @ ( posedge clk or negedge rstn ) if ( ~(rstn) ) signal <= bits; else 46 | `define FFx(signal,bits) always @ ( posedge clk or posedge rst ) if ( rst ) signal <= bits; else 47 | 48 | //others 49 | `include "define_para.v" 50 | 51 | `endif 52 | -------------------------------------------------------------------------------- /scr1/src/includes/scr1_arch_types.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_TYPES_SVH 2 | `define SCR1_ARCH_TYPES_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Pipeline types description file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v; 11 | typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v; 12 | 13 | //------------------------------------------------------------------------------- 14 | // Exception and IRQ codes 15 | //------------------------------------------------------------------------------- 16 | parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4; 17 | 18 | // Exceptions 19 | typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] { 20 | SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU 21 | SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU 22 | SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR 23 | SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM 24 | SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU 25 | SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU 26 | SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU 27 | SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU 28 | SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU 29 | } type_scr1_exc_code_e; 30 | 31 | // IRQs, reset 32 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3; 33 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7; 34 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11; 35 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0; 36 | 37 | //------------------------------------------------------------------------------- 38 | // Operand width for BRKM 39 | //------------------------------------------------------------------------------- 40 | typedef enum logic [1:0] { 41 | SCR1_OP_WIDTH_BYTE = 2'b00, 42 | SCR1_OP_WIDTH_HALF = 2'b01, 43 | SCR1_OP_WIDTH_WORD = 2'b10, 44 | SCR1_OP_WIDTH_ERROR = 'x 45 | } type_scr1_op_width_e; 46 | 47 | `endif //SCR1_ARCH_TYPES_SVH 48 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/includes/scr1_arch_types.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_TYPES_SVH 2 | `define SCR1_ARCH_TYPES_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Pipeline types description file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v; 11 | typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v; 12 | 13 | //------------------------------------------------------------------------------- 14 | // Exception and IRQ codes 15 | //------------------------------------------------------------------------------- 16 | parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4; 17 | 18 | // Exceptions 19 | typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] { 20 | SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU 21 | SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU 22 | SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR 23 | SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM 24 | SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU 25 | SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU 26 | SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU 27 | SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU 28 | SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU 29 | } type_scr1_exc_code_e; 30 | 31 | // IRQs, reset 32 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3; 33 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7; 34 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11; 35 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0; 36 | 37 | //------------------------------------------------------------------------------- 38 | // Operand width for BRKM 39 | //------------------------------------------------------------------------------- 40 | typedef enum logic [1:0] { 41 | SCR1_OP_WIDTH_BYTE = 2'b00, 42 | SCR1_OP_WIDTH_HALF = 2'b01, 43 | SCR1_OP_WIDTH_WORD = 2'b10, 44 | SCR1_OP_WIDTH_ERROR = 'x 45 | } type_scr1_op_width_e; 46 | 47 | `endif //SCR1_ARCH_TYPES_SVH 48 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/includes/scr1_arch_types.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_ARCH_TYPES_SVH 2 | `define SCR1_ARCH_TYPES_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Pipeline types description file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v; 11 | typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v; 12 | 13 | //------------------------------------------------------------------------------- 14 | // Exception and IRQ codes 15 | //------------------------------------------------------------------------------- 16 | parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4; 17 | 18 | // Exceptions 19 | typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] { 20 | SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU 21 | SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU 22 | SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR 23 | SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM 24 | SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU 25 | SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU 26 | SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU 27 | SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU 28 | SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU 29 | } type_scr1_exc_code_e; 30 | 31 | // IRQs, reset 32 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3; 33 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7; 34 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11; 35 | parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0; 36 | 37 | //------------------------------------------------------------------------------- 38 | // Operand width for BRKM 39 | //------------------------------------------------------------------------------- 40 | typedef enum logic [1:0] { 41 | SCR1_OP_WIDTH_BYTE = 2'b00, 42 | SCR1_OP_WIDTH_HALF = 2'b01, 43 | SCR1_OP_WIDTH_WORD = 2'b10, 44 | SCR1_OP_WIDTH_ERROR = 'x 45 | } type_scr1_op_width_e; 46 | 47 | `endif //SCR1_ARCH_TYPES_SVH 48 | -------------------------------------------------------------------------------- /scr1/sim/tests/common/link.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 3 | * @file 4 | * @brief bare metal tests' linker script 5 | */ 6 | 7 | OUTPUT_ARCH( "riscv" ) 8 | ENTRY(_start) 9 | 10 | MEMORY { 11 | RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K 12 | } 13 | 14 | STACK_SIZE = 1024; 15 | 16 | CL_SIZE = 32; 17 | 18 | SECTIONS { 19 | 20 | /* code segment */ 21 | .text.init 0 : { 22 | FILL(0); 23 | . = 0x100 - 12; 24 | SIM_EXIT = .; 25 | LONG(0x13); 26 | SIM_STOP = .; 27 | LONG(0x6F); 28 | LONG(-1); 29 | . = 0x100; 30 | PROVIDE(__TEXT_START__ = .); 31 | *(.text.init) 32 | } >RAM 33 | 34 | .text : { 35 | *crt.o(.text .text.*) 36 | *(.text .text.*) 37 | *(sc_test_section) 38 | . = ALIGN(CL_SIZE); 39 | PROVIDE(__TEXT_END__ = .); 40 | } >RAM 41 | 42 | /* data segment */ 43 | .data : { 44 | *(.data .data.*) 45 | . = ALIGN(CL_SIZE); 46 | } >RAM 47 | 48 | .sdata : { 49 | _gp = . + 0x800; 50 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) 51 | *(.sdata .sdata.* .gnu.linkonce.s.*) 52 | . = ALIGN(CL_SIZE); 53 | } >RAM 54 | 55 | /* thread-local data segment */ 56 | .tdata : { 57 | PROVIDE(_tls_data = .); 58 | PROVIDE(_tdata_begin = .); 59 | *(.tdata .tdata.*) 60 | PROVIDE(_tdata_end = .); 61 | . = ALIGN(CL_SIZE); 62 | } >RAM 63 | 64 | .tbss : { 65 | PROVIDE(__BSS_START__ = .); 66 | *(.tbss .tbss.*) 67 | . = ALIGN(CL_SIZE); 68 | PROVIDE(_tbss_end = .); 69 | } >RAM 70 | 71 | /* bss segment */ 72 | .sbss : { 73 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 74 | *(.scommon) 75 | } >RAM 76 | 77 | .bss : { 78 | *(.bss .bss.*) 79 | . = ALIGN(CL_SIZE); 80 | PROVIDE(__BSS_END__ = .); 81 | } >RAM 82 | 83 | _end = .; 84 | PROVIDE(__end = .); 85 | 86 | /* End of uninitalized data segement */ 87 | 88 | .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : { 89 | FILL(0); 90 | PROVIDE(__STACK_START__ = .); 91 | . += STACK_SIZE; 92 | PROVIDE(__C_STACK_TOP__ = .); 93 | PROVIDE(__STACK_END__ = .); 94 | } >RAM 95 | 96 | /DISCARD/ : { 97 | *(.eh_frame .eh_frame.*) 98 | } 99 | } 100 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/link.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 3 | * @file 4 | * @brief bare metal tests' linker script 5 | */ 6 | 7 | OUTPUT_ARCH( "riscv" ) 8 | ENTRY(_start) 9 | 10 | MEMORY { 11 | RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K 12 | } 13 | 14 | STACK_SIZE = 1024; 15 | 16 | CL_SIZE = 32; 17 | 18 | SECTIONS { 19 | 20 | /* code segment */ 21 | .text.init 0 : { 22 | FILL(0); 23 | . = 0x100 - 12; 24 | SIM_EXIT = .; 25 | LONG(0x13); 26 | SIM_STOP = .; 27 | LONG(0x6F); 28 | LONG(-1); 29 | . = 0x100; 30 | PROVIDE(__TEXT_START__ = .); 31 | *(.text.init) 32 | } >RAM 33 | 34 | .text : { 35 | *crt.o(.text .text.*) 36 | *(.text .text.*) 37 | *(sc_test_section) 38 | . = ALIGN(CL_SIZE); 39 | PROVIDE(__TEXT_END__ = .); 40 | } >RAM 41 | 42 | /* data segment */ 43 | .data : { 44 | *(.data .data.*) 45 | . = ALIGN(CL_SIZE); 46 | } >RAM 47 | 48 | .sdata : { 49 | _gp = . + 0x800; 50 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) 51 | *(.sdata .sdata.* .gnu.linkonce.s.*) 52 | . = ALIGN(CL_SIZE); 53 | } >RAM 54 | 55 | /* thread-local data segment */ 56 | .tdata : { 57 | PROVIDE(_tls_data = .); 58 | PROVIDE(_tdata_begin = .); 59 | *(.tdata .tdata.*) 60 | PROVIDE(_tdata_end = .); 61 | . = ALIGN(CL_SIZE); 62 | } >RAM 63 | 64 | .tbss : { 65 | PROVIDE(__BSS_START__ = .); 66 | *(.tbss .tbss.*) 67 | . = ALIGN(CL_SIZE); 68 | PROVIDE(_tbss_end = .); 69 | } >RAM 70 | 71 | /* bss segment */ 72 | .sbss : { 73 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 74 | *(.scommon) 75 | } >RAM 76 | 77 | .bss : { 78 | *(.bss .bss.*) 79 | . = ALIGN(CL_SIZE); 80 | PROVIDE(__BSS_END__ = .); 81 | } >RAM 82 | 83 | _end = .; 84 | PROVIDE(__end = .); 85 | 86 | /* End of uninitalized data segement */ 87 | 88 | .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : { 89 | FILL(0); 90 | PROVIDE(__STACK_START__ = .); 91 | . += STACK_SIZE; 92 | PROVIDE(__C_STACK_TOP__ = .); 93 | PROVIDE(__STACK_END__ = .); 94 | } >RAM 95 | 96 | /DISCARD/ : { 97 | *(.eh_frame .eh_frame.*) 98 | } 99 | } 100 | -------------------------------------------------------------------------------- /scr1/sim/tests/benchmarks/coremark/Makefile: -------------------------------------------------------------------------------- 1 | src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | FLAGS = -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las 4 | FLAGS_STR = "$(FLAGS)" 5 | 6 | CFLAGS := $(FLAGS) $(EXT_CFLAGS) \ 7 | -static -std=gnu99 -fno-common -fno-builtin-printf \ 8 | -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) \ 9 | -DFLAGS_STR=\"$(FLAGS_STR)\" 10 | LDFLAGS := -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI) 11 | VPATH += $(src_dir) $(src_dir)/src $(inc_dir) 12 | incs += -I$(src_dir) -I$(src_dir)/src -I$(inc_dir) 13 | 14 | ifdef TCM 15 | ld_script := $(inc_dir)/link_tcm.ld 16 | asm_src := crt_tcm.S 17 | else 18 | ld_script := $(inc_dir)/link.ld 19 | asm_src := crt.S 20 | endif 21 | 22 | ifeq ("$(ITERATIONS)","") 23 | ITERATIONS=1 24 | endif 25 | 26 | CFLAGS += -DITERATIONS=$(ITERATIONS) 27 | 28 | c_src := core_portme.c sc_print.c 29 | coremark_src := ./src/core_list_join.c ./src/core_matrix.c ./src/core_main.c ./src/core_util.c ./src/core_state.c 30 | c_src += core_list_join.c core_matrix.c core_main.c core_util.c core_state.c 31 | 32 | c_objs := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src))) 33 | asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) 34 | 35 | 36 | default: check_coremark_src $(bld_dir)/coremark.elf $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump 37 | 38 | check_coremark_src: 39 | @for i in $(coremark_src) ; do \ 40 | if [ ! -f $$i ] ; then \ 41 | printf "\n\n===========================================================================================\n"; \ 42 | printf "Source file: $$i not exist!\n"; \ 43 | printf "Please download CoreMark sources and place it '/coremark/src' directory in this repository\n"; \ 44 | printf "===========================================================================================\n\n"; \ 45 | exit 1; \ 46 | fi \ 47 | done 48 | 49 | 50 | $(bld_dir)/%.o: %.S 51 | $(RISCV_GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $(incs) $< -o $@ 52 | 53 | $(bld_dir)/%.o: %.c 54 | $(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@ 55 | 56 | $(bld_dir)/coremark.elf: $(ld_script) $(c_objs) $(asm_objs) 57 | $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) 58 | 59 | $(bld_dir)/coremark.hex: $(bld_dir)/coremark.elf 60 | $(RISCV_OBJCOPY) $^ $@ 61 | 62 | $(bld_dir)/coremark.dump: $(bld_dir)/coremark.elf 63 | $(RISCV_OBJDUMP) $^ > $@ 64 | 65 | clean: 66 | $(RM) $(c_objs) $(asm_objs) $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump -------------------------------------------------------------------------------- /scr1/sim/tests/vectored_isr_sample/timer.h: -------------------------------------------------------------------------------- 1 | #ifndef __TIMER__H 2 | #define __TIMER__H 3 | 4 | 5 | #define MCAUSE_TMR_IRQ (1 << 31 | 7) 6 | 7 | #define MEM_MTIME_MASK 0xF0000000 8 | #define MEM_MTIME_CTRL 0x00490000 9 | #define MEM_MTIME_DIV 0x00490004 10 | #define MEM_MTIME 0x00490008 11 | #define MEM_MTIMEH 0x0049000C 12 | #define MEM_MTIMECMP 0x00490010 13 | #define MEM_MTIMECMPH 0x00490014 14 | 15 | #define TMP t0 16 | #define TMP2 t1 17 | #define TMP3 t2 18 | 19 | // Reset 20 | .macro _reset_mtime 21 | li TMP, MEM_MTIME 22 | sw zero, 0(TMP) 23 | sw zero, 4(TMP) 24 | .endm 25 | 26 | .macro _reset_mtimecmp 27 | li TMP, MEM_MTIMECMP 28 | not TMP2, zero 29 | sw TMP2, 0(TMP) 30 | sw TMP2, 4(TMP) 31 | .endm 32 | 33 | // Write 34 | .macro _write_mtime_ctrl reg 35 | li TMP, MEM_MTIME_CTRL 36 | sw \reg, 0(TMP) 37 | .endm 38 | 39 | .macro _write_mtime_div reg 40 | li TMP, MEM_MTIME_DIV 41 | sw \reg, 0(TMP) 42 | .endm 43 | 44 | .macro _write_mtimecmp_32 reg 45 | li TMP, MEM_MTIMECMP 46 | li TMP2, -1 47 | sw TMP2, 0(TMP) 48 | sw zero, 4(TMP) 49 | sw \reg, 0(TMP) 50 | .endm 51 | 52 | .macro _write_mtime reg 53 | li TMP, MEM_MTIME 54 | sw \reg, 0(TMP) 55 | .endm 56 | 57 | .macro _read_mtime reg 58 | li TMP, MEM_MTIME 59 | lw \reg, 0(TMP) 60 | .endm 61 | 62 | // Read 63 | .macro _read_mtimecmp reg 64 | li TMP, MEM_MTIMECMP 65 | lw \reg, 0(TMP) 66 | .endm 67 | 68 | .macro _read_mtime_ctrl reg 69 | li TMP, MEM_MTIME_CTRL 70 | lw \reg, 0(TMP) 71 | .endm 72 | 73 | .macro _read_mtime_div reg 74 | li TMP, MEM_MTIME_DIV 75 | lw \reg, 0(TMP) 76 | .endm 77 | 78 | // Misc 79 | .macro _run_timer 80 | li TMP, MEM_MTIME_CTRL 81 | lw TMP2, 0(TMP) 82 | li TMP3, (1 << SCR1_MTIME_CTRL_EN) 83 | or TMP2, TMP2, TMP3 84 | sw TMP2, 0(TMP) 85 | .endm 86 | 87 | .macro _stop_timer 88 | li TMP, MEM_MTIME_CTRL 89 | lw TMP2, 0(TMP) 90 | li TMP3, (1 << SCR1_MTIME_CTRL_EN) 91 | not TMP3, TMP3 92 | and TMP2, TMP2, TMP3 93 | sw TMP2, 0(TMP) 94 | .endm 95 | 96 | 97 | 98 | #endif // #ifndef __TIMER__H 99 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/benchmarks/coremark/Makefile: -------------------------------------------------------------------------------- 1 | src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | 3 | FLAGS = -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las 4 | FLAGS_STR = "$(FLAGS)" 5 | 6 | CFLAGS := $(FLAGS) $(EXT_CFLAGS) \ 7 | -static -std=gnu99 -fno-common -fno-builtin-printf \ 8 | -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) \ 9 | -DFLAGS_STR=\"$(FLAGS_STR)\" 10 | LDFLAGS := -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI) 11 | VPATH += $(src_dir) $(src_dir)/src $(inc_dir) 12 | incs += -I$(src_dir) -I$(src_dir)/src -I$(inc_dir) 13 | 14 | ifdef TCM 15 | ld_script := $(inc_dir)/link_tcm.ld 16 | asm_src := crt_tcm.S 17 | else 18 | ld_script := $(inc_dir)/link.ld 19 | asm_src := crt.S 20 | endif 21 | 22 | ifeq ("$(ITERATIONS)","") 23 | ITERATIONS=1 24 | endif 25 | 26 | CFLAGS += -DITERATIONS=$(ITERATIONS) 27 | 28 | c_src := core_portme.c sc_print.c 29 | coremark_src := ./src/core_list_join.c ./src/core_matrix.c ./src/core_main.c ./src/core_util.c ./src/core_state.c 30 | c_src += core_list_join.c core_matrix.c core_main.c core_util.c core_state.c 31 | 32 | c_objs := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src))) 33 | asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) 34 | 35 | 36 | default: check_coremark_src $(bld_dir)/coremark.elf $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump 37 | 38 | check_coremark_src: 39 | @for i in $(coremark_src) ; do \ 40 | if [ ! -f $$i ] ; then \ 41 | printf "\n\n===========================================================================================\n"; \ 42 | printf "Source file: $$i not exist!\n"; \ 43 | printf "Please download CoreMark sources and place it '/coremark/src' directory in this repository\n"; \ 44 | printf "===========================================================================================\n\n"; \ 45 | exit 1; \ 46 | fi \ 47 | done 48 | 49 | 50 | $(bld_dir)/%.o: %.S 51 | $(RISCV_GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $(incs) $< -o $@ 52 | 53 | $(bld_dir)/%.o: %.c 54 | $(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@ 55 | 56 | $(bld_dir)/coremark.elf: $(ld_script) $(c_objs) $(asm_objs) 57 | $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) 58 | 59 | $(bld_dir)/coremark.hex: $(bld_dir)/coremark.elf 60 | $(RISCV_OBJCOPY) $^ $@ 61 | 62 | $(bld_dir)/coremark.dump: $(bld_dir)/coremark.elf 63 | $(RISCV_OBJDUMP) $^ > $@ 64 | 65 | clean: 66 | $(RM) $(c_objs) $(asm_objs) $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/vectored_isr_sample/timer.h: -------------------------------------------------------------------------------- 1 | #ifndef __TIMER__H 2 | #define __TIMER__H 3 | 4 | 5 | #define MCAUSE_TMR_IRQ (1 << 31 | 7) 6 | 7 | #define MEM_MTIME_MASK 0xF0000000 8 | #define MEM_MTIME_CTRL 0x00490000 9 | #define MEM_MTIME_DIV 0x00490004 10 | #define MEM_MTIME 0x00490008 11 | #define MEM_MTIMEH 0x0049000C 12 | #define MEM_MTIMECMP 0x00490010 13 | #define MEM_MTIMECMPH 0x00490014 14 | 15 | #define TMP t0 16 | #define TMP2 t1 17 | #define TMP3 t2 18 | 19 | // Reset 20 | .macro _reset_mtime 21 | li TMP, MEM_MTIME 22 | sw zero, 0(TMP) 23 | sw zero, 4(TMP) 24 | .endm 25 | 26 | .macro _reset_mtimecmp 27 | li TMP, MEM_MTIMECMP 28 | not TMP2, zero 29 | sw TMP2, 0(TMP) 30 | sw TMP2, 4(TMP) 31 | .endm 32 | 33 | // Write 34 | .macro _write_mtime_ctrl reg 35 | li TMP, MEM_MTIME_CTRL 36 | sw \reg, 0(TMP) 37 | .endm 38 | 39 | .macro _write_mtime_div reg 40 | li TMP, MEM_MTIME_DIV 41 | sw \reg, 0(TMP) 42 | .endm 43 | 44 | .macro _write_mtimecmp_32 reg 45 | li TMP, MEM_MTIMECMP 46 | li TMP2, -1 47 | sw TMP2, 0(TMP) 48 | sw zero, 4(TMP) 49 | sw \reg, 0(TMP) 50 | .endm 51 | 52 | .macro _write_mtime reg 53 | li TMP, MEM_MTIME 54 | sw \reg, 0(TMP) 55 | .endm 56 | 57 | .macro _read_mtime reg 58 | li TMP, MEM_MTIME 59 | lw \reg, 0(TMP) 60 | .endm 61 | 62 | // Read 63 | .macro _read_mtimecmp reg 64 | li TMP, MEM_MTIMECMP 65 | lw \reg, 0(TMP) 66 | .endm 67 | 68 | .macro _read_mtime_ctrl reg 69 | li TMP, MEM_MTIME_CTRL 70 | lw \reg, 0(TMP) 71 | .endm 72 | 73 | .macro _read_mtime_div reg 74 | li TMP, MEM_MTIME_DIV 75 | lw \reg, 0(TMP) 76 | .endm 77 | 78 | // Misc 79 | .macro _run_timer 80 | li TMP, MEM_MTIME_CTRL 81 | lw TMP2, 0(TMP) 82 | li TMP3, (1 << SCR1_MTIME_CTRL_EN) 83 | or TMP2, TMP2, TMP3 84 | sw TMP2, 0(TMP) 85 | .endm 86 | 87 | .macro _stop_timer 88 | li TMP, MEM_MTIME_CTRL 89 | lw TMP2, 0(TMP) 90 | li TMP3, (1 << SCR1_MTIME_CTRL_EN) 91 | not TMP3, TMP3 92 | and TMP2, TMP2, TMP3 93 | sw TMP2, 0(TMP) 94 | .endm 95 | 96 | 97 | 98 | #endif // #ifndef __TIMER__H 99 | -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_compliance/compliance_test.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance Test Header File 2 | // Copyright (c) 2017, Codasip Ltd. All Rights Reserved. 3 | // See LICENSE for license details. 4 | // 5 | // Description: Common header file for RV32I tests 6 | 7 | #ifndef _COMPLIANCE_TEST_H 8 | #define _COMPLIANCE_TEST_H 9 | 10 | //----------------------------------------------------------------------- 11 | // RV Compliance Macros 12 | //----------------------------------------------------------------------- 13 | 14 | #define RV_COMPLIANCE_HALT \ 15 | .global check; \ 16 | la a1, __BSS_START__; \ 17 | la a2, __BSS_END__; \ 18 | j 4f; \ 19 | 3: sw zero, 0(a1); \ 20 | add a1, a1, 4; \ 21 | 4: bne a1, a2, 3b; \ 22 | la sp, __C_STACK_TOP__; \ 23 | la t5, check; \ 24 | jalr x1, t5, 0; \ 25 | beqz a0, 1f; \ 26 | RVTEST_FAIL; \ 27 | 1: RVTEST_PASS \ 28 | 29 | #define RV_COMPLIANCE_RV32M \ 30 | RVTEST_RV32M \ 31 | 32 | #define RV_COMPLIANCE_CODE_BEGIN \ 33 | RVTEST_CODE_BEGIN \ 34 | 35 | #define RV_COMPLIANCE_CODE_END \ 36 | RVTEST_CODE_END \ 37 | 38 | #define RV_COMPLIANCE_DATA_BEGIN \ 39 | RVTEST_DATA_BEGIN \ 40 | 41 | #define RV_COMPLIANCE_DATA_END \ 42 | RVTEST_DATA_END \ 43 | 44 | #endif -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_compliance/compliance_test.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance Test Header File 2 | // Copyright (c) 2017, Codasip Ltd. All Rights Reserved. 3 | // See LICENSE for license details. 4 | // 5 | // Description: Common header file for RV32I tests 6 | 7 | #ifndef _COMPLIANCE_TEST_H 8 | #define _COMPLIANCE_TEST_H 9 | 10 | //----------------------------------------------------------------------- 11 | // RV Compliance Macros 12 | //----------------------------------------------------------------------- 13 | 14 | #define RV_COMPLIANCE_HALT \ 15 | .global check; \ 16 | la a1, __BSS_START__; \ 17 | la a2, __BSS_END__; \ 18 | j 4f; \ 19 | 3: sw zero, 0(a1); \ 20 | add a1, a1, 4; \ 21 | 4: bne a1, a2, 3b; \ 22 | la sp, __C_STACK_TOP__; \ 23 | la t5, check; \ 24 | jalr x1, t5, 0; \ 25 | beqz a0, 1f; \ 26 | RVTEST_FAIL; \ 27 | 1: RVTEST_PASS \ 28 | 29 | #define RV_COMPLIANCE_RV32M \ 30 | RVTEST_RV32M \ 31 | 32 | #define RV_COMPLIANCE_CODE_BEGIN \ 33 | RVTEST_CODE_BEGIN \ 34 | 35 | #define RV_COMPLIANCE_CODE_END \ 36 | RVTEST_CODE_END \ 37 | 38 | #define RV_COMPLIANCE_DATA_BEGIN \ 39 | RVTEST_DATA_BEGIN \ 40 | 41 | #define RV_COMPLIANCE_DATA_END \ 42 | RVTEST_DATA_END \ 43 | 44 | #endif -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/includes/scr1_tapc.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_INCLUDE_TAPC_DEFS 2 | `define SCR1_INCLUDE_TAPC_DEFS 3 | /// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details 4 | /// @file 5 | /// @brief TAPC header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | `ifdef SCR1_DBGC_EN 11 | 12 | //============================================================================== 13 | // Parameters 14 | //============================================================================== 15 | localparam int unsigned SCR1_TAP_STATE_WIDTH = 4; 16 | localparam int unsigned SCR1_TAP_INSTRUCTION_WIDTH = 5; 17 | localparam int unsigned SCR1_TAP_DR_IDCODE_WIDTH = 32; 18 | localparam int unsigned SCR1_TAP_DR_BLD_ID_WIDTH = 32; 19 | localparam int unsigned SCR1_TAP_DR_BYPASS_WIDTH = 1; 20 | //localparam bit [SCR1_TAP_DR_IDCODE_WIDTH-1:0] SCR1_TAP_IDCODE_RISCV_SC = `SCR1_TAP_IDCODE; 21 | localparam bit [SCR1_TAP_DR_BLD_ID_WIDTH-1:0] SCR1_TAP_BLD_ID_VALUE = `SCR1_MIMPID; 22 | 23 | //============================================================================== 24 | // Types 25 | //============================================================================== 26 | typedef enum logic [SCR1_TAP_STATE_WIDTH-1:0] { 27 | SCR1_TAP_STATE_RESET, 28 | SCR1_TAP_STATE_IDLE, 29 | SCR1_TAP_STATE_DR_SEL_SCAN, 30 | SCR1_TAP_STATE_DR_CAPTURE, 31 | SCR1_TAP_STATE_DR_SHIFT, 32 | SCR1_TAP_STATE_DR_EXIT1, 33 | SCR1_TAP_STATE_DR_PAUSE, 34 | SCR1_TAP_STATE_DR_EXIT2, 35 | SCR1_TAP_STATE_DR_UPDATE, 36 | SCR1_TAP_STATE_IR_SEL_SCAN, 37 | SCR1_TAP_STATE_IR_CAPTURE, 38 | SCR1_TAP_STATE_IR_SHIFT, 39 | SCR1_TAP_STATE_IR_EXIT1, 40 | SCR1_TAP_STATE_IR_PAUSE, 41 | SCR1_TAP_STATE_IR_EXIT2, 42 | SCR1_TAP_STATE_IR_UPDATE, 43 | SCR1_TAP_STATE_XXX = 'X 44 | } type_scr1_tap_state_e; 45 | 46 | typedef enum logic [SCR1_TAP_INSTRUCTION_WIDTH - 1:0] { 47 | SCR1_TAP_INSTR_IDCODE = 5'h01, 48 | SCR1_TAP_INSTR_BLD_ID = 5'h04, 49 | SCR1_TAP_INSTR_SCU_ACCESS = 5'h09, 50 | 51 | SCR1_TAP_INSTR_DTMCS = 5'h10, 52 | SCR1_TAP_INSTR_DMI_ACCESS = 5'h11, 53 | 54 | SCR1_TAP_INSTR_BYPASS = 5'h1F, 55 | SCR1_TAP_INSTR_XXX = 'X 56 | } type_scr1_tap_instr_e; 57 | 58 | `endif // SCR1_DBGC_EN 59 | `endif // SCR1_INCLUDE_TAPC_DEFS 60 | -------------------------------------------------------------------------------- /scr1/src/includes/scr1_tapc.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_INCLUDE_TAPC_DEFS 2 | `define SCR1_INCLUDE_TAPC_DEFS 3 | /// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details 4 | /// @file 5 | /// @brief TAPC header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | `ifdef SCR1_DBGC_EN 11 | package scr1_tapc_pkg; 12 | 13 | //============================================================================== 14 | // Parameters 15 | //============================================================================== 16 | localparam int unsigned SCR1_TAP_STATE_WIDTH = 4; 17 | localparam int unsigned SCR1_TAP_INSTRUCTION_WIDTH = 5; 18 | localparam int unsigned SCR1_TAP_DR_IDCODE_WIDTH = 32; 19 | localparam int unsigned SCR1_TAP_DR_BLD_ID_WIDTH = 32; 20 | localparam int unsigned SCR1_TAP_DR_BYPASS_WIDTH = 1; 21 | //localparam bit [SCR1_TAP_DR_IDCODE_WIDTH-1:0] SCR1_TAP_IDCODE_RISCV_SC = `SCR1_TAP_IDCODE; 22 | localparam bit [SCR1_TAP_DR_BLD_ID_WIDTH-1:0] SCR1_TAP_BLD_ID_VALUE = `SCR1_MIMPID; 23 | 24 | //============================================================================== 25 | // Types 26 | //============================================================================== 27 | typedef enum logic [SCR1_TAP_STATE_WIDTH-1:0] { 28 | SCR1_TAP_STATE_RESET, 29 | SCR1_TAP_STATE_IDLE, 30 | SCR1_TAP_STATE_DR_SEL_SCAN, 31 | SCR1_TAP_STATE_DR_CAPTURE, 32 | SCR1_TAP_STATE_DR_SHIFT, 33 | SCR1_TAP_STATE_DR_EXIT1, 34 | SCR1_TAP_STATE_DR_PAUSE, 35 | SCR1_TAP_STATE_DR_EXIT2, 36 | SCR1_TAP_STATE_DR_UPDATE, 37 | SCR1_TAP_STATE_IR_SEL_SCAN, 38 | SCR1_TAP_STATE_IR_CAPTURE, 39 | SCR1_TAP_STATE_IR_SHIFT, 40 | SCR1_TAP_STATE_IR_EXIT1, 41 | SCR1_TAP_STATE_IR_PAUSE, 42 | SCR1_TAP_STATE_IR_EXIT2, 43 | SCR1_TAP_STATE_IR_UPDATE, 44 | SCR1_TAP_STATE_XXX = 'X 45 | } type_scr1_tap_state_e; 46 | 47 | typedef enum logic [SCR1_TAP_INSTRUCTION_WIDTH - 1:0] { 48 | SCR1_TAP_INSTR_IDCODE = 5'h01, 49 | SCR1_TAP_INSTR_BLD_ID = 5'h04, 50 | SCR1_TAP_INSTR_SCU_ACCESS = 5'h09, 51 | 52 | SCR1_TAP_INSTR_DTMCS = 5'h10, 53 | SCR1_TAP_INSTR_DMI_ACCESS = 5'h11, 54 | 55 | SCR1_TAP_INSTR_BYPASS = 5'h1F, 56 | SCR1_TAP_INSTR_XXX = 'X 57 | } type_scr1_tap_instr_e; 58 | 59 | endpackage : scr1_tapc_pkg 60 | 61 | import scr1_tapc_pkg::*; 62 | 63 | `endif // SCR1_DBGC_EN 64 | `endif // SCR1_INCLUDE_TAPC_DEFS 65 | -------------------------------------------------------------------------------- /scr1/sim/tests/common/link_tcm.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 3 | * @file 4 | * @brief bare metal tests' linker script 5 | */ 6 | 7 | OUTPUT_ARCH( "riscv" ) 8 | ENTRY(_start) 9 | 10 | MEMORY { 11 | RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K 12 | TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 64K 13 | } 14 | 15 | STACK_SIZE = 1024; 16 | 17 | CL_SIZE = 32; 18 | 19 | SECTIONS { 20 | 21 | /* code segment */ 22 | .text.init ORIGIN(RAM) : { 23 | FILL(0); 24 | . = 0x100 - 12; 25 | SIM_EXIT = .; 26 | LONG(0x13); 27 | SIM_STOP = .; 28 | LONG(0x6F); 29 | LONG(-1); 30 | . = 0x100; 31 | *crt_tcm.o(.text .text.*) 32 | } >RAM 33 | 34 | __reloc_start = .; 35 | 36 | .text : { 37 | PROVIDE(__TEXT_START__ = .); 38 | *(.text .text.*) 39 | *(sc_test_section) 40 | . = ALIGN(CL_SIZE); 41 | PROVIDE(__TEXT_END__ = .); 42 | } >TCM AT>RAM 43 | 44 | .rodata : { 45 | _gp = . + 0x800; 46 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) 47 | . = ALIGN(16); 48 | } >TCM AT>RAM 49 | 50 | /* data segment */ 51 | .data : { 52 | PROVIDE(__DATA_START__ = .); 53 | *(.data .data.*) 54 | . = ALIGN(CL_SIZE); 55 | } >TCM AT>RAM 56 | 57 | .sdata : { 58 | *(.sdata .sdata.* .gnu.linkonce.s.*) 59 | . = ALIGN(CL_SIZE); 60 | PROVIDE(__DATA_END__ = .); 61 | } >TCM AT>RAM 62 | 63 | /* thread-local data segment */ 64 | .tdata : { 65 | PROVIDE(_tls_data = .); 66 | PROVIDE(_tdata_begin = .); 67 | *(.tdata .tdata.*) 68 | PROVIDE(_tdata_end = .); 69 | . = ALIGN(CL_SIZE); 70 | } >TCM AT>RAM 71 | 72 | .tbss : { 73 | PROVIDE(_tbss_begin = .); 74 | *(.tbss .tbss.*) 75 | . = ALIGN(CL_SIZE); 76 | PROVIDE(_tbss_end = .); 77 | } >TCM AT>RAM 78 | 79 | /* bss segment */ 80 | .sbss : { 81 | PROVIDE(__BSS_START__ = .); 82 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 83 | *(.scommon) 84 | } >TCM AT>RAM 85 | 86 | .bss : { 87 | *(.bss .bss.*) 88 | . = ALIGN(CL_SIZE); 89 | PROVIDE(__BSS_END__ = .); 90 | } >TCM AT>RAM 91 | 92 | _end = .; 93 | PROVIDE(__end = .); 94 | 95 | /* End of uninitalized data segement */ 96 | 97 | .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : { 98 | PROVIDE(__STACK_START__ = .); 99 | . += STACK_SIZE; 100 | PROVIDE(__C_STACK_TOP__ = .); 101 | PROVIDE(__STACK_END__ = .); 102 | } >TCM 103 | 104 | /DISCARD/ : { 105 | *(.eh_frame .eh_frame.*) 106 | } 107 | } 108 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/includes/scr1_tapc.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_INCLUDE_TAPC_DEFS 2 | `define SCR1_INCLUDE_TAPC_DEFS 3 | /// Copyright by Syntacore LLC © 2016-2019. See LICENSE for details 4 | /// @file 5 | /// @brief TAPC header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | `ifdef SCR1_DBGC_EN 11 | package scr1_tapc_pkg; 12 | 13 | //============================================================================== 14 | // Parameters 15 | //============================================================================== 16 | localparam int unsigned SCR1_TAP_STATE_WIDTH = 4; 17 | localparam int unsigned SCR1_TAP_INSTRUCTION_WIDTH = 5; 18 | localparam int unsigned SCR1_TAP_DR_IDCODE_WIDTH = 32; 19 | localparam int unsigned SCR1_TAP_DR_BLD_ID_WIDTH = 32; 20 | localparam int unsigned SCR1_TAP_DR_BYPASS_WIDTH = 1; 21 | //localparam bit [SCR1_TAP_DR_IDCODE_WIDTH-1:0] SCR1_TAP_IDCODE_RISCV_SC = `SCR1_TAP_IDCODE; 22 | localparam bit [SCR1_TAP_DR_BLD_ID_WIDTH-1:0] SCR1_TAP_BLD_ID_VALUE = `SCR1_MIMPID; 23 | 24 | //============================================================================== 25 | // Types 26 | //============================================================================== 27 | typedef enum logic [SCR1_TAP_STATE_WIDTH-1:0] { 28 | SCR1_TAP_STATE_RESET, 29 | SCR1_TAP_STATE_IDLE, 30 | SCR1_TAP_STATE_DR_SEL_SCAN, 31 | SCR1_TAP_STATE_DR_CAPTURE, 32 | SCR1_TAP_STATE_DR_SHIFT, 33 | SCR1_TAP_STATE_DR_EXIT1, 34 | SCR1_TAP_STATE_DR_PAUSE, 35 | SCR1_TAP_STATE_DR_EXIT2, 36 | SCR1_TAP_STATE_DR_UPDATE, 37 | SCR1_TAP_STATE_IR_SEL_SCAN, 38 | SCR1_TAP_STATE_IR_CAPTURE, 39 | SCR1_TAP_STATE_IR_SHIFT, 40 | SCR1_TAP_STATE_IR_EXIT1, 41 | SCR1_TAP_STATE_IR_PAUSE, 42 | SCR1_TAP_STATE_IR_EXIT2, 43 | SCR1_TAP_STATE_IR_UPDATE, 44 | SCR1_TAP_STATE_XXX = 'X 45 | } type_scr1_tap_state_e; 46 | 47 | typedef enum logic [SCR1_TAP_INSTRUCTION_WIDTH - 1:0] { 48 | SCR1_TAP_INSTR_IDCODE = 5'h01, 49 | SCR1_TAP_INSTR_BLD_ID = 5'h04, 50 | SCR1_TAP_INSTR_SCU_ACCESS = 5'h09, 51 | 52 | SCR1_TAP_INSTR_DTMCS = 5'h10, 53 | SCR1_TAP_INSTR_DMI_ACCESS = 5'h11, 54 | 55 | SCR1_TAP_INSTR_BYPASS = 5'h1F, 56 | SCR1_TAP_INSTR_XXX = 'X 57 | } type_scr1_tap_instr_e; 58 | 59 | endpackage : scr1_tapc_pkg 60 | 61 | import scr1_tapc_pkg::*; 62 | 63 | `endif // SCR1_DBGC_EN 64 | `endif // SCR1_INCLUDE_TAPC_DEFS 65 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/link_tcm.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 3 | * @file 4 | * @brief bare metal tests' linker script 5 | */ 6 | 7 | OUTPUT_ARCH( "riscv" ) 8 | ENTRY(_start) 9 | 10 | MEMORY { 11 | RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K 12 | TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 64K 13 | } 14 | 15 | STACK_SIZE = 1024; 16 | 17 | CL_SIZE = 32; 18 | 19 | SECTIONS { 20 | 21 | /* code segment */ 22 | .text.init ORIGIN(RAM) : { 23 | FILL(0); 24 | . = 0x100 - 12; 25 | SIM_EXIT = .; 26 | LONG(0x13); 27 | SIM_STOP = .; 28 | LONG(0x6F); 29 | LONG(-1); 30 | . = 0x100; 31 | *crt_tcm.o(.text .text.*) 32 | } >RAM 33 | 34 | __reloc_start = .; 35 | 36 | .text : { 37 | PROVIDE(__TEXT_START__ = .); 38 | *(.text .text.*) 39 | *(sc_test_section) 40 | . = ALIGN(CL_SIZE); 41 | PROVIDE(__TEXT_END__ = .); 42 | } >TCM AT>RAM 43 | 44 | .rodata : { 45 | _gp = . + 0x800; 46 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) 47 | . = ALIGN(16); 48 | } >TCM AT>RAM 49 | 50 | /* data segment */ 51 | .data : { 52 | PROVIDE(__DATA_START__ = .); 53 | *(.data .data.*) 54 | . = ALIGN(CL_SIZE); 55 | } >TCM AT>RAM 56 | 57 | .sdata : { 58 | *(.sdata .sdata.* .gnu.linkonce.s.*) 59 | . = ALIGN(CL_SIZE); 60 | PROVIDE(__DATA_END__ = .); 61 | } >TCM AT>RAM 62 | 63 | /* thread-local data segment */ 64 | .tdata : { 65 | PROVIDE(_tls_data = .); 66 | PROVIDE(_tdata_begin = .); 67 | *(.tdata .tdata.*) 68 | PROVIDE(_tdata_end = .); 69 | . = ALIGN(CL_SIZE); 70 | } >TCM AT>RAM 71 | 72 | .tbss : { 73 | PROVIDE(_tbss_begin = .); 74 | *(.tbss .tbss.*) 75 | . = ALIGN(CL_SIZE); 76 | PROVIDE(_tbss_end = .); 77 | } >TCM AT>RAM 78 | 79 | /* bss segment */ 80 | .sbss : { 81 | PROVIDE(__BSS_START__ = .); 82 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 83 | *(.scommon) 84 | } >TCM AT>RAM 85 | 86 | .bss : { 87 | *(.bss .bss.*) 88 | . = ALIGN(CL_SIZE); 89 | PROVIDE(__BSS_END__ = .); 90 | } >TCM AT>RAM 91 | 92 | _end = .; 93 | PROVIDE(__end = .); 94 | 95 | /* End of uninitalized data segement */ 96 | 97 | .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : { 98 | PROVIDE(__STACK_START__ = .); 99 | . += STACK_SIZE; 100 | PROVIDE(__C_STACK_TOP__ = .); 101 | PROVIDE(__STACK_END__ = .); 102 | } >TCM 103 | 104 | /DISCARD/ : { 105 | *(.eh_frame .eh_frame.*) 106 | } 107 | } 108 | -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_isa/rv32_tests.inc: -------------------------------------------------------------------------------- 1 | 2 | ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z) 3 | 4 | 5 | rv32_isa_tests += isa/rv32ui/add.S \ 6 | isa/rv32ui/addi.S \ 7 | isa/rv32ui/and.S \ 8 | isa/rv32ui/andi.S \ 9 | isa/rv32ui/auipc.S \ 10 | isa/rv32ui/beq.S \ 11 | isa/rv32ui/bge.S \ 12 | isa/rv32ui/bgeu.S \ 13 | isa/rv32ui/blt.S \ 14 | isa/rv32ui/bltu.S \ 15 | isa/rv32ui/bne.S \ 16 | isa/rv32mi/csr.S \ 17 | isa/rv32um/div.S \ 18 | isa/rv32um/divu.S \ 19 | isa/rv32ui/fence_i.S \ 20 | isa/rv32mi/illegal.S \ 21 | isa/rv32ui/jal.S \ 22 | isa/rv32ui/jalr.S \ 23 | isa/rv32ui/lb.S \ 24 | isa/rv32ui/lbu.S \ 25 | isa/rv32ui/lh.S \ 26 | isa/rv32ui/lhu.S \ 27 | isa/rv32ui/lui.S \ 28 | isa/rv32ui/lw.S \ 29 | isa/rv32mi/ma_addr.S \ 30 | isa/rv32mi/ma_fetch.S \ 31 | isa/rv32mi/mcsr.S \ 32 | isa/rv32ui/or.S \ 33 | isa/rv32ui/ori.S \ 34 | isa/rv32uc/rvc.S \ 35 | isa/rv32ui/sb.S \ 36 | isa/rv32mi/sbreak.S \ 37 | isa/rv32mi/scall.S \ 38 | isa/rv32ui/sh.S \ 39 | isa/rv32mi/shamt.S \ 40 | isa/rv32ui/simple.S \ 41 | isa/rv32ui/sll.S \ 42 | isa/rv32ui/slli.S \ 43 | isa/rv32ui/slt.S \ 44 | isa/rv32ui/slti.S \ 45 | isa/rv32ui/sltiu.S \ 46 | isa/rv32ui/sltu.S \ 47 | isa/rv32ui/sra.S \ 48 | isa/rv32ui/srai.S \ 49 | isa/rv32ui/srl.S \ 50 | isa/rv32ui/srli.S \ 51 | isa/rv32ui/sub.S \ 52 | isa/rv32ui/sw.S \ 53 | isa/rv32ui/xor.S \ 54 | isa/rv32ui/xori.S 55 | 56 | ifneq (,$(findstring m,$(ARCH_lowercase))) 57 | rv32_isa_tests += isa/rv32um/mul.S \ 58 | isa/rv32um/mulh.S \ 59 | isa/rv32um/mulhsu.S \ 60 | isa/rv32um/mulhu.S \ 61 | isa/rv32um/rem.S \ 62 | isa/rv32um/remu.S 63 | endif ## ifeq (m,$(findstring m,$(ARCH_lowercase))) 64 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_isa/rv32_tests.inc: -------------------------------------------------------------------------------- 1 | 2 | ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z) 3 | 4 | 5 | rv32_isa_tests += isa/rv32ui/add.S \ 6 | isa/rv32ui/addi.S \ 7 | isa/rv32ui/and.S \ 8 | isa/rv32ui/andi.S \ 9 | isa/rv32ui/auipc.S \ 10 | isa/rv32ui/beq.S \ 11 | isa/rv32ui/bge.S \ 12 | isa/rv32ui/bgeu.S \ 13 | isa/rv32ui/blt.S \ 14 | isa/rv32ui/bltu.S \ 15 | isa/rv32ui/bne.S \ 16 | isa/rv32mi/csr.S \ 17 | isa/rv32um/div.S \ 18 | isa/rv32um/divu.S \ 19 | isa/rv32ui/fence_i.S \ 20 | isa/rv32mi/illegal.S \ 21 | isa/rv32ui/jal.S \ 22 | isa/rv32ui/jalr.S \ 23 | isa/rv32ui/lb.S \ 24 | isa/rv32ui/lbu.S \ 25 | isa/rv32ui/lh.S \ 26 | isa/rv32ui/lhu.S \ 27 | isa/rv32ui/lui.S \ 28 | isa/rv32ui/lw.S \ 29 | isa/rv32mi/ma_addr.S \ 30 | isa/rv32mi/ma_fetch.S \ 31 | isa/rv32mi/mcsr.S \ 32 | isa/rv32ui/or.S \ 33 | isa/rv32ui/ori.S \ 34 | isa/rv32uc/rvc.S \ 35 | isa/rv32ui/sb.S \ 36 | isa/rv32mi/sbreak.S \ 37 | isa/rv32mi/scall.S \ 38 | isa/rv32ui/sh.S \ 39 | isa/rv32mi/shamt.S \ 40 | isa/rv32ui/simple.S \ 41 | isa/rv32ui/sll.S \ 42 | isa/rv32ui/slli.S \ 43 | isa/rv32ui/slt.S \ 44 | isa/rv32ui/slti.S \ 45 | isa/rv32ui/sltiu.S \ 46 | isa/rv32ui/sltu.S \ 47 | isa/rv32ui/sra.S \ 48 | isa/rv32ui/srai.S \ 49 | isa/rv32ui/srl.S \ 50 | isa/rv32ui/srli.S \ 51 | isa/rv32ui/sub.S \ 52 | isa/rv32ui/sw.S \ 53 | isa/rv32ui/xor.S \ 54 | isa/rv32ui/xori.S 55 | 56 | ifneq (,$(findstring m,$(ARCH_lowercase))) 57 | rv32_isa_tests += isa/rv32um/mul.S \ 58 | isa/rv32um/mulh.S \ 59 | isa/rv32um/mulhsu.S \ 60 | isa/rv32um/mulhu.S \ 61 | isa/rv32um/rem.S \ 62 | isa/rv32um/remu.S 63 | endif ## ifeq (m,$(findstring m,$(ARCH_lowercase))) 64 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/DE2_115/DE2_115.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************** 2 | # This .sdc file is created by Terasic Tool. 3 | # Users are recommended to modify this file to match users logic. 4 | #************************************************************** 5 | 6 | #************************************************************** 7 | # Create Clock 8 | #************************************************************** 9 | create_clock -period 20.000ns [get_ports CLOCK_50] 10 | create_clock -period 20.000ns [get_ports CLOCK2_50] 11 | create_clock -period 20.000ns [get_ports CLOCK3_50] 12 | 13 | #************************************************************** 14 | # Create Generated Clock 15 | #************************************************************** 16 | derive_pll_clocks 17 | 18 | 19 | 20 | #************************************************************** 21 | # Set Clock Latency 22 | #************************************************************** 23 | 24 | 25 | 26 | #************************************************************** 27 | # Set Clock Uncertainty 28 | #************************************************************** 29 | derive_clock_uncertainty 30 | 31 | 32 | 33 | #************************************************************** 34 | # Set Input Delay 35 | #************************************************************** 36 | 37 | 38 | 39 | #************************************************************** 40 | # Set Output Delay 41 | #************************************************************** 42 | 43 | 44 | 45 | #************************************************************** 46 | # Set Clock Groups 47 | #************************************************************** 48 | 49 | 50 | 51 | #************************************************************** 52 | # Set False Path 53 | #************************************************************** 54 | 55 | 56 | 57 | #************************************************************** 58 | # Set Multicycle Path 59 | #************************************************************** 60 | 61 | 62 | 63 | #************************************************************** 64 | # Set Maximum Delay 65 | #************************************************************** 66 | 67 | 68 | 69 | #************************************************************** 70 | # Set Minimum Delay 71 | #************************************************************** 72 | 73 | 74 | 75 | #************************************************************** 76 | # Set Input Transition 77 | #************************************************************** 78 | 79 | 80 | 81 | #************************************************************** 82 | # Set Load 83 | #************************************************************** 84 | 85 | 86 | 87 | -------------------------------------------------------------------------------- /scr1/sim/Makefile: -------------------------------------------------------------------------------- 1 | # src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | rtl_src_dir := $(root_dir)/src/ 3 | rtl_core_files ?= core.files 4 | rtl_top_files ?= ahb_top.files 5 | rtl_tb_files ?= ahb_tb.files 6 | rtl_inc_dir ?= $(root_dir)/src/includes 7 | top_module ?= scr1_top_tb_ahb 8 | 9 | rtl_core_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_core_files))) 10 | rtl_top_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_top_files))) 11 | rtl_tb_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_tb_files))) 12 | sv_list := $(rtl_core_list) $(rtl_top_list) $(rtl_tb_list) 13 | 14 | ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),build_verilator build_verilator_wf)) 15 | ifeq ($(BUS),AHB) 16 | export scr1_wrapper := $(root_dir)/sim/verilator_wrap/scr1_ahb_wrapper.c 17 | endif 18 | ifeq ($(BUS),AXI) 19 | export scr1_wrapper := $(root_dir)/sim/verilator_wrap/scr1_axi_wrapper.c 20 | endif 21 | export verilator_ver ?= $(shell expr `verilator --version | cut -f2 -d' '`) 22 | endif 23 | 24 | .PHONY: build_modelsim build_vcs build_ncsim build_verilator build_verilator_wf 25 | 26 | default: build_modelsim 27 | 28 | build_modelsim: $(sv_list) 29 | cd $(bld_dir); \ 30 | vlib work; \ 31 | vmap work work; \ 32 | vlog -work work -O1 -mfcu -sv +incdir+$(rtl_inc_dir) +nowarnSVCHK \ 33 | +define+SCR1_SIM_ENV \ 34 | $(sv_list) 35 | 36 | build_vcs: $(sv_list) 37 | cd $(bld_dir); \ 38 | vcs \ 39 | -full64 \ 40 | -lca \ 41 | -sverilog \ 42 | -notice \ 43 | +lint=all,noVCDE \ 44 | -timescale=1ns/1ps \ 45 | +incdir+$(rtl_inc_dir) \ 46 | +define+SCR1_SIM_ENV \ 47 | -nc \ 48 | -debug_all \ 49 | $(sv_list) 50 | 51 | build_ncsim: $(sv_list) 52 | cd $(bld_dir); \ 53 | irun \ 54 | -elaborate \ 55 | -64bit \ 56 | -disable_sem2009 \ 57 | -verbose \ 58 | -timescale 1ns/1ps \ 59 | -incdir $(rtl_inc_dir) \ 60 | -debug \ 61 | +define+SCR1_SIM_ENV \ 62 | $(sv_list) \ 63 | -top $(top_module) 64 | 65 | build_verilator: $(sv_list) 66 | cd $(bld_dir); \ 67 | verilator \ 68 | -cc \ 69 | -sv \ 70 | +1800-2017ext+sv \ 71 | -Wno-fatal \ 72 | --top-module $(top_module) \ 73 | -DSCR1_SIM_ENV \ 74 | --clk clk \ 75 | --exe $(scr1_wrapper) \ 76 | --Mdir $(bld_dir)/verilator \ 77 | -I$(rtl_inc_dir) \ 78 | $(sv_list); \ 79 | cd verilator; \ 80 | $(MAKE) -f V$(top_module).mk; 81 | 82 | build_verilator_wf: $(sv_list) 83 | cd $(bld_dir); \ 84 | verilator \ 85 | -cc \ 86 | -sv \ 87 | +1800-2017ext+sv \ 88 | -Wno-fatal \ 89 | --top-module $(top_module) \ 90 | -DSCR1_SIM_ENV \ 91 | -CFLAGS -DVCD_TRACE -CFLAGS -DTRACE_LVLV=20 \ 92 | -CFLAGS -DVCD_FNAME=simx.vcd \ 93 | --clk clk \ 94 | --exe $(scr1_wrapper) \ 95 | --trace \ 96 | --trace-params \ 97 | --trace-structs \ 98 | --trace-underscore \ 99 | --Mdir $(bld_dir)/verilator \ 100 | -I$(rtl_inc_dir) \ 101 | $(sv_list); \ 102 | cd verilator; \ 103 | $(MAKE) -f V$(top_module).mk; 104 | 105 | 106 | -------------------------------------------------------------------------------- /scr1/src/includes/scr1_ipic.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_IPIC_SVH 2 | `define SCR1_IPIC_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief IPIC header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | `ifdef SCR1_IPIC_EN 11 | //------------------------------------------------------------------------------- 12 | // Parameters declaration 13 | //------------------------------------------------------------------------------- 14 | parameter SCR1_IRQ_VECT_NUM = 16; // must be power of 2 in the current implementation 15 | parameter SCR1_IRQ_VECT_WIDTH = $clog2(SCR1_IRQ_VECT_NUM+1); 16 | parameter SCR1_IRQ_LINES_NUM = SCR1_IRQ_VECT_NUM; 17 | parameter SCR1_IRQ_LINES_WIDTH = $clog2(SCR1_IRQ_LINES_NUM); 18 | parameter logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM); 19 | parameter SCR1_IRQ_IDX_WIDTH = $clog2(SCR1_IRQ_VECT_NUM); 20 | 21 | // Address decoding parameters 22 | parameter logic [2:0] SCR1_IPIC_CISV = 3'h0; // RO 23 | parameter logic [2:0] SCR1_IPIC_CICSR = 3'h1; // {IP, IE} 24 | parameter logic [2:0] SCR1_IPIC_IPR = 3'h2; // RW1C 25 | parameter logic [2:0] SCR1_IPIC_ISVR = 3'h3; // RO 26 | parameter logic [2:0] SCR1_IPIC_EOI = 3'h4; // RZW 27 | parameter logic [2:0] SCR1_IPIC_SOI = 3'h5; // RZW 28 | parameter logic [2:0] SCR1_IPIC_IDX = 3'h6; // RW 29 | parameter logic [2:0] SCR1_IPIC_ICSR = 3'h7; // RW 30 | 31 | parameter SCR1_IPIC_ICSR_IP = 0; 32 | parameter SCR1_IPIC_ICSR_IE = 1; 33 | parameter SCR1_IPIC_ICSR_IM = 2; 34 | parameter SCR1_IPIC_ICSR_INV = 3; 35 | parameter SCR1_IPIC_ICSR_IS = 4; 36 | parameter SCR1_IPIC_ICSR_PRV_LSB = 8; 37 | parameter SCR1_IPIC_ICSR_PRV_MSB = 9; 38 | parameter SCR1_IPIC_ICSR_LN_LSB = 12; 39 | 40 | parameter logic [1:0] SCR1_IPIC_PRV_M = 2'b11; 41 | 42 | //------------------------------------------------------------------------------- 43 | // Types declaration 44 | //------------------------------------------------------------------------------- 45 | typedef enum logic { 46 | SCR1_CSR2IPIC_RD, 47 | SCR1_CSR2IPIC_WR, 48 | SCR1_CSR2IPIC_ERROR = 'x 49 | } type_scr1_csr2ipic_wr_e; 50 | 51 | `endif // SCR1_IPIC_EN 52 | `endif // SCR1_IPIC_SVH 53 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/includes/scr1_ipic.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_IPIC_SVH 2 | `define SCR1_IPIC_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief IPIC header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | `ifdef SCR1_IPIC_EN 11 | //------------------------------------------------------------------------------- 12 | // Parameters declaration 13 | //------------------------------------------------------------------------------- 14 | parameter SCR1_IRQ_VECT_NUM = 16; // must be power of 2 in the current implementation 15 | parameter SCR1_IRQ_VECT_WIDTH = $clog2(SCR1_IRQ_VECT_NUM+1); 16 | parameter SCR1_IRQ_LINES_NUM = SCR1_IRQ_VECT_NUM; 17 | parameter SCR1_IRQ_LINES_WIDTH = $clog2(SCR1_IRQ_LINES_NUM); 18 | parameter logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM); 19 | parameter SCR1_IRQ_IDX_WIDTH = $clog2(SCR1_IRQ_VECT_NUM); 20 | 21 | // Address decoding parameters 22 | parameter logic [2:0] SCR1_IPIC_CISV = 3'h0; // RO 23 | parameter logic [2:0] SCR1_IPIC_CICSR = 3'h1; // {IP, IE} 24 | parameter logic [2:0] SCR1_IPIC_IPR = 3'h2; // RW1C 25 | parameter logic [2:0] SCR1_IPIC_ISVR = 3'h3; // RO 26 | parameter logic [2:0] SCR1_IPIC_EOI = 3'h4; // RZW 27 | parameter logic [2:0] SCR1_IPIC_SOI = 3'h5; // RZW 28 | parameter logic [2:0] SCR1_IPIC_IDX = 3'h6; // RW 29 | parameter logic [2:0] SCR1_IPIC_ICSR = 3'h7; // RW 30 | 31 | parameter SCR1_IPIC_ICSR_IP = 0; 32 | parameter SCR1_IPIC_ICSR_IE = 1; 33 | parameter SCR1_IPIC_ICSR_IM = 2; 34 | parameter SCR1_IPIC_ICSR_INV = 3; 35 | parameter SCR1_IPIC_ICSR_IS = 4; 36 | parameter SCR1_IPIC_ICSR_PRV_LSB = 8; 37 | parameter SCR1_IPIC_ICSR_PRV_MSB = 9; 38 | parameter SCR1_IPIC_ICSR_LN_LSB = 12; 39 | 40 | parameter logic [1:0] SCR1_IPIC_PRV_M = 2'b11; 41 | 42 | //------------------------------------------------------------------------------- 43 | // Types declaration 44 | //------------------------------------------------------------------------------- 45 | typedef enum logic { 46 | SCR1_CSR2IPIC_RD, 47 | SCR1_CSR2IPIC_WR, 48 | SCR1_CSR2IPIC_ERROR = 'x 49 | } type_scr1_csr2ipic_wr_e; 50 | 51 | `endif // SCR1_IPIC_EN 52 | `endif // SCR1_IPIC_SVH 53 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/Makefile: -------------------------------------------------------------------------------- 1 | # src_dir := $(dir $(lastword $(MAKEFILE_LIST))) 2 | rtl_src_dir := $(root_dir)/src/ 3 | rtl_core_files ?= core.files 4 | rtl_top_files ?= ahb_top.files 5 | rtl_tb_files ?= ahb_tb.files 6 | rtl_inc_dir ?= $(root_dir)/src/includes 7 | top_module ?= scr1_top_tb_ahb 8 | 9 | rtl_core_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_core_files))) 10 | rtl_top_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_top_files))) 11 | rtl_tb_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_tb_files))) 12 | sv_list := $(rtl_core_list) $(rtl_top_list) $(rtl_tb_list) 13 | 14 | ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),build_verilator build_verilator_wf)) 15 | ifeq ($(BUS),AHB) 16 | export scr1_wrapper := $(root_dir)/sim/verilator_wrap/scr1_ahb_wrapper.c 17 | endif 18 | ifeq ($(BUS),AXI) 19 | export scr1_wrapper := $(root_dir)/sim/verilator_wrap/scr1_axi_wrapper.c 20 | endif 21 | export verilator_ver ?= $(shell expr `verilator --version | cut -f2 -d' '`) 22 | endif 23 | 24 | .PHONY: build_modelsim build_vcs build_ncsim build_verilator build_verilator_wf 25 | 26 | default: build_modelsim 27 | 28 | build_modelsim: $(sv_list) 29 | cd $(bld_dir); \ 30 | vlib work; \ 31 | vmap work work; \ 32 | vlog -work work -O1 -mfcu -sv +incdir+$(rtl_inc_dir) +nowarnSVCHK \ 33 | +define+SCR1_SIM_ENV \ 34 | $(sv_list) 35 | 36 | build_vcs: $(sv_list) 37 | cd $(bld_dir); \ 38 | vcs \ 39 | -full64 \ 40 | -lca \ 41 | -sverilog \ 42 | -notice \ 43 | +lint=all,noVCDE \ 44 | -timescale=1ns/1ps \ 45 | +incdir+$(rtl_inc_dir) \ 46 | +define+SCR1_SIM_ENV \ 47 | -nc \ 48 | -debug_all \ 49 | $(sv_list) 50 | 51 | build_ncsim: $(sv_list) 52 | cd $(bld_dir); \ 53 | irun \ 54 | -elaborate \ 55 | -64bit \ 56 | -disable_sem2009 \ 57 | -verbose \ 58 | -timescale 1ns/1ps \ 59 | -incdir $(rtl_inc_dir) \ 60 | -debug \ 61 | +define+SCR1_SIM_ENV \ 62 | $(sv_list) \ 63 | -top $(top_module) 64 | 65 | build_verilator: $(sv_list) 66 | cd $(bld_dir); \ 67 | verilator \ 68 | -cc \ 69 | -sv \ 70 | +1800-2017ext+sv \ 71 | -Wno-fatal \ 72 | --top-module $(top_module) \ 73 | -DSCR1_SIM_ENV \ 74 | --clk clk \ 75 | --exe $(scr1_wrapper) \ 76 | --Mdir $(bld_dir)/verilator \ 77 | -I$(rtl_inc_dir) \ 78 | $(sv_list); \ 79 | cd verilator; \ 80 | $(MAKE) -f V$(top_module).mk; 81 | 82 | build_verilator_wf: $(sv_list) 83 | cd $(bld_dir); \ 84 | verilator \ 85 | -cc \ 86 | -sv \ 87 | +1800-2017ext+sv \ 88 | -Wno-fatal \ 89 | --top-module $(top_module) \ 90 | -DSCR1_SIM_ENV \ 91 | -CFLAGS -DVCD_TRACE -CFLAGS -DTRACE_LVLV=20 \ 92 | -CFLAGS -DVCD_FNAME=simx.vcd \ 93 | --clk clk \ 94 | --exe $(scr1_wrapper) \ 95 | --trace \ 96 | --trace-params \ 97 | --trace-structs \ 98 | --trace-underscore \ 99 | --Mdir $(bld_dir)/verilator \ 100 | -I$(rtl_inc_dir) \ 101 | $(sv_list); \ 102 | cd verilator; \ 103 | $(MAKE) -f V$(top_module).mk; 104 | 105 | 106 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/includes/scr1_ipic.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_IPIC_SVH 2 | `define SCR1_IPIC_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief IPIC header file 6 | /// 7 | 8 | `include "scr1_arch_description.svh" 9 | 10 | `ifdef SCR1_IPIC_EN 11 | //------------------------------------------------------------------------------- 12 | // Parameters declaration 13 | //------------------------------------------------------------------------------- 14 | parameter SCR1_IRQ_VECT_NUM = 16; // must be power of 2 in the current implementation 15 | parameter SCR1_IRQ_VECT_WIDTH = $clog2(SCR1_IRQ_VECT_NUM+1); 16 | parameter SCR1_IRQ_LINES_NUM = SCR1_IRQ_VECT_NUM; 17 | parameter SCR1_IRQ_LINES_WIDTH = $clog2(SCR1_IRQ_LINES_NUM); 18 | parameter logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM); 19 | parameter SCR1_IRQ_IDX_WIDTH = $clog2(SCR1_IRQ_VECT_NUM); 20 | 21 | // Address decoding parameters 22 | parameter logic [2:0] SCR1_IPIC_CISV = 3'h0; // RO 23 | parameter logic [2:0] SCR1_IPIC_CICSR = 3'h1; // {IP, IE} 24 | parameter logic [2:0] SCR1_IPIC_IPR = 3'h2; // RW1C 25 | parameter logic [2:0] SCR1_IPIC_ISVR = 3'h3; // RO 26 | parameter logic [2:0] SCR1_IPIC_EOI = 3'h4; // RZW 27 | parameter logic [2:0] SCR1_IPIC_SOI = 3'h5; // RZW 28 | parameter logic [2:0] SCR1_IPIC_IDX = 3'h6; // RW 29 | parameter logic [2:0] SCR1_IPIC_ICSR = 3'h7; // RW 30 | 31 | parameter SCR1_IPIC_ICSR_IP = 0; 32 | parameter SCR1_IPIC_ICSR_IE = 1; 33 | parameter SCR1_IPIC_ICSR_IM = 2; 34 | parameter SCR1_IPIC_ICSR_INV = 3; 35 | parameter SCR1_IPIC_ICSR_IS = 4; 36 | parameter SCR1_IPIC_ICSR_PRV_LSB = 8; 37 | parameter SCR1_IPIC_ICSR_PRV_MSB = 9; 38 | parameter SCR1_IPIC_ICSR_LN_LSB = 12; 39 | 40 | parameter logic [1:0] SCR1_IPIC_PRV_M = 2'b11; 41 | 42 | //------------------------------------------------------------------------------- 43 | // Types declaration 44 | //------------------------------------------------------------------------------- 45 | typedef enum logic { 46 | SCR1_CSR2IPIC_RD, 47 | SCR1_CSR2IPIC_WR, 48 | SCR1_CSR2IPIC_ERROR = 'x 49 | } type_scr1_csr2ipic_wr_e; 50 | 51 | `endif // SCR1_IPIC_EN 52 | `endif // SCR1_IPIC_SVH 53 | -------------------------------------------------------------------------------- /scr1/src/includes/scr1_search_ms1.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_SEARCH_MS1_SVH 2 | `define SCR1_SEARCH_MS1_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Most significant one search function 6 | /// 7 | 8 | //------------------------------------------------------------------------------- 9 | // Local types declaration 10 | //------------------------------------------------------------------------------- 11 | typedef struct { 12 | logic vd; 13 | logic idx; 14 | } type_scr1_search_one_2_s; 15 | 16 | typedef struct { 17 | logic vd; 18 | logic [4:0] idx; 19 | } type_scr1_search_one_32_s; 20 | 21 | //------------------------------------------------------------------------------- 22 | // Leading Zeros Count Function 23 | //------------------------------------------------------------------------------- 24 | function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2( 25 | input logic [1:0] din 26 | ); 27 | type_scr1_search_one_2_s tmp; 28 | begin 29 | tmp.vd = |din; 30 | tmp.idx = ~din[1]; 31 | return tmp; 32 | end 33 | endfunction : scr1_lead_zeros_cnt_2 34 | 35 | function automatic logic [4:0] scr1_lead_zeros_cnt_32( 36 | input logic [31:0] din 37 | ); 38 | begin 39 | logic [15:0] stage1_vd; 40 | logic [7:0] stage2_vd; 41 | logic [3:0] stage3_vd; 42 | logic [1:0] stage4_vd; 43 | 44 | logic stage1_idx [15:0]; 45 | logic [1:0] stage2_idx [7:0]; 46 | logic [2:0] stage3_idx [3:0]; 47 | logic [3:0] stage4_idx [1:0]; 48 | type_scr1_search_one_32_s tmp; 49 | logic [4:0] res; 50 | 51 | // Stage 1 52 | for (int unsigned i=0; i<16; ++i) begin 53 | type_scr1_search_one_2_s tmp; 54 | tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]); 55 | stage1_vd[i] = tmp.vd; 56 | stage1_idx[i] = tmp.idx; 57 | end 58 | 59 | // Stage 2 60 | for (int unsigned i=0; i<8; ++i) begin 61 | type_scr1_search_one_2_s tmp; 62 | tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]); 63 | stage2_vd[i] = tmp.vd; 64 | stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]}; 65 | end 66 | 67 | // Stage 3 68 | for (int unsigned i=0; i<4; ++i) begin 69 | type_scr1_search_one_2_s tmp; 70 | tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]); 71 | stage3_vd[i] = tmp.vd; 72 | stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]}; 73 | end 74 | 75 | // Stage 4 76 | for (int unsigned i=0; i<2; ++i) begin 77 | type_scr1_search_one_2_s tmp; 78 | tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]); 79 | stage4_vd[i] = tmp.vd; 80 | stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]}; 81 | end 82 | 83 | // Stage 5 84 | tmp.vd = |stage4_vd; 85 | tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]}; 86 | 87 | res = tmp.idx; 88 | 89 | return res; 90 | end 91 | endfunction : scr1_lead_zeros_cnt_32 92 | 93 | `endif // SCR1_SEARCH_MS1_SVH 94 | -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_compliance/compliance_io.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance IO Test Header File 2 | 3 | /* 4 | * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 15 | * either express or implied. 16 | * 17 | * See the License for the specific language governing permissions and 18 | * limitations under the License. 19 | * 20 | */ 21 | 22 | #ifndef _COMPLIANCE_IO_H 23 | #define _COMPLIANCE_IO_H 24 | 25 | //----------------------------------------------------------------------- 26 | // RV IO Macros (Non functional) 27 | //----------------------------------------------------------------------- 28 | #ifdef _COMPLIANCE_OUTPUT 29 | 30 | #define RVTEST_IO_PUSH(_SP) \ 31 | la _SP, begin_regstate; \ 32 | sw x3, 0(_SP); \ 33 | sw x4, 4(_SP); \ 34 | sw x5, 8(_SP); 35 | 36 | #define RVTEST_IO_POP(_SP) \ 37 | la _SP, begin_regstate; \ 38 | lw x3, 0(_SP); \ 39 | lw x4, 4(_SP); \ 40 | lw x5, 8(_SP); 41 | 42 | #define RVTEST_IO_WRITE_STR(_SP, _STR) \ 43 | .section .data.string; \ 44 | 20001: \ 45 | .string _STR; \ 46 | .section .text; \ 47 | RVTEST_IO_PUSH(_SP) \ 48 | li x3, 0xF0000000; \ 49 | la x4, 20001b; \ 50 | 2: lb x5, 0(x4); \ 51 | sb x5, 0(x3); \ 52 | beq x5, zero, 1f; \ 53 | add x4, x4, 1; \ 54 | j 2b; \ 55 | 1: RVTEST_IO_POP(_SP) 56 | 57 | #else // #ifdef _COMPLIANCE_OUTPUT 58 | 59 | #define RVTEST_IO_WRITE_STR(_SP, _STR) 60 | 61 | #endif // #end #ifdef _COMPLIANCE_OUTPUT 62 | 63 | #define RVTEST_IO_INIT 64 | #define RVTEST_IO_CHECK() 65 | #define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) 66 | #define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) 67 | #define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) 68 | #define RVTEST_IO_ASSERT_EQ(_R, _I) 69 | 70 | #endif // _COMPLIANCE_IO_H 71 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/includes/scr1_search_ms1.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_SEARCH_MS1_SVH 2 | `define SCR1_SEARCH_MS1_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Most significant one search function 6 | /// 7 | 8 | //------------------------------------------------------------------------------- 9 | // Local types declaration 10 | //------------------------------------------------------------------------------- 11 | typedef struct { 12 | logic vd; 13 | logic idx; 14 | } type_scr1_search_one_2_s; 15 | 16 | typedef struct { 17 | logic vd; 18 | logic [4:0] idx; 19 | } type_scr1_search_one_32_s; 20 | 21 | //------------------------------------------------------------------------------- 22 | // Leading Zeros Count Function 23 | //------------------------------------------------------------------------------- 24 | function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2( 25 | input logic [1:0] din 26 | ); 27 | type_scr1_search_one_2_s tmp; 28 | begin 29 | tmp.vd = |din; 30 | tmp.idx = ~din[1]; 31 | return tmp; 32 | end 33 | endfunction : scr1_lead_zeros_cnt_2 34 | 35 | function automatic logic [4:0] scr1_lead_zeros_cnt_32( 36 | input logic [31:0] din 37 | ); 38 | begin 39 | logic [15:0] stage1_vd; 40 | logic [7:0] stage2_vd; 41 | logic [3:0] stage3_vd; 42 | logic [1:0] stage4_vd; 43 | 44 | logic stage1_idx [15:0]; 45 | logic [1:0] stage2_idx [7:0]; 46 | logic [2:0] stage3_idx [3:0]; 47 | logic [3:0] stage4_idx [1:0]; 48 | type_scr1_search_one_32_s tmp; 49 | logic [4:0] res; 50 | 51 | // Stage 1 52 | for (int unsigned i=0; i<16; ++i) begin 53 | type_scr1_search_one_2_s tmp; 54 | tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]); 55 | stage1_vd[i] = tmp.vd; 56 | stage1_idx[i] = tmp.idx; 57 | end 58 | 59 | // Stage 2 60 | for (int unsigned i=0; i<8; ++i) begin 61 | type_scr1_search_one_2_s tmp; 62 | tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]); 63 | stage2_vd[i] = tmp.vd; 64 | stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]}; 65 | end 66 | 67 | // Stage 3 68 | for (int unsigned i=0; i<4; ++i) begin 69 | type_scr1_search_one_2_s tmp; 70 | tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]); 71 | stage3_vd[i] = tmp.vd; 72 | stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]}; 73 | end 74 | 75 | // Stage 4 76 | for (int unsigned i=0; i<2; ++i) begin 77 | type_scr1_search_one_2_s tmp; 78 | tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]); 79 | stage4_vd[i] = tmp.vd; 80 | stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]}; 81 | end 82 | 83 | // Stage 5 84 | tmp.vd = |stage4_vd; 85 | tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]}; 86 | 87 | res = tmp.idx; 88 | 89 | return res; 90 | end 91 | endfunction : scr1_lead_zeros_cnt_32 92 | 93 | `endif // SCR1_SEARCH_MS1_SVH 94 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/includes/scr1_search_ms1.svh: -------------------------------------------------------------------------------- 1 | `ifndef SCR1_SEARCH_MS1_SVH 2 | `define SCR1_SEARCH_MS1_SVH 3 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 4 | /// @file 5 | /// @brief Most significant one search function 6 | /// 7 | 8 | //------------------------------------------------------------------------------- 9 | // Local types declaration 10 | //------------------------------------------------------------------------------- 11 | typedef struct { 12 | logic vd; 13 | logic idx; 14 | } type_scr1_search_one_2_s; 15 | 16 | typedef struct { 17 | logic vd; 18 | logic [4:0] idx; 19 | } type_scr1_search_one_32_s; 20 | 21 | //------------------------------------------------------------------------------- 22 | // Leading Zeros Count Function 23 | //------------------------------------------------------------------------------- 24 | function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2( 25 | input logic [1:0] din 26 | ); 27 | type_scr1_search_one_2_s tmp; 28 | begin 29 | tmp.vd = |din; 30 | tmp.idx = ~din[1]; 31 | return tmp; 32 | end 33 | endfunction : scr1_lead_zeros_cnt_2 34 | 35 | function automatic logic [4:0] scr1_lead_zeros_cnt_32( 36 | input logic [31:0] din 37 | ); 38 | begin 39 | logic [15:0] stage1_vd; 40 | logic [7:0] stage2_vd; 41 | logic [3:0] stage3_vd; 42 | logic [1:0] stage4_vd; 43 | 44 | logic stage1_idx [15:0]; 45 | logic [1:0] stage2_idx [7:0]; 46 | logic [2:0] stage3_idx [3:0]; 47 | logic [3:0] stage4_idx [1:0]; 48 | type_scr1_search_one_32_s tmp; 49 | logic [4:0] res; 50 | 51 | // Stage 1 52 | for (int unsigned i=0; i<16; ++i) begin 53 | type_scr1_search_one_2_s tmp; 54 | tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]); 55 | stage1_vd[i] = tmp.vd; 56 | stage1_idx[i] = tmp.idx; 57 | end 58 | 59 | // Stage 2 60 | for (int unsigned i=0; i<8; ++i) begin 61 | type_scr1_search_one_2_s tmp; 62 | tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]); 63 | stage2_vd[i] = tmp.vd; 64 | stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]}; 65 | end 66 | 67 | // Stage 3 68 | for (int unsigned i=0; i<4; ++i) begin 69 | type_scr1_search_one_2_s tmp; 70 | tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]); 71 | stage3_vd[i] = tmp.vd; 72 | stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]}; 73 | end 74 | 75 | // Stage 4 76 | for (int unsigned i=0; i<2; ++i) begin 77 | type_scr1_search_one_2_s tmp; 78 | tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]); 79 | stage4_vd[i] = tmp.vd; 80 | stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]}; 81 | end 82 | 83 | // Stage 5 84 | tmp.vd = |stage4_vd; 85 | tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]}; 86 | 87 | res = tmp.idx; 88 | 89 | return res; 90 | end 91 | endfunction : scr1_lead_zeros_cnt_32 92 | 93 | `endif // SCR1_SEARCH_MS1_SVH 94 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_compliance/compliance_io.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance IO Test Header File 2 | 3 | /* 4 | * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the "License"); 7 | * you may not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * http://www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an "AS IS" BASIS, 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 15 | * either express or implied. 16 | * 17 | * See the License for the specific language governing permissions and 18 | * limitations under the License. 19 | * 20 | */ 21 | 22 | #ifndef _COMPLIANCE_IO_H 23 | #define _COMPLIANCE_IO_H 24 | 25 | //----------------------------------------------------------------------- 26 | // RV IO Macros (Non functional) 27 | //----------------------------------------------------------------------- 28 | #ifdef _COMPLIANCE_OUTPUT 29 | 30 | #define RVTEST_IO_PUSH(_SP) \ 31 | la _SP, begin_regstate; \ 32 | sw x3, 0(_SP); \ 33 | sw x4, 4(_SP); \ 34 | sw x5, 8(_SP); 35 | 36 | #define RVTEST_IO_POP(_SP) \ 37 | la _SP, begin_regstate; \ 38 | lw x3, 0(_SP); \ 39 | lw x4, 4(_SP); \ 40 | lw x5, 8(_SP); 41 | 42 | #define RVTEST_IO_WRITE_STR(_SP, _STR) \ 43 | .section .data.string; \ 44 | 20001: \ 45 | .string _STR; \ 46 | .section .text; \ 47 | RVTEST_IO_PUSH(_SP) \ 48 | li x3, 0xF0000000; \ 49 | la x4, 20001b; \ 50 | 2: lb x5, 0(x4); \ 51 | sb x5, 0(x3); \ 52 | beq x5, zero, 1f; \ 53 | add x4, x4, 1; \ 54 | j 2b; \ 55 | 1: RVTEST_IO_POP(_SP) 56 | 57 | #else // #ifdef _COMPLIANCE_OUTPUT 58 | 59 | #define RVTEST_IO_WRITE_STR(_SP, _STR) 60 | 61 | #endif // #end #ifdef _COMPLIANCE_OUTPUT 62 | 63 | #define RVTEST_IO_INIT 64 | #define RVTEST_IO_CHECK() 65 | #define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) 66 | #define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) 67 | #define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) 68 | #define RVTEST_IO_ASSERT_EQ(_R, _I) 69 | 70 | #endif // _COMPLIANCE_IO_H 71 | -------------------------------------------------------------------------------- /scr1/src/pipeline/scr1_pipe_mprf.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief Multi Port Register File (MPRF) 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | `include "scr1_arch_types.svh" 8 | 9 | module scr1_pipe_mprf ( 10 | // Common 11 | `ifdef SCR1_MPRF_RST_EN 12 | input logic rst_n, 13 | `endif // SCR1_MPRF_RST_EN 14 | input logic clk, 15 | 16 | // EXU <-> MPRF interface 17 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rs1_addr, // MPRF rs1 read address 18 | output logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data, // MPRF rs1 read data 19 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rs2_addr, // MPRF rs2 read address 20 | output logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data, // MPRF rs2 read data 21 | input logic exu2mprf_w_req, // MPRF write request 22 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rd_addr, // MPRF rd write address 23 | input logic [`SCR1_XLEN-1:0] exu2mprf_rd_data // MPRF rd write data 24 | ); 25 | 26 | 27 | //------------------------------------------------------------------------------- 28 | // Local types declaration 29 | //------------------------------------------------------------------------------- 30 | `ifdef SCR1_RVE_EXT 31 | type_scr1_mprf_v [1:15] mprf_int; 32 | `else // ~SCR1_RVE_EXT 33 | type_scr1_mprf_v [1:31] mprf_int; 34 | `endif // ~SCR1_RVE_EXT 35 | 36 | //------------------------------------------------------------------------------- 37 | // Read MPRF 38 | //------------------------------------------------------------------------------- 39 | assign mprf2exu_rs1_data = (|exu2mprf_rs1_addr) ? mprf_int[exu2mprf_rs1_addr] : '0; 40 | assign mprf2exu_rs2_data = (|exu2mprf_rs2_addr) ? mprf_int[exu2mprf_rs2_addr] : '0; 41 | 42 | //------------------------------------------------------------------------------- 43 | // Write MPRF 44 | //------------------------------------------------------------------------------- 45 | `ifdef SCR1_MPRF_RST_EN 46 | 47 | always_ff @(negedge rst_n, posedge clk) begin 48 | if (~rst_n) begin 49 | mprf_int <= '0; 50 | end else begin 51 | if (exu2mprf_w_req & |exu2mprf_rd_addr) begin 52 | mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data; 53 | end 54 | end 55 | end 56 | 57 | `else // SCR1_MPRF_RST_EN 58 | 59 | always_ff @(posedge clk) begin 60 | if (exu2mprf_w_req & |exu2mprf_rd_addr) begin 61 | mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data; 62 | end 63 | end 64 | 65 | `endif // SCR1_MPRF_RST_EN 66 | 67 | 68 | `ifdef SCR1_SIM_ENV 69 | `ifndef VERILATOR 70 | //------------------------------------------------------------------------------- 71 | // Assertion 72 | //------------------------------------------------------------------------------- 73 | `ifdef SCR1_MPRF_RST_EN 74 | SCR1_SVA_MPRF_WRITEX : assert property ( 75 | @(negedge clk) disable iff (~rst_n) 76 | exu2mprf_w_req |-> !$isunknown({exu2mprf_rd_addr, (|exu2mprf_rd_addr ? exu2mprf_rd_data : `SCR1_XLEN'd0)}) 77 | ) else $error("MPRF error: unknown values"); 78 | `endif // SCR1_MPRF_RST_EN 79 | 80 | `endif // VERILATOR 81 | `endif // SCR1_SIM_ENV 82 | 83 | endmodule : scr1_pipe_mprf 84 | -------------------------------------------------------------------------------- /scr1/build/rem.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 15 | 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00 34 | 73 25 40 F1 01 E1 01 4E 97 02 00 00 93 82 82 FB 35 | 73 90 52 30 05 45 7E 05 63 48 05 00 0F 00 F0 0F 36 | F2 85 01 45 73 00 00 00 97 02 00 00 93 82 82 DD 37 | 63 8E 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 38 | 73 90 22 30 73 23 20 30 E3 93 62 FA 73 50 00 30 39 | 97 02 00 00 93 82 02 05 73 90 12 34 73 25 40 F1 40 | 73 00 20 30 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 E1 20 02 89 4E 09 4E 63 9B D1 09 45 | 93 00 C0 FE 19 41 B3 E1 20 02 93 0E E0 FF 0D 4E 46 | 63 91 D1 09 D1 40 13 01 A0 FF B3 E1 20 02 89 4E 47 | 11 4E 63 98 D1 07 93 00 C0 FE 13 01 A0 FF B3 E1 48 | 20 02 93 0E E0 FF 15 4E 63 9D D1 05 81 40 05 41 49 | B3 E1 20 02 81 4E 19 4E 63 95 D1 05 81 40 13 01 50 | F0 FF B3 E1 20 02 81 4E 1D 4E 63 9C D1 03 81 40 51 | 01 41 B3 E1 20 02 81 4E 21 4E 63 94 D1 03 85 40 52 | 01 41 B3 E1 20 02 85 4E 25 4E 63 9C D1 01 81 40 53 | 01 41 B3 E1 20 02 81 4E 29 4E 63 94 D1 01 63 18 54 | C0 01 0F 00 F0 0F F2 85 05 45 73 00 00 00 0F 00 55 | F0 0F F2 85 01 45 73 00 00 00 73 00 00 00 00 00 56 | 6F F0 5F D9 13 00 00 00 13 00 00 00 13 00 00 00 57 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 58 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | @000003A0 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | @000003C0 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 69 | -------------------------------------------------------------------------------- /scr1/build/remu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 F1 20 02 89 4E 09 4E 63 9A D1 09 45 | 93 00 C0 FE 19 41 B3 F1 20 02 89 4E 0D 4E 63 91 46 | D1 09 D1 40 13 01 A0 FF B3 F1 20 02 D1 4E 11 4E 47 | 63 98 D1 07 93 00 C0 FE 13 01 A0 FF B3 F1 20 02 48 | 93 0E C0 FE 15 4E 63 9D D1 05 81 40 05 41 B3 F1 49 | 20 02 81 4E 19 4E 63 95 D1 05 81 40 13 01 F0 FF 50 | B3 F1 20 02 81 4E 1D 4E 63 9C D1 03 81 40 01 41 51 | B3 F1 20 02 81 4E 21 4E 63 94 D1 03 85 40 01 41 52 | B3 F1 20 02 85 4E 25 4E 63 9C D1 01 81 40 01 41 53 | B3 F1 20 02 81 4E 29 4E 63 94 D1 01 63 18 C0 01 54 | 0F 00 F0 0F F2 85 05 45 73 00 00 00 0F 00 F0 0F 55 | F2 85 01 45 73 00 00 00 73 00 00 00 00 00 00 00 56 | 6F F0 5F D9 13 00 00 00 13 00 00 00 13 00 00 00 57 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 58 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | @000003A0 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | @000003C0 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 69 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/scr1/pipeline/scr1_pipe_mprf.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief Multi Port Register File (MPRF) 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | `include "scr1_arch_types.svh" 8 | 9 | module scr1_pipe_mprf ( 10 | // Common 11 | `ifdef SCR1_MPRF_RST_EN 12 | input logic rst_n, 13 | `endif // SCR1_MPRF_RST_EN 14 | input logic clk, 15 | 16 | // EXU <-> MPRF interface 17 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rs1_addr, // MPRF rs1 read address 18 | output logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data, // MPRF rs1 read data 19 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rs2_addr, // MPRF rs2 read address 20 | output logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data, // MPRF rs2 read data 21 | input logic exu2mprf_w_req, // MPRF write request 22 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rd_addr, // MPRF rd write address 23 | input logic [`SCR1_XLEN-1:0] exu2mprf_rd_data // MPRF rd write data 24 | ); 25 | 26 | 27 | //------------------------------------------------------------------------------- 28 | // Local types declaration 29 | //------------------------------------------------------------------------------- 30 | `ifdef SCR1_RVE_EXT 31 | type_scr1_mprf_v [1:15] mprf_int; 32 | `else // ~SCR1_RVE_EXT 33 | type_scr1_mprf_v [1:31] mprf_int; 34 | `endif // ~SCR1_RVE_EXT 35 | 36 | //------------------------------------------------------------------------------- 37 | // Read MPRF 38 | //------------------------------------------------------------------------------- 39 | assign mprf2exu_rs1_data = (|exu2mprf_rs1_addr) ? mprf_int[exu2mprf_rs1_addr] : '0; 40 | assign mprf2exu_rs2_data = (|exu2mprf_rs2_addr) ? mprf_int[exu2mprf_rs2_addr] : '0; 41 | 42 | //------------------------------------------------------------------------------- 43 | // Write MPRF 44 | //------------------------------------------------------------------------------- 45 | `ifdef SCR1_MPRF_RST_EN 46 | 47 | always_ff @(negedge rst_n, posedge clk) begin 48 | if (~rst_n) begin 49 | mprf_int <= '0; 50 | end else begin 51 | if (exu2mprf_w_req & |exu2mprf_rd_addr) begin 52 | mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data; 53 | end 54 | end 55 | end 56 | 57 | `else // SCR1_MPRF_RST_EN 58 | 59 | always_ff @(posedge clk) begin 60 | if (exu2mprf_w_req & |exu2mprf_rd_addr) begin 61 | mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data; 62 | end 63 | end 64 | 65 | `endif // SCR1_MPRF_RST_EN 66 | 67 | 68 | `ifdef SCR1_SIM_ENV 69 | `ifndef VERILATOR 70 | //------------------------------------------------------------------------------- 71 | // Assertion 72 | //------------------------------------------------------------------------------- 73 | `ifdef SCR1_MPRF_RST_EN 74 | SCR1_SVA_MPRF_WRITEX : assert property ( 75 | @(negedge clk) disable iff (~rst_n) 76 | exu2mprf_w_req |-> !$isunknown({exu2mprf_rd_addr, (|exu2mprf_rd_addr ? exu2mprf_rd_data : `SCR1_XLEN'd0)}) 77 | ) else $error("MPRF error: unknown values"); 78 | `endif // SCR1_MPRF_RST_EN 79 | 80 | `endif // VERILATOR 81 | `endif // SCR1_SIM_ENV 82 | 83 | endmodule : scr1_pipe_mprf 84 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/src/pipeline/scr1_pipe_mprf.sv: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016-2018. See LICENSE for details 2 | /// @file 3 | /// @brief Multi Port Register File (MPRF) 4 | /// 5 | 6 | `include "scr1_arch_description.svh" 7 | `include "scr1_arch_types.svh" 8 | 9 | module scr1_pipe_mprf ( 10 | // Common 11 | `ifdef SCR1_MPRF_RST_EN 12 | input logic rst_n, 13 | `endif // SCR1_MPRF_RST_EN 14 | input logic clk, 15 | 16 | // EXU <-> MPRF interface 17 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rs1_addr, // MPRF rs1 read address 18 | output logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data, // MPRF rs1 read data 19 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rs2_addr, // MPRF rs2 read address 20 | output logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data, // MPRF rs2 read data 21 | input logic exu2mprf_w_req, // MPRF write request 22 | input logic [`SCR1_MPRF_ADDR_WIDTH-1:0] exu2mprf_rd_addr, // MPRF rd write address 23 | input logic [`SCR1_XLEN-1:0] exu2mprf_rd_data // MPRF rd write data 24 | ); 25 | 26 | 27 | //------------------------------------------------------------------------------- 28 | // Local types declaration 29 | //------------------------------------------------------------------------------- 30 | `ifdef SCR1_RVE_EXT 31 | type_scr1_mprf_v [1:15] mprf_int; 32 | `else // ~SCR1_RVE_EXT 33 | type_scr1_mprf_v [1:31] mprf_int; 34 | `endif // ~SCR1_RVE_EXT 35 | 36 | //------------------------------------------------------------------------------- 37 | // Read MPRF 38 | //------------------------------------------------------------------------------- 39 | assign mprf2exu_rs1_data = (|exu2mprf_rs1_addr) ? mprf_int[exu2mprf_rs1_addr] : '0; 40 | assign mprf2exu_rs2_data = (|exu2mprf_rs2_addr) ? mprf_int[exu2mprf_rs2_addr] : '0; 41 | 42 | //------------------------------------------------------------------------------- 43 | // Write MPRF 44 | //------------------------------------------------------------------------------- 45 | `ifdef SCR1_MPRF_RST_EN 46 | 47 | always_ff @(negedge rst_n, posedge clk) begin 48 | if (~rst_n) begin 49 | mprf_int <= '0; 50 | end else begin 51 | if (exu2mprf_w_req & |exu2mprf_rd_addr) begin 52 | mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data; 53 | end 54 | end 55 | end 56 | 57 | `else // SCR1_MPRF_RST_EN 58 | 59 | always_ff @(posedge clk) begin 60 | if (exu2mprf_w_req & |exu2mprf_rd_addr) begin 61 | mprf_int[exu2mprf_rd_addr] <= exu2mprf_rd_data; 62 | end 63 | end 64 | 65 | `endif // SCR1_MPRF_RST_EN 66 | 67 | 68 | `ifdef SCR1_SIM_ENV 69 | `ifndef VERILATOR 70 | //------------------------------------------------------------------------------- 71 | // Assertion 72 | //------------------------------------------------------------------------------- 73 | `ifdef SCR1_MPRF_RST_EN 74 | SCR1_SVA_MPRF_WRITEX : assert property ( 75 | @(negedge clk) disable iff (~rst_n) 76 | exu2mprf_w_req |-> !$isunknown({exu2mprf_rd_addr, (|exu2mprf_rd_addr ? exu2mprf_rd_data : `SCR1_XLEN'd0)}) 77 | ) else $error("MPRF error: unknown values"); 78 | `endif // SCR1_MPRF_RST_EN 79 | 80 | `endif // VERILATOR 81 | `endif // SCR1_SIM_ENV 82 | 83 | endmodule : scr1_pipe_mprf 84 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/rem.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14 | 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 13 00 00 00 34 | 73 25 40 F1 01 E1 01 4E 97 02 00 00 93 82 82 FB 35 | 73 90 52 30 05 45 7E 05 63 48 05 00 0F 00 F0 0F 36 | F2 85 01 45 73 00 00 00 97 02 00 00 93 82 82 DD 37 | 63 8E 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 38 | 73 90 22 30 73 23 20 30 E3 93 62 FA 73 50 00 30 39 | 97 02 00 00 93 82 02 05 73 90 12 34 73 25 40 F1 40 | 73 00 20 30 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 E1 20 02 89 4E 09 4E 63 9B D1 09 45 | 93 00 C0 FE 19 41 B3 E1 20 02 93 0E E0 FF 0D 4E 46 | 63 91 D1 09 D1 40 13 01 A0 FF B3 E1 20 02 89 4E 47 | 11 4E 63 98 D1 07 93 00 C0 FE 13 01 A0 FF B3 E1 48 | 20 02 93 0E E0 FF 15 4E 63 9D D1 05 81 40 05 41 49 | B3 E1 20 02 81 4E 19 4E 63 95 D1 05 81 40 13 01 50 | F0 FF B3 E1 20 02 81 4E 1D 4E 63 9C D1 03 81 40 51 | 01 41 B3 E1 20 02 81 4E 21 4E 63 94 D1 03 85 40 52 | 01 41 B3 E1 20 02 85 4E 25 4E 63 9C D1 01 81 40 53 | 01 41 B3 E1 20 02 81 4E 29 4E 63 94 D1 01 63 18 54 | C0 01 0F 00 F0 0F F2 85 05 45 73 00 00 00 0F 00 55 | F0 0F F2 85 01 45 73 00 00 00 73 00 00 00 00 00 56 | 6F F0 5F D9 13 00 00 00 13 00 00 00 13 00 00 00 57 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 58 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | @000003A0 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | @000003C0 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 69 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/remu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 F1 20 02 89 4E 09 4E 63 9A D1 09 45 | 93 00 C0 FE 19 41 B3 F1 20 02 89 4E 0D 4E 63 91 46 | D1 09 D1 40 13 01 A0 FF B3 F1 20 02 D1 4E 11 4E 47 | 63 98 D1 07 93 00 C0 FE 13 01 A0 FF B3 F1 20 02 48 | 93 0E C0 FE 15 4E 63 9D D1 05 81 40 05 41 B3 F1 49 | 20 02 81 4E 19 4E 63 95 D1 05 81 40 13 01 F0 FF 50 | B3 F1 20 02 81 4E 1D 4E 63 9C D1 03 81 40 01 41 51 | B3 F1 20 02 81 4E 21 4E 63 94 D1 03 85 40 01 41 52 | B3 F1 20 02 85 4E 25 4E 63 9C D1 01 81 40 01 41 53 | B3 F1 20 02 81 4E 29 4E 63 94 D1 01 63 18 C0 01 54 | 0F 00 F0 0F F2 85 05 45 73 00 00 00 0F 00 F0 0F 55 | F2 85 01 45 73 00 00 00 73 00 00 00 00 00 00 00 56 | 6F F0 5F D9 13 00 00 00 13 00 00 00 13 00 00 00 57 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 58 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | @000003A0 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | @000003C0 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 69 | -------------------------------------------------------------------------------- /scr1/build/div.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 71 | -------------------------------------------------------------------------------- /scr1/build/divu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 15 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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93 82 82 FB 35 | 73 90 52 30 05 45 7E 05 63 48 05 00 0F 00 F0 0F 36 | F2 85 01 45 73 00 00 00 97 02 00 00 93 82 82 DD 37 | 63 8E 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 38 | 73 90 22 30 73 23 20 30 E3 93 62 FA 73 50 00 30 39 | 97 02 00 00 93 82 02 05 73 90 12 34 73 25 40 F1 40 | 73 00 20 30 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 D1 20 02 8D 4E 09 4E 63 93 D1 0B 45 | 93 00 C0 FE 19 41 B3 D1 20 02 B7 BE AA 2A 93 8E 46 | 7E AA 0D 4E 63 97 D1 09 D1 40 13 01 A0 FF B3 D1 47 | 20 02 81 4E 11 4E 63 9E D1 07 93 00 C0 FE 13 01 48 | A0 FF B3 D1 20 02 81 4E 15 4E 63 94 D1 07 B7 00 49 | 00 80 05 41 B3 D1 20 02 B7 0E 00 80 19 4E 63 9A 50 | D1 05 B7 00 00 80 13 01 F0 FF B3 D1 20 02 81 4E 51 | 1D 4E 63 90 D1 05 B7 00 00 80 01 41 B3 D1 20 02 52 | 93 0E F0 FF 21 4E 63 96 D1 03 85 40 01 41 B3 D1 53 | 20 02 93 0E F0 FF 25 4E 63 9D D1 01 81 40 01 41 54 | B3 D1 20 02 93 0E F0 FF 29 4E 63 94 D1 01 63 18 55 | C0 01 0F 00 F0 0F F2 85 05 45 73 00 00 00 0F 00 56 | F0 0F F2 85 01 45 73 00 00 00 73 00 00 00 00 00 57 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 | 6F F0 5F D7 13 00 00 00 13 00 00 00 13 00 00 00 59 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | @000003C0 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | @00000400 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 71 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/div.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 15 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17 | 00 00 00 00 13 00 00 00 6F 00 00 00 FF FF FF FF 18 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 19 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 22 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 23 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 24 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 25 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 27 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | 73 2F 20 34 A1 4F 63 05 FF 03 A5 4F 63 02 FF 03 31 | AD 4F 63 0F FF 01 17 0F 00 00 13 0F AF E2 63 03 32 | 0F 00 02 8F 73 2F 20 34 63 53 0F 00 09 A0 05 45 33 | 6F 00 00 19 13 00 00 00 13 00 00 00 13 00 00 00 34 | 73 25 40 F1 01 E1 01 4E 97 02 00 00 93 82 82 FB 35 | 73 90 52 30 05 45 7E 05 63 48 05 00 0F 00 F0 0F 36 | F2 85 01 45 73 00 00 00 97 02 00 00 93 82 82 DD 37 | 63 8E 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 38 | 73 90 22 30 73 23 20 30 E3 93 62 FA 73 50 00 30 39 | 97 02 00 00 93 82 02 05 73 90 12 34 73 25 40 F1 40 | 73 00 20 30 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 C1 20 02 8D 4E 09 4E 63 9E D1 09 45 | 93 00 C0 FE 19 41 B3 C1 20 02 93 0E D0 FF 0D 4E 46 | 63 94 D1 09 D1 40 13 01 A0 FF B3 C1 20 02 93 0E 47 | D0 FF 11 4E 63 9A D1 07 93 00 C0 FE 13 01 A0 FF 48 | B3 C1 20 02 8D 4E 15 4E 63 90 D1 07 81 40 05 41 49 | B3 C1 20 02 81 4E 19 4E 63 98 D1 05 81 40 13 01 50 | F0 FF B3 C1 20 02 81 4E 1D 4E 63 9F D1 03 81 40 51 | 01 41 B3 C1 20 02 93 0E F0 FF 21 4E 63 96 D1 03 52 | 85 40 01 41 B3 C1 20 02 93 0E F0 FF 25 4E 63 9D 53 | D1 01 81 40 01 41 B3 C1 20 02 93 0E F0 FF 29 4E 54 | 63 94 D1 01 63 18 C0 01 0F 00 F0 0F F2 85 05 45 55 | 73 00 00 00 0F 00 F0 0F F2 85 01 45 73 00 00 00 56 | 73 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 57 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 | 6F F0 5F D7 13 00 00 00 13 00 00 00 13 00 00 00 59 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | @000003C0 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | @00000400 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 71 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/build/divu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 15 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17 | 00 00 00 00 13 00 00 00 6F 00 00 00 FF FF FF FF 18 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 19 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 22 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 23 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 24 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 25 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 27 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | 73 2F 20 34 A1 4F 63 05 FF 03 A5 4F 63 02 FF 03 31 | AD 4F 63 0F FF 01 17 0F 00 00 13 0F AF E2 63 03 32 | 0F 00 02 8F 73 2F 20 34 63 53 0F 00 09 A0 05 45 33 | 6F 00 00 19 13 00 00 00 13 00 00 00 13 00 00 00 34 | 73 25 40 F1 01 E1 01 4E 97 02 00 00 93 82 82 FB 35 | 73 90 52 30 05 45 7E 05 63 48 05 00 0F 00 F0 0F 36 | F2 85 01 45 73 00 00 00 97 02 00 00 93 82 82 DD 37 | 63 8E 02 00 73 90 52 10 B7 B2 00 00 93 82 92 10 38 | 73 90 22 30 73 23 20 30 E3 93 62 FA 73 50 00 30 39 | 97 02 00 00 93 82 02 05 73 90 12 34 73 25 40 F1 40 | 73 00 20 30 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | @000002A0 44 | D1 40 19 41 B3 D1 20 02 8D 4E 09 4E 63 93 D1 0B 45 | 93 00 C0 FE 19 41 B3 D1 20 02 B7 BE AA 2A 93 8E 46 | 7E AA 0D 4E 63 97 D1 09 D1 40 13 01 A0 FF B3 D1 47 | 20 02 81 4E 11 4E 63 9E D1 07 93 00 C0 FE 13 01 48 | A0 FF B3 D1 20 02 81 4E 15 4E 63 94 D1 07 B7 00 49 | 00 80 05 41 B3 D1 20 02 B7 0E 00 80 19 4E 63 9A 50 | D1 05 B7 00 00 80 13 01 F0 FF B3 D1 20 02 81 4E 51 | 1D 4E 63 90 D1 05 B7 00 00 80 01 41 B3 D1 20 02 52 | 93 0E F0 FF 21 4E 63 96 D1 03 85 40 01 41 B3 D1 53 | 20 02 93 0E F0 FF 25 4E 63 9D D1 01 81 40 01 41 54 | B3 D1 20 02 93 0E F0 FF 29 4E 63 94 D1 01 63 18 55 | C0 01 0F 00 F0 0F F2 85 05 45 73 00 00 00 0F 00 56 | F0 0F F2 85 01 45 73 00 00 00 73 00 00 00 00 00 57 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 | 6F F0 5F D7 13 00 00 00 13 00 00 00 13 00 00 00 59 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | @000003C0 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | @00000400 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 71 | -------------------------------------------------------------------------------- /ssrv-on-scr1/readme.md: -------------------------------------------------------------------------------- 1 | SSRV is a main framework to build a high performance CPU core. If it is connected with system control units as the same as peripherals, it will provide the high-performance attribute for different CPU cores. 2 | 3 | Since the simulation environment is inherited from SCR1, it is very convenient to instantiate SSRV into SCR1 to improve instruction throughput ability. SSRV will replace the basic instruction processing modules. All instructions will be dealt with except system and CSR instructions, which will be forwarded to SCR1’s system and CSR module: scr1_pipe_csr.sv. 4 | 5 | ![ssrv-on-scr1](https://github.com/risclite/SuperScalar-RISCV-CPU/blob/master/wiki/png/ssrv-on-scr1.png) 6 | 7 | SSRV and "scr1_pipe_csr" constitute a new basic hierarchy level: "pipeline". The "pipeline" level could be instantiated by the upper level: "core", which has an accessorial module: "scr1_reset_cells". The top hierarchy level adds more functions: 64KB TCM, a 64-bit timer and AXI4/AHB-lite bus interfaces. 8 | 9 | Compared with the original SCR1 core, the DHRY score will be improved from 1.14 DMIPS/MHz to 1.87 DMIPS/MHz. Unfortunately, the instruction bus width is fixed to 32 bits by SCR1, which is a limitation of performance. It is obvious that SSRV could not issue 2 or 3 instructions simultaneously when only 1 instruction is fetched from the source memory. 10 | 11 | The directory "ssrv-on-scr1" is on the subject of this SSRV CPU core based on SCR1. It has two sub-directories: 12 | 13 | * sim/ 14 | 15 | It likes the simulation environment of SSRV, but the difference is that the instruction bus bit width is fixed to 32 bit and could not be adjusted to other values. 16 | 17 | The simulation could be switched from SSRV to SCR1 by commenting the verilog defination "USE_SSRV" of "rtl/define_para.v". 18 | 19 | * rtl/ 20 | 21 | "ssrv_pipe_top.sv" instantiates "ssrv_top" and " scr1_pipe_csr". It is the top module of SSRV CPU core. You can treat "rtl/" as a whole set of SSRV CPU core. 22 | 23 | * scr1/ 24 | 25 | This directory is inherited from SCR1, which provides a whole simulation package. 26 | 27 | build/ --- compiled hex/elf/dump files 28 | 29 | src/ --- source files of SCR1, which includes RTL and testbench files. 30 | 31 | sim/ --- where to start simulation and compile work library. 32 | 33 | Just enter sim/scr1/sim/ and run "compile.do" and "sim.do". 34 | 35 | 36 | * fpga/ 37 | 38 | The FPGA demonstration project is based on Altera DE2-115 development board. 39 | 40 | * DE2-115/ 41 | 42 | The main directory of this FPGA project. Open " DE2_115.qsf" file to find more details. DE2-115.v is the top module. 43 | 44 | * pll/ 45 | 46 | A PLL ip generated by "MegaWizard Plug-In Manager", which will turn a 50 MHz clock to a 30 MHz clock. 47 | 48 | * ram/ 49 | 50 | A 64KB dual-port ram generated by "MegaWizard Plug-In Manager", which contains a mif file: code.mif. This mif file is converted from build/ dhrystone21_imc_noinline.hex. 51 | 52 | * rtl/ --- The SSRV CPU core. 53 | 54 | * scr1/ --- SCR1 source files. 55 | 56 | * test/ 57 | 58 | Two synthesizable files: rxtx.v, which is a simple UART verilog file; and "ssrv_memory.v, which instantiates the 64KB dualport ram. 59 | 60 | The FPGA board should be connected with a UART terminal, which has a configuration of 9600, even, 1 stop bit. You can change the baud rate through the parameters of rxtx.v. Please open DE2-115.v, find the instantiation of rxtx and give your "mhz" and "baud". 61 | 62 | 63 | -------------------------------------------------------------------------------- /rtl/instrman.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | //Copyright 2020 Li Xinbing 4 | // 5 | //Licensed under the Apache License, Version 2.0 (the "License"); 6 | //you may not use this file except in compliance with the License. 7 | //You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | //Unless required by applicable law or agreed to in writing, software 12 | //distributed under the License is distributed on an "AS IS" BASIS, 13 | //WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | //See the License for the specific language governing permissions and 15 | //limitations under the License. 16 | // 17 | ///////////////////////////////////////////////////////////////////////////////////// 18 | 19 | //THis module manages instruction memory request. There are 3 methods to change PC. 20 | //1--- jump_vld/jump_pc: System jump to PC 21 | //2--- branch_vld/branch_pc: branch to PC 22 | //3--- buffer_free: Keep fetching instructions 23 | 24 | `include "define.v" 25 | module instrman 26 | ( 27 | input clk, 28 | input rst, 29 | 30 | output imem_req, 31 | output `N(`XLEN) imem_addr, 32 | input imem_resp, 33 | input `N(`BUS_WID) imem_rdata, 34 | input imem_err, 35 | 36 | input jump_vld, 37 | input `N(`XLEN) jump_pc, 38 | input branch_vld, 39 | input `N(`XLEN) branch_pc, 40 | input buffer_free, 41 | 42 | output imem_vld, 43 | output `N(`BUS_WID) imem_instr, 44 | output imem_status 45 | 46 | ); 47 | 48 | //--------------------------------------------------------------------------- 49 | //signal defination 50 | //--------------------------------------------------------------------------- 51 | reg `N(`XLEN) pc; 52 | reg req_sent; 53 | reg instr_verified; 54 | 55 | //--------------------------------------------------------------------------- 56 | //statements description 57 | //--------------------------------------------------------------------------- 58 | 59 | wire reload_vld = jump_vld|branch_vld; 60 | wire `N(`XLEN) reload_pc = ( jump_vld ? jump_pc : branch_pc ) & ( {`XLEN{1'b1}}<<1 ); 61 | wire `N(`XLEN) fetch_addr = reload_vld ? reload_pc : pc; 62 | assign imem_addr = fetch_addr & `PC_ALIGN; 63 | 64 | //imem_addr 65 | `FFx(pc,0) 66 | if ( imem_req ) 67 | pc <= fetch_addr + 4*`BUS_LEN; 68 | else if ( reload_vld ) 69 | pc <= reload_pc; 70 | else; 71 | 72 | //imem_req 73 | wire request_go = buffer_free|reload_vld; 74 | 75 | //if req_sent is 0, request_go can be asserted any time, if it is 1, only when imem_resp is OK. 76 | `FFx(req_sent,1'b0) 77 | if ( ~req_sent|imem_resp ) 78 | req_sent <= request_go; 79 | else; 80 | 81 | assign imem_req = request_go & ( ~req_sent|imem_resp ); 82 | 83 | //rdata could be cancelled by "reload_vld" 84 | `FFx(instr_verified,1'b0) 85 | if ( imem_req ) 86 | instr_verified <= 1'b1; 87 | else if ( reload_vld|imem_resp ) 88 | instr_verified <= 1'b0; 89 | else; 90 | 91 | assign imem_vld = instr_verified & imem_resp; 92 | assign imem_instr = imem_rdata; 93 | assign imem_status = imem_err; 94 | 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /ssrv-on-scr1/fpga/rtl/instrman.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | //Copyright 2020 Li Xinbing 4 | // 5 | //Licensed under the Apache License, Version 2.0 (the "License"); 6 | //you may not use this file except in compliance with the License. 7 | //You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | //Unless required by applicable law or agreed to in writing, software 12 | //distributed under the License is distributed on an "AS IS" BASIS, 13 | //WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | //See the License for the specific language governing permissions and 15 | //limitations under the License. 16 | // 17 | ///////////////////////////////////////////////////////////////////////////////////// 18 | 19 | //THis module manages instruction memory request. There are 3 methods to change PC. 20 | //1--- jump_vld/jump_pc: System jump to PC 21 | //2--- branch_vld/branch_pc: branch to PC 22 | //3--- buffer_free: Keep fetching instructions 23 | 24 | `include "define.v" 25 | module instrman 26 | ( 27 | input clk, 28 | input rst, 29 | 30 | output imem_req, 31 | output `N(`XLEN) imem_addr, 32 | input imem_resp, 33 | input `N(`BUS_WID) imem_rdata, 34 | input imem_err, 35 | 36 | input jump_vld, 37 | input `N(`XLEN) jump_pc, 38 | input branch_vld, 39 | input `N(`XLEN) branch_pc, 40 | input buffer_free, 41 | 42 | output imem_vld, 43 | output `N(`BUS_WID) imem_instr, 44 | output imem_status 45 | 46 | ); 47 | 48 | //--------------------------------------------------------------------------- 49 | //signal defination 50 | //--------------------------------------------------------------------------- 51 | reg `N(`XLEN) pc; 52 | reg req_sent; 53 | reg instr_verified; 54 | 55 | //--------------------------------------------------------------------------- 56 | //statements description 57 | //--------------------------------------------------------------------------- 58 | 59 | wire reload_vld = jump_vld|branch_vld; 60 | wire `N(`XLEN) reload_pc = ( jump_vld ? jump_pc : branch_pc ) & ( {`XLEN{1'b1}}<<1 ); 61 | wire `N(`XLEN) fetch_addr = reload_vld ? reload_pc : pc; 62 | assign imem_addr = fetch_addr & `PC_ALIGN; 63 | 64 | //imem_addr 65 | `FFx(pc,0) 66 | if ( imem_req ) 67 | pc <= fetch_addr + 4*`BUS_LEN; 68 | else if ( reload_vld ) 69 | pc <= reload_pc; 70 | else; 71 | 72 | //imem_req 73 | wire request_go = buffer_free|reload_vld; 74 | 75 | //if req_sent is 0, request_go can be asserted any time, if it is 1, only when imem_resp is OK. 76 | `FFx(req_sent,1'b0) 77 | if ( ~req_sent|imem_resp ) 78 | req_sent <= request_go; 79 | else; 80 | 81 | assign imem_req = request_go & ( ~req_sent|imem_resp ); 82 | 83 | //rdata could be cancelled by "reload_vld" 84 | `FFx(instr_verified,1'b0) 85 | if ( imem_req ) 86 | instr_verified <= 1'b1; 87 | else if ( reload_vld|imem_resp ) 88 | instr_verified <= 1'b0; 89 | else; 90 | 91 | assign imem_vld = instr_verified & imem_resp; 92 | assign imem_instr = imem_rdata; 93 | assign imem_status = imem_err; 94 | 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/rtl/instrman.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////////////////// 2 | // 3 | //Copyright 2020 Li Xinbing 4 | // 5 | //Licensed under the Apache License, Version 2.0 (the "License"); 6 | //you may not use this file except in compliance with the License. 7 | //You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | //Unless required by applicable law or agreed to in writing, software 12 | //distributed under the License is distributed on an "AS IS" BASIS, 13 | //WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | //See the License for the specific language governing permissions and 15 | //limitations under the License. 16 | // 17 | ///////////////////////////////////////////////////////////////////////////////////// 18 | 19 | //THis module manages instruction memory request. There are 3 methods to change PC. 20 | //1--- jump_vld/jump_pc: System jump to PC 21 | //2--- branch_vld/branch_pc: branch to PC 22 | //3--- buffer_free: Keep fetching instructions 23 | 24 | `include "define.v" 25 | module instrman 26 | ( 27 | input clk, 28 | input rst, 29 | 30 | output imem_req, 31 | output `N(`XLEN) imem_addr, 32 | input imem_resp, 33 | input `N(`BUS_WID) imem_rdata, 34 | input imem_err, 35 | 36 | input jump_vld, 37 | input `N(`XLEN) jump_pc, 38 | input branch_vld, 39 | input `N(`XLEN) branch_pc, 40 | input buffer_free, 41 | 42 | output imem_vld, 43 | output `N(`BUS_WID) imem_instr, 44 | output imem_status 45 | 46 | ); 47 | 48 | //--------------------------------------------------------------------------- 49 | //signal defination 50 | //--------------------------------------------------------------------------- 51 | reg `N(`XLEN) pc; 52 | reg req_sent; 53 | reg instr_verified; 54 | 55 | //--------------------------------------------------------------------------- 56 | //statements description 57 | //--------------------------------------------------------------------------- 58 | 59 | wire reload_vld = jump_vld|branch_vld; 60 | wire `N(`XLEN) reload_pc = ( jump_vld ? jump_pc : branch_pc ) & ( {`XLEN{1'b1}}<<1 ); 61 | wire `N(`XLEN) fetch_addr = reload_vld ? reload_pc : pc; 62 | assign imem_addr = fetch_addr & `PC_ALIGN; 63 | 64 | //imem_addr 65 | `FFx(pc,0) 66 | if ( imem_req ) 67 | pc <= fetch_addr + 4*`BUS_LEN; 68 | else if ( reload_vld ) 69 | pc <= reload_pc; 70 | else; 71 | 72 | //imem_req 73 | wire request_go = buffer_free|reload_vld; 74 | 75 | //if req_sent is 0, request_go can be asserted any time, if it is 1, only when imem_resp is OK. 76 | `FFx(req_sent,1'b0) 77 | if ( ~req_sent|imem_resp ) 78 | req_sent <= request_go; 79 | else; 80 | 81 | assign imem_req = request_go & ( ~req_sent|imem_resp ); 82 | 83 | //rdata could be cancelled by "reload_vld" 84 | `FFx(instr_verified,1'b0) 85 | if ( imem_req ) 86 | instr_verified <= 1'b1; 87 | else if ( reload_vld|imem_resp ) 88 | instr_verified <= 1'b0; 89 | else; 90 | 91 | assign imem_vld = instr_verified & imem_resp; 92 | assign imem_instr = imem_rdata; 93 | assign imem_status = imem_err; 94 | 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /scr1/sim/tests/riscv_isa/Makefile: -------------------------------------------------------------------------------- 1 | 2 | include rv32_tests.inc 3 | 4 | override ARCH := imfc 5 | 6 | src_dir := $(CURDIR) 7 | obj_dir := $(bld_dir)/riscv_objs 8 | test_list := $(patsubst %.S, %, $(notdir $(rv32_isa_tests))) 9 | objs := $(addprefix $(obj_dir)/,$(test_list:%=%.o)) 10 | test_elf := $(addprefix $(bld_dir)/,$(test_list:%=%.elf)) 11 | test_hex := $(addprefix $(bld_dir)/,$(test_list:%=%.hex)) 12 | test_dump := $(addprefix $(bld_dir)/,$(test_list:%=%.dump)) 13 | 14 | CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=ilp32f -D__riscv_xlen=32 15 | LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=rv32$(ARCH) -mabi=ilp32f 16 | 17 | VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(RISCV_TESTS) 18 | 19 | default: check_riscv_tests $(test_elf) $(test_hex) $(test_dump) 20 | 21 | define compile_template 22 | $(obj_dir)/$$(basename $(notdir $(SRC))).o: $$(SRC) | $(obj_dir) 23 | $(RISCV_GCC) -c $$< $(CFLAGS) -o $$@ 24 | endef 25 | 26 | $(foreach SRC,$(rv32_isa_tests), $(eval $(compile_template))) 27 | 28 | $(obj_dir) : 29 | mkdir -p $(obj_dir) 30 | 31 | $(bld_dir)/%.elf: $(obj_dir)/%.o | $(obj_dir) 32 | $(RISCV_GCC) $^ $(LDFLAGS) -o $@ 33 | 34 | $(bld_dir)/%.hex: $(bld_dir)/%.elf 35 | $(RISCV_OBJCOPY) $^ $@ 36 | 37 | $(bld_dir)/%.dump: $(bld_dir)/%.elf 38 | $(RISCV_OBJDUMP) $^ > $@ 39 | 40 | clean: 41 | $(RM) $(test_elf) $(test_hex) $(test_dump) $(objs) 42 | $(RM) -R $(obj_dir) 43 | 44 | 45 | .PHONY: check_riscv_tests 46 | 47 | riscv_tests_dir := $(if $(RISCV_TESTS), $(RISCV_TESTS), ./undefined) 48 | riscv_tests_commit := a9433c4daa287fbe101025f2a079261a10149225 49 | ## commit hash readed from local copy of https://github.com/riscv/riscv-tests 50 | tmp_commit = $(shell cd $(riscv_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ') 51 | is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true) 52 | 53 | # Color 54 | RED=\033[0;31m 55 | NC=\033[0m 56 | 57 | check_riscv_tests : $(riscv_tests_dir) 58 | @if [ ! -d $(riscv_tests_dir) ]; then \ 59 | echo -e "$(RED)==========================================================================" &&\ 60 | echo " Error! Environment variable RISCV_TESTS='$(riscv_tests_dir)' " &&\ 61 | echo " directory not exist!" && \ 62 | echo "==========================================================================$(NC)" ; \ 63 | fi 64 | ifneq (,$(is_repo_changed)) 65 | @echo -e "$(RED)==========================================================================" 66 | @echo " Error! Repo '$(riscv_tests_dir)' " 67 | @echo " must be unchanged!" 68 | @echo -e "==========================================================================$(NC)" 69 | exit 1 70 | endif 71 | ifneq ($(is_commit_good),true) 72 | @echo -e "$(RED)==========================================================================" 73 | @echo " Error! riscv-tests must point to commit $(riscv_tests_commit)" 74 | @echo -e "==========================================================================$(NC)" 75 | exit 1 76 | endif 77 | 78 | $(riscv_tests_dir) :. 79 | ifndef RISCV_TESTS 80 | @echo -e "$(RED)==========================================================================" 81 | @echo " Error! Environment variable RISCV_TESTS not set!" 82 | @echo " You must set the environment variable RISCV_TESTS" 83 | @echo " The variable should point to the local copy of the" 84 | @echo " repository https://github.com/riscv/riscv-tests" 85 | @echo " with the commit $(riscv_tests_commit)" 86 | @echo -e "==========================================================================$(NC)" 87 | exit 1 88 | endif -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/riscv_isa/Makefile: -------------------------------------------------------------------------------- 1 | 2 | include rv32_tests.inc 3 | 4 | override ARCH := imfc 5 | 6 | src_dir := $(CURDIR) 7 | obj_dir := $(bld_dir)/riscv_objs 8 | test_list := $(patsubst %.S, %, $(notdir $(rv32_isa_tests))) 9 | objs := $(addprefix $(obj_dir)/,$(test_list:%=%.o)) 10 | test_elf := $(addprefix $(bld_dir)/,$(test_list:%=%.elf)) 11 | test_hex := $(addprefix $(bld_dir)/,$(test_list:%=%.hex)) 12 | test_dump := $(addprefix $(bld_dir)/,$(test_list:%=%.dump)) 13 | 14 | CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=ilp32f -D__riscv_xlen=32 15 | LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=rv32$(ARCH) -mabi=ilp32f 16 | 17 | VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(RISCV_TESTS) 18 | 19 | default: check_riscv_tests $(test_elf) $(test_hex) $(test_dump) 20 | 21 | define compile_template 22 | $(obj_dir)/$$(basename $(notdir $(SRC))).o: $$(SRC) | $(obj_dir) 23 | $(RISCV_GCC) -c $$< $(CFLAGS) -o $$@ 24 | endef 25 | 26 | $(foreach SRC,$(rv32_isa_tests), $(eval $(compile_template))) 27 | 28 | $(obj_dir) : 29 | mkdir -p $(obj_dir) 30 | 31 | $(bld_dir)/%.elf: $(obj_dir)/%.o | $(obj_dir) 32 | $(RISCV_GCC) $^ $(LDFLAGS) -o $@ 33 | 34 | $(bld_dir)/%.hex: $(bld_dir)/%.elf 35 | $(RISCV_OBJCOPY) $^ $@ 36 | 37 | $(bld_dir)/%.dump: $(bld_dir)/%.elf 38 | $(RISCV_OBJDUMP) $^ > $@ 39 | 40 | clean: 41 | $(RM) $(test_elf) $(test_hex) $(test_dump) $(objs) 42 | $(RM) -R $(obj_dir) 43 | 44 | 45 | .PHONY: check_riscv_tests 46 | 47 | riscv_tests_dir := $(if $(RISCV_TESTS), $(RISCV_TESTS), ./undefined) 48 | riscv_tests_commit := a9433c4daa287fbe101025f2a079261a10149225 49 | ## commit hash readed from local copy of https://github.com/riscv/riscv-tests 50 | tmp_commit = $(shell cd $(riscv_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ') 51 | is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true) 52 | 53 | # Color 54 | RED=\033[0;31m 55 | NC=\033[0m 56 | 57 | check_riscv_tests : $(riscv_tests_dir) 58 | @if [ ! -d $(riscv_tests_dir) ]; then \ 59 | echo -e "$(RED)==========================================================================" &&\ 60 | echo " Error! Environment variable RISCV_TESTS='$(riscv_tests_dir)' " &&\ 61 | echo " directory not exist!" && \ 62 | echo "==========================================================================$(NC)" ; \ 63 | fi 64 | ifneq (,$(is_repo_changed)) 65 | @echo -e "$(RED)==========================================================================" 66 | @echo " Error! Repo '$(riscv_tests_dir)' " 67 | @echo " must be unchanged!" 68 | @echo -e "==========================================================================$(NC)" 69 | exit 1 70 | endif 71 | ifneq ($(is_commit_good),true) 72 | @echo -e "$(RED)==========================================================================" 73 | @echo " Error! riscv-tests must point to commit $(riscv_tests_commit)" 74 | @echo -e "==========================================================================$(NC)" 75 | exit 1 76 | endif 77 | 78 | $(riscv_tests_dir) :. 79 | ifndef RISCV_TESTS 80 | @echo -e "$(RED)==========================================================================" 81 | @echo " Error! Environment variable RISCV_TESTS not set!" 82 | @echo " You must set the environment variable RISCV_TESTS" 83 | @echo " The variable should point to the local copy of the" 84 | @echo " repository https://github.com/riscv/riscv-tests" 85 | @echo " with the commit $(riscv_tests_commit)" 86 | @echo -e "==========================================================================$(NC)" 87 | exit 1 88 | endif -------------------------------------------------------------------------------- /scr1/sim/tests/common/crt.S: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// 4 | 5 | #include "riscv_csr_encoding.h" 6 | 7 | # define LREG lw 8 | # define SREG sw 9 | # define REGBYTES 4 10 | 11 | .globl _start 12 | .globl main 13 | .globl trap_entry 14 | .globl handle_trap 15 | .globl sc_exit 16 | .weak trap_entry, handle_trap, sc_exit 17 | 18 | .text 19 | .org (64*3) 20 | .align 6 21 | machine_trap_entry: 22 | j trap_entry 23 | 24 | .align 6 25 | 26 | _start: 27 | # clear bss 28 | la a1, __BSS_START__ 29 | la a2, __BSS_END__ 30 | j 4f 31 | 3: sw zero, 0(a1) 32 | add a1, a1, 4 33 | 4: bne a1, a2, 3b 34 | auipc gp, %hi(_gp) 35 | addi gp, gp, %lo(_gp) 36 | la sp, __C_STACK_TOP__ 37 | 38 | // Timer init 39 | li t0, mtime_ctrl 40 | li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock 41 | sw t1, (t0) 42 | li t0, mtime_div 43 | li t1, (100-1) // divide by 100 44 | sw t1, (t0) 45 | li t0, mtimecmp 46 | li t1, -1 47 | sw t1, (t0) // max value for mtimecmp 48 | sw t1, 4(t0) 49 | 50 | li a0, 0 51 | li a1, 0 52 | jal main 53 | j sc_exit 54 | 55 | trap_entry: 56 | addi sp, sp, -272 57 | 58 | SREG x1, 1*REGBYTES(sp) 59 | SREG x2, 2*REGBYTES(sp) 60 | SREG x3, 3*REGBYTES(sp) 61 | SREG x4, 4*REGBYTES(sp) 62 | SREG x5, 5*REGBYTES(sp) 63 | SREG x6, 6*REGBYTES(sp) 64 | SREG x7, 7*REGBYTES(sp) 65 | SREG x8, 8*REGBYTES(sp) 66 | SREG x9, 9*REGBYTES(sp) 67 | SREG x10, 10*REGBYTES(sp) 68 | SREG x11, 11*REGBYTES(sp) 69 | SREG x12, 12*REGBYTES(sp) 70 | SREG x13, 13*REGBYTES(sp) 71 | SREG x14, 14*REGBYTES(sp) 72 | SREG x15, 15*REGBYTES(sp) 73 | #ifndef __RVE_EXT 74 | SREG x16, 16*REGBYTES(sp) 75 | SREG x17, 17*REGBYTES(sp) 76 | SREG x18, 18*REGBYTES(sp) 77 | SREG x19, 19*REGBYTES(sp) 78 | SREG x20, 20*REGBYTES(sp) 79 | SREG x21, 21*REGBYTES(sp) 80 | SREG x22, 22*REGBYTES(sp) 81 | SREG x23, 23*REGBYTES(sp) 82 | SREG x24, 24*REGBYTES(sp) 83 | SREG x25, 25*REGBYTES(sp) 84 | SREG x26, 26*REGBYTES(sp) 85 | SREG x27, 27*REGBYTES(sp) 86 | SREG x28, 28*REGBYTES(sp) 87 | SREG x29, 29*REGBYTES(sp) 88 | SREG x30, 30*REGBYTES(sp) 89 | SREG x31, 31*REGBYTES(sp) 90 | #endif // __RVE_EXT 91 | 92 | csrr a0, mcause 93 | csrr a1, mepc 94 | mv a2, sp 95 | jal handle_trap 96 | 97 | LREG x1, 1*REGBYTES(sp) 98 | LREG x2, 2*REGBYTES(sp) 99 | LREG x3, 3*REGBYTES(sp) 100 | LREG x4, 4*REGBYTES(sp) 101 | LREG x5, 5*REGBYTES(sp) 102 | LREG x6, 6*REGBYTES(sp) 103 | LREG x7, 7*REGBYTES(sp) 104 | LREG x8, 8*REGBYTES(sp) 105 | LREG x9, 9*REGBYTES(sp) 106 | LREG x10, 10*REGBYTES(sp) 107 | LREG x11, 11*REGBYTES(sp) 108 | LREG x12, 12*REGBYTES(sp) 109 | LREG x13, 13*REGBYTES(sp) 110 | LREG x14, 14*REGBYTES(sp) 111 | LREG x15, 15*REGBYTES(sp) 112 | #ifndef __RVE_EXT 113 | LREG x16, 16*REGBYTES(sp) 114 | LREG x17, 17*REGBYTES(sp) 115 | LREG x18, 18*REGBYTES(sp) 116 | LREG x19, 19*REGBYTES(sp) 117 | LREG x20, 20*REGBYTES(sp) 118 | LREG x21, 21*REGBYTES(sp) 119 | LREG x22, 22*REGBYTES(sp) 120 | LREG x23, 23*REGBYTES(sp) 121 | LREG x24, 24*REGBYTES(sp) 122 | LREG x25, 25*REGBYTES(sp) 123 | LREG x26, 26*REGBYTES(sp) 124 | LREG x27, 27*REGBYTES(sp) 125 | LREG x28, 28*REGBYTES(sp) 126 | LREG x29, 29*REGBYTES(sp) 127 | LREG x30, 30*REGBYTES(sp) 128 | LREG x31, 31*REGBYTES(sp) 129 | #endif // __RVE_EXT 130 | 131 | addi sp, sp, 272 132 | mret 133 | 134 | handle_trap: 135 | sc_exit: 136 | j SIM_EXIT 137 | 138 | // end of crt.S -------------------------------------------------------------------------------- /ssrv-on-scr1/sim/scr1/sim/tests/common/crt.S: -------------------------------------------------------------------------------- 1 | /// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details 2 | /// @file 3 | /// 4 | 5 | #include "riscv_csr_encoding.h" 6 | 7 | # define LREG lw 8 | # define SREG sw 9 | # define REGBYTES 4 10 | 11 | .globl _start 12 | .globl main 13 | .globl trap_entry 14 | .globl handle_trap 15 | .globl sc_exit 16 | .weak trap_entry, handle_trap, sc_exit 17 | 18 | .text 19 | .org (64*3) 20 | .align 6 21 | machine_trap_entry: 22 | j trap_entry 23 | 24 | .align 6 25 | 26 | _start: 27 | # clear bss 28 | la a1, __BSS_START__ 29 | la a2, __BSS_END__ 30 | j 4f 31 | 3: sw zero, 0(a1) 32 | add a1, a1, 4 33 | 4: bne a1, a2, 3b 34 | auipc gp, %hi(_gp) 35 | addi gp, gp, %lo(_gp) 36 | la sp, __C_STACK_TOP__ 37 | 38 | // Timer init 39 | li t0, mtime_ctrl 40 | li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock 41 | sw t1, (t0) 42 | li t0, mtime_div 43 | li t1, (100-1) // divide by 100 44 | sw t1, (t0) 45 | li t0, mtimecmp 46 | li t1, -1 47 | sw t1, (t0) // max value for mtimecmp 48 | sw t1, 4(t0) 49 | 50 | li a0, 0 51 | li a1, 0 52 | jal main 53 | j sc_exit 54 | 55 | trap_entry: 56 | addi sp, sp, -272 57 | 58 | SREG x1, 1*REGBYTES(sp) 59 | SREG x2, 2*REGBYTES(sp) 60 | SREG x3, 3*REGBYTES(sp) 61 | SREG x4, 4*REGBYTES(sp) 62 | SREG x5, 5*REGBYTES(sp) 63 | SREG x6, 6*REGBYTES(sp) 64 | SREG x7, 7*REGBYTES(sp) 65 | SREG x8, 8*REGBYTES(sp) 66 | SREG x9, 9*REGBYTES(sp) 67 | SREG x10, 10*REGBYTES(sp) 68 | SREG x11, 11*REGBYTES(sp) 69 | SREG x12, 12*REGBYTES(sp) 70 | SREG x13, 13*REGBYTES(sp) 71 | SREG x14, 14*REGBYTES(sp) 72 | SREG x15, 15*REGBYTES(sp) 73 | #ifndef __RVE_EXT 74 | SREG x16, 16*REGBYTES(sp) 75 | SREG x17, 17*REGBYTES(sp) 76 | SREG x18, 18*REGBYTES(sp) 77 | SREG x19, 19*REGBYTES(sp) 78 | SREG x20, 20*REGBYTES(sp) 79 | SREG x21, 21*REGBYTES(sp) 80 | SREG x22, 22*REGBYTES(sp) 81 | SREG x23, 23*REGBYTES(sp) 82 | SREG x24, 24*REGBYTES(sp) 83 | SREG x25, 25*REGBYTES(sp) 84 | SREG x26, 26*REGBYTES(sp) 85 | SREG x27, 27*REGBYTES(sp) 86 | SREG x28, 28*REGBYTES(sp) 87 | SREG x29, 29*REGBYTES(sp) 88 | SREG x30, 30*REGBYTES(sp) 89 | SREG x31, 31*REGBYTES(sp) 90 | #endif // __RVE_EXT 91 | 92 | csrr a0, mcause 93 | csrr a1, mepc 94 | mv a2, sp 95 | jal handle_trap 96 | 97 | LREG x1, 1*REGBYTES(sp) 98 | LREG x2, 2*REGBYTES(sp) 99 | LREG x3, 3*REGBYTES(sp) 100 | LREG x4, 4*REGBYTES(sp) 101 | LREG x5, 5*REGBYTES(sp) 102 | LREG x6, 6*REGBYTES(sp) 103 | LREG x7, 7*REGBYTES(sp) 104 | LREG x8, 8*REGBYTES(sp) 105 | LREG x9, 9*REGBYTES(sp) 106 | LREG x10, 10*REGBYTES(sp) 107 | LREG x11, 11*REGBYTES(sp) 108 | LREG x12, 12*REGBYTES(sp) 109 | LREG x13, 13*REGBYTES(sp) 110 | LREG x14, 14*REGBYTES(sp) 111 | LREG x15, 15*REGBYTES(sp) 112 | #ifndef __RVE_EXT 113 | LREG x16, 16*REGBYTES(sp) 114 | LREG x17, 17*REGBYTES(sp) 115 | LREG x18, 18*REGBYTES(sp) 116 | LREG x19, 19*REGBYTES(sp) 117 | LREG x20, 20*REGBYTES(sp) 118 | LREG x21, 21*REGBYTES(sp) 119 | LREG x22, 22*REGBYTES(sp) 120 | LREG x23, 23*REGBYTES(sp) 121 | LREG x24, 24*REGBYTES(sp) 122 | LREG x25, 25*REGBYTES(sp) 123 | LREG x26, 26*REGBYTES(sp) 124 | LREG x27, 27*REGBYTES(sp) 125 | LREG x28, 28*REGBYTES(sp) 126 | LREG x29, 29*REGBYTES(sp) 127 | LREG x30, 30*REGBYTES(sp) 128 | LREG x31, 31*REGBYTES(sp) 129 | #endif // __RVE_EXT 130 | 131 | addi sp, sp, 272 132 | mret 133 | 134 | handle_trap: 135 | sc_exit: 136 | j SIM_EXIT 137 | 138 | // end of crt.S --------------------------------------------------------------------------------