├── .gitattributes ├── .gitignore ├── README.md ├── rtl ├── alu.v ├── define.v ├── define_para.v ├── include_func.v ├── instrbits.v ├── instrman.v ├── lsu.v ├── membuf.v ├── mprf.v ├── mul.v ├── predictor.v ├── schedule.v ├── ssrv_top.v └── sys_csr.v ├── scr1 ├── build │ ├── coremark_i.dump │ ├── coremark_i.elf │ ├── coremark_i.hex │ ├── coremark_ic.dump │ ├── coremark_ic.elf │ ├── coremark_ic.hex │ ├── coremark_imc.dump │ ├── coremark_imc.elf │ ├── coremark_imc.hex │ ├── dhrystone21_i_max.dump │ ├── dhrystone21_i_max.elf │ ├── dhrystone21_i_max.hex │ ├── dhrystone21_i_noinline.dump │ ├── dhrystone21_i_noinline.elf │ ├── dhrystone21_i_noinline.hex │ ├── dhrystone21_ic_max.dump │ ├── dhrystone21_ic_max.elf │ ├── dhrystone21_ic_max.hex │ ├── dhrystone21_ic_noinline.dump │ ├── dhrystone21_ic_noinline.elf │ ├── dhrystone21_ic_noinline.hex │ ├── dhrystone21_imc_max.dump │ ├── dhrystone21_imc_max.elf │ ├── dhrystone21_imc_max.hex │ ├── dhrystone21_imc_noinline.dump │ ├── dhrystone21_imc_noinline.elf │ ├── dhrystone21_imc_noinline.hex │ ├── div.dump │ ├── div.elf │ ├── div.hex │ ├── divu.dump │ ├── divu.elf │ ├── divu.hex │ ├── mul.dump │ ├── mul.elf │ ├── mul.hex │ ├── mulh.dump │ ├── mulh.elf │ ├── mulh.hex │ ├── mulhsu.dump │ ├── mulhsu.elf │ ├── mulhsu.hex │ ├── mulhu.dump │ ├── mulhu.elf │ ├── mulhu.hex │ ├── rem.dump │ ├── rem.elf │ ├── rem.hex │ ├── remu.dump │ ├── remu.elf │ ├── remu.hex │ └── test_info ├── sim │ ├── Makefile │ ├── compile.do │ ├── readme.txt │ ├── sim.do │ ├── tests │ │ ├── benchmarks │ │ │ ├── coremark │ │ │ │ ├── Makefile │ │ │ │ ├── core_portme.c │ │ │ │ └── core_portme.h │ │ │ └── dhrystone21 │ │ │ │ ├── Makefile │ │ │ │ ├── dhry.h │ │ │ │ ├── dhry_1.c │ │ │ │ └── dhry_2.c │ │ ├── common │ │ │ ├── LICENSE │ │ │ ├── crt.S │ │ │ ├── crt_tcm.S │ │ │ ├── csr.h │ │ │ ├── link.ld │ │ │ ├── link_tcm.ld │ │ │ ├── riscv_csr_encoding.h │ │ │ ├── riscv_macros.h │ │ │ ├── sc_print.c │ │ │ ├── sc_print.h │ │ │ ├── sc_test.h │ │ │ └── scr1_specific.h │ │ ├── riscv_compliance │ │ │ ├── Makefile │ │ │ ├── aw_test_macros.h │ │ │ ├── check.c │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ ├── riscv_test.h │ │ │ └── test_macros.h │ │ ├── riscv_isa │ │ │ ├── Makefile │ │ │ ├── riscv_test.h │ │ │ ├── rv32_tests.inc │ │ │ └── test_macros.h │ │ └── vectored_isr_sample │ │ │ ├── Makefile │ │ │ ├── timer.h │ │ │ └── v_isr_sample.S │ └── verilator_wrap │ │ ├── scr1_ahb_wrapper.c │ │ └── scr1_axi_wrapper.c └── src │ ├── ahb_tb.files │ ├── ahb_top.files │ ├── axi_tb.files │ ├── axi_top.files │ ├── core.files │ ├── core │ ├── primitives │ │ ├── scr1_cg.sv │ │ └── scr1_reset_cells.sv │ ├── scr1_clk_ctrl.sv │ ├── scr1_core_top.sv │ ├── scr1_dm.sv │ ├── scr1_dmi.sv │ ├── scr1_scu.sv │ ├── scr1_tapc.sv │ ├── scr1_tapc_shift_reg.sv │ └── scr1_tapc_synchronizer.sv │ ├── includes │ ├── scr1_ahb.svh │ ├── scr1_arch_description.svh │ ├── scr1_arch_types.svh │ ├── scr1_csr.svh │ ├── scr1_dm.svh │ ├── scr1_hdu.svh │ ├── scr1_ipic.svh │ ├── scr1_memif.svh │ ├── scr1_riscv_isa_decoding.svh │ ├── scr1_search_ms1.svh │ ├── scr1_tapc.svh │ └── scr1_tdu.svh │ ├── pipeline │ ├── scr1_ipic.sv │ ├── scr1_pipe_csr.sv │ ├── scr1_pipe_exu.sv │ ├── scr1_pipe_hdu.sv │ ├── scr1_pipe_ialu.sv │ ├── scr1_pipe_idu.sv │ ├── scr1_pipe_ifu.sv │ ├── scr1_pipe_lsu.sv │ ├── scr1_pipe_mprf.sv │ ├── scr1_pipe_tdu.sv │ ├── scr1_pipe_top.sv │ └── scr1_tracelog.sv │ ├── tb │ ├── scr1_memory_tb_ahb.sv │ ├── scr1_memory_tb_axi.sv │ ├── scr1_top_tb_ahb.sv │ └── scr1_top_tb_axi.sv │ └── top │ ├── scr1_dmem_ahb.sv │ ├── scr1_dmem_router.sv │ ├── scr1_dp_memory.sv │ ├── scr1_imem_ahb.sv │ ├── scr1_imem_router.sv │ ├── scr1_mem_axi.sv │ ├── scr1_tcm.sv │ ├── scr1_timer.sv │ ├── scr1_top_ahb.sv │ └── scr1_top_axi.sv ├── ssrv-on-scr1 ├── fpga │ ├── DE2_115 │ │ ├── DE2_115.asm.rpt │ │ ├── DE2_115.done │ │ ├── DE2_115.fit.rpt │ │ ├── DE2_115.fit.smsg │ │ ├── DE2_115.fit.summary │ │ ├── DE2_115.flow.rpt │ │ ├── DE2_115.htm │ │ ├── DE2_115.jdi │ │ ├── DE2_115.map.rpt │ │ ├── DE2_115.map.summary │ │ ├── DE2_115.pin │ │ ├── DE2_115.qpf │ │ ├── DE2_115.qsf │ │ ├── DE2_115.qws │ │ ├── DE2_115.sdc │ │ ├── DE2_115.sld │ │ ├── DE2_115.sof │ │ ├── DE2_115.sta.rpt │ │ ├── DE2_115.sta.summary │ │ ├── DE2_115.v │ │ ├── DE2_115_assignment_defaults.qdf │ │ ├── PLLJ_PLLSPE_INFO.txt │ │ ├── dualram.qip │ │ └── plll.qip │ ├── pll │ │ ├── plll.ppf │ │ ├── plll.qip │ │ ├── plll.v │ │ ├── plll_bb.v │ │ └── plll_inst.v │ ├── ram │ │ ├── code.mif │ │ ├── code_dhry.mif │ │ ├── dualram.qip │ │ ├── dualram.v │ │ ├── dualram_bb.v │ │ └── dualram_inst.v │ ├── readme.md │ ├── rtl │ │ ├── alu.v │ │ ├── define.v │ │ ├── define_para.v │ │ ├── include_func.v │ │ ├── instrbits.v │ │ ├── instrman.v │ │ ├── lsu.v │ │ ├── membuf.v │ │ ├── mprf.v │ │ ├── mul.v │ │ ├── predictor.v │ │ ├── schedule.v │ │ ├── ssrv_pipe_top.sv │ │ ├── ssrv_top.v │ │ └── sys_csr.v │ ├── scr1 │ │ ├── ahb_tb.files │ │ ├── ahb_top.files │ │ ├── axi_tb.files │ │ ├── axi_top.files │ │ ├── core.files │ │ ├── core │ │ │ ├── primitives │ │ │ │ ├── scr1_cg.sv │ │ │ │ └── scr1_reset_cells.sv │ │ │ ├── scr1_clk_ctrl.sv │ │ │ ├── scr1_core_top.sv │ │ │ ├── scr1_dm.sv │ │ │ ├── scr1_dmi.sv │ │ │ ├── scr1_scu.sv │ │ │ ├── scr1_tapc.sv │ │ │ ├── scr1_tapc_shift_reg.sv │ │ │ └── scr1_tapc_synchronizer.sv │ │ ├── includes │ │ │ ├── scr1_ahb.svh │ │ │ ├── scr1_arch_description.svh │ │ │ ├── scr1_arch_types.svh │ │ │ ├── scr1_csr.svh │ │ │ ├── scr1_dm.svh │ │ │ ├── scr1_hdu.svh │ │ │ ├── scr1_ipic.svh │ │ │ ├── scr1_memif.svh │ │ │ ├── scr1_riscv_isa_decoding.svh │ │ │ ├── scr1_search_ms1.svh │ │ │ ├── scr1_tapc.svh │ │ │ └── scr1_tdu.svh │ │ ├── pipeline │ │ │ ├── scr1_ipic.sv │ │ │ ├── scr1_pipe_csr.sv │ │ │ ├── scr1_pipe_exu.sv │ │ │ ├── scr1_pipe_hdu.sv │ │ │ ├── scr1_pipe_ialu.sv │ │ │ ├── scr1_pipe_idu.sv │ │ │ ├── scr1_pipe_ifu.sv │ │ │ ├── scr1_pipe_lsu.sv │ │ │ ├── scr1_pipe_mprf.sv │ │ │ ├── scr1_pipe_tdu.sv │ │ │ ├── scr1_pipe_top.sv │ │ │ └── scr1_tracelog.sv │ │ ├── tb │ │ │ ├── scr1_memory_tb_ahb.sv │ │ │ ├── scr1_memory_tb_axi.sv │ │ │ ├── scr1_top_tb_ahb.sv │ │ │ └── scr1_top_tb_axi.sv │ │ └── top │ │ │ ├── scr1_dmem_ahb.sv │ │ │ ├── scr1_dmem_router.sv │ │ │ ├── scr1_dp_memory.sv │ │ │ ├── scr1_imem_ahb.sv │ │ │ ├── scr1_imem_router.sv │ │ │ ├── scr1_mem_axi.sv │ │ │ ├── scr1_tcm.sv │ │ │ ├── scr1_timer.sv │ │ │ ├── scr1_top_ahb.sv │ │ │ └── scr1_top_axi.sv │ └── test │ │ ├── rxtx.v │ │ └── ssrv_memory.v ├── readme.md └── sim │ ├── readme.md │ ├── rtl │ ├── alu.v │ ├── define.v │ ├── define_para.v │ ├── include_func.v │ ├── instrbits.v │ ├── instrman.v │ ├── lsu.v │ ├── membuf.v │ ├── mprf.v │ ├── mul.v │ ├── predictor.v │ ├── schedule.v │ ├── ssrv_pipe_top.sv │ ├── ssrv_top.v │ └── sys_csr.v │ └── scr1 │ ├── build │ ├── coremark_i.dump │ ├── coremark_i.elf │ ├── coremark_i.hex │ ├── coremark_ic.dump │ ├── coremark_ic.elf │ ├── coremark_ic.hex │ ├── coremark_imc.dump │ ├── coremark_imc.elf │ ├── coremark_imc.hex │ ├── dhrystone21_i_max.dump │ ├── dhrystone21_i_max.elf │ ├── dhrystone21_i_max.hex │ ├── dhrystone21_i_noinline.dump │ ├── dhrystone21_i_noinline.elf │ ├── dhrystone21_i_noinline.hex │ ├── dhrystone21_ic_max.dump │ ├── dhrystone21_ic_max.elf │ ├── dhrystone21_ic_max.hex │ ├── dhrystone21_ic_noinline.dump │ ├── dhrystone21_ic_noinline.elf │ ├── dhrystone21_ic_noinline.hex │ ├── dhrystone21_imc_max.dump │ ├── dhrystone21_imc_max.elf │ ├── dhrystone21_imc_max.hex │ ├── dhrystone21_imc_noinline.dump │ ├── dhrystone21_imc_noinline.elf │ ├── dhrystone21_imc_noinline.hex │ ├── div.dump │ ├── div.elf │ ├── div.hex │ ├── divu.dump │ ├── divu.elf │ ├── divu.hex │ ├── mul.dump │ ├── mul.elf │ ├── mul.hex │ ├── mulh.dump │ ├── mulh.elf │ ├── mulh.hex │ ├── mulhsu.dump │ ├── mulhsu.elf │ ├── mulhsu.hex │ ├── mulhu.dump │ ├── mulhu.elf │ ├── mulhu.hex │ ├── rem.dump │ ├── rem.elf │ ├── rem.hex │ ├── remu.dump │ ├── remu.elf │ ├── remu.hex │ └── test_info │ ├── sim │ ├── Makefile │ ├── compile.do │ ├── readme.txt │ ├── sim.do │ ├── tests │ │ ├── benchmarks │ │ │ ├── coremark │ │ │ │ ├── Makefile │ │ │ │ ├── core_portme.c │ │ │ │ └── core_portme.h │ │ │ └── dhrystone21 │ │ │ │ ├── Makefile │ │ │ │ ├── dhry.h │ │ │ │ ├── dhry_1.c │ │ │ │ └── dhry_2.c │ │ ├── common │ │ │ ├── LICENSE │ │ │ ├── crt.S │ │ │ ├── crt_tcm.S │ │ │ ├── csr.h │ │ │ ├── link.ld │ │ │ ├── link_tcm.ld │ │ │ ├── riscv_csr_encoding.h │ │ │ ├── riscv_macros.h │ │ │ ├── sc_print.c │ │ │ ├── sc_print.h │ │ │ ├── sc_test.h │ │ │ └── scr1_specific.h │ │ ├── riscv_compliance │ │ │ ├── Makefile │ │ │ ├── aw_test_macros.h │ │ │ ├── check.c │ │ │ ├── compliance_io.h │ │ │ ├── compliance_test.h │ │ │ ├── riscv_test.h │ │ │ └── test_macros.h │ │ ├── riscv_isa │ │ │ ├── Makefile │ │ │ ├── riscv_test.h │ │ │ ├── rv32_tests.inc │ │ │ └── test_macros.h │ │ └── vectored_isr_sample │ │ │ ├── Makefile │ │ │ ├── timer.h │ │ │ └── v_isr_sample.S │ └── verilator_wrap │ │ ├── scr1_ahb_wrapper.c │ │ └── scr1_axi_wrapper.c │ └── src │ ├── ahb_tb.files │ ├── ahb_top.files │ ├── axi_tb.files │ ├── axi_top.files │ ├── core.files │ ├── core │ ├── primitives │ │ ├── scr1_cg.sv │ │ └── scr1_reset_cells.sv │ ├── scr1_clk_ctrl.sv │ ├── scr1_core_top.sv │ ├── scr1_dm.sv │ ├── scr1_dmi.sv │ ├── scr1_scu.sv │ ├── scr1_tapc.sv │ ├── scr1_tapc_shift_reg.sv │ └── scr1_tapc_synchronizer.sv │ ├── includes │ ├── scr1_ahb.svh │ ├── scr1_arch_description.svh │ ├── scr1_arch_types.svh │ ├── scr1_csr.svh │ ├── scr1_dm.svh │ ├── scr1_hdu.svh │ ├── scr1_ipic.svh │ ├── scr1_memif.svh │ ├── scr1_riscv_isa_decoding.svh │ ├── scr1_search_ms1.svh │ ├── scr1_tapc.svh │ └── scr1_tdu.svh │ ├── pipeline │ ├── scr1_ipic.sv │ ├── scr1_pipe_csr.sv │ ├── scr1_pipe_exu.sv │ ├── scr1_pipe_hdu.sv │ ├── scr1_pipe_ialu.sv │ ├── scr1_pipe_idu.sv │ ├── scr1_pipe_ifu.sv │ ├── scr1_pipe_lsu.sv │ ├── scr1_pipe_mprf.sv │ ├── scr1_pipe_tdu.sv │ ├── scr1_pipe_top.sv │ └── scr1_tracelog.sv │ ├── tb │ ├── scr1_memory_tb_ahb.sv │ ├── scr1_memory_tb_axi.sv │ ├── scr1_top_tb_ahb.sv │ ├── scr1_top_tb_ahb.sv.original │ └── scr1_top_tb_axi.sv │ └── top │ ├── scr1_dmem_ahb.sv │ ├── scr1_dmem_router.sv │ ├── scr1_dp_memory.sv │ ├── scr1_imem_ahb.sv │ ├── scr1_imem_router.sv │ ├── scr1_mem_axi.sv │ ├── scr1_tcm.sv │ ├── scr1_timer.sv │ ├── scr1_top_ahb.sv │ └── scr1_top_axi.sv ├── testbench └── tb_ssrv.v └── wiki ├── SSRV全解析.pdf └── png ├── ProjBuffer.PNG ├── diagram.png ├── fpga.PNG ├── hierarchy.png └── ssrv-on-scr1.png /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/.gitattributes -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/HEAD/.gitignore -------------------------------------------------------------------------------- /README.md: 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