├── .github └── workflows │ └── main.yaml ├── .gitignore ├── LICENSE ├── README.md ├── config.gtkw ├── project ├── build.properties └── plugins.sbt ├── scalastyle-config.xml ├── scalastyle-test-config.xml ├── src ├── main │ └── scala │ │ ├── Main.scala │ │ ├── core_ │ │ ├── Bundles.scala │ │ ├── CSR.scala │ │ ├── Const.scala │ │ ├── Core.scala │ │ ├── EX.scala │ │ ├── ID.scala │ │ ├── IF.scala │ │ ├── MEM.scala │ │ ├── RegFile.scala │ │ └── mmu │ │ │ ├── MMU.scala │ │ │ ├── PTW.scala │ │ │ └── TLB.scala │ │ └── devices │ │ ├── IOManager.scala │ │ ├── MockRam.scala │ │ ├── MockSerial.scala │ │ └── NullDev.scala └── test │ └── scala │ ├── core_ │ ├── CSRTest.scala │ ├── CoreTest.scala │ ├── EXTest.scala │ ├── FENCETest.scala │ ├── IDTest.scala │ ├── IFTest.scala │ ├── MEMTest.scala │ ├── MulDivTest.scala │ ├── RegFileTest.scala │ └── mmu │ │ ├── PTWTest.scala │ │ └── TLBTest.scala │ └── devices │ ├── DataHelper.scala │ └── MockRamTest.scala ├── test_asm ├── .gitignore ├── Makefile ├── entry.h ├── hello.c ├── linker.ld ├── pagetable.c ├── riscv-test │ ├── Makefile │ └── obj │ │ ├── rv32mi-p-breakpoint │ │ ├── rv32mi-p-csr │ │ ├── rv32mi-p-illegal │ │ ├── rv32mi-p-ma_addr │ │ ├── rv32mi-p-ma_fetch │ │ ├── rv32mi-p-mcsr │ │ ├── rv32mi-p-sbreak │ │ ├── rv32mi-p-scall │ │ ├── rv32mi-p-shamt │ │ ├── rv32si-p-csr │ │ ├── rv32si-p-dirty │ │ ├── rv32si-p-ma_fetch │ │ ├── rv32si-p-sbreak │ │ ├── rv32si-p-scall │ │ ├── rv32si-p-wfi │ │ ├── rv32ui-p-add │ │ ├── rv32ui-p-addi │ │ ├── rv32ui-p-and │ │ ├── rv32ui-p-andi │ │ ├── rv32ui-p-auipc │ │ ├── rv32ui-p-beq │ │ ├── rv32ui-p-bge │ │ ├── rv32ui-p-bgeu │ │ ├── rv32ui-p-blt │ │ ├── rv32ui-p-bltu │ │ ├── rv32ui-p-bne │ │ ├── rv32ui-p-fence_i │ │ ├── rv32ui-p-jal │ │ ├── rv32ui-p-jalr │ │ ├── rv32ui-p-lb │ │ ├── rv32ui-p-lbu │ │ ├── rv32ui-p-lh │ │ ├── rv32ui-p-lhu │ │ ├── rv32ui-p-lui │ │ ├── rv32ui-p-lw │ │ ├── rv32ui-p-or │ │ ├── rv32ui-p-ori │ │ ├── rv32ui-p-sb │ │ ├── rv32ui-p-sh │ │ ├── rv32ui-p-simple │ │ ├── rv32ui-p-sll │ │ ├── rv32ui-p-slli │ │ ├── rv32ui-p-slt │ │ ├── rv32ui-p-slti │ │ ├── rv32ui-p-sltiu │ │ ├── rv32ui-p-sltu │ │ ├── rv32ui-p-sra │ │ ├── rv32ui-p-srai │ │ ├── rv32ui-p-srl │ │ ├── rv32ui-p-srli │ │ ├── rv32ui-p-sub │ │ ├── rv32ui-p-sw │ │ ├── rv32ui-p-xor │ │ ├── rv32ui-p-xori │ │ ├── rv32ui-v-add │ │ ├── rv32ui-v-addi │ │ ├── rv32ui-v-and │ │ ├── rv32ui-v-andi │ │ ├── rv32ui-v-auipc │ │ ├── rv32ui-v-beq │ │ ├── rv32ui-v-bge │ │ ├── rv32ui-v-bgeu │ │ ├── rv32ui-v-blt │ │ ├── rv32ui-v-bltu │ │ ├── rv32ui-v-bne │ │ ├── rv32ui-v-fence_i │ │ ├── rv32ui-v-jal │ │ ├── rv32ui-v-jalr │ │ ├── rv32ui-v-lb │ │ ├── rv32ui-v-lbu │ │ ├── rv32ui-v-lh │ │ ├── rv32ui-v-lhu │ │ ├── rv32ui-v-lui │ │ ├── rv32ui-v-lw │ │ ├── rv32ui-v-or │ │ ├── rv32ui-v-ori │ │ ├── rv32ui-v-sb │ │ ├── rv32ui-v-sh │ │ ├── rv32ui-v-simple │ │ ├── rv32ui-v-sll │ │ ├── rv32ui-v-slli │ │ ├── rv32ui-v-slt │ │ ├── rv32ui-v-slti │ │ ├── rv32ui-v-sltiu │ │ ├── rv32ui-v-sltu │ │ ├── rv32ui-v-sra │ │ ├── rv32ui-v-srai │ │ ├── rv32ui-v-srl │ │ ├── rv32ui-v-srli │ │ ├── rv32ui-v-sub │ │ ├── rv32ui-v-sw │ │ ├── rv32ui-v-xor │ │ └── rv32ui-v-xori ├── serial.h ├── test.s ├── test2.s ├── test3.s ├── test4.s ├── test5.s ├── test6.s ├── test_csr.s ├── test_ecall.s ├── test_fence.s ├── test_m_extension.s ├── test_mtime.s └── test_ret.s └── tools ├── genCSRCode.py └── qemu_trace.py /.github/workflows/main.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/.github/workflows/main.yaml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/.gitignore -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/README.md -------------------------------------------------------------------------------- /config.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/config.gtkw -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.3.10 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/project/plugins.sbt -------------------------------------------------------------------------------- /scalastyle-config.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/scalastyle-config.xml -------------------------------------------------------------------------------- /scalastyle-test-config.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/scalastyle-test-config.xml -------------------------------------------------------------------------------- /src/main/scala/Main.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/Main.scala -------------------------------------------------------------------------------- /src/main/scala/core_/Bundles.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/Bundles.scala -------------------------------------------------------------------------------- /src/main/scala/core_/CSR.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/CSR.scala -------------------------------------------------------------------------------- /src/main/scala/core_/Const.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/Const.scala -------------------------------------------------------------------------------- /src/main/scala/core_/Core.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/Core.scala -------------------------------------------------------------------------------- /src/main/scala/core_/EX.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/EX.scala -------------------------------------------------------------------------------- /src/main/scala/core_/ID.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/ID.scala -------------------------------------------------------------------------------- /src/main/scala/core_/IF.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/IF.scala -------------------------------------------------------------------------------- /src/main/scala/core_/MEM.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/MEM.scala -------------------------------------------------------------------------------- /src/main/scala/core_/RegFile.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/RegFile.scala -------------------------------------------------------------------------------- /src/main/scala/core_/mmu/MMU.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/mmu/MMU.scala -------------------------------------------------------------------------------- /src/main/scala/core_/mmu/PTW.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/mmu/PTW.scala -------------------------------------------------------------------------------- /src/main/scala/core_/mmu/TLB.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/core_/mmu/TLB.scala -------------------------------------------------------------------------------- /src/main/scala/devices/IOManager.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/devices/IOManager.scala -------------------------------------------------------------------------------- /src/main/scala/devices/MockRam.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/devices/MockRam.scala -------------------------------------------------------------------------------- /src/main/scala/devices/MockSerial.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/devices/MockSerial.scala -------------------------------------------------------------------------------- /src/main/scala/devices/NullDev.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/main/scala/devices/NullDev.scala -------------------------------------------------------------------------------- /src/test/scala/core_/CSRTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/CSRTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/CoreTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/CoreTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/EXTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/EXTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/FENCETest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/FENCETest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/IDTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/IDTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/IFTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/IFTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/MEMTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/MEMTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/MulDivTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/MulDivTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/RegFileTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/RegFileTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/mmu/PTWTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/mmu/PTWTest.scala -------------------------------------------------------------------------------- /src/test/scala/core_/mmu/TLBTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/core_/mmu/TLBTest.scala -------------------------------------------------------------------------------- /src/test/scala/devices/DataHelper.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/devices/DataHelper.scala -------------------------------------------------------------------------------- /src/test/scala/devices/MockRamTest.scala: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/src/test/scala/devices/MockRamTest.scala -------------------------------------------------------------------------------- /test_asm/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/.gitignore -------------------------------------------------------------------------------- /test_asm/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/Makefile -------------------------------------------------------------------------------- /test_asm/entry.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/entry.h -------------------------------------------------------------------------------- /test_asm/hello.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/hello.c -------------------------------------------------------------------------------- /test_asm/linker.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/linker.ld -------------------------------------------------------------------------------- /test_asm/pagetable.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/pagetable.c -------------------------------------------------------------------------------- /test_asm/riscv-test/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/Makefile -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-breakpoint: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-breakpoint -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-csr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-csr -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-illegal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-illegal -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-ma_addr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-ma_addr -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-ma_fetch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-ma_fetch -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-mcsr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-mcsr -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-sbreak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-sbreak -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-scall: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-scall -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32mi-p-shamt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32mi-p-shamt -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32si-p-csr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32si-p-csr -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32si-p-dirty: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32si-p-dirty -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32si-p-ma_fetch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32si-p-ma_fetch -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32si-p-sbreak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32si-p-sbreak -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32si-p-scall: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32si-p-scall -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32si-p-wfi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32si-p-wfi -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-add: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-add -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-addi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-addi -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-and: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-and -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-andi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-andi -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-auipc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-auipc -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-beq: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-beq -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-bge: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-bge -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-bgeu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-bgeu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-blt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-blt -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-bltu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-bltu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-bne: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-bne -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-fence_i: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-fence_i -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-jal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-jal -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-jalr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-jalr -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-lb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-lb -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-lbu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-lbu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-lh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-lh -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-lhu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-lhu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-lui: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-lui -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-lw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-lw -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-or: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-or -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-ori: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-ori -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sb -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sh -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-simple: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-simple -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sll -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-slli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-slli -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-slt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-slt -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-slti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-slti -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sltiu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sltiu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sltu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sltu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sra: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sra -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-srai: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-srai -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-srl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-srl -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-srli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-srli -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sub: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sub -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-sw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-sw -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-xor: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-xor -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-p-xori: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-p-xori -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-add: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-add -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-addi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-addi -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-and: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-and -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-andi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-andi -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-auipc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-auipc -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-beq: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-beq -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-bge: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-bge -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-bgeu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-bgeu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-blt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-blt -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-bltu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-bltu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-bne: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-bne -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-fence_i: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-fence_i -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-jal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-jal -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-jalr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-jalr -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-lb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-lb -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-lbu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-lbu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-lh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-lh -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-lhu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-lhu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-lui: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-lui -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-lw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-lw -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-or: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-or -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-ori: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-ori -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sb -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sh -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-simple: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-simple -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sll -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-slli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-slli -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-slt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-slt -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-slti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-slti -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sltiu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sltiu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sltu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sltu -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sra: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sra -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-srai: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-srai -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-srl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-srl -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-srli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-srli -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sub: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sub -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-sw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-sw -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-xor: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-xor -------------------------------------------------------------------------------- /test_asm/riscv-test/obj/rv32ui-v-xori: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/riscv-test/obj/rv32ui-v-xori -------------------------------------------------------------------------------- /test_asm/serial.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/serial.h -------------------------------------------------------------------------------- /test_asm/test.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test.s -------------------------------------------------------------------------------- /test_asm/test2.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test2.s -------------------------------------------------------------------------------- /test_asm/test3.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test3.s -------------------------------------------------------------------------------- /test_asm/test4.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test4.s -------------------------------------------------------------------------------- /test_asm/test5.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test5.s -------------------------------------------------------------------------------- /test_asm/test6.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test6.s -------------------------------------------------------------------------------- /test_asm/test_csr.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test_csr.s -------------------------------------------------------------------------------- /test_asm/test_ecall.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test_ecall.s -------------------------------------------------------------------------------- /test_asm/test_fence.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test_fence.s -------------------------------------------------------------------------------- /test_asm/test_m_extension.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test_m_extension.s -------------------------------------------------------------------------------- /test_asm/test_mtime.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test_mtime.s -------------------------------------------------------------------------------- /test_asm/test_ret.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/test_asm/test_ret.s -------------------------------------------------------------------------------- /tools/genCSRCode.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/tools/genCSRCode.py -------------------------------------------------------------------------------- /tools/qemu_trace.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/HEAD/tools/qemu_trace.py --------------------------------------------------------------------------------