├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── common ├── Makefrag ├── csrc │ ├── fesvr_zynq.cc │ ├── zynq_driver.cc │ └── zynq_driver.h ├── load_card.sh ├── make_bitstream.tcl ├── project │ ├── build.properties │ └── build.scala ├── rocketchip_wrapper.v ├── scripts │ ├── upgrade_version.sh │ └── upgrade_version.tcl ├── src │ └── main │ │ └── scala │ │ ├── BOOM.scala │ │ ├── Configs.scala │ │ ├── Drivers.scala │ │ ├── Generator.scala │ │ ├── Serdes.scala │ │ ├── TestHarness.scala │ │ ├── Top.scala │ │ └── ZynqAdapter.scala └── zynq_rocketchip.tcl ├── project └── build.properties ├── simulation ├── .gitignore ├── Makefile └── src │ └── verilog │ └── .gitkeep ├── src ├── sw ├── .gitignore ├── Makefile ├── README.md ├── build-pk.sh ├── build-riscv-tools.sh ├── buildroot-config ├── buildroot-overlay │ ├── .gitignore │ └── etc │ │ └── init.d │ │ ├── rcK │ │ └── rcS ├── busybox-config └── linux-config ├── zc706 ├── Makefile ├── soft_config │ ├── zc706_devicetree.dts │ └── zynq_zc70x.h └── src │ ├── constrs │ └── base.xdc │ ├── tcl │ └── zc706_bd.tcl │ └── verilog │ └── clocking.vh ├── zc706_MIG ├── Makefile ├── soft_config │ ├── zc706_devicetree.dts │ └── zynq_zc70x.h └── src │ ├── constrs │ └── base.xdc │ ├── tcl │ └── zc706_MIG_bd.tcl │ └── verilog │ ├── clocking.vh │ └── rocketchip_wrapper.v └── zedboard ├── Makefile ├── soft_config ├── skeleton.dtsi ├── zedboard_devicetree.dts ├── zynq-7000.dtsi └── zynq_zed.h └── src ├── constrs └── base.xdc ├── tcl └── zedboard_bd.tcl └── verilog └── clocking.vh /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-boom/fpga-zynq/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-boom/fpga-zynq/HEAD/.gitmodules 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