├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── build.sbt ├── common ├── Makefrag ├── csrc │ ├── fesvr_zynq.cc │ ├── zynq_driver.cc │ └── zynq_driver.h ├── load_card.sh ├── make_bitstream.tcl ├── project │ ├── build.properties │ └── build.scala ├── rocketchip_wrapper.v ├── scripts │ ├── upgrade_version.sh │ └── upgrade_version.tcl ├── src │ └── main │ │ └── scala │ │ ├── BOOM.scala │ │ ├── Configs.scala │ │ ├── Drivers.scala │ │ ├── Generator.scala │ │ ├── Serdes.scala │ │ ├── TestHarness.scala │ │ ├── Top.scala │ │ └── ZynqAdapter.scala └── zynq_rocketchip.tcl ├── project └── build.properties ├── simulation ├── .gitignore ├── Makefile └── src │ └── verilog │ └── .gitkeep ├── src ├── sw ├── .gitignore ├── Makefile ├── README.md ├── build-pk.sh ├── build-riscv-tools.sh ├── buildroot-config ├── buildroot-overlay │ ├── .gitignore │ └── etc │ │ └── init.d │ │ ├── rcK │ │ └── rcS ├── busybox-config └── linux-config ├── zc706 ├── Makefile ├── soft_config │ ├── zc706_devicetree.dts │ └── zynq_zc70x.h └── src │ ├── constrs │ └── base.xdc │ ├── tcl │ └── zc706_bd.tcl │ └── verilog │ └── clocking.vh ├── zc706_MIG ├── Makefile ├── soft_config │ ├── zc706_devicetree.dts │ └── zynq_zc70x.h └── src │ ├── constrs │ └── base.xdc │ ├── tcl │ └── zc706_MIG_bd.tcl │ └── verilog │ ├── clocking.vh │ └── rocketchip_wrapper.v └── zedboard ├── Makefile ├── soft_config ├── skeleton.dtsi ├── zedboard_devicetree.dts ├── zynq-7000.dtsi └── zynq_zed.h └── src ├── constrs └── base.xdc ├── tcl └── zedboard_bd.tcl └── verilog └── clocking.vh /.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | *.jou 3 | *.Xil 4 | *.swp 5 | *.bak 6 | firrtl_black_box_resource_files.f 7 | AsyncResetReg.v 8 | plusarg_reader.v 9 | rocketchip_wrapper.bit 10 | NA 11 | 12 | common/build 13 | common/target 14 | common/project/target 15 | common/lib 16 | common/Makefrag.pkgs 17 | 18 | zedboard/zedboard_rocketchip_* 19 | zedboard/src/tcl/zedboard_rocketchip_*.tcl 20 | zedboard/src/tcl/make_bitstream_*.tcl 21 | zedboard/src/verilog/rocketchip_wrapper.v 22 | zedboard/src/verilog/Top.*.v 23 | zedboard/src/verilog/AsyncResetReg.v 24 | zedboard/src/verilog/plusarg_reader.v 25 | zedboard/deliver_output 26 | zedboard/soft_build 27 | 28 | zc706/zc706_rocketchip_* 29 | zc706/src/tcl/zc706_rocketchip_*.tcl 30 | zc706/src/tcl/make_bitstream_*.tcl 31 | zc706/src/verilog/rocketchip_wrapper.v 32 | zc706/src/verilog/Top.*.v 33 | zc706/src/verilog/AsyncResetReg.v 34 | zc706/src/verilog/plusarg_reader.v 35 | zc706/deliver_output 36 | zc706/soft_build 37 | 38 | zc706_MIG/zc706_MIG_rocketchip_* 39 | zc706_MIG/src/tcl/zc706_MIG_rocketchip_*.tcl 40 | zc706_MIG/src/tcl/make_bitstream_*.tcl 41 | zc706_MIG/src/verilog/rocketchip_wrapper.v 42 | zc706_MIG/src/verilog/Top.*.v 43 | zc706_MIG/src/verilog/AsyncResetReg.v 44 | zc706_MIG/src/verilog/plusarg_reader.v 45 | zc706_MIG/deliver_output 46 | zc706_MIG/soft_build 47 | 48 | target 49 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "zedboard/fpga-images-zedboard"] 2 | path = zedboard/fpga-images-zedboard 3 | url = https://github.com/ucb-bar/fpga-images-zedboard.git 4 | [submodule "zc706/fpga-images-zc706"] 5 | path = zc706/fpga-images-zc706 6 | url = https://github.com/ucb-bar/fpga-images-zc706.git 7 | [submodule "testchipip"] 8 | path = testchipip 9 | url = https://github.com/ucb-bar/testchipip.git 10 | [submodule "boom-template"] 11 | path = boom-template 12 | url = https://github.com/riscv-boom/boom-template.git 13 | [submodule "sw/buildroot"] 14 | path = sw/buildroot 15 | url = https://github.com/sifive/buildroot.git 16 | [submodule "sw/linux"] 17 | path = sw/linux 18 | url = https://github.com/riscv/riscv-linux.git 19 | [submodule "sw/riscv-pk"] 20 | path = sw/riscv-pk 21 | url = https://github.com/riscv/riscv-pk.git 22 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2014, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Rocket Chip on Zynq FPGAs 2 | ========================= 3 | 4 | This repository contains the files needed to run the RISC-V [rocket chip](https://github.com/ucb-bar/rocket-chip) on 5 | various Zynq FPGA boards ([Zybo](http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO), [Zedboard](http://zedboard.org/product/zedboard), [ZC706](http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm)) with Vivado 2018.2. Efforts have been made to not only automate the process of generating files for these boards, but to also reduce duplication as well as the size of this repo. Prebuilt images are available in git submodules, and they are only shallowly cloned if requested. 6 | 7 | 8 | ### How to use this README 9 | 10 | This README contains 3 major sets of instructions: 11 | 12 | 1) [Quick Instructions](#quickinst): This is the simplest way to get started - you'll download the relevant prebuilt images for your board and learn how to run binaries on the RISC-V Rocket Core. These instructions require only that you have a compatible board - neither Vivado nor the RISC-V Toolchain are necessary. 13 | 14 | 2) [Pushing Your Rocket Modifications to the FPGA](#bitstream): These instructions walk through what we believe is the common case - a user wanting to utilize a custom-generated Rocket Core. 15 | 16 | 3) [Building Everything from Scratch](#fromscratch): Here, we discuss how to build the full stack from scratch. It is unlikely that you'll need to use these instructions, unless you are intending to make changes to the configuration of the Zynq ARM Core or `u-boot`. 17 | 18 | Finally, the bottom of the README contains a set of [Appendices](#appendices), which document some common operations that we believe are useful or provides more depth on commands described elsewhere in the documentation. 19 | 20 | To guide you through the rest of the documentation, we have provide both a [Table of Contents](#toc) and an [Overview](#overview). 21 | 22 | _Note_: If you are seeking to test your own modifications to rocket chip (RC) using this repository, it must be derived from RC commit [fb476d1](https://github.com/ucb-bar/rocket-chip/tree/fb476d193cc21dd66d81cc5890883bd466f889f7) or later, as this project expects both a debug module to be present, and links directly against RC to build a top-level project directly in chisel. Otherwise, you should use an older version of this repository [bf6d00c2](https://github.com/ucb-bar/fpga-zynq/tree/bf6d00c211c46d60662a9ef6e9460a405cc9b0d5) or earlier, which has support for HTIF-based rocket chip instances. 23 | 24 | ### Table of Contents 25 | + [Overview of System Stack](#overview) 26 | + [1 - Quick Instructions](#quickinst) 27 | + [2 - Pushing Your Rocket Modifications to the FPGA](#bitstream) 28 | + [Setting Up Your Workspace](#workspace) 29 | + [Configuring Rocket Chip](#configRC) 30 | + [Generating Verilog for Rocket Chip](#genRC) 31 | + [Generating Project for Configuration](#projRC) 32 | + [Repacking `boot.bin`](#repack) 33 | + [3 - Building Everything from Scratch](#fromscratch) 34 | + [Project Setup](#setup) 35 | + [Generating a Bitstream](#bitstream) 36 | + [Building the FSBL](#fsbl) 37 | + [Building u-boot for the Zynq ARM Core](#u-boot) 38 | + [Creating `boot.bin`](#boot.bin) 39 | + [Building linux for the ARM PS](#arm-linux) 40 | + [Building riscv-linux](#riscv-linux) 41 | + [Booting Up and Interacting with the RISC-V Rocket Core](#booting) 42 | + [Appendices](#appendices) 43 | + [Connecting to the Board](#connecting) 44 | + [Getting Files On & Off the Board](#transferring) 45 | + [Working with Vivado](#vivado) 46 | + [Changing the Processor's Clockrate](#clockrate) 47 | + [Contents of the SD Card](#sdcard) 48 | + [Building fesvr-zynq](#fesvr) 49 | + [Building riscv-tools for Zybo](#zybotools) 50 | + [Acknowledgements](#ack) 51 | 52 | 53 | 54 | ### Overview of System Stack 55 | Our system will allow you to run a RISC-V binary on a rocket core instantiated on a supported Zynq FPGA. This section will outline the stack of all of the parts involved and by proxy, outline the rest of the documentation. Going top-down from the RISC-V binary to the development system: 56 | 57 | **Target Application** (RISC-V binary) 58 | will run on top of whatever kernel the rocket chip is running. Compiled by [riscv-gcc](https://github.com/riscv/riscv-gcc) or [riscv-llvm](https://github.com/riscv/riscv-llvm). 59 | 60 | **RISC-V Kernel** ([proxy kernel](https://github.com/riscv/riscv-pk) or [RISC-V Linux](https://github.com/riscv/riscv-linux)) 61 | runs on top of the rocket chip. The proxy kernel is extremely lightweight and designed to be used with a single binary linked against Newlib while RISC-V Linux is appropriate for everything else. 62 | 63 | **Rocket Chip** ([rocket core](https://github.com/ucb-bar/rocket) with L1 instruction and data caches) 64 | is instantiated on the FPGA. Many of its structures will typically map to various hard blocks including BRAMs and DSP slices. It communicates to the host ARM core on the Zynq via AXI. 65 | 66 | **Front-end Server** ([riscv-fesvr](https://github.com/riscv/riscv-fesvr)) 67 | runs on the host ARM core and provides an interface to the rocket chip running on the FPGA (connected via AXI). 68 | 69 | **Zynq ARM Core** (actually dual Cortex A9) 70 | runs Linux and simplifies interfacing with the FPGA. 71 | 72 | **FPGA Board** (Zybo, Zedboard, or ZC706) 73 | contains the Zynq FPGA and several I/O devices. At power on, the contents of the SD card are used to configure the FPGA and boot Linux on the ARM core. 74 | 75 | **External Communication** (TTY over serial on USB or telnet/ssh over ethernet) 76 | allows the development system to communicate with the FPGA board. 77 | 78 | **Development System** (PC with SD card reader) 79 | generates the images to configure the FPGA. 80 | 81 | 82 | 83 | ### 1) Quick Instructions 84 | ------------------ 85 | _Using prebuilt images, run hello world and/or linux on rocket_ 86 | 87 | First, enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). From there, run the following to download all of the necessary images: 88 | 89 | $ make fetch-images 90 | 91 | If you'd also like to try riscv-linux on rocket, run the following: 92 | 93 | $ make fetch-riscv-linux 94 | 95 | Next, insert the SD card on the development system and copy over the images: 96 | 97 | $ make load-sd SD=path_to_mounted_sdcard 98 | 99 | Finally, eject the SD card, insert it into the board, set the board's boot jumper to "SD", and power the board on. Connect to the board with an ethernet cable (password is _root_) and run hello world: 100 | 101 | $ ssh root@192.168.1.5 102 | root@zynq:~# ./fesvr-zynq pk hello 103 | hello! 104 | 105 | Awesome! You can now run RISC-V binaries on Rocket. If you'd like to boot linux on the Rocket core, see _[Booting Up and Interacting with the RISC-V Rocket Core](#booting)_. 106 | 107 | 108 | 109 | ### 2) Pushing Your Rocket Modifications to the FPGA 110 | ------------------------- 111 | 112 | #### Setting Up Your Workspace 113 | _Requires: Vivado 2018.2 and its settings64.sh and a JVM that can run Scala_ 114 | 115 | After you clone the repository for the first time, you must initialize 116 | the submodules rocket-chip and testchipip, as well as the first-level 117 | submodules of rocket-chip itself. 118 | 119 | $ make init-submodules 120 | 121 | If you have your own working rocket-chip directory that you would like to use, override the `ROCKET_DIR` make variable set in common/Makefrag. 122 | 123 | #### Configuring Rocket Chip 124 | 125 | The verilog for the rocket chip is generated by [Chisel](https://chisel.eecs.berkeley.edu) and thus is not intended to be edited by humans. This project instantiates rocket chip as module larger top level chisel project, that includes an adapter to interface the ARM core with rocket chip's debug module. 126 | 127 | The configuration used to generate the rocket chip comes from the `CONFIG` environment variables. If `CONFIG` isn't set by the environment, it is taken from the `Makefile` for the current board. For this example, we use the Zybo which has a default configuration of `ZynqSmallConfig`. 128 | 129 | #### Generating Verilog for Rocket Chip 130 | 131 | Enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). After making changes within `rocket-chip` and/or `common/src/main/scala`, you can run the rocket chip generator and copy the newly generated verilog back into the board's src/verilog directory with: 132 | 133 | $ make rocket 134 | 135 | You can also explicitly set the `CONFIG` variable from the command-line (can do this for any command): 136 | 137 | $ make rocket CONFIG=MyFPGAConfig 138 | 139 | By default this will look up a configuration specified in the rocket chip library. You may define a custom one without recompiling rocketchip, by defining in the zynq chisel sources at `common/src/main/scala`, and instead calling: 140 | 141 | $ make rocket CONFIG_PROJECT=zynq CONFIG=MyCustomZynqConfig 142 | 143 | The generator will instead look for the configuration definition in the local project instead of the rocket chip library. 144 | 145 | 146 | #### Generating Project for Configuration 147 | To generate a Vivado project specific to the board and the configuration (one project per configuration): 148 | 149 | $ make project 150 | 151 | This step only needs to be done once per configuration. 152 | 153 | 154 | #### Repacking `boot.bin` 155 | 156 | Once you have changed the design, you will need to generate a new bitstream and that will need to be packaged in `boot.bin`. `boot.bin` also contains the binaries needed for startup (`FSBL.elf` and `u-boot.elf`) but these can be reused. From within the board's directory (_zybo_ in this example), to repack `boot.bin`: 157 | 158 | $ make fpga-images-zybo/boot.bin 159 | 160 | If you have modified the verilog for your project but not generated a new bitstream, `make` should generate a new bitstream automatically. To use the new `boot.bin`, copy it to the SD card, insert the SD card into the board, and power on the board. 161 | 162 | 163 | 164 | ### 3) Building Everything from Scratch 165 | ----------------------- 166 | This section describes how to build the entire project from scratch. Most likely, you will not need to perform all of these steps, however we keep them here for reference. Various other sections of this README may selectively refer to these sections. This section assumes that you've just pulled this repository and have sourced the settings file for Vivado 2018.2. 167 | 168 | For ease of exposition, we will be describing all of the commands assuming that we are working with the `zybo` and its default configuration `ZynqSmallConfig`. Replacing references to the `zybo` with `zedboard` or `zc706` will allow you to use these instructions for those boards. 169 | 170 | From here on, `$REPO` will refer to the location of the `fpga-zynq` repository. 171 | 172 | ### 3.1) Project Setup 173 | 174 | First, we need to generate a Vivado project from the source files that are present in a particular board's directory. 175 | 176 | $ cd $REPO/zybo 177 | $ make project 178 | 179 | ### 3.2) Generating a Bitstream 180 | 181 | Next, let's open up the project in the Vivado GUI: 182 | 183 | $ make vivado 184 | # OR 185 | $ cd zybo_rocketchip_ZynqSmallConfig 186 | $ vivado zybo_rocketchip_ZynqSmallConfig.xpr 187 | 188 | If you wish to make any modifications to the project, you may now do so. Once you've finished, let's move on: 189 | 190 | Inside Vivado, select _Open Block Design_ followed by _system.bd_ in the dropdown. This will open a block diagram for the Zynq PS Configuration and is necessary for correct FSBL generation. 191 | 192 | Next, select _Generate Bitstream_. Vivado will now step through the usual Synthesis/Implementation steps. Upon completion, if you're interested in only the bitstream, you can stop here; the file you want is in: 193 | 194 | `$REPO/zybo/zybo_rocketchip_ZynqSmallConfig/zybo_rocketchip_ZynqSmallConfig.runs/impl_1/rocketchip_wrapper.bit` 195 | 196 | Otherwise, let's continue on to select _Open Implemented Design_. This is again necessary to properly export the description of our Hardware for the Xilinx SDK to use. 197 | 198 | At this point, select _File -> Export -> Export Hardware_. This will create the following directory: 199 | 200 | `$REPO/zybo/zybo_rocketchip_ZynqSmallConfig/zybo_rocketchip_ZynqSmallConfig.sdk` 201 | 202 | This directory contains a variety of files that provide information about the hardware to the SDK. Let's continue on to building the FSBL. 203 | 204 | 205 | ### 3.3) Building the FSBL 206 | 207 | This step assumes that you have just generated the bitstream. Inside the Vivado GUI, select "Launch SDK". This will open up the Xilinx SDK preconfigured with the description of our hardware. In order to generate the FSBL, do the following: 208 | 209 | 1) Select _File -> New -> Application Project_ 210 | 211 | 2) In the new window, type "FSBL" as the Project name, and ensure that the rest of the properties are correctly set (disregarding the greyed out _Location_ field): 212 | 213 | 214 | 215 | 3) Select _Next_, at which point you should be given a set of options. Select _Zynq FSBL_ and _Finish_. 216 | 217 | 4) The SDK will proceed to automatically compile the FSBL. You can see the progress in the Console. 218 | 219 | 5) Once the build is finished, we need to build u-boot before returning to the SDK in order to create our BOOT.bin. 220 | 221 | ### 3.4) Building u-boot for the Zynq ARM Core 222 | 223 | Returning to the command line, do the following from the directory corresponding to your board: 224 | 225 | $ make arm-uboot 226 | 227 | This target performs a variety of commands. It will first pull the u-boot source from the Xilinx repositories (see the submodule in `$REPO/common/u-boot-xlnx`), patch it with the necessary files found in `$REPO/zybo/soft_config/`, compile u-boot, and place the resulting u-boot.elf file in `$REPO/zybo/soft_build/u-boot.elf`. 228 | 229 | ### 3.5) Creating `boot.bin` 230 | 231 | At this point, we have built up all of the necessary components to create our `boot.bin` file. Returning to the Xilinx SDK, select _Xilinx Tools -> Create Zynq Boot Image_. 232 | 233 | First, you should fill in the _Output BIF file path_ with `$REPO/zybo/deliver_output`. If this directory has not already been created, you may go ahead and create it (this is where we will place all of the items that we will ultimately transfer to the SD card). See the below for a sample path. Performing this step will also fill in the _Output path_ field, which specifies the location of the `BOOT.bin` file that we desire. 234 | 235 | Next, we will add the individual files that make up `BOOT.bin`. Order is important, so follow these steps exactly: 236 | 237 | 1) Select _Add_ and in the window that opens, click _Browse_ and specify the following location: 238 | 239 | `$REPO/zybo/zybo_rocketchip_ZynqSmallConfig/zybo_rocketchip_ZynqSmallConfig.sdk/FSBL/Debug/FSBL.elf` 240 | 241 | Once you have done so select the dropdown next to _Partition type_ and select _bootloader_. You must perform this step **after** selecting the path, else the SDK will change it back to _datafile_, and your `BOOT.bin` will not work. 242 | 243 | At the conclusion of this step, the _Add partition_ window will look something like: 244 | 245 | 246 | 247 | Click _OK_to return to the previous window. 248 | 249 | 2) Once more, click _Add_. In the new _Add partition_ window, click _Browse_ and specify the following location: 250 | 251 | `$REPO/zybo/zybo_rocketchip_ZynqSmallConfig/zybo_rocketchip_ZynqSmallConfig.runs/impl_1/rocketchip_wrapper.bit` 252 | 253 | Ensure that _Partition type_ is set to datafile and click _OK_. 254 | 255 | 3) Click _Add_ a final time. Click _Browse_ and this time select our compiled `u-boot.elf`: 256 | 257 | `$REPO/zybo/soft_build/u-boot.elf` 258 | 259 | Again, ensure that _Partition type_ is set to datafile and click _OK_. 260 | 261 | 4) At this point, the window should match the following (click the image to zoom in): 262 | 263 | 264 | 265 | Select _Create Image_. This will produce a `BOOT.bin` file in the `$REPO/zybo/deliver_output` directory. 266 | 267 | If you make modifications to the project in the future, you can avoid having to perform this step manually and 268 | instead may reuse the output.bif file that the SDK generates the first time you use _Create Zynq Boot Image._ 269 | Use the following make target to do so: 270 | 271 | $ make deliver_output/boot.bin 272 | 273 | ### 3.6) Building linux for the ARM PS 274 | 275 | As part of our bootstrapping process, we need to boot linux on the ARM core in the Zynq. We can build this copy of linux like so (again assuming that we are in `$REPO/zybo`): 276 | 277 | $ make arm-linux 278 | 279 | We additionally need to produce the `devicetree.dtb` file that linux will use to setup peripherals of the ARM core. We can produce this like so: 280 | 281 | $ make arm-dtb 282 | 283 | At this point, the `$REPO/zybo/deliver_output` directory contains the following files: 284 | 285 | * `BOOT.bin` - (the filename is case insensitive, you may see `boot.bin`). This contains the FSBL, the bitstream with Rocket, and u-boot. 286 | * `uImage` - Linux for the ARM PS 287 | * `devicetree.dtb` - Contains information about the ARM core's peripherals for linux. 288 | 289 | The only remaining file that we are missing at this point is `uramdisk.image.gz`, the root filesystem for linux on the ARM Core. You can obtain it like so (it will be placed in `$REPO/zybo/deliver_output`): 290 | 291 | $ make fetch-ramdisk 292 | 293 | Now, take the four files in `deliver_output/`, and place them on the root of the SD card that we will insert into the Zybo. The layout of your SD card should match the following: 294 | 295 | SD_ROOT/ 296 | |-> boot.bin 297 | |-> devicetree.dtb 298 | |-> uImage 299 | |-> uramdisk.image.gz 300 | 301 | At this point, you have performed the necessary steps to run binaries on Rocket. See [Section 3.8](#booting) for how to do so. If you are interested in running riscv-linux on Rocket, continue on to Section 3.7: 302 | 303 | ### 3.7) Building/Obtaining riscv-linux 304 | 305 | There are two options to obtain riscv-linux: 306 | 307 | #### Method 1) Build from Source 308 | 309 | Note: If you are working with the Zybo, you should not build `riscv-linux` from source. The Zybo cannot fit an FPU and thus uses a modified version of the kernel that ignores FPU instructions. Software floating point emulation support is planned but not yet available. The binary for this build can be obtained using Method 2 below. 310 | 311 | To build [riscv-linux](http://github.com/riscv/riscv-linux) for Rocket, follow the instructions [here](https://github.com/riscv/riscv-tools#linuxman). Upon completing the linked tutorial, you should have two files: `vmlinux` and `root.bin`. You should place them on your SD card in a directory called `riscv`. 312 | 313 | #### Method 2) Download the Pre-Built Binary and Root FS 314 | 315 | Run the following from within `$REPO/zybo`. 316 | 317 | $ make fetch-riscv-linux-deliver 318 | 319 | Then, copy the `$REPO/zybo/deliver_output/riscv` directory to the root of your SD Card. 320 | 321 | #### Continuing: 322 | 323 | After performing either of these steps, your SD card layout should match the following: 324 | 325 | SD_ROOT/ 326 | |-> riscv/ 327 | |-> root.bin 328 | |-> vmlinux 329 | |-> boot.bin 330 | |-> devicetree.dtb 331 | |-> uImage 332 | |-> uramdisk.image.gz 333 | 334 | 335 | ### 3.8) Booting Up and Interacting with the RISC-V Rocket Core 336 | 337 | First, insert the SD card and follow the instructions in [Appendix A](#connecting) 338 | to connect to your board. You can login to the board with username _root_ and 339 | password _root_. Once you're at the prompt, you can run a basic hello world 340 | program on rocket like so: 341 | 342 | root@zynq:~# ./fesvr-zynq pk hello 343 | hello! 344 | 345 | If you've downloaded the necessary files to boot riscv-linux, you may now do so. 346 | First however, you should mount the SD card using the instructions in [Appendix B](#mountsd). 347 | Then, to boot riscv-linux, run: 348 | 349 | root@zynq:~# ./fesvr-zynq +disk=/sdcard/riscv/root.bin bbl /sdcard/riscv/vmlinux 350 | 351 | Once you hit enter, you'll see the linux boot messages scroll by, and you'll be 352 | presented with a busybox prompt from riscv-linux running on rocket! 353 | 354 | Appendices 355 | ------------ 356 | 357 | ### A) Connecting to the Board 358 | 359 | #### Serial-USB 360 | On the Zybo and Zedboard a single serial-USB cable is needed but on the ZC706 you will also need a USB type A to type B cable (and possibly some drivers). To connect: 361 | 362 | $ screen /dev/tty.usbmodem1411 115200,cs8,-parenb,-cstopb 363 | 364 | _Note:_ The numbers following `tty.usbmodem` may vary slightly. On the Zybo, 365 | replace `usbmodem` with `usbserial-` and on the ZC706, replace it with 366 | `SLAB_USBtoUART`. 367 | 368 | #### Ethernet 369 | The board has an IP of 192.168.1.5 and can be accessed by username/password of root/root on telnet and ssh. For example: 370 | 371 | $ ssh root@192.168.1.5 372 | 373 | _Note:_ Make sure your development system ethernet interface is configured to be on the 192.168.1.x subnet. The default configuration intends for the board to be directly attached to the development system (single cable). If you want to place the board on a larger network, we recommend changing the root password to something stronger and changing the IP configuration to mesh well with your network. 374 | 375 | 376 | ### B) Getting Files On & Off the Board 377 | 378 | #### Copying Files over Ethernet 379 | The easiest way to get a file onto the board is to copy it with scp over ethernet: 380 | 381 | $ scp file root@192.168.1.5:~/ 382 | 383 | _Note:_ Linux is running out of a RAMdisk, so to make a file available after a reboot, copy it to the SD card or modify the RAMdisk. 384 | 385 | #### Mounting the SD Card on the Board 386 | You can mount the SD card on the board by: 387 | 388 | root@zynq:~# mkdir /sdcard 389 | root@zynq:~# mount /dev/mmcblk0p1 /sdcard 390 | 391 | When you are done, don't forget to unmount it: 392 | 393 | root@zynq:~# umount /sdcard 394 | 395 | #### Changing the RAMDisk 396 | _Requires: [u-boot](http://www.denx.de/wiki/U-Boot/) and sudo_ 397 | 398 | The RAMDisk (`uramdisk.image.gz`) that holds Linux for the ARM cores is a gzipped cpio archive with a u-boot header for the board. To open the RAMdisk: 399 | 400 | $ make ramdisk-open 401 | 402 | When changing or adding files, be sure to keep track of owners, groups, and permissions. When you are done, to package it back up: 403 | 404 | $ make ramdisk-close 405 | 406 | A useful application of this is to add your SSH public key to `.ssh/authorized_keys` so you can have passwordless login to the board. 407 | 408 | _Note:_ Since these ramdisk operations use sudo on files, they may not work on a network mounted filesystem. To get around this limitation, it is easiest to just copy it to a local filesystem when modifying the ramdisk. 409 | 410 | 411 | ### C) Working with Vivado 412 | 413 | _Requires: Vivado 2018.2 and its settings64.sh sourced_ 414 | 415 | First, enter into the directory for your board (current options are `zybo`, `zedboard`, and `zc706`). To generate a bitstream, you will need a Vivado project. You should only need to generate it once, but the automation this repo provides makes it easy to generate again if you delete the project. To generate a Vivado project from scratch: 416 | 417 | $ make project 418 | 419 | To generate a bitstream from the command-line: 420 | 421 | $ make bitstream 422 | 423 | To launch Vivado in GUI mode: 424 | 425 | $ make vivado 426 | 427 | 428 | ### D) Changing the Processor's Clockrate 429 | You can change the clockrate for the rocket chip by changing `RC_CLK_MULT` and `RC_CLK_DIVIDE` within a board's `src/verilog/clocking.vh`. After that change, you will need to generate a new bitstream (and `boot.bin`). 430 | 431 | _Note:_ Although rarely needed, it is possible to change the input clockrate to the FPGA by changing it within the block design, `src/constrs/base.xdc`, and `ZYNQ_CLK_PERIOD` within `src/verilog/clocking.vh`. This will also require regenerating `FSBL.elf`, the bitstream, and of course `boot.bin`. 432 | 433 | 434 | ### E) Contents of the SD Card 435 | The SD card is used by the board to configure the FPGA and boot up the ARM core. All of these files are available within a board's fpga-images submodule, but they can also be built from scratch. Here is a summary of the files and their purposes: 436 | 437 | * `boot.bin` is generated by the Xilinx SDK and is actually three files. To generate it from scratch, follow the instructions from Section 3 up through [Section 3.5 Creating boot.bin](#boot.bin). To repack it from existing components, follow [Repacking boot.bin](#repack). `boot.bin` contains: 438 | * Bitstream (`rocketchip_wrapper.bit`) configures the FPGA with the rocket chip design. To build it with the GUI, see [Section 3.2 Generating a Bitstream](#bitstream) and to build it with the command-line, see: [Working with Vivado](#vivado). 439 | * First Stage Bootloader (`FSBL.elf`) - This bootloader configures the Zynq processing system based on the block design in the Vivado project. The FSBL will hand-off to `u-boot` once the processing system is setup. We build the FSBL using the Xilinx SDK and hardware information exported from Vivado. (see [Section 3.3](#fsbl)) 440 | * u-boot (`u-boot.elf`) - This bootloader takes configuration information and prepares the ARM processing system for booting linux. Once configuration is complete, `u-boot` will hand-off execution to the ARM linux kernel. We build `u-boot` directly from the [Xilinx u-boot repository](https://github.com/Xilinx/u-boot-xlnx), with some configuration modifications to support Rocket. (see [Section 3.4](#u-boot)) 441 | * ARM Linux (`uImage`) - This is a copy of linux designed to run on the ARM processing system. From within this linux environment, we will be able to run tools (like `fesvr-zedboard`) to interact with the RISC-V Rocket Core. We build directly from the [Xilinx linux repository](https://github.com/Xilinx/linux-xlnx), with a custom device tree file to support Rocket. (see [Section 3.6](#arm-linux)) 442 | * ARM RAMDisk (`uramdisk.image.gz`) - The RAMDisk is mounted by ARM Linux and contains the root filesystem. For obtaining it, see [Section 3.6](#arm-linux), and for modifying it, see [Appendix B](#transferring). 443 | * `devicetree.dtb` - Contains information about the ARM core's peripherals for Linux. (See [Section 3.6](#arm-linux)) 444 | * `riscv/` (optional) - This directory is only needed if you intend to run Linux on the rocket chip itself. 445 | * RISC-V Linux (`riscv/vmlinux`) - This is the kernel binary for Linux on Rocket. If you are using the zybo, you will need to use a special kernel that ignores floating point instructions, since the zybo cannot fit an FPU. Fetching this version is handled automatically by our scripts. (See [Section 3.7](#riscv-linux)) 446 | * RISC-V RAMDisk (`riscv/root.bin`) - The RAMDisk is mounted by RISC-V Linux and contains the root filesystem. (See [Section 3.7](#riscv-linux)) 447 | 448 | 449 | ### F) Building fesvr-zynq 450 | 451 | The [riscv-fesvr repo](http://github.com/riscv/riscv-fesvr) provides against which the zynq-fesvr is linked. Additionally, `common/csrc` includes source for main, and a simple driver, which hands off debug module requests and reponses between the ARM core and rocket chip. Before building, make sure the 2018.2 version of settings64.sh is sourced. To build the riscv-fesvr binary for Linux ARM target (to run on Zynq board), type: 452 | 453 | $ make fesvr-zynq 454 | 455 | and make sure you have the Xilinx SDK in your PATH, and the riscv-tools/riscv-fesvr submodule initialized in your rocket chip directory. When installing fesvr-zynq, don't forget to copy the library as well (`common/build/libfesvr.so` to `/usr/local/lib` on the board). 456 | 457 | 458 | ### G) Building riscv-tools for Zybo 459 | 460 | The Zybo build was last tested with [this version of the toolchain](https://github.com/ucb-bar/rocket-chip/commit/2f71a3da5a7d41b4aa2c7a617902f2aee8f2cbe1). 461 | 462 | Because the Zybo board uses `ZynqSmallConfig`, [riscv-tools](https://github.com/riscv/riscv-tools) must be recompiled to omit floating point instructions. Add the `--with-arch=RV64IMA` tag to the line in `build.sh` that builds [riscv-gnu-toolchain](https://github.com/riscv/riscv-gnu-toolchain). It should read as follows: 463 | 464 | build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=RV64IMA 465 | 466 | Then run `./build.sh` as normal. 467 | 468 | When testing on spike, run spike with the `--isa=RV64IMA` flag. 469 | 470 | If [pk](https://github.com/riscv/riscv-pk) does not work, make sure it is being built using this version of the toolchain, since it is specifically generated to not have floating point instructions. Also make sure any binaries you want to run on the Zybo are compiled using this toolchain. 471 | 472 | 473 | 474 | 475 | Acknowledgments 476 | --------------- 477 | In addition to those that [contributed](https://github.com/ucb-bar/rocket-chip#contributors) to rocket chip, this repository is based on internal repositories contributed by: 478 | 479 | - Rimas Avizienis 480 | - Jonathan Bachrach 481 | - David Biancolin 482 | - Scott Beamer 483 | - Sagar Karandikar 484 | - Deborah Soung 485 | - Andrew Waterman 486 | 487 | -------------------------------------------------------------------------------- /build.sbt: -------------------------------------------------------------------------------- 1 | lazy val commonSettings = Seq( 2 | organization := "edu.berkeley.cs", 3 | version := "1.0", 4 | scalaVersion := "2.12.4", 5 | traceLevel := 15, 6 | scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), 7 | libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test", 8 | libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3", 9 | libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, 10 | addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), 11 | resolvers ++= Seq( 12 | Resolver.sonatypeRepo("snapshots"), 13 | Resolver.sonatypeRepo("releases"), 14 | Resolver.mavenLocal)) 15 | 16 | lazy val rocketchip = RootProject(file("boom-template/rocket-chip")) 17 | 18 | lazy val boom = (project in file("boom-template/boom")).settings(commonSettings).dependsOn(rocketchip) 19 | 20 | lazy val testchipip = project.settings(commonSettings).dependsOn(rocketchip) 21 | 22 | lazy val root = (project in file(".")).settings(commonSettings).dependsOn(boom, testchipip) 23 | 24 | -------------------------------------------------------------------------------- /common/Makefrag: -------------------------------------------------------------------------------- 1 | # This makefrag is sourced by each board's subdirectory 2 | 3 | JOBS = 16 4 | TEMPLATE_DIR ?= $(base_dir)/boom-template 5 | ROCKET_DIR ?= $(TEMPLATE_DIR)/rocket-chip 6 | TOP_MODULE ?= Top 7 | CFG_PROJECT ?= $(TOP_MODULE_PROJECT) 8 | SCALA_VERSION=2.12.4 9 | SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) 10 | 11 | base_dir = $(abspath ..) 12 | common = $(base_dir)/common 13 | common_build = $(common)/build 14 | testchipip = $(base_dir)/testchipip 15 | output_delivery = deliver_output 16 | SHELL := /bin/bash 17 | 18 | bootrom_img = $(testchipip)/bootrom/bootrom.rv64.img $(testchipip)/bootrom/bootrom.rv32.img 19 | 20 | ifneq ($(BOARD_MODEL),) 21 | insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board_part" "$(BOARD_MODEL)"/g 22 | endif 23 | 24 | proj_name = $(BOARD)_rocketchip_$(CONFIG) 25 | 26 | verilog_srcs = \ 27 | src/verilog/clocking.vh \ 28 | src/verilog/rocketchip_wrapper.v \ 29 | src/verilog/$(TOP_MODULE).$(CONFIG).v \ 30 | src/verilog/AsyncResetReg.v \ 31 | src/verilog/plusarg_reader.v \ 32 | 33 | bootimage = fpga-images-$(BOARD)/boot.bin 34 | ifneq ($(BOARD),zc706_MIG) 35 | bootimage: $(bootimage) 36 | else 37 | default: bitstream 38 | endif 39 | 40 | $(addprefix src/verilog/,AsyncResetReg.v plusarg_reader.v): \ 41 | src/verilog/%.v: \ 42 | $(ROCKET_DIR)/src/main/resources/vsrc/%.v 43 | cp $< $@ 44 | 45 | # Taken from rocket chip 2a5aeea. TODO: Maybe source this directly from makefrag? 46 | SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKET_DIR)/sbt-launch.jar ++$(SCALA_VERSION) 47 | 48 | ROCKET_CLASSES ?= "$(ROCKET_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKET_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" 49 | FIRRTL_JAR ?= $(ROCKET_DIR)/firrtl/utils/bin/firrtl.jar 50 | FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver 51 | 52 | $(FIRRTL_JAR): $(shell find $(ROCKET_DIR)/firrtl/src/main/scala -iname "*.scala" 2> /dev/null) 53 | $(MAKE) -C $(ROCKET_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKET_DIR)/firrtl build-scala 54 | 55 | .PRECIOUS: $(FIRRTL_JAR) 56 | 57 | # Initialize rocket-chip submodule 58 | # ------------------------------------------------------------------------------ 59 | 60 | init-submodules: 61 | cd $(base_dir) && git submodule update --init boom-template testchipip 62 | cd $(TEMPLATE_DIR) && git submodule update --init 63 | cd $(ROCKET_DIR) && git submodule update --init 64 | 65 | # Specialize sources for board 66 | # ------------------------------------------------------------------------------ 67 | ifneq ($(BOARD),zc706_MIG) 68 | src/verilog/rocketchip_wrapper.v: $(common)/rocketchip_wrapper.v 69 | cp $(common)/rocketchip_wrapper.v src/verilog/ 70 | endif 71 | 72 | src/tcl/$(proj_name).tcl: $(common)/zynq_rocketchip.tcl Makefile 73 | sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/PART_NUMBER_HERE/$(PART)/g;$(insert_board);s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \ 74 | $(common)/zynq_rocketchip.tcl > src/tcl/$(proj_name).tcl 75 | 76 | src/tcl/make_bitstream_$(CONFIG).tcl: $(common)/make_bitstream.tcl 77 | sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \ 78 | $(common)/make_bitstream.tcl > src/tcl/make_bitstream_$(CONFIG).tcl 79 | 80 | src/verilog/%.v: $(ROCKET_DIR)/vsrc/%.v 81 | cp $< $@ 82 | 83 | $(ROCKET_DIR)/lib/firrtl.jar: $(FIRRTL_JAR) 84 | mkdir -p $(@D) 85 | cp $< $@ 86 | 87 | FIRRTL_FILE=$(common_build)/$(TOP_MODULE).$(CONFIG).fir 88 | ANNO_FILE=$(common_build)/$(TOP_MODULE).$(CONFIG).anno 89 | VERILOG_FILE=$(common_build)/$(TOP_MODULE).$(CONFIG).v 90 | 91 | PACKAGES=boom-template/rocket-chip boom-template/boom testchipip 92 | SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) 93 | 94 | $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(FIRRTL_JAR) 95 | mkdir -p $(common_build) 96 | cd $(base_dir) && $(SBT) "runMain zynq.Generator $(common_build) \ 97 | $(TOP_MODULE_PROJECT) $(TOP_MODULE) $(CFG_PROJECT) $(CONFIG)" 98 | 99 | .PRECIOUS: $(FIRRTL_FILE) $(ANNO_FILE) 100 | 101 | $(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR) $(bootrom_img) 102 | $(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE) 103 | 104 | src/verilog/$(TOP_MODULE).$(CONFIG).v: $(VERILOG_FILE) 105 | cp $< $@ 106 | 107 | rocket: src/verilog/$(TOP_MODULE).$(CONFIG).v 108 | 109 | # Project generation 110 | # ------------------------------------------------------------------------------ 111 | project = $(proj_name)/$(proj_name).xpr 112 | $(project): src/tcl/$(proj_name).tcl | $(verilog_srcs) 113 | rm -rf $(proj_name) 114 | vivado -mode tcl -source src/tcl/$(proj_name).tcl; 115 | 116 | project: $(project) 117 | 118 | vivado: $(project) 119 | vivado $(project) & 120 | 121 | bitstream = $(proj_name)/$(proj_name).runs/impl_1/rocketchip_wrapper.bit 122 | $(bitstream): src/tcl/make_bitstream_$(CONFIG).tcl $(verilog_srcs) src/constrs/base.xdc | $(project) 123 | vivado -mode tcl -source src/tcl/make_bitstream_$(CONFIG).tcl 124 | 125 | rocketchip_wrapper.bit: $(bitstream) 126 | cp $< $@ 127 | 128 | bitstream: rocketchip_wrapper.bit 129 | 130 | 131 | 132 | # Platform software generation 133 | # ------------------------------------------------------------------------------ 134 | arm_linux_dir = $(base_dir)/common/linux-xlnx 135 | uboot_dir = $(base_dir)/common/u-boot-xlnx 136 | soft_build_dir = soft_build 137 | 138 | arm-linux: arm-uboot # must first build uboot because we need tools 139 | # compile kernel 140 | git submodule update --init $(arm_linux_dir) 141 | # no make clean included here since one copy of linux should work on all boards 142 | cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig 143 | cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS) 144 | # convert zImage to uImage 145 | cd $(arm_linux_dir) && export PATH=$(uboot_dir)/tools:$$PATH && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- UIMAGE_LOADADDR=0x8000 uImage 146 | mkdir -p $(output_delivery) 147 | cp $(arm_linux_dir)/arch/arm/boot/uImage $(output_delivery)/ 148 | 149 | arm-uboot: 150 | # compile board-compatible u-boot 151 | git submodule update --init $(uboot_dir) 152 | # copy relevant configuration files 153 | if [ -a soft_config/boards.cfg ] ; \ 154 | then \ 155 | cp soft_config/boards.cfg $(uboot_dir)/ ; \ 156 | fi; 157 | cp soft_config/zynq_$(UBOOT_CONFIG).h $(uboot_dir)/include/configs/ 158 | # actually build 159 | cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- zynq_$(UBOOT_CONFIG)_config 160 | cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS) 161 | mkdir -p $(soft_build_dir) 162 | cp $(uboot_dir)/u-boot $(soft_build_dir)/u-boot.elf 163 | 164 | arm-dtb: 165 | export PATH=$(arm_linux_dir)/scripts/dtc:$$PATH && dtc -I dts -O dtb -o $(output_delivery)/devicetree.dtb soft_config/$(BOARD)_devicetree.dts 166 | 167 | 168 | 169 | # Handle images and git submodule for prebuilt modules 170 | # ------------------------------------------------------------------------------ 171 | ifneq ($(BOARD),zc706_MIG) 172 | images = fpga-images-$(BOARD)/boot.bif 173 | $(images): 174 | git submodule update --init --depth=1 fpga-images-$(BOARD) 175 | 176 | fetch-images: $(images) 177 | 178 | $(bootimage): $(images) $(bitstream) 179 | ln -sf ../../$(bitstream) fpga-images-$(BOARD)/boot_image/rocketchip_wrapper.bit 180 | cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin 181 | 182 | load-sd: $(images) 183 | $(base_dir)/common/load_card.sh $(SD) 184 | 185 | ramdisk-open: $(images) 186 | mkdir ramdisk 187 | dd if=fpga-images-$(BOARD)/uramdisk.image.gz bs=64 skip=1 | \ 188 | gunzip -c | sudo sh -c 'cd ramdisk/ && cpio -i' 189 | 190 | ramdisk-close: 191 | @if [ ! -d "ramdisk" ]; then \ 192 | echo "No ramdisk to close (use make ramdisk-open first)"; \ 193 | exit 1; \ 194 | fi 195 | sh -c 'cd ramdisk/ && sudo find . | sudo cpio -H newc -o' | gzip -9 > uramdisk.cpio.gz 196 | mkimage -A arm -O linux -T ramdisk -d uramdisk.cpio.gz fpga-images-$(BOARD)/uramdisk.image.gz 197 | rm uramdisk.cpio.gz 198 | @echo "Don't forget to remove ramdisk before opening it again (sudo rm -rf ramdisk)" 199 | 200 | 201 | # Fetch ramdisk for user building from scratch 202 | # ------------------------------------------------------------------------------ 203 | s3_url = https://s3-us-west-1.amazonaws.com/riscv.org/fpga-zynq-files 204 | ramdisk_url = $(s3_url)/uramdisk.image.gz 205 | fetch-ramdisk: 206 | mkdir -p $(output_delivery) 207 | curl $(ramdisk_url) > $(output_delivery)/uramdisk.image.gz 208 | 209 | 210 | # Rebuild from bif for user building from scratch 211 | # ------------------------------------------------------------------------------ 212 | $(output_delivery)/boot.bin: 213 | cd $(output_delivery); bootgen -image output.bif -w -o boot.bin 214 | endif 215 | 216 | # Build riscv-fesvr for zynq 217 | # ------------------------------------------------------------------------------ 218 | 219 | fesvr-main = fesvr-zynq 220 | fesvr-srcs = \ 221 | $(common)/csrc/fesvr_zynq.cc \ 222 | $(common)/csrc/zynq_driver.cc \ 223 | $(testchipip)/csrc/blkdev.cc \ 224 | 225 | fesvr-hdrs = \ 226 | $(common)/csrc/zynq_driver.h \ 227 | $(testchipip)/csrc/blkdev.h \ 228 | 229 | fesvr-lib = $(common_build)/libfesvr.so 230 | 231 | CXX_FPGA = arm-xilinx-linux-gnueabi-g++ 232 | CXXFLAGS_FPGA = -O2 -std=c++11 -Wall -L$(common_build) -lfesvr \ 233 | -Wl,-rpath,/usr/local/lib \ 234 | -I $(common)/csrc -I $(testchipip)/csrc \ 235 | -I $(ROCKET_DIR)/riscv-tools/riscv-fesvr/ \ 236 | -Wl,-rpath,/usr/local/lib \ 237 | 238 | $(fesvr-lib): 239 | mkdir -p $(common_build) 240 | cd $(common_build) && \ 241 | $(ROCKET_DIR)/riscv-tools/riscv-fesvr/configure \ 242 | --host=arm-xilinx-linux-gnueabi && \ 243 | make libfesvr.so 244 | 245 | $(common_build)/$(fesvr-main): $(fesvr-lib) $(fesvr-srcs) $(fesvr-hdrs) 246 | $(CXX_FPGA) $(CXXFLAGS_FPGA) -o $(common_build)/$(fesvr-main) $(fesvr-srcs) 247 | 248 | fesvr-zynq: $(common_build)/$(fesvr-main) 249 | 250 | # Fetch pre-built risc-v linux binary and root fs from S3 251 | # ------------------------------------------------------------------------------ 252 | 253 | riscv_root_bin = $(s3_url)/root.bin 254 | ifeq ($(BOARD), zybo) 255 | riscv_vmlinux = $(s3_url)/vmlinux_nofpu 256 | else 257 | riscv_vmlinux = $(s3_url)/vmlinux 258 | endif 259 | sd_riscv = fpga-images-$(BOARD)/riscv 260 | sd_riscv_scratch = $(output_delivery)/riscv 261 | 262 | fetch-riscv-linux: 263 | mkdir -p $(sd_riscv) 264 | curl $(riscv_root_bin) > $(sd_riscv)/root.bin 265 | curl $(riscv_vmlinux) > $(sd_riscv)/vmlinux 266 | 267 | fetch-riscv-linux-deliver: 268 | mkdir -p $(sd_riscv_scratch) 269 | curl $(riscv_root_bin) > $(sd_riscv_scratch)/root.bin 270 | curl $(riscv_vmlinux) > $(sd_riscv_scratch)/vmlinux 271 | 272 | clean: 273 | rm -f *.log *.jou *.str 274 | rm -rf csrc simv-* output ucli.key vc_hdrs.h DVEfiles 275 | 276 | .PHONY: vivado project init-submodules rocket fesvr-zynq fetch-images load-sd ramdisk-open ramdisk-close clean 277 | -------------------------------------------------------------------------------- /common/csrc/fesvr_zynq.cc: -------------------------------------------------------------------------------- 1 | #include "zynq_driver.h" 2 | #include "fesvr/tsi.h" 3 | #include 4 | 5 | #define BLKDEV_NTAGS 2 6 | 7 | int main(int argc, char** argv) 8 | { 9 | tsi_t tsi(argc, argv); 10 | 11 | BlockDevice *blkdev = NULL; 12 | zynq_driver_t *driver; 13 | 14 | for (int i = 1; i < argc; i++) { 15 | const char *name = NULL; 16 | 17 | if (strncmp(argv[i], "+blkdev=", 8) == 0) { 18 | name = argv[i] + 8; 19 | blkdev = new BlockDevice(name, BLKDEV_NTAGS); 20 | } 21 | } 22 | 23 | driver = new zynq_driver_t(&tsi, blkdev); 24 | 25 | while(!tsi.done()){ 26 | driver->poll(); 27 | } 28 | 29 | delete driver; 30 | if (blkdev != NULL) 31 | delete blkdev; 32 | 33 | return tsi.exit_code(); 34 | } 35 | -------------------------------------------------------------------------------- /common/csrc/zynq_driver.cc: -------------------------------------------------------------------------------- 1 | #include "zynq_driver.h" 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #define ZYNQ_BASE_PADDR 0x43C00000L 9 | 10 | #define TSI_OUT_FIFO_DATA 0x00 11 | #define TSI_OUT_FIFO_COUNT 0x04 12 | #define TSI_IN_FIFO_DATA 0x08 13 | #define TSI_IN_FIFO_COUNT 0x0C 14 | #define SYSTEM_RESET 0x10 15 | #define BLKDEV_REQ_FIFO_DATA 0x20 16 | #define BLKDEV_REQ_FIFO_COUNT 0x24 17 | #define BLKDEV_DATA_FIFO_DATA 0x28 18 | #define BLKDEV_DATA_FIFO_COUNT 0x2C 19 | #define BLKDEV_RESP_FIFO_DATA 0x30 20 | #define BLKDEV_RESP_FIFO_COUNT 0x34 21 | #define BLKDEV_NSECTORS 0x38 22 | #define BLKDEV_MAX_REQUEST_LENGTH 0x3C 23 | #define NET_OUT_FIFO_DATA 0x40 24 | #define NET_OUT_FIFO_COUNT 0x44 25 | #define NET_IN_FIFO_DATA 0x48 26 | #define NET_IN_FIFO_COUNT 0x4C 27 | #define NET_MACADDR_LO 0x50 28 | #define NET_MACADDR_HI 0x54 29 | 30 | #define BLKDEV_REQ_NWORDS 3 31 | #define BLKDEV_DATA_NWORDS 3 32 | #define NET_FLIT_NWORDS 3 33 | 34 | zynq_driver_t::zynq_driver_t(tsi_t *tsi, BlockDevice *bdev) 35 | { 36 | this->tsi = tsi; 37 | this->bdev = bdev; 38 | 39 | fd = open("/dev/mem", O_RDWR|O_SYNC); 40 | assert(fd != -1); 41 | dev = (uint8_t *) mmap( 42 | 0, sysconf(_SC_PAGESIZE), 43 | PROT_READ|PROT_WRITE, MAP_SHARED, fd, ZYNQ_BASE_PADDR); 44 | assert(dev != MAP_FAILED); 45 | 46 | // reset the target 47 | write(SYSTEM_RESET, 1); 48 | write(SYSTEM_RESET, 0); 49 | 50 | // set nsectors and max_request_length 51 | if (bdev == NULL) { 52 | write(BLKDEV_NSECTORS, 0); 53 | write(BLKDEV_MAX_REQUEST_LENGTH, 0); 54 | } else { 55 | write(BLKDEV_NSECTORS, bdev->nsectors()); 56 | write(BLKDEV_MAX_REQUEST_LENGTH, bdev->max_request_length()); 57 | } 58 | } 59 | 60 | zynq_driver_t::~zynq_driver_t() 61 | { 62 | munmap(dev, sysconf(_SC_PAGESIZE)); 63 | close(fd); 64 | } 65 | 66 | uint32_t zynq_driver_t::read(int off) 67 | { 68 | volatile uint32_t *ptr = (volatile uint32_t *) (this->dev + off); 69 | return *ptr; 70 | } 71 | 72 | void zynq_driver_t::write(int off, uint32_t word) 73 | { 74 | volatile uint32_t *ptr = (volatile uint32_t *) (this->dev + off); 75 | *ptr = word; 76 | } 77 | 78 | struct blkdev_request zynq_driver_t::read_blkdev_request() 79 | { 80 | uint32_t word; 81 | struct blkdev_request req; 82 | 83 | // tag + write 84 | word = read(BLKDEV_REQ_FIFO_DATA); 85 | req.write = word & 0x1; 86 | req.tag = word >> 1; 87 | // offset, then len 88 | req.offset = read(BLKDEV_REQ_FIFO_DATA); 89 | req.len = read(BLKDEV_REQ_FIFO_DATA); 90 | 91 | return req; 92 | } 93 | 94 | struct blkdev_data zynq_driver_t::read_blkdev_req_data() 95 | { 96 | struct blkdev_data data; 97 | 98 | data.tag = read(BLKDEV_DATA_FIFO_DATA); 99 | data.data = read(BLKDEV_DATA_FIFO_DATA) & 0xffffffffU; 100 | data.data |= ((uint64_t) read(BLKDEV_DATA_FIFO_DATA)) << 32; 101 | 102 | return data; 103 | } 104 | 105 | void zynq_driver_t::write_blkdev_response(struct blkdev_data &resp) 106 | { 107 | write(BLKDEV_RESP_FIFO_DATA, resp.tag); 108 | write(BLKDEV_RESP_FIFO_DATA, resp.data & 0xffffffffU); 109 | write(BLKDEV_RESP_FIFO_DATA, resp.data >> 32); 110 | } 111 | 112 | void zynq_driver_t::poll(void) 113 | { 114 | if (tsi != NULL) { 115 | while (read(TSI_OUT_FIFO_COUNT) > 0) { 116 | uint32_t out_data = read(TSI_OUT_FIFO_DATA); 117 | tsi->send_word(out_data); 118 | } 119 | 120 | while (tsi->data_available() && read(TSI_IN_FIFO_COUNT) > 0) { 121 | uint32_t in_data = tsi->recv_word(); 122 | write(TSI_IN_FIFO_DATA, in_data); 123 | } 124 | 125 | tsi->switch_to_host(); 126 | } 127 | 128 | if (bdev != NULL) { 129 | while (read(BLKDEV_REQ_FIFO_COUNT) >= BLKDEV_REQ_NWORDS) { 130 | struct blkdev_request req = read_blkdev_request(); 131 | bdev->send_request(req); 132 | } 133 | 134 | while (read(BLKDEV_DATA_FIFO_COUNT) >= BLKDEV_DATA_NWORDS) { 135 | struct blkdev_data data = read_blkdev_req_data(); 136 | bdev->send_data(data); 137 | } 138 | 139 | while (bdev->resp_valid() && read(BLKDEV_RESP_FIFO_COUNT) >= BLKDEV_DATA_NWORDS) { 140 | struct blkdev_data resp = bdev->recv_response(); 141 | write_blkdev_response(resp); 142 | } 143 | 144 | bdev->switch_to_host(); 145 | } 146 | } 147 | -------------------------------------------------------------------------------- /common/csrc/zynq_driver.h: -------------------------------------------------------------------------------- 1 | #ifndef __ZYNQ_DRIVER_H 2 | #define __ZYNQ_DRIVER_H 3 | 4 | #include "fesvr/tsi.h" 5 | #include "blkdev.h" 6 | #include 7 | 8 | class zynq_driver_t { 9 | public: 10 | zynq_driver_t(tsi_t *tsi, BlockDevice *bdev); 11 | ~zynq_driver_t(); 12 | 13 | void poll(void); 14 | 15 | private: 16 | uint8_t *dev; 17 | int fd; 18 | tsi_t *tsi; 19 | BlockDevice *bdev; 20 | 21 | protected: 22 | uint32_t read(int off); 23 | void write(int off, uint32_t word); 24 | struct blkdev_request read_blkdev_request(); 25 | struct blkdev_data read_blkdev_req_data(); 26 | void write_blkdev_response(struct blkdev_data &resp); 27 | struct network_flit read_net_out(); 28 | void write_net_in(struct network_flit &flt); 29 | void write_macaddr(uint64_t macaddr); 30 | }; 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /common/load_card.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | if [ -z "$1" ] 4 | then 5 | echo "Please provide a path to a SD card" 6 | exit 1 7 | fi 8 | 9 | fpga_images_dir=`ls -d fpga-images-*` 10 | 11 | set -x 12 | cp $fpga_images_dir/boot.bin $1 13 | cp $fpga_images_dir/devicetree.dtb $1 14 | cp $fpga_images_dir/uImage $1 15 | cp $fpga_images_dir/uramdisk.image.gz $1 16 | # if user downloaded riscv-linux, copy that over also 17 | if [ -a $fpga_images_dir/riscv/vmlinux ] 18 | then 19 | mkdir -p $1/riscv 20 | cp $fpga_images_dir/riscv/vmlinux $1/riscv/ 21 | cp $fpga_images_dir/riscv/root.bin $1/riscv/ 22 | fi 23 | -------------------------------------------------------------------------------- /common/make_bitstream.tcl: -------------------------------------------------------------------------------- 1 | open_project BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE/BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE.xpr 2 | reset_run synth_1 3 | reset_run impl_1 4 | launch_runs synth_1 5 | wait_on_run synth_1 6 | launch_runs impl_1 -to_step write_bitstream 7 | wait_on_run impl_1 8 | exit 9 | -------------------------------------------------------------------------------- /common/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=0.13.15 2 | -------------------------------------------------------------------------------- /common/project/build.scala: -------------------------------------------------------------------------------- 1 | import sbt._ 2 | import Keys._ 3 | 4 | object BuildSettings extends Build { 5 | override lazy val settings = super.settings ++ Seq( 6 | organization := "berkeley", 7 | version := "1.2", 8 | scalaVersion := "2.11.12", 9 | parallelExecution in Global := false, 10 | traceLevel := 15, 11 | scalacOptions ++= Seq("-deprecation","-unchecked") 12 | ) 13 | lazy val zynq = (project in file(".")) 14 | } 15 | -------------------------------------------------------------------------------- /common/rocketchip_wrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | `include "clocking.vh" 3 | 4 | module rocketchip_wrapper 5 | (DDR_addr, 6 | DDR_ba, 7 | DDR_cas_n, 8 | DDR_ck_n, 9 | DDR_ck_p, 10 | DDR_cke, 11 | DDR_cs_n, 12 | DDR_dm, 13 | DDR_dq, 14 | DDR_dqs_n, 15 | DDR_dqs_p, 16 | DDR_odt, 17 | DDR_ras_n, 18 | DDR_reset_n, 19 | DDR_we_n, 20 | FIXED_IO_ddr_vrn, 21 | FIXED_IO_ddr_vrp, 22 | FIXED_IO_mio, 23 | FIXED_IO_ps_clk, 24 | FIXED_IO_ps_porb, 25 | FIXED_IO_ps_srstb, 26 | `ifndef differential_clock 27 | clk); 28 | `else 29 | SYSCLK_P, 30 | SYSCLK_N); 31 | `endif 32 | 33 | inout [14:0]DDR_addr; 34 | inout [2:0]DDR_ba; 35 | inout DDR_cas_n; 36 | inout DDR_ck_n; 37 | inout DDR_ck_p; 38 | inout DDR_cke; 39 | inout DDR_cs_n; 40 | inout [3:0]DDR_dm; 41 | inout [31:0]DDR_dq; 42 | inout [3:0]DDR_dqs_n; 43 | inout [3:0]DDR_dqs_p; 44 | inout DDR_odt; 45 | inout DDR_ras_n; 46 | inout DDR_reset_n; 47 | inout DDR_we_n; 48 | 49 | inout FIXED_IO_ddr_vrn; 50 | inout FIXED_IO_ddr_vrp; 51 | inout [53:0]FIXED_IO_mio; 52 | inout FIXED_IO_ps_clk; 53 | inout FIXED_IO_ps_porb; 54 | inout FIXED_IO_ps_srstb; 55 | 56 | `ifndef differential_clock 57 | input clk; 58 | `else 59 | input SYSCLK_P; 60 | input SYSCLK_N; 61 | `endif 62 | 63 | wire FCLK_RESET0_N; 64 | 65 | wire [31:0]M_AXI_araddr; 66 | wire [1:0]M_AXI_arburst; 67 | wire [7:0]M_AXI_arlen; 68 | wire M_AXI_arready; 69 | wire [2:0]M_AXI_arsize; 70 | wire M_AXI_arvalid; 71 | wire [31:0]M_AXI_awaddr; 72 | wire [1:0]M_AXI_awburst; 73 | wire [7:0]M_AXI_awlen; 74 | wire [3:0]M_AXI_wstrb; 75 | wire M_AXI_awready; 76 | wire [2:0]M_AXI_awsize; 77 | wire M_AXI_awvalid; 78 | wire M_AXI_bready; 79 | wire M_AXI_bvalid; 80 | wire [1:0] M_AXI_bresp; 81 | wire [31:0]M_AXI_rdata; 82 | wire M_AXI_rlast; 83 | wire M_AXI_rready; 84 | wire M_AXI_rvalid; 85 | wire [1:0] M_AXI_rresp; 86 | wire [31:0]M_AXI_wdata; 87 | wire M_AXI_wlast; 88 | wire M_AXI_wready; 89 | wire M_AXI_wvalid; 90 | wire [11:0] M_AXI_arid, M_AXI_awid; // outputs from ARM core 91 | wire [11:0] M_AXI_bid, M_AXI_rid; // inputs to ARM core 92 | 93 | wire S_AXI_arready; 94 | wire S_AXI_arvalid; 95 | wire [31:0] S_AXI_araddr; 96 | wire [5:0] S_AXI_arid; 97 | wire [2:0] S_AXI_arsize; 98 | wire [7:0] S_AXI_arlen; 99 | wire [1:0] S_AXI_arburst; 100 | wire S_AXI_arlock; 101 | wire [3:0] S_AXI_arcache; 102 | wire [2:0] S_AXI_arprot; 103 | wire [3:0] S_AXI_arqos; 104 | //wire [3:0] S_AXI_arregion; 105 | 106 | wire S_AXI_awready; 107 | wire S_AXI_awvalid; 108 | wire [31:0] S_AXI_awaddr; 109 | wire [5:0] S_AXI_awid; 110 | wire [2:0] S_AXI_awsize; 111 | wire [7:0] S_AXI_awlen; 112 | wire [1:0] S_AXI_awburst; 113 | wire S_AXI_awlock; 114 | wire [3:0] S_AXI_awcache; 115 | wire [2:0] S_AXI_awprot; 116 | wire [3:0] S_AXI_awqos; 117 | //wire [3:0] S_AXI_awregion; 118 | 119 | wire S_AXI_wready; 120 | wire S_AXI_wvalid; 121 | wire [7:0] S_AXI_wstrb; 122 | wire [63:0] S_AXI_wdata; 123 | wire S_AXI_wlast; 124 | 125 | wire S_AXI_bready; 126 | wire S_AXI_bvalid; 127 | wire [1:0] S_AXI_bresp; 128 | wire [5:0] S_AXI_bid; 129 | 130 | wire S_AXI_rready; 131 | wire S_AXI_rvalid; 132 | wire [1:0] S_AXI_rresp; 133 | wire [5:0] S_AXI_rid; 134 | wire [63:0] S_AXI_rdata; 135 | wire S_AXI_rlast; 136 | 137 | wire reset, reset_cpu; 138 | wire host_clk; 139 | wire gclk_i, gclk_fbout, host_clk_i, mmcm_locked; 140 | 141 | system system_i 142 | (.DDR_addr(DDR_addr), 143 | .DDR_ba(DDR_ba), 144 | .DDR_cas_n(DDR_cas_n), 145 | .DDR_ck_n(DDR_ck_n), 146 | .DDR_ck_p(DDR_ck_p), 147 | .DDR_cke(DDR_cke), 148 | .DDR_cs_n(DDR_cs_n), 149 | .DDR_dm(DDR_dm), 150 | .DDR_dq(DDR_dq), 151 | .DDR_dqs_n(DDR_dqs_n), 152 | .DDR_dqs_p(DDR_dqs_p), 153 | .DDR_odt(DDR_odt), 154 | .DDR_ras_n(DDR_ras_n), 155 | .DDR_reset_n(DDR_reset_n), 156 | .DDR_we_n(DDR_we_n), 157 | .FCLK_RESET0_N(FCLK_RESET0_N), 158 | .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), 159 | .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), 160 | .FIXED_IO_mio(FIXED_IO_mio), 161 | .FIXED_IO_ps_clk(FIXED_IO_ps_clk), 162 | .FIXED_IO_ps_porb(FIXED_IO_ps_porb), 163 | .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), 164 | // master AXI interface (zynq = master, fpga = slave) 165 | .M_AXI_araddr(M_AXI_araddr), 166 | .M_AXI_arburst(M_AXI_arburst), // burst type 167 | .M_AXI_arcache(), 168 | .M_AXI_arid(M_AXI_arid), 169 | .M_AXI_arlen(M_AXI_arlen), // burst length (#transfers) 170 | .M_AXI_arlock(), 171 | .M_AXI_arprot(), 172 | .M_AXI_arqos(), 173 | .M_AXI_arready(M_AXI_arready), 174 | .M_AXI_arregion(), 175 | .M_AXI_arsize(M_AXI_arsize), // burst size (bits/transfer) 176 | .M_AXI_arvalid(M_AXI_arvalid), 177 | // 178 | .M_AXI_awaddr(M_AXI_awaddr), 179 | .M_AXI_awburst(M_AXI_awburst), 180 | .M_AXI_awcache(), 181 | .M_AXI_awid(M_AXI_awid), 182 | .M_AXI_awlen(M_AXI_awlen), 183 | .M_AXI_awlock(), 184 | .M_AXI_awprot(), 185 | .M_AXI_awqos(), 186 | .M_AXI_awready(M_AXI_awready), 187 | .M_AXI_awregion(), 188 | .M_AXI_awsize(M_AXI_awsize), 189 | .M_AXI_awvalid(M_AXI_awvalid), 190 | // 191 | .M_AXI_bid(M_AXI_bid), 192 | .M_AXI_bready(M_AXI_bready), 193 | .M_AXI_bresp(M_AXI_bresp), 194 | .M_AXI_bvalid(M_AXI_bvalid), 195 | // 196 | .M_AXI_rdata(M_AXI_rdata), 197 | .M_AXI_rid(M_AXI_rid), 198 | .M_AXI_rlast(M_AXI_rlast), 199 | .M_AXI_rready(M_AXI_rready), 200 | .M_AXI_rresp(M_AXI_rresp), 201 | .M_AXI_rvalid(M_AXI_rvalid), 202 | // 203 | .M_AXI_wdata(M_AXI_wdata), 204 | .M_AXI_wlast(M_AXI_wlast), 205 | .M_AXI_wready(M_AXI_wready), 206 | .M_AXI_wstrb(M_AXI_wstrb), 207 | .M_AXI_wvalid(M_AXI_wvalid), 208 | 209 | // slave AXI interface (fpga = master, zynq = slave) 210 | // connected directly to DDR controller to handle test chip mem 211 | .S_AXI_araddr(S_AXI_araddr), 212 | .S_AXI_arburst(S_AXI_arburst), 213 | .S_AXI_arcache(S_AXI_arcache), 214 | .S_AXI_arid(S_AXI_arid), 215 | .S_AXI_arlen(S_AXI_arlen), 216 | .S_AXI_arlock(S_AXI_arlock), 217 | .S_AXI_arprot(S_AXI_arprot), 218 | .S_AXI_arqos(S_AXI_arqos), 219 | .S_AXI_arready(S_AXI_arready), 220 | .S_AXI_arregion(4'b0), 221 | .S_AXI_arsize(S_AXI_arsize), 222 | .S_AXI_arvalid(S_AXI_arvalid), 223 | // 224 | .S_AXI_awaddr(S_AXI_awaddr), 225 | .S_AXI_awburst(S_AXI_awburst), 226 | .S_AXI_awcache(S_AXI_awcache), 227 | .S_AXI_awid(S_AXI_awid), 228 | .S_AXI_awlen(S_AXI_awlen), 229 | .S_AXI_awlock(S_AXI_awlock), 230 | .S_AXI_awprot(S_AXI_awprot), 231 | .S_AXI_awqos(S_AXI_awqos), 232 | .S_AXI_awready(S_AXI_awready), 233 | .S_AXI_awregion(4'b0), 234 | .S_AXI_awsize(S_AXI_awsize), 235 | .S_AXI_awvalid(S_AXI_awvalid), 236 | // 237 | .S_AXI_bid(S_AXI_bid), 238 | .S_AXI_bready(S_AXI_bready), 239 | .S_AXI_bresp(S_AXI_bresp), 240 | .S_AXI_bvalid(S_AXI_bvalid), 241 | // 242 | .S_AXI_rid(S_AXI_rid), 243 | .S_AXI_rdata(S_AXI_rdata), 244 | .S_AXI_rlast(S_AXI_rlast), 245 | .S_AXI_rready(S_AXI_rready), 246 | .S_AXI_rresp(S_AXI_rresp), 247 | .S_AXI_rvalid(S_AXI_rvalid), 248 | // 249 | .S_AXI_wdata(S_AXI_wdata), 250 | .S_AXI_wlast(S_AXI_wlast), 251 | .S_AXI_wready(S_AXI_wready), 252 | .S_AXI_wstrb(S_AXI_wstrb), 253 | .S_AXI_wvalid(S_AXI_wvalid), 254 | .ext_clk_in(host_clk) 255 | ); 256 | 257 | assign reset = !FCLK_RESET0_N || !mmcm_locked; 258 | 259 | wire [31:0] mem_araddr; 260 | wire [31:0] mem_awaddr; 261 | 262 | // Memory given to Rocket is the upper 256 MB of the 512 MB DRAM 263 | assign S_AXI_araddr = {4'd1, mem_araddr[27:0]}; 264 | assign S_AXI_awaddr = {4'd1, mem_awaddr[27:0]}; 265 | 266 | Top top( 267 | .clock(host_clk), 268 | .reset(reset), 269 | 270 | .io_ps_axi_slave_aw_ready (M_AXI_awready), 271 | .io_ps_axi_slave_aw_valid (M_AXI_awvalid), 272 | .io_ps_axi_slave_aw_bits_addr (M_AXI_awaddr), 273 | .io_ps_axi_slave_aw_bits_len (M_AXI_awlen), 274 | .io_ps_axi_slave_aw_bits_size (M_AXI_awsize), 275 | .io_ps_axi_slave_aw_bits_burst (M_AXI_awburst), 276 | .io_ps_axi_slave_aw_bits_id (M_AXI_awid), 277 | .io_ps_axi_slave_aw_bits_lock (1'b0), 278 | .io_ps_axi_slave_aw_bits_cache (4'b0), 279 | .io_ps_axi_slave_aw_bits_prot (3'b0), 280 | .io_ps_axi_slave_aw_bits_qos (4'b0), 281 | 282 | .io_ps_axi_slave_ar_ready (M_AXI_arready), 283 | .io_ps_axi_slave_ar_valid (M_AXI_arvalid), 284 | .io_ps_axi_slave_ar_bits_addr (M_AXI_araddr), 285 | .io_ps_axi_slave_ar_bits_len (M_AXI_arlen), 286 | .io_ps_axi_slave_ar_bits_size (M_AXI_arsize), 287 | .io_ps_axi_slave_ar_bits_burst (M_AXI_arburst), 288 | .io_ps_axi_slave_ar_bits_id (M_AXI_arid), 289 | .io_ps_axi_slave_ar_bits_lock (1'b0), 290 | .io_ps_axi_slave_ar_bits_cache (4'b0), 291 | .io_ps_axi_slave_ar_bits_prot (3'b0), 292 | .io_ps_axi_slave_ar_bits_qos (4'b0), 293 | 294 | .io_ps_axi_slave_w_valid (M_AXI_wvalid), 295 | .io_ps_axi_slave_w_ready (M_AXI_wready), 296 | .io_ps_axi_slave_w_bits_data (M_AXI_wdata), 297 | .io_ps_axi_slave_w_bits_strb (M_AXI_wstrb), 298 | .io_ps_axi_slave_w_bits_last (M_AXI_wlast), 299 | 300 | .io_ps_axi_slave_r_valid (M_AXI_rvalid), 301 | .io_ps_axi_slave_r_ready (M_AXI_rready), 302 | .io_ps_axi_slave_r_bits_id (M_AXI_rid), 303 | .io_ps_axi_slave_r_bits_resp (M_AXI_rresp), 304 | .io_ps_axi_slave_r_bits_data (M_AXI_rdata), 305 | .io_ps_axi_slave_r_bits_last (M_AXI_rlast), 306 | 307 | .io_ps_axi_slave_b_valid (M_AXI_bvalid), 308 | .io_ps_axi_slave_b_ready (M_AXI_bready), 309 | .io_ps_axi_slave_b_bits_id (M_AXI_bid), 310 | .io_ps_axi_slave_b_bits_resp (M_AXI_bresp), 311 | 312 | .io_mem_axi_ar_valid (S_AXI_arvalid), 313 | .io_mem_axi_ar_ready (S_AXI_arready), 314 | .io_mem_axi_ar_bits_addr (mem_araddr), 315 | .io_mem_axi_ar_bits_id (S_AXI_arid), 316 | .io_mem_axi_ar_bits_size (S_AXI_arsize), 317 | .io_mem_axi_ar_bits_len (S_AXI_arlen), 318 | .io_mem_axi_ar_bits_burst (S_AXI_arburst), 319 | .io_mem_axi_ar_bits_cache (S_AXI_arcache), 320 | .io_mem_axi_ar_bits_lock (S_AXI_arlock), 321 | .io_mem_axi_ar_bits_prot (S_AXI_arprot), 322 | .io_mem_axi_ar_bits_qos (S_AXI_arqos), 323 | .io_mem_axi_aw_valid (S_AXI_awvalid), 324 | .io_mem_axi_aw_ready (S_AXI_awready), 325 | .io_mem_axi_aw_bits_addr (mem_awaddr), 326 | .io_mem_axi_aw_bits_id (S_AXI_awid), 327 | .io_mem_axi_aw_bits_size (S_AXI_awsize), 328 | .io_mem_axi_aw_bits_len (S_AXI_awlen), 329 | .io_mem_axi_aw_bits_burst (S_AXI_awburst), 330 | .io_mem_axi_aw_bits_cache (S_AXI_awcache), 331 | .io_mem_axi_aw_bits_lock (S_AXI_awlock), 332 | .io_mem_axi_aw_bits_prot (S_AXI_awprot), 333 | .io_mem_axi_aw_bits_qos (S_AXI_awqos), 334 | .io_mem_axi_w_valid (S_AXI_wvalid), 335 | .io_mem_axi_w_ready (S_AXI_wready), 336 | .io_mem_axi_w_bits_strb (S_AXI_wstrb), 337 | .io_mem_axi_w_bits_data (S_AXI_wdata), 338 | .io_mem_axi_w_bits_last (S_AXI_wlast), 339 | .io_mem_axi_b_valid (S_AXI_bvalid), 340 | .io_mem_axi_b_ready (S_AXI_bready), 341 | .io_mem_axi_b_bits_resp (S_AXI_bresp), 342 | .io_mem_axi_b_bits_id (S_AXI_bid), 343 | .io_mem_axi_r_valid (S_AXI_rvalid), 344 | .io_mem_axi_r_ready (S_AXI_rready), 345 | .io_mem_axi_r_bits_resp (S_AXI_rresp), 346 | .io_mem_axi_r_bits_id (S_AXI_rid), 347 | .io_mem_axi_r_bits_data (S_AXI_rdata), 348 | .io_mem_axi_r_bits_last (S_AXI_rlast) 349 | ); 350 | `ifndef differential_clock 351 | IBUFG ibufg_gclk (.I(clk), .O(gclk_i)); 352 | `else 353 | IBUFDS #(.DIFF_TERM("TRUE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) clk_ibufds (.O(gclk_i), .I(SYSCLK_P), .IB(SYSCLK_N)); 354 | `endif 355 | BUFG bufg_host_clk (.I(host_clk_i), .O(host_clk)); 356 | 357 | MMCME2_BASE #( 358 | .BANDWIDTH("OPTIMIZED"), 359 | .CLKFBOUT_MULT_F(`RC_CLK_MULT), 360 | .CLKFBOUT_PHASE(0.0), 361 | .CLKIN1_PERIOD(`ZYNQ_CLK_PERIOD), 362 | .CLKOUT1_DIVIDE(1), 363 | .CLKOUT2_DIVIDE(1), 364 | .CLKOUT3_DIVIDE(1), 365 | .CLKOUT4_DIVIDE(1), 366 | .CLKOUT5_DIVIDE(1), 367 | .CLKOUT6_DIVIDE(1), 368 | .CLKOUT0_DIVIDE_F(`RC_CLK_DIVIDE), 369 | .CLKOUT0_DUTY_CYCLE(0.5), 370 | .CLKOUT1_DUTY_CYCLE(0.5), 371 | .CLKOUT2_DUTY_CYCLE(0.5), 372 | .CLKOUT3_DUTY_CYCLE(0.5), 373 | .CLKOUT4_DUTY_CYCLE(0.5), 374 | .CLKOUT5_DUTY_CYCLE(0.5), 375 | .CLKOUT6_DUTY_CYCLE(0.5), 376 | .CLKOUT0_PHASE(0.0), 377 | .CLKOUT1_PHASE(0.0), 378 | .CLKOUT2_PHASE(0.0), 379 | .CLKOUT3_PHASE(0.0), 380 | .CLKOUT4_PHASE(0.0), 381 | .CLKOUT5_PHASE(0.0), 382 | .CLKOUT6_PHASE(0.0), 383 | .CLKOUT4_CASCADE("FALSE"), 384 | .DIVCLK_DIVIDE(1), 385 | .REF_JITTER1(0.0), 386 | .STARTUP_WAIT("FALSE") 387 | ) MMCME2_BASE_inst ( 388 | .CLKOUT0(host_clk_i), 389 | .CLKOUT0B(), 390 | .CLKOUT1(), 391 | .CLKOUT1B(), 392 | .CLKOUT2(), 393 | .CLKOUT2B(), 394 | .CLKOUT3(), 395 | .CLKOUT3B(), 396 | .CLKOUT4(), 397 | .CLKOUT5(), 398 | .CLKOUT6(), 399 | .CLKFBOUT(gclk_fbout), 400 | .CLKFBOUTB(), 401 | .LOCKED(mmcm_locked), 402 | .CLKIN1(gclk_i), 403 | .PWRDWN(1'b0), 404 | .RST(1'b0), 405 | .CLKFBIN(gclk_fbout)); 406 | 407 | endmodule 408 | -------------------------------------------------------------------------------- /common/scripts/upgrade_version.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | # Argument 1: old vivado version sourceme 4 | # Argument 2: new vivado version sourceme 5 | 6 | # Run this in the directory of the board you'd like to upgrade 7 | project=$(basename $(pwd)) 8 | source $1 9 | make project 10 | 11 | cp src/tcl/${project}_bd.tcl src/tcl/${project}_bd.tcl.bak 12 | 13 | source $2 14 | vivado -mode batch -source ../common/scripts/upgrade_version.tcl -tclargs */*.xpr src/tcl/${project}_bd.tcl 15 | -------------------------------------------------------------------------------- /common/scripts/upgrade_version.tcl: -------------------------------------------------------------------------------- 1 | open_project [lindex $argv 0] 2 | #update_compile_order -fileset sources_1 3 | export_ip_user_files -of_objects [get_ips -all] -no_script -reset -quiet 4 | upgrade_ip [get_ips -all] -log ip_upgrade.log 5 | validate_bd_design 6 | write_bd_tcl -force [lindex $argv 1] 7 | -------------------------------------------------------------------------------- /common/src/main/scala/BOOM.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | package boom 3 | 4 | import chisel3._ 5 | import freechips.rocketchip.config.{Parameters, Field} 6 | import freechips.rocketchip.devices.tilelink._ 7 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8 | import freechips.rocketchip.subsystem._ 9 | import freechips.rocketchip.util.DontTouch 10 | import freechips.rocketchip.config.Config 11 | import testchipip._ 12 | import _root_.boom.system.{BoomSubsystem, BoomSubsystemModule} 13 | 14 | class TestHarness(implicit val p: Parameters) extends Module { 15 | val io = IO(new Bundle { 16 | val success = Output(Bool()) 17 | }) 18 | 19 | val driver = Module(LazyModule(new TestHarnessDriver).module) 20 | val dut = Module(LazyModule(new FPGAZynqTop).module) 21 | 22 | dut.reset := driver.io.sys_reset 23 | dut.debug := DontCare 24 | dut.tieOffInterrupts() 25 | dut.dontTouchPorts() 26 | dut.connectSimAXIMem() 27 | 28 | driver.io.serial <> dut.serial 29 | driver.io.bdev <> dut.bdev 30 | io.success := driver.io.success 31 | } 32 | 33 | class Top(implicit val p: Parameters) extends Module { 34 | val address = p(ZynqAdapterBase) 35 | val config = p(ExtIn).get 36 | val target = Module(LazyModule(new FPGAZynqTop).module) 37 | val adapter = Module(LazyModule(new ZynqAdapter(address, config)).module) 38 | 39 | require(target.mem_axi4.size == 1) 40 | 41 | val io = IO(new Bundle { 42 | val ps_axi_slave = Flipped(adapter.axi.cloneType) 43 | val mem_axi = target.mem_axi4.head.cloneType 44 | }) 45 | 46 | io.mem_axi <> target.mem_axi4.head 47 | adapter.axi <> io.ps_axi_slave 48 | adapter.io.serial <> target.serial 49 | adapter.io.bdev <> target.bdev 50 | 51 | target.debug := DontCare 52 | target.tieOffInterrupts() 53 | target.dontTouchPorts() 54 | target.reset := adapter.io.sys_reset 55 | } 56 | 57 | class FPGAZynqTop(implicit p: Parameters) extends BoomSubsystem 58 | with CanHaveMasterAXI4MemPort 59 | // with HasSystemErrorSlave 60 | with HasPeripheryBootROM 61 | with HasSyncExtInterrupts 62 | with HasNoDebug 63 | with HasPeripherySerial 64 | with HasPeripheryBlockDevice { 65 | override lazy val module = new FPGAZynqTopModule(this) 66 | } 67 | 68 | class FPGAZynqTopModule(outer: FPGAZynqTop) extends BoomSubsystemModule(outer) 69 | with HasRTCModuleImp 70 | with CanHaveMasterAXI4MemPortModuleImp 71 | with HasPeripheryBootROMModuleImp 72 | with HasExtInterruptsModuleImp 73 | with HasNoDebugModuleImp 74 | with HasPeripherySerialModuleImp 75 | with HasPeripheryBlockDeviceModuleImp 76 | with DontTouch 77 | 78 | class SmallBoomZynqConfig extends Config( 79 | new WithBootROM ++ new WithZynqAdapter ++ new _root_.boom.system.SmallBoomConfig) 80 | class MediumBoomZynqConfig extends Config( 81 | new WithBootROM ++ new WithZynqAdapter ++ new _root_.boom.system.MediumBoomConfig) 82 | -------------------------------------------------------------------------------- /common/src/main/scala/Configs.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.config.{Parameters, Config} 5 | import freechips.rocketchip.subsystem._ 6 | import freechips.rocketchip.devices.tilelink.BootROMParams 7 | import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} 8 | import freechips.rocketchip.tile.{RocketTileParams, BuildCore, XLen} 9 | import testchipip._ 10 | 11 | class WithBootROM extends Config((site, here, up) => { 12 | case BootROMParams => BootROMParams( 13 | contentFileName = s"testchipip/bootrom/bootrom.rv${site(XLen)}.img") 14 | }) 15 | 16 | class WithZynqAdapter extends Config((site, here, up) => { 17 | case SerialFIFODepth => 16 18 | case ResetCycles => 10 19 | case ZynqAdapterBase => BigInt(0x43C00000L) 20 | case ExtMem => up(ExtMem, site) map (_.copy(idBits = 6)) 21 | case ExtIn => up(ExtIn, site) map (_.copy(beatBytes = 4, idBits = 12)) 22 | case BlockDeviceKey => BlockDeviceConfig(nTrackers = 2) 23 | case BlockDeviceFIFODepth => 16 24 | case NetworkFIFODepth => 16 25 | }) 26 | 27 | class WithNMediumCores(n: Int) extends Config((site, here, up) => { 28 | case RocketTilesKey => { 29 | val medium = RocketTileParams( 30 | core = RocketCoreParams(fpu = None), 31 | btb = None, 32 | dcache = Some(DCacheParams( 33 | rowBits = site(SystemBusKey).beatBytes*8, 34 | nSets = 64, 35 | nWays = 1, 36 | nTLBEntries = 4, 37 | nMSHRs = 0, 38 | blockBytes = site(CacheBlockBytes))), 39 | icache = Some(ICacheParams( 40 | rowBits = site(SystemBusKey).beatBytes*8, 41 | nSets = 64, 42 | nWays = 1, 43 | nTLBEntries = 4, 44 | blockBytes = site(CacheBlockBytes)))) 45 | List.tabulate(n)(i => medium.copy(hartId = i)) 46 | } 47 | }) 48 | 49 | class DefaultConfig extends Config( 50 | new WithBootROM ++ new freechips.rocketchip.system.DefaultConfig) 51 | class DefaultMediumConfig extends Config( 52 | new WithBootROM ++ new WithNMediumCores(1) ++ 53 | new freechips.rocketchip.system.BaseConfig) 54 | class DefaultSmallConfig extends Config( 55 | new WithBootROM ++ new freechips.rocketchip.system.DefaultSmallConfig) 56 | 57 | class ZynqConfig extends Config(new WithZynqAdapter ++ new DefaultConfig) 58 | class ZynqMediumConfig extends Config(new WithZynqAdapter ++ new DefaultMediumConfig) 59 | class ZynqSmallConfig extends Config(new WithZynqAdapter ++ new DefaultSmallConfig) 60 | 61 | class ZynqFPGAConfig extends Config(new WithoutTLMonitors ++ new ZynqConfig) 62 | class ZynqMediumFPGAConfig extends Config(new WithoutTLMonitors ++ new ZynqMediumConfig) 63 | class ZynqSmallFPGAConfig extends Config(new WithoutTLMonitors ++ new ZynqSmallConfig) 64 | -------------------------------------------------------------------------------- /common/src/main/scala/Drivers.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import freechips.rocketchip.config.Parameters 6 | import freechips.rocketchip.diplomacy._ 7 | import freechips.rocketchip.tilelink._ 8 | import freechips.rocketchip.util._ 9 | import testchipip._ 10 | import testchipip.SerialAdapter._ 11 | 12 | class InFIFODriver(name: String, addr: BigInt, maxSpace: Int) 13 | (implicit p: Parameters) extends LazyModule { 14 | 15 | val node = TLHelper.makeClientNode( 16 | name = name, sourceId = IdRange(0, 1)) 17 | 18 | lazy val module = new LazyModuleImp(this) { 19 | val (tl, edge) = node.out(0) 20 | val dataBits = edge.bundle.dataBits 21 | val beatBytes = dataBits / 8 22 | 23 | val io = IO(new Bundle { 24 | val in = Flipped(Decoupled(UInt(dataBits.W))) 25 | }) 26 | 27 | val timeout = 64 28 | val timer = RegInit(0.U(log2Ceil(timeout).W)) 29 | val space = RegInit(0.U(log2Ceil(maxSpace + 1).W)) 30 | 31 | val (s_start :: s_read_acq :: s_read_gnt :: 32 | s_req :: s_write_acq :: s_write_gnt :: Nil) = Enum(6) 33 | val state = RegInit(s_start) 34 | val data = Reg(UInt(dataBits.W)) 35 | 36 | val put_acq = edge.Put( 37 | fromSource = 0.U, 38 | toAddress = addr.U, 39 | lgSize = log2Ceil(beatBytes).U, 40 | data = data)._2 41 | 42 | val get_acq = edge.Get( 43 | fromSource = 0.U, 44 | toAddress = (addr + beatBytes).U, 45 | lgSize = log2Ceil(beatBytes).U)._2 46 | 47 | tl.a.valid := state.isOneOf(s_read_acq, s_write_acq) 48 | tl.a.bits := Mux(state === s_read_acq, get_acq, put_acq) 49 | tl.d.ready := state.isOneOf(s_read_gnt, s_write_gnt) 50 | io.in.ready := state === s_req 51 | 52 | when (state === s_start) { 53 | when (space =/= 0.U) { 54 | state := s_req 55 | } .elsewhen (timer === 0.U) { 56 | timer := (timeout - 1).U 57 | state := s_read_acq 58 | } .otherwise { 59 | timer := timer - 1.U 60 | } 61 | } 62 | 63 | when (state === s_read_acq && tl.a.ready) { state := s_read_gnt } 64 | when (state === s_read_gnt && tl.d.valid) { 65 | space := tl.d.bits.data 66 | state := s_start 67 | } 68 | 69 | when (io.in.fire()) { 70 | data := io.in.bits 71 | space := space - 1.U 72 | state := s_write_acq 73 | } 74 | 75 | when (state === s_write_acq && tl.a.ready) { state := s_write_gnt } 76 | when (state === s_write_gnt && tl.d.valid) { state := s_start } 77 | } 78 | } 79 | 80 | class OutFIFODriver(name: String, addr: BigInt, maxCount: Int) 81 | (implicit p: Parameters) extends LazyModule { 82 | 83 | val node = TLHelper.makeClientNode( 84 | name = name, sourceId = IdRange(0, 1)) 85 | 86 | lazy val module = new LazyModuleImp(this) { 87 | val (tl, edge) = node.out(0) 88 | val dataBits = edge.bundle.dataBits 89 | val beatBytes = dataBits / 8 90 | val lgSize = log2Ceil(beatBytes) 91 | 92 | val io = IO(new Bundle { 93 | val out = Decoupled(UInt(dataBits.W)) 94 | }) 95 | 96 | val timeout = 64 97 | val timer = RegInit(0.U(log2Ceil(timeout).W)) 98 | val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) 99 | val (s_start :: s_count_acq :: s_count_gnt :: 100 | s_fifo_acq :: s_fifo_gnt :: Nil) = Enum(5) 101 | val state = RegInit(s_start) 102 | 103 | tl.a.valid := state.isOneOf(s_count_acq, s_fifo_acq) 104 | tl.a.bits := edge.Get( 105 | fromSource = 0.U, 106 | toAddress = Mux(state === s_count_acq, (addr + beatBytes).U, addr.U), 107 | lgSize = lgSize.U)._2 108 | 109 | tl.d.ready := 110 | (state === s_count_gnt) || 111 | (state === s_fifo_gnt && io.out.ready) 112 | 113 | io.out.valid := state === s_fifo_gnt && tl.d.valid 114 | io.out.bits := tl.d.bits.data 115 | 116 | when (state === s_start) { 117 | when (count =/= 0.U) { 118 | state := s_fifo_acq 119 | } .elsewhen (timer === 0.U) { 120 | timer := (timeout - 1).U 121 | state := s_count_acq 122 | } .otherwise { 123 | timer := timer - 1.U 124 | } 125 | } 126 | 127 | when (tl.a.fire()) { 128 | state := Mux(state === s_count_acq, s_count_gnt, s_fifo_gnt) 129 | } 130 | 131 | when (tl.d.fire()) { 132 | count := Mux(state === s_count_gnt, tl.d.bits.data, count - 1.U) 133 | state := s_start 134 | } 135 | } 136 | } 137 | 138 | class SetRegisterDriver(name: String, addr: BigInt, n: Int) 139 | (implicit p: Parameters) extends LazyModule { 140 | 141 | val node = TLHelper.makeClientNode( 142 | name = name, sourceId = IdRange(0, 1)) 143 | 144 | lazy val module = new LazyModuleImp(this) { 145 | val (tl, edge) = node.out(0) 146 | val dataBits = edge.bundle.dataBits 147 | val beatBytes = dataBits / 8 148 | val lgSize = log2Ceil(beatBytes) 149 | 150 | val io = IO(new Bundle { 151 | val values = Input(Vec(n, UInt(dataBits.W))) 152 | }) 153 | 154 | val (s_start :: s_write_acq :: s_write_gnt :: s_wait :: Nil) = Enum(4) 155 | val state = RegInit(s_start) 156 | val values = Reg(Vec(n, UInt(dataBits.W))) 157 | 158 | val value_diff = Cat(io.values.zip(values).map { 159 | case (iovalue, value) => iovalue != value 160 | }.reverse) 161 | val value_set = RegInit(UInt(n.W), ~0.U(n.W)) 162 | val value_set_oh = PriorityEncoderOH(value_set) 163 | val value_idx = OHToUInt(value_set_oh) 164 | 165 | tl.a.valid := state === s_write_acq 166 | tl.a.bits := edge.Put( 167 | fromSource = 0.U, 168 | toAddress = addr.U + (value_idx << lgSize.U), 169 | lgSize = lgSize.U, 170 | data = values(value_idx))._2 171 | tl.d.ready := state === s_write_gnt 172 | 173 | when (state === s_start) { 174 | state := s_write_acq 175 | for (i <- 0 until n) { 176 | when (value_set(i)) { 177 | values(i) := io.values(i) 178 | } 179 | } 180 | } 181 | when (tl.a.fire()) { state := s_write_gnt } 182 | when (tl.d.fire()) { 183 | value_set := value_set & ~value_set_oh 184 | state := s_wait 185 | } 186 | when (state === s_wait) { 187 | when (value_set.orR) { 188 | state := s_write_acq 189 | } .elsewhen (value_diff.orR) { 190 | value_set := value_diff 191 | state := s_start 192 | } 193 | } 194 | } 195 | } 196 | 197 | class SerialDriver(implicit p: Parameters) extends LazyModule { 198 | val base = p(ZynqAdapterBase) 199 | val depth = p(SerialFIFODepth) 200 | 201 | val node = TLIdentityNode() 202 | val xbar = LazyModule(new TLXbar) 203 | val outdrv = LazyModule(new OutFIFODriver("serial-out", base, depth)) 204 | val indrv = LazyModule(new InFIFODriver("serial-in", base + BigInt(8), depth)) 205 | 206 | xbar.node := outdrv.node 207 | xbar.node := indrv.node 208 | node := xbar.node 209 | 210 | lazy val module = new LazyModuleImp(this) { 211 | val (tl, edge) = node.out(0) 212 | require(edge.bundle.dataBits == SERIAL_IF_WIDTH) 213 | 214 | val io = IO(new Bundle { 215 | val serial = new SerialIO(SERIAL_IF_WIDTH) 216 | }) 217 | 218 | indrv.module.io.in <> io.serial.in 219 | io.serial.out <> outdrv.module.io.out 220 | } 221 | } 222 | 223 | class ResetDriver(implicit p: Parameters) extends LazyModule { 224 | val base = p(ZynqAdapterBase) 225 | 226 | val node = TLIdentityNode() 227 | val driver = LazyModule(new SetRegisterDriver("reset", base + BigInt(0x10), 1)) 228 | 229 | node := driver.node 230 | 231 | lazy val module = new LazyModuleImp(this) { 232 | driver.module.io.values(0) := 0.U 233 | } 234 | } 235 | 236 | class BlockDeviceDriver(implicit p: Parameters) extends LazyModule { 237 | val base = p(ZynqAdapterBase) 238 | val depth = p(BlockDeviceFIFODepth) 239 | 240 | val node = TLIdentityNode() 241 | val xbar = LazyModule(new TLXbar) 242 | val reqdrv = LazyModule(new OutFIFODriver( 243 | "bdev-req", base + BigInt(0x20), depth)) 244 | val datadrv = LazyModule(new OutFIFODriver( 245 | "bdev-data", base + BigInt(0x28), depth)) 246 | val respdrv = LazyModule(new InFIFODriver( 247 | "bdev-resp", base + BigInt(0x30), depth)) 248 | val infodrv = LazyModule(new SetRegisterDriver( 249 | "bdev-info", base + BigInt(0x38), 2)) 250 | 251 | xbar.node := reqdrv.node 252 | xbar.node := datadrv.node 253 | xbar.node := respdrv.node 254 | xbar.node := infodrv.node 255 | node := xbar.node 256 | 257 | lazy val module = new LazyModuleImp(this) { 258 | val (tl, edge) = node.out(0) 259 | val dataBits = edge.bundle.dataBits 260 | 261 | val io = IO(new Bundle { 262 | val bdev = new BlockDeviceIO 263 | }) 264 | 265 | val desser = Module(new BlockDeviceDesser(dataBits)) 266 | io.bdev <> desser.io.bdev 267 | desser.io.ser.req <> reqdrv.module.io.out 268 | desser.io.ser.data <> datadrv.module.io.out 269 | respdrv.module.io.in <> desser.io.ser.resp 270 | infodrv.module.io.values := Seq( 271 | io.bdev.info.nsectors, io.bdev.info.max_req_len) 272 | } 273 | } 274 | -------------------------------------------------------------------------------- /common/src/main/scala/Generator.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | object Generator extends testchipip.GeneratorApp { 4 | override lazy val longName = names.topModuleClass + "." + names.configs 5 | generateFirrtl 6 | generateAnno 7 | } 8 | -------------------------------------------------------------------------------- /common/src/main/scala/Serdes.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import freechips.rocketchip.config.Parameters 6 | import testchipip._ 7 | 8 | class BlockDeviceSerialIO(w: Int) extends Bundle { 9 | val req = Decoupled(UInt(w.W)) 10 | val data = Decoupled(UInt(w.W)) 11 | val resp = Flipped(Decoupled(UInt(w.W))) 12 | 13 | override def cloneType = new BlockDeviceSerialIO(w).asInstanceOf[this.type] 14 | } 15 | 16 | class BlockDeviceSerdes(w: Int)(implicit p: Parameters) 17 | extends BlockDeviceModule { 18 | val io = IO(new Bundle { 19 | val bdev = Flipped(new BlockDeviceIO) 20 | val ser = new BlockDeviceSerialIO(w) 21 | }) 22 | 23 | require(w >= sectorBits) 24 | require(w >= (tagBits + 1)) 25 | require(dataBitsPerBeat % w == 0) 26 | 27 | val reqWords = 3 28 | val dataWords = 1 + dataBitsPerBeat / w 29 | 30 | val req = Reg(new BlockDeviceRequest) 31 | val data = Reg(new BlockDeviceData) 32 | val resp = Reg(new BlockDeviceData) 33 | 34 | val (req_idx, req_done) = Counter(io.ser.req.fire(), reqWords) 35 | val req_send = RegInit(false.B) 36 | 37 | val (data_idx, data_done) = Counter(io.ser.data.fire(), dataWords) 38 | val data_send = RegInit(false.B) 39 | 40 | val (resp_idx, resp_done) = Counter(io.ser.resp.fire(), dataWords) 41 | val resp_send = RegInit(false.B) 42 | 43 | when (io.bdev.req.fire()) { 44 | req := io.bdev.req.bits 45 | req_send := true.B 46 | } 47 | when (req_done) { req_send := false.B } 48 | 49 | when (io.bdev.data.fire()) { 50 | data := io.bdev.data.bits 51 | data_send := true.B 52 | } 53 | when (data_done) { data_send := false.B } 54 | 55 | when (io.ser.resp.fire()) { 56 | when (resp_idx === 0.U) { 57 | resp.tag := io.ser.resp.bits 58 | resp.data := 0.U 59 | } .otherwise { 60 | val shift_amt = (resp_idx - 1.U) << log2Ceil(w).U 61 | resp.data := resp.data | (io.ser.resp.bits << shift_amt) 62 | } 63 | } 64 | when (resp_done) { resp_send := true.B } 65 | when (io.bdev.resp.fire()) { resp_send := false.B } 66 | 67 | io.bdev.req.ready := !req_send 68 | io.bdev.data.ready := !data_send 69 | io.bdev.resp.valid := resp_send 70 | io.bdev.resp.bits := resp 71 | io.bdev.info := DontCare 72 | 73 | val req_vec = Vec(Cat(req.tag, req.write), req.offset, req.len) 74 | val data_vec = Vec(data.tag +: Seq.tabulate(dataBitsPerBeat/w) { 75 | i => data.data((i + 1) * w - 1, i * w) 76 | }) 77 | 78 | io.ser.req.valid := req_send 79 | io.ser.req.bits := req_vec(req_idx) 80 | io.ser.data.valid := data_send 81 | io.ser.data.bits := data_vec(data_idx) 82 | io.ser.resp.ready := !resp_send 83 | } 84 | 85 | class BlockDeviceDesser(w: Int)(implicit p: Parameters) extends BlockDeviceModule { 86 | val io = IO(new Bundle { 87 | val bdev = new BlockDeviceIO 88 | val ser = Flipped(new BlockDeviceSerialIO(w)) 89 | }) 90 | 91 | require(w >= sectorBits) 92 | require(w >= (tagBits + 1)) 93 | require(dataBitsPerBeat % w == 0) 94 | 95 | val reqWords = 3 96 | val dataWords = 1 + dataBitsPerBeat / w 97 | 98 | val req = Reg(new BlockDeviceRequest) 99 | val data = Reg(new BlockDeviceData) 100 | val resp = Reg(new BlockDeviceData) 101 | 102 | val (req_idx, req_done) = Counter(io.ser.req.fire(), reqWords) 103 | val req_send = RegInit(false.B) 104 | 105 | val (data_idx, data_done) = Counter(io.ser.data.fire(), dataWords) 106 | val data_send = RegInit(false.B) 107 | 108 | val (resp_idx, resp_done) = Counter(io.ser.resp.fire(), dataWords) 109 | val resp_send = RegInit(false.B) 110 | 111 | when (io.ser.req.fire()) { 112 | switch (req_idx) { 113 | is (0.U) { 114 | req.write := io.ser.req.bits(0) 115 | req.tag := io.ser.req.bits(tagBits, 1) 116 | } 117 | is (1.U) { 118 | req.offset := io.ser.req.bits 119 | } 120 | is (2.U) { 121 | req.len := io.ser.req.bits 122 | } 123 | } 124 | } 125 | when (req_done) { req_send := true.B } 126 | when (io.bdev.req.fire()) { 127 | req_send := false.B 128 | } 129 | 130 | when (io.ser.data.fire()) { 131 | when (data_idx === 0.U) { 132 | data.tag := io.ser.data.bits 133 | data.data := 0.U 134 | } .otherwise { 135 | val shift_amt = (data_idx - 1.U) << log2Ceil(w).U 136 | data.data := data.data | (io.ser.data.bits << shift_amt) 137 | } 138 | } 139 | when (data_done) { data_send := true.B } 140 | when (io.bdev.data.fire()) { data_send := false.B } 141 | 142 | when (io.bdev.resp.fire()) { 143 | resp := io.bdev.resp.bits 144 | resp_send := true.B 145 | } 146 | when (resp_done) { resp_send := false.B } 147 | 148 | io.bdev.req.valid := req_send 149 | io.bdev.req.bits := req 150 | io.bdev.data.valid := data_send 151 | io.bdev.data.bits := data 152 | io.bdev.resp.ready := !resp_send 153 | 154 | val resp_vec = Vec(resp.tag +: Seq.tabulate(dataBitsPerBeat/w) { 155 | i => resp.data((i + 1) * w - 1, i * w) 156 | }) 157 | 158 | io.ser.req.ready := !req_send 159 | io.ser.data.ready := !data_send 160 | io.ser.resp.valid := resp_send 161 | io.ser.resp.bits := resp_vec(resp_idx) 162 | } 163 | -------------------------------------------------------------------------------- /common/src/main/scala/TestHarness.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | import chisel3._ 4 | import chisel3.util.Queue 5 | import freechips.rocketchip.amba.axi4._ 6 | import freechips.rocketchip.subsystem.ExtIn 7 | import freechips.rocketchip.config.Parameters 8 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 9 | import freechips.rocketchip.tilelink._ 10 | import testchipip._ 11 | import testchipip.SerialAdapter._ 12 | 13 | class TestHarness(implicit val p: Parameters) extends Module { 14 | val io = IO(new Bundle { 15 | val success = Output(Bool()) 16 | }) 17 | 18 | val driver = Module(LazyModule(new TestHarnessDriver).module) 19 | val dut = Module(LazyModule(new FPGAZynqTop).module) 20 | 21 | dut.reset := driver.io.sys_reset 22 | dut.debug := DontCare 23 | dut.tieOffInterrupts() 24 | dut.dontTouchPorts() 25 | dut.connectSimAXIMem() 26 | 27 | driver.io.serial <> dut.serial 28 | driver.io.bdev <> dut.bdev 29 | io.success := driver.io.success 30 | } 31 | 32 | class TestHarnessDriver(implicit p: Parameters) extends LazyModule { 33 | val xbar = LazyModule(new TLXbar) 34 | val config = p(ExtIn).get 35 | val base = p(ZynqAdapterBase) 36 | 37 | val zynq = LazyModule(new ZynqAdapterCore(base, config.beatBytes)) 38 | val converter = LazyModule(new TLToAXI4) 39 | 40 | val serDriver = LazyModule(new SerialDriver) 41 | val resetDriver = LazyModule(new ResetDriver) 42 | val blkdevDriver = LazyModule(new BlockDeviceDriver) 43 | 44 | xbar.node := serDriver.node 45 | xbar.node := resetDriver.node 46 | xbar.node := blkdevDriver.node 47 | converter.node := xbar.node 48 | zynq.node := converter.node 49 | 50 | lazy val module = new LazyModuleImp(this) { 51 | val io = IO(new Bundle { 52 | val serial = Flipped(new SerialIO(SERIAL_IF_WIDTH)) 53 | val bdev = Flipped(new BlockDeviceIO) 54 | val sys_reset = Output(Bool()) 55 | val success = Output(Bool()) 56 | }) 57 | 58 | val simSerial = Module(new SimSerial(SERIAL_IF_WIDTH)) 59 | val simBlockDev = Module(new SimBlockDevice) 60 | simSerial.io.clock := clock 61 | simSerial.io.reset := reset 62 | simBlockDev.io.clock := clock 63 | simBlockDev.io.reset := reset 64 | serDriver.module.reset := zynq.module.io.sys_reset 65 | blkdevDriver.module.reset := zynq.module.io.sys_reset 66 | 67 | zynq.module.io.serial <> io.serial 68 | simSerial.io.serial <> serDriver.module.io.serial 69 | zynq.module.io.bdev <> io.bdev 70 | simBlockDev.io.bdev <> blkdevDriver.module.io.bdev 71 | 72 | io.sys_reset := zynq.module.io.sys_reset 73 | io.success := simSerial.io.exit 74 | } 75 | } 76 | -------------------------------------------------------------------------------- /common/src/main/scala/Top.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.config.{Parameters, Field} 5 | import freechips.rocketchip.devices.tilelink._ 6 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7 | import freechips.rocketchip.subsystem._ 8 | import freechips.rocketchip.util.DontTouch 9 | import testchipip._ 10 | 11 | case object ZynqAdapterBase extends Field[BigInt] 12 | 13 | class Top(implicit val p: Parameters) extends Module { 14 | val address = p(ZynqAdapterBase) 15 | val config = p(ExtIn).get 16 | val target = Module(LazyModule(new FPGAZynqTop).module) 17 | val adapter = Module(LazyModule(new ZynqAdapter(address, config)).module) 18 | 19 | require(target.mem_axi4.size == 1) 20 | 21 | val io = IO(new Bundle { 22 | val ps_axi_slave = Flipped(adapter.axi.cloneType) 23 | val mem_axi = target.mem_axi4.head.cloneType 24 | }) 25 | 26 | io.mem_axi <> target.mem_axi4.head 27 | adapter.axi <> io.ps_axi_slave 28 | adapter.io.serial <> target.serial 29 | adapter.io.bdev <> target.bdev 30 | 31 | target.debug := DontCare 32 | target.tieOffInterrupts() 33 | target.dontTouchPorts() 34 | target.reset := adapter.io.sys_reset 35 | } 36 | 37 | class FPGAZynqTop(implicit p: Parameters) extends RocketSubsystem 38 | with CanHaveMasterAXI4MemPort 39 | // with HasSystemErrorSlave 40 | with HasPeripheryBootROM 41 | with HasSyncExtInterrupts 42 | with HasNoDebug 43 | with HasPeripherySerial 44 | with HasPeripheryBlockDevice { 45 | override lazy val module = new FPGAZynqTopModule(this) 46 | } 47 | 48 | class FPGAZynqTopModule(outer: FPGAZynqTop) extends RocketSubsystemModuleImp(outer) 49 | with HasRTCModuleImp 50 | with CanHaveMasterAXI4MemPortModuleImp 51 | with HasPeripheryBootROMModuleImp 52 | with HasExtInterruptsModuleImp 53 | with HasNoDebugModuleImp 54 | with HasPeripherySerialModuleImp 55 | with HasPeripheryBlockDeviceModuleImp 56 | with DontTouch 57 | -------------------------------------------------------------------------------- /common/src/main/scala/ZynqAdapter.scala: -------------------------------------------------------------------------------- 1 | package zynq 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import freechips.rocketchip.amba.axi4._ 6 | import freechips.rocketchip.config.{Parameters, Field} 7 | import freechips.rocketchip.subsystem.SlavePortParams 8 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} 9 | import freechips.rocketchip.regmapper.{RegField, HasRegMap} 10 | import testchipip._ 11 | import testchipip.SerialAdapter._ 12 | 13 | case object SerialFIFODepth extends Field[Int] 14 | case object BlockDeviceFIFODepth extends Field[Int] 15 | case object NetworkFIFODepth extends Field[Int] 16 | case object ResetCycles extends Field[Int] 17 | 18 | trait ZynqAdapterCoreBundle extends Bundle { 19 | implicit val p: Parameters 20 | 21 | val sys_reset = Output(Bool()) 22 | val serial = Flipped(new SerialIO(SERIAL_IF_WIDTH)) 23 | val bdev = Flipped(new BlockDeviceIO) 24 | } 25 | 26 | trait ZynqAdapterCoreModule extends HasRegMap 27 | with HasBlockDeviceParameters { 28 | implicit val p: Parameters 29 | val io: ZynqAdapterCoreBundle 30 | val w = SERIAL_IF_WIDTH 31 | 32 | val serDepth = p(SerialFIFODepth) 33 | val bdevDepth = p(BlockDeviceFIFODepth) 34 | val serCountBits = log2Ceil(serDepth + 1) 35 | val bdevCountBits = log2Ceil(bdevDepth + 1) 36 | 37 | val ser_out_fifo = Module(new Queue(UInt(w.W), serDepth)) 38 | val ser_in_fifo = Module(new Queue(UInt(w.W), serDepth)) 39 | 40 | ser_out_fifo.io.enq <> io.serial.out 41 | io.serial.in <> ser_in_fifo.io.deq 42 | 43 | val sys_reset = RegInit(true.B) 44 | io.sys_reset := sys_reset 45 | 46 | val bdev_req_fifo = Module(new Queue(UInt(w.W), bdevDepth)) 47 | val bdev_data_fifo = Module(new Queue(UInt(w.W), bdevDepth)) 48 | val bdev_resp_fifo = Module(new Queue(UInt(w.W), bdevDepth)) 49 | val bdev_info = Reg(new BlockDeviceInfo) 50 | val bdev_serdes = Module(new BlockDeviceSerdes(w)) 51 | 52 | bdev_serdes.io.bdev <> io.bdev 53 | bdev_req_fifo.io.enq <> bdev_serdes.io.ser.req 54 | bdev_data_fifo.io.enq <> bdev_serdes.io.ser.data 55 | bdev_serdes.io.ser.resp <> bdev_resp_fifo.io.deq 56 | io.bdev.info := bdev_info 57 | 58 | val ser_in_space = (serDepth.U - ser_in_fifo.io.count) 59 | val bdev_resp_space = (bdevDepth.U - bdev_resp_fifo.io.count) 60 | 61 | /** 62 | * Address Map 63 | * 0x00 - serial out FIFO data 64 | * 0x04 - serial out FIFO data available (words) 65 | * 0x08 - serial in FIFO data 66 | * 0x0C - serial in FIFO space available (words) 67 | * 0x10 - system reset 68 | * 0x20 - req FIFO data 69 | * 0x24 - req FIFO data available (words) 70 | * 0x28 - data FIFO data 71 | * 0x2C - data FIFO data available (words) 72 | * 0x30 - resp FIFO data 73 | * 0x34 - resp FIFO space available (words) 74 | * 0x38 - nsectors 75 | * 0x3C - max request length 76 | */ 77 | regmap( 78 | 0x00 -> Seq(RegField.r(w, ser_out_fifo.io.deq)), 79 | 0x04 -> Seq(RegField.r(serCountBits, ser_out_fifo.io.count)), 80 | 0x08 -> Seq(RegField.w(w, ser_in_fifo.io.enq)), 81 | 0x0C -> Seq(RegField.r(serCountBits, ser_in_space)), 82 | 0x10 -> Seq(RegField(1, sys_reset)), 83 | 0x20 -> Seq(RegField.r(w, bdev_req_fifo.io.deq)), 84 | 0x24 -> Seq(RegField.r(bdevCountBits, bdev_req_fifo.io.count)), 85 | 0x28 -> Seq(RegField.r(w, bdev_data_fifo.io.deq)), 86 | 0x2C -> Seq(RegField.r(bdevCountBits, bdev_data_fifo.io.count)), 87 | 0x30 -> Seq(RegField.w(w, bdev_resp_fifo.io.enq)), 88 | 0x34 -> Seq(RegField.r(bdevCountBits, bdev_resp_space)), 89 | 0x38 -> Seq(RegField(sectorBits, bdev_info.nsectors)), 90 | 0x3C -> Seq(RegField(sectorBits, bdev_info.max_req_len))) 91 | } 92 | 93 | class ZynqAdapterCore(address: BigInt, beatBytes: Int)(implicit p: Parameters) 94 | extends AXI4RegisterRouter( 95 | address, beatBytes = beatBytes, concurrency = 1)( 96 | new AXI4RegBundle((), _) with ZynqAdapterCoreBundle)( 97 | new AXI4RegModule((), _, _) with ZynqAdapterCoreModule) 98 | 99 | class ZynqAdapter(address: BigInt, config: SlavePortParams)(implicit p: Parameters) 100 | extends LazyModule { 101 | 102 | val node = AXI4MasterNode(Seq(AXI4MasterPortParameters( 103 | masters = Seq(AXI4MasterParameters( 104 | name = "Zynq Adapter", 105 | id = IdRange(0, 1 << config.idBits)))))) 106 | 107 | val core = LazyModule(new ZynqAdapterCore(address, config.beatBytes)) 108 | core.node := AXI4Fragmenter() := node 109 | 110 | lazy val module = new LazyModuleImp(this) { 111 | val io = IO(new Bundle { 112 | val sys_reset = Output(Bool()) 113 | val serial = Flipped(new SerialIO(SERIAL_IF_WIDTH)) 114 | val bdev = Flipped(new BlockDeviceIO) 115 | }) 116 | val axi = IO(Flipped(node.out(0)._1.cloneType)) 117 | node.out(0)._1 <> axi 118 | 119 | val coreIO = core.module.io 120 | io.sys_reset := coreIO.sys_reset 121 | coreIO.serial <> io.serial 122 | coreIO.bdev <> io.bdev 123 | } 124 | } 125 | -------------------------------------------------------------------------------- /common/zynq_rocketchip.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Vivado (TM) v2015.4 (64-bit) 3 | # 4 | # BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE.tcl: Tcl script for re-creating project 'BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE' 5 | # 6 | # Generated by Vivado on Tue Jan 05 14:52:20 PST 2016 7 | # IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 8 | # 9 | # This file contains the Vivado Tcl commands for re-creating the project to the state* 10 | # when this script was generated. In order to re-create the project, please source this 11 | # file in the Vivado Tcl Shell. 12 | # 13 | # * Note that the runs in the created project will be configured the same way as the 14 | # original project, however they will not be launched automatically. To regenerate the 15 | # run results please launch the synthesis/implementation runs as needed. 16 | 17 | # Set the reference directory for source file relative paths (by default the value is script directory path) 18 | set origin_dir "." 19 | 20 | # Use origin directory path location variable, if specified in the tcl shell 21 | if { [info exists ::origin_dir_loc] } { 22 | set origin_dir $::origin_dir_loc 23 | } 24 | 25 | variable script_file 26 | set script_file "BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE.tcl" 27 | 28 | # Help information for this script 29 | proc help {} { 30 | variable script_file 31 | puts "\nDescription:" 32 | puts "Recreate a Vivado project from this script. The created project will be" 33 | puts "functionally equivalent to the original project for which this script was" 34 | puts "generated. The script contains commands for creating a project, filesets," 35 | puts "runs, adding/importing sources and setting properties on various objects.\n" 36 | puts "Syntax:" 37 | puts "$script_file" 38 | puts "$script_file -tclargs \[--origin_dir \]" 39 | puts "$script_file -tclargs \[--help\]\n" 40 | puts "Usage:" 41 | puts "Name Description" 42 | puts "-------------------------------------------------------------------------" 43 | puts "\[--origin_dir \] Determine source file paths wrt this path. Default" 44 | puts " origin_dir path value is \".\", otherwise, the value" 45 | puts " that was set with the \"-paths_relative_to\" switch" 46 | puts " when this script was generated.\n" 47 | puts "\[--help\] Print help information for this script" 48 | puts "-------------------------------------------------------------------------\n" 49 | exit 0 50 | } 51 | 52 | if { $::argc > 0 } { 53 | for {set i 0} {$i < [llength $::argc]} {incr i} { 54 | set option [string trim [lindex $::argv $i]] 55 | switch -regexp -- $option { 56 | "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } 57 | "--help" { help } 58 | default { 59 | if { [regexp {^-} $option] } { 60 | puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" 61 | return 1 62 | } 63 | } 64 | } 65 | } 66 | } 67 | 68 | # Set the directory path for the original project from where this script was exported 69 | set orig_proj_dir "[file normalize "$origin_dir/BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE"]" 70 | 71 | # Create project 72 | create_project BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE $orig_proj_dir 73 | 74 | # Set the directory path for the new project 75 | set proj_dir [get_property directory [current_project]] 76 | 77 | # Set project properties 78 | set obj [get_projects BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE] 79 | set_property "default_lib" "xil_defaultlib" $obj 80 | set_property "part" "PART_NUMBER_HERE" $obj 81 | # REPLACE FOR OFFICIAL BOARD NAME $obj 82 | set_property "simulator_language" "Mixed" $obj 83 | 84 | # Create 'sources_1' fileset (if not found) 85 | if {[string equal [get_filesets -quiet sources_1] ""]} { 86 | create_fileset -srcset sources_1 87 | } 88 | 89 | # Set 'sources_1' fileset object 90 | set obj [get_filesets sources_1] 91 | set files [list \ 92 | "[file normalize "$origin_dir/src/verilog/clocking.vh"]"\ 93 | "[file normalize "$origin_dir/src/verilog/Top.CHISEL_CONFIG_HERE.v"]"\ 94 | "[file normalize "$origin_dir/src/verilog/rocketchip_wrapper.v"]"\ 95 | "[file normalize "$origin_dir/src/verilog/AsyncResetReg.v"]" \ 96 | "[file normalize "$origin_dir/src/verilog/plusarg_reader.v"]" \ 97 | ] 98 | add_files -norecurse -fileset $obj $files 99 | 100 | # Set 'sources_1' fileset file properties for remote files 101 | # None 102 | 103 | # Set 'sources_1' fileset file properties for local files 104 | # None 105 | 106 | # Set 'sources_1' fileset properties 107 | set obj [get_filesets sources_1] 108 | set_property "top" "rocketchip_wrapper" $obj 109 | 110 | # Create 'constrs_1' fileset (if not found) 111 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 112 | create_fileset -constrset constrs_1 113 | } 114 | 115 | # Set 'constrs_1' fileset object 116 | set obj [get_filesets constrs_1] 117 | 118 | # Add/Import constrs file and set constrs file properties 119 | set file "[file normalize "$origin_dir/src/constrs/base.xdc"]" 120 | set file_added [add_files -norecurse -fileset $obj $file] 121 | set file "$origin_dir/src/constrs/base.xdc" 122 | set file [file normalize $file] 123 | set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] 124 | set_property "file_type" "XDC" $file_obj 125 | 126 | # Set 'constrs_1' fileset properties 127 | set obj [get_filesets constrs_1] 128 | set_property "target_constrs_file" "[file normalize "$origin_dir/src/constrs/base.xdc"]" $obj 129 | 130 | # Create 'sim_1' fileset (if not found) 131 | if {[string equal [get_filesets -quiet sim_1] ""]} { 132 | create_fileset -simset sim_1 133 | } 134 | 135 | # Set 'sim_1' fileset object 136 | set obj [get_filesets sim_1] 137 | # Empty (no sources present) 138 | 139 | # Set 'sim_1' fileset properties 140 | set obj [get_filesets sim_1] 141 | set_property "top" "rocketchip_wrapper" $obj 142 | 143 | # Create 'synth_1' run (if not found) 144 | if {[string equal [get_runs -quiet synth_1] ""]} { 145 | create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 146 | } else { 147 | set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] 148 | set_property flow "Vivado Synthesis 2015" [get_runs synth_1] 149 | } 150 | set obj [get_runs synth_1] 151 | set_property "needs_refresh" "1" $obj 152 | set_property "part" "PART_NUMBER_HERE" $obj 153 | 154 | # Create 'impl_1' run (if not found) 155 | if {[string equal [get_runs -quiet impl_1] ""]} { 156 | create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 157 | } else { 158 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 159 | set_property flow "Vivado Implementation 2015" [get_runs impl_1] 160 | } 161 | set obj [get_runs impl_1] 162 | set_property "needs_refresh" "1" $obj 163 | set_property "part" "PART_NUMBER_HERE" $obj 164 | 165 | puts "INFO: Project created:BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE" 166 | 167 | puts "INFO: Recreating block diagram from src/tcl/BOARD_NAME_HERE_bd.tcl" 168 | source src/tcl/BOARD_NAME_HERE_bd.tcl 169 | 170 | exit 171 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.1.1 2 | -------------------------------------------------------------------------------- /simulation/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !Makefile 3 | !.gitignore 4 | !src/verilog/.gitkeep 5 | -------------------------------------------------------------------------------- /simulation/Makefile: -------------------------------------------------------------------------------- 1 | #TOP_MODULE_PROJECT = zynq # for Rocket 2 | TOP_MODULE_PROJECT = zynq.boom # for BOOM 3 | TOP_MODULE = TestHarness 4 | #CONFIG ?= ZynqConfig 5 | CONFIG ?= SmallBoomZynqConfig 6 | #CONFIG ?= MediumBoomZynqConfig 7 | TB = TestDriver 8 | 9 | simv = simv-$(CONFIG) 10 | simv_debug = simv-$(CONFIG)-debug 11 | 12 | default: $(simv) 13 | debug: $(simv_debug) 14 | 15 | include ../common/Makefrag 16 | 17 | sim_vsrcs = \ 18 | src/verilog/$(TOP_MODULE).$(CONFIG).v \ 19 | $(ROCKET_DIR)/src/main/resources/vsrc/TestDriver.v \ 20 | $(ROCKET_DIR)/src/main/resources/vsrc/AsyncResetReg.v \ 21 | $(ROCKET_DIR)/src/main/resources/vsrc/plusarg_reader.v \ 22 | $(base_dir)/testchipip/vsrc/SimSerial.v \ 23 | $(base_dir)/testchipip/vsrc/SimBlockDevice.v \ 24 | 25 | sim_csrcs = \ 26 | $(base_dir)/testchipip/csrc/SimSerial.cc \ 27 | $(base_dir)/testchipip/csrc/SimBlockDevice.cc \ 28 | $(base_dir)/testchipip/csrc/blkdev.cc \ 29 | 30 | VCS = vcs -full64 31 | 32 | VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ 33 | +rad +v2k +vcs+lic+wait \ 34 | +vc+list -CC "-I$(VCS_HOME)/include" \ 35 | -CC "-I$(RISCV)/include -I$(base_dir)/testchipip/csrc" \ 36 | -CC "-std=c++11" \ 37 | -CC "-Wl,-rpath,$(RISCV)/lib" \ 38 | $(RISCV)/lib/libfesvr.so \ 39 | -sverilog \ 40 | +incdir+$(generated_dir) \ 41 | +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ 42 | +define+PRINTF_COND=$(TB).printf_cond \ 43 | +define+STOP_COND=!$(TB).reset \ 44 | +define+RANDOMIZE_MEM_INIT \ 45 | +define+RANDOMIZE_REG_INIT \ 46 | +define+RANDOMIZE_GARBAGE_ASSIGN \ 47 | +define+RANDOMIZE_INVALID_ASSIGN \ 48 | +libext+.v \ 49 | 50 | verilog: $(sim_vsrcs) 51 | 52 | $(simv): $(sim_vsrcs) $(sim_csrcs) 53 | rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ 54 | -debug_pp 55 | 56 | $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) 57 | rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ 58 | +define+DEBUG -debug_pp 59 | -------------------------------------------------------------------------------- /simulation/src/verilog/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-boom/fpga-zynq/9d6c243a2786eb4a898bc67a9e8688318b22f355/simulation/src/verilog/.gitkeep -------------------------------------------------------------------------------- /src: -------------------------------------------------------------------------------- 1 | common/src -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | bblvmlinux 2 | riscv-tools 3 | -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- 1 | all: bblvmlinux 2 | 3 | # This setups the repository for automatic generation of ramdisk images 4 | # by running through the manual configuration stages of linux and busybox 5 | setup: buildroot/.config.old linux/.config.old 6 | 7 | ############################################################################### 8 | # Get sources and configure 9 | ############################################################################### 10 | 11 | # Busybox is a submodule. Init it before commencing 12 | buildroot/.config: buildroot-config 13 | cp -f $< $@ 14 | 15 | # Configure buildroot. Hopefully this is a NOP! 16 | buildroot/.config.old: buildroot/.config 17 | make -C $(@D) oldconfig 18 | 19 | linux/.config: linux-config linux 20 | cp -f $< $@ 21 | 22 | # Configure linux. Hopefully this is a nop. 23 | linux/.config.old: linux/.config 24 | make -C $(@D) ARCH=riscv oldconfig 25 | 26 | ############################################################################### 27 | # Build 28 | ############################################################################### 29 | initramfs = buildroot/output/images/rootfs.cpio 30 | $(initramfs): buildroot/.config.old $(shell find buildroot-overlay) 31 | make -C buildroot -j1 32 | 33 | busybox/busybox: busybox/.config.old profile 34 | @echo "Building busybox." 35 | time make -C $(@D) -j 36 | 37 | linux/vmlinux: linux/.config.old $(initramfs) 38 | @echo "Building riscv linux." 39 | time make -C $(@D) -j ARCH=riscv vmlinux 40 | 41 | bblvmlinux: linux/vmlinux 42 | @echo "Building an bbl instance with your payload." 43 | time ./build-pk.sh 44 | 45 | clean: 46 | rm -rf bblvmlinux 47 | rm -rf riscv-pk/build 48 | rm -rf $(initramfs) 49 | rm -rf buildroot/output/target/etc/init.d/S02run 50 | 51 | .PHONY: setup buildroot all clean 52 | -------------------------------------------------------------------------------- /sw/README.md: -------------------------------------------------------------------------------- 1 | ## Step 0: Install the RISC-V tools 2 | 3 | Set the environment variable, `RISCV`, for the path where the RISC-V will be installed. Run `./build-riscv-tools.sh`. 4 | 5 | ## Step 1: Put your files in `buildroot-overlay/root` 6 | 7 | Also, change the content in `buildroot-overlay/etc/init.d/rcS`. 8 | 9 | ## Step 2: Build Linux 10 | 11 | Run `make`. 12 | 13 | ## Step 3: Test with `spike`. 14 | 15 | Run `spike bblvmlinux`. 16 | 17 | ## Step 4: Run in the Zynq board. 18 | 19 | Copy `bblvmlinux` to the SD card, and run `./fesvr-zynq bblvmlinux`. 20 | 21 | ## TODO 22 | 23 | Use FireMarshal: https://github.com/firesim/firesim-software 24 | -------------------------------------------------------------------------------- /sw/build-pk.sh: -------------------------------------------------------------------------------- 1 | VMLINUX=$PWD/linux/vmlinux 2 | JOBS=16 3 | # Use gmake instead of make if it exists. 4 | MAKE=`command -v gmake || command -v make` 5 | 6 | mkdir -p riscv-pk/build 7 | cd riscv-pk/build 8 | echo "Configuring riscv-pk" 9 | ../configure --prefix=$RISCV --host=riscv64-unknown-elf --with-payload=$VMLINUX > build.log 10 | echo "Building riscv-pk" 11 | $MAKE -j$JOBS >> build.log 12 | cd - 13 | cp riscv-pk/build/bbl bblvmlinux 14 | -------------------------------------------------------------------------------- /sw/build-riscv-tools.sh: -------------------------------------------------------------------------------- 1 | git clone -n https://github.com/firesim/riscv-tools.git 2 | cd riscv-tools 3 | git checkout 1859daea5e71809af62a6d4eb12d8f203c7efbc8 4 | git submodule update --init 5 | 6 | cd riscv-gnu-toolchain 7 | git submodule init 8 | git submodule update riscv-binutils-gdb 9 | git submodule update riscv-gcc 10 | git submodule update riscv-glibc 11 | git submodule update riscv-newlib 12 | git submodule update riscv-dejagnu 13 | 14 | ./build.sh 15 | cd riscv-gnu-toolchain/build 16 | make linux 17 | 18 | cd ../.. 19 | -------------------------------------------------------------------------------- /sw/buildroot-overlay/.gitignore: -------------------------------------------------------------------------------- 1 | root 2 | -------------------------------------------------------------------------------- /sw/buildroot-overlay/etc/init.d/rcK: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | 4 | # do nothing 5 | -------------------------------------------------------------------------------- /sw/buildroot-overlay/etc/init.d/rcS: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | 4 | poweroff 5 | -------------------------------------------------------------------------------- /sw/busybox-config: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated make config: don't edit 3 | # Busybox version: 1.26.2 4 | # Tue Oct 9 13:37:49 2018 5 | # 6 | CONFIG_HAVE_DOT_CONFIG=y 7 | 8 | # 9 | # Busybox Settings 10 | # 11 | CONFIG_DESKTOP=y 12 | # CONFIG_EXTRA_COMPAT is not set 13 | CONFIG_INCLUDE_SUSv2=y 14 | # CONFIG_USE_PORTABLE_CODE is not set 15 | CONFIG_PLATFORM_LINUX=y 16 | CONFIG_SHOW_USAGE=y 17 | CONFIG_FEATURE_VERBOSE_USAGE=y 18 | # CONFIG_FEATURE_COMPRESS_USAGE is not set 19 | CONFIG_BUSYBOX=y 20 | CONFIG_FEATURE_INSTALLER=y 21 | # CONFIG_INSTALL_NO_USR is not set 22 | # CONFIG_PAM is not set 23 | CONFIG_LONG_OPTS=y 24 | CONFIG_FEATURE_DEVPTS=y 25 | CONFIG_FEATURE_CLEAN_UP=y 26 | CONFIG_FEATURE_UTMP=y 27 | CONFIG_FEATURE_WTMP=y 28 | # CONFIG_FEATURE_PIDFILE is not set 29 | CONFIG_PID_FILE_PATH="" 30 | CONFIG_FEATURE_SUID=y 31 | # CONFIG_FEATURE_SUID_CONFIG is not set 32 | # CONFIG_FEATURE_SUID_CONFIG_QUIET is not set 33 | # CONFIG_SELINUX is not set 34 | # CONFIG_FEATURE_PREFER_APPLETS is not set 35 | CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe" 36 | CONFIG_FEATURE_SYSLOG=y 37 | # CONFIG_FEATURE_HAVE_RPC is not set 38 | 39 | # 40 | # Build Options 41 | # 42 | # CONFIG_STATIC is not set 43 | # CONFIG_PIE is not set 44 | # CONFIG_NOMMU is not set 45 | # CONFIG_BUILD_LIBBUSYBOX is not set 46 | # CONFIG_FEATURE_INDIVIDUAL is not set 47 | # CONFIG_FEATURE_SHARED_BUSYBOX is not set 48 | CONFIG_LFS=y 49 | CONFIG_CROSS_COMPILER_PREFIX="" 50 | CONFIG_SYSROOT="" 51 | CONFIG_EXTRA_CFLAGS="" 52 | CONFIG_EXTRA_LDFLAGS="" 53 | CONFIG_EXTRA_LDLIBS="" 54 | 55 | # 56 | # Installation Options ("make install" behavior) 57 | # 58 | CONFIG_INSTALL_APPLET_SYMLINKS=y 59 | # CONFIG_INSTALL_APPLET_HARDLINKS is not set 60 | # CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set 61 | # CONFIG_INSTALL_APPLET_DONT is not set 62 | # CONFIG_INSTALL_SH_APPLET_SYMLINK is not set 63 | # CONFIG_INSTALL_SH_APPLET_HARDLINK is not set 64 | # CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set 65 | CONFIG_PREFIX="./_install" 66 | 67 | # 68 | # Debugging Options 69 | # 70 | # CONFIG_DEBUG is not set 71 | # CONFIG_DEBUG_PESSIMIZE is not set 72 | # CONFIG_DEBUG_SANITIZE is not set 73 | # CONFIG_UNIT_TEST is not set 74 | # CONFIG_WERROR is not set 75 | CONFIG_NO_DEBUG_LIB=y 76 | # CONFIG_DMALLOC is not set 77 | # CONFIG_EFENCE is not set 78 | 79 | # 80 | # Busybox Library Tuning 81 | # 82 | # CONFIG_FEATURE_USE_BSS_TAIL is not set 83 | CONFIG_FEATURE_RTMINMAX=y 84 | CONFIG_FEATURE_BUFFERS_USE_MALLOC=y 85 | # CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set 86 | # CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set 87 | CONFIG_PASSWORD_MINLEN=6 88 | CONFIG_MD5_SMALL=1 89 | CONFIG_SHA3_SMALL=1 90 | # CONFIG_FEATURE_FAST_TOP is not set 91 | # CONFIG_FEATURE_ETC_NETWORKS is not set 92 | CONFIG_FEATURE_USE_TERMIOS=y 93 | CONFIG_FEATURE_EDITING=y 94 | CONFIG_FEATURE_EDITING_MAX_LEN=1024 95 | CONFIG_FEATURE_EDITING_VI=y 96 | CONFIG_FEATURE_EDITING_HISTORY=999 97 | CONFIG_FEATURE_EDITING_SAVEHISTORY=y 98 | # CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set 99 | CONFIG_FEATURE_REVERSE_SEARCH=y 100 | CONFIG_FEATURE_TAB_COMPLETION=y 101 | # CONFIG_FEATURE_USERNAME_COMPLETION is not set 102 | CONFIG_FEATURE_EDITING_FANCY_PROMPT=y 103 | # CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set 104 | # CONFIG_LOCALE_SUPPORT is not set 105 | # CONFIG_UNICODE_SUPPORT is not set 106 | # CONFIG_UNICODE_USING_LOCALE is not set 107 | # CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set 108 | CONFIG_SUBST_WCHAR=0 109 | CONFIG_LAST_SUPPORTED_WCHAR=0 110 | # CONFIG_UNICODE_COMBINING_WCHARS is not set 111 | # CONFIG_UNICODE_WIDE_WCHARS is not set 112 | # CONFIG_UNICODE_BIDI_SUPPORT is not set 113 | # CONFIG_UNICODE_NEUTRAL_TABLE is not set 114 | # CONFIG_UNICODE_PRESERVE_BROKEN is not set 115 | CONFIG_FEATURE_NON_POSIX_CP=y 116 | # CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set 117 | CONFIG_FEATURE_USE_SENDFILE=y 118 | CONFIG_FEATURE_COPYBUF_KB=4 119 | CONFIG_FEATURE_SKIP_ROOTFS=y 120 | CONFIG_MONOTONIC_SYSCALL=y 121 | CONFIG_IOCTL_HEX2STR_ERROR=y 122 | CONFIG_FEATURE_HWIB=y 123 | 124 | # 125 | # Applets 126 | # 127 | 128 | # 129 | # Archival Utilities 130 | # 131 | # CONFIG_FEATURE_SEAMLESS_XZ is not set 132 | # CONFIG_FEATURE_SEAMLESS_LZMA is not set 133 | # CONFIG_FEATURE_SEAMLESS_BZ2 is not set 134 | # CONFIG_FEATURE_SEAMLESS_GZ is not set 135 | # CONFIG_FEATURE_SEAMLESS_Z is not set 136 | CONFIG_AR=y 137 | # CONFIG_FEATURE_AR_LONG_FILENAMES is not set 138 | CONFIG_FEATURE_AR_CREATE=y 139 | # CONFIG_UNCOMPRESS is not set 140 | CONFIG_GUNZIP=y 141 | CONFIG_ZCAT=y 142 | CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y 143 | CONFIG_BUNZIP2=y 144 | CONFIG_BZCAT=y 145 | CONFIG_UNLZMA=y 146 | CONFIG_LZCAT=y 147 | CONFIG_LZMA=y 148 | # CONFIG_FEATURE_LZMA_FAST is not set 149 | CONFIG_UNXZ=y 150 | CONFIG_XZCAT=y 151 | CONFIG_XZ=y 152 | # CONFIG_BZIP2 is not set 153 | CONFIG_CPIO=y 154 | # CONFIG_FEATURE_CPIO_O is not set 155 | # CONFIG_FEATURE_CPIO_P is not set 156 | # CONFIG_DPKG is not set 157 | # CONFIG_DPKG_DEB is not set 158 | CONFIG_GZIP=y 159 | # CONFIG_FEATURE_GZIP_LONG_OPTIONS is not set 160 | CONFIG_GZIP_FAST=0 161 | # CONFIG_FEATURE_GZIP_LEVELS is not set 162 | # CONFIG_LZOP is not set 163 | CONFIG_UNLZOP=y 164 | CONFIG_LZOPCAT=y 165 | # CONFIG_LZOP_COMPR_HIGH is not set 166 | # CONFIG_RPM2CPIO is not set 167 | # CONFIG_RPM is not set 168 | CONFIG_TAR=y 169 | CONFIG_FEATURE_TAR_CREATE=y 170 | # CONFIG_FEATURE_TAR_AUTODETECT is not set 171 | CONFIG_FEATURE_TAR_FROM=y 172 | # CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY is not set 173 | # CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY is not set 174 | CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y 175 | CONFIG_FEATURE_TAR_LONG_OPTIONS=y 176 | CONFIG_FEATURE_TAR_TO_COMMAND=y 177 | # CONFIG_FEATURE_TAR_UNAME_GNAME is not set 178 | # CONFIG_FEATURE_TAR_NOPRESERVE_TIME is not set 179 | # CONFIG_FEATURE_TAR_SELINUX is not set 180 | CONFIG_UNZIP=y 181 | 182 | # 183 | # Coreutils 184 | # 185 | CONFIG_BASENAME=y 186 | # CONFIG_CAL is not set 187 | CONFIG_CAT=y 188 | CONFIG_CATV=y 189 | CONFIG_CHGRP=y 190 | CONFIG_CHMOD=y 191 | CONFIG_CHOWN=y 192 | # CONFIG_FEATURE_CHOWN_LONG_OPTIONS is not set 193 | CONFIG_CHROOT=y 194 | CONFIG_CKSUM=y 195 | # CONFIG_COMM is not set 196 | CONFIG_CP=y 197 | # CONFIG_FEATURE_CP_LONG_OPTIONS is not set 198 | CONFIG_CUT=y 199 | CONFIG_DATE=y 200 | CONFIG_FEATURE_DATE_ISOFMT=y 201 | # CONFIG_FEATURE_DATE_NANO is not set 202 | CONFIG_FEATURE_DATE_COMPAT=y 203 | CONFIG_DD=y 204 | CONFIG_FEATURE_DD_SIGNAL_HANDLING=y 205 | # CONFIG_FEATURE_DD_THIRD_STATUS_LINE is not set 206 | CONFIG_FEATURE_DD_IBS_OBS=y 207 | CONFIG_FEATURE_DD_STATUS=y 208 | CONFIG_DF=y 209 | # CONFIG_FEATURE_DF_FANCY is not set 210 | CONFIG_DIRNAME=y 211 | CONFIG_DOS2UNIX=y 212 | CONFIG_UNIX2DOS=y 213 | CONFIG_DU=y 214 | CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y 215 | CONFIG_ECHO=y 216 | CONFIG_FEATURE_FANCY_ECHO=y 217 | CONFIG_ENV=y 218 | # CONFIG_FEATURE_ENV_LONG_OPTIONS is not set 219 | # CONFIG_EXPAND is not set 220 | # CONFIG_FEATURE_EXPAND_LONG_OPTIONS is not set 221 | # CONFIG_UNEXPAND is not set 222 | # CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS is not set 223 | CONFIG_EXPR=y 224 | CONFIG_EXPR_MATH_SUPPORT_64=y 225 | CONFIG_FALSE=y 226 | CONFIG_FOLD=y 227 | # CONFIG_FSYNC is not set 228 | CONFIG_HEAD=y 229 | CONFIG_FEATURE_FANCY_HEAD=y 230 | CONFIG_HOSTID=y 231 | CONFIG_ID=y 232 | # CONFIG_GROUPS is not set 233 | CONFIG_INSTALL=y 234 | CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y 235 | CONFIG_LN=y 236 | CONFIG_LOGNAME=y 237 | CONFIG_LS=y 238 | CONFIG_FEATURE_LS_FILETYPES=y 239 | CONFIG_FEATURE_LS_FOLLOWLINKS=y 240 | CONFIG_FEATURE_LS_RECURSIVE=y 241 | CONFIG_FEATURE_LS_SORTFILES=y 242 | CONFIG_FEATURE_LS_TIMESTAMPS=y 243 | CONFIG_FEATURE_LS_USERNAME=y 244 | CONFIG_FEATURE_LS_COLOR=y 245 | CONFIG_FEATURE_LS_COLOR_IS_DEFAULT=y 246 | CONFIG_MD5SUM=y 247 | CONFIG_SHA1SUM=y 248 | CONFIG_SHA256SUM=y 249 | CONFIG_SHA512SUM=y 250 | CONFIG_SHA3SUM=y 251 | 252 | # 253 | # Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum 254 | # 255 | CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y 256 | CONFIG_MKDIR=y 257 | CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y 258 | CONFIG_MKFIFO=y 259 | CONFIG_MKNOD=y 260 | CONFIG_MV=y 261 | CONFIG_FEATURE_MV_LONG_OPTIONS=y 262 | CONFIG_NICE=y 263 | CONFIG_NOHUP=y 264 | CONFIG_OD=y 265 | CONFIG_PRINTENV=y 266 | CONFIG_PRINTF=y 267 | CONFIG_PWD=y 268 | CONFIG_READLINK=y 269 | CONFIG_FEATURE_READLINK_FOLLOW=y 270 | CONFIG_REALPATH=y 271 | CONFIG_RM=y 272 | CONFIG_RMDIR=y 273 | # CONFIG_FEATURE_RMDIR_LONG_OPTIONS is not set 274 | CONFIG_SEQ=y 275 | # CONFIG_SHUF is not set 276 | CONFIG_SLEEP=y 277 | CONFIG_FEATURE_FANCY_SLEEP=y 278 | CONFIG_FEATURE_FLOAT_SLEEP=y 279 | CONFIG_SORT=y 280 | CONFIG_FEATURE_SORT_BIG=y 281 | # CONFIG_SPLIT is not set 282 | # CONFIG_FEATURE_SPLIT_FANCY is not set 283 | # CONFIG_STAT is not set 284 | # CONFIG_FEATURE_STAT_FORMAT is not set 285 | # CONFIG_FEATURE_STAT_FILESYSTEM is not set 286 | CONFIG_STTY=y 287 | # CONFIG_SUM is not set 288 | CONFIG_SYNC=y 289 | # CONFIG_FEATURE_SYNC_FANCY is not set 290 | # CONFIG_TAC is not set 291 | CONFIG_TAIL=y 292 | CONFIG_FEATURE_FANCY_TAIL=y 293 | CONFIG_TEE=y 294 | CONFIG_FEATURE_TEE_USE_BLOCK_IO=y 295 | CONFIG_TEST=y 296 | CONFIG_TEST1=y 297 | CONFIG_TEST2=y 298 | CONFIG_FEATURE_TEST_64=y 299 | CONFIG_TOUCH=y 300 | # CONFIG_FEATURE_TOUCH_NODEREF is not set 301 | CONFIG_FEATURE_TOUCH_SUSV3=y 302 | CONFIG_TR=y 303 | CONFIG_FEATURE_TR_CLASSES=y 304 | CONFIG_FEATURE_TR_EQUIV=y 305 | CONFIG_TRUE=y 306 | CONFIG_TRUNCATE=y 307 | CONFIG_TTY=y 308 | CONFIG_UNAME=y 309 | CONFIG_UNAME_OSNAME="GNU/Linux" 310 | CONFIG_UNIQ=y 311 | CONFIG_UNLINK=y 312 | CONFIG_USLEEP=y 313 | CONFIG_UUDECODE=y 314 | # CONFIG_BASE64 is not set 315 | CONFIG_UUENCODE=y 316 | CONFIG_WC=y 317 | # CONFIG_FEATURE_WC_LARGE is not set 318 | CONFIG_WHOAMI=y 319 | CONFIG_WHO=y 320 | # CONFIG_USERS is not set 321 | CONFIG_YES=y 322 | 323 | # 324 | # Common options 325 | # 326 | CONFIG_FEATURE_VERBOSE=y 327 | 328 | # 329 | # Common options for cp and mv 330 | # 331 | CONFIG_FEATURE_PRESERVE_HARDLINKS=y 332 | 333 | # 334 | # Common options for ls, more and telnet 335 | # 336 | CONFIG_FEATURE_AUTOWIDTH=y 337 | 338 | # 339 | # Common options for df, du, ls 340 | # 341 | CONFIG_FEATURE_HUMAN_READABLE=y 342 | 343 | # 344 | # Console Utilities 345 | # 346 | CONFIG_CHVT=y 347 | CONFIG_CLEAR=y 348 | CONFIG_DEALLOCVT=y 349 | CONFIG_DUMPKMAP=y 350 | # CONFIG_FGCONSOLE is not set 351 | # CONFIG_KBD_MODE is not set 352 | CONFIG_LOADFONT=y 353 | # CONFIG_SETFONT is not set 354 | # CONFIG_FEATURE_SETFONT_TEXTUAL_MAP is not set 355 | CONFIG_DEFAULT_SETFONT_DIR="" 356 | 357 | # 358 | # Common options for loadfont and setfont 359 | # 360 | CONFIG_FEATURE_LOADFONT_PSF2=y 361 | CONFIG_FEATURE_LOADFONT_RAW=y 362 | CONFIG_LOADKMAP=y 363 | CONFIG_OPENVT=y 364 | CONFIG_RESET=y 365 | CONFIG_RESIZE=y 366 | CONFIG_FEATURE_RESIZE_PRINT=y 367 | CONFIG_SETCONSOLE=y 368 | # CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS is not set 369 | CONFIG_SETKEYCODES=y 370 | CONFIG_SETLOGCONS=y 371 | # CONFIG_SHOWKEY is not set 372 | 373 | # 374 | # Debian Utilities 375 | # 376 | CONFIG_MKTEMP=y 377 | CONFIG_PIPE_PROGRESS=y 378 | CONFIG_RUN_PARTS=y 379 | CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y 380 | # CONFIG_FEATURE_RUN_PARTS_FANCY is not set 381 | CONFIG_START_STOP_DAEMON=y 382 | CONFIG_FEATURE_START_STOP_DAEMON_FANCY=y 383 | CONFIG_FEATURE_START_STOP_DAEMON_LONG_OPTIONS=y 384 | CONFIG_WHICH=y 385 | 386 | # 387 | # Editors 388 | # 389 | CONFIG_AWK=y 390 | # CONFIG_FEATURE_AWK_LIBM is not set 391 | CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y 392 | CONFIG_CMP=y 393 | CONFIG_DIFF=y 394 | # CONFIG_FEATURE_DIFF_LONG_OPTIONS is not set 395 | CONFIG_FEATURE_DIFF_DIR=y 396 | # CONFIG_ED is not set 397 | CONFIG_PATCH=y 398 | CONFIG_SED=y 399 | CONFIG_VI=y 400 | CONFIG_FEATURE_VI_MAX_LEN=4096 401 | CONFIG_FEATURE_VI_8BIT=y 402 | CONFIG_FEATURE_VI_COLON=y 403 | CONFIG_FEATURE_VI_YANKMARK=y 404 | CONFIG_FEATURE_VI_SEARCH=y 405 | # CONFIG_FEATURE_VI_REGEX_SEARCH is not set 406 | CONFIG_FEATURE_VI_USE_SIGNALS=y 407 | CONFIG_FEATURE_VI_DOT_CMD=y 408 | CONFIG_FEATURE_VI_READONLY=y 409 | CONFIG_FEATURE_VI_SETOPTS=y 410 | CONFIG_FEATURE_VI_SET=y 411 | CONFIG_FEATURE_VI_WIN_RESIZE=y 412 | CONFIG_FEATURE_VI_ASK_TERMINAL=y 413 | CONFIG_FEATURE_VI_UNDO=y 414 | CONFIG_FEATURE_VI_UNDO_QUEUE=y 415 | CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256 416 | CONFIG_FEATURE_ALLOW_EXEC=y 417 | 418 | # 419 | # Finding Utilities 420 | # 421 | CONFIG_FIND=y 422 | CONFIG_FEATURE_FIND_PRINT0=y 423 | CONFIG_FEATURE_FIND_MTIME=y 424 | CONFIG_FEATURE_FIND_MMIN=y 425 | CONFIG_FEATURE_FIND_PERM=y 426 | CONFIG_FEATURE_FIND_TYPE=y 427 | CONFIG_FEATURE_FIND_XDEV=y 428 | CONFIG_FEATURE_FIND_MAXDEPTH=y 429 | CONFIG_FEATURE_FIND_NEWER=y 430 | # CONFIG_FEATURE_FIND_INUM is not set 431 | CONFIG_FEATURE_FIND_EXEC=y 432 | CONFIG_FEATURE_FIND_EXEC_PLUS=y 433 | CONFIG_FEATURE_FIND_USER=y 434 | CONFIG_FEATURE_FIND_GROUP=y 435 | CONFIG_FEATURE_FIND_NOT=y 436 | CONFIG_FEATURE_FIND_DEPTH=y 437 | CONFIG_FEATURE_FIND_PAREN=y 438 | CONFIG_FEATURE_FIND_SIZE=y 439 | CONFIG_FEATURE_FIND_PRUNE=y 440 | # CONFIG_FEATURE_FIND_DELETE is not set 441 | CONFIG_FEATURE_FIND_PATH=y 442 | CONFIG_FEATURE_FIND_REGEX=y 443 | # CONFIG_FEATURE_FIND_CONTEXT is not set 444 | # CONFIG_FEATURE_FIND_LINKS is not set 445 | CONFIG_GREP=y 446 | CONFIG_EGREP=y 447 | CONFIG_FGREP=y 448 | CONFIG_FEATURE_GREP_CONTEXT=y 449 | CONFIG_XARGS=y 450 | # CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION is not set 451 | CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y 452 | CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y 453 | CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y 454 | CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y 455 | 456 | # 457 | # Init Utilities 458 | # 459 | # CONFIG_BOOTCHARTD is not set 460 | # CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER is not set 461 | # CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE is not set 462 | CONFIG_HALT=y 463 | CONFIG_POWEROFF=y 464 | CONFIG_REBOOT=y 465 | # CONFIG_FEATURE_CALL_TELINIT is not set 466 | CONFIG_TELINIT_PATH="" 467 | CONFIG_INIT=y 468 | CONFIG_LINUXRC=y 469 | # CONFIG_FEATURE_USE_INITTAB is not set 470 | # CONFIG_FEATURE_KILL_REMOVED is not set 471 | CONFIG_FEATURE_KILL_DELAY=0 472 | CONFIG_FEATURE_INIT_SCTTY=y 473 | CONFIG_FEATURE_INIT_SYSLOG=y 474 | CONFIG_FEATURE_EXTRA_QUIET=y 475 | # CONFIG_FEATURE_INIT_COREDUMPS is not set 476 | CONFIG_INIT_TERMINAL_TYPE="linux" 477 | CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y 478 | CONFIG_MESG=y 479 | CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y 480 | 481 | # 482 | # Login/Password Management Utilities 483 | # 484 | CONFIG_FEATURE_SHADOWPASSWDS=y 485 | # CONFIG_USE_BB_PWD_GRP is not set 486 | # CONFIG_USE_BB_SHADOW is not set 487 | CONFIG_USE_BB_CRYPT=y 488 | # CONFIG_USE_BB_CRYPT_SHA is not set 489 | CONFIG_ADDGROUP=y 490 | # CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS is not set 491 | # CONFIG_FEATURE_ADDUSER_TO_GROUP is not set 492 | # CONFIG_ADD_SHELL is not set 493 | # CONFIG_REMOVE_SHELL is not set 494 | CONFIG_ADDUSER=y 495 | # CONFIG_FEATURE_ADDUSER_LONG_OPTIONS is not set 496 | # CONFIG_FEATURE_CHECK_NAMES is not set 497 | CONFIG_LAST_ID=60000 498 | CONFIG_FIRST_SYSTEM_ID=100 499 | CONFIG_LAST_SYSTEM_ID=999 500 | # CONFIG_CHPASSWD is not set 501 | CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="md5" 502 | # CONFIG_CRYPTPW is not set 503 | CONFIG_MKPASSWD=y 504 | CONFIG_DELUSER=y 505 | CONFIG_DELGROUP=y 506 | # CONFIG_FEATURE_DEL_USER_FROM_GROUP is not set 507 | CONFIG_GETTY=y 508 | CONFIG_LOGIN=y 509 | # CONFIG_LOGIN_SESSION_AS_CHILD is not set 510 | # CONFIG_LOGIN_SCRIPTS is not set 511 | CONFIG_FEATURE_NOLOGIN=y 512 | CONFIG_FEATURE_SECURETTY=y 513 | CONFIG_PASSWD=y 514 | CONFIG_FEATURE_PASSWD_WEAK_CHECK=y 515 | CONFIG_SU=y 516 | CONFIG_FEATURE_SU_SYSLOG=y 517 | CONFIG_FEATURE_SU_CHECKS_SHELLS=y 518 | CONFIG_SULOGIN=y 519 | CONFIG_VLOCK=y 520 | 521 | # 522 | # Linux Ext2 FS Progs 523 | # 524 | CONFIG_CHATTR=y 525 | CONFIG_FSCK=y 526 | CONFIG_LSATTR=y 527 | # CONFIG_TUNE2FS is not set 528 | 529 | # 530 | # Linux Module Utilities 531 | # 532 | # CONFIG_MODPROBE_SMALL is not set 533 | # CONFIG_DEPMOD is not set 534 | CONFIG_INSMOD=y 535 | CONFIG_LSMOD=y 536 | CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT=y 537 | # CONFIG_MODINFO is not set 538 | CONFIG_MODPROBE=y 539 | # CONFIG_FEATURE_MODPROBE_BLACKLIST is not set 540 | # CONFIG_FEATURE_MODPROBE_SMALL_OPTIONS_ON_CMDLINE is not set 541 | # CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED is not set 542 | CONFIG_RMMOD=y 543 | 544 | # 545 | # Options common to multiple modutils 546 | # 547 | # CONFIG_FEATURE_2_4_MODULES is not set 548 | # CONFIG_FEATURE_INSMOD_TRY_MMAP is not set 549 | # CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set 550 | # CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set 551 | # CONFIG_FEATURE_INSMOD_LOADINKMEM is not set 552 | # CONFIG_FEATURE_INSMOD_LOAD_MAP is not set 553 | # CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set 554 | CONFIG_FEATURE_CHECK_TAINTED_MODULE=y 555 | CONFIG_FEATURE_MODUTILS_ALIAS=y 556 | CONFIG_FEATURE_MODUTILS_SYMBOLS=y 557 | CONFIG_DEFAULT_MODULES_DIR="/lib/modules" 558 | CONFIG_DEFAULT_DEPMOD_FILE="modules.dep" 559 | 560 | # 561 | # Linux System Utilities 562 | # 563 | # CONFIG_ACPID is not set 564 | # CONFIG_FEATURE_ACPID_COMPAT is not set 565 | # CONFIG_BLKDISCARD is not set 566 | CONFIG_BLKID=y 567 | # CONFIG_FEATURE_BLKID_TYPE is not set 568 | # CONFIG_BLOCKDEV is not set 569 | CONFIG_DMESG=y 570 | CONFIG_FEATURE_DMESG_PRETTY=y 571 | # CONFIG_FATATTR is not set 572 | CONFIG_FBSET=y 573 | CONFIG_FEATURE_FBSET_FANCY=y 574 | CONFIG_FEATURE_FBSET_READMODE=y 575 | CONFIG_FDFORMAT=y 576 | CONFIG_FDISK=y 577 | # CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set 578 | CONFIG_FEATURE_FDISK_WRITABLE=y 579 | # CONFIG_FEATURE_AIX_LABEL is not set 580 | # CONFIG_FEATURE_SGI_LABEL is not set 581 | # CONFIG_FEATURE_SUN_LABEL is not set 582 | # CONFIG_FEATURE_OSF_LABEL is not set 583 | CONFIG_FEATURE_GPT_LABEL=y 584 | CONFIG_FEATURE_FDISK_ADVANCED=y 585 | # CONFIG_FINDFS is not set 586 | CONFIG_FLOCK=y 587 | CONFIG_FDFLUSH=y 588 | CONFIG_FREERAMDISK=y 589 | # CONFIG_FSCK_MINIX is not set 590 | CONFIG_FSTRIM=y 591 | CONFIG_GETOPT=y 592 | CONFIG_FEATURE_GETOPT_LONG=y 593 | CONFIG_HEXDUMP=y 594 | # CONFIG_FEATURE_HEXDUMP_REVERSE is not set 595 | # CONFIG_HD is not set 596 | CONFIG_HWCLOCK=y 597 | CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y 598 | CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS=y 599 | CONFIG_IPCRM=y 600 | CONFIG_IPCS=y 601 | CONFIG_LOSETUP=y 602 | CONFIG_LSPCI=y 603 | CONFIG_LSUSB=y 604 | CONFIG_MDEV=y 605 | CONFIG_FEATURE_MDEV_CONF=y 606 | CONFIG_FEATURE_MDEV_RENAME=y 607 | # CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set 608 | CONFIG_FEATURE_MDEV_EXEC=y 609 | CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y 610 | CONFIG_MKE2FS=y 611 | # CONFIG_MKFS_EXT2 is not set 612 | # CONFIG_MKFS_MINIX is not set 613 | # CONFIG_FEATURE_MINIX2 is not set 614 | # CONFIG_MKFS_REISER is not set 615 | CONFIG_MKDOSFS=y 616 | # CONFIG_MKFS_VFAT is not set 617 | CONFIG_MKSWAP=y 618 | # CONFIG_FEATURE_MKSWAP_UUID is not set 619 | CONFIG_MORE=y 620 | CONFIG_MOUNT=y 621 | # CONFIG_FEATURE_MOUNT_FAKE is not set 622 | # CONFIG_FEATURE_MOUNT_VERBOSE is not set 623 | # CONFIG_FEATURE_MOUNT_HELPERS is not set 624 | # CONFIG_FEATURE_MOUNT_LABEL is not set 625 | # CONFIG_FEATURE_MOUNT_NFS is not set 626 | # CONFIG_FEATURE_MOUNT_CIFS is not set 627 | # CONFIG_FEATURE_MOUNT_FLAGS is not set 628 | # CONFIG_FEATURE_MOUNT_FSTAB is not set 629 | # CONFIG_FEATURE_MOUNT_OTHERTAB is not set 630 | # CONFIG_NSENTER is not set 631 | # CONFIG_FEATURE_NSENTER_LONG_OPTS is not set 632 | CONFIG_PIVOT_ROOT=y 633 | CONFIG_RDATE=y 634 | # CONFIG_RDEV is not set 635 | CONFIG_READPROFILE=y 636 | # CONFIG_REV is not set 637 | # CONFIG_RTCWAKE is not set 638 | # CONFIG_SCRIPT is not set 639 | # CONFIG_SCRIPTREPLAY is not set 640 | CONFIG_SETARCH=y 641 | CONFIG_LINUX32=y 642 | CONFIG_LINUX64=y 643 | CONFIG_SWAPON=y 644 | # CONFIG_FEATURE_SWAPON_DISCARD is not set 645 | # CONFIG_FEATURE_SWAPON_PRI is not set 646 | CONFIG_SWAPOFF=y 647 | CONFIG_SWITCH_ROOT=y 648 | CONFIG_UEVENT=y 649 | CONFIG_UMOUNT=y 650 | CONFIG_FEATURE_UMOUNT_ALL=y 651 | # CONFIG_UNSHARE is not set 652 | 653 | # 654 | # Common options for mount/umount 655 | # 656 | CONFIG_FEATURE_MOUNT_LOOP=y 657 | CONFIG_FEATURE_MOUNT_LOOP_CREATE=y 658 | # CONFIG_FEATURE_MTAB_SUPPORT is not set 659 | CONFIG_VOLUMEID=y 660 | 661 | # 662 | # Filesystem/Volume identification 663 | # 664 | # CONFIG_FEATURE_VOLUMEID_BCACHE is not set 665 | # CONFIG_FEATURE_VOLUMEID_BTRFS is not set 666 | # CONFIG_FEATURE_VOLUMEID_CRAMFS is not set 667 | CONFIG_FEATURE_VOLUMEID_EXFAT=y 668 | CONFIG_FEATURE_VOLUMEID_EXT=y 669 | CONFIG_FEATURE_VOLUMEID_F2FS=y 670 | CONFIG_FEATURE_VOLUMEID_FAT=y 671 | # CONFIG_FEATURE_VOLUMEID_HFS is not set 672 | # CONFIG_FEATURE_VOLUMEID_ISO9660 is not set 673 | # CONFIG_FEATURE_VOLUMEID_JFS is not set 674 | # CONFIG_FEATURE_VOLUMEID_LINUXRAID is not set 675 | # CONFIG_FEATURE_VOLUMEID_LINUXSWAP is not set 676 | # CONFIG_FEATURE_VOLUMEID_LUKS is not set 677 | # CONFIG_FEATURE_VOLUMEID_NILFS is not set 678 | # CONFIG_FEATURE_VOLUMEID_NTFS is not set 679 | # CONFIG_FEATURE_VOLUMEID_OCFS2 is not set 680 | # CONFIG_FEATURE_VOLUMEID_REISERFS is not set 681 | # CONFIG_FEATURE_VOLUMEID_ROMFS is not set 682 | # CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set 683 | # CONFIG_FEATURE_VOLUMEID_SYSV is not set 684 | CONFIG_FEATURE_VOLUMEID_UBIFS=y 685 | # CONFIG_FEATURE_VOLUMEID_UDF is not set 686 | # CONFIG_FEATURE_VOLUMEID_XFS is not set 687 | 688 | # 689 | # Miscellaneous Utilities 690 | # 691 | # CONFIG_ADJTIMEX is not set 692 | # CONFIG_BBCONFIG is not set 693 | # CONFIG_FEATURE_COMPRESS_BBCONFIG is not set 694 | # CONFIG_BEEP is not set 695 | CONFIG_FEATURE_BEEP_FREQ=0 696 | CONFIG_FEATURE_BEEP_LENGTH_MS=0 697 | # CONFIG_CHAT is not set 698 | # CONFIG_FEATURE_CHAT_NOFAIL is not set 699 | # CONFIG_FEATURE_CHAT_TTY_HIFI is not set 700 | # CONFIG_FEATURE_CHAT_IMPLICIT_CR is not set 701 | # CONFIG_FEATURE_CHAT_SWALLOW_OPTS is not set 702 | # CONFIG_FEATURE_CHAT_SEND_ESCAPES is not set 703 | # CONFIG_FEATURE_CHAT_VAR_ABORT_LEN is not set 704 | # CONFIG_FEATURE_CHAT_CLR_ABORT is not set 705 | CONFIG_CHRT=y 706 | # CONFIG_CONSPY is not set 707 | CONFIG_CROND=y 708 | # CONFIG_FEATURE_CROND_D is not set 709 | # CONFIG_FEATURE_CROND_CALL_SENDMAIL is not set 710 | CONFIG_FEATURE_CROND_DIR="/var/spool/cron" 711 | CONFIG_CRONTAB=y 712 | CONFIG_DC=y 713 | # CONFIG_FEATURE_DC_LIBM is not set 714 | # CONFIG_DEVFSD is not set 715 | # CONFIG_DEVFSD_MODLOAD is not set 716 | # CONFIG_DEVFSD_FG_NP is not set 717 | # CONFIG_DEVFSD_VERBOSE is not set 718 | # CONFIG_FEATURE_DEVFS is not set 719 | CONFIG_DEVMEM=y 720 | CONFIG_EJECT=y 721 | # CONFIG_FEATURE_EJECT_SCSI is not set 722 | # CONFIG_FBSPLASH is not set 723 | # CONFIG_FLASHCP is not set 724 | # CONFIG_FLASH_ERASEALL is not set 725 | # CONFIG_FLASH_LOCK is not set 726 | # CONFIG_FLASH_UNLOCK is not set 727 | CONFIG_HDPARM=y 728 | CONFIG_FEATURE_HDPARM_GET_IDENTITY=y 729 | # CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF is not set 730 | # CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF is not set 731 | # CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET is not set 732 | # CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF is not set 733 | # CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA is not set 734 | CONFIG_I2CGET=y 735 | CONFIG_I2CSET=y 736 | CONFIG_I2CDUMP=y 737 | CONFIG_I2CDETECT=y 738 | # CONFIG_INOTIFYD is not set 739 | # CONFIG_IONICE is not set 740 | CONFIG_LAST=y 741 | # CONFIG_FEATURE_LAST_FANCY is not set 742 | CONFIG_LESS=y 743 | CONFIG_FEATURE_LESS_MAXLINES=9999999 744 | CONFIG_FEATURE_LESS_BRACKETS=y 745 | CONFIG_FEATURE_LESS_FLAGS=y 746 | CONFIG_FEATURE_LESS_TRUNCATE=y 747 | # CONFIG_FEATURE_LESS_MARKS is not set 748 | CONFIG_FEATURE_LESS_REGEXP=y 749 | # CONFIG_FEATURE_LESS_WINCH is not set 750 | # CONFIG_FEATURE_LESS_ASK_TERMINAL is not set 751 | # CONFIG_FEATURE_LESS_DASHCMD is not set 752 | # CONFIG_FEATURE_LESS_LINENUMS is not set 753 | CONFIG_MAKEDEVS=y 754 | # CONFIG_FEATURE_MAKEDEVS_LEAF is not set 755 | CONFIG_FEATURE_MAKEDEVS_TABLE=y 756 | # CONFIG_MAN is not set 757 | CONFIG_MICROCOM=y 758 | CONFIG_MOUNTPOINT=y 759 | CONFIG_MT=y 760 | # CONFIG_NANDWRITE is not set 761 | # CONFIG_NANDDUMP is not set 762 | # CONFIG_RAIDAUTORUN is not set 763 | # CONFIG_READAHEAD is not set 764 | # CONFIG_RFKILL is not set 765 | CONFIG_RUNLEVEL=y 766 | # CONFIG_RX is not set 767 | CONFIG_SETSERIAL=y 768 | CONFIG_SETSID=y 769 | CONFIG_STRINGS=y 770 | CONFIG_TASKSET=y 771 | CONFIG_FEATURE_TASKSET_FANCY=y 772 | CONFIG_TIME=y 773 | # CONFIG_TIMEOUT is not set 774 | # CONFIG_TTYSIZE is not set 775 | CONFIG_UBIRENAME=y 776 | # CONFIG_UBIATTACH is not set 777 | # CONFIG_UBIDETACH is not set 778 | # CONFIG_UBIMKVOL is not set 779 | # CONFIG_UBIRMVOL is not set 780 | # CONFIG_UBIRSVOL is not set 781 | # CONFIG_UBIUPDATEVOL is not set 782 | # CONFIG_VOLNAME is not set 783 | # CONFIG_WALL is not set 784 | CONFIG_WATCHDOG=y 785 | 786 | # 787 | # Networking Utilities 788 | # 789 | CONFIG_FEATURE_IPV6=y 790 | # CONFIG_FEATURE_UNIX_LOCAL is not set 791 | CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y 792 | # CONFIG_VERBOSE_RESOLUTION_ERRORS is not set 793 | CONFIG_ARP=y 794 | CONFIG_ARPING=y 795 | # CONFIG_BRCTL is not set 796 | # CONFIG_FEATURE_BRCTL_FANCY is not set 797 | # CONFIG_FEATURE_BRCTL_SHOW is not set 798 | CONFIG_DNSD=y 799 | CONFIG_ETHER_WAKE=y 800 | # CONFIG_FTPD is not set 801 | # CONFIG_FEATURE_FTPD_WRITE is not set 802 | # CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST is not set 803 | # CONFIG_FEATURE_FTPD_AUTHENTICATION is not set 804 | # CONFIG_FTPGET is not set 805 | # CONFIG_FTPPUT is not set 806 | # CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS is not set 807 | CONFIG_HOSTNAME=y 808 | CONFIG_DNSDOMAINNAME=y 809 | # CONFIG_HTTPD is not set 810 | # CONFIG_FEATURE_HTTPD_RANGES is not set 811 | # CONFIG_FEATURE_HTTPD_SETUID is not set 812 | # CONFIG_FEATURE_HTTPD_BASIC_AUTH is not set 813 | # CONFIG_FEATURE_HTTPD_AUTH_MD5 is not set 814 | # CONFIG_FEATURE_HTTPD_CGI is not set 815 | # CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR is not set 816 | # CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV is not set 817 | # CONFIG_FEATURE_HTTPD_ENCODE_URL_STR is not set 818 | # CONFIG_FEATURE_HTTPD_ERROR_PAGES is not set 819 | # CONFIG_FEATURE_HTTPD_PROXY is not set 820 | # CONFIG_FEATURE_HTTPD_GZIP is not set 821 | CONFIG_IFCONFIG=y 822 | CONFIG_FEATURE_IFCONFIG_STATUS=y 823 | CONFIG_FEATURE_IFCONFIG_SLIP=y 824 | CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y 825 | CONFIG_FEATURE_IFCONFIG_HW=y 826 | # CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS is not set 827 | # CONFIG_IFENSLAVE is not set 828 | # CONFIG_IFPLUGD is not set 829 | CONFIG_IFUP=y 830 | CONFIG_IFDOWN=y 831 | CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate" 832 | CONFIG_FEATURE_IFUPDOWN_IP=y 833 | CONFIG_FEATURE_IFUPDOWN_IPV4=y 834 | CONFIG_FEATURE_IFUPDOWN_IPV6=y 835 | CONFIG_FEATURE_IFUPDOWN_MAPPING=y 836 | # CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set 837 | CONFIG_INETD=y 838 | CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y 839 | CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y 840 | CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y 841 | CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y 842 | CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y 843 | # CONFIG_FEATURE_INETD_RPC is not set 844 | CONFIG_IP=y 845 | CONFIG_IPADDR=y 846 | CONFIG_IPLINK=y 847 | CONFIG_IPROUTE=y 848 | CONFIG_IPTUNNEL=y 849 | CONFIG_IPRULE=y 850 | CONFIG_IPNEIGH=y 851 | CONFIG_FEATURE_IP_ADDRESS=y 852 | CONFIG_FEATURE_IP_LINK=y 853 | CONFIG_FEATURE_IP_ROUTE=y 854 | CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2" 855 | CONFIG_FEATURE_IP_TUNNEL=y 856 | CONFIG_FEATURE_IP_RULE=y 857 | CONFIG_FEATURE_IP_NEIGH=y 858 | # CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set 859 | # CONFIG_IPCALC is not set 860 | # CONFIG_FEATURE_IPCALC_FANCY is not set 861 | # CONFIG_FEATURE_IPCALC_LONG_OPTIONS is not set 862 | # CONFIG_FAKEIDENTD is not set 863 | CONFIG_NAMEIF=y 864 | # CONFIG_FEATURE_NAMEIF_EXTENDED is not set 865 | # CONFIG_NBDCLIENT is not set 866 | # CONFIG_NC is not set 867 | # CONFIG_NC_SERVER is not set 868 | # CONFIG_NC_EXTRA is not set 869 | # CONFIG_NC_110_COMPAT is not set 870 | CONFIG_NETSTAT=y 871 | # CONFIG_FEATURE_NETSTAT_WIDE is not set 872 | # CONFIG_FEATURE_NETSTAT_PRG is not set 873 | CONFIG_NSLOOKUP=y 874 | # CONFIG_NTPD is not set 875 | # CONFIG_FEATURE_NTPD_SERVER is not set 876 | # CONFIG_FEATURE_NTPD_CONF is not set 877 | CONFIG_PING=y 878 | # CONFIG_PING6 is not set 879 | CONFIG_FEATURE_FANCY_PING=y 880 | # CONFIG_PSCAN is not set 881 | CONFIG_ROUTE=y 882 | # CONFIG_SLATTACH is not set 883 | # CONFIG_TCPSVD is not set 884 | # CONFIG_UDPSVD is not set 885 | CONFIG_TELNET=y 886 | CONFIG_FEATURE_TELNET_TTYPE=y 887 | CONFIG_FEATURE_TELNET_AUTOLOGIN=y 888 | # CONFIG_TELNETD is not set 889 | # CONFIG_FEATURE_TELNETD_STANDALONE is not set 890 | # CONFIG_FEATURE_TELNETD_INETD_WAIT is not set 891 | CONFIG_TFTP=y 892 | # CONFIG_TFTPD is not set 893 | 894 | # 895 | # Common options for tftp/tftpd 896 | # 897 | CONFIG_FEATURE_TFTP_GET=y 898 | CONFIG_FEATURE_TFTP_PUT=y 899 | CONFIG_FEATURE_TFTP_BLOCKSIZE=y 900 | # CONFIG_FEATURE_TFTP_PROGRESS_BAR is not set 901 | # CONFIG_TFTP_DEBUG is not set 902 | CONFIG_TRACEROUTE=y 903 | # CONFIG_TRACEROUTE6 is not set 904 | # CONFIG_FEATURE_TRACEROUTE_VERBOSE is not set 905 | # CONFIG_FEATURE_TRACEROUTE_USE_ICMP is not set 906 | # CONFIG_TUNCTL is not set 907 | # CONFIG_FEATURE_TUNCTL_UG is not set 908 | CONFIG_VCONFIG=y 909 | CONFIG_WGET=y 910 | CONFIG_FEATURE_WGET_STATUSBAR=y 911 | CONFIG_FEATURE_WGET_AUTHENTICATION=y 912 | CONFIG_FEATURE_WGET_LONG_OPTIONS=y 913 | CONFIG_FEATURE_WGET_TIMEOUT=y 914 | # CONFIG_FEATURE_WGET_OPENSSL is not set 915 | # CONFIG_FEATURE_WGET_SSL_HELPER is not set 916 | # CONFIG_WHOIS is not set 917 | # CONFIG_ZCIP is not set 918 | # CONFIG_UDHCPC6 is not set 919 | # CONFIG_UDHCPD is not set 920 | # CONFIG_DHCPRELAY is not set 921 | # CONFIG_DUMPLEASES is not set 922 | # CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY is not set 923 | # CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set 924 | CONFIG_DHCPD_LEASES_FILE="" 925 | CONFIG_UDHCPC=y 926 | CONFIG_FEATURE_UDHCPC_ARPING=y 927 | CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y 928 | # CONFIG_FEATURE_UDHCP_PORT is not set 929 | CONFIG_UDHCP_DEBUG=0 930 | # CONFIG_FEATURE_UDHCP_RFC3397 is not set 931 | CONFIG_FEATURE_UDHCP_8021Q=y 932 | CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script" 933 | CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80 934 | CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n" 935 | 936 | # 937 | # Print Utilities 938 | # 939 | # CONFIG_LPD is not set 940 | # CONFIG_LPR is not set 941 | # CONFIG_LPQ is not set 942 | 943 | # 944 | # Mail Utilities 945 | # 946 | # CONFIG_MAKEMIME is not set 947 | # CONFIG_POPMAILDIR is not set 948 | # CONFIG_FEATURE_POPMAILDIR_DELIVERY is not set 949 | # CONFIG_REFORMIME is not set 950 | # CONFIG_FEATURE_REFORMIME_COMPAT is not set 951 | # CONFIG_SENDMAIL is not set 952 | CONFIG_FEATURE_MIME_CHARSET="" 953 | 954 | # 955 | # Process Utilities 956 | # 957 | CONFIG_FREE=y 958 | CONFIG_FUSER=y 959 | # CONFIG_IOSTAT is not set 960 | CONFIG_KILL=y 961 | CONFIG_KILLALL=y 962 | CONFIG_KILLALL5=y 963 | CONFIG_LSOF=y 964 | # CONFIG_MPSTAT is not set 965 | # CONFIG_NMETER is not set 966 | # CONFIG_PGREP is not set 967 | # CONFIG_PKILL is not set 968 | CONFIG_PIDOF=y 969 | CONFIG_FEATURE_PIDOF_SINGLE=y 970 | CONFIG_FEATURE_PIDOF_OMIT=y 971 | # CONFIG_PMAP is not set 972 | # CONFIG_POWERTOP is not set 973 | CONFIG_PS=y 974 | # CONFIG_FEATURE_PS_WIDE is not set 975 | # CONFIG_FEATURE_PS_LONG is not set 976 | # CONFIG_FEATURE_PS_TIME is not set 977 | # CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS is not set 978 | # CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set 979 | # CONFIG_PSTREE is not set 980 | # CONFIG_PWDX is not set 981 | CONFIG_RENICE=y 982 | # CONFIG_SMEMCAP is not set 983 | CONFIG_BB_SYSCTL=y 984 | CONFIG_TOP=y 985 | CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y 986 | CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y 987 | # CONFIG_FEATURE_TOP_SMP_CPU is not set 988 | # CONFIG_FEATURE_TOP_DECIMALS is not set 989 | # CONFIG_FEATURE_TOP_SMP_PROCESS is not set 990 | # CONFIG_FEATURE_TOPMEM is not set 991 | CONFIG_UPTIME=y 992 | # CONFIG_FEATURE_UPTIME_UTMP_SUPPORT is not set 993 | CONFIG_WATCH=y 994 | # CONFIG_FEATURE_SHOW_THREADS is not set 995 | 996 | # 997 | # Runit Utilities 998 | # 999 | # CONFIG_CHPST is not set 1000 | # CONFIG_SETUIDGID is not set 1001 | # CONFIG_ENVUIDGID is not set 1002 | # CONFIG_ENVDIR is not set 1003 | # CONFIG_SOFTLIMIT is not set 1004 | # CONFIG_RUNSV is not set 1005 | # CONFIG_RUNSVDIR is not set 1006 | # CONFIG_FEATURE_RUNSVDIR_LOG is not set 1007 | # CONFIG_SV is not set 1008 | CONFIG_SV_DEFAULT_SERVICE_DIR="" 1009 | CONFIG_SVC=y 1010 | # CONFIG_SVLOGD is not set 1011 | # CONFIG_CHCON is not set 1012 | # CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set 1013 | # CONFIG_GETENFORCE is not set 1014 | # CONFIG_GETSEBOOL is not set 1015 | # CONFIG_LOAD_POLICY is not set 1016 | # CONFIG_MATCHPATHCON is not set 1017 | # CONFIG_RUNCON is not set 1018 | # CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set 1019 | # CONFIG_SELINUXENABLED is not set 1020 | # CONFIG_SESTATUS is not set 1021 | # CONFIG_SETENFORCE is not set 1022 | # CONFIG_SETFILES is not set 1023 | # CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set 1024 | # CONFIG_RESTORECON is not set 1025 | # CONFIG_SETSEBOOL is not set 1026 | 1027 | # 1028 | # Shells 1029 | # 1030 | CONFIG_SH_IS_ASH=y 1031 | # CONFIG_SH_IS_HUSH is not set 1032 | # CONFIG_SH_IS_NONE is not set 1033 | # CONFIG_BASH_IS_ASH is not set 1034 | # CONFIG_BASH_IS_HUSH is not set 1035 | CONFIG_BASH_IS_NONE=y 1036 | CONFIG_ASH=y 1037 | CONFIG_ASH_OPTIMIZE_FOR_SIZE=y 1038 | CONFIG_ASH_INTERNAL_GLOB=y 1039 | CONFIG_ASH_RANDOM_SUPPORT=y 1040 | CONFIG_ASH_EXPAND_PRMT=y 1041 | CONFIG_ASH_BASH_COMPAT=y 1042 | CONFIG_ASH_IDLE_TIMEOUT=y 1043 | CONFIG_ASH_JOB_CONTROL=y 1044 | CONFIG_ASH_ALIAS=y 1045 | CONFIG_ASH_GETOPTS=y 1046 | CONFIG_ASH_BUILTIN_ECHO=y 1047 | CONFIG_ASH_BUILTIN_PRINTF=y 1048 | CONFIG_ASH_BUILTIN_TEST=y 1049 | CONFIG_ASH_HELP=y 1050 | CONFIG_ASH_CMDCMD=y 1051 | # CONFIG_ASH_MAIL is not set 1052 | # CONFIG_CTTYHACK is not set 1053 | # CONFIG_HUSH is not set 1054 | # CONFIG_HUSH_BASH_COMPAT is not set 1055 | # CONFIG_HUSH_BRACE_EXPANSION is not set 1056 | # CONFIG_HUSH_HELP is not set 1057 | # CONFIG_HUSH_INTERACTIVE is not set 1058 | # CONFIG_HUSH_SAVEHISTORY is not set 1059 | # CONFIG_HUSH_JOB is not set 1060 | # CONFIG_HUSH_TICK is not set 1061 | # CONFIG_HUSH_IF is not set 1062 | # CONFIG_HUSH_LOOPS is not set 1063 | # CONFIG_HUSH_CASE is not set 1064 | # CONFIG_HUSH_FUNCTIONS is not set 1065 | # CONFIG_HUSH_LOCAL is not set 1066 | # CONFIG_HUSH_RANDOM_SUPPORT is not set 1067 | # CONFIG_HUSH_EXPORT_N is not set 1068 | # CONFIG_HUSH_MODE_X is not set 1069 | # CONFIG_MSH is not set 1070 | CONFIG_FEATURE_SH_MATH=y 1071 | CONFIG_FEATURE_SH_MATH_64=y 1072 | CONFIG_FEATURE_SH_EXTRA_QUIET=y 1073 | # CONFIG_FEATURE_SH_STANDALONE is not set 1074 | # CONFIG_FEATURE_SH_NOFORK is not set 1075 | # CONFIG_FEATURE_SH_HISTFILESIZE is not set 1076 | 1077 | # 1078 | # System Logging Utilities 1079 | # 1080 | CONFIG_KLOGD=y 1081 | CONFIG_FEATURE_KLOGD_KLOGCTL=y 1082 | CONFIG_LOGGER=y 1083 | # CONFIG_LOGREAD is not set 1084 | # CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING is not set 1085 | CONFIG_SYSLOGD=y 1086 | CONFIG_FEATURE_ROTATE_LOGFILE=y 1087 | CONFIG_FEATURE_REMOTE_LOG=y 1088 | # CONFIG_FEATURE_SYSLOGD_DUP is not set 1089 | # CONFIG_FEATURE_SYSLOGD_CFG is not set 1090 | CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256 1091 | # CONFIG_FEATURE_IPC_SYSLOG is not set 1092 | CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=0 1093 | # CONFIG_FEATURE_KMSG_SYSLOG is not set 1094 | -------------------------------------------------------------------------------- /zc706/Makefile: -------------------------------------------------------------------------------- 1 | BOARD = zc706 2 | UBOOT_CONFIG = zc70x 3 | BOARD_MODEL = xilinx.com:zc706:part0:1.0 4 | PART = xc7z045ffg900-2 5 | #TOP_MODULE_PROJECT = zynq 6 | #CONFIG = ZynqFPGAConfig 7 | TOP_MODULE_PROJECT = zynq.boom 8 | CONFIG ?= SmallBoomZynqConfig 9 | #CONFIG ?= MediumBoomZynqConfig 10 | 11 | include ../common/Makefrag 12 | -------------------------------------------------------------------------------- /zc706/soft_config/zc706_devicetree.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Generator version: 1.1 3 | * 4 | * (C) Copyright 2007-2013 Xilinx, Inc. 5 | * (C) Copyright 2007-2013 Michal Simek 6 | * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 7 | * 8 | * Michal SIMEK 9 | * Modified for RISC-V Rocket Support by Sagar Karandikar 10 | * 11 | * CAUTION: This file is automatically generated by libgen. 12 | * Version: Xilinx EDK 14.5 EDK_P.58f 13 | * 14 | */ 15 | 16 | /dts-v1/; 17 | / { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "xlnx,zynq-7000"; 21 | model = "Xilinx Zynq"; 22 | aliases { 23 | ethernet0 = &ps7_ethernet_0; 24 | i2c0 = &ps7_i2c_0; 25 | serial0 = &ps7_uart_1; 26 | spi0 = &ps7_qspi_0; 27 | } ; 28 | chosen { 29 | bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; 30 | linux,stdout-path = "/amba@0/serial@e0001000"; 31 | } ; 32 | cpus { 33 | #address-cells = <1>; 34 | #size-cells = <0>; 35 | ps7_cortexa9_0: cpu@0 { 36 | bus-handle = <&ps7_axi_interconnect_0>; 37 | clock-latency = <1000>; 38 | clocks = <&clkc 3>; 39 | compatible = "arm,cortex-a9"; 40 | device_type = "cpu"; 41 | interrupt-handle = <&ps7_scugic_0>; 42 | operating-points = <666667 1000000 333334 1000000 222223 1000000>; 43 | reg = <0x0>; 44 | } ; 45 | ps7_cortexa9_1: cpu@1 { 46 | bus-handle = <&ps7_axi_interconnect_0>; 47 | clocks = <&clkc 3>; 48 | compatible = "arm,cortex-a9"; 49 | device_type = "cpu"; 50 | interrupt-handle = <&ps7_scugic_0>; 51 | reg = <0x1>; 52 | } ; 53 | } ; 54 | pmu { 55 | compatible = "arm,cortex-a9-pmu"; 56 | interrupt-parent = <&ps7_scugic_0>; 57 | interrupts = <0 5 4>, <0 6 4>; 58 | reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; 59 | reg-names = "cpu0", "cpu1"; 60 | } ; 61 | ps7_ddr_0: memory@0 { 62 | device_type = "memory"; 63 | reg = <0x0 0x10000000>; 64 | } ; 65 | 66 | htif_0: htif@43c00000 { 67 | #address-cells = <1>; 68 | #size-cells = <1>; 69 | compatible = "generic-uio", "uio", "uio_pdrv"; 70 | reg = <0x43c00000 0x1000>; 71 | }; 72 | 73 | ps7_axi_interconnect_0: amba@0 { 74 | #address-cells = <1>; 75 | #size-cells = <1>; 76 | compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; 77 | ranges ; 78 | ps7_afi_0: ps7-afi@f8008000 { 79 | compatible = "xlnx,ps7-afi-1.00.a"; 80 | reg = <0xf8008000 0x1000>; 81 | } ; 82 | ps7_afi_1: ps7-afi@f8009000 { 83 | compatible = "xlnx,ps7-afi-1.00.a"; 84 | reg = <0xf8009000 0x1000>; 85 | } ; 86 | ps7_afi_2: ps7-afi@f800a000 { 87 | compatible = "xlnx,ps7-afi-1.00.a"; 88 | reg = <0xf800a000 0x1000>; 89 | } ; 90 | ps7_afi_3: ps7-afi@f800b000 { 91 | compatible = "xlnx,ps7-afi-1.00.a"; 92 | reg = <0xf800b000 0x1000>; 93 | } ; 94 | ps7_ddrc_0: ps7-ddrc@f8006000 { 95 | compatible = "xlnx,zynq-ddrc-1.0"; 96 | reg = <0xf8006000 0x1000>; 97 | xlnx,has-ecc = <0x0>; 98 | } ; 99 | ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { 100 | clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 101 | clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 102 | compatible = "xlnx,zynq-devcfg-1.0"; 103 | interrupt-parent = <&ps7_scugic_0>; 104 | interrupts = <0 8 4>; 105 | reg = <0xf8007000 0x100>; 106 | } ; 107 | ps7_dma_s: ps7-dma@f8003000 { 108 | #dma-cells = <1>; 109 | #dma-channels = <8>; 110 | #dma-requests = <4>; 111 | clock-names = "apb_pclk"; 112 | clocks = <&clkc 27>; 113 | compatible = "arm,primecell", "arm,pl330"; 114 | interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 115 | "dma4", "dma5", "dma6", "dma7"; 116 | interrupt-parent = <&ps7_scugic_0>; 117 | interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; 118 | reg = <0xf8003000 0x1000>; 119 | } ; 120 | ps7_ethernet_0: ps7-ethernet@e000b000 { 121 | #address-cells = <1>; 122 | #size-cells = <0>; 123 | clock-names = "ref_clk", "aper_clk"; 124 | clocks = <&clkc 13>, <&clkc 30>; 125 | compatible = "xlnx,ps7-ethernet-1.00.a"; 126 | enet-reset = <&ps7_gpio_0 47 0>; 127 | interrupt-parent = <&ps7_scugic_0>; 128 | interrupts = <0 22 4>; 129 | local-mac-address = [00 0a 35 00 00 00]; 130 | phy-handle = <&phy0>; 131 | phy-mode = "rgmii-id"; 132 | reg = <0xe000b000 0x1000>; 133 | xlnx,eth-mode = <0x1>; 134 | xlnx,has-mdio = <0x1>; 135 | xlnx,ptp-enet-clock = <111111115>; 136 | mdio { 137 | #address-cells = <1>; 138 | #size-cells = <0>; 139 | phy0: phy@7 { 140 | compatible = "marvell,88e1116r"; 141 | device_type = "ethernet-phy"; 142 | reg = <7>; 143 | } ; 144 | } ; 145 | } ; 146 | ps7_globaltimer_0: ps7-globaltimer@f8f00200 { 147 | clocks = <&clkc 4>; 148 | compatible = "arm,cortex-a9-global-timer"; 149 | interrupt-parent = <&ps7_scugic_0>; 150 | interrupts = <1 11 0x301>; 151 | reg = <0xf8f00200 0x100>; 152 | } ; 153 | ps7_gpio_0: ps7-gpio@e000a000 { 154 | #gpio-cells = <2>; 155 | clocks = <&clkc 42>; 156 | compatible = "xlnx,zynq-gpio-1.0"; 157 | emio-gpio-width = <64>; 158 | gpio-controller ; 159 | gpio-mask-high = <0x0>; 160 | gpio-mask-low = <0x0>; 161 | interrupt-parent = <&ps7_scugic_0>; 162 | interrupts = <0 20 4>; 163 | reg = <0xe000a000 0x1000>; 164 | } ; 165 | ps7_i2c_0: ps7-i2c@e0004000 { 166 | clock-frequency = <400000>; 167 | clocks = <&clkc 38>; 168 | compatible = "cdns,i2c-r1p10"; 169 | i2c-reset = <&ps7_gpio_0 46 0>; 170 | interrupt-parent = <&ps7_scugic_0>; 171 | interrupts = <0 25 4>; 172 | reg = <0xe0004000 0x1000>; 173 | xlnx,has-interrupt = <0x0>; 174 | #address-cells = <1>; 175 | #size-cells = <0>; 176 | i2cswitch@74 { 177 | compatible = "nxp,pca9548"; 178 | #address-cells = <1>; 179 | #size-cells = <0>; 180 | reg = <0x74>; 181 | 182 | i2c@0 { 183 | #address-cells = <1>; 184 | #size-cells = <0>; 185 | reg = <0>; 186 | si570: clock-generator@5d { 187 | #clock-cells = <0>; 188 | compatible = "silabs,si570"; 189 | temperature-stability = <50>; 190 | reg = <0x5d>; 191 | factory-fout = <156250000>; 192 | clock-frequency = <148500000>; 193 | }; 194 | }; 195 | 196 | i2c@2 { 197 | #address-cells = <1>; 198 | #size-cells = <0>; 199 | reg = <2>; 200 | eeprom@54 { 201 | compatible = "at,24c08"; 202 | reg = <0x54>; 203 | }; 204 | }; 205 | 206 | i2c@3 { 207 | #address-cells = <1>; 208 | #size-cells = <0>; 209 | reg = <3>; 210 | gpio@21 { 211 | compatible = "ti,tca6416"; 212 | reg = <0x21>; 213 | gpio-controller; 214 | #gpio-cells = <2>; 215 | }; 216 | }; 217 | 218 | i2c@4 { 219 | #address-cells = <1>; 220 | #size-cells = <0>; 221 | reg = <4>; 222 | rtc@51 { 223 | compatible = "nxp,pcf8563"; 224 | reg = <0x51>; 225 | }; 226 | }; 227 | 228 | 229 | i2c@7 { 230 | #address-cells = <1>; 231 | #size-cells = <0>; 232 | reg = <7>; 233 | ucd90120@65 { 234 | compatible = "ti,ucd90120"; 235 | reg = <0x65>; 236 | }; 237 | }; 238 | }; 239 | 240 | } ; 241 | ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { 242 | compatible = "xlnx,ps7-iop-bus-config-1.00.a"; 243 | reg = <0xe0200000 0x1000>; 244 | } ; 245 | ps7_ocmc_0: ps7-ocmc@f800c000 { 246 | compatible = "xlnx,zynq-ocmc-1.0"; 247 | interrupt-parent = <&ps7_scugic_0>; 248 | interrupts = <0 3 4>; 249 | reg = <0xf800c000 0x1000>; 250 | } ; 251 | ps7_pl310_0: ps7-pl310@f8f02000 { 252 | arm,data-latency = <3 2 2>; 253 | arm,tag-latency = <2 2 2>; 254 | cache-level = <2>; 255 | cache-unified ; 256 | compatible = "arm,pl310-cache"; 257 | interrupt-parent = <&ps7_scugic_0>; 258 | interrupts = <0 2 4>; 259 | reg = <0xf8f02000 0x1000>; 260 | } ; 261 | ps7_qspi_0: ps7-qspi@e000d000 { 262 | clock-names = "ref_clk", "pclk"; 263 | clocks = <&clkc 10>, <&clkc 43>; 264 | compatible = "xlnx,zynq-qspi-1.0"; 265 | interrupt-parent = <&ps7_scugic_0>; 266 | interrupts = <0 19 4>; 267 | is-dual = <1>; 268 | num-cs = <1>; 269 | reg = <0xe000d000 0x1000>; 270 | xlnx,fb-clk = <0x1>; 271 | xlnx,qspi-mode = <0x2>; 272 | #address-cells = <1>; 273 | #size-cells = <0>; 274 | flash@0 { 275 | compatible = "n25q128"; 276 | reg = <0x0>; 277 | spi-tx-bus-width = <1>; 278 | spi-rx-bus-width = <4>; 279 | spi-max-frequency = <50000000>; 280 | #address-cells = <1>; 281 | #size-cells = <1>; 282 | partition@qspi-fsbl-uboot { 283 | label = "qspi-fsbl-uboot"; 284 | reg = <0x0 0x100000>; 285 | }; 286 | partition@qspi-linux { 287 | label = "qspi-linux"; 288 | reg = <0x100000 0x500000>; 289 | }; 290 | partition@qspi-device-tree { 291 | label = "qspi-device-tree"; 292 | reg = <0x600000 0x20000>; 293 | }; 294 | partition@qspi-rootfs { 295 | label = "qspi-rootfs"; 296 | reg = <0x620000 0x5E0000>; 297 | }; 298 | partition@qspi-bitstream { 299 | label = "qspi-bitstream"; 300 | reg = <0xC00000 0x400000>; 301 | }; 302 | }; 303 | 304 | } ; 305 | ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { 306 | clock-names = "ref_clk", "aper_clk"; 307 | clocks = <&clkc 10>, <&clkc 43>; 308 | compatible = "xlnx,ps7-qspi-linear-1.00.a"; 309 | reg = <0xfc000000 0x2000000>; 310 | } ; 311 | ps7_scugic_0: ps7-scugic@f8f01000 { 312 | #address-cells = <2>; 313 | #interrupt-cells = <3>; 314 | #size-cells = <1>; 315 | compatible = "arm,cortex-a9-gic", "arm,gic"; 316 | interrupt-controller ; 317 | num_cpus = <2>; 318 | num_interrupts = <96>; 319 | reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; 320 | } ; 321 | ps7_scutimer_0: ps7-scutimer@f8f00600 { 322 | clocks = <&clkc 4>; 323 | compatible = "arm,cortex-a9-twd-timer"; 324 | interrupt-parent = <&ps7_scugic_0>; 325 | interrupts = <1 13 0x301>; 326 | reg = <0xf8f00600 0x20>; 327 | } ; 328 | ps7_scuwdt_0: ps7-scuwdt@f8f00620 { 329 | clocks = <&clkc 4>; 330 | compatible = "xlnx,ps7-scuwdt-1.00.a"; 331 | device_type = "watchdog"; 332 | interrupt-parent = <&ps7_scugic_0>; 333 | interrupts = <1 14 0x301>; 334 | reg = <0xf8f00620 0xe0>; 335 | } ; 336 | ps7_sd_0: ps7-sdio@e0100000 { 337 | clock-frequency = <50000000>; 338 | clock-names = "clk_xin", "clk_ahb"; 339 | clocks = <&clkc 21>, <&clkc 32>; 340 | compatible = "arasan,sdhci-8.9a"; 341 | interrupt-parent = <&ps7_scugic_0>; 342 | interrupts = <0 24 4>; 343 | reg = <0xe0100000 0x1000>; 344 | xlnx,has-cd = <0x1>; 345 | xlnx,has-power = <0x0>; 346 | xlnx,has-wp = <0x1>; 347 | } ; 348 | ps7_slcr_0: ps7-slcr@f8000000 { 349 | #address-cells = <1>; 350 | #size-cells = <1>; 351 | compatible = "xlnx,zynq-slcr", "syscon"; 352 | ranges ; 353 | reg = <0xf8000000 0x1000>; 354 | clkc: clkc@100 { 355 | #clock-cells = <1>; 356 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", 357 | "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", 358 | "lqspi", "smc", "pcap", "gem0", "gem1", 359 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", 360 | "can1", "sdio0", "sdio1", "uart0", "uart1", 361 | "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", 362 | "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", 363 | "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", 364 | "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", 365 | "swdt", "dbg_trc", "dbg_apb"; 366 | compatible = "xlnx,ps7-clkc"; 367 | fclk-enable = <0xf>; 368 | ps-clk-frequency = <33333333>; 369 | reg = <0x100 0x100>; 370 | } ; 371 | } ; 372 | ps7_ttc_0: ps7-ttc@f8001000 { 373 | clocks = <&clkc 6>; 374 | compatible = "cdns,ttc"; 375 | interrupt-names = "ttc0", "ttc1", "ttc2"; 376 | interrupt-parent = <&ps7_scugic_0>; 377 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 378 | reg = <0xf8001000 0x1000>; 379 | } ; 380 | ps7_ttc_1: ps7-ttc@f8002000 { 381 | clocks = <&clkc 6>; 382 | compatible = "cdns,ttc"; 383 | interrupt-names = "ttc0", "ttc1", "ttc2"; 384 | interrupt-parent = <&ps7_scugic_0>; 385 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 386 | reg = <0xf8002000 0x1000>; 387 | } ; 388 | ps7_uart_1: serial@e0001000 { 389 | clock-names = "uart_clk", "pclk"; 390 | clocks = <&clkc 24>, <&clkc 41>; 391 | compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 392 | current-speed = <115200>; 393 | device_type = "serial"; 394 | interrupt-parent = <&ps7_scugic_0>; 395 | interrupts = <0 50 4>; 396 | port-number = <0>; 397 | reg = <0xe0001000 0x1000>; 398 | xlnx,has-modem = <0x0>; 399 | } ; 400 | ps7_usb_0: ps7-usb@e0002000 { 401 | clocks = <&clkc 28>; 402 | compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; 403 | dr_mode = "host"; 404 | interrupt-parent = <&ps7_scugic_0>; 405 | interrupts = <0 21 4>; 406 | phy_type = "ulpi"; 407 | reg = <0xe0002000 0x1000>; 408 | usb-reset = <&ps7_gpio_0 7 0>; 409 | } ; 410 | ps7_wdt_0: ps7-wdt@f8005000 { 411 | clocks = <&clkc 45>; 412 | compatible = "xlnx,zynq-wdt-r1p2"; 413 | device_type = "watchdog"; 414 | interrupt-parent = <&ps7_scugic_0>; 415 | interrupts = <0 9 1>; 416 | reg = <0xf8005000 0x1000>; 417 | reset = <0>; 418 | timeout-sec = <10>; 419 | } ; 420 | ps7_xadc: ps7-xadc@f8007100 { 421 | clocks = <&clkc 12>; 422 | compatible = "xlnx,zynq-xadc-1.00.a"; 423 | interrupt-parent = <&ps7_scugic_0>; 424 | interrupts = <0 7 4>; 425 | reg = <0xf8007100 0x20>; 426 | } ; 427 | } ; 428 | } ; 429 | -------------------------------------------------------------------------------- /zc706/soft_config/zynq_zc70x.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Xilinx, Inc. 3 | * Modified by Sagar Karandikar for RISC-V Rocket Support 4 | * 5 | * u-boot Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards 6 | * See zynq-common.h for Zynq common configs 7 | * 8 | * Adapted for RISC-V Rocket Support 9 | * 10 | * SPDX-License-Identifier: GPL-2.0+ 11 | */ 12 | 13 | #ifndef __CONFIG_ZYNQ_ZC70X_H 14 | #define __CONFIG_ZYNQ_ZC70X_H 15 | 16 | #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 17 | 18 | #define CONFIG_ZYNQ_SERIAL_UART1 19 | #define CONFIG_ZYNQ_GEM0 20 | #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 21 | 22 | #define CONFIG_SYS_NO_FLASH 23 | 24 | #define CONFIG_ZYNQ_SDHCI0 25 | #define CONFIG_ZYNQ_USB 26 | #define CONFIG_ZYNQ_QSPI 27 | #define CONFIG_ZYNQ_I2C0 28 | #define CONFIG_ZYNQ_EEPROM 29 | #define CONFIG_ZYNQ_BOOT_FREEBSD 30 | #define CONFIG_DEFAULT_DEVICE_TREE zynq-zc702 31 | 32 | #include 33 | 34 | #endif /* __CONFIG_ZYNQ_ZC70X_H */ 35 | -------------------------------------------------------------------------------- /zc706/src/constrs/base.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H9 [get_ports SYSCLK_P] 2 | set_property IOSTANDARD LVDS [get_ports SYSCLK_P] 3 | set_property PACKAGE_PIN G9 [get_ports SYSCLK_N] 4 | set_property IOSTANDARD LVDS [get_ports SYSCLK_N] 5 | #set_property PACKAGE_PIN H9 [get_ports clk] 6 | #set_property IOSTANDARD LVCMOS33 [get_ports clk] 7 | create_clock -add -name SYSCLK_P -period 5.00 -waveform {0 2.5} [get_ports SYSCLK_P] 8 | -------------------------------------------------------------------------------- /zc706/src/verilog/clocking.vh: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Rocket Chip Clock Configuration 4 | 5 | 6 | Rocket Chip 1000 RC_CLK_MULT 7 | Clockrate = --------------- X ------------- 8 | (in MHz) ZYNQ_CLK_PERIOD RC_CLK_DIVIDE 9 | 10 | 11 | This sets the parameters used by rocketchip_wrapper.v to 12 | generate its own clock. 13 | 14 | Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE. 15 | ZYNQ_CLK_PERIOD should only be changed to match the input 16 | clock period set in the Vivado GUI and 17 | hw/src/constrs/pin_constraints.xdc 18 | 19 | */ 20 | 21 | 22 | `ifndef _clocking_vh_ 23 | `define _clocking_vh_ 24 | 25 | 26 | `define ZYNQ_CLK_PERIOD 5.0 27 | 28 | `define RC_CLK_MULT 4.0 29 | 30 | `define RC_CLK_DIVIDE 16.0 31 | 32 | `define differential_clock 33 | 34 | `endif // _clocking_vh_ 35 | -------------------------------------------------------------------------------- /zc706_MIG/Makefile: -------------------------------------------------------------------------------- 1 | BOARD = zc706_MIG 2 | UBOOT_CONFIG = zc70x 3 | BOARD_MODEL = xilinx.com:zc706:part0:1.0 4 | PART = xc7z045ffg900-2 5 | # CONFIG is the target configuration for the rocket-chip generator 6 | 7 | #TOP_MODULE_PROJECT = zynq 8 | #CONFIG = ZynqFPGAConfig 9 | TOP_MODULE_PROJECT = zynq.boom 10 | CONFIG ?= SmallBoomZynqConfig 11 | #CONFIG ?= MediumBoomZynqConfig 12 | 13 | include ../common/Makefrag 14 | -------------------------------------------------------------------------------- /zc706_MIG/soft_config/zc706_devicetree.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Device Tree Generator version: 1.1 3 | * 4 | * (C) Copyright 2007-2013 Xilinx, Inc. 5 | * (C) Copyright 2007-2013 Michal Simek 6 | * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 7 | * 8 | * Michal SIMEK 9 | * Modified for RISC-V Rocket Support by Sagar Karandikar 10 | * 11 | * CAUTION: This file is automatically generated by libgen. 12 | * Version: Xilinx EDK 14.5 EDK_P.58f 13 | * 14 | */ 15 | 16 | /dts-v1/; 17 | / { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "xlnx,zynq-7000"; 21 | model = "Xilinx Zynq"; 22 | aliases { 23 | ethernet0 = &ps7_ethernet_0; 24 | i2c0 = &ps7_i2c_0; 25 | serial0 = &ps7_uart_1; 26 | spi0 = &ps7_qspi_0; 27 | } ; 28 | chosen { 29 | bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; 30 | linux,stdout-path = "/amba@0/serial@e0001000"; 31 | } ; 32 | cpus { 33 | #address-cells = <1>; 34 | #size-cells = <0>; 35 | ps7_cortexa9_0: cpu@0 { 36 | bus-handle = <&ps7_axi_interconnect_0>; 37 | clock-latency = <1000>; 38 | clocks = <&clkc 3>; 39 | compatible = "arm,cortex-a9"; 40 | device_type = "cpu"; 41 | interrupt-handle = <&ps7_scugic_0>; 42 | operating-points = <666667 1000000 333334 1000000 222223 1000000>; 43 | reg = <0x0>; 44 | } ; 45 | ps7_cortexa9_1: cpu@1 { 46 | bus-handle = <&ps7_axi_interconnect_0>; 47 | clocks = <&clkc 3>; 48 | compatible = "arm,cortex-a9"; 49 | device_type = "cpu"; 50 | interrupt-handle = <&ps7_scugic_0>; 51 | reg = <0x1>; 52 | } ; 53 | } ; 54 | pmu { 55 | compatible = "arm,cortex-a9-pmu"; 56 | interrupt-parent = <&ps7_scugic_0>; 57 | interrupts = <0 5 4>, <0 6 4>; 58 | reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>; 59 | reg-names = "cpu0", "cpu1"; 60 | } ; 61 | ps7_ddr_0: memory@0 { 62 | device_type = "memory"; 63 | reg = <0x0 0x10000000>; 64 | } ; 65 | 66 | htif_0: htif@43c00000 { 67 | #address-cells = <1>; 68 | #size-cells = <1>; 69 | compatible = "generic-uio", "uio", "uio_pdrv"; 70 | reg = <0x43c00000 0x1000>; 71 | }; 72 | 73 | ps7_axi_interconnect_0: amba@0 { 74 | #address-cells = <1>; 75 | #size-cells = <1>; 76 | compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus"; 77 | ranges ; 78 | ps7_afi_0: ps7-afi@f8008000 { 79 | compatible = "xlnx,ps7-afi-1.00.a"; 80 | reg = <0xf8008000 0x1000>; 81 | } ; 82 | ps7_afi_1: ps7-afi@f8009000 { 83 | compatible = "xlnx,ps7-afi-1.00.a"; 84 | reg = <0xf8009000 0x1000>; 85 | } ; 86 | ps7_afi_2: ps7-afi@f800a000 { 87 | compatible = "xlnx,ps7-afi-1.00.a"; 88 | reg = <0xf800a000 0x1000>; 89 | } ; 90 | ps7_afi_3: ps7-afi@f800b000 { 91 | compatible = "xlnx,ps7-afi-1.00.a"; 92 | reg = <0xf800b000 0x1000>; 93 | } ; 94 | ps7_ddrc_0: ps7-ddrc@f8006000 { 95 | compatible = "xlnx,zynq-ddrc-1.0"; 96 | reg = <0xf8006000 0x1000>; 97 | xlnx,has-ecc = <0x0>; 98 | } ; 99 | ps7_dev_cfg_0: ps7-dev-cfg@f8007000 { 100 | clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 101 | clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 102 | compatible = "xlnx,zynq-devcfg-1.0"; 103 | interrupt-parent = <&ps7_scugic_0>; 104 | interrupts = <0 8 4>; 105 | reg = <0xf8007000 0x100>; 106 | } ; 107 | ps7_dma_s: ps7-dma@f8003000 { 108 | #dma-cells = <1>; 109 | #dma-channels = <8>; 110 | #dma-requests = <4>; 111 | clock-names = "apb_pclk"; 112 | clocks = <&clkc 27>; 113 | compatible = "arm,primecell", "arm,pl330"; 114 | interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 115 | "dma4", "dma5", "dma6", "dma7"; 116 | interrupt-parent = <&ps7_scugic_0>; 117 | interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; 118 | reg = <0xf8003000 0x1000>; 119 | } ; 120 | ps7_ethernet_0: ps7-ethernet@e000b000 { 121 | #address-cells = <1>; 122 | #size-cells = <0>; 123 | clock-names = "ref_clk", "aper_clk"; 124 | clocks = <&clkc 13>, <&clkc 30>; 125 | compatible = "xlnx,ps7-ethernet-1.00.a"; 126 | enet-reset = <&ps7_gpio_0 47 0>; 127 | interrupt-parent = <&ps7_scugic_0>; 128 | interrupts = <0 22 4>; 129 | local-mac-address = [00 0a 35 00 00 00]; 130 | phy-handle = <&phy0>; 131 | phy-mode = "rgmii-id"; 132 | reg = <0xe000b000 0x1000>; 133 | xlnx,eth-mode = <0x1>; 134 | xlnx,has-mdio = <0x1>; 135 | xlnx,ptp-enet-clock = <111111115>; 136 | mdio { 137 | #address-cells = <1>; 138 | #size-cells = <0>; 139 | phy0: phy@7 { 140 | compatible = "marvell,88e1116r"; 141 | device_type = "ethernet-phy"; 142 | reg = <7>; 143 | } ; 144 | } ; 145 | } ; 146 | ps7_globaltimer_0: ps7-globaltimer@f8f00200 { 147 | clocks = <&clkc 4>; 148 | compatible = "arm,cortex-a9-global-timer"; 149 | interrupt-parent = <&ps7_scugic_0>; 150 | interrupts = <1 11 0x301>; 151 | reg = <0xf8f00200 0x100>; 152 | } ; 153 | ps7_gpio_0: ps7-gpio@e000a000 { 154 | #gpio-cells = <2>; 155 | clocks = <&clkc 42>; 156 | compatible = "xlnx,zynq-gpio-1.0"; 157 | emio-gpio-width = <64>; 158 | gpio-controller ; 159 | gpio-mask-high = <0x0>; 160 | gpio-mask-low = <0x0>; 161 | interrupt-parent = <&ps7_scugic_0>; 162 | interrupts = <0 20 4>; 163 | reg = <0xe000a000 0x1000>; 164 | } ; 165 | ps7_i2c_0: ps7-i2c@e0004000 { 166 | clock-frequency = <400000>; 167 | clocks = <&clkc 38>; 168 | compatible = "cdns,i2c-r1p10"; 169 | i2c-reset = <&ps7_gpio_0 46 0>; 170 | interrupt-parent = <&ps7_scugic_0>; 171 | interrupts = <0 25 4>; 172 | reg = <0xe0004000 0x1000>; 173 | xlnx,has-interrupt = <0x0>; 174 | #address-cells = <1>; 175 | #size-cells = <0>; 176 | i2cswitch@74 { 177 | compatible = "nxp,pca9548"; 178 | #address-cells = <1>; 179 | #size-cells = <0>; 180 | reg = <0x74>; 181 | 182 | i2c@0 { 183 | #address-cells = <1>; 184 | #size-cells = <0>; 185 | reg = <0>; 186 | si570: clock-generator@5d { 187 | #clock-cells = <0>; 188 | compatible = "silabs,si570"; 189 | temperature-stability = <50>; 190 | reg = <0x5d>; 191 | factory-fout = <156250000>; 192 | clock-frequency = <148500000>; 193 | }; 194 | }; 195 | 196 | i2c@2 { 197 | #address-cells = <1>; 198 | #size-cells = <0>; 199 | reg = <2>; 200 | eeprom@54 { 201 | compatible = "at,24c08"; 202 | reg = <0x54>; 203 | }; 204 | }; 205 | 206 | i2c@3 { 207 | #address-cells = <1>; 208 | #size-cells = <0>; 209 | reg = <3>; 210 | gpio@21 { 211 | compatible = "ti,tca6416"; 212 | reg = <0x21>; 213 | gpio-controller; 214 | #gpio-cells = <2>; 215 | }; 216 | }; 217 | 218 | i2c@4 { 219 | #address-cells = <1>; 220 | #size-cells = <0>; 221 | reg = <4>; 222 | rtc@51 { 223 | compatible = "nxp,pcf8563"; 224 | reg = <0x51>; 225 | }; 226 | }; 227 | 228 | 229 | i2c@7 { 230 | #address-cells = <1>; 231 | #size-cells = <0>; 232 | reg = <7>; 233 | ucd90120@65 { 234 | compatible = "ti,ucd90120"; 235 | reg = <0x65>; 236 | }; 237 | }; 238 | }; 239 | 240 | } ; 241 | ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 { 242 | compatible = "xlnx,ps7-iop-bus-config-1.00.a"; 243 | reg = <0xe0200000 0x1000>; 244 | } ; 245 | ps7_ocmc_0: ps7-ocmc@f800c000 { 246 | compatible = "xlnx,zynq-ocmc-1.0"; 247 | interrupt-parent = <&ps7_scugic_0>; 248 | interrupts = <0 3 4>; 249 | reg = <0xf800c000 0x1000>; 250 | } ; 251 | ps7_pl310_0: ps7-pl310@f8f02000 { 252 | arm,data-latency = <3 2 2>; 253 | arm,tag-latency = <2 2 2>; 254 | cache-level = <2>; 255 | cache-unified ; 256 | compatible = "arm,pl310-cache"; 257 | interrupt-parent = <&ps7_scugic_0>; 258 | interrupts = <0 2 4>; 259 | reg = <0xf8f02000 0x1000>; 260 | } ; 261 | ps7_qspi_0: ps7-qspi@e000d000 { 262 | clock-names = "ref_clk", "pclk"; 263 | clocks = <&clkc 10>, <&clkc 43>; 264 | compatible = "xlnx,zynq-qspi-1.0"; 265 | interrupt-parent = <&ps7_scugic_0>; 266 | interrupts = <0 19 4>; 267 | is-dual = <1>; 268 | num-cs = <1>; 269 | reg = <0xe000d000 0x1000>; 270 | xlnx,fb-clk = <0x1>; 271 | xlnx,qspi-mode = <0x2>; 272 | #address-cells = <1>; 273 | #size-cells = <0>; 274 | flash@0 { 275 | compatible = "n25q128"; 276 | reg = <0x0>; 277 | spi-tx-bus-width = <1>; 278 | spi-rx-bus-width = <4>; 279 | spi-max-frequency = <50000000>; 280 | #address-cells = <1>; 281 | #size-cells = <1>; 282 | partition@qspi-fsbl-uboot { 283 | label = "qspi-fsbl-uboot"; 284 | reg = <0x0 0x100000>; 285 | }; 286 | partition@qspi-linux { 287 | label = "qspi-linux"; 288 | reg = <0x100000 0x500000>; 289 | }; 290 | partition@qspi-device-tree { 291 | label = "qspi-device-tree"; 292 | reg = <0x600000 0x20000>; 293 | }; 294 | partition@qspi-rootfs { 295 | label = "qspi-rootfs"; 296 | reg = <0x620000 0x5E0000>; 297 | }; 298 | partition@qspi-bitstream { 299 | label = "qspi-bitstream"; 300 | reg = <0xC00000 0x400000>; 301 | }; 302 | }; 303 | 304 | } ; 305 | ps7_qspi_linear_0: ps7-qspi-linear@fc000000 { 306 | clock-names = "ref_clk", "aper_clk"; 307 | clocks = <&clkc 10>, <&clkc 43>; 308 | compatible = "xlnx,ps7-qspi-linear-1.00.a"; 309 | reg = <0xfc000000 0x2000000>; 310 | } ; 311 | ps7_scugic_0: ps7-scugic@f8f01000 { 312 | #address-cells = <2>; 313 | #interrupt-cells = <3>; 314 | #size-cells = <1>; 315 | compatible = "arm,cortex-a9-gic", "arm,gic"; 316 | interrupt-controller ; 317 | num_cpus = <2>; 318 | num_interrupts = <96>; 319 | reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; 320 | } ; 321 | ps7_scutimer_0: ps7-scutimer@f8f00600 { 322 | clocks = <&clkc 4>; 323 | compatible = "arm,cortex-a9-twd-timer"; 324 | interrupt-parent = <&ps7_scugic_0>; 325 | interrupts = <1 13 0x301>; 326 | reg = <0xf8f00600 0x20>; 327 | } ; 328 | ps7_scuwdt_0: ps7-scuwdt@f8f00620 { 329 | clocks = <&clkc 4>; 330 | compatible = "xlnx,ps7-scuwdt-1.00.a"; 331 | device_type = "watchdog"; 332 | interrupt-parent = <&ps7_scugic_0>; 333 | interrupts = <1 14 0x301>; 334 | reg = <0xf8f00620 0xe0>; 335 | } ; 336 | ps7_sd_0: ps7-sdio@e0100000 { 337 | clock-frequency = <50000000>; 338 | clock-names = "clk_xin", "clk_ahb"; 339 | clocks = <&clkc 21>, <&clkc 32>; 340 | compatible = "arasan,sdhci-8.9a"; 341 | interrupt-parent = <&ps7_scugic_0>; 342 | interrupts = <0 24 4>; 343 | reg = <0xe0100000 0x1000>; 344 | xlnx,has-cd = <0x1>; 345 | xlnx,has-power = <0x0>; 346 | xlnx,has-wp = <0x1>; 347 | } ; 348 | ps7_slcr_0: ps7-slcr@f8000000 { 349 | #address-cells = <1>; 350 | #size-cells = <1>; 351 | compatible = "xlnx,zynq-slcr", "syscon"; 352 | ranges ; 353 | reg = <0xf8000000 0x1000>; 354 | clkc: clkc@100 { 355 | #clock-cells = <1>; 356 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", 357 | "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", 358 | "lqspi", "smc", "pcap", "gem0", "gem1", 359 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", 360 | "can1", "sdio0", "sdio1", "uart0", "uart1", 361 | "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", 362 | "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", 363 | "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", 364 | "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", 365 | "swdt", "dbg_trc", "dbg_apb"; 366 | compatible = "xlnx,ps7-clkc"; 367 | fclk-enable = <0xf>; 368 | ps-clk-frequency = <33333333>; 369 | reg = <0x100 0x100>; 370 | } ; 371 | } ; 372 | ps7_ttc_0: ps7-ttc@f8001000 { 373 | clocks = <&clkc 6>; 374 | compatible = "cdns,ttc"; 375 | interrupt-names = "ttc0", "ttc1", "ttc2"; 376 | interrupt-parent = <&ps7_scugic_0>; 377 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 378 | reg = <0xf8001000 0x1000>; 379 | } ; 380 | ps7_ttc_1: ps7-ttc@f8002000 { 381 | clocks = <&clkc 6>; 382 | compatible = "cdns,ttc"; 383 | interrupt-names = "ttc0", "ttc1", "ttc2"; 384 | interrupt-parent = <&ps7_scugic_0>; 385 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 386 | reg = <0xf8002000 0x1000>; 387 | } ; 388 | ps7_uart_1: serial@e0001000 { 389 | clock-names = "uart_clk", "pclk"; 390 | clocks = <&clkc 24>, <&clkc 41>; 391 | compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 392 | current-speed = <115200>; 393 | device_type = "serial"; 394 | interrupt-parent = <&ps7_scugic_0>; 395 | interrupts = <0 50 4>; 396 | port-number = <0>; 397 | reg = <0xe0001000 0x1000>; 398 | xlnx,has-modem = <0x0>; 399 | } ; 400 | ps7_usb_0: ps7-usb@e0002000 { 401 | clocks = <&clkc 28>; 402 | compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; 403 | dr_mode = "host"; 404 | interrupt-parent = <&ps7_scugic_0>; 405 | interrupts = <0 21 4>; 406 | phy_type = "ulpi"; 407 | reg = <0xe0002000 0x1000>; 408 | usb-reset = <&ps7_gpio_0 7 0>; 409 | } ; 410 | ps7_wdt_0: ps7-wdt@f8005000 { 411 | clocks = <&clkc 45>; 412 | compatible = "xlnx,zynq-wdt-r1p2"; 413 | device_type = "watchdog"; 414 | interrupt-parent = <&ps7_scugic_0>; 415 | interrupts = <0 9 1>; 416 | reg = <0xf8005000 0x1000>; 417 | reset = <0>; 418 | timeout-sec = <10>; 419 | } ; 420 | ps7_xadc: ps7-xadc@f8007100 { 421 | clocks = <&clkc 12>; 422 | compatible = "xlnx,zynq-xadc-1.00.a"; 423 | interrupt-parent = <&ps7_scugic_0>; 424 | interrupts = <0 7 4>; 425 | reg = <0xf8007100 0x20>; 426 | } ; 427 | } ; 428 | } ; 429 | -------------------------------------------------------------------------------- /zc706_MIG/soft_config/zynq_zc70x.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Xilinx, Inc. 3 | * Modified by Sagar Karandikar for RISC-V Rocket Support 4 | * 5 | * u-boot Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards 6 | * See zynq-common.h for Zynq common configs 7 | * 8 | * Adapted for RISC-V Rocket Support 9 | * 10 | * SPDX-License-Identifier: GPL-2.0+ 11 | */ 12 | 13 | #ifndef __CONFIG_ZYNQ_ZC70X_H 14 | #define __CONFIG_ZYNQ_ZC70X_H 15 | 16 | #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 17 | 18 | #define CONFIG_ZYNQ_SERIAL_UART1 19 | #define CONFIG_ZYNQ_GEM0 20 | #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 21 | 22 | #define CONFIG_SYS_NO_FLASH 23 | 24 | #define CONFIG_ZYNQ_SDHCI0 25 | #define CONFIG_ZYNQ_USB 26 | #define CONFIG_ZYNQ_QSPI 27 | #define CONFIG_ZYNQ_I2C0 28 | #define CONFIG_ZYNQ_EEPROM 29 | #define CONFIG_ZYNQ_BOOT_FREEBSD 30 | #define CONFIG_DEFAULT_DEVICE_TREE zynq-zc702 31 | 32 | #include 33 | 34 | #endif /* __CONFIG_ZYNQ_ZC70X_H */ 35 | -------------------------------------------------------------------------------- /zc706_MIG/src/verilog/clocking.vh: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Rocket Chip Clock Configuration 4 | 5 | 6 | Rocket Chip 1000 RC_CLK_MULT 7 | Clockrate = --------------- X ------------- 8 | (in MHz) ZYNQ_CLK_PERIOD RC_CLK_DIVIDE 9 | 10 | 11 | This sets the parameters used by rocketchip_wrapper.v to 12 | generate its own clock. 13 | 14 | Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE. 15 | ZYNQ_CLK_PERIOD should only be changed to match the input 16 | clock period set in the Vivado GUI and 17 | hw/src/constrs/pin_constraints.xdc 18 | 19 | */ 20 | 21 | 22 | `ifndef _clocking_vh_ 23 | `define _clocking_vh_ 24 | 25 | 26 | `define ZYNQ_CLK_PERIOD 5.0 27 | 28 | `define RC_CLK_MULT 4.0 29 | 30 | `define RC_CLK_DIVIDE 20.0 31 | 32 | `define differential_clock 33 | 34 | `endif // _clocking_vh_ 35 | -------------------------------------------------------------------------------- /zc706_MIG/src/verilog/rocketchip_wrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | `include "clocking.vh" 3 | 4 | module rocketchip_wrapper 5 | (DDR_addr, 6 | DDR_ba, 7 | DDR_cas_n, 8 | DDR_ck_n, 9 | DDR_ck_p, 10 | DDR_cke, 11 | DDR_cs_n, 12 | DDR_dm, 13 | DDR_dq, 14 | DDR_dqs_n, 15 | DDR_dqs_p, 16 | DDR_odt, 17 | DDR_ras_n, 18 | DDR_reset_n, 19 | DDR_we_n, 20 | DDR3_SODIMM_addr, 21 | DDR3_SODIMM_ba, 22 | DDR3_SODIMM_cas_n, 23 | DDR3_SODIMM_ck_n, 24 | DDR3_SODIMM_ck_p, 25 | DDR3_SODIMM_cke, 26 | DDR3_SODIMM_cs_n, 27 | DDR3_SODIMM_dm, 28 | DDR3_SODIMM_dq, 29 | DDR3_SODIMM_dqs_n, 30 | DDR3_SODIMM_dqs_p, 31 | DDR3_SODIMM_odt, 32 | DDR3_SODIMM_ras_n, 33 | DDR3_SODIMM_reset_n, 34 | DDR3_SODIMM_we_n, 35 | FIXED_IO_ddr_vrn, 36 | FIXED_IO_ddr_vrp, 37 | FIXED_IO_mio, 38 | FIXED_IO_ps_clk, 39 | FIXED_IO_ps_porb, 40 | FIXED_IO_ps_srstb, 41 | `ifndef differential_clock 42 | clk); 43 | `else 44 | SYSCLK_P, 45 | SYSCLK_N); 46 | `endif 47 | 48 | inout [14:0]DDR_addr; 49 | inout [2:0]DDR_ba; 50 | inout DDR_cas_n; 51 | inout DDR_ck_n; 52 | inout DDR_ck_p; 53 | inout DDR_cke; 54 | inout DDR_cs_n; 55 | inout [3:0]DDR_dm; 56 | inout [31:0]DDR_dq; 57 | inout [3:0]DDR_dqs_n; 58 | inout [3:0]DDR_dqs_p; 59 | inout DDR_odt; 60 | inout DDR_ras_n; 61 | inout DDR_reset_n; 62 | inout DDR_we_n; 63 | 64 | inout FIXED_IO_ddr_vrn; 65 | inout FIXED_IO_ddr_vrp; 66 | inout [53:0]FIXED_IO_mio; 67 | inout FIXED_IO_ps_clk; 68 | inout FIXED_IO_ps_porb; 69 | inout FIXED_IO_ps_srstb; 70 | 71 | output [13:0]DDR3_SODIMM_addr; 72 | output [2:0]DDR3_SODIMM_ba; 73 | output DDR3_SODIMM_cas_n; 74 | output [0:0]DDR3_SODIMM_ck_n; 75 | output [0:0]DDR3_SODIMM_ck_p; 76 | output [0:0]DDR3_SODIMM_cke; 77 | output [0:0]DDR3_SODIMM_cs_n; 78 | output [7:0]DDR3_SODIMM_dm; 79 | inout [63:0]DDR3_SODIMM_dq; 80 | inout [7:0]DDR3_SODIMM_dqs_n; 81 | inout [7:0]DDR3_SODIMM_dqs_p; 82 | output [0:0]DDR3_SODIMM_odt; 83 | output DDR3_SODIMM_ras_n; 84 | output DDR3_SODIMM_reset_n; 85 | output DDR3_SODIMM_we_n; 86 | 87 | `ifndef differential_clock 88 | input clk; 89 | `else 90 | input SYSCLK_P; 91 | input SYSCLK_N; 92 | `endif 93 | 94 | wire FCLK_RESET0_N; 95 | 96 | wire [31:0]M_AXI_araddr; 97 | wire [1:0]M_AXI_arburst; 98 | wire [7:0]M_AXI_arlen; 99 | wire M_AXI_arready; 100 | wire [2:0]M_AXI_arsize; 101 | wire M_AXI_arvalid; 102 | wire [31:0]M_AXI_awaddr; 103 | wire [1:0]M_AXI_awburst; 104 | wire [7:0]M_AXI_awlen; 105 | wire [3:0]M_AXI_wstrb; 106 | wire M_AXI_awready; 107 | wire [2:0]M_AXI_awsize; 108 | wire M_AXI_awvalid; 109 | wire M_AXI_bready; 110 | wire M_AXI_bvalid; 111 | wire [1:0] M_AXI_bresp; 112 | wire [31:0]M_AXI_rdata; 113 | wire M_AXI_rlast; 114 | wire M_AXI_rready; 115 | wire M_AXI_rvalid; 116 | wire [1:0] M_AXI_rresp; 117 | wire [31:0]M_AXI_wdata; 118 | wire M_AXI_wlast; 119 | wire M_AXI_wready; 120 | wire M_AXI_wvalid; 121 | wire [11:0] M_AXI_arid, M_AXI_awid; // outputs from ARM core 122 | wire [11:0] M_AXI_bid, M_AXI_rid; // inputs to ARM core 123 | 124 | wire S_AXI_arready; 125 | wire S_AXI_arvalid; 126 | wire [31:0] S_AXI_araddr; 127 | wire [5:0] S_AXI_arid; 128 | wire [2:0] S_AXI_arsize; 129 | wire [7:0] S_AXI_arlen; 130 | wire [1:0] S_AXI_arburst; 131 | wire S_AXI_arlock; 132 | wire [3:0] S_AXI_arcache; 133 | wire [2:0] S_AXI_arprot; 134 | wire [3:0] S_AXI_arqos; 135 | 136 | wire S_AXI_awready; 137 | wire S_AXI_awvalid; 138 | wire [31:0] S_AXI_awaddr; 139 | wire [5:0] S_AXI_awid; 140 | wire [2:0] S_AXI_awsize; 141 | wire [7:0] S_AXI_awlen; 142 | wire [1:0] S_AXI_awburst; 143 | wire S_AXI_awlock; 144 | wire [3:0] S_AXI_awcache; 145 | wire [2:0] S_AXI_awprot; 146 | wire [3:0] S_AXI_awqos; 147 | 148 | wire S_AXI_wready; 149 | wire S_AXI_wvalid; 150 | wire [7:0] S_AXI_wstrb; 151 | wire [63:0] S_AXI_wdata; 152 | wire S_AXI_wlast; 153 | 154 | wire S_AXI_bready; 155 | wire S_AXI_bvalid; 156 | wire [1:0] S_AXI_bresp; 157 | wire [5:0] S_AXI_bid; 158 | 159 | wire S_AXI_rready; 160 | wire S_AXI_rvalid; 161 | wire [1:0] S_AXI_rresp; 162 | wire [5:0] S_AXI_rid; 163 | wire [63:0] S_AXI_rdata; 164 | wire S_AXI_rlast; 165 | 166 | wire reset, reset_cpu; 167 | wire host_clk; 168 | wire gclk_i, gclk_fbout, host_clk_i, mmcm_locked; 169 | 170 | system system_i 171 | (.DDR_addr(DDR_addr), 172 | .DDR_ba(DDR_ba), 173 | .DDR_cas_n(DDR_cas_n), 174 | .DDR_ck_n(DDR_ck_n), 175 | .DDR_ck_p(DDR_ck_p), 176 | .DDR_cke(DDR_cke), 177 | .DDR_cs_n(DDR_cs_n), 178 | .DDR_dm(DDR_dm), 179 | .DDR_dq(DDR_dq), 180 | .DDR_dqs_n(DDR_dqs_n), 181 | .DDR_dqs_p(DDR_dqs_p), 182 | .DDR_odt(DDR_odt), 183 | .DDR_ras_n(DDR_ras_n), 184 | .DDR_reset_n(DDR_reset_n), 185 | .DDR_we_n(DDR_we_n), 186 | .FCLK_RESET0_N(FCLK_RESET0_N), 187 | .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), 188 | .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), 189 | .FIXED_IO_mio(FIXED_IO_mio), 190 | .FIXED_IO_ps_clk(FIXED_IO_ps_clk), 191 | .FIXED_IO_ps_porb(FIXED_IO_ps_porb), 192 | .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), 193 | // master AXI interface (zynq = master, fpga = slave) 194 | .M_AXI_araddr(M_AXI_araddr), 195 | .M_AXI_arburst(M_AXI_arburst), // burst type 196 | .M_AXI_arcache(), 197 | .M_AXI_arid(M_AXI_arid), 198 | .M_AXI_arlen(M_AXI_arlen), // burst length (#transfers) 199 | .M_AXI_arlock(), 200 | .M_AXI_arprot(), 201 | .M_AXI_arqos(), 202 | .M_AXI_arready(M_AXI_arready), 203 | .M_AXI_arregion(), 204 | .M_AXI_arsize(M_AXI_arsize), // burst size (bits/transfer) 205 | .M_AXI_arvalid(M_AXI_arvalid), 206 | // 207 | .M_AXI_awaddr(M_AXI_awaddr), 208 | .M_AXI_awburst(M_AXI_awburst), 209 | .M_AXI_awcache(), 210 | .M_AXI_awid(M_AXI_awid), 211 | .M_AXI_awlen(M_AXI_awlen), 212 | .M_AXI_awlock(), 213 | .M_AXI_awprot(), 214 | .M_AXI_awqos(), 215 | .M_AXI_awready(M_AXI_awready), 216 | .M_AXI_awregion(), 217 | .M_AXI_awsize(M_AXI_awsize), 218 | .M_AXI_awvalid(M_AXI_awvalid), 219 | // 220 | .M_AXI_bid(M_AXI_bid), 221 | .M_AXI_bready(M_AXI_bready), 222 | .M_AXI_bresp(M_AXI_bresp), 223 | .M_AXI_bvalid(M_AXI_bvalid), 224 | // 225 | .M_AXI_rdata(M_AXI_rdata), 226 | .M_AXI_rid(M_AXI_rid), 227 | .M_AXI_rlast(M_AXI_rlast), 228 | .M_AXI_rready(M_AXI_rready), 229 | .M_AXI_rresp(M_AXI_rresp), 230 | .M_AXI_rvalid(M_AXI_rvalid), 231 | // 232 | .M_AXI_wdata(M_AXI_wdata), 233 | .M_AXI_wlast(M_AXI_wlast), 234 | .M_AXI_wready(M_AXI_wready), 235 | .M_AXI_wstrb(M_AXI_wstrb), 236 | .M_AXI_wvalid(M_AXI_wvalid), 237 | 238 | // slave AXI interface (fpga = master, zynq = slave) 239 | // connected directly to DDR controller to handle test chip mem 240 | .S_AXI_araddr(S_AXI_araddr), 241 | .S_AXI_arburst(S_AXI_arburst), 242 | .S_AXI_arcache(S_AXI_arcache), 243 | .S_AXI_arid(S_AXI_arid), 244 | .S_AXI_arlen(S_AXI_arlen), 245 | .S_AXI_arlock(S_AXI_arlock), 246 | .S_AXI_arprot(S_AXI_arprot), 247 | .S_AXI_arqos(S_AXI_arqos), 248 | .S_AXI_arready(S_AXI_arready), 249 | .S_AXI_arregion(4'b0), 250 | .S_AXI_arsize(S_AXI_arsize), 251 | .S_AXI_arvalid(S_AXI_arvalid), 252 | // 253 | .S_AXI_awaddr(S_AXI_awaddr), 254 | .S_AXI_awburst(S_AXI_awburst), 255 | .S_AXI_awcache(S_AXI_awcache), 256 | .S_AXI_awid(S_AXI_awid), 257 | .S_AXI_awlen(S_AXI_awlen), 258 | .S_AXI_awlock(S_AXI_awlock), 259 | .S_AXI_awprot(S_AXI_awprot), 260 | .S_AXI_awqos(S_AXI_awqos), 261 | .S_AXI_awready(S_AXI_awready), 262 | .S_AXI_awregion(4'b0), 263 | .S_AXI_awsize(S_AXI_awsize), 264 | .S_AXI_awvalid(S_AXI_awvalid), 265 | // 266 | .S_AXI_bid(S_AXI_bid), 267 | .S_AXI_bready(S_AXI_bready), 268 | .S_AXI_bresp(S_AXI_bresp), 269 | .S_AXI_bvalid(S_AXI_bvalid), 270 | // 271 | .S_AXI_rid(S_AXI_rid), 272 | .S_AXI_rdata(S_AXI_rdata), 273 | .S_AXI_rlast(S_AXI_rlast), 274 | .S_AXI_rready(S_AXI_rready), 275 | .S_AXI_rresp(S_AXI_rresp), 276 | .S_AXI_rvalid(S_AXI_rvalid), 277 | // 278 | .S_AXI_wdata(S_AXI_wdata), 279 | .S_AXI_wlast(S_AXI_wlast), 280 | .S_AXI_wready(S_AXI_wready), 281 | .S_AXI_wstrb(S_AXI_wstrb), 282 | .S_AXI_wvalid(S_AXI_wvalid), 283 | 284 | .DDR3_SODIMM_addr(DDR3_SODIMM_addr), 285 | .DDR3_SODIMM_ba(DDR3_SODIMM_ba), 286 | .DDR3_SODIMM_cas_n(DDR3_SODIMM_cas_n), 287 | .DDR3_SODIMM_ck_n(DDR3_SODIMM_ck_n), 288 | .DDR3_SODIMM_ck_p(DDR3_SODIMM_ck_p), 289 | .DDR3_SODIMM_cke(DDR3_SODIMM_cke), 290 | .DDR3_SODIMM_cs_n(DDR3_SODIMM_cs_n), 291 | .DDR3_SODIMM_dm(DDR3_SODIMM_dm), 292 | .DDR3_SODIMM_dq(DDR3_SODIMM_dq), 293 | .DDR3_SODIMM_dqs_n(DDR3_SODIMM_dqs_n), 294 | .DDR3_SODIMM_dqs_p(DDR3_SODIMM_dqs_p), 295 | .DDR3_SODIMM_odt(DDR3_SODIMM_odt), 296 | .DDR3_SODIMM_ras_n(DDR3_SODIMM_ras_n), 297 | .DDR3_SODIMM_reset_n(DDR3_SODIMM_reset_n), 298 | .DDR3_SODIMM_we_n(DDR3_SODIMM_we_n), 299 | 300 | .ext_clk_in(host_clk), 301 | .gclk_i(gclk_i) 302 | ); 303 | 304 | assign reset = !FCLK_RESET0_N || !mmcm_locked; 305 | 306 | Top top( 307 | .clock(host_clk), 308 | .reset(reset), 309 | 310 | .io_ps_axi_slave_aw_ready (M_AXI_awready), 311 | .io_ps_axi_slave_aw_valid (M_AXI_awvalid), 312 | .io_ps_axi_slave_aw_bits_addr (M_AXI_awaddr), 313 | .io_ps_axi_slave_aw_bits_len (M_AXI_awlen), 314 | .io_ps_axi_slave_aw_bits_size (M_AXI_awsize), 315 | .io_ps_axi_slave_aw_bits_burst (M_AXI_awburst), 316 | .io_ps_axi_slave_aw_bits_id (M_AXI_awid), 317 | .io_ps_axi_slave_aw_bits_lock (1'b0), 318 | .io_ps_axi_slave_aw_bits_cache (4'b0), 319 | .io_ps_axi_slave_aw_bits_prot (3'b0), 320 | .io_ps_axi_slave_aw_bits_qos (4'b0), 321 | 322 | .io_ps_axi_slave_ar_ready (M_AXI_arready), 323 | .io_ps_axi_slave_ar_valid (M_AXI_arvalid), 324 | .io_ps_axi_slave_ar_bits_addr (M_AXI_araddr), 325 | .io_ps_axi_slave_ar_bits_len (M_AXI_arlen), 326 | .io_ps_axi_slave_ar_bits_size (M_AXI_arsize), 327 | .io_ps_axi_slave_ar_bits_burst (M_AXI_arburst), 328 | .io_ps_axi_slave_ar_bits_id (M_AXI_arid), 329 | .io_ps_axi_slave_ar_bits_lock (1'b0), 330 | .io_ps_axi_slave_ar_bits_cache (4'b0), 331 | .io_ps_axi_slave_ar_bits_prot (3'b0), 332 | .io_ps_axi_slave_ar_bits_qos (4'b0), 333 | 334 | .io_ps_axi_slave_w_valid (M_AXI_wvalid), 335 | .io_ps_axi_slave_w_ready (M_AXI_wready), 336 | .io_ps_axi_slave_w_bits_data (M_AXI_wdata), 337 | .io_ps_axi_slave_w_bits_strb (M_AXI_wstrb), 338 | .io_ps_axi_slave_w_bits_last (M_AXI_wlast), 339 | 340 | .io_ps_axi_slave_r_valid (M_AXI_rvalid), 341 | .io_ps_axi_slave_r_ready (M_AXI_rready), 342 | .io_ps_axi_slave_r_bits_id (M_AXI_rid), 343 | .io_ps_axi_slave_r_bits_resp (M_AXI_rresp), 344 | .io_ps_axi_slave_r_bits_data (M_AXI_rdata), 345 | .io_ps_axi_slave_r_bits_last (M_AXI_rlast), 346 | 347 | .io_ps_axi_slave_b_valid (M_AXI_bvalid), 348 | .io_ps_axi_slave_b_ready (M_AXI_bready), 349 | .io_ps_axi_slave_b_bits_id (M_AXI_bid), 350 | .io_ps_axi_slave_b_bits_resp (M_AXI_bresp), 351 | 352 | .io_mem_axi_ar_valid (S_AXI_arvalid), 353 | .io_mem_axi_ar_ready (S_AXI_arready), 354 | .io_mem_axi_ar_bits_addr (S_AXI_araddr), 355 | .io_mem_axi_ar_bits_id (S_AXI_arid), 356 | .io_mem_axi_ar_bits_size (S_AXI_arsize), 357 | .io_mem_axi_ar_bits_len (S_AXI_arlen), 358 | .io_mem_axi_ar_bits_burst (S_AXI_arburst), 359 | .io_mem_axi_ar_bits_cache (S_AXI_arcache), 360 | .io_mem_axi_ar_bits_lock (S_AXI_arlock), 361 | .io_mem_axi_ar_bits_prot (S_AXI_arprot), 362 | .io_mem_axi_ar_bits_qos (S_AXI_arqos), 363 | .io_mem_axi_aw_valid (S_AXI_awvalid), 364 | .io_mem_axi_aw_ready (S_AXI_awready), 365 | .io_mem_axi_aw_bits_addr (S_AXI_awaddr), 366 | .io_mem_axi_aw_bits_id (S_AXI_awid), 367 | .io_mem_axi_aw_bits_size (S_AXI_awsize), 368 | .io_mem_axi_aw_bits_len (S_AXI_awlen), 369 | .io_mem_axi_aw_bits_burst (S_AXI_awburst), 370 | .io_mem_axi_aw_bits_cache (S_AXI_awcache), 371 | .io_mem_axi_aw_bits_lock (S_AXI_awlock), 372 | .io_mem_axi_aw_bits_prot (S_AXI_awprot), 373 | .io_mem_axi_aw_bits_qos (S_AXI_awqos), 374 | .io_mem_axi_w_valid (S_AXI_wvalid), 375 | .io_mem_axi_w_ready (S_AXI_wready), 376 | .io_mem_axi_w_bits_strb (S_AXI_wstrb), 377 | .io_mem_axi_w_bits_data (S_AXI_wdata), 378 | .io_mem_axi_w_bits_last (S_AXI_wlast), 379 | .io_mem_axi_b_valid (S_AXI_bvalid), 380 | .io_mem_axi_b_ready (S_AXI_bready), 381 | .io_mem_axi_b_bits_resp (S_AXI_bresp), 382 | .io_mem_axi_b_bits_id (S_AXI_bid), 383 | .io_mem_axi_r_valid (S_AXI_rvalid), 384 | .io_mem_axi_r_ready (S_AXI_rready), 385 | .io_mem_axi_r_bits_resp (S_AXI_rresp), 386 | .io_mem_axi_r_bits_id (S_AXI_rid), 387 | .io_mem_axi_r_bits_data (S_AXI_rdata), 388 | .io_mem_axi_r_bits_last (S_AXI_rlast) 389 | ); 390 | `ifndef differential_clock 391 | IBUFG ibufg_gclk (.I(clk), .O(gclk_i)); 392 | `else 393 | IBUFDS #(.DIFF_TERM("TRUE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) clk_ibufds (.O(gclk_i), .I(SYSCLK_P), .IB(SYSCLK_N)); 394 | `endif 395 | BUFG bufg_host_clk (.I(host_clk_i), .O(host_clk)); 396 | 397 | MMCME2_BASE #( 398 | .BANDWIDTH("OPTIMIZED"), 399 | .CLKFBOUT_MULT_F(`RC_CLK_MULT), 400 | .CLKFBOUT_PHASE(0.0), 401 | .CLKIN1_PERIOD(`ZYNQ_CLK_PERIOD), 402 | .CLKOUT1_DIVIDE(1), 403 | .CLKOUT2_DIVIDE(1), 404 | .CLKOUT3_DIVIDE(1), 405 | .CLKOUT4_DIVIDE(1), 406 | .CLKOUT5_DIVIDE(1), 407 | .CLKOUT6_DIVIDE(1), 408 | .CLKOUT0_DIVIDE_F(`RC_CLK_DIVIDE), 409 | .CLKOUT0_DUTY_CYCLE(0.5), 410 | .CLKOUT1_DUTY_CYCLE(0.5), 411 | .CLKOUT2_DUTY_CYCLE(0.5), 412 | .CLKOUT3_DUTY_CYCLE(0.5), 413 | .CLKOUT4_DUTY_CYCLE(0.5), 414 | .CLKOUT5_DUTY_CYCLE(0.5), 415 | .CLKOUT6_DUTY_CYCLE(0.5), 416 | .CLKOUT0_PHASE(0.0), 417 | .CLKOUT1_PHASE(0.0), 418 | .CLKOUT2_PHASE(0.0), 419 | .CLKOUT3_PHASE(0.0), 420 | .CLKOUT4_PHASE(0.0), 421 | .CLKOUT5_PHASE(0.0), 422 | .CLKOUT6_PHASE(0.0), 423 | .CLKOUT4_CASCADE("FALSE"), 424 | .DIVCLK_DIVIDE(1), 425 | .REF_JITTER1(0.0), 426 | .STARTUP_WAIT("FALSE") 427 | ) MMCME2_BASE_inst ( 428 | .CLKOUT0(host_clk_i), 429 | .CLKOUT0B(), 430 | .CLKOUT1(), 431 | .CLKOUT1B(), 432 | .CLKOUT2(), 433 | .CLKOUT2B(), 434 | .CLKOUT3(), 435 | .CLKOUT3B(), 436 | .CLKOUT4(), 437 | .CLKOUT5(), 438 | .CLKOUT6(), 439 | .CLKFBOUT(gclk_fbout), 440 | .CLKFBOUTB(), 441 | .LOCKED(mmcm_locked), 442 | .CLKIN1(gclk_i), 443 | .PWRDWN(1'b0), 444 | .RST(1'b0), 445 | .CLKFBIN(gclk_fbout)); 446 | 447 | endmodule 448 | -------------------------------------------------------------------------------- /zedboard/Makefile: -------------------------------------------------------------------------------- 1 | BOARD = zedboard 2 | UBOOT_CONFIG = zed 3 | BOARD_MODEL = em.avnet.com:zed:part0:1.0 4 | PART = xc7z020clg484-1 5 | TOP_MODULE_PROJECT = zynq 6 | CONFIG = ZynqFPGAConfig 7 | 8 | include ../common/Makefrag 9 | -------------------------------------------------------------------------------- /zedboard/soft_config/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /zedboard/soft_config/zedboard_devicetree.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 - 2014 Xilinx 3 | * Copyright (C) 2012 National Instruments Corp. 4 | * 5 | * This software is licensed under the terms of the GNU General Public 6 | * License version 2, as published by the Free Software Foundation, and 7 | * may be copied, distributed, and modified under those terms. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | */ 14 | /dts-v1/; 15 | /include/ "zynq-7000.dtsi" 16 | 17 | / { 18 | model = "Zynq Zed Development Board"; 19 | compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; 20 | 21 | aliases { 22 | ethernet0 = &gem0; 23 | serial0 = &uart1; 24 | spi0 = &qspi; 25 | }; 26 | 27 | memory { 28 | device_type = "memory"; 29 | reg = <0x0 0x10000000>; 30 | }; 31 | 32 | htif_0: htif@43c00000 { 33 | #address-cells = <1>; 34 | #size-cells = <1>; 35 | compatible = "generic-uio", "uio", "uio_pdrv"; 36 | reg = <0x43c00000 0x1000>; 37 | }; 38 | 39 | chosen { 40 | bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; 41 | linux,stdout-path = "/amba/serial@e0001000"; 42 | }; 43 | }; 44 | 45 | &qspi { 46 | status = "okay"; 47 | is-dual = <0>; 48 | num-cs = <1>; 49 | xlnx,fb-clk = <0x1>; 50 | xlnx,qspi-mode = <0x0>; 51 | flash@0 { 52 | compatible = "n25q128"; 53 | reg = <0x0>; 54 | spi-tx-bus-width = <1>; 55 | spi-rx-bus-width = <4>; 56 | spi-max-frequency = <50000000>; 57 | #address-cells = <1>; 58 | #size-cells = <1>; 59 | partition@qspi-fsbl-uboot { 60 | label = "qspi-fsbl-uboot"; 61 | reg = <0x0 0x100000>; 62 | }; 63 | partition@qspi-linux { 64 | label = "qspi-linux"; 65 | reg = <0x100000 0x500000>; 66 | }; 67 | partition@qspi-device-tree { 68 | label = "qspi-device-tree"; 69 | reg = <0x600000 0x20000>; 70 | }; 71 | partition@qspi-rootfs { 72 | label = "qspi-rootfs"; 73 | reg = <0x620000 0x5E0000>; 74 | }; 75 | partition@qspi-bitstream { 76 | label = "qspi-bitstream"; 77 | reg = <0xC00000 0x400000>; 78 | }; 79 | }; 80 | }; 81 | 82 | &usb0 { 83 | status = "okay"; 84 | dr_mode = "host"; 85 | phy_type = "ulpi"; 86 | }; 87 | 88 | &gem0 { 89 | status = "okay"; 90 | phy-mode = "rgmii-id"; 91 | 92 | phy0: phy@0 { 93 | reg = <0>; 94 | }; 95 | }; 96 | 97 | &sdhci0 { 98 | status = "okay"; 99 | }; 100 | 101 | &uart1 { 102 | status = "okay"; 103 | }; 104 | -------------------------------------------------------------------------------- /zedboard/soft_config/zynq-7000.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2011 - 2014 Xilinx 3 | * 4 | * This software is licensed under the terms of the GNU General Public 5 | * License version 2, as published by the Free Software Foundation, and 6 | * may be copied, distributed, and modified under those terms. 7 | * 8 | * This program is distributed in the hope that it will be useful, 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | * GNU General Public License for more details. 12 | */ 13 | /include/ "skeleton.dtsi" 14 | 15 | / { 16 | compatible = "xlnx,zynq-7000"; 17 | 18 | cpus { 19 | #address-cells = <1>; 20 | #size-cells = <0>; 21 | 22 | cpu@0 { 23 | compatible = "arm,cortex-a9"; 24 | device_type = "cpu"; 25 | reg = <0>; 26 | clocks = <&clkc 3>; 27 | clock-latency = <1000>; 28 | cpu0-supply = <®ulator_vccpint>; 29 | operating-points = < 30 | /* kHz uV */ 31 | 666667 1000000 32 | 333334 1000000 33 | 222223 1000000 34 | >; 35 | }; 36 | 37 | cpu@1 { 38 | compatible = "arm,cortex-a9"; 39 | device_type = "cpu"; 40 | reg = <1>; 41 | clocks = <&clkc 3>; 42 | }; 43 | }; 44 | 45 | pmu { 46 | compatible = "arm,cortex-a9-pmu"; 47 | interrupts = <0 5 4>, <0 6 4>; 48 | interrupt-parent = <&intc>; 49 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; 50 | }; 51 | 52 | regulator_vccpint: fixedregulator@0 { 53 | compatible = "regulator-fixed"; 54 | regulator-name = "VCCPINT"; 55 | regulator-min-microvolt = <1000000>; 56 | regulator-max-microvolt = <1000000>; 57 | regulator-boot-on; 58 | regulator-always-on; 59 | }; 60 | 61 | amba { 62 | compatible = "simple-bus"; 63 | #address-cells = <1>; 64 | #size-cells = <1>; 65 | interrupt-parent = <&intc>; 66 | ranges; 67 | 68 | adc@f8007100 { 69 | compatible = "xlnx,zynq-xadc-1.00.a"; 70 | reg = <0xf8007100 0x20>; 71 | interrupts = <0 7 4>; 72 | interrupt-parent = <&intc>; 73 | clocks = <&clkc 12>; 74 | }; 75 | 76 | can0: can@e0008000 { 77 | compatible = "xlnx,zynq-can-1.0"; 78 | status = "disabled"; 79 | clocks = <&clkc 19>, <&clkc 36>; 80 | clock-names = "ref_clk", "aper_clk"; 81 | reg = <0xe0008000 0x1000>; 82 | interrupts = <0 28 4>; 83 | interrupt-parent = <&intc>; 84 | }; 85 | 86 | can1: can@e0009000 { 87 | compatible = "xlnx,zynq-can-1.0"; 88 | status = "disabled"; 89 | clocks = <&clkc 20>, <&clkc 37>; 90 | clock-names = "ref_clk", "aper_clk"; 91 | reg = <0xe0009000 0x1000>; 92 | interrupts = <0 51 4>; 93 | interrupt-parent = <&intc>; 94 | }; 95 | 96 | gpio0: gpio@e000a000 { 97 | compatible = "xlnx,zynq-gpio-1.0"; 98 | #gpio-cells = <2>; 99 | clocks = <&clkc 42>; 100 | gpio-controller; 101 | interrupt-parent = <&intc>; 102 | interrupts = <0 20 4>; 103 | reg = <0xe000a000 0x1000>; 104 | }; 105 | 106 | i2c0: i2c@e0004000 { 107 | compatible = "cdns,i2c-r1p10"; 108 | status = "disabled"; 109 | clocks = <&clkc 38>; 110 | interrupt-parent = <&intc>; 111 | interrupts = <0 25 4>; 112 | reg = <0xe0004000 0x1000>; 113 | #address-cells = <1>; 114 | #size-cells = <0>; 115 | }; 116 | 117 | i2c1: i2c@e0005000 { 118 | compatible = "cdns,i2c-r1p10"; 119 | status = "disabled"; 120 | clocks = <&clkc 39>; 121 | interrupt-parent = <&intc>; 122 | interrupts = <0 48 4>; 123 | reg = <0xe0005000 0x1000>; 124 | #address-cells = <1>; 125 | #size-cells = <0>; 126 | }; 127 | 128 | intc: interrupt-controller@f8f01000 { 129 | compatible = "arm,cortex-a9-gic"; 130 | #interrupt-cells = <3>; 131 | interrupt-controller; 132 | reg = <0xF8F01000 0x1000>, 133 | <0xF8F00100 0x100>; 134 | }; 135 | 136 | L2: cache-controller { 137 | compatible = "arm,pl310-cache"; 138 | reg = <0xF8F02000 0x1000>; 139 | arm,data-latency = <3 2 2>; 140 | arm,tag-latency = <2 2 2>; 141 | cache-unified; 142 | cache-level = <2>; 143 | }; 144 | 145 | memory-controller@f8006000 { 146 | compatible = "xlnx,zynq-ddrc-1.0"; 147 | reg = <0xf8006000 0x1000>; 148 | xlnx,has-ecc = <0x0>; 149 | }; 150 | 151 | ocmc: ocmc@f800c000 { 152 | compatible = "xlnx,zynq-ocmc-1.0"; 153 | interrupt-parent = <&intc>; 154 | interrupts = <0 3 4>; 155 | reg = <0xf800c000 0x1000>; 156 | }; 157 | 158 | uart0: serial@e0000000 { 159 | compatible = "xlnx,xuartps"; 160 | status = "disabled"; 161 | clocks = <&clkc 23>, <&clkc 40>; 162 | clock-names = "ref_clk", "aper_clk"; 163 | reg = <0xE0000000 0x1000>; 164 | interrupts = <0 27 4>; 165 | }; 166 | 167 | uart1: serial@e0001000 { 168 | compatible = "xlnx,xuartps"; 169 | status = "disabled"; 170 | clocks = <&clkc 24>, <&clkc 41>; 171 | clock-names = "ref_clk", "aper_clk"; 172 | reg = <0xE0001000 0x1000>; 173 | interrupts = <0 50 4>; 174 | }; 175 | 176 | spi0: spi@e0006000 { 177 | compatible = "xlnx,zynq-spi-r1p6"; 178 | reg = <0xe0006000 0x1000>; 179 | status = "disabled"; 180 | interrupt-parent = <&intc>; 181 | interrupts = <0 26 4>; 182 | clocks = <&clkc 25>, <&clkc 34>; 183 | clock-names = "ref_clk", "pclk"; 184 | #address-cells = <1>; 185 | #size-cells = <0>; 186 | }; 187 | 188 | spi1: spi@e0007000 { 189 | compatible = "xlnx,zynq-spi-r1p6"; 190 | reg = <0xe0007000 0x1000>; 191 | status = "disabled"; 192 | interrupt-parent = <&intc>; 193 | interrupts = <0 49 4>; 194 | clocks = <&clkc 26>, <&clkc 35>; 195 | clock-names = "ref_clk", "pclk"; 196 | #address-cells = <1>; 197 | #size-cells = <0>; 198 | }; 199 | 200 | qspi: spi@e000d000 { 201 | clock-names = "ref_clk", "pclk"; 202 | clocks = <&clkc 10>, <&clkc 43>; 203 | compatible = "xlnx,zynq-qspi-1.0"; 204 | status = "disabled"; 205 | interrupt-parent = <&intc>; 206 | interrupts = <0 19 4>; 207 | reg = <0xe000d000 0x1000>; 208 | #address-cells = <1>; 209 | #size-cells = <0>; 210 | }; 211 | 212 | smcc: memory-controller@e000e000 { 213 | #address-cells = <1>; 214 | #size-cells = <1>; 215 | status = "disabled"; 216 | clock-names = "memclk", "aclk"; 217 | clocks = <&clkc 11>, <&clkc 44>; 218 | compatible = "arm,pl353-smc-r2p1"; 219 | interrupt-parent = <&intc>; 220 | interrupts = <0 18 4>; 221 | ranges ; 222 | reg = <0xe000e000 0x1000>; 223 | nand0: flash@e1000000 { 224 | status = "disabled"; 225 | compatible = "arm,pl353-nand-r2p1"; 226 | reg = <0xe1000000 0x1000000>; 227 | #address-cells = <0x1>; 228 | #size-cells = <0x1>; 229 | }; 230 | nor0: flash@e2000000 { 231 | status = "disabled"; 232 | compatible = "cfi-flash"; 233 | reg = <0xe2000000 0x1000>; 234 | #address-cells = <1>; 235 | #size-cells = <1>; 236 | }; 237 | }; 238 | 239 | gem0: ethernet@e000b000 { 240 | compatible = "cdns,gem"; 241 | reg = <0xe000b000 0x4000>; 242 | status = "disabled"; 243 | interrupts = <0 22 4>; 244 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 245 | clock-names = "pclk", "hclk", "tx_clk"; 246 | #address-cells = <1>; 247 | #size-cells = <0>; 248 | }; 249 | 250 | gem1: ethernet@e000c000 { 251 | compatible = "cdns,gem"; 252 | reg = <0xe000c000 0x4000>; 253 | status = "disabled"; 254 | interrupts = <0 45 4>; 255 | clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 256 | clock-names = "pclk", "hclk", "tx_clk"; 257 | #address-cells = <1>; 258 | #size-cells = <0>; 259 | }; 260 | 261 | sdhci0: sdhci@e0100000 { 262 | compatible = "arasan,sdhci-8.9a"; 263 | status = "disabled"; 264 | clock-names = "clk_xin", "clk_ahb"; 265 | clocks = <&clkc 21>, <&clkc 32>; 266 | interrupt-parent = <&intc>; 267 | interrupts = <0 24 4>; 268 | reg = <0xe0100000 0x1000>; 269 | }; 270 | 271 | sdhci1: sdhci@e0101000 { 272 | compatible = "arasan,sdhci-8.9a"; 273 | status = "disabled"; 274 | clock-names = "clk_xin", "clk_ahb"; 275 | clocks = <&clkc 22>, <&clkc 33>; 276 | interrupt-parent = <&intc>; 277 | interrupts = <0 47 4>; 278 | reg = <0xe0101000 0x1000>; 279 | }; 280 | 281 | slcr: slcr@f8000000 { 282 | #address-cells = <1>; 283 | #size-cells = <1>; 284 | compatible = "xlnx,zynq-slcr", "syscon"; 285 | reg = <0xF8000000 0x1000>; 286 | ranges; 287 | clkc: clkc@100 { 288 | #clock-cells = <1>; 289 | compatible = "xlnx,ps7-clkc"; 290 | ps-clk-frequency = <33333333>; 291 | fclk-enable = <0>; 292 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 293 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 294 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 295 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 296 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 297 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", 298 | "gem1_aper", "sdio0_aper", "sdio1_aper", 299 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 300 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 301 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 302 | "dbg_trc", "dbg_apb"; 303 | reg = <0x100 0x100>; 304 | }; 305 | }; 306 | 307 | dmac_s: dmac@f8003000 { 308 | compatible = "arm,pl330", "arm,primecell"; 309 | reg = <0xf8003000 0x1000>; 310 | interrupt-parent = <&intc>; 311 | interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 312 | "dma4", "dma5", "dma6", "dma7"; 313 | interrupts = <0 13 4>, 314 | <0 14 4>, <0 15 4>, 315 | <0 16 4>, <0 17 4>, 316 | <0 40 4>, <0 41 4>, 317 | <0 42 4>, <0 43 4>; 318 | #dma-cells = <1>; 319 | #dma-channels = <8>; 320 | #dma-requests = <4>; 321 | clocks = <&clkc 27>; 322 | clock-names = "apb_pclk"; 323 | }; 324 | 325 | devcfg: devcfg@f8007000 { 326 | clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 327 | clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 328 | compatible = "xlnx,zynq-devcfg-1.0"; 329 | interrupt-parent = <&intc>; 330 | interrupts = <0 8 4>; 331 | reg = <0xf8007000 0x100>; 332 | }; 333 | 334 | global_timer: timer@f8f00200 { 335 | compatible = "arm,cortex-a9-global-timer"; 336 | reg = <0xf8f00200 0x20>; 337 | interrupts = <1 11 0x301>; 338 | interrupt-parent = <&intc>; 339 | clocks = <&clkc 4>; 340 | }; 341 | 342 | ttc0: timer@f8001000 { 343 | interrupt-parent = <&intc>; 344 | interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 345 | compatible = "cdns,ttc"; 346 | clocks = <&clkc 6>; 347 | reg = <0xF8001000 0x1000>; 348 | }; 349 | 350 | ttc1: timer@f8002000 { 351 | interrupt-parent = <&intc>; 352 | interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 353 | compatible = "cdns,ttc"; 354 | clocks = <&clkc 6>; 355 | reg = <0xF8002000 0x1000>; 356 | }; 357 | 358 | scutimer: timer@f8f00600 { 359 | interrupt-parent = <&intc>; 360 | interrupts = <1 13 0x301>; 361 | compatible = "arm,cortex-a9-twd-timer"; 362 | reg = <0xf8f00600 0x20>; 363 | clocks = <&clkc 4>; 364 | }; 365 | 366 | watchdog0: watchdog@f8005000 { 367 | clocks = <&clkc 45>; 368 | compatible = "xlnx,zynq-wdt-r1p2"; 369 | device_type = "watchdog"; 370 | interrupt-parent = <&intc>; 371 | interrupts = <0 9 1>; 372 | reg = <0xf8005000 0x1000>; 373 | reset = <0>; 374 | timeout-sec = <10>; 375 | }; 376 | 377 | scuwatchdog: watchdog@f8f00620 { 378 | clocks = <&clkc 4>; 379 | compatible = "xlnx,ps7-scuwdt-1.00.a"; 380 | device_type = "watchdog"; 381 | interrupt-parent = <&intc>; 382 | interrupts = <1 14 0x301>; 383 | reg = <0xf8f00620 0xe0>; 384 | }; 385 | 386 | usb0: usb@e0002000 { 387 | clocks = <&clkc 28>; 388 | compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; 389 | status = "disabled"; 390 | interrupt-parent = <&intc>; 391 | interrupts = <0 21 4>; 392 | reg = <0xe0002000 0x1000>; 393 | }; 394 | 395 | usb1: usb@e0003000 { 396 | clocks = <&clkc 29>; 397 | compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; 398 | status = "disabled"; 399 | interrupt-parent = <&intc>; 400 | interrupts = <0 44 4>; 401 | reg = <0xe0003000 0x1000>; 402 | }; 403 | }; 404 | }; 405 | -------------------------------------------------------------------------------- /zedboard/soft_config/zynq_zed.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Xilinx, Inc. 3 | * 4 | * Configuration for Zynq Evaluation and Development Board - ZedBoard 5 | * See zynq-common.h for Zynq common configs 6 | * 7 | * SPDX-License-Identifier: GPL-2.0+ 8 | */ 9 | 10 | #ifndef __CONFIG_ZYNQ_ZED_H 11 | #define __CONFIG_ZYNQ_ZED_H 12 | 13 | #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 14 | 15 | #define CONFIG_ZYNQ_SERIAL_UART1 16 | #define CONFIG_ZYNQ_GEM0 17 | #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 18 | 19 | #define CONFIG_SYS_NO_FLASH 20 | 21 | #define CONFIG_ZYNQ_USB 22 | #define CONFIG_ZYNQ_SDHCI0 23 | #define CONFIG_ZYNQ_QSPI 24 | 25 | #define CONFIG_ZYNQ_BOOT_FREEBSD 26 | #define CONFIG_DEFAULT_DEVICE_TREE zynq-zed 27 | 28 | #include 29 | 30 | #endif /* __CONFIG_ZYNQ_ZED_H */ 31 | -------------------------------------------------------------------------------- /zedboard/src/constrs/base.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN Y9 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | create_clock -name gclk_0 -period "10" -waveform {0.0 5.0} [get_ports clk] 4 | -------------------------------------------------------------------------------- /zedboard/src/verilog/clocking.vh: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Rocket Chip Clock Configuration 4 | 5 | 6 | Rocket Chip 1000 RC_CLK_MULT 7 | Clockrate = --------------- X ------------- 8 | (in MHz) ZYNQ_CLK_PERIOD RC_CLK_DIVIDE 9 | 10 | 11 | This sets the parameters used by rocketchip_wrapper.v to 12 | generate its own clock. 13 | 14 | Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE. 15 | ZYNQ_CLK_PERIOD should only be changed to match the input 16 | clock period set in the Vivado GUI and 17 | hw/src/constrs/pin_constraints.xdc 18 | 19 | */ 20 | 21 | 22 | `ifndef _clocking_vh_ 23 | `define _clocking_vh_ 24 | 25 | 26 | `define ZYNQ_CLK_PERIOD 10.0 27 | 28 | `define RC_CLK_MULT 10.0 29 | 30 | `define RC_CLK_DIVIDE 40.0 31 | 32 | 33 | `endif // _clocking_vh_ 34 | --------------------------------------------------------------------------------