├── .github └── workflows │ ├── build.yml │ └── remove-old-artifacts.yml ├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── gen_vector_type_infos.py ├── images ├── draft.png └── risc-v_logo.png ├── introduction.adoc ├── policy.md ├── preamble.adoc ├── prelude.adoc ├── resources ├── fonts │ ├── DroidSans-Bold.ttf │ ├── DroidSans.ttf │ ├── cmunbbx.ttf │ ├── cmunbmo.ttf │ ├── cmunbmr.ttf │ ├── cmunbso.ttf │ ├── cmunbtl.ttf │ ├── cmunbto.ttf │ ├── cmunbxo.ttf │ ├── cmunsi.ttf │ ├── cmunso.ttf │ ├── cmunss.ttf │ ├── cmunsx.ttf │ ├── droid-sans-fallback.ttf │ ├── mplus-1mn-bold.ttf │ ├── mplus-1mn-light.ttf │ ├── mplus-1mn-medium.ttf │ ├── mplus-1mn-regular.ttf │ ├── mplus-1mn-thin.ttf │ ├── mplus-1p-black.ttf │ ├── mplus-1p-bold.ttf │ ├── mplus-1p-heavy.ttf │ ├── mplus-1p-light.ttf │ ├── mplus-1p-medium.ttf │ ├── mplus-1p-regular-fallback.ttf │ ├── mplus-1p-regular.ttf │ └── mplus-1p-thin.ttf └── themes │ └── risc-v_spec-pdf.yml ├── riscv-abi.adoc ├── riscv-atomic.adoc ├── riscv-cc.adoc ├── riscv-dwarf.adoc ├── riscv-elf.adoc ├── riscv-rtabi.adoc └── vector_type_infos.adoc /.github/workflows/build.yml: -------------------------------------------------------------------------------- 1 | name: Build 2 | 3 | on: 4 | push: 5 | branches: 6 | - master 7 | pull_request: 8 | release: 9 | types: 10 | - created 11 | 12 | jobs: 13 | build: 14 | runs-on: ubuntu-latest 15 | steps: 16 | - uses: actions/checkout@v4 17 | 18 | - name: Install packages 19 | run: sudo apt-get update && sudo apt-get install -y make ruby 20 | 21 | - name: Install gems 22 | run: sudo gem install asciidoctor asciidoctor-pdf 23 | 24 | - name: Build 25 | run: make 26 | 27 | - name: Upload artifact 28 | uses: actions/upload-artifact@v4 29 | with: 30 | name: riscv-abi.pdf 31 | path: riscv-abi.pdf 32 | 33 | draft-release: 34 | if: github.event_name == 'push' && github.ref == 'refs/heads/master' 35 | needs: build 36 | runs-on: ubuntu-latest 37 | steps: 38 | - name: Download artifact 39 | uses: actions/download-artifact@v4 40 | with: 41 | name: riscv-abi.pdf 42 | path: ./ 43 | 44 | - name: Get current date 45 | id: date 46 | run: echo "::set-output name=date::$(date -u +'%Y%m%d')" 47 | 48 | - name: Create release 49 | id: create_release 50 | uses: actions/create-release@v1 51 | env: 52 | GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} 53 | with: 54 | tag_name: draft-${{ steps.date.outputs.date }}-${{ github.sha }} 55 | release_name: Draft release ${{ steps.date.outputs.date }} 56 | body: Latest snapshot (${{ github.sha }}) 57 | prerelease: true 58 | 59 | - name: Upload release asset 60 | id: upload-release-asset 61 | uses: actions/upload-release-asset@v1 62 | env: 63 | GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} 64 | with: 65 | upload_url: ${{ steps.create_release.outputs.upload_url }} 66 | asset_path: riscv-abi.pdf 67 | asset_name: riscv-abi.pdf 68 | asset_content_type: application/pdf 69 | 70 | release: 71 | if: github.event_name == 'release' && github.event.action == 'created' 72 | needs: build 73 | runs-on: ubuntu-latest 74 | steps: 75 | - name: Download artifact 76 | uses: actions/download-artifact@v4 77 | with: 78 | name: riscv-abi.pdf 79 | path: ./ 80 | 81 | - name: Upload release asset 82 | id: upload-release-asset 83 | uses: actions/upload-release-asset@v1 84 | env: 85 | GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} 86 | with: 87 | upload_url: ${{ github.event.release.upload_url }} 88 | asset_path: riscv-abi.pdf 89 | asset_name: riscv-abi.pdf 90 | asset_content_type: application/pdf 91 | -------------------------------------------------------------------------------- /.github/workflows/remove-old-artifacts.yml: -------------------------------------------------------------------------------- 1 | name: Remove old artifacts 2 | 3 | on: 4 | workflow_dispatch: 5 | schedule: 6 | # Every day at 1am 7 | - cron: '0 1 * * *' 8 | 9 | jobs: 10 | remove-old-artifacts: 11 | runs-on: ubuntu-latest 12 | timeout-minutes: 10 13 | 14 | steps: 15 | - name: Remove old artifacts 16 | uses: c-hive/gha-remove-artifacts@v1 17 | with: 18 | age: '1 month' 19 | skip-tags: true 20 | skip-recent: 10 21 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | *.pdf 3 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Attribution 4.0 International 2 | 3 | ======================================================================= 4 | 5 | Creative Commons Corporation ("Creative Commons") is not a law firm and 6 | does not provide legal services or legal advice. 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For 392 | the avoidance of doubt, this paragraph does not form part of the 393 | public licenses. 394 | 395 | Creative Commons may be contacted at creativecommons.org. 396 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | NAME = riscv-abi 2 | 3 | DATE = $(shell date '+%B %d, %Y') 4 | MONTHYEAR = $(shell date '+%B %Y') 5 | 6 | .PHONY: all 7 | all: $(NAME).pdf 8 | 9 | .PHONY: clean 10 | clean: 11 | rm -f $(NAME).pdf 12 | 13 | $(NAME).pdf: $(NAME).adoc $(wildcard *.adoc) resources/themes/risc-v_spec-pdf.yml 14 | asciidoctor-pdf \ 15 | -a compress \ 16 | -a date="$(DATE)" \ 17 | -a monthyear="$(MONTHYEAR)" \ 18 | -a pdf-style=resources/themes/risc-v_spec-pdf.yml \ 19 | -a pdf-fontsdir=resources/fonts \ 20 | -v \ 21 | $< -o $@ 22 | 23 | regen_vector_type_infos: 24 | python3 gen_vector_type_infos.py > vector_type_infos.adoc 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V ELF psABI Document 2 | Processor-specific application binary interface document for RISC-V. 3 | 4 | This document includes the following items: 5 | - Procedure Calling Convention 6 | - ELF Object Files Format 7 | - DWARF Debug Information Format 8 | - Code Model 9 | - Relocation 10 | - Relaxation 11 | 12 | The AsciiDoc sources can be rendered by GitHub, and pre-built PDFs can be downloaded from the repository's [releases](https://github.com/riscv/riscv-elf-psabi-doc/releases). 13 | 14 | # Navigation 15 | ---------------------------------------------------------------------------------------------------------- 16 | Name | URL | Description 17 | ------------------------------------|-------------------------------------------------------|-------------- 18 | RISC-V ELF psABI | https://github.com/riscv-non-isa/riscv-elf-psabi-doc | Processor-specific application binary interface document. 19 | RISC-V Embedded ABI (Draft) | https://github.com/riscv-non-isa/riscv-eabi-spec | Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems. 20 | RISC-V C API | https://github.com/riscv-non-isa/riscv-c-api-doc | RISC-V-specific predefined macros, function attributes and language extensions. 21 | RISC-V Assembly Programmer's Manual | https://github.com/riscv-non-isa/riscv-asm-manual | Document for pseudoinstructions and assembly directives. 22 | RISC-V Toolchain Conventions | https://github.com/riscv-non-isa/riscv-toolchain-conventions | RISC-V-specific toolchain behavior and command line option. 23 | RISC-V Semihosting Spec | https://github.com/riscv/riscv-semihosting-spec | Spec for semihosting. 24 | RISC-V Supervisor Binary Interface | https://github.com/riscv-non-isa/riscv-sbi-doc | Spec for SBI. 25 | 26 | # Links 27 | [Policy for Merging Pull Requests](policy.md) 28 | -------------------------------------------------------------------------------- /gen_vector_type_infos.py: -------------------------------------------------------------------------------- 1 | import subprocess 2 | import os 3 | import sys 4 | import math 5 | 6 | LMUL=["mf8", "mf4", "mf2", "m1", "m2", "m4", "m8"] 7 | NF=[2, 3, 4, 5, 6, 7, 8] 8 | SEW=[8, 16, 32, 64] 9 | TYPES = ["int", "uint", "float", "bfloat"] 10 | 11 | def lmul2nreg(lmul): 12 | if (lmul.startswith("mf")): 13 | return 1 14 | else: 15 | return int(lmul[1:]) 16 | 17 | def lmul2num(lmul): 18 | if (lmul.startswith("mf")): 19 | if lmul=="mf8": 20 | return 0.125 21 | if lmul=="mf4": 22 | return 0.25 23 | if lmul=="mf2": 24 | return 0.5 25 | assert false 26 | else: 27 | return int(lmul[1:]) 28 | 29 | def sizestr(lmul, nf=1): 30 | sz_mul = lmul2num(lmul) * nf 31 | if (sz_mul == 1): 32 | return "(VLEN / 8)" 33 | if (sz_mul > 1): 34 | return "(VLEN / 8) * %g" %(sz_mul) 35 | if (sz_mul < 1): 36 | if (sz_mul == 0.5): 37 | return "(VLEN / 8) / 2" 38 | if (sz_mul == 0.25): 39 | return "(VLEN / 8) / 4" 40 | if (sz_mul == 0.125): 41 | return "(VLEN / 8) / 8" 42 | if (sz_mul == 0.375): 43 | return "(VLEN / 8) * 0.375" 44 | if (sz_mul == 0.625): 45 | return "(VLEN / 8) * 0.625" 46 | if (sz_mul == 0.75): 47 | return "(VLEN / 8) * 0.75" 48 | if (sz_mul == 0.875): 49 | return "(VLEN / 8) * 0.875" 50 | assert false 51 | 52 | def valid_type(sew, lmul, base_t, nf=1): 53 | nreg = lmul2nreg(lmul) 54 | if nreg * nf > 8: 55 | return False 56 | if t == "bfloat" and sew != 16: 57 | return False 58 | if t == "float" and sew == 16: 59 | return False 60 | return True 61 | 62 | def get_note(sew, lmul, base_t, nf=1): 63 | ln = lmul2num(lmul) 64 | x = (32 / sew * ln) 65 | notes = [] 66 | if (32 / sew * ln) < 1: 67 | notes += ["`*1`"] 68 | if base_t == "float" and sew == 16: 69 | notes += ["`*2`"] 70 | if base_t == "bfloat": 71 | notes += ["`*3`"] 72 | if base_t == "float" and sew == 32: 73 | notes += ["`*4`"] 74 | if base_t == "float" and sew == 64: 75 | notes += ["`*5`"] 76 | if (base_t == "int" or base_t == "uint") and sew == 64: 77 | notes += ["`*6`"] 78 | return ", ".join(notes) 79 | 80 | print (".Type sizes and alignments for vector data types") 81 | print ("[cols=\"4,3,>3,>2\"]") 82 | print ("[width=80%]") 83 | print ("|===") 84 | print ("| Internal Name | Type | Size (Bytes) | Alignment (Bytes)") 85 | print("") 86 | 87 | for sew in SEW: 88 | for lmul in LMUL: 89 | for t in TYPES: 90 | if not valid_type(sew, lmul, t): 91 | continue 92 | typename = "v%s%s%s_t" %(t, sew, lmul) 93 | mname = "__rvv_" + typename 94 | size = sizestr(lmul) 95 | print ("| %-22s | %-20s | %-18s | %d" %(mname, typename, size, sew/8)) 96 | print ("|===") 97 | print ("") 98 | 99 | print (".Type sizes and alignments for vector tuple types") 100 | print ("[cols=\"4,3,>3,>2\"]") 101 | print ("[width=80%]") 102 | print ("|===") 103 | 104 | print ("| Internal Name | Type | Size (Bytes) | Alignment (Bytes)") 105 | print ("") 106 | for sew in SEW: 107 | for lmul in LMUL: 108 | for nf in NF: 109 | for t in TYPES: 110 | if not valid_type(sew, lmul, t, nf): 111 | continue 112 | typename = "v%s%s%sx%s_t" %(t, sew, lmul, nf) 113 | mname = "__rvv_" + typename 114 | size = sizestr(lmul, nf) 115 | print ("| %-22s | %-20s | %-18s | %d" %(mname, typename, size, sew/8)) 116 | print ("|===") 117 | -------------------------------------------------------------------------------- /images/draft.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-non-isa/riscv-elf-psabi-doc/87aecf601722171c570120a46003be3c17ad3108/images/draft.png -------------------------------------------------------------------------------- /images/risc-v_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-non-isa/riscv-elf-psabi-doc/87aecf601722171c570120a46003be3c17ad3108/images/risc-v_logo.png -------------------------------------------------------------------------------- /introduction.adoc: -------------------------------------------------------------------------------- 1 | = Introduction 2 | 3 | This specification provides the processor-specific application binary interface 4 | document for RISC-V. 5 | 6 | This specification consists of the following three parts: 7 | 8 | - Calling convention 9 | - ELF specification 10 | - DWARF specification 11 | 12 | A future revision of this ABI will include a canonical set of mappings for 13 | memory model synchronization primitives. 14 | 15 | = Terms and Abbreviations 16 | 17 | This specification uses the following terms and abbreviations: 18 | 19 | [width=80%] 20 | |=== 21 | | Term | Meaning 22 | 23 | | ABI | Application Binary Interface 24 | | gABI | Generic System V Application Binary Interface 25 | | ELF | Executable and Linking Format 26 | | psABI | Processor-Specific ABI 27 | | DWARF | Debugging With Arbitrary Record Formats 28 | | GOT | Global Offset Table 29 | | PLT | Procedure Linkage Table 30 | | PC | Program Counter 31 | | TLS | Thread-Local Storage 32 | | NTBS | Null-Terminated Byte String 33 | | XLEN | The width of an integer register in bits 34 | | FLEN | The width of a floating-point register in bits 35 | | Linker relaxation | A mechanism for optimizing programs at link-time, see <> for more detail. 36 | | RVWMO | RISC-V Weak Memory Order, as defined in the RISC-V specification. 37 | |=== 38 | 39 | = Status of ABI 40 | 41 | [width=80%] 42 | |=== 43 | | ABI Name | Status 44 | 45 | | ILP32 | Ratified 46 | | ILP32F | Ratified 47 | | ILP32D | Ratified 48 | | ILP32E | Draft 49 | | LP64 | Ratified 50 | | LP64F | Ratified 51 | | LP64D | Ratified 52 | | LP64Q | Ratified 53 | | RV64ILP32 | Draft 54 | | RV64ILP32F | Draft 55 | | RV64ILP32D | Draft 56 | | RV64ILP32Q | Draft 57 | |=== 58 | 59 | NOTE: ABI for big-endian is *NOT* included in this specification, we intend to 60 | define that in future version of this specification. 61 | -------------------------------------------------------------------------------- /policy.md: -------------------------------------------------------------------------------- 1 | # Policy for Merging Pull Requests 2 | 3 | Each type of modification has a different policy, based on the following rules: 4 | 5 | - Changes requiring linker changes 6 | - Require an open source PoC implementation for binutils or LLD, either as a 7 | patch on the mailing list/Phabricator as appropriate or in a GitHub fork 8 | - Require at least one binutils developer **_AND_** one LLD developer to 9 | approve 10 | 11 | - Changes requiring compiler changes 12 | - Require an open source PoC implementation for GCC or LLVM, either as a 13 | patch on the mailing list/Phabricator as appropriate or in a GitHub fork 14 | - Require at least one GCC developer **_AND_** one LLVM developer to approve 15 | 16 | - Clarifications for currently-implemented behaviour 17 | - Require approval from a developer of the corresponding component 18 | (binutils/LLD or GCC/LLVM) 19 | 20 | - General improvements and clarification 21 | - One of the psABI TG chair or co-chair. 22 | 23 | - Do **_NOT_** make incompatible changes 24 | - Changes that break compatibility are generally not acceptable 25 | - In the rare case there is a bug in the ABI that needs fixing and that 26 | cannot be done in a backwards-compatible way, or possibly for some 27 | edge-case behaviour that is not currently relied upon, breaking the ABI can 28 | be considered, but will require both the psABI TG chair and co-chair to 29 | approve, and is subject to the above requirements as appropriate 30 | 31 | # FAQ 32 | 33 | - Can I leave a comment, LGTM or approve the PR even if I am not a toolchain 34 | developer or chair/co-chair? 35 | - Don't hesitate to leave your comment, we encourage anyone who intends 36 | to contribute to the RISC-V community to participate in discussion. 37 | 38 | - When do I need to modify the compiler and/or linker? 39 | - Changes and additions to the ELF format itself generally require linker 40 | changes, e.g. new relocation types, new flags in the `e_flags` field, new 41 | sections and new symbol flags. 42 | - Changes and additions to calling conventions and code models generally 43 | require compiler changes. 44 | 45 | - Who are the psABI TG chair and co-chair? 46 | - The current chair is Kito Cheng ([@kito-cheng]) and the current co-chair is 47 | Jessica Clarke ([@jrtc27]). 48 | 49 | - Where can I find a RISC-V GCC/LLVM/binutils/LLD developer to review my PR? 50 | - The psABI TG chair or co-chair will generally contact the right people as 51 | needed for reviews, but in case you want to reach out yourself you can find 52 | an incomplete list from [RISC-V International's wiki page]. 53 | 54 | [@kito-cheng]: https://github.com/kito-cheng 55 | [@jrtc27]: https://github.com/jrtc27 56 | [RISC-V International's wiki page]: https://wiki.riscv.org/display/TECH/Toolchain+Projects 57 | -------------------------------------------------------------------------------- /preamble.adoc: -------------------------------------------------------------------------------- 1 | 2 | ifeval::["{revlifecycle}" == "dev"] 3 | [WARNING] 4 | .This document is in the link:http://riscv.org/spec-state[Development state] 5 | ==== 6 | Assume everything can change. 7 | ==== 8 | endif::[] 9 | ifeval::["{revlifecycle}" == "stable"] 10 | [WARNING] 11 | .This document is in the link:http://riscv.org/spec-state[Stable state] 12 | ==== 13 | Assume anything could still change, but limited change should be expected. 14 | ==== 15 | endif::[] 16 | ifeval::["{revlifecycle}" == "frozen"] 17 | [WARNING] 18 | .This document is in the link:http://riscv.org/spec-state[Frozen state] 19 | ==== 20 | Change is extremely unlikely. A high threshold will be used, and a change will 21 | only occur because of some truly critical issue being identified during the 22 | public review cycle. 23 | ==== 24 | endif::[] 25 | ifeval::["{revlifecycle}" == "ratified"] 26 | [WARNING] 27 | .This document is in the link:http://riscv.org/spec-state[Ratified state] 28 | ==== 29 | No changes are allowed. Any desired or needed changes can be the subject of 30 | a follow-on new extension. Ratified extensions are never revised. 31 | ==== 32 | endif::[] 33 | 34 | Contributors to all versions of the spec in alphabetical order: 35 | 36 | Alex Bradbury, 37 | Andrew Burgess, 38 | Chih-Mao Chen, 39 | Zakk Chen, 40 | Kito Cheng, 41 | Nelson Chu, 42 | Michael Clark, 43 | Jessica Clarke, 44 | Palmer Dabbelt, 45 | Sam Elliott, 46 | Gonzalo Brito Gadeschi, 47 | Sebastian Huber, 48 | Roger Ferrer Ibanez, 49 | Quey-Liang Kao, 50 | Nick Knight, 51 | Luís Marques, 52 | Evandro Menezes, 53 | Max Nordlund, 54 | Stefan O'Rear, 55 | Konrad Schwarz, 56 | Fangrui Song, 57 | Hsiangkai Wang, 58 | Andrew Waterman, 59 | Jim Wilson 60 | 61 | It is licensed under the Creative Commons Attribution 4.0 International 62 | License (CC-BY 4.0). The full license text is available at 63 | https://creativecommons.org/licenses/by/4.0/. 64 | 65 | Please cite as: `RISC-V ABIs Specification, 66 | Document Version {refrev}', Editors 67 | Kito Cheng and Jessica Clarke, RISC-V International, {monthyear}. 68 | 69 | The latest version of this document can be found here: 70 | https://github.com/riscv-non-isa/riscv-elf-psabi-doc. 71 | 72 | This specification is written in collaboration with the development communities 73 | of the major open-source toolchain and operating system communities, and as 74 | such specifies what has been agreed upon and implemented. As a result, any 75 | changes to this specification that are not backwards-compatible would break ABI 76 | compatibility for those toolchains, which is not permitted unless for features 77 | explicitly marked as experimental, and so will not be made unless absolutely 78 | necessary, regardless of whether the specification is a pre-release version, 79 | ratified version or anything in between. This means any version of this 80 | specification published at the above link can be regarded as stable in the 81 | technical sense of the word (but not necessarily in the official RISC-V 82 | International specification state meaning), with the official specification 83 | state being an indicator of the completeness, clarity and general editorial 84 | quality of the specification. 85 | -------------------------------------------------------------------------------- /prelude.adoc: -------------------------------------------------------------------------------- 1 | :company: RISC-V.org 2 | :revlifecycle: dev 3 | :revnumber: 1.1 4 | ifeval::["{revlifecycle}" == "dev"] 5 | :revdate: {date} 6 | :revremark: Pre-release 7 | :refrev: {date}-draft 8 | endif::[] 9 | ifeval::["{revlifecycle}" == "stable"] 10 | :revremark: Stable 11 | :refrev: {revnumber} 12 | endif::[] 13 | ifeval::["{revlifecycle}" == "frozen"] 14 | :revremark: Frozen 15 | :refrev: {revnumber} 16 | endif::[] 17 | ifeval::["{revlifecycle}" == "ratified"] 18 | :revremark: Ratified 19 | :refrev: {revnumber} 20 | endif::[] 21 | :url-riscv: http://riscv.org 22 | :doctype: book 23 | :preface-title: Preamble 24 | :colophon: 25 | :appendix-caption: Appendix 26 | :imagesdir: images 27 | :title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center] 28 | //:back-cover-image: image:backpage.png[opacity=25%] 29 | :experimental: 30 | :reproducible: 31 | :icons: font 32 | :lang: en 33 | :listing-caption: Listing 34 | :sectnums: 35 | :toc: left 36 | :toclevels: 3 37 | :source-highlighter: pygments 38 | ifdef::backend-pdf[] 39 | :source-highlighter: coderay 40 | endif::[] 41 | :data-uri: 42 | :hide-uri-scheme: 43 | :stem: latexmath 44 | :footnote: 45 | :xrefstyle: short 46 | 47 | include::preamble.adoc[] 48 | -------------------------------------------------------------------------------- /resources/fonts/DroidSans-Bold.ttf: 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italic: mplus-1mn-regular.ttf 20 | bold_italic: mplus-1mn-bold.ttf 21 | # M+ 1p supports Latin, Latin-1 Supplement, Latin Extended, Greek, Cyrillic, Vietnamese, Japanese & an assortment of symbols 22 | # It also provides arrows for ->, <-, => and <= replacements in case these glyphs are missing from font 23 | M+ 1p Fallback: 24 | normal: mplus-1p-regular-fallback.ttf 25 | bold: mplus-1p-regular-fallback.ttf 26 | italic: mplus-1p-regular-fallback.ttf 27 | bold_italic: mplus-1p-regular-fallback.ttf 28 | # Droid Fallback: 29 | # normal: droid-regular-fallback.ttf 30 | # bold: droid-regular-fallback.ttf 31 | # italic: droid-regular-fallback.ttf 32 | # bold_italic: droid-regular-fallback.ttf 33 | fallbacks: 34 | - M+ 1p Fallback 35 | # - Droid Fallback 36 | page: 37 | background_color: ffffff 38 | layout: portrait 39 | margin: [0.5in, 0.67in, 0.67in, 0.67in] 40 | # margin_inner and margin_outer keys are used for recto/verso print margins when media=prepress 41 | margin_inner: 0.75in 42 | margin_outer: 0.59in 43 | size: A4 44 | base: 45 | align: justify 46 | # color as hex string (leading # is optional) 47 | font_color: 383838 48 | # color as RGB array 49 | #font_color: [51, 51, 51] 50 | # color as CMYK array (approximated) 51 | #font_color: [0, 0, 0, 0.92] 52 | #font_color: [0, 0, 0, 92%] 53 | font_family: Computer Modern 54 | # choose one of these font_size/line_height_length combinations 55 | #font_size: 14 56 | #line_height_length: 20 57 | #font_size: 11.25 58 | #line_height_length: 18 59 | #font_size: 11.2 60 | #line_height_length: 16 61 | font_size: 10.5 62 | #line_height_length: 15 63 | # correct line height for Computer Modern metrics 64 | line_height_length: 12 65 | #font_size: 11.25 66 | #line_height_length: 18 67 | line_height: $base_line_height_length / $base_font_size 68 | font_size_large: round($base_font_size * 1.25) 69 | font_size_small: round($base_font_size * 0.85) 70 | font_size_min: $base_font_size * 0.75 71 | font_style: normal 72 | border_color: eeeeee 73 | border_radius: 3 74 | border_width: 0.2 75 | # FIXME vertical_rhythm is weird; we should think in terms of ems 76 | #vertical_rhythm: $base_line_height_length * 2 / 3 77 | # correct line height for Computer Modern metrics (comes with built-in line height) 78 | vertical_rhythm: $base_line_height_length 79 | horizontal_rhythm: $base_line_height_length 80 | # QUESTION should vertical_spacing be block_spacing instead? 81 | vertical_spacing: $vertical_rhythm 82 | link: 83 | font_color: 428bca 84 | # literal is currently used for inline monospaced in prose and table cells 85 | literal: 86 | font_color: b12146 87 | font_family: Code 88 | menu_caret_content: " \u203a " 89 | heading: 90 | align: left 91 | font_color: 3e058e 92 | #font_color: $base_font_color 93 | font_family: $base_font_family 94 | font_style: normal 95 | # h1 is used for part titles (book doctype only) 96 | h1_font_size: floor($base_font_size * 2.6) 97 | # h2 is used for chapter titles (book doctype only) 98 | h2_font_size: floor($base_font_size * 2.15) 99 | h3_font_size: round($base_font_size * 1.7) 100 | h4_font_size: $base_font_size_large 101 | h5_font_size: $base_font_size 102 | h6_font_size: $base_font_size_small 103 | #line_height: 1.4 104 | # correct line height for Computer Modern metrics (comes with built-in line height) 105 | line_height: 1 106 | margin_top: $vertical_rhythm * 0.4 107 | margin_bottom: $vertical_rhythm * 0.9 108 | title_page: 109 | align: right 110 | logo: 111 | top: 10% 112 | title: 113 | top: 55% 114 | font_size: $heading_h1_font_size 115 | font_color: 3e058e 116 | line_height: 0.9 117 | subtitle: 118 | font_size: $heading_h3_font_size 119 | font_style: bold_italic 120 | line_height: 1 121 | authors: 122 | margin_top: $base_font_size * 1.25 123 | font_size: $base_font_size_large 124 | font_color: 3e058e 125 | revision: 126 | margin_top: $base_font_size * 1.25 127 | block: 128 | margin_top: 0 129 | margin_bottom: $vertical_rhythm 130 | caption: 131 | align: left 132 | font_size: $base_font_size * 0.95 133 | font_style: italic 134 | # FIXME perhaps set line_height instead of / in addition to margins? 135 | margin_inside: $vertical_rhythm / 3 136 | #margin_inside: $vertical_rhythm / 4 137 | margin_outside: 0 138 | lead: 139 | font_size: $base_font_size_large 140 | line_height: 1.4 141 | abstract: 142 | font_color: 5c6266 143 | font_size: $lead_font_size 144 | line_height: $lead_line_height 145 | font_style: italic 146 | first_line_font_style: bold 147 | title: 148 | align: center 149 | font_color: $heading_font_color 150 | font_family: $heading_font_family 151 | font_size: $heading_h4_font_size 152 | font_style: $heading_font_style 153 | sidebar: 154 | font-style: italic 155 | background-color: f5f5fc 156 | border-color: 8d81b8 157 | border-radius: 3 158 | border-width: 0.2 159 | sidebar-title: 160 | font-style: italic 161 | font-color: $heading-font-color 162 | font-size: 11 163 | align: left 164 | admonition: 165 | column_rule_color: $base_border_color 166 | column_rule_width: $base_border_width 167 | padding: [0, $horizontal_rhythm, 0, $horizontal_rhythm] 168 | icon: 169 | note: 170 | name: pencil-square-o 171 | stroke_color: 6489b3 172 | tip: 173 | name: comments-o 174 | stroke_color: 646b74 175 | size: 24 176 | important: 177 | name: hand-pointer-o 178 | stroke_color: b58f5b 179 | warning: 180 | stroke_color: 9c4d4b 181 | caution: 182 | stroke_color: c99a2c 183 | label: 184 | text_transform: uppercase 185 | font_style: bold 186 | #blockquote: 187 | # font_color: $base_font_color 188 | # font_size: $base_font_size_large 189 | # border_color: $base_border_color 190 | # border_width: 2 191 | # FIXME disable negative padding bottom once margin collapsing is implemented 192 | # padding: [0, $horizontal_rhythm, $block_margin_bottom * -0.75, $horizontal_rhythm + $blockquote_border_width / 2] 193 | # cite_font_size: $base_font_size_small 194 | # cite_font_color: 51278d 195 | # code is used for source blocks (perhaps change to source or listing?) 196 | code: 197 | font_color: $base_font_color 198 | font_family: $literal_font_family 199 | font_size: ceil($base_font_size) 200 | padding: $code_font_size 201 | line_height: 1.25 202 | # line_gap is an experimental property to control how a background color is applied to an inline block element 203 | line_gap: 3.8 204 | background_color: f4f4fb 205 | border_color: cccccc 206 | border_radius: $base_border_radius 207 | border_width: 0.2 208 | conum: 209 | font_family: M+ 1mn 210 | font_color: $literal_font_color 211 | font_size: $base_font_size 212 | line_height: 4 / 3 213 | example: 214 | border_color: $base_border_color 215 | border_radius: $base_border_radius 216 | border_width: 0.2 217 | background_color: ffffff 218 | # FIXME reenable padding bottom once margin collapsing is implemented 219 | padding: [$vertical_rhythm, $horizontal_rhythm, 0, $horizontal_rhythm] 220 | image: 221 | align: left 222 | prose: 223 | margin_top: $block_margin_top 224 | margin_bottom: $block_margin_bottom 225 | thematic_break: 226 | border_color: $base_border_color 227 | border_style: solid 228 | border_width: $base_border_width 229 | margin_top: $vertical_rhythm * 0.5 230 | margin_bottom: $vertical_rhythm * 1.5 231 | description_list: 232 | term_font_style: bold 233 | term_spacing: $vertical_rhythm / 4 234 | description_indent: $horizontal_rhythm * 1.25 235 | outline_list: 236 | indent: $horizontal_rhythm * 1.5 237 | #marker_font_color: 404040 238 | # NOTE outline_list_item_spacing applies to list items that do not have complex content 239 | item_spacing: $vertical_rhythm / 2 240 | table: 241 | background_color: $page_background_color 242 | #head_background_color: 243 | #head_font_color: $base_font_color 244 | head_font_style: bold 245 | #body_background_color: 246 | body_stripe_background_color: d7d7d7 247 | foot_background_color: f0f0f0 248 | border_color: dddddd 249 | border_width: $base_border_width 250 | cell_padding: 3 251 | caption_side: bottom 252 | toc: 253 | indent: $horizontal_rhythm 254 | line_height: 1.4 255 | dot_leader: 256 | #content: ". " 257 | font_color: a9a9a9 258 | #levels: 2 3 259 | # NOTE in addition to footer, header is also supported 260 | header: 261 | font_size: $base_font_size_small 262 | # NOTE if background_color is set, background and border will span width of page 263 | border_color: dddddd 264 | border_width: 0.35 265 | height: $base_line_height_length * 2.6 266 | line_height: 1 267 | padding: [$base_line_height_length / 1.3, 1, 0, 1] 268 | vertical_align: margin_inside 269 | #image_vertical_align: or 270 | # additional attributes for content: 271 | # * {page-count} 272 | # * {page-number} 273 | # * {document-title} 274 | # * {document-subtitle} 275 | # * {chapter-title} 276 | # * {section-title} 277 | # * {section-or-chapter-title} 278 | recto: 279 | right: 280 | content: '{section-or-chapter-title} | Page {page-number}' 281 | verso: 282 | left: 283 | content: '{section-or-chapter-title} | Page {page-number}' 284 | # left: 'Page {page-number} | {section-or-chapter-title}' 285 | footer: 286 | font_size: $base_font_size_small 287 | # NOTE if background_color is set, background and border will span width of page 288 | border_color: dddddd 289 | border_width: 0.25 290 | height: $base_line_height_length * 2.5 291 | line_height: 1 292 | padding: [$base_line_height_length / 2, 1, 0, 1] 293 | vertical_align: top 294 | #image_vertical_align: or 295 | # additional attributes for content: 296 | # content: '{company}' 297 | # * {page-count} 298 | # * {page-number} 299 | #center: 300 | #content: '{document-title}' 301 | # * {document-subtitle} 302 | # * {chapter-title} 303 | # * {section-title} 304 | # * {section-or-chapter-title} 305 | recto: 306 | #columns: "<50% =0% >50%" 307 | right: 308 | #content: '{page-number}' 309 | content: '{document-title} | © RISC-V' 310 | #content: '{document-title} | © RISC-V' 311 | #center: '{page-number}' 312 | #content: '{revdate}' 313 | verso: 314 | #columns: $footer_recto_columns 315 | left: 316 | content: $footer_recto_right_content 317 | #center: '{page-number}' 318 | #content: '{page-number}' 319 | role: 320 | Changed: 321 | border: 322 | width: .25 323 | changebar: 1 324 | color: $base_font_color 325 | offset: 2 326 | 327 | 328 | -------------------------------------------------------------------------------- /riscv-abi.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-abi]] 2 | = RISC-V ABIs Specification 3 | ifeval::["{docname}" == "riscv-abi"] 4 | include::prelude.adoc[] 5 | endif::[] 6 | 7 | include::introduction.adoc[] 8 | 9 | include::riscv-cc.adoc[] 10 | 11 | include::riscv-elf.adoc[] 12 | 13 | include::riscv-dwarf.adoc[] 14 | 15 | include::riscv-rtabi.adoc[] 16 | 17 | include::riscv-atomic.adoc[] 18 | -------------------------------------------------------------------------------- /riscv-atomic.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-atomics]] 2 | = RISC-V Atomics ABI Specification 3 | ifeval::["{docname}" == "riscv-atomics"] 4 | include::prelude.adoc[] 5 | endif::[] 6 | 7 | == RISC-V atomics mappings 8 | 9 | This specifies mappings of C and {Cpp} atomic operations to RISC-V 10 | machine instructions. Other languages, for example Java, provide similar 11 | facilities that should be implemented in a consistent manner, usually 12 | by applying the mapping for the corresponding {Cpp} primitive. 13 | 14 | NOTE: Because different programming languages may be used within the same 15 | process, these mappings must be compatible across programming languages. For 16 | example, Java programmers expect memory ordering guarantees to be enforced even 17 | if some of the actual memory accesses are performed by a library written in 18 | C. 19 | 20 | NOTE: Though many mappings are possible, not all of them will interoperate 21 | correctly. In particular, many mapping combinations will not 22 | correctly enforce ordering  between a {Cpp} `memory_order_seq_cst` 23 | store and a subsequent `memory_order_seq_cst` load. 24 | 25 | NOTE: These mappings are very similar to those that originally appeared in the 26 | appendix of the RISC-V "unprivileged" architecture specification as 27 | "Mappings from C/{Cpp} primitives to RISC-V Primitives", which we will 28 | refer to by their 2019 historical label of "Table A.6". That mapping may 29 | be used, _except_ that `atomic_store(memory_order_seq_cst)` must have an 30 | an extra trailing fence for compatibility with the "Hypothetical mappings ..." 31 | table in the same section, which we similarly refer to as "Table A.7". 32 | As a result, we allow the "Table A.7" mappings as well. 33 | 34 | NOTE: Our primary design goal is to maximize performance of the "Table A.7" 35 | mappings. These require additional load-acquire and store-release instructions, 36 | and are this not immediately usable. By requiring the extra store fence. 37 | or equivalent, we avoid an ABI break when moving to the "Table A.7" 38 | mappings in the future, in return for a small performance penalty in the 39 | short term. 40 | 41 | For each construct, we provide a mapping that assumes only the A extension. 42 | In some cases, we provide additional mappings that assume a future load-acquire 43 | and store-release extension, as denoted by note 1 in the table. 44 | 45 | All mappings interoperate correctly, and with the original "Table A.6" 46 | mappings, _except_ that mappings marked with note 3 do not interoperate 47 | with the original "Table A.6" mappings. 48 | 49 | We present the mappings as a table in 3 sections. The first 50 | deals with translations for loads, stores, and fences. The next two sections 51 | address mappings for read-modify-write operations like `fetch_add`, and 52 | `exchange`. The second section deals with operations that have direct 53 | `amo` instruction equivalents in the RISC-V A extension. The final 54 | section deals with other read-modify-write operations that require 55 | the `lr` and `sc` instructions. 56 | 57 | [[tab:c11mappings]] 58 | .Mappings from C/{Cpp} primitives to RISC-V primitives 59 | [cols="<22,<18,<4",options="header",] 60 | |=== 61 | |C/{Cpp} Construct |RVWMO Mapping |Notes 62 | 63 | |Non-atomic load |`l{b\|h\|w\|d}` | 64 | 65 | |`atomic_load(memory_order_relaxed)` |`l{b\|h\|w\|d}` | 66 | 67 | |`atomic_load(memory_order_acquire)` |`l{b\|h\|w\|d}; fence r,rw` | 68 | 69 | |`atomic_load(memory_order_acquire)` | |1, 2 70 | 71 | |`atomic_load(memory_order_seq_cst)` |`fence rw,rw; l{b\|h\|w\|d}; fence r,rw` | 72 | 73 | |`atomic_load(memory_order_seq_cst)` | |1, 3 74 | 75 | |Non-atomic store |`s{b\|h\|w\|d}` | 76 | 77 | |`atomic_store(memory_order_relaxed)` |`s{b\|h\|w\|d}` | 78 | 79 | |`atomic_store(memory_order_release)` |`fence rw,w; s{b\|h\|w\|d}` | 80 | 81 | |`atomic_store(memory_order_release)` | |1, 2 82 | 83 | |`atomic_store(memory_order_seq_cst)` |`fence rw,w; s{b\|h\|w\|d}; fence rw,rw;` | 84 | 85 | |`atomic_store(memory_order_seq_cst)` |`amoswap.rl{w\|d};` |4 86 | 87 | |`atomic_store(memory_order_seq_cst)` | |1 88 | 89 | |`atomic_thread_fence(memory_order_acquire)` |`fence r,rw` | 90 | 91 | |`atomic_thread_fence(memory_order_release)` |`fence rw,w` | 92 | 93 | |`atomic_thread_fence(memory_order_acq_rel)` |`fence.tso` | 94 | 95 | |`atomic_thread_fence(memory_order_seq_cst)` |`fence rw,rw` | 96 | |=== 97 | 98 | [cols="<20,<20,<4",options="header",] 99 | |=== 100 | |C/{Cpp} Construct |RVWMO AMO Mapping |Notes 101 | 102 | |`atomic_(memory_order_relaxed)` |`amo.{w\|d}` |4 103 | 104 | |`atomic_(memory_order_acquire)` |`amo.{w\|d}.aq` |4 105 | 106 | |`atomic_(memory_order_release)` |`amo.{w\|d}.rl` |4 107 | 108 | |`atomic_(memory_order_acq_rel)` |`amo.{w\|d}.aqrl` |4 109 | 110 | |`atomic_(memory_order_seq_cst)` |`amo.{w\|d}.aqrl` |4, 5 111 | 112 | |=== 113 | 114 | [cols="<16,<24,<4",options="header",] 115 | |=== 116 | |C/{Cpp} Construct |RVWMO LR/SC Mapping |Notes 117 | 118 | |`atomic_(memory_order_relaxed)` |`loop:lr.{w\|d}; ; sc.{w\|d}; bnez loop` |4 119 | 120 | |`atomic_(memory_order_acquire)` 121 | |`loop:lr.{w\|d}.aq; ; sc.{w\|d}; bnez loop` |4 122 | 123 | |`atomic_(memory_order_release)` 124 | |`loop:lr.{w\|d}; ; sc.{w\|d}.rl; bnez loop` |4 125 | 126 | |`atomic_(memory_order_acq_rel)` 127 | |`loop:lr.{w\|d}.aq; ; sc.{w\|d}.rl; bnez loop` |4 128 | 129 | |`atomic_(memory_order_seq_cst)` 130 | |`loop:lr.{w\|d}.aqrl; ; sc.{w\|d}.rl; bnez loop` |4 131 | 132 | |`atomic_(memory_order_seq_cst)` 133 | |`loop:lr.{w\|d}.aq; ; sc.{w\|d}.rl; bnez loop` |3, 4 134 | |=== 135 | 136 | === Meaning of notes in table 137 | 138 | 1) Depends on a load instruction with an RCsc acquire annotation, 139 | or a store instruction with an RCsc release annotation. These are currently 140 | under discussion, but the specification has not yet been approved. 141 | 142 | 2) An RCpc load or store would also suffice, if it were to be introduced 143 | in the future. 144 | 145 | 3) Incompatible with the original "Table A.6" mapping. Do not combine these 146 | mappings with code generated by a compiler using those older mappings. 147 | (This was mostly used by the initial LLVM implementations for RISC-V.) 148 | 149 | 4) Currently only directly possible for 32- and 64-bit operands. 150 | 151 | 5) atomic_compare_exchange operations with a memory_order_seq_cst failure 152 | ordering are considered to have a note 3 annotation. 153 | To remove the note 3 annotation the amocas operation must be prepended with a 154 | leading fence (`fence rw,rw; amocas.{w\|d}.aqrl`). 155 | 156 | == Ztso atomics mappings 157 | 158 | This specifies additional mappings of C and {Cpp} atomic operations to RISC-V 159 | machine instructions. 160 | 161 | For each construct, we provide a mapping that assumes only the A and Ztso 162 | extension. 163 | 164 | All mappings interoperate correctly with the RVWMO mappings, and with the 165 | original "Table A.6" mappings, _except_ that mappings marked with note 3 do not 166 | interoperate with the original "Table A.6" mappings. 167 | 168 | We present the mappings as a table in 3 sections, as above. 169 | 170 | [[tab:c11mappingsztso]] 171 | .Mappings with Ztso extension from C/{Cpp} primitives to RISC-V primitives 172 | [cols="<22,<18,<4",options="header",] 173 | |=== 174 | |C/{Cpp} Construct |Ztso Mapping |Notes 175 | 176 | |`atomic_load(memory_order_acquire)` |`l{b\|h\|w\|d}` | 6 177 | 178 | |`atomic_load(memory_order_seq_cst)` |`fence rw,rw; l{b\|h\|w\|d}` | 6 179 | 180 | |`atomic_store(memory_order_release)` |`s{b\|h\|w\|d}` | 6 181 | 182 | |`atomic_store(memory_order_seq_cst)` |`s{b\|h\|w\|d}; fence rw, rw` | 6 183 | 184 | |`atomic_thread_fence(memory_order_acquire)` |`nop` | 6 185 | 186 | |`atomic_thread_fence(memory_order_release)` |`nop` | 6 187 | 188 | |`atomic_thread_fence(memory_order_acq_rel)` |`nop` | 6 189 | |=== 190 | 191 | [cols="<20,<20,<4",options="header",] 192 | |=== 193 | |C/{Cpp} Construct |Ztso AMO Mapping |Notes 194 | 195 | |`atomic_(memory_order_acquire)` |`amo.{w\|d}` |4, 6 196 | 197 | |`atomic_(memory_order_release)` |`amo.{w\|d}` |4, 6 198 | 199 | |`atomic_(memory_order_acq_rel)` |`amo.{w\|d}` |4, 6 200 | 201 | |`atomic_(memory_order_seq_cst)` |`amo.{w\|d}` |4, 5, 6 202 | 203 | |=== 204 | 205 | [cols="<16,<24,<4",options="header",] 206 | |=== 207 | |C/{Cpp} Construct |Ztso LR/SC Mapping |Notes 208 | 209 | |`atomic_(memory_order_acquire)` 210 | |`loop:lr.{w\|d}; ; sc.{w\|d}; bnez loop` |4, 6 211 | 212 | |`atomic_(memory_order_release)` 213 | |`loop:lr.{w\|d}; ; sc.{w\|d}; bnez loop` |4, 6 214 | 215 | |`atomic_(memory_order_acq_rel)` 216 | |`loop:lr.{w\|d}; ; sc.{w\|d}; bnez loop` |4, 6 217 | 218 | |=== 219 | 220 | === Meaning of notes in table 221 | 222 | 3) Incompatible with the original "Table A.6" mapping. Do not combine these 223 | mappings with code generated by a compiler using those older mappings. 224 | (This was mostly used by the initial LLVM implementations for RISC-V.) 225 | 226 | 4) Currently only directly possible for 32- and 64-bit operands. 227 | 228 | 5) atomic_compare_exchange operations with a memory_order_seq_cst failure 229 | ordering are considered to have a note 3 annotation. 230 | To remove the note 3 annotation the amocas operation must be prepended with a 231 | leading fence (`fence rw,rw; amocas.{w\|d}`). 232 | 233 | 6) Requires the Ztso extension. 234 | 235 | == Other conventions 236 | 237 | It is expected that the RVWMO and Ztso AMO Mappings will be used for atomic 238 | read-modify-write operations that are directly supported by corresponding AMO 239 | instructions, and that LR/SC mappings will be used for the remainder, currently 240 | including compare-exchange operations. Compare-exchange LR/SC sequences 241 | on the containing 32-bit word should be used for shorter operands. Thus, 242 | a `fetch_add` operation on a 16-bit quantity would use a 32-bit LR/SC sequence. 243 | 244 | It is acceptable, but usually undesirable for performance reasons, to use LR/SC 245 | mappings where an AMO mapping would suffice. 246 | 247 | Atomics do not imply any ordering for IO operations. IO operations 248 | should include sufficient fences to prevent them from being visibly 249 | reordered with atomic operations. 250 | 251 | Float and double atomic loads and stores should be implemented using 252 | the integer sequences. 253 | 254 | Float and double read-modify-write instructions should consist of a loop performing 255 | an initial plain load of the value, followed by the floating point 256 | computation, followed by an integer compare-and-swap sequence to try to 257 | store back the updated value. This avoids floating point 258 | instructions between LR and SC instructions. Depending on language requirements, 259 | it may be necessary to save and restore floating-point exception flags in the 260 | case of an operation that is later redone due to a failed SC operation. 261 | 262 | NOTE: The "Eventual Success of Store-Conditional Instructions" section 263 | in the ISA specification provides that essential progress guarantee only 264 | if there are no floating point instructions between the LR and matching SC 265 | instruction. By compiling such sequences with an "extra" ordinary load, 266 | and performing the floating point computation before the LR, we preserve 267 | the guarantee. 268 | -------------------------------------------------------------------------------- /riscv-cc.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-cc]] 2 | = RISC-V Calling Conventions 3 | ifeval::["{docname}" == "riscv-cc"] 4 | include::prelude.adoc[] 5 | endif::[] 6 | 7 | == Register Convention 8 | 9 | === Integer Register Convention 10 | 11 | .Integer register convention 12 | [cols="1,1,2,2"] 13 | |=== 14 | | Name | ABI Mnemonic | Meaning | Preserved across calls? 15 | 16 | | x0 | zero | Zero | -- (Immutable) 17 | | x1 | ra | Return address | No 18 | | x2 | sp | Stack pointer | Yes 19 | | x3 | gp | Global pointer | -- (Unallocatable) 20 | | x4 | tp | Thread pointer | -- (Unallocatable) 21 | | x5 - x7 | t0 - t2 | Temporary registers | No 22 | | x8 - x9 | s0 - s1 | Callee-saved registers | Yes 23 | | x10 - x17 | a0 - a7 | Argument registers | No 24 | | x18 - x27 | s2 - s11 | Callee-saved registers | Yes 25 | | x28 - x31 | t3 - t6 | Temporary registers | No 26 | |=== 27 | 28 | In the standard ABI, procedures should not modify the integer registers tp and 29 | gp, because signal handlers may rely upon their values. 30 | 31 | The presence of a frame pointer is optional. If a frame pointer exists, 32 | it must reside in x8 (s0); the register remains callee-saved. 33 | 34 | If a platform requires use of a dedicated general-purpose register for a 35 | platform-specific purpose, it is recommended to use gp (x3). The platform ABI 36 | specification must document the use of this register. For such platforms, care 37 | must be taken to ensure all code (compiler generated or otherwise) avoids using 38 | gp in a way incompatible with the platform specific purpose, and that global 39 | pointer relaxation is disabled in the toolchain. 40 | 41 | === Frame Pointer Convention 42 | 43 | The presence of a frame pointer is optional. If a frame pointer exists, 44 | it must reside in x8 (s0); the register remains callee-saved. 45 | 46 | Code that uses a frame pointer will construct a linked list of stack frames, 47 | where each frame links to its caller using a "frame record". A frame record 48 | consists of two XLEN values on the stack; the return address and the link to 49 | the next frame record. The frame pointer register will point to the innermost 50 | frame, thereby starting the linked list. By convention, the lowest XLEN value 51 | shall point to the previous frame, while the next XLEN value shall be the 52 | return address. The end of the frame record chain is indicated by the address 53 | zero appearing as the next link in the chain. 54 | 55 | After the prologue, the frame pointer register will point to the Canonical 56 | Frame Address or CFA, which is the stack pointer value on entry to the current 57 | procedure. The previous frame pointer and return address pair will reside just 58 | prior to the current stack address held in `fp`. This puts the return address 59 | at `fp - XLEN/8`, and the previous frame pointer at `fp - 2 * XLEN/8`. 60 | 61 | It is left to the platform to determine the level of conformance with this 62 | convention. A platform may choose: 63 | 64 | - not to maintain a frame chain and use the frame pointer register as a general 65 | purpose callee-saved register. 66 | 67 | - to allow the frame pointer register be used as a general purpose callee-saved 68 | register, but provide a platform specific mechanism to reliably detect this 69 | condition. 70 | 71 | - to use a frame pointer to address a valid frame record at all times, but 72 | allow any procedure to choose to forgo creating a frame record. 73 | 74 | - to use the frame pointer to address a valid frame record at all times, except 75 | leaf functions, who may elect to forgo creating a frame record. 76 | 77 | === Floating-point Register Convention 78 | 79 | .Floating-point register convention 80 | [cols="1,1,2,2"] 81 | |=== 82 | | Name | ABI Mnemonic | Meaning | Preserved across calls? 83 | 84 | | f0 - f7 | ft0 - ft7 | Temporary registers | No 85 | | f8 - f9 | fs0 - fs1 | Callee-saved registers | Yes* 86 | | f10 - f17 | fa0 - fa7 | Argument registers | No 87 | | f18 - f27 | fs2 - fs11 | Callee-saved registers | Yes* 88 | | f28 - f31 | ft8 - ft11 | Temporary registers | No 89 | |=== 90 | 91 | *: Floating-point values in callee-saved registers are only preserved across 92 | calls if they are no larger than the width of a floating-point register in the 93 | targeted ABI. Therefore, these registers can always be considered temporaries 94 | if targeting the base integer calling convention. 95 | 96 | The Floating-Point Control and Status Register (fcsr) must have thread storage 97 | duration in accordance with C11 section 7.6 "Floating-point environment 98 | ". 99 | 100 | === Vector Register Convention 101 | 102 | ==== Standard calling convention 103 | .Standard vector register calling convention 104 | [%autowidth] 105 | |=== 106 | | Name | ABI Mnemonic | Meaning | Preserved across calls? 107 | 108 | | v0-v31 | | Temporary registers | No 109 | | vl | | Vector length | No 110 | | vtype | | Vector data type register | No 111 | | vxrm | | Vector fixed-point rounding mode register | No 112 | | vxsat | | Vector fixed-point saturation flag register | No 113 | |=== 114 | 115 | NOTE: Vector registers are not used for passing arguments or return values in this 116 | calling convention. Use the calling convention variant to pass arguments and return 117 | values in vector registers. 118 | 119 | The `vxrm` and `vxsat` fields of `vcsr` are not preserved across calls and their 120 | values are unspecified upon entry. 121 | 122 | Procedures may assume that `vstart` is zero upon entry. Procedures may assume 123 | that `vstart` is zero upon return from a procedure call. 124 | 125 | NOTE: Application software should normally not write `vstart` explicitly. 126 | Any procedure that does explicitly write `vstart` to a nonzero value must zero 127 | `vstart` before either returning or calling another procedure. 128 | 129 | ==== Calling convention variant 130 | .Variant vector register calling convention* 131 | [%autowidth] 132 | |=== 133 | | Name | ABI Mnemonic | Meaning | Preserved across calls? 134 | 135 | | v0 | | Argument register | No 136 | | v1-v7 | | Callee-saved registers | Yes 137 | | v8-v23 | | Argument registers | No 138 | | v24-v31 | | Callee-saved registers | Yes 139 | | vl | | Vector length | No 140 | | vtype | | Vector data type register | No 141 | | vxrm | | Vector fixed-point rounding mode register | No 142 | | vxsat | | Vector fixed-point saturation flag register | No 143 | |=== 144 | 145 | *: Functions that use vector registers to pass arguments and return values must 146 | follow this calling convention. Some programming languages can require extra 147 | functions to follow this calling convention (e.g. C/C++ functions with 148 | attribute `riscv_vector_cc`). 149 | 150 | Please refer to the <> section for 151 | more details about standard vector calling convention variant. 152 | 153 | NOTE: The `vxrm` and `vxsat` fields of `vcsr` follow the same behavior as the 154 | standard calling convention. 155 | 156 | == Procedure Calling Convention 157 | 158 | This chapter defines standard calling conventions and standard calling 159 | convention variants, and describes how to pass arguments and return values. 160 | 161 | Functions must follow the register convention defined in calling convention: the 162 | contents of any register without specifying it as an argument register 163 | in the calling convention are unspecified upon entry, and the content of any 164 | register without specifying it as a return value register or callee-saved in 165 | the calling convention are unspecified upon exit, the contents of all 166 | callee-saved registers must be restored to what was set on entry, and the 167 | contents of any fixed registers like `gp` and `tp` never change. 168 | 169 | 170 | NOTE: Calling convention for big-endian is *NOT* included in this specification 171 | yet, we intend to define that in future version of this specification. 172 | 173 | [#integer-cc] 174 | === Integer Calling Convention 175 | 176 | The base integer calling convention provides eight argument registers, 177 | a0-a7, the first two of which are also used to return values. 178 | 179 | Scalars that are at most XLEN bits wide are passed in a single argument 180 | register, or on the stack by value if none is available. 181 | When passed in registers or on the stack, integer scalars narrower than XLEN 182 | bits are widened according to the sign of their type up to 32 bits, then 183 | sign-extended to XLEN bits. 184 | When passed in registers or on the stack, floating-point types narrower than 185 | XLEN bits are widened to XLEN bits, with the upper bits undefined. 186 | 187 | Scalars that are 2×XLEN bits wide are passed in a pair of argument registers, 188 | with the low-order XLEN bits in the lower-numbered register and the high-order 189 | XLEN bits in the higher-numbered register. If no argument registers are 190 | available, the scalar is passed on the stack by value. If exactly one 191 | register is available, the low-order XLEN bits are passed in the register and 192 | the high-order XLEN bits are passed on the stack. 193 | 194 | Scalars wider than 2×XLEN bits are passed by reference and are replaced in the 195 | argument list with the address. 196 | 197 | Aggregates whose total size is no more than XLEN bits are passed in 198 | a register, with the fields laid out as though they were passed in memory. If 199 | no register is available, the aggregate is passed on the stack. 200 | Aggregates whose total size is no more than 2×XLEN bits are passed in a pair 201 | of registers; if only one register is available, the first XLEN bits are passed 202 | in a register and the remaining bits are passed on the stack. If no registers are 203 | available, the aggregate is passed on the stack. Bits unused due to 204 | padding, and bits past the end of an aggregate whose size in bits is not 205 | divisible by XLEN, are undefined. 206 | 207 | Aggregates or scalars passed on the stack are aligned to the greater of the 208 | type alignment and XLEN bits, but never more than the stack alignment. 209 | 210 | Aggregates larger than 2×XLEN bits are passed by reference and are replaced in 211 | the argument list with the address, as are {Cpp} aggregates with nontrivial copy 212 | constructors, destructors, or vtables. 213 | 214 | Fixed-length vectors are treated as aggregates. 215 | 216 | Empty structs or union arguments or return values are ignored by C compilers 217 | which support them as a non-standard extension. This is not the case for {Cpp}, 218 | which requires them to be sized types. 219 | 220 | Arguments passed by reference may be modified by the callee. 221 | 222 | Floating-point reals are passed the same way as aggregates of the same size; 223 | complex floating-point numbers are passed the same way as a struct containing 224 | two floating-point reals. (This constraint changes when the integer calling 225 | convention is augmented by the hardware floating-point calling convention.) 226 | 227 | In the base integer calling convention, variadic arguments are passed in the 228 | same manner as named arguments, with one exception. Variadic arguments with 229 | 2×XLEN-bit alignment and size at most 2×XLEN bits are passed in an 230 | *aligned* register pair (i.e., the first register in the pair is 231 | even-numbered), or on the stack by value if none is available. After a 232 | variadic argument has been passed on the stack, all future arguments will also 233 | be passed on the stack (i.e. the last argument register may be left unused due 234 | to the aligned register pair rule). 235 | 236 | Values are returned in the same manner as a first named argument of the same 237 | type would be passed. If such an argument would have been passed by 238 | reference, the caller allocates memory for the return value, and passes the 239 | address as an implicit first parameter. 240 | 241 | NOTE: There is no requirement that the address be returned from the function 242 | and so software should not assume that a0 will hold the address of the return 243 | value on return. 244 | 245 | The stack grows downwards (towards lower addresses) and the stack pointer shall 246 | be aligned to a 128-bit boundary upon procedure entry. 247 | The first argument passed on the stack is located at offset zero of the stack pointer 248 | on function entry; following arguments are stored at correspondingly 249 | higher addresses. 250 | 251 | In the standard ABI, the stack pointer must remain 252 | aligned throughout procedure execution. Non-standard ABI code must realign the 253 | stack pointer prior to invoking standard ABI procedures. The operating system 254 | must realign the stack pointer prior to invoking a signal handler; hence, 255 | POSIX signal handlers need not realign the stack pointer. In systems that 256 | service interrupts using the interruptee's stack, the interrupt service 257 | routine must realign the stack pointer if linked with any code that uses 258 | a non-standard stack-alignment discipline, but need not realign the stack 259 | pointer if all code adheres to the standard ABI. 260 | 261 | Procedures must not rely upon the persistence of 262 | stack-allocated data whose addresses lie below the stack pointer. 263 | 264 | Registers s0-s11 shall be preserved across procedure calls. 265 | No floating-point registers, if present, are preserved across calls. (This 266 | property changes when the integer calling convention is augmented by the 267 | hardware floating-point calling convention.) 268 | 269 | === Hardware Floating-point Calling Convention 270 | 271 | The hardware floating-point calling convention adds eight floating-point 272 | argument registers, fa0-fa7, the first two of which are also used to return 273 | values. Values are passed in floating-point registers whenever possible, 274 | whether or not the integer registers have been exhausted. 275 | 276 | The remainder of this section applies only to named arguments. Variadic 277 | arguments are passed according to the integer calling convention. 278 | 279 | ABI_FLEN refers to the width of a floating-point register in the ABI. 280 | The ABI_FLEN must be no wider than the ISA's FLEN. The ISA might have wider 281 | floating-point registers than the ABI. 282 | 283 | For the purposes of this section, "struct" refers to a C struct with its 284 | hierarchy flattened, including any array fields. That is, `struct { struct 285 | { float f[1]; } a[2]; }` and `struct { float f0; float f1; }` are 286 | treated the same. Fields containing empty structs or unions are ignored while 287 | flattening, even in {Cpp}, unless they have nontrivial copy constructors or 288 | destructors. Fields containing zero-length bit-fields or zero-length arrays are 289 | ignored while flattening. Attributes such as `aligned` or `packed` do not 290 | interfere with a struct's eligibility for being passed in registers according 291 | to the rules below, i.e. `struct { int i; double d; }` and `+struct 292 | __attribute__((__packed__)) { int i; double d }+` are treated the same, as are 293 | `struct { float f; float g; }` and `+struct { float f; float g __attribute__ 294 | ((aligned (8))); }+`. 295 | 296 | NOTE: One exceptional case for the flattening rule is an array of empty 297 | structs or unions; C treats it as an empty field, but {Cpp} 298 | treats it as a non-empty field since {Cpp} defines the size of an empty struct 299 | or union as 1. i.e. for `struct { struct {} e[1]; float f; }` as the first 300 | argument, C will treat it like `struct { float f; }` and pass `f` in `fa0` as 301 | described below, whereas {Cpp} will pass the pass the entire aggregate in `a0` 302 | (XLEN = 64) or `a0` and `a1` (XLEN = 32), as described in the integer calling 303 | convention. 304 | Zero-length arrays of empty structs or union will be 305 | ignored for both C and {Cpp}. i.e. For `struct { struct {} e[0]; float f; };`, 306 | as the first argument, C and {Cpp} will treat it like `struct { float f; }` 307 | and pass `f` in `fa0` as described below. 308 | 309 | A real floating-point argument is passed in a floating-point argument 310 | register if it is no more than ABI_FLEN bits wide and at least one floating-point 311 | argument register is available. Otherwise, it is passed according to the 312 | integer calling convention. 313 | When a floating-point argument narrower than FLEN bits is passed in a 314 | floating-point register, it is 1-extended (NaN-boxed) to FLEN bits. 315 | 316 | A struct containing just one floating-point real is passed as though it were 317 | a standalone floating-point real. 318 | 319 | A struct containing two floating-point reals is passed in two floating-point 320 | registers, if neither real is more than ABI_FLEN bits wide and at least two floating-point 321 | argument registers are available. (The registers need not be an aligned pair.) 322 | Otherwise, it is passed according to the integer calling convention. 323 | 324 | A complex floating-point number, or a struct containing just one complex 325 | floating-point number, is passed as though it were a struct containing two 326 | floating-point reals. 327 | 328 | A struct containing one floating-point real and one integer (or bitfield), in 329 | either order, is passed in a floating-point register and an integer register, 330 | provided the floating-point real is no more than ABI_FLEN bits wide and the 331 | integer is no more than XLEN bits wide, and at least one floating-point 332 | argument register and at least one integer argument register is available. 333 | If the struct is passed in this manner, and the integer is narrower than XLEN 334 | bits, the remaining bits are unspecified. 335 | If the struct is not passed in this manner, then it is passed according to the 336 | integer calling convention. 337 | 338 | Unions are never flattened and are always passed according to the integer 339 | calling convention. 340 | 341 | Values are returned in the same manner as a first named argument of the same 342 | type would be passed. 343 | 344 | Floating-point registers fs0-fs11 shall be preserved across procedure calls, 345 | provided they hold values no more than ABI_FLEN bits wide. 346 | 347 | === Standard Vector Calling Convention Variant 348 | 349 | The _RISC-V V Vector Extension_<> defines a set of thirty-two 350 | vector registers, v0-v31. The _RISC-V Vector Extension Intrinsic 351 | Document_<> defines vector types which include vector mask 352 | types, vector data types, and tuple vector data types. A value of vector type can 353 | be stored in vector register groups. 354 | 355 | The remainder of this section applies only to named vector arguments, other 356 | named arguments and return values follow the standard calling convention. 357 | Variadic vector arguments are passed by reference. 358 | 359 | v0 is used to pass the first vector mask argument to a function, and to return 360 | vector mask result from a function. v8-v23 are used to pass vector data 361 | arguments, tuple vector data arguments and the rest vector mask arguments to a 362 | function, and to return vector data and vector tuple results from a function. 363 | 364 | It must ensure that the entire contents of v1-v7 and v24-v31 are preserved 365 | across the call. 366 | 367 | Each vector data type and vector tuple type has an LMUL attribute that 368 | indicates a vector register group. The value of LMUL indicates the number of 369 | vector registers in the vector register group and requires the first vector 370 | register number in the vector register group must be a multiple of it. For 371 | example, the LMUL of `vint64m8_t` is 8, so v8-v15 vector register group can be 372 | allocated to this type, but v9-v16 can not because the v9 register number is 373 | not a multiple of 8. If LMUL is less than 1, it is treated as 1. If it is a 374 | vector mask type, its LMUL is 1. 375 | 376 | Each vector tuple type also has an NFIELDS attribute that indicates how many 377 | vector register groups the type contains. Thus a vector tuple type needs to 378 | take up LMUL×NFIELDS registers. 379 | 380 | The rules for passing vector arguments are as follows: 381 | 382 | 1. For the first vector mask argument, use v0 to pass it. 383 | 384 | 2. For vector data arguments or rest vector mask arguments, starting from the 385 | v8 register, if a vector register group between v8-v23 that has not been 386 | allocated can be found and the first register number is a multiple of LMUL, 387 | then allocate this vector register group to the argument and mark these 388 | registers as allocated. Otherwise, pass it by reference and are replaced in 389 | the argument list with the address. 390 | 391 | 3. For tuple vector data arguments, starting from the v8 register, if NFIELDS 392 | consecutive vector register groups between v8-v23 that have not been allocated 393 | can be found and the first register number is a multiple of LMUL, then allocate 394 | these vector register groups to the argument and mark these registers as 395 | allocated. Otherwise, pass it by reference and are replaced in the argument list 396 | with the address. 397 | 398 | NOTE: The registers assigned to the tuple vector data argument must be 399 | consecutive. For example, for the function 400 | `void foo(vint32m1_t a, vint32m2_t b, vint32m1x2_t c)`, v8 will be allocated 401 | to `a`, v10-v11 will be allocated to `b`, v12-v13 instead of v9 and v12 will 402 | beallocated to `c`. 403 | 404 | NOTE: It should be stressed that the search for the appropriate vector register 405 | groups starts at v8 each time and does not start at the next register after the 406 | registers are allocated for the previous vector argument. Therefore, it is 407 | possible that the vector register number allocated to a vector argument can be 408 | less than the vector register number allocated to previous vector arguments. 409 | For example, for the function 410 | `void foo (vint32m1_t a, vint32m2_t b, vint32m1_t c)`, according to the rules 411 | of allocation, v8 will be allocated to `a`, v10-v11 will be allocated to `b` 412 | and v9 will be allocated to `c`. This approach allows more vector registers to 413 | be allocated to arguments in some cases. 414 | 415 | Vector values are returned in the same manner as the first named argument of 416 | the same type would be passed. 417 | 418 | Vector types are disallowed in struct or union. 419 | 420 | Vector arguments and return values are disallowed to pass to an unprototyped 421 | function. 422 | 423 | NOTE: Functions that use the standard vector calling convention variant must be 424 | marked with `STO_RISCV_VARIANT_CC`, see <> for the meaning of 425 | `STO_RISCV_VARIANT_CC`. 426 | 427 | NOTE: `setjmp`/`longjmp` follow the standard calling convention, which clobbers 428 | all vector registers. Hence, the standard vector calling convention variant 429 | won't disrupt the `jmp_buf` ABI. 430 | 431 | === ILP32E Calling Convention 432 | 433 | IMPORTANT: RV32E is not a ratified base ISA and so we cannot guarantee the 434 | stability of ILP32E, in contrast with the rest of this document. This documents 435 | the current implementation in GCC as of the time of writing, but may be subject 436 | to change. 437 | 438 | The ILP32E calling convention is designed to be usable with the RV32E ISA. This 439 | calling convention is the same as the integer calling convention, except for the 440 | following differences. The stack pointer need only be aligned to a 32-bit 441 | boundary. Registers x16-x31 do not participate in the calling convention, so 442 | there are only six argument registers, a0-a5, only two callee-saved registers, 443 | s0-s1, and only three temporaries, t0-t2. 444 | 445 | If used with an ISA that has any of the registers x16-x31 and f0-f31, then 446 | these registers are considered temporaries. 447 | 448 | The ILP32E calling convention is not compatible with ISAs that have registers 449 | that require load and store alignments of more than 32 bits. In particular, this 450 | calling convention must not be used with the D ISA extension. 451 | 452 | === RV64ILP32* Calling Convention 453 | 454 | IMPORTANT: RV64ILP32* ABIs are experimental. 455 | 456 | The RV64ILP32* calling convention is designed to be usable with the RV64* ISA. 457 | These calling conventions are composed of the integer & floating-point & vector 458 | calling conventions. When passed in registers or on the stack, pointer scalars 459 | (32-bit), narrower than XLEN bits (64-bit), are sign-extended to XLEN bits. 460 | 461 | === Named ABIs 462 | 463 | This specification defines the following named ABIs: 464 | 465 | [[abi-ilp32]] 466 | ILP32:: Integer calling-convention only, hardware 467 | floating-point calling convention is not used (i.e. <> and 468 | <>). 469 | 470 | [[abi-ilp32f]] 471 | ILP32F:: ILP32 with hardware floating-point calling 472 | convention for ABI_FLEN=32 (i.e. <> and 473 | <>). 474 | 475 | [[abi-ilp32d]] 476 | ILP32D:: ILP32 with hardware floating-point calling 477 | convention for ABI_FLEN=64 (i.e. <> and 478 | <>). 479 | 480 | [[abi-ilp32e]] 481 | ILP32E:: <> only, 482 | hardware floating-point calling convention is not used (i.e. <>, 483 | <>, and <>). 484 | 485 | [[abi-lp64]] 486 | LP64:: Integer calling-convention only, hardware 487 | floating-point calling convention is not used (i.e. <> and 488 | <>). 489 | 490 | [[abi-lp64f]] 491 | LP64F:: LP64 with hardware floating-point calling 492 | convention for ABI_FLEN=32 (i.e. <> and 493 | <>). 494 | 495 | [[abi-lp64d]] 496 | LP64D:: LP64 with hardware floating-point calling 497 | convention for ABI_FLEN=64 (i.e. <> and 498 | <>). 499 | 500 | [[abi-lp64q]] 501 | LP64Q:: LP64 with hardware floating-point calling 502 | convention for ABI_FLEN=128 (i.e. <> and 503 | <>). 504 | 505 | [[abi-rv64ilp32]] 506 | RV64ILP32:: Integer calling-convention only, hardware 507 | floating-point calling convention is not used (i.e. <> and 508 | <>). 509 | 510 | [[abi-rv64ilp32f]] 511 | RV64ILP32F:: RV64ILP32 with hardware floating-point calling 512 | convention for ABI_FLEN=32 (i.e. <> and 513 | <>). 514 | 515 | [[abi-rv64ilp32d]] 516 | RV64ILP32D:: RV64ILP32 with hardware floating-point calling 517 | convention for ABI_FLEN=64 (i.e. <> and 518 | <>). 519 | 520 | [[abi-rv64ilp32q]] 521 | RV64ILP32Q:: RV64ILP32 with hardware floating-point calling 522 | convention for ABI_FLEN=128 (i.e. <> and 523 | <>). 524 | 525 | The LP64* ABIs are only compatible with RV64* ISAs. The ILP32* are compatible 526 | with RV32* and RV64* ISAs. 527 | 528 | NOTE: RV64ILP32* ABIs are experimental. 529 | 530 | The *F ABIs require the *F ISA extension, the *D ABIs require the *D ISA 531 | extension, and the LP64Q ABI requires the Q ISA extension. 532 | 533 | NOTE: This means code targeting the Zfinx extension always uses the ILP32, 534 | ILP32E or LP64 integer calling-convention only ABIs as there is no dedicated 535 | hardware floating-point register file. 536 | 537 | === Default ABIs 538 | 539 | While various different ABIs are technically possible, for software 540 | compatibility reasons it is strongly recommended to use the following 541 | default ABIs for specific architectures: 542 | 543 | [horizontal] 544 | on RV32G:: <> 545 | on RV64G:: <> 546 | 547 | NOTE: Although RV64GQ systems can technically use <>, it is 548 | strongly recommended to use LP64D on general-purpose RV64GQ systems for 549 | compatibility with standard RV64G software. 550 | 551 | == Calling Convention for System Calls 552 | 553 | The calling convention for system calls does not fall within the scope of this 554 | document. 555 | Please refer to the documentation of the RISC-V execution environment interface 556 | (e.g OS kernel ABI, SBI). 557 | 558 | == C/{Cpp} type details 559 | 560 | === C/{Cpp} type sizes and alignments 561 | 562 | There are two conventions for C/{Cpp} type sizes and alignments. 563 | 564 | ILP32, ILP32F, ILP32D, and ILP32E:: Use the following type sizes and 565 | alignments (based on the ILP32 convention): 566 | + 567 | .C/{Cpp} type sizes and alignments for ILP32 568 | [cols="4,>2,>3,4"] 569 | [width=60%] 570 | |=== 571 | | Type | Size (Bytes) | Alignment (Bytes) | Note 572 | 573 | | bool/_Bool | 1 | 1 | 574 | | char | 1 | 1 | 575 | | short | 2 | 2 | 576 | | int | 4 | 4 | 577 | | long | 4 | 4 | 578 | | long long | 8 | 8 | 579 | | void * | 4 | 4 | 580 | | +++__bf16+++ | 2 | 2 | Half precision floating point (bfloat16) 581 | | _Float16 | 2 | 2 | Half precision floating point (binary16 in IEEE 754-2008) 582 | | float | 4 | 4 | Single precision floating point (binary32 in IEEE 754-2008) 583 | | double | 8 | 8 | Double precision floating point (binary64 in IEEE 754-2008) 584 | | long double | 16 | 16 | Quadruple precision floating point (binary128 in IEEE 754-2008) 585 | | float _Complex | 8 | 4 | 586 | | double _Complex | 16 | 8 | 587 | | long double _Complex | 32 | 16 | 588 | |=== 589 | 590 | LP64, LP64F, LP64D, and LP64Q:: Use the following type sizes and 591 | alignments (based on the LP64 convention): 592 | + 593 | .C/{Cpp} type sizes and alignments for LP64 594 | [cols="4,>2,>3,4"] 595 | [width=60%] 596 | |=== 597 | | Type | Size (Bytes) | Alignment (Bytes) | Note 598 | 599 | | bool/_Bool | 1 | 1 | 600 | | char | 1 | 1 | 601 | | short | 2 | 2 | 602 | | int | 4 | 4 | 603 | | long | 8 | 8 | 604 | | long long | 8 | 8 | 605 | | +++__int128+++ | 16 | 16 | 606 | | void * | 8 | 8 | 607 | | +++__bf16+++ | 2 | 2 | Half precision floating point (bfloat16) 608 | | _Float16 | 2 | 2 | Half precision floating point (binary16 in IEEE 754-2008) 609 | | float | 4 | 4 | Single precision floating point (binary32 in IEEE 754-2008) 610 | | double | 8 | 8 | Double precision floating point (binary64 in IEEE 754-2008) 611 | | long double | 16 | 16 | Quadruple precision floating point (binary128 in IEEE 754-2008) 612 | | float _Complex | 8 | 4 | 613 | | double _Complex | 16 | 8 | 614 | | long double _Complex | 32 | 16 | 615 | |=== 616 | 617 | The alignment of `max_align_t` is 16. 618 | 619 | `CHAR_BIT` is 8. 620 | 621 | Structs and unions are aligned to the alignment of their most strictly aligned 622 | member. The size of any object is a multiple of its alignment. 623 | 624 | === Fixed-length vector 625 | 626 | Various compilers have support for fixed-length vector types, for example GCC 627 | and Clang both support declaring a type with `\\__attribute__\((vector_size(N))`, 628 | where N is a positive number larger than zero. 629 | 630 | The alignment requirement for the fixed length vector shall be equivalent to the 631 | alignment requirement of its elemental type. 632 | 633 | The size of the fixed length vector is determined by multiplying the size of its 634 | elemental type by the total number of elements within the vector. 635 | 636 | === C/{Cpp} type representations 637 | 638 | `char` is unsigned. 639 | 640 | Booleans (`bool`/`_Bool`) stored in memory or when being passed as scalar 641 | arguments are either `0` (`false`) or `1` (`true`). 642 | 643 | A null pointer (for all types) has the value zero. 644 | 645 | `_Float16` is as defined in the C ISO/IEC TS 18661-3 extension. 646 | 647 | `__bf16` has the same parameter passing and return rules as for `_Float16`. 648 | 649 | `_Complex` types have the same layout as a struct containing two fields of the 650 | corresponding real type (`float`, `double`, or `long double`), with the first 651 | member holding the real part and the second member holding the imaginary part. 652 | 653 | The type `size_t` is defined as `unsigned int` for RV32 and `unsigned long` for RV64. 654 | 655 | The type `ptrdiff_t` is defined as `int` for RV32 and `long` for RV64. 656 | 657 | === Bit-fields 658 | 659 | Bit-fields are packed in little-endian fashion. A bit-field that would span the 660 | alignment boundary of its integer type is padded to begin at the next 661 | alignment boundary. For example, `struct { int x : 10; int y : 12; }` is 662 | a 32-bit type with `x` in bits 9-0, `y` in bits 21-10, and bits 31-22 663 | undefined. By contrast, `struct { short x : 10; short y : 12; }` is a 32-bit 664 | type with `x` in bits 9-0, `y` in bits 27-16, and bits 31-28 and bits 15-10 665 | undefined. 666 | 667 | Bit-fields which are larger than their integer types are only present in {Cpp} 668 | and are defined by the _Itanium {Cpp} ABI_ <>. The bit-field 669 | and containing struct are aligned on a boundary corresponding to the largest 670 | integral type smaller than the bit-field, up to 64-bit alignment on RV32 or 671 | 128-bit alignment on RV64. Any bits in excess of the size of the declared type 672 | are treated as padding. For example `struct { char x : 9; char y; }` is a 673 | 24-bit type with `x` in bits 7-0, `y` in bit 23-16, and bits 15-8 undefined; 674 | `struct { char x : 9; char y : 2 }` is a 16-bit type with `x` in bits 7-0, `y` 675 | in bit 10-9, and bits 8 and 15-11 undefined. 676 | 677 | Unnamed nonzero length bit-fields allocate space in the same fashion as named 678 | bitfields but do not affect the alignment of the containing struct. 679 | 680 | Zero length bit-fields are aligned relative to the start of the containing 681 | struct according to their declared type and, since they must be unnamed, do not 682 | affect the struct alignment. C requires bit-fields on opposite sides of a 683 | zero-length bitfield to be treated as separate memory locations for the 684 | purposes of data races. 685 | 686 | === va_list, va_start, and va_arg 687 | 688 | The `va_list` type has the same representation as `void*` and points to a 689 | sequence of zero or more arguments with preceding padding for alignment, 690 | formatted and aligned as variadic arguments passed on the stack according to 691 | the integer calling convention (<>). All standard calling conventions use the 692 | same representation for variadic arguments to allow `va_list` types to be 693 | shared between them. 694 | 695 | The `va_start` macro in a function initializes its `va_list` argument to point 696 | to the first address at which a variadic argument could be passed to the 697 | function. If all integer argument registers are used for named formal 698 | arguments, the first variadic argument will have been passed on the stack by 699 | the caller, and the `va_list` can point to the address immediately after the 700 | last named argument passed on the stack, or the `sp` value on entry if no named 701 | arguments were passed on the stack. If some integer argument registers were not 702 | used for named formal arguments, then the first variadic argument may have been 703 | passed in a register. The function is then expected to construct a _varargs 704 | save area_ immediately below the entry `sp` and fill it with the entry values 705 | of all integer argument registers not used for named arguments, in sequence. 706 | The `va_list` value can then be initialized to the start of the varargs save 707 | area, and it will iterate through any variadic arguments passed via registers 708 | before continuing to variadic arguments passed on the stack, if any. 709 | 710 | The `va_arg` macro will align its `va_list` argument, fetch a value, and 711 | increment the `va_list` according to the alignment and size of a variadic 712 | argument of the given type, which may not be the same as the alignment and size 713 | of the given type in memory. If the type is passed by reference, the size and 714 | alignment used will be those of a pointer, and the fetched pointer will be used 715 | as the address of the actual argument. The `va_copy` macro is a single pointer 716 | copy and the `va_end` macro performs no operation. 717 | 718 | === Vector type sizes and alignments 719 | 720 | This section defines the sizes and alignments for the vector types defined in 721 | the _RISC-V Vector Extension Intrinsic Document_<>. 722 | The actual size of each type is determined by the hardware configuration, which 723 | is based on the content of the `vlenb` register. 724 | 725 | There are three classes of vector types: the vector mask types, the vector 726 | data types and the vector tuple types. 727 | 728 | .Type sizes and alignments for vector mask types 729 | [cols="4,3,>3,>2"] 730 | [width=80%] 731 | |=== 732 | | Internal Name | Type | Size (Bytes) | Alignment (Bytes) 733 | 734 | | __rvv_vbool1_t | vbool1_t | VLENB | 1 735 | | __rvv_vbool2_t | vbool2_t | VLENB / 2 | 1 736 | | __rvv_vbool4_t | vbool4_t | VLENB / 4 | 1 737 | | __rvv_vbool8_t | vbool8_t | ceil(VLENB / 8) | 1 738 | | __rvv_vbool16_t | vbool16_t | ceil(VLENB / 16) | 1 739 | | __rvv_vbool32_t | vbool32_t | ceil(VLENB / 32) | 1 740 | | __rvv_vbool64_t | vbool64_t | ceil(VLENB / 64) | 1 741 | |=== 742 | 743 | include::vector_type_infos.adoc[] 744 | 745 | NOTE: The vector mask types utilize a portion of the space, while the remaining 746 | content may be undefined, both in the register and in memory. 747 | 748 | NOTE: Size must be a positive integer. 749 | 750 | [appendix] 751 | == Linux-specific ABI 752 | 753 | NOTE: This section of the RISC-V calling convention specification only applies 754 | to Linux-based systems. 755 | 756 | In order to ensure compatibility between different implementations of the C 757 | library for Linux, we provide some extra definitions which only apply on those 758 | systems. These are noted in this section. 759 | 760 | === Linux-specific C type sizes and alignments 761 | 762 | The following definitions apply for all ABIs defined in this document. Here 763 | there is no differentiation between ILP32 and LP64 ABIs. 764 | 765 | .Linux-specific C type sizes and alignments 766 | [cols="2,>1,>1"] 767 | [width=80%] 768 | |=== 769 | | Type | Size (Bytes) | Alignment (Bytes) 770 | 771 | | wchar_t | 4 | 4 772 | | wint_t | 4 | 4 773 | |=== 774 | 775 | === Linux-specific C type representations 776 | 777 | The following definitions apply for all ABIs defined in this document. Here 778 | there is no differentiation between ILP32 and LP64 ABIs. 779 | 780 | `wchar_t` is signed. `wint_t` is unsigned. 781 | 782 | [bibliography] 783 | == References 784 | 785 | * [[[riscv-v-extension]]] "RISC-V V vector extension specification" 786 | https://github.com/riscv/riscv-v-spec 787 | 788 | * [[[rvv-intrinsic-doc]]] "RISC-V Vector Extension Intrinsic Document" 789 | https://github.com/riscv-non-isa/rvv-intrinsic-doc 790 | 791 | -------------------------------------------------------------------------------- /riscv-dwarf.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-dwarf]] 2 | = RISC-V DWARF Specification 3 | ifeval::["{docname}" == "riscv-dwarf"] 4 | include::prelude.adoc[] 5 | endif::[] 6 | 7 | == DWARF Debugging Format 8 | 9 | The DWARF debugging format for RISC-V follows the 10 | https://dwarfstd.org/[standard DWARF specification]; this specification only 11 | describes RISC-V-specific definitions. 12 | 13 | == DWARF Register Numbers 14 | 15 | The table below lists the mapping from DWARF register numbers to machine 16 | registers. 17 | 18 | .DWARF register number encodings 19 | [cols="2,2,4"] 20 | [width=80%] 21 | |=== 22 | | DWARF Number | Register Name | Description 23 | 24 | | 0 - 31 | x0 - x31 | Integer Registers 25 | | 32 - 63 | f0 - f31 | Floating-point Registers 26 | | 64 | | Alternate Frame Return Column 27 | | 65 - 95 | | Reserved for future standard extensions 28 | | 96 - 127 | v0 - v31 | Vector Registers 29 | | 128 - 3071 | | Reserved for future standard extensions 30 | | 3072 - 4095 | | Reserved for custom extensions 31 | | 4096 - 8191 | | CSRs 32 | |=== 33 | 34 | The alternate frame return column is meant to be used when unwinding from 35 | signal handlers, and stores the address where the signal handler will return 36 | to. 37 | 38 | The RISC-V specification defines a total of 4096 CSRs (see <>). 39 | Each CSR is assigned a DWARF register number corresponding to its specified CSR 40 | number plus 4096. 41 | 42 | [bibliography] 43 | == References 44 | 45 | * [[[riscv-priv]]] "The RISC-V Instruction Set Manual, Volume II: Privileged 46 | Architecture, Document", Editors Andrew Waterman, Krste Asanovi´c, and 47 | John Hauser, RISC-V International. 48 | -------------------------------------------------------------------------------- /riscv-rtabi.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-dwarf]] 2 | = RISC-V Run-time ABI Specification 3 | ifeval::["{docname}" == "riscv-rtabi"] 4 | include::prelude.adoc[] 5 | endif::[] 6 | 7 | == Run-time ABI 8 | 9 | This document defines the run-time helper function ABI for RISC-V, which 10 | includes compiler helper functions, but does not cover the language standard 11 | library functions. 12 | -------------------------------------------------------------------------------- /vector_type_infos.adoc: -------------------------------------------------------------------------------- 1 | .Type sizes and alignments for vector data types 2 | [cols="4,3,>3,>2"] 3 | [width=80%] 4 | |=== 5 | | Internal Name | Type | Size (Bytes) | Alignment (Bytes) 6 | 7 | | __rvv_vint8mf8_t | vint8mf8_t | (VLEN / 8) / 8 | 1 8 | | __rvv_vuint8mf8_t | vuint8mf8_t | (VLEN / 8) / 8 | 1 9 | | __rvv_vfloat8mf8_t | vfloat8mf8_t | (VLEN / 8) / 8 | 1 10 | | __rvv_vint8mf4_t | vint8mf4_t | (VLEN / 8) / 4 | 1 11 | | __rvv_vuint8mf4_t | vuint8mf4_t | (VLEN / 8) / 4 | 1 12 | | __rvv_vfloat8mf4_t | vfloat8mf4_t | (VLEN / 8) / 4 | 1 13 | | __rvv_vint8mf2_t | vint8mf2_t | (VLEN / 8) / 2 | 1 14 | | __rvv_vuint8mf2_t | vuint8mf2_t | (VLEN / 8) / 2 | 1 15 | | __rvv_vfloat8mf2_t | vfloat8mf2_t | (VLEN / 8) / 2 | 1 16 | | __rvv_vint8m1_t | vint8m1_t | (VLEN / 8) | 1 17 | | __rvv_vuint8m1_t | vuint8m1_t | (VLEN / 8) | 1 18 | | __rvv_vfloat8m1_t | vfloat8m1_t | (VLEN / 8) | 1 19 | | __rvv_vint8m2_t | vint8m2_t | (VLEN / 8) * 2 | 1 20 | | __rvv_vuint8m2_t | vuint8m2_t | (VLEN / 8) * 2 | 1 21 | | __rvv_vfloat8m2_t | vfloat8m2_t | (VLEN / 8) * 2 | 1 22 | | __rvv_vint8m4_t | vint8m4_t | (VLEN / 8) * 4 | 1 23 | | __rvv_vuint8m4_t | vuint8m4_t | (VLEN / 8) * 4 | 1 24 | | __rvv_vfloat8m4_t | vfloat8m4_t | (VLEN / 8) * 4 | 1 25 | | __rvv_vint8m8_t | vint8m8_t | (VLEN / 8) * 8 | 1 26 | | __rvv_vuint8m8_t | vuint8m8_t | (VLEN / 8) * 8 | 1 27 | | __rvv_vfloat8m8_t | vfloat8m8_t | (VLEN / 8) * 8 | 1 28 | | __rvv_vint16mf8_t | vint16mf8_t | (VLEN / 8) / 8 | 2 29 | | __rvv_vuint16mf8_t | vuint16mf8_t | (VLEN / 8) / 8 | 2 30 | | __rvv_vbfloat16mf8_t | vbfloat16mf8_t | (VLEN / 8) / 8 | 2 31 | | __rvv_vint16mf4_t | vint16mf4_t | (VLEN / 8) / 4 | 2 32 | | __rvv_vuint16mf4_t | vuint16mf4_t | (VLEN / 8) / 4 | 2 33 | | __rvv_vbfloat16mf4_t | vbfloat16mf4_t | (VLEN / 8) / 4 | 2 34 | | __rvv_vint16mf2_t | vint16mf2_t | (VLEN / 8) / 2 | 2 35 | | __rvv_vuint16mf2_t | vuint16mf2_t | (VLEN / 8) / 2 | 2 36 | | __rvv_vbfloat16mf2_t | vbfloat16mf2_t | (VLEN / 8) / 2 | 2 37 | | __rvv_vint16m1_t | vint16m1_t | (VLEN / 8) | 2 38 | | __rvv_vuint16m1_t | vuint16m1_t | (VLEN / 8) | 2 39 | | __rvv_vbfloat16m1_t | vbfloat16m1_t | (VLEN / 8) | 2 40 | | __rvv_vint16m2_t | vint16m2_t | (VLEN / 8) * 2 | 2 41 | | __rvv_vuint16m2_t | vuint16m2_t | (VLEN / 8) * 2 | 2 42 | | __rvv_vbfloat16m2_t | vbfloat16m2_t | (VLEN / 8) * 2 | 2 43 | | __rvv_vint16m4_t | vint16m4_t | (VLEN / 8) * 4 | 2 44 | | __rvv_vuint16m4_t | vuint16m4_t | (VLEN / 8) * 4 | 2 45 | | __rvv_vbfloat16m4_t | vbfloat16m4_t | (VLEN / 8) * 4 | 2 46 | | __rvv_vint16m8_t | vint16m8_t | (VLEN / 8) * 8 | 2 47 | | __rvv_vuint16m8_t | vuint16m8_t | (VLEN / 8) * 8 | 2 48 | | __rvv_vbfloat16m8_t | vbfloat16m8_t | (VLEN / 8) * 8 | 2 49 | | __rvv_vint32mf8_t | vint32mf8_t | (VLEN / 8) / 8 | 4 50 | | __rvv_vuint32mf8_t | vuint32mf8_t | (VLEN / 8) / 8 | 4 51 | | __rvv_vfloat32mf8_t | vfloat32mf8_t | (VLEN / 8) / 8 | 4 52 | | __rvv_vint32mf4_t | vint32mf4_t | (VLEN / 8) / 4 | 4 53 | | __rvv_vuint32mf4_t | vuint32mf4_t | (VLEN / 8) / 4 | 4 54 | | __rvv_vfloat32mf4_t | vfloat32mf4_t | (VLEN / 8) / 4 | 4 55 | | __rvv_vint32mf2_t | vint32mf2_t | (VLEN / 8) / 2 | 4 56 | | __rvv_vuint32mf2_t | vuint32mf2_t | (VLEN / 8) / 2 | 4 57 | | __rvv_vfloat32mf2_t | vfloat32mf2_t | (VLEN / 8) / 2 | 4 58 | | __rvv_vint32m1_t | vint32m1_t | (VLEN / 8) | 4 59 | | __rvv_vuint32m1_t | vuint32m1_t | (VLEN / 8) | 4 60 | | __rvv_vfloat32m1_t | vfloat32m1_t | (VLEN / 8) | 4 61 | | __rvv_vint32m2_t | vint32m2_t | (VLEN / 8) * 2 | 4 62 | | __rvv_vuint32m2_t | vuint32m2_t | (VLEN / 8) * 2 | 4 63 | | __rvv_vfloat32m2_t | vfloat32m2_t | (VLEN / 8) * 2 | 4 64 | | __rvv_vint32m4_t | vint32m4_t | (VLEN / 8) * 4 | 4 65 | | __rvv_vuint32m4_t | vuint32m4_t | (VLEN / 8) * 4 | 4 66 | | __rvv_vfloat32m4_t | vfloat32m4_t | (VLEN / 8) * 4 | 4 67 | | __rvv_vint32m8_t | vint32m8_t | (VLEN / 8) * 8 | 4 68 | | __rvv_vuint32m8_t | vuint32m8_t | (VLEN / 8) * 8 | 4 69 | | __rvv_vfloat32m8_t | vfloat32m8_t | (VLEN / 8) * 8 | 4 70 | | __rvv_vint64mf8_t | vint64mf8_t | (VLEN / 8) / 8 | 8 71 | | __rvv_vuint64mf8_t | vuint64mf8_t | (VLEN / 8) / 8 | 8 72 | | __rvv_vfloat64mf8_t | vfloat64mf8_t | (VLEN / 8) / 8 | 8 73 | | __rvv_vint64mf4_t | vint64mf4_t | (VLEN / 8) / 4 | 8 74 | | __rvv_vuint64mf4_t | vuint64mf4_t | (VLEN / 8) / 4 | 8 75 | | __rvv_vfloat64mf4_t | vfloat64mf4_t | (VLEN / 8) / 4 | 8 76 | | __rvv_vint64mf2_t | vint64mf2_t | (VLEN / 8) / 2 | 8 77 | | __rvv_vuint64mf2_t | vuint64mf2_t | (VLEN / 8) / 2 | 8 78 | | __rvv_vfloat64mf2_t | vfloat64mf2_t | (VLEN / 8) / 2 | 8 79 | | __rvv_vint64m1_t | vint64m1_t | (VLEN / 8) | 8 80 | | __rvv_vuint64m1_t | vuint64m1_t | (VLEN / 8) | 8 81 | | __rvv_vfloat64m1_t | vfloat64m1_t | (VLEN / 8) | 8 82 | | __rvv_vint64m2_t | vint64m2_t | (VLEN / 8) * 2 | 8 83 | | __rvv_vuint64m2_t | vuint64m2_t | (VLEN / 8) * 2 | 8 84 | | __rvv_vfloat64m2_t | vfloat64m2_t | (VLEN / 8) * 2 | 8 85 | | __rvv_vint64m4_t | vint64m4_t | (VLEN / 8) * 4 | 8 86 | | __rvv_vuint64m4_t | vuint64m4_t | (VLEN / 8) * 4 | 8 87 | | __rvv_vfloat64m4_t | vfloat64m4_t | (VLEN / 8) * 4 | 8 88 | | __rvv_vint64m8_t | vint64m8_t | (VLEN / 8) * 8 | 8 89 | | __rvv_vuint64m8_t | vuint64m8_t | (VLEN / 8) * 8 | 8 90 | | __rvv_vfloat64m8_t | vfloat64m8_t | (VLEN / 8) * 8 | 8 91 | |=== 92 | 93 | .Type sizes and alignments for vector tuple types 94 | [cols="4,3,>3,>2"] 95 | [width=80%] 96 | |=== 97 | | Internal Name | Type | Size (Bytes) | Alignment (Bytes) 98 | 99 | | __rvv_vint8mf8x2_t | vint8mf8x2_t | (VLEN / 8) / 4 | 1 100 | | __rvv_vuint8mf8x2_t | vuint8mf8x2_t | (VLEN / 8) / 4 | 1 101 | | __rvv_vfloat8mf8x2_t | vfloat8mf8x2_t | (VLEN / 8) / 4 | 1 102 | | __rvv_vint8mf8x3_t | vint8mf8x3_t | (VLEN / 8) * 0.375 | 1 103 | | __rvv_vuint8mf8x3_t | vuint8mf8x3_t | (VLEN / 8) * 0.375 | 1 104 | | __rvv_vfloat8mf8x3_t | vfloat8mf8x3_t | (VLEN / 8) * 0.375 | 1 105 | | __rvv_vint8mf8x4_t | vint8mf8x4_t | (VLEN / 8) / 2 | 1 106 | | __rvv_vuint8mf8x4_t | vuint8mf8x4_t | (VLEN / 8) / 2 | 1 107 | | __rvv_vfloat8mf8x4_t | vfloat8mf8x4_t | (VLEN / 8) / 2 | 1 108 | | __rvv_vint8mf8x5_t | vint8mf8x5_t | (VLEN / 8) * 0.625 | 1 109 | | __rvv_vuint8mf8x5_t | vuint8mf8x5_t | (VLEN / 8) * 0.625 | 1 110 | | __rvv_vfloat8mf8x5_t | vfloat8mf8x5_t | (VLEN / 8) * 0.625 | 1 111 | | __rvv_vint8mf8x6_t | vint8mf8x6_t | (VLEN / 8) * 0.75 | 1 112 | | __rvv_vuint8mf8x6_t | vuint8mf8x6_t | (VLEN / 8) * 0.75 | 1 113 | | __rvv_vfloat8mf8x6_t | vfloat8mf8x6_t | (VLEN / 8) * 0.75 | 1 114 | | __rvv_vint8mf8x7_t | vint8mf8x7_t | (VLEN / 8) * 0.875 | 1 115 | | __rvv_vuint8mf8x7_t | vuint8mf8x7_t | (VLEN / 8) * 0.875 | 1 116 | | __rvv_vfloat8mf8x7_t | vfloat8mf8x7_t | (VLEN / 8) * 0.875 | 1 117 | | __rvv_vint8mf8x8_t | vint8mf8x8_t | (VLEN / 8) | 1 118 | | __rvv_vuint8mf8x8_t | vuint8mf8x8_t | (VLEN / 8) | 1 119 | | __rvv_vfloat8mf8x8_t | vfloat8mf8x8_t | (VLEN / 8) | 1 120 | | __rvv_vint8mf4x2_t | vint8mf4x2_t | (VLEN / 8) / 2 | 1 121 | | __rvv_vuint8mf4x2_t | vuint8mf4x2_t | (VLEN / 8) / 2 | 1 122 | | __rvv_vfloat8mf4x2_t | vfloat8mf4x2_t | (VLEN / 8) / 2 | 1 123 | | __rvv_vint8mf4x3_t | vint8mf4x3_t | (VLEN / 8) * 0.75 | 1 124 | | __rvv_vuint8mf4x3_t | vuint8mf4x3_t | (VLEN / 8) * 0.75 | 1 125 | | __rvv_vfloat8mf4x3_t | vfloat8mf4x3_t | (VLEN / 8) * 0.75 | 1 126 | | __rvv_vint8mf4x4_t | vint8mf4x4_t | (VLEN / 8) | 1 127 | | __rvv_vuint8mf4x4_t | vuint8mf4x4_t | (VLEN / 8) | 1 128 | | __rvv_vfloat8mf4x4_t | vfloat8mf4x4_t | (VLEN / 8) | 1 129 | | __rvv_vint8mf4x5_t | vint8mf4x5_t | (VLEN / 8) * 1.25 | 1 130 | | __rvv_vuint8mf4x5_t | vuint8mf4x5_t | (VLEN / 8) * 1.25 | 1 131 | | __rvv_vfloat8mf4x5_t | vfloat8mf4x5_t | (VLEN / 8) * 1.25 | 1 132 | | __rvv_vint8mf4x6_t | vint8mf4x6_t | (VLEN / 8) * 1.5 | 1 133 | | __rvv_vuint8mf4x6_t | vuint8mf4x6_t | (VLEN / 8) * 1.5 | 1 134 | | __rvv_vfloat8mf4x6_t | vfloat8mf4x6_t | (VLEN / 8) * 1.5 | 1 135 | | __rvv_vint8mf4x7_t | vint8mf4x7_t | (VLEN / 8) * 1.75 | 1 136 | | __rvv_vuint8mf4x7_t | vuint8mf4x7_t | (VLEN / 8) * 1.75 | 1 137 | | __rvv_vfloat8mf4x7_t | vfloat8mf4x7_t | (VLEN / 8) * 1.75 | 1 138 | | __rvv_vint8mf4x8_t | vint8mf4x8_t | (VLEN / 8) * 2 | 1 139 | | __rvv_vuint8mf4x8_t | vuint8mf4x8_t | (VLEN / 8) * 2 | 1 140 | | __rvv_vfloat8mf4x8_t | vfloat8mf4x8_t | (VLEN / 8) * 2 | 1 141 | | __rvv_vint8mf2x2_t | vint8mf2x2_t | (VLEN / 8) | 1 142 | | __rvv_vuint8mf2x2_t | vuint8mf2x2_t | (VLEN / 8) | 1 143 | | __rvv_vfloat8mf2x2_t | vfloat8mf2x2_t | (VLEN / 8) | 1 144 | | __rvv_vint8mf2x3_t | vint8mf2x3_t | (VLEN / 8) * 1.5 | 1 145 | | __rvv_vuint8mf2x3_t | vuint8mf2x3_t | (VLEN / 8) * 1.5 | 1 146 | | __rvv_vfloat8mf2x3_t | vfloat8mf2x3_t | (VLEN / 8) * 1.5 | 1 147 | | __rvv_vint8mf2x4_t | vint8mf2x4_t | (VLEN / 8) * 2 | 1 148 | | __rvv_vuint8mf2x4_t | vuint8mf2x4_t | (VLEN / 8) * 2 | 1 149 | | __rvv_vfloat8mf2x4_t | vfloat8mf2x4_t | (VLEN / 8) * 2 | 1 150 | | __rvv_vint8mf2x5_t | vint8mf2x5_t | (VLEN / 8) * 2.5 | 1 151 | | __rvv_vuint8mf2x5_t | vuint8mf2x5_t | (VLEN / 8) * 2.5 | 1 152 | | __rvv_vfloat8mf2x5_t | vfloat8mf2x5_t | (VLEN / 8) * 2.5 | 1 153 | | __rvv_vint8mf2x6_t | vint8mf2x6_t | (VLEN / 8) * 3 | 1 154 | | __rvv_vuint8mf2x6_t | vuint8mf2x6_t | (VLEN / 8) * 3 | 1 155 | | __rvv_vfloat8mf2x6_t | vfloat8mf2x6_t | (VLEN / 8) * 3 | 1 156 | | __rvv_vint8mf2x7_t | vint8mf2x7_t | (VLEN / 8) * 3.5 | 1 157 | | __rvv_vuint8mf2x7_t | vuint8mf2x7_t | (VLEN / 8) * 3.5 | 1 158 | | __rvv_vfloat8mf2x7_t | vfloat8mf2x7_t | (VLEN / 8) * 3.5 | 1 159 | | __rvv_vint8mf2x8_t | vint8mf2x8_t | (VLEN / 8) * 4 | 1 160 | | __rvv_vuint8mf2x8_t | vuint8mf2x8_t | (VLEN / 8) * 4 | 1 161 | | __rvv_vfloat8mf2x8_t | vfloat8mf2x8_t | (VLEN / 8) * 4 | 1 162 | | __rvv_vint8m1x2_t | vint8m1x2_t | (VLEN / 8) * 2 | 1 163 | | __rvv_vuint8m1x2_t | vuint8m1x2_t | (VLEN / 8) * 2 | 1 164 | | __rvv_vfloat8m1x2_t | vfloat8m1x2_t | (VLEN / 8) * 2 | 1 165 | | __rvv_vint8m1x3_t | vint8m1x3_t | (VLEN / 8) * 3 | 1 166 | | __rvv_vuint8m1x3_t | vuint8m1x3_t | (VLEN / 8) * 3 | 1 167 | | __rvv_vfloat8m1x3_t | vfloat8m1x3_t | (VLEN / 8) * 3 | 1 168 | | __rvv_vint8m1x4_t | vint8m1x4_t | (VLEN / 8) * 4 | 1 169 | | __rvv_vuint8m1x4_t | vuint8m1x4_t | (VLEN / 8) * 4 | 1 170 | | __rvv_vfloat8m1x4_t | vfloat8m1x4_t | (VLEN / 8) * 4 | 1 171 | | __rvv_vint8m1x5_t | vint8m1x5_t | (VLEN / 8) * 5 | 1 172 | | __rvv_vuint8m1x5_t | vuint8m1x5_t | (VLEN / 8) * 5 | 1 173 | | __rvv_vfloat8m1x5_t | vfloat8m1x5_t | (VLEN / 8) * 5 | 1 174 | | __rvv_vint8m1x6_t | vint8m1x6_t | (VLEN / 8) * 6 | 1 175 | | __rvv_vuint8m1x6_t | vuint8m1x6_t | (VLEN / 8) * 6 | 1 176 | | __rvv_vfloat8m1x6_t | vfloat8m1x6_t | (VLEN / 8) * 6 | 1 177 | | __rvv_vint8m1x7_t | vint8m1x7_t | (VLEN / 8) * 7 | 1 178 | | __rvv_vuint8m1x7_t | vuint8m1x7_t | (VLEN / 8) * 7 | 1 179 | | __rvv_vfloat8m1x7_t | vfloat8m1x7_t | (VLEN / 8) * 7 | 1 180 | | __rvv_vint8m1x8_t | vint8m1x8_t | (VLEN / 8) * 8 | 1 181 | | __rvv_vuint8m1x8_t | vuint8m1x8_t | (VLEN / 8) * 8 | 1 182 | | __rvv_vfloat8m1x8_t | vfloat8m1x8_t | (VLEN / 8) * 8 | 1 183 | | __rvv_vint8m2x2_t | vint8m2x2_t | (VLEN / 8) * 4 | 1 184 | | __rvv_vuint8m2x2_t | vuint8m2x2_t | (VLEN / 8) * 4 | 1 185 | | __rvv_vfloat8m2x2_t | vfloat8m2x2_t | (VLEN / 8) * 4 | 1 186 | | __rvv_vint8m2x3_t | vint8m2x3_t | (VLEN / 8) * 6 | 1 187 | | __rvv_vuint8m2x3_t | vuint8m2x3_t | (VLEN / 8) * 6 | 1 188 | | __rvv_vfloat8m2x3_t | vfloat8m2x3_t | (VLEN / 8) * 6 | 1 189 | | __rvv_vint8m2x4_t | vint8m2x4_t | (VLEN / 8) * 8 | 1 190 | | __rvv_vuint8m2x4_t | vuint8m2x4_t | (VLEN / 8) * 8 | 1 191 | | __rvv_vfloat8m2x4_t | vfloat8m2x4_t | (VLEN / 8) * 8 | 1 192 | | __rvv_vint8m4x2_t | vint8m4x2_t | (VLEN / 8) * 8 | 1 193 | | __rvv_vuint8m4x2_t | vuint8m4x2_t | (VLEN / 8) * 8 | 1 194 | | __rvv_vfloat8m4x2_t | vfloat8m4x2_t | (VLEN / 8) * 8 | 1 195 | | __rvv_vint16mf8x2_t | vint16mf8x2_t | (VLEN / 8) / 4 | 2 196 | | __rvv_vuint16mf8x2_t | vuint16mf8x2_t | (VLEN / 8) / 4 | 2 197 | | __rvv_vbfloat16mf8x2_t | vbfloat16mf8x2_t | (VLEN / 8) / 4 | 2 198 | | __rvv_vint16mf8x3_t | vint16mf8x3_t | (VLEN / 8) * 0.375 | 2 199 | | __rvv_vuint16mf8x3_t | vuint16mf8x3_t | (VLEN / 8) * 0.375 | 2 200 | | __rvv_vbfloat16mf8x3_t | vbfloat16mf8x3_t | (VLEN / 8) * 0.375 | 2 201 | | __rvv_vint16mf8x4_t | vint16mf8x4_t | (VLEN / 8) / 2 | 2 202 | | __rvv_vuint16mf8x4_t | vuint16mf8x4_t | (VLEN / 8) / 2 | 2 203 | | __rvv_vbfloat16mf8x4_t | vbfloat16mf8x4_t | (VLEN / 8) / 2 | 2 204 | | __rvv_vint16mf8x5_t | vint16mf8x5_t | (VLEN / 8) * 0.625 | 2 205 | | __rvv_vuint16mf8x5_t | vuint16mf8x5_t | (VLEN / 8) * 0.625 | 2 206 | | __rvv_vbfloat16mf8x5_t | vbfloat16mf8x5_t | (VLEN / 8) * 0.625 | 2 207 | | __rvv_vint16mf8x6_t | vint16mf8x6_t | (VLEN / 8) * 0.75 | 2 208 | | __rvv_vuint16mf8x6_t | vuint16mf8x6_t | (VLEN / 8) * 0.75 | 2 209 | | __rvv_vbfloat16mf8x6_t | vbfloat16mf8x6_t | (VLEN / 8) * 0.75 | 2 210 | | __rvv_vint16mf8x7_t | vint16mf8x7_t | (VLEN / 8) * 0.875 | 2 211 | | __rvv_vuint16mf8x7_t | vuint16mf8x7_t | (VLEN / 8) * 0.875 | 2 212 | | __rvv_vbfloat16mf8x7_t | vbfloat16mf8x7_t | (VLEN / 8) * 0.875 | 2 213 | | __rvv_vint16mf8x8_t | vint16mf8x8_t | (VLEN / 8) | 2 214 | | __rvv_vuint16mf8x8_t | vuint16mf8x8_t | (VLEN / 8) | 2 215 | | __rvv_vbfloat16mf8x8_t | vbfloat16mf8x8_t | (VLEN / 8) | 2 216 | | __rvv_vint16mf4x2_t | vint16mf4x2_t | (VLEN / 8) / 2 | 2 217 | | __rvv_vuint16mf4x2_t | vuint16mf4x2_t | (VLEN / 8) / 2 | 2 218 | | __rvv_vbfloat16mf4x2_t | vbfloat16mf4x2_t | (VLEN / 8) / 2 | 2 219 | | __rvv_vint16mf4x3_t | vint16mf4x3_t | (VLEN / 8) * 0.75 | 2 220 | | __rvv_vuint16mf4x3_t | vuint16mf4x3_t | (VLEN / 8) * 0.75 | 2 221 | | __rvv_vbfloat16mf4x3_t | vbfloat16mf4x3_t | (VLEN / 8) * 0.75 | 2 222 | | __rvv_vint16mf4x4_t | vint16mf4x4_t | (VLEN / 8) | 2 223 | | __rvv_vuint16mf4x4_t | vuint16mf4x4_t | (VLEN / 8) | 2 224 | | __rvv_vbfloat16mf4x4_t | vbfloat16mf4x4_t | (VLEN / 8) | 2 225 | | __rvv_vint16mf4x5_t | vint16mf4x5_t | (VLEN / 8) * 1.25 | 2 226 | | __rvv_vuint16mf4x5_t | vuint16mf4x5_t | (VLEN / 8) * 1.25 | 2 227 | | __rvv_vbfloat16mf4x5_t | vbfloat16mf4x5_t | (VLEN / 8) * 1.25 | 2 228 | | __rvv_vint16mf4x6_t | vint16mf4x6_t | (VLEN / 8) * 1.5 | 2 229 | | __rvv_vuint16mf4x6_t | vuint16mf4x6_t | (VLEN / 8) * 1.5 | 2 230 | | __rvv_vbfloat16mf4x6_t | vbfloat16mf4x6_t | (VLEN / 8) * 1.5 | 2 231 | | __rvv_vint16mf4x7_t | vint16mf4x7_t | (VLEN / 8) * 1.75 | 2 232 | | __rvv_vuint16mf4x7_t | vuint16mf4x7_t | (VLEN / 8) * 1.75 | 2 233 | | __rvv_vbfloat16mf4x7_t | vbfloat16mf4x7_t | (VLEN / 8) * 1.75 | 2 234 | | __rvv_vint16mf4x8_t | vint16mf4x8_t | (VLEN / 8) * 2 | 2 235 | | __rvv_vuint16mf4x8_t | vuint16mf4x8_t | (VLEN / 8) * 2 | 2 236 | | __rvv_vbfloat16mf4x8_t | vbfloat16mf4x8_t | (VLEN / 8) * 2 | 2 237 | | __rvv_vint16mf2x2_t | vint16mf2x2_t | (VLEN / 8) | 2 238 | | __rvv_vuint16mf2x2_t | vuint16mf2x2_t | (VLEN / 8) | 2 239 | | __rvv_vbfloat16mf2x2_t | vbfloat16mf2x2_t | (VLEN / 8) | 2 240 | | __rvv_vint16mf2x3_t | vint16mf2x3_t | (VLEN / 8) * 1.5 | 2 241 | | __rvv_vuint16mf2x3_t | vuint16mf2x3_t | (VLEN / 8) * 1.5 | 2 242 | | __rvv_vbfloat16mf2x3_t | vbfloat16mf2x3_t | (VLEN / 8) * 1.5 | 2 243 | | __rvv_vint16mf2x4_t | vint16mf2x4_t | (VLEN / 8) * 2 | 2 244 | | __rvv_vuint16mf2x4_t | vuint16mf2x4_t | (VLEN / 8) * 2 | 2 245 | | __rvv_vbfloat16mf2x4_t | vbfloat16mf2x4_t | (VLEN / 8) * 2 | 2 246 | | __rvv_vint16mf2x5_t | vint16mf2x5_t | (VLEN / 8) * 2.5 | 2 247 | | __rvv_vuint16mf2x5_t | vuint16mf2x5_t | (VLEN / 8) * 2.5 | 2 248 | | __rvv_vbfloat16mf2x5_t | vbfloat16mf2x5_t | (VLEN / 8) * 2.5 | 2 249 | | __rvv_vint16mf2x6_t | vint16mf2x6_t | (VLEN / 8) * 3 | 2 250 | | __rvv_vuint16mf2x6_t | vuint16mf2x6_t | (VLEN / 8) * 3 | 2 251 | | __rvv_vbfloat16mf2x6_t | vbfloat16mf2x6_t | (VLEN / 8) * 3 | 2 252 | | __rvv_vint16mf2x7_t | vint16mf2x7_t | (VLEN / 8) * 3.5 | 2 253 | | __rvv_vuint16mf2x7_t | vuint16mf2x7_t | (VLEN / 8) * 3.5 | 2 254 | | __rvv_vbfloat16mf2x7_t | vbfloat16mf2x7_t | (VLEN / 8) * 3.5 | 2 255 | | __rvv_vint16mf2x8_t | vint16mf2x8_t | (VLEN / 8) * 4 | 2 256 | | __rvv_vuint16mf2x8_t | vuint16mf2x8_t | (VLEN / 8) * 4 | 2 257 | | __rvv_vbfloat16mf2x8_t | vbfloat16mf2x8_t | (VLEN / 8) * 4 | 2 258 | | __rvv_vint16m1x2_t | vint16m1x2_t | (VLEN / 8) * 2 | 2 259 | | __rvv_vuint16m1x2_t | vuint16m1x2_t | (VLEN / 8) * 2 | 2 260 | | __rvv_vbfloat16m1x2_t | vbfloat16m1x2_t | (VLEN / 8) * 2 | 2 261 | | __rvv_vint16m1x3_t | vint16m1x3_t | (VLEN / 8) * 3 | 2 262 | | __rvv_vuint16m1x3_t | vuint16m1x3_t | (VLEN / 8) * 3 | 2 263 | | __rvv_vbfloat16m1x3_t | vbfloat16m1x3_t | (VLEN / 8) * 3 | 2 264 | | __rvv_vint16m1x4_t | vint16m1x4_t | (VLEN / 8) * 4 | 2 265 | | __rvv_vuint16m1x4_t | vuint16m1x4_t | (VLEN / 8) * 4 | 2 266 | | __rvv_vbfloat16m1x4_t | vbfloat16m1x4_t | (VLEN / 8) * 4 | 2 267 | | __rvv_vint16m1x5_t | vint16m1x5_t | (VLEN / 8) * 5 | 2 268 | | __rvv_vuint16m1x5_t | vuint16m1x5_t | (VLEN / 8) * 5 | 2 269 | | __rvv_vbfloat16m1x5_t | vbfloat16m1x5_t | (VLEN / 8) * 5 | 2 270 | | __rvv_vint16m1x6_t | vint16m1x6_t | (VLEN / 8) * 6 | 2 271 | | __rvv_vuint16m1x6_t | vuint16m1x6_t | (VLEN / 8) * 6 | 2 272 | | __rvv_vbfloat16m1x6_t | vbfloat16m1x6_t | (VLEN / 8) * 6 | 2 273 | | __rvv_vint16m1x7_t | vint16m1x7_t | (VLEN / 8) * 7 | 2 274 | | __rvv_vuint16m1x7_t | vuint16m1x7_t | (VLEN / 8) * 7 | 2 275 | | __rvv_vbfloat16m1x7_t | vbfloat16m1x7_t | (VLEN / 8) * 7 | 2 276 | | __rvv_vint16m1x8_t | vint16m1x8_t | (VLEN / 8) * 8 | 2 277 | | __rvv_vuint16m1x8_t | vuint16m1x8_t | (VLEN / 8) * 8 | 2 278 | | __rvv_vbfloat16m1x8_t | vbfloat16m1x8_t | (VLEN / 8) * 8 | 2 279 | | __rvv_vint16m2x2_t | vint16m2x2_t | (VLEN / 8) * 4 | 2 280 | | __rvv_vuint16m2x2_t | vuint16m2x2_t | (VLEN / 8) * 4 | 2 281 | | __rvv_vbfloat16m2x2_t | vbfloat16m2x2_t | (VLEN / 8) * 4 | 2 282 | | __rvv_vint16m2x3_t | vint16m2x3_t | (VLEN / 8) * 6 | 2 283 | | __rvv_vuint16m2x3_t | vuint16m2x3_t | (VLEN / 8) * 6 | 2 284 | | __rvv_vbfloat16m2x3_t | vbfloat16m2x3_t | (VLEN / 8) * 6 | 2 285 | | __rvv_vint16m2x4_t | vint16m2x4_t | (VLEN / 8) * 8 | 2 286 | | __rvv_vuint16m2x4_t | vuint16m2x4_t | (VLEN / 8) * 8 | 2 287 | | __rvv_vbfloat16m2x4_t | vbfloat16m2x4_t | (VLEN / 8) * 8 | 2 288 | | __rvv_vint16m4x2_t | vint16m4x2_t | (VLEN / 8) * 8 | 2 289 | | __rvv_vuint16m4x2_t | vuint16m4x2_t | (VLEN / 8) * 8 | 2 290 | | __rvv_vbfloat16m4x2_t | vbfloat16m4x2_t | (VLEN / 8) * 8 | 2 291 | | __rvv_vint32mf8x2_t | vint32mf8x2_t | (VLEN / 8) / 4 | 4 292 | | __rvv_vuint32mf8x2_t | vuint32mf8x2_t | (VLEN / 8) / 4 | 4 293 | | __rvv_vfloat32mf8x2_t | vfloat32mf8x2_t | (VLEN / 8) / 4 | 4 294 | | __rvv_vint32mf8x3_t | vint32mf8x3_t | (VLEN / 8) * 0.375 | 4 295 | | __rvv_vuint32mf8x3_t | vuint32mf8x3_t | (VLEN / 8) * 0.375 | 4 296 | | __rvv_vfloat32mf8x3_t | vfloat32mf8x3_t | (VLEN / 8) * 0.375 | 4 297 | | __rvv_vint32mf8x4_t | vint32mf8x4_t | (VLEN / 8) / 2 | 4 298 | | __rvv_vuint32mf8x4_t | vuint32mf8x4_t | (VLEN / 8) / 2 | 4 299 | | __rvv_vfloat32mf8x4_t | vfloat32mf8x4_t | (VLEN / 8) / 2 | 4 300 | | __rvv_vint32mf8x5_t | vint32mf8x5_t | (VLEN / 8) * 0.625 | 4 301 | | __rvv_vuint32mf8x5_t | vuint32mf8x5_t | (VLEN / 8) * 0.625 | 4 302 | | __rvv_vfloat32mf8x5_t | vfloat32mf8x5_t | (VLEN / 8) * 0.625 | 4 303 | | __rvv_vint32mf8x6_t | vint32mf8x6_t | (VLEN / 8) * 0.75 | 4 304 | | __rvv_vuint32mf8x6_t | vuint32mf8x6_t | (VLEN / 8) * 0.75 | 4 305 | | __rvv_vfloat32mf8x6_t | vfloat32mf8x6_t | (VLEN / 8) * 0.75 | 4 306 | | __rvv_vint32mf8x7_t | vint32mf8x7_t | (VLEN / 8) * 0.875 | 4 307 | | __rvv_vuint32mf8x7_t | vuint32mf8x7_t | (VLEN / 8) * 0.875 | 4 308 | | __rvv_vfloat32mf8x7_t | vfloat32mf8x7_t | (VLEN / 8) * 0.875 | 4 309 | | __rvv_vint32mf8x8_t | vint32mf8x8_t | (VLEN / 8) | 4 310 | | __rvv_vuint32mf8x8_t | vuint32mf8x8_t | (VLEN / 8) | 4 311 | | __rvv_vfloat32mf8x8_t | vfloat32mf8x8_t | (VLEN / 8) | 4 312 | | __rvv_vint32mf4x2_t | vint32mf4x2_t | (VLEN / 8) / 2 | 4 313 | | __rvv_vuint32mf4x2_t | vuint32mf4x2_t | (VLEN / 8) / 2 | 4 314 | | __rvv_vfloat32mf4x2_t | vfloat32mf4x2_t | (VLEN / 8) / 2 | 4 315 | | __rvv_vint32mf4x3_t | vint32mf4x3_t | (VLEN / 8) * 0.75 | 4 316 | | __rvv_vuint32mf4x3_t | vuint32mf4x3_t | (VLEN / 8) * 0.75 | 4 317 | | __rvv_vfloat32mf4x3_t | vfloat32mf4x3_t | (VLEN / 8) * 0.75 | 4 318 | | __rvv_vint32mf4x4_t | vint32mf4x4_t | (VLEN / 8) | 4 319 | | __rvv_vuint32mf4x4_t | vuint32mf4x4_t | (VLEN / 8) | 4 320 | | __rvv_vfloat32mf4x4_t | vfloat32mf4x4_t | (VLEN / 8) | 4 321 | | __rvv_vint32mf4x5_t | vint32mf4x5_t | (VLEN / 8) * 1.25 | 4 322 | | __rvv_vuint32mf4x5_t | vuint32mf4x5_t | (VLEN / 8) * 1.25 | 4 323 | | __rvv_vfloat32mf4x5_t | vfloat32mf4x5_t | (VLEN / 8) * 1.25 | 4 324 | | __rvv_vint32mf4x6_t | vint32mf4x6_t | (VLEN / 8) * 1.5 | 4 325 | | __rvv_vuint32mf4x6_t | vuint32mf4x6_t | (VLEN / 8) * 1.5 | 4 326 | | __rvv_vfloat32mf4x6_t | vfloat32mf4x6_t | (VLEN / 8) * 1.5 | 4 327 | | __rvv_vint32mf4x7_t | vint32mf4x7_t | (VLEN / 8) * 1.75 | 4 328 | | __rvv_vuint32mf4x7_t | vuint32mf4x7_t | (VLEN / 8) * 1.75 | 4 329 | | __rvv_vfloat32mf4x7_t | vfloat32mf4x7_t | (VLEN / 8) * 1.75 | 4 330 | | __rvv_vint32mf4x8_t | vint32mf4x8_t | (VLEN / 8) * 2 | 4 331 | | __rvv_vuint32mf4x8_t | vuint32mf4x8_t | (VLEN / 8) * 2 | 4 332 | | __rvv_vfloat32mf4x8_t | vfloat32mf4x8_t | (VLEN / 8) * 2 | 4 333 | | __rvv_vint32mf2x2_t | vint32mf2x2_t | (VLEN / 8) | 4 334 | | __rvv_vuint32mf2x2_t | vuint32mf2x2_t | (VLEN / 8) | 4 335 | | __rvv_vfloat32mf2x2_t | vfloat32mf2x2_t | (VLEN / 8) | 4 336 | | __rvv_vint32mf2x3_t | vint32mf2x3_t | (VLEN / 8) * 1.5 | 4 337 | | __rvv_vuint32mf2x3_t | vuint32mf2x3_t | (VLEN / 8) * 1.5 | 4 338 | | __rvv_vfloat32mf2x3_t | vfloat32mf2x3_t | (VLEN / 8) * 1.5 | 4 339 | | __rvv_vint32mf2x4_t | vint32mf2x4_t | (VLEN / 8) * 2 | 4 340 | | __rvv_vuint32mf2x4_t | vuint32mf2x4_t | (VLEN / 8) * 2 | 4 341 | | __rvv_vfloat32mf2x4_t | vfloat32mf2x4_t | (VLEN / 8) * 2 | 4 342 | | __rvv_vint32mf2x5_t | vint32mf2x5_t | (VLEN / 8) * 2.5 | 4 343 | | __rvv_vuint32mf2x5_t | vuint32mf2x5_t | (VLEN / 8) * 2.5 | 4 344 | | __rvv_vfloat32mf2x5_t | vfloat32mf2x5_t | (VLEN / 8) * 2.5 | 4 345 | | __rvv_vint32mf2x6_t | vint32mf2x6_t | (VLEN / 8) * 3 | 4 346 | | __rvv_vuint32mf2x6_t | vuint32mf2x6_t | (VLEN / 8) * 3 | 4 347 | | __rvv_vfloat32mf2x6_t | vfloat32mf2x6_t | (VLEN / 8) * 3 | 4 348 | | __rvv_vint32mf2x7_t | vint32mf2x7_t | (VLEN / 8) * 3.5 | 4 349 | | __rvv_vuint32mf2x7_t | vuint32mf2x7_t | (VLEN / 8) * 3.5 | 4 350 | | __rvv_vfloat32mf2x7_t | vfloat32mf2x7_t | (VLEN / 8) * 3.5 | 4 351 | | __rvv_vint32mf2x8_t | vint32mf2x8_t | (VLEN / 8) * 4 | 4 352 | | __rvv_vuint32mf2x8_t | vuint32mf2x8_t | (VLEN / 8) * 4 | 4 353 | | __rvv_vfloat32mf2x8_t | vfloat32mf2x8_t | (VLEN / 8) * 4 | 4 354 | | __rvv_vint32m1x2_t | vint32m1x2_t | (VLEN / 8) * 2 | 4 355 | | __rvv_vuint32m1x2_t | vuint32m1x2_t | (VLEN / 8) * 2 | 4 356 | | __rvv_vfloat32m1x2_t | vfloat32m1x2_t | (VLEN / 8) * 2 | 4 357 | | __rvv_vint32m1x3_t | vint32m1x3_t | (VLEN / 8) * 3 | 4 358 | | __rvv_vuint32m1x3_t | vuint32m1x3_t | (VLEN / 8) * 3 | 4 359 | | __rvv_vfloat32m1x3_t | vfloat32m1x3_t | (VLEN / 8) * 3 | 4 360 | | __rvv_vint32m1x4_t | vint32m1x4_t | (VLEN / 8) * 4 | 4 361 | | __rvv_vuint32m1x4_t | vuint32m1x4_t | (VLEN / 8) * 4 | 4 362 | | __rvv_vfloat32m1x4_t | vfloat32m1x4_t | (VLEN / 8) * 4 | 4 363 | | __rvv_vint32m1x5_t | vint32m1x5_t | (VLEN / 8) * 5 | 4 364 | | __rvv_vuint32m1x5_t | vuint32m1x5_t | (VLEN / 8) * 5 | 4 365 | | __rvv_vfloat32m1x5_t | vfloat32m1x5_t | (VLEN / 8) * 5 | 4 366 | | __rvv_vint32m1x6_t | vint32m1x6_t | (VLEN / 8) * 6 | 4 367 | | __rvv_vuint32m1x6_t | vuint32m1x6_t | (VLEN / 8) * 6 | 4 368 | | __rvv_vfloat32m1x6_t | vfloat32m1x6_t | (VLEN / 8) * 6 | 4 369 | | __rvv_vint32m1x7_t | vint32m1x7_t | (VLEN / 8) * 7 | 4 370 | | __rvv_vuint32m1x7_t | vuint32m1x7_t | (VLEN / 8) * 7 | 4 371 | | __rvv_vfloat32m1x7_t | vfloat32m1x7_t | (VLEN / 8) * 7 | 4 372 | | __rvv_vint32m1x8_t | vint32m1x8_t | (VLEN / 8) * 8 | 4 373 | | __rvv_vuint32m1x8_t | vuint32m1x8_t | (VLEN / 8) * 8 | 4 374 | | __rvv_vfloat32m1x8_t | vfloat32m1x8_t | (VLEN / 8) * 8 | 4 375 | | __rvv_vint32m2x2_t | vint32m2x2_t | (VLEN / 8) * 4 | 4 376 | | __rvv_vuint32m2x2_t | vuint32m2x2_t | (VLEN / 8) * 4 | 4 377 | | __rvv_vfloat32m2x2_t | vfloat32m2x2_t | (VLEN / 8) * 4 | 4 378 | | __rvv_vint32m2x3_t | vint32m2x3_t | (VLEN / 8) * 6 | 4 379 | | __rvv_vuint32m2x3_t | vuint32m2x3_t | (VLEN / 8) * 6 | 4 380 | | __rvv_vfloat32m2x3_t | vfloat32m2x3_t | (VLEN / 8) * 6 | 4 381 | | __rvv_vint32m2x4_t | vint32m2x4_t | (VLEN / 8) * 8 | 4 382 | | __rvv_vuint32m2x4_t | vuint32m2x4_t | (VLEN / 8) * 8 | 4 383 | | __rvv_vfloat32m2x4_t | vfloat32m2x4_t | (VLEN / 8) * 8 | 4 384 | | __rvv_vint32m4x2_t | vint32m4x2_t | (VLEN / 8) * 8 | 4 385 | | __rvv_vuint32m4x2_t | vuint32m4x2_t | (VLEN / 8) * 8 | 4 386 | | __rvv_vfloat32m4x2_t | vfloat32m4x2_t | (VLEN / 8) * 8 | 4 387 | | __rvv_vint64mf8x2_t | vint64mf8x2_t | (VLEN / 8) / 4 | 8 388 | | __rvv_vuint64mf8x2_t | vuint64mf8x2_t | (VLEN / 8) / 4 | 8 389 | | __rvv_vfloat64mf8x2_t | vfloat64mf8x2_t | (VLEN / 8) / 4 | 8 390 | | __rvv_vint64mf8x3_t | vint64mf8x3_t | (VLEN / 8) * 0.375 | 8 391 | | __rvv_vuint64mf8x3_t | vuint64mf8x3_t | (VLEN / 8) * 0.375 | 8 392 | | __rvv_vfloat64mf8x3_t | vfloat64mf8x3_t | (VLEN / 8) * 0.375 | 8 393 | | __rvv_vint64mf8x4_t | vint64mf8x4_t | (VLEN / 8) / 2 | 8 394 | | __rvv_vuint64mf8x4_t | vuint64mf8x4_t | (VLEN / 8) / 2 | 8 395 | | __rvv_vfloat64mf8x4_t | vfloat64mf8x4_t | (VLEN / 8) / 2 | 8 396 | | __rvv_vint64mf8x5_t | vint64mf8x5_t | (VLEN / 8) * 0.625 | 8 397 | | __rvv_vuint64mf8x5_t | vuint64mf8x5_t | (VLEN / 8) * 0.625 | 8 398 | | __rvv_vfloat64mf8x5_t | vfloat64mf8x5_t | (VLEN / 8) * 0.625 | 8 399 | | __rvv_vint64mf8x6_t | vint64mf8x6_t | (VLEN / 8) * 0.75 | 8 400 | | __rvv_vuint64mf8x6_t | vuint64mf8x6_t | (VLEN / 8) * 0.75 | 8 401 | | __rvv_vfloat64mf8x6_t | vfloat64mf8x6_t | (VLEN / 8) * 0.75 | 8 402 | | __rvv_vint64mf8x7_t | vint64mf8x7_t | (VLEN / 8) * 0.875 | 8 403 | | __rvv_vuint64mf8x7_t | vuint64mf8x7_t | (VLEN / 8) * 0.875 | 8 404 | | __rvv_vfloat64mf8x7_t | vfloat64mf8x7_t | (VLEN / 8) * 0.875 | 8 405 | | __rvv_vint64mf8x8_t | vint64mf8x8_t | (VLEN / 8) | 8 406 | | __rvv_vuint64mf8x8_t | vuint64mf8x8_t | (VLEN / 8) | 8 407 | | __rvv_vfloat64mf8x8_t | vfloat64mf8x8_t | (VLEN / 8) | 8 408 | | __rvv_vint64mf4x2_t | vint64mf4x2_t | (VLEN / 8) / 2 | 8 409 | | __rvv_vuint64mf4x2_t | vuint64mf4x2_t | (VLEN / 8) / 2 | 8 410 | | __rvv_vfloat64mf4x2_t | vfloat64mf4x2_t | (VLEN / 8) / 2 | 8 411 | | __rvv_vint64mf4x3_t | vint64mf4x3_t | (VLEN / 8) * 0.75 | 8 412 | | __rvv_vuint64mf4x3_t | vuint64mf4x3_t | (VLEN / 8) * 0.75 | 8 413 | | __rvv_vfloat64mf4x3_t | vfloat64mf4x3_t | (VLEN / 8) * 0.75 | 8 414 | | __rvv_vint64mf4x4_t | vint64mf4x4_t | (VLEN / 8) | 8 415 | | __rvv_vuint64mf4x4_t | vuint64mf4x4_t | (VLEN / 8) | 8 416 | | __rvv_vfloat64mf4x4_t | vfloat64mf4x4_t | (VLEN / 8) | 8 417 | | __rvv_vint64mf4x5_t | vint64mf4x5_t | (VLEN / 8) * 1.25 | 8 418 | | __rvv_vuint64mf4x5_t | vuint64mf4x5_t | (VLEN / 8) * 1.25 | 8 419 | | __rvv_vfloat64mf4x5_t | vfloat64mf4x5_t | (VLEN / 8) * 1.25 | 8 420 | | __rvv_vint64mf4x6_t | vint64mf4x6_t | (VLEN / 8) * 1.5 | 8 421 | | __rvv_vuint64mf4x6_t | vuint64mf4x6_t | (VLEN / 8) * 1.5 | 8 422 | | __rvv_vfloat64mf4x6_t | vfloat64mf4x6_t | (VLEN / 8) * 1.5 | 8 423 | | __rvv_vint64mf4x7_t | vint64mf4x7_t | (VLEN / 8) * 1.75 | 8 424 | | __rvv_vuint64mf4x7_t | vuint64mf4x7_t | (VLEN / 8) * 1.75 | 8 425 | | __rvv_vfloat64mf4x7_t | vfloat64mf4x7_t | (VLEN / 8) * 1.75 | 8 426 | | __rvv_vint64mf4x8_t | vint64mf4x8_t | (VLEN / 8) * 2 | 8 427 | | __rvv_vuint64mf4x8_t | vuint64mf4x8_t | (VLEN / 8) * 2 | 8 428 | | __rvv_vfloat64mf4x8_t | vfloat64mf4x8_t | (VLEN / 8) * 2 | 8 429 | | __rvv_vint64mf2x2_t | vint64mf2x2_t | (VLEN / 8) | 8 430 | | __rvv_vuint64mf2x2_t | vuint64mf2x2_t | (VLEN / 8) | 8 431 | | __rvv_vfloat64mf2x2_t | vfloat64mf2x2_t | (VLEN / 8) | 8 432 | | __rvv_vint64mf2x3_t | vint64mf2x3_t | (VLEN / 8) * 1.5 | 8 433 | | __rvv_vuint64mf2x3_t | vuint64mf2x3_t | (VLEN / 8) * 1.5 | 8 434 | | __rvv_vfloat64mf2x3_t | vfloat64mf2x3_t | (VLEN / 8) * 1.5 | 8 435 | | __rvv_vint64mf2x4_t | vint64mf2x4_t | (VLEN / 8) * 2 | 8 436 | | __rvv_vuint64mf2x4_t | vuint64mf2x4_t | (VLEN / 8) * 2 | 8 437 | | __rvv_vfloat64mf2x4_t | vfloat64mf2x4_t | (VLEN / 8) * 2 | 8 438 | | __rvv_vint64mf2x5_t | vint64mf2x5_t | (VLEN / 8) * 2.5 | 8 439 | | __rvv_vuint64mf2x5_t | vuint64mf2x5_t | (VLEN / 8) * 2.5 | 8 440 | | __rvv_vfloat64mf2x5_t | vfloat64mf2x5_t | (VLEN / 8) * 2.5 | 8 441 | | __rvv_vint64mf2x6_t | vint64mf2x6_t | (VLEN / 8) * 3 | 8 442 | | __rvv_vuint64mf2x6_t | vuint64mf2x6_t | (VLEN / 8) * 3 | 8 443 | | __rvv_vfloat64mf2x6_t | vfloat64mf2x6_t | (VLEN / 8) * 3 | 8 444 | | __rvv_vint64mf2x7_t | vint64mf2x7_t | (VLEN / 8) * 3.5 | 8 445 | | __rvv_vuint64mf2x7_t | vuint64mf2x7_t | (VLEN / 8) * 3.5 | 8 446 | | __rvv_vfloat64mf2x7_t | vfloat64mf2x7_t | (VLEN / 8) * 3.5 | 8 447 | | __rvv_vint64mf2x8_t | vint64mf2x8_t | (VLEN / 8) * 4 | 8 448 | | __rvv_vuint64mf2x8_t | vuint64mf2x8_t | (VLEN / 8) * 4 | 8 449 | | __rvv_vfloat64mf2x8_t | vfloat64mf2x8_t | (VLEN / 8) * 4 | 8 450 | | __rvv_vint64m1x2_t | vint64m1x2_t | (VLEN / 8) * 2 | 8 451 | | __rvv_vuint64m1x2_t | vuint64m1x2_t | (VLEN / 8) * 2 | 8 452 | | __rvv_vfloat64m1x2_t | vfloat64m1x2_t | (VLEN / 8) * 2 | 8 453 | | __rvv_vint64m1x3_t | vint64m1x3_t | (VLEN / 8) * 3 | 8 454 | | __rvv_vuint64m1x3_t | vuint64m1x3_t | (VLEN / 8) * 3 | 8 455 | | __rvv_vfloat64m1x3_t | vfloat64m1x3_t | (VLEN / 8) * 3 | 8 456 | | __rvv_vint64m1x4_t | vint64m1x4_t | (VLEN / 8) * 4 | 8 457 | | __rvv_vuint64m1x4_t | vuint64m1x4_t | (VLEN / 8) * 4 | 8 458 | | __rvv_vfloat64m1x4_t | vfloat64m1x4_t | (VLEN / 8) * 4 | 8 459 | | __rvv_vint64m1x5_t | vint64m1x5_t | (VLEN / 8) * 5 | 8 460 | | __rvv_vuint64m1x5_t | vuint64m1x5_t | (VLEN / 8) * 5 | 8 461 | | __rvv_vfloat64m1x5_t | vfloat64m1x5_t | (VLEN / 8) * 5 | 8 462 | | __rvv_vint64m1x6_t | vint64m1x6_t | (VLEN / 8) * 6 | 8 463 | | __rvv_vuint64m1x6_t | vuint64m1x6_t | (VLEN / 8) * 6 | 8 464 | | __rvv_vfloat64m1x6_t | vfloat64m1x6_t | (VLEN / 8) * 6 | 8 465 | | __rvv_vint64m1x7_t | vint64m1x7_t | (VLEN / 8) * 7 | 8 466 | | __rvv_vuint64m1x7_t | vuint64m1x7_t | (VLEN / 8) * 7 | 8 467 | | __rvv_vfloat64m1x7_t | vfloat64m1x7_t | (VLEN / 8) * 7 | 8 468 | | __rvv_vint64m1x8_t | vint64m1x8_t | (VLEN / 8) * 8 | 8 469 | | __rvv_vuint64m1x8_t | vuint64m1x8_t | (VLEN / 8) * 8 | 8 470 | | __rvv_vfloat64m1x8_t | vfloat64m1x8_t | (VLEN / 8) * 8 | 8 471 | | __rvv_vint64m2x2_t | vint64m2x2_t | (VLEN / 8) * 4 | 8 472 | | __rvv_vuint64m2x2_t | vuint64m2x2_t | (VLEN / 8) * 4 | 8 473 | | __rvv_vfloat64m2x2_t | vfloat64m2x2_t | (VLEN / 8) * 4 | 8 474 | | __rvv_vint64m2x3_t | vint64m2x3_t | (VLEN / 8) * 6 | 8 475 | | __rvv_vuint64m2x3_t | vuint64m2x3_t | (VLEN / 8) * 6 | 8 476 | | __rvv_vfloat64m2x3_t | vfloat64m2x3_t | (VLEN / 8) * 6 | 8 477 | | __rvv_vint64m2x4_t | vint64m2x4_t | (VLEN / 8) * 8 | 8 478 | | __rvv_vuint64m2x4_t | vuint64m2x4_t | (VLEN / 8) * 8 | 8 479 | | __rvv_vfloat64m2x4_t | vfloat64m2x4_t | (VLEN / 8) * 8 | 8 480 | | __rvv_vint64m4x2_t | vint64m4x2_t | (VLEN / 8) * 8 | 8 481 | | __rvv_vuint64m4x2_t | vuint64m4x2_t | (VLEN / 8) * 8 | 8 482 | | __rvv_vfloat64m4x2_t | vfloat64m4x2_t | (VLEN / 8) * 8 | 8 483 | |=== 484 | --------------------------------------------------------------------------------