├── .github └── workflows │ ├── apt-packages.txt │ ├── brew-packages.txt │ ├── continuous-integration.yml │ └── debug-smoke.yml ├── .gitignore ├── ChangeLog.md ├── LICENSE ├── Makefile.in ├── README.md ├── VERSION ├── aclocal.m4 ├── arch_test_target └── spike │ ├── Makefile.include │ ├── README.md │ ├── device │ ├── Makefile_common.inc │ ├── rv32e_unratified │ │ ├── C │ │ │ └── Makefile.include │ │ ├── E │ │ │ └── Makefile.include │ │ └── M │ │ │ └── Makefile.include │ ├── rv32i_m │ │ ├── C │ │ │ └── Makefile.include │ │ ├── F │ │ │ └── Makefile.include │ │ ├── I │ │ │ └── Makefile.include │ │ ├── M │ │ │ └── Makefile.include │ │ ├── Zifencei │ │ │ └── Makefile.include │ │ └── privilege │ │ │ └── Makefile.include │ └── rv64i_m │ │ ├── C │ │ └── Makefile.include │ │ ├── D │ │ └── Makefile.include │ │ ├── I │ │ └── Makefile.include │ │ ├── M │ │ └── Makefile.include │ │ ├── Zifencei │ │ └── Makefile.include │ │ └── privilege │ │ └── Makefile.include │ ├── link.ld │ └── model_test.h ├── ci-tests ├── .gitignore ├── atomics.c ├── build-spike ├── custom-csr.cc ├── customcsr.c ├── dummy-slliuw.c ├── generate-snippy-test.sh ├── generate-snippy-tests.sh ├── hello.c ├── run-snippy-tests.sh ├── snippy-tests │ ├── atomic.yaml │ ├── basic.yaml │ ├── boot-code-f.s │ ├── boot-code-vf.s │ ├── boot-code.s │ ├── compressed.yaml │ ├── double-fp.yaml │ ├── linker-entry.ld │ ├── single-fp.yaml │ └── vector.yaml ├── test-customext.cc ├── test-spike └── testlib.cc ├── config.h.in ├── configure ├── configure.ac ├── customext ├── cflush.cc ├── customext.ac ├── customext.mk.in ├── dummy_rocc.cc └── dummy_rocc_test.c ├── debug_rom ├── .gitignore ├── Makefile ├── debug_rom.S ├── debug_rom.h └── link.ld ├── disasm ├── disasm.ac ├── disasm.cc ├── disasm.mk.in ├── isa_parser.cc └── regnames.cc ├── fdt ├── fdt.ac ├── fdt.c ├── fdt.h ├── fdt.mk.in ├── fdt_addresses.c ├── fdt_empty_tree.c ├── fdt_overlay.c ├── fdt_ro.c ├── fdt_rw.c ├── fdt_strerror.c ├── fdt_sw.c ├── fdt_wip.c ├── libfdt.h ├── libfdt_env.h └── libfdt_internal.h ├── fesvr ├── byteorder.h ├── context.cc ├── context.h ├── device.cc ├── device.h ├── dtm.cc ├── dtm.h ├── dummy.cc ├── elf.h ├── elf2hex.cc ├── elfloader.cc ├── elfloader.h ├── fesvr.ac ├── fesvr.mk.in ├── fesvr.pc.in ├── htif.cc ├── htif.h ├── htif_hexwriter.cc ├── htif_hexwriter.h ├── htif_pthread.cc ├── htif_pthread.h ├── memif.cc ├── memif.h ├── option_parser.cc ├── option_parser.h ├── rfb.cc ├── rfb.h ├── syscall.cc ├── syscall.h ├── term.cc ├── term.h ├── tsi.cc └── tsi.h ├── m4 ├── ax_append_flag.m4 ├── ax_append_link_flags.m4 ├── ax_boost_asio.m4 ├── ax_boost_base.m4 ├── ax_boost_regex.m4 ├── ax_check_compile_flag.m4 ├── ax_check_link_flag.m4 └── ax_require_defined.m4 ├── riscv-disasm.pc.in ├── riscv-fesvr.pc.in ├── riscv-riscv.pc.in ├── riscv ├── abstract_device.h ├── abstract_interrupt_controller.h ├── arith.h ├── bloom_filter.h ├── bulknormdot.h ├── cachesim.cc ├── cachesim.h ├── cfg.cc ├── cfg.h ├── check-opcode-overlap.t.cc ├── clint.cc ├── common.h ├── csr_init.cc ├── csrs.cc ├── csrs.h ├── debug_defines.h ├── debug_module.cc ├── debug_module.h ├── debug_rom_defines.h ├── decode.h ├── decode_macros.h ├── devices.cc ├── devices.h ├── disasm.h ├── dts.cc ├── dts.h ├── encoding.h ├── entropy_source.h ├── execute.cc ├── extension.cc ├── extension.h ├── extensions.cc ├── insn_macros.h ├── insn_template.cc ├── insn_template.h ├── insns │ ├── add.h │ ├── add_uw.h │ ├── addi.h │ ├── addiw.h │ ├── addw.h │ ├── aes32dsi.h │ ├── aes32dsmi.h │ ├── aes32esi.h │ ├── aes32esmi.h │ ├── aes64ds.h │ ├── aes64dsm.h │ ├── aes64es.h │ ├── aes64esm.h │ ├── aes64im.h │ ├── aes64ks1i.h │ ├── aes64ks2.h │ ├── aes_common.h │ ├── amoadd_b.h │ ├── amoadd_d.h │ ├── amoadd_h.h │ ├── amoadd_w.h │ ├── amoand_b.h │ ├── amoand_d.h │ ├── amoand_h.h │ ├── amoand_w.h │ ├── amocas_b.h │ ├── amocas_d.h │ ├── amocas_h.h │ ├── amocas_q.h │ ├── amocas_w.h │ ├── amomax_b.h │ ├── amomax_d.h │ ├── amomax_h.h │ ├── amomax_w.h │ ├── amomaxu_b.h │ ├── amomaxu_d.h │ ├── amomaxu_h.h │ ├── amomaxu_w.h │ ├── amomin_b.h │ ├── amomin_d.h │ ├── amomin_h.h │ ├── amomin_w.h │ ├── amominu_b.h │ ├── amominu_d.h │ ├── amominu_h.h │ ├── amominu_w.h │ ├── amoor_b.h │ ├── amoor_d.h │ ├── amoor_h.h │ ├── amoor_w.h │ ├── amoswap_b.h │ ├── amoswap_d.h │ ├── amoswap_h.h │ ├── amoswap_w.h │ ├── amoxor_b.h │ ├── amoxor_d.h │ ├── amoxor_h.h │ ├── amoxor_w.h │ ├── and.h │ ├── andi.h │ ├── andn.h │ ├── auipc.h │ ├── bclr.h │ ├── bclri.h │ ├── beq.h │ ├── beqi.h │ ├── bext.h │ ├── bexti.h │ ├── bge.h │ ├── bgeu.h │ ├── binv.h │ ├── binvi.h │ ├── blt.h │ ├── bltu.h │ ├── bne.h │ ├── bnei.h │ ├── bset.h │ ├── bseti.h │ ├── c_add.h │ ├── c_addi.h │ ├── c_addi4spn.h │ ├── c_addw.h │ ├── c_and.h │ ├── c_andi.h │ ├── c_beqz.h │ ├── c_bnez.h │ ├── c_ebreak.h │ ├── c_fld.h │ ├── c_fldsp.h │ ├── c_flw.h │ ├── c_flwsp.h │ ├── c_fsd.h │ ├── c_fsdsp.h │ ├── c_fsw.h │ ├── c_fswsp.h │ ├── c_j.h │ ├── c_jal.h │ ├── c_jalr.h │ ├── c_jr.h │ ├── c_lbu.h │ ├── c_ld.h │ ├── c_ldsp.h │ ├── c_lh.h │ ├── c_lhu.h │ ├── c_li.h │ ├── c_lui.h │ ├── c_lw.h │ ├── c_lwsp.h │ ├── c_mop_N.h │ ├── c_mul.h │ ├── c_mv.h │ ├── c_not.h │ ├── c_or.h │ ├── c_sb.h │ ├── c_sd.h │ ├── c_sdsp.h │ ├── c_sext_b.h │ ├── c_sext_h.h │ ├── c_sh.h │ ├── c_slli.h │ ├── c_srai.h │ ├── c_srli.h │ ├── c_sspopchk_x5.h │ ├── c_sspush_x1.h │ ├── c_sub.h │ ├── c_subw.h │ ├── c_sw.h │ ├── c_swsp.h │ ├── c_xor.h │ ├── c_zext_b.h │ ├── c_zext_h.h │ ├── c_zext_w.h │ ├── cbo_clean.h │ ├── cbo_flush.h │ ├── cbo_inval.h │ ├── cbo_zero.h │ ├── clmul.h │ ├── clmulh.h │ ├── clmulr.h │ ├── clz.h │ ├── clzw.h │ ├── cm_jalt.h │ ├── cm_mva01s.h │ ├── cm_mvsa01.h │ ├── cm_pop.h │ ├── cm_popret.h │ ├── cm_popretz.h │ ├── cm_push.h │ ├── cpop.h │ ├── cpopw.h │ ├── csrrc.h │ ├── csrrci.h │ ├── csrrs.h │ ├── csrrsi.h │ ├── csrrw.h │ ├── csrrwi.h │ ├── ctz.h │ ├── ctzw.h │ ├── czero_eqz.h │ ├── czero_nez.h │ ├── div.h │ ├── divu.h │ ├── divuw.h │ ├── divw.h │ ├── dret.h │ ├── ebreak.h │ ├── ecall.h │ ├── fadd_d.h │ ├── fadd_h.h │ ├── fadd_q.h │ ├── fadd_s.h │ ├── fclass_d.h │ ├── fclass_h.h │ ├── fclass_q.h │ ├── fclass_s.h │ ├── fcvt_bf16_s.h │ ├── fcvt_d_h.h │ ├── fcvt_d_l.h │ ├── fcvt_d_lu.h │ ├── fcvt_d_q.h │ ├── fcvt_d_s.h │ ├── fcvt_d_w.h │ ├── fcvt_d_wu.h │ ├── fcvt_h_d.h │ ├── fcvt_h_l.h │ ├── fcvt_h_lu.h │ ├── fcvt_h_q.h │ ├── fcvt_h_s.h │ ├── fcvt_h_w.h │ ├── fcvt_h_wu.h │ ├── fcvt_l_d.h │ ├── fcvt_l_h.h │ ├── fcvt_l_q.h │ ├── fcvt_l_s.h │ ├── fcvt_lu_d.h │ ├── fcvt_lu_h.h │ ├── fcvt_lu_q.h │ ├── fcvt_lu_s.h │ ├── fcvt_q_d.h │ ├── fcvt_q_h.h │ ├── fcvt_q_l.h │ ├── fcvt_q_lu.h │ ├── fcvt_q_s.h │ ├── fcvt_q_w.h │ ├── fcvt_q_wu.h │ ├── fcvt_s_bf16.h │ ├── fcvt_s_d.h │ ├── fcvt_s_h.h │ ├── fcvt_s_l.h │ ├── fcvt_s_lu.h │ ├── fcvt_s_q.h │ ├── fcvt_s_w.h │ ├── fcvt_s_wu.h │ ├── fcvt_w_d.h │ ├── fcvt_w_h.h │ ├── fcvt_w_q.h │ ├── fcvt_w_s.h │ ├── fcvt_wu_d.h │ ├── fcvt_wu_h.h │ ├── fcvt_wu_q.h │ ├── fcvt_wu_s.h │ ├── fcvtmod_w_d.h │ ├── fdiv_d.h │ ├── fdiv_h.h │ ├── fdiv_q.h │ ├── fdiv_s.h │ ├── fence.h │ ├── fence_i.h │ ├── feq_d.h │ ├── feq_h.h │ ├── feq_q.h │ ├── feq_s.h │ ├── fld.h │ ├── fle_d.h │ ├── fle_h.h │ ├── fle_q.h │ ├── fle_s.h │ ├── fleq_d.h │ ├── fleq_h.h │ ├── fleq_q.h │ ├── fleq_s.h │ ├── flh.h │ ├── fli_d.h │ ├── fli_h.h │ ├── fli_q.h │ ├── fli_s.h │ ├── flq.h │ ├── flt_d.h │ ├── flt_h.h │ ├── flt_q.h │ ├── flt_s.h │ ├── fltq_d.h │ ├── fltq_h.h │ ├── fltq_q.h │ ├── fltq_s.h │ ├── flw.h │ ├── fmadd_d.h │ ├── fmadd_h.h │ ├── fmadd_q.h │ ├── fmadd_s.h │ ├── fmax_d.h │ ├── fmax_h.h │ ├── fmax_q.h │ ├── fmax_s.h │ ├── fmaxm_d.h │ ├── fmaxm_h.h │ ├── fmaxm_q.h │ ├── fmaxm_s.h │ ├── fmin_d.h │ ├── fmin_h.h │ ├── fmin_q.h │ ├── fmin_s.h │ ├── fminm_d.h │ ├── fminm_h.h │ ├── fminm_q.h │ ├── fminm_s.h │ ├── fmsub_d.h │ ├── fmsub_h.h │ ├── fmsub_q.h │ ├── fmsub_s.h │ ├── fmul_d.h │ ├── fmul_h.h │ ├── fmul_q.h │ ├── fmul_s.h │ ├── fmv_d_x.h │ ├── fmv_h_x.h │ ├── fmv_w_x.h │ ├── fmv_x_d.h │ ├── fmv_x_h.h │ ├── fmv_x_w.h │ ├── fmvh_x_d.h │ ├── fmvh_x_q.h │ ├── fmvp_d_x.h │ ├── fmvp_q_x.h │ ├── fnmadd_d.h │ ├── fnmadd_h.h │ ├── fnmadd_q.h │ ├── fnmadd_s.h │ ├── fnmsub_d.h │ ├── fnmsub_h.h │ ├── fnmsub_q.h │ ├── fnmsub_s.h │ ├── fround_d.h │ ├── fround_h.h │ ├── fround_q.h │ ├── fround_s.h │ ├── froundnx_d.h │ ├── froundnx_h.h │ ├── froundnx_q.h │ ├── froundnx_s.h │ ├── fsd.h │ ├── fsgnj_d.h │ ├── fsgnj_h.h │ ├── fsgnj_q.h │ ├── fsgnj_s.h │ ├── fsgnjn_d.h │ ├── fsgnjn_h.h │ ├── fsgnjn_q.h │ ├── fsgnjn_s.h │ ├── fsgnjx_d.h │ ├── fsgnjx_h.h │ ├── fsgnjx_q.h │ ├── fsgnjx_s.h │ ├── fsh.h │ ├── fsq.h │ ├── fsqrt_d.h │ ├── fsqrt_h.h │ ├── fsqrt_q.h │ ├── fsqrt_s.h │ ├── fsub_d.h │ ├── fsub_h.h │ ├── fsub_q.h │ ├── fsub_s.h │ ├── fsw.h │ ├── gorci.h │ ├── grevi.h │ ├── hfence_gvma.h │ ├── hfence_vvma.h │ ├── hinval_gvma.h │ ├── hinval_vvma.h │ ├── hlv_b.h │ ├── hlv_bu.h │ ├── hlv_d.h │ ├── hlv_h.h │ ├── hlv_hu.h │ ├── hlv_w.h │ ├── hlv_wu.h │ ├── hlvx_hu.h │ ├── hlvx_wu.h │ ├── hsv_b.h │ ├── hsv_d.h │ ├── hsv_h.h │ ├── hsv_w.h │ ├── jal.h │ ├── jalr.h │ ├── lb.h │ ├── lb_aq.h │ ├── lbu.h │ ├── ld.h │ ├── ld_aq.h │ ├── lh.h │ ├── lh_aq.h │ ├── lhu.h │ ├── lpad.h │ ├── lr_d.h │ ├── lr_w.h │ ├── lui.h │ ├── lw.h │ ├── lw_aq.h │ ├── lwu.h │ ├── max.h │ ├── maxu.h │ ├── min.h │ ├── minu.h │ ├── mnret.h │ ├── mop_r_N.h │ ├── mop_rr_N.h │ ├── mret.h │ ├── mul.h │ ├── mulh.h │ ├── mulhsu.h │ ├── mulhu.h │ ├── mulw.h │ ├── or.h │ ├── ori.h │ ├── orn.h │ ├── pack.h │ ├── packh.h │ ├── packw.h │ ├── rem.h │ ├── remu.h │ ├── remuw.h │ ├── remw.h │ ├── rol.h │ ├── rolw.h │ ├── ror.h │ ├── rori.h │ ├── roriw.h │ ├── rorw.h │ ├── sb.h │ ├── sb_rl.h │ ├── sc_d.h │ ├── sc_w.h │ ├── sd.h │ ├── sd_rl.h │ ├── sext_b.h │ ├── sext_h.h │ ├── sfence_inval_ir.h │ ├── sfence_vma.h │ ├── sfence_w_inval.h │ ├── sh.h │ ├── sh1add.h │ ├── sh1add_uw.h │ ├── sh2add.h │ ├── sh2add_uw.h │ ├── sh3add.h │ ├── sh3add_uw.h │ ├── sh_rl.h │ ├── sha256sig0.h │ ├── sha256sig1.h │ ├── sha256sum0.h │ ├── sha256sum1.h │ ├── sha512sig0.h │ ├── sha512sig0h.h │ ├── sha512sig0l.h │ ├── sha512sig1.h │ ├── sha512sig1h.h │ ├── sha512sig1l.h │ ├── sha512sum0.h │ ├── sha512sum0r.h │ ├── sha512sum1.h │ ├── sha512sum1r.h │ ├── shfli.h │ ├── sinval_vma.h │ ├── sll.h │ ├── slli.h │ ├── slli_uw.h │ ├── slliw.h │ ├── sllw.h │ ├── slt.h │ ├── slti.h │ ├── sltiu.h │ ├── sltu.h │ ├── sm3p0.h │ ├── sm3p1.h │ ├── sm4_common.h │ ├── sm4ed.h │ ├── sm4ks.h │ ├── sra.h │ ├── srai.h │ ├── sraiw.h │ ├── sraw.h │ ├── sret.h │ ├── srl.h │ ├── srli.h │ ├── srliw.h │ ├── srlw.h │ ├── ssamoswap_d.h │ ├── ssamoswap_w.h │ ├── sspopchk_x1.h │ ├── sspopchk_x5.h │ ├── sspush_x1.h │ ├── sspush_x5.h │ ├── ssrdp.h │ ├── sub.h │ ├── subw.h │ ├── sw.h │ ├── sw_rl.h │ ├── unshfli.h │ ├── vaadd_vv.h │ ├── vaadd_vx.h │ ├── vaaddu_vv.h │ ├── vaaddu_vx.h │ ├── vadc_vim.h │ ├── vadc_vvm.h │ ├── vadc_vxm.h │ ├── vadd_vi.h │ ├── vadd_vv.h │ ├── vadd_vx.h │ ├── vaesdf_vs.h │ ├── vaesdf_vv.h │ ├── vaesdm_vs.h │ ├── vaesdm_vv.h │ ├── vaesef_vs.h │ ├── vaesef_vv.h │ ├── vaesem_vs.h │ ├── vaesem_vv.h │ ├── vaeskf1_vi.h │ ├── vaeskf2_vi.h │ ├── vaesz_vs.h │ ├── vand_vi.h │ ├── vand_vv.h │ ├── vand_vx.h │ ├── vandn_vv.h │ ├── vandn_vx.h │ ├── vasub_vv.h │ ├── vasub_vx.h │ ├── vasubu_vv.h │ ├── vasubu_vx.h │ ├── vbrev8_v.h │ ├── vbrev_v.h │ ├── vclmul_vv.h │ ├── vclmul_vx.h │ ├── vclmulh_vv.h │ ├── vclmulh_vx.h │ ├── vclz_v.h │ ├── vcompress_vm.h │ ├── vcpop_m.h │ ├── vcpop_v.h │ ├── vctz_v.h │ ├── vdiv_vv.h │ ├── vdiv_vx.h │ ├── vdivu_vv.h │ ├── vdivu_vx.h │ ├── vfadd_vf.h │ ├── vfadd_vv.h │ ├── vfbdot_vv.h │ ├── vfclass_v.h │ ├── vfcvt_f_x_v.h │ ├── vfcvt_f_xu_v.h │ ├── vfcvt_rtz_x_f_v.h │ ├── vfcvt_rtz_xu_f_v.h │ ├── vfcvt_x_f_v.h │ ├── vfcvt_xu_f_v.h │ ├── vfdiv_vf.h │ ├── vfdiv_vv.h │ ├── vfext_vf2.h │ ├── vfirst_m.h │ ├── vfmacc_vf.h │ ├── vfmacc_vv.h │ ├── vfmadd_vf.h │ ├── vfmadd_vv.h │ ├── vfmax_vf.h │ ├── vfmax_vv.h │ ├── vfmerge_vfm.h │ ├── vfmin_vf.h │ ├── vfmin_vv.h │ ├── vfmsac_vf.h │ ├── vfmsac_vv.h │ ├── vfmsub_vf.h │ ├── vfmsub_vv.h │ ├── vfmul_vf.h │ ├── vfmul_vv.h │ ├── vfmv_f_s.h │ ├── vfmv_s_f.h │ ├── vfmv_v_f.h │ ├── vfncvt_f_f_q.h │ ├── vfncvt_f_f_w.h │ ├── vfncvt_f_x_w.h │ ├── vfncvt_f_xu_w.h │ ├── vfncvt_rod_f_f_w.h │ ├── vfncvt_rtz_x_f_w.h │ ├── vfncvt_rtz_xu_f_w.h │ ├── vfncvt_sat_f_f_q.h │ ├── vfncvt_x_f_w.h │ ├── vfncvt_xu_f_w.h │ ├── vfncvtbf16_f_f_w.h │ ├── vfncvtbf16_sat_f_f_w.h │ ├── vfnmacc_vf.h │ ├── vfnmacc_vv.h │ ├── vfnmadd_vf.h │ ├── vfnmadd_vv.h │ ├── vfnmsac_vf.h │ ├── vfnmsac_vv.h │ ├── vfnmsub_vf.h │ ├── vfnmsub_vv.h │ ├── vfqbdot_alt_vv.h │ ├── vfqbdot_vv.h │ ├── vfqldot_alt_vv.h │ ├── vfqldot_vv.h │ ├── vfrdiv_vf.h │ ├── vfrec7_v.h │ ├── vfredmax_vs.h │ ├── vfredmin_vs.h │ ├── vfredosum_vs.h │ ├── vfredusum_vs.h │ ├── vfrsqrt7_v.h │ ├── vfrsub_vf.h │ ├── vfsgnj_vf.h │ ├── vfsgnj_vv.h │ ├── vfsgnjn_vf.h │ ├── vfsgnjn_vv.h │ ├── vfsgnjx_vf.h │ ├── vfsgnjx_vv.h │ ├── vfslide1down_vf.h │ ├── vfslide1up_vf.h │ ├── vfsqrt_v.h │ ├── vfsub_vf.h │ ├── vfsub_vv.h │ ├── vfwadd_vf.h │ ├── vfwadd_vv.h │ ├── vfwadd_wf.h │ ├── vfwadd_wv.h │ ├── vfwbdot_vv.h │ ├── vfwcvt_f_f_v.h │ ├── vfwcvt_f_x_v.h │ ├── vfwcvt_f_xu_v.h │ ├── vfwcvt_rtz_x_f_v.h │ ├── vfwcvt_rtz_xu_f_v.h │ ├── vfwcvt_x_f_v.h │ ├── vfwcvt_xu_f_v.h │ ├── vfwcvtbf16_f_f_v.h │ ├── vfwldot_vv.h │ ├── vfwmacc_vf.h │ ├── vfwmacc_vv.h │ ├── vfwmaccbf16_vf.h │ ├── vfwmaccbf16_vv.h │ ├── vfwmsac_vf.h │ ├── vfwmsac_vv.h │ ├── vfwmul_vf.h │ ├── vfwmul_vv.h │ ├── vfwnmacc_vf.h │ ├── vfwnmacc_vv.h │ ├── vfwnmsac_vf.h │ ├── vfwnmsac_vv.h │ ├── vfwredosum_vs.h │ ├── vfwredusum_vs.h │ ├── vfwsub_vf.h │ ├── vfwsub_vv.h │ ├── vfwsub_wf.h │ ├── vfwsub_wv.h │ ├── vghsh_vv.h │ ├── vgmul_vv.h │ ├── vid_v.h │ ├── viota_m.h │ ├── vl1re16_v.h │ ├── vl1re32_v.h │ ├── vl1re64_v.h │ ├── vl1re8_v.h │ ├── vl2re16_v.h │ ├── vl2re32_v.h │ ├── vl2re64_v.h │ ├── vl2re8_v.h │ ├── vl4re16_v.h │ ├── vl4re32_v.h │ ├── vl4re64_v.h │ ├── vl4re8_v.h │ ├── vl8re16_v.h │ ├── vl8re32_v.h │ ├── vl8re64_v.h │ ├── vl8re8_v.h │ ├── vle16_v.h │ ├── vle16ff_v.h │ ├── vle32_v.h │ ├── vle32ff_v.h │ ├── vle64_v.h │ ├── vle64ff_v.h │ ├── vle8_v.h │ ├── vle8ff_v.h │ ├── vlm_v.h │ ├── vloxei16_v.h │ ├── vloxei32_v.h │ ├── vloxei64_v.h │ ├── vloxei8_v.h │ ├── vlse16_v.h │ ├── vlse32_v.h │ ├── vlse64_v.h │ ├── vlse8_v.h │ ├── vluxei16_v.h │ ├── vluxei32_v.h │ ├── vluxei64_v.h │ ├── vluxei8_v.h │ ├── vmacc_vv.h │ ├── vmacc_vx.h │ ├── vmadc_vi.h │ ├── vmadc_vim.h │ ├── vmadc_vv.h │ ├── vmadc_vvm.h │ ├── vmadc_vx.h │ ├── vmadc_vxm.h │ ├── vmadd_vv.h │ ├── vmadd_vx.h │ ├── vmand_mm.h │ ├── vmandn_mm.h │ ├── vmax_vv.h │ ├── vmax_vx.h │ ├── vmaxu_vv.h │ ├── vmaxu_vx.h │ ├── vmerge_vim.h │ ├── vmerge_vvm.h │ ├── vmerge_vxm.h │ ├── vmfeq_vf.h │ ├── vmfeq_vv.h │ ├── vmfge_vf.h │ ├── vmfgt_vf.h │ ├── vmfle_vf.h │ ├── vmfle_vv.h │ ├── vmflt_vf.h │ ├── vmflt_vv.h │ ├── vmfne_vf.h │ ├── vmfne_vv.h │ ├── vmin_vv.h │ ├── vmin_vx.h │ ├── vminu_vv.h │ ├── vminu_vx.h │ ├── vmnand_mm.h │ ├── vmnor_mm.h │ ├── vmor_mm.h │ ├── vmorn_mm.h │ ├── vmsbc_vv.h │ ├── vmsbc_vvm.h │ ├── vmsbc_vx.h │ ├── vmsbc_vxm.h │ ├── vmsbf_m.h │ ├── vmseq_vi.h │ ├── vmseq_vv.h │ ├── vmseq_vx.h │ ├── vmsgt_vi.h │ ├── vmsgt_vx.h │ ├── vmsgtu_vi.h │ ├── vmsgtu_vx.h │ ├── vmsif_m.h │ ├── vmsle_vi.h │ ├── vmsle_vv.h │ ├── vmsle_vx.h │ ├── vmsleu_vi.h │ ├── vmsleu_vv.h │ ├── vmsleu_vx.h │ ├── vmslt_vv.h │ ├── vmslt_vx.h │ ├── vmsltu_vv.h │ ├── vmsltu_vx.h │ ├── vmsne_vi.h │ ├── vmsne_vv.h │ ├── vmsne_vx.h │ ├── vmsof_m.h │ ├── vmul_vv.h │ ├── vmul_vx.h │ ├── vmulh_vv.h │ ├── vmulh_vx.h │ ├── vmulhsu_vv.h │ ├── vmulhsu_vx.h │ ├── vmulhu_vv.h │ ├── vmulhu_vx.h │ ├── vmv1r_v.h │ ├── vmv2r_v.h │ ├── vmv4r_v.h │ ├── vmv8r_v.h │ ├── vmv_s_x.h │ ├── vmv_v_i.h │ ├── vmv_v_v.h │ ├── vmv_v_x.h │ ├── vmv_x_s.h │ ├── vmvnfr_v.h │ ├── vmxnor_mm.h │ ├── vmxor_mm.h │ ├── vnclip_wi.h │ ├── vnclip_wv.h │ ├── vnclip_wx.h │ ├── vnclipu_wi.h │ ├── vnclipu_wv.h │ ├── vnclipu_wx.h │ ├── vnmsac_vv.h │ ├── vnmsac_vx.h │ ├── vnmsub_vv.h │ ├── vnmsub_vx.h │ ├── vnsra_wi.h │ ├── vnsra_wv.h │ ├── vnsra_wx.h │ ├── vnsrl_wi.h │ ├── vnsrl_wv.h │ ├── vnsrl_wx.h │ ├── vor_vi.h │ ├── vor_vv.h │ ├── vor_vx.h │ ├── vqbdots_vv.h │ ├── vqbdotu_vv.h │ ├── vqdot_common.h │ ├── vqdot_vv.h │ ├── vqdot_vx.h │ ├── vqdotsu_vv.h │ ├── vqdotsu_vx.h │ ├── vqdotu_vv.h │ ├── vqdotu_vx.h │ ├── vqdotus_vx.h │ ├── vqldots_vv.h │ ├── vqldotu_vv.h │ ├── vredand_vs.h │ ├── vredmax_vs.h │ ├── vredmaxu_vs.h │ ├── vredmin_vs.h │ ├── vredminu_vs.h │ ├── vredor_vs.h │ ├── vredsum_vs.h │ ├── vredxor_vs.h │ ├── vrem_vv.h │ ├── vrem_vx.h │ ├── vremu_vv.h │ ├── vremu_vx.h │ ├── vrev8_v.h │ ├── vrgather_vi.h │ ├── vrgather_vv.h │ ├── vrgather_vx.h │ ├── vrgatherei16_vv.h │ ├── vrol_vv.h │ ├── vrol_vx.h │ ├── vror_vi.h │ ├── vror_vv.h │ ├── vror_vx.h │ ├── vrsub_vi.h │ ├── vrsub_vx.h │ ├── vs1r_v.h │ ├── vs2r_v.h │ ├── vs4r_v.h │ ├── vs8r_v.h │ ├── vsadd_vi.h │ ├── vsadd_vv.h │ ├── vsadd_vx.h │ ├── vsaddu_vi.h │ ├── vsaddu_vv.h │ ├── vsaddu_vx.h │ ├── vsbc_vvm.h │ ├── vsbc_vxm.h │ ├── vse16_v.h │ ├── vse32_v.h │ ├── vse64_v.h │ ├── vse8_v.h │ ├── vsetivli.h │ ├── vsetvl.h │ ├── vsetvli.h │ ├── vsext_vf2.h │ ├── vsext_vf4.h │ ├── vsext_vf8.h │ ├── vsha2ch_vv.h │ ├── vsha2cl_vv.h │ ├── vsha2ms_vv.h │ ├── vslide1down_vx.h │ ├── vslide1up_vx.h │ ├── vslidedown_vi.h │ ├── vslidedown_vx.h │ ├── vslideup_vi.h │ ├── vslideup_vx.h │ ├── vsll_vi.h │ ├── vsll_vv.h │ ├── vsll_vx.h │ ├── vsm3c_vi.h │ ├── vsm3me_vv.h │ ├── vsm4k_vi.h │ ├── vsm4r_vs.h │ ├── vsm4r_vv.h │ ├── vsm_v.h │ ├── vsmul_vv.h │ ├── vsmul_vx.h │ ├── vsoxei16_v.h │ ├── vsoxei32_v.h │ ├── vsoxei64_v.h │ ├── vsoxei8_v.h │ ├── vsra_vi.h │ ├── vsra_vv.h │ ├── vsra_vx.h │ ├── vsrl_vi.h │ ├── vsrl_vv.h │ ├── vsrl_vx.h │ ├── vsse16_v.h │ ├── vsse32_v.h │ ├── vsse64_v.h │ ├── vsse8_v.h │ ├── vssra_vi.h │ ├── vssra_vv.h │ ├── vssra_vx.h │ ├── vssrl_vi.h │ ├── vssrl_vv.h │ ├── vssrl_vx.h │ ├── vssub_vv.h │ ├── vssub_vx.h │ ├── vssubu_vv.h │ ├── vssubu_vx.h │ ├── vsub_vv.h │ ├── vsub_vx.h │ ├── vsuxei16_v.h │ ├── vsuxei32_v.h │ ├── vsuxei64_v.h │ ├── vsuxei8_v.h │ ├── vwadd_vv.h │ ├── vwadd_vx.h │ ├── vwadd_wv.h │ ├── vwadd_wx.h │ ├── vwaddu_vv.h │ ├── vwaddu_vx.h │ ├── vwaddu_wv.h │ ├── vwaddu_wx.h │ ├── vwmacc_vv.h │ ├── vwmacc_vx.h │ ├── vwmaccsu_vv.h │ ├── vwmaccsu_vx.h │ ├── vwmaccu_vv.h │ ├── vwmaccu_vx.h │ ├── vwmaccus_vx.h │ ├── vwmul_vv.h │ ├── vwmul_vx.h │ ├── vwmulsu_vv.h │ ├── vwmulsu_vx.h │ ├── vwmulu_vv.h │ ├── vwmulu_vx.h │ ├── vwredsum_vs.h │ ├── vwredsumu_vs.h │ ├── vwsll_vi.h │ ├── vwsll_vv.h │ ├── vwsll_vx.h │ ├── vwsub_vv.h │ ├── vwsub_vx.h │ ├── vwsub_wv.h │ ├── vwsub_wx.h │ ├── vwsubu_vv.h │ ├── vwsubu_vx.h │ ├── vwsubu_wv.h │ ├── vwsubu_wx.h │ ├── vxor_vi.h │ ├── vxor_vv.h │ ├── vxor_vx.h │ ├── vzext_vf2.h │ ├── vzext_vf4.h │ ├── vzext_vf8.h │ ├── wfi.h │ ├── wrs_nto.h │ ├── wrs_sto.h │ ├── xnor.h │ ├── xor.h │ ├── xori.h │ ├── xperm4.h │ └── xperm8.h ├── interactive.cc ├── isa_parser.h ├── jtag_dtm.cc ├── jtag_dtm.h ├── log_file.h ├── memtracer.h ├── mmu.cc ├── mmu.h ├── ns16550.cc ├── opcodes.h ├── overlap_list.h ├── platform.h ├── plic.cc ├── processor.cc ├── processor.h ├── remote_bitbang.cc ├── remote_bitbang.h ├── riscv.ac ├── riscv.mk.in ├── rocc.cc ├── rocc.h ├── rom.cc ├── sim.cc ├── sim.h ├── simif.h ├── socketif.cc ├── socketif.h ├── tracer.h ├── trap.h ├── triggers.cc ├── triggers.h ├── v_ext_macros.h ├── vector_unit.cc ├── vector_unit.h ├── zicfiss.h ├── zvbdot.h ├── zvk_ext_macros.h ├── zvkned_ext_macros.h ├── zvknh_ext_macros.h ├── zvksed_ext_macros.h └── zvksh_ext_macros.h ├── scripts ├── config.guess ├── config.sub ├── install-sh ├── mk-install-dirs.sh └── vcs-version.sh ├── softfloat ├── bf16_add.c ├── bf16_classify.c ├── bf16_cmp.c ├── bf16_div.c ├── bf16_mul.c ├── bf16_mulAdd.c ├── bf16_sqrt.c ├── bf16_sub.c ├── bf16_to_e4m3.c ├── bf16_to_e5m2.c ├── bf16_to_f32.c ├── bf16_to_f64.c ├── bf16_to_i32.c ├── bf16_to_i8.c ├── bf16_to_ui32.c ├── bf16_to_ui8.c ├── e4m3_to_bf16.c ├── e4m3_to_f16.c ├── e5m2_to_bf16.c ├── e5m2_to_f16.c ├── f128_add.c ├── f128_classify.c ├── f128_div.c ├── f128_eq.c ├── f128_eq_signaling.c ├── f128_isSignalingNaN.c ├── f128_le.c ├── f128_le_quiet.c ├── f128_lt.c ├── f128_lt_quiet.c ├── f128_mul.c ├── f128_mulAdd.c ├── f128_rem.c ├── f128_roundToInt.c ├── f128_sqrt.c ├── f128_sub.c ├── f128_to_f16.c ├── f128_to_f32.c ├── f128_to_f64.c ├── f128_to_i32.c ├── f128_to_i32_r_minMag.c ├── f128_to_i64.c ├── f128_to_i64_r_minMag.c ├── f128_to_ui32.c ├── f128_to_ui32_r_minMag.c ├── f128_to_ui64.c ├── f128_to_ui64_r_minMag.c ├── f16_add.c ├── f16_classify.c ├── f16_div.c ├── f16_eq.c ├── f16_eq_signaling.c ├── f16_isSignalingNaN.c ├── f16_le.c ├── f16_le_quiet.c ├── f16_lt.c ├── f16_lt_quiet.c ├── f16_mul.c ├── f16_mulAdd.c ├── f16_rem.c ├── f16_roundToInt.c ├── f16_sqrt.c ├── f16_sub.c ├── f16_to_e4m3.c ├── f16_to_e5m2.c ├── f16_to_f128.c ├── f16_to_f32.c ├── f16_to_f64.c ├── f16_to_i16.c ├── f16_to_i32.c ├── f16_to_i32_r_minMag.c ├── f16_to_i64.c ├── f16_to_i64_r_minMag.c ├── f16_to_i8.c ├── f16_to_ui16.c ├── f16_to_ui32.c ├── f16_to_ui32_r_minMag.c ├── f16_to_ui64.c ├── f16_to_ui64_r_minMag.c ├── f16_to_ui8.c ├── f32_add.c ├── f32_classify.c ├── f32_div.c ├── f32_eq.c ├── f32_eq_signaling.c ├── f32_isSignalingNaN.c ├── f32_le.c ├── f32_le_quiet.c ├── f32_lt.c ├── f32_lt_quiet.c ├── f32_mul.c ├── f32_mulAdd.c ├── f32_rem.c ├── f32_roundToInt.c ├── f32_sqrt.c ├── f32_sub.c ├── f32_to_bf16.c ├── f32_to_e4m3.c ├── f32_to_e5m2.c ├── f32_to_f128.c ├── f32_to_f16.c ├── f32_to_f64.c ├── f32_to_i16.c ├── f32_to_i32.c ├── f32_to_i32_r_minMag.c ├── f32_to_i64.c ├── f32_to_i64_r_minMag.c ├── f32_to_i8.c ├── f32_to_ui16.c ├── f32_to_ui32.c ├── f32_to_ui32_r_minMag.c ├── f32_to_ui64.c ├── f32_to_ui64_r_minMag.c ├── f32_to_ui8.c ├── f64_add.c ├── f64_classify.c ├── f64_div.c ├── f64_eq.c ├── f64_eq_signaling.c ├── f64_isSignalingNaN.c ├── f64_le.c ├── f64_le_quiet.c ├── f64_lt.c ├── f64_lt_quiet.c ├── f64_mul.c ├── f64_mulAdd.c ├── f64_rem.c ├── f64_roundToInt.c ├── f64_sqrt.c ├── f64_sub.c ├── f64_to_bf16.c ├── f64_to_f128.c ├── f64_to_f16.c ├── f64_to_f32.c ├── f64_to_i32.c ├── f64_to_i32_r_minMag.c ├── f64_to_i64.c ├── f64_to_i64_r_minMag.c ├── f64_to_ui32.c ├── f64_to_ui32_r_minMag.c ├── f64_to_ui64.c ├── f64_to_ui64_r_minMag.c ├── fall_maxmin.c ├── fall_reciprocal.c ├── fall_sign.c ├── i32_to_bf16.c ├── i32_to_f128.c ├── i32_to_f16.c ├── i32_to_f32.c ├── i32_to_f64.c ├── i64_to_f128.c ├── i64_to_f16.c ├── i64_to_f32.c ├── i64_to_f64.c ├── internals.h ├── platform.h ├── primitiveTypes.h ├── primitives.h ├── s_add128.c ├── s_add256M.c ├── s_addCarryM.c ├── s_addComplCarryM.c ├── s_addM.c ├── s_addMagsF128.c ├── s_addMagsF16.c ├── s_addMagsF32.c ├── s_addMagsF64.c ├── s_approxRecip32_1.c ├── s_approxRecipSqrt32_1.c ├── s_approxRecipSqrt_1Ks.c ├── s_approxRecip_1Ks.c ├── s_commonNaNToF128UI.c ├── s_commonNaNToF16UI.c ├── s_commonNaNToF32UI.c ├── s_commonNaNToF64UI.c ├── s_compare128M.c ├── s_compare96M.c ├── s_countLeadingZeros16.c ├── s_countLeadingZeros32.c ├── s_countLeadingZeros64.c ├── s_countLeadingZeros8.c ├── s_eq128.c ├── s_f128UIToCommonNaN.c ├── s_f16UIToCommonNaN.c ├── s_f32UIToCommonNaN.c ├── s_f64UIToCommonNaN.c ├── s_le128.c ├── s_lt128.c ├── s_mul128By32.c ├── s_mul128MTo256M.c ├── s_mul128To256M.c ├── s_mul64ByShifted32To128.c ├── s_mul64To128.c ├── s_mul64To128M.c ├── s_mulAddF128.c ├── s_mulAddF16.c ├── s_mulAddF32.c ├── s_mulAddF64.c ├── s_negXM.c ├── s_normRoundPackToF128.c ├── s_normRoundPackToF16.c ├── s_normRoundPackToF32.c ├── s_normRoundPackToF64.c ├── s_normSubnormalE4M3Sig.c ├── s_normSubnormalE5M2Sig.c ├── s_normSubnormalF128Sig.c ├── s_normSubnormalF16Sig.c ├── s_normSubnormalF32Sig.c ├── s_normSubnormalF64Sig.c ├── s_propagateNaNF128UI.c ├── s_propagateNaNF16UI.c ├── s_propagateNaNF32UI.c ├── s_propagateNaNF64UI.c ├── s_remStepMBy32.c ├── s_roundMToI64.c ├── s_roundMToUI64.c ├── s_roundPackMToI64.c ├── s_roundPackMToUI64.c ├── s_roundPackToBF16.c ├── s_roundPackToE4M3.c ├── s_roundPackToE5M2.c ├── s_roundPackToF128.c ├── s_roundPackToF16.c ├── s_roundPackToF32.c ├── s_roundPackToF64.c ├── s_roundPackToI32.c ├── s_roundPackToI64.c ├── s_roundPackToUI32.c ├── s_roundPackToUI64.c ├── s_roundToI32.c ├── s_roundToI64.c ├── s_roundToUI32.c ├── s_roundToUI64.c ├── s_shiftRightJam128.c ├── s_shiftRightJam128Extra.c ├── s_shiftRightJam256M.c ├── s_shiftRightJam32.c ├── s_shiftRightJam64.c ├── s_shiftRightJam64Extra.c ├── s_shortShiftLeft128.c ├── s_shortShiftLeft64To96M.c ├── s_shortShiftRight128.c ├── s_shortShiftRightExtendM.c ├── s_shortShiftRightJam128.c ├── s_shortShiftRightJam128Extra.c ├── s_shortShiftRightJam64.c ├── s_shortShiftRightJam64Extra.c ├── s_shortShiftRightM.c ├── s_sub128.c ├── s_sub1XM.c ├── s_sub256M.c ├── s_subM.c ├── s_subMagsF128.c ├── s_subMagsF16.c ├── s_subMagsF32.c ├── s_subMagsF64.c ├── softfloat.ac ├── softfloat.h ├── softfloat.mk.in ├── softfloat_raiseFlags.c ├── softfloat_state.c ├── softfloat_types.h ├── specialize.h ├── ui32_to_bf16.c ├── ui32_to_f128.c ├── ui32_to_f16.c ├── ui32_to_f32.c ├── ui32_to_f64.c ├── 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WRITE_RD(MMU.load_reserved(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/lui.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.u_imm()); 2 | -------------------------------------------------------------------------------- /riscv/insns/lw.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lw_aq.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | WRITE_RD(MMU.load(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/lwu.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 3 | 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-------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srlw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/sspopchk_x5.h: -------------------------------------------------------------------------------- 1 | #include "sspopchk_x1.h" 2 | -------------------------------------------------------------------------------- /riscv/insns/sspush_x5.h: -------------------------------------------------------------------------------- 1 | #include "sspush_x1.h" 2 | -------------------------------------------------------------------------------- /riscv/insns/ssrdp.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/ssrdp.h -------------------------------------------------------------------------------- /riscv/insns/sub.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 - RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/subw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 - RS2)); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/sw.h: -------------------------------------------------------------------------------- 1 | MMU.store(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/sw_rl.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | MMU.store(RS1, RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/unshfli.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/unshfli.h -------------------------------------------------------------------------------- /riscv/insns/vaadd_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vaadd_vv.h -------------------------------------------------------------------------------- /riscv/insns/vaadd_vx.h: -------------------------------------------------------------------------------- 1 | // vaadd.vx vd, vs2, rs1 2 | VI_VX_LOOP_AVG(+); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaaddu_vx.h: -------------------------------------------------------------------------------- 1 | // vaaddu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_AVG(+); 3 | -------------------------------------------------------------------------------- /riscv/insns/vadc_vim.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vadc_vim.h -------------------------------------------------------------------------------- /riscv/insns/vadc_vvm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vadc_vvm.h -------------------------------------------------------------------------------- /riscv/insns/vadc_vxm.h: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /riscv/insns/vaesz_vs.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vaesz_vs.h -------------------------------------------------------------------------------- /riscv/insns/vand_vi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vand_vi.h -------------------------------------------------------------------------------- /riscv/insns/vand_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vand_vv.h -------------------------------------------------------------------------------- /riscv/insns/vand_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vand_vx.h -------------------------------------------------------------------------------- /riscv/insns/vandn_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vandn_vv.h -------------------------------------------------------------------------------- /riscv/insns/vandn_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vandn_vx.h -------------------------------------------------------------------------------- /riscv/insns/vasub_vv.h: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /riscv/insns/vdivu_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vdivu_vv.h -------------------------------------------------------------------------------- /riscv/insns/vdivu_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vdivu_vx.h -------------------------------------------------------------------------------- /riscv/insns/vfadd_vf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfadd_vf.h -------------------------------------------------------------------------------- /riscv/insns/vfadd_vv.h: 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-------------------------------------------------------------------------------- /riscv/insns/vfmin_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfmin_vv.h -------------------------------------------------------------------------------- /riscv/insns/vfmul_vf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfmul_vf.h -------------------------------------------------------------------------------- /riscv/insns/vfmul_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfmul_vv.h -------------------------------------------------------------------------------- /riscv/insns/vfmv_f_s.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfmv_f_s.h -------------------------------------------------------------------------------- /riscv/insns/vfmv_s_f.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfmv_s_f.h -------------------------------------------------------------------------------- /riscv/insns/vfmv_v_f.h: -------------------------------------------------------------------------------- 1 | // vfmv_vf vd, vs1 2 | VI_VF_MERGE_LOOP({ 3 | vd = rs1; 4 | }) 5 | -------------------------------------------------------------------------------- /riscv/insns/vfrec7_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfrec7_v.h -------------------------------------------------------------------------------- /riscv/insns/vfsqrt_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfsqrt_v.h -------------------------------------------------------------------------------- /riscv/insns/vfsub_vf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfsub_vf.h -------------------------------------------------------------------------------- /riscv/insns/vfsub_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vfsub_vv.h -------------------------------------------------------------------------------- /riscv/insns/vghsh_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vghsh_vv.h -------------------------------------------------------------------------------- /riscv/insns/vgmul_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vgmul_vv.h -------------------------------------------------------------------------------- /riscv/insns/vid_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vid_v.h -------------------------------------------------------------------------------- /riscv/insns/viota_m.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/viota_m.h -------------------------------------------------------------------------------- /riscv/insns/vl1re16_v.h: -------------------------------------------------------------------------------- 1 | // vl1re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re32_v.h: -------------------------------------------------------------------------------- 1 | // vl1re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re64_v.h: -------------------------------------------------------------------------------- 1 | // vl1re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re8_v.h: -------------------------------------------------------------------------------- 1 | // vl1re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re16_v.h: -------------------------------------------------------------------------------- 1 | // vl2e16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re32_v.h: -------------------------------------------------------------------------------- 1 | // vl2re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re64_v.h: -------------------------------------------------------------------------------- 1 | // vl2re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re8_v.h: -------------------------------------------------------------------------------- 1 | // vl2re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re16_v.h: -------------------------------------------------------------------------------- 1 | // vl4re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re32_v.h: -------------------------------------------------------------------------------- 1 | // vl4re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re64_v.h: -------------------------------------------------------------------------------- 1 | // vl4re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re8_v.h: -------------------------------------------------------------------------------- 1 | // vl4re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re16_v.h: -------------------------------------------------------------------------------- 1 | // vl8re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re32_v.h: -------------------------------------------------------------------------------- 1 | // vl8re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re64_v.h: -------------------------------------------------------------------------------- 1 | // vl8re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re8_v.h: -------------------------------------------------------------------------------- 1 | // vl8re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle16_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vle16_v.h -------------------------------------------------------------------------------- /riscv/insns/vle32_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vle32_v.h -------------------------------------------------------------------------------- /riscv/insns/vle64_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vle64_v.h -------------------------------------------------------------------------------- /riscv/insns/vle8_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vle8_v.h -------------------------------------------------------------------------------- /riscv/insns/vle8ff_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vle8ff_v.h -------------------------------------------------------------------------------- /riscv/insns/vlm_v.h: -------------------------------------------------------------------------------- 1 | // vle1.v and vlseg[2-8]e8.v 2 | VI_LD(0, (i * nf + fn), int8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse16_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vlse16_v.h -------------------------------------------------------------------------------- /riscv/insns/vlse32_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vlse32_v.h -------------------------------------------------------------------------------- /riscv/insns/vlse64_v.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vlse64_v.h -------------------------------------------------------------------------------- /riscv/insns/vlse8_v.h: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /riscv/insns/vmadc_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmadc_vv.h -------------------------------------------------------------------------------- /riscv/insns/vmadc_vx.h: -------------------------------------------------------------------------------- 1 | // vadc.vx vd, vs2, rs1 2 | #include "vmadc_vxm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadd_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmadd_vv.h -------------------------------------------------------------------------------- /riscv/insns/vmadd_vx.h: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /riscv/insns/vmaxu_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmaxu_vv.h -------------------------------------------------------------------------------- /riscv/insns/vmaxu_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmaxu_vx.h -------------------------------------------------------------------------------- /riscv/insns/vmfeq_vf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmfeq_vf.h -------------------------------------------------------------------------------- /riscv/insns/vmfeq_vv.h: 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-------------------------------------------------------------------------------- /riscv/insns/vmulh_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmulh_vx.h -------------------------------------------------------------------------------- /riscv/insns/vmv1r_v.h: -------------------------------------------------------------------------------- 1 | // vmv1r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv2r_v.h: -------------------------------------------------------------------------------- 1 | // vmv2r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv4r_v.h: -------------------------------------------------------------------------------- 1 | // vmv4r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv8r_v.h: -------------------------------------------------------------------------------- 1 | // vmv8r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv_s_x.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmv_s_x.h -------------------------------------------------------------------------------- /riscv/insns/vmv_v_i.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmv_v_i.h -------------------------------------------------------------------------------- /riscv/insns/vmv_v_v.h: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /riscv/insns/vmxor_mm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vmxor_mm.h -------------------------------------------------------------------------------- /riscv/insns/vnsra_wi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vnsra_wi.h -------------------------------------------------------------------------------- /riscv/insns/vnsra_wv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vnsra_wv.h -------------------------------------------------------------------------------- /riscv/insns/vnsra_wx.h: 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-------------------------------------------------------------------------------- /riscv/insns/vrol_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vrol_vv.h -------------------------------------------------------------------------------- /riscv/insns/vrol_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vrol_vx.h -------------------------------------------------------------------------------- /riscv/insns/vror_vi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vror_vi.h -------------------------------------------------------------------------------- /riscv/insns/vror_vv.h: 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VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vsadd_vi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsadd_vi.h -------------------------------------------------------------------------------- /riscv/insns/vsadd_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsadd_vv.h -------------------------------------------------------------------------------- /riscv/insns/vsadd_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsadd_vx.h -------------------------------------------------------------------------------- /riscv/insns/vsbc_vvm.h: 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-------------------------------------------------------------------------------- /riscv/insns/vsetvl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsetvl.h -------------------------------------------------------------------------------- /riscv/insns/vsetvli.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsetvli.h -------------------------------------------------------------------------------- /riscv/insns/vsext_vf2.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(2, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf4.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(4, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf8.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(8, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsll_vi.h -------------------------------------------------------------------------------- /riscv/insns/vsll_vv.h: -------------------------------------------------------------------------------- 1 | // vsll 2 | VI_VV_ULOOP 3 | ({ 4 | vd = vs2 << (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vx.h: -------------------------------------------------------------------------------- 1 | // vsll 2 | VI_VX_ULOOP 3 | ({ 4 | vd = vs2 << (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsm3c_vi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsm3c_vi.h -------------------------------------------------------------------------------- /riscv/insns/vsm4k_vi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsm4k_vi.h -------------------------------------------------------------------------------- /riscv/insns/vsm4r_vs.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vsm4r_vs.h -------------------------------------------------------------------------------- /riscv/insns/vsm4r_vv.h: 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-------------------------------------------------------------------------------- /riscv/insns/vsuxei16_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe16.v 2 | VI_ST_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei32_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe32.v 2 | VI_ST_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei64_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe64.v 2 | VI_ST_INDEX(e64, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei8_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe8.v 2 | VI_ST_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_vv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vwadd_vv.h -------------------------------------------------------------------------------- /riscv/insns/vwadd_vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vwadd_vx.h -------------------------------------------------------------------------------- /riscv/insns/vwadd_wv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/vwadd_wv.h -------------------------------------------------------------------------------- /riscv/insns/vwadd_wx.h: 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-------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vv.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vx.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf2.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(2, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf4.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(4, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf8.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(8, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/wfi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/wfi.h -------------------------------------------------------------------------------- /riscv/insns/wrs_nto.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-isa-sim/HEAD/riscv/insns/wrs_nto.h -------------------------------------------------------------------------------- /riscv/insns/wrs_sto.h: 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