├── fdt └── fdt.ac ├── disasm ├── disasm.ac └── disasm.mk.in ├── customext ├── customext.ac └── customext.mk.in ├── riscv ├── insns │ ├── fence.h │ ├── and.h │ ├── or.h │ ├── sltu.h │ ├── xor.h │ ├── fence_i.h │ ├── lui.h │ ├── vsext_vf2.h │ ├── vsext_vf4.h │ ├── vsext_vf8.h │ ├── vzext_vf2.h │ ├── vzext_vf4.h │ ├── vzext_vf8.h │ ├── add.h │ ├── andi.h │ ├── sspush_x5.h │ ├── sub.h │ ├── xori.h │ ├── slt.h │ ├── sspopchk_x5.h │ ├── addi.h │ ├── auipc.h │ ├── cm_popret.h │ ├── sfence_w_inval.h │ ├── sltiu.h │ ├── vs1r_v.h │ ├── vs2r_v.h │ ├── vs4r_v.h │ ├── vs8r_v.h │ ├── beq.h │ ├── bgeu.h │ ├── bltu.h │ ├── bne.h │ ├── lb.h │ ├── sb.h │ ├── sh.h │ ├── sll.h │ ├── slti.h │ ├── sw.h │ ├── vsuxei8_v.h │ ├── addw.h │ ├── c_mv.h │ ├── lbu.h │ ├── lh.h │ ├── lhu.h │ ├── lw.h │ ├── mop_r_N.h │ ├── mop_rr_N.h │ ├── slliw.h │ ├── vl1re8_v.h │ ├── vl2re8_v.h │ ├── vl4re8_v.h │ ├── vl8re8_v.h │ ├── vmv1r_v.h │ ├── vmv2r_v.h │ ├── vmv4r_v.h │ ├── vmv8r_v.h │ ├── vsuxei16_v.h │ ├── vsuxei32_v.h │ ├── vsuxei64_v.h │ ├── cm_popretz.h │ ├── sra.h │ ├── srl.h │ ├── subw.h │ ├── vaadd_vv.h │ ├── vaadd_vx.h │ ├── vaaddu_vv.h │ ├── vaaddu_vx.h │ ├── vasub_vv.h │ ├── vasub_vx.h │ ├── vasubu_vv.h │ ├── vasubu_vx.h │ ├── vl1re16_v.h │ ├── vl1re32_v.h │ ├── vl1re64_v.h │ ├── vl2re16_v.h │ ├── vl2re32_v.h │ ├── vl2re64_v.h │ ├── vl4re16_v.h │ ├── vl4re32_v.h │ ├── vl4re64_v.h │ ├── vl8re16_v.h │ ├── vl8re32_v.h │ ├── vl8re64_v.h │ ├── vmadc_vx.h │ ├── vmor_mm.h │ ├── vmsbc_vv.h │ ├── vmsbc_vx.h │ ├── vsm_v.h │ ├── addiw.h │ ├── bge.h │ ├── blt.h │ ├── c_li.h │ ├── sllw.h │ ├── sraiw.h │ ├── srliw.h │ ├── vle8ff_v.h │ ├── vmadc_vi.h │ ├── vmadc_vv.h │ ├── vmand_mm.h │ ├── vmandn_mm.h │ ├── vmnor_mm.h │ ├── vmorn_mm.h │ ├── vmxor_mm.h │ ├── vor_vv.h │ ├── vor_vx.h │ ├── c_j.h │ ├── c_mop_N.h │ ├── sb_rl.h │ ├── sinval_vma.h │ ├── slli.h │ ├── sraw.h │ ├── vle16ff_v.h │ ├── vle32ff_v.h │ ├── vle64ff_v.h │ ├── vloxei8_v.h │ ├── vluxei8_v.h │ ├── vmnand_mm.h │ ├── vmxnor_mm.h │ ├── vor_vi.h │ ├── vsoxei8_v.h │ ├── vsub_vv.h │ ├── vxor_vi.h │ ├── vxor_vv.h │ ├── vxor_vx.h │ ├── andn.h │ ├── c_and.h │ ├── c_not.h │ ├── c_or.h │ ├── c_xor.h │ ├── czero_eqz.h │ ├── czero_nez.h │ ├── fmv_w_x.h │ ├── hinval_gvma.h │ ├── hinval_vvma.h │ ├── lb_aq.h │ ├── lh_aq.h │ ├── lw_aq.h │ ├── lwu.h │ ├── orn.h │ ├── sext_b.h │ ├── sext_h.h │ ├── sh_rl.h │ ├── srlw.h │ ├── sw_rl.h │ ├── vfmv_v_f.h │ ├── vlm_v.h │ ├── vloxei16_v.h │ ├── vloxei32_v.h │ ├── vlse8_v.h │ ├── vluxei16_v.h │ ├── vluxei32_v.h │ ├── vsoxei16_v.h │ ├── vsoxei32_v.h │ ├── vsoxei64_v.h │ ├── xnor.h │ ├── c_add.h │ ├── fmv_x_w.h │ ├── jal.h │ ├── maxu.h │ ├── minu.h │ ├── sh1add.h │ ├── sh2add.h │ ├── sh3add.h │ ├── srai.h │ ├── srli.h │ ├── vle8_v.h │ ├── vloxei64_v.h │ ├── vlse16_v.h │ ├── vlse32_v.h │ ├── vlse64_v.h │ ├── vluxei64_v.h │ ├── vmul_vv.h │ ├── vmul_vx.h │ ├── vmv_v_v.h │ ├── vmv_v_x.h │ ├── vse8_v.h │ ├── vsse16_v.h │ ├── vsse32_v.h │ ├── vsse64_v.h │ ├── vsse8_v.h │ ├── c_addi.h │ ├── c_andi.h │ ├── c_sub.h │ ├── c_zext_b.h │ ├── lr_w.h │ ├── mul.h │ ├── vle16_v.h │ ├── vle32_v.h │ ├── vle64_v.h │ ├── vmv_v_i.h │ ├── vse16_v.h │ ├── vse32_v.h │ ├── vse64_v.h │ ├── vsll_vv.h │ ├── vsll_vx.h │ ├── wrs_sto.h │ ├── c_sspush_x1.h │ ├── fclass_q.h │ ├── fmv_d_x.h │ ├── fmv_h_x.h │ ├── fmv_x_d.h │ ├── sd_rl.h │ ├── vadd_vi.h │ ├── vadd_vv.h │ ├── vadd_vx.h │ ├── vand_vi.h │ ├── vand_vv.h │ ├── vand_vx.h │ ├── vmseq_vx.h │ ├── vmsgt_vx.h │ ├── vmsle_vv.h │ ├── vmsle_vx.h │ ├── vmslt_vv.h │ ├── vmslt_vx.h │ ├── vmsne_vv.h │ ├── vmsne_vx.h │ ├── xperm4.h │ ├── xperm8.h │ ├── c_beqz.h │ ├── c_bnez.h │ ├── c_sb.h │ ├── fsgnjn_q.h │ ├── ld_aq.h │ ├── max.h │ ├── min.h │ ├── ori.h │ ├── vmseq_vi.h │ ├── vmseq_vv.h │ ├── vmsgt_vi.h │ ├── vmsgtu_vx.h │ ├── vmsle_vi.h │ ├── vmsleu_vv.h │ ├── vmsleu_vx.h │ ├── vmsltu_vv.h │ ├── vmsltu_vx.h │ ├── vmsne_vi.h │ ├── add_uw.h │ ├── c_lh.h │ ├── c_sh.h │ ├── c_sw.h │ ├── c_swsp.h │ ├── fsd.h │ ├── fsgnj_q.h │ ├── fsgnjx_q.h │ ├── fsw.h │ ├── lr_d.h │ ├── mulw.h │ ├── slli_uw.h │ ├── vredand_vs.h │ ├── vredor_vs.h │ ├── vredsum_vs.h │ ├── vredxor_vs.h │ ├── vsetvl.h │ ├── vsra_vv.h │ ├── vsra_vx.h │ ├── vsrl_vv.h │ ├── vsrl_vx.h │ ├── beqi.h │ ├── bnei.h │ ├── c_addw.h │ ├── c_lbu.h │ ├── c_lhu.h │ ├── c_lw.h │ ├── c_subw.h │ ├── fclass_d.h │ ├── fclass_s.h │ ├── fld.h │ ├── flw.h │ ├── vsll_vi.h │ ├── vsrl_vi.h │ ├── vsub_vx.h │ ├── amocas_w.h │ ├── bext.h │ ├── fclass_h.h │ ├── fmv_x_h.h │ ├── hfence_vvma.h │ ├── sh1add_uw.h │ ├── sh2add_uw.h │ ├── sh3add_uw.h │ ├── vfmerge_vfm.h │ ├── vmadd_vv.h │ ├── vmadd_vx.h │ ├── vmerge_vim.h │ ├── vmerge_vvm.h │ ├── vmerge_vxm.h │ ├── vnsra_wv.h │ ├── vnsra_wx.h │ ├── vsetivli.h │ ├── vsetvli.h │ ├── vsra_vi.h │ ├── vwredsum_vs.h │ ├── vwredsumu_vs.h │ ├── bclr.h │ ├── binv.h │ ├── bset.h │ ├── c_sspopchk_x5.h │ ├── feq_q.h │ ├── fle_q.h │ ├── flt_q.h │ ├── vmacc_vv.h │ ├── vmacc_vx.h │ ├── vnmsac_vx.h │ ├── vnsra_wi.h │ ├── vnsrl_wv.h │ ├── vnsrl_wx.h │ ├── vrsub_vi.h │ ├── vrsub_vx.h │ ├── amoor_b.h │ ├── c_fsd.h │ ├── c_fsw.h │ ├── c_sext_b.h │ ├── c_sext_h.h │ ├── c_zext_h.h │ ├── cbo_zero.h │ ├── cm_mva01s.h │ ├── fsh.h │ ├── vnmsac_vv.h │ ├── vnmsub_vv.h │ ├── vnmsub_vx.h │ ├── vnsrl_wi.h │ ├── amoadd_b.h │ ├── amoadd_h.h │ ├── amoadd_w.h │ ├── amoand_b.h │ ├── amoand_h.h │ ├── amoand_w.h │ ├── amoor_h.h │ ├── amoor_w.h │ ├── amoswap_b.h │ ├── amoswap_h.h │ ├── amoxor_b.h │ ├── amoxor_h.h │ ├── amoxor_w.h │ ├── c_fld.h │ ├── c_fldsp.h │ ├── c_flw.h │ ├── c_flwsp.h │ ├── c_fsdsp.h │ ├── c_fswsp.h │ ├── c_slli.h │ ├── feq_d.h │ ├── feq_s.h │ ├── fle_d.h │ ├── fle_s.h │ ├── flh.h │ ├── flt_d.h │ ├── flt_s.h │ ├── vfwmaccbf16_vf.h │ ├── vfwmaccbf16_vv.h │ ├── amoswap_w.h │ ├── c_lwsp.h │ ├── feq_h.h │ ├── fle_h.h │ ├── flt_h.h │ ├── sspush_x1.h │ ├── vredmax_vs.h │ ├── vredmin_vs.h │ ├── vwadd_wv.h │ ├── vwadd_wx.h │ ├── vwaddu_wv.h │ ├── vwsub_wv.h │ ├── vwsub_wx.h │ ├── vwsubu_wv.h │ ├── amoadd_d.h │ ├── amoand_d.h │ ├── amoor_d.h │ ├── amoxor_d.h │ ├── c_mul.h │ ├── c_zext_w.h │ ├── fmax_h.h │ ├── fmin_h.h │ ├── fsgnj_d.h │ ├── fsgnj_s.h │ ├── fsgnjn_d.h │ ├── fsgnjn_h.h │ ├── fsgnjn_s.h │ ├── fsgnjx_d.h │ ├── fsgnjx_s.h │ ├── vdivu_vv.h │ ├── vdivu_vx.h │ ├── vredmaxu_vs.h │ ├── vredminu_vs.h │ ├── vwaddu_wx.h │ ├── vwsubu_wx.h │ ├── amomax_b.h │ ├── amomin_b.h │ ├── amoswap_d.h │ ├── bexti.h │ ├── c_jr.h │ ├── cbo_clean.h │ ├── cbo_flush.h │ ├── fsgnj_h.h │ ├── fsgnjx_h.h │ ├── jalr.h │ ├── vremu_vv.h │ ├── vremu_vx.h │ ├── amocas_b.h │ ├── amocas_h.h │ ├── amomax_h.h │ ├── amomax_w.h │ ├── amomaxu_b.h │ ├── amomaxu_d.h │ ├── amomaxu_h.h │ ├── amomaxu_w.h │ ├── amomin_h.h │ ├── amomin_w.h │ ├── amominu_b.h │ ├── amominu_d.h │ ├── amominu_h.h │ ├── amominu_w.h │ ├── bclri.h │ ├── binvi.h │ ├── bseti.h │ ├── c_srai.h │ ├── c_srli.h │ ├── cpop.h │ ├── fcvt_d_q.h │ ├── fcvt_q_d.h │ ├── fcvt_q_s.h │ ├── fcvt_s_q.h │ ├── fleq_d.h │ ├── fleq_s.h │ ├── fltq_d.h │ ├── fltq_s.h │ ├── fsqrt_q.h │ ├── sfence_inval_ir.h │ ├── sspopchk_x1.h │ ├── ssrdp.h │ ├── vadc_vvm.h │ ├── vadc_vxm.h │ ├── vmadc_vxm.h │ ├── vmsgtu_vi.h │ ├── vmsleu_vi.h │ ├── vsbc_vvm.h │ ├── vsbc_vxm.h │ ├── vwadd_vv.h │ ├── vwmul_vv.h │ ├── vwsub_vv.h │ ├── c_addi4spn.h │ ├── fcvt_q_w.h │ ├── fcvt_q_wu.h │ ├── fleq_h.h │ ├── fltq_h.h │ ├── sc_w.h │ ├── vadc_vim.h │ ├── vfwadd_vf.h │ ├── vfwadd_wf.h │ ├── vfwadd_wv.h │ ├── vfwmul_vf.h │ ├── vfwmul_vv.h │ ├── vfwsub_vf.h │ ├── vfwsub_vv.h │ ├── vfwsub_wf.h │ ├── vfwsub_wv.h │ ├── vmadc_vvm.h │ ├── vmsbc_vvm.h │ ├── vmsbc_vxm.h │ ├── vwadd_vx.h │ ├── vwaddu_vv.h │ ├── vwaddu_vx.h │ ├── vwmacc_vv.h │ ├── vwmul_vx.h │ ├── vwmulu_vv.h │ ├── vwmulu_vx.h │ ├── vwsub_vx.h │ ├── vwsubu_vv.h │ ├── vwsubu_vx.h │ ├── amomax_d.h │ ├── amomin_d.h │ ├── c_jalr.h │ ├── fadd_q.h │ ├── fcvt_bf16_s.h │ ├── fcvt_q_l.h │ ├── fcvt_s_bf16.h │ ├── fdiv_q.h │ ├── fleq_q.h │ ├── fltq_q.h │ ├── fmul_q.h │ ├── fround_d.h │ ├── fround_s.h │ ├── fsq.h │ ├── fsub_q.h │ ├── vmadc_vim.h │ ├── vwmacc_vx.h │ ├── vwmaccu_vv.h │ ├── vwmaccu_vx.h │ ├── cpopw.h │ ├── ctz.h │ ├── fcvt_d_s.h │ ├── fcvt_q_lu.h │ ├── fcvt_s_d.h │ ├── fround_h.h │ ├── fround_q.h │ ├── froundnx_d.h │ ├── froundnx_h.h │ ├── froundnx_q.h │ ├── froundnx_s.h │ ├── fsqrt_d.h │ ├── fsqrt_h.h │ ├── fsqrt_s.h │ ├── csrrw.h │ ├── fadd_d.h │ ├── fadd_s.h │ ├── fcvt_d_w.h │ ├── fcvt_s_w.h │ ├── fcvt_w_q.h │ ├── fcvt_wu_q.h │ ├── fdiv_d.h │ ├── fdiv_s.h │ ├── fmul_d.h │ ├── fmul_s.h │ ├── fmvh_x_q.h │ ├── fsub_d.h │ ├── fsub_s.h │ ├── hfence_gvma.h │ ├── vfwmacc_vf.h │ ├── vfwmacc_vv.h │ ├── vmulh_vv.h │ ├── vmulh_vx.h │ ├── vwmulsu_vv.h │ ├── vwmulsu_vx.h │ ├── clz.h │ ├── cm_mvsa01.h │ ├── ctzw.h │ ├── fadd_h.h │ ├── fcvt_d_wu.h │ ├── fcvt_h_s.h │ ├── fcvt_h_w.h │ ├── fcvt_s_h.h │ ├── fcvt_s_wu.h │ ├── fdiv_h.h │ ├── fmadd_q.h │ ├── fmul_h.h │ ├── fmvh_x_d.h │ ├── fsub_h.h │ ├── mulh.h │ ├── sc_d.h │ ├── vandn_vv.h │ ├── vandn_vx.h │ ├── vmulhu_vv.h │ ├── vmulhu_vx.h │ ├── vwmaccsu_vv.h │ ├── vwmaccsu_vx.h │ ├── vwmaccus_vx.h │ ├── clzw.h │ ├── csrrwi.h │ ├── fcvt_d_l.h │ ├── fcvt_h_wu.h │ ├── fcvt_l_q.h │ ├── fcvt_lu_q.h │ ├── fcvt_s_l.h │ ├── fcvt_w_d.h │ ├── fcvt_w_s.h │ ├── flq.h │ ├── fmadd_d.h │ ├── fmadd_s.h │ ├── fcvt_d_lu.h │ ├── fcvt_h_l.h │ ├── fcvt_h_lu.h │ ├── fcvt_h_q.h │ ├── fcvt_q_h.h │ ├── fcvt_s_lu.h │ ├── fcvt_w_h.h │ ├── fcvt_wu_d.h │ ├── fcvt_wu_h.h │ ├── fcvt_wu_s.h │ ├── fmadd_h.h │ ├── fmsub_q.h │ ├── hlv_b.h │ ├── hlv_h.h │ ├── hlv_w.h │ ├── hsv_b.h │ ├── hsv_h.h │ ├── hsv_w.h │ ├── mulhsu.h │ ├── packh.h │ ├── vmaxu_vv.h │ ├── vmaxu_vx.h │ ├── vminu_vv.h │ ├── vmulhsu_vv.h │ ├── vmulhsu_vx.h │ ├── divu.h │ ├── fcvt_l_d.h │ ├── fcvt_l_s.h │ ├── fmvp_q_x.h │ ├── fnmsub_q.h │ ├── hlv_bu.h │ ├── hlv_hu.h │ ├── hlvx_hu.h │ ├── vmax_vv.h │ ├── vmax_vx.h │ ├── vminu_vx.h │ ├── fcvt_l_h.h │ ├── fcvt_lu_d.h │ ├── fcvt_lu_h.h │ ├── fcvt_lu_s.h │ ├── remu.h │ ├── remw.h │ ├── rol.h │ ├── rolw.h │ ├── ror.h │ ├── rorw.h │ ├── vfwadd_vv.h │ ├── vmin_vv.h │ ├── vmin_vx.h │ ├── divuw.h │ ├── fmsub_d.h │ ├── fmsub_s.h │ ├── fnmadd_q.h │ ├── fnmsub_d.h │ ├── fnmsub_s.h │ ├── hsv_d.h │ ├── mulhu.h │ ├── ssamoswap_w.h │ ├── divw.h │ ├── fmsub_h.h │ ├── fnmsub_h.h │ ├── hlv_d.h │ ├── hlv_wu.h │ ├── hlvx_wu.h │ ├── remuw.h │ ├── vfwmsac_vf.h │ ├── vfwmsac_vv.h │ ├── vfwnmsac_vf.h │ ├── vfwnmsac_vv.h │ ├── vsaddu_vv.h │ ├── fmvp_d_x.h │ ├── ssamoswap_d.h │ ├── vfrsub_vf.h │ ├── vmfeq_vf.h │ ├── vmfge_vf.h │ ├── vmfgt_vf.h │ ├── vmfle_vf.h │ ├── vmflt_vf.h │ ├── vsaddu_vx.h │ ├── clmulr.h │ ├── vfsqrt_v.h │ ├── vfwredusum_vs.h │ ├── vmfne_vf.h │ ├── clmul.h │ ├── fcvt_d_h.h │ ├── fcvt_h_d.h │ ├── fnmadd_d.h │ ├── fnmadd_h.h │ ├── fnmadd_s.h │ ├── roriw.h │ ├── sd.h │ ├── vfwredosum_vs.h │ ├── rori.h │ ├── vfmax_vf.h │ ├── vfmax_vv.h │ ├── vfrec7_v.h │ ├── clmulh.h │ ├── vdiv_vv.h │ ├── vdiv_vx.h │ ├── vfdiv_vf.h │ ├── vfdiv_vv.h │ ├── ld.h │ ├── vfadd_vf.h │ ├── vfadd_vv.h │ ├── vfmin_vf.h │ ├── vfmin_vv.h │ ├── vfrsqrt7_v.h │ ├── vfsub_vf.h │ ├── vfsub_vv.h │ ├── vrem_vx.h │ ├── csrrc.h │ ├── csrrs.h │ ├── vfmul_vf.h │ ├── vfmul_vv.h │ ├── vmfeq_vv.h │ ├── vmfle_vv.h │ ├── vmflt_vv.h │ ├── vmfne_vv.h │ ├── vssra_vv.h │ ├── vssra_vx.h │ ├── vssrl_vv.h │ ├── vssrl_vx.h │ ├── csrrsi.h │ ├── vfcvt_f_x_v.h │ ├── vfwnmacc_vf.h │ ├── vfwnmacc_vv.h │ ├── vrem_vv.h │ ├── vssrl_vi.h │ ├── vssra_vi.h │ ├── wrs_nto.h │ ├── csrrci.h │ ├── vfclass_v.h │ ├── vfcvt_f_xu_v.h │ ├── vfredmax_vs.h │ ├── vfredmin_vs.h │ ├── vsaddu_vi.h │ ├── rem.h │ ├── vwsll_vi.h │ ├── vwsll_vv.h │ ├── vwsll_vx.h │ ├── div.h │ ├── vqdot_vv.h │ ├── vqdot_vx.h │ ├── c_jal.h │ ├── sha256sig0.h │ ├── vfmadd_vf.h │ ├── vfmadd_vv.h │ ├── vfrdiv_vf.h │ ├── vfredosum_vs.h │ ├── vfredusum_vs.h │ ├── vqdotsu_vv.h │ ├── vqdotsu_vx.h │ ├── vqdotu_vv.h │ ├── vqdotu_vx.h │ ├── vqdotus_vx.h │ ├── sha256sig1.h │ ├── sha256sum0.h │ ├── sha256sum1.h │ ├── vctz_v.h │ ├── c_sd.h │ ├── c_sdsp.h │ ├── sha512sig0.h │ ├── sha512sig1.h │ ├── sha512sum0.h │ ├── packw.h │ ├── sha512sig0h.h │ ├── sha512sig0l.h │ ├── sha512sig1h.h │ ├── sha512sig1l.h │ ├── sha512sum0r.h │ ├── sha512sum1.h │ └── sha512sum1r.h └── tracer.h ├── softfloat ├── softfloat.ac ├── s_commonNaNToF16UI.c ├── s_commonNaNToF32UI.c ├── s_commonNaNToF64UI.c ├── s_f128UIToCommonNaN.c ├── s_f16UIToCommonNaN.c ├── s_f32UIToCommonNaN.c └── s_f64UIToCommonNaN.c ├── spike_dasm ├── spike_dasm.ac ├── spike_dasm_option_parser.cc └── spike_dasm.mk.in ├── spike_main └── spike_main.ac ├── .github └── workflows │ ├── brew-packages.txt │ └── apt-packages.txt ├── VERSION ├── ci-tests ├── .gitignore ├── snippy-tests │ └── linker-entry.ld └── dummy-slliuw.c ├── debug_rom ├── .gitignore └── link.ld ├── .gitignore ├── fesvr ├── dummy.cc └── term.h └── arch_test_target └── spike └── device ├── rv32i_m ├── C │ └── Makefile.include ├── I │ └── Makefile.include ├── M │ └── Makefile.include └── F │ └── Makefile.include ├── rv64i_m ├── C │ └── Makefile.include └── I │ └── Makefile.include └── rv32e_unratified └── C └── Makefile.include /fdt/fdt.ac: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /disasm/disasm.ac: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /customext/customext.ac: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /riscv/insns/fence.h: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /softfloat/softfloat.ac: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /spike_dasm/spike_dasm.ac: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /spike_main/spike_main.ac: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.github/workflows/brew-packages.txt: -------------------------------------------------------------------------------- 1 | dtc 2 | -------------------------------------------------------------------------------- /riscv/insns/and.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 & RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/or.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 | RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/sltu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 < RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/xor.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 ^ RS2); 2 | -------------------------------------------------------------------------------- /VERSION: -------------------------------------------------------------------------------- 1 | #define SPIKE_VERSION "1.1.1-dev" 2 | -------------------------------------------------------------------------------- /riscv/insns/fence_i.h: -------------------------------------------------------------------------------- 1 | MMU.flush_icache(); 2 | -------------------------------------------------------------------------------- /riscv/insns/lui.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.u_imm()); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf2.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(2, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf4.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(4, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsext_vf8.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(8, int); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf2.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(2, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf4.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(4, uint); 2 | -------------------------------------------------------------------------------- /riscv/insns/vzext_vf8.h: -------------------------------------------------------------------------------- 1 | VI_VV_EXT(8, uint); 2 | -------------------------------------------------------------------------------- /ci-tests/.gitignore: -------------------------------------------------------------------------------- 1 | /install 2 | /build 3 | /run 4 | -------------------------------------------------------------------------------- /riscv/insns/add.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 + RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/andi.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.i_imm() & RS1); 2 | -------------------------------------------------------------------------------- /riscv/insns/sspush_x5.h: -------------------------------------------------------------------------------- 1 | #include "sspush_x1.h" 2 | -------------------------------------------------------------------------------- /riscv/insns/sub.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 - RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/xori.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(insn.i_imm() ^ RS1); 2 | -------------------------------------------------------------------------------- /ci-tests/snippy-tests/linker-entry.ld: -------------------------------------------------------------------------------- 1 | ENTRY(_entry) 2 | -------------------------------------------------------------------------------- /riscv/insns/slt.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sreg_t(RS1) < sreg_t(RS2)); 2 | -------------------------------------------------------------------------------- /riscv/insns/sspopchk_x5.h: -------------------------------------------------------------------------------- 1 | #include "sspopchk_x1.h" 2 | -------------------------------------------------------------------------------- /riscv/insns/addi.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/auipc.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(insn.u_imm() + pc)); 2 | -------------------------------------------------------------------------------- /riscv/insns/cm_popret.h: -------------------------------------------------------------------------------- 1 | #include "cm_pop.h" 2 | set_pc(RA); 3 | -------------------------------------------------------------------------------- /riscv/insns/sfence_w_inval.h: -------------------------------------------------------------------------------- 1 | #include "sfence_inval_ir.h" 2 | -------------------------------------------------------------------------------- /riscv/insns/sltiu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(RS1 < reg_t(insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/vs1r_v.h: -------------------------------------------------------------------------------- 1 | // vs1r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vs2r_v.h: -------------------------------------------------------------------------------- 1 | // vs2r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vs4r_v.h: -------------------------------------------------------------------------------- 1 | // vs4r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /riscv/insns/vs8r_v.h: -------------------------------------------------------------------------------- 1 | // vs8r.v vs3, (rs1) 2 | VI_ST_WHOLE 3 | -------------------------------------------------------------------------------- /spike_dasm/spike_dasm_option_parser.cc: -------------------------------------------------------------------------------- 1 | ../fesvr/option_parser.cc -------------------------------------------------------------------------------- /riscv/insns/beq.h: -------------------------------------------------------------------------------- 1 | if (RS1 == RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bgeu.h: -------------------------------------------------------------------------------- 1 | if (RS1 >= RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bltu.h: -------------------------------------------------------------------------------- 1 | if (RS1 < RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/bne.h: -------------------------------------------------------------------------------- 1 | if (RS1 != RS2) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/lb.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/sb.h: -------------------------------------------------------------------------------- 1 | MMU.store(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/sh.h: -------------------------------------------------------------------------------- 1 | MMU.store(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/sll.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(RS1 << (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /riscv/insns/slti.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/sw.h: -------------------------------------------------------------------------------- 1 | MMU.store(RS1 + insn.s_imm(), RS2); 2 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei8_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe8.v 2 | VI_ST_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/addw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_mv.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RD(RVC_RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/lbu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lh.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lhu.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/lw.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 2 | -------------------------------------------------------------------------------- /riscv/insns/mop_r_N.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZIMOP); 2 | WRITE_RD(0); 3 | -------------------------------------------------------------------------------- /riscv/insns/mop_rr_N.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZIMOP); 2 | WRITE_RD(0); 3 | -------------------------------------------------------------------------------- /riscv/insns/slliw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 << SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re8_v.h: -------------------------------------------------------------------------------- 1 | // vl1re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re8_v.h: -------------------------------------------------------------------------------- 1 | // vl2re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re8_v.h: -------------------------------------------------------------------------------- 1 | // vl4re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re8_v.h: -------------------------------------------------------------------------------- 1 | // vl8re8.v vd, (rs1) 2 | VI_LD_WHOLE(uint8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv1r_v.h: -------------------------------------------------------------------------------- 1 | // vmv1r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv2r_v.h: -------------------------------------------------------------------------------- 1 | // vmv2r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv4r_v.h: -------------------------------------------------------------------------------- 1 | // vmv4r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv8r_v.h: -------------------------------------------------------------------------------- 1 | // vmv8r.v vd, vs2 2 | #include "vmvnfr_v.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei16_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe16.v 2 | VI_ST_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei32_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe32.v 2 | VI_ST_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsuxei64_v.h: -------------------------------------------------------------------------------- 1 | // vsuxe64.v 2 | VI_ST_INDEX(e64, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/cm_popretz.h: -------------------------------------------------------------------------------- 1 | #include "cm_popret.h" 2 | WRITE_REG(X_A0, 0); 3 | -------------------------------------------------------------------------------- /riscv/insns/sra.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(sext_xlen(RS1) >> (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /riscv/insns/srl.h: -------------------------------------------------------------------------------- 1 | WRITE_RD(sext_xlen(zext_xlen(RS1) >> (RS2 & (xlen-1)))); 2 | -------------------------------------------------------------------------------- /riscv/insns/subw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 - RS2)); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/vaadd_vv.h: -------------------------------------------------------------------------------- 1 | // vaadd.vv vd, vs2, vs1 2 | VI_VV_LOOP_AVG(+); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaadd_vx.h: -------------------------------------------------------------------------------- 1 | // vaadd.vx vd, vs2, rs1 2 | VI_VX_LOOP_AVG(+); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaaddu_vv.h: -------------------------------------------------------------------------------- 1 | // vaaddu.vv vd, vs2, vs1 2 | VI_VV_ULOOP_AVG(+); 3 | -------------------------------------------------------------------------------- /riscv/insns/vaaddu_vx.h: -------------------------------------------------------------------------------- 1 | // vaaddu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_AVG(+); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasub_vv.h: -------------------------------------------------------------------------------- 1 | // vasub.vv vd, vs2, vs1 2 | VI_VV_LOOP_AVG(-); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasub_vx.h: -------------------------------------------------------------------------------- 1 | // vasub.vx vd, vs2, rs1 2 | VI_VX_LOOP_AVG(-); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasubu_vv.h: -------------------------------------------------------------------------------- 1 | // vasubu.vv vd, vs2, vs1 2 | VI_VV_ULOOP_AVG(-); 3 | -------------------------------------------------------------------------------- /riscv/insns/vasubu_vx.h: -------------------------------------------------------------------------------- 1 | // vasubu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_AVG(-); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re16_v.h: -------------------------------------------------------------------------------- 1 | // vl1re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re32_v.h: -------------------------------------------------------------------------------- 1 | // vl1re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl1re64_v.h: -------------------------------------------------------------------------------- 1 | // vl1re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re16_v.h: -------------------------------------------------------------------------------- 1 | // vl2e16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re32_v.h: -------------------------------------------------------------------------------- 1 | // vl2re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl2re64_v.h: -------------------------------------------------------------------------------- 1 | // vl2re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re16_v.h: -------------------------------------------------------------------------------- 1 | // vl4re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re32_v.h: -------------------------------------------------------------------------------- 1 | // vl4re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl4re64_v.h: -------------------------------------------------------------------------------- 1 | // vl4re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re16_v.h: -------------------------------------------------------------------------------- 1 | // vl8re16.v vd, (rs1) 2 | VI_LD_WHOLE(uint16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re32_v.h: -------------------------------------------------------------------------------- 1 | // vl8re32.v vd, (rs1) 2 | VI_LD_WHOLE(uint32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vl8re64_v.h: -------------------------------------------------------------------------------- 1 | // vl8re64.v vd, (rs1) 2 | VI_LD_WHOLE(uint64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vx.h: -------------------------------------------------------------------------------- 1 | // vadc.vx vd, vs2, rs1 2 | #include "vmadc_vxm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmor_mm.h: -------------------------------------------------------------------------------- 1 | // vmor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 | vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmsbc_vv.h: -------------------------------------------------------------------------------- 1 | // vmsbc.vv vd, vs2, rs1 2 | #include "vmsbc_vvm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmsbc_vx.h: -------------------------------------------------------------------------------- 1 | // vmsbc.vx vd, vs2, rs1 2 | #include "vmsbc_vxm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vsm_v.h: -------------------------------------------------------------------------------- 1 | // vse1.v 2 | VI_ST(0, (i * nf + fn), uint8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/addiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(insn.i_imm() + RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/bge.h: -------------------------------------------------------------------------------- 1 | if (sreg_t(RS1) >= sreg_t(RS2)) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/blt.h: -------------------------------------------------------------------------------- 1 | if (sreg_t(RS1) < sreg_t(RS2)) 2 | set_pc(BRANCH_TARGET); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_li.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RD(insn.rvc_imm()); 3 | -------------------------------------------------------------------------------- /riscv/insns/sllw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(RS1 << (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/sraiw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(int32_t(RS1) >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srliw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle8ff_v.h: -------------------------------------------------------------------------------- 1 | // vle8ff.v and vlseg[2-8]e8ff.v 2 | VI_LDST_FF(int8); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vi.h: -------------------------------------------------------------------------------- 1 | // vmadc.vi vd, vs2, simm5 2 | #include "vmadc_vim.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vv.h: -------------------------------------------------------------------------------- 1 | // vmadc.vvm vd, vs2, rs1 2 | #include "vmadc_vvm.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/vmand_mm.h: -------------------------------------------------------------------------------- 1 | // vmand.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 & vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmandn_mm.h: -------------------------------------------------------------------------------- 1 | // vmandn.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 & !vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmnor_mm.h: -------------------------------------------------------------------------------- 1 | // vmnor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(!(vs2 | vs1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmorn_mm.h: -------------------------------------------------------------------------------- 1 | // vmorn.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 | !vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmxor_mm.h: -------------------------------------------------------------------------------- 1 | // vmxor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(vs2 ^ vs1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vor_vv.h: -------------------------------------------------------------------------------- 1 | // vor 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 | vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vor_vx.h: -------------------------------------------------------------------------------- 1 | // vor 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 | vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/c_j.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | set_pc(pc + insn.rvc_j_imm()); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_mop_N.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require_extension(EXT_ZCMOP); 3 | -------------------------------------------------------------------------------- /riscv/insns/sb_rl.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | MMU.store(RS1, RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/sinval_vma.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_SVINVAL); 2 | #include "sfence_vma.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/slli.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | WRITE_RD(sext_xlen(RS1 << SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sraw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle16ff_v.h: -------------------------------------------------------------------------------- 1 | // vle16ff.v and vlseg[2-8]e16ff.v 2 | VI_LDST_FF(int16); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle32ff_v.h: -------------------------------------------------------------------------------- 1 | // vle32ff.v and vlseg[2-8]e32ff.v 2 | VI_LDST_FF(int32); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle64ff_v.h: -------------------------------------------------------------------------------- 1 | // vle64ff.v and vlseg[2-8]e64ff.v 2 | VI_LDST_FF(int64); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei8_v.h: -------------------------------------------------------------------------------- 1 | // vlxei8.v and vlxseg[2-8]ei8.v 2 | VI_LD_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei8_v.h: -------------------------------------------------------------------------------- 1 | // vlxei8.v and vlxseg[2-8]ei8.v 2 | VI_LD_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmnand_mm.h: -------------------------------------------------------------------------------- 1 | // vmnand.mm vd, vs2, vs1 2 | VI_LOOP_MASK(!(vs2 & vs1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmxnor_mm.h: -------------------------------------------------------------------------------- 1 | // vmnxor.mm vd, vs2, vs1 2 | VI_LOOP_MASK(!(vs2 ^ vs1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vor_vi.h: -------------------------------------------------------------------------------- 1 | // vor 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 | vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei8_v.h: -------------------------------------------------------------------------------- 1 | // vsxei8.v and vsxseg[2-8]ei8.v 2 | VI_ST_INDEX(e8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsub_vv.h: -------------------------------------------------------------------------------- 1 | // vsub 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 - vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vi.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vv.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vxor_vx.h: -------------------------------------------------------------------------------- 1 | // vxor 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 ^ vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/andn.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | WRITE_RD(RS1 & ~RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_and.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RVC_RS1S(RVC_RS1S & RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_not.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | WRITE_RVC_RS1S(sext_xlen(~RVC_RS1S)); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_or.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RVC_RS1S(RVC_RS1S | RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_xor.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RVC_RS1S(RVC_RS1S ^ RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/czero_eqz.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICOND); 2 | WRITE_RD(RS2 == 0 ? 0 : RS1); 3 | -------------------------------------------------------------------------------- /riscv/insns/czero_nez.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICOND); 2 | WRITE_RD(RS2 != 0 ? 0 : RS1); 3 | -------------------------------------------------------------------------------- /riscv/insns/fmv_w_x.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(f32(RS1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/hinval_gvma.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_SVINVAL); 2 | #include "hfence_gvma.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/hinval_vvma.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_SVINVAL); 2 | #include "hfence_vvma.h" 3 | -------------------------------------------------------------------------------- /riscv/insns/lb_aq.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | WRITE_RD(MMU.load(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/lh_aq.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | WRITE_RD(MMU.load(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/lw_aq.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | WRITE_RD(MMU.load(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/lwu.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/orn.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | WRITE_RD(RS1 | ~RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/sext_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD((sreg_t)(int8_t)(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sext_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD((sreg_t)(int16_t)(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh_rl.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | MMU.store(RS1, RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/srlw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); 3 | -------------------------------------------------------------------------------- /riscv/insns/sw_rl.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALASR); 2 | MMU.store(RS1, RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/vfmv_v_f.h: -------------------------------------------------------------------------------- 1 | // vfmv_vf vd, vs1 2 | VI_VF_MERGE_LOOP({ 3 | vd = rs1; 4 | }) 5 | -------------------------------------------------------------------------------- /riscv/insns/vlm_v.h: -------------------------------------------------------------------------------- 1 | // vle1.v and vlseg[2-8]e8.v 2 | VI_LD(0, (i * nf + fn), int8, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei16_v.h: -------------------------------------------------------------------------------- 1 | // vlxei16.v and vlxseg[2-8]e16.v 2 | VI_LD_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei32_v.h: -------------------------------------------------------------------------------- 1 | // vlxe32.v and vlxseg[2-8]ei32.v 2 | VI_LD_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse8_v.h: -------------------------------------------------------------------------------- 1 | // vlse8.v and vlsseg[2-8]e8.v 2 | VI_LD(i * RS2, fn, int8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei16_v.h: -------------------------------------------------------------------------------- 1 | // vlxei16.v and vlxseg[2-8]e16.v 2 | VI_LD_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei32_v.h: -------------------------------------------------------------------------------- 1 | // vlxe32.v and vlxseg[2-8]ei32.v 2 | VI_LD_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei16_v.h: -------------------------------------------------------------------------------- 1 | // vsxei16.v and vsxseg[2-8]ei16.v 2 | VI_ST_INDEX(e16, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei32_v.h: -------------------------------------------------------------------------------- 1 | // vsxei32.v and vsxseg[2-8]ei32.v 2 | VI_ST_INDEX(e32, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsoxei64_v.h: -------------------------------------------------------------------------------- 1 | // vsxei64.v and vsxseg[2-8]ei64.v 2 | VI_ST_INDEX(e64, true); 3 | -------------------------------------------------------------------------------- /riscv/insns/xnor.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | WRITE_RD(RS1 ^ ~RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/fmv_x_w.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_RD(sext32(FRS1.v[0])); 4 | -------------------------------------------------------------------------------- /riscv/insns/jal.h: -------------------------------------------------------------------------------- 1 | CHECK_RD(); 2 | reg_t tmp = npc; 3 | set_pc(JUMP_TARGET); 4 | WRITE_RD(tmp); 5 | -------------------------------------------------------------------------------- /riscv/insns/maxu.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(RS1 > RS2 ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/minu.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(RS1 < RS2 ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh1add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBA); 2 | WRITE_RD(sext_xlen((RS1 << 1) + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh2add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBA); 2 | WRITE_RD(sext_xlen((RS1 << 2) + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/sh3add.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBA); 2 | WRITE_RD(sext_xlen((RS1 << 3) + RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srai.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | WRITE_RD(sext_xlen(sext_xlen(RS1) >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/srli.h: -------------------------------------------------------------------------------- 1 | require(SHAMT < xlen); 2 | WRITE_RD(sext_xlen(zext_xlen(RS1) >> SHAMT)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle8_v.h: -------------------------------------------------------------------------------- 1 | // vle8.v and vlseg[2-8]e8.v 2 | VI_LD(0, (i * nf + fn), int8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vloxei64_v.h: -------------------------------------------------------------------------------- 1 | // vlxei64.v and vlxseg[2-8]ei64.v 2 | VI_LD_INDEX(e64, true); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/vlse16_v.h: -------------------------------------------------------------------------------- 1 | // vlse16.v and vlsseg[2-8]e16.v 2 | VI_LD(i * RS2, fn, int16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse32_v.h: -------------------------------------------------------------------------------- 1 | // vlse32.v and vlsseg[2-8]e32.v 2 | VI_LD(i * RS2, fn, int32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vlse64_v.h: -------------------------------------------------------------------------------- 1 | // vlse64.v and vlsseg[2-8]e64.v 2 | VI_LD(i * RS2, fn, int64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vluxei64_v.h: -------------------------------------------------------------------------------- 1 | // vlxei64.v and vlxseg[2-8]ei64.v 2 | VI_LD_INDEX(e64, true); 3 | 4 | -------------------------------------------------------------------------------- /riscv/insns/vmul_vv.h: -------------------------------------------------------------------------------- 1 | // vmul vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 * vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmul_vx.h: -------------------------------------------------------------------------------- 1 | // vmul vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 * rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmv_v_v.h: -------------------------------------------------------------------------------- 1 | // vvmv.v.v vd, vs1 2 | VI_VV_MERGE_LOOP 3 | ({ 4 | vd = vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmv_v_x.h: -------------------------------------------------------------------------------- 1 | // vmv.v.x vd, rs1 2 | VI_VX_MERGE_LOOP 3 | ({ 4 | vd = rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vse8_v.h: -------------------------------------------------------------------------------- 1 | // vse8.v and vsseg[2-8]e8.v 2 | VI_ST(0, (i * nf + fn), uint8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse16_v.h: -------------------------------------------------------------------------------- 1 | // vsse16v and vssseg[2-8]e16.v 2 | VI_ST(i * RS2, fn, uint16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse32_v.h: -------------------------------------------------------------------------------- 1 | // vsse32.v and vssseg[2-8]e32.v 2 | VI_ST(i * RS2, fn, uint32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse64_v.h: -------------------------------------------------------------------------------- 1 | // vsse64.v and vssseg[2-8]e64.v 2 | VI_ST(i * RS2, fn, uint64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsse8_v.h: -------------------------------------------------------------------------------- 1 | // vsse8.v and vssseg[2-8]e8.v 2 | VI_ST(i * RS2, fn, uint8, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_addi.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_andi.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RVC_RS1S(RVC_RS1S & insn.rvc_imm()); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_sub.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RVC_RS1S(sext_xlen(RVC_RS1S - RVC_RS2S)); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_zext_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | WRITE_RVC_RS1S((reg_t)(uint8_t)(RVC_RS1S)); 3 | -------------------------------------------------------------------------------- /riscv/insns/lr_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALRSC); 2 | WRITE_RD(MMU.load_reserved(RS1)); 3 | -------------------------------------------------------------------------------- /riscv/insns/mul.h: -------------------------------------------------------------------------------- 1 | require_either_extension('M', EXT_ZMMUL); 2 | WRITE_RD(sext_xlen(RS1 * RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle16_v.h: -------------------------------------------------------------------------------- 1 | // vle16.v and vlseg[2-8]e16.v 2 | VI_LD(0, (i * nf + fn), int16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle32_v.h: -------------------------------------------------------------------------------- 1 | // vle32.v and vlseg[2-8]e32.v 2 | VI_LD(0, (i * nf + fn), int32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vle64_v.h: -------------------------------------------------------------------------------- 1 | // vle64.v and vlseg[2-8]e64.v 2 | VI_LD(0, (i * nf + fn), int64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmv_v_i.h: -------------------------------------------------------------------------------- 1 | // vmv.v.i vd, simm5 2 | VI_VI_MERGE_LOOP 3 | ({ 4 | vd = simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vse16_v.h: -------------------------------------------------------------------------------- 1 | // vse16.v and vsseg[2-8]e16.v 2 | VI_ST(0, (i * nf + fn), uint16, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vse32_v.h: -------------------------------------------------------------------------------- 1 | // vse32.v and vsseg[2-8]e32.v 2 | VI_ST(0, (i * nf + fn), uint32, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vse64_v.h: -------------------------------------------------------------------------------- 1 | // vse64.v and vsseg[2-8]e64.v 2 | VI_ST(0, (i * nf + fn), uint64, false); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vv.h: -------------------------------------------------------------------------------- 1 | // vsll 2 | VI_VV_ULOOP 3 | ({ 4 | vd = vs2 << (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vx.h: -------------------------------------------------------------------------------- 1 | // vsll 2 | VI_VX_ULOOP 3 | ({ 4 | vd = vs2 << (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/wrs_sto.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAWRS); 2 | 3 | // WRS.STO stalls for a short duration 4 | -------------------------------------------------------------------------------- /debug_rom/.gitignore: -------------------------------------------------------------------------------- 1 | /debug_rom 2 | /debug_rom32 3 | /debug_rom64 4 | /debug_rom32.h 5 | /debug_rom64.h 6 | -------------------------------------------------------------------------------- /riscv/insns/c_sspush_x1.h: -------------------------------------------------------------------------------- 1 | #include "zicfiss.h" 2 | 3 | if (xSSE()) { 4 | PUSH_VALUE_TO_SS(RA); 5 | } 6 | -------------------------------------------------------------------------------- /riscv/insns/fclass_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_classify(f128(FRS1))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmv_d_x.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_rv64; 3 | require_fp; 4 | WRITE_FRD(f64(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/fmv_h_x.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_INTERNAL_ZFH_MOVE); 2 | require_fp; 3 | WRITE_FRD(f16(RS1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmv_x_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_rv64; 3 | require_fp; 4 | WRITE_RD(FRS1.v[0]); 5 | -------------------------------------------------------------------------------- /riscv/insns/sd_rl.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZALASR); 3 | MMU.store(RS1, RS2); 4 | -------------------------------------------------------------------------------- /riscv/insns/vadd_vi.h: -------------------------------------------------------------------------------- 1 | // vadd.vi vd, simm5, vs2, vm 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vadd_vv.h: -------------------------------------------------------------------------------- 1 | // vadd.vv vd, vs1, vs2, vm 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vadd_vx.h: -------------------------------------------------------------------------------- 1 | // vadd.vx vd, rs1, vs2, vm 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vand_vi.h: -------------------------------------------------------------------------------- 1 | // vand.vi vd, simm5, vs2, vm 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 & vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vand_vv.h: -------------------------------------------------------------------------------- 1 | // vand.vv vd, vs1, vs2, vm 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 & vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vand_vx.h: -------------------------------------------------------------------------------- 1 | // vand.vx vd, rs1, vs2, vm 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 & vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmseq_vx.h: -------------------------------------------------------------------------------- 1 | // vseq.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = rs1 == vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgt_vx.h: -------------------------------------------------------------------------------- 1 | // vsgt.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 > rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsle_vv.h: -------------------------------------------------------------------------------- 1 | // vsle.vv vd, vs2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 <= vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsle_vx.h: -------------------------------------------------------------------------------- 1 | // vsle.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 <= rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmslt_vv.h: -------------------------------------------------------------------------------- 1 | // vslt.vv vd, vd2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 < vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmslt_vx.h: -------------------------------------------------------------------------------- 1 | // vslt.vx vd, vs2, vs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 < rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsne_vv.h: -------------------------------------------------------------------------------- 1 | // vneq.vv vd, vs2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 != vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsne_vx.h: -------------------------------------------------------------------------------- 1 | // vsne.vx vd, vs2, rs1 2 | VI_VX_LOOP_CMP 3 | ({ 4 | res = vs2 != rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/xperm4.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBKX); 2 | WRITE_RD(sext_xlen(xperm(RS1, RS2, 2, xlen))); 3 | -------------------------------------------------------------------------------- /riscv/insns/xperm8.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBKX); 2 | WRITE_RD(sext_xlen(xperm(RS1, RS2, 3, xlen))); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_beqz.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | if (RVC_RS1S == 0) 3 | set_pc(pc + insn.rvc_b_imm()); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_bnez.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | if (RVC_RS1S != 0) 3 | set_pc(pc + insn.rvc_b_imm()); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_sb.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | MMU.store(RVC_RS1S + insn.rvc_lbimm(), RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(fsgnj128(FRS1, FRS2, true, false)); -------------------------------------------------------------------------------- /riscv/insns/ld_aq.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZALASR); 3 | WRITE_RD(MMU.load(RS1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/max.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(sreg_t(RS1) > sreg_t(RS2) ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/min.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | WRITE_RD(sext_xlen(sreg_t(RS1) < sreg_t(RS2) ? RS1 : RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/ori.h: -------------------------------------------------------------------------------- 1 | // prefetch.i/r/w hint when rd = 0 and i_imm[4:0] = 0/1/3 2 | WRITE_RD(insn.i_imm() | RS1); 3 | -------------------------------------------------------------------------------- /riscv/insns/vmseq_vi.h: -------------------------------------------------------------------------------- 1 | // vseq.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = simm5 == vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmseq_vv.h: -------------------------------------------------------------------------------- 1 | // vseq.vv vd, vs2, vs1 2 | VI_VV_LOOP_CMP 3 | ({ 4 | res = vs2 == vs1; 5 | }) 6 | 7 | -------------------------------------------------------------------------------- /riscv/insns/vmsgt_vi.h: -------------------------------------------------------------------------------- 1 | // vsgt.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = vs2 > simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgtu_vx.h: -------------------------------------------------------------------------------- 1 | // vsgtu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_CMP 3 | ({ 4 | res = vs2 > rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsle_vi.h: -------------------------------------------------------------------------------- 1 | // vsle.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = vs2 <= simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsleu_vv.h: -------------------------------------------------------------------------------- 1 | // vsleu.vv vd, vs2, vs1 2 | VI_VV_ULOOP_CMP 3 | ({ 4 | res = vs2 <= vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsleu_vx.h: -------------------------------------------------------------------------------- 1 | // vsleu.vx vd, vs2, rs1 2 | VI_VX_ULOOP_CMP 3 | ({ 4 | res = vs2 <= rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsltu_vv.h: -------------------------------------------------------------------------------- 1 | // vsltu.vv vd, vs2, vs1 2 | VI_VV_ULOOP_CMP 3 | ({ 4 | res = vs2 < vs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsltu_vx.h: -------------------------------------------------------------------------------- 1 | // vsltu.vx vd, vs2, vs1 2 | VI_VX_ULOOP_CMP 3 | ({ 4 | res = vs2 < rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsne_vi.h: -------------------------------------------------------------------------------- 1 | // vsne.vi vd, vs2, simm5 2 | VI_VI_LOOP_CMP 3 | ({ 4 | res = vs2 != simm5; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen(zext32(RS1) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_lh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lhimm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_sh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | MMU.store(RVC_RS1S + insn.rvc_lhimm(), RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_sw.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | MMU.store(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_swsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | MMU.store(RVC_SP + insn.rvc_swsp_imm(), RVC_RS2); 3 | -------------------------------------------------------------------------------- /riscv/insns/fsd.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | MMU.store(RS1 + insn.s_imm(), FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(fsgnj128(FRS1, FRS2, false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_FRD(fsgnj128(FRS1, FRS2, false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsw.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | MMU.store(RS1 + insn.s_imm(), FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/lr_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALRSC); 2 | require_rv64; 3 | WRITE_RD(MMU.load_reserved(RS1)); 4 | -------------------------------------------------------------------------------- /riscv/insns/mulw.h: -------------------------------------------------------------------------------- 1 | require_either_extension('M', EXT_ZMMUL); 2 | require_rv64; 3 | WRITE_RD(sext32(RS1 * RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/slli_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen(zext32(RS1) << SHAMT)); 4 | -------------------------------------------------------------------------------- /riscv/insns/vredand_vs.h: -------------------------------------------------------------------------------- 1 | // vredand.vs vd, vs2, vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res &= vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredor_vs.h: -------------------------------------------------------------------------------- 1 | // vredor.vs vd, vs2, vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res |= vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredsum_vs.h: -------------------------------------------------------------------------------- 1 | // vredsum.vs vd, vs2, vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res += vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredxor_vs.h: -------------------------------------------------------------------------------- 1 | // vredxor.vs vd, vs2, vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res ^= vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsetvl.h: -------------------------------------------------------------------------------- 1 | require_vector_novtype(false); 2 | WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsra_vv.h: -------------------------------------------------------------------------------- 1 | // vsra.vv vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs2 >> (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsra_vx.h: -------------------------------------------------------------------------------- 1 | // vsra.vx vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 >> (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsrl_vv.h: -------------------------------------------------------------------------------- 1 | // vsrl.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | vd = vs2 >> (vs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsrl_vx.h: -------------------------------------------------------------------------------- 1 | // vsrl.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | vd = vs2 >> (rs1 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/beqi.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZIBI); 2 | 3 | if (RS1 == insn.b_imm5()) { 4 | set_pc(BRANCH_TARGET); 5 | } 6 | -------------------------------------------------------------------------------- /riscv/insns/bnei.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZIBI); 2 | 3 | if (RS1 != insn.b_imm5()) { 4 | set_pc(BRANCH_TARGET); 5 | } 6 | -------------------------------------------------------------------------------- /riscv/insns/c_addw.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require_rv64; 3 | WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_lbu.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lbimm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_lhu.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lhimm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_lw.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | WRITE_RVC_RS2S(MMU.load(RVC_RS1S + insn.rvc_lw_imm())); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_subw.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require_rv64; 3 | WRITE_RVC_RS1S(sext32(RVC_RS1S - RVC_RS2S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fclass_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_RD(f64_classify(FRS1_D)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fclass_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_RD(f32_classify(FRS1_F)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fld.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_fp; 3 | WRITE_FRD(f64(MMU.load(RS1 + insn.i_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/flw.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_fp; 3 | WRITE_FRD(f32(MMU.load(RS1 + insn.i_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/vsll_vi.h: -------------------------------------------------------------------------------- 1 | // vsll.vi vd, vs2, zimm5 2 | VI_VI_ULOOP 3 | ({ 4 | vd = vs2 << (zimm5 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsrl_vi.h: -------------------------------------------------------------------------------- 1 | // vsrl.vi vd, vs2, zimm5 2 | VI_VI_ULOOP 3 | ({ 4 | vd = vs2 >> (zimm5 & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsub_vx.h: -------------------------------------------------------------------------------- 1 | // vsub: vd[i] = (vd[i] * x[rs1]) - vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = vs2 - rs1; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/amocas_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZACAS); 2 | WRITE_RD(sext32(MMU.amo_compare_and_swap(RS1, RD, RS2))); 3 | -------------------------------------------------------------------------------- /riscv/insns/bext.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(1 & (RS1 >> shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/fclass_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_RD(f16_classify(FRS1_H)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fmv_x_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_INTERNAL_ZFH_MOVE); 2 | require_fp; 3 | WRITE_RD(sext32((int16_t)(FRS1.v[0]))); 4 | -------------------------------------------------------------------------------- /riscv/insns/hfence_vvma.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(PRV_S); 4 | MMU.flush_tlb(); 5 | -------------------------------------------------------------------------------- /riscv/insns/sh1add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen((zext32(RS1) << 1) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/sh2add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen((zext32(RS1) << 2) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/sh3add_uw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBA); 3 | WRITE_RD(sext_xlen((zext32(RS1) << 3) + RS2)); 4 | -------------------------------------------------------------------------------- /riscv/insns/vfmerge_vfm.h: -------------------------------------------------------------------------------- 1 | // vfmerge_vf vd, vs2, vs1, vm 2 | VI_VF_MERGE_LOOP({ 3 | vd = use_first ? rs1 : vs2; 4 | }) 5 | -------------------------------------------------------------------------------- /riscv/insns/vmadd_vv.h: -------------------------------------------------------------------------------- 1 | // vmadd: vd[i] = (vd[i] * vs1[i]) + vs2[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = vd * vs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmadd_vx.h: -------------------------------------------------------------------------------- 1 | // vmadd: vd[i] = (vd[i] * x[rs1]) + vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = vd * rs1 + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmerge_vim.h: -------------------------------------------------------------------------------- 1 | // vmerge.vim vd, vs2, simm5 2 | VI_VI_MERGE_LOOP 3 | ({ 4 | vd = use_first ? simm5 : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmerge_vvm.h: -------------------------------------------------------------------------------- 1 | // vmerge.vvm vd, vs2, vs1 2 | VI_VV_MERGE_LOOP 3 | ({ 4 | vd = use_first ? vs1 : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmerge_vxm.h: -------------------------------------------------------------------------------- 1 | // vmerge.vxm vd, vs2, rs1 2 | VI_VX_MERGE_LOOP 3 | ({ 4 | vd = use_first ? rs1 : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsra_wv.h: -------------------------------------------------------------------------------- 1 | // vnsra.vv vd, vs2, vs1 2 | VI_VV_LOOP_NSHIFT 3 | ({ 4 | vd = vs2 >> (vs1 & (sew * 2 - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsra_wx.h: -------------------------------------------------------------------------------- 1 | // vnsra.vx vd, vs2, rs1 2 | VI_VX_LOOP_NSHIFT 3 | ({ 4 | vd = vs2 >> (rs1 & (sew * 2 - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsetivli.h: -------------------------------------------------------------------------------- 1 | require_vector_novtype(false); 2 | WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10())); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsetvli.h: -------------------------------------------------------------------------------- 1 | require_vector_novtype(false); 2 | WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); 3 | -------------------------------------------------------------------------------- /riscv/insns/vsra_vi.h: -------------------------------------------------------------------------------- 1 | // vsra.vi vd, vs2, zimm5 2 | VI_VI_LOOP 3 | ({ 4 | vd = vs2 >> (insn.v_zimm5() & (sew - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwredsum_vs.h: -------------------------------------------------------------------------------- 1 | // vwredsum.vs vd, vs2, vs1 2 | VI_VV_LOOP_WIDE_REDUCTION 3 | ({ 4 | vd_0_res += vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwredsumu_vs.h: -------------------------------------------------------------------------------- 1 | // vwredsum.vs vd, vs2, vs1 2 | VI_VV_ULOOP_WIDE_REDUCTION 3 | ({ 4 | vd_0_res += vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /.github/workflows/apt-packages.txt: -------------------------------------------------------------------------------- 1 | build-essential 2 | device-tree-compiler 3 | g++-riscv64-linux-gnu 4 | libc6-dev-riscv64-cross 5 | -------------------------------------------------------------------------------- /riscv/insns/bclr.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 & ~(1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/binv.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 ^ (1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/bset.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | int shamt = RS2 & (xlen-1); 3 | WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_sspopchk_x5.h: -------------------------------------------------------------------------------- 1 | #include "zicfiss.h" 2 | 3 | if (xSSE()) { 4 | POP_VALUE_FROM_SS_AND_CHECK(READ_REG(X_T0)); 5 | } 6 | -------------------------------------------------------------------------------- /riscv/insns/feq_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_eq(f128(FRS1), f128(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_le(f128(FRS1), f128(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flt_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | WRITE_RD(f128_lt(f128(FRS1), f128(FRS2))); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/vmacc_vv.h: -------------------------------------------------------------------------------- 1 | // vmacc.vv: vd[i] = +(vs1[i] * vs2[i]) + vd[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = vs1 * vs2 + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmacc_vx.h: -------------------------------------------------------------------------------- 1 | // vmacc.vx: vd[i] = +(x[rs1] * vs2[i]) + vd[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 * vs2 + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnmsac_vx.h: -------------------------------------------------------------------------------- 1 | // vmsac: vd[i] = -(x[rs1] * vs2[i]) + vd[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = -(rs1 * vs2) + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsra_wi.h: -------------------------------------------------------------------------------- 1 | // vnsra.vi vd, vs2, zimm5 2 | VI_VI_LOOP_NSHIFT 3 | ({ 4 | vd = vs2 >> (zimm5 & (sew * 2 - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsrl_wv.h: -------------------------------------------------------------------------------- 1 | // vnsrl.vv vd, vs2, vs1 2 | VI_VV_LOOP_NSHIFT 3 | ({ 4 | vd = vs2_u >> (vs1 & (sew * 2 - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsrl_wx.h: -------------------------------------------------------------------------------- 1 | // vnsrl.vx vd, vs2, rs1 2 | VI_VX_LOOP_NSHIFT 3 | ({ 4 | vd = vs2_u >> (rs1 & (sew * 2 - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vrsub_vi.h: -------------------------------------------------------------------------------- 1 | // vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i] 2 | VI_VI_LOOP 3 | ({ 4 | vd = simm5 - vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vrsub_vx.h: -------------------------------------------------------------------------------- 1 | // vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = rs1 - vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | *.gch 3 | autom4te.cache/ 4 | .*.swp 5 | *.o 6 | *.d 7 | .gdb_history 8 | .#* 9 | *~ 10 | config.log 11 | -------------------------------------------------------------------------------- /riscv/insns/amoor_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs | RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_fsd.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCD); 2 | require_fp; 3 | MMU.store(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_fsw.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCF); 2 | require_fp; 3 | MMU.store(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_sext_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | require_extension(EXT_ZBB); 3 | WRITE_RVC_RS1S((sreg_t)(int8_t)(RVC_RS1S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_sext_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | require_extension(EXT_ZBB); 3 | WRITE_RVC_RS1S((sreg_t)(int16_t)(RVC_RS1S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_zext_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | require_extension(EXT_ZBB); 3 | WRITE_RVC_RS1S((reg_t)(uint16_t)(RVC_RS1S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/cbo_zero.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICBOZ); 2 | DECLARE_XENVCFG_VARS(CBZE); 3 | require_envcfg(CBZE); 4 | MMU.cbo_zero(RS1); 5 | -------------------------------------------------------------------------------- /riscv/insns/cm_mva01s.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCMP); 2 | WRITE_REG(X_A0, READ_REG(RVC_R1S)); 3 | WRITE_REG(X_A1, READ_REG(RVC_R2S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_INTERNAL_ZFH_MOVE); 2 | require_fp; 3 | MMU.store(RS1 + insn.s_imm(), FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/vnmsac_vv.h: -------------------------------------------------------------------------------- 1 | // vmsac.vv: vd[i] = -(vs1[i] * vs2[i]) + vd[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = -(vs1 * vs2) + vd; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnmsub_vv.h: -------------------------------------------------------------------------------- 1 | // vnmsub.vv: vd[i] = -(vd[i] * vs1[i]) + vs2[i] 2 | VI_VV_LOOP 3 | ({ 4 | vd = -(vd * vs1) + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnmsub_vx.h: -------------------------------------------------------------------------------- 1 | // vnmsub.vx: vd[i] = -(vd[i] * x[rs1]) + vs2[i] 2 | VI_VX_LOOP 3 | ({ 4 | vd = -(vd * rs1) + vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vnsrl_wi.h: -------------------------------------------------------------------------------- 1 | // vnsrl.vi vd, vs2, zimm5 2 | VI_VI_LOOP_NSHIFT 3 | ({ 4 | vd = vs2_u >> (zimm5 & (sew * 2 - 1)); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/amoadd_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs + RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoadd_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs + RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoadd_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t lhs) { return lhs + RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoand_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs & RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoand_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs & RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoand_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t lhs) { return lhs & RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoor_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs | RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoor_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t lhs) { return lhs | RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoswap_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t UNUSED lhs) { return RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoswap_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t UNUSED lhs) { return RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoxor_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return lhs ^ RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoxor_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return lhs ^ RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoxor_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t lhs) { return lhs ^ RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_fld.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCD); 2 | require_fp; 3 | WRITE_RVC_FRS2S(f64(MMU.load(RVC_RS1S + insn.rvc_ld_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_fldsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCD); 2 | require_fp; 3 | WRITE_FRD(f64(MMU.load(RVC_SP + insn.rvc_ldsp_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_flw.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCF); 2 | require_fp; 3 | WRITE_RVC_FRS2S(f32(MMU.load(RVC_RS1S + insn.rvc_lw_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_flwsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCF); 2 | require_fp; 3 | WRITE_FRD(f32(MMU.load(RVC_SP + insn.rvc_lwsp_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_fsdsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCD); 2 | require_fp; 3 | MMU.store(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_fswsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCF); 2 | require_fp; 3 | MMU.store(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_slli.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require(insn.rvc_zimm() < xlen); 3 | WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/feq_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_RD(f64_eq(FRS1_D, FRS2_D)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/feq_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_RD(f32_eq(FRS1_F, FRS2_F)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_RD(f64_le(FRS1_D, FRS2_D)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_RD(f32_le(FRS1_F, FRS2_F)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_INTERNAL_ZFH_MOVE); 2 | require_fp; 3 | WRITE_FRD(f16(MMU.load(RS1 + insn.i_imm()))); 4 | -------------------------------------------------------------------------------- /riscv/insns/flt_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_RD(f64_lt(FRS1_D, FRS2_D)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flt_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_RD(f32_lt(FRS1_F, FRS2_F)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/vfwmaccbf16_vf.h: -------------------------------------------------------------------------------- 1 | // vfwmaccbf16.vf vd, vs2, rs1 2 | VI_VFP_BF16_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(rs1, vs2, vd); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vfwmaccbf16_vv.h: -------------------------------------------------------------------------------- 1 | // vfwmaccbf16.vv vd, vs2, vs1 2 | VI_VFP_BF16_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(vs1, vs2, vd); 5 | }) 6 | -------------------------------------------------------------------------------- /fesvr/dummy.cc: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | // help out poor, C-centric autoconf 4 | extern "C" void libfesvr_is_present() {} 5 | -------------------------------------------------------------------------------- /riscv/insns/amoswap_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t UNUSED lhs) { return RS2; }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/c_lwsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require(insn.rvc_rd() != 0); 3 | WRITE_RD(MMU.load(RVC_SP + insn.rvc_lwsp_imm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/feq_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_RD(f16_eq(FRS1_H, FRS2_H)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fle_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_RD(f16_le(FRS1_H, FRS2_H)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/flt_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_RD(f16_lt(FRS1_H, FRS2_H)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/sspush_x1.h: -------------------------------------------------------------------------------- 1 | #include "zicfiss.h" 2 | 3 | if (xSSE()) { 4 | PUSH_VALUE_TO_SS(RS2); 5 | } else { 6 | #include "mop_rr_N.h" 7 | } 8 | -------------------------------------------------------------------------------- /riscv/insns/vredmax_vs.h: -------------------------------------------------------------------------------- 1 | // vredmax.vs vd, vs2 ,vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredmin_vs.h: -------------------------------------------------------------------------------- 1 | // vredmin.vs vd, vs2, vs1 2 | VI_VV_LOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_wv.h: -------------------------------------------------------------------------------- 1 | // vwadd.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_wx.h: -------------------------------------------------------------------------------- 1 | // vwaddu.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_wv.h: -------------------------------------------------------------------------------- 1 | // vwaddu.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_wv.h: -------------------------------------------------------------------------------- 1 | // vwsub.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, -, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_wx.h: -------------------------------------------------------------------------------- 1 | // vwsub.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, -, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_wv.h: -------------------------------------------------------------------------------- 1 | // vwsubu.wv vd, vs2, vs1 2 | VI_CHECK_DDS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(vs1, -, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/amoadd_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t lhs) { return lhs + RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoand_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t lhs) { return lhs & RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoor_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t lhs) { return lhs | RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amoxor_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t lhs) { return lhs ^ RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_mul.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | require_either_extension('M', EXT_ZMMUL); 3 | WRITE_RVC_RS1S(sext_xlen(RVC_RS1S * RVC_RS2S)); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_zext_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCB); 2 | require_extension(EXT_ZBA); 3 | require_rv64; 4 | WRITE_RVC_RS1S((reg_t)(uint32_t)(RVC_RS1S)); 5 | -------------------------------------------------------------------------------- /riscv/insns/fmax_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_FRD_H(f16_max(FRS1_H, FRS2_H)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fmin_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_FRD_H(f16_min(FRS1_H, FRS2_H)); 4 | set_fp_exceptions; 5 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), true, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), true, false)); -------------------------------------------------------------------------------- /riscv/insns/fsgnjn_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), true, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/vdivu_vv.h: -------------------------------------------------------------------------------- 1 | // vdivu.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | if (vs1 == 0) 5 | vd = -1; 6 | else 7 | vd = vs2 / vs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vdivu_vx.h: -------------------------------------------------------------------------------- 1 | // vdivu.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | if (rs1 == 0) 5 | vd = -1; 6 | else 7 | vd = vs2 / rs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vredmaxu_vs.h: -------------------------------------------------------------------------------- 1 | // vredmaxu.vs vd, vs2, vs1 2 | VI_VV_ULOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vredminu_vs.h: -------------------------------------------------------------------------------- 1 | // vredminu.vs vd, vs2, vs1 2 | VI_VV_ULOOP_REDUCTION 3 | ({ 4 | vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_wx.h: -------------------------------------------------------------------------------- 1 | // vwaddu.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_wx.h: -------------------------------------------------------------------------------- 1 | // vwsubu.wx vd, vs2, rs1 2 | VI_CHECK_DDS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_WVX_OP(rs1, -, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/amomax_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return std::max(lhs, int8_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomin_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int8_t lhs) { return std::min(lhs, int8_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amoswap_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t UNUSED lhs) { return RS2; })); 4 | -------------------------------------------------------------------------------- /riscv/insns/bexti.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | require(SHAMT < xlen); 3 | int shamt = SHAMT & (xlen-1); 4 | WRITE_RD(sext_xlen(1 & (RS1 >> shamt))); 5 | -------------------------------------------------------------------------------- /riscv/insns/c_jr.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require(insn.rvc_rs1() != 0); 3 | set_pc(RVC_RS1 & ~reg_t(1)); 4 | 5 | maybe_set_elp(insn.rvc_rs1()); 6 | -------------------------------------------------------------------------------- /riscv/insns/cbo_clean.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICBOM); 2 | DECLARE_XENVCFG_VARS(CBCFE); 3 | require_envcfg(CBCFE); 4 | MMU.clean_inval(RS1, true, false); 5 | -------------------------------------------------------------------------------- /riscv/insns/cbo_flush.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICBOM); 2 | DECLARE_XENVCFG_VARS(CBCFE); 3 | require_envcfg(CBCFE); 4 | MMU.clean_inval(RS1, true, true); 5 | -------------------------------------------------------------------------------- /riscv/insns/fsgnj_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, false)); 4 | -------------------------------------------------------------------------------- /riscv/insns/fsgnjx_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, true)); 4 | -------------------------------------------------------------------------------- /riscv/insns/jalr.h: -------------------------------------------------------------------------------- 1 | CHECK_RD(); 2 | reg_t tmp = npc; 3 | set_pc((RS1 + insn.i_imm()) & ~reg_t(1)); 4 | WRITE_RD(tmp); 5 | 6 | maybe_set_elp(insn.rs1()); 7 | -------------------------------------------------------------------------------- /riscv/insns/vremu_vv.h: -------------------------------------------------------------------------------- 1 | // vremu.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | if (vs1 == 0) 5 | vd = vs2; 6 | else 7 | vd = vs2 % vs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vremu_vx.h: -------------------------------------------------------------------------------- 1 | // vremu.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | if (rs1 == 0) 5 | vd = vs2; 6 | else 7 | vd = vs2 % rs1; 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/amocas_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZACAS); 2 | require_extension(EXT_ZABHA); 3 | WRITE_RD(sreg_t(MMU.amo_compare_and_swap(RS1, RD, RS2))); 4 | -------------------------------------------------------------------------------- /riscv/insns/amocas_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZACAS); 2 | require_extension(EXT_ZABHA); 3 | WRITE_RD(sreg_t(MMU.amo_compare_and_swap(RS1, RD, RS2))); 4 | -------------------------------------------------------------------------------- /riscv/insns/amomax_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return std::max(lhs, int16_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomax_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomaxu_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint8_t lhs) { return std::max(lhs, uint8_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomaxu_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amomaxu_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint16_t lhs) { return std::max(lhs, uint16_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomaxu_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomin_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](int16_t lhs) { return std::min(lhs, int16_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amomin_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amominu_b.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint8_t lhs) { return std::min(lhs, uint8_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amominu_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amominu_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZABHA); 2 | WRITE_RD(sreg_t(MMU.amo(RS1, [&](uint16_t lhs) { return std::min(lhs, uint16_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/amominu_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | WRITE_RD(sext32(MMU.amo(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); }))); 3 | -------------------------------------------------------------------------------- /riscv/insns/bclri.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | require(SHAMT < xlen); 3 | int shamt = SHAMT & (xlen-1); 4 | WRITE_RD(sext_xlen(RS1 & ~(1LL << shamt))); 5 | -------------------------------------------------------------------------------- /riscv/insns/binvi.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | require(SHAMT < xlen); 3 | int shamt = SHAMT & (xlen-1); 4 | WRITE_RD(sext_xlen(RS1 ^ (1LL << shamt))); 5 | -------------------------------------------------------------------------------- /riscv/insns/bseti.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBS); 2 | require(SHAMT < xlen); 3 | int shamt = SHAMT & (xlen-1); 4 | WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); 5 | -------------------------------------------------------------------------------- /riscv/insns/c_srai.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require(insn.rvc_zimm() < xlen); 3 | WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_srli.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require(insn.rvc_zimm() < xlen); 3 | WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/cpop.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | reg_t x = 0; 3 | for (int i = 0; i < xlen; i++) 4 | if (1 & (RS1 >> i)) x++; 5 | WRITE_RD(sext_xlen(x)); 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_to_f64(f128(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_d.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f64_to_f128(f64(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_s.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f32_to_f128(f32(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_to_f32(f128(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fleq_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f64_le_quiet(FRS1_D, FRS2_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fleq_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f32_le_quiet(FRS1_F, FRS2_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fltq_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f64_lt_quiet(FRS1_D, FRS2_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fltq_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f32_lt_quiet(FRS1_F, FRS2_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_sqrt(f128(FRS1))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/sfence_inval_ir.h: -------------------------------------------------------------------------------- 1 | require_extension('S'); 2 | require_extension(EXT_SVINVAL); 3 | require(p->has_mmu()); 4 | require_privilege_hs_qualified(PRV_S); 5 | -------------------------------------------------------------------------------- /riscv/insns/sspopchk_x1.h: -------------------------------------------------------------------------------- 1 | #include "zicfiss.h" 2 | 3 | if (xSSE()) { 4 | POP_VALUE_FROM_SS_AND_CHECK(RS1); 5 | } else { 6 | #include "mop_r_N.h" 7 | } 8 | -------------------------------------------------------------------------------- /riscv/insns/ssrdp.h: -------------------------------------------------------------------------------- 1 | #include "zicfiss.h" 2 | 3 | if (xSSE()) { 4 | WRITE_RD(sext_xlen(STATE.ssp->read())); 5 | } else { 6 | #include "mop_r_N.h" 7 | } 8 | -------------------------------------------------------------------------------- /riscv/insns/vadc_vvm.h: -------------------------------------------------------------------------------- 1 | // vadc.vvm vd, vs2, rs1, v0 2 | VI_VV_LOOP_WITH_CARRY 3 | ({ 4 | vd = (uint128_t)((op_mask & vs1) + (op_mask & vs2) + carry); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vadc_vxm.h: -------------------------------------------------------------------------------- 1 | // vadc.vxm vd, vs2, rs1, v0 2 | VI_XI_LOOP_WITH_CARRY 3 | ({ 4 | vd = (uint128_t)((op_mask & rs1) + (op_mask & vs2) + carry); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vxm.h: -------------------------------------------------------------------------------- 1 | // vadc.vx vd, vs2, rs1, v0 2 | VI_XI_LOOP_CARRY 3 | ({ 4 | res = (((op_mask & rs1) + (op_mask & vs2) + carry) >> sew) & 0x1u; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsgtu_vi.h: -------------------------------------------------------------------------------- 1 | // vmsgtu.vi vd, vd2, simm5 2 | VI_VI_ULOOP_CMP 3 | ({ 4 | res = vs2 > (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsleu_vi.h: -------------------------------------------------------------------------------- 1 | // vmsleu.vi vd, vs2, simm5 2 | VI_VI_ULOOP_CMP 3 | ({ 4 | res = vs2 <= (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsbc_vvm.h: -------------------------------------------------------------------------------- 1 | // vsbc.vvm vd, vs2, rs1, v0 2 | VI_VV_LOOP_WITH_CARRY 3 | ({ 4 | vd = (uint128_t)((op_mask & vs2) - (op_mask & vs1) - carry); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vsbc_vxm.h: -------------------------------------------------------------------------------- 1 | // vsbc.vxm vd, vs2, rs1, v0 2 | VI_XI_LOOP_WITH_CARRY 3 | ({ 4 | vd = (uint128_t)((op_mask & vs2) - (op_mask & rs1) - carry); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_vv.h: -------------------------------------------------------------------------------- 1 | // vwadd.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmul_vv.h: -------------------------------------------------------------------------------- 1 | // vwmul.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_vv.h: -------------------------------------------------------------------------------- 1 | // vwsub.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /disasm/disasm.mk.in: -------------------------------------------------------------------------------- 1 | disasm_srcs = \ 2 | disasm.cc \ 3 | isa_parser.cc \ 4 | regnames.cc \ 5 | 6 | disasm_install_lib = yes 7 | 8 | disasm_install_pcs = yes 9 | -------------------------------------------------------------------------------- /riscv/insns/c_addi4spn.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require(insn.rvc_addi4spn_imm() != 0); 3 | WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm())); 4 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_w.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(i32_to_f128((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_wu.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(ui32_to_f128((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fleq_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f16_le_quiet(FRS1_H, FRS2_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fltq_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f16_lt_quiet(FRS1_H, FRS2_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/sc_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALRSC); 2 | 3 | bool have_reservation = MMU.store_conditional(RS1, RS2); 4 | 5 | WRITE_RD(!have_reservation); 6 | -------------------------------------------------------------------------------- /riscv/insns/vadc_vim.h: -------------------------------------------------------------------------------- 1 | // vadc.vim vd, vs2, simm5, v0 2 | VI_XI_LOOP_WITH_CARRY 3 | ({ 4 | vd = (uint128_t)((op_mask & simm5) + (op_mask & vs2) + carry); 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_vf.h: -------------------------------------------------------------------------------- 1 | // vfwadd.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_wf.h: -------------------------------------------------------------------------------- 1 | // vfwadd.wf vd, vs2, vs1 2 | VI_VFP_WF_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_wv.h: -------------------------------------------------------------------------------- 1 | // vfwadd.wv vd, vs2, vs1 2 | VI_VFP_WV_LOOP_WIDE 3 | ({ 4 | vd = f32_add(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_add(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmul_vf.h: -------------------------------------------------------------------------------- 1 | // vfwmul.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mul(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_mul(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmul_vv.h: -------------------------------------------------------------------------------- 1 | // vfwmul.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mul(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_mul(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_vf.h: -------------------------------------------------------------------------------- 1 | // vfwsub.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_vv.h: -------------------------------------------------------------------------------- 1 | // vfwsub.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_wf.h: -------------------------------------------------------------------------------- 1 | // vfwsub.wf vd, vs2, rs1 2 | VI_VFP_WF_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, rs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, rs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwsub_wv.h: -------------------------------------------------------------------------------- 1 | // vfwsub.wv vd, vs2, vs1 2 | VI_VFP_WV_LOOP_WIDE 3 | ({ 4 | vd = f32_sub(vs2, vs1); 5 | }, 6 | { 7 | vd = f64_sub(vs2, vs1); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vvm.h: -------------------------------------------------------------------------------- 1 | // vmadc.vvm vd, vs2, rs1, v0 2 | VI_VV_LOOP_CARRY 3 | ({ 4 | res = (((op_mask & vs1) + (op_mask & vs2) + carry) >> sew) & 0x1u; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsbc_vvm.h: -------------------------------------------------------------------------------- 1 | // vmsbc.vvm vd, vs2, rs1, v0 2 | VI_VV_LOOP_CARRY 3 | ({ 4 | res = (((op_mask & vs2) - (op_mask & vs1) - carry) >> sew) & 0x1u; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vmsbc_vxm.h: -------------------------------------------------------------------------------- 1 | // vmsbc.vxm vd, vs2, rs1, v0 2 | VI_XI_LOOP_CARRY 3 | ({ 4 | res = (((op_mask & vs2) - (op_mask & rs1) - carry) >> sew) & 0x1u; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwadd_vx.h: -------------------------------------------------------------------------------- 1 | // vwadd.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_vv.h: -------------------------------------------------------------------------------- 1 | // vwaddu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwaddu_vx.h: -------------------------------------------------------------------------------- 1 | // vwaddu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmacc_vv.h: -------------------------------------------------------------------------------- 1 | // vwmacc.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmul_vx.h: -------------------------------------------------------------------------------- 1 | // vwmul.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmulu_vv.h: -------------------------------------------------------------------------------- 1 | // vwmulu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmulu_vx.h: -------------------------------------------------------------------------------- 1 | // vwmul.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsub_vx.h: -------------------------------------------------------------------------------- 1 | // vwsub.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_vv.h: -------------------------------------------------------------------------------- 1 | // vwsubu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwsubu_vx.h: -------------------------------------------------------------------------------- 1 | // vwsubu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/amomax_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/amomin_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAAMO); 2 | require_rv64; 3 | WRITE_RD(MMU.amo(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); })); 4 | -------------------------------------------------------------------------------- /riscv/insns/c_jalr.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | reg_t tmp = npc; 3 | set_pc(RVC_RS1 & ~reg_t(1)); 4 | WRITE_REG(X_RA, tmp); 5 | 6 | maybe_set_elp(insn.rvc_rs1()); 7 | -------------------------------------------------------------------------------- /riscv/insns/fadd_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_add(f128(FRS1), f128(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_bf16_s.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFBFMIN); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_BF(f32_to_bf16(FRS1_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_l.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD(i64_to_f128(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_bf16.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFBFMIN); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(bf16_to_f32(FRS1_BF)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fdiv_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_div(f128(FRS1), f128(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fleq_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f128_le_quiet(f128(FRS1), f128(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fltq_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_RD(f128_lt_quiet(f128(FRS1), f128(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmul_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_mul(f128(FRS1), f128(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fround_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD_D(f64_roundToInt(FRS1_D, RM, false)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fround_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD_F(f32_roundToInt(FRS1_F, RM, false)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsq.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | uint128_t v = FRS2.v[0] | (uint128_t(FRS2.v[1]) << 64); 4 | MMU.store(RS1 + insn.s_imm(), v); 5 | -------------------------------------------------------------------------------- /riscv/insns/fsub_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_sub(f128(FRS1), f128(FRS2))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/vmadc_vim.h: -------------------------------------------------------------------------------- 1 | // vmadc.vim vd, vs2, simm5, v0 2 | VI_XI_LOOP_CARRY 3 | ({ 4 | res = (((op_mask & simm5) + (op_mask & vs2) + carry) >> sew) & 0x1u; 5 | }) 6 | -------------------------------------------------------------------------------- /riscv/insns/vwmacc_vx.h: -------------------------------------------------------------------------------- 1 | // vwmacc.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmaccu_vv.h: -------------------------------------------------------------------------------- 1 | // vwmaccu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmaccu_vx.h: -------------------------------------------------------------------------------- 1 | // vwmaccu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/cpopw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBB); 3 | reg_t x = 0; 4 | for (int i = 0; i < 32; i++) 5 | if (1 & (RS1 >> i)) x++; 6 | WRITE_RD(sext32(x)); 7 | -------------------------------------------------------------------------------- /riscv/insns/ctz.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | reg_t x = xlen; 3 | for (int i = 0; i < xlen; i++) 4 | if (1 & (RS1 >> i)) { x = i; break; } 5 | WRITE_RD(sext_xlen(x)); 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f32_to_f64(FRS1_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_lu.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD(ui64_to_f128(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f64_to_f32(FRS1_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fround_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD_H(f16_roundToInt(FRS1_H, RM, false)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fround_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD(f128_roundToInt(f128(FRS1), RM, false)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/froundnx_d.h: -------------------------------------------------------------------------------- 1 | require_extension('D'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD_D(f64_roundToInt(FRS1_D, RM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/froundnx_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFH); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD_H(f16_roundToInt(FRS1_H, RM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/froundnx_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD(f128_roundToInt(f128(FRS1), RM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/froundnx_s.h: -------------------------------------------------------------------------------- 1 | require_extension('F'); 2 | require_extension(EXT_ZFA); 3 | require_fp; 4 | WRITE_FRD_F(f32_roundToInt(FRS1_F, RM, true)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_sqrt(FRS1_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_sqrt(FRS1_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsqrt_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_sqrt(FRS1_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/csrrw.h: -------------------------------------------------------------------------------- 1 | int csr = validate_csr(insn.csr(), true); 2 | reg_t old = p->get_csr(csr, insn, true); 3 | p->put_csr(csr, RS1); 4 | WRITE_RD(sext_xlen(old)); 5 | serialize(); 6 | -------------------------------------------------------------------------------- /riscv/insns/fadd_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_add(FRS1_D, FRS2_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fadd_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_add(FRS1_F, FRS2_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_w.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(i32_to_f64((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_w.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(i32_to_f32((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_w_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f128_to_i32(f128(FRS1), RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_wu_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f128_to_ui32(f128(FRS1), RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fdiv_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_div(FRS1_D, FRS2_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fdiv_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_div(FRS1_F, FRS2_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmul_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_mul(FRS1_D, FRS2_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmul_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_mul(FRS1_F, FRS2_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmvh_x_q.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension('Q'); 3 | require_extension(EXT_ZFA); 4 | require_fp; 5 | ui128_f128 ui; 6 | ui.f = f128(FRS1); 7 | WRITE_RD(ui.ui.v64); 8 | -------------------------------------------------------------------------------- /riscv/insns/fsub_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_sub(FRS1_D, FRS2_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fsub_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_sub(FRS1_F, FRS2_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/hfence_gvma.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.mstatus->read(), MSTATUS_TVM) ? PRV_M : PRV_S); 4 | MMU.flush_tlb(); 5 | -------------------------------------------------------------------------------- /riscv/insns/vfwmacc_vf.h: -------------------------------------------------------------------------------- 1 | // vfwmacc.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(rs1, vs2, vd); 5 | }, 6 | { 7 | vd = f64_mulAdd(rs1, vs2, vd); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmacc_vv.h: -------------------------------------------------------------------------------- 1 | // vfwmacc.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(vs1, vs2, vd); 5 | }, 6 | { 7 | vd = f64_mulAdd(vs1, vs2, vd); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vmulh_vv.h: -------------------------------------------------------------------------------- 1 | // vmulh vd, vs2, vs1 2 | require(p->extension_enabled('V') || P.VU.vsew < e64); 3 | 4 | VI_VV_LOOP 5 | ({ 6 | vd = ((int128_t)vs2 * vs1) >> sew; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vmulh_vx.h: -------------------------------------------------------------------------------- 1 | // vmulh vd, vs2, rs1 2 | require(p->extension_enabled('V') || P.VU.vsew < e64); 3 | 4 | VI_VX_LOOP 5 | ({ 6 | vd = ((int128_t)vs2 * rs1) >> sew; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vwmulsu_vv.h: -------------------------------------------------------------------------------- 1 | // vwmulsu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, 0, *, +, uint, int, uint) 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmulsu_vx.h: -------------------------------------------------------------------------------- 1 | // vwmulsu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, 0, *, +, uint, int, uint) 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/clz.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBB); 2 | reg_t x = xlen; 3 | for (int i = 0; i < xlen; i++) 4 | if (1 & (RS1 >> (xlen-i-1))) { x = i; break; } 5 | WRITE_RD(sext_xlen(x)); 6 | -------------------------------------------------------------------------------- /riscv/insns/cm_mvsa01.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCMP); 2 | require(insn.rvc_r1sc() != insn.rvc_r2sc()); 3 | WRITE_REG(RVC_R1S, READ_REG(X_A0)); 4 | WRITE_REG(RVC_R2S, READ_REG(X_A1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/ctzw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBB); 3 | reg_t x = 32; 4 | for (int i = 0; i < 32; i++) 5 | if (1 & (RS1 >> i)) { x = i; break; } 6 | WRITE_RD(sext32(x)); 7 | -------------------------------------------------------------------------------- /riscv/insns/fadd_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_add(FRS1_H, FRS2_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_wu.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(ui32_to_f64((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f32_to_f16(FRS1_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_w.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(i32_to_f16((int32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f16_to_f32(FRS1_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_wu.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(ui32_to_f32((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fdiv_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_div(FRS1_H, FRS2_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmadd_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128(FRS3))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmul_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_mul(FRS1_H, FRS2_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmvh_x_d.h: -------------------------------------------------------------------------------- 1 | require_rv32; 2 | require_extension('D'); 3 | require_extension(EXT_ZFA); 4 | require_fp; 5 | ui64_f64 ui; 6 | ui.f = FRS1_D; 7 | WRITE_RD(sext32(ui.ui >> 32)); 8 | -------------------------------------------------------------------------------- /riscv/insns/fsub_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_sub(FRS1_H, FRS2_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/mulh.h: -------------------------------------------------------------------------------- 1 | require_either_extension('M', EXT_ZMMUL); 2 | if (xlen == 64) 3 | WRITE_RD(mulh(RS1, RS2)); 4 | else 5 | WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32)); 6 | -------------------------------------------------------------------------------- /riscv/insns/sc_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZALRSC); 2 | require_rv64; 3 | 4 | bool have_reservation = MMU.store_conditional(RS1, RS2); 5 | 6 | WRITE_RD(!have_reservation); 7 | -------------------------------------------------------------------------------- /riscv/insns/vandn_vv.h: -------------------------------------------------------------------------------- 1 | // vandn.vv vd, vs2, vs1, vm 2 | 3 | #include "zvk_ext_macros.h" 4 | 5 | require_zvkb; 6 | 7 | VI_VV_LOOP 8 | ({ 9 | vd = vs2 & (~vs1); 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vandn_vx.h: -------------------------------------------------------------------------------- 1 | // vandn.vx vd, vs2, rs1, vm 2 | 3 | #include "zvk_ext_macros.h" 4 | 5 | require_zvkb; 6 | 7 | VI_VX_LOOP 8 | ({ 9 | vd = vs2 & (~rs1); 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vmulhu_vv.h: -------------------------------------------------------------------------------- 1 | // vmulhu vd, vs2, vs1 2 | require(p->extension_enabled('V') || P.VU.vsew < e64); 3 | 4 | VI_VV_ULOOP 5 | ({ 6 | vd = ((uint128_t)vs2 * vs1) >> sew; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vmulhu_vx.h: -------------------------------------------------------------------------------- 1 | // vmulhu vd ,vs2, rs1 2 | require(p->extension_enabled('V') || P.VU.vsew < e64); 3 | 4 | VI_VX_ULOOP 5 | ({ 6 | vd = ((uint128_t)vs2 * rs1) >> sew; 7 | }) 8 | -------------------------------------------------------------------------------- /riscv/insns/vwmaccsu_vv.h: -------------------------------------------------------------------------------- 1 | // vwmaccsu.vv vd, vs2, vs1 2 | VI_CHECK_DSS(true); 3 | VI_VV_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, vd_w, *, +, int, uint, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmaccsu_vx.h: -------------------------------------------------------------------------------- 1 | // vwmaccsu.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, uint, int); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vwmaccus_vx.h: -------------------------------------------------------------------------------- 1 | // vwmaccus.vx vd, vs2, rs1 2 | VI_CHECK_DSS(false); 3 | VI_VX_LOOP_WIDEN 4 | ({ 5 | VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, int, uint); 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/clzw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZBB); 3 | reg_t x = 32; 4 | for (int i = 0; i < 32; i++) 5 | if (1 & (RS1 >> (31-i))) { x = i; break; } 6 | WRITE_RD(sext32(x)); 7 | -------------------------------------------------------------------------------- /riscv/insns/csrrwi.h: -------------------------------------------------------------------------------- 1 | int csr = validate_csr(insn.csr(), true); 2 | reg_t old = p->get_csr(csr, insn, true); 3 | p->put_csr(csr, insn.rs1()); 4 | WRITE_RD(sext_xlen(old)); 5 | serialize(); 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_l.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_D(i64_to_f64(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_wu.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(ui32_to_f16((uint32_t)RS1)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_l_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f128_to_i64(f128(FRS1), RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_lu_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f128_to_ui64(f128(FRS1), RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_l.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_F(i64_to_f32(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_w_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f64_to_i32(FRS1_D, RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_w_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f32_to_i32(FRS1_F, RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/flq.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | uint128_t v = MMU.load(RS1 + insn.i_imm()); 4 | float128_t f = { uint64_t(v), uint64_t(v >> 64) }; 5 | WRITE_FRD(f); 6 | -------------------------------------------------------------------------------- /riscv/insns/fmadd_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, FRS3_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmadd_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, FRS3_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /ci-tests/dummy-slliuw.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() { 4 | // as if slli.uw zero, t1, 3 5 | asm(".4byte 0x0833101b"); 6 | printf("Executed successfully\n"); 7 | return 0; 8 | } 9 | -------------------------------------------------------------------------------- /fesvr/term.h: -------------------------------------------------------------------------------- 1 | #ifndef _TERM_H 2 | #define _TERM_H 3 | 4 | class canonical_terminal_t 5 | { 6 | public: 7 | static int read(); 8 | static void write(char); 9 | }; 10 | 11 | #endif 12 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_lu.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_D(ui64_to_f64(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_l.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_H(i64_to_f16(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_lu.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_H(ui64_to_f16(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_q.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFHMIN); 2 | require_extension('Q'); 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD(f128_to_f16(f128(FRS1))); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_q_h.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZFHMIN); 2 | require_extension('Q'); 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD(f16_to_f128(f16(FRS1))); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_s_lu.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_F(ui64_to_f32(RS1)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_w_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f16_to_i32(FRS1_H, RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_wu_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f64_to_ui32(FRS1_D, RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_wu_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f16_to_ui32(FRS1_H, RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_wu_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_RD(sext32(f32_to_ui32(FRS1_F, RM, true))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmadd_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, FRS3_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmsub_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128_negate(f128(FRS3)))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/hlv_b.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(MMU.guest_load(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/hlv_h.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(MMU.guest_load(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/hlv_w.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(MMU.guest_load(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/hsv_b.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | MMU.guest_store(RS1, RS2); 5 | -------------------------------------------------------------------------------- /riscv/insns/hsv_h.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | MMU.guest_store(RS1, RS2); 5 | -------------------------------------------------------------------------------- /riscv/insns/hsv_w.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | MMU.guest_store(RS1, RS2); 5 | -------------------------------------------------------------------------------- /riscv/insns/mulhsu.h: -------------------------------------------------------------------------------- 1 | require_either_extension('M', EXT_ZMMUL); 2 | if (xlen == 64) 3 | WRITE_RD(mulhsu(RS1, RS2)); 4 | else 5 | WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32)); 6 | -------------------------------------------------------------------------------- /riscv/insns/packh.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBKB); 2 | reg_t lo = zext_xlen(RS1 << (xlen-8)) >> (xlen-8); 3 | reg_t hi = zext_xlen(RS2 << (xlen-8)) >> (xlen-16); 4 | WRITE_RD(sext_xlen(lo | hi)); 5 | -------------------------------------------------------------------------------- /riscv/insns/vmaxu_vv.h: -------------------------------------------------------------------------------- 1 | // vmaxu.vv vd, vs2, vs1, vm # Vector-vector 2 | VI_VV_ULOOP 3 | ({ 4 | if (vs1 >= vs2) { 5 | vd = vs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | }) 10 | -------------------------------------------------------------------------------- /riscv/insns/vmaxu_vx.h: -------------------------------------------------------------------------------- 1 | // vmaxu.vx vd, vs2, rs1, vm # vector-scalar 2 | VI_VX_ULOOP 3 | ({ 4 | if (rs1 >= vs2) { 5 | vd = rs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | }) 10 | -------------------------------------------------------------------------------- /riscv/insns/vminu_vv.h: -------------------------------------------------------------------------------- 1 | // vminu.vv vd, vs2, vs1, vm # Vector-vector 2 | VI_VV_ULOOP 3 | ({ 4 | if (vs1 <= vs2) { 5 | vd = vs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | }) 10 | -------------------------------------------------------------------------------- /riscv/insns/vmulhsu_vv.h: -------------------------------------------------------------------------------- 1 | // vmulhsu.vv vd, vs2, vs1 2 | require(p->extension_enabled('V') || P.VU.vsew < e64); 3 | 4 | VI_VV_SU_LOOP({ 5 | vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew; 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/vmulhsu_vx.h: -------------------------------------------------------------------------------- 1 | // vmulhsu.vx vd, vs2, rs1 2 | require(p->extension_enabled('V') || P.VU.vsew < e64); 3 | 4 | VI_VX_SU_LOOP({ 5 | vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew; 6 | }) 7 | -------------------------------------------------------------------------------- /riscv/insns/divu.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | reg_t lhs = zext_xlen(RS1); 3 | reg_t rhs = zext_xlen(RS2); 4 | if (rhs == 0) 5 | WRITE_RD(UINT64_MAX); 6 | else 7 | WRITE_RD(sext_xlen(lhs / rhs)); 8 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_l_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f64_to_i64(FRS1_D, RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_l_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f32_to_i64(FRS1_F, RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fmvp_q_x.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension('Q'); 3 | require_extension(EXT_ZFA); 4 | require_fp; 5 | ui128_f128 ui; 6 | ui.ui.v64 = RS2; 7 | ui.ui.v0 = RS1; 8 | WRITE_FRD(f128(ui.f)); 9 | -------------------------------------------------------------------------------- /riscv/insns/fnmsub_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128(FRS3))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/hlv_bu.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(MMU.guest_load(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/hlv_hu.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(MMU.guest_load(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/hlvx_hu.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(MMU.guest_load_x(RS1)); 5 | -------------------------------------------------------------------------------- /riscv/insns/vmax_vv.h: -------------------------------------------------------------------------------- 1 | // vmax.vv vd, vs2, vs1, vm # Vector-vector 2 | VI_VV_LOOP 3 | ({ 4 | if (vs1 >= vs2) { 5 | vd = vs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vmax_vx.h: -------------------------------------------------------------------------------- 1 | // vmax.vx vd, vs2, rs1, vm # vector-scalar 2 | VI_VX_LOOP 3 | ({ 4 | if (rs1 >= vs2) { 5 | vd = rs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vminu_vx.h: -------------------------------------------------------------------------------- 1 | // vminu.vx vd, vs2, rs1, vm # vector-scalar 2 | VI_VX_ULOOP 3 | ({ 4 | if (rs1 <= vs2) { 5 | vd = rs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_l_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f16_to_i64(FRS1_H, RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_lu_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f64_to_ui64(FRS1_D, RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_lu_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f16_to_ui64(FRS1_H, RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_lu_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_rv64; 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_RD(f32_to_ui64(FRS1_F, RM, true)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/remu.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | reg_t lhs = zext_xlen(RS1); 3 | reg_t rhs = zext_xlen(RS2); 4 | if (rhs == 0) 5 | WRITE_RD(sext_xlen(RS1)); 6 | else 7 | WRITE_RD(sext_xlen(lhs % rhs)); 8 | -------------------------------------------------------------------------------- /riscv/insns/remw.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | require_rv64; 3 | sreg_t lhs = sext32(RS1); 4 | sreg_t rhs = sext32(RS2); 5 | if (rhs == 0) 6 | WRITE_RD(lhs); 7 | else 8 | WRITE_RD(sext32(lhs % rhs)); 9 | -------------------------------------------------------------------------------- /riscv/insns/rol.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | int shamt = RS2 & (xlen-1); 3 | int rshamt = -shamt & (xlen-1); 4 | WRITE_RD(sext_xlen((RS1 << shamt) | (zext_xlen(RS1) >> rshamt))); 5 | -------------------------------------------------------------------------------- /riscv/insns/rolw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_either_extension(EXT_ZBB, EXT_ZBKB); 3 | int shamt = RS2 & 31; 4 | int rshamt = -shamt & 31; 5 | WRITE_RD(sext32((RS1 << shamt) | (zext32(RS1) >> rshamt))); 6 | -------------------------------------------------------------------------------- /riscv/insns/ror.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | int shamt = RS2 & (xlen-1); 3 | int rshamt = -shamt & (xlen-1); 4 | WRITE_RD(sext_xlen((RS1 << rshamt) | (zext_xlen(RS1) >> shamt))); 5 | -------------------------------------------------------------------------------- /riscv/insns/rorw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_either_extension(EXT_ZBB, EXT_ZBKB); 3 | int shamt = RS2 & 31; 4 | int rshamt = -shamt & 31; 5 | WRITE_RD(sext32((RS1 << rshamt) | (zext32(RS1) >> shamt))); 6 | -------------------------------------------------------------------------------- /riscv/insns/vfwadd_vv.h: -------------------------------------------------------------------------------- 1 | // vfwadd.vv vd, vs2, vs1 2 | 3 | require_zvfbfa 4 | 5 | VI_VFP_VV_LOOP_WIDE 6 | ({ 7 | vd = f32_add(vs2, vs1); 8 | }, 9 | { 10 | vd = f64_add(vs2, vs1); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmin_vv.h: -------------------------------------------------------------------------------- 1 | // vmin.vv vd, vs2, vs1, vm # Vector-vector 2 | VI_VV_LOOP 3 | ({ 4 | if (vs1 <= vs2) { 5 | vd = vs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | 10 | 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmin_vx.h: -------------------------------------------------------------------------------- 1 | // vminx.vx vd, vs2, rs1, vm # vector-scalar 2 | VI_VX_LOOP 3 | ({ 4 | if (rs1 <= vs2) { 5 | vd = rs1; 6 | } else { 7 | vd = vs2; 8 | } 9 | 10 | 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/divuw.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | require_rv64; 3 | reg_t lhs = zext32(RS1); 4 | reg_t rhs = zext32(RS2); 5 | if (rhs == 0) 6 | WRITE_RD(UINT64_MAX); 7 | else 8 | WRITE_RD(sext32(lhs / rhs)); 9 | -------------------------------------------------------------------------------- /riscv/insns/fmsub_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, f64(FRS3_D.v ^ F64_SIGN))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fmsub_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fnmadd_q.h: -------------------------------------------------------------------------------- 1 | require_extension('Q'); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128_negate(f128(FRS3)))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fnmsub_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, FRS3_D)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fnmsub_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, FRS3_F)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/hsv_d.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_rv64; 3 | require_novirt(); 4 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 5 | MMU.guest_store(RS1, RS2); 6 | -------------------------------------------------------------------------------- /riscv/insns/mulhu.h: -------------------------------------------------------------------------------- 1 | require_either_extension('M', EXT_ZMMUL); 2 | if (xlen == 64) 3 | WRITE_RD(mulhu(RS1, RS2)); 4 | else 5 | WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32)); 6 | -------------------------------------------------------------------------------- /riscv/insns/ssamoswap_w.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICFISS); 2 | require_extension(EXT_ZAAMO); 3 | 4 | DECLARE_XENVCFG_VARS(SSE); 5 | require_envcfg(SSE); 6 | WRITE_RD(sext32(MMU.ssamoswap(RS1, RS2))); 7 | -------------------------------------------------------------------------------- /riscv/insns/divw.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | require_rv64; 3 | sreg_t lhs = sext32(RS1); 4 | sreg_t rhs = sext32(RS2); 5 | if (rhs == 0) 6 | WRITE_RD(UINT64_MAX); 7 | else 8 | WRITE_RD(sext32(lhs / rhs)); 9 | -------------------------------------------------------------------------------- /riscv/insns/fmsub_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, f16(FRS3_H.v ^ F16_SIGN))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fnmsub_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, FRS3_H)); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/hlv_d.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_rv64; 3 | require_novirt(); 4 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 5 | WRITE_RD(MMU.guest_load(RS1)); 6 | -------------------------------------------------------------------------------- /riscv/insns/hlv_wu.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_rv64; 3 | require_novirt(); 4 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 5 | WRITE_RD(MMU.guest_load(RS1)); 6 | -------------------------------------------------------------------------------- /riscv/insns/hlvx_wu.h: -------------------------------------------------------------------------------- 1 | require_extension('H'); 2 | require_novirt(); 3 | require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); 4 | WRITE_RD(sext_xlen(MMU.guest_load_x(RS1))); 5 | -------------------------------------------------------------------------------- /riscv/insns/remuw.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | require_rv64; 3 | reg_t lhs = zext32(RS1); 4 | reg_t rhs = zext32(RS2); 5 | if (rhs == 0) 6 | WRITE_RD(sext32(lhs)); 7 | else 8 | WRITE_RD(sext32(lhs % rhs)); 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmsac_vf.h: -------------------------------------------------------------------------------- 1 | // vfwmsac.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN)); 5 | }, 6 | { 7 | vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN)); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwmsac_vv.h: -------------------------------------------------------------------------------- 1 | // vfwmsac.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN)); 5 | }, 6 | { 7 | vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN)); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwnmsac_vf.h: -------------------------------------------------------------------------------- 1 | // vfwnmacc.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, vd); 5 | }, 6 | { 7 | vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, vd); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwnmsac_vv.h: -------------------------------------------------------------------------------- 1 | // vfwnmsac.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd); 5 | }, 6 | { 7 | vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vsaddu_vv.h: -------------------------------------------------------------------------------- 1 | // vsaddu vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | bool sat = false; 5 | vd = vs2 + vs1; 6 | 7 | sat = vd < vs2; 8 | vd |= -(vd < vs2); 9 | 10 | P_SET_OV(sat); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/fmvp_d_x.h: -------------------------------------------------------------------------------- 1 | require_rv32; 2 | require_extension('D'); 3 | require_extension(EXT_ZFA); 4 | require_fp; 5 | ui64_f64 ui; 6 | ui.ui = ((uint64_t)RS2) << 32; 7 | ui.ui |= zext32(RS1); 8 | WRITE_FRD_D(f64(ui.ui)); 9 | -------------------------------------------------------------------------------- /riscv/insns/ssamoswap_d.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZICFISS); 2 | require_extension(EXT_ZAAMO); 3 | require_rv64; 4 | 5 | DECLARE_XENVCFG_VARS(SSE); 6 | require_envcfg(SSE); 7 | WRITE_RD(MMU.ssamoswap(RS1, RS2)); 8 | -------------------------------------------------------------------------------- /riscv/insns/vfrsub_vf.h: -------------------------------------------------------------------------------- 1 | // vfsub.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP 3 | ({ 4 | vd = VFP_OP_16(sub, rs1, vs2); 5 | }, 6 | { 7 | vd = f32_sub(rs1, vs2); 8 | }, 9 | { 10 | vd = f64_sub(rs1, vs2); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmfeq_vf.h: -------------------------------------------------------------------------------- 1 | // vmfeq.vf vd, vs2, fs1 2 | VI_VFP_VF_LOOP_CMP 3 | ({ 4 | res = VFP_OP_16(eq, vs2, rs1); 5 | }, 6 | { 7 | res = f32_eq(vs2, rs1); 8 | }, 9 | { 10 | res = f64_eq(vs2, rs1); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmfge_vf.h: -------------------------------------------------------------------------------- 1 | // vmfge.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_CMP 3 | ({ 4 | res = VFP_OP_16(le, rs1, vs2); 5 | }, 6 | { 7 | res = f32_le(rs1, vs2); 8 | }, 9 | { 10 | res = f64_le(rs1, vs2); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmfgt_vf.h: -------------------------------------------------------------------------------- 1 | // vmfgt.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_CMP 3 | ({ 4 | res = VFP_OP_16(lt, rs1, vs2); 5 | }, 6 | { 7 | res = f32_lt(rs1, vs2); 8 | }, 9 | { 10 | res = f64_lt(rs1, vs2); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmfle_vf.h: -------------------------------------------------------------------------------- 1 | // vmfle.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_CMP 3 | ({ 4 | res = VFP_OP_16(le, vs2, rs1); 5 | }, 6 | { 7 | res = f32_le(vs2, rs1); 8 | }, 9 | { 10 | res = f64_le(vs2, rs1); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vmflt_vf.h: -------------------------------------------------------------------------------- 1 | // vmflt.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_CMP 3 | ({ 4 | res = VFP_OP_16(lt, vs2, rs1); 5 | }, 6 | { 7 | res = f32_lt(vs2, rs1); 8 | }, 9 | { 10 | res = f64_lt(vs2, rs1); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vsaddu_vx.h: -------------------------------------------------------------------------------- 1 | // vsaddu vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | bool sat = false; 5 | vd = vs2 + rs1; 6 | 7 | sat = vd < vs2; 8 | vd |= -(vd < vs2); 9 | 10 | P_SET_OV(sat); 11 | 12 | }) 13 | -------------------------------------------------------------------------------- /riscv/insns/clmulr.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZBC); 2 | reg_t a = zext_xlen(RS1), b = zext_xlen(RS2), x = 0; 3 | for (int i = 0; i < xlen; i++) 4 | if ((b >> i) & 1) 5 | x ^= a >> (xlen-i-1); 6 | WRITE_RD(sext_xlen(x)); 7 | -------------------------------------------------------------------------------- /riscv/insns/vfsqrt_v.h: -------------------------------------------------------------------------------- 1 | // vsqrt.v vd, vd2, vm 2 | VI_NON_ALTFMT_INSN 3 | 4 | VI_VFP_V_LOOP 5 | ({ 6 | vd = f16_sqrt(vs2); 7 | }, 8 | { 9 | vd = f32_sqrt(vs2); 10 | }, 11 | { 12 | vd = f64_sqrt(vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfwredusum_vs.h: -------------------------------------------------------------------------------- 1 | // vfwredsum.vs vd, vs2, vs1 2 | bool is_propagate = true; 3 | VI_VFP_VV_LOOP_WIDE_REDUCTION 4 | ({ 5 | vd_0 = f32_add(vd_0, vs2); 6 | }, 7 | { 8 | vd_0 = f64_add(vd_0, vs2); 9 | }) 10 | -------------------------------------------------------------------------------- /riscv/insns/vmfne_vf.h: -------------------------------------------------------------------------------- 1 | // vmfne.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_CMP 3 | ({ 4 | res = !VFP_OP_16(eq, vs2, rs1); 5 | }, 6 | { 7 | res = !f32_eq(vs2, rs1); 8 | }, 9 | { 10 | res = !f64_eq(vs2, rs1); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/clmul.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBC, EXT_ZBKC); 2 | reg_t a = zext_xlen(RS1), b = zext_xlen(RS2), x = 0; 3 | for (int i = 0; i < xlen; i++) 4 | if ((b >> i) & 1) 5 | x ^= a << i; 6 | WRITE_RD(sext_xlen(x)); 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_d_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); 2 | require_either_extension('D', EXT_ZDINX); 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_D(f16_to_f64(FRS1_H)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fcvt_h_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); 2 | require_either_extension('D', EXT_ZDINX); 3 | require_fp; 4 | softfloat_roundingMode = RM; 5 | WRITE_FRD_H(f64_to_f16(FRS1_D)); 6 | set_fp_exceptions; 7 | -------------------------------------------------------------------------------- /riscv/insns/fnmadd_d.h: -------------------------------------------------------------------------------- 1 | require_either_extension('D', EXT_ZDINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, f64(FRS3_D.v ^ F64_SIGN))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fnmadd_h.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZFH, EXT_ZHINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, f16(FRS3_H.v ^ F16_SIGN))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/fnmadd_s.h: -------------------------------------------------------------------------------- 1 | require_either_extension('F', EXT_ZFINX); 2 | require_fp; 3 | softfloat_roundingMode = RM; 4 | WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); 5 | set_fp_exceptions; 6 | -------------------------------------------------------------------------------- /riscv/insns/roriw.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_either_extension(EXT_ZBB, EXT_ZBKB); 3 | require(SHAMT < 32); 4 | int shamt = SHAMT & 31; 5 | int rshamt = -shamt & 31; 6 | WRITE_RD(sext32((RS1 << rshamt) | (zext32(RS1) >> shamt))); 7 | -------------------------------------------------------------------------------- /riscv/insns/sd.h: -------------------------------------------------------------------------------- 1 | require((xlen == 64) || p->extension_enabled(EXT_ZILSD)); 2 | 3 | if (xlen == 32) { 4 | MMU.store(RS1 + insn.s_imm(), RS2_PAIR); 5 | } else { 6 | MMU.store(RS1 + insn.s_imm(), RS2); 7 | } 8 | -------------------------------------------------------------------------------- /riscv/insns/vfwredosum_vs.h: -------------------------------------------------------------------------------- 1 | // vfwredosum.vs vd, vs2, vs1 2 | bool is_propagate = false; 3 | VI_VFP_VV_LOOP_WIDE_REDUCTION 4 | ({ 5 | vd_0 = f32_add(vd_0, vs2); 6 | }, 7 | { 8 | vd_0 = f64_add(vd_0, vs2); 9 | }) 10 | -------------------------------------------------------------------------------- /riscv/insns/rori.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBB, EXT_ZBKB); 2 | require(SHAMT < xlen); 3 | int shamt = SHAMT & (xlen-1); 4 | int rshamt = -shamt & (xlen-1); 5 | WRITE_RD(sext_xlen((RS1 << rshamt) | (zext_xlen(RS1) >> shamt))); 6 | -------------------------------------------------------------------------------- /riscv/insns/vfmax_vf.h: -------------------------------------------------------------------------------- 1 | // vfmax 2 | 3 | require_zvfbfa 4 | 5 | VI_VFP_VF_LOOP 6 | ({ 7 | vd = VFP_OP_16(max, vs2, rs1); 8 | }, 9 | { 10 | vd = f32_max(vs2, rs1); 11 | }, 12 | { 13 | vd = f64_max(vs2, rs1); 14 | }) 15 | -------------------------------------------------------------------------------- /riscv/insns/vfmax_vv.h: -------------------------------------------------------------------------------- 1 | // vfmax 2 | 3 | require_zvfbfa 4 | 5 | VI_VFP_VV_LOOP 6 | ({ 7 | vd = VFP_OP_16(max, vs2, vs1); 8 | }, 9 | { 10 | vd = f32_max(vs2, vs1); 11 | }, 12 | { 13 | vd = f64_max(vs2, vs1); 14 | }) 15 | -------------------------------------------------------------------------------- /riscv/insns/vfrec7_v.h: -------------------------------------------------------------------------------- 1 | // vfclass.v vd, vs2, vm 2 | VI_VFP_V_LOOP 3 | ({ 4 | vd = P.VU.altfmt ? bf16_recip7(vs2) : f16_recip7(vs2); 5 | }, 6 | { 7 | vd = f32_recip7(vs2); 8 | }, 9 | { 10 | vd = f64_recip7(vs2); 11 | }) 12 | -------------------------------------------------------------------------------- /customext/customext.mk.in: -------------------------------------------------------------------------------- 1 | customext_subproject_deps = \ 2 | spike_main \ 3 | riscv \ 4 | disasm \ 5 | softfloat \ 6 | 7 | customext_srcs = \ 8 | dummy_rocc.cc \ 9 | cflush.cc \ 10 | 11 | customext_install_shared_lib = yes 12 | -------------------------------------------------------------------------------- /riscv/insns/clmulh.h: -------------------------------------------------------------------------------- 1 | require_either_extension(EXT_ZBC, EXT_ZBKC); 2 | reg_t a = zext_xlen(RS1), b = zext_xlen(RS2), x = 0; 3 | for (int i = 1; i < xlen; i++) 4 | if ((b >> i) & 1) 5 | x ^= a >> (xlen-i); 6 | WRITE_RD(sext_xlen(x)); 7 | -------------------------------------------------------------------------------- /riscv/insns/vdiv_vv.h: -------------------------------------------------------------------------------- 1 | // vdiv.vv vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | if (vs1 == 0) 5 | vd = -1; 6 | else if (vs2 == (INT64_MIN >> (64 - sew)) && vs1 == -1) 7 | vd = vs2; 8 | else 9 | vd = vs2 / vs1; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vdiv_vx.h: -------------------------------------------------------------------------------- 1 | // vdiv.vx vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | if (rs1 == 0) 5 | vd = -1; 6 | else if (vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) 7 | vd = vs2; 8 | else 9 | vd = vs2 / rs1; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vfdiv_vf.h: -------------------------------------------------------------------------------- 1 | // vfdiv.vf vd, vs2, rs1 2 | VI_NON_ALTFMT_INSN 3 | 4 | VI_VFP_VF_LOOP 5 | ({ 6 | vd = f16_div(vs2, rs1); 7 | }, 8 | { 9 | vd = f32_div(vs2, rs1); 10 | }, 11 | { 12 | vd = f64_div(vs2, rs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfdiv_vv.h: -------------------------------------------------------------------------------- 1 | // vfdiv.vv vd, vs2, vs1 2 | VI_NON_ALTFMT_INSN 3 | 4 | VI_VFP_VV_LOOP 5 | ({ 6 | vd = f16_div(vs2, vs1); 7 | }, 8 | { 9 | vd = f32_div(vs2, vs1); 10 | }, 11 | { 12 | vd = f64_div(vs2, vs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/ld.h: -------------------------------------------------------------------------------- 1 | require((xlen == 64) || p->extension_enabled(EXT_ZILSD)); 2 | 3 | if (xlen == 32) { 4 | WRITE_RD_PAIR(MMU.load(RS1 + insn.i_imm())); 5 | } else { 6 | WRITE_RD(MMU.load(RS1 + insn.i_imm())); 7 | } 8 | 9 | -------------------------------------------------------------------------------- /riscv/insns/vfadd_vf.h: -------------------------------------------------------------------------------- 1 | // vfadd.vf vd, vs2, rs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VF_LOOP 5 | ({ 6 | vd = VFP_OP_16(add, vs2, rs1); 7 | }, 8 | { 9 | vd = f32_add(rs1, vs2); 10 | }, 11 | { 12 | vd = f64_add(rs1, vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfadd_vv.h: -------------------------------------------------------------------------------- 1 | // vfadd.vv vd, vs2, vs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP 5 | ({ 6 | vd = VFP_OP_16(add, vs2, vs1); 7 | }, 8 | { 9 | vd = f32_add(vs1, vs2); 10 | }, 11 | { 12 | vd = f64_add(vs1, vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfmin_vf.h: -------------------------------------------------------------------------------- 1 | // vfmin vd, vs2, rs1 2 | 3 | require_zvfbfa 4 | 5 | VI_VFP_VF_LOOP 6 | ({ 7 | vd = VFP_OP_16(min, vs2, rs1); 8 | }, 9 | { 10 | vd = f32_min(vs2, rs1); 11 | }, 12 | { 13 | vd = f64_min(vs2, rs1); 14 | }) 15 | -------------------------------------------------------------------------------- /riscv/insns/vfmin_vv.h: -------------------------------------------------------------------------------- 1 | // vfmin vd, vs2, vs1 2 | 3 | require_zvfbfa 4 | 5 | VI_VFP_VV_LOOP 6 | ({ 7 | vd = VFP_OP_16(min, vs2, vs1); 8 | }, 9 | { 10 | vd = f32_min(vs2, vs1); 11 | }, 12 | { 13 | vd = f64_min(vs2, vs1); 14 | }) 15 | -------------------------------------------------------------------------------- /riscv/insns/vfrsqrt7_v.h: -------------------------------------------------------------------------------- 1 | // vfrsqrt7.v vd, vs2, vm 2 | VI_VFP_V_LOOP 3 | ({ 4 | vd = P.VU.altfmt ? bf16_rsqrte7(vs2) : f16_rsqrte7(vs2); 5 | }, 6 | { 7 | vd = f32_rsqrte7(vs2); 8 | }, 9 | { 10 | vd = f64_rsqrte7(vs2); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vfsub_vf.h: -------------------------------------------------------------------------------- 1 | // vfsub.vf vd, vs2, rs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VF_LOOP 5 | ({ 6 | vd = VFP_OP_16(sub, vs2, rs1); 7 | }, 8 | { 9 | vd = f32_sub(vs2, rs1); 10 | }, 11 | { 12 | vd = f64_sub(vs2, rs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfsub_vv.h: -------------------------------------------------------------------------------- 1 | // vfsub.vv vd, vs2, vs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP 5 | ({ 6 | vd = VFP_OP_16(sub, vs2, vs1); 7 | }, 8 | { 9 | vd = f32_sub(vs2, vs1); 10 | }, 11 | { 12 | vd = f64_sub(vs2, vs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vrem_vx.h: -------------------------------------------------------------------------------- 1 | // vrem.vx vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | if (rs1 == 0) 5 | vd = vs2; 6 | else if (vs2 == -(((intmax_t)1) << (sew - 1)) && rs1 == -1) 7 | vd = 0; 8 | else 9 | vd = vs2 % rs1; 10 | }) 11 | -------------------------------------------------------------------------------- /spike_dasm/spike_dasm.mk.in: -------------------------------------------------------------------------------- 1 | spike_dasm_subproject_deps = \ 2 | disasm \ 3 | softfloat \ 4 | riscv \ 5 | 6 | spike_dasm_srcs = \ 7 | spike_dasm_option_parser.cc \ 8 | 9 | spike_dasm_install_prog_srcs = \ 10 | spike-dasm.cc \ 11 | -------------------------------------------------------------------------------- /riscv/insns/csrrc.h: -------------------------------------------------------------------------------- 1 | bool write = insn.rs1() != 0; 2 | int csr = validate_csr(insn.csr(), write); 3 | reg_t old = p->get_csr(csr, insn, write); 4 | if (write) { 5 | p->put_csr(csr, old & ~RS1); 6 | } 7 | WRITE_RD(sext_xlen(old)); 8 | serialize(); 9 | -------------------------------------------------------------------------------- /riscv/insns/csrrs.h: -------------------------------------------------------------------------------- 1 | bool write = insn.rs1() != 0; 2 | int csr = validate_csr(insn.csr(), write); 3 | reg_t old = p->get_csr(csr, insn, write); 4 | if (write) { 5 | p->put_csr(csr, old | RS1); 6 | } 7 | WRITE_RD(sext_xlen(old)); 8 | serialize(); 9 | -------------------------------------------------------------------------------- /riscv/insns/vfmul_vf.h: -------------------------------------------------------------------------------- 1 | // vfmul.vf vd, vs2, rs1, vm 2 | require_zvfbfa 3 | 4 | VI_VFP_VF_LOOP 5 | ({ 6 | vd = VFP_OP_16(mul, vs2, rs1); 7 | }, 8 | { 9 | vd = f32_mul(vs2, rs1); 10 | }, 11 | { 12 | vd = f64_mul(vs2, rs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfmul_vv.h: -------------------------------------------------------------------------------- 1 | // vfmul.vv vd, vs1, vs2, vm 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP 5 | ({ 6 | vd = VFP_OP_16(mul, vs1, vs2); 7 | }, 8 | { 9 | vd = f32_mul(vs1, vs2); 10 | }, 11 | { 12 | vd = f64_mul(vs1, vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vmfeq_vv.h: -------------------------------------------------------------------------------- 1 | // vmfeq.vv vd, vs2, vs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP_CMP 5 | ({ 6 | res = VFP_OP_16(eq, vs2, vs1); 7 | }, 8 | { 9 | res = f32_eq(vs2, vs1); 10 | }, 11 | { 12 | res = f64_eq(vs2, vs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vmfle_vv.h: -------------------------------------------------------------------------------- 1 | // vmfle.vv vd, vs2, rs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP_CMP 5 | ({ 6 | res = VFP_OP_16(le, vs2, vs1); 7 | }, 8 | { 9 | res = f32_le(vs2, vs1); 10 | }, 11 | { 12 | res = f64_le(vs2, vs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vmflt_vv.h: -------------------------------------------------------------------------------- 1 | // vmflt.vv vd, vs2, vs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP_CMP 5 | ({ 6 | res = VFP_OP_16(lt, vs2, vs1); 7 | }, 8 | { 9 | res = f32_lt(vs2, vs1); 10 | }, 11 | { 12 | res = f64_lt(vs2, vs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vmfne_vv.h: -------------------------------------------------------------------------------- 1 | // vmfne.vv vd, vs2, rs1 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP_CMP 5 | ({ 6 | res = !VFP_OP_16(eq, vs2, vs1); 7 | }, 8 | { 9 | res = !f32_eq(vs2, vs1); 10 | }, 11 | { 12 | res = !f64_eq(vs2, vs1); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vssra_vv.h: -------------------------------------------------------------------------------- 1 | // vssra.vv vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | VRM xrm = P.VU.get_vround_mode(); 5 | int sh = vs1 & (sew - 1); 6 | int128_t val = vs2; 7 | 8 | INT_ROUNDING(val, xrm, sh); 9 | vd = val >> sh; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vssra_vx.h: -------------------------------------------------------------------------------- 1 | // vssra.vx vd, vs2, rs1 2 | VI_VX_LOOP 3 | ({ 4 | VRM xrm = P.VU.get_vround_mode(); 5 | int sh = rs1 & (sew - 1); 6 | int128_t val = vs2; 7 | 8 | INT_ROUNDING(val, xrm, sh); 9 | vd = val >> sh; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vssrl_vv.h: -------------------------------------------------------------------------------- 1 | // vssrl.vv vd, vs2, vs1 2 | VI_VV_ULOOP 3 | ({ 4 | VRM xrm = P.VU.get_vround_mode(); 5 | int sh = vs1 & (sew - 1); 6 | uint128_t val = vs2; 7 | 8 | INT_ROUNDING(val, xrm, sh); 9 | vd = val >> sh; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/vssrl_vx.h: -------------------------------------------------------------------------------- 1 | // vssrl.vx vd, vs2, rs1 2 | VI_VX_ULOOP 3 | ({ 4 | VRM xrm = P.VU.get_vround_mode(); 5 | int sh = rs1 & (sew - 1); 6 | uint128_t val = vs2; 7 | 8 | INT_ROUNDING(val, xrm, sh); 9 | vd = val >> sh; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/csrrsi.h: -------------------------------------------------------------------------------- 1 | bool write = insn.rs1() != 0; 2 | int csr = validate_csr(insn.csr(), write); 3 | reg_t old = p->get_csr(csr, insn, write); 4 | if (write) { 5 | p->put_csr(csr, old | insn.rs1()); 6 | } 7 | WRITE_RD(sext_xlen(old)); 8 | serialize(); 9 | -------------------------------------------------------------------------------- /riscv/insns/vfcvt_f_x_v.h: -------------------------------------------------------------------------------- 1 | // vfcvt.f.x.v vd, vd2, vm 2 | VI_VFP_CVT_INT_TO_FP( 3 | { vd = i32_to_f16(vs2); }, // BODY16 4 | { vd = i32_to_f32(vs2); }, // BODY32 5 | { vd = i64_to_f64(vs2); }, // BODY64 6 | int // sign 7 | ) 8 | -------------------------------------------------------------------------------- /riscv/insns/vfwnmacc_vf.h: -------------------------------------------------------------------------------- 1 | // vfwnmacc.vf vd, vs2, rs1 2 | VI_VFP_VF_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN)); 5 | }, 6 | { 7 | vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vfwnmacc_vv.h: -------------------------------------------------------------------------------- 1 | // vfwnmacc.vv vd, vs2, vs1 2 | VI_VFP_VV_LOOP_WIDE 3 | ({ 4 | vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN)); 5 | }, 6 | { 7 | vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); 8 | }) 9 | -------------------------------------------------------------------------------- /riscv/insns/vrem_vv.h: -------------------------------------------------------------------------------- 1 | // vrem.vv vd, vs2, vs1 2 | VI_VV_LOOP 3 | ({ 4 | if (vs1 == 0) 5 | vd = vs2; 6 | else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) 7 | vd = 0; 8 | else { 9 | vd = vs2 % vs1; 10 | } 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vssrl_vi.h: -------------------------------------------------------------------------------- 1 | // vssra.vi vd, vs2, zimm5 2 | VI_VI_ULOOP 3 | ({ 4 | VRM xrm = P.VU.get_vround_mode(); 5 | int sh = zimm5 & (sew - 1); 6 | uint128_t val = vs2; 7 | 8 | INT_ROUNDING(val, xrm, sh); 9 | vd = val >> sh; 10 | }) 11 | -------------------------------------------------------------------------------- /softfloat/s_commonNaNToF16UI.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /softfloat/s_commonNaNToF32UI.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /softfloat/s_commonNaNToF64UI.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /softfloat/s_f128UIToCommonNaN.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /softfloat/s_f16UIToCommonNaN.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /softfloat/s_f32UIToCommonNaN.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /softfloat/s_f64UIToCommonNaN.c: -------------------------------------------------------------------------------- 1 | 2 | /*---------------------------------------------------------------------------- 3 | | This file intentionally contains no code. 4 | *----------------------------------------------------------------------------*/ 5 | 6 | -------------------------------------------------------------------------------- /riscv/insns/vssra_vi.h: -------------------------------------------------------------------------------- 1 | // vssra.vi vd, vs2, zimm5 2 | VI_VI_LOOP 3 | ({ 4 | VRM xrm = P.VU.get_vround_mode(); 5 | int sh = insn.v_zimm5() & (sew - 1); 6 | int128_t val = vs2; 7 | 8 | INT_ROUNDING(val, xrm, sh); 9 | vd = val >> sh; 10 | }) 11 | -------------------------------------------------------------------------------- /riscv/insns/wrs_nto.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZAWRS); 2 | 3 | if (get_field(STATE.mstatus->read(), MSTATUS_TW)) { 4 | require_privilege(PRV_M); 5 | } else if (STATE.v) { 6 | if (get_field(STATE.hstatus->read(), HSTATUS_VTW)) 7 | require_novirt(); 8 | } 9 | -------------------------------------------------------------------------------- /riscv/insns/csrrci.h: -------------------------------------------------------------------------------- 1 | bool write = insn.rs1() != 0; 2 | int csr = validate_csr(insn.csr(), write); 3 | reg_t old = p->get_csr(csr, insn, write); 4 | if (write) { 5 | p->put_csr(csr, old & ~(reg_t)insn.rs1()); 6 | } 7 | WRITE_RD(sext_xlen(old)); 8 | serialize(); 9 | -------------------------------------------------------------------------------- /riscv/insns/vfclass_v.h: -------------------------------------------------------------------------------- 1 | // vfclass.v vd, vs2, vm 2 | VI_VFP_V_LOOP 3 | ({ 4 | vd = P.VU.altfmt ? bf16(bf16_classify(vs2)) : f16(f16_classify(vs2)); 5 | }, 6 | { 7 | vd = f32(f32_classify(vs2)); 8 | }, 9 | { 10 | vd = f64(f64_classify(vs2)); 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vfcvt_f_xu_v.h: -------------------------------------------------------------------------------- 1 | // vfcvt.f.xu.v vd, vd2, vm 2 | VI_VFP_CVT_INT_TO_FP( 3 | { vd = ui32_to_f16(vs2); }, // BODY16 4 | { vd = ui32_to_f32(vs2); }, // BODY32 5 | { vd = ui64_to_f64(vs2); }, // BODY64 6 | uint // sign 7 | ) 8 | -------------------------------------------------------------------------------- /riscv/insns/vfredmax_vs.h: -------------------------------------------------------------------------------- 1 | // vfredmax vd, vs2, vs1 2 | bool is_propagate = false; 3 | VI_VFP_VV_LOOP_REDUCTION 4 | ({ 5 | vd_0 = f16_max(vd_0, vs2); 6 | }, 7 | { 8 | vd_0 = f32_max(vd_0, vs2); 9 | }, 10 | { 11 | vd_0 = f64_max(vd_0, vs2); 12 | }) 13 | -------------------------------------------------------------------------------- /riscv/insns/vfredmin_vs.h: -------------------------------------------------------------------------------- 1 | // vfredmin vd, vs2, vs1 2 | bool is_propagate = false; 3 | VI_VFP_VV_LOOP_REDUCTION 4 | ({ 5 | vd_0 = f16_min(vd_0, vs2); 6 | }, 7 | { 8 | vd_0 = f32_min(vd_0, vs2); 9 | }, 10 | { 11 | vd_0 = f64_min(vd_0, vs2); 12 | }) 13 | -------------------------------------------------------------------------------- /riscv/insns/vsaddu_vi.h: -------------------------------------------------------------------------------- 1 | // vsaddu vd, vs2, zimm5 2 | VI_VI_ULOOP 3 | ({ 4 | bool sat = false; 5 | vd = vs2 + (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); 6 | 7 | sat = vd < vs2; 8 | vd |= -(vd < vs2); 9 | 10 | P_SET_OV(sat); 11 | }) 12 | -------------------------------------------------------------------------------- /debug_rom/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY( entry ) 3 | SECTIONS 4 | { 5 | .whereto 0x300 : 6 | { 7 | *(.whereto) 8 | } 9 | . = 0x800; 10 | .text : 11 | { 12 | *(.text) 13 | } 14 | _end = .; 15 | } 16 | -------------------------------------------------------------------------------- /riscv/insns/rem.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | sreg_t lhs = sext_xlen(RS1); 3 | sreg_t rhs = sext_xlen(RS2); 4 | if (rhs == 0) 5 | WRITE_RD(lhs); 6 | else if (lhs == INT64_MIN && rhs == -1) 7 | WRITE_RD(0); 8 | else 9 | WRITE_RD(sext_xlen(lhs % rhs)); 10 | -------------------------------------------------------------------------------- /riscv/insns/vwsll_vi.h: -------------------------------------------------------------------------------- 1 | // vwsll.vi vd, vs2, zimm5, vm 2 | 3 | #include "zvk_ext_macros.h" 4 | 5 | require_zvbb; 6 | VI_CHECK_DSS(false); 7 | 8 | VI_ZVK_VI_WIDENING_ULOOP({ 9 | const reg_t shift = zimm5 & ((2 * sew) - 1); 10 | vd_w = vs2_w << shift; 11 | }); 12 | -------------------------------------------------------------------------------- /riscv/insns/vwsll_vv.h: -------------------------------------------------------------------------------- 1 | // vwsll.vv vd, vs2, zimm5, vm 2 | 3 | #include "zvk_ext_macros.h" 4 | 5 | require_zvbb; 6 | VI_CHECK_DSS(true); 7 | 8 | VI_ZVK_VV_WIDENING_ULOOP({ 9 | const reg_t shift = (vs1 & ((2 * sew) - 1)); 10 | vd_w = vs2_w << shift; 11 | }); 12 | -------------------------------------------------------------------------------- /riscv/insns/vwsll_vx.h: -------------------------------------------------------------------------------- 1 | // vwsll.vx vd, vs2, zimm5, vm 2 | 3 | #include "zvk_ext_macros.h" 4 | 5 | require_zvbb; 6 | VI_CHECK_DSS(false); 7 | 8 | VI_ZVK_VX_WIDENING_ULOOP({ 9 | const reg_t shift = (rs1 & ((2 * sew) - 1)); 10 | vd_w = vs2_w << shift; 11 | }); 12 | -------------------------------------------------------------------------------- /riscv/insns/div.h: -------------------------------------------------------------------------------- 1 | require_extension('M'); 2 | sreg_t lhs = sext_xlen(RS1); 3 | sreg_t rhs = sext_xlen(RS2); 4 | if (rhs == 0) 5 | WRITE_RD(UINT64_MAX); 6 | else if (lhs == INT64_MIN && rhs == -1) 7 | WRITE_RD(lhs); 8 | else 9 | WRITE_RD(sext_xlen(lhs / rhs)); 10 | -------------------------------------------------------------------------------- /riscv/insns/vqdot_vv.h: -------------------------------------------------------------------------------- 1 | // vqdot.vv vd, vs2, vs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VV_LOOP 8 | ({ 9 | VQDOT(vs1, vs2, int8_t, int8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vqdot_vx.h: -------------------------------------------------------------------------------- 1 | // vqdot.vx vd, vs2, rs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VX_LOOP 8 | ({ 9 | VQDOT(rs1, vs2, int8_t, int8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/c_jal.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | if (xlen == 32) { 3 | reg_t tmp = npc; 4 | set_pc(pc + insn.rvc_j_imm()); 5 | WRITE_REG(X_RA, tmp); 6 | } else { // c.addiw 7 | require(insn.rvc_rd() != 0); 8 | WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm())); 9 | } 10 | -------------------------------------------------------------------------------- /riscv/insns/sha256sig0.h: -------------------------------------------------------------------------------- 1 | 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) 5 | 6 | uint32_t a = RS1; 7 | 8 | WRITE_RD( 9 | sext32(ROR32(a, 7) ^ ROR32(a,18) ^ (a >> 3)) 10 | ); 11 | 12 | #undef ROR32 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/vfmadd_vf.h: -------------------------------------------------------------------------------- 1 | // vfmadd: vd[i] = +(vd[i] * f[rs1]) + vs2[i] 2 | require_zvfbfa 3 | 4 | VI_VFP_VF_LOOP 5 | ({ 6 | vd = VFP_MULADD_16(vd, rs1, vs2); 7 | }, 8 | { 9 | vd = f32_mulAdd(vd, rs1, vs2); 10 | }, 11 | { 12 | vd = f64_mulAdd(vd, rs1, vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfmadd_vv.h: -------------------------------------------------------------------------------- 1 | // vfmadd: vd[i] = +(vd[i] * vs1[i]) + vs2[i] 2 | require_zvfbfa 3 | 4 | VI_VFP_VV_LOOP 5 | ({ 6 | vd = VFP_MULADD_16(vd, vs1, vs2); 7 | }, 8 | { 9 | vd = f32_mulAdd(vd, vs1, vs2); 10 | }, 11 | { 12 | vd = f64_mulAdd(vd, vs1, vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfrdiv_vf.h: -------------------------------------------------------------------------------- 1 | // vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] 2 | VI_NON_ALTFMT_INSN 3 | 4 | VI_VFP_VF_LOOP 5 | ({ 6 | vd = f16_div(rs1, vs2); 7 | }, 8 | { 9 | vd = f32_div(rs1, vs2); 10 | }, 11 | { 12 | vd = f64_div(rs1, vs2); 13 | }) 14 | -------------------------------------------------------------------------------- /riscv/insns/vfredosum_vs.h: -------------------------------------------------------------------------------- 1 | // vfredosum: vd[0] = sum( vs2[*] , vs1[0] ) 2 | bool is_propagate = false; 3 | VI_VFP_VV_LOOP_REDUCTION 4 | ({ 5 | vd_0 = f16_add(vd_0, vs2); 6 | }, 7 | { 8 | vd_0 = f32_add(vd_0, vs2); 9 | }, 10 | { 11 | vd_0 = f64_add(vd_0, vs2); 12 | }) 13 | -------------------------------------------------------------------------------- /riscv/insns/vfredusum_vs.h: -------------------------------------------------------------------------------- 1 | // vfredsum: vd[0] = sum( vs2[*] , vs1[0] ) 2 | bool is_propagate = true; 3 | VI_VFP_VV_LOOP_REDUCTION 4 | ({ 5 | vd_0 = f16_add(vd_0, vs2); 6 | }, 7 | { 8 | vd_0 = f32_add(vd_0, vs2); 9 | }, 10 | { 11 | vd_0 = f64_add(vd_0, vs2); 12 | }) 13 | -------------------------------------------------------------------------------- /riscv/insns/vqdotsu_vv.h: -------------------------------------------------------------------------------- 1 | // vqdotsu.vv vd, vs2, vs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VV_LOOP 8 | ({ 9 | VQDOT(vs1, vs2, uint8_t, int8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vqdotsu_vx.h: -------------------------------------------------------------------------------- 1 | // vqdotsu.vx vd, vs2, rs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VX_LOOP 8 | ({ 9 | VQDOT(rs1, vs2, uint8_t, int8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vqdotu_vv.h: -------------------------------------------------------------------------------- 1 | // vqdotu.vv vd, vs2, vs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VV_LOOP 8 | ({ 9 | VQDOT(vs1, vs2, uint8_t, uint8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vqdotu_vx.h: -------------------------------------------------------------------------------- 1 | // vqdotu.vx vd, vs2, rs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VX_LOOP 8 | ({ 9 | VQDOT(rs1, vs2, uint8_t, uint8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/vqdotus_vx.h: -------------------------------------------------------------------------------- 1 | // vqdotus.vx vd, vs2, rs1, vm 2 | #include "vqdot_common.h" 3 | 4 | require_extension(EXT_ZVQDOTQ); 5 | require(P.VU.vsew == e32); 6 | 7 | VI_VX_LOOP 8 | ({ 9 | VQDOT(rs1, vs2, int8_t, uint8_t); 10 | vd = (vd + result) & 0xffffffff; 11 | }) 12 | -------------------------------------------------------------------------------- /riscv/insns/sha256sig1.h: -------------------------------------------------------------------------------- 1 | 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) 5 | 6 | uint32_t a = RS1; 7 | 8 | WRITE_RD( 9 | sext32(ROR32(a, 17) ^ ROR32(a,19) ^ (a >> 10)) 10 | ); 11 | 12 | #undef ROR32 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/sha256sum0.h: -------------------------------------------------------------------------------- 1 | 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) 5 | 6 | uint32_t a = RS1; 7 | 8 | WRITE_RD( 9 | sext32(ROR32(a, 2) ^ ROR32(a,13) ^ ROR32(a, 22)) 10 | ); 11 | 12 | #undef ROR32 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/sha256sum1.h: -------------------------------------------------------------------------------- 1 | 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) 5 | 6 | uint32_t a = RS1; 7 | 8 | WRITE_RD( 9 | sext32(ROR32(a, 6) ^ ROR32(a,11) ^ ROR32(a, 25)) 10 | ); 11 | 12 | #undef ROR32 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/vctz_v.h: -------------------------------------------------------------------------------- 1 | // vctz.v vd, vs2 2 | 3 | #include "zvk_ext_macros.h" 4 | 5 | require_zvbb; 6 | 7 | VI_V_ULOOP 8 | ({ 9 | unsigned int i = 0; 10 | for (; i < P.VU.vsew; ++i) { 11 | if (1 & (vs2 >> i)) { 12 | break; 13 | } 14 | } 15 | vd = i; 16 | }) 17 | -------------------------------------------------------------------------------- /riscv/tracer.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef _RISCV_TRACER_H 4 | #define _RISCV_TRACER_H 5 | 6 | #include "processor.h" 7 | 8 | static inline void trace_opcode(processor_t UNUSED *p, insn_bits_t UNUSED opc, insn_t UNUSED insn) { 9 | } 10 | 11 | #endif 12 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv32i_m/C/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ic \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv32i_m/I/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv32i_m/M/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32im \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv64i_m/C/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ic \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv64i_m/I/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64i \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | -------------------------------------------------------------------------------- /riscv/insns/c_sd.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require((xlen == 64) || p->extension_enabled(EXT_ZCLSD)); 3 | 4 | if (xlen == 32) { 5 | MMU.store(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S_PAIR); 6 | } else { 7 | MMU.store(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); 8 | } 9 | -------------------------------------------------------------------------------- /riscv/insns/c_sdsp.h: -------------------------------------------------------------------------------- 1 | require_extension(EXT_ZCA); 2 | require((xlen == 64) || p->extension_enabled(EXT_ZCLSD)); 3 | 4 | if (xlen == 32) { 5 | MMU.store(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2_PAIR); 6 | } else { 7 | MMU.store(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2); 8 | } 9 | -------------------------------------------------------------------------------- /riscv/insns/sha512sig0.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) 5 | 6 | uint64_t a = RS1; 7 | 8 | WRITE_RD( 9 | ROR64(a, 1) ^ ROR64(a, 8) ^ (a >> 7) 10 | ); 11 | 12 | #undef ROR64 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/sha512sig1.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) 5 | 6 | uint64_t a = RS1; 7 | 8 | WRITE_RD( 9 | ROR64(a, 19) ^ ROR64(a,61) ^ (a >> 6) 10 | ); 11 | 12 | #undef ROR64 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/sha512sum0.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) 5 | 6 | uint64_t a = RS1; 7 | 8 | WRITE_RD( 9 | ROR64(a, 28) ^ ROR64(a,34) ^ ROR64(a,39) 10 | ); 11 | 12 | #undef ROR64 13 | 14 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv32i_m/F/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32if \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | -------------------------------------------------------------------------------- /riscv/insns/packw.h: -------------------------------------------------------------------------------- 1 | // RV64Zbb contains zext.h but not general packw 2 | require(((insn.rs2() == 0) && p->extension_enabled(EXT_ZBB)) 3 | || p->extension_enabled(EXT_ZBKB)); 4 | require_rv64; 5 | reg_t lo = zext32(RS1 << 16) >> 16; 6 | reg_t hi = zext32(RS2 << 16); 7 | WRITE_RD(sext32(lo | hi)); 8 | -------------------------------------------------------------------------------- /riscv/insns/sha512sig0h.h: -------------------------------------------------------------------------------- 1 | 2 | require_rv32; 3 | require_extension(EXT_ZKNH); 4 | 5 | reg_t result = 6 | (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^ 7 | (zext32(RS2) << 31) ^ (zext32(RS2) << 24); 8 | 9 | WRITE_RD(sext_xlen(result)); 10 | -------------------------------------------------------------------------------- /riscv/insns/sha512sig0l.h: -------------------------------------------------------------------------------- 1 | 2 | require_rv32; 3 | require_extension(EXT_ZKNH); 4 | 5 | reg_t result = 6 | (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^ 7 | (zext32(RS2) << 31) ^ (zext32(RS2) << 25) ^ (zext32(RS2) << 24); 8 | 9 | WRITE_RD(sext_xlen(result)); 10 | -------------------------------------------------------------------------------- /riscv/insns/sha512sig1h.h: -------------------------------------------------------------------------------- 1 | 2 | require_rv32; 3 | require_extension(EXT_ZKNH); 4 | 5 | reg_t result = 6 | (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^ 7 | (zext32(RS2) >> 29) ^ (zext32(RS2) << 13); 8 | 9 | WRITE_RD(sext_xlen(result)); 10 | -------------------------------------------------------------------------------- /riscv/insns/sha512sig1l.h: -------------------------------------------------------------------------------- 1 | 2 | require_rv32; 3 | require_extension(EXT_ZKNH); 4 | 5 | reg_t result = 6 | (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^ 7 | (zext32(RS2) >> 29) ^ (zext32(RS2) << 26) ^ (zext32(RS2) << 13); 8 | 9 | WRITE_RD(sext_xlen(result)); 10 | -------------------------------------------------------------------------------- /riscv/insns/sha512sum0r.h: -------------------------------------------------------------------------------- 1 | 2 | require_rv32; 3 | require_extension(EXT_ZKNH); 4 | 5 | reg_t result = 6 | (zext32(RS1) << 25) ^ (zext32(RS1) << 30) ^ (zext32(RS1) >> 28) ^ 7 | (zext32(RS2) >> 7) ^ (zext32(RS2) >> 2) ^ (zext32(RS2) << 4); 8 | 9 | WRITE_RD(sext_xlen(result)); 10 | -------------------------------------------------------------------------------- /riscv/insns/sha512sum1.h: -------------------------------------------------------------------------------- 1 | require_rv64; 2 | require_extension(EXT_ZKNH); 3 | 4 | #define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) 5 | 6 | uint64_t a = RS1; 7 | 8 | WRITE_RD( 9 | ROR64(a, 14) ^ ROR64(a, 18) ^ ROR64(a, 41) 10 | ); 11 | 12 | #undef ROR64 13 | 14 | -------------------------------------------------------------------------------- /riscv/insns/sha512sum1r.h: -------------------------------------------------------------------------------- 1 | 2 | require_rv32; 3 | require_extension(EXT_ZKNH); 4 | 5 | reg_t result = 6 | (zext32(RS1) << 23) ^ (zext32(RS1) >> 14) ^ (zext32(RS1) >> 18) ^ 7 | (zext32(RS2) >> 9) ^ (zext32(RS2) << 18) ^ (zext32(RS2) << 14); 8 | 9 | WRITE_RD(sext_xlen(result)); 10 | -------------------------------------------------------------------------------- /arch_test_target/spike/device/rv32e_unratified/C/Makefile.include: -------------------------------------------------------------------------------- 1 | include $(TARGETDIR)/spike/device/Makefile_common.inc 2 | RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ec \ 3 | +signature=$(*).signature.output +signature-granularity=4\ 4 | $< 5 | 6 | RUN_TARGET=\ 7 | $(RUN_CMD) 8 | --------------------------------------------------------------------------------