├── .github └── workflows │ ├── debug.yml │ └── spike-openocd-tests.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile.in ├── README.md ├── benchmarks ├── Makefile ├── common │ ├── crt.S │ ├── syscalls.c │ ├── test.ld │ └── util.h ├── dhrystone │ ├── dhrystone.c │ ├── dhrystone.h │ └── dhrystone_main.c ├── median │ ├── dataset1.h │ ├── median.c │ ├── median.h │ ├── median_gendata.pl │ └── median_main.c ├── memcpy │ ├── dataset1.h │ ├── memcpy_gendata.pl │ └── memcpy_main.c ├── mm │ ├── common.h │ ├── gen.scala │ ├── mm.c │ ├── mm_main.c │ └── rb.h ├── mt-matmul │ ├── dataset.h │ ├── matmul.c │ ├── matmul_gendata.pl │ └── mt-matmul.c ├── mt-memcpy │ ├── dataset1.h │ ├── memcpy_gendata.pl │ └── mt-memcpy.c ├── mt-vvadd │ ├── dataset.h │ ├── mt-vvadd.c │ ├── vvadd.c │ └── vvadd_gendata.pl ├── multiply │ ├── dataset1.h │ ├── multiply.c │ ├── multiply.h │ ├── multiply_gendata.pl │ └── multiply_main.c ├── pmp │ └── pmp.c ├── qsort │ ├── dataset1.h │ ├── qsort_gendata.pl │ └── qsort_main.c ├── readme.txt ├── rsort │ ├── dataset1.h │ └── rsort.c ├── spmv │ ├── dataset1.h │ ├── spmv_gendata.scala │ └── spmv_main.c ├── towers │ └── towers_main.c ├── vec-daxpy │ ├── dataset1.h │ ├── daxpy_gendata.pl │ ├── vec-daxpy.S │ └── vec-daxpy_main.c ├── vec-memcpy │ ├── dataset1.h │ ├── memcpy_gendata.pl │ ├── vec-memcpy.S │ └── vec-memcpy_main.c ├── vec-sgemm │ ├── dataset1.h │ ├── sgemm_gendata.pl │ ├── vec-sgemm.S │ └── vec-sgemm_main.c ├── vec-strcmp │ ├── vec-strcmp.S │ └── vec-strcmp_main.c └── vvadd │ ├── dataset1-large.h │ ├── dataset1.h │ ├── vvadd_gendata.pl │ └── vvadd_main.c ├── configure ├── configure.ac ├── debug ├── Makefile ├── README.md ├── bin │ ├── README.md │ ├── RTOSDemo32.axf │ └── RTOSDemo64.axf ├── excluded.yaml.example ├── gdbserver.py ├── hifive1_excludes.yaml ├── openocd.py ├── programs │ ├── checksum.c │ ├── counting_loop.c │ ├── debug.c │ ├── ebreak.c │ ├── encoding.h │ ├── entry.S │ ├── infinite_loop.S │ ├── init.c │ ├── init.h │ ├── interrupt.c │ ├── mprv.S │ ├── multicore.c │ ├── priv.S │ ├── regs.S │ ├── run_halt_timing.S │ ├── semihosting.c │ ├── semihosting.h │ ├── step.S │ ├── tiny-malloc.c │ ├── translate.c │ ├── trigger.S │ └── vectors.S ├── pylint.rc ├── rbb_daisychain.py ├── requirements.txt ├── targets.py ├── targets │ ├── RISC-V │ │ ├── spike-1.cfg │ │ ├── spike-2-hwthread.cfg │ │ ├── spike-2.cfg │ │ ├── spike-multi.cfg │ │ ├── spike-multi.py │ │ ├── spike32-2-hwthread.py │ │ ├── spike32-2.py │ │ ├── spike32.lds │ │ ├── spike32.py │ │ ├── spike64-2-hwthread.py │ │ ├── spike64-2-rtos.py │ │ ├── spike64-2.py │ │ ├── spike64.lds │ │ └── spike64.py │ └── SiFive │ │ ├── Freedom │ │ ├── E300.py │ │ ├── Freedom.cfg │ │ ├── Freedom.lds │ │ ├── U500.py │ │ └── U500Sim.py │ │ ├── HiFive1-flash.lds │ │ ├── HiFive1-flash.py │ │ ├── HiFive1.cfg │ │ ├── HiFive1.lds │ │ ├── HiFive1.py │ │ ├── HiFiveUnleashed-flash.lds │ │ ├── HiFiveUnleashed-flash.py │ │ ├── HiFiveUnleashed.cfg │ │ ├── HiFiveUnleashed.lds │ │ ├── HiFiveUnleashed.py │ │ └── HiFiveUnleashed_setup.bin └── testlib.py ├── isa ├── .gitignore ├── Makefile ├── hypervisor │ ├── 2-stage_translation.S │ └── Makefrag ├── macros │ └── scalar │ │ └── test_macros.h ├── rv32mi │ ├── Makefrag │ ├── breakpoint.S │ ├── csr.S │ ├── illegal.S │ ├── instret_overflow.S │ ├── lh-misaligned.S │ ├── lw-misaligned.S │ ├── ma_addr.S │ ├── ma_fetch.S │ ├── mcsr.S │ ├── pmpaddr.S │ ├── sbreak.S │ ├── scall.S │ ├── sh-misaligned.S │ ├── shamt.S │ ├── sw-misaligned.S │ └── zicntr.S ├── rv32si │ ├── Makefrag │ ├── csr.S │ ├── dirty.S │ ├── ma_fetch.S │ ├── sbreak.S │ ├── scall.S │ └── wfi.S ├── rv32ua │ ├── Makefrag │ ├── amoadd_w.S │ ├── amoand_w.S │ ├── amomax_w.S │ ├── amomaxu_w.S │ ├── amomin_w.S │ ├── amominu_w.S │ ├── amoor_w.S │ ├── amoswap_w.S │ ├── amoxor_w.S │ └── lrsc.S ├── rv32uc │ ├── Makefrag │ └── rvc.S ├── rv32ud │ ├── Makefrag │ ├── fadd.S │ ├── fclass.S │ ├── fcmp.S │ ├── fcvt.S │ ├── fcvt_w.S │ ├── fdiv.S │ ├── fmadd.S │ ├── fmin.S │ ├── ldst.S │ ├── move.S │ └── recoding.S ├── rv32uf │ ├── Makefrag │ ├── fadd.S │ ├── fclass.S │ ├── fcmp.S │ ├── fcvt.S │ ├── fcvt_w.S │ ├── fdiv.S │ ├── fmadd.S │ ├── fmin.S │ ├── ldst.S │ ├── move.S │ └── recoding.S ├── rv32ui │ ├── Makefrag │ ├── add.S │ ├── addi.S │ ├── and.S │ ├── andi.S │ ├── auipc.S │ ├── beq.S │ ├── bge.S │ ├── bgeu.S │ ├── blt.S │ ├── bltu.S │ ├── bne.S │ ├── fence_i.S │ ├── jal.S │ ├── jalr.S │ ├── lb.S │ ├── lbu.S │ ├── ld_st.S │ ├── lh.S │ ├── lhu.S │ ├── lui.S │ ├── lw.S │ ├── ma_data.S │ ├── or.S │ ├── ori.S │ ├── sb.S │ ├── sh.S │ ├── simple.S │ ├── sll.S │ ├── slli.S │ ├── slt.S │ ├── slti.S │ ├── sltiu.S │ ├── sltu.S │ ├── sra.S │ ├── srai.S │ ├── srl.S │ ├── srli.S │ ├── st_ld.S │ ├── sub.S │ ├── sw.S │ ├── xor.S │ └── xori.S ├── rv32um │ ├── Makefrag │ ├── div.S │ ├── divu.S │ ├── mul.S │ ├── mulh.S │ ├── mulhsu.S │ ├── mulhu.S │ ├── rem.S │ └── remu.S ├── rv32uzba │ ├── Makefrag │ ├── sh1add.S │ ├── sh2add.S │ └── sh3add.S ├── rv32uzbb │ ├── Makefrag │ ├── andn.S │ ├── clz.S │ ├── cpop.S │ ├── ctz.S │ ├── max.S │ ├── maxu.S │ ├── min.S │ ├── minu.S │ ├── orc_b.S │ ├── orn.S │ ├── rev8.S │ ├── rol.S │ ├── ror.S │ ├── rori.S │ ├── sext_b.S │ ├── sext_h.S │ ├── xnor.S │ └── zext_h.S ├── rv32uzbc │ ├── Makefrag │ ├── clmul.S │ ├── clmulh.S │ └── clmulr.S ├── rv32uzbs │ ├── Makefrag │ ├── bclr.S │ ├── bclri.S │ ├── bext.S │ ├── bexti.S │ ├── binv.S │ ├── binvi.S │ ├── bset.S │ └── bseti.S ├── rv32uzfh │ ├── Makefrag │ ├── fadd.S │ ├── fclass.S │ ├── fcmp.S │ ├── fcvt.S │ ├── fcvt_w.S │ ├── fdiv.S │ ├── fmadd.S │ ├── fmin.S │ ├── ldst.S │ ├── move.S │ └── recoding.S ├── rv64mi │ ├── Makefrag │ ├── breakpoint.S │ ├── csr.S │ ├── illegal.S │ ├── instret_overflow.S │ ├── ld-misaligned.S │ ├── lh-misaligned.S │ ├── lw-misaligned.S │ ├── ma_addr.S │ ├── ma_fetch.S │ ├── mcsr.S │ ├── pmpaddr.S │ ├── sbreak.S │ ├── scall.S │ ├── sd-misaligned.S │ ├── sh-misaligned.S │ ├── sw-misaligned.S │ └── zicntr.S ├── rv64mzicbo │ ├── Makefrag │ └── zero.S ├── rv64si │ ├── Makefrag │ ├── csr.S │ ├── dirty.S │ ├── icache-alias.S │ ├── ma_fetch.S │ ├── sbreak.S │ ├── scall.S │ └── wfi.S ├── rv64ssvnapot │ ├── Makefrag │ └── napot.S ├── rv64ua │ ├── Makefrag │ ├── amoadd_d.S │ ├── amoadd_w.S │ ├── amoand_d.S │ ├── amoand_w.S │ ├── amomax_d.S │ ├── amomax_w.S │ ├── amomaxu_d.S │ ├── amomaxu_w.S │ ├── amomin_d.S │ ├── amomin_w.S │ ├── amominu_d.S │ ├── amominu_w.S │ ├── amoor_d.S │ ├── amoor_w.S │ ├── amoswap_d.S │ ├── amoswap_w.S │ ├── amoxor_d.S │ ├── amoxor_w.S │ └── lrsc.S ├── rv64uc │ ├── Makefrag │ └── rvc.S ├── rv64ud │ ├── Makefrag │ ├── fadd.S │ ├── fclass.S │ ├── fcmp.S │ ├── fcvt.S │ ├── fcvt_w.S │ ├── fdiv.S │ ├── fmadd.S │ ├── fmin.S │ ├── ldst.S │ ├── move.S │ ├── recoding.S │ └── structural.S ├── rv64uf │ ├── Makefrag │ ├── fadd.S │ ├── fclass.S │ ├── fcmp.S │ ├── fcvt.S │ ├── fcvt_w.S │ ├── fdiv.S │ ├── fmadd.S │ ├── fmin.S │ ├── ldst.S │ ├── move.S │ └── recoding.S ├── rv64ui │ ├── Makefrag │ ├── add.S │ ├── addi.S │ ├── addiw.S │ ├── addw.S │ ├── and.S │ ├── andi.S │ ├── auipc.S │ ├── beq.S │ ├── bge.S │ ├── bgeu.S │ ├── blt.S │ ├── bltu.S │ ├── bne.S │ ├── fence_i.S │ ├── jal.S │ ├── jalr.S │ ├── lb.S │ ├── lbu.S │ ├── ld.S │ ├── ld_st.S │ ├── lh.S │ ├── lhu.S │ ├── lui.S │ ├── lw.S │ ├── lwu.S │ ├── ma_data.S │ ├── or.S │ ├── ori.S │ ├── sb.S │ ├── sd.S │ ├── sh.S │ ├── simple.S │ ├── sll.S │ ├── slli.S │ ├── slliw.S │ ├── sllw.S │ ├── slt.S │ ├── slti.S │ ├── sltiu.S │ ├── sltu.S │ ├── sra.S │ ├── srai.S │ ├── sraiw.S │ ├── sraw.S │ ├── srl.S │ ├── srli.S │ ├── srliw.S │ ├── srlw.S │ ├── st_ld.S │ ├── sub.S │ ├── subw.S │ ├── sw.S │ ├── xor.S │ └── xori.S ├── rv64um │ ├── Makefrag │ ├── div.S │ ├── divu.S │ ├── divuw.S │ ├── divw.S │ ├── mul.S │ ├── mulh.S │ ├── mulhsu.S │ ├── mulhu.S │ ├── mulw.S │ ├── rem.S │ ├── remu.S │ ├── remuw.S │ └── remw.S ├── rv64uzba │ ├── Makefrag │ ├── add_uw.S │ ├── sh1add.S │ ├── sh1add_uw.S │ ├── sh2add.S │ ├── sh2add_uw.S │ ├── sh3add.S │ ├── sh3add_uw.S │ └── slli_uw.S ├── rv64uzbb │ ├── Makefrag │ ├── andn.S │ ├── clz.S │ ├── clzw.S │ ├── cpop.S │ ├── cpopw.S │ ├── ctz.S │ ├── ctzw.S │ ├── max.S │ ├── maxu.S │ ├── min.S │ ├── minu.S │ ├── orc_b.S │ ├── orn.S │ ├── rev8.S │ ├── rol.S │ ├── rolw.S │ ├── ror.S │ ├── rori.S │ ├── roriw.S │ ├── rorw.S │ ├── sext_b.S │ ├── sext_h.S │ ├── xnor.S │ └── zext_h.S ├── rv64uzbc │ ├── Makefrag │ ├── clmul.S │ ├── clmulh.S │ └── clmulr.S ├── rv64uzbs │ ├── Makefrag │ ├── bclr.S │ ├── bclri.S │ ├── bext.S │ ├── bexti.S │ ├── binv.S │ ├── binvi.S │ ├── bset.S │ └── bseti.S └── rv64uzfh │ ├── Makefrag │ ├── fadd.S │ ├── fclass.S │ ├── fcmp.S │ ├── fcvt.S │ ├── fcvt_w.S │ ├── fdiv.S │ ├── fmadd.S │ ├── fmin.S │ ├── ldst.S │ ├── move.S │ └── recoding.S └── mt ├── .gitignore ├── Makefile ├── ad_matmul.c ├── ae_matmul.c ├── af_matmul.c ├── ag_matmul.c ├── ai_matmul.c ├── ak_matmul.c ├── al_matmul.c ├── am_matmul.c ├── an_matmul.c ├── ap_matmul.c ├── aq_matmul.c ├── ar_matmul.c ├── at_matmul.c ├── av_matmul.c ├── ay_matmul.c ├── az_matmul.c ├── bb_matmul.c ├── bc_matmul.c ├── bf_matmul.c ├── bh_matmul.c ├── bj_matmul.c ├── bk_matmul.c ├── bm_matmul.c ├── bo_matmul.c ├── br_matmul.c ├── bs_matmul.c ├── ce_matmul.c ├── cf_matmul.c ├── cg_matmul.c ├── ci_matmul.c ├── ck_matmul.c ├── cl_matmul.c ├── cm_matmul.c ├── cs_matmul.c ├── cv_matmul.c ├── cy_matmul.c ├── dc_matmul.c ├── df_matmul.c ├── dm_matmul.c ├── do_matmul.c ├── dr_matmul.c ├── ds_matmul.c ├── du_matmul.c ├── dv_matmul.c ├── vvadd0.c ├── vvadd1.c ├── vvadd2.c ├── vvadd3.c └── vvadd4.c /.github/workflows/debug.yml: -------------------------------------------------------------------------------- 1 | on: 2 | pull_request: 3 | paths: 4 | - 'debug/**' 5 | 6 | name: Check Debug Code Style (pylint) 7 | 8 | jobs: 9 | check: 10 | runs-on: ubuntu-24.04 11 | steps: 12 | - name: Checkout Code 13 | uses: actions/checkout@v3 14 | with: 15 | fetch-depth: 0 16 | - name: Install required packages (pip3) 17 | run: | 18 | pip3 install pylint 19 | - name: Run pylint 20 | run: make -C debug pylint 21 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.riscv 3 | *.host 4 | *.o 5 | *.dump 6 | *.out 7 | *.hex 8 | .*.swp 9 | *.pyc 10 | /autom4te.cache 11 | /Makefile 12 | /config.log 13 | /config.status 14 | /build 15 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "env"] 2 | path = env 3 | url = https://github.com/riscv/riscv-test-env.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2012-2015, The Regents of the University of California (Regents). 2 | All Rights Reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 1. Redistributions of source code must retain the above copyright 7 | notice, this list of conditions and the following disclaimer. 8 | 2. Redistributions in binary form must reproduce the above copyright 9 | notice, this list of conditions and the following disclaimer in the 10 | documentation and/or other materials provided with the distribution. 11 | 3. Neither the name of the Regents nor the 12 | names of its contributors may be used to endorse or promote products 13 | derived from this software without specific prior written permission. 14 | 15 | IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 16 | SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 17 | OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 18 | BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | 20 | REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 23 | HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 24 | MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 25 | -------------------------------------------------------------------------------- /benchmarks/median/median.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Median filter (c version) 5 | //-------------------------------------------------------------------------- 6 | 7 | void median( int n, int input[], int results[] ) 8 | { 9 | int A, B, C, i; 10 | 11 | // Zero the ends 12 | results[0] = 0; 13 | results[n-1] = 0; 14 | 15 | // Do the filter 16 | for ( i = 1; i < (n-1); i++ ) { 17 | 18 | A = input[i-1]; 19 | B = input[i]; 20 | C = input[i+1]; 21 | 22 | if ( A < B ) { 23 | if ( B < C ) 24 | results[i] = B; 25 | else if ( C < A ) 26 | results[i] = A; 27 | else 28 | results[i] = C; 29 | } 30 | 31 | else { 32 | if ( A < C ) 33 | results[i] = A; 34 | else if ( C < B ) 35 | results[i] = B; 36 | else 37 | results[i] = C; 38 | } 39 | 40 | } 41 | 42 | } 43 | -------------------------------------------------------------------------------- /benchmarks/median/median.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Median filters 5 | //-------------------------------------------------------------------------- 6 | 7 | // Simple C version 8 | void median( int n, int input[], int results[] ); 9 | 10 | // Simple assembly version 11 | void median_asm( int n, int input[], int results[] ); 12 | -------------------------------------------------------------------------------- /benchmarks/median/median_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Median filter bencmark 5 | //-------------------------------------------------------------------------- 6 | // 7 | // This benchmark performs a 1D three element median filter. The 8 | // input data (and reference data) should be generated using the 9 | // median_gendata.pl perl script and dumped to a file named 10 | // dataset1.h. 11 | 12 | #include "util.h" 13 | 14 | #include "median.h" 15 | 16 | //-------------------------------------------------------------------------- 17 | // Input/Reference Data 18 | 19 | #include "dataset1.h" 20 | 21 | //-------------------------------------------------------------------------- 22 | // Main 23 | 24 | int main( int argc, char* argv[] ) 25 | { 26 | int results_data[DATA_SIZE]; 27 | 28 | #if PREALLOCATE 29 | // If needed we preallocate everything in the caches 30 | median( DATA_SIZE, input_data, results_data ); 31 | #endif 32 | 33 | // Do the filter 34 | setStats(1); 35 | median( DATA_SIZE, input_data, results_data ); 36 | setStats(0); 37 | 38 | // Check the results 39 | return verify( DATA_SIZE, results_data, verify_data ); 40 | } 41 | -------------------------------------------------------------------------------- /benchmarks/memcpy/memcpy_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Memcpy benchmark 5 | //-------------------------------------------------------------------------- 6 | // 7 | // This benchmark tests the memcpy implementation in syscalls.c. 8 | // The input data (and reference data) should be generated using 9 | // the memcpy_gendata.pl perl script and dumped to a file named 10 | // dataset1.h. 11 | 12 | #include 13 | #include "util.h" 14 | 15 | //-------------------------------------------------------------------------- 16 | // Input/Reference Data 17 | 18 | #include "dataset1.h" 19 | 20 | //-------------------------------------------------------------------------- 21 | // Main 22 | 23 | int main( int argc, char* argv[] ) 24 | { 25 | int results_data[DATA_SIZE]; 26 | 27 | #if PREALLOCATE 28 | // If needed we preallocate everything in the caches 29 | memcpy(results_data, input_data, sizeof(int) * DATA_SIZE); 30 | #endif 31 | 32 | // Do the riscv-linux memcpy 33 | setStats(1); 34 | memcpy(results_data, input_data, sizeof(int) * DATA_SIZE); //, DATA_SIZE * sizeof(int)); 35 | setStats(0); 36 | 37 | // Check the results 38 | return verify( DATA_SIZE, results_data, input_data ); 39 | } 40 | -------------------------------------------------------------------------------- /benchmarks/mm/common.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef _MM_H 4 | #define _MM_H 5 | 6 | #include 7 | #include 8 | #include 9 | 10 | #ifdef SP 11 | typedef float t; 12 | #define fma fmaf 13 | #else 14 | typedef double t; 15 | #endif 16 | 17 | #define inline inline __attribute__((always_inline)) 18 | 19 | #define alloca_aligned(s, a) ((void*)(((uintptr_t)alloca((s)+(a)-1)+(a)-1)&~((a)-1))) 20 | 21 | #include "rb.h" 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | void mm(size_t m, size_t n, size_t p, 28 | t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc); 29 | 30 | #ifdef __cplusplus 31 | } 32 | #endif 33 | 34 | //void rb(t* a, t* b, t* c, size_t lda, size_t ldb, size_t ldc); 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /benchmarks/mt-matmul/matmul.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #include "dataset.h" 4 | #include "util.h" 5 | #include 6 | 7 | #pragma GCC optimize ("unroll-loops") 8 | 9 | void matmul(const size_t coreid, const size_t ncores, const size_t lda, const data_t A[], const data_t B[], data_t C[]) 10 | { 11 | size_t i, j, k; 12 | size_t block = lda / ncores; 13 | size_t start = block * coreid; 14 | 15 | for (i = 0; i < lda; i++) { 16 | for (j = start; j < (start+block); j++) { 17 | data_t sum = 0; 18 | for (k = 0; k < lda; k++) 19 | sum += A[j*lda + k] * B[k*lda + i]; 20 | C[i + j*lda] = sum; 21 | } 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /benchmarks/mt-vvadd/vvadd.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #include "stdlib.h" 4 | #include "dataset.h" 5 | 6 | //-------------------------------------------------------------------------- 7 | // vvadd function 8 | 9 | void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z) 10 | { 11 | size_t i; 12 | 13 | // interleave accesses 14 | for (i = coreid; i < n; i+=ncores) 15 | { 16 | z[i] = x[i] + y[i]; 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /benchmarks/multiply/multiply.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | // ************************************************************************* 4 | // multiply function (c version) 5 | // ------------------------------------------------------------------------- 6 | 7 | int multiply( int x, int y ) 8 | { 9 | 10 | int i; 11 | int result = 0; 12 | 13 | for (i = 0; i < 32; i++) { 14 | if ((x & 0x1) == 1) 15 | result = result + y; 16 | 17 | x = x >> 1; 18 | y = y << 1; 19 | } 20 | 21 | return result; 22 | 23 | } 24 | 25 | -------------------------------------------------------------------------------- /benchmarks/multiply/multiply.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Software multiply function 5 | //-------------------------------------------------------------------------- 6 | 7 | // Simple C version 8 | int multiply(int x, int y); 9 | 10 | // Simple assembly version 11 | int multiply_asm(int x, int y); 12 | -------------------------------------------------------------------------------- /benchmarks/multiply/multiply_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | // ************************************************************************* 4 | // multiply filter bencmark 5 | // ------------------------------------------------------------------------- 6 | // 7 | // This benchmark tests the software multiply implemenation. The 8 | // input data (and reference data) should be generated using the 9 | // multiply_gendata.pl perl script and dumped to a file named 10 | // dataset1.h 11 | 12 | #include "util.h" 13 | 14 | #include "multiply.h" 15 | 16 | //-------------------------------------------------------------------------- 17 | // Input/Reference Data 18 | 19 | #include "dataset1.h" 20 | 21 | //-------------------------------------------------------------------------- 22 | // Main 23 | 24 | int main( int argc, char* argv[] ) 25 | { 26 | int i; 27 | int results_data[DATA_SIZE]; 28 | 29 | #if PREALLOCATE 30 | for (i = 0; i < DATA_SIZE; i++) 31 | { 32 | results_data[i] = multiply( input_data1[i], input_data2[i] ); 33 | } 34 | #endif 35 | 36 | setStats(1); 37 | for (i = 0; i < DATA_SIZE; i++) 38 | { 39 | results_data[i] = multiply( input_data1[i], input_data2[i] ); 40 | } 41 | setStats(0); 42 | 43 | // Check the results 44 | return verify( DATA_SIZE, results_data, verify_data ); 45 | } 46 | -------------------------------------------------------------------------------- /benchmarks/spmv/spmv_gendata.scala: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env scala 2 | !# 3 | 4 | val m = args(0).toInt 5 | val n = args(1).toInt 6 | val approx_nnz = args(2).toInt 7 | 8 | val pnnz = approx_nnz.toDouble/(m*n) 9 | val idx = collection.mutable.ArrayBuffer[Int]() 10 | val p = collection.mutable.ArrayBuffer(0) 11 | 12 | for (i <- 0 until m) { 13 | for (j <- 0 until n) { 14 | if (util.Random.nextDouble < pnnz) 15 | idx += j 16 | } 17 | p += idx.length 18 | } 19 | 20 | val nnz = idx.length 21 | val v = Array.tabulate(n)(i => util.Random.nextInt(1000)) 22 | val d = Array.tabulate(nnz)(i => util.Random.nextInt(1000)) 23 | 24 | def printVec(t: String, name: String, data: Seq[Int]) = { 25 | println("const " + t + " " + name + "[" + data.length + "] = {") 26 | println(" "+data.map(_.toString).reduceLeft(_+",\n "+_)) 27 | println("};") 28 | } 29 | 30 | def spmv(p: Seq[Int], d: Seq[Int], idx: Seq[Int], v: Seq[Int]) = { 31 | val y = collection.mutable.ArrayBuffer[Int]() 32 | for (i <- 0 until p.length-1) { 33 | var yi = 0 34 | for (k <- p(i) until p(i+1)) 35 | yi = yi + d(k)*v(idx(k)) 36 | y += yi 37 | } 38 | y 39 | } 40 | 41 | println("#define R " + m) 42 | println("#define C " + n) 43 | println("#define NNZ " + nnz) 44 | printVec("double", "val", d) 45 | printVec("int", "idx", idx) 46 | printVec("double", "x", v) 47 | printVec("int", "ptr", p) 48 | printVec("double", "verify_data", spmv(p, d, idx, v)) 49 | -------------------------------------------------------------------------------- /benchmarks/spmv/spmv_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Double-precision sparse matrix-vector multiplication benchmark 5 | //-------------------------------------------------------------------------- 6 | 7 | #include "util.h" 8 | 9 | //-------------------------------------------------------------------------- 10 | // Input/Reference Data 11 | 12 | #include "dataset1.h" 13 | 14 | void spmv(int r, const double* val, const int* idx, const double* x, 15 | const int* ptr, double* y) 16 | { 17 | for (int i = 0; i < r; i++) 18 | { 19 | int k; 20 | double yi0 = 0, yi1 = 0, yi2 = 0, yi3 = 0; 21 | for (k = ptr[i]; k < ptr[i+1]-3; k+=4) 22 | { 23 | yi0 += val[k+0]*x[idx[k+0]]; 24 | yi1 += val[k+1]*x[idx[k+1]]; 25 | yi2 += val[k+2]*x[idx[k+2]]; 26 | yi3 += val[k+3]*x[idx[k+3]]; 27 | } 28 | for ( ; k < ptr[i+1]; k++) 29 | { 30 | yi0 += val[k]*x[idx[k]]; 31 | } 32 | y[i] = (yi0+yi1)+(yi2+yi3); 33 | } 34 | } 35 | 36 | //-------------------------------------------------------------------------- 37 | // Main 38 | 39 | int main( int argc, char* argv[] ) 40 | { 41 | double y[R]; 42 | 43 | #if PREALLOCATE 44 | spmv(R, val, idx, x, ptr, y); 45 | #endif 46 | 47 | setStats(1); 48 | spmv(R, val, idx, x, ptr, y); 49 | setStats(0); 50 | 51 | return verifyDouble(R, y, verify_data); 52 | } 53 | -------------------------------------------------------------------------------- /benchmarks/vec-daxpy/vec-daxpy.S: -------------------------------------------------------------------------------- 1 | .text 2 | .balign 4 3 | .global vec_daxpy 4 | # void 5 | # vec_daxpy(size_t n, const double a, const double *x, const double *y, double* z) 6 | # { 7 | # size_t i; 8 | # for (i=0; i 13 | #include "util.h" 14 | 15 | //-------------------------------------------------------------------------- 16 | // Input/Reference Data 17 | 18 | typedef double data_t; 19 | #include "dataset1.h" 20 | 21 | //-------------------------------------------------------------------------- 22 | // Main 23 | 24 | void vec_daxpy(size_t n, const double a, const double *x, const double *y, double* z); 25 | 26 | 27 | int main( int argc, char* argv[] ) 28 | { 29 | data_t results_data[DATA_SIZE]; 30 | 31 | #if PREALLOCATE 32 | // If needed we preallocate everything in the caches 33 | vec_daxpy(DATA_SIZE, input0, input1_data, input2_data, results_data); 34 | #endif 35 | 36 | // Do the daxpy 37 | setStats(1); 38 | vec_daxpy(DATA_SIZE, input0, input1_data, input2_data, results_data); 39 | setStats(0); 40 | 41 | // Check the results 42 | return verifyDouble( DATA_SIZE, results_data, verify_data ); 43 | } 44 | -------------------------------------------------------------------------------- /benchmarks/vec-memcpy/vec-memcpy.S: -------------------------------------------------------------------------------- 1 | .text 2 | .balign 4 3 | .global vec_memcpy 4 | # void *vec_memcpy(void* dest, const void* src, size_t n) 5 | # a0=dest, a1=src, a2=n 6 | # 7 | vec_memcpy: 8 | mv a3, a0 # Copy destination 9 | loop: 10 | vsetvli t0, a2, e8, m8, ta, ma # Vectors of 8b 11 | vle8.v v0, (a1) # Load bytes 12 | add a1, a1, t0 # Bump pointer 13 | sub a2, a2, t0 # Decrement count 14 | vse8.v v0, (a3) # Store bytes 15 | add a3, a3, t0 # Bump pointer 16 | bnez a2, loop # Any more? 17 | ret # Return 18 | -------------------------------------------------------------------------------- /benchmarks/vec-memcpy/vec-memcpy_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Memcpy benchmark 5 | //-------------------------------------------------------------------------- 6 | // 7 | // This benchmark tests a vectorized memcpy implementation. 8 | // The input data (and reference data) should be generated using 9 | // the memcpy_gendata.pl perl script and dumped to a file named 10 | // dataset1.h. 11 | 12 | #include 13 | #include "util.h" 14 | 15 | //-------------------------------------------------------------------------- 16 | // Input/Reference Data 17 | 18 | #include "dataset1.h" 19 | 20 | //-------------------------------------------------------------------------- 21 | // Main 22 | 23 | void *vec_memcpy(void*, const void*, size_t); 24 | 25 | int main( int argc, char* argv[] ) 26 | { 27 | int results_data[DATA_SIZE]; 28 | 29 | #if PREALLOCATE 30 | // If needed we preallocate everything in the caches 31 | vec_memcpy(results_data, input_data, sizeof(int) * DATA_SIZE); 32 | #endif 33 | 34 | // Do the riscv-linux memcpy 35 | setStats(1); 36 | vec_memcpy(results_data, input_data, sizeof(int) * DATA_SIZE); //, DATA_SIZE * sizeof(int)); 37 | setStats(0); 38 | 39 | // Check the results 40 | return verify( DATA_SIZE, results_data, input_data ); 41 | } 42 | -------------------------------------------------------------------------------- /benchmarks/vec-sgemm/vec-sgemm_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // SGEMM benchmark 5 | //-------------------------------------------------------------------------- 6 | // 7 | // This benchmark tests a vectorized sgemm implementation. 8 | 9 | #include 10 | #include "util.h" 11 | 12 | //-------------------------------------------------------------------------- 13 | // Input/Reference Data 14 | 15 | #include "dataset1.h" 16 | 17 | //-------------------------------------------------------------------------- 18 | // Main 19 | 20 | void *vec_sgemm_nn (size_t, size_t, size_t, const float*, size_t, const float*, size_t, float*, size_t); 21 | 22 | int main( int argc, char* argv[] ) 23 | { 24 | float results_data[ARRAY_SIZE] = {0}; 25 | 26 | #if PREALLOCATE 27 | // If needed we preallocate everything in the caches 28 | vec_sgemm_nn(DIM_SIZE, DIM_SIZE, DIM_SIZE, input1_data, DIM_SIZE, input2_data, DIM_SIZE, results_data, DIM_SIZE); 29 | memset(results_data, 0, sizeof(results_data)); 30 | #endif 31 | 32 | // Do the sgemm 33 | setStats(1); 34 | vec_sgemm_nn(DIM_SIZE, DIM_SIZE, DIM_SIZE, input1_data, DIM_SIZE, input2_data, DIM_SIZE, results_data, DIM_SIZE); 35 | setStats(0); 36 | 37 | // Check the results 38 | return verifyFloat( ARRAY_SIZE, results_data, verify_data ); 39 | } 40 | -------------------------------------------------------------------------------- /benchmarks/vec-strcmp/vec-strcmp.S: -------------------------------------------------------------------------------- 1 | .text 2 | .balign 4 3 | .global vec_strcmp 4 | # int vec_strcmp(const char *src1, const char* src2) 5 | vec_strcmp: 6 | ## Using LMUL=2, but same register names work for larger LMULs 7 | li t1, 0 # Initial pointer bump 8 | loop: 9 | vsetvli t0, x0, e8, m2, ta, ma # Max length vectors of bytes 10 | add a0, a0, t1 # Bump src1 pointer 11 | vle8ff.v v8, (a0) # Get src1 bytes 12 | add a1, a1, t1 # Bump src2 pointer 13 | vle8ff.v v16, (a1) # Get src2 bytes 14 | 15 | vmseq.vi v0, v8, 0 # Flag zero bytes in src1 16 | vmsne.vv v1, v8, v16 # Flag if src1 != src2 17 | vmor.mm v0, v0, v1 # Combine exit conditions 18 | 19 | vfirst.m a2, v0 # ==0 or != ? 20 | csrr t1, vl # Get number of bytes fetched 21 | 22 | bltz a2, loop # Loop if all same and no zero byte 23 | 24 | add a0, a0, a2 # Get src1 element address 25 | lbu a3, (a0) # Get src1 byte from memory 26 | 27 | add a1, a1, a2 # Get src2 element address 28 | lbu a4, (a1) # Get src2 byte from memory 29 | 30 | sub a0, a3, a4 # Return value. 31 | 32 | ret 33 | -------------------------------------------------------------------------------- /benchmarks/vec-strcmp/vec-strcmp_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Strcmp benchmark 5 | //-------------------------------------------------------------------------- 6 | // 7 | // This benchmark tests a vectorized strcmp implementation. 8 | 9 | #include 10 | #include "util.h" 11 | 12 | //-------------------------------------------------------------------------- 13 | // Input/Reference Data 14 | 15 | const char* test_str = "The quick brown fox jumped over the lazy dog"; 16 | const char* same_str = "The quick brown fox jumped over the lazy dog"; 17 | char* diff_str = "The quick brown fox jumped over the lazy cat"; 18 | 19 | //-------------------------------------------------------------------------- 20 | // Main 21 | 22 | int vec_strcmp(const char *src1, const char* src2); 23 | 24 | int main( int argc, char* argv[] ) 25 | { 26 | // Do the strcmp 27 | setStats(1); 28 | int r0 = vec_strcmp(test_str, same_str); 29 | int r1 = vec_strcmp(test_str, diff_str); 30 | setStats(0); 31 | 32 | // Check the results 33 | return !(r0 == 0 && r1 != 0); 34 | } 35 | -------------------------------------------------------------------------------- /benchmarks/vvadd/vvadd_main.c: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | //************************************************************************** 4 | // Vector-vector add benchmark 5 | //-------------------------------------------------------------------------- 6 | // 7 | // This benchmark uses adds to vectors and writes the results to a 8 | // third vector. The input data (and reference data) should be 9 | // generated using the vvadd_gendata.pl perl script and dumped 10 | // to a file named dataset1.h. 11 | 12 | #include "util.h" 13 | 14 | //-------------------------------------------------------------------------- 15 | // Input/Reference Data 16 | 17 | #include "dataset1.h" 18 | 19 | //-------------------------------------------------------------------------- 20 | // vvadd function 21 | 22 | void vvadd( int n, int a[], int b[], int c[] ) 23 | { 24 | int i; 25 | for ( i = 0; i < n; i++ ) 26 | c[i] = a[i] + b[i]; 27 | } 28 | 29 | //-------------------------------------------------------------------------- 30 | // Main 31 | 32 | int main( int argc, char* argv[] ) 33 | { 34 | int results_data[DATA_SIZE]; 35 | 36 | #if PREALLOCATE 37 | // If needed we preallocate everything in the caches 38 | vvadd( DATA_SIZE, input1_data, input2_data, results_data ); 39 | #endif 40 | 41 | // Do the vvadd 42 | setStats(1); 43 | vvadd( DATA_SIZE, input1_data, input2_data, results_data ); 44 | setStats(0); 45 | 46 | // Check the results 47 | return verify( DATA_SIZE, results_data, verify_data ); 48 | } 49 | -------------------------------------------------------------------------------- /configure.ac: -------------------------------------------------------------------------------- 1 | AC_INIT([riscv-tests],[1.0]) 2 | 3 | cross_compiling=yes 4 | AC_PROG_CC 5 | 6 | AC_ARG_WITH(xlen, 7 | [AS_HELP_STRING([--with-xlen=XLEN], 8 | [Set XLEN, the X-register bit width (default is 64)])], 9 | AC_SUBST(XLEN, $withval), 10 | AC_SUBST(XLEN, 64) 11 | ) 12 | 13 | 14 | AC_CONFIG_FILES([Makefile 15 | ]) 16 | AC_OUTPUT 17 | -------------------------------------------------------------------------------- /debug/Makefile: -------------------------------------------------------------------------------- 1 | XLEN ?= 64 2 | 3 | src_dir ?= . 4 | GDBSERVER_PY = $(src_dir)/gdbserver.py 5 | TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py) 6 | MULTI_TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py | \ 7 | grep -i multi) 8 | 9 | default: spike$(XLEN) spike$(XLEN)-2 10 | 11 | all-tests: spike32 spike-multi-limited spike32-2 spike32-2-hwthread \ 12 | spike64 spike64-2 spike64-2-hwthread 13 | 14 | slow-tests: spike-multi all-tests 15 | 16 | all: pylint all-tests 17 | 18 | run.%: 19 | $(GDBSERVER_PY) \ 20 | $(src_dir)/targets/RISC-V/$(word 2, $(subst ., ,$@)).py \ 21 | $(word 3, $(subst ., ,$@)) \ 22 | --isolate \ 23 | --print-failures \ 24 | $(if $(EXCLUDE_TESTS),--exclude-tests $(EXCLUDE_TESTS)) 25 | 26 | # Target to check all the multicore options. 27 | multi-tests: spike32-2 spike32-2-hwthread 28 | 29 | pylint: 30 | pylint --rcfile=pylint.rc `git ls-files '*.py'` 31 | 32 | spike-multi-limited: $(foreach test, $(MULTI_TESTS), run.spike-multi.$(test)) 33 | echo Finished $@ 34 | 35 | spike%: $(foreach test, $(TESTS), run.spike%.$(test)) 36 | echo Finished $@ 37 | 38 | clean: 39 | rm -f *.pyc 40 | -------------------------------------------------------------------------------- /debug/bin/README.md: -------------------------------------------------------------------------------- 1 | This directory contains binaries that are not easy to compile. 2 | 3 | RTOSDemo32.axf and RTOSDemo64.axf are created by checking out 4 | https://github.com/FreeRTOS/FreeRTOS, following the instructions in 5 | `FreeRTOS/Demo/RISC-V-spike-htif_GCC/README.md`, and building: 6 | * `make XLEN=32 BASE_ADDRESS=0x10100000` 7 | * `make XLEN=64 BASE_ADDRESS=0x1212340000` 8 | -------------------------------------------------------------------------------- /debug/bin/RTOSDemo32.axf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-tests/355f1fb9b8a7142bee718e4123fea0aa8f49c319/debug/bin/RTOSDemo32.axf -------------------------------------------------------------------------------- /debug/bin/RTOSDemo64.axf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-tests/355f1fb9b8a7142bee718e4123fea0aa8f49c319/debug/bin/RTOSDemo64.axf -------------------------------------------------------------------------------- /debug/excluded.yaml.example: -------------------------------------------------------------------------------- 1 | # This is an example file showing the exclusion list format. 2 | # It can be passed to gdb_server.py using the --exclude-tests argument. 3 | 4 | 5 | # Tests excluded for all targets 6 | all: 7 | - SimpleF18Test 8 | 9 | # Tests excluded for the "spike32" target only 10 | spike32: 11 | - MemTest32 12 | - PrivRw 13 | - Sv32Test 14 | 15 | # Tests excluded for the "spike64" target only 16 | spike64: 17 | - UserInterrupt 18 | -------------------------------------------------------------------------------- /debug/hifive1_excludes.yaml: -------------------------------------------------------------------------------- 1 | # Below are known failing tests on riscv-openocd on HiFive1 board, rev. A01. 2 | # This board uses the legacy debug spec v 0.11. 3 | 4 | # Tested on Jun-26-2023. 5 | # riscv-openocd commit: a45589d60aa6864475fddcded885c8ff47d50be1 6 | # riscv-tests commit: 7b52ba3b7167acb4d8b38f4d4633112b4699cb26 7 | 8 | all: 9 | - EtriggerTest 10 | - IcountTest 11 | - InstantHaltTest 12 | - ItriggerTest 13 | - MemorySampleMixed 14 | - MemorySampleSingle 15 | - MemTestReadInvalid 16 | - RepeatReadTest 17 | - Semihosting 18 | - SemihostingFileio 19 | 20 | HiFive1Flash: 21 | - DebugBreakpoint 22 | - DebugExit 23 | - DebugFunctionCall 24 | - Hwbp1 25 | - Hwbp2 26 | - Registers 27 | - TooManyHwbp 28 | - UserInterrupt 29 | -------------------------------------------------------------------------------- /debug/programs/checksum.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | // CRC code from http://www.hackersdelight.org/hdcodetxt/crc.c.txt 4 | 5 | // Reverses (reflects) bits in a 32-bit word. 6 | unsigned reverse(unsigned x) { 7 | x = ((x & 0x55555555) << 1) | ((x >> 1) & 0x55555555); 8 | x = ((x & 0x33333333) << 2) | ((x >> 2) & 0x33333333); 9 | x = ((x & 0x0F0F0F0F) << 4) | ((x >> 4) & 0x0F0F0F0F); 10 | x = (x << 24) | ((x & 0xFF00) << 8) | 11 | ((x >> 8) & 0xFF00) | (x >> 24); 12 | return x; 13 | } 14 | 15 | // ----------------------------- crc32a -------------------------------- 16 | 17 | /* This is the basic CRC algorithm with no optimizations. It follows the 18 | logic circuit as closely as possible. */ 19 | 20 | unsigned int crc32a(uint8_t *message, unsigned int size) { 21 | int i, j; 22 | unsigned int byte, crc; 23 | 24 | i = 0; 25 | crc = 0xFFFFFFFF; 26 | while (i < size) { 27 | byte = message[i]; // Get next byte. 28 | byte = reverse(byte); // 32-bit reversal. 29 | for (j = 0; j <= 7; j++) { // Do eight times. 30 | if ((int)(crc ^ byte) < 0) 31 | crc = (crc << 1) ^ 0x04C11DB7; 32 | else crc = crc << 1; 33 | byte = byte << 1; // Ready next msg bit. 34 | } 35 | i = i + 1; 36 | } 37 | return reverse(~crc); 38 | } 39 | -------------------------------------------------------------------------------- /debug/programs/counting_loop.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | int main() 7 | { 8 | int sum = 0; 9 | int counter = 0; 10 | 11 | while (counter < 10) { 12 | counter = counter + 1; 13 | sum = sum + counter; 14 | } 15 | 16 | return counter; 17 | } 18 | -------------------------------------------------------------------------------- /debug/programs/ebreak.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | void ebreak() 4 | { 5 | asm volatile("ebreak"); 6 | } 7 | 8 | unsigned int fib(unsigned int n) 9 | { 10 | if (n == 0) { 11 | return 0; 12 | } 13 | 14 | unsigned int a = 0; 15 | unsigned int b = 1; 16 | 17 | for (unsigned int i = 1; i < n; i++) { 18 | unsigned int next = a + b; 19 | a = b; 20 | b = next; 21 | ebreak(); 22 | } 23 | 24 | return b; 25 | } 26 | 27 | int main() 28 | { 29 | begin: 30 | fib(4); 31 | } 32 | -------------------------------------------------------------------------------- /debug/programs/encoding.h: -------------------------------------------------------------------------------- 1 | ../../env/encoding.h -------------------------------------------------------------------------------- /debug/programs/infinite_loop.S: -------------------------------------------------------------------------------- 1 | #include "encoding.h" 2 | 3 | .global main 4 | .global main_end 5 | .global main_post_csrr 6 | 7 | // Load constants into all registers so we can test no register are 8 | // clobbered after attaching. 9 | main: 10 | csrr x1, CSR_MHARTID 11 | slli x1, x1, 8 12 | main_post_csrr: 13 | addi x2, x1, 1 14 | addi x3, x2, 1 15 | addi x4, x3, 1 16 | addi x5, x4, 1 17 | addi x6, x5, 1 18 | addi x7, x6, 1 19 | addi x8, x7, 1 20 | addi x9, x8, 1 21 | addi x10, x9, 1 22 | addi x11, x10, 1 23 | addi x12, x11, 1 24 | addi x13, x12, 1 25 | addi x14, x13, 1 26 | addi x15, x14, 1 27 | addi x16, x15, 1 28 | addi x17, x16, 1 29 | addi x18, x17, 1 30 | addi x19, x18, 1 31 | addi x20, x19, 1 32 | addi x21, x20, 1 33 | addi x22, x21, 1 34 | addi x23, x22, 1 35 | addi x24, x23, 1 36 | addi x25, x24, 1 37 | addi x26, x25, 1 38 | addi x27, x26, 1 39 | addi x28, x27, 1 40 | addi x29, x28, 1 41 | addi x30, x29, 1 42 | addi x31, x30, 1 43 | main_end: 44 | j main_end 45 | -------------------------------------------------------------------------------- /debug/programs/init.c: -------------------------------------------------------------------------------- 1 | #include "init.h" 2 | #include "encoding.h" 3 | 4 | int main(void); 5 | 6 | trap_handler_t trap_handler[NHARTS] = {0}; 7 | 8 | void set_trap_handler(trap_handler_t handler) 9 | { 10 | unsigned hartid = read_csr(mhartid); 11 | trap_handler[hartid] = handler; 12 | } 13 | 14 | void enable_timer_interrupts() 15 | { 16 | set_csr(mie, MIP_MTIP); 17 | set_csr(mstatus, MSTATUS_MIE); 18 | } 19 | 20 | void handle_trap(unsigned int mcause, void *mepc, void *sp) 21 | { 22 | unsigned hartid = read_csr(mhartid); 23 | if (trap_handler[hartid]) { 24 | trap_handler[hartid](hartid, mcause, mepc, sp); 25 | return; 26 | } 27 | 28 | while (1) 29 | ; 30 | } 31 | 32 | void _exit(int status) 33 | { 34 | // Make sure gcc doesn't inline _exit, so we can actually set a breakpoint 35 | // on it. 36 | volatile int i = 42; 37 | while (i) 38 | ; 39 | // _exit isn't supposed to return. 40 | while (1) 41 | ; 42 | } 43 | 44 | void _init() 45 | { 46 | _exit(main()); 47 | } 48 | -------------------------------------------------------------------------------- /debug/programs/init.h: -------------------------------------------------------------------------------- 1 | #ifndef INIT_H 2 | #define INIT_H 3 | 4 | #ifdef CLINT 5 | #define MTIME (*(volatile long long *)(CLINT + 0xbff8)) 6 | #define MTIMECMP ((volatile long long *)(CLINT + 0x4000)) 7 | #endif 8 | 9 | typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc, 10 | void *sp); 11 | void set_trap_handler(trap_handler_t handler); 12 | void enable_timer_interrupts(); 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /debug/programs/interrupt.c: -------------------------------------------------------------------------------- 1 | #include "init.h" 2 | #include "encoding.h" 3 | 4 | static volatile unsigned interrupt_count; 5 | static volatile unsigned local; 6 | static volatile unsigned keep_running; 7 | 8 | static unsigned delta = 0x100; 9 | void *increment_count(unsigned hartid, unsigned mcause, void *mepc, void *sp) 10 | { 11 | interrupt_count++; 12 | // There is no guarantee that the interrupt is cleared immediately when 13 | // MTIMECMP is written, so stick around here until that happens. 14 | while (read_csr(mip) & MIP_MTIP) { 15 | MTIMECMP[hartid] = MTIME + delta; 16 | } 17 | return mepc; 18 | } 19 | 20 | int main() 21 | { 22 | interrupt_count = 0; 23 | local = 0; 24 | keep_running = 1; 25 | unsigned hartid = read_csr(mhartid); 26 | 27 | set_trap_handler(increment_count); 28 | MTIMECMP[hartid] = MTIME - 1; 29 | enable_timer_interrupts(); 30 | 31 | while (keep_running) { 32 | local++; 33 | } 34 | return 10; 35 | } 36 | -------------------------------------------------------------------------------- /debug/programs/mprv.S: -------------------------------------------------------------------------------- 1 | #include "encoding.h" 2 | #define PGSHIFT 12 3 | 4 | .global main 5 | 6 | .section .text 7 | main: 8 | # Set up a page table entry that maps 0x0... to 0x8... 9 | la t0, page_table 10 | srli t0, t0, PGSHIFT 11 | csrw CSR_SATP, t0 12 | 13 | # update mstatus 14 | csrr t1, CSR_MSTATUS 15 | #if XLEN == 32 16 | li t0, (MSTATUS_MPRV | (SATP_MODE_SV32 << 24)) 17 | #else 18 | li t0, (MSTATUS_MPRV | (SATP_MODE_SV39 << 24)) 19 | #endif 20 | #li t0, ((VM_SV39 << 24)) 21 | or t1, t0, t1 22 | csrw CSR_MSTATUS, t1 23 | 24 | la t0, (loop - 0x80000000) 25 | csrw CSR_MEPC, t0 26 | 27 | # Exit supervisor mode, entering user mode at loop. 28 | mret 29 | 30 | loop: 31 | la t0, data 32 | lw t1, 0(t0) 33 | j loop 34 | 35 | .section .data 36 | data: 37 | .word 0xbead 38 | 39 | .balign 0x1000 40 | page_table: 41 | #if XLEN == 32 42 | .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) 43 | #else 44 | .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) 45 | .word 0 46 | #endif 47 | -------------------------------------------------------------------------------- /debug/programs/priv.S: -------------------------------------------------------------------------------- 1 | #include "encoding.h" 2 | 3 | .global main 4 | 5 | .section .text 6 | main: 7 | # MISA is only readable from machine mode 8 | csrr t0, CSR_MISA 9 | csrr t0, CSR_MISA 10 | csrr t0, CSR_MISA 11 | csrr t0, CSR_MISA 12 | -------------------------------------------------------------------------------- /debug/programs/regs.S: -------------------------------------------------------------------------------- 1 | #if XLEN == 64 2 | # define LREG ld 3 | # define SREG sd 4 | # define REGBYTES 8 5 | #else 6 | # define LREG lw 7 | # define SREG sw 8 | # define REGBYTES 4 9 | #endif 10 | 11 | #include "encoding.h" 12 | 13 | .global main 14 | main: 15 | nop 16 | j main 17 | 18 | write_regs: 19 | SREG x2, 0(x1) 20 | SREG x3, 8(x1) 21 | SREG x4, 16(x1) 22 | SREG x5, 24(x1) 23 | SREG x6, 32(x1) 24 | SREG x7, 40(x1) 25 | SREG x8, 48(x1) 26 | SREG x9, 56(x1) 27 | SREG x10, 64(x1) 28 | SREG x11, 72(x1) 29 | SREG x12, 80(x1) 30 | SREG x13, 88(x1) 31 | SREG x14, 96(x1) 32 | SREG x15, 104(x1) 33 | #ifndef RV32E 34 | SREG x16, 112(x1) 35 | SREG x17, 120(x1) 36 | SREG x18, 128(x1) 37 | SREG x19, 136(x1) 38 | SREG x20, 144(x1) 39 | SREG x21, 152(x1) 40 | SREG x22, 160(x1) 41 | SREG x23, 168(x1) 42 | SREG x24, 176(x1) 43 | SREG x25, 184(x1) 44 | SREG x26, 192(x1) 45 | SREG x27, 200(x1) 46 | SREG x28, 208(x1) 47 | SREG x29, 216(x1) 48 | SREG x30, 224(x1) 49 | SREG x31, 232(x1) 50 | #endif 51 | 52 | csrr x1, CSR_MSCRATCH 53 | 54 | all_done: 55 | j all_done 56 | 57 | .section .bss 58 | .balign 16 59 | data: 60 | .fill 64, 8, 0 61 | -------------------------------------------------------------------------------- /debug/programs/run_halt_timing.S: -------------------------------------------------------------------------------- 1 | #if XLEN == 64 2 | # define LREG ld 3 | # define SREG sd 4 | # define REGBYTES 8 5 | #else 6 | # define LREG lw 7 | # define SREG sw 8 | # define REGBYTES 4 9 | #endif 10 | 11 | #ifdef CLINT 12 | #define MTIME_ADDR CLINT + 0xbff8 13 | #endif 14 | 15 | .global main 16 | main: 17 | li s0, 0 18 | li s1, MTIME_ADDR 19 | loop: 20 | addi s0, s0, 1 21 | LREG s2, 0(s1) 22 | j loop 23 | -------------------------------------------------------------------------------- /debug/programs/step.S: -------------------------------------------------------------------------------- 1 | // Test stepping over a variety of instructions. 2 | 3 | .global main 4 | 5 | main: 6 | la t0, trap_entry // 0, 4 7 | csrw mtvec, t0 // 0x8 8 | 9 | li t0, 5 // 0xc 10 | beq zero, zero, one // 0x10 11 | nop // 0x14 12 | one: 13 | beq zero, t0, one // 0x18 14 | // Use t0 instead of ra to force a 32-bit opcode in C mode. Otherwise 15 | // 32-bit and 64-bit binaries end up with different instructions (I 16 | // didn't pursue this). 17 | jal t0, two // 0x1c 18 | 19 | three: 20 | .word 0 // 0x20 21 | nop // 0x24 22 | 23 | two: 24 | jr t0 // 0x28 25 | 26 | .align 2 27 | trap_entry: 28 | j trap_entry // 0x2c 29 | -------------------------------------------------------------------------------- /debug/requirements.txt: -------------------------------------------------------------------------------- 1 | pexpect>=4.0.0 2 | pyyaml>=3.12 3 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike-1.cfg: -------------------------------------------------------------------------------- 1 | adapter speed 10000 2 | 3 | adapter driver remote_bitbang 4 | remote_bitbang host $::env(REMOTE_BITBANG_HOST) 5 | remote_bitbang port $::env(REMOTE_BITBANG_PORT) 6 | 7 | set _CHIPNAME riscv 8 | jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef 9 | 10 | set _TARGETNAME $_CHIPNAME.cpu 11 | if {$::env(USE_FREERTOS)} { 12 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos FreeRTOS 13 | } else { 14 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 15 | } 16 | $_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1 17 | 18 | gdb_report_data_abort enable 19 | gdb_report_register_access_error enable 20 | 21 | # Expose an unimplemented CSR so we can test non-existent register access 22 | # behavior. 23 | riscv expose_csrs 2288 24 | riscv expose_custom 1,12345-12348 25 | 26 | init 27 | 28 | set challenge [riscv authdata_read] 29 | riscv authdata_write [expr {$challenge + 1}] 30 | 31 | halt 32 | 33 | arm semihosting enable 34 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike-2-hwthread.cfg: -------------------------------------------------------------------------------- 1 | # Connect to a mult-icore RISC-V target, exposing each hart as a thread. 2 | adapter speed 10000 3 | 4 | adapter driver remote_bitbang 5 | remote_bitbang host $::env(REMOTE_BITBANG_HOST) 6 | remote_bitbang port $::env(REMOTE_BITBANG_PORT) 7 | 8 | set _CHIPNAME riscv 9 | jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef 10 | 11 | set _TARGETNAME_0 $_CHIPNAME.cpu0 12 | set _TARGETNAME_1 $_CHIPNAME.cpu1 13 | target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread 14 | target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 15 | target smp $_TARGETNAME_0 $_TARGETNAME_1 16 | 17 | gdb_report_data_abort enable 18 | gdb_report_register_access_error enable 19 | 20 | # Expose an unimplemented CSR so we can test non-existent register access 21 | # behavior. 22 | foreach t [target names] { 23 | targets $t 24 | riscv expose_csrs 2288 25 | riscv expose_custom 1,12345-12348 26 | } 27 | 28 | riscv resume_order reversed 29 | 30 | init 31 | 32 | set challenge [riscv authdata_read] 33 | riscv authdata_write [expr {$challenge + 1}] 34 | 35 | halt 36 | 37 | foreach t [target names] { 38 | targets $t 39 | arm semihosting enable 40 | } 41 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike-2.cfg: -------------------------------------------------------------------------------- 1 | # Connect to a mult-icore RISC-V target, exposing each hart as a thread. 2 | adapter speed 10000 3 | 4 | adapter driver remote_bitbang 5 | remote_bitbang host $::env(REMOTE_BITBANG_HOST) 6 | remote_bitbang port $::env(REMOTE_BITBANG_PORT) 7 | 8 | set _CHIPNAME riscv 9 | jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef 10 | 11 | set _TARGETNAME_0 $_CHIPNAME.cpu0 12 | set _TARGETNAME_1 $_CHIPNAME.cpu1 13 | target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 14 | target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 15 | 16 | gdb_report_data_abort enable 17 | gdb_report_register_access_error enable 18 | 19 | # Expose an unimplemented CSR so we can test non-existent register access 20 | # behavior. 21 | foreach t [target names] { 22 | targets $t 23 | riscv expose_csrs 2288 24 | riscv expose_custom 1,12345-12348 25 | } 26 | 27 | init 28 | 29 | set challenge [riscv authdata_read] 30 | riscv authdata_write [expr {$challenge + 1}] 31 | 32 | foreach t [target names] { 33 | targets $t 34 | halt 35 | arm semihosting enable 36 | } 37 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike-multi.py: -------------------------------------------------------------------------------- 1 | import spike32 # pylint: disable=import-error 2 | import spike64 # pylint: disable=import-error 3 | 4 | import targets 5 | import testlib 6 | 7 | class multispike(targets.Target): 8 | harts = [ 9 | spike32.spike32_hart(misa=0x4034112d, system=0), 10 | spike32.spike32_hart(misa=0x4034112d, system=0), 11 | spike64.spike64_hart(misa=0x8000000000341129, system=1), 12 | spike64.spike64_hart(misa=0x8000000000341129, system=1)] 13 | openocd_config_path = "spike-multi.cfg" 14 | timeout_sec = 180 15 | server_timeout_sec = 120 16 | implements_custom_test = True 17 | support_hasel = False 18 | support_memory_sampling = False # Needs SBA 19 | 20 | def create(self): 21 | return testlib.MultiSpike( 22 | [ 23 | testlib.Spike(self, isa="RV64IMAFDV", 24 | support_hasel=False, support_abstract_csr=False, 25 | vlen=512, elen=64, harts=self.harts[2:]), 26 | testlib.Spike(self, isa="RV32IMAFDCV", 27 | support_abstract_csr=True, support_haltgroups=False, 28 | # elen must be at least 64 because D is supported. 29 | elen=64, harts=self.harts[:2]), 30 | ]) 31 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike32-2-hwthread.py: -------------------------------------------------------------------------------- 1 | import spike32 # pylint: disable=import-error 2 | 3 | import targets 4 | import testlib 5 | 6 | class spike32_2(targets.Target): 7 | harts = [spike32.spike32_hart(misa=0x40341129), 8 | spike32.spike32_hart(misa=0x40341129)] 9 | openocd_config_path = "spike-2-hwthread.cfg" 10 | timeout_sec = 180 11 | implements_custom_test = True 12 | support_memory_sampling = False # not supported without sba 13 | support_unavailable_control = True 14 | 15 | def create(self): 16 | return testlib.Spike(self, isa="RV32IMAFDV", support_hasel=True, 17 | support_haltgroups=False) 18 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike32-2.py: -------------------------------------------------------------------------------- 1 | import spike32 # pylint: disable=import-error 2 | 3 | import targets 4 | import testlib 5 | 6 | class spike32_2(targets.Target): 7 | harts = [spike32.spike32_hart(misa=0x40141125), 8 | spike32.spike32_hart(misa=0x40141125)] 9 | openocd_config_path = "spike-2.cfg" 10 | timeout_sec = 180 11 | implements_custom_test = True 12 | support_unavailable_control = True 13 | 14 | def create(self): 15 | return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4, 16 | support_abstract_csr=True, support_abstract_fpr=True, 17 | support_haltgroups=False) 18 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike32.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | /* Leave some space for pk's data structures, which includes tohost/fromhost 6 | * which are special addresses we ought to leave alone. */ 7 | . = 0x10110000; 8 | .text : 9 | { 10 | *(.text.entry) 11 | *(.text) 12 | *(.text.*) 13 | } 14 | 15 | /* data segment */ 16 | .rodata : { *(.rodata .rodata.*) } 17 | 18 | .data : { *(.data .data.*) } 19 | 20 | .sdata : { 21 | __global_pointer$ = . + 0x800; 22 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 23 | *(.srodata*) 24 | *(.sdata .sdata.* .gnu.linkonce.s.*) 25 | } 26 | 27 | /* bss segment */ 28 | __bss_start = .; 29 | .sbss : { 30 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 31 | *(.scommon) 32 | } 33 | .bss : { *(.bss .bss.*) } 34 | __bss_end = .; 35 | 36 | __malloc_start = .; 37 | . = . + 512; 38 | 39 | /* End of uninitalized data segement */ 40 | _end = .; 41 | } 42 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike32.py: -------------------------------------------------------------------------------- 1 | import targets 2 | import testlib 3 | 4 | class spike32_hart(targets.Hart): 5 | xlen = 32 6 | ram = 0x10100000 7 | ram_size = 0x10000000 8 | bad_address = ram - 8 9 | instruction_hardware_breakpoint_count = 4 10 | reset_vectors = [0x1000] 11 | link_script_path = "spike32.lds" 12 | 13 | class spike32(targets.Target): 14 | harts = [spike32_hart(misa=0x4034112d)] 15 | openocd_config_path = "spike-1.cfg" 16 | timeout_sec = 180 17 | implements_custom_test = True 18 | support_memory_sampling = False # Needs SBA 19 | freertos_binary = "bin/RTOSDemo32.axf" 20 | support_unavailable_control = True 21 | 22 | def create(self): 23 | # 64-bit FPRs on 32-bit target 24 | return testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4, 25 | support_abstract_csr=True, support_haltgroups=False, 26 | # elen must be at least 64 because D is supported. 27 | elen=64) 28 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike64-2-hwthread.py: -------------------------------------------------------------------------------- 1 | import spike64 # pylint: disable=import-error 2 | 3 | import targets 4 | import testlib 5 | 6 | class spike64_2(targets.Target): 7 | harts = [spike64.spike64_hart(misa=0x8000000000341129), 8 | spike64.spike64_hart(misa=0x8000000000341129)] 9 | openocd_config_path = "spike-2-hwthread.cfg" 10 | timeout_sec = 180 11 | implements_custom_test = True 12 | support_hasel = False 13 | support_memory_sampling = False # Needs SBA 14 | support_unavailable_control = True 15 | 16 | def create(self): 17 | return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, 18 | support_hasel=False, support_abstract_csr=False, 19 | vlen=512, elen=64) 20 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike64-2-rtos.py: -------------------------------------------------------------------------------- 1 | import spike64 # pylint: disable=import-error 2 | 3 | import targets 4 | import testlib 5 | 6 | class spike64_2_rtos(targets.Target): 7 | harts = [spike64.spike64_hart(misa=0x8000000000141129), 8 | spike64.spike64_hart(misa=0x8000000000141129)] 9 | openocd_config_path = "spike-rtos.cfg" 10 | timeout_sec = 180 11 | implements_custom_test = True 12 | support_hasel = False 13 | test_semihosting = False 14 | support_manual_hwbp = False # not supported with `-rtos riscv` 15 | support_memory_sampling = False # not supported with `-rtos riscv` 16 | support_unavailable_control = True 17 | 18 | def create(self): 19 | return testlib.Spike(self, abstract_rti=30, support_hasel=False, 20 | support_abstract_csr=False) 21 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike64-2.py: -------------------------------------------------------------------------------- 1 | import spike64 # pylint: disable=import-error 2 | 3 | import targets 4 | import testlib 5 | 6 | class spike64_2(targets.Target): 7 | harts = [spike64.spike64_hart(misa=0x8000000000141129), 8 | spike64.spike64_hart(misa=0x8000000000141129)] 9 | openocd_config_path = "spike-2.cfg" 10 | timeout_sec = 180 11 | implements_custom_test = True 12 | support_memory_sampling = False # Needs SBA 13 | support_unavailable_control = True 14 | 15 | def create(self): 16 | return testlib.Spike(self) 17 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike64.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x1212340000; 6 | .text : 7 | { 8 | *(.text.entry) 9 | *(.text) 10 | *(.text.*) 11 | } 12 | 13 | /* data segment */ 14 | .rodata : { *(.rodata .rodata.*) } 15 | 16 | .data : { *(.data .data.*) } 17 | 18 | .sdata : { 19 | __global_pointer$ = . + 0x800; 20 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 21 | *(.srodata*) 22 | *(.sdata .sdata.* .gnu.linkonce.s.*) 23 | } 24 | 25 | /* bss segment */ 26 | __bss_start = .; 27 | .sbss : { 28 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 29 | *(.scommon) 30 | } 31 | .bss : { *(.bss .bss.*) } 32 | __bss_end = .; 33 | 34 | __malloc_start = .; 35 | . = . + 512; 36 | 37 | /* End of uninitalized data segement */ 38 | _end = .; 39 | } 40 | -------------------------------------------------------------------------------- /debug/targets/RISC-V/spike64.py: -------------------------------------------------------------------------------- 1 | import targets 2 | import testlib 3 | 4 | class spike64_hart(targets.Hart): 5 | xlen = 64 6 | ram = 0x1212340000 7 | ram_size = 0x10000000 8 | bad_address = ram - 8 9 | instruction_hardware_breakpoint_count = 4 10 | reset_vectors = [0x1000] 11 | link_script_path = "spike64.lds" 12 | misa = 0x8000000000141125 13 | 14 | class spike64(targets.Target): 15 | harts = [spike64_hart()] 16 | openocd_config_path = "spike-1.cfg" 17 | timeout_sec = 180 18 | implements_custom_test = True 19 | freertos_binary = "bin/RTOSDemo64.axf" 20 | support_unavailable_control = True 21 | 22 | def create(self): 23 | # 32-bit FPRs only 24 | return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0, 25 | abstract_rti=30, support_abstract_csr=True, 26 | support_abstract_fpr=True) 27 | -------------------------------------------------------------------------------- /debug/targets/SiFive/Freedom/E300.py: -------------------------------------------------------------------------------- 1 | import targets 2 | 3 | class E300Hart(targets.Hart): 4 | xlen = 32 5 | ram = 0x80000000 6 | ram_size = 64 * 1024 7 | instruction_hardware_breakpoint_count = 2 8 | link_script_path = "Freedom.lds" 9 | 10 | class E300(targets.Target): 11 | openocd_config_path = "Freedom.cfg" 12 | harts = [E300Hart()] 13 | invalid_memory_returns_zero = True 14 | -------------------------------------------------------------------------------- /debug/targets/SiFive/Freedom/Freedom.cfg: -------------------------------------------------------------------------------- 1 | adapter speed 10000 2 | 3 | source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] 4 | 5 | set _CHIPNAME riscv 6 | jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 7 | 8 | set _TARGETNAME $_CHIPNAME.cpu 9 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv 10 | 11 | init 12 | 13 | halt 14 | echo "Ready for Remote Connections" 15 | -------------------------------------------------------------------------------- /debug/targets/SiFive/Freedom/Freedom.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x80000000; 6 | .text : 7 | { 8 | *(.text.entry) 9 | *(.text) 10 | } 11 | 12 | /* data segment */ 13 | .data : { *(.data) } 14 | 15 | .sdata : { 16 | __global_pointer$ = . + 0x800; 17 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 18 | *(.srodata*) 19 | *(.sdata .sdata.* .gnu.linkonce.s.*) 20 | } 21 | 22 | /* bss segment */ 23 | __bss_start = .; 24 | .sbss : { 25 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 26 | *(.scommon) 27 | } 28 | .bss : { *(.bss) } 29 | __bss_end = .; 30 | 31 | __malloc_start = .; 32 | . = . + 512; 33 | 34 | /* End of uninitalized data segement */ 35 | _end = .; 36 | } 37 | -------------------------------------------------------------------------------- /debug/targets/SiFive/Freedom/U500.py: -------------------------------------------------------------------------------- 1 | import targets 2 | 3 | class U500Hart(targets.Hart): 4 | xlen = 64 5 | ram = 0x80000000 6 | ram_size = 64 * 1024 7 | instruction_hardware_breakpoint_count = 2 8 | link_script_path = "Freedom.lds" 9 | 10 | class U500(targets.Target): 11 | openocd_config_path = "Freedom.cfg" 12 | harts = [U500Hart()] 13 | invalid_memory_returns_zero = True 14 | -------------------------------------------------------------------------------- /debug/targets/SiFive/Freedom/U500Sim.py: -------------------------------------------------------------------------------- 1 | import targets 2 | import testlib 3 | 4 | class U500Hart(targets.Hart): 5 | xlen = 64 6 | ram = 0x80000000 7 | ram_size = 256 * 1024 * 1024 8 | instruction_hardware_breakpoint_count = 2 9 | link_script_path = "Freedom.lds" 10 | 11 | class U500Sim(targets.Target): 12 | timeout_sec = 6000 13 | openocd_config_path = "Freedom.cfg" 14 | harts = [U500Hart()] 15 | 16 | def target(self): 17 | return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) 18 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFive1-flash.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY 4 | { 5 | flash (rxl) : ORIGIN = 0x20400000, LENGTH = 128K 6 | ram (wx) : ORIGIN = 0x80000000, LENGTH = 16K 7 | } 8 | 9 | SECTIONS 10 | { 11 | flash_text : { 12 | *(.text.entry) 13 | *(.text) 14 | } >flash 15 | 16 | /* data segment */ 17 | .data : { *(.data) } >ram 18 | 19 | .sdata : { 20 | __global_pointer$ = . + 0x800; 21 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 22 | *(.srodata*) 23 | *(.sdata .sdata.* .gnu.linkonce.s.*) 24 | } >ram 25 | 26 | /* bss segment */ 27 | __bss_start = .; 28 | .sbss : { 29 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 30 | *(.scommon) 31 | } >ram 32 | .bss : { *(.bss) } >ram 33 | __bss_end = .; 34 | 35 | __malloc_start = .; 36 | . = . + 512; 37 | 38 | /* End of uninitalized data segement */ 39 | _end = .; 40 | } 41 | 42 | ENTRY(_start) 43 | 44 | ASSERT(_end < 0x80004000, "program is too large") 45 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFive1-flash.py: -------------------------------------------------------------------------------- 1 | import targets 2 | 3 | # Like HiFive1, but put code in flash 4 | 5 | class HiFive1FlashHart(targets.Hart): 6 | xlen = 32 7 | ram = 0x80000000 8 | ram_size = 16 * 1024 9 | instruction_hardware_breakpoint_count = 2 10 | misa = 0x40001105 11 | link_script_path = "HiFive1-flash.lds" 12 | 13 | class HiFive1Flash(targets.Target): 14 | harts = [HiFive1FlashHart()] 15 | openocd_config_path = "HiFive1.cfg" 16 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFive1.cfg: -------------------------------------------------------------------------------- 1 | adapter speed 10000 2 | 3 | adapter driver ftdi 4 | ftdi device_desc "Dual RS232-HS" 5 | ftdi vid_pid 0x0403 0x6010 6 | 7 | ftdi layout_init 0x0008 0x001b 8 | ftdi layout_signal nSRST -oe 0x0020 9 | 10 | # ... 11 | 12 | set _CHIPNAME riscv 13 | jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 14 | 15 | set _TARGETNAME $_CHIPNAME.cpu 16 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 17 | $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 18 | #-rtos riscv 19 | 20 | gdb_report_data_abort enable 21 | gdb_report_register_access_error enable 22 | 23 | # Expose an unimplemented CSR so we can test non-existent register access 24 | # behavior. 25 | riscv expose_csrs 2288 26 | 27 | flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME 28 | init 29 | #reset 30 | halt 31 | flash protect 0 64 last off 32 | 33 | echo "Ready for Remote Connections" 34 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFive1.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x80000000; 6 | .text : 7 | { 8 | *(.text.entry) 9 | *(.text) 10 | } 11 | 12 | /* data segment */ 13 | .data : { *(.data) } 14 | 15 | .sdata : { 16 | __global_pointer$ = . + 0x800; 17 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 18 | *(.srodata*) 19 | *(.sdata .sdata.* .gnu.linkonce.s.*) 20 | } 21 | 22 | /* bss segment */ 23 | __bss_start = .; 24 | .sbss : { 25 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 26 | *(.scommon) 27 | } 28 | .bss : { *(.bss) } 29 | __bss_end = .; 30 | 31 | __malloc_start = .; 32 | . = . + 512; 33 | 34 | /* End of uninitalized data segement */ 35 | _end = .; 36 | } 37 | 38 | ASSERT(_end < 0x80004000, "program is too large") 39 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFive1.py: -------------------------------------------------------------------------------- 1 | import targets 2 | 3 | class HiFive1Hart(targets.Hart): 4 | xlen = 32 5 | ram = 0x80000000 6 | ram_size = 16 * 1024 7 | instruction_hardware_breakpoint_count = 2 8 | misa = 0x40001105 9 | 10 | class HiFive1(targets.Target): 11 | harts = [HiFive1Hart()] 12 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFiveUnleashed-flash.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x20000000; 6 | .text : 7 | { 8 | *(.text.entry) 9 | *(.text) 10 | } 11 | _text_end = .; 12 | 13 | . = 0x80000000; 14 | /* data segment */ 15 | .data : { *(.data) } 16 | 17 | .sdata : { 18 | __global_pointer$ = . + 0x800; 19 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 20 | *(.srodata*) 21 | *(.sdata .sdata.* .gnu.linkonce.s.*) 22 | } 23 | 24 | /* bss segment */ 25 | __bss_start = .; 26 | .sbss : { 27 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 28 | *(.scommon) 29 | } 30 | .bss : { *(.bss) } 31 | __bss_end = .; 32 | 33 | __malloc_start = .; 34 | . = . + 512; 35 | 36 | /* End of uninitalized data segement */ 37 | _end = .; 38 | } 39 | 40 | ASSERT(_text_end < 0x20100000, "program is too large") 41 | ASSERT(_end < 0x80100000, "program is too large") 42 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFiveUnleashed-flash.py: -------------------------------------------------------------------------------- 1 | import targets 2 | 3 | class E51(targets.Hart): 4 | xlen = 64 5 | ram = 0x80000000 6 | ram_size = 1024 * 1024 7 | bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1 8 | instruction_hardware_breakpoint_count = 2 9 | link_script_path = "HiFiveUnleashed-flash.lds" 10 | reset_vectors = [0x1004] 11 | 12 | class U54(targets.Hart): 13 | xlen = 64 14 | ram = 0x80000000 15 | ram_size = 1024 * 1024 16 | bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1 17 | instruction_hardware_breakpoint_count = 2 18 | link_script_path = "HiFiveUnleashed-flash.lds" 19 | reset_vectors = [0x1004] 20 | 21 | class HiFiveUnleashedFlash(targets.Target): 22 | support_hasel = False 23 | harts = [E51(), U54(), U54(), U54(), U54()] 24 | support_memory_sampling = False # Needs SBA 25 | openocd_config_path = "HiFiveUnleashed.cfg" 26 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFiveUnleashed.lds: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | SECTIONS 4 | { 5 | . = 0x80000000; 6 | .text : 7 | { 8 | *(.text.entry) 9 | *(.text) 10 | } 11 | 12 | /* data segment */ 13 | .data : { *(.data) } 14 | 15 | .sdata : { 16 | __global_pointer$ = . + 0x800; 17 | *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) 18 | *(.srodata*) 19 | *(.sdata .sdata.* .gnu.linkonce.s.*) 20 | } 21 | 22 | /* bss segment */ 23 | __bss_start = .; 24 | .sbss : { 25 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 26 | *(.scommon) 27 | } 28 | .bss : { *(.bss) } 29 | __bss_end = .; 30 | 31 | __malloc_start = .; 32 | . = . + 512; 33 | 34 | /* End of uninitalized data segement */ 35 | _end = .; 36 | } 37 | 38 | ASSERT(_end < 0x80100000, "program is too large") 39 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFiveUnleashed.py: -------------------------------------------------------------------------------- 1 | import targets 2 | 3 | class E51(targets.Hart): 4 | xlen = 64 5 | ram = 0x80000000 6 | ram_size = 1024 * 1024 7 | bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1 8 | instruction_hardware_breakpoint_count = 2 9 | reset_vectors = [0x1004] 10 | misa = 0x8000000000101105 11 | 12 | class U54(targets.Hart): 13 | xlen = 64 14 | ram = 0x80000000 15 | ram_size = 1024 * 1024 16 | bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1 17 | instruction_hardware_breakpoint_count = 2 18 | reset_vectors = [0x1004] 19 | misa = 0x800000000014112d 20 | 21 | class HiFiveUnleashed(targets.Target): 22 | support_hasel = False 23 | support_memory_sampling = False # Needs SBA 24 | harts = [E51(), U54(), U54(), U54(), U54()] 25 | -------------------------------------------------------------------------------- /debug/targets/SiFive/HiFiveUnleashed_setup.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv-software-src/riscv-tests/355f1fb9b8a7142bee718e4123fea0aa8f49c319/debug/targets/SiFive/HiFiveUnleashed_setup.bin -------------------------------------------------------------------------------- /isa/.gitignore: -------------------------------------------------------------------------------- 1 | rv*-* 2 | -------------------------------------------------------------------------------- /isa/hypervisor/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for hypervisor tests 3 | #----------------------------------------------------------------------- 4 | 5 | hypervisor_sc_tests = \ 6 | 2-stage_translation \ 7 | 8 | hypervisor_p_tests = $(addprefix hypervisor-p-, $(hypervisor_sc_tests)) 9 | -------------------------------------------------------------------------------- /isa/rv32mi/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32mi tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32mi_sc_tests = \ 6 | breakpoint \ 7 | csr \ 8 | mcsr \ 9 | illegal \ 10 | ma_fetch \ 11 | ma_addr \ 12 | scall \ 13 | sbreak \ 14 | shamt \ 15 | lw-misaligned \ 16 | lh-misaligned \ 17 | sh-misaligned \ 18 | sw-misaligned \ 19 | zicntr \ 20 | instret_overflow \ 21 | pmpaddr \ 22 | 23 | rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests)) 24 | -------------------------------------------------------------------------------- /isa/rv32mi/breakpoint.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/breakpoint.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/csr.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/illegal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/illegal.S" 8 | -------------------------------------------------------------------------------- /isa/rv32mi/instret_overflow.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/instret_overflow.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/lh-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/lh-misaligned.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/lw-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/lw-misaligned.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/ma_addr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/ma_addr.S" 8 | -------------------------------------------------------------------------------- /isa/rv32mi/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/ma_fetch.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/mcsr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #include "../rv64mi/mcsr.S" 8 | -------------------------------------------------------------------------------- /isa/rv32mi/pmpaddr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/pmpaddr.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/sbreak.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/scall.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/sh-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/sh-misaligned.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/shamt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # shamt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test illegal shamt[5] of shift instruction in 32-bit ISA. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32M 14 | RVTEST_CODE_BEGIN 15 | 16 | # Make sure slli with shamt[4] set is legal. 17 | TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); 18 | 19 | # Make sure slli with shamt[5] set is not legal. 20 | TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32 21 | 22 | TEST_PASSFAIL 23 | 24 | .align 2 25 | .global mtvec_handler 26 | mtvec_handler: 27 | # Trapping on test 3 is good. 28 | li t0, 3 29 | bne TESTNUM, t0, fail 30 | 31 | # Make sure CAUSE indicates an illegal instructino. 32 | csrr t0, mcause 33 | li t1, CAUSE_ILLEGAL_INSTRUCTION 34 | bne t0, t1, fail 35 | j pass 36 | 37 | RVTEST_CODE_END 38 | 39 | .data 40 | RVTEST_DATA_BEGIN 41 | 42 | TEST_DATA 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /isa/rv32mi/sw-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/sw-misaligned.S" 9 | -------------------------------------------------------------------------------- /isa/rv32mi/zicntr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64mi/zicntr.S" 9 | -------------------------------------------------------------------------------- /isa/rv32si/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | ma_fetch \ 9 | scall \ 10 | sbreak \ 11 | wfi \ 12 | 13 | rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) 14 | -------------------------------------------------------------------------------- /isa/rv32si/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/csr.S" 8 | -------------------------------------------------------------------------------- /isa/rv32si/dirty.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64M 5 | #define RVTEST_RV64M RVTEST_RV32M 6 | 7 | #undef SATP_MODE_SV39 8 | #define SATP_MODE_SV39 SATP_MODE_SV32 9 | 10 | #include "../rv64si/dirty.S" 11 | -------------------------------------------------------------------------------- /isa/rv32si/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/ma_fetch.S" 8 | -------------------------------------------------------------------------------- /isa/rv32si/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/sbreak.S" 8 | -------------------------------------------------------------------------------- /isa/rv32si/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/scall.S" 8 | -------------------------------------------------------------------------------- /isa/rv32si/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV32S 6 | 7 | #include "../rv64si/wfi.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ua tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ua_sc_tests = \ 6 | amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ 7 | lrsc \ 8 | 9 | rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) 10 | rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) 11 | -------------------------------------------------------------------------------- /isa/rv32ua/amoadd_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoadd_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amoand_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoand_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amomax_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomax_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amomaxu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomaxu_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amomin_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amomin_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amominu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amominu_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amoor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoor_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amoswap_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoswap_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/amoxor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/amoxor_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ua/lrsc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ua/lrsc.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uc_sc_tests = \ 6 | rvc \ 7 | 8 | rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests)) 9 | rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests)) 10 | -------------------------------------------------------------------------------- /isa/rv32uc/rvc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uc/rvc.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ud tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ud_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst recoding \ 8 | 9 | # TODO: use this line instead of the last of the previous once move and structural tests have been implemented 10 | # ldst move structural recoding \ 11 | 12 | rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests)) 13 | rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests)) 14 | -------------------------------------------------------------------------------- /isa/rv32ud/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fadd.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fclass.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcmp.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fcvt.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "test_macros.h" 8 | #undef TEST_FP_INT_OP_D 9 | #define TEST_FP_INT_OP_D TEST_FP_INT_OP_D32 10 | 11 | #include "../rv64ud/fcvt_w.S" 12 | -------------------------------------------------------------------------------- /isa/rv32ud/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fdiv.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fmadd.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/fmin.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32UF 14 | RVTEST_CODE_BEGIN 15 | 16 | la s0, tdat 17 | TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 18 | TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 19 | TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 20 | TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 21 | TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) 22 | 23 | TEST_PASSFAIL 24 | 25 | RVTEST_CODE_END 26 | 27 | .data 28 | RVTEST_DATA_BEGIN 29 | 30 | TEST_DATA 31 | 32 | tdat: 33 | .word 0xbf800000 34 | .word 0x40000000 35 | .word 0x40400000 36 | .word 0xc0800000 37 | .word 0xdeadbeef 38 | .word 0xcafebabe 39 | .word 0xabad1dea 40 | .word 0x1337d00d 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /isa/rv32ud/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/move.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ud/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64ud/recoding.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uf tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uf_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests)) 10 | rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests)) 11 | -------------------------------------------------------------------------------- /isa/rv32uf/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fadd.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fclass.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcmp.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fcvt_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fdiv.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fmadd.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/fmin.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32UF 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1)) 17 | TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RVTEST_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf800000 30 | .word 0x40000000 31 | .word 0x40400000 32 | .word 0xc0800000 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /isa/rv32uf/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/move.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uf/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uf/recoding.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32ui tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32ui_sc_tests = \ 6 | simple \ 7 | add addi \ 8 | and andi \ 9 | auipc \ 10 | beq bge bgeu blt bltu bne \ 11 | fence_i \ 12 | jal jalr \ 13 | lb lbu lh lhu lw ld_st \ 14 | lui \ 15 | ma_data \ 16 | or ori \ 17 | sb sh sw st_ld \ 18 | sll slli \ 19 | slt slti sltiu sltu \ 20 | sra srai \ 21 | srl srli \ 22 | sub \ 23 | xor xori \ 24 | 25 | rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) 26 | rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests)) 27 | -------------------------------------------------------------------------------- /isa/rv32ui/add.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/add.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/addi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/addi.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/and.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/and.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/andi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/andi.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/auipc.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/beq.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/beq.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/bge.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bge.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/bgeu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bgeu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/blt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/blt.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/bltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bltu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/bne.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/bne.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/fence_i.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/jal.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/jalr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/jalr.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/lb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lb.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/lbu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lbu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/ld_st.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/ld_st.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/lh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lh.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/lhu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lhu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lui.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/lw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/lw.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/ma_data.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/ma_data.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/or.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/or.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/ori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/ori.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sb.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sh.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/simple.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sll.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sll.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/slli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slli.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/slt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slt.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/slti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/slti.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sltiu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sltiu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sltu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sra.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sra.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/srai.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srai.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/srl.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srl.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/srli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/srli.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/st_ld.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/st_ld.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sub.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sub.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/sw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/sw.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/xor.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/xor.S" 8 | -------------------------------------------------------------------------------- /isa/rv32ui/xori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64ui/xori.S" 8 | -------------------------------------------------------------------------------- /isa/rv32um/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32um tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32um_sc_tests = \ 6 | div divu \ 7 | mul mulh mulhsu mulhu \ 8 | rem remu \ 9 | 10 | rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests)) 11 | rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests)) 12 | -------------------------------------------------------------------------------- /isa/rv32um/div.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # div.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test div instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, div, 3, 20, 6 ); 21 | TEST_RR_OP( 3, div, -3, -20, 6 ); 22 | TEST_RR_OP( 4, div, -3, 20, -6 ); 23 | TEST_RR_OP( 5, div, 3, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, div, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, div, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, div, -1, 1, 0 ); 30 | TEST_RR_OP(10, div, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv32um/divu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divu, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divu, 715827879, -20, 6 ); 22 | TEST_RR_OP( 4, divu, 0, 20, -6 ); 23 | TEST_RR_OP( 5, divu, 0, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, divu, -1, 1, 0 ); 30 | TEST_RR_OP(10, divu, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv32um/rem.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # rem.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test rem instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, rem, 2, 20, 6 ); 21 | TEST_RR_OP( 3, rem, -2, -20, 6 ); 22 | TEST_RR_OP( 4, rem, 2, 20, -6 ); 23 | TEST_RR_OP( 5, rem, -2, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, rem, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, rem, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, rem, 1, 1, 0 ); 30 | TEST_RR_OP(10, rem, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv32um/remu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remu, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remu, 2, -20, 6 ); 22 | TEST_RR_OP( 4, remu, 20, 20, -6 ); 23 | TEST_RR_OP( 5, remu, -20, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remu, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, remu, 1, 1, 0 ); 30 | TEST_RR_OP(10, remu, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv32uzba/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uzba tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uzba_sc_tests = \ 6 | sh1add \ 7 | sh2add \ 8 | sh3add \ 9 | 10 | rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests)) 11 | rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests)) 12 | rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests)) 13 | 14 | spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests) 15 | -------------------------------------------------------------------------------- /isa/rv32uzbb/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uzbb tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uzbb_sc_tests = \ 6 | andn \ 7 | clz \ 8 | cpop \ 9 | ctz \ 10 | max maxu \ 11 | min minu \ 12 | orc_b \ 13 | orn \ 14 | rev8 \ 15 | rol \ 16 | ror \ 17 | rori \ 18 | sext_b sext_h \ 19 | xnor \ 20 | zext_h \ 21 | 22 | rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests)) 23 | rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests)) 24 | rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests)) 25 | 26 | spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests) 27 | -------------------------------------------------------------------------------- /isa/rv32uzbb/andn.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/andn.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/max.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/max.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/maxu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/maxu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/min.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/min.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/minu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/minu.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/orn.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/orn.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/sext_b.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/sext_b.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/sext_h.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/sext_h.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/xnor.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/xnor.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbb/zext_h.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbb/zext_h.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uzbc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uzbc_sc_tests = \ 6 | clmul \ 7 | clmulh \ 8 | clmulr \ 9 | 10 | rv32uzbc_p_tests = $(addprefix rv32uzbc-p-, $(rv32uzbc_sc_tests)) 11 | rv32uzbc_v_tests = $(addprefix rv32uzbc-v-, $(rv32uzbc_sc_tests)) 12 | rv32uzbc_ps_tests = $(addprefix rv32uzbc-ps-, $(rv32uzbc_sc_tests)) 13 | 14 | spike_tests += $(rv32uzbc_p_tests) $(rv32uzbc_v_tests) 15 | -------------------------------------------------------------------------------- /isa/rv32uzbs/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uzbs tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uzbs_sc_tests = \ 6 | bclr bclri \ 7 | bext bexti \ 8 | binv binvi \ 9 | bset bseti \ 10 | 11 | rv32uzbs_p_tests = $(addprefix rv32uzbs-p-, $(rv32uzbs_sc_tests)) 12 | rv32uzbs_v_tests = $(addprefix rv32uzbs-v-, $(rv32uzbs_sc_tests)) 13 | rv32uzbs_ps_tests = $(addprefix rv32uzbs-ps-, $(rv32uzbs_sc_tests)) 14 | 15 | spike_tests += $(rv32uzbs_p_tests) $(rv32uzbs_v_tests) 16 | -------------------------------------------------------------------------------- /isa/rv32uzbs/bclr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/bclr.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/bclri.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/bclri.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/bext.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/bext.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/bexti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/bexti.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/binv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/binv.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/binvi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/binvi.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/bset.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/bset.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzbs/bseti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64U 5 | #define RVTEST_RV64U RVTEST_RV32U 6 | 7 | #include "../rv64uzbs/bseti.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv32uzfh tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv32uzfh_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv32uzfh_p_tests = $(addprefix rv32uzfh-p-, $(rv32uzfh_sc_tests)) 10 | rv32uzfh_v_tests = $(addprefix rv32uzfh-v-, $(rv32uzfh_sc_tests)) 11 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/fadd.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/fclass.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/fcmp.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uzfh/fcvt.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fcvt_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UF 5 | #define RVTEST_RV64UF RVTEST_RV32UF 6 | 7 | #include "../rv64uzfh/fcvt_w.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/fdiv.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fmadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/fmadd.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/fmin.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/fmin.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32UF 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0xcafe4000, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); lw a0, 20(a1)) 17 | TEST_CASE(3, a0, 0xabadbf80, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); lw a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RVTEST_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf80bf80 30 | .word 0x40004000 31 | .word 0x40404040 32 | .word 0xc080c080 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /isa/rv32uzfh/move.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/move.S" 8 | -------------------------------------------------------------------------------- /isa/rv32uzfh/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64UH 5 | #define RVTEST_RV64UH RVTEST_RV32UH 6 | 7 | #include "../rv64uzfh/recoding.S" 8 | -------------------------------------------------------------------------------- /isa/rv64mi/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64mi tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64mi_sc_tests = \ 6 | breakpoint \ 7 | csr \ 8 | mcsr \ 9 | illegal \ 10 | ma_fetch \ 11 | ma_addr \ 12 | scall \ 13 | sbreak \ 14 | ld-misaligned \ 15 | lw-misaligned \ 16 | lh-misaligned \ 17 | sh-misaligned \ 18 | sw-misaligned \ 19 | sd-misaligned \ 20 | zicntr \ 21 | instret_overflow \ 22 | pmpaddr \ 23 | 24 | rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) 25 | -------------------------------------------------------------------------------- /isa/rv64mi/csr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/csr.S" 9 | -------------------------------------------------------------------------------- /isa/rv64mi/instret_overflow.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # minstret_overflow.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test if overflow of instret is handled correctly 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64M 14 | RVTEST_CODE_BEGIN 15 | 16 | # The value written to instret will be the value read by the following 17 | # instruction (i.e. the increment is suppressed) 18 | TEST_CASE(2, a0, 0, csrwi minstret, 0; csrr a0, minstret); 19 | 20 | #if __riscv_xlen == 32 21 | # Writes to instreth are considered writes to instret and so also 22 | # suppress the increment 23 | TEST_CASE(3, a0, 0, li t0, 0xffffffff; csrw minstret, t0; csrw minstreth, t0; nop; csrr a0, minstret); 24 | TEST_CASE(4, a0, 0, csrr a0, minstreth); 25 | #endif 26 | 27 | 2: 28 | TEST_PASSFAIL 29 | 30 | .align 2 31 | .global mtvec_handler 32 | mtvec_handler: 33 | j fail 34 | 35 | RVTEST_CODE_END 36 | 37 | .data 38 | RVTEST_DATA_BEGIN 39 | 40 | TEST_DATA 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /isa/rv64mi/ld-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lw-unaligned.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test that misaligned loads work or raise the correct exception 8 | # This test assumes the target is little-endian 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64M 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_LD_OP( 2, ld, 0x0807060504030201, 0, tdat ); 18 | TEST_LD_OP( 3, ld, 0x0908070605040302, 1, tdat ); 19 | TEST_LD_OP( 4, ld, 0x0a09080706050403, 2, tdat ); 20 | TEST_LD_OP( 5, ld, 0x0b0a090807060504, 3, tdat ); 21 | TEST_LD_OP( 6, ld, 0x0c0b0a0908070605, 4, tdat ); 22 | TEST_LD_OP( 7, ld, 0x0d0c0b0a09080706, 5, tdat ); 23 | TEST_LD_OP( 8, ld, 0x0e0d0c0b0a090807, 6, tdat ); 24 | TEST_LD_OP( 9, ld, 0x0f0e0d0c0b0a0908, 7, tdat ); 25 | 26 | 2: 27 | TEST_PASSFAIL 28 | 29 | .align 2 30 | .global mtvec_handler 31 | mtvec_handler: 32 | MISALIGNED_LOAD_HANDLER 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | tdat: 42 | .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 43 | .byte 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 44 | 45 | RVTEST_DATA_END 46 | -------------------------------------------------------------------------------- /isa/rv64mi/lh-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lh-unaligned.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test that misaligned loads work or raise the correct exception 8 | # This test assumes the target is little-endian 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64M 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_LD_OP( 2, lh, 0x0201, 0, tdat ); 18 | TEST_LD_OP( 3, lh, 0x0302, 1, tdat ); 19 | 20 | 2: 21 | TEST_PASSFAIL 22 | 23 | .align 2 24 | .global mtvec_handler 25 | mtvec_handler: 26 | MISALIGNED_LOAD_HANDLER 27 | 28 | RVTEST_CODE_END 29 | 30 | .data 31 | RVTEST_DATA_BEGIN 32 | 33 | TEST_DATA 34 | 35 | tdat: 36 | .byte 0x01, 0x02, 0x03, 0x04 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /isa/rv64mi/lw-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lw-unaligned.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test that misaligned loads work or raise the correct exception 8 | # This test assumes the target is little-endian 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64M 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_LD_OP( 2, lw, 0x04030201, 0, tdat ); 18 | TEST_LD_OP( 3, lw, 0x05040302, 1, tdat ); 19 | TEST_LD_OP( 4, lw, 0x06050403, 2, tdat ); 20 | TEST_LD_OP( 5, lw, 0x07060504, 3, tdat ); 21 | 22 | 2: 23 | TEST_PASSFAIL 24 | 25 | .align 2 26 | .global mtvec_handler 27 | mtvec_handler: 28 | MISALIGNED_LOAD_HANDLER 29 | 30 | RVTEST_CODE_END 31 | 32 | .data 33 | RVTEST_DATA_BEGIN 34 | 35 | TEST_DATA 36 | 37 | tdat: 38 | .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 39 | 40 | RVTEST_DATA_END 41 | -------------------------------------------------------------------------------- /isa/rv64mi/ma_fetch.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/ma_fetch.S" 9 | -------------------------------------------------------------------------------- /isa/rv64mi/mcsr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # mcsr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test various M-mode CSRs. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64M 14 | RVTEST_CODE_BEGIN 15 | 16 | # Check that mcpuid reports the correct XLEN 17 | #if __riscv_xlen == 64 18 | TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) 19 | #else 20 | TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) 21 | #endif 22 | 23 | # Check that mhartid reports 0 24 | TEST_CASE(3, a0, 0x0, csrr a0, mhartid) 25 | 26 | # Check that reading the following CSRs doesn't cause an exception 27 | csrr a0, mimpid 28 | csrr a0, marchid 29 | csrr a0, mvendorid 30 | 31 | # Check that writing the following CSRs doesn't cause an exception 32 | li t0, 0 33 | csrs mtvec, t0 34 | csrs mepc, t0 35 | 36 | TEST_PASSFAIL 37 | 38 | RVTEST_CODE_END 39 | 40 | .data 41 | RVTEST_DATA_BEGIN 42 | 43 | TEST_DATA 44 | 45 | RVTEST_DATA_END 46 | -------------------------------------------------------------------------------- /isa/rv64mi/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/sbreak.S" 9 | -------------------------------------------------------------------------------- /isa/rv64mi/scall.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #include "riscv_test.h" 4 | #undef RVTEST_RV64S 5 | #define RVTEST_RV64S RVTEST_RV64M 6 | #define __MACHINE_MODE 7 | 8 | #include "../rv64si/scall.S" 9 | -------------------------------------------------------------------------------- /isa/rv64mi/sd-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sd-unaligned.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test that misaligned stores work or raise the correct exception 8 | # This test assumes the target is little-endian 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64M 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_ST_OP( 2, ld, sd, 0x0102030405060708, 0, tdat ); 18 | TEST_ST_OP( 3, ld, sd, 0x090a0b0c0d0e0f10, 1, tdat ); 19 | TEST_ST_OP( 4, ld, sd, 0x1112131415161718, 2, tdat ); 20 | TEST_ST_OP( 5, ld, sd, 0x191a1b1c1d1e1f20, 3, tdat ); 21 | TEST_ST_OP( 6, ld, sd, 0x2122232425262728, 4, tdat ); 22 | TEST_ST_OP( 7, ld, sd, 0x292a2b2c2d2e2f30, 5, tdat ); 23 | TEST_ST_OP( 8, ld, sd, 0x3132333435363738, 6, tdat ); 24 | TEST_ST_OP( 9, ld, sd, 0x393a3b3c3d3e3f40, 7, tdat ); 25 | 26 | 2: 27 | TEST_PASSFAIL 28 | 29 | .align 2 30 | .global mtvec_handler 31 | mtvec_handler: 32 | MISALIGNED_STORE_HANDLER 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | tdat: 42 | .zero 16 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /isa/rv64mi/sh-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sh-unaligned.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test that misaligned stores work or raise the correct exception 8 | # This test assumes the target is little-endian 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64M 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_ST_OP( 2, lh, sh, 0x1234, 0, tdat ); 18 | TEST_ST_OP( 3, lh, sh, 0x5678, 1, tdat ); 19 | 20 | 2: 21 | TEST_PASSFAIL 22 | 23 | .align 2 24 | .global mtvec_handler 25 | mtvec_handler: 26 | MISALIGNED_STORE_HANDLER 27 | 28 | RVTEST_CODE_END 29 | 30 | .data 31 | RVTEST_DATA_BEGIN 32 | 33 | TEST_DATA 34 | 35 | tdat: 36 | .zero 4 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /isa/rv64mi/sw-misaligned.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sw-unaligned.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test that misaligned stores work or raise the correct exception 8 | # This test assumes the target is little-endian 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64M 15 | RVTEST_CODE_BEGIN 16 | 17 | TEST_ST_OP( 2, lw, sw, 0x12345678, 0, tdat ); 18 | TEST_ST_OP( 3, lw, sw, 0xffffffff9abcdef0, 1, tdat ); 19 | TEST_ST_OP( 4, lw, sw, 0xffffffffdeadbeef, 2, tdat ); 20 | TEST_ST_OP( 5, lw, sw, 0xfffffffffeed0011, 3, tdat ); 21 | 22 | 2: 23 | TEST_PASSFAIL 24 | 25 | .align 2 26 | .global mtvec_handler 27 | mtvec_handler: 28 | MISALIGNED_STORE_HANDLER 29 | 30 | RVTEST_CODE_END 31 | 32 | .data 33 | RVTEST_DATA_BEGIN 34 | 35 | TEST_DATA 36 | 37 | tdat: 38 | .zero 8 39 | 40 | RVTEST_DATA_END 41 | -------------------------------------------------------------------------------- /isa/rv64mi/zicntr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # zicntr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test if Zicntr is implemented correctly 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64M 14 | RVTEST_CODE_BEGIN 15 | 16 | # Make sure reading the cycle counter in four ways doesn't trap. 17 | TEST_CASE( 2, x0, 0, csrrc x0, cycle, x0); 18 | TEST_CASE( 3, x0, 0, csrrs x0, cycle, x0); 19 | TEST_CASE( 4, x0, 0, csrrci x0, cycle, 0); 20 | TEST_CASE( 5, x0, 0, csrrsi x0, cycle, 0); 21 | TEST_CASE( 6, x0, 0, csrrc x0, instret, x0); 22 | TEST_CASE( 7, x0, 0, csrrs x0, instret, x0); 23 | TEST_CASE( 8, x0, 0, csrrci x0, instret, 0); 24 | TEST_CASE( 9, x0, 0, csrrsi x0, instret, 0); 25 | #if __riscv_xlen == 32 26 | TEST_CASE(12, x0, 0, csrrc x0, cycleh, x0); 27 | TEST_CASE(13, x0, 0, csrrs x0, cycleh, x0); 28 | TEST_CASE(14, x0, 0, csrrci x0, cycleh, 0); 29 | TEST_CASE(15, x0, 0, csrrsi x0, cycleh, 0); 30 | TEST_CASE(16, x0, 0, csrrc x0, instreth, x0); 31 | TEST_CASE(17, x0, 0, csrrs x0, instreth, x0); 32 | TEST_CASE(18, x0, 0, csrrci x0, instreth, 0); 33 | TEST_CASE(19, x0, 0, csrrsi x0, instreth, 0); 34 | #endif 35 | 36 | 2: 37 | TEST_PASSFAIL 38 | 39 | .align 2 40 | .global mtvec_handler 41 | mtvec_handler: 42 | j fail 43 | 44 | RVTEST_CODE_END 45 | 46 | .data 47 | RVTEST_DATA_BEGIN 48 | 49 | TEST_DATA 50 | 51 | RVTEST_DATA_END 52 | -------------------------------------------------------------------------------- /isa/rv64mzicbo/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64mzicbo tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64mzicbo_sc_tests = \ 6 | zero \ 7 | 8 | rv64mzicbo_p_tests = $(addprefix rv64mzicbo-p-, $(rv64mzicbo_sc_tests)) 9 | -------------------------------------------------------------------------------- /isa/rv64mzicbo/zero.S: -------------------------------------------------------------------------------- 1 | #***************************************************************************** 2 | #----------------------------------------------------------------------------- 3 | # 4 | # Test CBO.ZERO instruction. 5 | # 6 | 7 | #include "riscv_test.h" 8 | #include "test_macros.h" 9 | 10 | RVTEST_RV64M 11 | RVTEST_CODE_BEGIN 12 | 13 | la x1, tdat 14 | .word 0x0040A00F # cbo.zero(x1) 15 | TEST_LD_OP( 1, ld, 0, 0, tdat ) 16 | TEST_LD_OP( 2, ld, 0, 8, tdat ) 17 | TEST_LD_OP( 3, ld, 0, 16, tdat ) 18 | TEST_LD_OP( 4, ld, 0, 24, tdat ) 19 | TEST_LD_OP( 5, ld, 0, 32, tdat ) 20 | TEST_LD_OP( 6, ld, 0, 40, tdat ) 21 | TEST_LD_OP( 7, ld, 0, 48, tdat ) 22 | TEST_LD_OP( 8, ld, 0, 56, tdat ) 23 | 24 | j pass 25 | 26 | TEST_PASSFAIL 27 | 28 | RVTEST_CODE_END 29 | 30 | .data 31 | RVTEST_DATA_BEGIN 32 | 33 | TEST_DATA 34 | 35 | tdat: .dword 0xdeadbeefdeadbeef 36 | 37 | RVTEST_DATA_END 38 | -------------------------------------------------------------------------------- /isa/rv64si/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64si tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64si_sc_tests = \ 6 | csr \ 7 | dirty \ 8 | icache-alias \ 9 | ma_fetch \ 10 | scall \ 11 | wfi \ 12 | sbreak \ 13 | 14 | rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) 15 | -------------------------------------------------------------------------------- /isa/rv64si/sbreak.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # scall.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test syscall trap. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64S 14 | RVTEST_CODE_BEGIN 15 | 16 | #ifdef __MACHINE_MODE 17 | #define sscratch mscratch 18 | #define sstatus mstatus 19 | #define scause mcause 20 | #define stvec mtvec 21 | #define sepc mepc 22 | #define sret mret 23 | #define stvec_handler mtvec_handler 24 | #endif 25 | 26 | li TESTNUM, 2 27 | 28 | do_break: 29 | sbreak 30 | j fail 31 | 32 | TEST_PASSFAIL 33 | 34 | .align 2 35 | .global stvec_handler 36 | stvec_handler: 37 | li t1, CAUSE_BREAKPOINT 38 | csrr t0, scause 39 | # Check if CLIC mode 40 | csrr t2, stvec 41 | andi t2, t2, 2 42 | # Skip masking if non-CLIC mode 43 | beqz t2, skip_mask 44 | andi t0, t0, 255 45 | skip_mask: 46 | bne t0, t1, fail 47 | la t1, do_break 48 | csrr t0, sepc 49 | bne t0, t1, fail 50 | j pass 51 | 52 | RVTEST_CODE_END 53 | 54 | .data 55 | RVTEST_DATA_BEGIN 56 | 57 | TEST_DATA 58 | 59 | RVTEST_DATA_END 60 | -------------------------------------------------------------------------------- /isa/rv64si/wfi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # wfi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test wait-for-interrupt instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64S 14 | RVTEST_CODE_BEGIN 15 | 16 | # Make sure wfi doesn't halt the hart, even if interrupts are disabled 17 | csrc sstatus, SSTATUS_SIE 18 | csrs sie, SIP_SSIP 19 | csrs sip, SIP_SSIP 20 | wfi 21 | 22 | RVTEST_PASS 23 | 24 | TEST_PASSFAIL 25 | 26 | RVTEST_CODE_END 27 | 28 | .data 29 | RVTEST_DATA_BEGIN 30 | 31 | TEST_DATA 32 | 33 | RVTEST_DATA_END 34 | -------------------------------------------------------------------------------- /isa/rv64ssvnapot/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ssvnapot tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ssvnapot_sc_tests = \ 6 | napot \ 7 | 8 | rv64ssvnapot_p_tests = $(addprefix rv64ssvnapot-p-, $(rv64ssvnapot_sc_tests)) 9 | -------------------------------------------------------------------------------- /isa/rv64ua/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ua tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ua_sc_tests = \ 6 | amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ 7 | amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ 8 | lrsc \ 9 | 10 | rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) 11 | rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) 12 | -------------------------------------------------------------------------------- /isa/rv64ua/amoadd_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoadd_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoadd.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoadd.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xffffffff7ffff800, \ 28 | amoadd.d a4, a1, 0(a3); \ 29 | ) 30 | 31 | TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) 32 | 33 | TEST_PASSFAIL 34 | 35 | RVTEST_CODE_END 36 | 37 | .data 38 | RVTEST_DATA_BEGIN 39 | 40 | TEST_DATA 41 | 42 | RVTEST_DATA_END 43 | 44 | .bss 45 | .align 3 46 | amo_operand: 47 | .dword 0 48 | -------------------------------------------------------------------------------- /isa/rv64ua/amoadd_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoadd_w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoadd.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoadd.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0x000000007ffff800, \ 28 | li a1, 0xffffffff80000000; \ 29 | amoadd.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoand_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoand_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoand.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoand.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xffffffff80000000, \ 28 | li a1, 0x0000000080000000; \ 29 | amoand.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoand_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoand.w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoand.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoand.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xffffffff80000000, \ 28 | li a1, 0x0000000080000000; \ 29 | amoand.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amomax_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomax_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomax.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amomax.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 1; \ 28 | sd x0, 0(a3); \ 29 | amomax.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 1, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amomax_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomax_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomax.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amomax.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 1; \ 28 | sw x0, 0(a3); \ 29 | amomax.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 1, lw a5, 0(a3)) 33 | 34 | TEST_CASE(6, a4, 1, \ 35 | li a0, 0x0000000000000001; \ 36 | li a1, 0x0000000080000000; \ 37 | la a3, amo_operand; \ 38 | sw a0, 0(a3); \ 39 | amomax.w a4, a1, 0(a3); \ 40 | ) 41 | 42 | TEST_CASE(7, a5, 1, lw a5, 0(a3)) 43 | 44 | TEST_PASSFAIL 45 | 46 | RVTEST_CODE_END 47 | 48 | .data 49 | RVTEST_DATA_BEGIN 50 | 51 | TEST_DATA 52 | 53 | RVTEST_DATA_END 54 | 55 | .bss 56 | .align 3 57 | amo_operand: 58 | .dword 0 59 | -------------------------------------------------------------------------------- /isa/rv64ua/amomaxu_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomaxu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomaxu.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amomaxu.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sd x0, 0(a3); \ 29 | amomaxu.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amomaxu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomaxu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomaxu.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amomaxu.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sw x0, 0(a3); \ 29 | amomaxu.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) 33 | 34 | # The following two cases check that the upper 32 bits are ignored on rv64 35 | # implementations. Only enable them for rv64. 36 | #if __riscv_xlen == 64 37 | TEST_CASE(6, a4, 1, \ 38 | li a0, 0x0000000000000001; \ 39 | li a1, 0x8000000000000000; \ 40 | la a3, amo_operand; \ 41 | sw a0, 0(a3); \ 42 | amomaxu.w a4, a1, 0(a3); \ 43 | ) 44 | 45 | TEST_CASE(7, a5, 1, lw a5, 0(a3)) 46 | #endif 47 | 48 | TEST_PASSFAIL 49 | 50 | RVTEST_CODE_END 51 | 52 | .data 53 | RVTEST_DATA_BEGIN 54 | 55 | TEST_DATA 56 | 57 | RVTEST_DATA_END 58 | 59 | .bss 60 | .align 3 61 | amo_operand: 62 | .dword 0 63 | -------------------------------------------------------------------------------- /isa/rv64ua/amomin_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomin_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomin.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amomin.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sd x0, 0(a3); \ 29 | amomin.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amomin_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amomin_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amomin.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amomin.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sw x0, 0(a3); \ 29 | amomin.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) 33 | 34 | TEST_CASE(6, a4, 1, \ 35 | li a0, 0x0000000000000001; \ 36 | li a1, 0x0000000080000000; \ 37 | la a3, amo_operand; \ 38 | sw a0, 0(a3); \ 39 | amomin.w a4, a1, 0(a3); \ 40 | ) 41 | 42 | TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3)) 43 | 44 | TEST_PASSFAIL 45 | 46 | RVTEST_CODE_END 47 | 48 | .data 49 | RVTEST_DATA_BEGIN 50 | 51 | TEST_DATA 52 | 53 | RVTEST_DATA_END 54 | 55 | .bss 56 | .align 3 57 | amo_operand: 58 | .dword 0 59 | -------------------------------------------------------------------------------- /isa/rv64ua/amominu_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amominu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amominu.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amominu.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sd x0, 0(a3); \ 29 | amominu.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | 50 | -------------------------------------------------------------------------------- /isa/rv64ua/amominu_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amominu_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amominu.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amominu.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) 25 | 26 | TEST_CASE(4, a4, 0, \ 27 | li a1, 0xffffffffffffffff; \ 28 | sw x0, 0(a3); \ 29 | amominu.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0, lw a5, 0(a3)) 33 | 34 | # The following two cases check that the upper 32 bits are ignored on rv64 35 | # implementations. Only enable them for rv64. 36 | #if __riscv_xlen == 64 37 | TEST_CASE(6, a4, 1, \ 38 | li a0, 0x0000000000000001; \ 39 | li a1, 0x8000000000000000; \ 40 | la a3, amo_operand; \ 41 | sw a0, 0(a3); \ 42 | amominu.w a4, a1, 0(a3); \ 43 | ) 44 | 45 | TEST_CASE(7, a5, 0, lw a5, 0(a3)) 46 | #endif 47 | 48 | TEST_PASSFAIL 49 | 50 | RVTEST_CODE_END 51 | 52 | .data 53 | RVTEST_DATA_BEGIN 54 | 55 | TEST_DATA 56 | 57 | RVTEST_DATA_END 58 | 59 | .bss 60 | .align 3 61 | amo_operand: 62 | .dword 0 63 | -------------------------------------------------------------------------------- /isa/rv64ua/amoor_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoor_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoor.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoor.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 1; \ 29 | amoor.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoor.w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoor.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoor.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 1; \ 29 | amoor.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoswap_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoswap.d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoswap.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoswap.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 0x0000000080000000; \ 29 | amoswap.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoswap_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoswap_w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoswap.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoswap.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0xfffffffffffff800, \ 28 | li a1, 0x0000000080000000; \ 29 | amoswap.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoxor_d.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoxor_d.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoxor.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sd a0, 0(a3); \ 21 | amoxor.d a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0x000000007ffff800, \ 28 | li a1, 1; \ 29 | amoxor.d a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64ua/amoxor_w.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # amoxor_w.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test amoxor.w instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a4, 0xffffffff80000000, \ 17 | li a0, 0xffffffff80000000; \ 18 | li a1, 0xfffffffffffff800; \ 19 | la a3, amo_operand; \ 20 | sw a0, 0(a3); \ 21 | amoxor.w a4, a1, 0(a3); \ 22 | ) 23 | 24 | TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) 25 | 26 | # try again after a cache miss 27 | TEST_CASE(4, a4, 0x7ffff800, \ 28 | li a1, 0xc0000001; \ 29 | amoxor.w a4, a1, 0(a3); \ 30 | ) 31 | 32 | TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | 45 | .bss 46 | .align 3 47 | amo_operand: 48 | .dword 0 49 | -------------------------------------------------------------------------------- /isa/rv64uc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uc_sc_tests = \ 6 | rvc \ 7 | 8 | rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests)) 9 | rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests)) 10 | -------------------------------------------------------------------------------- /isa/rv64ud/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ud tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ud_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move structural recoding \ 8 | 9 | rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) 10 | rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) 11 | -------------------------------------------------------------------------------- /isa/rv64ud/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fclass.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fclass.d instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #if __riscv_xlen == 32 17 | # Replace the function with the 32-bit variant defined in test_macros.h 18 | #undef TEST_FCLASS_D 19 | #define TEST_FCLASS_D TEST_FCLASS_D32 20 | #endif 21 | 22 | #------------------------------------------------------------- 23 | # Arithmetic tests 24 | #------------------------------------------------------------- 25 | 26 | TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 ) 27 | TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 ) 28 | TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff ) 29 | TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 ) 30 | TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 ) 31 | TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff ) 32 | TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 ) 33 | TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 ) 34 | TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 ) 35 | TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 ) 36 | 37 | TEST_PASSFAIL 38 | 39 | RVTEST_CODE_END 40 | 41 | .data 42 | RVTEST_DATA_BEGIN 43 | 44 | TEST_DATA 45 | 46 | RVTEST_DATA_END 47 | -------------------------------------------------------------------------------- /isa/rv64ud/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | la s0, tdat 17 | TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0)) 18 | TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) 19 | TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) 20 | TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) 21 | TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) 22 | 23 | TEST_PASSFAIL 24 | 25 | RVTEST_CODE_END 26 | 27 | .data 28 | RVTEST_DATA_BEGIN 29 | 30 | TEST_DATA 31 | 32 | tdat: 33 | .word 0xbf800000 34 | .word 0x40000000 35 | .word 0x40400000 36 | .word 0xc0800000 37 | .word 0xdeadbeef 38 | .word 0xcafebabe 39 | .word 0xabad1dea 40 | .word 0x1337d00d 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /isa/rv64ud/structural.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # structural.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that the FPU correctly obviates structural hazards on its 8 | # writeback port (e.g. fadd followed by fsgnj) 9 | # 10 | 11 | #include "riscv_test.h" 12 | #include "test_macros.h" 13 | 14 | RVTEST_RV64UF 15 | RVTEST_CODE_BEGIN 16 | 17 | li x12, 1 18 | 19 | li x2, 0x3FF0000000000000 20 | li x1, 0x3F800000 21 | 22 | #define TEST(testnum, nops) \ 23 | test_ ## testnum: \ 24 | li TESTNUM, testnum; \ 25 | fmv.d.x f4, x0 ;\ 26 | fmv.s.x f3, x0 ;\ 27 | fmv.d.x f2, x2 ;\ 28 | fmv.s.x f1, x1 ;\ 29 | j 1f ;\ 30 | .align 5 ;\ 31 | 1:fmul.d f4, f2, f2 ;\ 32 | nops ;\ 33 | fsgnj.s f3, f1, f1 ;\ 34 | fmv.x.d x4, f4 ;\ 35 | fmv.x.s x5, f3 ;\ 36 | beq x1, x5, 2f ;\ 37 | j fail;\ 38 | 2:beq x2, x4, 2f ;\ 39 | j fail; \ 40 | 2:fmv.d.x f2, zero ;\ 41 | fmv.s.x f1, zero ;\ 42 | 43 | TEST(1,;) 44 | TEST(2,nop) 45 | TEST(3,nop;nop) 46 | TEST(4,nop;nop;nop) 47 | TEST(5,nop;nop;nop;nop) 48 | TEST(6,nop;nop;nop;nop;nop) 49 | TEST(7,nop;nop;nop;nop;nop;nop) 50 | 51 | TEST_PASSFAIL 52 | 53 | RVTEST_CODE_END 54 | 55 | .data 56 | RVTEST_DATA_BEGIN 57 | 58 | TEST_DATA 59 | 60 | RVTEST_DATA_END 61 | -------------------------------------------------------------------------------- /isa/rv64uf/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uf tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uf_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) 10 | rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) 11 | -------------------------------------------------------------------------------- /isa/rv64uf/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fadd.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{add|sub|mul}.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 ); 21 | TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); 22 | TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); 23 | 24 | TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); 25 | TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); 26 | TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); 27 | 28 | TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); 29 | TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); 30 | TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); 31 | 32 | # Is the canonical NaN generated for Inf - Inf? 33 | TEST_FP_OP2_S_HEX(11, fsub.s, 0x10, 0x7fc00000, 0x7f800000, 0x7f800000); 34 | 35 | TEST_PASSFAIL 36 | 37 | RVTEST_CODE_END 38 | 39 | .data 40 | RVTEST_DATA_BEGIN 41 | 42 | TEST_DATA 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /isa/rv64uf/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fclass.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fclass.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FCLASS_S( 2, 1 << 0, 0xff800000 ) 21 | TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 ) 22 | TEST_FCLASS_S( 4, 1 << 2, 0x807fffff ) 23 | TEST_FCLASS_S( 5, 1 << 3, 0x80000000 ) 24 | TEST_FCLASS_S( 6, 1 << 4, 0x00000000 ) 25 | TEST_FCLASS_S( 7, 1 << 5, 0x007fffff ) 26 | TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 ) 27 | TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 ) 28 | TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) 29 | TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) 30 | 31 | TEST_PASSFAIL 32 | 33 | RVTEST_CODE_END 34 | 35 | .data 36 | RVTEST_DATA_BEGIN 37 | 38 | TEST_DATA 39 | 40 | RVTEST_DATA_END 41 | -------------------------------------------------------------------------------- /isa/rv64uf/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fcvt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2); 21 | TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2); 22 | 23 | TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2); 24 | TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2); 25 | 26 | #if __riscv_xlen >= 64 27 | TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2); 28 | TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2); 29 | 30 | TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); 31 | TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); 32 | #endif 33 | 34 | TEST_PASSFAIL 35 | 36 | RVTEST_CODE_END 37 | 38 | .data 39 | RVTEST_DATA_BEGIN 40 | 41 | TEST_DATA 42 | 43 | RVTEST_DATA_END 44 | -------------------------------------------------------------------------------- /isa/rv64uf/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fdiv.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{div|sqrt}.s instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); 21 | TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); 22 | TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); 23 | 24 | TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); 25 | TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); 26 | 27 | TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); 28 | 29 | TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); 30 | 31 | TEST_PASSFAIL 32 | 33 | RVTEST_CODE_END 34 | 35 | .data 36 | RVTEST_DATA_BEGIN 37 | 38 | TEST_DATA 39 | 40 | RVTEST_DATA_END 41 | -------------------------------------------------------------------------------- /isa/rv64uf/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) 17 | TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RVTEST_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf800000 30 | .word 0x40000000 31 | .word 0x40400000 32 | .word 0xc0800000 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /isa/rv64uf/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # recoding.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test corner cases of John Hauser's microarchitectural recoding scheme. 8 | # There are twice as many recoded values as IEEE-754 values; some of these 9 | # extras are redundant (e.g. Inf) and others are illegal (subnormals with 10 | # too many bits set). 11 | # 12 | 13 | #include "riscv_test.h" 14 | #include "test_macros.h" 15 | 16 | RVTEST_RV64UF 17 | RVTEST_CODE_BEGIN 18 | 19 | # Make sure infinities with different mantissas compare as equal. 20 | flw f0, minf, a0 21 | flw f1, three, a0 22 | fmul.s f1, f1, f0 23 | TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) 24 | TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) 25 | TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) 26 | 27 | # Likewise, but for zeroes. 28 | fcvt.s.w f0, x0 29 | li a0, 1 30 | fcvt.s.w f1, a0 31 | fmul.s f1, f1, f0 32 | TEST_CASE(5, a0, 1, feq.s a0, f0, f1) 33 | TEST_CASE(6, a0, 1, fle.s a0, f0, f1) 34 | TEST_CASE(7, a0, 0, flt.s a0, f0, f1) 35 | 36 | TEST_PASSFAIL 37 | 38 | RVTEST_CODE_END 39 | 40 | .data 41 | RVTEST_DATA_BEGIN 42 | 43 | minf: .float -Inf 44 | three: .float 3.0 45 | 46 | RVTEST_DATA_END 47 | -------------------------------------------------------------------------------- /isa/rv64ui/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64ui tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64ui_sc_tests = \ 6 | add addi addiw addw \ 7 | and andi \ 8 | auipc \ 9 | beq bge bgeu blt bltu bne \ 10 | simple \ 11 | fence_i \ 12 | jal jalr \ 13 | lb lbu lh lhu lw lwu ld ld_st \ 14 | lui \ 15 | ma_data \ 16 | or ori \ 17 | sb sh sw sd st_ld \ 18 | sll slli slliw sllw \ 19 | slt slti sltiu sltu \ 20 | sra srai sraiw sraw \ 21 | srl srli srliw srlw \ 22 | sub subw \ 23 | xor xori \ 24 | 25 | rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests)) 26 | rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests)) 27 | -------------------------------------------------------------------------------- /isa/rv64ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # auipc.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test auipc instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 10000, \ 17 | .align 3; \ 18 | lla a0, 1f + 10000; \ 19 | jal a1, 1f; \ 20 | 1: sub a0, a0, a1; \ 21 | ) 22 | 23 | TEST_CASE(3, a0, -10000, \ 24 | .align 3; \ 25 | lla a0, 1f - 10000; \ 26 | jal a1, 1f; \ 27 | 1: sub a0, a0, a1; \ 28 | ) 29 | 30 | TEST_PASSFAIL 31 | 32 | RVTEST_CODE_END 33 | 34 | .data 35 | RVTEST_DATA_BEGIN 36 | 37 | TEST_DATA 38 | 39 | RVTEST_DATA_END 40 | -------------------------------------------------------------------------------- /isa/rv64ui/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fence_i.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test self-modifying code and the fence.i instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | li a3, 111 17 | lh a0, insn 18 | lh a1, insn+2 19 | 20 | # test I$ hit 21 | .align 6 22 | sh a0, 2f, t0 23 | sh a1, 2f+2, t0 24 | fence.i 25 | 26 | la a5, 2f 27 | jalr t1, a5, 0 28 | TEST_CASE( 2, a3, 444, nop ) 29 | 30 | # test prefetcher hit 31 | li a4, 100 32 | 1: addi a4, a4, -1 33 | bnez a4, 1b 34 | 35 | sh a0, 3f, t0 36 | sh a1, 3f+2, t0 37 | fence.i 38 | 39 | .align 6 40 | la a5, 3f 41 | jalr t1, a5, 0 42 | TEST_CASE( 3, a3, 777, nop ) 43 | 44 | TEST_PASSFAIL 45 | 46 | RVTEST_CODE_END 47 | 48 | .data 49 | RVTEST_DATA_BEGIN 50 | 51 | TEST_DATA 52 | 53 | insn: 54 | addi a3, a3, 333 55 | 56 | 2: addi a3, a3, 222 57 | jalr a5, t1, 0 58 | 59 | 3: addi a3, a3, 555 60 | jalr a5, t1, 0 61 | 62 | RVTEST_DATA_END 63 | -------------------------------------------------------------------------------- /isa/rv64ui/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jal.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jal instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li ra, 0 23 | 24 | jal x4, target_2 25 | linkaddr_2: 26 | nop 27 | nop 28 | 29 | j fail 30 | 31 | target_2: 32 | la x2, linkaddr_2 33 | bne x2, x4, fail 34 | 35 | #------------------------------------------------------------- 36 | # Test delay slot instructions not executed nor bypassed 37 | #------------------------------------------------------------- 38 | 39 | TEST_CASE( 3, ra, 3, \ 40 | li ra, 1; \ 41 | jal x0, 1f; \ 42 | addi ra, ra, 1; \ 43 | addi ra, ra, 1; \ 44 | addi ra, ra, 1; \ 45 | addi ra, ra, 1; \ 46 | 1: addi ra, ra, 1; \ 47 | addi ra, ra, 1; \ 48 | ) 49 | 50 | TEST_PASSFAIL 51 | 52 | RVTEST_CODE_END 53 | 54 | .data 55 | RVTEST_DATA_BEGIN 56 | 57 | TEST_DATA 58 | 59 | RVTEST_DATA_END 60 | -------------------------------------------------------------------------------- /isa/rv64ui/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lui.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lui instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); 21 | TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); 22 | TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); 23 | TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); 24 | 25 | TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); 26 | 27 | TEST_PASSFAIL 28 | 29 | RVTEST_CODE_END 30 | 31 | .data 32 | RVTEST_DATA_BEGIN 33 | 34 | TEST_DATA 35 | 36 | RVTEST_DATA_END 37 | -------------------------------------------------------------------------------- /isa/rv64ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # simple.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This is the most basic self checking test. If your simulator does not 8 | # pass thiss then there is little chance that it will pass any of the 9 | # more complicated self checking tests. 10 | # 11 | 12 | #include "riscv_test.h" 13 | #include "test_macros.h" 14 | 15 | RVTEST_RV64U 16 | RVTEST_CODE_BEGIN 17 | 18 | RVTEST_PASS 19 | 20 | RVTEST_CODE_END 21 | 22 | .data 23 | RVTEST_DATA_BEGIN 24 | 25 | TEST_DATA 26 | 27 | RVTEST_DATA_END 28 | -------------------------------------------------------------------------------- /isa/rv64um/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64um tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64um_sc_tests = \ 6 | div divu divuw divw \ 7 | mul mulh mulhsu mulhu mulw \ 8 | rem remu remuw remw \ 9 | 10 | rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests)) 11 | rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests)) 12 | -------------------------------------------------------------------------------- /isa/rv64um/div.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # div.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test div instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, div, 3, 20, 6 ); 21 | TEST_RR_OP( 3, div, -3, -20, 6 ); 22 | TEST_RR_OP( 4, div, -3, 20, -6 ); 23 | TEST_RR_OP( 5, div, 3, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); 26 | TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, div, -1, -1<<63, 0 ); 29 | TEST_RR_OP( 9, div, -1, 1, 0 ); 30 | TEST_RR_OP(10, div, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/divu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divu, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); 22 | TEST_RR_OP( 4, divu, 0, 20, -6 ); 23 | TEST_RR_OP( 5, divu, 0, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); 26 | TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); 29 | TEST_RR_OP( 9, divu, -1, 1, 0 ); 30 | TEST_RR_OP(10, divu, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/divuw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divuw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divuw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divuw, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); 22 | TEST_RR_OP( 4, divuw, 0, 20, -6 ); 23 | TEST_RR_OP( 5, divuw, 0, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, divuw, -1, 1, 0 ); 30 | TEST_RR_OP(10, divuw, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/divw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # divw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test divw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, divw, 3, 20, 6 ); 21 | TEST_RR_OP( 3, divw, -3, -20, 6 ); 22 | TEST_RR_OP( 4, divw, -3, 20, -6 ); 23 | TEST_RR_OP( 5, divw, 3, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); 26 | TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); 29 | TEST_RR_OP( 9, divw, -1, 1, 0 ); 30 | TEST_RR_OP(10, divw, -1, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/rem.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # rem.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test rem instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, rem, 2, 20, 6 ); 21 | TEST_RR_OP( 3, rem, -2, -20, 6 ); 22 | TEST_RR_OP( 4, rem, 2, 20, -6 ); 23 | TEST_RR_OP( 5, rem, -2, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); 26 | TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); 29 | TEST_RR_OP( 9, rem, 1, 1, 0 ); 30 | TEST_RR_OP(10, rem, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/remu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remu instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remu, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remu, 2, -20, 6 ); 22 | TEST_RR_OP( 4, remu, 20, 20, -6 ); 23 | TEST_RR_OP( 5, remu, -20, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); 26 | TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); 27 | 28 | TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); 29 | TEST_RR_OP( 9, remu, 1, 1, 0 ); 30 | TEST_RR_OP(10, remu, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/remuw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remuw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remuw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remuw, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remuw, 2, -20, 6 ); 22 | TEST_RR_OP( 4, remuw, 20, 20, -6 ); 23 | TEST_RR_OP( 5, remuw, -20, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, remuw, 1, 1, 0 ); 30 | TEST_RR_OP(10, remuw, 0, 0, 0 ); 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64um/remw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # remw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test remw instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, remw, 2, 20, 6 ); 21 | TEST_RR_OP( 3, remw, -2, -20, 6 ); 22 | TEST_RR_OP( 4, remw, 2, 20, -6 ); 23 | TEST_RR_OP( 5, remw, -2, -20, -6 ); 24 | 25 | TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); 26 | TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); 27 | 28 | TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); 29 | TEST_RR_OP( 9, remw, 1, 1, 0 ); 30 | TEST_RR_OP(10, remw, 0, 0, 0 ); 31 | TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); 32 | 33 | TEST_PASSFAIL 34 | 35 | RVTEST_CODE_END 36 | 37 | .data 38 | RVTEST_DATA_BEGIN 39 | 40 | TEST_DATA 41 | 42 | RVTEST_DATA_END 43 | -------------------------------------------------------------------------------- /isa/rv64uzba/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uzba tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uzba_sc_tests = \ 6 | add_uw \ 7 | sh1add sh1add_uw \ 8 | sh2add sh2add_uw \ 9 | sh3add sh3add_uw \ 10 | slli_uw \ 11 | 12 | rv64uzba_p_tests = $(addprefix rv64uzba-p-, $(rv64uzba_sc_tests)) 13 | rv64uzba_v_tests = $(addprefix rv64uzba-v-, $(rv64uzba_sc_tests)) 14 | rv64uzba_ps_tests = $(addprefix rv64uzba-ps-, $(rv64uzba_sc_tests)) 15 | 16 | spike_tests += $(rv64uzba_p_tests) $(rv64uzba_v_tests) 17 | -------------------------------------------------------------------------------- /isa/rv64uzbb/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uzbb tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uzbb_sc_tests = \ 6 | andn \ 7 | clz clzw \ 8 | cpop cpopw \ 9 | ctz ctzw \ 10 | max maxu \ 11 | min minu \ 12 | orc_b \ 13 | orn \ 14 | rev8 \ 15 | rol rolw \ 16 | ror rorw \ 17 | rori roriw \ 18 | sext_b sext_h \ 19 | xnor \ 20 | zext_h \ 21 | 22 | rv64uzbb_p_tests = $(addprefix rv64uzbb-p-, $(rv64uzbb_sc_tests)) 23 | rv64uzbb_v_tests = $(addprefix rv64uzbb-v-, $(rv64uzbb_sc_tests)) 24 | rv64uzbb_ps_tests = $(addprefix rv64uzbb-ps-, $(rv64uzbb_sc_tests)) 25 | 26 | spike_tests += $(rv64uzbb_p_tests) $(rv64uzbb_v_tests) 27 | -------------------------------------------------------------------------------- /isa/rv64uzbc/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uzbc tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uzbc_sc_tests = \ 6 | clmul \ 7 | clmulh \ 8 | clmulr \ 9 | 10 | rv64uzbc_p_tests = $(addprefix rv64uzbc-p-, $(rv64uzbc_sc_tests)) 11 | rv64uzbc_v_tests = $(addprefix rv64uzbc-v-, $(rv64uzbc_sc_tests)) 12 | rv64uzbc_ps_tests = $(addprefix rv64uzbc-ps-, $(rv64uzbc_sc_tests)) 13 | 14 | spike_tests += $(rv64uzbc_p_tests) $(rv64uzbc_v_tests) 15 | -------------------------------------------------------------------------------- /isa/rv64uzbs/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uzbs tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uzbs_sc_tests = \ 6 | bclr bclri \ 7 | bext bexti \ 8 | binv binvi \ 9 | bset bseti \ 10 | 11 | rv64uzbs_p_tests = $(addprefix rv64uzbs-p-, $(rv64uzbs_sc_tests)) 12 | rv64uzbs_v_tests = $(addprefix rv64uzbs-v-, $(rv64uzbs_sc_tests)) 13 | rv64uzbs_ps_tests = $(addprefix rv64uzbs-ps-, $(rv64uzbs_sc_tests)) 14 | 15 | spike_tests += $(rv64uzbs_p_tests) $(rv64uzbs_v_tests) 16 | -------------------------------------------------------------------------------- /isa/rv64uzfh/Makefrag: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # Makefrag for rv64uzfh tests 3 | #----------------------------------------------------------------------- 4 | 5 | rv64uzfh_sc_tests = \ 6 | fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ 7 | ldst move recoding \ 8 | 9 | rv64uzfh_p_tests = $(addprefix rv64uzfh-p-, $(rv64uzfh_sc_tests)) 10 | rv64uzfh_v_tests = $(addprefix rv64uzfh-v-, $(rv64uzfh_sc_tests)) 11 | -------------------------------------------------------------------------------- /isa/rv64uzfh/fadd.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fadd.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{add|sub|mul}.h instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_OP2_H( 2, fadd.h, 0, 3.5, 2.5, 1.0 ); 21 | TEST_FP_OP2_H( 3, fadd.h, 1, -1234, -1235.1, 1.1 ); 22 | TEST_FP_OP2_H( 4, fadd.h, 1, 3.14, 3.13, 0.01 ); 23 | 24 | TEST_FP_OP2_H( 5, fsub.h, 0, 1.5, 2.5, 1.0 ); 25 | TEST_FP_OP2_H( 6, fsub.h, 1, -1234, -1235.1, -1.1 ); 26 | TEST_FP_OP2_H( 7, fsub.h, 1, 3.14, 3.15, 0.01 ); 27 | 28 | TEST_FP_OP2_H( 8, fmul.h, 0, 2.5, 2.5, 1.0 ); 29 | TEST_FP_OP2_H( 9, fmul.h, 0, 1235.1, -1235.1, -1.0 ); 30 | TEST_FP_OP2_H(10, fmul.h, 1, 1.1, 11.0, 0.1 ); 31 | 32 | # Is the canonical NaN generated for Inf - Inf? 33 | TEST_FP_OP2_H_HEX(11, fsub.h, 0x10, 0x7e00, 0x7c00, 0x7c00); 34 | 35 | TEST_PASSFAIL 36 | 37 | RVTEST_CODE_END 38 | 39 | .data 40 | RVTEST_DATA_BEGIN 41 | 42 | TEST_DATA 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /isa/rv64uzfh/fclass.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fclass.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fclass.h instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | #define TEST_FCLASS_H(testnum, correct, input) \ 21 | TEST_CASE(testnum, a0, correct, li a0, input; fmv.h.x fa0, a0; \ 22 | fclass.h a0, fa0) 23 | 24 | TEST_FCLASS_H( 2, 1 << 0, 0xfc00 ) 25 | TEST_FCLASS_H( 3, 1 << 1, 0xbc00 ) 26 | TEST_FCLASS_H( 4, 1 << 2, 0x83ff ) 27 | TEST_FCLASS_H( 5, 1 << 3, 0x8000 ) 28 | TEST_FCLASS_H( 6, 1 << 4, 0x0000 ) 29 | TEST_FCLASS_H( 7, 1 << 5, 0x03ff ) 30 | TEST_FCLASS_H( 8, 1 << 6, 0x3c00 ) 31 | TEST_FCLASS_H( 9, 1 << 7, 0x7c00 ) 32 | TEST_FCLASS_H(10, 1 << 8, 0x7c01 ) 33 | TEST_FCLASS_H(11, 1 << 9, 0x7e00 ) 34 | 35 | TEST_PASSFAIL 36 | 37 | RVTEST_CODE_END 38 | 39 | .data 40 | RVTEST_DATA_BEGIN 41 | 42 | TEST_DATA 43 | 44 | RVTEST_DATA_END 45 | -------------------------------------------------------------------------------- /isa/rv64uzfh/fcmp.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fcmp.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{eq|lt|le}.h instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_CMP_OP_H( 2, feq.h, 0x00, 1, -1.36, -1.36) 21 | TEST_FP_CMP_OP_H( 3, fle.h, 0x00, 1, -1.36, -1.36) 22 | TEST_FP_CMP_OP_H( 4, flt.h, 0x00, 0, -1.36, -1.36) 23 | 24 | TEST_FP_CMP_OP_H( 5, feq.h, 0x00, 0, -1.37, -1.36) 25 | TEST_FP_CMP_OP_H( 6, fle.h, 0x00, 1, -1.37, -1.36) 26 | TEST_FP_CMP_OP_H( 7, flt.h, 0x00, 1, -1.37, -1.36) 27 | 28 | TEST_PASSFAIL 29 | 30 | RVTEST_CODE_END 31 | 32 | .data 33 | RVTEST_DATA_BEGIN 34 | 35 | TEST_DATA 36 | 37 | RVTEST_DATA_END 38 | -------------------------------------------------------------------------------- /isa/rv64uzfh/fcvt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fcvt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test fcvt.h.{wu|w|lu|l}, fcvt.h.d, and fcvt.d.h instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_INT_FP_OP_H( 2, fcvt.h.w, 2.0, 2); 21 | TEST_INT_FP_OP_H( 3, fcvt.h.w, -2.0, -2); 22 | 23 | TEST_INT_FP_OP_H( 4, fcvt.h.wu, 2.0, 2); 24 | TEST_INT_FP_OP_H( 5, fcvt.h.wu, 0h:7c00, -2); 25 | 26 | #if __riscv_xlen >= 64 27 | TEST_INT_FP_OP_H( 6, fcvt.h.l, 2.0, 2); 28 | TEST_INT_FP_OP_H( 7, fcvt.h.l, -2.0, -2); 29 | 30 | TEST_INT_FP_OP_H( 8, fcvt.h.lu, 2.0, 2); 31 | TEST_INT_FP_OP_H( 9, fcvt.h.lu, 0h:7c00, -2); 32 | #endif 33 | 34 | TEST_FCVT_H_S( 10, -1.5, -1.5) 35 | 36 | #if __riscv_xlen >= 64 37 | TEST_FCVT_H_D( 11, -1.5, -1.5) 38 | #endif 39 | 40 | TEST_PASSFAIL 41 | 42 | RVTEST_CODE_END 43 | 44 | .data 45 | RVTEST_DATA_BEGIN 46 | 47 | TEST_DATA 48 | 49 | RVTEST_DATA_END 50 | -------------------------------------------------------------------------------- /isa/rv64uzfh/fdiv.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fdiv.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test f{div|sqrt}.h instructions. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_FP_OP2_H(2, fdiv.h, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); 21 | TEST_FP_OP2_H(3, fdiv.h, 1,-0.9991093838555584, -1234, 1235.1 ); 22 | TEST_FP_OP2_H(4, fdiv.h, 0, 3.14159265, 3.14159265, 1.0 ); 23 | 24 | TEST_FP_OP1_H(5, fsqrt.h, 1, 1.7724538498928541, 3.14159265 ); 25 | TEST_FP_OP1_H(6, fsqrt.h, 0, 100, 10000 ); 26 | 27 | TEST_FP_OP1_H_DWORD_RESULT(7, fsqrt.h, 0x10, 0x00007e00, -1.0 ); 28 | 29 | TEST_FP_OP1_H(8, fsqrt.h, 1, 13.076696, 171.0); 30 | 31 | 32 | TEST_PASSFAIL 33 | 34 | RVTEST_CODE_END 35 | 36 | .data 37 | RVTEST_DATA_BEGIN 38 | 39 | TEST_DATA 40 | 41 | RVTEST_DATA_END 42 | -------------------------------------------------------------------------------- /isa/rv64uzfh/ldst.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ldst.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This test verifies that flw, fld, fsw, and fsd work properly. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV64UF 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 0xcafe1000deadbeef, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); ld a0, 16(a1)) 17 | TEST_CASE(3, a0, 0x1337d00dabad0001, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); ld a0, 24(a1)) 18 | 19 | TEST_PASSFAIL 20 | 21 | RVTEST_CODE_END 22 | 23 | .data 24 | RVTEST_DATA_BEGIN 25 | 26 | TEST_DATA 27 | 28 | tdat: 29 | .word 0xbf800001 30 | .word 0x40001000 31 | .word 0x40400000 32 | .word 0xc0800000 33 | .word 0xdeadbeef 34 | .word 0xcafebabe 35 | .word 0xabad1dea 36 | .word 0x1337d00d 37 | 38 | RVTEST_DATA_END 39 | -------------------------------------------------------------------------------- /isa/rv64uzfh/recoding.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # recoding.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test corner cases of John Hauser's microarchitectural recoding scheme. 8 | # There are twice as many recoded values as IEEE-754 values; some of these 9 | # extras are redundant (e.g. Inf) and others are illegal (subnormals with 10 | # too many bits set). 11 | # 12 | 13 | #include "riscv_test.h" 14 | #include "test_macros.h" 15 | 16 | RVTEST_RV64UF 17 | RVTEST_CODE_BEGIN 18 | 19 | # Make sure infinities with different mantissas compare as equal. 20 | flw f0, minf, a0 21 | flw f1, three, a0 22 | fmul.s f1, f1, f0 23 | TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) 24 | TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) 25 | TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) 26 | 27 | # Likewise, but for zeroes. 28 | fcvt.s.w f0, x0 29 | li a0, 1 30 | fcvt.s.w f1, a0 31 | fmul.s f1, f1, f0 32 | TEST_CASE(5, a0, 1, feq.s a0, f0, f1) 33 | TEST_CASE(6, a0, 1, fle.s a0, f0, f1) 34 | TEST_CASE(7, a0, 0, flt.s a0, f0, f1) 35 | 36 | TEST_PASSFAIL 37 | 38 | RVTEST_CODE_END 39 | 40 | .data 41 | RVTEST_DATA_BEGIN 42 | 43 | minf: .float -Inf 44 | three: .float 3.0 45 | 46 | RVTEST_DATA_END 47 | -------------------------------------------------------------------------------- /mt/.gitignore: -------------------------------------------------------------------------------- 1 | *.riscv 2 | *.host 3 | *.o 4 | *.dump 5 | *.out 6 | *.hex 7 | -------------------------------------------------------------------------------- /mt/ad_matmul.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | 3 | #include "util.h" 4 | 5 | #include "dataset.h" 6 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 7 | { 8 | int i, k; 9 | int j = coreid*(lda/ncores); 10 | int jend = (coreid+1)*(lda/ncores); 11 | for ( ; j < jend; j++ ) 12 | { 13 | int j32 = j << 5; 14 | data_t* Cj32 = C + j32; 15 | for ( k = 0; k < 32; k+=2 ) 16 | { 17 | data_t Aj32k = A[k + j32]; 18 | data_t Aj32k2 = A[k + 1 + j32]; 19 | data_t* Bk32 = B + (k << 5); 20 | data_t* Bk322 = Bk32 + 32; 21 | for ( i = 0; i < 32; i+=4 ) 22 | { 23 | Cj32[i] += Aj32k * Bk32 [i]; 24 | Cj32[i] += Aj32k2 * Bk322 [i]; 25 | Cj32[i+1] += Aj32k * Bk32 [i+1]; 26 | Cj32[i+1] += Aj32k2 * Bk322[i+1]; 27 | Cj32[i+2] += Aj32k * Bk32 [i+2]; 28 | Cj32[i+2] += Aj32k2 * Bk322[i+2]; 29 | Cj32[i+3] += Aj32k * Bk32 [i+3]; 30 | Cj32[i+3] += Aj32k2 * Bk322[i+3]; 31 | } 32 | barrier(ncores); 33 | } 34 | } 35 | 36 | 37 | } 38 | -------------------------------------------------------------------------------- /mt/an_matmul.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | 3 | #include "util.h" 4 | 5 | #include "dataset.h" 6 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 7 | { 8 | 9 | // ***************************** // 10 | // **** ADD YOUR CODE HERE ***** // 11 | int i, j, k, limit, end, kblock, iblock, r, jblock; 12 | int tempA1; 13 | int tempB1; 14 | 15 | limit = lda / ncores; 16 | j = (coreid)*limit; 17 | end = (coreid+1)*limit; 18 | 19 | kblock = 1; 20 | iblock = 1; 21 | jblock = 1; 22 | for (; j < end; j+= jblock) 23 | for ( k = 0; k < lda; k = k + kblock ) 24 | { 25 | r = j*lda + k; 26 | tempA1 = A[r]; 27 | 28 | for ( i = 0; i < lda; i = i + iblock ) { 29 | tempB1 = k*lda + i; 30 | 31 | C[i + j*lda] += tempA1*B[tempB1]; 32 | 33 | } 34 | barrier(ncores); 35 | } 36 | // ***************************** // 37 | // 38 | // feel free to make a separate function for MI and MSI versions. 39 | 40 | } 41 | -------------------------------------------------------------------------------- /mt/ap_matmul.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | 3 | #include "util.h" 4 | 5 | #include "dataset.h" 6 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 7 | { 8 | 9 | // ***************************** // 10 | // **** ADD YOUR CODE HERE ***** // 11 | // ***************************** // 12 | // 13 | // feel free to make a separate function for MI and MSI versions. 14 | int i, j, k, ii, jj, kk; 15 | int block = lda / ncores; 16 | int leftover = lda % ncores; 17 | int start = block * coreid; 18 | 19 | 20 | 21 | for ( j = start; j < (start+block); j++ ) 22 | for ( k = 0; k < lda; k++ ) 23 | { 24 | for ( i = 0; i < lda; i++ ) 25 | { 26 | C[i + j*lda] += A[j*lda + k] * B[k*lda + i]; 27 | } 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /mt/aq_matmul.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | 3 | #include "util.h" 4 | 5 | #include "dataset.h" 6 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 7 | { 8 | 9 | // ***************************** // 10 | // **** ADD YOUR CODE HERE ***** // 11 | // ***************************** // 12 | // 13 | // feel free to make a separate function for MI and MSI versions. 14 | 15 | for (int i = coreid; i < lda; i+=ncores*2) 16 | { 17 | for (int j = 0; j < lda; j++) 18 | { 19 | for (int k = 0; k < lda; k++) 20 | { 21 | int A12 = A[j*lda + k]; 22 | int B1 = B[k*lda + i]; 23 | int B2 = B[k*lda + i + ncores]; 24 | C[i+j*lda] += A12 * B1; 25 | C[i+ncores+j*lda] += A12 * B2; 26 | //C[i+j*lda] += A[j*lda +k] * B[k*lda +i]; 27 | } 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /mt/ar_matmul.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | 3 | #include "util.h" 4 | 5 | #include "dataset.h" 6 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 7 | { 8 | 9 | // ***************************** // 10 | // **** ADD YOUR CODE HERE ***** // 11 | // ***************************** // 12 | // 13 | // feel free to make a separate function for MI and MSI versions. 14 | 15 | int i, j, k, B_t[32*32], x, y; 16 | int ALoc, BLoc, CLoc; 17 | // int ii = 0, done = 0; 18 | //for(x = coreid*(lda/ncores); x < (coreid+1)*(lda/ncores) && x < lda; x++) { 19 | for (x = 0; x < lda; x++) { 20 | for(y = 0; y < lda; y++) { 21 | B_t[y*lda + x] = B[x*lda + y]; 22 | } 23 | } 24 | // for ( ii = lda/4 ; ii < lda ; ii += lda/4) 25 | //{ 26 | // for ( i = coreid*(ii/ncores); i < (coreid+1)*(ii/ncores) && i < ii; i++ ) 27 | for ( i = coreid*(lda/ncores); i < (coreid+1)*(lda/ncores) && i < lda; i++ ) 28 | { 29 | ALoc = i*lda; 30 | for ( j = 0; j < lda; j++ ) 31 | { 32 | BLoc = j*lda; 33 | CLoc = i*lda + j; 34 | for ( k = 0; k < lda; k++ ) 35 | { 36 | C[CLoc] += A[ALoc + k] * B_t[BLoc + k]; 37 | } 38 | } 39 | } 40 | //} 41 | } 42 | -------------------------------------------------------------------------------- /mt/bb_matmul.c: -------------------------------------------------------------------------------- 1 | #include "dataset.h" 2 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 3 | { 4 | int i, j, k; 5 | 6 | for (i = 0; i < lda; i += 2) { 7 | for (j = coreid * (lda / ncores); j < (coreid + 1) * (lda / ncores); j += 4) { 8 | register data_t c00 = 0, c01 = 0; 9 | register data_t c10 = 0, c11 = 0; 10 | register data_t c20 = 0, c21 = 0; 11 | register data_t c30 = 0, c31 = 0; 12 | 13 | register data_t a0, a1, a2, a3, b0, b1; 14 | for (k = 0; k < lda; k++) { 15 | a0 = A[j*lda + k + 0*lda]; 16 | a1 = A[j*lda + k + 1*lda]; 17 | a2 = A[j*lda + k + 2*lda]; 18 | a3 = A[j*lda + k + 3*lda]; 19 | 20 | b0 = B[k*lda + i + 0]; 21 | b1 = B[k*lda + i + 1]; 22 | 23 | c00 += a0 * b0; c01 += a0 * b1; 24 | c10 += a1 * b0; c11 += a1 * b1; 25 | c20 += a2 * b0; c21 += a2 * b1; 26 | c30 += a3 * b0; c31 += a3 * b1; 27 | } 28 | 29 | C[i + j*lda + 0 + 0*lda] = c00; C[i + j*lda + 1 + 0*lda] = c01; 30 | C[i + j*lda + 0 + 1*lda] = c10; C[i + j*lda + 1 + 1*lda] = c11; 31 | C[i + j*lda + 0 + 2*lda] = c20; C[i + j*lda + 1 + 2*lda] = c21; 32 | C[i + j*lda + 0 + 3*lda] = c30; C[i + j*lda + 1 + 3*lda] = c31; 33 | } 34 | } 35 | } 36 | -------------------------------------------------------------------------------- /mt/bs_matmul.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | 3 | #include "util.h" 4 | 5 | #include "dataset.h" 6 | void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda, const data_t A[], const data_t B[], data_t C[] ) 7 | { 8 | int i,j,k,a,b,a1,a2,a3,c; 9 | for (j=coreid; j 0); 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /mt/vvadd4.c: -------------------------------------------------------------------------------- 1 | #include "stdlib.h" 2 | #include "dataset.h" 3 | 4 | //-------------------------------------------------------------------------- 5 | // vvadd function 6 | 7 | void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z) 8 | { 9 | size_t i; 10 | 11 | // interleave accesses 12 | for (i = coreid; i < n; i+=ncores) 13 | { 14 | z[i] = x[i] + y[i]; 15 | } 16 | } 17 | --------------------------------------------------------------------------------